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Merge remote-tracking branch 'origin/master' into amd-common
[deliverable/binutils-gdb.git]
/
include
/
opcode
/
riscv-opc.h
2018-10-02
Palmer Dabbelt
RISC-V: Add fence.tso instruction
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2018-05-08
Jim Wilson
RISC-V: Add missing hint instructions from RV128I.
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2018-01-04
Jim Wilson
RISC-V: Add 2 missing privileged registers.
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2017-12-28
Jim Wilson
RISC-V: Add missing privileged spec registers.
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2017-11-07
Palmer Dabbelt
RISC-V: Add satp as an alias for sptbr
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2017-03-31
Andrew Waterman
RISC-V: Add physical memory protection CSRs
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2017-02-24
Andrew Waterman
Add new counter-enable CSRs
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2017-02-15
Andrew Waterman
Add SFENCE.VMA instruction
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2017-01-03
Kito Cheng
Add support for the Q extension to the RISCV ISA.
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2016-11-01
Nick Clifton
Add support for RISC-V architecture.
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