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RISC-V: Support debug and float CSR as the unprivileged ones.
[deliverable/binutils-gdb.git]
/
include
/
opcode
/
riscv.h
2020-06-30
Nelson Chu
RISC-V: Support debug and float CSR as the unprivileged...
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2020-06-22
Nelson Chu
RISC-V: Report warning when linking the objects with...
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2020-06-12
Nelson Chu
RISC-V: Drop the privileged spec v1.9 support.
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2020-06-03
Nelson Chu
RISC-V: Fix the error when building RISC-V linux native...
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2020-05-20
Nelson Chu
[PATCH v2 0/9] RISC-V: Support version controling for...
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2020-01-01
Alan Modra
Update year range in copyright notice of binutils files
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2019-09-18
Jim Wilson
RISC-V: Gate opcode tables by enum rather than string.
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2019-01-01
Alan Modra
Update year range in copyright notice of binutils files
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2018-12-06
Andrew Burgess
opcodes/riscv: Hide '.L0 ' fake symbols
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2018-12-03
Jim Wilson
RISC-V: Accept version, supervisor ext and more than...
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2018-11-27
Jim Wilson
RISC-V: Add .insn CA support.
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2018-08-30
Jim Wilson
RISC-V: Allow instruction require more than one extension
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2018-07-30
Jim Wilson
RISC-V: Set insn info fields correctly when disassembling.
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2018-03-14
Jim Wilson
RISC-V: Add .insn support.
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2018-01-03
Alan Modra
Update year range in copyright notice of binutils files
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2017-10-24
Andrew Waterman
RISC-V: Only relax to C.LUI when imm != 0 and rd !...
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2017-01-03
Kito Cheng
Add support for the Q extension to the RISCV ISA.
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2017-01-02
Alan Modra
Update year range in copyright notice of all files.
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2016-11-01
Nick Clifton
Add support for RISC-V architecture.
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