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RISC-V: Only relax to C.LUI when imm != 0 and rd != 0/2
[deliverable/binutils-gdb.git] / include / opcode / riscv.h
2017-10-24  Andrew WatermanRISC-V: Only relax to C.LUI when imm != 0 and rd !... blob | commitdiff | raw
2017-01-03  Kito ChengAdd support for the Q extension to the RISCV ISA. blob | commitdiff | raw | diff to current
2017-01-02  Alan ModraUpdate year range in copyright notice of all files. blob | commitdiff | raw | diff to current
2016-11-01  Nick CliftonAdd support for RISC-V architecture. blob | commitdiff | raw | diff to current
GDB Binutils - Deliverables
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