Fixes a compile time warnng about left shifting a negative value.
[deliverable/binutils-gdb.git] / sim / bfin /
2011-05-25  Mike Frysingersim: bfin: add bf526-0.2/bf54x-0.4 rom regions
2011-05-14  Mike Frysingersim: bfin: allow pushing of SP
2011-05-14  Mike Frysingersim: bfin: implement loop back support in the UARTs
2011-05-09  Mike Frysingersim: bfin: fix UART LSR read-only bit saturation
2011-04-27  Mike Frysingersim: bfin: constify dmac pmap arrays
2011-04-26  Mike Frysingersim: gpio: add output support
2011-04-26  Mike Frysingersim: gpio: update mask a/b signals better
2011-04-16  Mike Frysingersim: bfin: use store buffer with more 32bit insns
2011-04-15  Mike Frysingersim: bfin: handle implicit DISALGNEXCPT with video...
2011-04-11  Mike Frysingersim: bfin: respect the port level on signals to the SIC
2011-04-11  Mike Frysingersim: bfin: add missing GPIO pin 15
2011-04-01  Mike Frysingersim: bfin: add OTP output port
2011-03-29  Mike Frysingersim: bfin: regen configure to include new cfi device
2011-03-29  Mike Frysingersim: bfin: fix sign extension with 16bit acc add insns
2011-03-27  Mike Frysingersim: bfin: handle saturation with RND12 sub insns
2011-03-26  Mike Frysingersim: bfin: add missing VS set with add/sub insns
2011-03-25  Mike Frysingersim: bfin: add hw tracing to gpio/sic port events
2011-03-25  Mike Frysingersim: bfin: fix GPIO logic bugs when processing events
2011-03-25  Mike Frysingersim: bfin: fix clear/set/toggle GPIO handling
2011-03-24  Mike Frysingersim: bfin: document SIC limitation
2011-03-24  Mike Frysingersim: bfin: fix inverted W1C logic
2011-03-24  Mike Frysingersim: bfin: define more UART LSR bits
2011-03-24  Mike Frysingersim: bfin: fix typo in TWI stat reg
2011-03-24  Mike Frysingersim: bfin: update VIT_MAX behavior to match hardware...
2011-03-24  Mike Frysingersim: bfin: always do 16bit sign extension with the...
2011-03-24  Mike Frysingersim: bfin: update AV and AC ASTAT bits with acc negation
2011-03-24  Mike Frysingersim: bfin: fix thinko in SIC pin encoding
2011-03-24  Mike Frysingersim: bfin: allow byteop[123]p src regs to be the same
2011-03-24  Mike Frysingersim: bfin: fix thinko in bfin_gpio bus addresses
2011-03-17  Mike Frysingersim: bfin: check for kill/pread
2011-03-15  Mike Frysingersim: bfin: add GPIO device simulation
2011-03-15  Mike Frysingersim: bfin: fix brace style
2011-03-15  Mike Frysingersim: bfin: fix brace style
2011-03-15  Mike Frysingersim: bfin: handle AZ updates with 16bit adds/subs
2011-03-15  Mike Frysingersim: bfin: skip acc/ASTAT updates for moves
2011-03-15  Mike Frysingersim: bfin: handle AN (negative overflows) in dsp mult...
2011-03-15  Mike Frysingersim: bfin: handle V overflows in dsp mult insns
2011-03-15  Mike Frysingersim: bfin: decode ASTAT on failure
2011-03-15  Mike Frysingersim: bfin: handle saturation with fract multiplications
2011-03-14  Mike Frysingersim: bfin: forgot to cvs add the changelog
2011-03-06  Mike Frysingersim: bfin: new port
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