From 75b06e7b7a1972cba3f0f3b1e36010eb7cd99d78 Mon Sep 17 00:00:00 2001 From: DJ Delorie Date: Wed, 21 Mar 2007 02:53:50 +0000 Subject: [PATCH] * m32c.cpu (f-dsp-40-u20, f-dsp-48-u20, Dsp-40-u20, Dsp-40-u20, mem20): New. (src16-16-20-An-relative-*): New. (dst16-*-20-An-relative-*): New. (dst16-16-16sa-*): New (dst16-16-16ar-*): New (dst32-16-16sa-Unprefixed-*): New (jsri): Fix operands. (setzx): Fix encoding. * m32c-asm.c: Regenerate. * m32c-desc.c: Regenerate. * m32c-desc.h: Regenerate. * m32c-dis.h: Regenerate. * m32c-ibld.c: Regenerate. * m32c-opc.c: Regenerate. * m32c-opc.h: Regenerate. --- cpu/ChangeLog | 12 ++ cpu/m32c.cpu | 111 +++++++++++++-- opcodes/ChangeLog | 10 ++ opcodes/m32c-asm.c | 6 + opcodes/m32c-desc.c | 147 +++++++++++++------- opcodes/m32c-desc.h | 325 ++++++++++++++++++++++---------------------- opcodes/m32c-dis.c | 6 + opcodes/m32c-ibld.c | 73 ++++++++++ opcodes/m32c-opc.c | 140 ++++++++++--------- opcodes/m32c-opc.h | 20 +-- 10 files changed, 553 insertions(+), 297 deletions(-) diff --git a/cpu/ChangeLog b/cpu/ChangeLog index f14be5809e..41c359f3c9 100644 --- a/cpu/ChangeLog +++ b/cpu/ChangeLog @@ -1,3 +1,15 @@ +2007-03-20 DJ Delorie + + * m32c.cpu (f-dsp-40-u20, f-dsp-48-u20, Dsp-40-u20, Dsp-40-u20, + mem20): New. + (src16-16-20-An-relative-*): New. + (dst16-*-20-An-relative-*): New. + (dst16-16-16sa-*): New + (dst16-16-16ar-*): New + (dst32-16-16sa-Unprefixed-*): New + (jsri): Fix operands. + (setzx): Fix encoding. + 2007-03-08 Alan Modra * m32r.opc: Formatting. diff --git a/cpu/m32c.cpu b/cpu/m32c.cpu index a645a48b59..4c76afe316 100644 --- a/cpu/m32c.cpu +++ b/cpu/m32c.cpu @@ -624,6 +624,18 @@ (and USI (sll UHI value 16) #xff0000))) ; extract ) +(df f-dsp-40-u20 "20 bit unsigned" (all-isas) 40 20 UINT + ((value pc) (or USI + (or USI + (and (srl value 16) #x0000ff) + (and value #x00ff00)) + (and (sll value 16) #x0f0000))) ; insert + ((value pc) (or USI + (or USI + (and USI (srl UHI value 16) #x0000ff) + (and USI value #x00ff00)) + (and USI (sll UHI value 16) #x0f0000))) ; extract +) (df f-dsp-40-u24 "24 bit unsigned" (all-isas) 40 24 UINT ((value pc) (or USI (or USI @@ -649,6 +661,17 @@ ) ) +(dnmf f-dsp-48-u20 "20 bit unsigned" (all-isas) UINT + (f-dsp-48-u16 f-dsp-64-u8) + (sequence () ; insert + (set (ifield f-dsp-64-u8) (and (srl (ifield f-dsp-48-u20) 16) #x0f)) + (set (ifield f-dsp-48-u16) (and (ifield f-dsp-48-u20) #xffff)) + ) + (sequence () ; extract + (set (ifield f-dsp-48-u20) (or (and (ifield f-dsp-48-u16) #xffff) + (and (sll (ifield f-dsp-64-u8) 16) #x0f0000))) + ) +) (dnmf f-dsp-48-u24 "24 bit unsigned" (all-isas) UINT (f-dsp-48-u16 f-dsp-64-u8) (sequence () ; insert @@ -1877,6 +1900,10 @@ h-sint DFLT f-dsp-40-s16 ((parse "signed16")) () () ) +(define-full-operand Dsp-40-u20 "unsigned 20 bit displacement at offset 40 bits" (all-isas) + h-uint DFLT f-dsp-40-u20 + ((parse "unsigned20")) () () +) (define-full-operand Dsp-40-u24 "unsigned 24 bit displacement at offset 40 bits" (all-isas) h-uint DFLT f-dsp-40-u24 ((parse "unsigned24")) () () @@ -1897,6 +1924,10 @@ h-sint DFLT f-dsp-48-s16 ((parse "signed16")) () () ) +(define-full-operand Dsp-48-u20 "unsigned 24 bit displacement at offset 40 bits" (all-isas) + h-uint DFLT f-dsp-48-u20 + ((parse "unsigned24")) () () +) (define-full-operand Dsp-48-u24 "unsigned 24 bit displacement at offset 48 bits" (all-isas) h-uint DFLT f-dsp-48-u24 ((parse "unsigned24")) () () @@ -2209,6 +2240,9 @@ (define-pmacro (mem16 mode address) (mem mode (and #xffff address))) +(define-pmacro (mem20 mode address) + (mem mode (and #xfffff address))) + (define-pmacro (mem32 mode address) (mem mode (and #xffffff address))) @@ -2441,6 +2475,19 @@ (getter (mem16 xmode (add Dsp-16-u16 Src16An))) (setter (set (mem16 xmode (add Dsp-16-u16 Src16An)) newval)) ) + (define-derived-operand + (name (.sym src16-16-20-An-relative- xmode)) + (comment (.str "m16c dsp:20[An] relative destination " xmode)) + (attrs (machine 16)) + (mode xmode) + (args (Src16An Dsp-16-u20)) + (syntax "${Dsp-16-u20}[$Src16An]") + (base-ifield f-8-4) + (encoding (+ (f-8-2 3) (f-10-1 0) Dsp-16-u20 Src16An)) + (ifield-assertion (andif (eq f-8-2 3) (eq f-10-1 0))) + (getter (mem20 xmode (add Dsp-16-u20 Src16An))) + (setter (set (mem20 xmode (add Dsp-16-u20 Src16An)) newval)) + ) ) ) @@ -3157,6 +3204,19 @@ (getter (mem16 xmode (add (.sym Dsp- offset -u16) Dst16An))) (setter (set (mem16 xmode (add (.sym Dsp- offset -u16) Dst16An)) newval)) ) + (define-derived-operand + (name (.sym dst16- offset -20-An-relative- xmode)) + (comment (.str "m16c dsp:20[An] relative destination " xmode)) + (attrs (machine 16)) + (mode xmode) + (args (Dst16An (.sym Dsp- offset -u20))) + (syntax (.str "${Dsp-" offset "-u20}[$Dst16An]")) + (base-ifield f-12-4) + (encoding (+ (f-12-2 3) (f-14-1 0) (.sym Dsp- offset -u20) Dst16An)) + (ifield-assertion (andif (eq f-12-2 3) (eq f-14-1 0))) + (getter (mem16 xmode (add (.sym Dsp- offset -u20) Dst16An))) + (setter (set (mem16 xmode (add (.sym Dsp- offset -u20) Dst16An)) newval)) + ) ) ) @@ -4727,6 +4787,25 @@ (.sym dst16-16-16-absolute- xmode) ) ) + (define-anyof-operand + (name (.sym dst16-16-16sa- xmode)) + (comment (.str "m16c destination operand of size " xmode " with additional fields at offset 16")) + (attrs (machine 16)) + (mode xmode) + (choices + (.sym dst16-16-16-SB-relative- xmode) + (.sym dst16-16-16-absolute- xmode) + ) + ) + (define-anyof-operand + (name (.sym dst16-16-20ar- xmode)) + (comment (.str "m16c destination operand of size " xmode " with additional fields at offset 16")) + (attrs (machine 16)) + (mode xmode) + (choices + (.sym dst16-16-20-An-relative- xmode) + ) + ) ) ) @@ -5095,6 +5174,17 @@ (.sym dst32-16-16-absolute-Unprefixed- xmode) ) ) + (define-anyof-operand + (name (.sym dst32-16-16sa-Unprefixed- xmode)) + (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 16")) + (attrs (machine 32)) + (mode xmode) + (choices + (.sym dst32-16-16-SB-relative-Unprefixed- xmode) + (.sym dst32-16-16-FB-relative-Unprefixed- xmode) + (.sym dst32-16-16-absolute-Unprefixed- xmode) + ) + ) (define-anyof-operand (name (.sym dst32-16-24-Unprefixed- xmode)) (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 16")) @@ -8246,28 +8336,27 @@ ) ) ; jsri.w dst (m16 #1 m32 #1)) +(jsri-defn w dst16-16-20ar-HI (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #x3) jsr16-sem + dst32-16-24-Unprefixed-HI (f-0-4 #xC) (f-7-1 1) (f-10-2 #x1) (f-12-4 #xF) jsr32-sem 4) +(jsri-defn w dst16-16-16sa-HI (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #x3) jsr16-sem + dst32-16-16sa-Unprefixed-HI (f-0-4 #xC) (f-7-1 1) (f-10-2 #x1) (f-12-4 #xF) jsr32-sem 4) (jsri-defn w dst16-16-8-HI (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #x3) jsr16-sem dst32-16-8-Unprefixed-HI (f-0-4 #xC) (f-7-1 1) (f-10-2 #x1) (f-12-4 #xF) jsr32-sem 3) -(jsri-defn w dst16-16-16-HI (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #x3) jsr16-sem - dst32-16-16-Unprefixed-HI (f-0-4 #xC) (f-7-1 1) (f-10-2 #x1) (f-12-4 #xF) jsr32-sem 4) (jsri-defn w dst16-basic-HI (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #x3) jsr16-sem dst32-basic-Unprefixed-HI (f-0-4 #xC) (f-7-1 1) (f-10-2 #x1) (f-12-4 #xF) jsr32-sem 2) -(dni jsri32.w "jsr.w dst32-16-24-Unprefixed-HI" (RL_1ADDR (machine 32)) - ("jsri.w ${dst32-16-24-Unprefixed-HI}") - (+ (f-0-4 #xC) (f-7-1 1) dst32-16-24-Unprefixed-HI (f-10-2 #x1) (f-12-4 #xF)) - (jsr32-sem 6 dst32-16-24-Unprefixed-HI) - ()) ; jsri.a (m16 #2 m32 #2) +(jsri-defn a dst16-16-20ar-SI (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #x1) jsr16-sem + dst32-16-24-Unprefixed-SI (f-0-4 #x9) (f-7-1 0) (f-10-2 #x0) (f-12-4 #x1) jsr32-sem 4) (jsri-defn a dst16-16-8-SI (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #x1) jsr16-sem dst32-16-8-Unprefixed-SI (f-0-4 #x9) (f-7-1 0) (f-10-2 #x0) (f-12-4 #x1) jsr32-sem 3) -(jsri-defn a dst16-16-16-SI (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #x1) jsr16-sem - dst32-16-16-Unprefixed-SI (f-0-4 #x9) (f-7-1 0) (f-10-2 #x0) (f-12-4 #x1) jsr32-sem 4) +(jsri-defn a dst16-16-16sa-SI (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #x1) jsr16-sem + dst32-16-16sa-Unprefixed-SI (f-0-4 #x9) (f-7-1 0) (f-10-2 #x0) (f-12-4 #x1) jsr32-sem 4) (jsri-defn a dst16-basic-SI (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #x1) jsr16-sem dst32-basic-Unprefixed-SI (f-0-4 #x9) (f-7-1 0) (f-10-2 #x0) (f-12-4 #x1) jsr32-sem 2) (dni jsri32.a "jsr.w dst32-16-24-Unprefixed-HI" (RL_1ADDR (machine 32)) - ("jsri.w ${dst32-16-24-Unprefixed-SI}") + ("jsri.a ${dst32-16-24-Unprefixed-SI}") (+ (f-0-4 #x9) (f-7-1 0) dst32-16-24-Unprefixed-SI (f-10-2 #x0) (f-12-4 #x1)) (jsr32-sem 6 dst32-16-24-Unprefixed-SI) ()) @@ -10233,7 +10322,7 @@ ()) (dni stzx16-imm8-imm8-abs16 "stzx #Imm8,#Imm8,abs16" ((machine 16)) ("stzx #${Imm-8-QI},#${Imm-32-QI},${Dsp-16-u16}") - (+ (f-0-4 #xD) (f-4-4 #xE) Imm-8-QI Dsp-16-u16 Imm-32-QI) + (+ (f-0-4 #xD) (f-4-4 #xF) Imm-8-QI Dsp-16-u16 Imm-32-QI) (stzx-sem QI Imm-8-QI Imm-32-QI (mem16 QI Dsp-16-u16)) ()) ; stzx.BW #imm,dst (m32) diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 3d0b34fe87..00a328a441 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,13 @@ +2007-03-20 DJ Delorie + + * m32c-asm.c: Regenerate. + * m32c-desc.c: Regenerate. + * m32c-desc.h: Regenerate. + * m32c-dis.h: Regenerate. + * m32c-ibld.c: Regenerate. + * m32c-opc.c: Regenerate. + * m32c-opc.h: Regenerate. + 2007-03-15 H.J. Lu * i386-opc.c: Include "libiberty.h". diff --git a/opcodes/m32c-asm.c b/opcodes/m32c-asm.c index a1e9c62ec5..7d2aac8512 100644 --- a/opcodes/m32c-asm.c +++ b/opcodes/m32c-asm.c @@ -1114,6 +1114,9 @@ m32c_cgen_parse_operand (CGEN_CPU_DESC cd, case M32C_OPERAND_DSP_40_U16 : errmsg = parse_unsigned16 (cd, strp, M32C_OPERAND_DSP_40_U16, (unsigned long *) (& fields->f_dsp_40_u16)); break; + case M32C_OPERAND_DSP_40_U20 : + errmsg = parse_unsigned20 (cd, strp, M32C_OPERAND_DSP_40_U20, (unsigned long *) (& fields->f_dsp_40_u20)); + break; case M32C_OPERAND_DSP_40_U24 : errmsg = parse_unsigned24 (cd, strp, M32C_OPERAND_DSP_40_U24, (unsigned long *) (& fields->f_dsp_40_u24)); break; @@ -1129,6 +1132,9 @@ m32c_cgen_parse_operand (CGEN_CPU_DESC cd, case M32C_OPERAND_DSP_48_U16 : errmsg = parse_unsigned16 (cd, strp, M32C_OPERAND_DSP_48_U16, (unsigned long *) (& fields->f_dsp_48_u16)); break; + case M32C_OPERAND_DSP_48_U20 : + errmsg = parse_unsigned24 (cd, strp, M32C_OPERAND_DSP_48_U20, (unsigned long *) (& fields->f_dsp_48_u20)); + break; case M32C_OPERAND_DSP_48_U24 : errmsg = parse_unsigned24 (cd, strp, M32C_OPERAND_DSP_48_U24, (unsigned long *) (& fields->f_dsp_48_u24)); break; diff --git a/opcodes/m32c-desc.c b/opcodes/m32c-desc.c index c87ddc7631..74c9d40f09 100644 --- a/opcodes/m32c-desc.c +++ b/opcodes/m32c-desc.c @@ -916,8 +916,10 @@ const CGEN_IFLD m32c_cgen_ifld_table[] = { M32C_F_DSP_16_U24, "f-dsp-16-u24", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<f_dsp_40_u16, 0, pc, length); break; + case M32C_OPERAND_DSP_40_U20 : + print_normal (cd, info, fields->f_dsp_40_u20, 0, pc, length); + break; case M32C_OPERAND_DSP_40_U24 : print_normal (cd, info, fields->f_dsp_40_u24, 0, pc, length); break; @@ -468,6 +471,9 @@ m32c_cgen_print_operand (CGEN_CPU_DESC cd, case M32C_OPERAND_DSP_48_U16 : print_normal (cd, info, fields->f_dsp_48_u16, 0, pc, length); break; + case M32C_OPERAND_DSP_48_U20 : + print_normal (cd, info, fields->f_dsp_48_u20, 0|(1<f_dsp_48_u24, 0|(1<f_dsp_40_u20; + value = ((((((((unsigned int) (value) >> (16))) & (255))) | (((value) & (65280))))) | (((((value) << (16))) & (983040)))); + errmsg = insert_normal (cd, value, 0, 32, 8, 20, 32, total_length, buffer); + } + break; case M32C_OPERAND_DSP_40_U24 : { long value = fields->f_dsp_40_u24; @@ -1027,6 +1034,24 @@ m32c_cgen_insert_operand (CGEN_CPU_DESC cd, errmsg = insert_normal (cd, value, 0, 32, 16, 16, 32, total_length, buffer); } break; + case M32C_OPERAND_DSP_48_U20 : + { +{ + FLD (f_dsp_64_u8) = ((((unsigned int) (FLD (f_dsp_48_u20)) >> (16))) & (15)); + FLD (f_dsp_48_u16) = ((FLD (f_dsp_48_u20)) & (65535)); +} + { + long value = fields->f_dsp_48_u16; + value = ((((((unsigned int) (value) >> (8))) & (255))) | (((((value) << (8))) & (65280)))); + errmsg = insert_normal (cd, value, 0, 32, 16, 16, 32, total_length, buffer); + } + if (errmsg) + break; + errmsg = insert_normal (cd, fields->f_dsp_64_u8, 0, 64, 0, 8, 32, total_length, buffer); + if (errmsg) + break; + } + break; case M32C_OPERAND_DSP_48_U24 : { { @@ -2131,6 +2156,14 @@ m32c_cgen_extract_operand (CGEN_CPU_DESC cd, fields->f_dsp_40_u16 = value; } break; + case M32C_OPERAND_DSP_40_U20 : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0, 32, 8, 20, 32, total_length, pc, & value); + value = ((((((((unsigned int) (value) >> (16))) & (255))) | (((value) & (65280))))) | (((((value) << (16))) & (983040)))); + fields->f_dsp_40_u20 = value; + } + break; case M32C_OPERAND_DSP_40_U24 : { long value; @@ -2161,6 +2194,22 @@ m32c_cgen_extract_operand (CGEN_CPU_DESC cd, fields->f_dsp_48_u16 = value; } break; + case M32C_OPERAND_DSP_48_U20 : + { + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0, 32, 16, 16, 32, total_length, pc, & value); + value = ((((((unsigned int) (value) >> (8))) & (255))) | (((((value) << (8))) & (65280)))); + fields->f_dsp_48_u16 = value; + } + if (length <= 0) break; + length = extract_normal (cd, ex_info, insn_value, 0, 64, 0, 8, 32, total_length, pc, & fields->f_dsp_64_u8); + if (length <= 0) break; +{ + FLD (f_dsp_48_u20) = ((((FLD (f_dsp_48_u16)) & (65535))) | (((((FLD (f_dsp_64_u8)) << (16))) & (983040)))); +} + } + break; case M32C_OPERAND_DSP_48_U24 : { { @@ -3018,6 +3067,9 @@ m32c_cgen_get_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, case M32C_OPERAND_DSP_40_U16 : value = fields->f_dsp_40_u16; break; + case M32C_OPERAND_DSP_40_U20 : + value = fields->f_dsp_40_u20; + break; case M32C_OPERAND_DSP_40_U24 : value = fields->f_dsp_40_u24; break; @@ -3033,6 +3085,9 @@ m32c_cgen_get_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, case M32C_OPERAND_DSP_48_U16 : value = fields->f_dsp_48_u16; break; + case M32C_OPERAND_DSP_48_U20 : + value = fields->f_dsp_48_u20; + break; case M32C_OPERAND_DSP_48_U24 : value = fields->f_dsp_48_u24; break; @@ -3611,6 +3666,9 @@ m32c_cgen_get_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, case M32C_OPERAND_DSP_40_U16 : value = fields->f_dsp_40_u16; break; + case M32C_OPERAND_DSP_40_U20 : + value = fields->f_dsp_40_u20; + break; case M32C_OPERAND_DSP_40_U24 : value = fields->f_dsp_40_u24; break; @@ -3626,6 +3684,9 @@ m32c_cgen_get_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, case M32C_OPERAND_DSP_48_U16 : value = fields->f_dsp_48_u16; break; + case M32C_OPERAND_DSP_48_U20 : + value = fields->f_dsp_48_u20; + break; case M32C_OPERAND_DSP_48_U24 : value = fields->f_dsp_48_u24; break; @@ -4209,6 +4270,9 @@ m32c_cgen_set_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, case M32C_OPERAND_DSP_40_U16 : fields->f_dsp_40_u16 = value; break; + case M32C_OPERAND_DSP_40_U20 : + fields->f_dsp_40_u20 = value; + break; case M32C_OPERAND_DSP_40_U24 : fields->f_dsp_40_u24 = value; break; @@ -4224,6 +4288,9 @@ m32c_cgen_set_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, case M32C_OPERAND_DSP_48_U16 : fields->f_dsp_48_u16 = value; break; + case M32C_OPERAND_DSP_48_U20 : + fields->f_dsp_48_u20 = value; + break; case M32C_OPERAND_DSP_48_U24 : fields->f_dsp_48_u24 = value; break; @@ -4780,6 +4847,9 @@ m32c_cgen_set_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, case M32C_OPERAND_DSP_40_U16 : fields->f_dsp_40_u16 = value; break; + case M32C_OPERAND_DSP_40_U20 : + fields->f_dsp_40_u20 = value; + break; case M32C_OPERAND_DSP_40_U24 : fields->f_dsp_40_u24 = value; break; @@ -4795,6 +4865,9 @@ m32c_cgen_set_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, case M32C_OPERAND_DSP_48_U16 : fields->f_dsp_48_u16 = value; break; + case M32C_OPERAND_DSP_48_U20 : + fields->f_dsp_48_u20 = value; + break; case M32C_OPERAND_DSP_48_U24 : fields->f_dsp_48_u24 = value; break; diff --git a/opcodes/m32c-opc.c b/opcodes/m32c-opc.c index 2d051cbc4d..257c461bff 100644 --- a/opcodes/m32c-opc.c +++ b/opcodes/m32c-opc.c @@ -7081,15 +7081,11 @@ static const CGEN_IFMT ifmt_jsri16a_dst16_basic_SI_dst16_An_indirect_SI ATTRIBUT 16, 16, 0xfffe, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } } }; -static const CGEN_IFMT ifmt_jsri16a_dst16_16_16_SI_dst16_16_16_An_relative_SI ATTRIBUTE_UNUSED = { - 32, 32, 0xfffe0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } } -}; - -static const CGEN_IFMT ifmt_jsri16a_dst16_16_16_SI_dst16_16_16_SB_relative_SI ATTRIBUTE_UNUSED = { +static const CGEN_IFMT ifmt_jsri16a_dst16_16_16sa_SI_dst16_16_16_SB_relative_SI ATTRIBUTE_UNUSED = { 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } } }; -static const CGEN_IFMT ifmt_jsri16a_dst16_16_16_SI_dst16_16_16_absolute_SI ATTRIBUTE_UNUSED = { +static const CGEN_IFMT ifmt_jsri16a_dst16_16_16sa_SI_dst16_16_16_absolute_SI ATTRIBUTE_UNUSED = { 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } } }; @@ -7105,6 +7101,18 @@ static const CGEN_IFMT ifmt_jsri16a_dst16_16_8_SI_dst16_16_8_FB_relative_SI ATTR 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } } }; +static const CGEN_IFMT ifmt_jsri16a_dst16_16_20ar_SI_dst16_16_20_An_relative_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xfffe0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U24) }, { F (F_DST16_AN) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_jsri16w_dst16_16_20ar_HI_dst16_16_20_An_relative_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xfffe0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U24) }, { F (F_DST16_AN) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_jmpi16_a_16_dst16_16_16_An_relative_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xfffe0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } } +}; + static const CGEN_IFMT ifmt_cmp32_w_S_src2_r0_HI_src32_2_S_8_SB_relative_HI ATTRIBUTE_UNUSED = { 16, 16, 0xff00, { { F (F_0_2) }, { F (F_2_2) }, { F (F_DSP_8_U8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } }; @@ -46044,13 +46052,13 @@ static const CGEN_OPCODE m32c_cgen_insn_opcode_table[MAX_INSNS] = { { MNEM, ' ', OP (DSP_16_U16), ',', OP (CR16), 0 } }, & ifmt_stc16_src_dst16_16_16_absolute_HI, { 0x7a8f0000 } }, -/* jsri.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */ +/* jsri.a ${Dsp-16-u24}[$Dst32AnUnprefixed] */ { { 0, 0, 0, 0 }, { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, & ifmt_shl32_l_dst_dst32_16_24_An_relative_Unprefixed_SI, { 0x96010000 } }, -/* jsri.w ${Dsp-16-u24} */ +/* jsri.a ${Dsp-16-u24} */ { { 0, 0, 0, 0 }, { { MNEM, ' ', OP (DSP_16_U24), 0 } }, @@ -46092,12 +46100,6 @@ static const CGEN_OPCODE m32c_cgen_insn_opcode_table[MAX_INSNS] = { { MNEM, ' ', '[', OP (DST16AN), ']', 0 } }, & ifmt_jsri16a_dst16_basic_SI_dst16_An_indirect_SI, { 0x7d16 } }, -/* jsri.a ${Dsp-16-u16}[$Dst32AnUnprefixed] */ - { - { 0, 0, 0, 0 }, - { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, - & ifmt_shl32_l_dst_dst32_16_16_An_relative_Unprefixed_SI, { 0x94010000 } - }, /* jsri.a ${Dsp-16-u16}[sb] */ { { 0, 0, 0, 0 }, @@ -46116,23 +46118,17 @@ static const CGEN_OPCODE m32c_cgen_insn_opcode_table[MAX_INSNS] = { { MNEM, ' ', OP (DSP_16_U16), 0 } }, & ifmt_shl32_l_dst_dst32_16_16_absolute_Unprefixed_SI, { 0x96c10000 } }, -/* jsri.a ${Dsp-16-u16}[$Dst16An] */ - { - { 0, 0, 0, 0 }, - { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, - & ifmt_jsri16a_dst16_16_16_SI_dst16_16_16_An_relative_SI, { 0x7d1c0000 } - }, /* jsri.a ${Dsp-16-u16}[sb] */ { { 0, 0, 0, 0 }, { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, - & ifmt_jsri16a_dst16_16_16_SI_dst16_16_16_SB_relative_SI, { 0x7d1e0000 } + & ifmt_jsri16a_dst16_16_16sa_SI_dst16_16_16_SB_relative_SI, { 0x7d1e0000 } }, /* jsri.a ${Dsp-16-u16} */ { { 0, 0, 0, 0 }, { { MNEM, ' ', OP (DSP_16_U16), 0 } }, - & ifmt_jsri16a_dst16_16_16_SI_dst16_16_16_absolute_SI, { 0x7d1f0000 } + & ifmt_jsri16a_dst16_16_16sa_SI_dst16_16_16_absolute_SI, { 0x7d1f0000 } }, /* jsri.a ${Dsp-16-u8}[$Dst32AnUnprefixed] */ { @@ -46170,17 +46166,23 @@ static const CGEN_OPCODE m32c_cgen_insn_opcode_table[MAX_INSNS] = { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, & ifmt_jsri16a_dst16_16_8_SI_dst16_16_8_FB_relative_SI, { 0x7d1b00 } }, -/* jsri.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */ +/* jsri.a ${Dsp-16-u24}[$Dst32AnUnprefixed] */ { { 0, 0, 0, 0 }, { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, - & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0xc71f0000 } + & ifmt_shl32_l_dst_dst32_16_24_An_relative_Unprefixed_SI, { 0x96010000 } }, -/* jsri.w ${Dsp-16-u24} */ +/* jsri.a ${Dsp-16-u24} */ { { 0, 0, 0, 0 }, { { MNEM, ' ', OP (DSP_16_U24), 0 } }, - & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0xc79f0000 } + & ifmt_shl32_l_dst_dst32_16_24_absolute_Unprefixed_SI, { 0x96810000 } + }, +/* jsri.a ${Dsp-16-u20}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U20), '[', OP (DST16AN), ']', 0 } }, + & ifmt_jsri16a_dst16_16_20ar_SI_dst16_16_20_An_relative_SI, { 0x7d1c0000 } }, /* jsri.w $Dst32RnUnprefixedHI */ { @@ -46218,11 +46220,41 @@ static const CGEN_OPCODE m32c_cgen_insn_opcode_table[MAX_INSNS] = { { MNEM, ' ', '[', OP (DST16AN), ']', 0 } }, & ifmt_shl16_w_dst_dst16_An_indirect_HI, { 0x7d36 } }, -/* jsri.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */ +/* jsri.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */ { { 0, 0, 0, 0 }, - { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, - & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0xc51f0000 } + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0xc31f00 } + }, +/* jsri.w ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0xc39f00 } + }, +/* jsri.w ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0xc3df00 } + }, +/* jsri.w ${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_shl16_w_dst_dst16_16_8_An_relative_HI, { 0x7d3800 } + }, +/* jsri.w ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl16_w_dst_dst16_16_8_SB_relative_HI, { 0x7d3a00 } + }, +/* jsri.w ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl16_w_dst_dst16_16_8_FB_relative_HI, { 0x7d3b00 } }, /* jsri.w ${Dsp-16-u16}[sb] */ { @@ -46242,12 +46274,6 @@ static const CGEN_OPCODE m32c_cgen_insn_opcode_table[MAX_INSNS] = { { MNEM, ' ', OP (DSP_16_U16), 0 } }, & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0xc7df0000 } }, -/* jsri.w ${Dsp-16-u16}[$Dst16An] */ - { - { 0, 0, 0, 0 }, - { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, - & ifmt_shl16_w_dst_dst16_16_16_An_relative_HI, { 0x7d3c0000 } - }, /* jsri.w ${Dsp-16-u16}[sb] */ { { 0, 0, 0, 0 }, @@ -46260,41 +46286,23 @@ static const CGEN_OPCODE m32c_cgen_insn_opcode_table[MAX_INSNS] = { { MNEM, ' ', OP (DSP_16_U16), 0 } }, & ifmt_shl16_w_dst_dst16_16_16_absolute_HI, { 0x7d3f0000 } }, -/* jsri.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */ - { - { 0, 0, 0, 0 }, - { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, - & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0xc31f00 } - }, -/* jsri.w ${Dsp-16-u8}[sb] */ - { - { 0, 0, 0, 0 }, - { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, - & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0xc39f00 } - }, -/* jsri.w ${Dsp-16-s8}[fb] */ - { - { 0, 0, 0, 0 }, - { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, - & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0xc3df00 } - }, -/* jsri.w ${Dsp-16-u8}[$Dst16An] */ +/* jsri.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */ { { 0, 0, 0, 0 }, - { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, - & ifmt_shl16_w_dst_dst16_16_8_An_relative_HI, { 0x7d3800 } + { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0xc71f0000 } }, -/* jsri.w ${Dsp-16-u8}[sb] */ +/* jsri.w ${Dsp-16-u24} */ { { 0, 0, 0, 0 }, - { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, - & ifmt_shl16_w_dst_dst16_16_8_SB_relative_HI, { 0x7d3a00 } + { { MNEM, ' ', OP (DSP_16_U24), 0 } }, + & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0xc79f0000 } }, -/* jsri.w ${Dsp-16-s8}[fb] */ +/* jsri.w ${Dsp-16-u20}[$Dst16An] */ { { 0, 0, 0, 0 }, - { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, - & ifmt_shl16_w_dst_dst16_16_8_FB_relative_HI, { 0x7d3b00 } + { { MNEM, ' ', OP (DSP_16_U20), '[', OP (DST16AN), ']', 0 } }, + & ifmt_jsri16w_dst16_16_20ar_HI_dst16_16_20_An_relative_HI, { 0x7d3c0000 } }, /* jmpi.a $Dst32RnUnprefixedSI */ { @@ -46396,7 +46404,7 @@ static const CGEN_OPCODE m32c_cgen_insn_opcode_table[MAX_INSNS] = { { 0, 0, 0, 0 }, { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, - & ifmt_jsri16a_dst16_16_16_SI_dst16_16_16_An_relative_SI, { 0x7d0c0000 } + & ifmt_jmpi16_a_16_dst16_16_16_An_relative_SI, { 0x7d0c0000 } }, /* jmpi.a ${Dsp-16-u8}[sb] */ { @@ -46408,7 +46416,7 @@ static const CGEN_OPCODE m32c_cgen_insn_opcode_table[MAX_INSNS] = { { 0, 0, 0, 0 }, { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, - & ifmt_jsri16a_dst16_16_16_SI_dst16_16_16_SB_relative_SI, { 0x7d0e0000 } + & ifmt_jsri16a_dst16_16_16sa_SI_dst16_16_16_SB_relative_SI, { 0x7d0e0000 } }, /* jmpi.a ${Dsp-16-s8}[fb] */ { @@ -46420,7 +46428,7 @@ static const CGEN_OPCODE m32c_cgen_insn_opcode_table[MAX_INSNS] = { { 0, 0, 0, 0 }, { { MNEM, ' ', OP (DSP_16_U16), 0 } }, - & ifmt_jsri16a_dst16_16_16_SI_dst16_16_16_absolute_SI, { 0x7d0f0000 } + & ifmt_jsri16a_dst16_16_16sa_SI_dst16_16_16_absolute_SI, { 0x7d0f0000 } }, /* jmpi.w $Dst32RnUnprefixedHI */ { @@ -80002,7 +80010,7 @@ static const CGEN_OPCODE m32c_cgen_insn_opcode_table[MAX_INSNS] = { { 0, 0, 0, 0 }, { { MNEM, ' ', '#', OP (IMM_8_QI), ',', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } }, - & ifmt_stzx16_imm8_imm8_abs16, { 0xde000000 } + & ifmt_stzx16_imm8_imm8_abs16, { 0xdf000000 } }, /* und */ { diff --git a/opcodes/m32c-opc.h b/opcodes/m32c-opc.h index 7f0e6e566d..50defe434a 100644 --- a/opcodes/m32c-opc.h +++ b/opcodes/m32c-opc.h @@ -1638,15 +1638,15 @@ typedef enum cgen_insn_type { , M32C_INSN_LDC16_DST_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_LDC16_DST_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_LDC16_DST_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_LDC16_DST_DST16_16_8_FB_RELATIVE_HI , M32C_INSN_LDC16_DST_DST16_16_16_ABSOLUTE_HI, M32C_INSN_JSRI32_A_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_JSRI32_A_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_JSRI32A_DST32_BASIC_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI , M32C_INSN_JSRI32A_DST32_BASIC_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_JSRI32A_DST32_BASIC_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_JSRI16A_DST16_BASIC_SI_DST16_RN_DIRECT_SI, M32C_INSN_JSRI16A_DST16_BASIC_SI_DST16_AN_DIRECT_SI - , M32C_INSN_JSRI16A_DST16_BASIC_SI_DST16_AN_INDIRECT_SI, M32C_INSN_JSRI32A_DST32_16_16_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_JSRI32A_DST32_16_16_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_JSRI32A_DST32_16_16_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI - , M32C_INSN_JSRI32A_DST32_16_16_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_JSRI16A_DST16_16_16_SI_DST16_16_16_AN_RELATIVE_SI, M32C_INSN_JSRI16A_DST16_16_16_SI_DST16_16_16_SB_RELATIVE_SI, M32C_INSN_JSRI16A_DST16_16_16_SI_DST16_16_16_ABSOLUTE_SI - , M32C_INSN_JSRI32A_DST32_16_8_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_JSRI32A_DST32_16_8_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_JSRI32A_DST32_16_8_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_JSRI16A_DST16_16_8_SI_DST16_16_8_AN_RELATIVE_SI - , M32C_INSN_JSRI16A_DST16_16_8_SI_DST16_16_8_SB_RELATIVE_SI, M32C_INSN_JSRI16A_DST16_16_8_SI_DST16_16_8_FB_RELATIVE_SI, M32C_INSN_JSRI32_W_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_JSRI32_W_DST32_16_24_ABSOLUTE_UNPREFIXED_HI - , M32C_INSN_JSRI32W_DST32_BASIC_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_JSRI32W_DST32_BASIC_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_JSRI32W_DST32_BASIC_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_JSRI16W_DST16_BASIC_HI_DST16_RN_DIRECT_HI - , M32C_INSN_JSRI16W_DST16_BASIC_HI_DST16_AN_DIRECT_HI, M32C_INSN_JSRI16W_DST16_BASIC_HI_DST16_AN_INDIRECT_HI, M32C_INSN_JSRI32W_DST32_16_16_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_JSRI32W_DST32_16_16_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI - , M32C_INSN_JSRI32W_DST32_16_16_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_JSRI32W_DST32_16_16_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_JSRI16W_DST16_16_16_HI_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_JSRI16W_DST16_16_16_HI_DST16_16_16_SB_RELATIVE_HI - , M32C_INSN_JSRI16W_DST16_16_16_HI_DST16_16_16_ABSOLUTE_HI, M32C_INSN_JSRI32W_DST32_16_8_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_JSRI32W_DST32_16_8_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_JSRI32W_DST32_16_8_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI - , M32C_INSN_JSRI16W_DST16_16_8_HI_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_JSRI16W_DST16_16_8_HI_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_JSRI16W_DST16_16_8_HI_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI + , M32C_INSN_JSRI16A_DST16_BASIC_SI_DST16_AN_INDIRECT_SI, M32C_INSN_JSRI32A_DST32_16_16SA_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_JSRI32A_DST32_16_16SA_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_JSRI32A_DST32_16_16SA_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI + , M32C_INSN_JSRI16A_DST16_16_16SA_SI_DST16_16_16_SB_RELATIVE_SI, M32C_INSN_JSRI16A_DST16_16_16SA_SI_DST16_16_16_ABSOLUTE_SI, M32C_INSN_JSRI32A_DST32_16_8_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_JSRI32A_DST32_16_8_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_JSRI32A_DST32_16_8_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_JSRI16A_DST16_16_8_SI_DST16_16_8_AN_RELATIVE_SI, M32C_INSN_JSRI16A_DST16_16_8_SI_DST16_16_8_SB_RELATIVE_SI, M32C_INSN_JSRI16A_DST16_16_8_SI_DST16_16_8_FB_RELATIVE_SI + , M32C_INSN_JSRI32A_DST32_16_24_UNPREFIXED_SI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_JSRI32A_DST32_16_24_UNPREFIXED_SI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_JSRI16A_DST16_16_20AR_SI_DST16_16_20_AN_RELATIVE_SI, M32C_INSN_JSRI32W_DST32_BASIC_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI + , M32C_INSN_JSRI32W_DST32_BASIC_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_JSRI32W_DST32_BASIC_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_JSRI16W_DST16_BASIC_HI_DST16_RN_DIRECT_HI, M32C_INSN_JSRI16W_DST16_BASIC_HI_DST16_AN_DIRECT_HI + , M32C_INSN_JSRI16W_DST16_BASIC_HI_DST16_AN_INDIRECT_HI, M32C_INSN_JSRI32W_DST32_16_8_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_JSRI32W_DST32_16_8_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_JSRI32W_DST32_16_8_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_JSRI16W_DST16_16_8_HI_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_JSRI16W_DST16_16_8_HI_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_JSRI16W_DST16_16_8_HI_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_JSRI32W_DST32_16_16SA_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_JSRI32W_DST32_16_16SA_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_JSRI32W_DST32_16_16SA_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_JSRI16W_DST16_16_16SA_HI_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_JSRI16W_DST16_16_16SA_HI_DST16_16_16_ABSOLUTE_HI + , M32C_INSN_JSRI32W_DST32_16_24_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_JSRI32W_DST32_16_24_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_JSRI16W_DST16_16_20AR_HI_DST16_16_20_AN_RELATIVE_HI, M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI , M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI , M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI , M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_JMPI16_A_16_DST16_RN_DIRECT_SI @@ -3186,8 +3186,10 @@ struct cgen_fields long f_dsp_16_u24; long f_dsp_24_u24; long f_dsp_32_u24; + long f_dsp_40_u20; long f_dsp_40_u24; long f_dsp_40_s32; + long f_dsp_48_u20; long f_dsp_48_u24; long f_dsp_16_s32; long f_dsp_24_s32; -- 2.34.1