From 353abf7c10561aab3e8e7ffce6e270c3743376f0 Mon Sep 17 00:00:00 2001 From: "Maciej W. Rozycki" Date: Wed, 14 Dec 2016 21:18:16 +0000 Subject: [PATCH] MIPS16: Fix SP-relative SD instruction annotation Fix the annotation of SP-relative SD instructions incorrectly marked as reading from the PC rather than SP, which in turn prevented their 16-bit forms from being scheduled into jump delay slots. This bug has been there since forever. opcodes/ * mips16-opc.c (mips16_opcodes): Set RD_SP rather than RD_PC in `pinfo2' with SP-relative "sd" entries. gas/ * testsuite/gas/mips/mips16-sprel-swap.d: New test. * testsuite/gas/mips/mips16-sprel-swap.s: New test source. * testsuite/gas/mips/mips.exp: Run the new test. --- gas/ChangeLog | 6 ++++++ gas/testsuite/gas/mips/mips.exp | 1 + gas/testsuite/gas/mips/mips16-sprel-swap.d | 20 ++++++++++++++++++ gas/testsuite/gas/mips/mips16-sprel-swap.s | 24 ++++++++++++++++++++++ opcodes/ChangeLog | 5 +++++ opcodes/mips16-opc.c | 4 ++-- 6 files changed, 58 insertions(+), 2 deletions(-) create mode 100644 gas/testsuite/gas/mips/mips16-sprel-swap.d create mode 100644 gas/testsuite/gas/mips/mips16-sprel-swap.s diff --git a/gas/ChangeLog b/gas/ChangeLog index b2eaa8d962..742da3ecfd 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,9 @@ +2016-12-14 Maciej W. Rozycki + + * testsuite/gas/mips/mips16-sprel-swap.d: New test. + * testsuite/gas/mips/mips16-sprel-swap.s: New test source. + * testsuite/gas/mips/mips.exp: Run the new test. + 2016-12-13 Renlin Li * config/tc-aarch64.c (AARCH64_REG_TYPES): Remove CN register. diff --git a/gas/testsuite/gas/mips/mips.exp b/gas/testsuite/gas/mips/mips.exp index 38c57f4f7b..da8d5693db 100644 --- a/gas/testsuite/gas/mips/mips.exp +++ b/gas/testsuite/gas/mips/mips.exp @@ -1296,6 +1296,7 @@ if { [istarget mips*-*-vxworks*] } { run_list_test "mips16e-64" "-march=mips32 -32" run_dump_test "mips16-intermix" run_dump_test "mips16-extend" + run_dump_test "mips16-sprel-swap" run_dump_test "vxworks1" run_dump_test "vxworks1-xgot" diff --git a/gas/testsuite/gas/mips/mips16-sprel-swap.d b/gas/testsuite/gas/mips/mips16-sprel-swap.d new file mode 100644 index 0000000000..3b34fc8d8c --- /dev/null +++ b/gas/testsuite/gas/mips/mips16-sprel-swap.d @@ -0,0 +1,20 @@ +#objdump: -d --prefix-addresses --show-raw-insn +#name: MIPS16 jump delay slot scheduling for SP-relative instructions +#as: -32 + +.*: +file format .*mips.* + +Disassembly of section \.text: +[0-9a-f]+ <[^>]*> eb00 jr v1 +[0-9a-f]+ <[^>]*> d204 sw v0,16\(sp\) +[0-9a-f]+ <[^>]*> eb00 jr v1 +[0-9a-f]+ <[^>]*> 6206 sw ra,24\(sp\) +[0-9a-f]+ <[^>]*> eb00 jr v1 +[0-9a-f]+ <[^>]*> f944 sd v0,32\(sp\) +[0-9a-f]+ <[^>]*> eb00 jr v1 +[0-9a-f]+ <[^>]*> fa05 sd ra,40\(sp\) +[0-9a-f]+ <[^>]*> eb00 jr v1 +[0-9a-f]+ <[^>]*> 920c lw v0,48\(sp\) +[0-9a-f]+ <[^>]*> eb00 jr v1 +[0-9a-f]+ <[^>]*> f847 ld v0,56\(sp\) + \.\.\. diff --git a/gas/testsuite/gas/mips/mips16-sprel-swap.s b/gas/testsuite/gas/mips/mips16-sprel-swap.s new file mode 100644 index 0000000000..3538158e03 --- /dev/null +++ b/gas/testsuite/gas/mips/mips16-sprel-swap.s @@ -0,0 +1,24 @@ + .module mips3 + .set mips16 +foo: + sw $2, 0x10($29) + jr $3 + + sw $31, 0x18($29) + jr $3 + + sd $2, 0x20($29) + jr $3 + + sd $31, 0x28($29) + jr $3 + + lw $2, 0x30($29) + jr $3 + + ld $2, 0x38($29) + jr $3 + +# Force some (non-delay-slot) zero bytes, to make 'objdump' print ... + .align 4, 0 + .space 16 diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index ed5764bb8b..0138a9e5f6 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,8 @@ +2016-12-14 Maciej W. Rozycki + + * mips16-opc.c (mips16_opcodes): Set RD_SP rather than RD_PC in + `pinfo2' with SP-relative "sd" entries. + 2016-12-14 Maciej W. Rozycki * mips16-opc.c (mips16_opcodes): Update comments on MIPS16e diff --git a/opcodes/mips16-opc.c b/opcodes/mips16-opc.c index 0fcefc6d24..3c90147e90 100644 --- a/opcodes/mips16-opc.c +++ b/opcodes/mips16-opc.c @@ -321,8 +321,8 @@ const struct mips_opcode mips16_opcodes[] = {"remu", "z,v,y", 0, (int) M_REMU_3, INSN_MACRO, 0, I1, 0, 0 }, {"sb", "y,5(x)", 0xc000, 0xf800, RD_1|RD_3, 0, I1, 0, 0 }, {"sd", "y,D(x)", 0x7800, 0xf800, RD_1|RD_3, 0, I3, 0, 0 }, -{"sd", "y,D(S)", 0xf900, 0xff00, RD_1, RD_PC, I3, 0, 0 }, -{"sd", "R,C(S)", 0xfa00, 0xff00, 0, RD_31|RD_PC, I1, 0, 0 }, +{"sd", "y,D(S)", 0xf900, 0xff00, RD_1, RD_SP, I3, 0, 0 }, +{"sd", "R,C(S)", 0xfa00, 0xff00, 0, RD_31|RD_SP, I1, 0, 0 }, {"sh", "y,H(x)", 0xc800, 0xf800, RD_1|RD_3, 0, I1, 0, 0 }, {"sllv", "y,x", 0xe804, 0xf81f, MOD_1|RD_2, 0, I1, 0, 0 }, {"sll", "x,w,<", 0x3000, 0xf803, WR_1|RD_2, 0, I1, 0, 0 }, -- 2.34.1