From 5c936ef50f02fe21a6e1306e30849b4487c65b2c Mon Sep 17 00:00:00 2001 From: Nick Clifton Date: Wed, 29 Apr 2020 13:13:55 +0100 Subject: [PATCH] Fix the disassmbly of SH instructions which have an unsigned 8-bit immediate operand. PR 22699 opcodes * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U. Use IMM0_8S for arithmetic insns and IMM0_8U for logical insns. * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add IMM0_8U case. gas * config/tc-sh.c (build_Mytes): Change operand type IMM0_8 to IMM0_8S and add support for IMM0_8U. * testsuite/gas/sh/sh4a.s: Add test of a logical insn using an unsigned 8-bit immediate. * testsuite/gas/sh/sh4a.d: Extended expected disassembly. --- gas/ChangeLog | 9 +++++++++ gas/config/tc-sh.c | 3 ++- gas/testsuite/gas/sh/sh4a.d | 2 ++ gas/testsuite/gas/sh/sh4a.s | 2 ++ opcodes/ChangeLog | 8 ++++++++ opcodes/sh-dis.c | 6 +++++- opcodes/sh-opc.h | 35 ++++++++++++++++++----------------- 7 files changed, 46 insertions(+), 19 deletions(-) diff --git a/gas/ChangeLog b/gas/ChangeLog index 8cbe5ecf2b..8df687bbb7 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,12 @@ +2020-04-29 Nick Clifton + + PR 22699 + * config/tc-sh.c (build_Mytes): Change operand type IMM0_8 to + IMM0_8S and add support for IMM0_8U. + * testsuite/gas/sh/sh4a.s: Add test of a logical insn using an + unsigned 8-bit immediate. + * testsuite/gas/sh/sh4a.d: Extended expected disassembly. + 2020-04-27 Tamar Christina * NEWS: Add news entry for big-obj. diff --git a/gas/config/tc-sh.c b/gas/config/tc-sh.c index decbb29a16..d06cc5e9b8 100644 --- a/gas/config/tc-sh.c +++ b/gas/config/tc-sh.c @@ -2091,7 +2091,8 @@ build_Mytes (sh_opcode_info *opcode, sh_operand_info *operand) case IMM0_8BY2: insert (output + low_byte, BFD_RELOC_SH_IMM8BY2, 0, operand); break; - case IMM0_8: + case IMM0_8U: + case IMM0_8S: insert (output + low_byte, BFD_RELOC_SH_IMM8, 0, operand); break; case IMM1_8BY4: diff --git a/gas/testsuite/gas/sh/sh4a.d b/gas/testsuite/gas/sh/sh4a.d index 0cdbf330da..45fade6a7e 100644 --- a/gas/testsuite/gas/sh/sh4a.d +++ b/gas/testsuite/gas/sh/sh4a.d @@ -25,3 +25,5 @@ Disassembly of section \.text: 0x0000001e 05 d3 prefi @r5 0x00000020 0a d3 prefi @r10 0x00000022 00 ab synco +0x00000024 c8 80[ ]+tst[ ]+#128,r0 +#pass diff --git a/gas/testsuite/gas/sh/sh4a.s b/gas/testsuite/gas/sh/sh4a.s index 51c2382e3a..6b68ec2a3d 100644 --- a/gas/testsuite/gas/sh/sh4a.s +++ b/gas/testsuite/gas/sh/sh4a.s @@ -26,3 +26,5 @@ prefi @r10 synco + + tst #128,r0 diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index e2cbe60cde..94b8a03a8d 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,11 @@ +2020-04-29 Nick Clifton + + PR 22699 + * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U. Use + IMM0_8S for arithmetic insns and IMM0_8U for logical insns. + * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add + IMM0_8U case. + 2020-04-21 Andreas Schwab PR 25848 diff --git a/opcodes/sh-dis.c b/opcodes/sh-dis.c index 5d771a53a5..00bcffa7c7 100644 --- a/opcodes/sh-dis.c +++ b/opcodes/sh-dis.c @@ -597,7 +597,7 @@ print_insn_sh (bfd_vma memaddr, struct disassemble_info *info) case IMM1_4BY4: imm = nibs[3] << 2; goto ok; - case IMM0_8: + case IMM0_8S: case IMM1_8: imm = (nibs[2] << 4) | nibs[3]; disp = imm; @@ -605,6 +605,10 @@ print_insn_sh (bfd_vma memaddr, struct disassemble_info *info) if (imm & 0x80) imm -= 0x100; goto ok; + case IMM0_8U: + disp = imm = (nibs[2] << 4) | nibs[3]; + has_disp = 1; + goto ok; case PCRELIMM_8BY2: imm = ((nibs[2] << 4) | nibs[3]) << 1; relmask = ~(bfd_vma) 1; diff --git a/opcodes/sh-opc.h b/opcodes/sh-opc.h index 93b5e983e7..cd9d2c27a3 100644 --- a/opcodes/sh-opc.h +++ b/opcodes/sh-opc.h @@ -61,7 +61,8 @@ typedef enum IMM1_4BY4, PCRELIMM_8BY2, PCRELIMM_8BY4, - IMM0_8, + IMM0_8S, + IMM0_8U, IMM0_8BY2, IMM0_8BY4, IMM1_8, @@ -381,7 +382,7 @@ typedef struct const sh_opcode_info sh_table[] = { -/* 0111nnnni8*1.... add #, */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}, +/* 0111nnnni8*1.... add #, */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8S}, arch_sh_up}, /* 0011nnnnmmmm1100 add , */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}, @@ -389,11 +390,11 @@ const sh_opcode_info sh_table[] = /* 0011nnnnmmmm1111 addv ,*/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh_up}, -/* 11001001i8*1.... and #,R0 */{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh_up}, +/* 11001001i8*1.... and #,R0 */{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8U}, arch_sh_up}, /* 0010nnnnmmmm1001 and , */{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh_up}, -/* 11001101i8*1.... and.b #,@(R0,GBR)*/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh_up}, +/* 11001101i8*1.... and.b #,@(R0,GBR)*/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8U}, arch_sh_up}, /* 1010i12......... bra */{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh_up}, @@ -419,7 +420,7 @@ const sh_opcode_info sh_table[] = /* 0000000000001000 clrt */{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh_up}, -/* 10001000i8*1.... cmp/eq #,R0 */{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh_up}, +/* 10001000i8*1.... cmp/eq #,R0 */{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8S}, arch_sh_up}, /* 0011nnnnmmmm0000 cmp/eq ,*/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh_up}, @@ -504,7 +505,7 @@ const sh_opcode_info sh_table[] = /* 0100nnnn1xxx0111 ldc.l @+,Rn_BANK */{"ldc.l",{A_INC_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_7}, arch_sh3_nommu_up}, /* 0100mmmm00110100 ldrc */{"ldrc",{A_REG_M},{HEX_4,REG_M,HEX_3,HEX_4}, arch_sh4al_dsp_up}, -/* 10001010i8*1.... ldrc # */{"ldrc",{A_IMM},{HEX_8,HEX_A,IMM0_8}, arch_sh4al_dsp_up}, +/* 10001010i8*1.... ldrc # */{"ldrc",{A_IMM},{HEX_8,HEX_A,IMM0_8S}, arch_sh4al_dsp_up}, /* 10001110i8p2.... ldre @(,PC) */{"ldre",{A_DISP_PC},{HEX_8,HEX_E,PCRELIMM_8BY2}, arch_sh_dsp_up}, @@ -558,7 +559,7 @@ const sh_opcode_info sh_table[] = /* 0100nnnnmmmm1111 mac.w @+,@+*/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh_up}, -/* 1110nnnni8*1.... mov #, */{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh_up}, +/* 1110nnnni8*1.... mov #, */{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8S}, arch_sh_up}, /* 0110nnnnmmmm0011 mov , */{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh_up}, @@ -570,7 +571,7 @@ const sh_opcode_info sh_table[] = /* 10000100mmmmi4*1 mov.b @(,),R0*/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh_up}, -/* 11000100i8*1.... mov.b @(,GBR),R0*/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh_up}, +/* 11000100i8*1.... mov.b @(,GBR),R0*/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8S}, arch_sh_up}, /* 0000nnnnmmmm1100 mov.b @(R0,),*/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh_up}, @@ -677,11 +678,11 @@ const sh_opcode_info sh_table[] = /* 0000nnnn10110011 ocbwb @ */{"ocbwb",{A_IND_N},{HEX_0,REG_N,HEX_B,HEX_3}, arch_sh4_nommu_nofpu_up}, -/* 11001011i8*1.... or #,R0 */{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh_up}, +/* 11001011i8*1.... or #,R0 */{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8U}, arch_sh_up}, /* 0010nnnnmmmm1011 or , */{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh_up}, -/* 11001111i8*1.... or.b #,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh_up}, +/* 11001111i8*1.... or.b #,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8U}, arch_sh_up}, /* 0000nnnn10000011 pref @ */{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh2a_nofpu_or_sh3_nommu_up}, @@ -707,11 +708,11 @@ const sh_opcode_info sh_table[] = /* 0100nnnn00010100 setrc */{"setrc",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_4}, arch_sh_dsp_up}, -/* 10000010i8*1.... setrc # */{"setrc",{A_IMM},{HEX_8,HEX_2,IMM0_8}, arch_sh_dsp_up}, +/* 10000010i8*1.... setrc # */{"setrc",{A_IMM},{HEX_8,HEX_2,IMM0_8S}, arch_sh_dsp_up}, /* repeat start end */{"repeat",{A_DISP_PC,A_DISP_PC,A_REG_N},{REPEAT,REG_N,HEX_1,HEX_4}, arch_sh_dsp_up}, -/* repeat start end # */{"repeat",{A_DISP_PC,A_DISP_PC,A_IMM},{REPEAT,HEX_2,IMM0_8,HEX_8}, arch_sh_dsp_up}, +/* repeat start end # */{"repeat",{A_DISP_PC,A_DISP_PC,A_IMM},{REPEAT,HEX_2,IMM0_8S,HEX_8}, arch_sh_dsp_up}, /* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}, @@ -843,19 +844,19 @@ const sh_opcode_info sh_table[] = /* 0100nnnn00011011 tas.b @ */{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh_up}, -/* 11000011i8*1.... trapa # */{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh_up}, +/* 11000011i8*1.... trapa # */{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8U}, arch_sh_up}, -/* 11001000i8*1.... tst #,R0 */{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh_up}, +/* 11001000i8*1.... tst #,R0 */{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8U}, arch_sh_up}, /* 0010nnnnmmmm1000 tst , */{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh_up}, -/* 11001100i8*1.... tst.b #,@(R0,GBR)*/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh_up}, +/* 11001100i8*1.... tst.b #,@(R0,GBR)*/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8U}, arch_sh_up}, -/* 11001010i8*1.... xor #,R0 */{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh_up}, +/* 11001010i8*1.... xor #,R0 */{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8U}, arch_sh_up}, /* 0010nnnnmmmm1010 xor , */{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh_up}, -/* 11001110i8*1.... xor.b #,@(R0,GBR)*/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh_up}, +/* 11001110i8*1.... xor.b #,@(R0,GBR)*/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8U}, arch_sh_up}, /* 0010nnnnmmmm1101 xtrct ,*/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh_up}, -- 2.34.1