From ac1b0e6d011306988d78708017c4b0035f801982 Mon Sep 17 00:00:00 2001
From: Dave Brolley <brolley@redhat.com>
Date: Fri, 4 Dec 1998 22:08:56 +0000
Subject: [PATCH] Fri Dec  4 17:08:08 1998  Dave Brolley  <brolley@cygnus.com>

	* fr30-asm.c,fr30-dis.c,fr30-opc.c,fr30-opc.h: Regenerated.
---
 opcodes/ChangeLog  |   8 +
 opcodes/fr30-asm.c |  50 +++---
 opcodes/fr30-dis.c |  58 ++++---
 opcodes/fr30-opc.c | 425 +++++++++++++++++++++++++++++++++------------
 opcodes/fr30-opc.h |  11 +-
 5 files changed, 389 insertions(+), 163 deletions(-)

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 10c17b5ac0..30fc9d0a44 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,4 +1,12 @@
 start-sanitize-fr30
+Fri Dec  4 17:08:08 1998  Dave Brolley  <brolley@cygnus.com>
+
+	* fr30-asm.c,fr30-dis.c,fr30-opc.c,fr30-opc.h: Regenerated.
+
+Thu Dec  3 14:26:20 1998  Dave Brolley  <brolley@cygnus.com>
+
+	* fr30-asm.c,fr30-dis.c,fr30-opc.c,fr30-opc.h: Regenerated.
+
 Thu Dec  3 00:09:17 1998  Doug Evans  <devans@canuck.cygnus.com>
 
 	* fr30-asm.c,fr30-dis.c,fr30-opc.c,fr30-opc.h: Regenerate.
diff --git a/opcodes/fr30-asm.c b/opcodes/fr30-asm.c
index 32b47a3109..54418bf2c1 100644
--- a/opcodes/fr30-asm.c
+++ b/opcodes/fr30-asm.c
@@ -157,9 +157,6 @@ fr30_cgen_parse_operand (od, opindex, strp, fields)
     case FR30_OPERAND_U4C :
       errmsg = cgen_parse_unsigned_integer (od, strp, FR30_OPERAND_U4C, &fields->f_u4c);
       break;
-    case FR30_OPERAND_M4 :
-      errmsg = cgen_parse_unsigned_integer (od, strp, FR30_OPERAND_M4, &fields->f_m4);
-      break;
     case FR30_OPERAND_U8 :
       errmsg = cgen_parse_unsigned_integer (od, strp, FR30_OPERAND_U8, &fields->f_u8);
       break;
@@ -187,16 +184,12 @@ fr30_cgen_parse_operand (od, opindex, strp, fields)
     case FR30_OPERAND_I32 :
       errmsg = cgen_parse_unsigned_integer (od, strp, FR30_OPERAND_I32, &fields->f_i32);
       break;
+    case FR30_OPERAND_M4 :
+      errmsg = cgen_parse_signed_integer (od, strp, FR30_OPERAND_M4, &fields->f_m4);
+      break;
     case FR30_OPERAND_I20 :
       errmsg = cgen_parse_unsigned_integer (od, strp, FR30_OPERAND_I20, &fields->f_i20);
       break;
-    case FR30_OPERAND_LABEL9 :
-      {
-        bfd_vma value;
-        errmsg = cgen_parse_address (od, strp, FR30_OPERAND_LABEL9, 0, NULL,  & value);
-        fields->f_rel9 = value;
-      }
-      break;
     case FR30_OPERAND_DIR8 :
       errmsg = cgen_parse_unsigned_integer (od, strp, FR30_OPERAND_DIR8, &fields->f_dir8);
       break;
@@ -206,6 +199,13 @@ fr30_cgen_parse_operand (od, opindex, strp, fields)
     case FR30_OPERAND_DIR10 :
       errmsg = cgen_parse_unsigned_integer (od, strp, FR30_OPERAND_DIR10, &fields->f_dir10);
       break;
+    case FR30_OPERAND_LABEL9 :
+      {
+        bfd_vma value;
+        errmsg = cgen_parse_address (od, strp, FR30_OPERAND_LABEL9, 0, NULL,  & value);
+        fields->f_rel9 = value;
+      }
+      break;
     case FR30_OPERAND_LABEL12 :
       {
         bfd_vma value;
@@ -305,13 +305,6 @@ fr30_cgen_insert_operand (od, opindex, fields, buffer, pc)
     case FR30_OPERAND_U4C :
       errmsg = insert_normal (od, fields->f_u4c, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), 0, 12, 4, 16, total_length, buffer);
       break;
-    case FR30_OPERAND_M4 :
-      {
-        long value = fields->f_m4;
-        value = ((value) & (15));
-        errmsg = insert_normal (od, value, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), 0, 8, 4, 16, total_length, buffer);
-      }
-      break;
     case FR30_OPERAND_U8 :
       errmsg = insert_normal (od, fields->f_u8, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), 0, 8, 8, 16, total_length, buffer);
       break;
@@ -359,6 +352,13 @@ fr30_cgen_insert_operand (od, opindex, fields, buffer, pc)
     case FR30_OPERAND_I32 :
       errmsg = insert_normal (od, fields->f_i32, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_SIGN_OPT)|(1<<CGEN_OPERAND_UNSIGNED), 16, 0, 32, 32, total_length, buffer);
       break;
+    case FR30_OPERAND_M4 :
+      {
+        long value = fields->f_m4;
+        value = ((value) & (15));
+        errmsg = insert_normal (od, value, 0|(1<<CGEN_OPERAND_UNSIGNED), 0, 8, 4, 16, total_length, buffer);
+      }
+      break;
     case FR30_OPERAND_I20 :
       {
 do {
@@ -373,13 +373,6 @@ do {
           break;
       }
       break;
-    case FR30_OPERAND_LABEL9 :
-      {
-        long value = fields->f_rel9;
-        value = ((int) (((value) - (((pc) + (2))))) >> (1));
-        errmsg = insert_normal (od, value, 0|(1<<CGEN_OPERAND_PCREL_ADDR)|(1<<CGEN_OPERAND_SIGNED), 0, 8, 8, 16, total_length, buffer);
-      }
-      break;
     case FR30_OPERAND_DIR8 :
       errmsg = insert_normal (od, fields->f_dir8, 0|(1<<CGEN_OPERAND_UNSIGNED), 0, 8, 8, 16, total_length, buffer);
       break;
@@ -397,10 +390,17 @@ do {
         errmsg = insert_normal (od, value, 0|(1<<CGEN_OPERAND_UNSIGNED), 0, 8, 8, 16, total_length, buffer);
       }
       break;
+    case FR30_OPERAND_LABEL9 :
+      {
+        long value = fields->f_rel9;
+        value = ((int) (((value) - (((pc) + (2))))) >> (1));
+        errmsg = insert_normal (od, value, 0|(1<<CGEN_OPERAND_PCREL_ADDR)|(1<<CGEN_OPERAND_SIGNED), 0, 8, 8, 16, total_length, buffer);
+      }
+      break;
     case FR30_OPERAND_LABEL12 :
       {
         long value = fields->f_rel12;
-        value = ((int) (((value) - (((pc) & (-2))))) >> (1));
+        value = ((int) (((value) - (((pc) + (2))))) >> (1));
         errmsg = insert_normal (od, value, 0|(1<<CGEN_OPERAND_PCREL_ADDR)|(1<<CGEN_OPERAND_SIGNED), 0, 5, 11, 16, total_length, buffer);
       }
       break;
diff --git a/opcodes/fr30-dis.c b/opcodes/fr30-dis.c
index 76ca0958fd..b0b8414fd7 100644
--- a/opcodes/fr30-dis.c
+++ b/opcodes/fr30-dis.c
@@ -112,6 +112,18 @@ print_low_register_list (od, dis_info, value, attrs, pc, length)
   print_register_list (dis_info, value, 0);
 }
 
+static void
+print_m4 (od, dis_info, value, attrs, pc, length)
+     CGEN_OPCODE_DESC od;
+     PTR dis_info;
+     long value;
+     unsigned int attrs;
+     bfd_vma pc;
+     int length;
+{
+  disassemble_info *info = (disassemble_info *) dis_info;
+  (*info->fprintf_func) (info->stream, "%ld", value);
+}
 /* -- */
 
 /* Main entry point for operand extraction.
@@ -184,14 +196,6 @@ fr30_cgen_extract_operand (od, opindex, ex_info, insn_value, fields, pc)
     case FR30_OPERAND_U4C :
       length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), 0, 12, 4, 16, total_length, pc, & fields->f_u4c);
       break;
-    case FR30_OPERAND_M4 :
-      {
-        long value;
-        length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), 0, 8, 4, 16, total_length, pc, & value);
-        value = ((value) | ((! (15))));
-        fields->f_m4 = value;
-      }
-      break;
     case FR30_OPERAND_U8 :
       length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), 0, 8, 8, 16, total_length, pc, & fields->f_u8);
       break;
@@ -244,6 +248,14 @@ fr30_cgen_extract_operand (od, opindex, ex_info, insn_value, fields, pc)
     case FR30_OPERAND_I32 :
       length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_SIGN_OPT)|(1<<CGEN_OPERAND_UNSIGNED), 16, 0, 32, 32, total_length, pc, & fields->f_i32);
       break;
+    case FR30_OPERAND_M4 :
+      {
+        long value;
+        length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 0, 8, 4, 16, total_length, pc, & value);
+        value = ((value) | (((-1) << (4))));
+        fields->f_m4 = value;
+      }
+      break;
     case FR30_OPERAND_I20 :
       {
         length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED)|(1<<CGEN_OPERAND_VIRTUAL), 0, 8, 4, 16, total_length, pc, & fields->f_i20_4);
@@ -253,14 +265,6 @@ do {
 } while (0);
       }
       break;
-    case FR30_OPERAND_LABEL9 :
-      {
-        long value;
-        length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_PCREL_ADDR)|(1<<CGEN_OPERAND_SIGNED), 0, 8, 8, 16, total_length, pc, & value);
-        value = ((((value) << (1))) + (((pc) + (2))));
-        fields->f_rel9 = value;
-      }
-      break;
     case FR30_OPERAND_DIR8 :
       length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 0, 8, 8, 16, total_length, pc, & fields->f_dir8);
       break;
@@ -280,11 +284,19 @@ do {
         fields->f_dir10 = value;
       }
       break;
+    case FR30_OPERAND_LABEL9 :
+      {
+        long value;
+        length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_PCREL_ADDR)|(1<<CGEN_OPERAND_SIGNED), 0, 8, 8, 16, total_length, pc, & value);
+        value = ((((value) << (1))) + (((pc) + (2))));
+        fields->f_rel9 = value;
+      }
+      break;
     case FR30_OPERAND_LABEL12 :
       {
         long value;
         length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_PCREL_ADDR)|(1<<CGEN_OPERAND_SIGNED), 0, 5, 11, 16, total_length, pc, & value);
-        value = ((((value) << (1))) + (((pc) & (-2))));
+        value = ((((value) << (1))) + (((pc) + (2))));
         fields->f_rel12 = value;
       }
       break;
@@ -379,9 +391,6 @@ fr30_cgen_print_operand (od, opindex, info, fields, attrs, pc, length)
     case FR30_OPERAND_U4C :
       print_normal (od, info, fields->f_u4c, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), pc, length);
       break;
-    case FR30_OPERAND_M4 :
-      print_normal (od, info, fields->f_m4, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), pc, length);
-      break;
     case FR30_OPERAND_U8 :
       print_normal (od, info, fields->f_u8, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), pc, length);
       break;
@@ -409,12 +418,12 @@ fr30_cgen_print_operand (od, opindex, info, fields, attrs, pc, length)
     case FR30_OPERAND_I32 :
       print_normal (od, info, fields->f_i32, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_SIGN_OPT)|(1<<CGEN_OPERAND_UNSIGNED), pc, length);
       break;
+    case FR30_OPERAND_M4 :
+      print_m4 (od, info, fields->f_m4, 0|(1<<CGEN_OPERAND_UNSIGNED), pc, length);
+      break;
     case FR30_OPERAND_I20 :
       print_normal (od, info, fields->f_i20, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED)|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
       break;
-    case FR30_OPERAND_LABEL9 :
-      print_address (od, info, fields->f_rel9, 0|(1<<CGEN_OPERAND_PCREL_ADDR)|(1<<CGEN_OPERAND_SIGNED), pc, length);
-      break;
     case FR30_OPERAND_DIR8 :
       print_normal (od, info, fields->f_dir8, 0|(1<<CGEN_OPERAND_UNSIGNED), pc, length);
       break;
@@ -424,6 +433,9 @@ fr30_cgen_print_operand (od, opindex, info, fields, attrs, pc, length)
     case FR30_OPERAND_DIR10 :
       print_normal (od, info, fields->f_dir10, 0|(1<<CGEN_OPERAND_UNSIGNED), pc, length);
       break;
+    case FR30_OPERAND_LABEL9 :
+      print_address (od, info, fields->f_rel9, 0|(1<<CGEN_OPERAND_PCREL_ADDR)|(1<<CGEN_OPERAND_SIGNED), pc, length);
+      break;
     case FR30_OPERAND_LABEL12 :
       print_address (od, info, fields->f_rel12, 0|(1<<CGEN_OPERAND_PCREL_ADDR)|(1<<CGEN_OPERAND_SIGNED), pc, length);
       break;
diff --git a/opcodes/fr30-opc.c b/opcodes/fr30-opc.c
index 941989b10c..85161975da 100644
--- a/opcodes/fr30-opc.c
+++ b/opcodes/fr30-opc.c
@@ -390,6 +390,8 @@ static const CGEN_HW_ENTRY fr30_cgen_hw_entries[] =
   { HW_H_IBIT, & HW_ENT (HW_H_IBIT + 1), "h-ibit", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
   { HW_H_SBIT, & HW_ENT (HW_H_SBIT + 1), "h-sbit", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
   { HW_H_CCR, & HW_ENT (HW_H_CCR + 1), "h-ccr", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0|(1<<CGEN_HW_FUN_ACCESS), { 0 } } },
+  { HW_H_SCR, & HW_ENT (HW_H_SCR + 1), "h-scr", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0|(1<<CGEN_HW_FUN_ACCESS), { 0 } } },
+  { HW_H_ILM, & HW_ENT (HW_H_ILM + 1), "h-ilm", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0|(1<<CGEN_HW_FUN_ACCESS), { 0 } } },
   { 0 }
 };
 
@@ -523,9 +525,6 @@ const CGEN_OPERAND fr30_cgen_operand_table[MAX_OPERANDS] =
 /* i20: 20 bit immediate */
   { "i20", & HW_ENT (HW_H_UINT), 0, 20,
     { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED)|(1<<CGEN_OPERAND_VIRTUAL), { 0 } }  },
-/* label9: 9  bit pc relative address */
-  { "label9", & HW_ENT (HW_H_IADDR), 8, 8,
-    { 0, 0|(1<<CGEN_OPERAND_PCREL_ADDR)|(1<<CGEN_OPERAND_SIGNED), { 0 } }  },
 /* dir8: 8  bit direct address */
   { "dir8", & HW_ENT (HW_H_UINT), 8, 8,
     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
@@ -535,6 +534,9 @@ const CGEN_OPERAND fr30_cgen_operand_table[MAX_OPERANDS] =
 /* dir10: 10 bit direct address */
   { "dir10", & HW_ENT (HW_H_UINT), 8, 8,
     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
+/* label9: 9  bit pc relative address */
+  { "label9", & HW_ENT (HW_H_IADDR), 8, 8,
+    { 0, 0|(1<<CGEN_OPERAND_PCREL_ADDR)|(1<<CGEN_OPERAND_SIGNED), { 0 } }  },
 /* label12: 12 bit pc relative address */
   { "label12", & HW_ENT (HW_H_IADDR), 5, 11,
     { 0, 0|(1<<CGEN_OPERAND_PCREL_ADDR)|(1<<CGEN_OPERAND_SIGNED), { 0 } }  },
@@ -571,6 +573,12 @@ const CGEN_OPERAND fr30_cgen_operand_table[MAX_OPERANDS] =
 /* ccr: condition code bits */
   { "ccr", & HW_ENT (HW_H_CCR), 0, 0,
     { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } }  },
+/* scr: system condition bits */
+  { "scr", & HW_ENT (HW_H_SCR), 0, 0,
+    { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } }  },
+/* ilm: condition code bits */
+  { "ilm", & HW_ENT (HW_H_ILM), 0, 0,
+    { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } }  },
 };
 
 /* Operand references.  */
@@ -884,7 +892,24 @@ static const CGEN_OPERAND_INSTANCE fmt_ldr15_ops[] = {
 static const CGEN_OPERAND_INSTANCE fmt_ldr15gr_ops[] = {
   { INPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
   { INPUT, "h_memory_reg__VM_h_gr_15", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { INPUT, "f_Ri", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
   { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
+  { OUTPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, COND_REF },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_ldr15dr_ops[] = {
+  { INPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
+  { INPUT, "h_memory_reg__VM_h_gr_15", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "Rs2", & HW_ENT (HW_H_DR), CGEN_MODE_SI, & OP_ENT (RS2), 0, 0 },
+  { OUTPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_ldr15ps_ops[] = {
+  { INPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
+  { INPUT, "h_memory_reg__VM_h_gr_15", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "ps", & HW_ENT (HW_H_PS), CGEN_MODE_USI, 0, 0, 0 },
   { OUTPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
   { 0 }
 };
@@ -896,6 +921,100 @@ static const CGEN_OPERAND_INSTANCE fmt_st_ops[] = {
   { 0 }
 };
 
+static const CGEN_OPERAND_INSTANCE fmt_sth_ops[] = {
+  { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (RJ), 0, 0 },
+  { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
+  { OUTPUT, "h_memory_Rj", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_stb_ops[] = {
+  { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (RJ), 0, 0 },
+  { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
+  { OUTPUT, "h_memory_Rj", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_str13_ops[] = {
+  { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
+  { INPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
+  { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
+  { OUTPUT, "h_memory_add__VM_Rj_reg__VM_h_gr_13", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_str13h_ops[] = {
+  { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
+  { INPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
+  { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
+  { OUTPUT, "h_memory_add__VM_Rj_reg__VM_h_gr_13", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_str13b_ops[] = {
+  { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
+  { INPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
+  { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
+  { OUTPUT, "h_memory_add__VM_Rj_reg__VM_h_gr_13", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_str14_ops[] = {
+  { INPUT, "disp10", & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (DISP10), 0, 0 },
+  { INPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14, 0 },
+  { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
+  { OUTPUT, "h_memory_add__VM_disp10_reg__VM_h_gr_14", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_str14h_ops[] = {
+  { INPUT, "disp9", & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (DISP9), 0, 0 },
+  { INPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14, 0 },
+  { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
+  { OUTPUT, "h_memory_add__VM_disp9_reg__VM_h_gr_14", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_str14b_ops[] = {
+  { INPUT, "disp8", & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (DISP8), 0, 0 },
+  { INPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14, 0 },
+  { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
+  { OUTPUT, "h_memory_add__VM_disp8_reg__VM_h_gr_14", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_str15_ops[] = {
+  { INPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
+  { INPUT, "udisp6", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (UDISP6), 0, 0 },
+  { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
+  { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_15_udisp6", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_str15gr_ops[] = {
+  { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
+  { INPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
+  { OUTPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
+  { OUTPUT, "h_memory_reg__VM_h_gr_15", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_str15dr_ops[] = {
+  { INPUT, "Rs2", & HW_ENT (HW_H_DR), CGEN_MODE_SI, & OP_ENT (RS2), 0, 0 },
+  { INPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
+  { OUTPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
+  { OUTPUT, "h_memory_reg__VM_h_gr_15", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_str15ps_ops[] = {
+  { INPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
+  { INPUT, "ps", & HW_ENT (HW_H_PS), CGEN_MODE_USI, 0, 0, 0 },
+  { OUTPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
+  { OUTPUT, "h_memory_reg__VM_h_gr_15", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { 0 }
+};
+
 static const CGEN_OPERAND_INSTANCE fmt_mov_ops[] = {
   { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
   { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
@@ -908,14 +1027,48 @@ static const CGEN_OPERAND_INSTANCE fmt_movdr_ops[] = {
   { 0 }
 };
 
+static const CGEN_OPERAND_INSTANCE fmt_movps_ops[] = {
+  { INPUT, "ps", & HW_ENT (HW_H_PS), CGEN_MODE_USI, 0, 0, 0 },
+  { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
+  { 0 }
+};
+
 static const CGEN_OPERAND_INSTANCE fmt_mov2dr_ops[] = {
   { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
   { OUTPUT, "Rs1", & HW_ENT (HW_H_DR), CGEN_MODE_SI, & OP_ENT (RS1), 0, 0 },
   { 0 }
 };
 
-static const CGEN_OPERAND_INSTANCE fmt_jmpd_ops[] = {
+static const CGEN_OPERAND_INSTANCE fmt_mov2ps_ops[] = {
   { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
+  { OUTPUT, "ps", & HW_ENT (HW_H_PS), CGEN_MODE_USI, 0, 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_jmp_ops[] = {
+  { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
+  { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_callr_ops[] = {
+  { INPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 },
+  { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
+  { OUTPUT, "h_dr_1", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 1, 0 },
+  { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_call_ops[] = {
+  { INPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 },
+  { INPUT, "label12", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (LABEL12), 0, 0 },
+  { OUTPUT, "h_dr_1", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 1, 0 },
+  { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_ret_ops[] = {
+  { INPUT, "h_dr_1", & HW_ENT (HW_H_DR), CGEN_MODE_SI, 0, 1, 0 },
   { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 },
   { 0 }
 };
@@ -1169,6 +1322,10 @@ static const CGEN_IFMT fmt_ldr15dr = {
   16, 16, 0xfff0, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_RS2), 0 }
 };
 
+static const CGEN_IFMT fmt_ldr15ps = {
+  16, 16, 0xffff, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_OP4), 0 }
+};
+
 static const CGEN_IFMT fmt_st = {
   16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
 };
@@ -1177,6 +1334,22 @@ static const CGEN_IFMT fmt_sth = {
   16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
 };
 
+static const CGEN_IFMT fmt_stb = {
+  16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
+};
+
+static const CGEN_IFMT fmt_str13 = {
+  16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
+};
+
+static const CGEN_IFMT fmt_str13h = {
+  16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
+};
+
+static const CGEN_IFMT fmt_str13b = {
+  16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
+};
+
 static const CGEN_IFMT fmt_str14 = {
   16, 16, 0xf000, { F (F_OP1), F (F_DISP10), F (F_RI), 0 }
 };
@@ -1193,6 +1366,18 @@ static const CGEN_IFMT fmt_str15 = {
   16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_UDISP6), F (F_RI), 0 }
 };
 
+static const CGEN_IFMT fmt_str15gr = {
+  16, 16, 0xfff0, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_RI), 0 }
+};
+
+static const CGEN_IFMT fmt_str15dr = {
+  16, 16, 0xfff0, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_RS2), 0 }
+};
+
+static const CGEN_IFMT fmt_str15ps = {
+  16, 16, 0xffff, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_OP4), 0 }
+};
+
 static const CGEN_IFMT fmt_mov = {
   16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
 };
@@ -1201,11 +1386,23 @@ static const CGEN_IFMT fmt_movdr = {
   16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RS1), F (F_RI), 0 }
 };
 
+static const CGEN_IFMT fmt_movps = {
+  16, 16, 0xfff0, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_RI), 0 }
+};
+
 static const CGEN_IFMT fmt_mov2dr = {
   16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RS1), F (F_RI), 0 }
 };
 
-static const CGEN_IFMT fmt_jmpd = {
+static const CGEN_IFMT fmt_mov2ps = {
+  16, 16, 0xfff0, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_RI), 0 }
+};
+
+static const CGEN_IFMT fmt_jmp = {
+  16, 16, 0xfff0, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_RI), 0 }
+};
+
+static const CGEN_IFMT fmt_callr = {
   16, 16, 0xfff0, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_RI), 0 }
 };
 
@@ -1213,6 +1410,10 @@ static const CGEN_IFMT fmt_call = {
   16, 16, 0xf400, { F (F_OP1), F (F_OP5), F (F_REL12), 0 }
 };
 
+static const CGEN_IFMT fmt_ret = {
+  16, 16, 0xffff, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_OP4), 0 }
+};
+
 static const CGEN_IFMT fmt_int = {
   16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_U8), 0 }
 };
@@ -1305,6 +1506,10 @@ static const CGEN_IFMT fmt_enter = {
   16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_U10), 0 }
 };
 
+static const CGEN_IFMT fmt_xchb = {
+  16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
+};
+
 #undef F
 
 #define A(a) (1 << CONCAT2 (CGEN_INSN_,a))
@@ -1921,7 +2126,7 @@ const CGEN_INSN fr30_cgen_insn_table_entries[MAX_INSNS] =
     FR30_INSN_LDR15DR, "ldr15dr", "ld",
     { { MNEM, ' ', '@', OP (R15), '+', ',', OP (RS2), 0 } },
     & fmt_ldr15dr, { 0x780 },
-    (PTR) 0,
+    (PTR) & fmt_ldr15dr_ops[0],
     { 0, 0, { 0 } }
   },
 /* ld @$R15+,$ps */
@@ -1929,8 +2134,8 @@ const CGEN_INSN fr30_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     FR30_INSN_LDR15PS, "ldr15ps", "ld",
     { { MNEM, ' ', '@', OP (R15), '+', ',', OP (PS), 0 } },
-    & fmt_div3, { 0x790 },
-    (PTR) 0,
+    & fmt_ldr15ps, { 0x790 },
+    (PTR) & fmt_ldr15ps_ops[0],
     { 0, 0, { 0 } }
   },
 /* st $Ri,@$Rj */
@@ -1948,7 +2153,7 @@ const CGEN_INSN fr30_cgen_insn_table_entries[MAX_INSNS] =
     FR30_INSN_STH, "sth", "sth",
     { { MNEM, ' ', OP (RI), ',', '@', OP (RJ), 0 } },
     & fmt_sth, { 0x1500 },
-    (PTR) 0,
+    (PTR) & fmt_sth_ops[0],
     { 0, 0, { 0 } }
   },
 /* stb $Ri,@$Rj */
@@ -1956,8 +2161,8 @@ const CGEN_INSN fr30_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     FR30_INSN_STB, "stb", "stb",
     { { MNEM, ' ', OP (RI), ',', '@', OP (RJ), 0 } },
-    & fmt_sth, { 0x1600 },
-    (PTR) 0,
+    & fmt_stb, { 0x1600 },
+    (PTR) & fmt_stb_ops[0],
     { 0, 0, { 0 } }
   },
 /* st $Ri,@($R13,$Rj) */
@@ -1965,8 +2170,8 @@ const CGEN_INSN fr30_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     FR30_INSN_STR13, "str13", "st",
     { { MNEM, ' ', OP (RI), ',', '@', '(', OP (R13), ',', OP (RJ), ')', 0 } },
-    & fmt_sth, { 0x1000 },
-    (PTR) 0,
+    & fmt_str13, { 0x1000 },
+    (PTR) & fmt_str13_ops[0],
     { 0, 0, { 0 } }
   },
 /* sth $Ri,@($R13,$Rj) */
@@ -1974,44 +2179,44 @@ const CGEN_INSN fr30_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     FR30_INSN_STR13H, "str13h", "sth",
     { { MNEM, ' ', OP (RI), ',', '@', '(', OP (R13), ',', OP (RJ), ')', 0 } },
-    & fmt_sth, { 0x1100 },
-    (PTR) 0,
+    & fmt_str13h, { 0x1100 },
+    (PTR) & fmt_str13h_ops[0],
     { 0, 0, { 0 } }
   },
 /* stb $Ri,@($R13,$Rj) */
   {
     { 1, 1, 1, 1 },
-    FR30_INSN_STR13B, "stR13b", "stb",
+    FR30_INSN_STR13B, "str13b", "stb",
     { { MNEM, ' ', OP (RI), ',', '@', '(', OP (R13), ',', OP (RJ), ')', 0 } },
-    & fmt_sth, { 0x1200 },
-    (PTR) 0,
+    & fmt_str13b, { 0x1200 },
+    (PTR) & fmt_str13b_ops[0],
     { 0, 0, { 0 } }
   },
-/* st $Ri,@($R14,$disp10) */
+/* st Ri,@($R14,$disp10) */
   {
     { 1, 1, 1, 1 },
     FR30_INSN_STR14, "str14", "st",
-    { { MNEM, ' ', OP (RI), ',', '@', '(', OP (R14), ',', OP (DISP10), ')', 0 } },
+    { { MNEM, ' ', 'R', 'i', ',', '@', '(', OP (R14), ',', OP (DISP10), ')', 0 } },
     & fmt_str14, { 0x3000 },
-    (PTR) 0,
+    (PTR) & fmt_str14_ops[0],
     { 0, 0, { 0 } }
   },
-/* sth $Ri,@($R14,$disp9) */
+/* sth Ri,@($R14,$disp9) */
   {
     { 1, 1, 1, 1 },
     FR30_INSN_STR14H, "str14h", "sth",
-    { { MNEM, ' ', OP (RI), ',', '@', '(', OP (R14), ',', OP (DISP9), ')', 0 } },
+    { { MNEM, ' ', 'R', 'i', ',', '@', '(', OP (R14), ',', OP (DISP9), ')', 0 } },
     & fmt_str14h, { 0x5000 },
-    (PTR) 0,
+    (PTR) & fmt_str14h_ops[0],
     { 0, 0, { 0 } }
   },
-/* stb $Ri,@($R14,$disp8) */
+/* stb Ri,@($R14,$disp8) */
   {
     { 1, 1, 1, 1 },
     FR30_INSN_STR14B, "str14b", "stb",
-    { { MNEM, ' ', OP (RI), ',', '@', '(', OP (R14), ',', OP (DISP8), ')', 0 } },
+    { { MNEM, ' ', 'R', 'i', ',', '@', '(', OP (R14), ',', OP (DISP8), ')', 0 } },
     & fmt_str14b, { 0x7000 },
-    (PTR) 0,
+    (PTR) & fmt_str14b_ops[0],
     { 0, 0, { 0 } }
   },
 /* st $Ri,@($R15,$udisp6) */
@@ -2020,7 +2225,7 @@ const CGEN_INSN fr30_cgen_insn_table_entries[MAX_INSNS] =
     FR30_INSN_STR15, "str15", "st",
     { { MNEM, ' ', OP (RI), ',', '@', '(', OP (R15), ',', OP (UDISP6), ')', 0 } },
     & fmt_str15, { 0x1300 },
-    (PTR) 0,
+    (PTR) & fmt_str15_ops[0],
     { 0, 0, { 0 } }
   },
 /* st $Ri,@-$R15 */
@@ -2028,8 +2233,8 @@ const CGEN_INSN fr30_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     FR30_INSN_STR15GR, "str15gr", "st",
     { { MNEM, ' ', OP (RI), ',', '@', '-', OP (R15), 0 } },
-    & fmt_div0s, { 0x1700 },
-    (PTR) 0,
+    & fmt_str15gr, { 0x1700 },
+    (PTR) & fmt_str15gr_ops[0],
     { 0, 0, { 0 } }
   },
 /* st $Rs2,@-$R15 */
@@ -2037,8 +2242,8 @@ const CGEN_INSN fr30_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     FR30_INSN_STR15DR, "str15dr", "st",
     { { MNEM, ' ', OP (RS2), ',', '@', '-', OP (R15), 0 } },
-    & fmt_ldr15dr, { 0x1780 },
-    (PTR) 0,
+    & fmt_str15dr, { 0x1780 },
+    (PTR) & fmt_str15dr_ops[0],
     { 0, 0, { 0 } }
   },
 /* st $ps,@-$R15 */
@@ -2046,8 +2251,8 @@ const CGEN_INSN fr30_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     FR30_INSN_STR15PS, "str15ps", "st",
     { { MNEM, ' ', OP (PS), ',', '@', '-', OP (R15), 0 } },
-    & fmt_div3, { 0x1790 },
-    (PTR) 0,
+    & fmt_str15ps, { 0x1790 },
+    (PTR) & fmt_str15ps_ops[0],
     { 0, 0, { 0 } }
   },
 /* mov $Rj,$Ri */
@@ -2073,8 +2278,8 @@ const CGEN_INSN fr30_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     FR30_INSN_MOVPS, "movps", "mov",
     { { MNEM, ' ', OP (PS), ',', OP (RI), 0 } },
-    & fmt_div0s, { 0x1710 },
-    (PTR) 0,
+    & fmt_movps, { 0x1710 },
+    (PTR) & fmt_movps_ops[0],
     { 0, 0, { 0 } }
   },
 /* mov $Ri,$Rs1 */
@@ -2091,8 +2296,8 @@ const CGEN_INSN fr30_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     FR30_INSN_MOV2PS, "mov2ps", "mov",
     { { MNEM, ' ', OP (RI), ',', OP (PS), 0 } },
-    & fmt_div0s, { 0x710 },
-    (PTR) 0,
+    & fmt_mov2ps, { 0x710 },
+    (PTR) & fmt_mov2ps_ops[0],
     { 0, 0, { 0 } }
   },
 /* jmp @$Ri */
@@ -2100,17 +2305,17 @@ const CGEN_INSN fr30_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     FR30_INSN_JMP, "jmp", "jmp",
     { { MNEM, ' ', '@', OP (RI), 0 } },
-    & fmt_div0s, { 0x9700 },
-    (PTR) 0,
-    { 0, 0, { 0 } }
+    & fmt_jmp, { 0x9700 },
+    (PTR) & fmt_jmp_ops[0],
+    { 0, 0|A(UNCOND_CTI), { 0 } }
   },
 /* jmp:d @$Ri */
   {
     { 1, 1, 1, 1 },
     FR30_INSN_JMPD, "jmpd", "jmp:d",
     { { MNEM, ' ', '@', OP (RI), 0 } },
-    & fmt_jmpd, { 0x9f00 },
-    (PTR) & fmt_jmpd_ops[0],
+    & fmt_jmp, { 0x9f00 },
+    (PTR) & fmt_jmp_ops[0],
     { 0, 0|A(NOT_IN_DELAY_SLOT)|A(DELAY_SLOT)|A(UNCOND_CTI), { 0 } }
   },
 /* call @$Ri */
@@ -2118,18 +2323,18 @@ const CGEN_INSN fr30_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     FR30_INSN_CALLR, "callr", "call",
     { { MNEM, ' ', '@', OP (RI), 0 } },
-    & fmt_div0s, { 0x9710 },
-    (PTR) 0,
-    { 0, 0, { 0 } }
+    & fmt_callr, { 0x9710 },
+    (PTR) & fmt_callr_ops[0],
+    { 0, 0|A(UNCOND_CTI), { 0 } }
   },
-/* call:D @$Ri */
+/* call:d @$Ri */
   {
     { 1, 1, 1, 1 },
-    FR30_INSN_CALLRD, "callrd", "call:D",
+    FR30_INSN_CALLRD, "callrd", "call:d",
     { { MNEM, ' ', '@', OP (RI), 0 } },
-    & fmt_div0s, { 0x9f10 },
-    (PTR) 0,
-    { 0, 0, { 0 } }
+    & fmt_callr, { 0x9f10 },
+    (PTR) & fmt_callr_ops[0],
+    { 0, 0|A(DELAY_SLOT)|A(UNCOND_CTI), { 0 } }
   },
 /* call $label12 */
   {
@@ -2137,35 +2342,35 @@ const CGEN_INSN fr30_cgen_insn_table_entries[MAX_INSNS] =
     FR30_INSN_CALL, "call", "call",
     { { MNEM, ' ', OP (LABEL12), 0 } },
     & fmt_call, { 0xd000 },
-    (PTR) 0,
-    { 0, 0, { 0 } }
+    (PTR) & fmt_call_ops[0],
+    { 0, 0|A(UNCOND_CTI), { 0 } }
   },
-/* call:D $label12 */
+/* call:d $label12 */
   {
     { 1, 1, 1, 1 },
-    FR30_INSN_CALLD, "calld", "call:D",
+    FR30_INSN_CALLD, "calld", "call:d",
     { { MNEM, ' ', OP (LABEL12), 0 } },
     & fmt_call, { 0xd400 },
-    (PTR) 0,
-    { 0, 0, { 0 } }
+    (PTR) & fmt_call_ops[0],
+    { 0, 0|A(DELAY_SLOT)|A(UNCOND_CTI), { 0 } }
   },
 /* ret */
   {
     { 1, 1, 1, 1 },
     FR30_INSN_RET, "ret", "ret",
     { { MNEM, 0 } },
-    & fmt_div3, { 0x9720 },
-    (PTR) 0,
-    { 0, 0, { 0 } }
+    & fmt_ret, { 0x9720 },
+    (PTR) & fmt_ret_ops[0],
+    { 0, 0|A(UNCOND_CTI), { 0 } }
   },
-/* ret:D */
+/* ret:d */
   {
     { 1, 1, 1, 1 },
-    FR30_INSN_RETD, "retd", "ret:D",
+    FR30_INSN_RET_D, "ret:d", "ret:d",
     { { MNEM, 0 } },
-    & fmt_div3, { 0x9f20 },
-    (PTR) 0,
-    { 0, 0, { 0 } }
+    & fmt_ret, { 0x9f20 },
+    (PTR) & fmt_ret_ops[0],
+    { 0, 0|A(DELAY_SLOT)|A(UNCOND_CTI), { 0 } }
   },
 /* int $u8 */
   {
@@ -2203,10 +2408,10 @@ const CGEN_INSN fr30_cgen_insn_table_entries[MAX_INSNS] =
     (PTR) & fmt_bra_ops[0],
     { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
   },
-/* bra:D $label9 */
+/* bra:d $label9 */
   {
     { 1, 1, 1, 1 },
-    FR30_INSN_BRAD, "brad", "bra:D",
+    FR30_INSN_BRAD, "brad", "bra:d",
     { { MNEM, ' ', OP (LABEL9), 0 } },
     & fmt_bra, { 0xf000 },
     (PTR) & fmt_bra_ops[0],
@@ -2221,10 +2426,10 @@ const CGEN_INSN fr30_cgen_insn_table_entries[MAX_INSNS] =
     (PTR) & fmt_bra_ops[0],
     { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
   },
-/* bno:D $label9 */
+/* bno:d $label9 */
   {
     { 1, 1, 1, 1 },
-    FR30_INSN_BNOD, "bnod", "bno:D",
+    FR30_INSN_BNOD, "bnod", "bno:d",
     { { MNEM, ' ', OP (LABEL9), 0 } },
     & fmt_bra, { 0xf100 },
     (PTR) & fmt_bra_ops[0],
@@ -2239,10 +2444,10 @@ const CGEN_INSN fr30_cgen_insn_table_entries[MAX_INSNS] =
     (PTR) & fmt_beq_ops[0],
     { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
   },
-/* beq:D $label9 */
+/* beq:d $label9 */
   {
     { 1, 1, 1, 1 },
-    FR30_INSN_BEQD, "beqd", "beq:D",
+    FR30_INSN_BEQD, "beqd", "beq:d",
     { { MNEM, ' ', OP (LABEL9), 0 } },
     & fmt_beq, { 0xf200 },
     (PTR) & fmt_beq_ops[0],
@@ -2257,10 +2462,10 @@ const CGEN_INSN fr30_cgen_insn_table_entries[MAX_INSNS] =
     (PTR) & fmt_beq_ops[0],
     { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
   },
-/* bne:D $label9 */
+/* bne:d $label9 */
   {
     { 1, 1, 1, 1 },
-    FR30_INSN_BNED, "bned", "bne:D",
+    FR30_INSN_BNED, "bned", "bne:d",
     { { MNEM, ' ', OP (LABEL9), 0 } },
     & fmt_beq, { 0xf300 },
     (PTR) & fmt_beq_ops[0],
@@ -2275,10 +2480,10 @@ const CGEN_INSN fr30_cgen_insn_table_entries[MAX_INSNS] =
     (PTR) & fmt_bc_ops[0],
     { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
   },
-/* bc:D $label9 */
+/* bc:d $label9 */
   {
     { 1, 1, 1, 1 },
-    FR30_INSN_BCD, "bcd", "bc:D",
+    FR30_INSN_BCD, "bcd", "bc:d",
     { { MNEM, ' ', OP (LABEL9), 0 } },
     & fmt_bc, { 0xf400 },
     (PTR) & fmt_bc_ops[0],
@@ -2293,10 +2498,10 @@ const CGEN_INSN fr30_cgen_insn_table_entries[MAX_INSNS] =
     (PTR) & fmt_bc_ops[0],
     { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
   },
-/* bnc:D $label9 */
+/* bnc:d $label9 */
   {
     { 1, 1, 1, 1 },
-    FR30_INSN_BNCD, "bncd", "bnc:D",
+    FR30_INSN_BNCD, "bncd", "bnc:d",
     { { MNEM, ' ', OP (LABEL9), 0 } },
     & fmt_bc, { 0xf500 },
     (PTR) & fmt_bc_ops[0],
@@ -2311,10 +2516,10 @@ const CGEN_INSN fr30_cgen_insn_table_entries[MAX_INSNS] =
     (PTR) & fmt_bn_ops[0],
     { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
   },
-/* bn:D $label9 */
+/* bn:d $label9 */
   {
     { 1, 1, 1, 1 },
-    FR30_INSN_BND, "bnd", "bn:D",
+    FR30_INSN_BND, "bnd", "bn:d",
     { { MNEM, ' ', OP (LABEL9), 0 } },
     & fmt_bn, { 0xf600 },
     (PTR) & fmt_bn_ops[0],
@@ -2329,10 +2534,10 @@ const CGEN_INSN fr30_cgen_insn_table_entries[MAX_INSNS] =
     (PTR) & fmt_bn_ops[0],
     { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
   },
-/* bp:D $label9 */
+/* bp:d $label9 */
   {
     { 1, 1, 1, 1 },
-    FR30_INSN_BPD, "bpd", "bp:D",
+    FR30_INSN_BPD, "bpd", "bp:d",
     { { MNEM, ' ', OP (LABEL9), 0 } },
     & fmt_bn, { 0xf700 },
     (PTR) & fmt_bn_ops[0],
@@ -2347,10 +2552,10 @@ const CGEN_INSN fr30_cgen_insn_table_entries[MAX_INSNS] =
     (PTR) & fmt_bv_ops[0],
     { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
   },
-/* bv:D $label9 */
+/* bv:d $label9 */
   {
     { 1, 1, 1, 1 },
-    FR30_INSN_BVD, "bvd", "bv:D",
+    FR30_INSN_BVD, "bvd", "bv:d",
     { { MNEM, ' ', OP (LABEL9), 0 } },
     & fmt_bv, { 0xf800 },
     (PTR) & fmt_bv_ops[0],
@@ -2365,10 +2570,10 @@ const CGEN_INSN fr30_cgen_insn_table_entries[MAX_INSNS] =
     (PTR) & fmt_bv_ops[0],
     { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
   },
-/* bnv:D $label9 */
+/* bnv:d $label9 */
   {
     { 1, 1, 1, 1 },
-    FR30_INSN_BNVD, "bnvd", "bnv:D",
+    FR30_INSN_BNVD, "bnvd", "bnv:d",
     { { MNEM, ' ', OP (LABEL9), 0 } },
     & fmt_bv, { 0xf900 },
     (PTR) & fmt_bv_ops[0],
@@ -2383,10 +2588,10 @@ const CGEN_INSN fr30_cgen_insn_table_entries[MAX_INSNS] =
     (PTR) & fmt_blt_ops[0],
     { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
   },
-/* blt:D $label9 */
+/* blt:d $label9 */
   {
     { 1, 1, 1, 1 },
-    FR30_INSN_BLTD, "bltd", "blt:D",
+    FR30_INSN_BLTD, "bltd", "blt:d",
     { { MNEM, ' ', OP (LABEL9), 0 } },
     & fmt_blt, { 0xfa00 },
     (PTR) & fmt_blt_ops[0],
@@ -2401,10 +2606,10 @@ const CGEN_INSN fr30_cgen_insn_table_entries[MAX_INSNS] =
     (PTR) & fmt_blt_ops[0],
     { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
   },
-/* bge:D $label9 */
+/* bge:d $label9 */
   {
     { 1, 1, 1, 1 },
-    FR30_INSN_BGED, "bged", "bge:D",
+    FR30_INSN_BGED, "bged", "bge:d",
     { { MNEM, ' ', OP (LABEL9), 0 } },
     & fmt_blt, { 0xfb00 },
     (PTR) & fmt_blt_ops[0],
@@ -2419,10 +2624,10 @@ const CGEN_INSN fr30_cgen_insn_table_entries[MAX_INSNS] =
     (PTR) & fmt_ble_ops[0],
     { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
   },
-/* ble:D $label9 */
+/* ble:d $label9 */
   {
     { 1, 1, 1, 1 },
-    FR30_INSN_BLED, "bled", "ble:D",
+    FR30_INSN_BLED, "bled", "ble:d",
     { { MNEM, ' ', OP (LABEL9), 0 } },
     & fmt_ble, { 0xfc00 },
     (PTR) & fmt_ble_ops[0],
@@ -2437,10 +2642,10 @@ const CGEN_INSN fr30_cgen_insn_table_entries[MAX_INSNS] =
     (PTR) & fmt_ble_ops[0],
     { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
   },
-/* bgt:D $label9 */
+/* bgt:d $label9 */
   {
     { 1, 1, 1, 1 },
-    FR30_INSN_BGTD, "bgtd", "bgt:D",
+    FR30_INSN_BGTD, "bgtd", "bgt:d",
     { { MNEM, ' ', OP (LABEL9), 0 } },
     & fmt_ble, { 0xfd00 },
     (PTR) & fmt_ble_ops[0],
@@ -2455,10 +2660,10 @@ const CGEN_INSN fr30_cgen_insn_table_entries[MAX_INSNS] =
     (PTR) & fmt_bls_ops[0],
     { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
   },
-/* bls:D $label9 */
+/* bls:d $label9 */
   {
     { 1, 1, 1, 1 },
-    FR30_INSN_BLSD, "blsd", "bls:D",
+    FR30_INSN_BLSD, "blsd", "bls:d",
     { { MNEM, ' ', OP (LABEL9), 0 } },
     & fmt_bls, { 0xfe00 },
     (PTR) & fmt_bls_ops[0],
@@ -2473,10 +2678,10 @@ const CGEN_INSN fr30_cgen_insn_table_entries[MAX_INSNS] =
     (PTR) & fmt_bls_ops[0],
     { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
   },
-/* bhi:D $label9 */
+/* bhi:d $label9 */
   {
     { 1, 1, 1, 1 },
-    FR30_INSN_BHID, "bhid", "bhi:D",
+    FR30_INSN_BHID, "bhid", "bhi:d",
     { { MNEM, ' ', OP (LABEL9), 0 } },
     & fmt_bls, { 0xff00 },
     (PTR) & fmt_bls_ops[0],
@@ -2802,7 +3007,7 @@ const CGEN_INSN fr30_cgen_insn_table_entries[MAX_INSNS] =
     { 1, 1, 1, 1 },
     FR30_INSN_XCHB, "xchb", "xchb",
     { { MNEM, ' ', '@', OP (RJ), ',', OP (RI), 0 } },
-    & fmt_sth, { 0x8a00 },
+    & fmt_xchb, { 0x8a00 },
     (PTR) 0,
     { 0, 0, { 0 } }
   },
@@ -3084,9 +3289,6 @@ fr30_cgen_get_int_operand (opindex, fields)
     case FR30_OPERAND_I20 :
       value = fields->f_i20;
       break;
-    case FR30_OPERAND_LABEL9 :
-      value = fields->f_rel9;
-      break;
     case FR30_OPERAND_DIR8 :
       value = fields->f_dir8;
       break;
@@ -3096,6 +3298,9 @@ fr30_cgen_get_int_operand (opindex, fields)
     case FR30_OPERAND_DIR10 :
       value = fields->f_dir10;
       break;
+    case FR30_OPERAND_LABEL9 :
+      value = fields->f_rel9;
+      break;
     case FR30_OPERAND_LABEL12 :
       value = fields->f_rel12;
       break;
@@ -3206,9 +3411,6 @@ fr30_cgen_get_vma_operand (opindex, fields)
     case FR30_OPERAND_I20 :
       value = fields->f_i20;
       break;
-    case FR30_OPERAND_LABEL9 :
-      value = fields->f_rel9;
-      break;
     case FR30_OPERAND_DIR8 :
       value = fields->f_dir8;
       break;
@@ -3218,6 +3420,9 @@ fr30_cgen_get_vma_operand (opindex, fields)
     case FR30_OPERAND_DIR10 :
       value = fields->f_dir10;
       break;
+    case FR30_OPERAND_LABEL9 :
+      value = fields->f_rel9;
+      break;
     case FR30_OPERAND_LABEL12 :
       value = fields->f_rel12;
       break;
@@ -3332,9 +3537,6 @@ fr30_cgen_set_int_operand (opindex, fields, value)
     case FR30_OPERAND_I20 :
       fields->f_i20 = value;
       break;
-    case FR30_OPERAND_LABEL9 :
-      fields->f_rel9 = value;
-      break;
     case FR30_OPERAND_DIR8 :
       fields->f_dir8 = value;
       break;
@@ -3344,6 +3546,9 @@ fr30_cgen_set_int_operand (opindex, fields, value)
     case FR30_OPERAND_DIR10 :
       fields->f_dir10 = value;
       break;
+    case FR30_OPERAND_LABEL9 :
+      fields->f_rel9 = value;
+      break;
     case FR30_OPERAND_LABEL12 :
       fields->f_rel12 = value;
       break;
@@ -3451,9 +3656,6 @@ fr30_cgen_set_vma_operand (opindex, fields, value)
     case FR30_OPERAND_I20 :
       fields->f_i20 = value;
       break;
-    case FR30_OPERAND_LABEL9 :
-      fields->f_rel9 = value;
-      break;
     case FR30_OPERAND_DIR8 :
       fields->f_dir8 = value;
       break;
@@ -3463,6 +3665,9 @@ fr30_cgen_set_vma_operand (opindex, fields, value)
     case FR30_OPERAND_DIR10 :
       fields->f_dir10 = value;
       break;
+    case FR30_OPERAND_LABEL9 :
+      fields->f_rel9 = value;
+      break;
     case FR30_OPERAND_LABEL12 :
       fields->f_rel12 = value;
       break;
diff --git a/opcodes/fr30-opc.h b/opcodes/fr30-opc.h
index ae0342778b..bfd2a6238d 100644
--- a/opcodes/fr30-opc.h
+++ b/opcodes/fr30-opc.h
@@ -152,11 +152,12 @@ typedef enum cgen_operand_type {
  , FR30_OPERAND_PS, FR30_OPERAND_U4, FR30_OPERAND_U4C, FR30_OPERAND_U8
  , FR30_OPERAND_I8, FR30_OPERAND_UDISP6, FR30_OPERAND_DISP8, FR30_OPERAND_DISP9
  , FR30_OPERAND_DISP10, FR30_OPERAND_S10, FR30_OPERAND_U10, FR30_OPERAND_I32
- , FR30_OPERAND_M4, FR30_OPERAND_I20, FR30_OPERAND_LABEL9, FR30_OPERAND_DIR8
- , FR30_OPERAND_DIR9, FR30_OPERAND_DIR10, FR30_OPERAND_LABEL12, FR30_OPERAND_REGLIST_LOW
+ , FR30_OPERAND_M4, FR30_OPERAND_I20, FR30_OPERAND_DIR8, FR30_OPERAND_DIR9
+ , FR30_OPERAND_DIR10, FR30_OPERAND_LABEL9, FR30_OPERAND_LABEL12, FR30_OPERAND_REGLIST_LOW
  , FR30_OPERAND_REGLIST_HI, FR30_OPERAND_CC, FR30_OPERAND_CCC, FR30_OPERAND_NBIT
  , FR30_OPERAND_VBIT, FR30_OPERAND_ZBIT, FR30_OPERAND_CBIT, FR30_OPERAND_IBIT
- , FR30_OPERAND_SBIT, FR30_OPERAND_CCR, FR30_OPERAND_MAX
+ , FR30_OPERAND_SBIT, FR30_OPERAND_CCR, FR30_OPERAND_SCR, FR30_OPERAND_ILM
+ , FR30_OPERAND_MAX
 } CGEN_OPERAND_TYPE;
 
 /* Non-boolean attributes.  */
@@ -257,7 +258,7 @@ typedef enum cgen_insn_type {
  , FR30_INSN_STR15DR, FR30_INSN_STR15PS, FR30_INSN_MOV, FR30_INSN_MOVDR
  , FR30_INSN_MOVPS, FR30_INSN_MOV2DR, FR30_INSN_MOV2PS, FR30_INSN_JMP
  , FR30_INSN_JMPD, FR30_INSN_CALLR, FR30_INSN_CALLRD, FR30_INSN_CALL
- , FR30_INSN_CALLD, FR30_INSN_RET, FR30_INSN_RETD, FR30_INSN_INT
+ , FR30_INSN_CALLD, FR30_INSN_RET, FR30_INSN_RET_D, FR30_INSN_INT
  , FR30_INSN_INTE, FR30_INSN_RETI, FR30_INSN_BRA, FR30_INSN_BRAD
  , FR30_INSN_BNO, FR30_INSN_BNOD, FR30_INSN_BEQ, FR30_INSN_BEQD
  , FR30_INSN_BNE, FR30_INSN_BNED, FR30_INSN_BC, FR30_INSN_BCD
@@ -343,7 +344,7 @@ typedef enum hw_type {
  , HW_H_DR, HW_H_PS, HW_H_R13, HW_H_R14
  , HW_H_R15, HW_H_NBIT, HW_H_ZBIT, HW_H_VBIT
  , HW_H_CBIT, HW_H_IBIT, HW_H_SBIT, HW_H_CCR
- , HW_MAX
+ , HW_H_SCR, HW_H_ILM, HW_MAX
 } HW_TYPE;
 
 #define MAX_HW ((int) HW_MAX)
-- 
2.34.1