From b5639b37c53e7a0d54b6c321b1b363075fa7cb01 Mon Sep 17 00:00:00 2001 From: Martin Schwidefsky Date: Tue, 6 Mar 2007 13:19:08 +0000 Subject: [PATCH] 2007-03-06 Andreas Krebbel * opcodes/s390-opc.c (INSTR_RRE_FR, INSTR_RRF_F0FF2, INSTR_RRF_F0FR, INSTR_RRF_UUFF, INSTR_RRF_0UFF, INSTR_RRF_FFFU, INSTR_RRR_F0FF): New instruction formats added. (MASK_RRE_FR, MASK_RRF_F0FF2, MASK_RRF_F0FR, MASK_RRF_UUFF, MASK_RRF_0UFF, MASK_RRF_FFFU, MASK_RRR_F0FF): New instruction format masks added. * opcodes/s390-opc.txt (lpdfr - tgxt): Decimal floating point instructions added. * opcodes/s390-mkopc.c (s390_opcode_cpu_val): S390_OPCODE_Z9_EC added. (main): z9-ec cpu type option added. * include/opcode/s390.h (s390_opcode_cpu_val): S390_OPCODE_Z9_EC added. 2007-03-06 Andreas Krebbel * config/tc-s390.c (md_parse_option): z9-ec option added. 2007-03-06 Andreas Krebbel * gas/s390/zarch-z9-ec.d: New file. * gas/s390/zarch-z9-ec.s: New file. * gas/s390/s390.exp: Run the z9-ec testcases. --- gas/ChangeLog | 4 ++ gas/config/tc-s390.c | 2 + gas/testsuite/ChangeLog | 6 +++ gas/testsuite/gas/s390/s390.exp | 1 + gas/testsuite/gas/s390/zarch-z9-ec.d | 71 ++++++++++++++++++++++++++++ gas/testsuite/gas/s390/zarch-z9-ec.s | 65 +++++++++++++++++++++++++ include/opcode/s390.h | 3 +- opcodes/ChangeLog | 14 ++++++ opcodes/s390-mkopc.c | 5 +- opcodes/s390-opc.c | 14 ++++++ opcodes/s390-opc.txt | 63 ++++++++++++++++++++++++ 11 files changed, 246 insertions(+), 2 deletions(-) create mode 100644 gas/testsuite/gas/s390/zarch-z9-ec.d create mode 100644 gas/testsuite/gas/s390/zarch-z9-ec.s diff --git a/gas/ChangeLog b/gas/ChangeLog index 289d1ce790..dde64e6514 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,7 @@ +2007-03-06 Andreas Krebbel + + * config/tc-s390.c (md_parse_option): z9-ec option added. + 2007-03-02 Paul Brook * config/tc-arm.c (relax_immediate): Always return positive values. diff --git a/gas/config/tc-s390.c b/gas/config/tc-s390.c index 463cde7a07..6ca31f7b43 100644 --- a/gas/config/tc-s390.c +++ b/gas/config/tc-s390.c @@ -411,6 +411,8 @@ md_parse_option (c, arg) current_cpu = S390_OPCODE_Z990; else if (strcmp (arg + 5, "z9-109") == 0) current_cpu = S390_OPCODE_Z9_109; + else if (strcmp (arg + 5, "z9-ec") == 0) + current_cpu = S390_OPCODE_Z9_EC; else { as_bad (_("invalid switch -m%s"), arg); diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog index 57ac6ecd99..4e483b115c 100644 --- a/gas/testsuite/ChangeLog +++ b/gas/testsuite/ChangeLog @@ -1,3 +1,9 @@ +2007-03-06 Andreas Krebbel + + * gas/s390/zarch-z9-ec.d: New file. + * gas/s390/zarch-z9-ec.s: New file. + * gas/s390/s390.exp: Run the z9-ec testcases. + 2007-03-05 H.J. Lu PR gas/3918 diff --git a/gas/testsuite/gas/s390/s390.exp b/gas/testsuite/gas/s390/s390.exp index 3d9a4a135c..db49134775 100644 --- a/gas/testsuite/gas/s390/s390.exp +++ b/gas/testsuite/gas/s390/s390.exp @@ -32,6 +32,7 @@ if [expr [istarget "s390-*-*"] || [istarget "s390x-*-*"]] then { run_dump_test "zarch-z900" "{as -m64}" run_dump_test "zarch-z990" "{as -m64} {as -march=z990}" run_dump_test "zarch-z9-109" "{as -m64} {as -march=z9-109}" + run_dump_test "zarch-z9-ec" "{as -m64} {as -march=z9-ec}" run_dump_test "zarch-reloc" "{as -m64}" run_dump_test "zarch-operands" "{as -m64} {as -march=z9-109}" } diff --git a/gas/testsuite/gas/s390/zarch-z9-ec.d b/gas/testsuite/gas/s390/zarch-z9-ec.d new file mode 100644 index 0000000000..f2bb0bfd00 --- /dev/null +++ b/gas/testsuite/gas/s390/zarch-z9-ec.d @@ -0,0 +1,71 @@ +#name: s390x opcode +#objdump: -drw + +.*: +file format .* + +Disassembly of section .text: + +.* : +.*: b3 70 00 62 [ ]*lpdfr %f6,%f2 +.*: b3 71 00 62 [ ]*lndfr %f6,%f2 +.*: b3 72 10 62 [ ]*cpsdr %f6,%f1,%f2 +.*: b3 73 00 62 [ ]*lcdfr %f6,%f2 +.*: b3 c1 00 62 [ ]*ldgr %f6,%r2 +.*: b3 cd 00 26 [ ]*lgdr %r2,%f6 +.*: b3 d2 40 62 [ ]*adtr %f6,%f2,%f4 +.*: b3 da 40 62 [ ]*axtr %f6,%f2,%f4 +.*: b3 e4 00 62 [ ]*cdtr %f6,%f2 +.*: b3 ec 00 62 [ ]*cxtr %f6,%f2 +.*: b3 e0 00 62 [ ]*kdtr %f6,%f2 +.*: b3 e8 00 62 [ ]*kxtr %f6,%f2 +.*: b3 f4 00 62 [ ]*cedtr %f6,%f2 +.*: b3 fc 00 62 [ ]*cextr %f6,%f2 +.*: b3 f1 00 62 [ ]*cdgtr %f6,%r2 +.*: b3 f9 00 62 [ ]*cxgtr %f6,%r2 +.*: b3 f3 00 62 [ ]*cdstr %f6,%r2 +.*: b3 fb 00 62 [ ]*cxstr %f6,%r2 +.*: b3 f2 00 62 [ ]*cdutr %f6,%r2 +.*: b3 fa 00 62 [ ]*cxutr %f6,%r2 +.*: b3 e1 10 26 [ ]*cgdtr %r2,1,%f6 +.*: b3 e9 10 26 [ ]*cgxtr %r2,1,%f6 +.*: b3 e3 00 26 [ ]*csdtr %r2,%f6 +.*: b3 eb 00 26 [ ]*csxtr %r2,%f6 +.*: b3 e2 00 26 [ ]*cudtr %r2,%f6 +.*: b3 ea 00 26 [ ]*cuxtr %r2,%f6 +.*: b3 d1 40 62 [ ]*ddtr %f6,%f2,%f4 +.*: b3 d9 40 62 [ ]*dxtr %f6,%f2,%f4 +.*: b3 e5 00 26 [ ]*eedtr %r2,%f6 +.*: b3 ed 00 26 [ ]*eextr %r2,%f6 +.*: b3 e7 00 26 [ ]*esdtr %r2,%f6 +.*: b3 ef 00 26 [ ]*esxtr %r2,%f6 +.*: b3 f6 20 64 [ ]*iedtr %f6,%f2,%r4 +.*: b3 fe 20 64 [ ]*iextr %f6,%f2,%r4 +.*: b3 d6 00 62 [ ]*ltdtr %f6,%f2 +.*: b3 de 00 62 [ ]*ltxtr %f6,%f2 +.*: b3 d7 13 62 [ ]*fidtr %f6,1,%f2,3 +.*: b3 df 13 62 [ ]*fixtr %f6,1,%f2,3 +.*: b2 bd 10 03 [ ]*lfas 3\(%r1\) +.*: b3 d4 01 62 [ ]*ldetr %f6,%f2,1 +.*: b3 dc 01 62 [ ]*lxdtr %f6,%f2,1 +.*: b3 d5 13 62 [ ]*ledtr %f6,1,%f2,3 +.*: b3 dd 13 62 [ ]*ldxtr %f6,1,%f2,3 +.*: b3 d0 40 62 [ ]*mdtr %f6,%f2,%f4 +.*: b3 d8 40 62 [ ]*mxtr %f6,%f2,%f4 +.*: b3 f5 21 64 [ ]*qadtr %f6,%f2,%f4,1 +.*: b3 fd 21 64 [ ]*qaxtr %f6,%f2,%f4,1 +.*: b3 f7 21 64 [ ]*rrdtr %f6,%f2,%f4,1 +.*: b3 ff 21 64 [ ]*rrxtr %f6,%f2,%f4,1 +.*: b2 b9 10 03 [ ]*srnmt 3\(%r1\) +.*: b3 85 00 20 [ ]*sfasr %r2 +.*: ed 21 40 03 60 40 [ ]*sldt %f6,%f2,3\(%r1,%r4\) +.*: ed 21 40 03 60 48 [ ]*slxt %f6,%f2,3\(%r1,%r4\) +.*: ed 21 40 03 60 41 [ ]*srdt %f6,%f2,3\(%r1,%r4\) +.*: ed 21 40 03 60 49 [ ]*srxt %f6,%f2,3\(%r1,%r4\) +.*: b3 d3 40 62 [ ]*sdtr %f6,%f2,%f4 +.*: b3 db 40 62 [ ]*sxtr %f6,%f2,%f4 +.*: ed 61 20 03 00 50 [ ]*tcet %f6,3\(%r1,%r2\) +.*: ed 61 20 03 00 54 [ ]*tcdt %f6,3\(%r1,%r2\) +.*: ed 61 20 03 00 58 [ ]*tcxt %f6,3\(%r1,%r2\) +.*: ed 61 20 03 00 51 [ ]*tget %f6,3\(%r1,%r2\) +.*: ed 61 20 03 00 55 [ ]*tgdt %f6,3\(%r1,%r2\) +.*: ed 61 20 03 00 59 [ ]*tgxt %f6,3\(%r1,%r2\) diff --git a/gas/testsuite/gas/s390/zarch-z9-ec.s b/gas/testsuite/gas/s390/zarch-z9-ec.s new file mode 100644 index 0000000000..15435117e5 --- /dev/null +++ b/gas/testsuite/gas/s390/zarch-z9-ec.s @@ -0,0 +1,65 @@ +.text +foo: + lpdfr %f6,%f2 + lndfr %f6,%f2 + cpsdr %f6,%f1,%f2 + lcdfr %f6,%f2 + ldgr %f6,%r2 + lgdr %r2,%f6 + adtr %f6,%f2,%f4 + axtr %f6,%f2,%f4 + cdtr %f6,%f2 + cxtr %f6,%f2 + kdtr %f6,%f2 + kxtr %f6,%f2 + cedtr %f6,%f2 + cextr %f6,%f2 + cdgtr %f6,%r2 + cxgtr %f6,%r2 + cdstr %f6,%r2 + cxstr %f6,%r2 + cdutr %f6,%r2 + cxutr %f6,%r2 + cgdtr %r2,1,%f6 + cgxtr %r2,1,%f6 + csdtr %r2,%f6 + csxtr %r2,%f6 + cudtr %r2,%f6 + cuxtr %r2,%f6 + ddtr %f6,%f2,%f4 + dxtr %f6,%f2,%f4 + eedtr %r2,%f6 + eextr %r2,%f6 + esdtr %r2,%f6 + esxtr %r2,%f6 + iedtr %f6,%f2,%r4 + iextr %f6,%f2,%r4 + ltdtr %f6,%f2 + ltxtr %f6,%f2 + fidtr %f6,1,%f2,3 + fixtr %f6,1,%f2,3 + lfas 3(%r1) + ldetr %f6,%f2,1 + lxdtr %f6,%f2,1 + ledtr %f6,1,%f2,3 + ldxtr %f6,1,%f2,3 + mdtr %f6,%f2,%f4 + mxtr %f6,%f2,%f4 + qadtr %f6,%f2,%f4,1 + qaxtr %f6,%f2,%f4,1 + rrdtr %f6,%f2,%f4,1 + rrxtr %f6,%f2,%f4,1 + srnmt 3(%r1) + sfasr %r2 + sldt %f6,%f2,3(%r1,%r4) + slxt %f6,%f2,3(%r1,%r4) + srdt %f6,%f2,3(%r1,%r4) + srxt %f6,%f2,3(%r1,%r4) + sdtr %f6,%f2,%f4 + sxtr %f6,%f2,%f4 + tcet %f6,3(%r1,%r2) + tcdt %f6,3(%r1,%r2) + tcxt %f6,3(%r1,%r2) + tget %f6,3(%r1,%r2) + tgdt %f6,3(%r1,%r2) + tgxt %f6,3(%r1,%r2) diff --git a/include/opcode/s390.h b/include/opcode/s390.h index 7bb30de285..ae039efe0f 100644 --- a/include/opcode/s390.h +++ b/include/opcode/s390.h @@ -36,7 +36,8 @@ enum s390_opcode_cpu_val S390_OPCODE_G6, S390_OPCODE_Z900, S390_OPCODE_Z990, - S390_OPCODE_Z9_109 + S390_OPCODE_Z9_109, + S390_OPCODE_Z9_EC }; /* The opcode table is an array of struct s390_opcode. */ diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index a1be1e631c..0a66f5a2cc 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,17 @@ +2007-03-06 Andreas Krebbel + + * opcodes/s390-opc.c (INSTR_RRE_FR, INSTR_RRF_F0FF2, INSTR_RRF_F0FR, + INSTR_RRF_UUFF, INSTR_RRF_0UFF, INSTR_RRF_FFFU, INSTR_RRR_F0FF): New + instruction formats added. + (MASK_RRE_FR, MASK_RRF_F0FF2, MASK_RRF_F0FR, MASK_RRF_UUFF, + MASK_RRF_0UFF, MASK_RRF_FFFU, MASK_RRR_F0FF): New instruction format + masks added. + * opcodes/s390-opc.txt (lpdfr - tgxt): Decimal floating point + instructions added. + * opcodes/s390-mkopc.c (s390_opcode_cpu_val): S390_OPCODE_Z9_EC added. + (main): z9-ec cpu type option added. + * include/opcode/s390.h (s390_opcode_cpu_val): S390_OPCODE_Z9_EC added. + 2007-02-22 DJ Delorie * s390-opc.c (INSTR_SS_L2RDRD): New. diff --git a/opcodes/s390-mkopc.c b/opcodes/s390-mkopc.c index 5a794fdd5d..9e94f24871 100644 --- a/opcodes/s390-mkopc.c +++ b/opcodes/s390-mkopc.c @@ -36,7 +36,8 @@ enum s390_opcode_cpu_val S390_OPCODE_G6, S390_OPCODE_Z900, S390_OPCODE_Z990, - S390_OPCODE_Z9_109 + S390_OPCODE_Z9_109, + S390_OPCODE_Z9_EC }; struct op_struct @@ -198,6 +199,8 @@ main (void) min_cpu = S390_OPCODE_Z990; else if (strcmp (cpu_string, "z9-109") == 0) min_cpu = S390_OPCODE_Z9_109; + else if (strcmp (cpu_string, "z9-ec") == 0) + min_cpu = S390_OPCODE_Z9_EC; else { fprintf (stderr, "Couldn't parse cpu string %s\n", cpu_string); exit (1); diff --git a/opcodes/s390-opc.c b/opcodes/s390-opc.c index d5913c0fe2..8b0b72f222 100644 --- a/opcodes/s390-opc.c +++ b/opcodes/s390-opc.c @@ -205,15 +205,21 @@ const struct s390_operand s390_operands[] = #define INSTR_RRE_RA 4, { R_24,A_28,0,0,0,0 } /* e.g. ear */ #define INSTR_RRE_RF 4, { R_24,F_28,0,0,0,0 } /* e.g. cefbr */ #define INSTR_RRE_RR 4, { R_24,R_28,0,0,0,0 } /* e.g. lura */ +#define INSTR_RRE_FR 4, { F_24,R_28,0,0,0,0 } /* e.g. ldgr */ /* Actually efpc and sfpc do not take an optional operand. This is just a workaround for existing code e.g. glibc. */ #define INSTR_RRE_RR_OPT 4, { R_24,RO_28,0,0,0,0 } /* efpc, sfpc */ #define INSTR_RRF_F0FF 4, { F_16,F_24,F_28,0,0,0 } /* e.g. madbr */ +#define INSTR_RRF_F0FF2 4, { F_24,F_16,F_28,0,0,0 } /* e.g. cpsdr */ +#define INSTR_RRF_F0FR 4, { F_24,F_16,R_28,0,0,0 } /* e.g. iedtr */ #define INSTR_RRF_FUFF 4, { F_24,F_16,F_28,U4_20,0,0 } /* e.g. didbr */ #define INSTR_RRF_RURR 4, { R_24,R_28,R_16,U4_20,0,0 } /* e.g. .insn */ #define INSTR_RRF_R0RR 4, { R_24,R_28,R_16,0,0,0 } /* e.g. idte */ #define INSTR_RRF_U0FF 4, { F_24,U4_16,F_28,0,0,0 } /* e.g. fixr */ #define INSTR_RRF_U0RF 4, { R_24,U4_16,F_28,0,0,0 } /* e.g. cfebr */ +#define INSTR_RRF_UUFF 4, { F_24,U4_16,F_28,U4_20,0,0 } /* e.g. fidtr */ +#define INSTR_RRF_0UFF 4, { F_24,F_28,U4_20,0,0,0 } /* e.g. ldetr */ +#define INSTR_RRF_FFFU 4, { F_24,F_16,F_28,U4_20,0,0 } /* e.g. qadtr */ #define INSTR_RRF_M0RR 4, { R_24,R_28,M_16,0,0,0 } /* e.g. sske */ #define INSTR_RR_0R 2, { R_12, 0,0,0,0,0 } /* e.g. br */ #define INSTR_RR_FF 2, { F_8,F_12,0,0,0,0 } /* e.g. adr */ @@ -221,6 +227,7 @@ const struct s390_operand s390_operands[] = #define INSTR_RR_RR 2, { R_8,R_12,0,0,0,0 } /* e.g. lr */ #define INSTR_RR_U0 2, { U8_8, 0,0,0,0,0 } /* e.g. svc */ #define INSTR_RR_UR 2, { U4_8,R_12,0,0,0,0 } /* e.g. bcr */ +#define INSTR_RRR_F0FF 4, { F_24,F_28,F_16,0,0,0 } /* e.g. ddtr */ #define INSTR_RSE_RRRD 6, { R_8,R_12,D_20,B_16,0,0 } /* e.g. lmh */ #define INSTR_RSE_CCRD 6, { C_8,C_12,D_20,B_16,0,0 } /* e.g. lmh */ #define INSTR_RSE_RURD 6, { R_8,U4_12,D_20,B_16,0,0 } /* e.g. icmh */ @@ -281,13 +288,19 @@ const struct s390_operand s390_operands[] = #define MASK_RRE_RA { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } #define MASK_RRE_RF { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } #define MASK_RRE_RR { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } +#define MASK_RRE_FR { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } #define MASK_RRE_RR_OPT { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } #define MASK_RRF_F0FF { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } +#define MASK_RRF_F0FF2 { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } +#define MASK_RRF_F0FR { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } #define MASK_RRF_FUFF { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } #define MASK_RRF_RURR { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } #define MASK_RRF_R0RR { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } #define MASK_RRF_U0FF { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } #define MASK_RRF_U0RF { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } +#define MASK_RRF_UUFF { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RRF_0UFF { 0xff, 0xff, 0xf0, 0x00, 0x00, 0x00 } +#define MASK_RRF_FFFU { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } #define MASK_RRF_M0RR { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } #define MASK_RR_0R { 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00 } #define MASK_RR_FF { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } @@ -295,6 +308,7 @@ const struct s390_operand s390_operands[] = #define MASK_RR_RR { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } #define MASK_RR_U0 { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } #define MASK_RR_UR { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RRR_F0FF { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } #define MASK_RSE_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } #define MASK_RSE_CCRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } #define MASK_RSE_RURD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } diff --git a/opcodes/s390-opc.txt b/opcodes/s390-opc.txt index db0ccdab54..239b134b14 100644 --- a/opcodes/s390-opc.txt +++ b/opcodes/s390-opc.txt @@ -863,3 +863,66 @@ b338 maylr RRF_F0FF "multiply and add unnormalized long hfp low" z9-109 zarch ed000000003a may RXF_FRRDF "multiply and add unnormalized long hfp" z9-109 zarch ed000000003c mayh RXF_FRRDF "multiply and add unnormalized long hfp high" z9-109 zarch ed0000000038 mayl RXF_FRRDF "multiply and add unnormalized long hfp low" z9-109 zarch +b370 lpdfr RRE_FF "load positive no cc" z9-ec zarch +b371 lndfr RRE_FF "load negative no cc" z9-ec zarch +b372 cpsdr RRF_F0FF2 "copy sign" z9-ec zarch +b373 lcdfr RRE_FF "load complement no cc" z9-ec zarch +b3c1 ldgr RRE_FR "load fpr from gr" z9-ec zarch +b3cd lgdr RRE_RF "load gr from fpr" z9-ec zarch +b3d2 adtr RRR_F0FF "add long dfp" z9-ec zarch +b3da axtr RRR_F0FF "add extended dfp" z9-ec zarch +b3e4 cdtr RRE_FF "compare long dfp" z9-ec zarch +b3ec cxtr RRE_FF "compare extended dfp" z9-ec zarch +b3e0 kdtr RRE_FF "compare and signal long dfp" z9-ec zarch +b3e8 kxtr RRE_FF "compare and signal extended dfp" z9-ec zarch +b3f4 cedtr RRE_FF "compare exponent long dfp" z9-ec zarch +b3fc cextr RRE_FF "compare exponent extended dfp" z9-ec zarch +b3f1 cdgtr RRE_FR "convert from fixed long dfp" z9-ec zarch +b3f9 cxgtr RRE_FR "convert from fixed extended dfp" z9-ec zarch +b3f3 cdstr RRE_FR "convert from signed bcd long dfp" z9-ec zarch +b3fb cxstr RRE_FR "convert from signed bcd extended dfp" z9-ec zarch +b3f2 cdutr RRE_FR "convert from unsigned bcd to long dfp" z9-ec zarch +b3fa cxutr RRE_FR "convert from unsigned bcd to extended dfp" z9-ec zarch +b3e1 cgdtr RRF_U0RF "convert from long dfp to fixed" z9-ec zarch +b3e9 cgxtr RRF_U0RF "convert from extended dfp to fixed" z9-ec zarch +b3e3 csdtr RRE_RF "convert from long dfp to signed bcd" z9-ec zarch +b3eb csxtr RRE_RF "convert from extended dfp to signed bcd" z9-ec zarch +b3e2 cudtr RRE_RF "convert from long dfp to unsigned bcd" z9-ec zarch +b3ea cuxtr RRE_RF "convert from extended dfp to unsigned bcd" z9-ec zarch +b3d1 ddtr RRR_F0FF "divide long dfp" z9-ec zarch +b3d9 dxtr RRR_F0FF "divide extended dfp" z9-ec zarch +b3e5 eedtr RRE_RF "extract biased exponent from long dfp" z9-ec zarch +b3ed eextr RRE_RF "extract biased exponent from extended dfp" z9-ec zarch +b3e7 esdtr RRE_RF "extract significance from long dfp" z9-ec zarch +b3ef esxtr RRE_RF "extract significance from extended dfp" z9-ec zarch +b3f6 iedtr RRF_F0FR "insert biased exponent long dfp" z9-ec zarch +b3fe iextr RRF_F0FR "insert biased exponent extended dfp" z9-ec zarch +b3d6 ltdtr RRE_FF "load and test long dfp" z9-ec zarch +b3de ltxtr RRE_FF "load and test extended dfp" z9-ec zarch +b3d7 fidtr RRF_UUFF "load fp integer long dfp" z9-ec zarch +b3df fixtr RRF_UUFF "load fp integer extended dfp" z9-ec zarch +b2bd lfas S_RD "load fpd and signal" z9-ec zarch +b3d4 ldetr RRF_0UFF "load lengthened long dfp" z9-ec zarch +b3dc lxdtr RRF_0UFF "load lengthened extended dfp" z9-ec zarch +b3d5 ledtr RRF_UUFF "load rounded long dfp" z9-ec zarch +b3dd ldxtr RRF_UUFF "load rounded extended dfp" z9-ec zarch +b3d0 mdtr RRR_F0FF "multiply long dfp" z9-ec zarch +b3d8 mxtr RRR_F0FF "multiply extended dfp" z9-ec zarch +b3f5 qadtr RRF_FFFU "Quantize long dfp" z9-ec zarch +b3fd qaxtr RRF_FFFU "Quantize extended dfp" z9-ec zarch +b3f7 rrdtr RRF_FFFU "Reround long dfp" z9-ec zarch +b3ff rrxtr RRF_FFFU "Reround extended dfp" z9-ec zarch +b2b9 srnmt S_RD "set rounding mode dfp" z9-ec zarch +b385 sfasr RRE_R0 "set fpc and signal" z9-ec zarch +ed0000000040 sldt RXF_FRRDF "shift coefficient left long dfp" z9-ec zarch +ed0000000048 slxt RXF_FRRDF "shift coefficient left extended dfp" z9-ec zarch +ed0000000041 srdt RXF_FRRDF "shift coefficient right long dfp" z9-ec zarch +ed0000000049 srxt RXF_FRRDF "shift coefficient right extended dfp" z9-ec zarch +b3d3 sdtr RRR_F0FF "subtract long dfp" z9-ec zarch +b3db sxtr RRR_F0FF "subtract extended dfp" z9-ec zarch +ed0000000050 tcet RXE_FRRD "test data class short dfp" z9-ec zarch +ed0000000054 tcdt RXE_FRRD "test data class long dfp" z9-ec zarch +ed0000000058 tcxt RXE_FRRD "test data class extended dfp" z9-ec zarch +ed0000000051 tget RXE_FRRD "test data group short dfp" z9-ec zarch +ed0000000055 tgdt RXE_FRRD "test data group long dfp" z9-ec zarch +ed0000000059 tgxt RXE_FRRD "test data group extended dfp" z9-ec zarch -- 2.34.1