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drm/i915: Disable FDI RX/TX before the ports
2015-05-21  Ville Syrjälädrm/i915: Disable FDI RX/TX before the ports
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2015-05-21  Ville Syrjälädrm/i915: Disable CRT port after pipe on PCH platforms
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2015-05-21  Ville Syrjälädrm/i915: Disable SDVO port after the pipe on PCH platforms
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2015-05-21  Ville Syrjälädrm/i915: Disable HDMI port after the pipe on PCH platforms
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2015-05-21  Ville Syrjälädrm/i915: Fix the IBX transcoder B workarounds
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2015-05-21  Ville Syrjälädrm/i915: Write the SDVO reg twice on IBX
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2015-05-21  Ville Syrjälädrm/i915: Fix DP enhanced framing for CPT
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2015-05-21  Ville Syrjälädrm/i915: Clean up the CPT DP .get_hw_state() port...
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2015-05-21  Ville Syrjälädrm/i915: Clarfify the DP code platform checks
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2015-05-21  Ville Syrjälädrm/i915: Remove the double register write from intel_disabl...
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2015-05-21  Ville Syrjälädrm/i915: Remove a bogus 12bpc "toggle" from intel_disable_h...
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2015-05-20  Ville Syrjälädrm/i915: Use HOTPLUG_INT_STATUS_G4X on VLV/CHV
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2015-05-20  Ville Syrjälädrm/i915: Remove excess inline keywords
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2015-05-12  Ville Syrjälädrm/edid: Add CEA modes before inferred modes
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2015-05-08  Ville Syrjälädrm/i915: Only wait for required lanes in vlv_wait_port_ready()
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2015-05-08  Ville SyrjäläRevert "drm/i915: Hack to tie both common lanes together...
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2015-05-08  Ville Syrjälädrm/i915: Work around DISPLAY_PHY_CONTROL register...
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2015-05-08  Ville Syrjälädrm/i915: Implement chv display PHY lane stagger setup
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2015-05-08  Ville Syrjälädrm/i915: Add missing POSTING_READ()s to BXT dbuf enable...
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2015-05-08  Ville Syrjälädrm/i915: s/9/intel_freq_opcode(450)/
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2015-05-08  Ville Syrjälädrm/i915: Use POSTING_READ() in intel_sdvo_write_sdvox()
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2015-05-07  Ville Syrjälädrm/edid: Add DMT modes with ID > 0x50
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2015-05-07  Ville Syrjälädrm/edid: Add the DMT ID in the comments
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2015-05-07  Ville Syrjälädrm/edid: Fix up DMT modes
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2015-04-10  Ville Syrjälädrm/i915: Fix the VBT child device parsing for BSW
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2015-04-10  Ville Syrjälädrm/i915: Silence a sparse warning
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2015-04-02  Ville Syrjälädrm/i915: Reject the colorkey ioctls for primary and...
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2015-03-31  Ville Syrjälädrm/i915: Convert the ddi cdclk code to get_display_clock_speed
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2015-03-31  Ville Syrjälädrm/i915: Simplify ilk_get_aux_clock_divider
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2015-03-31  Ville Syrjälädrm/i915: Assume 400MHz cdclk for the rest of gen4-7
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2015-03-31  Ville Syrjälädrm/i915: ILK cdclk seems to be 450MHz
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2015-03-31  Ville Syrjälädrm/i915: Return more precise cdclk for gen2/3
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2015-03-31  Ville Syrjälädrm/i915: Enable DVO 2x clock around DVO encoder init
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2015-03-31  Ville Syrjälädrm/i915: Mark the overlay active only if we got ring...
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2015-03-31  Ville Syrjälädrm/i915: Convert overlay->{active, pfit_active} to...
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2015-03-31  Ville Syrjälädrm/i915: Convert BUGs to WARNs in the video overlay...
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2015-03-27  Ville Syrjälädrm: Rewrite drm_ioctl_flags() to resemble the new...
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2015-03-27  Ville Syrjälädrm: Use max() to make the ioctl alloc size code cleaner
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2015-03-27  Ville Syrjälädrm: Simplify core vs. drv ioctl handling
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2015-03-27  Ville Syrjälädrm: Drop ioctl->cmd_drv
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2015-03-27  Ville Syrjälädrm: Fix DRM_IOCTL_DEF_DRV()
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2015-03-23  Ville Syrjälädrm/dp: Print the number of bytes processed for aux...
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2015-03-23  Ville Syrjälädrm/i915: Use usleep_range() in wait_for()
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2015-03-20  Ville Syrjälädrm/i915: Fix SKL sprite disable double buffer register...
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2015-03-20  Ville Syrjälädrm/i915: Eliminate plane control register RMW from...
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2015-03-20  Ville Syrjälädrm/i915: Eliminate the RMW sprite colorkey management
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2015-03-20  Ville Syrjälädrm/i915: Kill intel_plane->obj
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2015-03-20  Ville Syrjälädrm/i915: Send out the full AUX address
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2015-03-20  Ville Syrjälädrm/i915: Unconfuse DP link rate array names
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2015-03-20  Ville Syrjälädrm/i915: Include the sink/source/supported rates in...
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2015-03-20  Ville Syrjälädrm/i915: Add eDP intermediate frequencies for CHV
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2015-03-20  Ville Syrjälädrm/i915: Avoid overflowing the DP link rate arrays
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2015-03-20  Ville Syrjälädrm/i915: Fix MST link rate handling
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2015-03-20  Ville Syrjälädrm/i915: Use DP_LINK_RATE_SET whenever possible
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2015-03-20  Ville Syrjälädrm/i915: Fix max link rate in intel_dp_mode_valid()
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2015-03-20  Ville Syrjälädrm/i915: Hide the source vs. sink rate handling from...
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2015-03-20  Ville Syrjälädrm/i915: Fully separate source vs. sink rates
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2015-03-20  Ville Syrjälädrm/i915: Remove special case from intel_supported_rates()
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2015-03-20  Ville Syrjälädrm/i915: Don't copy sink rates either
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2015-03-20  Ville Syrjälädrm/i915: Don't copy the DP source rates arrays
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2015-03-20  Ville Syrjälädrm/i915: Store the converted link rates in intel_dp...
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2015-03-20  Ville Syrjälädrm/i915: Make the DP rates int instead of uint32_t
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2015-03-17  Ville Syrjälädrm/i915: Remove the preliminary_hw_support shackles...
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2015-03-17  Ville Syrjälädrm/i915: Read CHV_PLL_DW8 from the correct offset
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2015-03-17  Ville Syrjälädrm/i915: Rewrite IVB FDI bifurcation conflict checks
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2015-03-17  Ville Syrjälädrm/i915: Rewrite some some of the FDI lane checks
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2015-03-17  Ville Syrjälädrm/i915: Use FW_WM() macro for older gmch platforms too
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2015-03-17  Ville Syrjälädrm/i915: Add polish to VLV WM shift+mask operations
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2015-03-17  Ville Syrjälädrm/i915: Use plane->state->fb instead of plane->fb...
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2015-03-17  Ville Syrjälädrm/i915: Reduce clutter by using the local plane pointer
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2015-03-17  Ville Syrjälädrm/i915: Remove debug prints from primary plane update...
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2015-03-17  Ville Syrjälädrm/i915: Disable DDR DVFS on CHV
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2015-03-17  Ville Syrjälädrm/i915: Enable the maxfifo PM5 mode when appropriate...
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2015-03-17  Ville Syrjälädrm/i915: Rewrite VLV/CHV watermark code
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2015-03-17  Ville Syrjälädrm/i915: Fix chv cdclk support
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2015-03-17  Ville Syrjälädrm/i915: Allow pixel clock up to 95% of cdclk on CHV
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2015-03-17  Ville Syrjälädrm/i915: Make sure PND deadline mode is enabled on...
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2015-03-17  Ville Syrjälädrm/i915: Read out display FIFO size on VLV/CHV
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2015-03-17  Ville Syrjälädrm/i915: Pass plane to vlv_compute_drain_latency()
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2015-03-17  Ville Syrjälädrm/i915: Reorganize VLV DDL setup
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2015-03-17  Ville Syrjälädrm/i915: Hide VLV DDL precision handling
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2015-03-17  Ville Syrjälädrm/i915: Simplify VLV drain latency computation
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2015-03-17  Ville Syrjälädrm/i915: Kill DRAIN_LATENCY_PRECISION_* defines
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2015-03-17  Ville Syrjälädrm/i915: Reduce CHV DDL multiplier to 16/8
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2015-03-17  Ville Syrjälädrm/i915: Reduce CHV DPLL min vco frequency to 4.8 GHz
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2015-03-13  Ville Syrjälädrm: Silence sparse warnings
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2015-03-11  Ville Syrjälädrm/atomic: Constify a bunch of functions pointer structs
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2015-03-09  Ville Syrjälädrm/i915: Fix struct_mutex deadlock due to merge fumble
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2015-02-26  Ville Syrjälädrm/i915: Add media rc6 residency file to sysfs
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2015-02-13  Ville Syrjälädrm/i915: Introduce intel_set_rps()
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2015-02-11  Ville Syrjälädrm/i915: Really ignore long HPD pulses on eDP
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2015-02-03  Ville Syrjälädrm/modes: Print the mode status in human readable...
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2015-02-03  Ville Syrjälädrm/modes: Print the mode status in human readable...
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2015-01-30  Ville Syrjälädrm/i915: Handle CHV in vlv_set_rps_idle()
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2015-01-27  Ville Syrjälädrm/i915: Use intel_gpu_freq() and intel_freq_opcode()
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2015-01-27  Ville Syrjälädrm/i915: Add intel_gpu_freq() and intel_freq_opcode()
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2015-01-27  Ville Syrjälädrm/i915: Add gt_act_freq_mhz sysfs file
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2015-01-27  Ville Syrjälädrm/i915: Update PMINTRMSK on VLV/CHV after sysfs min...
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2015-01-27  Ville Syrjälädrm/i915: Change VLV WIZ hashing mode to 16x4
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2015-01-27  Ville Syrjälädrm/i915: Change CHV WIZ hashing mode to 16x4
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