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gdb: make gdbarch_displaced_step_copy_insn return an std::unique_ptr
[deliverable/binutils-gdb.git] / gdb / aarch64-tdep.c
CommitLineData
07b287a0
MS		 1/* Common target dependent code for GDB on AArch64 systems.
2
11bc5fe4 3 Copyright (C) 2009-2020 Free Software Foundation, Inc.
07b287a0
MS		 4 Contributed by ARM Ltd.
5
6 This file is part of GDB.
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
20
21#include "defs.h"
22
23#include "frame.h"
07b287a0
MS		 24#include "gdbcmd.h"
25#include "gdbcore.h"
4de283e4 26#include "dis-asm.h"
d55e5aa6
TT		 27#include "regcache.h"
28#include "reggroups.h"
4de283e4
TT		 29#include "value.h"
30#include "arch-utils.h"
31#include "osabi.h"
32#include "frame-unwind.h"
33#include "frame-base.h"
d55e5aa6 34#include "trad-frame.h"
4de283e4
TT		 35#include "objfiles.h"
36#include "dwarf2.h"
37#include "dwarf2-frame.h"
38#include "gdbtypes.h"
39#include "prologue-value.h"
40#include "target-descriptions.h"
07b287a0 41#include "user-regs.h"
4de283e4 42#include "ax-gdb.h"
268a13a5 43#include "gdbsupport/selftest.h"
4de283e4
TT		 44
45#include "aarch64-tdep.h"
46#include "aarch64-ravenscar-thread.h"
47
4de283e4
TT		 48#include "record.h"
49#include "record-full.h"
50#include "arch/aarch64-insn.h"
0d12e84c 51#include "gdbarch.h"
4de283e4
TT		 52
53#include "opcode/aarch64.h"
54#include <algorithm>
f77ee802
YQ		 55
56#define submask(x) ((1L << ((x) + 1)) - 1)
57#define bit(obj,st) (((obj) >> (st)) & 1)
58#define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st)))
59
ea92689a
AH		 60/* A Homogeneous Floating-Point or Short-Vector Aggregate may have at most
61 four members. */
62#define HA_MAX_NUM_FLDS 4
63
95228a0d 64/* All possible aarch64 target descriptors. */
6dc0ebde 65struct target_desc *tdesc_aarch64_list[AARCH64_MAX_SVE_VQ + 1][2/*pauth*/];
95228a0d 66
07b287a0
MS		 67/* The standard register names, and all the valid aliases for them. */
68static const struct
69{
70 const char *const name;
71 int regnum;
72} aarch64_register_aliases[] =
73{
74 /* 64-bit register names. */
75 {"fp", AARCH64_FP_REGNUM},
76 {"lr", AARCH64_LR_REGNUM},
77 {"sp", AARCH64_SP_REGNUM},
78
79 /* 32-bit register names. */
80 {"w0", AARCH64_X0_REGNUM + 0},
81 {"w1", AARCH64_X0_REGNUM + 1},
82 {"w2", AARCH64_X0_REGNUM + 2},
83 {"w3", AARCH64_X0_REGNUM + 3},
84 {"w4", AARCH64_X0_REGNUM + 4},
85 {"w5", AARCH64_X0_REGNUM + 5},
86 {"w6", AARCH64_X0_REGNUM + 6},
87 {"w7", AARCH64_X0_REGNUM + 7},
88 {"w8", AARCH64_X0_REGNUM + 8},
89 {"w9", AARCH64_X0_REGNUM + 9},
90 {"w10", AARCH64_X0_REGNUM + 10},
91 {"w11", AARCH64_X0_REGNUM + 11},
92 {"w12", AARCH64_X0_REGNUM + 12},
93 {"w13", AARCH64_X0_REGNUM + 13},
94 {"w14", AARCH64_X0_REGNUM + 14},
95 {"w15", AARCH64_X0_REGNUM + 15},
96 {"w16", AARCH64_X0_REGNUM + 16},
97 {"w17", AARCH64_X0_REGNUM + 17},
98 {"w18", AARCH64_X0_REGNUM + 18},
99 {"w19", AARCH64_X0_REGNUM + 19},
100 {"w20", AARCH64_X0_REGNUM + 20},
101 {"w21", AARCH64_X0_REGNUM + 21},
102 {"w22", AARCH64_X0_REGNUM + 22},
103 {"w23", AARCH64_X0_REGNUM + 23},
104 {"w24", AARCH64_X0_REGNUM + 24},
105 {"w25", AARCH64_X0_REGNUM + 25},
106 {"w26", AARCH64_X0_REGNUM + 26},
107 {"w27", AARCH64_X0_REGNUM + 27},
108 {"w28", AARCH64_X0_REGNUM + 28},
109 {"w29", AARCH64_X0_REGNUM + 29},
110 {"w30", AARCH64_X0_REGNUM + 30},
111
112 /* specials */
113 {"ip0", AARCH64_X0_REGNUM + 16},
114 {"ip1", AARCH64_X0_REGNUM + 17}
115};
116
117/* The required core 'R' registers. */
118static const char *const aarch64_r_register_names[] =
119{
120 /* These registers must appear in consecutive RAW register number
121 order and they must begin with AARCH64_X0_REGNUM! */
122 "x0", "x1", "x2", "x3",
123 "x4", "x5", "x6", "x7",
124 "x8", "x9", "x10", "x11",
125 "x12", "x13", "x14", "x15",
126 "x16", "x17", "x18", "x19",
127 "x20", "x21", "x22", "x23",
128 "x24", "x25", "x26", "x27",
129 "x28", "x29", "x30", "sp",
130 "pc", "cpsr"
131};
132
133/* The FP/SIMD 'V' registers. */
134static const char *const aarch64_v_register_names[] =
135{
136 /* These registers must appear in consecutive RAW register number
137 order and they must begin with AARCH64_V0_REGNUM! */
138 "v0", "v1", "v2", "v3",
139 "v4", "v5", "v6", "v7",
140 "v8", "v9", "v10", "v11",
141 "v12", "v13", "v14", "v15",
142 "v16", "v17", "v18", "v19",
143 "v20", "v21", "v22", "v23",
144 "v24", "v25", "v26", "v27",
145 "v28", "v29", "v30", "v31",
146 "fpsr",
147 "fpcr"
148};
149
739e8682
AH		 150/* The SVE 'Z' and 'P' registers. */
151static const char *const aarch64_sve_register_names[] =
152{
153 /* These registers must appear in consecutive RAW register number
154 order and they must begin with AARCH64_SVE_Z0_REGNUM! */
155 "z0", "z1", "z2", "z3",
156 "z4", "z5", "z6", "z7",
157 "z8", "z9", "z10", "z11",
158 "z12", "z13", "z14", "z15",
159 "z16", "z17", "z18", "z19",
160 "z20", "z21", "z22", "z23",
161 "z24", "z25", "z26", "z27",
162 "z28", "z29", "z30", "z31",
163 "fpsr", "fpcr",
164 "p0", "p1", "p2", "p3",
165 "p4", "p5", "p6", "p7",
166 "p8", "p9", "p10", "p11",
167 "p12", "p13", "p14", "p15",
168 "ffr", "vg"
169};
170
76bed0fd
AH		 171static const char *const aarch64_pauth_register_names[] =
172{
173 /* Authentication mask for data pointer. */
174 "pauth_dmask",
175 /* Authentication mask for code pointer. */
176 "pauth_cmask"
177};
178
07b287a0
MS		 179/* AArch64 prologue cache structure. */
180struct aarch64_prologue_cache
181{
db634143
PL		 182 /* The program counter at the start of the function. It is used to
183 identify this frame as a prologue frame. */
184 CORE_ADDR func;
185
186 /* The program counter at the time this frame was created; i.e. where
187 this function was called from. It is used to identify this frame as a
188 stub frame. */
189 CORE_ADDR prev_pc;
190
07b287a0
MS		 191 /* The stack pointer at the time this frame was created; i.e. the
192 caller's stack pointer when this function was called. It is used
193 to identify this frame. */
194 CORE_ADDR prev_sp;
195
7dfa3edc
PL		 196 /* Is the target available to read from? */
197 int available_p;
198
07b287a0
MS		 199 /* The frame base for this frame is just prev_sp - frame size.
200 FRAMESIZE is the distance from the frame pointer to the
201 initial stack pointer. */
202 int framesize;
203
204 /* The register used to hold the frame pointer for this frame. */
205 int framereg;
206
207 /* Saved register offsets. */
208 struct trad_frame_saved_reg *saved_regs;
209};
210
07b287a0
MS		 211static void
212show_aarch64_debug (struct ui_file *file, int from_tty,
213 struct cmd_list_element *c, const char *value)
214{
215 fprintf_filtered (file, _("AArch64 debugging is %s.\n"), value);
216}
217
ffdbe864
YQ		 218namespace {
219
4d9a9006
YQ		 220/* Abstract instruction reader. */
221
222class abstract_instruction_reader
223{
224public:
225 /* Read in one instruction. */
226 virtual ULONGEST read (CORE_ADDR memaddr, int len,
227 enum bfd_endian byte_order) = 0;
228};
229
230/* Instruction reader from real target. */
231
232class instruction_reader : public abstract_instruction_reader
233{
234 public:
235 ULONGEST read (CORE_ADDR memaddr, int len, enum bfd_endian byte_order)
632e107b 236 override
4d9a9006 237 {
fc2f703e 238 return read_code_unsigned_integer (memaddr, len, byte_order);
4d9a9006
YQ		 239 }
240};
241
ffdbe864
YQ		 242} // namespace
243
3d31bc39
AH		 244/* If address signing is enabled, mask off the signature bits from the link
245 register, which is passed by value in ADDR, using the register values in
246 THIS_FRAME. */
11e1b75f
AH		 247
248static CORE_ADDR
3d31bc39
AH		 249aarch64_frame_unmask_lr (struct gdbarch_tdep *tdep,
250 struct frame_info *this_frame, CORE_ADDR addr)
11e1b75f
AH		 251{
252 if (tdep->has_pauth ()
253 && frame_unwind_register_unsigned (this_frame,
254 tdep->pauth_ra_state_regnum))
255 {
256 int cmask_num = AARCH64_PAUTH_CMASK_REGNUM (tdep->pauth_reg_base);
257 CORE_ADDR cmask = frame_unwind_register_unsigned (this_frame, cmask_num);
258 addr = addr & ~cmask;
3d31bc39
AH		 259
260 /* Record in the frame that the link register required unmasking. */
261 set_frame_previous_pc_masked (this_frame);
11e1b75f
AH		 262 }
263
264 return addr;
265}
266
aa7ca1bb
AH		 267/* Implement the "get_pc_address_flags" gdbarch method. */
268
269static std::string
270aarch64_get_pc_address_flags (frame_info *frame, CORE_ADDR pc)
271{
272 if (pc != 0 && get_frame_pc_masked (frame))
273 return "PAC";
274
275 return "";
276}
277
07b287a0
MS		 278/* Analyze a prologue, looking for a recognizable stack frame
279 and frame pointer. Scan until we encounter a store that could
280 clobber the stack frame unexpectedly, or an unknown instruction. */
281
282static CORE_ADDR
283aarch64_analyze_prologue (struct gdbarch *gdbarch,
284 CORE_ADDR start, CORE_ADDR limit,
4d9a9006
YQ		 285 struct aarch64_prologue_cache *cache,
286 abstract_instruction_reader& reader)
07b287a0
MS		 287{
288 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
289 int i;
187f5d00
YQ		 290 /* Track X registers and D registers in prologue. */
291 pv_t regs[AARCH64_X_REGISTER_COUNT + AARCH64_D_REGISTER_COUNT];
07b287a0 292
187f5d00 293 for (i = 0; i < AARCH64_X_REGISTER_COUNT + AARCH64_D_REGISTER_COUNT; i++)
07b287a0 294 regs[i] = pv_register (i, 0);
f7b7ed97 295 pv_area stack (AARCH64_SP_REGNUM, gdbarch_addr_bit (gdbarch));
07b287a0
MS		 296
297 for (; start < limit; start += 4)
298 {
299 uint32_t insn;
d9ebcbce 300 aarch64_inst inst;
07b287a0 301
4d9a9006 302 insn = reader.read (start, 4, byte_order_for_code);
07b287a0 303
561a72d4 304 if (aarch64_decode_insn (insn, &inst, 1, NULL) != 0)
d9ebcbce
YQ		 305 break;
306
307 if (inst.opcode->iclass == addsub_imm
308 && (inst.opcode->op == OP_ADD
309 || strcmp ("sub", inst.opcode->name) == 0))
07b287a0 310 {
d9ebcbce
YQ		 311 unsigned rd = inst.operands[0].reg.regno;
312 unsigned rn = inst.operands[1].reg.regno;
313
314 gdb_assert (aarch64_num_of_operands (inst.opcode) == 3);
315 gdb_assert (inst.operands[0].type == AARCH64_OPND_Rd_SP);
316 gdb_assert (inst.operands[1].type == AARCH64_OPND_Rn_SP);
317 gdb_assert (inst.operands[2].type == AARCH64_OPND_AIMM);
318
319 if (inst.opcode->op == OP_ADD)
320 {
321 regs[rd] = pv_add_constant (regs[rn],
322 inst.operands[2].imm.value);
323 }
324 else
325 {
326 regs[rd] = pv_add_constant (regs[rn],
327 -inst.operands[2].imm.value);
328 }
329 }
330 else if (inst.opcode->iclass == pcreladdr
331 && inst.operands[1].type == AARCH64_OPND_ADDR_ADRP)
332 {
333 gdb_assert (aarch64_num_of_operands (inst.opcode) == 2);
334 gdb_assert (inst.operands[0].type == AARCH64_OPND_Rd);
335
336 regs[inst.operands[0].reg.regno] = pv_unknown ();
07b287a0 337 }
d9ebcbce 338 else if (inst.opcode->iclass == branch_imm)
07b287a0
MS		 339 {
340 /* Stop analysis on branch. */
341 break;
342 }
d9ebcbce 343 else if (inst.opcode->iclass == condbranch)
07b287a0
MS		 344 {
345 /* Stop analysis on branch. */
346 break;
347 }
d9ebcbce 348 else if (inst.opcode->iclass == branch_reg)
07b287a0
MS		 349 {
350 /* Stop analysis on branch. */
351 break;
352 }
d9ebcbce 353 else if (inst.opcode->iclass == compbranch)
07b287a0
MS		 354 {
355 /* Stop analysis on branch. */
356 break;
357 }
d9ebcbce
YQ		 358 else if (inst.opcode->op == OP_MOVZ)
359 {
360 gdb_assert (inst.operands[0].type == AARCH64_OPND_Rd);
361 regs[inst.operands[0].reg.regno] = pv_unknown ();
362 }
363 else if (inst.opcode->iclass == log_shift
364 && strcmp (inst.opcode->name, "orr") == 0)
07b287a0 365 {
d9ebcbce
YQ		 366 unsigned rd = inst.operands[0].reg.regno;
367 unsigned rn = inst.operands[1].reg.regno;
368 unsigned rm = inst.operands[2].reg.regno;
369
370 gdb_assert (inst.operands[0].type == AARCH64_OPND_Rd);
371 gdb_assert (inst.operands[1].type == AARCH64_OPND_Rn);
372 gdb_assert (inst.operands[2].type == AARCH64_OPND_Rm_SFT);
373
374 if (inst.operands[2].shifter.amount == 0
375 && rn == AARCH64_SP_REGNUM)
07b287a0
MS		 376 regs[rd] = regs[rm];
377 else
378 {
379 if (aarch64_debug)
b277c936
PL		 380 {
381 debug_printf ("aarch64: prologue analysis gave up "
0a0da556 382 "addr=%s opcode=0x%x (orr x register)\n",
b277c936
PL		 383 core_addr_to_string_nz (start), insn);
384 }
07b287a0
MS		 385 break;
386 }
387 }
d9ebcbce 388 else if (inst.opcode->op == OP_STUR)
07b287a0 389 {
d9ebcbce
YQ		 390 unsigned rt = inst.operands[0].reg.regno;
391 unsigned rn = inst.operands[1].addr.base_regno;
75faf5c4 392 int size = aarch64_get_qualifier_esize (inst.operands[0].qualifier);
d9ebcbce
YQ		 393
394 gdb_assert (aarch64_num_of_operands (inst.opcode) == 2);
395 gdb_assert (inst.operands[0].type == AARCH64_OPND_Rt);
396 gdb_assert (inst.operands[1].type == AARCH64_OPND_ADDR_SIMM9);
397 gdb_assert (!inst.operands[1].addr.offset.is_reg);
398
75faf5c4
AH		 399 stack.store
400 (pv_add_constant (regs[rn], inst.operands[1].addr.offset.imm),
401 size, regs[rt]);
07b287a0 402 }
d9ebcbce 403 else if ((inst.opcode->iclass == ldstpair_off
03bcd739
YQ		 404 || (inst.opcode->iclass == ldstpair_indexed
405 && inst.operands[2].addr.preind))
d9ebcbce 406 && strcmp ("stp", inst.opcode->name) == 0)
07b287a0 407 {
03bcd739 408 /* STP with addressing mode Pre-indexed and Base register. */
187f5d00
YQ		 409 unsigned rt1;
410 unsigned rt2;
d9ebcbce
YQ		 411 unsigned rn = inst.operands[2].addr.base_regno;
412 int32_t imm = inst.operands[2].addr.offset.imm;
75faf5c4 413 int size = aarch64_get_qualifier_esize (inst.operands[0].qualifier);
d9ebcbce 414
187f5d00
YQ		 415 gdb_assert (inst.operands[0].type == AARCH64_OPND_Rt
416 || inst.operands[0].type == AARCH64_OPND_Ft);
417 gdb_assert (inst.operands[1].type == AARCH64_OPND_Rt2
418 || inst.operands[1].type == AARCH64_OPND_Ft2);
d9ebcbce
YQ		 419 gdb_assert (inst.operands[2].type == AARCH64_OPND_ADDR_SIMM7);
420 gdb_assert (!inst.operands[2].addr.offset.is_reg);
421
07b287a0
MS		 422 /* If recording this store would invalidate the store area
423 (perhaps because rn is not known) then we should abandon
424 further prologue analysis. */
f7b7ed97 425 if (stack.store_would_trash (pv_add_constant (regs[rn], imm)))
07b287a0
MS		 426 break;
427
f7b7ed97 428 if (stack.store_would_trash (pv_add_constant (regs[rn], imm + 8)))
07b287a0
MS		 429 break;
430
187f5d00
YQ		 431 rt1 = inst.operands[0].reg.regno;
432 rt2 = inst.operands[1].reg.regno;
433 if (inst.operands[0].type == AARCH64_OPND_Ft)
434 {
187f5d00
YQ		 435 rt1 += AARCH64_X_REGISTER_COUNT;
436 rt2 += AARCH64_X_REGISTER_COUNT;
437 }
438
75faf5c4
AH		 439 stack.store (pv_add_constant (regs[rn], imm), size, regs[rt1]);
440 stack.store (pv_add_constant (regs[rn], imm + size), size, regs[rt2]);
14ac654f 441
d9ebcbce 442 if (inst.operands[2].addr.writeback)
93d96012 443 regs[rn] = pv_add_constant (regs[rn], imm);
07b287a0 444
07b287a0 445 }
432ec081
YQ		 446 else if ((inst.opcode->iclass == ldst_imm9 /* Signed immediate. */
447 || (inst.opcode->iclass == ldst_pos /* Unsigned immediate. */
448 && (inst.opcode->op == OP_STR_POS
449 || inst.opcode->op == OP_STRF_POS)))
450 && inst.operands[1].addr.base_regno == AARCH64_SP_REGNUM
451 && strcmp ("str", inst.opcode->name) == 0)
452 {
453 /* STR (immediate) */
454 unsigned int rt = inst.operands[0].reg.regno;
455 int32_t imm = inst.operands[1].addr.offset.imm;
456 unsigned int rn = inst.operands[1].addr.base_regno;
75faf5c4 457 int size = aarch64_get_qualifier_esize (inst.operands[0].qualifier);
432ec081
YQ		 458 gdb_assert (inst.operands[0].type == AARCH64_OPND_Rt
459 || inst.operands[0].type == AARCH64_OPND_Ft);
460
461 if (inst.operands[0].type == AARCH64_OPND_Ft)
75faf5c4 462 rt += AARCH64_X_REGISTER_COUNT;
432ec081 463
75faf5c4 464 stack.store (pv_add_constant (regs[rn], imm), size, regs[rt]);
432ec081
YQ		 465 if (inst.operands[1].addr.writeback)
466 regs[rn] = pv_add_constant (regs[rn], imm);
467 }
d9ebcbce 468 else if (inst.opcode->iclass == testbranch)
07b287a0
MS		 469 {
470 /* Stop analysis on branch. */
471 break;
472 }
17e116a7
AH		 473 else if (inst.opcode->iclass == ic_system)
474 {
475 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
476 int ra_state_val = 0;
477
478 if (insn == 0xd503233f /* paciasp. */
479 || insn == 0xd503237f /* pacibsp. */)
480 {
481 /* Return addresses are mangled. */
482 ra_state_val = 1;
483 }
484 else if (insn == 0xd50323bf /* autiasp. */
485 || insn == 0xd50323ff /* autibsp. */)
486 {
487 /* Return addresses are not mangled. */
488 ra_state_val = 0;
489 }
490 else
491 {
492 if (aarch64_debug)
493 debug_printf ("aarch64: prologue analysis gave up addr=%s"
494 " opcode=0x%x (iclass)\n",
495 core_addr_to_string_nz (start), insn);
496 break;
497 }
498
499 if (tdep->has_pauth () && cache != nullptr)
500 trad_frame_set_value (cache->saved_regs,
501 tdep->pauth_ra_state_regnum,
502 ra_state_val);
503 }
07b287a0
MS		 504 else
505 {
506 if (aarch64_debug)
b277c936 507 {
0a0da556 508 debug_printf ("aarch64: prologue analysis gave up addr=%s"
b277c936
PL		 509 " opcode=0x%x\n",
510 core_addr_to_string_nz (start), insn);
511 }
07b287a0
MS		 512 break;
513 }
514 }
515
516 if (cache == NULL)
f7b7ed97 517 return start;
07b287a0
MS		 518
519 if (pv_is_register (regs[AARCH64_FP_REGNUM], AARCH64_SP_REGNUM))
520 {
521 /* Frame pointer is fp. Frame size is constant. */
522 cache->framereg = AARCH64_FP_REGNUM;
523 cache->framesize = -regs[AARCH64_FP_REGNUM].k;
524 }
525 else if (pv_is_register (regs[AARCH64_SP_REGNUM], AARCH64_SP_REGNUM))
526 {
527 /* Try the stack pointer. */
528 cache->framesize = -regs[AARCH64_SP_REGNUM].k;
529 cache->framereg = AARCH64_SP_REGNUM;
530 }
531 else
532 {
533 /* We're just out of luck. We don't know where the frame is. */
534 cache->framereg = -1;
535 cache->framesize = 0;
536 }
537
538 for (i = 0; i < AARCH64_X_REGISTER_COUNT; i++)
539 {
540 CORE_ADDR offset;
541
f7b7ed97 542 if (stack.find_reg (gdbarch, i, &offset))
07b287a0
MS		 543 cache->saved_regs[i].addr = offset;
544 }
545
187f5d00
YQ		 546 for (i = 0; i < AARCH64_D_REGISTER_COUNT; i++)
547 {
548 int regnum = gdbarch_num_regs (gdbarch);
549 CORE_ADDR offset;
550
f7b7ed97
TT		 551 if (stack.find_reg (gdbarch, i + AARCH64_X_REGISTER_COUNT,
552 &offset))
187f5d00
YQ		 553 cache->saved_regs[i + regnum + AARCH64_D0_REGNUM].addr = offset;
554 }
555
07b287a0
MS		 556 return start;
557}
558
4d9a9006
YQ		 559static CORE_ADDR
560aarch64_analyze_prologue (struct gdbarch *gdbarch,
561 CORE_ADDR start, CORE_ADDR limit,
562 struct aarch64_prologue_cache *cache)
563{
564 instruction_reader reader;
565
566 return aarch64_analyze_prologue (gdbarch, start, limit, cache,
567 reader);
568}
569
570#if GDB_SELF_TEST
571
572namespace selftests {
573
574/* Instruction reader from manually cooked instruction sequences. */
575
576class instruction_reader_test : public abstract_instruction_reader
577{
578public:
579 template<size_t SIZE>
580 explicit instruction_reader_test (const uint32_t (&insns)[SIZE])
581 : m_insns (insns), m_insns_size (SIZE)
582 {}
583
584 ULONGEST read (CORE_ADDR memaddr, int len, enum bfd_endian byte_order)
632e107b 585 override
4d9a9006
YQ		 586 {
587 SELF_CHECK (len == 4);
588 SELF_CHECK (memaddr % 4 == 0);
589 SELF_CHECK (memaddr / 4 < m_insns_size);
590
591 return m_insns[memaddr / 4];
592 }
593
594private:
595 const uint32_t *m_insns;
596 size_t m_insns_size;
597};
598
599static void
600aarch64_analyze_prologue_test (void)
601{
602 struct gdbarch_info info;
603
604 gdbarch_info_init (&info);
605 info.bfd_arch_info = bfd_scan_arch ("aarch64");
606
607 struct gdbarch *gdbarch = gdbarch_find_by_info (info);
608 SELF_CHECK (gdbarch != NULL);
609
17e116a7
AH		 610 struct aarch64_prologue_cache cache;
611 cache.saved_regs = trad_frame_alloc_saved_regs (gdbarch);
612
613 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
614
4d9a9006
YQ		 615 /* Test the simple prologue in which frame pointer is used. */
616 {
4d9a9006
YQ		 617 static const uint32_t insns[] = {
618 0xa9af7bfd, /* stp x29, x30, [sp,#-272]! */
619 0x910003fd, /* mov x29, sp */
620 0x97ffffe6, /* bl 0x400580 */
621 };
622 instruction_reader_test reader (insns);
623
624 CORE_ADDR end = aarch64_analyze_prologue (gdbarch, 0, 128, &cache, reader);
625 SELF_CHECK (end == 4 * 2);
626
627 SELF_CHECK (cache.framereg == AARCH64_FP_REGNUM);
628 SELF_CHECK (cache.framesize == 272);
629
630 for (int i = 0; i < AARCH64_X_REGISTER_COUNT; i++)
631 {
632 if (i == AARCH64_FP_REGNUM)
633 SELF_CHECK (cache.saved_regs[i].addr == -272);
634 else if (i == AARCH64_LR_REGNUM)
635 SELF_CHECK (cache.saved_regs[i].addr == -264);
636 else
637 SELF_CHECK (cache.saved_regs[i].addr == -1);
638 }
639
640 for (int i = 0; i < AARCH64_D_REGISTER_COUNT; i++)
641 {
642 int regnum = gdbarch_num_regs (gdbarch);
643
644 SELF_CHECK (cache.saved_regs[i + regnum + AARCH64_D0_REGNUM].addr
645 == -1);
646 }
647 }
432ec081
YQ		 648
649 /* Test a prologue in which STR is used and frame pointer is not
650 used. */
651 {
432ec081
YQ		 652 static const uint32_t insns[] = {
653 0xf81d0ff3, /* str x19, [sp, #-48]! */
654 0xb9002fe0, /* str w0, [sp, #44] */
655 0xf90013e1, /* str x1, [sp, #32]*/
656 0xfd000fe0, /* str d0, [sp, #24] */
657 0xaa0203f3, /* mov x19, x2 */
658 0xf94013e0, /* ldr x0, [sp, #32] */
659 };
660 instruction_reader_test reader (insns);
661
68811f8f 662 trad_frame_reset_saved_regs (gdbarch, cache.saved_regs);
432ec081
YQ		 663 CORE_ADDR end = aarch64_analyze_prologue (gdbarch, 0, 128, &cache, reader);
664
665 SELF_CHECK (end == 4 * 5);
666
667 SELF_CHECK (cache.framereg == AARCH64_SP_REGNUM);
668 SELF_CHECK (cache.framesize == 48);
669
670 for (int i = 0; i < AARCH64_X_REGISTER_COUNT; i++)
671 {
672 if (i == 1)
673 SELF_CHECK (cache.saved_regs[i].addr == -16);
674 else if (i == 19)
675 SELF_CHECK (cache.saved_regs[i].addr == -48);
676 else
677 SELF_CHECK (cache.saved_regs[i].addr == -1);
678 }
679
680 for (int i = 0; i < AARCH64_D_REGISTER_COUNT; i++)
681 {
682 int regnum = gdbarch_num_regs (gdbarch);
683
684 if (i == 0)
685 SELF_CHECK (cache.saved_regs[i + regnum + AARCH64_D0_REGNUM].addr
686 == -24);
687 else
688 SELF_CHECK (cache.saved_regs[i + regnum + AARCH64_D0_REGNUM].addr
689 == -1);
690 }
691 }
17e116a7
AH		 692
693 /* Test a prologue in which there is a return address signing instruction. */
694 if (tdep->has_pauth ())
695 {
696 static const uint32_t insns[] = {
697 0xd503233f, /* paciasp */
698 0xa9bd7bfd, /* stp x29, x30, [sp, #-48]! */
699 0x910003fd, /* mov x29, sp */
700 0xf801c3f3, /* str x19, [sp, #28] */
701 0xb9401fa0, /* ldr x19, [x29, #28] */
702 };
703 instruction_reader_test reader (insns);
704
68811f8f 705 trad_frame_reset_saved_regs (gdbarch, cache.saved_regs);
17e116a7
AH		 706 CORE_ADDR end = aarch64_analyze_prologue (gdbarch, 0, 128, &cache,
707 reader);
708
709 SELF_CHECK (end == 4 * 4);
710 SELF_CHECK (cache.framereg == AARCH64_FP_REGNUM);
711 SELF_CHECK (cache.framesize == 48);
712
713 for (int i = 0; i < AARCH64_X_REGISTER_COUNT; i++)
714 {
715 if (i == 19)
716 SELF_CHECK (cache.saved_regs[i].addr == -20);
717 else if (i == AARCH64_FP_REGNUM)
718 SELF_CHECK (cache.saved_regs[i].addr == -48);
719 else if (i == AARCH64_LR_REGNUM)
720 SELF_CHECK (cache.saved_regs[i].addr == -40);
721 else
722 SELF_CHECK (cache.saved_regs[i].addr == -1);
723 }
724
725 if (tdep->has_pauth ())
726 {
727 SELF_CHECK (trad_frame_value_p (cache.saved_regs,
728 tdep->pauth_ra_state_regnum));
729 SELF_CHECK (cache.saved_regs[tdep->pauth_ra_state_regnum].addr == 1);
730 }
731 }
4d9a9006
YQ		 732}
733} // namespace selftests
734#endif /* GDB_SELF_TEST */
735
07b287a0
MS		 736/* Implement the "skip_prologue" gdbarch method. */
737
738static CORE_ADDR
739aarch64_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
740{
07b287a0 741 CORE_ADDR func_addr, limit_pc;
07b287a0
MS		 742
743 /* See if we can determine the end of the prologue via the symbol
744 table. If so, then return either PC, or the PC after the
745 prologue, whichever is greater. */
746 if (find_pc_partial_function (pc, NULL, &func_addr, NULL))
747 {
748 CORE_ADDR post_prologue_pc
749 = skip_prologue_using_sal (gdbarch, func_addr);
750
751 if (post_prologue_pc != 0)
325fac50 752 return std::max (pc, post_prologue_pc);
07b287a0
MS		 753 }
754
755 /* Can't determine prologue from the symbol table, need to examine
756 instructions. */
757
758 /* Find an upper limit on the function prologue using the debug
759 information. If the debug information could not be used to
760 provide that bound, then use an arbitrary large number as the
761 upper bound. */
762 limit_pc = skip_prologue_using_sal (gdbarch, pc);
763 if (limit_pc == 0)
764 limit_pc = pc + 128; /* Magic. */
765
766 /* Try disassembling prologue. */
767 return aarch64_analyze_prologue (gdbarch, pc, limit_pc, NULL);
768}
769
770/* Scan the function prologue for THIS_FRAME and populate the prologue
771 cache CACHE. */
772
773static void
774aarch64_scan_prologue (struct frame_info *this_frame,
775 struct aarch64_prologue_cache *cache)
776{
777 CORE_ADDR block_addr = get_frame_address_in_block (this_frame);
778 CORE_ADDR prologue_start;
779 CORE_ADDR prologue_end;
780 CORE_ADDR prev_pc = get_frame_pc (this_frame);
781 struct gdbarch *gdbarch = get_frame_arch (this_frame);
782
db634143
PL		 783 cache->prev_pc = prev_pc;
784
07b287a0
MS		 785 /* Assume we do not find a frame. */
786 cache->framereg = -1;
787 cache->framesize = 0;
788
789 if (find_pc_partial_function (block_addr, NULL, &prologue_start,
790 &prologue_end))
791 {
792 struct symtab_and_line sal = find_pc_line (prologue_start, 0);
793
794 if (sal.line == 0)
795 {
796 /* No line info so use the current PC. */
797 prologue_end = prev_pc;
798 }
799 else if (sal.end < prologue_end)
800 {
801 /* The next line begins after the function end. */
802 prologue_end = sal.end;
803 }
804
325fac50 805 prologue_end = std::min (prologue_end, prev_pc);
07b287a0
MS		 806 aarch64_analyze_prologue (gdbarch, prologue_start, prologue_end, cache);
807 }
808 else
809 {
810 CORE_ADDR frame_loc;
07b287a0
MS		 811
812 frame_loc = get_frame_register_unsigned (this_frame, AARCH64_FP_REGNUM);
813 if (frame_loc == 0)
814 return;
815
816 cache->framereg = AARCH64_FP_REGNUM;
817 cache->framesize = 16;
818 cache->saved_regs[29].addr = 0;
819 cache->saved_regs[30].addr = 8;
820 }
821}
822
7dfa3edc
PL		 823/* Fill in *CACHE with information about the prologue of *THIS_FRAME. This
824 function may throw an exception if the inferior's registers or memory is
825 not available. */
07b287a0 826
7dfa3edc
PL		 827static void
828aarch64_make_prologue_cache_1 (struct frame_info *this_frame,
829 struct aarch64_prologue_cache *cache)
07b287a0 830{
07b287a0
MS		 831 CORE_ADDR unwound_fp;
832 int reg;
833
07b287a0
MS		 834 aarch64_scan_prologue (this_frame, cache);
835
836 if (cache->framereg == -1)
7dfa3edc 837 return;
07b287a0
MS		 838
839 unwound_fp = get_frame_register_unsigned (this_frame, cache->framereg);
840 if (unwound_fp == 0)
7dfa3edc 841 return;
07b287a0
MS		 842
843 cache->prev_sp = unwound_fp + cache->framesize;
844
845 /* Calculate actual addresses of saved registers using offsets
846 determined by aarch64_analyze_prologue. */
847 for (reg = 0; reg < gdbarch_num_regs (get_frame_arch (this_frame)); reg++)
848 if (trad_frame_addr_p (cache->saved_regs, reg))
849 cache->saved_regs[reg].addr += cache->prev_sp;
850
db634143
PL		 851 cache->func = get_frame_func (this_frame);
852
7dfa3edc
PL		 853 cache->available_p = 1;
854}
855
856/* Allocate and fill in *THIS_CACHE with information about the prologue of
857 *THIS_FRAME. Do not do this is if *THIS_CACHE was already allocated.
858 Return a pointer to the current aarch64_prologue_cache in
859 *THIS_CACHE. */
860
861static struct aarch64_prologue_cache *
862aarch64_make_prologue_cache (struct frame_info *this_frame, void **this_cache)
863{
864 struct aarch64_prologue_cache *cache;
865
866 if (*this_cache != NULL)
9a3c8263 867 return (struct aarch64_prologue_cache *) *this_cache;
7dfa3edc
PL		 868
869 cache = FRAME_OBSTACK_ZALLOC (struct aarch64_prologue_cache);
870 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
871 *this_cache = cache;
872
a70b8144 873 try
7dfa3edc
PL		 874 {
875 aarch64_make_prologue_cache_1 (this_frame, cache);
876 }
230d2906 877 catch (const gdb_exception_error &ex)
7dfa3edc
PL		 878 {
879 if (ex.error != NOT_AVAILABLE_ERROR)
eedc3f4f 880 throw;
7dfa3edc 881 }
7dfa3edc 882
07b287a0
MS		 883 return cache;
884}
885
7dfa3edc
PL		 886/* Implement the "stop_reason" frame_unwind method. */
887
888static enum unwind_stop_reason
889aarch64_prologue_frame_unwind_stop_reason (struct frame_info *this_frame,
890 void **this_cache)
891{
892 struct aarch64_prologue_cache *cache
893 = aarch64_make_prologue_cache (this_frame, this_cache);
894
895 if (!cache->available_p)
896 return UNWIND_UNAVAILABLE;
897
898 /* Halt the backtrace at "_start". */
899 if (cache->prev_pc <= gdbarch_tdep (get_frame_arch (this_frame))->lowest_pc)
900 return UNWIND_OUTERMOST;
901
902 /* We've hit a wall, stop. */
903 if (cache->prev_sp == 0)
904 return UNWIND_OUTERMOST;
905
906 return UNWIND_NO_REASON;
907}
908
07b287a0
MS		 909/* Our frame ID for a normal frame is the current function's starting
910 PC and the caller's SP when we were called. */
911
912static void
913aarch64_prologue_this_id (struct frame_info *this_frame,
914 void **this_cache, struct frame_id *this_id)
915{
7c8edfae
PL		 916 struct aarch64_prologue_cache *cache
917 = aarch64_make_prologue_cache (this_frame, this_cache);
07b287a0 918
7dfa3edc
PL		 919 if (!cache->available_p)
920 *this_id = frame_id_build_unavailable_stack (cache->func);
921 else
922 *this_id = frame_id_build (cache->prev_sp, cache->func);
07b287a0
MS		 923}
924
925/* Implement the "prev_register" frame_unwind method. */
926
927static struct value *
928aarch64_prologue_prev_register (struct frame_info *this_frame,
929 void **this_cache, int prev_regnum)
930{
7c8edfae
PL		 931 struct aarch64_prologue_cache *cache
932 = aarch64_make_prologue_cache (this_frame, this_cache);
07b287a0
MS		 933
934 /* If we are asked to unwind the PC, then we need to return the LR
935 instead. The prologue may save PC, but it will point into this
936 frame's prologue, not the next frame's resume location. */
937 if (prev_regnum == AARCH64_PC_REGNUM)
938 {
939 CORE_ADDR lr;
17e116a7
AH		 940 struct gdbarch *gdbarch = get_frame_arch (this_frame);
941 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
07b287a0
MS		 942
943 lr = frame_unwind_register_unsigned (this_frame, AARCH64_LR_REGNUM);
17e116a7
AH		 944
945 if (tdep->has_pauth ()
946 && trad_frame_value_p (cache->saved_regs,
947 tdep->pauth_ra_state_regnum))
3d31bc39 948 lr = aarch64_frame_unmask_lr (tdep, this_frame, lr);
17e116a7 949
07b287a0
MS		 950 return frame_unwind_got_constant (this_frame, prev_regnum, lr);
951 }
952
953 /* SP is generally not saved to the stack, but this frame is
954 identified by the next frame's stack pointer at the time of the
955 call. The value was already reconstructed into PREV_SP. */
956 /*
957 +----------+ ^
958 | saved lr | |
959 +->| saved fp |--+
960 | | |
961 | | | <- Previous SP
962 | +----------+
963 | | saved lr |
964 +--| saved fp |<- FP
965 | |
966 | |<- SP
967 +----------+ */
968 if (prev_regnum == AARCH64_SP_REGNUM)
969 return frame_unwind_got_constant (this_frame, prev_regnum,
970 cache->prev_sp);
971
972 return trad_frame_get_prev_register (this_frame, cache->saved_regs,
973 prev_regnum);
974}
975
976/* AArch64 prologue unwinder. */
977struct frame_unwind aarch64_prologue_unwind =
978{
979 NORMAL_FRAME,
7dfa3edc 980 aarch64_prologue_frame_unwind_stop_reason,
07b287a0
MS		 981 aarch64_prologue_this_id,
982 aarch64_prologue_prev_register,
983 NULL,
984 default_frame_sniffer
985};
986
8b61f75d
PL		 987/* Allocate and fill in *THIS_CACHE with information about the prologue of
988 *THIS_FRAME. Do not do this is if *THIS_CACHE was already allocated.
989 Return a pointer to the current aarch64_prologue_cache in
990 *THIS_CACHE. */
07b287a0
MS		 991
992static struct aarch64_prologue_cache *
8b61f75d 993aarch64_make_stub_cache (struct frame_info *this_frame, void **this_cache)
07b287a0 994{
07b287a0 995 struct aarch64_prologue_cache *cache;
8b61f75d
PL		 996
997 if (*this_cache != NULL)
9a3c8263 998 return (struct aarch64_prologue_cache *) *this_cache;
07b287a0
MS		 999
1000 cache = FRAME_OBSTACK_ZALLOC (struct aarch64_prologue_cache);
1001 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
8b61f75d 1002 *this_cache = cache;
07b287a0 1003
a70b8144 1004 try
02a2a705
PL		 1005 {
1006 cache->prev_sp = get_frame_register_unsigned (this_frame,
1007 AARCH64_SP_REGNUM);
1008 cache->prev_pc = get_frame_pc (this_frame);
1009 cache->available_p = 1;
1010 }
230d2906 1011 catch (const gdb_exception_error &ex)
02a2a705
PL		 1012 {
1013 if (ex.error != NOT_AVAILABLE_ERROR)
eedc3f4f 1014 throw;
02a2a705 1015 }
07b287a0
MS		 1016
1017 return cache;
1018}
1019
02a2a705
PL		 1020/* Implement the "stop_reason" frame_unwind method. */
1021
1022static enum unwind_stop_reason
1023aarch64_stub_frame_unwind_stop_reason (struct frame_info *this_frame,
1024 void **this_cache)
1025{
1026 struct aarch64_prologue_cache *cache
1027 = aarch64_make_stub_cache (this_frame, this_cache);
1028
1029 if (!cache->available_p)
1030 return UNWIND_UNAVAILABLE;
1031
1032 return UNWIND_NO_REASON;
1033}
1034
07b287a0
MS		 1035/* Our frame ID for a stub frame is the current SP and LR. */
1036
1037static void
1038aarch64_stub_this_id (struct frame_info *this_frame,
1039 void **this_cache, struct frame_id *this_id)
1040{
8b61f75d
PL		 1041 struct aarch64_prologue_cache *cache
1042 = aarch64_make_stub_cache (this_frame, this_cache);
07b287a0 1043
02a2a705
PL		 1044 if (cache->available_p)
1045 *this_id = frame_id_build (cache->prev_sp, cache->prev_pc);
1046 else
1047 *this_id = frame_id_build_unavailable_stack (cache->prev_pc);
07b287a0
MS		 1048}
1049
1050/* Implement the "sniffer" frame_unwind method. */
1051
1052static int
1053aarch64_stub_unwind_sniffer (const struct frame_unwind *self,
1054 struct frame_info *this_frame,
1055 void **this_prologue_cache)
1056{
1057 CORE_ADDR addr_in_block;
1058 gdb_byte dummy[4];
1059
1060 addr_in_block = get_frame_address_in_block (this_frame);
3e5d3a5a 1061 if (in_plt_section (addr_in_block)
07b287a0
MS		 1062 /* We also use the stub winder if the target memory is unreadable
1063 to avoid having the prologue unwinder trying to read it. */
1064 || target_read_memory (get_frame_pc (this_frame), dummy, 4) != 0)
1065 return 1;
1066
1067 return 0;
1068}
1069
1070/* AArch64 stub unwinder. */
1071struct frame_unwind aarch64_stub_unwind =
1072{
1073 NORMAL_FRAME,
02a2a705 1074 aarch64_stub_frame_unwind_stop_reason,
07b287a0
MS		 1075 aarch64_stub_this_id,
1076 aarch64_prologue_prev_register,
1077 NULL,
1078 aarch64_stub_unwind_sniffer
1079};
1080
1081/* Return the frame base address of *THIS_FRAME. */
1082
1083static CORE_ADDR
1084aarch64_normal_frame_base (struct frame_info *this_frame, void **this_cache)
1085{
7c8edfae
PL		 1086 struct aarch64_prologue_cache *cache
1087 = aarch64_make_prologue_cache (this_frame, this_cache);
07b287a0
MS		 1088
1089 return cache->prev_sp - cache->framesize;
1090}
1091
1092/* AArch64 default frame base information. */
1093struct frame_base aarch64_normal_base =
1094{
1095 &aarch64_prologue_unwind,
1096 aarch64_normal_frame_base,
1097 aarch64_normal_frame_base,
1098 aarch64_normal_frame_base
1099};
1100
07b287a0
MS		 1101/* Return the value of the REGNUM register in the previous frame of
1102 *THIS_FRAME. */
1103
1104static struct value *
1105aarch64_dwarf2_prev_register (struct frame_info *this_frame,
1106 void **this_cache, int regnum)
1107{
11e1b75f 1108 struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (this_frame));
07b287a0
MS		 1109 CORE_ADDR lr;
1110
1111 switch (regnum)
1112 {
1113 case AARCH64_PC_REGNUM:
1114 lr = frame_unwind_register_unsigned (this_frame, AARCH64_LR_REGNUM);
3d31bc39 1115 lr = aarch64_frame_unmask_lr (tdep, this_frame, lr);
07b287a0
MS		 1116 return frame_unwind_got_constant (this_frame, regnum, lr);
1117
1118 default:
1119 internal_error (__FILE__, __LINE__,
1120 _("Unexpected register %d"), regnum);
1121 }
1122}
1123
11e1b75f
AH		 1124static const unsigned char op_lit0 = DW_OP_lit0;
1125static const unsigned char op_lit1 = DW_OP_lit1;
1126
07b287a0
MS		 1127/* Implement the "init_reg" dwarf2_frame_ops method. */
1128
1129static void
1130aarch64_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum,
1131 struct dwarf2_frame_state_reg *reg,
1132 struct frame_info *this_frame)
1133{
11e1b75f
AH		 1134 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1135
07b287a0
MS		 1136 switch (regnum)
1137 {
1138 case AARCH64_PC_REGNUM:
1139 reg->how = DWARF2_FRAME_REG_FN;
1140 reg->loc.fn = aarch64_dwarf2_prev_register;
11e1b75f
AH		 1141 return;
1142
07b287a0
MS		 1143 case AARCH64_SP_REGNUM:
1144 reg->how = DWARF2_FRAME_REG_CFA;
11e1b75f
AH		 1145 return;
1146 }
1147
1148 /* Init pauth registers. */
1149 if (tdep->has_pauth ())
1150 {
1151 if (regnum == tdep->pauth_ra_state_regnum)
1152 {
1153 /* Initialize RA_STATE to zero. */
1154 reg->how = DWARF2_FRAME_REG_SAVED_VAL_EXP;
1155 reg->loc.exp.start = &op_lit0;
1156 reg->loc.exp.len = 1;
1157 return;
1158 }
1159 else if (regnum == AARCH64_PAUTH_DMASK_REGNUM (tdep->pauth_reg_base)
1160 || regnum == AARCH64_PAUTH_CMASK_REGNUM (tdep->pauth_reg_base))
1161 {
1162 reg->how = DWARF2_FRAME_REG_SAME_VALUE;
1163 return;
1164 }
07b287a0
MS		 1165 }
1166}
1167
11e1b75f
AH		 1168/* Implement the execute_dwarf_cfa_vendor_op method. */
1169
1170static bool
1171aarch64_execute_dwarf_cfa_vendor_op (struct gdbarch *gdbarch, gdb_byte op,
1172 struct dwarf2_frame_state *fs)
1173{
1174 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1175 struct dwarf2_frame_state_reg *ra_state;
1176
8fca4da0 1177 if (op == DW_CFA_AARCH64_negate_ra_state)
11e1b75f 1178 {
8fca4da0
AH		 1179 /* On systems without pauth, treat as a nop. */
1180 if (!tdep->has_pauth ())
1181 return true;
1182
11e1b75f
AH		 1183 /* Allocate RA_STATE column if it's not allocated yet. */
1184 fs->regs.alloc_regs (AARCH64_DWARF_PAUTH_RA_STATE + 1);
1185
1186 /* Toggle the status of RA_STATE between 0 and 1. */
1187 ra_state = &(fs->regs.reg[AARCH64_DWARF_PAUTH_RA_STATE]);
1188 ra_state->how = DWARF2_FRAME_REG_SAVED_VAL_EXP;
1189
1190 if (ra_state->loc.exp.start == nullptr
1191 || ra_state->loc.exp.start == &op_lit0)
1192 ra_state->loc.exp.start = &op_lit1;
1193 else
1194 ra_state->loc.exp.start = &op_lit0;
1195
1196 ra_state->loc.exp.len = 1;
1197
1198 return true;
1199 }
1200
1201 return false;
1202}
1203
07b287a0
MS		 1204/* When arguments must be pushed onto the stack, they go on in reverse
1205 order. The code below implements a FILO (stack) to do this. */
1206
89055eaa 1207struct stack_item_t
07b287a0 1208{
c3c87445
YQ		 1209 /* Value to pass on stack. It can be NULL if this item is for stack
1210 padding. */
7c543f7b 1211 const gdb_byte *data;
07b287a0
MS		 1212
1213 /* Size in bytes of value to pass on stack. */
1214 int len;
89055eaa 1215};
07b287a0 1216
b907456c
AB		 1217/* Implement the gdbarch type alignment method, overrides the generic
1218 alignment algorithm for anything that is aarch64 specific. */
07b287a0 1219
b907456c
AB		 1220static ULONGEST
1221aarch64_type_align (gdbarch *gdbarch, struct type *t)
07b287a0 1222{
07b287a0 1223 t = check_typedef (t);
b907456c 1224 if (TYPE_CODE (t) == TYPE_CODE_ARRAY && TYPE_VECTOR (t))
07b287a0 1225 {
b907456c
AB		 1226 /* Use the natural alignment for vector types (the same for
1227 scalar type), but the maximum alignment is 128-bit. */
1228 if (TYPE_LENGTH (t) > 16)
1229 return 16;
238f2452 1230 else
b907456c 1231 return TYPE_LENGTH (t);
07b287a0 1232 }
b907456c
AB		 1233
1234 /* Allow the common code to calculate the alignment. */
1235 return 0;
07b287a0
MS		 1236}
1237
ea92689a
AH		 1238/* Worker function for aapcs_is_vfp_call_or_return_candidate.
1239
1240 Return the number of register required, or -1 on failure.
1241
1242 When encountering a base element, if FUNDAMENTAL_TYPE is not set then set it
1243 to the element, else fail if the type of this element does not match the
1244 existing value. */
1245
1246static int
1247aapcs_is_vfp_call_or_return_candidate_1 (struct type *type,
1248 struct type **fundamental_type)
1249{
1250 if (type == nullptr)
1251 return -1;
1252
1253 switch (TYPE_CODE (type))
1254 {
1255 case TYPE_CODE_FLT:
1256 if (TYPE_LENGTH (type) > 16)
1257 return -1;
1258
1259 if (*fundamental_type == nullptr)
1260 *fundamental_type = type;
1261 else if (TYPE_LENGTH (type) != TYPE_LENGTH (*fundamental_type)
1262 || TYPE_CODE (type) != TYPE_CODE (*fundamental_type))
1263 return -1;
1264
1265 return 1;
1266
1267 case TYPE_CODE_COMPLEX:
1268 {
1269 struct type *target_type = check_typedef (TYPE_TARGET_TYPE (type));
1270 if (TYPE_LENGTH (target_type) > 16)
1271 return -1;
1272
1273 if (*fundamental_type == nullptr)
1274 *fundamental_type = target_type;
1275 else if (TYPE_LENGTH (target_type) != TYPE_LENGTH (*fundamental_type)
1276 || TYPE_CODE (target_type) != TYPE_CODE (*fundamental_type))
1277 return -1;
1278
1279 return 2;
1280 }
1281
1282 case TYPE_CODE_ARRAY:
1283 {
1284 if (TYPE_VECTOR (type))
1285 {
1286 if (TYPE_LENGTH (type) != 8 && TYPE_LENGTH (type) != 16)
1287 return -1;
1288
1289 if (*fundamental_type == nullptr)
1290 *fundamental_type = type;
1291 else if (TYPE_LENGTH (type) != TYPE_LENGTH (*fundamental_type)
1292 || TYPE_CODE (type) != TYPE_CODE (*fundamental_type))
1293 return -1;
1294
1295 return 1;
1296 }
1297 else
1298 {
1299 struct type *target_type = TYPE_TARGET_TYPE (type);
1300 int count = aapcs_is_vfp_call_or_return_candidate_1
1301 (target_type, fundamental_type);
1302
1303 if (count == -1)
1304 return count;
1305
d4718d5c 1306 count *= (TYPE_LENGTH (type) / TYPE_LENGTH (target_type));
ea92689a
AH		 1307 return count;
1308 }
1309 }
1310
1311 case TYPE_CODE_STRUCT:
1312 case TYPE_CODE_UNION:
1313 {
1314 int count = 0;
1315
1316 for (int i = 0; i < TYPE_NFIELDS (type); i++)
1317 {
353229bf
AH		 1318 /* Ignore any static fields. */
1319 if (field_is_static (&TYPE_FIELD (type, i)))
1320 continue;
1321
ea92689a
AH		 1322 struct type *member = check_typedef (TYPE_FIELD_TYPE (type, i));
1323
1324 int sub_count = aapcs_is_vfp_call_or_return_candidate_1
1325 (member, fundamental_type);
1326 if (sub_count == -1)
1327 return -1;
1328 count += sub_count;
1329 }
73021deb
AH		 1330
1331 /* Ensure there is no padding between the fields (allowing for empty
1332 zero length structs) */
1333 int ftype_length = (*fundamental_type == nullptr)
1334 ? 0 : TYPE_LENGTH (*fundamental_type);
1335 if (count * ftype_length != TYPE_LENGTH (type))
1336 return -1;
1337
ea92689a
AH		 1338 return count;
1339 }
1340
1341 default:
1342 break;
1343 }
1344
1345 return -1;
1346}
1347
1348/* Return true if an argument, whose type is described by TYPE, can be passed or
1349 returned in simd/fp registers, providing enough parameter passing registers
1350 are available. This is as described in the AAPCS64.
1351
1352 Upon successful return, *COUNT returns the number of needed registers,
1353 *FUNDAMENTAL_TYPE contains the type of those registers.
1354
1355 Candidate as per the AAPCS64 5.4.2.C is either a:
1356 - float.
1357 - short-vector.
1358 - HFA (Homogeneous Floating-point Aggregate, 4.3.5.1). A Composite type where
1359 all the members are floats and has at most 4 members.
1360 - HVA (Homogeneous Short-vector Aggregate, 4.3.5.2). A Composite type where
1361 all the members are short vectors and has at most 4 members.
1362 - Complex (7.1.1)
1363
1364 Note that HFAs and HVAs can include nested structures and arrays. */
1365
0e745c60 1366static bool
ea92689a
AH		 1367aapcs_is_vfp_call_or_return_candidate (struct type *type, int *count,
1368 struct type **fundamental_type)
1369{
1370 if (type == nullptr)
1371 return false;
1372
1373 *fundamental_type = nullptr;
1374
1375 int ag_count = aapcs_is_vfp_call_or_return_candidate_1 (type,
1376 fundamental_type);
1377
1378 if (ag_count > 0 && ag_count <= HA_MAX_NUM_FLDS)
1379 {
1380 *count = ag_count;
1381 return true;
1382 }
1383 else
1384 return false;
1385}
1386
07b287a0
MS		 1387/* AArch64 function call information structure. */
1388struct aarch64_call_info
1389{
1390 /* the current argument number. */
89055eaa 1391 unsigned argnum = 0;
07b287a0
MS		 1392
1393 /* The next general purpose register number, equivalent to NGRN as
1394 described in the AArch64 Procedure Call Standard. */
89055eaa 1395 unsigned ngrn = 0;
07b287a0
MS		 1396
1397 /* The next SIMD and floating point register number, equivalent to
1398 NSRN as described in the AArch64 Procedure Call Standard. */
89055eaa 1399 unsigned nsrn = 0;
07b287a0
MS		 1400
1401 /* The next stacked argument address, equivalent to NSAA as
1402 described in the AArch64 Procedure Call Standard. */
89055eaa 1403 unsigned nsaa = 0;
07b287a0
MS		 1404
1405 /* Stack item vector. */
89055eaa 1406 std::vector<stack_item_t> si;
07b287a0
MS		 1407};
1408
1409/* Pass a value in a sequence of consecutive X registers. The caller
30baf67b 1410 is responsible for ensuring sufficient registers are available. */
07b287a0
MS		 1411
1412static void
1413pass_in_x (struct gdbarch *gdbarch, struct regcache *regcache,
1414 struct aarch64_call_info *info, struct type *type,
8e80f9d1 1415 struct value *arg)
07b287a0
MS		 1416{
1417 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1418 int len = TYPE_LENGTH (type);
1419 enum type_code typecode = TYPE_CODE (type);
1420 int regnum = AARCH64_X0_REGNUM + info->ngrn;
8e80f9d1 1421 const bfd_byte *buf = value_contents (arg);
07b287a0
MS		 1422
1423 info->argnum++;
1424
1425 while (len > 0)
1426 {
1427 int partial_len = len < X_REGISTER_SIZE ? len : X_REGISTER_SIZE;
1428 CORE_ADDR regval = extract_unsigned_integer (buf, partial_len,
1429 byte_order);
1430
1431
1432 /* Adjust sub-word struct/union args when big-endian. */
1433 if (byte_order == BFD_ENDIAN_BIG
1434 && partial_len < X_REGISTER_SIZE
1435 && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION))
1436 regval <<= ((X_REGISTER_SIZE - partial_len) * TARGET_CHAR_BIT);
1437
1438 if (aarch64_debug)
b277c936
PL		 1439 {
1440 debug_printf ("arg %d in %s = 0x%s\n", info->argnum,
1441 gdbarch_register_name (gdbarch, regnum),
1442 phex (regval, X_REGISTER_SIZE));
1443 }
07b287a0
MS		 1444 regcache_cooked_write_unsigned (regcache, regnum, regval);
1445 len -= partial_len;
1446 buf += partial_len;
1447 regnum++;
1448 }
1449}
1450
1451/* Attempt to marshall a value in a V register. Return 1 if
1452 successful, or 0 if insufficient registers are available. This
1453 function, unlike the equivalent pass_in_x() function does not
1454 handle arguments spread across multiple registers. */
1455
1456static int
1457pass_in_v (struct gdbarch *gdbarch,
1458 struct regcache *regcache,
1459 struct aarch64_call_info *info,
0735fddd 1460 int len, const bfd_byte *buf)
07b287a0
MS		 1461{
1462 if (info->nsrn < 8)
1463 {
07b287a0 1464 int regnum = AARCH64_V0_REGNUM + info->nsrn;
3ff2c72e
AH		 1465 /* Enough space for a full vector register. */
1466 gdb_byte reg[register_size (gdbarch, regnum)];
1467 gdb_assert (len <= sizeof (reg));
07b287a0
MS		 1468
1469 info->argnum++;
1470 info->nsrn++;
1471
0735fddd
YQ		 1472 memset (reg, 0, sizeof (reg));
1473 /* PCS C.1, the argument is allocated to the least significant
1474 bits of V register. */
1475 memcpy (reg, buf, len);
b66f5587 1476 regcache->cooked_write (regnum, reg);
0735fddd 1477
07b287a0 1478 if (aarch64_debug)
b277c936
PL		 1479 {
1480 debug_printf ("arg %d in %s\n", info->argnum,
1481 gdbarch_register_name (gdbarch, regnum));
1482 }
07b287a0
MS		 1483 return 1;
1484 }
1485 info->nsrn = 8;
1486 return 0;
1487}
1488
1489/* Marshall an argument onto the stack. */
1490
1491static void
1492pass_on_stack (struct aarch64_call_info *info, struct type *type,
8e80f9d1 1493 struct value *arg)
07b287a0 1494{
8e80f9d1 1495 const bfd_byte *buf = value_contents (arg);
07b287a0
MS		 1496 int len = TYPE_LENGTH (type);
1497 int align;
1498 stack_item_t item;
1499
1500 info->argnum++;
1501
b907456c 1502 align = type_align (type);
07b287a0
MS		 1503
1504 /* PCS C.17 Stack should be aligned to the larger of 8 bytes or the
1505 Natural alignment of the argument's type. */
1506 align = align_up (align, 8);
1507
1508 /* The AArch64 PCS requires at most doubleword alignment. */
1509 if (align > 16)
1510 align = 16;
1511
1512 if (aarch64_debug)
b277c936
PL		 1513 {
1514 debug_printf ("arg %d len=%d @ sp + %d\n", info->argnum, len,
1515 info->nsaa);
1516 }
07b287a0
MS		 1517
1518 item.len = len;
1519 item.data = buf;
89055eaa 1520 info->si.push_back (item);
07b287a0
MS		 1521
1522 info->nsaa += len;
1523 if (info->nsaa & (align - 1))
1524 {
1525 /* Push stack alignment padding. */
1526 int pad = align - (info->nsaa & (align - 1));
1527
1528 item.len = pad;
c3c87445 1529 item.data = NULL;
07b287a0 1530
89055eaa 1531 info->si.push_back (item);
07b287a0
MS		 1532 info->nsaa += pad;
1533 }
1534}
1535
1536/* Marshall an argument into a sequence of one or more consecutive X
1537 registers or, if insufficient X registers are available then onto
1538 the stack. */
1539
1540static void
1541pass_in_x_or_stack (struct gdbarch *gdbarch, struct regcache *regcache,
1542 struct aarch64_call_info *info, struct type *type,
8e80f9d1 1543 struct value *arg)
07b287a0
MS		 1544{
1545 int len = TYPE_LENGTH (type);
1546 int nregs = (len + X_REGISTER_SIZE - 1) / X_REGISTER_SIZE;
1547
1548 /* PCS C.13 - Pass in registers if we have enough spare */
1549 if (info->ngrn + nregs <= 8)
1550 {
8e80f9d1 1551 pass_in_x (gdbarch, regcache, info, type, arg);
07b287a0
MS		 1552 info->ngrn += nregs;
1553 }
1554 else
1555 {
1556 info->ngrn = 8;
8e80f9d1 1557 pass_on_stack (info, type, arg);
07b287a0
MS		 1558 }
1559}
1560
0e745c60
AH		 1561/* Pass a value, which is of type arg_type, in a V register. Assumes value is a
1562 aapcs_is_vfp_call_or_return_candidate and there are enough spare V
1563 registers. A return value of false is an error state as the value will have
1564 been partially passed to the stack. */
1565static bool
1566pass_in_v_vfp_candidate (struct gdbarch *gdbarch, struct regcache *regcache,
1567 struct aarch64_call_info *info, struct type *arg_type,
1568 struct value *arg)
07b287a0 1569{
0e745c60
AH		 1570 switch (TYPE_CODE (arg_type))
1571 {
1572 case TYPE_CODE_FLT:
1573 return pass_in_v (gdbarch, regcache, info, TYPE_LENGTH (arg_type),
1574 value_contents (arg));
1575 break;
1576
1577 case TYPE_CODE_COMPLEX:
1578 {
1579 const bfd_byte *buf = value_contents (arg);
1580 struct type *target_type = check_typedef (TYPE_TARGET_TYPE (arg_type));
1581
1582 if (!pass_in_v (gdbarch, regcache, info, TYPE_LENGTH (target_type),
1583 buf))
1584 return false;
1585
1586 return pass_in_v (gdbarch, regcache, info, TYPE_LENGTH (target_type),
1587 buf + TYPE_LENGTH (target_type));
1588 }
1589
1590 case TYPE_CODE_ARRAY:
1591 if (TYPE_VECTOR (arg_type))
1592 return pass_in_v (gdbarch, regcache, info, TYPE_LENGTH (arg_type),
1593 value_contents (arg));
1594 /* fall through. */
1595
1596 case TYPE_CODE_STRUCT:
1597 case TYPE_CODE_UNION:
1598 for (int i = 0; i < TYPE_NFIELDS (arg_type); i++)
1599 {
353229bf
AH		 1600 /* Don't include static fields. */
1601 if (field_is_static (&TYPE_FIELD (arg_type, i)))
1602 continue;
1603
0e745c60
AH		 1604 struct value *field = value_primitive_field (arg, 0, i, arg_type);
1605 struct type *field_type = check_typedef (value_type (field));
1606
1607 if (!pass_in_v_vfp_candidate (gdbarch, regcache, info, field_type,
1608 field))
1609 return false;
1610 }
1611 return true;
1612
1613 default:
1614 return false;
1615 }
07b287a0
MS		 1616}
1617
1618/* Implement the "push_dummy_call" gdbarch method. */
1619
1620static CORE_ADDR
1621aarch64_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
1622 struct regcache *regcache, CORE_ADDR bp_addr,
1623 int nargs,
cf84fa6b
AH		 1624 struct value **args, CORE_ADDR sp,
1625 function_call_return_method return_method,
07b287a0
MS		 1626 CORE_ADDR struct_addr)
1627{
07b287a0 1628 int argnum;
07b287a0 1629 struct aarch64_call_info info;
07b287a0 1630
07b287a0
MS		 1631 /* We need to know what the type of the called function is in order
1632 to determine the number of named/anonymous arguments for the
1633 actual argument placement, and the return type in order to handle
1634 return value correctly.
1635
1636 The generic code above us views the decision of return in memory
1637 or return in registers as a two stage processes. The language
1638 handler is consulted first and may decide to return in memory (eg
1639 class with copy constructor returned by value), this will cause
1640 the generic code to allocate space AND insert an initial leading
1641 argument.
1642
1643 If the language code does not decide to pass in memory then the
1644 target code is consulted.
1645
1646 If the language code decides to pass in memory we want to move
1647 the pointer inserted as the initial argument from the argument
1648 list and into X8, the conventional AArch64 struct return pointer
38a72da0 1649 register. */
07b287a0
MS		 1650
1651 /* Set the return address. For the AArch64, the return breakpoint
1652 is always at BP_ADDR. */
1653 regcache_cooked_write_unsigned (regcache, AARCH64_LR_REGNUM, bp_addr);
1654
38a72da0
AH		 1655 /* If we were given an initial argument for the return slot, lose it. */
1656 if (return_method == return_method_hidden_param)
07b287a0
MS		 1657 {
1658 args++;
1659 nargs--;
1660 }
1661
1662 /* The struct_return pointer occupies X8. */
38a72da0 1663 if (return_method != return_method_normal)
07b287a0
MS		 1664 {
1665 if (aarch64_debug)
b277c936
PL		 1666 {
1667 debug_printf ("struct return in %s = 0x%s\n",
1668 gdbarch_register_name (gdbarch,
1669 AARCH64_STRUCT_RETURN_REGNUM),
1670 paddress (gdbarch, struct_addr));
1671 }
07b287a0
MS		 1672 regcache_cooked_write_unsigned (regcache, AARCH64_STRUCT_RETURN_REGNUM,
1673 struct_addr);
1674 }
1675
1676 for (argnum = 0; argnum < nargs; argnum++)
1677 {
1678 struct value *arg = args[argnum];
0e745c60
AH		 1679 struct type *arg_type, *fundamental_type;
1680 int len, elements;
07b287a0
MS		 1681
1682 arg_type = check_typedef (value_type (arg));
1683 len = TYPE_LENGTH (arg_type);
1684
0e745c60
AH		 1685 /* If arg can be passed in v registers as per the AAPCS64, then do so if
1686 if there are enough spare registers. */
1687 if (aapcs_is_vfp_call_or_return_candidate (arg_type, &elements,
1688 &fundamental_type))
1689 {
1690 if (info.nsrn + elements <= 8)
1691 {
1692 /* We know that we have sufficient registers available therefore
1693 this will never need to fallback to the stack. */
1694 if (!pass_in_v_vfp_candidate (gdbarch, regcache, &info, arg_type,
1695 arg))
1696 gdb_assert_not_reached ("Failed to push args");
1697 }
1698 else
1699 {
1700 info.nsrn = 8;
1701 pass_on_stack (&info, arg_type, arg);
1702 }
1703 continue;
1704 }
1705
07b287a0
MS		 1706 switch (TYPE_CODE (arg_type))
1707 {
1708 case TYPE_CODE_INT:
1709 case TYPE_CODE_BOOL:
1710 case TYPE_CODE_CHAR:
1711 case TYPE_CODE_RANGE:
1712 case TYPE_CODE_ENUM:
1713 if (len < 4)
1714 {
1715 /* Promote to 32 bit integer. */
1716 if (TYPE_UNSIGNED (arg_type))
1717 arg_type = builtin_type (gdbarch)->builtin_uint32;
1718 else
1719 arg_type = builtin_type (gdbarch)->builtin_int32;
1720 arg = value_cast (arg_type, arg);
1721 }
8e80f9d1 1722 pass_in_x_or_stack (gdbarch, regcache, &info, arg_type, arg);
07b287a0
MS		 1723 break;
1724
07b287a0
MS		 1725 case TYPE_CODE_STRUCT:
1726 case TYPE_CODE_ARRAY:
1727 case TYPE_CODE_UNION:
0e745c60 1728 if (len > 16)
07b287a0
MS		 1729 {
1730 /* PCS B.7 Aggregates larger than 16 bytes are passed by
1731 invisible reference. */
1732
1733 /* Allocate aligned storage. */
1734 sp = align_down (sp - len, 16);
1735
1736 /* Write the real data into the stack. */
1737 write_memory (sp, value_contents (arg), len);
1738
1739 /* Construct the indirection. */
1740 arg_type = lookup_pointer_type (arg_type);
1741 arg = value_from_pointer (arg_type, sp);
8e80f9d1 1742 pass_in_x_or_stack (gdbarch, regcache, &info, arg_type, arg);
07b287a0
MS		 1743 }
1744 else
1745 /* PCS C.15 / C.18 multiple values pass. */
8e80f9d1 1746 pass_in_x_or_stack (gdbarch, regcache, &info, arg_type, arg);
07b287a0
MS		 1747 break;
1748
1749 default:
8e80f9d1 1750 pass_in_x_or_stack (gdbarch, regcache, &info, arg_type, arg);
07b287a0
MS		 1751 break;
1752 }
1753 }
1754
1755 /* Make sure stack retains 16 byte alignment. */
1756 if (info.nsaa & 15)
1757 sp -= 16 - (info.nsaa & 15);
1758
89055eaa 1759 while (!info.si.empty ())
07b287a0 1760 {
89055eaa 1761 const stack_item_t &si = info.si.back ();
07b287a0 1762
89055eaa
TT		 1763 sp -= si.len;
1764 if (si.data != NULL)
1765 write_memory (sp, si.data, si.len);
1766 info.si.pop_back ();
07b287a0
MS		 1767 }
1768
07b287a0
MS		 1769 /* Finally, update the SP register. */
1770 regcache_cooked_write_unsigned (regcache, AARCH64_SP_REGNUM, sp);
1771
1772 return sp;
1773}
1774
1775/* Implement the "frame_align" gdbarch method. */
1776
1777static CORE_ADDR
1778aarch64_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
1779{
1780 /* Align the stack to sixteen bytes. */
1781 return sp & ~(CORE_ADDR) 15;
1782}
1783
1784/* Return the type for an AdvSISD Q register. */
1785
1786static struct type *
1787aarch64_vnq_type (struct gdbarch *gdbarch)
1788{
1789 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1790
1791 if (tdep->vnq_type == NULL)
1792 {
1793 struct type *t;
1794 struct type *elem;
1795
1796 t = arch_composite_type (gdbarch, "__gdb_builtin_type_vnq",
1797 TYPE_CODE_UNION);
1798
1799 elem = builtin_type (gdbarch)->builtin_uint128;
1800 append_composite_type_field (t, "u", elem);
1801
1802 elem = builtin_type (gdbarch)->builtin_int128;
1803 append_composite_type_field (t, "s", elem);
1804
1805 tdep->vnq_type = t;
1806 }
1807
1808 return tdep->vnq_type;
1809}
1810
1811/* Return the type for an AdvSISD D register. */
1812
1813static struct type *
1814aarch64_vnd_type (struct gdbarch *gdbarch)
1815{
1816 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1817
1818 if (tdep->vnd_type == NULL)
1819 {
1820 struct type *t;
1821 struct type *elem;
1822
1823 t = arch_composite_type (gdbarch, "__gdb_builtin_type_vnd",
1824 TYPE_CODE_UNION);
1825
1826 elem = builtin_type (gdbarch)->builtin_double;
1827 append_composite_type_field (t, "f", elem);
1828
1829 elem = builtin_type (gdbarch)->builtin_uint64;
1830 append_composite_type_field (t, "u", elem);
1831
1832 elem = builtin_type (gdbarch)->builtin_int64;
1833 append_composite_type_field (t, "s", elem);
1834
1835 tdep->vnd_type = t;
1836 }
1837
1838 return tdep->vnd_type;
1839}
1840
1841/* Return the type for an AdvSISD S register. */
1842
1843static struct type *
1844aarch64_vns_type (struct gdbarch *gdbarch)
1845{
1846 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1847
1848 if (tdep->vns_type == NULL)
1849 {
1850 struct type *t;
1851 struct type *elem;
1852
1853 t = arch_composite_type (gdbarch, "__gdb_builtin_type_vns",
1854 TYPE_CODE_UNION);
1855
1856 elem = builtin_type (gdbarch)->builtin_float;
1857 append_composite_type_field (t, "f", elem);
1858
1859 elem = builtin_type (gdbarch)->builtin_uint32;
1860 append_composite_type_field (t, "u", elem);
1861
1862 elem = builtin_type (gdbarch)->builtin_int32;
1863 append_composite_type_field (t, "s", elem);
1864
1865 tdep->vns_type = t;
1866 }
1867
1868 return tdep->vns_type;
1869}
1870
1871/* Return the type for an AdvSISD H register. */
1872
1873static struct type *
1874aarch64_vnh_type (struct gdbarch *gdbarch)
1875{
1876 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1877
1878 if (tdep->vnh_type == NULL)
1879 {
1880 struct type *t;
1881 struct type *elem;
1882
1883 t = arch_composite_type (gdbarch, "__gdb_builtin_type_vnh",
1884 TYPE_CODE_UNION);
1885
a6d0f249
AH		 1886 elem = builtin_type (gdbarch)->builtin_half;
1887 append_composite_type_field (t, "f", elem);
1888
07b287a0
MS		 1889 elem = builtin_type (gdbarch)->builtin_uint16;
1890 append_composite_type_field (t, "u", elem);
1891
1892 elem = builtin_type (gdbarch)->builtin_int16;
1893 append_composite_type_field (t, "s", elem);
1894
1895 tdep->vnh_type = t;
1896 }
1897
1898 return tdep->vnh_type;
1899}
1900
1901/* Return the type for an AdvSISD B register. */
1902
1903static struct type *
1904aarch64_vnb_type (struct gdbarch *gdbarch)
1905{
1906 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1907
1908 if (tdep->vnb_type == NULL)
1909 {
1910 struct type *t;
1911 struct type *elem;
1912
1913 t = arch_composite_type (gdbarch, "__gdb_builtin_type_vnb",
1914 TYPE_CODE_UNION);
1915
1916 elem = builtin_type (gdbarch)->builtin_uint8;
1917 append_composite_type_field (t, "u", elem);
1918
1919 elem = builtin_type (gdbarch)->builtin_int8;
1920 append_composite_type_field (t, "s", elem);
1921
1922 tdep->vnb_type = t;
1923 }
1924
1925 return tdep->vnb_type;
1926}
1927
63bad7b6
AH		 1928/* Return the type for an AdvSISD V register. */
1929
1930static struct type *
1931aarch64_vnv_type (struct gdbarch *gdbarch)
1932{
1933 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1934
1935 if (tdep->vnv_type == NULL)
1936 {
bffa1015
AH		 1937 /* The other AArch64 psuedo registers (Q,D,H,S,B) refer to a single value
1938 slice from the non-pseudo vector registers. However NEON V registers
1939 are always vector registers, and need constructing as such. */
1940 const struct builtin_type *bt = builtin_type (gdbarch);
1941
63bad7b6
AH		 1942 struct type *t = arch_composite_type (gdbarch, "__gdb_builtin_type_vnv",
1943 TYPE_CODE_UNION);
1944
bffa1015
AH		 1945 struct type *sub = arch_composite_type (gdbarch, "__gdb_builtin_type_vnd",
1946 TYPE_CODE_UNION);
1947 append_composite_type_field (sub, "f",
1948 init_vector_type (bt->builtin_double, 2));
1949 append_composite_type_field (sub, "u",
1950 init_vector_type (bt->builtin_uint64, 2));
1951 append_composite_type_field (sub, "s",
1952 init_vector_type (bt->builtin_int64, 2));
1953 append_composite_type_field (t, "d", sub);
1954
1955 sub = arch_composite_type (gdbarch, "__gdb_builtin_type_vns",
1956 TYPE_CODE_UNION);
1957 append_composite_type_field (sub, "f",
1958 init_vector_type (bt->builtin_float, 4));
1959 append_composite_type_field (sub, "u",
1960 init_vector_type (bt->builtin_uint32, 4));
1961 append_composite_type_field (sub, "s",
1962 init_vector_type (bt->builtin_int32, 4));
1963 append_composite_type_field (t, "s", sub);
1964
1965 sub = arch_composite_type (gdbarch, "__gdb_builtin_type_vnh",
1966 TYPE_CODE_UNION);
a6d0f249
AH		 1967 append_composite_type_field (sub, "f",
1968 init_vector_type (bt->builtin_half, 8));
bffa1015
AH		 1969 append_composite_type_field (sub, "u",
1970 init_vector_type (bt->builtin_uint16, 8));
1971 append_composite_type_field (sub, "s",
1972 init_vector_type (bt->builtin_int16, 8));
1973 append_composite_type_field (t, "h", sub);
1974
1975 sub = arch_composite_type (gdbarch, "__gdb_builtin_type_vnb",
1976 TYPE_CODE_UNION);
1977 append_composite_type_field (sub, "u",
1978 init_vector_type (bt->builtin_uint8, 16));
1979 append_composite_type_field (sub, "s",
1980 init_vector_type (bt->builtin_int8, 16));
1981 append_composite_type_field (t, "b", sub);
1982
1983 sub = arch_composite_type (gdbarch, "__gdb_builtin_type_vnq",
1984 TYPE_CODE_UNION);
1985 append_composite_type_field (sub, "u",
1986 init_vector_type (bt->builtin_uint128, 1));
1987 append_composite_type_field (sub, "s",
1988 init_vector_type (bt->builtin_int128, 1));
1989 append_composite_type_field (t, "q", sub);
63bad7b6
AH		 1990
1991 tdep->vnv_type = t;
1992 }
1993
1994 return tdep->vnv_type;
1995}
1996
07b287a0
MS		 1997/* Implement the "dwarf2_reg_to_regnum" gdbarch method. */
1998
1999static int
2000aarch64_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg)
2001{
34dcc7cf
AH		 2002 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2003
07b287a0
MS		 2004 if (reg >= AARCH64_DWARF_X0 && reg <= AARCH64_DWARF_X0 + 30)
2005 return AARCH64_X0_REGNUM + reg - AARCH64_DWARF_X0;
2006
2007 if (reg == AARCH64_DWARF_SP)
2008 return AARCH64_SP_REGNUM;
2009
2010 if (reg >= AARCH64_DWARF_V0 && reg <= AARCH64_DWARF_V0 + 31)
2011 return AARCH64_V0_REGNUM + reg - AARCH64_DWARF_V0;
2012
65d4cada
AH		 2013 if (reg == AARCH64_DWARF_SVE_VG)
2014 return AARCH64_SVE_VG_REGNUM;
2015
2016 if (reg == AARCH64_DWARF_SVE_FFR)
2017 return AARCH64_SVE_FFR_REGNUM;
2018
2019 if (reg >= AARCH64_DWARF_SVE_P0 && reg <= AARCH64_DWARF_SVE_P0 + 15)
2020 return AARCH64_SVE_P0_REGNUM + reg - AARCH64_DWARF_SVE_P0;
2021
2022 if (reg >= AARCH64_DWARF_SVE_Z0 && reg <= AARCH64_DWARF_SVE_Z0 + 15)
2023 return AARCH64_SVE_Z0_REGNUM + reg - AARCH64_DWARF_SVE_Z0;
2024
34dcc7cf
AH		 2025 if (tdep->has_pauth ())
2026 {
2027 if (reg >= AARCH64_DWARF_PAUTH_DMASK && reg <= AARCH64_DWARF_PAUTH_CMASK)
2028 return tdep->pauth_reg_base + reg - AARCH64_DWARF_PAUTH_DMASK;
2029
2030 if (reg == AARCH64_DWARF_PAUTH_RA_STATE)
2031 return tdep->pauth_ra_state_regnum;
2032 }
2033
07b287a0
MS		 2034 return -1;
2035}
07b287a0
MS		 2036
2037/* Implement the "print_insn" gdbarch method. */
2038
2039static int
2040aarch64_gdb_print_insn (bfd_vma memaddr, disassemble_info *info)
2041{
2042 info->symbols = NULL;
6394c606 2043 return default_print_insn (memaddr, info);
07b287a0
MS		 2044}
2045
2046/* AArch64 BRK software debug mode instruction.
2047 Note that AArch64 code is always little-endian.
2048 1101.0100.0010.0000.0000.0000.0000.0000 = 0xd4200000. */
04180708 2049constexpr gdb_byte aarch64_default_breakpoint[] = {0x00, 0x00, 0x20, 0xd4};
07b287a0 2050
04180708 2051typedef BP_MANIPULATION (aarch64_default_breakpoint) aarch64_breakpoint;
07b287a0
MS		 2052
2053/* Extract from an array REGS containing the (raw) register state a
2054 function return value of type TYPE, and copy that, in virtual
2055 format, into VALBUF. */
2056
2057static void
2058aarch64_extract_return_value (struct type *type, struct regcache *regs,
2059 gdb_byte *valbuf)
2060{
ac7936df 2061 struct gdbarch *gdbarch = regs->arch ();
07b287a0 2062 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
4f4aedeb
AH		 2063 int elements;
2064 struct type *fundamental_type;
07b287a0 2065
4f4aedeb
AH		 2066 if (aapcs_is_vfp_call_or_return_candidate (type, &elements,
2067 &fundamental_type))
07b287a0 2068 {
4f4aedeb
AH		 2069 int len = TYPE_LENGTH (fundamental_type);
2070
2071 for (int i = 0; i < elements; i++)
2072 {
2073 int regno = AARCH64_V0_REGNUM + i;
3ff2c72e
AH		 2074 /* Enough space for a full vector register. */
2075 gdb_byte buf[register_size (gdbarch, regno)];
2076 gdb_assert (len <= sizeof (buf));
4f4aedeb
AH		 2077
2078 if (aarch64_debug)
2079 {
2080 debug_printf ("read HFA or HVA return value element %d from %s\n",
2081 i + 1,
2082 gdbarch_register_name (gdbarch, regno));
2083 }
2084 regs->cooked_read (regno, buf);
07b287a0 2085
4f4aedeb
AH		 2086 memcpy (valbuf, buf, len);
2087 valbuf += len;
2088 }
07b287a0
MS		 2089 }
2090 else if (TYPE_CODE (type) == TYPE_CODE_INT
2091 || TYPE_CODE (type) == TYPE_CODE_CHAR
2092 || TYPE_CODE (type) == TYPE_CODE_BOOL
2093 || TYPE_CODE (type) == TYPE_CODE_PTR
aa006118 2094 || TYPE_IS_REFERENCE (type)
07b287a0
MS		 2095 || TYPE_CODE (type) == TYPE_CODE_ENUM)
2096 {
6471e7d2 2097 /* If the type is a plain integer, then the access is
07b287a0
MS		 2098 straight-forward. Otherwise we have to play around a bit
2099 more. */
2100 int len = TYPE_LENGTH (type);
2101 int regno = AARCH64_X0_REGNUM;
2102 ULONGEST tmp;
2103
2104 while (len > 0)
2105 {
2106 /* By using store_unsigned_integer we avoid having to do
2107 anything special for small big-endian values. */
2108 regcache_cooked_read_unsigned (regs, regno++, &tmp);
2109 store_unsigned_integer (valbuf,
2110 (len > X_REGISTER_SIZE
2111 ? X_REGISTER_SIZE : len), byte_order, tmp);
2112 len -= X_REGISTER_SIZE;
2113 valbuf += X_REGISTER_SIZE;
2114 }
2115 }
07b287a0
MS		 2116 else
2117 {
2118 /* For a structure or union the behaviour is as if the value had
2119 been stored to word-aligned memory and then loaded into
2120 registers with 64-bit load instruction(s). */
2121 int len = TYPE_LENGTH (type);
2122 int regno = AARCH64_X0_REGNUM;
2123 bfd_byte buf[X_REGISTER_SIZE];
2124
2125 while (len > 0)
2126 {
dca08e1f 2127 regs->cooked_read (regno++, buf);
07b287a0
MS		 2128 memcpy (valbuf, buf, len > X_REGISTER_SIZE ? X_REGISTER_SIZE : len);
2129 len -= X_REGISTER_SIZE;
2130 valbuf += X_REGISTER_SIZE;
2131 }
2132 }
2133}
2134
2135
2136/* Will a function return an aggregate type in memory or in a
2137 register? Return 0 if an aggregate type can be returned in a
2138 register, 1 if it must be returned in memory. */
2139
2140static int
2141aarch64_return_in_memory (struct gdbarch *gdbarch, struct type *type)
2142{
f168693b 2143 type = check_typedef (type);
4f4aedeb
AH		 2144 int elements;
2145 struct type *fundamental_type;
07b287a0 2146
4f4aedeb
AH		 2147 if (aapcs_is_vfp_call_or_return_candidate (type, &elements,
2148 &fundamental_type))
07b287a0 2149 {
cd635f74
YQ		 2150 /* v0-v7 are used to return values and one register is allocated
2151 for one member. However, HFA or HVA has at most four members. */
07b287a0
MS		 2152 return 0;
2153 }
2154
2155 if (TYPE_LENGTH (type) > 16)
2156 {
2157 /* PCS B.6 Aggregates larger than 16 bytes are passed by
2158 invisible reference. */
2159
2160 return 1;
2161 }
2162
2163 return 0;
2164}
2165
2166/* Write into appropriate registers a function return value of type
2167 TYPE, given in virtual format. */
2168
2169static void
2170aarch64_store_return_value (struct type *type, struct regcache *regs,
2171 const gdb_byte *valbuf)
2172{
ac7936df 2173 struct gdbarch *gdbarch = regs->arch ();
07b287a0 2174 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
4f4aedeb
AH		 2175 int elements;
2176 struct type *fundamental_type;
07b287a0 2177
4f4aedeb
AH		 2178 if (aapcs_is_vfp_call_or_return_candidate (type, &elements,
2179 &fundamental_type))
07b287a0 2180 {
4f4aedeb
AH		 2181 int len = TYPE_LENGTH (fundamental_type);
2182
2183 for (int i = 0; i < elements; i++)
2184 {
2185 int regno = AARCH64_V0_REGNUM + i;
3ff2c72e
AH		 2186 /* Enough space for a full vector register. */
2187 gdb_byte tmpbuf[register_size (gdbarch, regno)];
2188 gdb_assert (len <= sizeof (tmpbuf));
4f4aedeb
AH		 2189
2190 if (aarch64_debug)
2191 {
2192 debug_printf ("write HFA or HVA return value element %d to %s\n",
2193 i + 1,
2194 gdbarch_register_name (gdbarch, regno));
2195 }
07b287a0 2196
4f4aedeb
AH		 2197 memcpy (tmpbuf, valbuf,
2198 len > V_REGISTER_SIZE ? V_REGISTER_SIZE : len);
2199 regs->cooked_write (regno, tmpbuf);
2200 valbuf += len;
2201 }
07b287a0
MS		 2202 }
2203 else if (TYPE_CODE (type) == TYPE_CODE_INT
2204 || TYPE_CODE (type) == TYPE_CODE_CHAR
2205 || TYPE_CODE (type) == TYPE_CODE_BOOL
2206 || TYPE_CODE (type) == TYPE_CODE_PTR
aa006118 2207 || TYPE_IS_REFERENCE (type)
07b287a0
MS		 2208 || TYPE_CODE (type) == TYPE_CODE_ENUM)
2209 {
2210 if (TYPE_LENGTH (type) <= X_REGISTER_SIZE)
2211 {
2212 /* Values of one word or less are zero/sign-extended and
2213 returned in r0. */
2214 bfd_byte tmpbuf[X_REGISTER_SIZE];
2215 LONGEST val = unpack_long (type, valbuf);
2216
2217 store_signed_integer (tmpbuf, X_REGISTER_SIZE, byte_order, val);
b66f5587 2218 regs->cooked_write (AARCH64_X0_REGNUM, tmpbuf);
07b287a0
MS		 2219 }
2220 else
2221 {
2222 /* Integral values greater than one word are stored in
2223 consecutive registers starting with r0. This will always
2224 be a multiple of the regiser size. */
2225 int len = TYPE_LENGTH (type);
2226 int regno = AARCH64_X0_REGNUM;
2227
2228 while (len > 0)
2229 {
b66f5587 2230 regs->cooked_write (regno++, valbuf);
07b287a0
MS		 2231 len -= X_REGISTER_SIZE;
2232 valbuf += X_REGISTER_SIZE;
2233 }
2234 }
2235 }
07b287a0
MS		 2236 else
2237 {
2238 /* For a structure or union the behaviour is as if the value had
2239 been stored to word-aligned memory and then loaded into
2240 registers with 64-bit load instruction(s). */
2241 int len = TYPE_LENGTH (type);
2242 int regno = AARCH64_X0_REGNUM;
2243 bfd_byte tmpbuf[X_REGISTER_SIZE];
2244
2245 while (len > 0)
2246 {
2247 memcpy (tmpbuf, valbuf,
2248 len > X_REGISTER_SIZE ? X_REGISTER_SIZE : len);
b66f5587 2249 regs->cooked_write (regno++, tmpbuf);
07b287a0
MS		 2250 len -= X_REGISTER_SIZE;
2251 valbuf += X_REGISTER_SIZE;
2252 }
2253 }
2254}
2255
2256/* Implement the "return_value" gdbarch method. */
2257
2258static enum return_value_convention
2259aarch64_return_value (struct gdbarch *gdbarch, struct value *func_value,
2260 struct type *valtype, struct regcache *regcache,
2261 gdb_byte *readbuf, const gdb_byte *writebuf)
2262{
07b287a0
MS		 2263
2264 if (TYPE_CODE (valtype) == TYPE_CODE_STRUCT
2265 || TYPE_CODE (valtype) == TYPE_CODE_UNION
2266 || TYPE_CODE (valtype) == TYPE_CODE_ARRAY)
2267 {
2268 if (aarch64_return_in_memory (gdbarch, valtype))
2269 {
2270 if (aarch64_debug)
b277c936 2271 debug_printf ("return value in memory\n");
07b287a0
MS		 2272 return RETURN_VALUE_STRUCT_CONVENTION;
2273 }
2274 }
2275
2276 if (writebuf)
2277 aarch64_store_return_value (valtype, regcache, writebuf);
2278
2279 if (readbuf)
2280 aarch64_extract_return_value (valtype, regcache, readbuf);
2281
2282 if (aarch64_debug)
b277c936 2283 debug_printf ("return value in registers\n");
07b287a0
MS		 2284
2285 return RETURN_VALUE_REGISTER_CONVENTION;
2286}
2287
2288/* Implement the "get_longjmp_target" gdbarch method. */
2289
2290static int
2291aarch64_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc)
2292{
2293 CORE_ADDR jb_addr;
2294 gdb_byte buf[X_REGISTER_SIZE];
2295 struct gdbarch *gdbarch = get_frame_arch (frame);
2296 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2297 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2298
2299 jb_addr = get_frame_register_unsigned (frame, AARCH64_X0_REGNUM);
2300
2301 if (target_read_memory (jb_addr + tdep->jb_pc * tdep->jb_elt_size, buf,
2302 X_REGISTER_SIZE))
2303 return 0;
2304
2305 *pc = extract_unsigned_integer (buf, X_REGISTER_SIZE, byte_order);
2306 return 1;
2307}
ea873d8e
PL		 2308
2309/* Implement the "gen_return_address" gdbarch method. */
2310
2311static void
2312aarch64_gen_return_address (struct gdbarch *gdbarch,
2313 struct agent_expr *ax, struct axs_value *value,
2314 CORE_ADDR scope)
2315{
2316 value->type = register_type (gdbarch, AARCH64_LR_REGNUM);
2317 value->kind = axs_lvalue_register;
2318 value->u.reg = AARCH64_LR_REGNUM;
2319}
07b287a0
MS		 2320\f
2321
2322/* Return the pseudo register name corresponding to register regnum. */
2323
2324static const char *
2325aarch64_pseudo_register_name (struct gdbarch *gdbarch, int regnum)
2326{
63bad7b6
AH		 2327 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2328
07b287a0
MS		 2329 static const char *const q_name[] =
2330 {
2331 "q0", "q1", "q2", "q3",
2332 "q4", "q5", "q6", "q7",
2333 "q8", "q9", "q10", "q11",
2334 "q12", "q13", "q14", "q15",
2335 "q16", "q17", "q18", "q19",
2336 "q20", "q21", "q22", "q23",
2337 "q24", "q25", "q26", "q27",
2338 "q28", "q29", "q30", "q31",
2339 };
2340
2341 static const char *const d_name[] =
2342 {
2343 "d0", "d1", "d2", "d3",
2344 "d4", "d5", "d6", "d7",
2345 "d8", "d9", "d10", "d11",
2346 "d12", "d13", "d14", "d15",
2347 "d16", "d17", "d18", "d19",
2348 "d20", "d21", "d22", "d23",
2349 "d24", "d25", "d26", "d27",
2350 "d28", "d29", "d30", "d31",
2351 };
2352
2353 static const char *const s_name[] =
2354 {
2355 "s0", "s1", "s2", "s3",
2356 "s4", "s5", "s6", "s7",
2357 "s8", "s9", "s10", "s11",
2358 "s12", "s13", "s14", "s15",
2359 "s16", "s17", "s18", "s19",
2360 "s20", "s21", "s22", "s23",
2361 "s24", "s25", "s26", "s27",
2362 "s28", "s29", "s30", "s31",
2363 };
2364
2365 static const char *const h_name[] =
2366 {
2367 "h0", "h1", "h2", "h3",
2368 "h4", "h5", "h6", "h7",
2369 "h8", "h9", "h10", "h11",
2370 "h12", "h13", "h14", "h15",
2371 "h16", "h17", "h18", "h19",
2372 "h20", "h21", "h22", "h23",
2373 "h24", "h25", "h26", "h27",
2374 "h28", "h29", "h30", "h31",
2375 };
2376
2377 static const char *const b_name[] =
2378 {
2379 "b0", "b1", "b2", "b3",
2380 "b4", "b5", "b6", "b7",
2381 "b8", "b9", "b10", "b11",
2382 "b12", "b13", "b14", "b15",
2383 "b16", "b17", "b18", "b19",
2384 "b20", "b21", "b22", "b23",
2385 "b24", "b25", "b26", "b27",
2386 "b28", "b29", "b30", "b31",
2387 };
2388
34dcc7cf 2389 int p_regnum = regnum - gdbarch_num_regs (gdbarch);
07b287a0 2390
34dcc7cf
AH		 2391 if (p_regnum >= AARCH64_Q0_REGNUM && p_regnum < AARCH64_Q0_REGNUM + 32)
2392 return q_name[p_regnum - AARCH64_Q0_REGNUM];
07b287a0 2393
34dcc7cf
AH		 2394 if (p_regnum >= AARCH64_D0_REGNUM && p_regnum < AARCH64_D0_REGNUM + 32)
2395 return d_name[p_regnum - AARCH64_D0_REGNUM];
07b287a0 2396
34dcc7cf
AH		 2397 if (p_regnum >= AARCH64_S0_REGNUM && p_regnum < AARCH64_S0_REGNUM + 32)
2398 return s_name[p_regnum - AARCH64_S0_REGNUM];
07b287a0 2399
34dcc7cf
AH		 2400 if (p_regnum >= AARCH64_H0_REGNUM && p_regnum < AARCH64_H0_REGNUM + 32)
2401 return h_name[p_regnum - AARCH64_H0_REGNUM];
07b287a0 2402
34dcc7cf
AH		 2403 if (p_regnum >= AARCH64_B0_REGNUM && p_regnum < AARCH64_B0_REGNUM + 32)
2404 return b_name[p_regnum - AARCH64_B0_REGNUM];
07b287a0 2405
63bad7b6
AH		 2406 if (tdep->has_sve ())
2407 {
2408 static const char *const sve_v_name[] =
2409 {
2410 "v0", "v1", "v2", "v3",
2411 "v4", "v5", "v6", "v7",
2412 "v8", "v9", "v10", "v11",
2413 "v12", "v13", "v14", "v15",
2414 "v16", "v17", "v18", "v19",
2415 "v20", "v21", "v22", "v23",
2416 "v24", "v25", "v26", "v27",
2417 "v28", "v29", "v30", "v31",
2418 };
2419
34dcc7cf
AH		 2420 if (p_regnum >= AARCH64_SVE_V0_REGNUM
2421 && p_regnum < AARCH64_SVE_V0_REGNUM + AARCH64_V_REGS_NUM)
2422 return sve_v_name[p_regnum - AARCH64_SVE_V0_REGNUM];
63bad7b6
AH		 2423 }
2424
34dcc7cf
AH		 2425 /* RA_STATE is used for unwinding only. Do not assign it a name - this
2426 prevents it from being read by methods such as
2427 mi_cmd_trace_frame_collected. */
2428 if (tdep->has_pauth () && regnum == tdep->pauth_ra_state_regnum)
2429 return "";
2430
07b287a0
MS		 2431 internal_error (__FILE__, __LINE__,
2432 _("aarch64_pseudo_register_name: bad register number %d"),
34dcc7cf 2433 p_regnum);
07b287a0
MS		 2434}
2435
2436/* Implement the "pseudo_register_type" tdesc_arch_data method. */
2437
2438static struct type *
2439aarch64_pseudo_register_type (struct gdbarch *gdbarch, int regnum)
2440{
63bad7b6
AH		 2441 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2442
34dcc7cf 2443 int p_regnum = regnum - gdbarch_num_regs (gdbarch);
07b287a0 2444
34dcc7cf 2445 if (p_regnum >= AARCH64_Q0_REGNUM && p_regnum < AARCH64_Q0_REGNUM + 32)
07b287a0
MS		 2446 return aarch64_vnq_type (gdbarch);
2447
34dcc7cf 2448 if (p_regnum >= AARCH64_D0_REGNUM && p_regnum < AARCH64_D0_REGNUM + 32)
07b287a0
MS		 2449 return aarch64_vnd_type (gdbarch);
2450
34dcc7cf 2451 if (p_regnum >= AARCH64_S0_REGNUM && p_regnum < AARCH64_S0_REGNUM + 32)
07b287a0
MS		 2452 return aarch64_vns_type (gdbarch);
2453
34dcc7cf 2454 if (p_regnum >= AARCH64_H0_REGNUM && p_regnum < AARCH64_H0_REGNUM + 32)
07b287a0
MS		 2455 return aarch64_vnh_type (gdbarch);
2456
34dcc7cf 2457 if (p_regnum >= AARCH64_B0_REGNUM && p_regnum < AARCH64_B0_REGNUM + 32)
07b287a0
MS		 2458 return aarch64_vnb_type (gdbarch);
2459
34dcc7cf
AH		 2460 if (tdep->has_sve () && p_regnum >= AARCH64_SVE_V0_REGNUM
2461 && p_regnum < AARCH64_SVE_V0_REGNUM + AARCH64_V_REGS_NUM)
63bad7b6
AH		 2462 return aarch64_vnv_type (gdbarch);
2463
34dcc7cf
AH		 2464 if (tdep->has_pauth () && regnum == tdep->pauth_ra_state_regnum)
2465 return builtin_type (gdbarch)->builtin_uint64;
2466
07b287a0
MS		 2467 internal_error (__FILE__, __LINE__,
2468 _("aarch64_pseudo_register_type: bad register number %d"),
34dcc7cf 2469 p_regnum);
07b287a0
MS		 2470}
2471
2472/* Implement the "pseudo_register_reggroup_p" tdesc_arch_data method. */
2473
2474static int
2475aarch64_pseudo_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
2476 struct reggroup *group)
2477{
63bad7b6
AH		 2478 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2479
34dcc7cf 2480 int p_regnum = regnum - gdbarch_num_regs (gdbarch);
07b287a0 2481
34dcc7cf 2482 if (p_regnum >= AARCH64_Q0_REGNUM && p_regnum < AARCH64_Q0_REGNUM + 32)
07b287a0 2483 return group == all_reggroup || group == vector_reggroup;
34dcc7cf 2484 else if (p_regnum >= AARCH64_D0_REGNUM && p_regnum < AARCH64_D0_REGNUM + 32)
07b287a0
MS		 2485 return (group == all_reggroup || group == vector_reggroup
2486 || group == float_reggroup);
34dcc7cf 2487 else if (p_regnum >= AARCH64_S0_REGNUM && p_regnum < AARCH64_S0_REGNUM + 32)
07b287a0
MS		 2488 return (group == all_reggroup || group == vector_reggroup
2489 || group == float_reggroup);
34dcc7cf 2490 else if (p_regnum >= AARCH64_H0_REGNUM && p_regnum < AARCH64_H0_REGNUM + 32)
07b287a0 2491 return group == all_reggroup || group == vector_reggroup;
34dcc7cf 2492 else if (p_regnum >= AARCH64_B0_REGNUM && p_regnum < AARCH64_B0_REGNUM + 32)
07b287a0 2493 return group == all_reggroup || group == vector_reggroup;
34dcc7cf
AH		 2494 else if (tdep->has_sve () && p_regnum >= AARCH64_SVE_V0_REGNUM
2495 && p_regnum < AARCH64_SVE_V0_REGNUM + AARCH64_V_REGS_NUM)
63bad7b6 2496 return group == all_reggroup || group == vector_reggroup;
34dcc7cf
AH		 2497 /* RA_STATE is used for unwinding only. Do not assign it to any groups. */
2498 if (tdep->has_pauth () && regnum == tdep->pauth_ra_state_regnum)
2499 return 0;
07b287a0
MS		 2500
2501 return group == all_reggroup;
2502}
2503
3c5cd5c3
AH		 2504/* Helper for aarch64_pseudo_read_value. */
2505
2506static struct value *
63bad7b6
AH		 2507aarch64_pseudo_read_value_1 (struct gdbarch *gdbarch,
2508 readable_regcache *regcache, int regnum_offset,
3c5cd5c3
AH		 2509 int regsize, struct value *result_value)
2510{
3c5cd5c3
AH		 2511 unsigned v_regnum = AARCH64_V0_REGNUM + regnum_offset;
2512
63bad7b6
AH		 2513 /* Enough space for a full vector register. */
2514 gdb_byte reg_buf[register_size (gdbarch, AARCH64_V0_REGNUM)];
2515 gdb_static_assert (AARCH64_V0_REGNUM == AARCH64_SVE_Z0_REGNUM);
2516
3c5cd5c3
AH		 2517 if (regcache->raw_read (v_regnum, reg_buf) != REG_VALID)
2518 mark_value_bytes_unavailable (result_value, 0,
2519 TYPE_LENGTH (value_type (result_value)));
2520 else
2521 memcpy (value_contents_raw (result_value), reg_buf, regsize);
63bad7b6 2522
3c5cd5c3
AH		 2523 return result_value;
2524 }
2525
07b287a0
MS		 2526/* Implement the "pseudo_register_read_value" gdbarch method. */
2527
2528static struct value *
3c5cd5c3 2529aarch64_pseudo_read_value (struct gdbarch *gdbarch, readable_regcache *regcache,
07b287a0
MS		 2530 int regnum)
2531{
63bad7b6 2532 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3c5cd5c3 2533 struct value *result_value = allocate_value (register_type (gdbarch, regnum));
07b287a0 2534
07b287a0
MS		 2535 VALUE_LVAL (result_value) = lval_register;
2536 VALUE_REGNUM (result_value) = regnum;
07b287a0
MS		 2537
2538 regnum -= gdbarch_num_regs (gdbarch);
2539
2540 if (regnum >= AARCH64_Q0_REGNUM && regnum < AARCH64_Q0_REGNUM + 32)
63bad7b6
AH		 2541 return aarch64_pseudo_read_value_1 (gdbarch, regcache,
2542 regnum - AARCH64_Q0_REGNUM,
3c5cd5c3 2543 Q_REGISTER_SIZE, result_value);
07b287a0
MS		 2544
2545 if (regnum >= AARCH64_D0_REGNUM && regnum < AARCH64_D0_REGNUM + 32)
63bad7b6
AH		 2546 return aarch64_pseudo_read_value_1 (gdbarch, regcache,
2547 regnum - AARCH64_D0_REGNUM,
3c5cd5c3 2548 D_REGISTER_SIZE, result_value);
07b287a0
MS		 2549
2550 if (regnum >= AARCH64_S0_REGNUM && regnum < AARCH64_S0_REGNUM + 32)
63bad7b6
AH		 2551 return aarch64_pseudo_read_value_1 (gdbarch, regcache,
2552 regnum - AARCH64_S0_REGNUM,
3c5cd5c3 2553 S_REGISTER_SIZE, result_value);
07b287a0
MS		 2554
2555 if (regnum >= AARCH64_H0_REGNUM && regnum < AARCH64_H0_REGNUM + 32)
63bad7b6
AH		 2556 return aarch64_pseudo_read_value_1 (gdbarch, regcache,
2557 regnum - AARCH64_H0_REGNUM,
3c5cd5c3 2558 H_REGISTER_SIZE, result_value);
07b287a0
MS		 2559
2560 if (regnum >= AARCH64_B0_REGNUM && regnum < AARCH64_B0_REGNUM + 32)
63bad7b6
AH		 2561 return aarch64_pseudo_read_value_1 (gdbarch, regcache,
2562 regnum - AARCH64_B0_REGNUM,
3c5cd5c3 2563 B_REGISTER_SIZE, result_value);
07b287a0 2564
63bad7b6
AH		 2565 if (tdep->has_sve () && regnum >= AARCH64_SVE_V0_REGNUM
2566 && regnum < AARCH64_SVE_V0_REGNUM + 32)
2567 return aarch64_pseudo_read_value_1 (gdbarch, regcache,
2568 regnum - AARCH64_SVE_V0_REGNUM,
2569 V_REGISTER_SIZE, result_value);
2570
07b287a0
MS		 2571 gdb_assert_not_reached ("regnum out of bound");
2572}
2573
3c5cd5c3 2574/* Helper for aarch64_pseudo_write. */
07b287a0
MS		 2575
2576static void
63bad7b6
AH		 2577aarch64_pseudo_write_1 (struct gdbarch *gdbarch, struct regcache *regcache,
2578 int regnum_offset, int regsize, const gdb_byte *buf)
07b287a0 2579{
3c5cd5c3 2580 unsigned v_regnum = AARCH64_V0_REGNUM + regnum_offset;
07b287a0 2581
63bad7b6
AH		 2582 /* Enough space for a full vector register. */
2583 gdb_byte reg_buf[register_size (gdbarch, AARCH64_V0_REGNUM)];
2584 gdb_static_assert (AARCH64_V0_REGNUM == AARCH64_SVE_Z0_REGNUM);
2585
07b287a0
MS		 2586 /* Ensure the register buffer is zero, we want gdb writes of the
2587 various 'scalar' pseudo registers to behavior like architectural
2588 writes, register width bytes are written the remainder are set to
2589 zero. */
63bad7b6 2590 memset (reg_buf, 0, register_size (gdbarch, AARCH64_V0_REGNUM));
07b287a0 2591
3c5cd5c3
AH		 2592 memcpy (reg_buf, buf, regsize);
2593 regcache->raw_write (v_regnum, reg_buf);
2594}
2595
2596/* Implement the "pseudo_register_write" gdbarch method. */
2597
2598static void
2599aarch64_pseudo_write (struct gdbarch *gdbarch, struct regcache *regcache,
2600 int regnum, const gdb_byte *buf)
2601{
63bad7b6 2602 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
07b287a0
MS		 2603 regnum -= gdbarch_num_regs (gdbarch);
2604
2605 if (regnum >= AARCH64_Q0_REGNUM && regnum < AARCH64_Q0_REGNUM + 32)
63bad7b6
AH		 2606 return aarch64_pseudo_write_1 (gdbarch, regcache,
2607 regnum - AARCH64_Q0_REGNUM, Q_REGISTER_SIZE,
2608 buf);
07b287a0
MS		 2609
2610 if (regnum >= AARCH64_D0_REGNUM && regnum < AARCH64_D0_REGNUM + 32)
63bad7b6
AH		 2611 return aarch64_pseudo_write_1 (gdbarch, regcache,
2612 regnum - AARCH64_D0_REGNUM, D_REGISTER_SIZE,
2613 buf);
07b287a0
MS		 2614
2615 if (regnum >= AARCH64_S0_REGNUM && regnum < AARCH64_S0_REGNUM + 32)
63bad7b6
AH		 2616 return aarch64_pseudo_write_1 (gdbarch, regcache,
2617 regnum - AARCH64_S0_REGNUM, S_REGISTER_SIZE,
2618 buf);
07b287a0
MS		 2619
2620 if (regnum >= AARCH64_H0_REGNUM && regnum < AARCH64_H0_REGNUM + 32)
63bad7b6
AH		 2621 return aarch64_pseudo_write_1 (gdbarch, regcache,
2622 regnum - AARCH64_H0_REGNUM, H_REGISTER_SIZE,
2623 buf);
07b287a0
MS		 2624
2625 if (regnum >= AARCH64_B0_REGNUM && regnum < AARCH64_B0_REGNUM + 32)
63bad7b6
AH		 2626 return aarch64_pseudo_write_1 (gdbarch, regcache,
2627 regnum - AARCH64_B0_REGNUM, B_REGISTER_SIZE,
2628 buf);
2629
2630 if (tdep->has_sve () && regnum >= AARCH64_SVE_V0_REGNUM
2631 && regnum < AARCH64_SVE_V0_REGNUM + 32)
2632 return aarch64_pseudo_write_1 (gdbarch, regcache,
2633 regnum - AARCH64_SVE_V0_REGNUM,
2634 V_REGISTER_SIZE, buf);
07b287a0
MS		 2635
2636 gdb_assert_not_reached ("regnum out of bound");
2637}
2638
07b287a0
MS		 2639/* Callback function for user_reg_add. */
2640
2641static struct value *
2642value_of_aarch64_user_reg (struct frame_info *frame, const void *baton)
2643{
9a3c8263 2644 const int *reg_p = (const int *) baton;
07b287a0
MS		 2645
2646 return value_of_register (*reg_p, frame);
2647}
2648\f
2649
9404b58f
KM		 2650/* Implement the "software_single_step" gdbarch method, needed to
2651 single step through atomic sequences on AArch64. */
2652
a0ff9e1a 2653static std::vector<CORE_ADDR>
f5ea389a 2654aarch64_software_single_step (struct regcache *regcache)
9404b58f 2655{
ac7936df 2656 struct gdbarch *gdbarch = regcache->arch ();
9404b58f
KM		 2657 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
2658 const int insn_size = 4;
2659 const int atomic_sequence_length = 16; /* Instruction sequence length. */
0187a92f 2660 CORE_ADDR pc = regcache_read_pc (regcache);
70ab8ccd 2661 CORE_ADDR breaks[2] = { CORE_ADDR_MAX, CORE_ADDR_MAX };
9404b58f
KM		 2662 CORE_ADDR loc = pc;
2663 CORE_ADDR closing_insn = 0;
2664 uint32_t insn = read_memory_unsigned_integer (loc, insn_size,
2665 byte_order_for_code);
2666 int index;
2667 int insn_count;
2668 int bc_insn_count = 0; /* Conditional branch instruction count. */
2669 int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */
f77ee802
YQ		 2670 aarch64_inst inst;
2671
561a72d4 2672 if (aarch64_decode_insn (insn, &inst, 1, NULL) != 0)
a0ff9e1a 2673 return {};
9404b58f
KM		 2674
2675 /* Look for a Load Exclusive instruction which begins the sequence. */
f77ee802 2676 if (inst.opcode->iclass != ldstexcl || bit (insn, 22) == 0)
a0ff9e1a 2677 return {};
9404b58f
KM		 2678
2679 for (insn_count = 0; insn_count < atomic_sequence_length; ++insn_count)
2680 {
9404b58f
KM		 2681 loc += insn_size;
2682 insn = read_memory_unsigned_integer (loc, insn_size,
2683 byte_order_for_code);
2684
561a72d4 2685 if (aarch64_decode_insn (insn, &inst, 1, NULL) != 0)
a0ff9e1a 2686 return {};
9404b58f 2687 /* Check if the instruction is a conditional branch. */
f77ee802 2688 if (inst.opcode->iclass == condbranch)
9404b58f 2689 {
f77ee802
YQ		 2690 gdb_assert (inst.operands[0].type == AARCH64_OPND_ADDR_PCREL19);
2691
9404b58f 2692 if (bc_insn_count >= 1)
a0ff9e1a 2693 return {};
9404b58f
KM		 2694
2695 /* It is, so we'll try to set a breakpoint at the destination. */
f77ee802 2696 breaks[1] = loc + inst.operands[0].imm.value;
9404b58f
KM		 2697
2698 bc_insn_count++;
2699 last_breakpoint++;
2700 }
2701
2702 /* Look for the Store Exclusive which closes the atomic sequence. */
f77ee802 2703 if (inst.opcode->iclass == ldstexcl && bit (insn, 22) == 0)
9404b58f
KM		 2704 {
2705 closing_insn = loc;
2706 break;
2707 }
2708 }
2709
2710 /* We didn't find a closing Store Exclusive instruction, fall back. */
2711 if (!closing_insn)
a0ff9e1a 2712 return {};
9404b58f
KM		 2713
2714 /* Insert breakpoint after the end of the atomic sequence. */
2715 breaks[0] = loc + insn_size;
2716
2717 /* Check for duplicated breakpoints, and also check that the second
2718 breakpoint is not within the atomic sequence. */
2719 if (last_breakpoint
2720 && (breaks[1] == breaks[0]
2721 || (breaks[1] >= pc && breaks[1] <= closing_insn)))
2722 last_breakpoint = 0;
2723
a0ff9e1a
SM		 2724 std::vector<CORE_ADDR> next_pcs;
2725
9404b58f
KM		 2726 /* Insert the breakpoint at the end of the sequence, and one at the
2727 destination of the conditional branch, if it exists. */
2728 for (index = 0; index <= last_breakpoint; index++)
a0ff9e1a 2729 next_pcs.push_back (breaks[index]);
9404b58f 2730
93f9a11f 2731 return next_pcs;
9404b58f
KM		 2732}
2733
cfba9872 2734struct aarch64_displaced_step_closure : public displaced_step_closure
b6542f81
YQ		 2735{
2736 /* It is true when condition instruction, such as B.CON, TBZ, etc,
2737 is being displaced stepping. */
cfba9872 2738 int cond = 0;
b6542f81
YQ		 2739
2740 /* PC adjustment offset after displaced stepping. */
cfba9872 2741 int32_t pc_adjust = 0;
b6542f81
YQ		 2742};
2743
2744/* Data when visiting instructions for displaced stepping. */
2745
2746struct aarch64_displaced_step_data
2747{
2748 struct aarch64_insn_data base;
2749
2750 /* The address where the instruction will be executed at. */
2751 CORE_ADDR new_addr;
2752 /* Buffer of instructions to be copied to NEW_ADDR to execute. */
e935475c 2753 uint32_t insn_buf[AARCH64_DISPLACED_MODIFIED_INSNS];
b6542f81
YQ		 2754 /* Number of instructions in INSN_BUF. */
2755 unsigned insn_count;
2756 /* Registers when doing displaced stepping. */
2757 struct regcache *regs;
2758
cfba9872 2759 aarch64_displaced_step_closure *dsc;
b6542f81
YQ		 2760};
2761
2762/* Implementation of aarch64_insn_visitor method "b". */
2763
2764static void
2765aarch64_displaced_step_b (const int is_bl, const int32_t offset,
2766 struct aarch64_insn_data *data)
2767{
2768 struct aarch64_displaced_step_data *dsd
2769 = (struct aarch64_displaced_step_data *) data;
2ac09a5b 2770 int64_t new_offset = data->insn_addr - dsd->new_addr + offset;
b6542f81
YQ		 2771
2772 if (can_encode_int32 (new_offset, 28))
2773 {
2774 /* Emit B rather than BL, because executing BL on a new address
2775 will get the wrong address into LR. In order to avoid this,
2776 we emit B, and update LR if the instruction is BL. */
2777 emit_b (dsd->insn_buf, 0, new_offset);
2778 dsd->insn_count++;
2779 }
2780 else
2781 {
2782 /* Write NOP. */
2783 emit_nop (dsd->insn_buf);
2784 dsd->insn_count++;
2785 dsd->dsc->pc_adjust = offset;
2786 }
2787
2788 if (is_bl)
2789 {
2790 /* Update LR. */
2791 regcache_cooked_write_unsigned (dsd->regs, AARCH64_LR_REGNUM,
2792 data->insn_addr + 4);
2793 }
2794}
2795
2796/* Implementation of aarch64_insn_visitor method "b_cond". */
2797
2798static void
2799aarch64_displaced_step_b_cond (const unsigned cond, const int32_t offset,
2800 struct aarch64_insn_data *data)
2801{
2802 struct aarch64_displaced_step_data *dsd
2803 = (struct aarch64_displaced_step_data *) data;
b6542f81
YQ		 2804
2805 /* GDB has to fix up PC after displaced step this instruction
2806 differently according to the condition is true or false. Instead
2807 of checking COND against conditional flags, we can use
2808 the following instructions, and GDB can tell how to fix up PC
2809 according to the PC value.
2810
2811 B.COND TAKEN ; If cond is true, then jump to TAKEN.
2812 INSN1 ;
2813 TAKEN:
2814 INSN2
2815 */
2816
2817 emit_bcond (dsd->insn_buf, cond, 8);
2818 dsd->dsc->cond = 1;
2819 dsd->dsc->pc_adjust = offset;
2820 dsd->insn_count = 1;
2821}
2822
2823/* Dynamically allocate a new register. If we know the register
2824 statically, we should make it a global as above instead of using this
2825 helper function. */
2826
2827static struct aarch64_register
2828aarch64_register (unsigned num, int is64)
2829{
2830 return (struct aarch64_register) { num, is64 };
2831}
2832
2833/* Implementation of aarch64_insn_visitor method "cb". */
2834
2835static void
2836aarch64_displaced_step_cb (const int32_t offset, const int is_cbnz,
2837 const unsigned rn, int is64,
2838 struct aarch64_insn_data *data)
2839{
2840 struct aarch64_displaced_step_data *dsd
2841 = (struct aarch64_displaced_step_data *) data;
b6542f81
YQ		 2842
2843 /* The offset is out of range for a compare and branch
2844 instruction. We can use the following instructions instead:
2845
2846 CBZ xn, TAKEN ; xn == 0, then jump to TAKEN.
2847 INSN1 ;
2848 TAKEN:
2849 INSN2
2850 */
2851 emit_cb (dsd->insn_buf, is_cbnz, aarch64_register (rn, is64), 8);
2852 dsd->insn_count = 1;
2853 dsd->dsc->cond = 1;
2854 dsd->dsc->pc_adjust = offset;
2855}
2856
2857/* Implementation of aarch64_insn_visitor method "tb". */
2858
2859static void
2860aarch64_displaced_step_tb (const int32_t offset, int is_tbnz,
2861 const unsigned rt, unsigned bit,
2862 struct aarch64_insn_data *data)
2863{
2864 struct aarch64_displaced_step_data *dsd
2865 = (struct aarch64_displaced_step_data *) data;
b6542f81
YQ		 2866
2867 /* The offset is out of range for a test bit and branch
2868 instruction We can use the following instructions instead:
2869
2870 TBZ xn, #bit, TAKEN ; xn[bit] == 0, then jump to TAKEN.
2871 INSN1 ;
2872 TAKEN:
2873 INSN2
2874
2875 */
2876 emit_tb (dsd->insn_buf, is_tbnz, bit, aarch64_register (rt, 1), 8);
2877 dsd->insn_count = 1;
2878 dsd->dsc->cond = 1;
2879 dsd->dsc->pc_adjust = offset;
2880}
2881
2882/* Implementation of aarch64_insn_visitor method "adr". */
2883
2884static void
2885aarch64_displaced_step_adr (const int32_t offset, const unsigned rd,
2886 const int is_adrp, struct aarch64_insn_data *data)
2887{
2888 struct aarch64_displaced_step_data *dsd
2889 = (struct aarch64_displaced_step_data *) data;
2890 /* We know exactly the address the ADR{P,} instruction will compute.
2891 We can just write it to the destination register. */
2892 CORE_ADDR address = data->insn_addr + offset;
2893
2894 if (is_adrp)
2895 {
2896 /* Clear the lower 12 bits of the offset to get the 4K page. */
2897 regcache_cooked_write_unsigned (dsd->regs, AARCH64_X0_REGNUM + rd,
2898 address & ~0xfff);
2899 }
2900 else
2901 regcache_cooked_write_unsigned (dsd->regs, AARCH64_X0_REGNUM + rd,
2902 address);
2903
2904 dsd->dsc->pc_adjust = 4;
2905 emit_nop (dsd->insn_buf);
2906 dsd->insn_count = 1;
2907}
2908
2909/* Implementation of aarch64_insn_visitor method "ldr_literal". */
2910
2911static void
2912aarch64_displaced_step_ldr_literal (const int32_t offset, const int is_sw,
2913 const unsigned rt, const int is64,
2914 struct aarch64_insn_data *data)
2915{
2916 struct aarch64_displaced_step_data *dsd
2917 = (struct aarch64_displaced_step_data *) data;
2918 CORE_ADDR address = data->insn_addr + offset;
2919 struct aarch64_memory_operand zero = { MEMORY_OPERAND_OFFSET, 0 };
2920
2921 regcache_cooked_write_unsigned (dsd->regs, AARCH64_X0_REGNUM + rt,
2922 address);
2923
2924 if (is_sw)
2925 dsd->insn_count = emit_ldrsw (dsd->insn_buf, aarch64_register (rt, 1),
2926 aarch64_register (rt, 1), zero);
2927 else
2928 dsd->insn_count = emit_ldr (dsd->insn_buf, aarch64_register (rt, is64),
2929 aarch64_register (rt, 1), zero);
2930
2931 dsd->dsc->pc_adjust = 4;
2932}
2933
2934/* Implementation of aarch64_insn_visitor method "others". */
2935
2936static void
2937aarch64_displaced_step_others (const uint32_t insn,
2938 struct aarch64_insn_data *data)
2939{
2940 struct aarch64_displaced_step_data *dsd
2941 = (struct aarch64_displaced_step_data *) data;
2942
e1c587c3 2943 aarch64_emit_insn (dsd->insn_buf, insn);
b6542f81
YQ		 2944 dsd->insn_count = 1;
2945
2946 if ((insn & 0xfffffc1f) == 0xd65f0000)
2947 {
2948 /* RET */
2949 dsd->dsc->pc_adjust = 0;
2950 }
2951 else
2952 dsd->dsc->pc_adjust = 4;
2953}
2954
2955static const struct aarch64_insn_visitor visitor =
2956{
2957 aarch64_displaced_step_b,
2958 aarch64_displaced_step_b_cond,
2959 aarch64_displaced_step_cb,
2960 aarch64_displaced_step_tb,
2961 aarch64_displaced_step_adr,
2962 aarch64_displaced_step_ldr_literal,
2963 aarch64_displaced_step_others,
2964};
2965
2966/* Implement the "displaced_step_copy_insn" gdbarch method. */
2967
18b28e13 2968std::unique_ptr<displaced_step_closure>
b6542f81
YQ		 2969aarch64_displaced_step_copy_insn (struct gdbarch *gdbarch,
2970 CORE_ADDR from, CORE_ADDR to,
2971 struct regcache *regs)
2972{
b6542f81
YQ		 2973 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
2974 uint32_t insn = read_memory_unsigned_integer (from, 4, byte_order_for_code);
2975 struct aarch64_displaced_step_data dsd;
c86a40c6
YQ		 2976 aarch64_inst inst;
2977
561a72d4 2978 if (aarch64_decode_insn (insn, &inst, 1, NULL) != 0)
c86a40c6 2979 return NULL;
b6542f81
YQ		 2980
2981 /* Look for a Load Exclusive instruction which begins the sequence. */
c86a40c6 2982 if (inst.opcode->iclass == ldstexcl && bit (insn, 22))
b6542f81
YQ		 2983 {
2984 /* We can't displaced step atomic sequences. */
2985 return NULL;
2986 }
2987
cfba9872
SM		 2988 std::unique_ptr<aarch64_displaced_step_closure> dsc
2989 (new aarch64_displaced_step_closure);
b6542f81
YQ		 2990 dsd.base.insn_addr = from;
2991 dsd.new_addr = to;
2992 dsd.regs = regs;
cfba9872 2993 dsd.dsc = dsc.get ();
034f1a81 2994 dsd.insn_count = 0;
b6542f81
YQ		 2995 aarch64_relocate_instruction (insn, &visitor,
2996 (struct aarch64_insn_data *) &dsd);
e935475c 2997 gdb_assert (dsd.insn_count <= AARCH64_DISPLACED_MODIFIED_INSNS);
b6542f81
YQ		 2998
2999 if (dsd.insn_count != 0)
3000 {
3001 int i;
3002
3003 /* Instruction can be relocated to scratch pad. Copy
3004 relocated instruction(s) there. */
3005 for (i = 0; i < dsd.insn_count; i++)
3006 {
3007 if (debug_displaced)
3008 {
3009 debug_printf ("displaced: writing insn ");
3010 debug_printf ("%.8x", dsd.insn_buf[i]);
3011 debug_printf (" at %s\n", paddress (gdbarch, to + i * 4));
3012 }
3013 write_memory_unsigned_integer (to + i * 4, 4, byte_order_for_code,
3014 (ULONGEST) dsd.insn_buf[i]);
3015 }
3016 }
3017 else
3018 {
b6542f81
YQ		 3019 dsc = NULL;
3020 }
3021
18b28e13 3022 return dsc;
b6542f81
YQ		 3023}
3024
3025/* Implement the "displaced_step_fixup" gdbarch method. */
3026
3027void
3028aarch64_displaced_step_fixup (struct gdbarch *gdbarch,
cfba9872 3029 struct displaced_step_closure *dsc_,
b6542f81
YQ		 3030 CORE_ADDR from, CORE_ADDR to,
3031 struct regcache *regs)
3032{
cfba9872
SM		 3033 aarch64_displaced_step_closure *dsc = (aarch64_displaced_step_closure *) dsc_;
3034
b6542f81
YQ		 3035 if (dsc->cond)
3036 {
3037 ULONGEST pc;
3038
3039 regcache_cooked_read_unsigned (regs, AARCH64_PC_REGNUM, &pc);
3040 if (pc - to == 8)
3041 {
3042 /* Condition is true. */
3043 }
3044 else if (pc - to == 4)
3045 {
3046 /* Condition is false. */
3047 dsc->pc_adjust = 4;
3048 }
3049 else
3050 gdb_assert_not_reached ("Unexpected PC value after displaced stepping");
3051 }
3052
3053 if (dsc->pc_adjust != 0)
3054 {
3055 if (debug_displaced)
3056 {
3057 debug_printf ("displaced: fixup: set PC to %s:%d\n",
3058 paddress (gdbarch, from), dsc->pc_adjust);
3059 }
3060 regcache_cooked_write_unsigned (regs, AARCH64_PC_REGNUM,
3061 from + dsc->pc_adjust);
3062 }
3063}
3064
3065/* Implement the "displaced_step_hw_singlestep" gdbarch method. */
3066
3067int
3068aarch64_displaced_step_hw_singlestep (struct gdbarch *gdbarch,
3069 struct displaced_step_closure *closure)
3070{
3071 return 1;
3072}
3073
95228a0d
AH		 3074/* Get the correct target description for the given VQ value.
3075 If VQ is zero then it is assumed SVE is not supported.
3076 (It is not possible to set VQ to zero on an SVE system). */
da434ccb
AH		 3077
3078const target_desc *
6dc0ebde 3079aarch64_read_description (uint64_t vq, bool pauth_p)
da434ccb 3080{
95228a0d 3081 if (vq > AARCH64_MAX_SVE_VQ)
39bfb937 3082 error (_("VQ is %" PRIu64 ", maximum supported value is %d"), vq,
95228a0d
AH		 3083 AARCH64_MAX_SVE_VQ);
3084
6dc0ebde 3085 struct target_desc *tdesc = tdesc_aarch64_list[vq][pauth_p];
da434ccb 3086
95228a0d
AH		 3087 if (tdesc == NULL)
3088 {
6dc0ebde
AH		 3089 tdesc = aarch64_create_target_description (vq, pauth_p);
3090 tdesc_aarch64_list[vq][pauth_p] = tdesc;
95228a0d 3091 }
da434ccb 3092
95228a0d 3093 return tdesc;
da434ccb
AH		 3094}
3095
ba2d2bb2
AH		 3096/* Return the VQ used when creating the target description TDESC. */
3097
1332a140 3098static uint64_t
ba2d2bb2
AH		 3099aarch64_get_tdesc_vq (const struct target_desc *tdesc)
3100{
3101 const struct tdesc_feature *feature_sve;
3102
3103 if (!tdesc_has_registers (tdesc))
3104 return 0;
3105
3106 feature_sve = tdesc_find_feature (tdesc, "org.gnu.gdb.aarch64.sve");
3107
3108 if (feature_sve == nullptr)
3109 return 0;
3110
12863263
AH		 3111 uint64_t vl = tdesc_register_bitsize (feature_sve,
3112 aarch64_sve_register_names[0]) / 8;
ba2d2bb2
AH		 3113 return sve_vq_from_vl (vl);
3114}
3115
0ef8a082
AH		 3116/* Add all the expected register sets into GDBARCH. */
3117
3118static void
3119aarch64_add_reggroups (struct gdbarch *gdbarch)
3120{
3121 reggroup_add (gdbarch, general_reggroup);
3122 reggroup_add (gdbarch, float_reggroup);
3123 reggroup_add (gdbarch, system_reggroup);
3124 reggroup_add (gdbarch, vector_reggroup);
3125 reggroup_add (gdbarch, all_reggroup);
3126 reggroup_add (gdbarch, save_reggroup);
3127 reggroup_add (gdbarch, restore_reggroup);
3128}
ba2d2bb2 3129
76bed0fd
AH		 3130/* Implement the "cannot_store_register" gdbarch method. */
3131
3132static int
3133aarch64_cannot_store_register (struct gdbarch *gdbarch, int regnum)
3134{
3135 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3136
3137 if (!tdep->has_pauth ())
3138 return 0;
3139
3140 /* Pointer authentication registers are read-only. */
3141 return (regnum == AARCH64_PAUTH_DMASK_REGNUM (tdep->pauth_reg_base)
3142 || regnum == AARCH64_PAUTH_CMASK_REGNUM (tdep->pauth_reg_base));
3143}
3144
07b287a0
MS		 3145/* Initialize the current architecture based on INFO. If possible,
3146 re-use an architecture from ARCHES, which is a list of
3147 architectures already created during this debugging session.
3148
3149 Called e.g. at program startup, when reading a core file, and when
3150 reading a binary file. */
3151
3152static struct gdbarch *
3153aarch64_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
3154{
ccb8d7e8 3155 const struct tdesc_feature *feature_core, *feature_fpu, *feature_sve;
76bed0fd 3156 const struct tdesc_feature *feature_pauth;
ccb8d7e8
AH		 3157 bool valid_p = true;
3158 int i, num_regs = 0, num_pseudo_regs = 0;
3159 int first_pauth_regnum = -1, pauth_ra_state_offset = -1;
3160
4da037ef
AH		 3161 /* Use the vector length passed via the target info. Here -1 is used for no
3162 SVE, and 0 is unset. If unset then use the vector length from the existing
3163 tdesc. */
3164 uint64_t vq = 0;
3165 if (info.id == (int *) -1)
3166 vq = 0;
3167 else if (info.id != 0)
3168 vq = (uint64_t) info.id;
3169 else
3170 vq = aarch64_get_tdesc_vq (info.target_desc);
3171
3172 if (vq > AARCH64_MAX_SVE_VQ)
596179f7
SDJ		 3173 internal_error (__FILE__, __LINE__, _("VQ out of bounds: %s (max %d)"),
3174 pulongest (vq), AARCH64_MAX_SVE_VQ);
4da037ef 3175
ccb8d7e8
AH		 3176 /* If there is already a candidate, use it. */
3177 for (gdbarch_list *best_arch = gdbarch_list_lookup_by_info (arches, &info);
3178 best_arch != nullptr;
3179 best_arch = gdbarch_list_lookup_by_info (best_arch->next, &info))
3180 {
3181 struct gdbarch_tdep *tdep = gdbarch_tdep (best_arch->gdbarch);
4da037ef 3182 if (tdep && tdep->vq == vq)
ccb8d7e8
AH		 3183 return best_arch->gdbarch;
3184 }
07b287a0 3185
4da037ef
AH		 3186 /* Ensure we always have a target descriptor, and that it is for the given VQ
3187 value. */
ccb8d7e8 3188 const struct target_desc *tdesc = info.target_desc;
4da037ef
AH		 3189 if (!tdesc_has_registers (tdesc) || vq != aarch64_get_tdesc_vq (tdesc))
3190 tdesc = aarch64_read_description (vq, false);
07b287a0
MS		 3191 gdb_assert (tdesc);
3192
ccb8d7e8 3193 feature_core = tdesc_find_feature (tdesc,"org.gnu.gdb.aarch64.core");
ba2d2bb2
AH		 3194 feature_fpu = tdesc_find_feature (tdesc, "org.gnu.gdb.aarch64.fpu");
3195 feature_sve = tdesc_find_feature (tdesc, "org.gnu.gdb.aarch64.sve");
76bed0fd 3196 feature_pauth = tdesc_find_feature (tdesc, "org.gnu.gdb.aarch64.pauth");
07b287a0 3197
ccb8d7e8
AH		 3198 if (feature_core == nullptr)
3199 return nullptr;
07b287a0 3200
ccb8d7e8 3201 struct tdesc_arch_data *tdesc_data = tdesc_data_alloc ();
07b287a0 3202
ba2d2bb2 3203 /* Validate the description provides the mandatory core R registers
07b287a0
MS		 3204 and allocate their numbers. */
3205 for (i = 0; i < ARRAY_SIZE (aarch64_r_register_names); i++)
ba2d2bb2
AH		 3206 valid_p &= tdesc_numbered_register (feature_core, tdesc_data,
3207 AARCH64_X0_REGNUM + i,
3208 aarch64_r_register_names[i]);
07b287a0
MS		 3209
3210 num_regs = AARCH64_X0_REGNUM + i;
3211
ba2d2bb2 3212 /* Add the V registers. */
ccb8d7e8 3213 if (feature_fpu != nullptr)
07b287a0 3214 {
ccb8d7e8 3215 if (feature_sve != nullptr)
ba2d2bb2
AH		 3216 error (_("Program contains both fpu and SVE features."));
3217
3218 /* Validate the description provides the mandatory V registers
3219 and allocate their numbers. */
07b287a0 3220 for (i = 0; i < ARRAY_SIZE (aarch64_v_register_names); i++)
ba2d2bb2
AH		 3221 valid_p &= tdesc_numbered_register (feature_fpu, tdesc_data,
3222 AARCH64_V0_REGNUM + i,
3223 aarch64_v_register_names[i]);
07b287a0
MS		 3224
3225 num_regs = AARCH64_V0_REGNUM + i;
ba2d2bb2 3226 }
07b287a0 3227
ba2d2bb2 3228 /* Add the SVE registers. */
ccb8d7e8 3229 if (feature_sve != nullptr)
ba2d2bb2
AH		 3230 {
3231 /* Validate the description provides the mandatory SVE registers
3232 and allocate their numbers. */
3233 for (i = 0; i < ARRAY_SIZE (aarch64_sve_register_names); i++)
3234 valid_p &= tdesc_numbered_register (feature_sve, tdesc_data,
3235 AARCH64_SVE_Z0_REGNUM + i,
3236 aarch64_sve_register_names[i]);
3237
3238 num_regs = AARCH64_SVE_Z0_REGNUM + i;
3239 num_pseudo_regs += 32; /* add the Vn register pseudos. */
3240 }
3241
ccb8d7e8 3242 if (feature_fpu != nullptr || feature_sve != nullptr)
ba2d2bb2 3243 {
07b287a0
MS		 3244 num_pseudo_regs += 32; /* add the Qn scalar register pseudos */
3245 num_pseudo_regs += 32; /* add the Dn scalar register pseudos */
3246 num_pseudo_regs += 32; /* add the Sn scalar register pseudos */
3247 num_pseudo_regs += 32; /* add the Hn scalar register pseudos */
3248 num_pseudo_regs += 32; /* add the Bn scalar register pseudos */
3249 }
3250
76bed0fd
AH		 3251 /* Add the pauth registers. */
3252 if (feature_pauth != NULL)
3253 {
3254 first_pauth_regnum = num_regs;
34dcc7cf 3255 pauth_ra_state_offset = num_pseudo_regs;
76bed0fd
AH		 3256 /* Validate the descriptor provides the mandatory PAUTH registers and
3257 allocate their numbers. */
3258 for (i = 0; i < ARRAY_SIZE (aarch64_pauth_register_names); i++)
3259 valid_p &= tdesc_numbered_register (feature_pauth, tdesc_data,
3260 first_pauth_regnum + i,
3261 aarch64_pauth_register_names[i]);
3262
3263 num_regs += i;
34dcc7cf 3264 num_pseudo_regs += 1; /* Count RA_STATE pseudo register. */
76bed0fd
AH		 3265 }
3266
07b287a0
MS		 3267 if (!valid_p)
3268 {
3269 tdesc_data_cleanup (tdesc_data);
ccb8d7e8 3270 return nullptr;
07b287a0
MS		 3271 }
3272
3273 /* AArch64 code is always little-endian. */
3274 info.byte_order_for_code = BFD_ENDIAN_LITTLE;
3275
ccb8d7e8
AH		 3276 struct gdbarch_tdep *tdep = XCNEW (struct gdbarch_tdep);
3277 struct gdbarch *gdbarch = gdbarch_alloc (&info, tdep);
07b287a0
MS		 3278
3279 /* This should be low enough for everything. */
3280 tdep->lowest_pc = 0x20;
3281 tdep->jb_pc = -1; /* Longjump support not enabled by default. */
3282 tdep->jb_elt_size = 8;
4da037ef 3283 tdep->vq = vq;
76bed0fd 3284 tdep->pauth_reg_base = first_pauth_regnum;
34dcc7cf
AH		 3285 tdep->pauth_ra_state_regnum = (feature_pauth == NULL) ? -1
3286 : pauth_ra_state_offset + num_regs;
3287
07b287a0
MS		 3288 set_gdbarch_push_dummy_call (gdbarch, aarch64_push_dummy_call);
3289 set_gdbarch_frame_align (gdbarch, aarch64_frame_align);
3290
07b287a0
MS		 3291 /* Advance PC across function entry code. */
3292 set_gdbarch_skip_prologue (gdbarch, aarch64_skip_prologue);
3293
3294 /* The stack grows downward. */
3295 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
3296
3297 /* Breakpoint manipulation. */
04180708
YQ		 3298 set_gdbarch_breakpoint_kind_from_pc (gdbarch,
3299 aarch64_breakpoint::kind_from_pc);
3300 set_gdbarch_sw_breakpoint_from_kind (gdbarch,
3301 aarch64_breakpoint::bp_from_kind);
07b287a0 3302 set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1);
9404b58f 3303 set_gdbarch_software_single_step (gdbarch, aarch64_software_single_step);
07b287a0
MS		 3304
3305 /* Information about registers, etc. */
3306 set_gdbarch_sp_regnum (gdbarch, AARCH64_SP_REGNUM);
3307 set_gdbarch_pc_regnum (gdbarch, AARCH64_PC_REGNUM);
3308 set_gdbarch_num_regs (gdbarch, num_regs);
3309
3310 set_gdbarch_num_pseudo_regs (gdbarch, num_pseudo_regs);
3311 set_gdbarch_pseudo_register_read_value (gdbarch, aarch64_pseudo_read_value);
3312 set_gdbarch_pseudo_register_write (gdbarch, aarch64_pseudo_write);
3313 set_tdesc_pseudo_register_name (gdbarch, aarch64_pseudo_register_name);
3314 set_tdesc_pseudo_register_type (gdbarch, aarch64_pseudo_register_type);
3315 set_tdesc_pseudo_register_reggroup_p (gdbarch,
3316 aarch64_pseudo_register_reggroup_p);
76bed0fd 3317 set_gdbarch_cannot_store_register (gdbarch, aarch64_cannot_store_register);
07b287a0
MS		 3318
3319 /* ABI */
3320 set_gdbarch_short_bit (gdbarch, 16);
3321 set_gdbarch_int_bit (gdbarch, 32);
3322 set_gdbarch_float_bit (gdbarch, 32);
3323 set_gdbarch_double_bit (gdbarch, 64);
3324 set_gdbarch_long_double_bit (gdbarch, 128);
3325 set_gdbarch_long_bit (gdbarch, 64);
3326 set_gdbarch_long_long_bit (gdbarch, 64);
3327 set_gdbarch_ptr_bit (gdbarch, 64);
3328 set_gdbarch_char_signed (gdbarch, 0);
53375380 3329 set_gdbarch_wchar_signed (gdbarch, 0);
07b287a0
MS		 3330 set_gdbarch_float_format (gdbarch, floatformats_ieee_single);
3331 set_gdbarch_double_format (gdbarch, floatformats_ieee_double);
3332 set_gdbarch_long_double_format (gdbarch, floatformats_ia64_quad);
b907456c 3333 set_gdbarch_type_align (gdbarch, aarch64_type_align);
07b287a0
MS		 3334
3335 /* Internal <-> external register number maps. */
3336 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, aarch64_dwarf_reg_to_regnum);
3337
3338 /* Returning results. */
3339 set_gdbarch_return_value (gdbarch, aarch64_return_value);
3340
3341 /* Disassembly. */
3342 set_gdbarch_print_insn (gdbarch, aarch64_gdb_print_insn);
3343
3344 /* Virtual tables. */
3345 set_gdbarch_vbit_in_delta (gdbarch, 1);
3346
0ef8a082
AH		 3347 /* Register architecture. */
3348 aarch64_add_reggroups (gdbarch);
3349
07b287a0
MS		 3350 /* Hook in the ABI-specific overrides, if they have been registered. */
3351 info.target_desc = tdesc;
0dba2a6c 3352 info.tdesc_data = tdesc_data;
07b287a0
MS		 3353 gdbarch_init_osabi (info, gdbarch);
3354
3355 dwarf2_frame_set_init_reg (gdbarch, aarch64_dwarf2_frame_init_reg);
11e1b75f
AH		 3356 /* Register DWARF CFA vendor handler. */
3357 set_gdbarch_execute_dwarf_cfa_vendor_op (gdbarch,
3358 aarch64_execute_dwarf_cfa_vendor_op);
07b287a0
MS		 3359
3360 /* Add some default predicates. */
3361 frame_unwind_append_unwinder (gdbarch, &aarch64_stub_unwind);
3362 dwarf2_append_unwinders (gdbarch);
3363 frame_unwind_append_unwinder (gdbarch, &aarch64_prologue_unwind);
3364
3365 frame_base_set_default (gdbarch, &aarch64_normal_base);
3366
3367 /* Now we have tuned the configuration, set a few final things,
3368 based on what the OS ABI has told us. */
3369
3370 if (tdep->jb_pc >= 0)
3371 set_gdbarch_get_longjmp_target (gdbarch, aarch64_get_longjmp_target);
3372
ea873d8e
PL		 3373 set_gdbarch_gen_return_address (gdbarch, aarch64_gen_return_address);
3374
aa7ca1bb
AH		 3375 set_gdbarch_get_pc_address_flags (gdbarch, aarch64_get_pc_address_flags);
3376
07b287a0
MS		 3377 tdesc_use_registers (gdbarch, tdesc, tdesc_data);
3378
3379 /* Add standard register aliases. */
3380 for (i = 0; i < ARRAY_SIZE (aarch64_register_aliases); i++)
3381 user_reg_add (gdbarch, aarch64_register_aliases[i].name,
3382 value_of_aarch64_user_reg,
3383 &aarch64_register_aliases[i].regnum);
3384
e8bf1ce4
JB		 3385 register_aarch64_ravenscar_ops (gdbarch);
3386
07b287a0
MS		 3387 return gdbarch;
3388}
3389
3390static void
3391aarch64_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file)
3392{
3393 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3394
3395 if (tdep == NULL)
3396 return;
3397
3398 fprintf_unfiltered (file, _("aarch64_dump_tdep: Lowest pc = 0x%s"),
3399 paddress (gdbarch, tdep->lowest_pc));
3400}
3401
0d4c07af 3402#if GDB_SELF_TEST
1e2b521d
YQ		 3403namespace selftests
3404{
3405static void aarch64_process_record_test (void);
3406}
0d4c07af 3407#endif
1e2b521d 3408
07b287a0
MS		 3409void
3410_initialize_aarch64_tdep (void)
3411{
3412 gdbarch_register (bfd_arch_aarch64, aarch64_gdbarch_init,
3413 aarch64_dump_tdep);
3414
07b287a0
MS		 3415 /* Debug this file's internals. */
3416 add_setshow_boolean_cmd ("aarch64", class_maintenance, &aarch64_debug, _("\
3417Set AArch64 debugging."), _("\
3418Show AArch64 debugging."), _("\
3419When on, AArch64 specific debugging is enabled."),
3420 NULL,
3421 show_aarch64_debug,
3422 &setdebuglist, &showdebuglist);
4d9a9006
YQ		 3423
3424#if GDB_SELF_TEST
1526853e
SM		 3425 selftests::register_test ("aarch64-analyze-prologue",
3426 selftests::aarch64_analyze_prologue_test);
3427 selftests::register_test ("aarch64-process-record",
3428 selftests::aarch64_process_record_test);
4d9a9006 3429#endif
07b287a0 3430}
99afc88b
OJ		 3431
3432/* AArch64 process record-replay related structures, defines etc. */
3433
99afc88b
OJ		 3434#define REG_ALLOC(REGS, LENGTH, RECORD_BUF) \
3435 do \
3436 { \
3437 unsigned int reg_len = LENGTH; \
3438 if (reg_len) \
3439 { \
3440 REGS = XNEWVEC (uint32_t, reg_len); \
3441 memcpy(&REGS[0], &RECORD_BUF[0], sizeof(uint32_t)*LENGTH); \
3442 } \
3443 } \
3444 while (0)
3445
3446#define MEM_ALLOC(MEMS, LENGTH, RECORD_BUF) \
3447 do \
3448 { \
3449 unsigned int mem_len = LENGTH; \
3450 if (mem_len) \
3451 { \
3452 MEMS = XNEWVEC (struct aarch64_mem_r, mem_len); \
3453 memcpy(&MEMS->len, &RECORD_BUF[0], \
3454 sizeof(struct aarch64_mem_r) * LENGTH); \
3455 } \
3456 } \
3457 while (0)
3458
3459/* AArch64 record/replay structures and enumerations. */
3460
3461struct aarch64_mem_r
3462{
3463 uint64_t len; /* Record length. */
3464 uint64_t addr; /* Memory address. */
3465};
3466
3467enum aarch64_record_result
3468{
3469 AARCH64_RECORD_SUCCESS,
99afc88b
OJ		 3470 AARCH64_RECORD_UNSUPPORTED,
3471 AARCH64_RECORD_UNKNOWN
3472};
3473
3474typedef struct insn_decode_record_t
3475{
3476 struct gdbarch *gdbarch;
3477 struct regcache *regcache;
3478 CORE_ADDR this_addr; /* Address of insn to be recorded. */
3479 uint32_t aarch64_insn; /* Insn to be recorded. */
3480 uint32_t mem_rec_count; /* Count of memory records. */
3481 uint32_t reg_rec_count; /* Count of register records. */
3482 uint32_t *aarch64_regs; /* Registers to be recorded. */
3483 struct aarch64_mem_r *aarch64_mems; /* Memory locations to be recorded. */
3484} insn_decode_record;
3485
3486/* Record handler for data processing - register instructions. */
3487
3488static unsigned int
3489aarch64_record_data_proc_reg (insn_decode_record *aarch64_insn_r)
3490{
3491 uint8_t reg_rd, insn_bits24_27, insn_bits21_23;
3492 uint32_t record_buf[4];
3493
3494 reg_rd = bits (aarch64_insn_r->aarch64_insn, 0, 4);
3495 insn_bits24_27 = bits (aarch64_insn_r->aarch64_insn, 24, 27);
3496 insn_bits21_23 = bits (aarch64_insn_r->aarch64_insn, 21, 23);
3497
3498 if (!bit (aarch64_insn_r->aarch64_insn, 28))
3499 {
3500 uint8_t setflags;
3501
3502 /* Logical (shifted register). */
3503 if (insn_bits24_27 == 0x0a)
3504 setflags = (bits (aarch64_insn_r->aarch64_insn, 29, 30) == 0x03);
3505 /* Add/subtract. */
3506 else if (insn_bits24_27 == 0x0b)
3507 setflags = bit (aarch64_insn_r->aarch64_insn, 29);
3508 else
3509 return AARCH64_RECORD_UNKNOWN;
3510
3511 record_buf[0] = reg_rd;
3512 aarch64_insn_r->reg_rec_count = 1;
3513 if (setflags)
3514 record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_CPSR_REGNUM;
3515 }
3516 else
3517 {
3518 if (insn_bits24_27 == 0x0b)
3519 {
3520 /* Data-processing (3 source). */
3521 record_buf[0] = reg_rd;
3522 aarch64_insn_r->reg_rec_count = 1;
3523 }
3524 else if (insn_bits24_27 == 0x0a)
3525 {
3526 if (insn_bits21_23 == 0x00)
3527 {
3528 /* Add/subtract (with carry). */
3529 record_buf[0] = reg_rd;
3530 aarch64_insn_r->reg_rec_count = 1;
3531 if (bit (aarch64_insn_r->aarch64_insn, 29))
3532 {
3533 record_buf[1] = AARCH64_CPSR_REGNUM;
3534 aarch64_insn_r->reg_rec_count = 2;
3535 }
3536 }
3537 else if (insn_bits21_23 == 0x02)
3538 {
3539 /* Conditional compare (register) and conditional compare
3540 (immediate) instructions. */
3541 record_buf[0] = AARCH64_CPSR_REGNUM;
3542 aarch64_insn_r->reg_rec_count = 1;
3543 }
3544 else if (insn_bits21_23 == 0x04 || insn_bits21_23 == 0x06)
3545 {
85102364 3546 /* Conditional select. */
99afc88b
OJ		 3547 /* Data-processing (2 source). */
3548 /* Data-processing (1 source). */
3549 record_buf[0] = reg_rd;
3550 aarch64_insn_r->reg_rec_count = 1;
3551 }
3552 else
3553 return AARCH64_RECORD_UNKNOWN;
3554 }
3555 }
3556
3557 REG_ALLOC (aarch64_insn_r->aarch64_regs, aarch64_insn_r->reg_rec_count,
3558 record_buf);
3559 return AARCH64_RECORD_SUCCESS;
3560}
3561
3562/* Record handler for data processing - immediate instructions. */
3563
3564static unsigned int
3565aarch64_record_data_proc_imm (insn_decode_record *aarch64_insn_r)
3566{
78cc6c2d 3567 uint8_t reg_rd, insn_bit23, insn_bits24_27, setflags;
99afc88b
OJ		 3568 uint32_t record_buf[4];
3569
3570 reg_rd = bits (aarch64_insn_r->aarch64_insn, 0, 4);
99afc88b
OJ		 3571 insn_bit23 = bit (aarch64_insn_r->aarch64_insn, 23);
3572 insn_bits24_27 = bits (aarch64_insn_r->aarch64_insn, 24, 27);
3573
3574 if (insn_bits24_27 == 0x00 /* PC rel addressing. */
3575 || insn_bits24_27 == 0x03 /* Bitfield and Extract. */
3576 || (insn_bits24_27 == 0x02 && insn_bit23)) /* Move wide (immediate). */
3577 {
3578 record_buf[0] = reg_rd;
3579 aarch64_insn_r->reg_rec_count = 1;
3580 }
3581 else if (insn_bits24_27 == 0x01)
3582 {
3583 /* Add/Subtract (immediate). */
3584 setflags = bit (aarch64_insn_r->aarch64_insn, 29);
3585 record_buf[0] = reg_rd;
3586 aarch64_insn_r->reg_rec_count = 1;
3587 if (setflags)
3588 record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_CPSR_REGNUM;
3589 }
3590 else if (insn_bits24_27 == 0x02 && !insn_bit23)
3591 {
3592 /* Logical (immediate). */
3593 setflags = bits (aarch64_insn_r->aarch64_insn, 29, 30) == 0x03;
3594 record_buf[0] = reg_rd;
3595 aarch64_insn_r->reg_rec_count = 1;
3596 if (setflags)
3597 record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_CPSR_REGNUM;
3598 }
3599 else
3600 return AARCH64_RECORD_UNKNOWN;
3601
3602 REG_ALLOC (aarch64_insn_r->aarch64_regs, aarch64_insn_r->reg_rec_count,
3603 record_buf);
3604 return AARCH64_RECORD_SUCCESS;
3605}
3606
3607/* Record handler for branch, exception generation and system instructions. */
3608
3609static unsigned int
3610aarch64_record_branch_except_sys (insn_decode_record *aarch64_insn_r)
3611{
3612 struct gdbarch_tdep *tdep = gdbarch_tdep (aarch64_insn_r->gdbarch);
3613 uint8_t insn_bits24_27, insn_bits28_31, insn_bits22_23;
3614 uint32_t record_buf[4];
3615
3616 insn_bits24_27 = bits (aarch64_insn_r->aarch64_insn, 24, 27);
3617 insn_bits28_31 = bits (aarch64_insn_r->aarch64_insn, 28, 31);
3618 insn_bits22_23 = bits (aarch64_insn_r->aarch64_insn, 22, 23);
3619
3620 if (insn_bits28_31 == 0x0d)
3621 {
3622 /* Exception generation instructions. */
3623 if (insn_bits24_27 == 0x04)
3624 {
5d98d3cd
YQ		 3625 if (!bits (aarch64_insn_r->aarch64_insn, 2, 4)
3626 && !bits (aarch64_insn_r->aarch64_insn, 21, 23)
3627 && bits (aarch64_insn_r->aarch64_insn, 0, 1) == 0x01)
99afc88b
OJ		 3628 {
3629 ULONGEST svc_number;
3630
3631 regcache_raw_read_unsigned (aarch64_insn_r->regcache, 8,
3632 &svc_number);
3633 return tdep->aarch64_syscall_record (aarch64_insn_r->regcache,
3634 svc_number);
3635 }
3636 else
3637 return AARCH64_RECORD_UNSUPPORTED;
3638 }
3639 /* System instructions. */
3640 else if (insn_bits24_27 == 0x05 && insn_bits22_23 == 0x00)
3641 {
3642 uint32_t reg_rt, reg_crn;
3643
3644 reg_rt = bits (aarch64_insn_r->aarch64_insn, 0, 4);
3645 reg_crn = bits (aarch64_insn_r->aarch64_insn, 12, 15);
3646
3647 /* Record rt in case of sysl and mrs instructions. */
3648 if (bit (aarch64_insn_r->aarch64_insn, 21))
3649 {
3650 record_buf[0] = reg_rt;
3651 aarch64_insn_r->reg_rec_count = 1;
3652 }
3653 /* Record cpsr for hint and msr(immediate) instructions. */
3654 else if (reg_crn == 0x02 || reg_crn == 0x04)
3655 {
3656 record_buf[0] = AARCH64_CPSR_REGNUM;
3657 aarch64_insn_r->reg_rec_count = 1;
3658 }
3659 }
3660 /* Unconditional branch (register). */
3661 else if((insn_bits24_27 & 0x0e) == 0x06)
3662 {
3663 record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_PC_REGNUM;
3664 if (bits (aarch64_insn_r->aarch64_insn, 21, 22) == 0x01)
3665 record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_LR_REGNUM;
3666 }
3667 else
3668 return AARCH64_RECORD_UNKNOWN;
3669 }
3670 /* Unconditional branch (immediate). */
3671 else if ((insn_bits28_31 & 0x07) == 0x01 && (insn_bits24_27 & 0x0c) == 0x04)
3672 {
3673 record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_PC_REGNUM;
3674 if (bit (aarch64_insn_r->aarch64_insn, 31))
3675 record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_LR_REGNUM;
3676 }
3677 else
3678 /* Compare & branch (immediate), Test & branch (immediate) and
3679 Conditional branch (immediate). */
3680 record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_PC_REGNUM;
3681
3682 REG_ALLOC (aarch64_insn_r->aarch64_regs, aarch64_insn_r->reg_rec_count,
3683 record_buf);
3684 return AARCH64_RECORD_SUCCESS;
3685}
3686
3687/* Record handler for advanced SIMD load and store instructions. */
3688
3689static unsigned int
3690aarch64_record_asimd_load_store (insn_decode_record *aarch64_insn_r)
3691{
3692 CORE_ADDR address;
3693 uint64_t addr_offset = 0;
3694 uint32_t record_buf[24];
3695 uint64_t record_buf_mem[24];
3696 uint32_t reg_rn, reg_rt;
3697 uint32_t reg_index = 0, mem_index = 0;
3698 uint8_t opcode_bits, size_bits;
3699
3700 reg_rt = bits (aarch64_insn_r->aarch64_insn, 0, 4);
3701 reg_rn = bits (aarch64_insn_r->aarch64_insn, 5, 9);
3702 size_bits = bits (aarch64_insn_r->aarch64_insn, 10, 11);
3703 opcode_bits = bits (aarch64_insn_r->aarch64_insn, 12, 15);
3704 regcache_raw_read_unsigned (aarch64_insn_r->regcache, reg_rn, &address);
3705
3706 if (record_debug)
b277c936 3707 debug_printf ("Process record: Advanced SIMD load/store\n");
99afc88b
OJ		 3708
3709 /* Load/store single structure. */
3710 if (bit (aarch64_insn_r->aarch64_insn, 24))
3711 {
3712 uint8_t sindex, scale, selem, esize, replicate = 0;
3713 scale = opcode_bits >> 2;
3714 selem = ((opcode_bits & 0x02) |
3715 bit (aarch64_insn_r->aarch64_insn, 21)) + 1;
3716 switch (scale)
3717 {
3718 case 1:
3719 if (size_bits & 0x01)
3720 return AARCH64_RECORD_UNKNOWN;
3721 break;
3722 case 2:
3723 if ((size_bits >> 1) & 0x01)
3724 return AARCH64_RECORD_UNKNOWN;
3725 if (size_bits & 0x01)
3726 {
3727 if (!((opcode_bits >> 1) & 0x01))
3728 scale = 3;
3729 else
3730 return AARCH64_RECORD_UNKNOWN;
3731 }
3732 break;
3733 case 3:
3734 if (bit (aarch64_insn_r->aarch64_insn, 22) && !(opcode_bits & 0x01))
3735 {
3736 scale = size_bits;
3737 replicate = 1;
3738 break;
3739 }
3740 else
3741 return AARCH64_RECORD_UNKNOWN;
3742 default:
3743 break;
3744 }
3745 esize = 8 << scale;
3746 if (replicate)
3747 for (sindex = 0; sindex < selem; sindex++)
3748 {
3749 record_buf[reg_index++] = reg_rt + AARCH64_V0_REGNUM;
3750 reg_rt = (reg_rt + 1) % 32;
3751 }
3752 else
3753 {
3754 for (sindex = 0; sindex < selem; sindex++)
a2e3e93f
SM		 3755 {
3756 if (bit (aarch64_insn_r->aarch64_insn, 22))
3757 record_buf[reg_index++] = reg_rt + AARCH64_V0_REGNUM;
3758 else
3759 {
3760 record_buf_mem[mem_index++] = esize / 8;
3761 record_buf_mem[mem_index++] = address + addr_offset;
3762 }
3763 addr_offset = addr_offset + (esize / 8);
3764 reg_rt = (reg_rt + 1) % 32;
3765 }
99afc88b
OJ		 3766 }
3767 }
3768 /* Load/store multiple structure. */
3769 else
3770 {
3771 uint8_t selem, esize, rpt, elements;
3772 uint8_t eindex, rindex;
3773
3774 esize = 8 << size_bits;
3775 if (bit (aarch64_insn_r->aarch64_insn, 30))
3776 elements = 128 / esize;
3777 else
3778 elements = 64 / esize;
3779
3780 switch (opcode_bits)
3781 {
3782 /*LD/ST4 (4 Registers). */
3783 case 0:
3784 rpt = 1;
3785 selem = 4;
3786 break;
3787 /*LD/ST1 (4 Registers). */
3788 case 2:
3789 rpt = 4;
3790 selem = 1;
3791 break;
3792 /*LD/ST3 (3 Registers). */
3793 case 4:
3794 rpt = 1;
3795 selem = 3;
3796 break;
3797 /*LD/ST1 (3 Registers). */
3798 case 6:
3799 rpt = 3;
3800 selem = 1;
3801 break;
3802 /*LD/ST1 (1 Register). */
3803 case 7:
3804 rpt = 1;
3805 selem = 1;
3806 break;
3807 /*LD/ST2 (2 Registers). */
3808 case 8:
3809 rpt = 1;
3810 selem = 2;
3811 break;
3812 /*LD/ST1 (2 Registers). */
3813 case 10:
3814 rpt = 2;
3815 selem = 1;
3816 break;
3817 default:
3818 return AARCH64_RECORD_UNSUPPORTED;
3819 break;
3820 }
3821 for (rindex = 0; rindex < rpt; rindex++)
3822 for (eindex = 0; eindex < elements; eindex++)
3823 {
3824 uint8_t reg_tt, sindex;
3825 reg_tt = (reg_rt + rindex) % 32;
3826 for (sindex = 0; sindex < selem; sindex++)
3827 {
3828 if (bit (aarch64_insn_r->aarch64_insn, 22))
3829 record_buf[reg_index++] = reg_tt + AARCH64_V0_REGNUM;
3830 else
3831 {
3832 record_buf_mem[mem_index++] = esize / 8;
3833 record_buf_mem[mem_index++] = address + addr_offset;
3834 }
3835 addr_offset = addr_offset + (esize / 8);
3836 reg_tt = (reg_tt + 1) % 32;
3837 }
3838 }
3839 }
3840
3841 if (bit (aarch64_insn_r->aarch64_insn, 23))
3842 record_buf[reg_index++] = reg_rn;
3843
3844 aarch64_insn_r->reg_rec_count = reg_index;
3845 aarch64_insn_r->mem_rec_count = mem_index / 2;
3846 MEM_ALLOC (aarch64_insn_r->aarch64_mems, aarch64_insn_r->mem_rec_count,
3847 record_buf_mem);
3848 REG_ALLOC (aarch64_insn_r->aarch64_regs, aarch64_insn_r->reg_rec_count,
3849 record_buf);
3850 return AARCH64_RECORD_SUCCESS;
3851}
3852
3853/* Record handler for load and store instructions. */
3854
3855static unsigned int
3856aarch64_record_load_store (insn_decode_record *aarch64_insn_r)
3857{
3858 uint8_t insn_bits24_27, insn_bits28_29, insn_bits10_11;
3859 uint8_t insn_bit23, insn_bit21;
3860 uint8_t opc, size_bits, ld_flag, vector_flag;
3861 uint32_t reg_rn, reg_rt, reg_rt2;
3862 uint64_t datasize, offset;
3863 uint32_t record_buf[8];
3864 uint64_t record_buf_mem[8];
3865 CORE_ADDR address;
3866
3867 insn_bits10_11 = bits (aarch64_insn_r->aarch64_insn, 10, 11);
3868 insn_bits24_27 = bits (aarch64_insn_r->aarch64_insn, 24, 27);
3869 insn_bits28_29 = bits (aarch64_insn_r->aarch64_insn, 28, 29);
3870 insn_bit21 = bit (aarch64_insn_r->aarch64_insn, 21);
3871 insn_bit23 = bit (aarch64_insn_r->aarch64_insn, 23);
3872 ld_flag = bit (aarch64_insn_r->aarch64_insn, 22);
3873 vector_flag = bit (aarch64_insn_r->aarch64_insn, 26);
3874 reg_rt = bits (aarch64_insn_r->aarch64_insn, 0, 4);
3875 reg_rn = bits (aarch64_insn_r->aarch64_insn, 5, 9);
3876 reg_rt2 = bits (aarch64_insn_r->aarch64_insn, 10, 14);
3877 size_bits = bits (aarch64_insn_r->aarch64_insn, 30, 31);
3878
3879 /* Load/store exclusive. */
3880 if (insn_bits24_27 == 0x08 && insn_bits28_29 == 0x00)
3881 {
3882 if (record_debug)
b277c936 3883 debug_printf ("Process record: load/store exclusive\n");
99afc88b
OJ		 3884
3885 if (ld_flag)
3886 {
3887 record_buf[0] = reg_rt;
3888 aarch64_insn_r->reg_rec_count = 1;
3889 if (insn_bit21)
3890 {
3891 record_buf[1] = reg_rt2;
3892 aarch64_insn_r->reg_rec_count = 2;
3893 }
3894 }
3895 else
3896 {
3897 if (insn_bit21)
3898 datasize = (8 << size_bits) * 2;
3899 else
3900 datasize = (8 << size_bits);
3901 regcache_raw_read_unsigned (aarch64_insn_r->regcache, reg_rn,
3902 &address);
3903 record_buf_mem[0] = datasize / 8;
3904 record_buf_mem[1] = address;
3905 aarch64_insn_r->mem_rec_count = 1;
3906 if (!insn_bit23)
3907 {
3908 /* Save register rs. */
3909 record_buf[0] = bits (aarch64_insn_r->aarch64_insn, 16, 20);
3910 aarch64_insn_r->reg_rec_count = 1;
3911 }
3912 }
3913 }
3914 /* Load register (literal) instructions decoding. */
3915 else if ((insn_bits24_27 & 0x0b) == 0x08 && insn_bits28_29 == 0x01)
3916 {
3917 if (record_debug)
b277c936 3918 debug_printf ("Process record: load register (literal)\n");
99afc88b
OJ		 3919 if (vector_flag)
3920 record_buf[0] = reg_rt + AARCH64_V0_REGNUM;
3921 else
3922 record_buf[0] = reg_rt;
3923 aarch64_insn_r->reg_rec_count = 1;
3924 }
3925 /* All types of load/store pair instructions decoding. */
3926 else if ((insn_bits24_27 & 0x0a) == 0x08 && insn_bits28_29 == 0x02)
3927 {
3928 if (record_debug)
b277c936 3929 debug_printf ("Process record: load/store pair\n");
99afc88b
OJ		 3930
3931 if (ld_flag)
3932 {
3933 if (vector_flag)
3934 {
3935 record_buf[0] = reg_rt + AARCH64_V0_REGNUM;
3936 record_buf[1] = reg_rt2 + AARCH64_V0_REGNUM;
3937 }
3938 else
3939 {
3940 record_buf[0] = reg_rt;
3941 record_buf[1] = reg_rt2;
3942 }
3943 aarch64_insn_r->reg_rec_count = 2;
3944 }
3945 else
3946 {
3947 uint16_t imm7_off;
3948 imm7_off = bits (aarch64_insn_r->aarch64_insn, 15, 21);
3949 if (!vector_flag)
3950 size_bits = size_bits >> 1;
3951 datasize = 8 << (2 + size_bits);
3952 offset = (imm7_off & 0x40) ? (~imm7_off & 0x007f) + 1 : imm7_off;
3953 offset = offset << (2 + size_bits);
3954 regcache_raw_read_unsigned (aarch64_insn_r->regcache, reg_rn,
3955 &address);
3956 if (!((insn_bits24_27 & 0x0b) == 0x08 && insn_bit23))
3957 {
3958 if (imm7_off & 0x40)
3959 address = address - offset;
3960 else
3961 address = address + offset;
3962 }
3963
3964 record_buf_mem[0] = datasize / 8;
3965 record_buf_mem[1] = address;
3966 record_buf_mem[2] = datasize / 8;
3967 record_buf_mem[3] = address + (datasize / 8);
3968 aarch64_insn_r->mem_rec_count = 2;
3969 }
3970 if (bit (aarch64_insn_r->aarch64_insn, 23))
3971 record_buf[aarch64_insn_r->reg_rec_count++] = reg_rn;
3972 }
3973 /* Load/store register (unsigned immediate) instructions. */
3974 else if ((insn_bits24_27 & 0x0b) == 0x09 && insn_bits28_29 == 0x03)
3975 {
3976 opc = bits (aarch64_insn_r->aarch64_insn, 22, 23);
3977 if (!(opc >> 1))
33877125
YQ		 3978 {
3979 if (opc & 0x01)
3980 ld_flag = 0x01;
3981 else
3982 ld_flag = 0x0;
3983 }
99afc88b 3984 else
33877125 3985 {
1e2b521d
YQ		 3986 if (size_bits == 0x3 && vector_flag == 0x0 && opc == 0x2)
3987 {
3988 /* PRFM (immediate) */
3989 return AARCH64_RECORD_SUCCESS;
3990 }
3991 else if (size_bits == 0x2 && vector_flag == 0x0 && opc == 0x2)
3992 {
3993 /* LDRSW (immediate) */
3994 ld_flag = 0x1;
3995 }
33877125 3996 else
1e2b521d
YQ		 3997 {
3998 if (opc & 0x01)
3999 ld_flag = 0x01;
4000 else
4001 ld_flag = 0x0;
4002 }
33877125 4003 }
99afc88b
OJ		 4004
4005 if (record_debug)
4006 {
b277c936
PL		 4007 debug_printf ("Process record: load/store (unsigned immediate):"
4008 " size %x V %d opc %x\n", size_bits, vector_flag,
4009 opc);
99afc88b
OJ		 4010 }
4011
4012 if (!ld_flag)
4013 {
4014 offset = bits (aarch64_insn_r->aarch64_insn, 10, 21);
4015 datasize = 8 << size_bits;
4016 regcache_raw_read_unsigned (aarch64_insn_r->regcache, reg_rn,
4017 &address);
4018 offset = offset << size_bits;
4019 address = address + offset;
4020
4021 record_buf_mem[0] = datasize >> 3;
4022 record_buf_mem[1] = address;
4023 aarch64_insn_r->mem_rec_count = 1;
4024 }
4025 else
4026 {
4027 if (vector_flag)
4028 record_buf[0] = reg_rt + AARCH64_V0_REGNUM;
4029 else
4030 record_buf[0] = reg_rt;
4031 aarch64_insn_r->reg_rec_count = 1;
4032 }
4033 }
4034 /* Load/store register (register offset) instructions. */
5d98d3cd
YQ		 4035 else if ((insn_bits24_27 & 0x0b) == 0x08 && insn_bits28_29 == 0x03
4036 && insn_bits10_11 == 0x02 && insn_bit21)
99afc88b
OJ		 4037 {
4038 if (record_debug)
b277c936 4039 debug_printf ("Process record: load/store (register offset)\n");
99afc88b
OJ		 4040 opc = bits (aarch64_insn_r->aarch64_insn, 22, 23);
4041 if (!(opc >> 1))
4042 if (opc & 0x01)
4043 ld_flag = 0x01;
4044 else
4045 ld_flag = 0x0;
4046 else
4047 if (size_bits != 0x03)
4048 ld_flag = 0x01;
4049 else
4050 return AARCH64_RECORD_UNKNOWN;
4051
4052 if (!ld_flag)
4053 {
d9436c7c
PA		 4054 ULONGEST reg_rm_val;
4055
99afc88b
OJ		 4056 regcache_raw_read_unsigned (aarch64_insn_r->regcache,
4057 bits (aarch64_insn_r->aarch64_insn, 16, 20), &reg_rm_val);
4058 if (bit (aarch64_insn_r->aarch64_insn, 12))
4059 offset = reg_rm_val << size_bits;
4060 else
4061 offset = reg_rm_val;
4062 datasize = 8 << size_bits;
4063 regcache_raw_read_unsigned (aarch64_insn_r->regcache, reg_rn,
4064 &address);
4065 address = address + offset;
4066 record_buf_mem[0] = datasize >> 3;
4067 record_buf_mem[1] = address;
4068 aarch64_insn_r->mem_rec_count = 1;
4069 }
4070 else
4071 {
4072 if (vector_flag)
4073 record_buf[0] = reg_rt + AARCH64_V0_REGNUM;
4074 else
4075 record_buf[0] = reg_rt;
4076 aarch64_insn_r->reg_rec_count = 1;
4077 }
4078 }
4079 /* Load/store register (immediate and unprivileged) instructions. */
5d98d3cd
YQ		 4080 else if ((insn_bits24_27 & 0x0b) == 0x08 && insn_bits28_29 == 0x03
4081 && !insn_bit21)
99afc88b
OJ		 4082 {
4083 if (record_debug)
4084 {
b277c936
PL		 4085 debug_printf ("Process record: load/store "
4086 "(immediate and unprivileged)\n");
99afc88b
OJ		 4087 }
4088 opc = bits (aarch64_insn_r->aarch64_insn, 22, 23);
4089 if (!(opc >> 1))
4090 if (opc & 0x01)
4091 ld_flag = 0x01;
4092 else
4093 ld_flag = 0x0;
4094 else
4095 if (size_bits != 0x03)
4096 ld_flag = 0x01;
4097 else
4098 return AARCH64_RECORD_UNKNOWN;
4099
4100 if (!ld_flag)
4101 {
4102 uint16_t imm9_off;
4103 imm9_off = bits (aarch64_insn_r->aarch64_insn, 12, 20);
4104 offset = (imm9_off & 0x0100) ? (((~imm9_off) & 0x01ff) + 1) : imm9_off;
4105 datasize = 8 << size_bits;
4106 regcache_raw_read_unsigned (aarch64_insn_r->regcache, reg_rn,
4107 &address);
4108 if (insn_bits10_11 != 0x01)
4109 {
4110 if (imm9_off & 0x0100)
4111 address = address - offset;
4112 else
4113 address = address + offset;
4114 }
4115 record_buf_mem[0] = datasize >> 3;
4116 record_buf_mem[1] = address;
4117 aarch64_insn_r->mem_rec_count = 1;
4118 }
4119 else
4120 {
4121 if (vector_flag)
4122 record_buf[0] = reg_rt + AARCH64_V0_REGNUM;
4123 else
4124 record_buf[0] = reg_rt;
4125 aarch64_insn_r->reg_rec_count = 1;
4126 }
4127 if (insn_bits10_11 == 0x01 || insn_bits10_11 == 0x03)
4128 record_buf[aarch64_insn_r->reg_rec_count++] = reg_rn;
4129 }
4130 /* Advanced SIMD load/store instructions. */
4131 else
4132 return aarch64_record_asimd_load_store (aarch64_insn_r);
4133
4134 MEM_ALLOC (aarch64_insn_r->aarch64_mems, aarch64_insn_r->mem_rec_count,
4135 record_buf_mem);
4136 REG_ALLOC (aarch64_insn_r->aarch64_regs, aarch64_insn_r->reg_rec_count,
4137 record_buf);
4138 return AARCH64_RECORD_SUCCESS;
4139}
4140
4141/* Record handler for data processing SIMD and floating point instructions. */
4142
4143static unsigned int
4144aarch64_record_data_proc_simd_fp (insn_decode_record *aarch64_insn_r)
4145{
4146 uint8_t insn_bit21, opcode, rmode, reg_rd;
4147 uint8_t insn_bits24_27, insn_bits28_31, insn_bits10_11, insn_bits12_15;
4148 uint8_t insn_bits11_14;
4149 uint32_t record_buf[2];
4150
4151 insn_bits24_27 = bits (aarch64_insn_r->aarch64_insn, 24, 27);
4152 insn_bits28_31 = bits (aarch64_insn_r->aarch64_insn, 28, 31);
4153 insn_bits10_11 = bits (aarch64_insn_r->aarch64_insn, 10, 11);
4154 insn_bits12_15 = bits (aarch64_insn_r->aarch64_insn, 12, 15);
4155 insn_bits11_14 = bits (aarch64_insn_r->aarch64_insn, 11, 14);
4156 opcode = bits (aarch64_insn_r->aarch64_insn, 16, 18);
4157 rmode = bits (aarch64_insn_r->aarch64_insn, 19, 20);
4158 reg_rd = bits (aarch64_insn_r->aarch64_insn, 0, 4);
4159 insn_bit21 = bit (aarch64_insn_r->aarch64_insn, 21);
4160
4161 if (record_debug)
b277c936 4162 debug_printf ("Process record: data processing SIMD/FP: ");
99afc88b
OJ		 4163
4164 if ((insn_bits28_31 & 0x05) == 0x01 && insn_bits24_27 == 0x0e)
4165 {
4166 /* Floating point - fixed point conversion instructions. */
4167 if (!insn_bit21)
4168 {
4169 if (record_debug)
b277c936 4170 debug_printf ("FP - fixed point conversion");
99afc88b
OJ		 4171
4172 if ((opcode >> 1) == 0x0 && rmode == 0x03)
4173 record_buf[0] = reg_rd;
4174 else
4175 record_buf[0] = reg_rd + AARCH64_V0_REGNUM;
4176 }
4177 /* Floating point - conditional compare instructions. */
4178 else if (insn_bits10_11 == 0x01)
4179 {
4180 if (record_debug)
b277c936 4181 debug_printf ("FP - conditional compare");
99afc88b
OJ		 4182
4183 record_buf[0] = AARCH64_CPSR_REGNUM;
4184 }
4185 /* Floating point - data processing (2-source) and
4186 conditional select instructions. */
4187 else if (insn_bits10_11 == 0x02 || insn_bits10_11 == 0x03)
4188 {
4189 if (record_debug)
b277c936 4190 debug_printf ("FP - DP (2-source)");
99afc88b
OJ		 4191
4192 record_buf[0] = reg_rd + AARCH64_V0_REGNUM;
4193 }
4194 else if (insn_bits10_11 == 0x00)
4195 {
4196 /* Floating point - immediate instructions. */
4197 if ((insn_bits12_15 & 0x01) == 0x01
4198 || (insn_bits12_15 & 0x07) == 0x04)
4199 {
4200 if (record_debug)
b277c936 4201 debug_printf ("FP - immediate");
99afc88b
OJ		 4202 record_buf[0] = reg_rd + AARCH64_V0_REGNUM;
4203 }
4204 /* Floating point - compare instructions. */
4205 else if ((insn_bits12_15 & 0x03) == 0x02)
4206 {
4207 if (record_debug)
b277c936 4208 debug_printf ("FP - immediate");
99afc88b
OJ		 4209 record_buf[0] = AARCH64_CPSR_REGNUM;
4210 }
4211 /* Floating point - integer conversions instructions. */
f62fce35 4212 else if (insn_bits12_15 == 0x00)
99afc88b
OJ		 4213 {
4214 /* Convert float to integer instruction. */
4215 if (!(opcode >> 1) || ((opcode >> 1) == 0x02 && !rmode))
4216 {
4217 if (record_debug)
b277c936 4218 debug_printf ("float to int conversion");
99afc88b
OJ		 4219
4220 record_buf[0] = reg_rd + AARCH64_X0_REGNUM;
4221 }
4222 /* Convert integer to float instruction. */
4223 else if ((opcode >> 1) == 0x01 && !rmode)
4224 {
4225 if (record_debug)
b277c936 4226 debug_printf ("int to float conversion");
99afc88b
OJ		 4227
4228 record_buf[0] = reg_rd + AARCH64_V0_REGNUM;
4229 }
4230 /* Move float to integer instruction. */
4231 else if ((opcode >> 1) == 0x03)
4232 {
4233 if (record_debug)
b277c936 4234 debug_printf ("move float to int");
99afc88b
OJ		 4235
4236 if (!(opcode & 0x01))
4237 record_buf[0] = reg_rd + AARCH64_X0_REGNUM;
4238 else
4239 record_buf[0] = reg_rd + AARCH64_V0_REGNUM;
4240 }
f62fce35
YQ		 4241 else
4242 return AARCH64_RECORD_UNKNOWN;
99afc88b 4243 }
f62fce35
YQ		 4244 else
4245 return AARCH64_RECORD_UNKNOWN;
99afc88b 4246 }
f62fce35
YQ		 4247 else
4248 return AARCH64_RECORD_UNKNOWN;
99afc88b
OJ		 4249 }
4250 else if ((insn_bits28_31 & 0x09) == 0x00 && insn_bits24_27 == 0x0e)
4251 {
4252 if (record_debug)
b277c936 4253 debug_printf ("SIMD copy");
99afc88b
OJ		 4254
4255 /* Advanced SIMD copy instructions. */
4256 if (!bits (aarch64_insn_r->aarch64_insn, 21, 23)
4257 && !bit (aarch64_insn_r->aarch64_insn, 15)
4258 && bit (aarch64_insn_r->aarch64_insn, 10))
4259 {
4260 if (insn_bits11_14 == 0x05 || insn_bits11_14 == 0x07)
4261 record_buf[0] = reg_rd + AARCH64_X0_REGNUM;
4262 else
4263 record_buf[0] = reg_rd + AARCH64_V0_REGNUM;
4264 }
4265 else
4266 record_buf[0] = reg_rd + AARCH64_V0_REGNUM;
4267 }
4268 /* All remaining floating point or advanced SIMD instructions. */
4269 else
4270 {
4271 if (record_debug)
b277c936 4272 debug_printf ("all remain");
99afc88b
OJ		 4273
4274 record_buf[0] = reg_rd + AARCH64_V0_REGNUM;
4275 }
4276
4277 if (record_debug)
b277c936 4278 debug_printf ("\n");
99afc88b
OJ		 4279
4280 aarch64_insn_r->reg_rec_count++;
4281 gdb_assert (aarch64_insn_r->reg_rec_count == 1);
4282 REG_ALLOC (aarch64_insn_r->aarch64_regs, aarch64_insn_r->reg_rec_count,
4283 record_buf);
4284 return AARCH64_RECORD_SUCCESS;
4285}
4286
4287/* Decodes insns type and invokes its record handler. */
4288
4289static unsigned int
4290aarch64_record_decode_insn_handler (insn_decode_record *aarch64_insn_r)
4291{
4292 uint32_t ins_bit25, ins_bit26, ins_bit27, ins_bit28;
4293
4294 ins_bit25 = bit (aarch64_insn_r->aarch64_insn, 25);
4295 ins_bit26 = bit (aarch64_insn_r->aarch64_insn, 26);
4296 ins_bit27 = bit (aarch64_insn_r->aarch64_insn, 27);
4297 ins_bit28 = bit (aarch64_insn_r->aarch64_insn, 28);
4298
4299 /* Data processing - immediate instructions. */
4300 if (!ins_bit26 && !ins_bit27 && ins_bit28)
4301 return aarch64_record_data_proc_imm (aarch64_insn_r);
4302
4303 /* Branch, exception generation and system instructions. */
4304 if (ins_bit26 && !ins_bit27 && ins_bit28)
4305 return aarch64_record_branch_except_sys (aarch64_insn_r);
4306
4307 /* Load and store instructions. */
4308 if (!ins_bit25 && ins_bit27)
4309 return aarch64_record_load_store (aarch64_insn_r);
4310
4311 /* Data processing - register instructions. */
4312 if (ins_bit25 && !ins_bit26 && ins_bit27)
4313 return aarch64_record_data_proc_reg (aarch64_insn_r);
4314
4315 /* Data processing - SIMD and floating point instructions. */
4316 if (ins_bit25 && ins_bit26 && ins_bit27)
4317 return aarch64_record_data_proc_simd_fp (aarch64_insn_r);
4318
4319 return AARCH64_RECORD_UNSUPPORTED;
4320}
4321
4322/* Cleans up local record registers and memory allocations. */
4323
4324static void
4325deallocate_reg_mem (insn_decode_record *record)
4326{
4327 xfree (record->aarch64_regs);
4328 xfree (record->aarch64_mems);
4329}
4330
1e2b521d
YQ		 4331#if GDB_SELF_TEST
4332namespace selftests {
4333
4334static void
4335aarch64_process_record_test (void)
4336{
4337 struct gdbarch_info info;
4338 uint32_t ret;
4339
4340 gdbarch_info_init (&info);
4341 info.bfd_arch_info = bfd_scan_arch ("aarch64");
4342
4343 struct gdbarch *gdbarch = gdbarch_find_by_info (info);
4344 SELF_CHECK (gdbarch != NULL);
4345
4346 insn_decode_record aarch64_record;
4347
4348 memset (&aarch64_record, 0, sizeof (insn_decode_record));
4349 aarch64_record.regcache = NULL;
4350 aarch64_record.this_addr = 0;
4351 aarch64_record.gdbarch = gdbarch;
4352
4353 /* 20 00 80 f9 prfm pldl1keep, [x1] */
4354 aarch64_record.aarch64_insn = 0xf9800020;
4355 ret = aarch64_record_decode_insn_handler (&aarch64_record);
4356 SELF_CHECK (ret == AARCH64_RECORD_SUCCESS);
4357 SELF_CHECK (aarch64_record.reg_rec_count == 0);
4358 SELF_CHECK (aarch64_record.mem_rec_count == 0);
4359
4360 deallocate_reg_mem (&aarch64_record);
4361}
4362
4363} // namespace selftests
4364#endif /* GDB_SELF_TEST */
4365
99afc88b
OJ		 4366/* Parse the current instruction and record the values of the registers and
4367 memory that will be changed in current instruction to record_arch_list
4368 return -1 if something is wrong. */
4369
4370int
4371aarch64_process_record (struct gdbarch *gdbarch, struct regcache *regcache,
4372 CORE_ADDR insn_addr)
4373{
4374 uint32_t rec_no = 0;
4375 uint8_t insn_size = 4;
4376 uint32_t ret = 0;
99afc88b
OJ		 4377 gdb_byte buf[insn_size];
4378 insn_decode_record aarch64_record;
4379
4380 memset (&buf[0], 0, insn_size);
4381 memset (&aarch64_record, 0, sizeof (insn_decode_record));
4382 target_read_memory (insn_addr, &buf[0], insn_size);
4383 aarch64_record.aarch64_insn
4384 = (uint32_t) extract_unsigned_integer (&buf[0],
4385 insn_size,
4386 gdbarch_byte_order (gdbarch));
4387 aarch64_record.regcache = regcache;
4388 aarch64_record.this_addr = insn_addr;
4389 aarch64_record.gdbarch = gdbarch;
4390
4391 ret = aarch64_record_decode_insn_handler (&aarch64_record);
4392 if (ret == AARCH64_RECORD_UNSUPPORTED)
4393 {
4394 printf_unfiltered (_("Process record does not support instruction "
4395 "0x%0x at address %s.\n"),
4396 aarch64_record.aarch64_insn,
4397 paddress (gdbarch, insn_addr));
4398 ret = -1;
4399 }
4400
4401 if (0 == ret)
4402 {
4403 /* Record registers. */
4404 record_full_arch_list_add_reg (aarch64_record.regcache,
4405 AARCH64_PC_REGNUM);
4406 /* Always record register CPSR. */
4407 record_full_arch_list_add_reg (aarch64_record.regcache,
4408 AARCH64_CPSR_REGNUM);
4409 if (aarch64_record.aarch64_regs)
4410 for (rec_no = 0; rec_no < aarch64_record.reg_rec_count; rec_no++)
4411 if (record_full_arch_list_add_reg (aarch64_record.regcache,
4412 aarch64_record.aarch64_regs[rec_no]))
4413 ret = -1;
4414
4415 /* Record memories. */
4416 if (aarch64_record.aarch64_mems)
4417 for (rec_no = 0; rec_no < aarch64_record.mem_rec_count; rec_no++)
4418 if (record_full_arch_list_add_mem
4419 ((CORE_ADDR)aarch64_record.aarch64_mems[rec_no].addr,
4420 aarch64_record.aarch64_mems[rec_no].len))
4421 ret = -1;
4422
4423 if (record_full_arch_list_add_end ())
4424 ret = -1;
4425 }
4426
4427 deallocate_reg_mem (&aarch64_record);
4428 return ret;
4429}
GDB Binutils - Deliverables
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