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tic4x: sign extension using shifts
[deliverable/binutils-gdb.git] / include / opcode / tic4x.h
CommitLineData
026df7c5
NC		 1/* Table of opcodes for the Texas Instruments TMS320C[34]X family.
2
b3adc24a 3 Copyright (C) 2002-2020 Free Software Foundation, Inc.
026df7c5
NC		 4
5 Contributed by Michael P. Hayes (m.hayes@elec.canterbury.ac.nz)
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
e4e42b45 9 the Free Software Foundation; either version 3 of the License, or
026df7c5
NC		 10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
e4e42b45
NC		 19 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
20 MA 02110-1301, USA. */
026df7c5 21
be33c5dd
SS		 22#define IS_CPU_TIC3X(v) ((v) == 30 || (v) == 31 || (v) == 32 || (v) == 33)
23#define IS_CPU_TIC4X(v) ((v) == 0 || (v) == 40 || (v) == 44)
026df7c5
NC		 24
25/* Define some bitfield extraction/insertion macros. */
5496abe1
AM		 26#define EXTRU(inst, m, l) \
27 (((inst) >> (l)) & ((2u << ((m) - (l))) - 1))
28#define EXTRS(inst, m, l) \
29 ((int) ((EXTRU (inst, m, l) ^ (1u << ((m) - (l)))) - (1u << ((m) - (l)))))
30#define INSERTU(inst, val, m, l) \
31 ((inst) |= ((val) & ((2u << ((m) - (l))) - 1)) << (l))
32#define INSERTS INSERTU
026df7c5
NC		 33
34/* Define register numbers. */
35typedef enum
36 {
37 REG_R0, REG_R1, REG_R2, REG_R3,
38 REG_R4, REG_R5, REG_R6, REG_R7,
39 REG_AR0, REG_AR1, REG_AR2, REG_AR3,
40 REG_AR4, REG_AR5, REG_AR6, REG_AR7,
41 REG_DP, REG_IR0, REG_IR1, REG_BK,
42 REG_SP, REG_ST, REG_DIE, REG_IIE,
43 REG_IIF, REG_RS, REG_RE, REG_RC,
44 REG_R8, REG_R9, REG_R10, REG_R11,
45 REG_IVTP, REG_TVTP
46 }
47c4x_reg_t;
48
49/* Note that the actual register numbers for IVTP is 0 and TVTP is 1. */
50
51#define REG_IE REG_DIE /* C3x only */
52#define REG_IF REG_IIE /* C3x only */
53#define REG_IOF REG_IIF /* C3x only */
54
be33c5dd
SS		 55#define TIC3X_REG_MAX REG_RC
56#define TIC4X_REG_MAX REG_TVTP
026df7c5
NC		 57
58/* Register table size including C4x expansion regs. */
be33c5dd 59#define REG_TABLE_SIZE (TIC4X_REG_MAX + 1)
026df7c5 60
be33c5dd 61struct tic4x_register
026df7c5 62{
f86f5863 63 const char * name;
026df7c5
NC		 64 unsigned long regno;
65};
66
be33c5dd 67typedef struct tic4x_register tic4x_register_t;
026df7c5
NC		 68
69/* We could store register synonyms here. */
be33c5dd 70static const tic4x_register_t tic3x_registers[] =
026df7c5
NC		 71{
72 {"f0", REG_R0},
73 {"r0", REG_R0},
74 {"f1", REG_R1},
75 {"r1", REG_R1},
76 {"f2", REG_R2},
77 {"r2", REG_R2},
78 {"f3", REG_R3},
79 {"r3", REG_R3},
80 {"f4", REG_R4},
81 {"r4", REG_R4},
82 {"f5", REG_R5},
83 {"r5", REG_R5},
84 {"f6", REG_R6},
85 {"r6", REG_R6},
86 {"f7", REG_R7},
87 {"r7", REG_R7},
88 {"ar0", REG_AR0},
89 {"ar1", REG_AR1},
90 {"ar2", REG_AR2},
91 {"ar3", REG_AR3},
92 {"ar4", REG_AR4},
93 {"ar5", REG_AR5},
94 {"ar6", REG_AR6},
95 {"ar7", REG_AR7},
96 {"dp", REG_DP},
97 {"ir0", REG_IR0},
98 {"ir1", REG_IR1},
99 {"bk", REG_BK},
100 {"sp", REG_SP},
101 {"st", REG_ST},
102 {"ie", REG_IE},
103 {"if", REG_IF},
104 {"iof", REG_IOF},
105 {"rs", REG_RS},
106 {"re", REG_RE},
107 {"rc", REG_RC},
108 {"", 0}
109};
110
be33c5dd 111const unsigned int tic3x_num_registers = (((sizeof tic3x_registers) / (sizeof tic3x_registers[0])) - 1);
026df7c5
NC		 112
113/* Define C4x registers in addition to C3x registers. */
be33c5dd 114static const tic4x_register_t tic4x_registers[] =
026df7c5
NC		 115{
116 {"die", REG_DIE}, /* Clobbers C3x REG_IE */
117 {"iie", REG_IIE}, /* Clobbers C3x REG_IF */
118 {"iif", REG_IIF}, /* Clobbers C3x REG_IOF */
119 {"f8", REG_R8},
120 {"r8", REG_R8},
121 {"f9", REG_R9},
122 {"r9", REG_R9},
123 {"f10", REG_R10},
124 {"r10", REG_R10},
125 {"f11", REG_R11},
126 {"r11", REG_R11},
127 {"ivtp", REG_IVTP},
128 {"tvtp", REG_TVTP},
129 {"", 0}
130};
131
be33c5dd 132const unsigned int tic4x_num_registers = (((sizeof tic4x_registers) / (sizeof tic4x_registers[0])) - 1);
026df7c5 133
be33c5dd 134struct tic4x_cond
9c87d6c7 135{
f86f5863 136 const char * name;
9c87d6c7
SS		 137 unsigned long cond;
138};
139
be33c5dd 140typedef struct tic4x_cond tic4x_cond_t;
9c87d6c7
SS		 141
142/* Define conditional branch/load suffixes. Put desired form for
143 disassembler last. */
be33c5dd 144static const tic4x_cond_t tic4x_conds[] =
9c87d6c7
SS		 145{
146 { "u", 0x00 },
147 { "c", 0x01 }, { "lo", 0x01 },
148 { "ls", 0x02 },
149 { "hi", 0x03 },
150 { "nc", 0x04 }, { "hs", 0x04 },
151 { "z", 0x05 }, { "eq", 0x05 },
152 { "nz", 0x06 }, { "ne", 0x06 },
153 { "n", 0x07 }, { "l", 0x07 }, { "lt", 0x07 },
154 { "le", 0x08 },
155 { "p", 0x09 }, { "gt", 0x09 },
156 { "nn", 0x0a }, { "ge", 0x0a },
157 { "nv", 0x0c },
158 { "v", 0x0d },
159 { "nuf", 0x0e },
160 { "uf", 0x0f },
161 { "nlv", 0x10 },
162 { "lv", 0x11 },
163 { "nluf", 0x12 },
164 { "luf", 0x13 },
165 { "zuf", 0x14 },
166 /* Dummy entry, not included in num_conds. This
167 lets code examine entry i+1 without checking
168 if we've run off the end of the table. */
169 { "", 0x0}
170};
171
be33c5dd 172const unsigned int tic4x_num_conds = (((sizeof tic4x_conds) / (sizeof tic4x_conds[0])) - 1);
9c87d6c7 173
be33c5dd 174struct tic4x_indirect
9c87d6c7 175{
f86f5863 176 const char * name;
9c87d6c7
SS		 177 unsigned long modn;
178};
179
be33c5dd 180typedef struct tic4x_indirect tic4x_indirect_t;
9c87d6c7
SS		 181
182/* Define indirect addressing modes where:
183 d displacement (signed)
184 y ir0
185 z ir1 */
186
be33c5dd 187static const tic4x_indirect_t tic4x_indirects[] =
9c87d6c7
SS		 188{
189 { "*+a(d)", 0x00 },
190 { "*-a(d)", 0x01 },
191 { "*++a(d)", 0x02 },
192 { "*--a(d)", 0x03 },
193 { "*a++(d)", 0x04 },
194 { "*a--(d)", 0x05 },
195 { "*a++(d)%", 0x06 },
196 { "*a--(d)%", 0x07 },
197 { "*+a(y)", 0x08 },
198 { "*-a(y)", 0x09 },
199 { "*++a(y)", 0x0a },
200 { "*--a(y)", 0x0b },
201 { "*a++(y)", 0x0c },
202 { "*a--(y)", 0x0d },
203 { "*a++(y)%", 0x0e },
204 { "*a--(y)%", 0x0f },
205 { "*+a(z)", 0x10 },
206 { "*-a(z)", 0x11 },
207 { "*++a(z)", 0x12 },
208 { "*--a(z)", 0x13 },
209 { "*a++(z)", 0x14 },
210 { "*a--(z)", 0x15 },
211 { "*a++(z)%", 0x16 },
212 { "*a--(z)%", 0x17 },
213 { "*a", 0x18 },
214 { "*a++(y)b", 0x19 },
215 /* Dummy entry, not included in num_indirects. This
216 lets code examine entry i+1 without checking
217 if we've run off the end of the table. */
218 { "", 0x0}
219};
220
be33c5dd 221#define TIC3X_MODN_MAX 0x19
9c87d6c7 222
be33c5dd 223const unsigned int tic4x_num_indirects = (((sizeof tic4x_indirects) / (sizeof tic4x_indirects[0])) - 1);
9c87d6c7 224
026df7c5 225/* Instruction template. */
be33c5dd 226struct tic4x_inst
026df7c5 227{
f86f5863 228 const char * name;
026df7c5
NC		 229 unsigned long opcode;
230 unsigned long opmask;
b9bb4a93 231 const char * args;
44287f60 232 unsigned long oplevel;
026df7c5
NC		 233};
234
be33c5dd 235typedef struct tic4x_inst tic4x_inst_t;
026df7c5 236
44287f60
SS		 237/* Opcode infix
238 B condition 16--20 U,C,Z,LO,HI, etc.
239 C condition 23--27 U,C,Z,LO,HI, etc.
240
241 Arguments
026df7c5
NC		 242 , required arg follows
243 ; optional arg follows
44287f60
SS		 244
245 Argument types bits [classes] - example
246 -----------------------------------------------------------
247 * indirect (all) 0--15 [A,AB,AU,AF,A2,A3,A6,A7,AY,B,BA,BB,BI,B6,B7] - *+AR0(5), *++AR0(IR0)
248 # direct (for LDP) 0--15 [Z] - @start, start
249 @ direct 0--15 [A,AB,AU,AF,A3,A6,A7,AY,B,BA,BB,BI,B6,B7] - @start, start
250 A address register 22--24 [D] - AR0, AR7
251 B unsigned integer 0--23 [I,I2] - @start, start (absolute on C3x, relative on C4x)
252 C indirect (disp - C4x) 0--7 [S,SC,S2,T,TC,T2,T2C] - *+AR0(5)
253 E register (all) 0--7 [T,TC,T2,T2C] - R0, R7, R11, AR0, DP
254 e register (0-11) 0--7 [S,SC,S2] - R0, R7, R11
255 F short float immediate 0--15 [AF,B,BA,BB] - 3.5, 0e-3.5e-1
256 G register (all) 8--15 [T,TC,T2,T2C] - R0, R7, R11, AR0, DP
257 g register (0-11) 0--7 [S,SC,S2] - R0, R7, R11
258 H register (0-7) 18--16 [LS,M,P,Q] - R0, R7
9c87d6c7
SS		 259 I indirect (no disp) 0--7 [S,SC,S2,T,TC,T2,T2C] - *+AR0(1), *+AR0(IR0)
260 i indirect (enhanced) 0--7 [LL,LS,M,P,Q,QC] - *+AR0(1), R5
261 J indirect (no disp) 8--15 [LL,LS,P,Q,QC,S,SC,S2,T,TC,T2,T2C] - *+AR0(1), *+AR0(IR0)
262 j indirect (enhanced) 8--15 [M] - *+AR0(1), R5
44287f60
SS		 263 K register 19--21 [LL,M,Q,QC] - R0, R7
264 L register 22--24 [LL,LS,P,Q,QC] - R0, R7
265 M register (R2,R3) 22--22 [M] R2, R3
266 N register (R0,R1) 23--23 [M] R0, R1
267 O indirect(disp - C4x) 8--15 [S,SC,S2,T,TC,T2] - *+AR0(5)
268 P displacement (PC Rel) 0--15 [D,J,JS] - @start, start
269 Q register (all) 0--15 [A,AB,AU,A2,A3,AY,BA,BI,D,I2,J,JS] - R0, AR0, DP, SP
270 q register (0-11) 0--15 [AF,B,BB] - R0, R7, R11
271 R register (all) 16--20 [A,AB,AU,AF,A6,A7,R,T,TC] - R0, AR0, DP, SP
272 r register (0-11) 16--20 [B,BA,BB,BI,B6,B7,RF,S,SC] - R0, R1, R11
273 S short int immediate 0--15 [A,AB,AY,BI] - -5, 5
274 T integer (C4x) 16--20 [Z] - -5, 12
275 U unsigned integer 0--15 [AU,A3] - 0, 65535
276 V vector (C4x: 0--8) 0--4 [Z] - 25, 7
277 W short int (C4x) 0--7 [T,TC,T2,T2C] - -3, 5
278 X expansion reg (C4x) 0--4 [Z] - IVTP, TVTP
279 Y address reg (C4x) 16--20 [Z] - AR0, DP, SP, IR0
280 Z expansion reg (C4x) 16--20 [Z] - IVTP, TVTP
281*/
026df7c5 282
be33c5dd
SS		 283#define TIC4X_OPERANDS_MAX 7 /* Max number of operands for an inst. */
284#define TIC4X_NAME_MAX 16 /* Max number of chars in parallel name. */
026df7c5 285
44287f60 286/* Define the instruction level */
9c87d6c7
SS		 287#define OP_C3X 0x1 /* C30 support - supported by all */
288#define OP_C4X 0x2 /* C40 support - C40, C44 */
289#define OP_ENH 0x4 /* Class LL,LS,M,P,Q,QC enhancements. Argument type
290 I and J is enhanced in these classes - C31>=6.0,
291 C32>=2.0, C33 */
292#define OP_LPWR 0x8 /* Low power support (LOPOWER, MAXSPEED) - C30>=7.0,
293 LC31, C31>=5.0, C32 */
294#define OP_IDLE2 0x10 /* Idle2 support (IDLE2) - C30>=7.0, LC31, C31>=5.0,
295 C32, C33, C40>=5.0, C44 */
44287f60
SS		 296
297/* The following class definition is a classification scheme for
298 putting instructions with similar type of arguments together. It
299 simplifies the op-code definitions significantly, as we then only
300 need to use the class macroes for 95% of the DSP's opcodes.
301*/
302
303/* A: General 2-operand integer operations
304 Syntax: <i> src, dst
305 src = Register (Q), Direct (@), Indirect (*), Signed immediate (S)
306 dst = Register (R)
307 Instr: 15/8 - ABSI, ADDC, ADDI, ASH, CMPI, LDI, LSH, MPYI, NEGB, NEGI,
308 SUBB, SUBC, SUBI, SUBRB, SUBRI, C4x: LBn, LHn, LWLn, LWRn,
309 MBn, MHn, MPYSHI, MPYUHI
310*/
311#define A_CLASS_INSN(name, opcode, level) \
312 { name, opcode|0x00000000, 0xffe00000, "Q;R", level }, \
313 { name, opcode|0x00200000, 0xffe00000, "@,R", level }, \
314 { name, opcode|0x00400000, 0xffe00000, "*,R", level }, \
315 { name, opcode|0x00600000, 0xffe00000, "S,R", level }
316
317/* AB: General 2-operand integer operation with condition
318 Syntax: <i>c src, dst
319 c = Condition
320 src = Register (Q), Direct (@), Indirect (*), Signed immediate (S)
321 dst = Register (R)
322 Instr: 1/0 - LDIc
323*/
324#define AB_CLASS_INSN(name, opcode, level) \
325 { name, opcode|0x40000000, 0xf0600000, "Q;R", level }, \
326 { name, opcode|0x40200000, 0xf0600000, "@,R", level }, \
327 { name, opcode|0x40400000, 0xf0600000, "*,R", level }, \
328 { name, opcode|0x40600000, 0xf0600000, "S,R", level }
329
330/* AU: General 2-operand unsigned integer operation
331 Syntax: <i> src, dst
332 src = Register (Q), Direct (@), Indirect (*), Unsigned immediate (U)
333 dst = Register (R)
334 Instr: 6/2 - AND, ANDN, NOT, OR, TSTB, XOR, C4x: LBUn, LHUn
335*/
336#define AU_CLASS_INSN(name, opcode, level) \
337 { name, opcode|0x00000000, 0xffe00000, "Q;R", level }, \
338 { name, opcode|0x00200000, 0xffe00000, "@,R", level }, \
339 { name, opcode|0x00400000, 0xffe00000, "*,R", level }, \
340 { name, opcode|0x00600000, 0xffe00000, "U,R", level }
341
342/* AF: General 2-operand float to integer operation
343 Syntax: <i> src, dst
344 src = Register 0-11 (q), Direct (@), Indirect (*), Float immediate (F)
345 dst = Register (R)
346 Instr: 1/0 - FIX
347*/
348#define AF_CLASS_INSN(name, opcode, level) \
349 { name, opcode|0x00000000, 0xffe00000, "q;R", level }, \
350 { name, opcode|0x00200000, 0xffe00000, "@,R", level }, \
351 { name, opcode|0x00400000, 0xffe00000, "*,R", level }, \
352 { name, opcode|0x00600000, 0xffe00000, "F,R", level }
353
354/* A2: Limited 1-operand (integer) operation
355 Syntax: <i> src
356 src = Register (Q), Indirect (*), None
357 Instr: 1/0 - NOP
358*/
359#define A2_CLASS_INSN(name, opcode, level) \
360 { name, opcode|0x00000000, 0xffe00000, "Q", level }, \
361 { name, opcode|0x00400000, 0xffe00000, "*", level }, \
362 { name, opcode|0x00000000, 0xffe00000, "" , level }
363
364/* A3: General 1-operand unsigned integer operation
365 Syntax: <i> src
366 src = Register (Q), Direct (@), Indirect (*), Unsigned immediate (U)
367 Instr: 1/0 - RPTS
368*/
369#define A3_CLASS_INSN(name, opcode, level) \
370 { name, opcode|0x00000000, 0xffff0000, "Q", level }, \
371 { name, opcode|0x00200000, 0xffff0000, "@", level }, \
372 { name, opcode|0x00400000, 0xffff0000, "*", level }, \
373 { name, opcode|0x00600000, 0xffff0000, "U", level }
374
375/* A6: Limited 2-operand integer operation
376 Syntax: <i> src, dst
377 src = Direct (@), Indirect (*)
378 dst = Register (R)
379 Instr: 1/1 - LDII, C4x: SIGI
380*/
381#define A6_CLASS_INSN(name, opcode, level) \
382 { name, opcode|0x00200000, 0xffe00000, "@,R", level }, \
383 { name, opcode|0x00400000, 0xffe00000, "*,R", level }
384
385/* A7: Limited 2-operand integer store operation
386 Syntax: <i> src, dst
387 src = Register (R)
388 dst = Direct (@), Indirect (*)
389 Instr: 2/0 - STI, STII
390*/
391#define A7_CLASS_INSN(name, opcode, level) \
392 { name, opcode|0x00200000, 0xffe00000, "R,@", level }, \
393 { name, opcode|0x00400000, 0xffe00000, "R,*", level }
394
395/* AY: General 2-operand signed address load operation
396 Syntax: <i> src, dst
397 src = Register (Q), Direct (@), Indirect (*), Signed immediate (S)
398 dst = Address register - ARx, IRx, DP, BK, SP (Y)
399 Instr: 0/1 - C4x: LDA
400 Note: Q and Y should *never* be the same register
401*/
402#define AY_CLASS_INSN(name, opcode, level) \
403 { name, opcode|0x00000000, 0xffe00000, "Q,Y", level }, \
404 { name, opcode|0x00200000, 0xffe00000, "@,Y", level }, \
405 { name, opcode|0x00400000, 0xffe00000, "*,Y", level }, \
406 { name, opcode|0x00600000, 0xffe00000, "S,Y", level }
407
408/* B: General 2-operand float operation
409 Syntax: <i> src, dst
410 src = Register 0-11 (q), Direct (@), Indirect (*), Float immediate (F)
411 dst = Register 0-11 (r)
412 Instr: 12/2 - ABSF, ADDF, CMPF, LDE, LDF, LDM, MPYF, NEGF, NORM, RND,
413 SUBF, SUBRF, C4x: RSQRF, TOIEEE
414*/
415#define B_CLASS_INSN(name, opcode, level) \
416 { name, opcode|0x00000000, 0xffe00000, "q;r", level }, \
417 { name, opcode|0x00200000, 0xffe00000, "@,r", level }, \
418 { name, opcode|0x00400000, 0xffe00000, "*,r", level }, \
419 { name, opcode|0x00600000, 0xffe00000, "F,r", level }
420
421/* BA: General 2-operand integer to float operation
422 Syntax: <i> src, dst
423 src = Register (Q), Direct (@), Indirect (*), Float immediate (F)
424 dst = Register 0-11 (r)
425 Instr: 0/1 - C4x: CRCPF
426*/
427#define BA_CLASS_INSN(name, opcode, level) \
428 { name, opcode|0x00000000, 0xffe00000, "Q;r", level }, \
429 { name, opcode|0x00200000, 0xffe00000, "@,r", level }, \
430 { name, opcode|0x00400000, 0xffe00000, "*,r", level }, \
431 { name, opcode|0x00600000, 0xffe00000, "F,r", level }
432
433/* BB: General 2-operand conditional float operation
434 Syntax: <i>c src, dst
435 c = Condition
436 src = Register 0-11 (q), Direct (@), Indirect (*), Float immediate (F)
437 dst = Register 0-11 (r)
438 Instr: 1/0 - LDFc
439*/
440#define BB_CLASS_INSN(name, opcode, level) \
441 { name, opcode|0x40000000, 0xf0600000, "q;r", level }, \
442 { name, opcode|0x40200000, 0xf0600000, "@,r", level }, \
443 { name, opcode|0x40400000, 0xf0600000, "*,r", level }, \
444 { name, opcode|0x40600000, 0xf0600000, "F,r", level }
445
446/* BI: General 2-operand integer to float operation (yet different to BA)
447 Syntax: <i> src, dst
448 src = Register (Q), Direct (@), Indirect (*), Signed immediate (S)
449 dst = Register 0-11 (r)
450 Instr: 1/0 - FLOAT
451*/
452#define BI_CLASS_INSN(name, opcode, level) \
453 { name, opcode|0x00000000, 0xffe00000, "Q;r", level }, \
454 { name, opcode|0x00200000, 0xffe00000, "@,r", level }, \
455 { name, opcode|0x00400000, 0xffe00000, "*,r", level }, \
456 { name, opcode|0x00600000, 0xffe00000, "S,r", level }
457
458/* B6: Limited 2-operand float operation
459 Syntax: <i> src, dst
460 src = Direct (@), Indirect (*)
461 dst = Register 0-11 (r)
462 Instr: 1/1 - LDFI, C4x: FRIEEE
463*/
464#define B6_CLASS_INSN(name, opcode, level) \
465 { name, opcode|0x00200000, 0xffe00000, "@,r", level }, \
466 { name, opcode|0x00400000, 0xffe00000, "*,r", level }
467
468/* B7: Limited 2-operand float store operation
469 Syntax: <i> src, dst
470 src = Register 0-11 (r)
471 dst = Direct (@), Indirect (*)
472 Instr: 2/0 - STF, STFI
473*/
474#define B7_CLASS_INSN(name, opcode, level) \
475 { name, opcode|0x00200000, 0xffe00000, "r,@", level }, \
476 { name, opcode|0x00400000, 0xffe00000, "r,*", level }
477
478/* D: Decrement and brach operations
479 Syntax: <i>c ARn, dst
480 c = condition
481 ARn = AR register 0-7 (A)
482 dst = Register (Q), PC-relative (P)
483 Instr: 2/0 - DBc, DBcD
484 Alias: <name1> <name2>
485*/
486#define D_CLASS_INSN(name1, name2, opcode, level) \
487 { name1, opcode|0x00000000, 0xfe200000, "A,Q", level }, \
488 { name1, opcode|0x02000000, 0xfe200000, "A,P", level }, \
489 { name2, opcode|0x00000000, 0xfe200000, "A,Q", level }, \
490 { name2, opcode|0x02000000, 0xfe200000, "A,P", level }
491
492/* I: General branch operations
493 Syntax: <i> dst
494 dst = Address (B)
495 Instr: 3/1 - BR, BRD, CALL, C4x: LAJ
496*/
497
498/* I2: General branch operations (C4x addition)
499 Syntax: <i> dst
500 dst = Address (B), C4x: Register (Q)
501 Instr: 2/0 - RPTB, RPTBD
502*/
503
504/* J: General conditional branch operations
505 Syntax: <i>c dst
506 c = Condition
507 dst = Register (Q), PC-relative (P)
508 Instr: 2/3 - Bc, BcD, C4x: BcAF, BcAT, LAJc
509 Alias: <name1> <name2>
510*/
511#define J_CLASS_INSN(name1, name2, opcode, level) \
512 { name1, opcode|0x00000000, 0xffe00000, "Q", level }, \
513 { name1, opcode|0x02000000, 0xffe00000, "P", level }, \
514 { name2, opcode|0x00000000, 0xffe00000, "Q", level }, \
515 { name2, opcode|0x02000000, 0xffe00000, "P", level }
516
517/* JS: General conditional branch operations
518 Syntax: <i>c dst
519 c = Condition
520 dst = Register (Q), PC-relative (P)
521 Instr: 1/1 - CALLc, C4X: LAJc
522*/
523
524/* LL: Load-load parallell operation
525 Syntax: <i> src2, dst2 || <i> src1, dst1
526 src1 = Indirect 0,1,IR0,IR1 (J)
527 dst1 = Register 0-7 (K)
9c87d6c7 528 src2 = Indirect 0,1,IR0,IR1, ENH: Register (i)
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SS		 529 dst2 = Register 0-7 (L)
530 Instr: 2/0 - LDF||LDF, LDI||LDI
531 Alias: i||i, i1||i2, i2||i1
532*/
533#define LL_CLASS_INSN(name, opcode, level) \
9c87d6c7
SS		 534 { name "_" name , opcode, 0xfe000000, "i;L|J,K", level }, \
535 { name "2_" name "1", opcode, 0xfe000000, "i;L|J,K", level }, \
536 { name "1_" name "2", opcode, 0xfe000000, "J,K|i;L", level }
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SS		 537
538/* LS: Store-store parallell operation
539 Syntax: <i> src2, dst2 || <i> src1, dst1
540 src1 = Register 0-7 (H)
541 dst1 = Indirect 0,1,IR0,IR1 (J)
542 src2 = Register 0-7 (L)
9c87d6c7 543 dst2 = Indirect 0,1,IR0,IR1, ENH: register (i)
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SS		 544 Instr: 2/0 - STF||STF, STI||STI
545 Alias: i||i, i1||i2, i2||i1.
546*/
547#define LS_CLASS_INSN(name, opcode, level) \
9c87d6c7
SS		 548 { name "_" name , opcode, 0xfe000000, "L;i|H,J", level }, \
549 { name "2_" name "1", opcode, 0xfe000000, "L;i|H,J", level }, \
550 { name "1_" name "2", opcode, 0xfe000000, "H,J|L;i", level }
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SS		 551
552/* M: General multiply and add/sub operations
553 Syntax: <ia> src3,src4,dst1 || <ib> src2,src1,dst2 [00] - Manual
554 <ia> src3,src1,dst1 || <ib> src2,src4,dst2 [01] - Manual
555 <ia> src1,src3,dst1 || <ib> src2,src4,dst2 [01]
556 <ia> src1,src2,dst1 || <ib> src4,src3,dst2 [02] - Manual
557 <ia> src3,src1,dst1 || <ib> src4,src2,dst2 [03] - Manual
558 <ia> src1,src3,dst1 || <ib> src4,src2,dst2 [03]
559 src1 = Register 0-7 (K)
560 src2 = Register 0-7 (H)
9c87d6c7
SS		 561 src3 = Indirect 0,1,IR0,IR1, ENH: register (j)
562 src4 = Indirect 0,1,IR0,IR1, ENH: register (i)
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SS		 563 dst1 = Register 0-1 (N)
564 dst2 = Register 2-3 (M)
565 Instr: 4/0 - MPYF3||ADDF3, MPYF3||SUBF3, MPYI3||ADDI3, MPYI3||SUBI3
566 Alias: a||b, a3||n, a||b3, a3||b3, b||a, b3||a, b||a3, b3||a3
567*/
568#define M_CLASS_INSN(namea, nameb, opcode, level) \
9c87d6c7
SS		 569 { namea "_" nameb, opcode|0x00000000, 0xff000000, "i;j;N|H;K;M", level }, \
570 { namea "_" nameb, opcode|0x01000000, 0xff000000, "j;K;N|H;i;M", level }, \
571 { namea "_" nameb, opcode|0x01000000, 0xff000000, "K;j;N|H;i;M", level }, \
572 { namea "_" nameb, opcode|0x02000000, 0xff000000, "H;K;N|i;j;M", level }, \
573 { namea "_" nameb, opcode|0x03000000, 0xff000000, "j;K;N|i;H;M", level }, \
574 { namea "_" nameb, opcode|0x03000000, 0xff000000, "K;j;N|i;H;M", level }, \
575 { namea "3_" nameb, opcode|0x00000000, 0xff000000, "i;j;N|H;K;M", level }, \
576 { namea "3_" nameb, opcode|0x01000000, 0xff000000, "j;K;N|H;i;M", level }, \
577 { namea "3_" nameb, opcode|0x01000000, 0xff000000, "K;j;N|H;i;M", level }, \
578 { namea "3_" nameb, opcode|0x02000000, 0xff000000, "H;K;N|i;j;M", level }, \
579 { namea "3_" nameb, opcode|0x03000000, 0xff000000, "j;K;N|i;H;M", level }, \
580 { namea "3_" nameb, opcode|0x03000000, 0xff000000, "K;j;N|i;H;M", level }, \
581 { namea "_" nameb "3", opcode|0x00000000, 0xff000000, "i;j;N|H;K;M", level }, \
582 { namea "_" nameb "3", opcode|0x01000000, 0xff000000, "j;K;N|H;i;M", level }, \
583 { namea "_" nameb "3", opcode|0x01000000, 0xff000000, "K;j;N|H;i;M", level }, \
584 { namea "_" nameb "3", opcode|0x02000000, 0xff000000, "H;K;N|i;j;M", level }, \
585 { namea "_" nameb "3", opcode|0x03000000, 0xff000000, "j;K;N|i;H;M", level }, \
586 { namea "_" nameb "3", opcode|0x03000000, 0xff000000, "K;j;N|i;H;M", level }, \
587 { namea "3_" nameb "3", opcode|0x00000000, 0xff000000, "i;j;N|H;K;M", level }, \
588 { namea "3_" nameb "3", opcode|0x01000000, 0xff000000, "j;K;N|H;i;M", level }, \
589 { namea "3_" nameb "3", opcode|0x01000000, 0xff000000, "K;j;N|H;i;M", level }, \
590 { namea "3_" nameb "3", opcode|0x02000000, 0xff000000, "H;K;N|i;j;M", level }, \
591 { namea "3_" nameb "3", opcode|0x03000000, 0xff000000, "j;K;N|i;H;M", level }, \
592 { namea "3_" nameb "3", opcode|0x03000000, 0xff000000, "K;j;N|i;H;M", level }, \
593 { nameb "_" namea, opcode|0x00000000, 0xff000000, "H;K;M|i;j;N", level }, \
594 { nameb "_" namea, opcode|0x01000000, 0xff000000, "H;i;M|j;K;N", level }, \
595 { nameb "_" namea, opcode|0x01000000, 0xff000000, "H;i;M|K;j;N", level }, \
596 { nameb "_" namea, opcode|0x02000000, 0xff000000, "i;j;M|H;K;N", level }, \
597 { nameb "_" namea, opcode|0x03000000, 0xff000000, "i;H;M|j;K;N", level }, \
598 { nameb "_" namea, opcode|0x03000000, 0xff000000, "i;H;M|K;j;N", level }, \
599 { nameb "3_" namea, opcode|0x00000000, 0xff000000, "H;K;M|i;j;N", level }, \
600 { nameb "3_" namea, opcode|0x01000000, 0xff000000, "H;i;M|j;K;N", level }, \
601 { nameb "3_" namea, opcode|0x01000000, 0xff000000, "H;i;M|K;j;N", level }, \
602 { nameb "3_" namea, opcode|0x02000000, 0xff000000, "i;j;M|H;K;N", level }, \
603 { nameb "3_" namea, opcode|0x03000000, 0xff000000, "i;H;M|j;K;N", level }, \
604 { nameb "3_" namea, opcode|0x03000000, 0xff000000, "i;H;M|K;j;N", level }, \
605 { nameb "_" namea "3", opcode|0x00000000, 0xff000000, "H;K;M|i;j;N", level }, \
606 { nameb "_" namea "3", opcode|0x01000000, 0xff000000, "H;i;M|j;K;N", level }, \
607 { nameb "_" namea "3", opcode|0x01000000, 0xff000000, "H;i;M|K;j;N", level }, \
608 { nameb "_" namea "3", opcode|0x02000000, 0xff000000, "i;j;M|H;K;N", level }, \
609 { nameb "_" namea "3", opcode|0x03000000, 0xff000000, "i;H;M|j;K;N", level }, \
610 { nameb "_" namea "3", opcode|0x03000000, 0xff000000, "i;H;M|K;j;N", level }, \
611 { nameb "3_" namea "3", opcode|0x00000000, 0xff000000, "H;K;M|i;j;N", level }, \
612 { nameb "3_" namea "3", opcode|0x01000000, 0xff000000, "H;i;M|j;K;N", level }, \
613 { nameb "3_" namea "3", opcode|0x01000000, 0xff000000, "H;i;M|K;j;N", level }, \
614 { nameb "3_" namea "3", opcode|0x02000000, 0xff000000, "i;j;M|H;K;N", level }, \
615 { nameb "3_" namea "3", opcode|0x03000000, 0xff000000, "i;H;M|j;K;N", level }, \
616 { nameb "3_" namea "3", opcode|0x03000000, 0xff000000, "i;H;M|K;j;N", level }
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SS		 617
618/* P: General 2-operand operation with parallell store
619 Syntax: <ia> src2, dst1 || <ib> src3, dst2
9c87d6c7 620 src2 = Indirect 0,1,IR0,IR1, ENH: register (i)
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SS		 621 dst1 = Register 0-7 (L)
622 src3 = Register 0-7 (H)
623 dst2 = Indirect 0,1,IR0,IR1 (J)
624 Instr: 9/2 - ABSF||STF, ABSI||STI, FIX||STI, FLOAT||STF, LDF||STF,
625 LDI||STI, NEGF||STF, NEGI||STI, NOT||STI, C4x: FRIEEE||STF,
626 TOIEEE||STF
627 Alias: a||b, b||a
628*/
629#define P_CLASS_INSN(namea, nameb, opcode, level) \
9c87d6c7
SS		 630 { namea "_" nameb, opcode, 0xfe000000, "i;L|H,J", level }, \
631 { nameb "_" namea, opcode, 0xfe000000, "H,J|i;L", level }
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SS		 632
633/* Q: General 3-operand operation with parallell store
634 Syntax: <ia> src1, src2, dst1 || <ib> src3, dst2
635 src1 = Register 0-7 (K)
9c87d6c7 636 src2 = Indirect 0,1,IR0,IR1, ENH: register (i)
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SS		 637 dst1 = Register 0-7 (L)
638 src3 = Register 0-7 (H)
639 dst2 = Indirect 0,1,IR0,IR1 (J)
640 Instr: 4/0 - ASH3||STI, LSH3||STI, SUBF3||STF, SUBI3||STI
641 Alias: a||b, b||a, a3||b, b||a3
642*/
643#define Q_CLASS_INSN(namea, nameb, opcode, level) \
9c87d6c7
SS		 644 { namea "_" nameb , opcode, 0xfe000000, "K,i;L|H,J", level }, \
645 { nameb "_" namea , opcode, 0xfe000000, "H,J|K,i;L", level }, \
646 { namea "3_" nameb , opcode, 0xfe000000, "K,i;L|H,J", level }, \
647 { nameb "_" namea "3", opcode, 0xfe000000, "H,J|K,i;L", level }
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SS		 648
649/* QC: General commutative 3-operand operation with parallell store
650 Syntax: <ia> src2, src1, dst1 || <ib> src3, dst2
651 <ia> src1, src2, dst1 || <ib> src3, dst2 - Manual
652 src1 = Register 0-7 (K)
9c87d6c7 653 src2 = Indirect 0,1,IR0,IR1, ENH: register (i)
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SS		 654 dst1 = Register 0-7 (L)
655 src3 = Register 0-7 (H)
656 dst2 = Indirect 0,1,IR0,IR1 (J)
657 Instr: 7/0 - ADDF3||STF, ADDI3||STI, AND3||STI, MPYF3||STF, MPYI3||STI,
658 OR3||STI, XOR3||STI
659 Alias: a||b, b||a, a3||b, b||a3
660*/
661#define QC_CLASS_INSN(namea, nameb, opcode, level) \
9c87d6c7
SS		 662 { namea "_" nameb , opcode, 0xfe000000, "i;K;L|H,J", level }, \
663 { namea "_" nameb , opcode, 0xfe000000, "K;i;L|H,J", level }, \
664 { nameb "_" namea , opcode, 0xfe000000, "H,J|i;K;L", level }, \
665 { nameb "_" namea , opcode, 0xfe000000, "H,J|K;i;L", level }, \
666 { namea "3_" nameb , opcode, 0xfe000000, "i;K;L|H,J", level }, \
667 { namea "3_" nameb , opcode, 0xfe000000, "K;i;L|H,J", level }, \
668 { nameb "_" namea "3", opcode, 0xfe000000, "H,J|i;K;L", level }, \
669 { nameb "_" namea "3", opcode, 0xfe000000, "H,J|K;i;L", level }
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SS		 670
671/* R: General register integer operation
672 Syntax: <i> dst
673 dst = Register (R)
674 Instr: 6/0 - POP, PUSH, ROL, ROLC, ROR, RORC
675*/
676#define R_CLASS_INSN(name, opcode, level) \
677 { name, opcode, 0xffe0ffff, "R", level }
678
679/* RF: General register float operation
680 Syntax: <i> dst
681 dst = Register 0-11 (r)
682 Instr: 2/0 - POPF, PUSHF
683*/
684#define RF_CLASS_INSN(name, opcode, level) \
685 { name, opcode, 0xffe0ffff, "r", level }
686
687/* S: General 3-operand float operation
688 Syntax: <i> src2, src1, dst
689 src2 = Register 0-11 (e), Indirect 0,1,IR0,IR1 (I), C4x T2: Indirect (C)
690 src1 = Register 0-11 (g), Indirect 0,1,IR0,IR1 (J), C4x T2: Indirect (O)
691 dst = Register 0-11 (r)
692 Instr: 1/0 - SUBF3
693 Alias: i, i3
694*/
695#define S_CLASS_INSN(name, opcode, level) \
696 { name, opcode|0x20000000, 0xffe00000, "e,g;r", level }, \
697 { name, opcode|0x20200000, 0xffe00000, "e,J,r", level }, \
698 { name, opcode|0x20400000, 0xffe00000, "I,g;r", level }, \
699 { name, opcode|0x20600000, 0xffe00000, "I,J,r", level }, \
700 { name, opcode|0x30200000, 0xffe00000, "C,g;r", OP_C4X }, \
701 { name, opcode|0x30600000, 0xffe00000, "C,O,r", OP_C4X }, \
702 { name "3", opcode|0x20000000, 0xffe00000, "e,g;r", level }, \
703 { name "3", opcode|0x20200000, 0xffe00000, "e,J,r", level }, \
704 { name "3", opcode|0x20400000, 0xffe00000, "I,g;r", level }, \
705 { name "3", opcode|0x20600000, 0xffe00000, "I,J,r", level }, \
706 { name "3", opcode|0x30200000, 0xffe00000, "C,g;r", OP_C4X }, \
707 { name "3", opcode|0x30600000, 0xffe00000, "C,O,r", OP_C4X }
708
709/* SC: General commutative 3-operand float operation
710 Syntax: <i> src2, src1, dst - Manual
711 <i> src1, src2, dst
712 src2 = Register 0-11 (e), Indirect 0,1,IR0,IR1 (I), C4x T2: Indirect (C)
713 src1 = Register 0-11 (g), Indirect 0,1,IR0,IR1 (J), C4x T2: Indirect (O)
714 dst = Register 0-11 (r)
715 Instr: 2/0 - ADDF3, MPYF3
716 Alias: i, i3
717*/
718#define SC_CLASS_INSN(name, opcode, level) \
719 { name, opcode|0x20000000, 0xffe00000, "e,g;r", level }, \
720 { name, opcode|0x20200000, 0xffe00000, "e,J,r", level }, \
721 { name, opcode|0x20400000, 0xffe00000, "I,g;r", level }, \
722 { name, opcode|0x20600000, 0xffe00000, "I,J,r", level }, \
723 { name, opcode|0x30200000, 0xffe00000, "C,g;r", OP_C4X }, \
724 { name, opcode|0x30200000, 0xffe00000, "g,C,r", OP_C4X }, \
725 { name, opcode|0x30600000, 0xffe00000, "C,O,r", OP_C4X }, \
726 { name "3", opcode|0x20000000, 0xffe00000, "e,g;r", level }, \
727 { name "3", opcode|0x20200000, 0xffe00000, "e,J,r", level }, \
728 { name "3", opcode|0x20400000, 0xffe00000, "I,g;r", level }, \
729 { name "3", opcode|0x20600000, 0xffe00000, "I,J,r", level }, \
730 { name "3", opcode|0x30200000, 0xffe00000, "g,C,r", OP_C4X }, \
731 { name "3", opcode|0x30200000, 0xffe00000, "C,g;r", OP_C4X }, \
732 { name "3", opcode|0x30600000, 0xffe00000, "C,O,r", OP_C4X }
733
734/* S2: General 3-operand float operation with 2 args
735 Syntax: <i> src2, src1
736 src2 = Register 0-11 (e), Indirect 0,1,IR0,IR1 (I), C4x T2: Indirect (C)
737 src1 = Register 0-11 (g), Indirect 0,1,IR0,IR1 (J), C4x T2: Indirect (O)
738 Instr: 1/0 - CMPF3
739 Alias: i, i3
740*/
741#define S2_CLASS_INSN(name, opcode, level) \
742 { name, opcode|0x20000000, 0xffe00000, "e,g", level }, \
743 { name, opcode|0x20200000, 0xffe00000, "e,J", level }, \
744 { name, opcode|0x20400000, 0xffe00000, "I,g", level }, \
745 { name, opcode|0x20600000, 0xffe00000, "I,J", level }, \
746 { name, opcode|0x30200000, 0xffe00000, "C,g", OP_C4X }, \
747 { name, opcode|0x30600000, 0xffe00000, "C,O", OP_C4X }, \
748 { name "3", opcode|0x20000000, 0xffe00000, "e,g", level }, \
749 { name "3", opcode|0x20200000, 0xffe00000, "e,J", level }, \
750 { name "3", opcode|0x20400000, 0xffe00000, "I,g", level }, \
751 { name "3", opcode|0x20600000, 0xffe00000, "I,J", level }, \
752 { name "3", opcode|0x30200000, 0xffe00000, "C,g", OP_C4X }, \
753 { name "3", opcode|0x30600000, 0xffe00000, "C,O", OP_C4X }
754
755/* T: General 3-operand integer operand
756 Syntax: <i> src2, src1, dst
757 src2 = Register (E), Indirect 0,1,IR0,IR1 (I), C4x T2: Indirect (C), Immediate (W)
758 src1 = Register (G), Indirect 0,1,IR0,IR1 (J), C4x T2: Indirect (O)
759 dst = Register (R)
760 Instr: 5/0 - ANDN3, ASH3, LSH3, SUBB3, SUBI3
761 Alias: i, i3
762*/
763#define T_CLASS_INSN(name, opcode, level) \
764 { name, opcode|0x20000000, 0xffe00000, "E,G;R", level }, \
765 { name, opcode|0x20200000, 0xffe00000, "E,J,R", level }, \
766 { name, opcode|0x20400000, 0xffe00000, "I,G;R", level }, \
767 { name, opcode|0x20600000, 0xffe00000, "I,J,R", level }, \
768 { name, opcode|0x30000000, 0xffe00000, "W,G;R", OP_C4X }, \
769 { name, opcode|0x30200000, 0xffe00000, "C,G;R", OP_C4X }, \
770 { name, opcode|0x30400000, 0xffe00000, "W,O,R", OP_C4X }, \
771 { name, opcode|0x30600000, 0xffe00000, "C,O,R", OP_C4X }, \
772 { name "3", opcode|0x20000000, 0xffe00000, "E,G;R", level }, \
773 { name "3", opcode|0x20200000, 0xffe00000, "E,J,R", level }, \
774 { name "3", opcode|0x20400000, 0xffe00000, "I,G;R", level }, \
775 { name "3", opcode|0x20600000, 0xffe00000, "I,J,R", level }, \
776 { name "3", opcode|0x30000000, 0xffe00000, "W,G;R", OP_C4X }, \
777 { name "3", opcode|0x30200000, 0xffe00000, "C,G;R", OP_C4X }, \
778 { name "3", opcode|0x30400000, 0xffe00000, "W,O,R", OP_C4X }, \
779 { name "3", opcode|0x30600000, 0xffe00000, "C,O,R", OP_C4X }
780
781/* TC: General commutative 3-operand integer operation
782 Syntax: <i> src2, src1, dst
783 <i> src1, src2, dst
784 src2 = Register (E), Indirect 0,1,IR0,IR1 (I), C4x T2: Indirect (C), Immediate (W)
785 src1 = Register (G), Indirect 0,1,IR0,IR1 (J), C4x T2: Indirect (O)
786 dst = Register (R)
787 Instr: 6/2 - ADDC3, ADDI3, AND3, MPYI3, OR3, XOR3, C4x: MPYSHI, MPYUHI
788 Alias: i, i3
789*/
790#define TC_CLASS_INSN(name, opcode, level) \
791 { name, opcode|0x20000000, 0xffe00000, "E,G;R", level }, \
792 { name, opcode|0x20200000, 0xffe00000, "E,J,R", level }, \
793 { name, opcode|0x20400000, 0xffe00000, "I,G;R", level }, \
794 { name, opcode|0x20600000, 0xffe00000, "I,J,R", level }, \
795 { name, opcode|0x30000000, 0xffe00000, "W,G;R", OP_C4X }, \
796 { name, opcode|0x30000000, 0xffe00000, "G,W,R", OP_C4X }, \
797 { name, opcode|0x30200000, 0xffe00000, "C,G;R", OP_C4X }, \
798 { name, opcode|0x30200000, 0xffe00000, "G,C,R", OP_C4X }, \
799 { name, opcode|0x30400000, 0xffe00000, "W,O,R", OP_C4X }, \
800 { name, opcode|0x30400000, 0xffe00000, "O,W,R", OP_C4X }, \
801 { name, opcode|0x30600000, 0xffe00000, "C,O,R", OP_C4X }, \
802 { name "3", opcode|0x20000000, 0xffe00000, "E,G;R", level }, \
803 { name "3", opcode|0x20200000, 0xffe00000, "E,J,R", level }, \
804 { name "3", opcode|0x20400000, 0xffe00000, "I,G;R", level }, \
805 { name "3", opcode|0x20600000, 0xffe00000, "I,J,R", level }, \
806 { name "3", opcode|0x30000000, 0xffe00000, "W,G;R", OP_C4X }, \
807 { name "3", opcode|0x30000000, 0xffe00000, "G,W,R", OP_C4X }, \
808 { name "3", opcode|0x30200000, 0xffe00000, "C,G;R", OP_C4X }, \
809 { name "3", opcode|0x30200000, 0xffe00000, "G,C,R", OP_C4X }, \
810 { name "3", opcode|0x30400000, 0xffe00000, "W,O,R", OP_C4X }, \
811 { name "3", opcode|0x30400000, 0xffe00000, "O,W,R", OP_C4X }, \
812 { name "3", opcode|0x30600000, 0xffe00000, "C,O,R", OP_C4X }
813
814/* T2: General 3-operand integer operation with 2 args
815 Syntax: <i> src2, src1
816 src2 = Register (E), Indirect 0,1,IR0,IR1 (I), C4x T2: Indirect (C), Immediate (W)
817 src1 = Register (G), Indirect 0,1,IR0,IR1 (J), C4x T2: Indirect (O)
818 Instr: 1/0 - CMPI3
819 Alias: i, i3
820*/
821#define T2_CLASS_INSN(name, opcode, level) \
822 { name, opcode|0x20000000, 0xffe00000, "E,G", level }, \
823 { name, opcode|0x20200000, 0xffe00000, "E,J", level }, \
824 { name, opcode|0x20400000, 0xffe00000, "I,G", level }, \
825 { name, opcode|0x20600000, 0xffe00000, "I,J", level }, \
826 { name, opcode|0x30000000, 0xffe00000, "W,G", OP_C4X }, \
827 { name, opcode|0x30200000, 0xffe00000, "C,G", OP_C4X }, \
828 { name, opcode|0x30400000, 0xffe00000, "W,O", OP_C4X }, \
829 { name, opcode|0x30600000, 0xffe00000, "C,O", OP_C4X }, \
830 { name "3", opcode|0x20000000, 0xffe00000, "E,G", level }, \
831 { name "3", opcode|0x20200000, 0xffe00000, "E,J", level }, \
832 { name "3", opcode|0x20400000, 0xffe00000, "I,G", level }, \
833 { name "3", opcode|0x20600000, 0xffe00000, "I,J", level }, \
834 { name "3", opcode|0x30000000, 0xffe00000, "W,G", OP_C4X }, \
835 { name "3", opcode|0x30200000, 0xffe00000, "C,G", OP_C4X }, \
836 { name "3", opcode|0x30400000, 0xffe00000, "W,O", OP_C4X }, \
837 { name "3", opcode|0x30600000, 0xffe00000, "C,O", OP_C4X }
838
839/* T2C: General commutative 3-operand integer operation with 2 args
840 Syntax: <i> src2, src1 - Manual
841 <i> src1, src2
842 src2 = Register (E), Indirect 0,1,IR0,IR1 (I), C4x T2: Indirect (C), Immediate (W)
843 src1 = Register (G), Indirect 0,1,IR0,IR1 (J), C4x T2: Indirect (0)
844 Instr: 1/0 - TSTB3
845 Alias: i, i3
846*/
847#define T2C_CLASS_INSN(name, opcode, level) \
848 { name, opcode|0x20000000, 0xffe00000, "E,G", level }, \
849 { name, opcode|0x20200000, 0xffe00000, "E,J", level }, \
850 { name, opcode|0x20400000, 0xffe00000, "I,G", level }, \
851 { name, opcode|0x20600000, 0xffe00000, "I,J", level }, \
852 { name, opcode|0x30000000, 0xffe00000, "W,G", OP_C4X }, \
853 { name, opcode|0x30000000, 0xffe00000, "G,W", OP_C4X }, \
854 { name, opcode|0x30200000, 0xffe00000, "C,G", OP_C4X }, \
855 { name, opcode|0x30200000, 0xffe00000, "G,C", OP_C4X }, \
856 { name, opcode|0x30400000, 0xffe00000, "W,O", OP_C4X }, \
857 { name, opcode|0x30400000, 0xffe00000, "O,W", OP_C4X }, \
858 { name, opcode|0x30600000, 0xffe00000, "C,O", OP_C4X }, \
859 { name "3", opcode|0x20000000, 0xffe00000, "E,G", level }, \
860 { name "3", opcode|0x20200000, 0xffe00000, "E,J", level }, \
861 { name "3", opcode|0x20400000, 0xffe00000, "I,G", level }, \
862 { name "3", opcode|0x20600000, 0xffe00000, "I,J", level }, \
863 { name "3", opcode|0x30000000, 0xffe00000, "W,G", OP_C4X }, \
864 { name "3", opcode|0x30000000, 0xffe00000, "G,W", OP_C4X }, \
865 { name "3", opcode|0x30200000, 0xffe00000, "C,G", OP_C4X }, \
866 { name "3", opcode|0x30200000, 0xffe00000, "G,C", OP_C4X }, \
867 { name "3", opcode|0x30400000, 0xffe00000, "W,O", OP_C4X }, \
868 { name "3", opcode|0x30400000, 0xffe00000, "O,W", OP_C4X }, \
869 { name "3", opcode|0x30600000, 0xffe00000, "C,O", OP_C4X }
870
871/* Z: Misc operations with or without arguments
872 Syntax: <i> <arg1>,...
873 Instr: 16 - RETIc, RETSc, SIGI(c3X), SWI, IDLE, IDLE2, RETIcD,
874 TRAPc, LATc, LDEP, LDEHI, LDEPE, LDPK, STIK, LDP, IACK
875*/
876
026df7c5 877
be33c5dd
SS		 878/* Define tic4x opcodes for assembler and disassembler. */
879static const tic4x_inst_t tic4x_insts[] =
026df7c5
NC		 880{
881 /* Put synonyms after the desired forms in table so that they get
882 overwritten in the lookup table. The disassembler will thus
883 print the `proper' mnemonics. Note that the disassembler
884 only decodes the 11 MSBs, so instructions like ldp @0x500 will
885 be printed as ldiu 5, dp. Note that with parallel instructions,
886 the second part is executed before the first part, unless
887 the sti1||sti2 form is used. We also allow sti2||sti1
888 which is equivalent to the default sti||sti form.
44287f60 889 */
9c87d6c7
SS		 890 B_CLASS_INSN( "absf", 0x00000000, OP_C3X ),
891 P_CLASS_INSN( "absf", "stf", 0xc8000000, OP_C3X ),
892 A_CLASS_INSN( "absi", 0x00800000, OP_C3X ),
893 P_CLASS_INSN( "absi", "sti", 0xca000000, OP_C3X ),
894 A_CLASS_INSN( "addc", 0x01000000, OP_C3X ),
895 TC_CLASS_INSN( "addc", 0x00000000, OP_C3X ),
896 B_CLASS_INSN( "addf", 0x01800000, OP_C3X ),
897 SC_CLASS_INSN( "addf", 0x00800000, OP_C3X ),
898 QC_CLASS_INSN( "addf", "stf", 0xcc000000, OP_C3X ),
899 A_CLASS_INSN( "addi", 0x02000000, OP_C3X ),
900 TC_CLASS_INSN( "addi", 0x01000000, OP_C3X ),
901 QC_CLASS_INSN( "addi", "sti", 0xce000000, OP_C3X ),
902 AU_CLASS_INSN( "and", 0x02800000, OP_C3X ),
903 TC_CLASS_INSN( "and", 0x01800000, OP_C3X ),
904 QC_CLASS_INSN( "and", "sti", 0xd0000000, OP_C3X ),
905 AU_CLASS_INSN( "andn", 0x03000000, OP_C3X ),
906 T_CLASS_INSN( "andn", 0x02000000, OP_C3X ),
907 A_CLASS_INSN( "ash", 0x03800000, OP_C3X ),
908 T_CLASS_INSN( "ash", 0x02800000, OP_C3X ),
909 Q_CLASS_INSN( "ash", "sti", 0xd2000000, OP_C3X ),
910 J_CLASS_INSN( "bB", "b", 0x68000000, OP_C3X ),
911 J_CLASS_INSN( "bBd", "bd", 0x68200000, OP_C3X ),
912 J_CLASS_INSN( "bBaf", "baf", 0x68a00000, OP_C4X ),
913 J_CLASS_INSN( "bBat", "bat", 0x68600000, OP_C4X ),
914 { "br", 0x60000000, 0xff000000, "B" , OP_C3X }, /* I_CLASS */
915 { "brd", 0x61000000, 0xff000000, "B" , OP_C3X }, /* I_CLASS */
916 { "call", 0x62000000, 0xff000000, "B" , OP_C3X }, /* I_CLASS */
917 { "callB", 0x70000000, 0xffe00000, "Q" , OP_C3X }, /* JS_CLASS */
918 { "callB", 0x72000000, 0xffe00000, "P" , OP_C3X }, /* JS_CLASS */
919 B_CLASS_INSN( "cmpf", 0x04000000, OP_C3X ),
920 S2_CLASS_INSN( "cmpf", 0x03000000, OP_C3X ),
921 A_CLASS_INSN( "cmpi", 0x04800000, OP_C3X ),
922 T2_CLASS_INSN( "cmpi", 0x03800000, OP_C3X ),
923 D_CLASS_INSN( "dbB", "db", 0x6c000000, OP_C3X ),
924 D_CLASS_INSN( "dbBd", "dbd", 0x6c200000, OP_C3X ),
925 AF_CLASS_INSN( "fix", 0x05000000, OP_C3X ),
926 P_CLASS_INSN( "fix", "sti", 0xd4000000, OP_C3X ),
927 BI_CLASS_INSN( "float", 0x05800000, OP_C3X ),
928 P_CLASS_INSN( "float", "stf", 0xd6000000, OP_C3X ),
929 B6_CLASS_INSN( "frieee", 0x1c000000, OP_C4X ),
930 P_CLASS_INSN( "frieee","stf", 0xf2000000, OP_C4X ),
931 { "iack", 0x1b200000, 0xffe00000, "@" , OP_C3X }, /* Z_CLASS */
932 { "iack", 0x1b400000, 0xffe00000, "*" , OP_C3X }, /* Z_CLASS */
933 { "idle", 0x06000000, 0xffffffff, "" , OP_C3X }, /* Z_CLASS */
934 { "idlez", 0x06000000, 0xffffffff, "" , OP_C3X }, /* Z_CLASS */
935 { "idle2", 0x06000001, 0xffffffff, "" , OP_IDLE2 }, /* Z_CLASS */
936 { "laj", 0x63000000, 0xff000000, "B" , OP_C4X }, /* I_CLASS */
937 { "lajB", 0x70200000, 0xffe00000, "Q" , OP_C4X }, /* JS_CLASS */
938 { "lajB", 0x72200000, 0xffe00000, "P" , OP_C4X }, /* JS_CLASS */
939 { "latB", 0x74800000, 0xffe00000, "V" , OP_C4X }, /* Z_CLASS */
940 A_CLASS_INSN( "lb0", 0xb0000000, OP_C4X ),
941 A_CLASS_INSN( "lb1", 0xb0800000, OP_C4X ),
942 A_CLASS_INSN( "lb2", 0xb1000000, OP_C4X ),
943 A_CLASS_INSN( "lb3", 0xb1800000, OP_C4X ),
944 AU_CLASS_INSN( "lbu0", 0xb2000000, OP_C4X ),
945 AU_CLASS_INSN( "lbu1", 0xb2800000, OP_C4X ),
946 AU_CLASS_INSN( "lbu2", 0xb3000000, OP_C4X ),
947 AU_CLASS_INSN( "lbu3", 0xb3800000, OP_C4X ),
948 AY_CLASS_INSN( "lda", 0x1e800000, OP_C4X ),
949 B_CLASS_INSN( "lde", 0x06800000, OP_C3X ),
950 { "ldep", 0x76000000, 0xffe00000, "X,R" , OP_C4X }, /* Z_CLASS */
951 B_CLASS_INSN( "ldf", 0x07000000, OP_C3X ),
952 LL_CLASS_INSN( "ldf", 0xc4000000, OP_C3X ),
953 P_CLASS_INSN( "ldf", "stf", 0xd8000000, OP_C3X ),
954 BB_CLASS_INSN( "ldfC", 0x00000000, OP_C3X ),
955 B6_CLASS_INSN( "ldfi", 0x07800000, OP_C3X ),
5dec9182
SS		 956 { "ldhi", 0x1fe00000, 0xffe00000, "U,R" , OP_C4X }, /* Z_CLASS */
957 { "ldhi", 0x1fe00000, 0xffe00000, "#,R" , OP_C4X }, /* Z_CLASS */
9c87d6c7
SS		 958 A_CLASS_INSN( "ldi", 0x08000000, OP_C3X ),
959 LL_CLASS_INSN( "ldi", 0xc6000000, OP_C3X ),
960 P_CLASS_INSN( "ldi", "sti", 0xda000000, OP_C3X ),
961 AB_CLASS_INSN( "ldiC", 0x10000000, OP_C3X ),
962 A6_CLASS_INSN( "ldii", 0x08800000, OP_C3X ),
963 { "ldp", 0x50700000, 0xffff0000, "#" , OP_C3X }, /* Z_CLASS - synonym for ldiu #,dp */
964 B_CLASS_INSN( "ldm", 0x09000000, OP_C3X ),
965 { "ldpe", 0x76800000, 0xffe00000, "Q,Z" , OP_C4X }, /* Z_CLASS */
966 { "ldpk", 0x1F700000, 0xffff0000, "#" , OP_C4X }, /* Z_CLASS */
967 A_CLASS_INSN( "lh0", 0xba000000, OP_C4X ),
968 A_CLASS_INSN( "lh1", 0xba800000, OP_C4X ),
969 AU_CLASS_INSN( "lhu0", 0xbb000000, OP_C4X ),
970 AU_CLASS_INSN( "lhu1", 0xbb800000, OP_C4X ),
971 { "lopower", 0x10800001,0xffffffff, "" , OP_LPWR }, /* Z_CLASS */
972 A_CLASS_INSN( "lsh", 0x09800000, OP_C3X ),
973 T_CLASS_INSN( "lsh", 0x04000000, OP_C3X ),
974 Q_CLASS_INSN( "lsh", "sti", 0xdc000000, OP_C3X ),
975 A_CLASS_INSN( "lwl0", 0xb4000000, OP_C4X ),
976 A_CLASS_INSN( "lwl1", 0xb4800000, OP_C4X ),
977 A_CLASS_INSN( "lwl2", 0xb5000000, OP_C4X ),
978 A_CLASS_INSN( "lwl3", 0xb5800000, OP_C4X ),
979 A_CLASS_INSN( "lwr0", 0xb6000000, OP_C4X ),
980 A_CLASS_INSN( "lwr1", 0xb6800000, OP_C4X ),
981 A_CLASS_INSN( "lwr2", 0xb7000000, OP_C4X ),
982 A_CLASS_INSN( "lwr3", 0xb7800000, OP_C4X ),
983 { "maxspeed",0x10800000,0xffffffff, "" , OP_LPWR }, /* Z_CLASS */
984 A_CLASS_INSN( "mb0", 0xb8000000, OP_C4X ),
985 A_CLASS_INSN( "mb1", 0xb8800000, OP_C4X ),
986 A_CLASS_INSN( "mb2", 0xb9000000, OP_C4X ),
987 A_CLASS_INSN( "mb3", 0xb9800000, OP_C4X ),
988 A_CLASS_INSN( "mh0", 0xbc000000, OP_C4X ),
989 A_CLASS_INSN( "mh1", 0xbc800000, OP_C4X ),
990 A_CLASS_INSN( "mh2", 0xbd000000, OP_C4X ),
991 A_CLASS_INSN( "mh3", 0xbd800000, OP_C4X ),
992 B_CLASS_INSN( "mpyf", 0x0a000000, OP_C3X ),
993 SC_CLASS_INSN( "mpyf", 0x04800000, OP_C3X ),
994 M_CLASS_INSN( "mpyf", "addf", 0x80000000, OP_C3X ),
995 QC_CLASS_INSN( "mpyf", "stf", 0xde000000, OP_C3X ),
996 M_CLASS_INSN( "mpyf", "subf", 0x84000000, OP_C3X ),
997 A_CLASS_INSN( "mpyi", 0x0a800000, OP_C3X ),
998 TC_CLASS_INSN( "mpyi", 0x05000000, OP_C3X ),
999 M_CLASS_INSN( "mpyi", "addi", 0x88000000, OP_C3X ),
1000 QC_CLASS_INSN( "mpyi", "sti", 0xe0000000, OP_C3X ),
1001 M_CLASS_INSN( "mpyi", "subi", 0x8c000000, OP_C3X ),
1002 A_CLASS_INSN( "mpyshi", 0x1d800000, OP_C4X ),
1003 TC_CLASS_INSN( "mpyshi", 0x28800000, OP_C4X ),
1004 A_CLASS_INSN( "mpyuhi", 0x1e000000, OP_C4X ),
1005 TC_CLASS_INSN( "mpyuhi", 0x29000000, OP_C4X ),
1006 A_CLASS_INSN( "negb", 0x0b000000, OP_C3X ),
1007 B_CLASS_INSN( "negf", 0x0b800000, OP_C3X ),
1008 P_CLASS_INSN( "negf", "stf", 0xe2000000, OP_C3X ),
1009 A_CLASS_INSN( "negi", 0x0c000000, OP_C3X ),
1010 P_CLASS_INSN( "negi", "sti", 0xe4000000, OP_C3X ),
1011 A2_CLASS_INSN( "nop", 0x0c800000, OP_C3X ),
1012 B_CLASS_INSN( "norm", 0x0d000000, OP_C3X ),
1013 AU_CLASS_INSN( "not", 0x0d800000, OP_C3X ),
1014 P_CLASS_INSN( "not", "sti", 0xe6000000, OP_C3X ),
1015 AU_CLASS_INSN( "or", 0x10000000, OP_C3X ),
1016 TC_CLASS_INSN( "or", 0x05800000, OP_C3X ),
1017 QC_CLASS_INSN( "or", "sti", 0xe8000000, OP_C3X ),
1018 R_CLASS_INSN( "pop", 0x0e200000, OP_C3X ),
1019 RF_CLASS_INSN( "popf", 0x0ea00000, OP_C3X ),
1020 R_CLASS_INSN( "push", 0x0f200000, OP_C3X ),
1021 RF_CLASS_INSN( "pushf", 0x0fa00000, OP_C3X ),
1022 BA_CLASS_INSN( "rcpf", 0x1d000000, OP_C4X ),
1023 { "retiB", 0x78000000, 0xffe00000, "" , OP_C3X }, /* Z_CLASS */
1024 { "reti", 0x78000000, 0xffe00000, "" , OP_C3X }, /* Z_CLASS - Alias for retiu */
1025 { "retiBd", 0x78200000, 0xffe00000, "" , OP_C4X }, /* Z_CLASS */
1026 { "retid", 0x78200000, 0xffe00000, "" , OP_C4X }, /* Z_CLASS - Alias for retiud */
1027 { "retsB", 0x78800000, 0xffe00000, "" , OP_C3X }, /* Z_CLASS */
1028 { "rets", 0x78800000, 0xffe00000, "" , OP_C3X }, /* Z_CLASS - Alias for retsu */
1029 B_CLASS_INSN( "rnd", 0x11000000, OP_C3X ),
1030 R_CLASS_INSN( "rol", 0x11e00001, OP_C3X ),
1031 R_CLASS_INSN( "rolc", 0x12600001, OP_C3X ),
1032 R_CLASS_INSN( "ror", 0x12e0ffff, OP_C3X ),
1033 R_CLASS_INSN( "rorc", 0x1360ffff, OP_C3X ),
1034 { "rptb", 0x64000000, 0xff000000, "B" , OP_C3X }, /* I2_CLASS */
1035 { "rptb", 0x79000000, 0xff000000, "Q" , OP_C4X }, /* I2_CLASS */
1036 { "rptbd", 0x65000000, 0xff000000, "B" , OP_C4X }, /* I2_CLASS */
1037 { "rptbd", 0x79800000, 0xff000000, "Q" , OP_C4X }, /* I2_CLASS */
1038 A3_CLASS_INSN( "rpts", 0x139b0000, OP_C3X ),
1039 B_CLASS_INSN( "rsqrf", 0x1c800000, OP_C4X ),
1040 { "sigi", 0x16000000, 0xffe00000, "" , OP_C3X }, /* Z_CLASS */
1041 A6_CLASS_INSN( "sigi", 0x16000000, OP_C4X ),
1042 B7_CLASS_INSN( "stf", 0x14000000, OP_C3X ),
1043 LS_CLASS_INSN( "stf", 0xc0000000, OP_C3X ),
1044 B7_CLASS_INSN( "stfi", 0x14800000, OP_C3X ),
1045 A7_CLASS_INSN( "sti", 0x15000000, OP_C3X ),
1046 { "sti", 0x15000000, 0xffe00000, "T,@" , OP_C4X }, /* Class A7 - Alias for stik */
1047 { "sti", 0x15600000, 0xffe00000, "T,*" , OP_C4X }, /* Class A7 */
1048 LS_CLASS_INSN( "sti", 0xc2000000, OP_C3X ),
1049 A7_CLASS_INSN( "stii", 0x15800000, OP_C3X ),
1050 { "stik", 0x15000000, 0xffe00000, "T,@" , OP_C4X }, /* Z_CLASS */
1051 { "stik", 0x15600000, 0xffe00000, "T,*" , OP_C4X }, /* Z_CLASS */
1052 A_CLASS_INSN( "subb", 0x16800000, OP_C3X ),
1053 T_CLASS_INSN( "subb", 0x06000000, OP_C3X ),
1054 A_CLASS_INSN( "subc", 0x17000000, OP_C3X ),
1055 B_CLASS_INSN( "subf", 0x17800000, OP_C3X ),
1056 S_CLASS_INSN( "subf", 0x06800000, OP_C3X ),
1057 Q_CLASS_INSN( "subf", "stf", 0xea000000, OP_C3X ),
1058 A_CLASS_INSN( "subi", 0x18000000, OP_C3X ),
1059 T_CLASS_INSN( "subi", 0x07000000, OP_C3X ),
1060 Q_CLASS_INSN( "subi", "sti", 0xec000000, OP_C3X ),
1061 A_CLASS_INSN( "subrb", 0x18800000, OP_C3X ),
1062 B_CLASS_INSN( "subrf", 0x19000000, OP_C3X ),
1063 A_CLASS_INSN( "subri", 0x19800000, OP_C3X ),
1064 { "swi", 0x66000000, 0xffffffff, "" , OP_C3X }, /* Z_CLASS */
1065 B_CLASS_INSN( "toieee", 0x1b800000, OP_C4X ),
1066 P_CLASS_INSN( "toieee","stf", 0xf0000000, OP_C4X ),
1067 { "trapB", 0x74000000, 0xffe00000, "V" , OP_C3X }, /* Z_CLASS */
1068 { "trap", 0x74000000, 0xffe00000, "V" , OP_C3X }, /* Z_CLASS - Alias for trapu */
1069 AU_CLASS_INSN( "tstb", 0x1a000000, OP_C3X ),
1070 T2C_CLASS_INSN("tstb", 0x07800000, OP_C3X ),
1071 AU_CLASS_INSN( "xor", 0x1a800000, OP_C3X ),
1072 TC_CLASS_INSN( "xor", 0x08000000, OP_C3X ),
1073 QC_CLASS_INSN( "xor", "sti", 0xee000000, OP_C3X ),
1074
be33c5dd 1075 /* Dummy entry, not included in tic4x_num_insts. This
026df7c5
NC		 1076 lets code examine entry i + 1 without checking
1077 if we've run off the end of the table. */
44287f60 1078 { "", 0x0, 0x00, "", 0 }
026df7c5
NC		 1079};
1080
be33c5dd 1081const unsigned int tic4x_num_insts = (((sizeof tic4x_insts) / (sizeof tic4x_insts[0])) - 1);
GDB Binutils - Deliverables
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