RISC-V: Support debug and float CSR as the unprivileged ones.

[deliverable/binutils-gdb.git] / opcodes / ChangeLog

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+2020-06-30  Nelson Chu  <nelson.chu@sifive.com>
+
+       * riscv-dis.c (print_insn_args, case 'E'): Updated.  Let the
+       unprivileged CSR can also be initialized.
+
 2020-06-29  Alan Modra  <amodra@gmail.com>
 
        * arm-dis.c: Use C style comments.