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drm/i915/skl: Don't warn if reading back DPLL0 is disabled
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_ddi.c
CommitLineData
45244b87
ED		 1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
28#include "i915_drv.h"
29#include "intel_drv.h"
30
10122051
JN		 31struct ddi_buf_trans {
32 u32 trans1; /* balance leg enable, de-emph level */
33 u32 trans2; /* vref sel, vswing */
34};
35
45244b87
ED		 36/* HDMI/DVI modes ignore everything but the last 2 items. So we share
37 * them for both DP and FDI transports, allowing those ports to
38 * automatically adapt to HDMI connections as well
39 */
10122051
JN		 40static const struct ddi_buf_trans hsw_ddi_translations_dp[] = {
41 { 0x00FFFFFF, 0x0006000E },
42 { 0x00D75FFF, 0x0005000A },
43 { 0x00C30FFF, 0x00040006 },
44 { 0x80AAAFFF, 0x000B0000 },
45 { 0x00FFFFFF, 0x0005000A },
46 { 0x00D75FFF, 0x000C0004 },
47 { 0x80C30FFF, 0x000B0000 },
48 { 0x00FFFFFF, 0x00040006 },
49 { 0x80D75FFF, 0x000B0000 },
45244b87
ED		 50};
51
10122051
JN		 52static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = {
53 { 0x00FFFFFF, 0x0007000E },
54 { 0x00D75FFF, 0x000F000A },
55 { 0x00C30FFF, 0x00060006 },
56 { 0x00AAAFFF, 0x001E0000 },
57 { 0x00FFFFFF, 0x000F000A },
58 { 0x00D75FFF, 0x00160004 },
59 { 0x00C30FFF, 0x001E0000 },
60 { 0x00FFFFFF, 0x00060006 },
61 { 0x00D75FFF, 0x001E0000 },
6acab15a
PZ		 62};
63
10122051
JN		 64static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = {
65 /* Idx NT mV d T mV d db */
66 { 0x00FFFFFF, 0x0006000E }, /* 0: 400 400 0 */
67 { 0x00E79FFF, 0x000E000C }, /* 1: 400 500 2 */
68 { 0x00D75FFF, 0x0005000A }, /* 2: 400 600 3.5 */
69 { 0x00FFFFFF, 0x0005000A }, /* 3: 600 600 0 */
70 { 0x00E79FFF, 0x001D0007 }, /* 4: 600 750 2 */
71 { 0x00D75FFF, 0x000C0004 }, /* 5: 600 900 3.5 */
72 { 0x00FFFFFF, 0x00040006 }, /* 6: 800 800 0 */
73 { 0x80E79FFF, 0x00030002 }, /* 7: 800 1000 2 */
74 { 0x00FFFFFF, 0x00140005 }, /* 8: 850 850 0 */
75 { 0x00FFFFFF, 0x000C0004 }, /* 9: 900 900 0 */
76 { 0x00FFFFFF, 0x001C0003 }, /* 10: 950 950 0 */
77 { 0x80FFFFFF, 0x00030002 }, /* 11: 1000 1000 0 */
45244b87
ED		 78};
79
10122051
JN		 80static const struct ddi_buf_trans bdw_ddi_translations_edp[] = {
81 { 0x00FFFFFF, 0x00000012 },
82 { 0x00EBAFFF, 0x00020011 },
83 { 0x00C71FFF, 0x0006000F },
84 { 0x00AAAFFF, 0x000E000A },
85 { 0x00FFFFFF, 0x00020011 },
86 { 0x00DB6FFF, 0x0005000F },
87 { 0x00BEEFFF, 0x000A000C },
88 { 0x00FFFFFF, 0x0005000F },
89 { 0x00DB6FFF, 0x000A000C },
300644c7
PZ		 90};
91
10122051
JN		 92static const struct ddi_buf_trans bdw_ddi_translations_dp[] = {
93 { 0x00FFFFFF, 0x0007000E },
94 { 0x00D75FFF, 0x000E000A },
95 { 0x00BEFFFF, 0x00140006 },
96 { 0x80B2CFFF, 0x001B0002 },
97 { 0x00FFFFFF, 0x000E000A },
17b523ba 98 { 0x00DB6FFF, 0x00160005 },
6805b2a7 99 { 0x80C71FFF, 0x001A0002 },
10122051
JN		 100 { 0x00F7DFFF, 0x00180004 },
101 { 0x80D75FFF, 0x001B0002 },
e58623cb
AR		 102};
103
10122051
JN		 104static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = {
105 { 0x00FFFFFF, 0x0001000E },
106 { 0x00D75FFF, 0x0004000A },
107 { 0x00C30FFF, 0x00070006 },
108 { 0x00AAAFFF, 0x000C0000 },
109 { 0x00FFFFFF, 0x0004000A },
110 { 0x00D75FFF, 0x00090004 },
111 { 0x00C30FFF, 0x000C0000 },
112 { 0x00FFFFFF, 0x00070006 },
113 { 0x00D75FFF, 0x000C0000 },
e58623cb
AR		 114};
115
10122051
JN		 116static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = {
117 /* Idx NT mV d T mV df db */
118 { 0x00FFFFFF, 0x0007000E }, /* 0: 400 400 0 */
119 { 0x00D75FFF, 0x000E000A }, /* 1: 400 600 3.5 */
120 { 0x00BEFFFF, 0x00140006 }, /* 2: 400 800 6 */
121 { 0x00FFFFFF, 0x0009000D }, /* 3: 450 450 0 */
122 { 0x00FFFFFF, 0x000E000A }, /* 4: 600 600 0 */
123 { 0x00D7FFFF, 0x00140006 }, /* 5: 600 800 2.5 */
124 { 0x80CB2FFF, 0x001B0002 }, /* 6: 600 1000 4.5 */
125 { 0x00FFFFFF, 0x00140006 }, /* 7: 800 800 0 */
126 { 0x80E79FFF, 0x001B0002 }, /* 8: 800 1000 2 */
127 { 0x80FFFFFF, 0x001B0002 }, /* 9: 1000 1000 0 */
a26aa8ba
DL		 128};
129
7f88e3af 130static const struct ddi_buf_trans skl_ddi_translations_dp[] = {
6c930688
DL		 131 { 0x00000018, 0x000000a2 },
132 { 0x00004014, 0x0000009B },
7f88e3af 133 { 0x00006012, 0x00000088 },
6c930688
DL		 134 { 0x00008010, 0x00000087 },
135 { 0x00000018, 0x0000009B },
7f88e3af 136 { 0x00004014, 0x00000088 },
6c930688 137 { 0x00006012, 0x00000087 },
7f88e3af 138 { 0x00000018, 0x00000088 },
6c930688 139 { 0x00004014, 0x00000087 },
7f88e3af
DL		 140};
141
7ad14a29
SJ		 142/* eDP 1.4 low vswing translation parameters */
143static const struct ddi_buf_trans skl_ddi_translations_edp[] = {
144 { 0x00000018, 0x000000a8 },
145 { 0x00002016, 0x000000ab },
146 { 0x00006012, 0x000000a2 },
147 { 0x00008010, 0x00000088 },
148 { 0x00000018, 0x000000ab },
149 { 0x00004014, 0x000000a2 },
150 { 0x00006012, 0x000000a6 },
151 { 0x00000018, 0x000000a2 },
152 { 0x00005013, 0x0000009c },
153 { 0x00000018, 0x00000088 },
154};
155
156
7f88e3af 157static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = {
b7192a56
SJ		 158 { 0x00000018, 0x000000ac },
159 { 0x00005012, 0x0000009d },
160 { 0x00007011, 0x00000088 },
161 { 0x00000018, 0x000000a1 },
162 { 0x00000018, 0x00000098 },
163 { 0x00004013, 0x00000088 },
164 { 0x00006012, 0x00000087 },
165 { 0x00000018, 0x000000df },
166 { 0x00003015, 0x00000087 },
167 { 0x00003015, 0x000000c7 },
168 { 0x00000018, 0x000000c7 },
7f88e3af
DL		 169};
170
96fb9f9b
VK		 171struct bxt_ddi_buf_trans {
172 u32 margin; /* swing value */
173 u32 scale; /* scale value */
174 u32 enable; /* scale enable */
175 u32 deemphasis;
176 bool default_index; /* true if the entry represents default value */
177};
178
179/* BSpec does not define separate vswing/pre-emphasis values for eDP.
180 * Using DP values for eDP as well.
181 */
182static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = {
183 /* Idx NT mV diff db */
184 { 52, 0, 0, 128, true }, /* 0: 400 0 */
185 { 78, 0, 0, 85, false }, /* 1: 400 3.5 */
186 { 104, 0, 0, 64, false }, /* 2: 400 6 */
187 { 154, 0, 0, 43, false }, /* 3: 400 9.5 */
188 { 77, 0, 0, 128, false }, /* 4: 600 0 */
189 { 116, 0, 0, 85, false }, /* 5: 600 3.5 */
190 { 154, 0, 0, 64, false }, /* 6: 600 6 */
191 { 102, 0, 0, 128, false }, /* 7: 800 0 */
192 { 154, 0, 0, 85, false }, /* 8: 800 3.5 */
193 { 154, 0x9A, 1, 128, false }, /* 9: 1200 0 */
194};
195
196/* BSpec has 2 recommended values - entries 0 and 8.
197 * Using the entry with higher vswing.
198 */
199static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi[] = {
200 /* Idx NT mV diff db */
201 { 52, 0, 0, 128, false }, /* 0: 400 0 */
202 { 52, 0, 0, 85, false }, /* 1: 400 3.5 */
203 { 52, 0, 0, 64, false }, /* 2: 400 6 */
204 { 42, 0, 0, 43, false }, /* 3: 400 9.5 */
205 { 77, 0, 0, 128, false }, /* 4: 600 0 */
206 { 77, 0, 0, 85, false }, /* 5: 600 3.5 */
207 { 77, 0, 0, 64, false }, /* 6: 600 6 */
208 { 102, 0, 0, 128, false }, /* 7: 800 0 */
209 { 102, 0, 0, 85, false }, /* 8: 800 3.5 */
210 { 154, 0x9A, 1, 128, true }, /* 9: 1200 0 */
211};
212
a1e6ad66
ID		 213static void ddi_get_encoder_port(struct intel_encoder *intel_encoder,
214 struct intel_digital_port **dig_port,
215 enum port *port)
fc914639 216{
0bdee30e 217 struct drm_encoder *encoder = &intel_encoder->base;
fc914639
PZ		 218 int type = intel_encoder->type;
219
0e32b39c 220 if (type == INTEL_OUTPUT_DP_MST) {
a1e6ad66
ID		 221 *dig_port = enc_to_mst(encoder)->primary;
222 *port = (*dig_port)->port;
0e32b39c 223 } else if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP ||
00c09d70 224 type == INTEL_OUTPUT_HDMI || type == INTEL_OUTPUT_UNKNOWN) {
a1e6ad66
ID		 225 *dig_port = enc_to_dig_port(encoder);
226 *port = (*dig_port)->port;
fc914639 227 } else if (type == INTEL_OUTPUT_ANALOG) {
a1e6ad66
ID		 228 *dig_port = NULL;
229 *port = PORT_E;
fc914639
PZ		 230 } else {
231 DRM_ERROR("Invalid DDI encoder type %d\n", type);
232 BUG();
233 }
234}
235
a1e6ad66
ID		 236enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder)
237{
238 struct intel_digital_port *dig_port;
239 enum port port;
240
241 ddi_get_encoder_port(intel_encoder, &dig_port, &port);
242
243 return port;
244}
245
ce3b7e9b
DL		 246static bool
247intel_dig_port_supports_hdmi(const struct intel_digital_port *intel_dig_port)
248{
249 return intel_dig_port->hdmi.hdmi_reg;
250}
251
e58623cb
AR		 252/*
253 * Starting with Haswell, DDI port buffers must be programmed with correct
254 * values in advance. The buffer values are different for FDI and DP modes,
45244b87
ED		 255 * but the HDMI/DVI fields are shared among those. So we program the DDI
256 * in either FDI or DP modes only, as HDMI connections will work with both
257 * of those
258 */
faa0cdbe
ID		 259static void intel_prepare_ddi_buffers(struct drm_device *dev, enum port port,
260 bool supports_hdmi)
45244b87
ED		 261{
262 struct drm_i915_private *dev_priv = dev->dev_private;
263 u32 reg;
7ff44670 264 int i, n_hdmi_entries, n_dp_entries, n_edp_entries, hdmi_default_entry,
7ad14a29 265 size;
6acab15a 266 int hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
10122051
JN		 267 const struct ddi_buf_trans *ddi_translations_fdi;
268 const struct ddi_buf_trans *ddi_translations_dp;
269 const struct ddi_buf_trans *ddi_translations_edp;
270 const struct ddi_buf_trans *ddi_translations_hdmi;
271 const struct ddi_buf_trans *ddi_translations;
e58623cb 272
96fb9f9b 273 if (IS_BROXTON(dev)) {
faa0cdbe 274 if (!supports_hdmi)
96fb9f9b
VK		 275 return;
276
277 /* Vswing programming for HDMI */
278 bxt_ddi_vswing_sequence(dev, hdmi_level, port,
279 INTEL_OUTPUT_HDMI);
280 return;
281 } else if (IS_SKYLAKE(dev)) {
7f88e3af
DL		 282 ddi_translations_fdi = NULL;
283 ddi_translations_dp = skl_ddi_translations_dp;
7ad14a29 284 n_dp_entries = ARRAY_SIZE(skl_ddi_translations_dp);
9e458034 285 if (dev_priv->edp_low_vswing) {
7ad14a29
SJ		 286 ddi_translations_edp = skl_ddi_translations_edp;
287 n_edp_entries = ARRAY_SIZE(skl_ddi_translations_edp);
288 } else {
289 ddi_translations_edp = skl_ddi_translations_dp;
290 n_edp_entries = ARRAY_SIZE(skl_ddi_translations_dp);
291 }
292
7f88e3af
DL		 293 ddi_translations_hdmi = skl_ddi_translations_hdmi;
294 n_hdmi_entries = ARRAY_SIZE(skl_ddi_translations_hdmi);
b7192a56 295 hdmi_default_entry = 7;
7f88e3af 296 } else if (IS_BROADWELL(dev)) {
e58623cb
AR		 297 ddi_translations_fdi = bdw_ddi_translations_fdi;
298 ddi_translations_dp = bdw_ddi_translations_dp;
300644c7 299 ddi_translations_edp = bdw_ddi_translations_edp;
a26aa8ba 300 ddi_translations_hdmi = bdw_ddi_translations_hdmi;
7ad14a29
SJ		 301 n_edp_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
302 n_dp_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
10122051 303 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
7ff44670 304 hdmi_default_entry = 7;
e58623cb
AR		 305 } else if (IS_HASWELL(dev)) {
306 ddi_translations_fdi = hsw_ddi_translations_fdi;
307 ddi_translations_dp = hsw_ddi_translations_dp;
300644c7 308 ddi_translations_edp = hsw_ddi_translations_dp;
a26aa8ba 309 ddi_translations_hdmi = hsw_ddi_translations_hdmi;
7ad14a29 310 n_dp_entries = n_edp_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
10122051 311 n_hdmi_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
7ff44670 312 hdmi_default_entry = 6;
e58623cb
AR		 313 } else {
314 WARN(1, "ddi translation table missing\n");
300644c7 315 ddi_translations_edp = bdw_ddi_translations_dp;
e58623cb
AR		 316 ddi_translations_fdi = bdw_ddi_translations_fdi;
317 ddi_translations_dp = bdw_ddi_translations_dp;
a26aa8ba 318 ddi_translations_hdmi = bdw_ddi_translations_hdmi;
7ad14a29
SJ		 319 n_edp_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
320 n_dp_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
10122051 321 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
7ff44670 322 hdmi_default_entry = 7;
e58623cb
AR		 323 }
324
300644c7
PZ		 325 switch (port) {
326 case PORT_A:
327 ddi_translations = ddi_translations_edp;
7ad14a29 328 size = n_edp_entries;
300644c7
PZ		 329 break;
330 case PORT_B:
331 case PORT_C:
300644c7 332 ddi_translations = ddi_translations_dp;
7ad14a29 333 size = n_dp_entries;
300644c7 334 break;
77d8d009 335 case PORT_D:
7ad14a29 336 if (intel_dp_is_edp(dev, PORT_D)) {
77d8d009 337 ddi_translations = ddi_translations_edp;
7ad14a29
SJ		 338 size = n_edp_entries;
339 } else {
77d8d009 340 ddi_translations = ddi_translations_dp;
7ad14a29
SJ		 341 size = n_dp_entries;
342 }
77d8d009 343 break;
300644c7 344 case PORT_E:
7f88e3af
DL		 345 if (ddi_translations_fdi)
346 ddi_translations = ddi_translations_fdi;
347 else
348 ddi_translations = ddi_translations_dp;
7ad14a29 349 size = n_dp_entries;
300644c7
PZ		 350 break;
351 default:
352 BUG();
353 }
45244b87 354
7ad14a29 355 for (i = 0, reg = DDI_BUF_TRANS(port); i < size; i++) {
10122051
JN		 356 I915_WRITE(reg, ddi_translations[i].trans1);
357 reg += 4;
358 I915_WRITE(reg, ddi_translations[i].trans2);
45244b87
ED		 359 reg += 4;
360 }
ce4dd49e 361
faa0cdbe 362 if (!supports_hdmi)
ce3b7e9b
DL		 363 return;
364
ce4dd49e
DL		 365 /* Choose a good default if VBT is badly populated */
366 if (hdmi_level == HDMI_LEVEL_SHIFT_UNKNOWN ||
367 hdmi_level >= n_hdmi_entries)
7ff44670 368 hdmi_level = hdmi_default_entry;
ce4dd49e 369
6acab15a 370 /* Entry 9 is for HDMI: */
10122051
JN		 371 I915_WRITE(reg, ddi_translations_hdmi[hdmi_level].trans1);
372 reg += 4;
373 I915_WRITE(reg, ddi_translations_hdmi[hdmi_level].trans2);
374 reg += 4;
45244b87
ED		 375}
376
377/* Program DDI buffers translations for DP. By default, program ports A-D in DP
378 * mode and port E for FDI.
379 */
380void intel_prepare_ddi(struct drm_device *dev)
381{
faa0cdbe 382 struct intel_encoder *intel_encoder;
b403745c 383 bool visited[I915_MAX_PORTS] = { 0, };
45244b87 384
0d536cb4
PZ		 385 if (!HAS_DDI(dev))
386 return;
45244b87 387
faa0cdbe
ID		 388 for_each_intel_encoder(dev, intel_encoder) {
389 struct intel_digital_port *intel_dig_port;
390 enum port port;
391 bool supports_hdmi;
392
393 ddi_get_encoder_port(intel_encoder, &intel_dig_port, &port);
394
395 if (visited[port])
b403745c
DL		 396 continue;
397
faa0cdbe
ID		 398 supports_hdmi = intel_dig_port &&
399 intel_dig_port_supports_hdmi(intel_dig_port);
400
401 intel_prepare_ddi_buffers(dev, port, supports_hdmi);
402 visited[port] = true;
b403745c 403 }
45244b87 404}
c82e4d26 405
248138b5
PZ		 406static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
407 enum port port)
408{
409 uint32_t reg = DDI_BUF_CTL(port);
410 int i;
411
3449ca85 412 for (i = 0; i < 16; i++) {
248138b5
PZ		 413 udelay(1);
414 if (I915_READ(reg) & DDI_BUF_IS_IDLE)
415 return;
416 }
417 DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port));
418}
c82e4d26
ED		 419
420/* Starting with Haswell, different DDI ports can work in FDI mode for
421 * connection to the PCH-located connectors. For this, it is necessary to train
422 * both the DDI port and PCH receiver for the desired DDI buffer settings.
423 *
424 * The recommended port to work in FDI mode is DDI E, which we use here. Also,
425 * please note that when FDI mode is active on DDI E, it shares 2 lines with
426 * DDI A (which is used for eDP)
427 */
428
429void hsw_fdi_link_train(struct drm_crtc *crtc)
430{
431 struct drm_device *dev = crtc->dev;
432 struct drm_i915_private *dev_priv = dev->dev_private;
433 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
04945641 434 u32 temp, i, rx_ctl_val;
c82e4d26 435
04945641
PZ		 436 /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
437 * mode set "sequence for CRT port" document:
438 * - TP1 to TP2 time with the default value
439 * - FDI delay to 90h
8693a824
DL		 440 *
441 * WaFDIAutoLinkSetTimingOverrride:hsw
04945641
PZ		 442 */
443 I915_WRITE(_FDI_RXA_MISC, FDI_RX_PWRDN_LANE1_VAL(2) |
444 FDI_RX_PWRDN_LANE0_VAL(2) |
445 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
446
447 /* Enable the PCH Receiver FDI PLL */
3e68320e 448 rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
33d29b14 449 FDI_RX_PLL_ENABLE |
6e3c9717 450 FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
04945641
PZ		 451 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
452 POSTING_READ(_FDI_RXA_CTL);
453 udelay(220);
454
455 /* Switch from Rawclk to PCDclk */
456 rx_ctl_val |= FDI_PCDCLK;
457 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
458
459 /* Configure Port Clock Select */
6e3c9717
ACO		 460 I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->config->ddi_pll_sel);
461 WARN_ON(intel_crtc->config->ddi_pll_sel != PORT_CLK_SEL_SPLL);
04945641
PZ		 462
463 /* Start the training iterating through available voltages and emphasis,
464 * testing each value twice. */
10122051 465 for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) {
c82e4d26
ED		 466 /* Configure DP_TP_CTL with auto-training */
467 I915_WRITE(DP_TP_CTL(PORT_E),
468 DP_TP_CTL_FDI_AUTOTRAIN |
469 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
470 DP_TP_CTL_LINK_TRAIN_PAT1 |
471 DP_TP_CTL_ENABLE);
472
876a8cdf
DL		 473 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
474 * DDI E does not support port reversal, the functionality is
475 * achieved on the PCH side in FDI_RX_CTL, so no need to set the
476 * port reversal bit */
c82e4d26 477 I915_WRITE(DDI_BUF_CTL(PORT_E),
04945641 478 DDI_BUF_CTL_ENABLE |
6e3c9717 479 ((intel_crtc->config->fdi_lanes - 1) << 1) |
c5fe6a06 480 DDI_BUF_TRANS_SELECT(i / 2));
04945641 481 POSTING_READ(DDI_BUF_CTL(PORT_E));
c82e4d26
ED		 482
483 udelay(600);
484
04945641
PZ		 485 /* Program PCH FDI Receiver TU */
486 I915_WRITE(_FDI_RXA_TUSIZE1, TU_SIZE(64));
487
488 /* Enable PCH FDI Receiver with auto-training */
489 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
490 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
491 POSTING_READ(_FDI_RXA_CTL);
492
493 /* Wait for FDI receiver lane calibration */
494 udelay(30);
495
496 /* Unset FDI_RX_MISC pwrdn lanes */
497 temp = I915_READ(_FDI_RXA_MISC);
498 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
499 I915_WRITE(_FDI_RXA_MISC, temp);
500 POSTING_READ(_FDI_RXA_MISC);
501
502 /* Wait for FDI auto training time */
503 udelay(5);
c82e4d26
ED		 504
505 temp = I915_READ(DP_TP_STATUS(PORT_E));
506 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
04945641 507 DRM_DEBUG_KMS("FDI link training done on step %d\n", i);
c82e4d26
ED		 508
509 /* Enable normal pixel sending for FDI */
510 I915_WRITE(DP_TP_CTL(PORT_E),
04945641
PZ		 511 DP_TP_CTL_FDI_AUTOTRAIN |
512 DP_TP_CTL_LINK_TRAIN_NORMAL |
513 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
514 DP_TP_CTL_ENABLE);
c82e4d26 515
04945641 516 return;
c82e4d26 517 }
04945641 518
248138b5
PZ		 519 temp = I915_READ(DDI_BUF_CTL(PORT_E));
520 temp &= ~DDI_BUF_CTL_ENABLE;
521 I915_WRITE(DDI_BUF_CTL(PORT_E), temp);
522 POSTING_READ(DDI_BUF_CTL(PORT_E));
523
04945641 524 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
248138b5
PZ		 525 temp = I915_READ(DP_TP_CTL(PORT_E));
526 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
527 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
528 I915_WRITE(DP_TP_CTL(PORT_E), temp);
529 POSTING_READ(DP_TP_CTL(PORT_E));
530
531 intel_wait_ddi_buf_idle(dev_priv, PORT_E);
04945641
PZ		 532
533 rx_ctl_val &= ~FDI_RX_ENABLE;
534 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
248138b5 535 POSTING_READ(_FDI_RXA_CTL);
04945641
PZ		 536
537 /* Reset FDI_RX_MISC pwrdn lanes */
538 temp = I915_READ(_FDI_RXA_MISC);
539 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
540 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
541 I915_WRITE(_FDI_RXA_MISC, temp);
248138b5 542 POSTING_READ(_FDI_RXA_MISC);
c82e4d26
ED		 543 }
544
04945641 545 DRM_ERROR("FDI link training failed!\n");
c82e4d26 546}
0e72a5b5 547
44905a27
DA		 548void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder)
549{
550 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
551 struct intel_digital_port *intel_dig_port =
552 enc_to_dig_port(&encoder->base);
553
554 intel_dp->DP = intel_dig_port->saved_port_bits |
c5fe6a06 555 DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0);
44905a27
DA		 556 intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
557
558}
559
8d9ddbcb
PZ		 560static struct intel_encoder *
561intel_ddi_get_crtc_encoder(struct drm_crtc *crtc)
562{
563 struct drm_device *dev = crtc->dev;
564 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
565 struct intel_encoder *intel_encoder, *ret = NULL;
566 int num_encoders = 0;
567
568 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
569 ret = intel_encoder;
570 num_encoders++;
571 }
572
573 if (num_encoders != 1)
84f44ce7
VS		 574 WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders,
575 pipe_name(intel_crtc->pipe));
8d9ddbcb
PZ		 576
577 BUG_ON(ret == NULL);
578 return ret;
579}
580
bcddf610 581struct intel_encoder *
3165c074 582intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state)
d0737e1d 583{
3165c074
ACO		 584 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
585 struct intel_encoder *ret = NULL;
586 struct drm_atomic_state *state;
da3ced29
ACO		 587 struct drm_connector *connector;
588 struct drm_connector_state *connector_state;
d0737e1d 589 int num_encoders = 0;
3165c074 590 int i;
d0737e1d 591
3165c074
ACO		 592 state = crtc_state->base.state;
593
da3ced29
ACO		 594 for_each_connector_in_state(state, connector, connector_state, i) {
595 if (connector_state->crtc != crtc_state->base.crtc)
3165c074
ACO		 596 continue;
597
da3ced29 598 ret = to_intel_encoder(connector_state->best_encoder);
3165c074 599 num_encoders++;
d0737e1d
ACO		 600 }
601
602 WARN(num_encoders != 1, "%d encoders on crtc for pipe %c\n", num_encoders,
603 pipe_name(crtc->pipe));
604
605 BUG_ON(ret == NULL);
606 return ret;
607}
608
1c0b85c5 609#define LC_FREQ 2700
27893390 610#define LC_FREQ_2K U64_C(LC_FREQ * 2000)
1c0b85c5
DL		 611
612#define P_MIN 2
613#define P_MAX 64
614#define P_INC 2
615
616/* Constraints for PLL good behavior */
617#define REF_MIN 48
618#define REF_MAX 400
619#define VCO_MIN 2400
620#define VCO_MAX 4800
621
27893390
DL		 622#define abs_diff(a, b) ({ \
623 typeof(a) __a = (a); \
624 typeof(b) __b = (b); \
625 (void) (&__a == &__b); \
626 __a > __b ? (__a - __b) : (__b - __a); })
1c0b85c5 627
63582983 628struct hsw_wrpll_rnp {
1c0b85c5
DL		 629 unsigned p, n2, r2;
630};
631
63582983 632static unsigned hsw_wrpll_get_budget_for_freq(int clock)
6441ab5f 633{
1c0b85c5
DL		 634 unsigned budget;
635
636 switch (clock) {
637 case 25175000:
638 case 25200000:
639 case 27000000:
640 case 27027000:
641 case 37762500:
642 case 37800000:
643 case 40500000:
644 case 40541000:
645 case 54000000:
646 case 54054000:
647 case 59341000:
648 case 59400000:
649 case 72000000:
650 case 74176000:
651 case 74250000:
652 case 81000000:
653 case 81081000:
654 case 89012000:
655 case 89100000:
656 case 108000000:
657 case 108108000:
658 case 111264000:
659 case 111375000:
660 case 148352000:
661 case 148500000:
662 case 162000000:
663 case 162162000:
664 case 222525000:
665 case 222750000:
666 case 296703000:
667 case 297000000:
668 budget = 0;
669 break;
670 case 233500000:
671 case 245250000:
672 case 247750000:
673 case 253250000:
674 case 298000000:
675 budget = 1500;
676 break;
677 case 169128000:
678 case 169500000:
679 case 179500000:
680 case 202000000:
681 budget = 2000;
682 break;
683 case 256250000:
684 case 262500000:
685 case 270000000:
686 case 272500000:
687 case 273750000:
688 case 280750000:
689 case 281250000:
690 case 286000000:
691 case 291750000:
692 budget = 4000;
693 break;
694 case 267250000:
695 case 268500000:
696 budget = 5000;
697 break;
698 default:
699 budget = 1000;
700 break;
701 }
6441ab5f 702
1c0b85c5
DL		 703 return budget;
704}
705
63582983
DL		 706static void hsw_wrpll_update_rnp(uint64_t freq2k, unsigned budget,
707 unsigned r2, unsigned n2, unsigned p,
708 struct hsw_wrpll_rnp *best)
1c0b85c5
DL		 709{
710 uint64_t a, b, c, d, diff, diff_best;
6441ab5f 711
1c0b85c5
DL		 712 /* No best (r,n,p) yet */
713 if (best->p == 0) {
714 best->p = p;
715 best->n2 = n2;
716 best->r2 = r2;
717 return;
718 }
6441ab5f 719
1c0b85c5
DL		 720 /*
721 * Output clock is (LC_FREQ_2K / 2000) * N / (P * R), which compares to
722 * freq2k.
723 *
724 * delta = 1e6 *
725 * abs(freq2k - (LC_FREQ_2K * n2/(p * r2))) /
726 * freq2k;
727 *
728 * and we would like delta <= budget.
729 *
730 * If the discrepancy is above the PPM-based budget, always prefer to
731 * improve upon the previous solution. However, if you're within the
732 * budget, try to maximize Ref * VCO, that is N / (P * R^2).
733 */
734 a = freq2k * budget * p * r2;
735 b = freq2k * budget * best->p * best->r2;
27893390
DL		 736 diff = abs_diff(freq2k * p * r2, LC_FREQ_2K * n2);
737 diff_best = abs_diff(freq2k * best->p * best->r2,
738 LC_FREQ_2K * best->n2);
1c0b85c5
DL		 739 c = 1000000 * diff;
740 d = 1000000 * diff_best;
741
742 if (a < c && b < d) {
743 /* If both are above the budget, pick the closer */
744 if (best->p * best->r2 * diff < p * r2 * diff_best) {
745 best->p = p;
746 best->n2 = n2;
747 best->r2 = r2;
748 }
749 } else if (a >= c && b < d) {
750 /* If A is below the threshold but B is above it? Update. */
751 best->p = p;
752 best->n2 = n2;
753 best->r2 = r2;
754 } else if (a >= c && b >= d) {
755 /* Both are below the limit, so pick the higher n2/(r2*r2) */
756 if (n2 * best->r2 * best->r2 > best->n2 * r2 * r2) {
757 best->p = p;
758 best->n2 = n2;
759 best->r2 = r2;
760 }
761 }
762 /* Otherwise a < c && b >= d, do nothing */
763}
764
63582983 765static int hsw_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv, int reg)
11578553
JB		 766{
767 int refclk = LC_FREQ;
768 int n, p, r;
769 u32 wrpll;
770
771 wrpll = I915_READ(reg);
114fe488
DV		 772 switch (wrpll & WRPLL_PLL_REF_MASK) {
773 case WRPLL_PLL_SSC:
774 case WRPLL_PLL_NON_SSC:
11578553
JB		 775 /*
776 * We could calculate spread here, but our checking
777 * code only cares about 5% accuracy, and spread is a max of
778 * 0.5% downspread.
779 */
780 refclk = 135;
781 break;
114fe488 782 case WRPLL_PLL_LCPLL:
11578553
JB		 783 refclk = LC_FREQ;
784 break;
785 default:
786 WARN(1, "bad wrpll refclk\n");
787 return 0;
788 }
789
790 r = wrpll & WRPLL_DIVIDER_REF_MASK;
791 p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT;
792 n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT;
793
20f0ec16
JB		 794 /* Convert to KHz, p & r have a fixed point portion */
795 return (refclk * n * 100) / (p * r);
11578553
JB		 796}
797
540e732c
S		 798static int skl_calc_wrpll_link(struct drm_i915_private *dev_priv,
799 uint32_t dpll)
800{
801 uint32_t cfgcr1_reg, cfgcr2_reg;
802 uint32_t cfgcr1_val, cfgcr2_val;
803 uint32_t p0, p1, p2, dco_freq;
804
805 cfgcr1_reg = GET_CFG_CR1_REG(dpll);
806 cfgcr2_reg = GET_CFG_CR2_REG(dpll);
807
808 cfgcr1_val = I915_READ(cfgcr1_reg);
809 cfgcr2_val = I915_READ(cfgcr2_reg);
810
811 p0 = cfgcr2_val & DPLL_CFGCR2_PDIV_MASK;
812 p2 = cfgcr2_val & DPLL_CFGCR2_KDIV_MASK;
813
814 if (cfgcr2_val & DPLL_CFGCR2_QDIV_MODE(1))
815 p1 = (cfgcr2_val & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8;
816 else
817 p1 = 1;
818
819
820 switch (p0) {
821 case DPLL_CFGCR2_PDIV_1:
822 p0 = 1;
823 break;
824 case DPLL_CFGCR2_PDIV_2:
825 p0 = 2;
826 break;
827 case DPLL_CFGCR2_PDIV_3:
828 p0 = 3;
829 break;
830 case DPLL_CFGCR2_PDIV_7:
831 p0 = 7;
832 break;
833 }
834
835 switch (p2) {
836 case DPLL_CFGCR2_KDIV_5:
837 p2 = 5;
838 break;
839 case DPLL_CFGCR2_KDIV_2:
840 p2 = 2;
841 break;
842 case DPLL_CFGCR2_KDIV_3:
843 p2 = 3;
844 break;
845 case DPLL_CFGCR2_KDIV_1:
846 p2 = 1;
847 break;
848 }
849
850 dco_freq = (cfgcr1_val & DPLL_CFGCR1_DCO_INTEGER_MASK) * 24 * 1000;
851
852 dco_freq += (((cfgcr1_val & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9) * 24 *
853 1000) / 0x8000;
854
855 return dco_freq / (p0 * p1 * p2 * 5);
856}
857
858
859static void skl_ddi_clock_get(struct intel_encoder *encoder,
5cec258b 860 struct intel_crtc_state *pipe_config)
540e732c
S		 861{
862 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
540e732c
S		 863 int link_clock = 0;
864 uint32_t dpll_ctl1, dpll;
865
134ffa44 866 dpll = pipe_config->ddi_pll_sel;
540e732c
S		 867
868 dpll_ctl1 = I915_READ(DPLL_CTRL1);
869
870 if (dpll_ctl1 & DPLL_CTRL1_HDMI_MODE(dpll)) {
871 link_clock = skl_calc_wrpll_link(dev_priv, dpll);
872 } else {
71cd8423
DL		 873 link_clock = dpll_ctl1 & DPLL_CTRL1_LINK_RATE_MASK(dpll);
874 link_clock >>= DPLL_CTRL1_LINK_RATE_SHIFT(dpll);
540e732c
S		 875
876 switch (link_clock) {
71cd8423 877 case DPLL_CTRL1_LINK_RATE_810:
540e732c
S		 878 link_clock = 81000;
879 break;
71cd8423 880 case DPLL_CTRL1_LINK_RATE_1080:
a8f3ef61
SJ		 881 link_clock = 108000;
882 break;
71cd8423 883 case DPLL_CTRL1_LINK_RATE_1350:
540e732c
S		 884 link_clock = 135000;
885 break;
71cd8423 886 case DPLL_CTRL1_LINK_RATE_1620:
a8f3ef61
SJ		 887 link_clock = 162000;
888 break;
71cd8423 889 case DPLL_CTRL1_LINK_RATE_2160:
a8f3ef61
SJ		 890 link_clock = 216000;
891 break;
71cd8423 892 case DPLL_CTRL1_LINK_RATE_2700:
540e732c
S		 893 link_clock = 270000;
894 break;
895 default:
896 WARN(1, "Unsupported link rate\n");
897 break;
898 }
899 link_clock *= 2;
900 }
901
902 pipe_config->port_clock = link_clock;
903
904 if (pipe_config->has_dp_encoder)
2d112de7 905 pipe_config->base.adjusted_mode.crtc_clock =
540e732c
S		 906 intel_dotclock_calculate(pipe_config->port_clock,
907 &pipe_config->dp_m_n);
908 else
2d112de7 909 pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock;
540e732c
S		 910}
911
3d51278a 912static void hsw_ddi_clock_get(struct intel_encoder *encoder,
5cec258b 913 struct intel_crtc_state *pipe_config)
11578553
JB		 914{
915 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
11578553
JB		 916 int link_clock = 0;
917 u32 val, pll;
918
26804afd 919 val = pipe_config->ddi_pll_sel;
11578553
JB		 920 switch (val & PORT_CLK_SEL_MASK) {
921 case PORT_CLK_SEL_LCPLL_810:
922 link_clock = 81000;
923 break;
924 case PORT_CLK_SEL_LCPLL_1350:
925 link_clock = 135000;
926 break;
927 case PORT_CLK_SEL_LCPLL_2700:
928 link_clock = 270000;
929 break;
930 case PORT_CLK_SEL_WRPLL1:
63582983 931 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL1);
11578553
JB		 932 break;
933 case PORT_CLK_SEL_WRPLL2:
63582983 934 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL2);
11578553
JB		 935 break;
936 case PORT_CLK_SEL_SPLL:
937 pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK;
938 if (pll == SPLL_PLL_FREQ_810MHz)
939 link_clock = 81000;
940 else if (pll == SPLL_PLL_FREQ_1350MHz)
941 link_clock = 135000;
942 else if (pll == SPLL_PLL_FREQ_2700MHz)
943 link_clock = 270000;
944 else {
945 WARN(1, "bad spll freq\n");
946 return;
947 }
948 break;
949 default:
950 WARN(1, "bad port clock sel\n");
951 return;
952 }
953
954 pipe_config->port_clock = link_clock * 2;
955
956 if (pipe_config->has_pch_encoder)
2d112de7 957 pipe_config->base.adjusted_mode.crtc_clock =
11578553
JB		 958 intel_dotclock_calculate(pipe_config->port_clock,
959 &pipe_config->fdi_m_n);
960 else if (pipe_config->has_dp_encoder)
2d112de7 961 pipe_config->base.adjusted_mode.crtc_clock =
11578553
JB		 962 intel_dotclock_calculate(pipe_config->port_clock,
963 &pipe_config->dp_m_n);
964 else
2d112de7 965 pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock;
11578553
JB		 966}
967
977bb38d
S		 968static int bxt_calc_pll_link(struct drm_i915_private *dev_priv,
969 enum intel_dpll_id dpll)
970{
971 /* FIXME formula not available in bspec */
972 return 0;
973}
974
975static void bxt_ddi_clock_get(struct intel_encoder *encoder,
976 struct intel_crtc_state *pipe_config)
977{
978 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
979 enum port port = intel_ddi_get_encoder_port(encoder);
980 uint32_t dpll = port;
981
982 pipe_config->port_clock =
983 bxt_calc_pll_link(dev_priv, dpll);
984
985 if (pipe_config->has_dp_encoder)
986 pipe_config->base.adjusted_mode.crtc_clock =
987 intel_dotclock_calculate(pipe_config->port_clock,
988 &pipe_config->dp_m_n);
989 else
990 pipe_config->base.adjusted_mode.crtc_clock =
991 pipe_config->port_clock;
992}
993
3d51278a 994void intel_ddi_clock_get(struct intel_encoder *encoder,
5cec258b 995 struct intel_crtc_state *pipe_config)
3d51278a 996{
22606a18
DL		 997 struct drm_device *dev = encoder->base.dev;
998
999 if (INTEL_INFO(dev)->gen <= 8)
1000 hsw_ddi_clock_get(encoder, pipe_config);
977bb38d 1001 else if (IS_SKYLAKE(dev))
22606a18 1002 skl_ddi_clock_get(encoder, pipe_config);
977bb38d
S		 1003 else if (IS_BROXTON(dev))
1004 bxt_ddi_clock_get(encoder, pipe_config);
3d51278a
DV		 1005}
1006
1c0b85c5 1007static void
d664c0ce
DL		 1008hsw_ddi_calculate_wrpll(int clock /* in Hz */,
1009 unsigned *r2_out, unsigned *n2_out, unsigned *p_out)
1c0b85c5
DL		 1010{
1011 uint64_t freq2k;
1012 unsigned p, n2, r2;
63582983 1013 struct hsw_wrpll_rnp best = { 0, 0, 0 };
1c0b85c5
DL		 1014 unsigned budget;
1015
1016 freq2k = clock / 100;
1017
63582983 1018 budget = hsw_wrpll_get_budget_for_freq(clock);
1c0b85c5
DL		 1019
1020 /* Special case handling for 540 pixel clock: bypass WR PLL entirely
1021 * and directly pass the LC PLL to it. */
1022 if (freq2k == 5400000) {
1023 *n2_out = 2;
1024 *p_out = 1;
1025 *r2_out = 2;
1026 return;
1027 }
1028
1029 /*
1030 * Ref = LC_FREQ / R, where Ref is the actual reference input seen by
1031 * the WR PLL.
1032 *
1033 * We want R so that REF_MIN <= Ref <= REF_MAX.
1034 * Injecting R2 = 2 * R gives:
1035 * REF_MAX * r2 > LC_FREQ * 2 and
1036 * REF_MIN * r2 < LC_FREQ * 2
1037 *
1038 * Which means the desired boundaries for r2 are:
1039 * LC_FREQ * 2 / REF_MAX < r2 < LC_FREQ * 2 / REF_MIN
1040 *
1041 */
1042 for (r2 = LC_FREQ * 2 / REF_MAX + 1;
1043 r2 <= LC_FREQ * 2 / REF_MIN;
1044 r2++) {
1045
1046 /*
1047 * VCO = N * Ref, that is: VCO = N * LC_FREQ / R
1048 *
1049 * Once again we want VCO_MIN <= VCO <= VCO_MAX.
1050 * Injecting R2 = 2 * R and N2 = 2 * N, we get:
1051 * VCO_MAX * r2 > n2 * LC_FREQ and
1052 * VCO_MIN * r2 < n2 * LC_FREQ)
1053 *
1054 * Which means the desired boundaries for n2 are:
1055 * VCO_MIN * r2 / LC_FREQ < n2 < VCO_MAX * r2 / LC_FREQ
1056 */
1057 for (n2 = VCO_MIN * r2 / LC_FREQ + 1;
1058 n2 <= VCO_MAX * r2 / LC_FREQ;
1059 n2++) {
1060
1061 for (p = P_MIN; p <= P_MAX; p += P_INC)
63582983
DL		 1062 hsw_wrpll_update_rnp(freq2k, budget,
1063 r2, n2, p, &best);
1c0b85c5
DL		 1064 }
1065 }
6441ab5f 1066
1c0b85c5
DL		 1067 *n2_out = best.n2;
1068 *p_out = best.p;
1069 *r2_out = best.r2;
6441ab5f
PZ		 1070}
1071
0220ab6e 1072static bool
d664c0ce 1073hsw_ddi_pll_select(struct intel_crtc *intel_crtc,
190f68c5 1074 struct intel_crtc_state *crtc_state,
d664c0ce
DL		 1075 struct intel_encoder *intel_encoder,
1076 int clock)
6441ab5f 1077{
d664c0ce 1078 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
e0b01be4 1079 struct intel_shared_dpll *pll;
716c2e55 1080 uint32_t val;
1c0b85c5 1081 unsigned p, n2, r2;
6441ab5f 1082
d664c0ce 1083 hsw_ddi_calculate_wrpll(clock * 1000, &r2, &n2, &p);
0694001b 1084
114fe488 1085 val = WRPLL_PLL_ENABLE | WRPLL_PLL_LCPLL |
0694001b
PZ		 1086 WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) |
1087 WRPLL_DIVIDER_POST(p);
1088
dd3cd74a
ACO		 1089 memset(&crtc_state->dpll_hw_state, 0,
1090 sizeof(crtc_state->dpll_hw_state));
1091
190f68c5 1092 crtc_state->dpll_hw_state.wrpll = val;
6441ab5f 1093
190f68c5 1094 pll = intel_get_shared_dpll(intel_crtc, crtc_state);
716c2e55
DV		 1095 if (pll == NULL) {
1096 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
1097 pipe_name(intel_crtc->pipe));
1098 return false;
0694001b 1099 }
d452c5b6 1100
190f68c5 1101 crtc_state->ddi_pll_sel = PORT_CLK_SEL_WRPLL(pll->id);
6441ab5f
PZ		 1102 }
1103
6441ab5f
PZ		 1104 return true;
1105}
1106
82d35437
S		 1107struct skl_wrpll_params {
1108 uint32_t dco_fraction;
1109 uint32_t dco_integer;
1110 uint32_t qdiv_ratio;
1111 uint32_t qdiv_mode;
1112 uint32_t kdiv;
1113 uint32_t pdiv;
1114 uint32_t central_freq;
1115};
1116
76516fbc
DL		 1117static void skl_wrpll_params_populate(struct skl_wrpll_params *params,
1118 uint64_t afe_clock,
1119 uint64_t central_freq,
1120 uint32_t p0, uint32_t p1, uint32_t p2)
1121{
1122 uint64_t dco_freq;
1123
76516fbc
DL		 1124 switch (central_freq) {
1125 case 9600000000ULL:
1126 params->central_freq = 0;
1127 break;
1128 case 9000000000ULL:
1129 params->central_freq = 1;
1130 break;
1131 case 8400000000ULL:
1132 params->central_freq = 3;
1133 }
1134
1135 switch (p0) {
1136 case 1:
1137 params->pdiv = 0;
1138 break;
1139 case 2:
1140 params->pdiv = 1;
1141 break;
1142 case 3:
1143 params->pdiv = 2;
1144 break;
1145 case 7:
1146 params->pdiv = 4;
1147 break;
1148 default:
1149 WARN(1, "Incorrect PDiv\n");
1150 }
1151
1152 switch (p2) {
1153 case 5:
1154 params->kdiv = 0;
1155 break;
1156 case 2:
1157 params->kdiv = 1;
1158 break;
1159 case 3:
1160 params->kdiv = 2;
1161 break;
1162 case 1:
1163 params->kdiv = 3;
1164 break;
1165 default:
1166 WARN(1, "Incorrect KDiv\n");
1167 }
1168
1169 params->qdiv_ratio = p1;
1170 params->qdiv_mode = (params->qdiv_ratio == 1) ? 0 : 1;
1171
1172 dco_freq = p0 * p1 * p2 * afe_clock;
1173
1174 /*
1175 * Intermediate values are in Hz.
1176 * Divide by MHz to match bsepc
1177 */
30a7862d 1178 params->dco_integer = div_u64(dco_freq, 24 * MHz(1));
76516fbc 1179 params->dco_fraction =
30a7862d
DL		 1180 div_u64((div_u64(dco_freq, 24) -
1181 params->dco_integer * MHz(1)) * 0x8000, MHz(1));
76516fbc
DL		 1182}
1183
318bd821 1184static bool
82d35437
S		 1185skl_ddi_calculate_wrpll(int clock /* in Hz */,
1186 struct skl_wrpll_params *wrpll_params)
1187{
1188 uint64_t afe_clock = clock * 5; /* AFE Clock is 5x Pixel clock */
21318cce
DL		 1189 uint64_t dco_central_freq[3] = {8400000000ULL,
1190 9000000000ULL,
1191 9600000000ULL};
82d35437
S		 1192 uint32_t min_dco_deviation = 400;
1193 uint32_t min_dco_index = 3;
1194 uint32_t P0[4] = {1, 2, 3, 7};
1195 uint32_t P2[4] = {1, 2, 3, 5};
1196 bool found = false;
1197 uint32_t candidate_p = 0;
1198 uint32_t candidate_p0[3] = {0}, candidate_p1[3] = {0};
1199 uint32_t candidate_p2[3] = {0};
1200 uint32_t dco_central_freq_deviation[3];
1201 uint32_t i, P1, k, dco_count;
1202 bool retry_with_odd = false;
82d35437
S		 1203
1204 /* Determine P0, P1 or P2 */
1205 for (dco_count = 0; dco_count < 3; dco_count++) {
1206 found = false;
1207 candidate_p =
1208 div64_u64(dco_central_freq[dco_count], afe_clock);
1209 if (retry_with_odd == false)
1210 candidate_p = (candidate_p % 2 == 0 ?
1211 candidate_p : candidate_p + 1);
1212
1213 for (P1 = 1; P1 < candidate_p; P1++) {
1214 for (i = 0; i < 4; i++) {
1215 if (!(P0[i] != 1 || P1 == 1))
1216 continue;
1217
1218 for (k = 0; k < 4; k++) {
1219 if (P1 != 1 && P2[k] != 2)
1220 continue;
1221
1222 if (candidate_p == P0[i] * P1 * P2[k]) {
1223 /* Found possible P0, P1, P2 */
1224 found = true;
1225 candidate_p0[dco_count] = P0[i];
1226 candidate_p1[dco_count] = P1;
1227 candidate_p2[dco_count] = P2[k];
1228 goto found;
1229 }
1230
1231 }
1232 }
1233 }
1234
1235found:
1236 if (found) {
1237 dco_central_freq_deviation[dco_count] =
1238 div64_u64(10000 *
64311571 1239 abs_diff(candidate_p * afe_clock,
82d35437
S		 1240 dco_central_freq[dco_count]),
1241 dco_central_freq[dco_count]);
1242
1243 if (dco_central_freq_deviation[dco_count] <
1244 min_dco_deviation) {
1245 min_dco_deviation =
1246 dco_central_freq_deviation[dco_count];
1247 min_dco_index = dco_count;
1248 }
1249 }
1250
1251 if (min_dco_index > 2 && dco_count == 2) {
6cf75178
DL		 1252 /* oh well, we tried... */
1253 if (retry_with_odd)
1254 break;
1255
82d35437
S		 1256 retry_with_odd = true;
1257 dco_count = 0;
1258 }
1259 }
1260
9c236753
DL		 1261 if (WARN(min_dco_index > 2,
1262 "No valid parameters found for pixel clock: %dHz\n", clock))
318bd821 1263 return false;
82d35437 1264
76516fbc
DL		 1265 skl_wrpll_params_populate(wrpll_params,
1266 afe_clock,
1267 dco_central_freq[min_dco_index],
1268 candidate_p0[min_dco_index],
1269 candidate_p1[min_dco_index],
1270 candidate_p2[min_dco_index]);
318bd821
DL		 1271
1272 return true;
82d35437
S		 1273}
1274
1275
1276static bool
1277skl_ddi_pll_select(struct intel_crtc *intel_crtc,
190f68c5 1278 struct intel_crtc_state *crtc_state,
82d35437
S		 1279 struct intel_encoder *intel_encoder,
1280 int clock)
1281{
1282 struct intel_shared_dpll *pll;
1283 uint32_t ctrl1, cfgcr1, cfgcr2;
1284
1285 /*
1286 * See comment in intel_dpll_hw_state to understand why we always use 0
1287 * as the DPLL id in this function.
1288 */
1289
1290 ctrl1 = DPLL_CTRL1_OVERRIDE(0);
1291
1292 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
1293 struct skl_wrpll_params wrpll_params = { 0, };
1294
1295 ctrl1 |= DPLL_CTRL1_HDMI_MODE(0);
1296
318bd821
DL		 1297 if (!skl_ddi_calculate_wrpll(clock * 1000, &wrpll_params))
1298 return false;
82d35437
S		 1299
1300 cfgcr1 = DPLL_CFGCR1_FREQ_ENABLE |
1301 DPLL_CFGCR1_DCO_FRACTION(wrpll_params.dco_fraction) |
1302 wrpll_params.dco_integer;
1303
1304 cfgcr2 = DPLL_CFGCR2_QDIV_RATIO(wrpll_params.qdiv_ratio) |
1305 DPLL_CFGCR2_QDIV_MODE(wrpll_params.qdiv_mode) |
1306 DPLL_CFGCR2_KDIV(wrpll_params.kdiv) |
1307 DPLL_CFGCR2_PDIV(wrpll_params.pdiv) |
1308 wrpll_params.central_freq;
1309 } else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT) {
1310 struct drm_encoder *encoder = &intel_encoder->base;
1311 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1312
1313 switch (intel_dp->link_bw) {
1314 case DP_LINK_BW_1_62:
71cd8423 1315 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, 0);
82d35437
S		 1316 break;
1317 case DP_LINK_BW_2_7:
71cd8423 1318 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, 0);
82d35437
S		 1319 break;
1320 case DP_LINK_BW_5_4:
71cd8423 1321 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, 0);
82d35437
S		 1322 break;
1323 }
1324
1325 cfgcr1 = cfgcr2 = 0;
1326 } else /* eDP */
1327 return true;
1328
dd3cd74a
ACO		 1329 memset(&crtc_state->dpll_hw_state, 0,
1330 sizeof(crtc_state->dpll_hw_state));
1331
190f68c5
ACO		 1332 crtc_state->dpll_hw_state.ctrl1 = ctrl1;
1333 crtc_state->dpll_hw_state.cfgcr1 = cfgcr1;
1334 crtc_state->dpll_hw_state.cfgcr2 = cfgcr2;
82d35437 1335
190f68c5 1336 pll = intel_get_shared_dpll(intel_crtc, crtc_state);
82d35437
S		 1337 if (pll == NULL) {
1338 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
1339 pipe_name(intel_crtc->pipe));
1340 return false;
1341 }
1342
1343 /* shared DPLL id 0 is DPLL 1 */
190f68c5 1344 crtc_state->ddi_pll_sel = pll->id + 1;
82d35437
S		 1345
1346 return true;
1347}
0220ab6e 1348
d683f3bc
S		 1349/* bxt clock parameters */
1350struct bxt_clk_div {
64987fc5 1351 int clock;
d683f3bc
S		 1352 uint32_t p1;
1353 uint32_t p2;
1354 uint32_t m2_int;
1355 uint32_t m2_frac;
1356 bool m2_frac_en;
1357 uint32_t n;
d683f3bc
S		 1358};
1359
1360/* pre-calculated values for DP linkrates */
64987fc5
SJ		 1361static const struct bxt_clk_div bxt_dp_clk_val[] = {
1362 {162000, 4, 2, 32, 1677722, 1, 1},
1363 {270000, 4, 1, 27, 0, 0, 1},
1364 {540000, 2, 1, 27, 0, 0, 1},
1365 {216000, 3, 2, 32, 1677722, 1, 1},
1366 {243000, 4, 1, 24, 1258291, 1, 1},
1367 {324000, 4, 1, 32, 1677722, 1, 1},
1368 {432000, 3, 1, 32, 1677722, 1, 1}
d683f3bc
S		 1369};
1370
1371static bool
1372bxt_ddi_pll_select(struct intel_crtc *intel_crtc,
1373 struct intel_crtc_state *crtc_state,
1374 struct intel_encoder *intel_encoder,
1375 int clock)
1376{
1377 struct intel_shared_dpll *pll;
1378 struct bxt_clk_div clk_div = {0};
b6dc71f3
VK		 1379 int vco = 0;
1380 uint32_t prop_coef, int_coef, gain_ctl, targ_cnt;
e0681e38 1381 uint32_t dcoampovr_en_h, dco_amp, lanestagger;
d683f3bc
S		 1382
1383 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
1384 intel_clock_t best_clock;
1385
1386 /* Calculate HDMI div */
1387 /*
1388 * FIXME: tie the following calculation into
1389 * i9xx_crtc_compute_clock
1390 */
1391 if (!bxt_find_best_dpll(crtc_state, clock, &best_clock)) {
1392 DRM_DEBUG_DRIVER("no PLL dividers found for clock %d pipe %c\n",
1393 clock, pipe_name(intel_crtc->pipe));
1394 return false;
1395 }
1396
1397 clk_div.p1 = best_clock.p1;
1398 clk_div.p2 = best_clock.p2;
1399 WARN_ON(best_clock.m1 != 2);
1400 clk_div.n = best_clock.n;
1401 clk_div.m2_int = best_clock.m2 >> 22;
1402 clk_div.m2_frac = best_clock.m2 & ((1 << 22) - 1);
1403 clk_div.m2_frac_en = clk_div.m2_frac != 0;
1404
b6dc71f3 1405 vco = best_clock.vco;
d683f3bc
S		 1406 } else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
1407 intel_encoder->type == INTEL_OUTPUT_EDP) {
64987fc5 1408 int i;
d683f3bc 1409
64987fc5
SJ		 1410 clk_div = bxt_dp_clk_val[0];
1411 for (i = 0; i < ARRAY_SIZE(bxt_dp_clk_val); ++i) {
1412 if (bxt_dp_clk_val[i].clock == clock) {
1413 clk_div = bxt_dp_clk_val[i];
1414 break;
1415 }
d683f3bc 1416 }
b6dc71f3
VK		 1417 vco = clock * 10 / 2 * clk_div.p1 * clk_div.p2;
1418 }
1419
1420 dco_amp = 15;
1421 dcoampovr_en_h = 0;
1422 if (vco >= 6200000 && vco <= 6480000) {
1423 prop_coef = 4;
1424 int_coef = 9;
1425 gain_ctl = 3;
1426 targ_cnt = 8;
1427 } else if ((vco > 5400000 && vco < 6200000) ||
1428 (vco >= 4800000 && vco < 5400000)) {
1429 prop_coef = 5;
1430 int_coef = 11;
1431 gain_ctl = 3;
1432 targ_cnt = 9;
1433 if (vco >= 4800000 && vco < 5400000)
1434 dcoampovr_en_h = 1;
1435 } else if (vco == 5400000) {
1436 prop_coef = 3;
1437 int_coef = 8;
1438 gain_ctl = 1;
1439 targ_cnt = 9;
1440 } else {
1441 DRM_ERROR("Invalid VCO\n");
1442 return false;
d683f3bc
S		 1443 }
1444
dd3cd74a
ACO		 1445 memset(&crtc_state->dpll_hw_state, 0,
1446 sizeof(crtc_state->dpll_hw_state));
1447
e0681e38
VK		 1448 if (clock > 270000)
1449 lanestagger = 0x18;
1450 else if (clock > 135000)
1451 lanestagger = 0x0d;
1452 else if (clock > 67000)
1453 lanestagger = 0x07;
1454 else if (clock > 33000)
1455 lanestagger = 0x04;
1456 else
1457 lanestagger = 0x02;
1458
d683f3bc
S		 1459 crtc_state->dpll_hw_state.ebb0 =
1460 PORT_PLL_P1(clk_div.p1) | PORT_PLL_P2(clk_div.p2);
1461 crtc_state->dpll_hw_state.pll0 = clk_div.m2_int;
1462 crtc_state->dpll_hw_state.pll1 = PORT_PLL_N(clk_div.n);
1463 crtc_state->dpll_hw_state.pll2 = clk_div.m2_frac;
1464
1465 if (clk_div.m2_frac_en)
1466 crtc_state->dpll_hw_state.pll3 =
1467 PORT_PLL_M2_FRAC_ENABLE;
1468
1469 crtc_state->dpll_hw_state.pll6 =
b6dc71f3 1470 prop_coef | PORT_PLL_INT_COEFF(int_coef);
d683f3bc 1471 crtc_state->dpll_hw_state.pll6 |=
b6dc71f3
VK		 1472 PORT_PLL_GAIN_CTL(gain_ctl);
1473
1474 crtc_state->dpll_hw_state.pll8 = targ_cnt;
d683f3bc 1475
b6dc71f3
VK		 1476 if (dcoampovr_en_h)
1477 crtc_state->dpll_hw_state.pll10 = PORT_PLL_DCO_AMP_OVR_EN_H;
1478
1479 crtc_state->dpll_hw_state.pll10 |= PORT_PLL_DCO_AMP(dco_amp);
d683f3bc
S		 1480
1481 crtc_state->dpll_hw_state.pcsdw12 =
e0681e38 1482 LANESTAGGER_STRAP_OVRD | lanestagger;
d683f3bc
S		 1483
1484 pll = intel_get_shared_dpll(intel_crtc, crtc_state);
1485 if (pll == NULL) {
1486 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
1487 pipe_name(intel_crtc->pipe));
1488 return false;
1489 }
1490
1491 /* shared DPLL id 0 is DPLL A */
1492 crtc_state->ddi_pll_sel = pll->id;
1493
1494 return true;
1495}
1496
0220ab6e
DL		 1497/*
1498 * Tries to find a *shared* PLL for the CRTC and store it in
1499 * intel_crtc->ddi_pll_sel.
1500 *
1501 * For private DPLLs, compute_config() should do the selection for us. This
1502 * function should be folded into compute_config() eventually.
1503 */
190f68c5
ACO		 1504bool intel_ddi_pll_select(struct intel_crtc *intel_crtc,
1505 struct intel_crtc_state *crtc_state)
0220ab6e 1506{
82d35437 1507 struct drm_device *dev = intel_crtc->base.dev;
d0737e1d 1508 struct intel_encoder *intel_encoder =
3165c074 1509 intel_ddi_get_crtc_new_encoder(crtc_state);
190f68c5 1510 int clock = crtc_state->port_clock;
0220ab6e 1511
82d35437 1512 if (IS_SKYLAKE(dev))
190f68c5
ACO		 1513 return skl_ddi_pll_select(intel_crtc, crtc_state,
1514 intel_encoder, clock);
d683f3bc
S		 1515 else if (IS_BROXTON(dev))
1516 return bxt_ddi_pll_select(intel_crtc, crtc_state,
1517 intel_encoder, clock);
82d35437 1518 else
190f68c5
ACO		 1519 return hsw_ddi_pll_select(intel_crtc, crtc_state,
1520 intel_encoder, clock);
0220ab6e
DL		 1521}
1522
dae84799
PZ		 1523void intel_ddi_set_pipe_settings(struct drm_crtc *crtc)
1524{
1525 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1526 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1527 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
6e3c9717 1528 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
dae84799
PZ		 1529 int type = intel_encoder->type;
1530 uint32_t temp;
1531
0e32b39c 1532 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP || type == INTEL_OUTPUT_DP_MST) {
c9809791 1533 temp = TRANS_MSA_SYNC_CLK;
6e3c9717 1534 switch (intel_crtc->config->pipe_bpp) {
dae84799 1535 case 18:
c9809791 1536 temp |= TRANS_MSA_6_BPC;
dae84799
PZ		 1537 break;
1538 case 24:
c9809791 1539 temp |= TRANS_MSA_8_BPC;
dae84799
PZ		 1540 break;
1541 case 30:
c9809791 1542 temp |= TRANS_MSA_10_BPC;
dae84799
PZ		 1543 break;
1544 case 36:
c9809791 1545 temp |= TRANS_MSA_12_BPC;
dae84799
PZ		 1546 break;
1547 default:
4e53c2e0 1548 BUG();
dae84799 1549 }
c9809791 1550 I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
dae84799
PZ		 1551 }
1552}
1553
0e32b39c
DA		 1554void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state)
1555{
1556 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1557 struct drm_device *dev = crtc->dev;
1558 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 1559 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
0e32b39c
DA		 1560 uint32_t temp;
1561 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1562 if (state == true)
1563 temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1564 else
1565 temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1566 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1567}
1568
8228c251 1569void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc)
8d9ddbcb
PZ		 1570{
1571 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1572 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
7739c33b 1573 struct drm_encoder *encoder = &intel_encoder->base;
c7670b10
PZ		 1574 struct drm_device *dev = crtc->dev;
1575 struct drm_i915_private *dev_priv = dev->dev_private;
8d9ddbcb 1576 enum pipe pipe = intel_crtc->pipe;
6e3c9717 1577 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
174edf1f 1578 enum port port = intel_ddi_get_encoder_port(intel_encoder);
7739c33b 1579 int type = intel_encoder->type;
8d9ddbcb
PZ		 1580 uint32_t temp;
1581
ad80a810
PZ		 1582 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
1583 temp = TRANS_DDI_FUNC_ENABLE;
174edf1f 1584 temp |= TRANS_DDI_SELECT_PORT(port);
dfcef252 1585
6e3c9717 1586 switch (intel_crtc->config->pipe_bpp) {
dfcef252 1587 case 18:
ad80a810 1588 temp |= TRANS_DDI_BPC_6;
dfcef252
PZ		 1589 break;
1590 case 24:
ad80a810 1591 temp |= TRANS_DDI_BPC_8;
dfcef252
PZ		 1592 break;
1593 case 30:
ad80a810 1594 temp |= TRANS_DDI_BPC_10;
dfcef252
PZ		 1595 break;
1596 case 36:
ad80a810 1597 temp |= TRANS_DDI_BPC_12;
dfcef252
PZ		 1598 break;
1599 default:
4e53c2e0 1600 BUG();
dfcef252 1601 }
72662e10 1602
6e3c9717 1603 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
ad80a810 1604 temp |= TRANS_DDI_PVSYNC;
6e3c9717 1605 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
ad80a810 1606 temp |= TRANS_DDI_PHSYNC;
f63eb7c4 1607
e6f0bfc4
PZ		 1608 if (cpu_transcoder == TRANSCODER_EDP) {
1609 switch (pipe) {
1610 case PIPE_A:
c7670b10
PZ		 1611 /* On Haswell, can only use the always-on power well for
1612 * eDP when not using the panel fitter, and when not
1613 * using motion blur mitigation (which we don't
1614 * support). */
fabf6e51 1615 if (IS_HASWELL(dev) &&
6e3c9717
ACO		 1616 (intel_crtc->config->pch_pfit.enabled ||
1617 intel_crtc->config->pch_pfit.force_thru))
d6dd9eb1
DV		 1618 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
1619 else
1620 temp |= TRANS_DDI_EDP_INPUT_A_ON;
e6f0bfc4
PZ		 1621 break;
1622 case PIPE_B:
1623 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
1624 break;
1625 case PIPE_C:
1626 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
1627 break;
1628 default:
1629 BUG();
1630 break;
1631 }
1632 }
1633
7739c33b 1634 if (type == INTEL_OUTPUT_HDMI) {
6e3c9717 1635 if (intel_crtc->config->has_hdmi_sink)
ad80a810 1636 temp |= TRANS_DDI_MODE_SELECT_HDMI;
8d9ddbcb 1637 else
ad80a810 1638 temp |= TRANS_DDI_MODE_SELECT_DVI;
8d9ddbcb 1639
7739c33b 1640 } else if (type == INTEL_OUTPUT_ANALOG) {
ad80a810 1641 temp |= TRANS_DDI_MODE_SELECT_FDI;
6e3c9717 1642 temp |= (intel_crtc->config->fdi_lanes - 1) << 1;
7739c33b
PZ		 1643
1644 } else if (type == INTEL_OUTPUT_DISPLAYPORT ||
1645 type == INTEL_OUTPUT_EDP) {
1646 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1647
0e32b39c
DA		 1648 if (intel_dp->is_mst) {
1649 temp |= TRANS_DDI_MODE_SELECT_DP_MST;
1650 } else
1651 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
1652
1653 temp |= DDI_PORT_WIDTH(intel_dp->lane_count);
1654 } else if (type == INTEL_OUTPUT_DP_MST) {
1655 struct intel_dp *intel_dp = &enc_to_mst(encoder)->primary->dp;
1656
1657 if (intel_dp->is_mst) {
1658 temp |= TRANS_DDI_MODE_SELECT_DP_MST;
1659 } else
1660 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
7739c33b 1661
17aa6be9 1662 temp |= DDI_PORT_WIDTH(intel_dp->lane_count);
8d9ddbcb 1663 } else {
84f44ce7
VS		 1664 WARN(1, "Invalid encoder type %d for pipe %c\n",
1665 intel_encoder->type, pipe_name(pipe));
8d9ddbcb
PZ		 1666 }
1667
ad80a810 1668 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
8d9ddbcb 1669}
72662e10 1670
ad80a810
PZ		 1671void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
1672 enum transcoder cpu_transcoder)
8d9ddbcb 1673{
ad80a810 1674 uint32_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
8d9ddbcb
PZ		 1675 uint32_t val = I915_READ(reg);
1676
0e32b39c 1677 val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
ad80a810 1678 val |= TRANS_DDI_PORT_NONE;
8d9ddbcb 1679 I915_WRITE(reg, val);
72662e10
ED		 1680}
1681
bcbc889b
PZ		 1682bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
1683{
1684 struct drm_device *dev = intel_connector->base.dev;
1685 struct drm_i915_private *dev_priv = dev->dev_private;
1686 struct intel_encoder *intel_encoder = intel_connector->encoder;
1687 int type = intel_connector->base.connector_type;
1688 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1689 enum pipe pipe = 0;
1690 enum transcoder cpu_transcoder;
882244a3 1691 enum intel_display_power_domain power_domain;
bcbc889b
PZ		 1692 uint32_t tmp;
1693
882244a3 1694 power_domain = intel_display_port_power_domain(intel_encoder);
f458ebbc 1695 if (!intel_display_power_is_enabled(dev_priv, power_domain))
882244a3
PZ		 1696 return false;
1697
bcbc889b
PZ		 1698 if (!intel_encoder->get_hw_state(intel_encoder, &pipe))
1699 return false;
1700
1701 if (port == PORT_A)
1702 cpu_transcoder = TRANSCODER_EDP;
1703 else
1a240d4d 1704 cpu_transcoder = (enum transcoder) pipe;
bcbc889b
PZ		 1705
1706 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1707
1708 switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
1709 case TRANS_DDI_MODE_SELECT_HDMI:
1710 case TRANS_DDI_MODE_SELECT_DVI:
1711 return (type == DRM_MODE_CONNECTOR_HDMIA);
1712
1713 case TRANS_DDI_MODE_SELECT_DP_SST:
1714 if (type == DRM_MODE_CONNECTOR_eDP)
1715 return true;
bcbc889b 1716 return (type == DRM_MODE_CONNECTOR_DisplayPort);
0e32b39c
DA		 1717 case TRANS_DDI_MODE_SELECT_DP_MST:
1718 /* if the transcoder is in MST state then
1719 * connector isn't connected */
1720 return false;
bcbc889b
PZ		 1721
1722 case TRANS_DDI_MODE_SELECT_FDI:
1723 return (type == DRM_MODE_CONNECTOR_VGA);
1724
1725 default:
1726 return false;
1727 }
1728}
1729
85234cdc
DV		 1730bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
1731 enum pipe *pipe)
1732{
1733 struct drm_device *dev = encoder->base.dev;
1734 struct drm_i915_private *dev_priv = dev->dev_private;
fe43d3f5 1735 enum port port = intel_ddi_get_encoder_port(encoder);
6d129bea 1736 enum intel_display_power_domain power_domain;
85234cdc
DV		 1737 u32 tmp;
1738 int i;
1739
6d129bea 1740 power_domain = intel_display_port_power_domain(encoder);
f458ebbc 1741 if (!intel_display_power_is_enabled(dev_priv, power_domain))
6d129bea
ID		 1742 return false;
1743
fe43d3f5 1744 tmp = I915_READ(DDI_BUF_CTL(port));
85234cdc
DV		 1745
1746 if (!(tmp & DDI_BUF_CTL_ENABLE))
1747 return false;
1748
ad80a810
PZ		 1749 if (port == PORT_A) {
1750 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
85234cdc 1751
ad80a810
PZ		 1752 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
1753 case TRANS_DDI_EDP_INPUT_A_ON:
1754 case TRANS_DDI_EDP_INPUT_A_ONOFF:
1755 *pipe = PIPE_A;
1756 break;
1757 case TRANS_DDI_EDP_INPUT_B_ONOFF:
1758 *pipe = PIPE_B;
1759 break;
1760 case TRANS_DDI_EDP_INPUT_C_ONOFF:
1761 *pipe = PIPE_C;
1762 break;
1763 }
1764
1765 return true;
1766 } else {
1767 for (i = TRANSCODER_A; i <= TRANSCODER_C; i++) {
1768 tmp = I915_READ(TRANS_DDI_FUNC_CTL(i));
1769
1770 if ((tmp & TRANS_DDI_PORT_MASK)
1771 == TRANS_DDI_SELECT_PORT(port)) {
0e32b39c
DA		 1772 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_DP_MST)
1773 return false;
1774
ad80a810
PZ		 1775 *pipe = i;
1776 return true;
1777 }
85234cdc
DV		 1778 }
1779 }
1780
84f44ce7 1781 DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port));
85234cdc 1782
22f9fe50 1783 return false;
85234cdc
DV		 1784}
1785
fc914639
PZ		 1786void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc)
1787{
1788 struct drm_crtc *crtc = &intel_crtc->base;
1789 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1790 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
1791 enum port port = intel_ddi_get_encoder_port(intel_encoder);
6e3c9717 1792 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
fc914639 1793
bb523fc0
PZ		 1794 if (cpu_transcoder != TRANSCODER_EDP)
1795 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
1796 TRANS_CLK_SEL_PORT(port));
fc914639
PZ		 1797}
1798
1799void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc)
1800{
1801 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
6e3c9717 1802 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
fc914639 1803
bb523fc0
PZ		 1804 if (cpu_transcoder != TRANSCODER_EDP)
1805 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
1806 TRANS_CLK_SEL_DISABLED);
fc914639
PZ		 1807}
1808
96fb9f9b
VK		 1809void bxt_ddi_vswing_sequence(struct drm_device *dev, u32 level,
1810 enum port port, int type)
1811{
1812 struct drm_i915_private *dev_priv = dev->dev_private;
1813 const struct bxt_ddi_buf_trans *ddi_translations;
1814 u32 n_entries, i;
1815 uint32_t val;
1816
1817 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
1818 n_entries = ARRAY_SIZE(bxt_ddi_translations_dp);
1819 ddi_translations = bxt_ddi_translations_dp;
1820 } else if (type == INTEL_OUTPUT_HDMI) {
1821 n_entries = ARRAY_SIZE(bxt_ddi_translations_hdmi);
1822 ddi_translations = bxt_ddi_translations_hdmi;
1823 } else {
1824 DRM_DEBUG_KMS("Vswing programming not done for encoder %d\n",
1825 type);
1826 return;
1827 }
1828
1829 /* Check if default value has to be used */
1830 if (level >= n_entries ||
1831 (type == INTEL_OUTPUT_HDMI && level == HDMI_LEVEL_SHIFT_UNKNOWN)) {
1832 for (i = 0; i < n_entries; i++) {
1833 if (ddi_translations[i].default_index) {
1834 level = i;
1835 break;
1836 }
1837 }
1838 }
1839
1840 /*
1841 * While we write to the group register to program all lanes at once we
1842 * can read only lane registers and we pick lanes 0/1 for that.
1843 */
1844 val = I915_READ(BXT_PORT_PCS_DW10_LN01(port));
1845 val &= ~(TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT);
1846 I915_WRITE(BXT_PORT_PCS_DW10_GRP(port), val);
1847
1848 val = I915_READ(BXT_PORT_TX_DW2_LN0(port));
1849 val &= ~(MARGIN_000 | UNIQ_TRANS_SCALE);
1850 val |= ddi_translations[level].margin << MARGIN_000_SHIFT |
1851 ddi_translations[level].scale << UNIQ_TRANS_SCALE_SHIFT;
1852 I915_WRITE(BXT_PORT_TX_DW2_GRP(port), val);
1853
1854 val = I915_READ(BXT_PORT_TX_DW3_LN0(port));
1855 val &= ~UNIQE_TRANGE_EN_METHOD;
1856 if (ddi_translations[level].enable)
1857 val |= UNIQE_TRANGE_EN_METHOD;
1858 I915_WRITE(BXT_PORT_TX_DW3_GRP(port), val);
1859
1860 val = I915_READ(BXT_PORT_TX_DW4_LN0(port));
1861 val &= ~DE_EMPHASIS;
1862 val |= ddi_translations[level].deemphasis << DEEMPH_SHIFT;
1863 I915_WRITE(BXT_PORT_TX_DW4_GRP(port), val);
1864
1865 val = I915_READ(BXT_PORT_PCS_DW10_LN01(port));
1866 val |= TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT;
1867 I915_WRITE(BXT_PORT_PCS_DW10_GRP(port), val);
1868}
1869
00c09d70 1870static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder)
6441ab5f 1871{
c19b0669 1872 struct drm_encoder *encoder = &intel_encoder->base;
efa80add
S		 1873 struct drm_device *dev = encoder->dev;
1874 struct drm_i915_private *dev_priv = dev->dev_private;
30cf6db8 1875 struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
6441ab5f 1876 enum port port = intel_ddi_get_encoder_port(intel_encoder);
82a4d9c0 1877 int type = intel_encoder->type;
96fb9f9b 1878 int hdmi_level;
6441ab5f 1879
82a4d9c0
PZ		 1880 if (type == INTEL_OUTPUT_EDP) {
1881 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4be73780 1882 intel_edp_panel_on(intel_dp);
82a4d9c0 1883 }
6441ab5f 1884
efa80add 1885 if (IS_SKYLAKE(dev)) {
6e3c9717 1886 uint32_t dpll = crtc->config->ddi_pll_sel;
efa80add
S		 1887 uint32_t val;
1888
5416d871
DL		 1889 /*
1890 * DPLL0 is used for eDP and is the only "private" DPLL (as
1891 * opposed to shared) on SKL
1892 */
1893 if (type == INTEL_OUTPUT_EDP) {
1894 WARN_ON(dpll != SKL_DPLL0);
1895
1896 val = I915_READ(DPLL_CTRL1);
1897
1898 val &= ~(DPLL_CTRL1_HDMI_MODE(dpll) |
1899 DPLL_CTRL1_SSC(dpll) |
71cd8423 1900 DPLL_CTRL1_LINK_RATE_MASK(dpll));
6e3c9717 1901 val |= crtc->config->dpll_hw_state.ctrl1 << (dpll * 6);
5416d871
DL		 1902
1903 I915_WRITE(DPLL_CTRL1, val);
1904 POSTING_READ(DPLL_CTRL1);
1905 }
1906
1907 /* DDI -> PLL mapping */
efa80add
S		 1908 val = I915_READ(DPLL_CTRL2);
1909
1910 val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) |
1911 DPLL_CTRL2_DDI_CLK_SEL_MASK(port));
1912 val |= (DPLL_CTRL2_DDI_CLK_SEL(dpll, port) |
1913 DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
1914
1915 I915_WRITE(DPLL_CTRL2, val);
5416d871 1916
1ab23380 1917 } else if (INTEL_INFO(dev)->gen < 9) {
6e3c9717
ACO		 1918 WARN_ON(crtc->config->ddi_pll_sel == PORT_CLK_SEL_NONE);
1919 I915_WRITE(PORT_CLK_SEL(port), crtc->config->ddi_pll_sel);
efa80add 1920 }
c19b0669 1921
82a4d9c0 1922 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
c19b0669 1923 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
30cf6db8 1924
44905a27 1925 intel_ddi_init_dp_buf_reg(intel_encoder);
c19b0669
PZ		 1926
1927 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1928 intel_dp_start_link_train(intel_dp);
1929 intel_dp_complete_link_train(intel_dp);
23f08d83 1930 if (port != PORT_A || INTEL_INFO(dev)->gen >= 9)
3ab9c637 1931 intel_dp_stop_link_train(intel_dp);
30cf6db8
DV		 1932 } else if (type == INTEL_OUTPUT_HDMI) {
1933 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
1934
96fb9f9b
VK		 1935 if (IS_BROXTON(dev)) {
1936 hdmi_level = dev_priv->vbt.
1937 ddi_port_info[port].hdmi_level_shift;
1938 bxt_ddi_vswing_sequence(dev, hdmi_level, port,
1939 INTEL_OUTPUT_HDMI);
1940 }
30cf6db8 1941 intel_hdmi->set_infoframes(encoder,
6e3c9717
ACO		 1942 crtc->config->has_hdmi_sink,
1943 &crtc->config->base.adjusted_mode);
c19b0669 1944 }
6441ab5f
PZ		 1945}
1946
00c09d70 1947static void intel_ddi_post_disable(struct intel_encoder *intel_encoder)
6441ab5f
PZ		 1948{
1949 struct drm_encoder *encoder = &intel_encoder->base;
efa80add
S		 1950 struct drm_device *dev = encoder->dev;
1951 struct drm_i915_private *dev_priv = dev->dev_private;
6441ab5f 1952 enum port port = intel_ddi_get_encoder_port(intel_encoder);
82a4d9c0 1953 int type = intel_encoder->type;
2886e93f 1954 uint32_t val;
a836bdf9 1955 bool wait = false;
2886e93f
PZ		 1956
1957 val = I915_READ(DDI_BUF_CTL(port));
1958 if (val & DDI_BUF_CTL_ENABLE) {
1959 val &= ~DDI_BUF_CTL_ENABLE;
1960 I915_WRITE(DDI_BUF_CTL(port), val);
a836bdf9 1961 wait = true;
2886e93f 1962 }
6441ab5f 1963
a836bdf9
PZ		 1964 val = I915_READ(DP_TP_CTL(port));
1965 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
1966 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
1967 I915_WRITE(DP_TP_CTL(port), val);
1968
1969 if (wait)
1970 intel_wait_ddi_buf_idle(dev_priv, port);
1971
76bb80ed 1972 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
82a4d9c0 1973 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
76bb80ed 1974 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
24f3e092 1975 intel_edp_panel_vdd_on(intel_dp);
4be73780 1976 intel_edp_panel_off(intel_dp);
82a4d9c0
PZ		 1977 }
1978
efa80add
S		 1979 if (IS_SKYLAKE(dev))
1980 I915_WRITE(DPLL_CTRL2, (I915_READ(DPLL_CTRL2) |
1981 DPLL_CTRL2_DDI_CLK_OFF(port)));
1ab23380 1982 else if (INTEL_INFO(dev)->gen < 9)
efa80add 1983 I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
6441ab5f
PZ		 1984}
1985
00c09d70 1986static void intel_enable_ddi(struct intel_encoder *intel_encoder)
72662e10 1987{
6547fef8 1988 struct drm_encoder *encoder = &intel_encoder->base;
7b9f35a6
WX		 1989 struct drm_crtc *crtc = encoder->crtc;
1990 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6547fef8 1991 struct drm_device *dev = encoder->dev;
72662e10 1992 struct drm_i915_private *dev_priv = dev->dev_private;
6547fef8
PZ		 1993 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1994 int type = intel_encoder->type;
72662e10 1995
6547fef8 1996 if (type == INTEL_OUTPUT_HDMI) {
876a8cdf
DL		 1997 struct intel_digital_port *intel_dig_port =
1998 enc_to_dig_port(encoder);
1999
6547fef8
PZ		 2000 /* In HDMI/DVI mode, the port width, and swing/emphasis values
2001 * are ignored so nothing special needs to be done besides
2002 * enabling the port.
2003 */
876a8cdf 2004 I915_WRITE(DDI_BUF_CTL(port),
bcf53de4
SM		 2005 intel_dig_port->saved_port_bits |
2006 DDI_BUF_CTL_ENABLE);
d6c50ff8
PZ		 2007 } else if (type == INTEL_OUTPUT_EDP) {
2008 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2009
23f08d83 2010 if (port == PORT_A && INTEL_INFO(dev)->gen < 9)
3ab9c637
ID		 2011 intel_dp_stop_link_train(intel_dp);
2012
4be73780 2013 intel_edp_backlight_on(intel_dp);
0bc12bcb 2014 intel_psr_enable(intel_dp);
c395578e 2015 intel_edp_drrs_enable(intel_dp);
6547fef8 2016 }
7b9f35a6 2017
6e3c9717 2018 if (intel_crtc->config->has_audio) {
d45a0bf5 2019 intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
69bfe1a9 2020 intel_audio_codec_enable(intel_encoder);
7b9f35a6 2021 }
5ab432ef
DV		 2022}
2023
00c09d70 2024static void intel_disable_ddi(struct intel_encoder *intel_encoder)
5ab432ef 2025{
d6c50ff8 2026 struct drm_encoder *encoder = &intel_encoder->base;
7b9f35a6
WX		 2027 struct drm_crtc *crtc = encoder->crtc;
2028 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
d6c50ff8 2029 int type = intel_encoder->type;
7b9f35a6
WX		 2030 struct drm_device *dev = encoder->dev;
2031 struct drm_i915_private *dev_priv = dev->dev_private;
d6c50ff8 2032
6e3c9717 2033 if (intel_crtc->config->has_audio) {
69bfe1a9 2034 intel_audio_codec_disable(intel_encoder);
d45a0bf5
PZ		 2035 intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO);
2036 }
2831d842 2037
d6c50ff8
PZ		 2038 if (type == INTEL_OUTPUT_EDP) {
2039 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2040
c395578e 2041 intel_edp_drrs_disable(intel_dp);
0bc12bcb 2042 intel_psr_disable(intel_dp);
4be73780 2043 intel_edp_backlight_off(intel_dp);
d6c50ff8 2044 }
72662e10 2045}
79f689aa 2046
e0b01be4
DV		 2047static void hsw_ddi_pll_enable(struct drm_i915_private *dev_priv,
2048 struct intel_shared_dpll *pll)
2049{
3e369b76 2050 I915_WRITE(WRPLL_CTL(pll->id), pll->config.hw_state.wrpll);
e0b01be4
DV		 2051 POSTING_READ(WRPLL_CTL(pll->id));
2052 udelay(20);
2053}
2054
12030431
DV		 2055static void hsw_ddi_pll_disable(struct drm_i915_private *dev_priv,
2056 struct intel_shared_dpll *pll)
2057{
2058 uint32_t val;
2059
2060 val = I915_READ(WRPLL_CTL(pll->id));
12030431
DV		 2061 I915_WRITE(WRPLL_CTL(pll->id), val & ~WRPLL_PLL_ENABLE);
2062 POSTING_READ(WRPLL_CTL(pll->id));
2063}
2064
d452c5b6
DV		 2065static bool hsw_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
2066 struct intel_shared_dpll *pll,
2067 struct intel_dpll_hw_state *hw_state)
2068{
2069 uint32_t val;
2070
f458ebbc 2071 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
d452c5b6
DV		 2072 return false;
2073
2074 val = I915_READ(WRPLL_CTL(pll->id));
2075 hw_state->wrpll = val;
2076
2077 return val & WRPLL_PLL_ENABLE;
2078}
2079
ca1381b5 2080static const char * const hsw_ddi_pll_names[] = {
9cd86933
DV		 2081 "WRPLL 1",
2082 "WRPLL 2",
2083};
2084
143b307c 2085static void hsw_shared_dplls_init(struct drm_i915_private *dev_priv)
79f689aa 2086{
9cd86933
DV		 2087 int i;
2088
716c2e55 2089 dev_priv->num_shared_dpll = 2;
9cd86933 2090
716c2e55 2091 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
9cd86933
DV		 2092 dev_priv->shared_dplls[i].id = i;
2093 dev_priv->shared_dplls[i].name = hsw_ddi_pll_names[i];
12030431 2094 dev_priv->shared_dplls[i].disable = hsw_ddi_pll_disable;
e0b01be4 2095 dev_priv->shared_dplls[i].enable = hsw_ddi_pll_enable;
d452c5b6
DV		 2096 dev_priv->shared_dplls[i].get_hw_state =
2097 hsw_ddi_pll_get_hw_state;
9cd86933 2098 }
143b307c
DL		 2099}
2100
d1a2dc78
S		 2101static const char * const skl_ddi_pll_names[] = {
2102 "DPLL 1",
2103 "DPLL 2",
2104 "DPLL 3",
2105};
2106
2107struct skl_dpll_regs {
2108 u32 ctl, cfgcr1, cfgcr2;
2109};
2110
2111/* this array is indexed by the *shared* pll id */
2112static const struct skl_dpll_regs skl_dpll_regs[3] = {
2113 {
2114 /* DPLL 1 */
2115 .ctl = LCPLL2_CTL,
2116 .cfgcr1 = DPLL1_CFGCR1,
2117 .cfgcr2 = DPLL1_CFGCR2,
2118 },
2119 {
2120 /* DPLL 2 */
2121 .ctl = WRPLL_CTL1,
2122 .cfgcr1 = DPLL2_CFGCR1,
2123 .cfgcr2 = DPLL2_CFGCR2,
2124 },
2125 {
2126 /* DPLL 3 */
2127 .ctl = WRPLL_CTL2,
2128 .cfgcr1 = DPLL3_CFGCR1,
2129 .cfgcr2 = DPLL3_CFGCR2,
2130 },
2131};
2132
2133static void skl_ddi_pll_enable(struct drm_i915_private *dev_priv,
2134 struct intel_shared_dpll *pll)
2135{
2136 uint32_t val;
2137 unsigned int dpll;
2138 const struct skl_dpll_regs *regs = skl_dpll_regs;
2139
2140 /* DPLL0 is not part of the shared DPLLs, so pll->id is 0 for DPLL1 */
2141 dpll = pll->id + 1;
2142
2143 val = I915_READ(DPLL_CTRL1);
2144
2145 val &= ~(DPLL_CTRL1_HDMI_MODE(dpll) | DPLL_CTRL1_SSC(dpll) |
71cd8423 2146 DPLL_CTRL1_LINK_RATE_MASK(dpll));
d1a2dc78
S		 2147 val |= pll->config.hw_state.ctrl1 << (dpll * 6);
2148
2149 I915_WRITE(DPLL_CTRL1, val);
2150 POSTING_READ(DPLL_CTRL1);
2151
2152 I915_WRITE(regs[pll->id].cfgcr1, pll->config.hw_state.cfgcr1);
2153 I915_WRITE(regs[pll->id].cfgcr2, pll->config.hw_state.cfgcr2);
2154 POSTING_READ(regs[pll->id].cfgcr1);
2155 POSTING_READ(regs[pll->id].cfgcr2);
2156
2157 /* the enable bit is always bit 31 */
2158 I915_WRITE(regs[pll->id].ctl,
2159 I915_READ(regs[pll->id].ctl) | LCPLL_PLL_ENABLE);
2160
2161 if (wait_for(I915_READ(DPLL_STATUS) & DPLL_LOCK(dpll), 5))
2162 DRM_ERROR("DPLL %d not locked\n", dpll);
2163}
2164
2165static void skl_ddi_pll_disable(struct drm_i915_private *dev_priv,
2166 struct intel_shared_dpll *pll)
2167{
2168 const struct skl_dpll_regs *regs = skl_dpll_regs;
2169
2170 /* the enable bit is always bit 31 */
2171 I915_WRITE(regs[pll->id].ctl,
2172 I915_READ(regs[pll->id].ctl) & ~LCPLL_PLL_ENABLE);
2173 POSTING_READ(regs[pll->id].ctl);
2174}
2175
2176static bool skl_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
2177 struct intel_shared_dpll *pll,
2178 struct intel_dpll_hw_state *hw_state)
2179{
2180 uint32_t val;
2181 unsigned int dpll;
2182 const struct skl_dpll_regs *regs = skl_dpll_regs;
2183
2184 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
2185 return false;
2186
2187 /* DPLL0 is not part of the shared DPLLs, so pll->id is 0 for DPLL1 */
2188 dpll = pll->id + 1;
2189
2190 val = I915_READ(regs[pll->id].ctl);
2191 if (!(val & LCPLL_PLL_ENABLE))
2192 return false;
2193
2194 val = I915_READ(DPLL_CTRL1);
2195 hw_state->ctrl1 = (val >> (dpll * 6)) & 0x3f;
2196
2197 /* avoid reading back stale values if HDMI mode is not enabled */
2198 if (val & DPLL_CTRL1_HDMI_MODE(dpll)) {
2199 hw_state->cfgcr1 = I915_READ(regs[pll->id].cfgcr1);
2200 hw_state->cfgcr2 = I915_READ(regs[pll->id].cfgcr2);
2201 }
2202
2203 return true;
2204}
2205
2206static void skl_shared_dplls_init(struct drm_i915_private *dev_priv)
2207{
2208 int i;
2209
2210 dev_priv->num_shared_dpll = 3;
2211
2212 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
2213 dev_priv->shared_dplls[i].id = i;
2214 dev_priv->shared_dplls[i].name = skl_ddi_pll_names[i];
2215 dev_priv->shared_dplls[i].disable = skl_ddi_pll_disable;
2216 dev_priv->shared_dplls[i].enable = skl_ddi_pll_enable;
2217 dev_priv->shared_dplls[i].get_hw_state =
2218 skl_ddi_pll_get_hw_state;
2219 }
2220}
2221
5c6706e5
VK		 2222static void broxton_phy_init(struct drm_i915_private *dev_priv,
2223 enum dpio_phy phy)
2224{
2225 enum port port;
2226 uint32_t val;
2227
2228 val = I915_READ(BXT_P_CR_GT_DISP_PWRON);
2229 val |= GT_DISPLAY_POWER_ON(phy);
2230 I915_WRITE(BXT_P_CR_GT_DISP_PWRON, val);
2231
2232 /* Considering 10ms timeout until BSpec is updated */
2233 if (wait_for(I915_READ(BXT_PORT_CL1CM_DW0(phy)) & PHY_POWER_GOOD, 10))
2234 DRM_ERROR("timeout during PHY%d power on\n", phy);
2235
2236 for (port = (phy == DPIO_PHY0 ? PORT_B : PORT_A);
2237 port <= (phy == DPIO_PHY0 ? PORT_C : PORT_A); port++) {
2238 int lane;
2239
2240 for (lane = 0; lane < 4; lane++) {
2241 val = I915_READ(BXT_PORT_TX_DW14_LN(port, lane));
2242 /*
2243 * Note that on CHV this flag is called UPAR, but has
2244 * the same function.
2245 */
2246 val &= ~LATENCY_OPTIM;
2247 if (lane != 1)
2248 val |= LATENCY_OPTIM;
2249
2250 I915_WRITE(BXT_PORT_TX_DW14_LN(port, lane), val);
2251 }
2252 }
2253
2254 /* Program PLL Rcomp code offset */
2255 val = I915_READ(BXT_PORT_CL1CM_DW9(phy));
2256 val &= ~IREF0RC_OFFSET_MASK;
2257 val |= 0xE4 << IREF0RC_OFFSET_SHIFT;
2258 I915_WRITE(BXT_PORT_CL1CM_DW9(phy), val);
2259
2260 val = I915_READ(BXT_PORT_CL1CM_DW10(phy));
2261 val &= ~IREF1RC_OFFSET_MASK;
2262 val |= 0xE4 << IREF1RC_OFFSET_SHIFT;
2263 I915_WRITE(BXT_PORT_CL1CM_DW10(phy), val);
2264
2265 /* Program power gating */
2266 val = I915_READ(BXT_PORT_CL1CM_DW28(phy));
2267 val |= OCL1_POWER_DOWN_EN | DW28_OLDO_DYN_PWR_DOWN_EN |
2268 SUS_CLK_CONFIG;
2269 I915_WRITE(BXT_PORT_CL1CM_DW28(phy), val);
2270
2271 if (phy == DPIO_PHY0) {
2272 val = I915_READ(BXT_PORT_CL2CM_DW6_BC);
2273 val |= DW6_OLDO_DYN_PWR_DOWN_EN;
2274 I915_WRITE(BXT_PORT_CL2CM_DW6_BC, val);
2275 }
2276
2277 val = I915_READ(BXT_PORT_CL1CM_DW30(phy));
2278 val &= ~OCL2_LDOFUSE_PWR_DIS;
2279 /*
2280 * On PHY1 disable power on the second channel, since no port is
2281 * connected there. On PHY0 both channels have a port, so leave it
2282 * enabled.
2283 * TODO: port C is only connected on BXT-P, so on BXT0/1 we should
2284 * power down the second channel on PHY0 as well.
2285 */
2286 if (phy == DPIO_PHY1)
2287 val |= OCL2_LDOFUSE_PWR_DIS;
2288 I915_WRITE(BXT_PORT_CL1CM_DW30(phy), val);
2289
2290 if (phy == DPIO_PHY0) {
2291 uint32_t grc_code;
2292 /*
2293 * PHY0 isn't connected to an RCOMP resistor so copy over
2294 * the corresponding calibrated value from PHY1, and disable
2295 * the automatic calibration on PHY0.
2296 */
2297 if (wait_for(I915_READ(BXT_PORT_REF_DW3(DPIO_PHY1)) & GRC_DONE,
2298 10))
2299 DRM_ERROR("timeout waiting for PHY1 GRC\n");
2300
2301 val = I915_READ(BXT_PORT_REF_DW6(DPIO_PHY1));
2302 val = (val & GRC_CODE_MASK) >> GRC_CODE_SHIFT;
2303 grc_code = val << GRC_CODE_FAST_SHIFT |
2304 val << GRC_CODE_SLOW_SHIFT |
2305 val;
2306 I915_WRITE(BXT_PORT_REF_DW6(DPIO_PHY0), grc_code);
2307
2308 val = I915_READ(BXT_PORT_REF_DW8(DPIO_PHY0));
2309 val |= GRC_DIS | GRC_RDY_OVRD;
2310 I915_WRITE(BXT_PORT_REF_DW8(DPIO_PHY0), val);
2311 }
2312
2313 val = I915_READ(BXT_PHY_CTL_FAMILY(phy));
2314 val |= COMMON_RESET_DIS;
2315 I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val);
2316}
2317
2318void broxton_ddi_phy_init(struct drm_device *dev)
2319{
2320 /* Enable PHY1 first since it provides Rcomp for PHY0 */
2321 broxton_phy_init(dev->dev_private, DPIO_PHY1);
2322 broxton_phy_init(dev->dev_private, DPIO_PHY0);
2323}
2324
2325static void broxton_phy_uninit(struct drm_i915_private *dev_priv,
2326 enum dpio_phy phy)
2327{
2328 uint32_t val;
2329
2330 val = I915_READ(BXT_PHY_CTL_FAMILY(phy));
2331 val &= ~COMMON_RESET_DIS;
2332 I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val);
2333}
2334
2335void broxton_ddi_phy_uninit(struct drm_device *dev)
2336{
2337 struct drm_i915_private *dev_priv = dev->dev_private;
2338
2339 broxton_phy_uninit(dev_priv, DPIO_PHY1);
2340 broxton_phy_uninit(dev_priv, DPIO_PHY0);
2341
2342 /* FIXME: do this in broxton_phy_uninit per phy */
2343 I915_WRITE(BXT_P_CR_GT_DISP_PWRON, 0);
2344}
2345
dfb82408
S		 2346static const char * const bxt_ddi_pll_names[] = {
2347 "PORT PLL A",
2348 "PORT PLL B",
2349 "PORT PLL C",
2350};
2351
2352static void bxt_ddi_pll_enable(struct drm_i915_private *dev_priv,
2353 struct intel_shared_dpll *pll)
2354{
2355 uint32_t temp;
2356 enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */
2357
2358 temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
2359 temp &= ~PORT_PLL_REF_SEL;
2360 /* Non-SSC reference */
2361 I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
2362
2363 /* Disable 10 bit clock */
2364 temp = I915_READ(BXT_PORT_PLL_EBB_4(port));
2365 temp &= ~PORT_PLL_10BIT_CLK_ENABLE;
2366 I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp);
2367
2368 /* Write P1 & P2 */
2369 temp = I915_READ(BXT_PORT_PLL_EBB_0(port));
2370 temp &= ~(PORT_PLL_P1_MASK | PORT_PLL_P2_MASK);
2371 temp |= pll->config.hw_state.ebb0;
2372 I915_WRITE(BXT_PORT_PLL_EBB_0(port), temp);
2373
2374 /* Write M2 integer */
2375 temp = I915_READ(BXT_PORT_PLL(port, 0));
2376 temp &= ~PORT_PLL_M2_MASK;
2377 temp |= pll->config.hw_state.pll0;
2378 I915_WRITE(BXT_PORT_PLL(port, 0), temp);
2379
2380 /* Write N */
2381 temp = I915_READ(BXT_PORT_PLL(port, 1));
2382 temp &= ~PORT_PLL_N_MASK;
2383 temp |= pll->config.hw_state.pll1;
2384 I915_WRITE(BXT_PORT_PLL(port, 1), temp);
2385
2386 /* Write M2 fraction */
2387 temp = I915_READ(BXT_PORT_PLL(port, 2));
2388 temp &= ~PORT_PLL_M2_FRAC_MASK;
2389 temp |= pll->config.hw_state.pll2;
2390 I915_WRITE(BXT_PORT_PLL(port, 2), temp);
2391
2392 /* Write M2 fraction enable */
2393 temp = I915_READ(BXT_PORT_PLL(port, 3));
2394 temp &= ~PORT_PLL_M2_FRAC_ENABLE;
2395 temp |= pll->config.hw_state.pll3;
2396 I915_WRITE(BXT_PORT_PLL(port, 3), temp);
2397
2398 /* Write coeff */
2399 temp = I915_READ(BXT_PORT_PLL(port, 6));
2400 temp &= ~PORT_PLL_PROP_COEFF_MASK;
2401 temp &= ~PORT_PLL_INT_COEFF_MASK;
2402 temp &= ~PORT_PLL_GAIN_CTL_MASK;
2403 temp |= pll->config.hw_state.pll6;
2404 I915_WRITE(BXT_PORT_PLL(port, 6), temp);
2405
2406 /* Write calibration val */
2407 temp = I915_READ(BXT_PORT_PLL(port, 8));
2408 temp &= ~PORT_PLL_TARGET_CNT_MASK;
2409 temp |= pll->config.hw_state.pll8;
2410 I915_WRITE(BXT_PORT_PLL(port, 8), temp);
2411
b6dc71f3
VK		 2412 temp = I915_READ(BXT_PORT_PLL(port, 9));
2413 temp &= ~PORT_PLL_LOCK_THRESHOLD_MASK;
2414 temp |= (5 << 1);
2415 I915_WRITE(BXT_PORT_PLL(port, 9), temp);
2416
2417 temp = I915_READ(BXT_PORT_PLL(port, 10));
2418 temp &= ~PORT_PLL_DCO_AMP_OVR_EN_H;
2419 temp &= ~PORT_PLL_DCO_AMP_MASK;
2420 temp |= pll->config.hw_state.pll10;
2421 I915_WRITE(BXT_PORT_PLL(port, 10), temp);
dfb82408
S		 2422
2423 /* Recalibrate with new settings */
2424 temp = I915_READ(BXT_PORT_PLL_EBB_4(port));
2425 temp |= PORT_PLL_RECALIBRATE;
2426 I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp);
2427 /* Enable 10 bit clock */
2428 temp |= PORT_PLL_10BIT_CLK_ENABLE;
2429 I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp);
2430
2431 /* Enable PLL */
2432 temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
2433 temp |= PORT_PLL_ENABLE;
2434 I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
2435 POSTING_READ(BXT_PORT_PLL_ENABLE(port));
2436
2437 if (wait_for_atomic_us((I915_READ(BXT_PORT_PLL_ENABLE(port)) &
2438 PORT_PLL_LOCK), 200))
2439 DRM_ERROR("PLL %d not locked\n", port);
2440
2441 /*
2442 * While we write to the group register to program all lanes at once we
2443 * can read only lane registers and we pick lanes 0/1 for that.
2444 */
2445 temp = I915_READ(BXT_PORT_PCS_DW12_LN01(port));
2446 temp &= ~LANE_STAGGER_MASK;
2447 temp &= ~LANESTAGGER_STRAP_OVRD;
2448 temp |= pll->config.hw_state.pcsdw12;
2449 I915_WRITE(BXT_PORT_PCS_DW12_GRP(port), temp);
2450}
2451
2452static void bxt_ddi_pll_disable(struct drm_i915_private *dev_priv,
2453 struct intel_shared_dpll *pll)
2454{
2455 enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */
2456 uint32_t temp;
2457
2458 temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
2459 temp &= ~PORT_PLL_ENABLE;
2460 I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
2461 POSTING_READ(BXT_PORT_PLL_ENABLE(port));
2462}
2463
2464static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
2465 struct intel_shared_dpll *pll,
2466 struct intel_dpll_hw_state *hw_state)
2467{
2468 enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */
2469 uint32_t val;
2470
2471 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
2472 return false;
2473
2474 val = I915_READ(BXT_PORT_PLL_ENABLE(port));
2475 if (!(val & PORT_PLL_ENABLE))
2476 return false;
2477
2478 hw_state->ebb0 = I915_READ(BXT_PORT_PLL_EBB_0(port));
2479 hw_state->pll0 = I915_READ(BXT_PORT_PLL(port, 0));
2480 hw_state->pll1 = I915_READ(BXT_PORT_PLL(port, 1));
2481 hw_state->pll2 = I915_READ(BXT_PORT_PLL(port, 2));
2482 hw_state->pll3 = I915_READ(BXT_PORT_PLL(port, 3));
2483 hw_state->pll6 = I915_READ(BXT_PORT_PLL(port, 6));
2484 hw_state->pll8 = I915_READ(BXT_PORT_PLL(port, 8));
b6dc71f3 2485 hw_state->pll10 = I915_READ(BXT_PORT_PLL(port, 10));
dfb82408
S		 2486 /*
2487 * While we write to the group register to program all lanes at once we
2488 * can read only lane registers. We configure all lanes the same way, so
2489 * here just read out lanes 0/1 and output a note if lanes 2/3 differ.
2490 */
2491 hw_state->pcsdw12 = I915_READ(BXT_PORT_PCS_DW12_LN01(port));
2492 if (I915_READ(BXT_PORT_PCS_DW12_LN23(port) != hw_state->pcsdw12))
2493 DRM_DEBUG_DRIVER("lane stagger config different for lane 01 (%08x) and 23 (%08x)\n",
2494 hw_state->pcsdw12,
2495 I915_READ(BXT_PORT_PCS_DW12_LN23(port)));
2496
2497 return true;
2498}
2499
2500static void bxt_shared_dplls_init(struct drm_i915_private *dev_priv)
2501{
2502 int i;
2503
2504 dev_priv->num_shared_dpll = 3;
2505
2506 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
2507 dev_priv->shared_dplls[i].id = i;
2508 dev_priv->shared_dplls[i].name = bxt_ddi_pll_names[i];
2509 dev_priv->shared_dplls[i].disable = bxt_ddi_pll_disable;
2510 dev_priv->shared_dplls[i].enable = bxt_ddi_pll_enable;
2511 dev_priv->shared_dplls[i].get_hw_state =
2512 bxt_ddi_pll_get_hw_state;
2513 }
2514}
2515
143b307c
DL		 2516void intel_ddi_pll_init(struct drm_device *dev)
2517{
2518 struct drm_i915_private *dev_priv = dev->dev_private;
2519 uint32_t val = I915_READ(LCPLL_CTL);
5d96d8af 2520 int cdclk_freq;
143b307c 2521
d1a2dc78
S		 2522 if (IS_SKYLAKE(dev))
2523 skl_shared_dplls_init(dev_priv);
dfb82408
S		 2524 else if (IS_BROXTON(dev))
2525 bxt_shared_dplls_init(dev_priv);
d1a2dc78
S		 2526 else
2527 hsw_shared_dplls_init(dev_priv);
79f689aa 2528
5d96d8af
DL		 2529 cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
2530 DRM_DEBUG_KMS("CDCLK running at %dKHz\n", cdclk_freq);
79f689aa 2531
121643c2 2532 if (IS_SKYLAKE(dev)) {
5d96d8af 2533 dev_priv->skl_boot_cdclk = cdclk_freq;
121643c2
S		 2534 if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE))
2535 DRM_ERROR("LCPLL1 is disabled\n");
5d96d8af
DL		 2536 else
2537 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
f8437dd1
VK		 2538 } else if (IS_BROXTON(dev)) {
2539 broxton_init_cdclk(dev);
5c6706e5 2540 broxton_ddi_phy_init(dev);
121643c2
S		 2541 } else {
2542 /*
2543 * The LCPLL register should be turned on by the BIOS. For now
2544 * let's just check its state and print errors in case
2545 * something is wrong. Don't even try to turn it on.
2546 */
2547
2548 if (val & LCPLL_CD_SOURCE_FCLK)
2549 DRM_ERROR("CDCLK source is not LCPLL\n");
79f689aa 2550
121643c2
S		 2551 if (val & LCPLL_PLL_DISABLE)
2552 DRM_ERROR("LCPLL is disabled\n");
2553 }
79f689aa 2554}
c19b0669
PZ		 2555
2556void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder)
2557{
174edf1f
PZ		 2558 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
2559 struct intel_dp *intel_dp = &intel_dig_port->dp;
c19b0669 2560 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
174edf1f 2561 enum port port = intel_dig_port->port;
c19b0669 2562 uint32_t val;
f3e227df 2563 bool wait = false;
c19b0669
PZ		 2564
2565 if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
2566 val = I915_READ(DDI_BUF_CTL(port));
2567 if (val & DDI_BUF_CTL_ENABLE) {
2568 val &= ~DDI_BUF_CTL_ENABLE;
2569 I915_WRITE(DDI_BUF_CTL(port), val);
2570 wait = true;
2571 }
2572
2573 val = I915_READ(DP_TP_CTL(port));
2574 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
2575 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
2576 I915_WRITE(DP_TP_CTL(port), val);
2577 POSTING_READ(DP_TP_CTL(port));
2578
2579 if (wait)
2580 intel_wait_ddi_buf_idle(dev_priv, port);
2581 }
2582
0e32b39c 2583 val = DP_TP_CTL_ENABLE |
c19b0669 2584 DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
0e32b39c
DA		 2585 if (intel_dp->is_mst)
2586 val |= DP_TP_CTL_MODE_MST;
2587 else {
2588 val |= DP_TP_CTL_MODE_SST;
2589 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2590 val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
2591 }
c19b0669
PZ		 2592 I915_WRITE(DP_TP_CTL(port), val);
2593 POSTING_READ(DP_TP_CTL(port));
2594
2595 intel_dp->DP |= DDI_BUF_CTL_ENABLE;
2596 I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
2597 POSTING_READ(DDI_BUF_CTL(port));
2598
2599 udelay(600);
2600}
00c09d70 2601
1ad960f2
PZ		 2602void intel_ddi_fdi_disable(struct drm_crtc *crtc)
2603{
2604 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
2605 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
2606 uint32_t val;
2607
2608 intel_ddi_post_disable(intel_encoder);
2609
2610 val = I915_READ(_FDI_RXA_CTL);
2611 val &= ~FDI_RX_ENABLE;
2612 I915_WRITE(_FDI_RXA_CTL, val);
2613
2614 val = I915_READ(_FDI_RXA_MISC);
2615 val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
2616 val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
2617 I915_WRITE(_FDI_RXA_MISC, val);
2618
2619 val = I915_READ(_FDI_RXA_CTL);
2620 val &= ~FDI_PCDCLK;
2621 I915_WRITE(_FDI_RXA_CTL, val);
2622
2623 val = I915_READ(_FDI_RXA_CTL);
2624 val &= ~FDI_RX_PLL_ENABLE;
2625 I915_WRITE(_FDI_RXA_CTL, val);
2626}
2627
6801c18c 2628void intel_ddi_get_config(struct intel_encoder *encoder,
5cec258b 2629 struct intel_crtc_state *pipe_config)
045ac3b5
JB		 2630{
2631 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
2632 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
0cb09a97 2633 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
bbd440fb 2634 struct intel_hdmi *intel_hdmi;
045ac3b5
JB		 2635 u32 temp, flags = 0;
2636
2637 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
2638 if (temp & TRANS_DDI_PHSYNC)
2639 flags |= DRM_MODE_FLAG_PHSYNC;
2640 else
2641 flags |= DRM_MODE_FLAG_NHSYNC;
2642 if (temp & TRANS_DDI_PVSYNC)
2643 flags |= DRM_MODE_FLAG_PVSYNC;
2644 else
2645 flags |= DRM_MODE_FLAG_NVSYNC;
2646
2d112de7 2647 pipe_config->base.adjusted_mode.flags |= flags;
42571aef
VS		 2648
2649 switch (temp & TRANS_DDI_BPC_MASK) {
2650 case TRANS_DDI_BPC_6:
2651 pipe_config->pipe_bpp = 18;
2652 break;
2653 case TRANS_DDI_BPC_8:
2654 pipe_config->pipe_bpp = 24;
2655 break;
2656 case TRANS_DDI_BPC_10:
2657 pipe_config->pipe_bpp = 30;
2658 break;
2659 case TRANS_DDI_BPC_12:
2660 pipe_config->pipe_bpp = 36;
2661 break;
2662 default:
2663 break;
2664 }
eb14cb74
VS		 2665
2666 switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
2667 case TRANS_DDI_MODE_SELECT_HDMI:
6897b4b5 2668 pipe_config->has_hdmi_sink = true;
bbd440fb
DV		 2669 intel_hdmi = enc_to_intel_hdmi(&encoder->base);
2670
2671 if (intel_hdmi->infoframe_enabled(&encoder->base))
2672 pipe_config->has_infoframe = true;
cbc572a9 2673 break;
eb14cb74
VS		 2674 case TRANS_DDI_MODE_SELECT_DVI:
2675 case TRANS_DDI_MODE_SELECT_FDI:
2676 break;
2677 case TRANS_DDI_MODE_SELECT_DP_SST:
2678 case TRANS_DDI_MODE_SELECT_DP_MST:
2679 pipe_config->has_dp_encoder = true;
2680 intel_dp_get_m_n(intel_crtc, pipe_config);
2681 break;
2682 default:
2683 break;
2684 }
10214420 2685
f458ebbc 2686 if (intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO)) {
a60551b1 2687 temp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
82910ac6 2688 if (temp & AUDIO_OUTPUT_ENABLE(intel_crtc->pipe))
a60551b1
PZ		 2689 pipe_config->has_audio = true;
2690 }
9ed109a7 2691
10214420
DV		 2692 if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp_bpp &&
2693 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
2694 /*
2695 * This is a big fat ugly hack.
2696 *
2697 * Some machines in UEFI boot mode provide us a VBT that has 18
2698 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2699 * unknown we fail to light up. Yet the same BIOS boots up with
2700 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2701 * max, not what it tells us to use.
2702 *
2703 * Note: This will still be broken if the eDP panel is not lit
2704 * up by the BIOS, and thus we can't get the mode at module
2705 * load.
2706 */
2707 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2708 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
2709 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
2710 }
11578553 2711
22606a18 2712 intel_ddi_clock_get(encoder, pipe_config);
045ac3b5
JB		 2713}
2714
00c09d70
PZ		 2715static void intel_ddi_destroy(struct drm_encoder *encoder)
2716{
2717 /* HDMI has nothing special to destroy, so we can go with this. */
2718 intel_dp_encoder_destroy(encoder);
2719}
2720
5bfe2ac0 2721static bool intel_ddi_compute_config(struct intel_encoder *encoder,
5cec258b 2722 struct intel_crtc_state *pipe_config)
00c09d70 2723{
5bfe2ac0 2724 int type = encoder->type;
eccb140b 2725 int port = intel_ddi_get_encoder_port(encoder);
00c09d70 2726
5bfe2ac0 2727 WARN(type == INTEL_OUTPUT_UNKNOWN, "compute_config() on unknown output!\n");
00c09d70 2728
eccb140b
DV		 2729 if (port == PORT_A)
2730 pipe_config->cpu_transcoder = TRANSCODER_EDP;
2731
00c09d70 2732 if (type == INTEL_OUTPUT_HDMI)
5bfe2ac0 2733 return intel_hdmi_compute_config(encoder, pipe_config);
00c09d70 2734 else
5bfe2ac0 2735 return intel_dp_compute_config(encoder, pipe_config);
00c09d70
PZ		 2736}
2737
2738static const struct drm_encoder_funcs intel_ddi_funcs = {
2739 .destroy = intel_ddi_destroy,
2740};
2741
4a28ae58
PZ		 2742static struct intel_connector *
2743intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port)
2744{
2745 struct intel_connector *connector;
2746 enum port port = intel_dig_port->port;
2747
9bdbd0b9 2748 connector = intel_connector_alloc();
4a28ae58
PZ		 2749 if (!connector)
2750 return NULL;
2751
2752 intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
2753 if (!intel_dp_init_connector(intel_dig_port, connector)) {
2754 kfree(connector);
2755 return NULL;
2756 }
2757
2758 return connector;
2759}
2760
2761static struct intel_connector *
2762intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port)
2763{
2764 struct intel_connector *connector;
2765 enum port port = intel_dig_port->port;
2766
9bdbd0b9 2767 connector = intel_connector_alloc();
4a28ae58
PZ		 2768 if (!connector)
2769 return NULL;
2770
2771 intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
2772 intel_hdmi_init_connector(intel_dig_port, connector);
2773
2774 return connector;
2775}
2776
00c09d70
PZ		 2777void intel_ddi_init(struct drm_device *dev, enum port port)
2778{
876a8cdf 2779 struct drm_i915_private *dev_priv = dev->dev_private;
00c09d70
PZ		 2780 struct intel_digital_port *intel_dig_port;
2781 struct intel_encoder *intel_encoder;
2782 struct drm_encoder *encoder;
311a2094
PZ		 2783 bool init_hdmi, init_dp;
2784
2785 init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi ||
2786 dev_priv->vbt.ddi_port_info[port].supports_hdmi);
2787 init_dp = dev_priv->vbt.ddi_port_info[port].supports_dp;
2788 if (!init_dp && !init_hdmi) {
f68d697e 2789 DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, assuming it is\n",
311a2094
PZ		 2790 port_name(port));
2791 init_hdmi = true;
2792 init_dp = true;
2793 }
00c09d70 2794
b14c5679 2795 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
00c09d70
PZ		 2796 if (!intel_dig_port)
2797 return;
2798
00c09d70
PZ		 2799 intel_encoder = &intel_dig_port->base;
2800 encoder = &intel_encoder->base;
2801
2802 drm_encoder_init(dev, encoder, &intel_ddi_funcs,
2803 DRM_MODE_ENCODER_TMDS);
00c09d70 2804
5bfe2ac0 2805 intel_encoder->compute_config = intel_ddi_compute_config;
00c09d70
PZ		 2806 intel_encoder->enable = intel_enable_ddi;
2807 intel_encoder->pre_enable = intel_ddi_pre_enable;
2808 intel_encoder->disable = intel_disable_ddi;
2809 intel_encoder->post_disable = intel_ddi_post_disable;
2810 intel_encoder->get_hw_state = intel_ddi_get_hw_state;
045ac3b5 2811 intel_encoder->get_config = intel_ddi_get_config;
00c09d70
PZ		 2812
2813 intel_dig_port->port = port;
bcf53de4
SM		 2814 intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
2815 (DDI_BUF_PORT_REVERSAL |
2816 DDI_A_4_LANES);
00c09d70
PZ		 2817
2818 intel_encoder->type = INTEL_OUTPUT_UNKNOWN;
f68d697e 2819 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
bc079e8b 2820 intel_encoder->cloneable = 0;
00c09d70 2821
f68d697e
CW		 2822 if (init_dp) {
2823 if (!intel_ddi_init_dp_connector(intel_dig_port))
2824 goto err;
13cf5504 2825
f68d697e 2826 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
5fcece80 2827 dev_priv->hotplug.irq_port[port] = intel_dig_port;
f68d697e 2828 }
21a8e6a4 2829
311a2094
PZ		 2830 /* In theory we don't need the encoder->type check, but leave it just in
2831 * case we have some really bad VBTs... */
f68d697e
CW		 2832 if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi) {
2833 if (!intel_ddi_init_hdmi_connector(intel_dig_port))
2834 goto err;
21a8e6a4 2835 }
f68d697e
CW		 2836
2837 return;
2838
2839err:
2840 drm_encoder_cleanup(encoder);
2841 kfree(intel_dig_port);
00c09d70 2842}
Linux kernel - Deliverables
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