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drm/i915: HSW FBC WaFbcDisableDpfcClockGating
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_ddi.c
CommitLineData
45244b87
ED		 1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
28#include "i915_drv.h"
29#include "intel_drv.h"
30
31/* HDMI/DVI modes ignore everything but the last 2 items. So we share
32 * them for both DP and FDI transports, allowing those ports to
33 * automatically adapt to HDMI connections as well
34 */
35static const u32 hsw_ddi_translations_dp[] = {
36 0x00FFFFFF, 0x0006000E, /* DP parameters */
37 0x00D75FFF, 0x0005000A,
38 0x00C30FFF, 0x00040006,
39 0x80AAAFFF, 0x000B0000,
40 0x00FFFFFF, 0x0005000A,
41 0x00D75FFF, 0x000C0004,
42 0x80C30FFF, 0x000B0000,
43 0x00FFFFFF, 0x00040006,
44 0x80D75FFF, 0x000B0000,
45 0x00FFFFFF, 0x00040006 /* HDMI parameters */
46};
47
48static const u32 hsw_ddi_translations_fdi[] = {
49 0x00FFFFFF, 0x0007000E, /* FDI parameters */
50 0x00D75FFF, 0x000F000A,
51 0x00C30FFF, 0x00060006,
52 0x00AAAFFF, 0x001E0000,
53 0x00FFFFFF, 0x000F000A,
54 0x00D75FFF, 0x00160004,
55 0x00C30FFF, 0x001E0000,
56 0x00FFFFFF, 0x00060006,
57 0x00D75FFF, 0x001E0000,
58 0x00FFFFFF, 0x00040006 /* HDMI parameters */
59};
60
fc914639
PZ		 61static enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder)
62{
0bdee30e 63 struct drm_encoder *encoder = &intel_encoder->base;
fc914639
PZ		 64 int type = intel_encoder->type;
65
174edf1f 66 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP ||
00c09d70 67 type == INTEL_OUTPUT_HDMI || type == INTEL_OUTPUT_UNKNOWN) {
174edf1f
PZ		 68 struct intel_digital_port *intel_dig_port =
69 enc_to_dig_port(encoder);
70 return intel_dig_port->port;
0bdee30e 71
fc914639
PZ		 72 } else if (type == INTEL_OUTPUT_ANALOG) {
73 return PORT_E;
0bdee30e 74
fc914639
PZ		 75 } else {
76 DRM_ERROR("Invalid DDI encoder type %d\n", type);
77 BUG();
78 }
79}
80
45244b87
ED		 81/* On Haswell, DDI port buffers must be programmed with correct values
82 * in advance. The buffer values are different for FDI and DP modes,
83 * but the HDMI/DVI fields are shared among those. So we program the DDI
84 * in either FDI or DP modes only, as HDMI connections will work with both
85 * of those
86 */
c1f63f9d
PZ		 87static void intel_prepare_ddi_buffers(struct drm_device *dev, enum port port,
88 bool use_fdi_mode)
45244b87
ED		 89{
90 struct drm_i915_private *dev_priv = dev->dev_private;
91 u32 reg;
92 int i;
93 const u32 *ddi_translations = ((use_fdi_mode) ?
94 hsw_ddi_translations_fdi :
95 hsw_ddi_translations_dp);
96
97 DRM_DEBUG_DRIVER("Initializing DDI buffers for port %c in %s mode\n",
98 port_name(port),
99 use_fdi_mode ? "FDI" : "DP");
100
101 WARN((use_fdi_mode && (port != PORT_E)),
102 "Programming port %c in FDI mode, this probably will not work.\n",
103 port_name(port));
104
105 for (i=0, reg=DDI_BUF_TRANS(port); i < ARRAY_SIZE(hsw_ddi_translations_fdi); i++) {
106 I915_WRITE(reg, ddi_translations[i]);
107 reg += 4;
108 }
109}
110
111/* Program DDI buffers translations for DP. By default, program ports A-D in DP
112 * mode and port E for FDI.
113 */
114void intel_prepare_ddi(struct drm_device *dev)
115{
116 int port;
117
0d536cb4
PZ		 118 if (!HAS_DDI(dev))
119 return;
45244b87 120
0d536cb4
PZ		 121 for (port = PORT_A; port < PORT_E; port++)
122 intel_prepare_ddi_buffers(dev, port, false);
123
124 /* DDI E is the suggested one to work in FDI mode, so program is as such
125 * by default. It will have to be re-programmed in case a digital DP
126 * output will be detected on it
127 */
128 intel_prepare_ddi_buffers(dev, PORT_E, true);
45244b87 129}
c82e4d26
ED		 130
131static const long hsw_ddi_buf_ctl_values[] = {
132 DDI_BUF_EMP_400MV_0DB_HSW,
133 DDI_BUF_EMP_400MV_3_5DB_HSW,
134 DDI_BUF_EMP_400MV_6DB_HSW,
135 DDI_BUF_EMP_400MV_9_5DB_HSW,
136 DDI_BUF_EMP_600MV_0DB_HSW,
137 DDI_BUF_EMP_600MV_3_5DB_HSW,
138 DDI_BUF_EMP_600MV_6DB_HSW,
139 DDI_BUF_EMP_800MV_0DB_HSW,
140 DDI_BUF_EMP_800MV_3_5DB_HSW
141};
142
248138b5
PZ		 143static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
144 enum port port)
145{
146 uint32_t reg = DDI_BUF_CTL(port);
147 int i;
148
149 for (i = 0; i < 8; i++) {
150 udelay(1);
151 if (I915_READ(reg) & DDI_BUF_IS_IDLE)
152 return;
153 }
154 DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port));
155}
c82e4d26
ED		 156
157/* Starting with Haswell, different DDI ports can work in FDI mode for
158 * connection to the PCH-located connectors. For this, it is necessary to train
159 * both the DDI port and PCH receiver for the desired DDI buffer settings.
160 *
161 * The recommended port to work in FDI mode is DDI E, which we use here. Also,
162 * please note that when FDI mode is active on DDI E, it shares 2 lines with
163 * DDI A (which is used for eDP)
164 */
165
166void hsw_fdi_link_train(struct drm_crtc *crtc)
167{
168 struct drm_device *dev = crtc->dev;
169 struct drm_i915_private *dev_priv = dev->dev_private;
170 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
04945641 171 u32 temp, i, rx_ctl_val;
c82e4d26 172
04945641
PZ		 173 /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
174 * mode set "sequence for CRT port" document:
175 * - TP1 to TP2 time with the default value
176 * - FDI delay to 90h
8693a824
DL		 177 *
178 * WaFDIAutoLinkSetTimingOverrride:hsw
04945641
PZ		 179 */
180 I915_WRITE(_FDI_RXA_MISC, FDI_RX_PWRDN_LANE1_VAL(2) |
181 FDI_RX_PWRDN_LANE0_VAL(2) |
182 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
183
184 /* Enable the PCH Receiver FDI PLL */
3e68320e 185 rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
33d29b14 186 FDI_RX_PLL_ENABLE |
627eb5a3 187 FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
04945641
PZ		 188 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
189 POSTING_READ(_FDI_RXA_CTL);
190 udelay(220);
191
192 /* Switch from Rawclk to PCDclk */
193 rx_ctl_val |= FDI_PCDCLK;
194 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
195
196 /* Configure Port Clock Select */
197 I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->ddi_pll_sel);
198
199 /* Start the training iterating through available voltages and emphasis,
200 * testing each value twice. */
201 for (i = 0; i < ARRAY_SIZE(hsw_ddi_buf_ctl_values) * 2; i++) {
c82e4d26
ED		 202 /* Configure DP_TP_CTL with auto-training */
203 I915_WRITE(DP_TP_CTL(PORT_E),
204 DP_TP_CTL_FDI_AUTOTRAIN |
205 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
206 DP_TP_CTL_LINK_TRAIN_PAT1 |
207 DP_TP_CTL_ENABLE);
208
876a8cdf
DL		 209 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
210 * DDI E does not support port reversal, the functionality is
211 * achieved on the PCH side in FDI_RX_CTL, so no need to set the
212 * port reversal bit */
c82e4d26 213 I915_WRITE(DDI_BUF_CTL(PORT_E),
04945641 214 DDI_BUF_CTL_ENABLE |
33d29b14 215 ((intel_crtc->config.fdi_lanes - 1) << 1) |
04945641
PZ		 216 hsw_ddi_buf_ctl_values[i / 2]);
217 POSTING_READ(DDI_BUF_CTL(PORT_E));
c82e4d26
ED		 218
219 udelay(600);
220
04945641
PZ		 221 /* Program PCH FDI Receiver TU */
222 I915_WRITE(_FDI_RXA_TUSIZE1, TU_SIZE(64));
223
224 /* Enable PCH FDI Receiver with auto-training */
225 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
226 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
227 POSTING_READ(_FDI_RXA_CTL);
228
229 /* Wait for FDI receiver lane calibration */
230 udelay(30);
231
232 /* Unset FDI_RX_MISC pwrdn lanes */
233 temp = I915_READ(_FDI_RXA_MISC);
234 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
235 I915_WRITE(_FDI_RXA_MISC, temp);
236 POSTING_READ(_FDI_RXA_MISC);
237
238 /* Wait for FDI auto training time */
239 udelay(5);
c82e4d26
ED		 240
241 temp = I915_READ(DP_TP_STATUS(PORT_E));
242 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
04945641 243 DRM_DEBUG_KMS("FDI link training done on step %d\n", i);
c82e4d26
ED		 244
245 /* Enable normal pixel sending for FDI */
246 I915_WRITE(DP_TP_CTL(PORT_E),
04945641
PZ		 247 DP_TP_CTL_FDI_AUTOTRAIN |
248 DP_TP_CTL_LINK_TRAIN_NORMAL |
249 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
250 DP_TP_CTL_ENABLE);
c82e4d26 251
04945641 252 return;
c82e4d26 253 }
04945641 254
248138b5
PZ		 255 temp = I915_READ(DDI_BUF_CTL(PORT_E));
256 temp &= ~DDI_BUF_CTL_ENABLE;
257 I915_WRITE(DDI_BUF_CTL(PORT_E), temp);
258 POSTING_READ(DDI_BUF_CTL(PORT_E));
259
04945641 260 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
248138b5
PZ		 261 temp = I915_READ(DP_TP_CTL(PORT_E));
262 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
263 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
264 I915_WRITE(DP_TP_CTL(PORT_E), temp);
265 POSTING_READ(DP_TP_CTL(PORT_E));
266
267 intel_wait_ddi_buf_idle(dev_priv, PORT_E);
04945641
PZ		 268
269 rx_ctl_val &= ~FDI_RX_ENABLE;
270 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
248138b5 271 POSTING_READ(_FDI_RXA_CTL);
04945641
PZ		 272
273 /* Reset FDI_RX_MISC pwrdn lanes */
274 temp = I915_READ(_FDI_RXA_MISC);
275 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
276 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
277 I915_WRITE(_FDI_RXA_MISC, temp);
248138b5 278 POSTING_READ(_FDI_RXA_MISC);
c82e4d26
ED		 279 }
280
04945641 281 DRM_ERROR("FDI link training failed!\n");
c82e4d26 282}
0e72a5b5 283
12a13a33
ED		 284/* WRPLL clock dividers */
285struct wrpll_tmds_clock {
286 u32 clock;
287 u16 p; /* Post divider */
288 u16 n2; /* Feedback divider */
289 u16 r2; /* Reference divider */
290};
291
126e9be8
PZ		 292/* Table of matching values for WRPLL clocks programming for each frequency.
293 * The code assumes this table is sorted. */
12a13a33
ED		 294static const struct wrpll_tmds_clock wrpll_tmds_clock_table[] = {
295 {19750, 38, 25, 18},
296 {20000, 48, 32, 18},
297 {21000, 36, 21, 15},
298 {21912, 42, 29, 17},
299 {22000, 36, 22, 15},
300 {23000, 36, 23, 15},
301 {23500, 40, 40, 23},
302 {23750, 26, 16, 14},
12a13a33
ED		 303 {24000, 36, 24, 15},
304 {25000, 36, 25, 15},
305 {25175, 26, 40, 33},
306 {25200, 30, 21, 15},
307 {26000, 36, 26, 15},
308 {27000, 30, 21, 14},
309 {27027, 18, 100, 111},
310 {27500, 30, 29, 19},
311 {28000, 34, 30, 17},
312 {28320, 26, 30, 22},
313 {28322, 32, 42, 25},
314 {28750, 24, 23, 18},
315 {29000, 30, 29, 18},
316 {29750, 32, 30, 17},
317 {30000, 30, 25, 15},
318 {30750, 30, 41, 24},
319 {31000, 30, 31, 18},
320 {31500, 30, 28, 16},
321 {32000, 30, 32, 18},
322 {32500, 28, 32, 19},
323 {33000, 24, 22, 15},
324 {34000, 28, 30, 17},
325 {35000, 26, 32, 19},
326 {35500, 24, 30, 19},
327 {36000, 26, 26, 15},
328 {36750, 26, 46, 26},
329 {37000, 24, 23, 14},
330 {37762, 22, 40, 26},
331 {37800, 20, 21, 15},
332 {38000, 24, 27, 16},
333 {38250, 24, 34, 20},
334 {39000, 24, 26, 15},
335 {40000, 24, 32, 18},
336 {40500, 20, 21, 14},
337 {40541, 22, 147, 89},
338 {40750, 18, 19, 14},
339 {41000, 16, 17, 14},
340 {41500, 22, 44, 26},
341 {41540, 22, 44, 26},
342 {42000, 18, 21, 15},
343 {42500, 22, 45, 26},
344 {43000, 20, 43, 27},
345 {43163, 20, 24, 15},
346 {44000, 18, 22, 15},
347 {44900, 20, 108, 65},
348 {45000, 20, 25, 15},
349 {45250, 20, 52, 31},
350 {46000, 18, 23, 15},
351 {46750, 20, 45, 26},
352 {47000, 20, 40, 23},
353 {48000, 18, 24, 15},
354 {49000, 18, 49, 30},
355 {49500, 16, 22, 15},
356 {50000, 18, 25, 15},
357 {50500, 18, 32, 19},
358 {51000, 18, 34, 20},
359 {52000, 18, 26, 15},
360 {52406, 14, 34, 25},
361 {53000, 16, 22, 14},
362 {54000, 16, 24, 15},
363 {54054, 16, 173, 108},
364 {54500, 14, 24, 17},
365 {55000, 12, 22, 18},
366 {56000, 14, 45, 31},
367 {56250, 16, 25, 15},
368 {56750, 14, 25, 17},
369 {57000, 16, 27, 16},
370 {58000, 16, 43, 25},
371 {58250, 16, 38, 22},
372 {58750, 16, 40, 23},
373 {59000, 14, 26, 17},
374 {59341, 14, 40, 26},
375 {59400, 16, 44, 25},
376 {60000, 16, 32, 18},
377 {60500, 12, 39, 29},
378 {61000, 14, 49, 31},
379 {62000, 14, 37, 23},
380 {62250, 14, 42, 26},
381 {63000, 12, 21, 15},
382 {63500, 14, 28, 17},
383 {64000, 12, 27, 19},
384 {65000, 14, 32, 19},
385 {65250, 12, 29, 20},
386 {65500, 12, 32, 22},
387 {66000, 12, 22, 15},
388 {66667, 14, 38, 22},
389 {66750, 10, 21, 17},
390 {67000, 14, 33, 19},
391 {67750, 14, 58, 33},
392 {68000, 14, 30, 17},
393 {68179, 14, 46, 26},
394 {68250, 14, 46, 26},
395 {69000, 12, 23, 15},
396 {70000, 12, 28, 18},
397 {71000, 12, 30, 19},
398 {72000, 12, 24, 15},
399 {73000, 10, 23, 17},
400 {74000, 12, 23, 14},
401 {74176, 8, 100, 91},
402 {74250, 10, 22, 16},
403 {74481, 12, 43, 26},
404 {74500, 10, 29, 21},
405 {75000, 12, 25, 15},
406 {75250, 10, 39, 28},
407 {76000, 12, 27, 16},
408 {77000, 12, 53, 31},
409 {78000, 12, 26, 15},
410 {78750, 12, 28, 16},
411 {79000, 10, 38, 26},
412 {79500, 10, 28, 19},
413 {80000, 12, 32, 18},
414 {81000, 10, 21, 14},
415 {81081, 6, 100, 111},
416 {81624, 8, 29, 24},
417 {82000, 8, 17, 14},
418 {83000, 10, 40, 26},
419 {83950, 10, 28, 18},
420 {84000, 10, 28, 18},
421 {84750, 6, 16, 17},
422 {85000, 6, 17, 18},
423 {85250, 10, 30, 19},
424 {85750, 10, 27, 17},
425 {86000, 10, 43, 27},
426 {87000, 10, 29, 18},
427 {88000, 10, 44, 27},
428 {88500, 10, 41, 25},
429 {89000, 10, 28, 17},
430 {89012, 6, 90, 91},
431 {89100, 10, 33, 20},
432 {90000, 10, 25, 15},
433 {91000, 10, 32, 19},
434 {92000, 10, 46, 27},
435 {93000, 10, 31, 18},
436 {94000, 10, 40, 23},
437 {94500, 10, 28, 16},
438 {95000, 10, 44, 25},
439 {95654, 10, 39, 22},
440 {95750, 10, 39, 22},
441 {96000, 10, 32, 18},
442 {97000, 8, 23, 16},
443 {97750, 8, 42, 29},
444 {98000, 8, 45, 31},
445 {99000, 8, 22, 15},
446 {99750, 8, 34, 23},
447 {100000, 6, 20, 18},
448 {100500, 6, 19, 17},
449 {101000, 6, 37, 33},
450 {101250, 8, 21, 14},
451 {102000, 6, 17, 15},
452 {102250, 6, 25, 22},
453 {103000, 8, 29, 19},
454 {104000, 8, 37, 24},
455 {105000, 8, 28, 18},
456 {106000, 8, 22, 14},
457 {107000, 8, 46, 29},
458 {107214, 8, 27, 17},
459 {108000, 8, 24, 15},
460 {108108, 8, 173, 108},
461 {109000, 6, 23, 19},
12a13a33
ED		 462 {110000, 6, 22, 18},
463 {110013, 6, 22, 18},
464 {110250, 8, 49, 30},
465 {110500, 8, 36, 22},
466 {111000, 8, 23, 14},
467 {111264, 8, 150, 91},
468 {111375, 8, 33, 20},
469 {112000, 8, 63, 38},
470 {112500, 8, 25, 15},
471 {113100, 8, 57, 34},
472 {113309, 8, 42, 25},
473 {114000, 8, 27, 16},
474 {115000, 6, 23, 18},
475 {116000, 8, 43, 25},
476 {117000, 8, 26, 15},
477 {117500, 8, 40, 23},
478 {118000, 6, 38, 29},
479 {119000, 8, 30, 17},
480 {119500, 8, 46, 26},
481 {119651, 8, 39, 22},
482 {120000, 8, 32, 18},
483 {121000, 6, 39, 29},
484 {121250, 6, 31, 23},
485 {121750, 6, 23, 17},
486 {122000, 6, 42, 31},
487 {122614, 6, 30, 22},
488 {123000, 6, 41, 30},
489 {123379, 6, 37, 27},
490 {124000, 6, 51, 37},
491 {125000, 6, 25, 18},
492 {125250, 4, 13, 14},
493 {125750, 4, 27, 29},
494 {126000, 6, 21, 15},
495 {127000, 6, 24, 17},
496 {127250, 6, 41, 29},
497 {128000, 6, 27, 19},
498 {129000, 6, 43, 30},
499 {129859, 4, 25, 26},
500 {130000, 6, 26, 18},
501 {130250, 6, 42, 29},
502 {131000, 6, 32, 22},
503 {131500, 6, 38, 26},
504 {131850, 6, 41, 28},
505 {132000, 6, 22, 15},
506 {132750, 6, 28, 19},
507 {133000, 6, 34, 23},
508 {133330, 6, 37, 25},
509 {134000, 6, 61, 41},
510 {135000, 6, 21, 14},
511 {135250, 6, 167, 111},
512 {136000, 6, 62, 41},
513 {137000, 6, 35, 23},
514 {138000, 6, 23, 15},
515 {138500, 6, 40, 26},
516 {138750, 6, 37, 24},
517 {139000, 6, 34, 22},
518 {139050, 6, 34, 22},
519 {139054, 6, 34, 22},
520 {140000, 6, 28, 18},
521 {141000, 6, 36, 23},
522 {141500, 6, 22, 14},
523 {142000, 6, 30, 19},
524 {143000, 6, 27, 17},
525 {143472, 4, 17, 16},
526 {144000, 6, 24, 15},
527 {145000, 6, 29, 18},
528 {146000, 6, 47, 29},
529 {146250, 6, 26, 16},
530 {147000, 6, 49, 30},
531 {147891, 6, 23, 14},
532 {148000, 6, 23, 14},
533 {148250, 6, 28, 17},
534 {148352, 4, 100, 91},
535 {148500, 6, 33, 20},
536 {149000, 6, 48, 29},
537 {150000, 6, 25, 15},
538 {151000, 4, 19, 17},
539 {152000, 6, 27, 16},
540 {152280, 6, 44, 26},
541 {153000, 6, 34, 20},
542 {154000, 6, 53, 31},
543 {155000, 6, 31, 18},
544 {155250, 6, 50, 29},
545 {155750, 6, 45, 26},
546 {156000, 6, 26, 15},
547 {157000, 6, 61, 35},
548 {157500, 6, 28, 16},
549 {158000, 6, 65, 37},
550 {158250, 6, 44, 25},
551 {159000, 6, 53, 30},
552 {159500, 6, 39, 22},
553 {160000, 6, 32, 18},
554 {161000, 4, 31, 26},
555 {162000, 4, 18, 15},
556 {162162, 4, 131, 109},
557 {162500, 4, 53, 44},
558 {163000, 4, 29, 24},
559 {164000, 4, 17, 14},
560 {165000, 4, 22, 18},
561 {166000, 4, 32, 26},
562 {167000, 4, 26, 21},
563 {168000, 4, 46, 37},
564 {169000, 4, 104, 83},
565 {169128, 4, 64, 51},
566 {169500, 4, 39, 31},
567 {170000, 4, 34, 27},
568 {171000, 4, 19, 15},
569 {172000, 4, 51, 40},
570 {172750, 4, 32, 25},
571 {172800, 4, 32, 25},
572 {173000, 4, 41, 32},
573 {174000, 4, 49, 38},
574 {174787, 4, 22, 17},
575 {175000, 4, 35, 27},
576 {176000, 4, 30, 23},
577 {177000, 4, 38, 29},
578 {178000, 4, 29, 22},
579 {178500, 4, 37, 28},
580 {179000, 4, 53, 40},
581 {179500, 4, 73, 55},
582 {180000, 4, 20, 15},
583 {181000, 4, 55, 41},
584 {182000, 4, 31, 23},
585 {183000, 4, 42, 31},
586 {184000, 4, 30, 22},
587 {184750, 4, 26, 19},
588 {185000, 4, 37, 27},
589 {186000, 4, 51, 37},
590 {187000, 4, 36, 26},
591 {188000, 4, 32, 23},
592 {189000, 4, 21, 15},
593 {190000, 4, 38, 27},
594 {190960, 4, 41, 29},
595 {191000, 4, 41, 29},
596 {192000, 4, 27, 19},
597 {192250, 4, 37, 26},
598 {193000, 4, 20, 14},
599 {193250, 4, 53, 37},
600 {194000, 4, 23, 16},
601 {194208, 4, 23, 16},
602 {195000, 4, 26, 18},
603 {196000, 4, 45, 31},
604 {197000, 4, 35, 24},
605 {197750, 4, 41, 28},
606 {198000, 4, 22, 15},
607 {198500, 4, 25, 17},
608 {199000, 4, 28, 19},
609 {200000, 4, 37, 25},
610 {201000, 4, 61, 41},
611 {202000, 4, 112, 75},
612 {202500, 4, 21, 14},
613 {203000, 4, 146, 97},
614 {204000, 4, 62, 41},
615 {204750, 4, 44, 29},
616 {205000, 4, 38, 25},
617 {206000, 4, 29, 19},
618 {207000, 4, 23, 15},
619 {207500, 4, 40, 26},
620 {208000, 4, 37, 24},
621 {208900, 4, 48, 31},
622 {209000, 4, 48, 31},
623 {209250, 4, 31, 20},
624 {210000, 4, 28, 18},
625 {211000, 4, 25, 16},
626 {212000, 4, 22, 14},
627 {213000, 4, 30, 19},
628 {213750, 4, 38, 24},
629 {214000, 4, 46, 29},
630 {214750, 4, 35, 22},
631 {215000, 4, 43, 27},
632 {216000, 4, 24, 15},
633 {217000, 4, 37, 23},
634 {218000, 4, 42, 26},
635 {218250, 4, 42, 26},
636 {218750, 4, 34, 21},
637 {219000, 4, 47, 29},
12a13a33
ED		 638 {220000, 4, 44, 27},
639 {220640, 4, 49, 30},
640 {220750, 4, 36, 22},
641 {221000, 4, 36, 22},
642 {222000, 4, 23, 14},
643 {222525, 4, 28, 17},
644 {222750, 4, 33, 20},
645 {227000, 4, 37, 22},
646 {230250, 4, 29, 17},
647 {233500, 4, 38, 22},
648 {235000, 4, 40, 23},
649 {238000, 4, 30, 17},
650 {241500, 2, 17, 19},
651 {245250, 2, 20, 22},
652 {247750, 2, 22, 24},
653 {253250, 2, 15, 16},
654 {256250, 2, 18, 19},
655 {262500, 2, 31, 32},
656 {267250, 2, 66, 67},
657 {268500, 2, 94, 95},
658 {270000, 2, 14, 14},
659 {272500, 2, 77, 76},
660 {273750, 2, 57, 56},
661 {280750, 2, 24, 23},
662 {281250, 2, 23, 22},
663 {286000, 2, 17, 16},
664 {291750, 2, 26, 24},
665 {296703, 2, 56, 51},
666 {297000, 2, 22, 20},
667 {298000, 2, 21, 19},
668};
72662e10 669
00c09d70
PZ		 670static void intel_ddi_mode_set(struct drm_encoder *encoder,
671 struct drm_display_mode *mode,
672 struct drm_display_mode *adjusted_mode)
72662e10 673{
72662e10
ED		 674 struct drm_crtc *crtc = encoder->crtc;
675 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
247d89f6
PZ		 676 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
677 int port = intel_ddi_get_encoder_port(intel_encoder);
72662e10 678 int pipe = intel_crtc->pipe;
247d89f6 679 int type = intel_encoder->type;
72662e10 680
bf98a726 681 DRM_DEBUG_KMS("Preparing DDI mode on port %c, pipe %c\n",
247d89f6 682 port_name(port), pipe_name(pipe));
72662e10 683
7b9f35a6 684 intel_crtc->eld_vld = false;
247d89f6
PZ		 685 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
686 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
876a8cdf
DL		 687 struct intel_digital_port *intel_dig_port =
688 enc_to_dig_port(encoder);
4f07854d 689
876a8cdf
DL		 690 intel_dp->DP = intel_dig_port->port_reversal |
691 DDI_BUF_CTL_ENABLE | DDI_BUF_EMP_400MV_0DB_HSW;
17aa6be9 692 intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
247d89f6 693
8fed6193
TI		 694 if (intel_dp->has_audio) {
695 DRM_DEBUG_DRIVER("DP audio on pipe %c on DDI\n",
696 pipe_name(intel_crtc->pipe));
697
698 /* write eld */
699 DRM_DEBUG_DRIVER("DP audio: write eld information\n");
700 intel_write_eld(encoder, adjusted_mode);
701 }
702
247d89f6
PZ		 703 intel_dp_init_link_config(intel_dp);
704
705 } else if (type == INTEL_OUTPUT_HDMI) {
706 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
707
708 if (intel_hdmi->has_audio) {
709 /* Proper support for digital audio needs a new logic
710 * and a new set of registers, so we leave it for future
711 * patch bombing.
712 */
713 DRM_DEBUG_DRIVER("HDMI audio on pipe %c on DDI\n",
714 pipe_name(intel_crtc->pipe));
715
716 /* write eld */
717 DRM_DEBUG_DRIVER("HDMI audio: write eld information\n");
718 intel_write_eld(encoder, adjusted_mode);
719 }
72662e10 720
247d89f6
PZ		 721 intel_hdmi->set_infoframes(encoder, adjusted_mode);
722 }
8d9ddbcb
PZ		 723}
724
725static struct intel_encoder *
726intel_ddi_get_crtc_encoder(struct drm_crtc *crtc)
727{
728 struct drm_device *dev = crtc->dev;
729 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
730 struct intel_encoder *intel_encoder, *ret = NULL;
731 int num_encoders = 0;
732
733 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
734 ret = intel_encoder;
735 num_encoders++;
736 }
737
738 if (num_encoders != 1)
84f44ce7
VS		 739 WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders,
740 pipe_name(intel_crtc->pipe));
8d9ddbcb
PZ		 741
742 BUG_ON(ret == NULL);
743 return ret;
744}
745
6441ab5f
PZ		 746void intel_ddi_put_crtc_pll(struct drm_crtc *crtc)
747{
748 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
749 struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
750 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
751 uint32_t val;
752
753 switch (intel_crtc->ddi_pll_sel) {
754 case PORT_CLK_SEL_SPLL:
755 plls->spll_refcount--;
756 if (plls->spll_refcount == 0) {
757 DRM_DEBUG_KMS("Disabling SPLL\n");
758 val = I915_READ(SPLL_CTL);
759 WARN_ON(!(val & SPLL_PLL_ENABLE));
760 I915_WRITE(SPLL_CTL, val & ~SPLL_PLL_ENABLE);
761 POSTING_READ(SPLL_CTL);
762 }
763 break;
764 case PORT_CLK_SEL_WRPLL1:
765 plls->wrpll1_refcount--;
766 if (plls->wrpll1_refcount == 0) {
767 DRM_DEBUG_KMS("Disabling WRPLL 1\n");
768 val = I915_READ(WRPLL_CTL1);
769 WARN_ON(!(val & WRPLL_PLL_ENABLE));
770 I915_WRITE(WRPLL_CTL1, val & ~WRPLL_PLL_ENABLE);
771 POSTING_READ(WRPLL_CTL1);
772 }
773 break;
774 case PORT_CLK_SEL_WRPLL2:
775 plls->wrpll2_refcount--;
776 if (plls->wrpll2_refcount == 0) {
777 DRM_DEBUG_KMS("Disabling WRPLL 2\n");
778 val = I915_READ(WRPLL_CTL2);
779 WARN_ON(!(val & WRPLL_PLL_ENABLE));
780 I915_WRITE(WRPLL_CTL2, val & ~WRPLL_PLL_ENABLE);
781 POSTING_READ(WRPLL_CTL2);
782 }
783 break;
784 }
785
786 WARN(plls->spll_refcount < 0, "Invalid SPLL refcount\n");
787 WARN(plls->wrpll1_refcount < 0, "Invalid WRPLL1 refcount\n");
788 WARN(plls->wrpll2_refcount < 0, "Invalid WRPLL2 refcount\n");
789
790 intel_crtc->ddi_pll_sel = PORT_CLK_SEL_NONE;
791}
792
793static void intel_ddi_calculate_wrpll(int clock, int *p, int *n2, int *r2)
794{
795 u32 i;
796
797 for (i = 0; i < ARRAY_SIZE(wrpll_tmds_clock_table); i++)
798 if (clock <= wrpll_tmds_clock_table[i].clock)
799 break;
800
801 if (i == ARRAY_SIZE(wrpll_tmds_clock_table))
802 i--;
803
804 *p = wrpll_tmds_clock_table[i].p;
805 *n2 = wrpll_tmds_clock_table[i].n2;
806 *r2 = wrpll_tmds_clock_table[i].r2;
807
808 if (wrpll_tmds_clock_table[i].clock != clock)
809 DRM_INFO("WRPLL: using settings for %dKHz on %dKHz mode\n",
810 wrpll_tmds_clock_table[i].clock, clock);
811
812 DRM_DEBUG_KMS("WRPLL: %dKHz refresh rate with p=%d, n2=%d r2=%d\n",
813 clock, *p, *n2, *r2);
814}
815
816bool intel_ddi_pll_mode_set(struct drm_crtc *crtc, int clock)
817{
818 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
819 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
068759bd 820 struct drm_encoder *encoder = &intel_encoder->base;
6441ab5f
PZ		 821 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
822 struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
823 int type = intel_encoder->type;
824 enum pipe pipe = intel_crtc->pipe;
825 uint32_t reg, val;
826
827 /* TODO: reuse PLLs when possible (compare values) */
828
829 intel_ddi_put_crtc_pll(crtc);
830
068759bd
PZ		 831 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
832 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
833
834 switch (intel_dp->link_bw) {
835 case DP_LINK_BW_1_62:
836 intel_crtc->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;
837 break;
838 case DP_LINK_BW_2_7:
839 intel_crtc->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350;
840 break;
841 case DP_LINK_BW_5_4:
842 intel_crtc->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700;
843 break;
844 default:
845 DRM_ERROR("Link bandwidth %d unsupported\n",
846 intel_dp->link_bw);
847 return false;
848 }
849
850 /* We don't need to turn any PLL on because we'll use LCPLL. */
851 return true;
852
853 } else if (type == INTEL_OUTPUT_HDMI) {
6441ab5f
PZ		 854 int p, n2, r2;
855
856 if (plls->wrpll1_refcount == 0) {
857 DRM_DEBUG_KMS("Using WRPLL 1 on pipe %c\n",
858 pipe_name(pipe));
859 plls->wrpll1_refcount++;
860 reg = WRPLL_CTL1;
861 intel_crtc->ddi_pll_sel = PORT_CLK_SEL_WRPLL1;
862 } else if (plls->wrpll2_refcount == 0) {
863 DRM_DEBUG_KMS("Using WRPLL 2 on pipe %c\n",
864 pipe_name(pipe));
865 plls->wrpll2_refcount++;
866 reg = WRPLL_CTL2;
867 intel_crtc->ddi_pll_sel = PORT_CLK_SEL_WRPLL2;
868 } else {
869 DRM_ERROR("No WRPLLs available!\n");
870 return false;
871 }
872
873 WARN(I915_READ(reg) & WRPLL_PLL_ENABLE,
874 "WRPLL already enabled\n");
875
876 intel_ddi_calculate_wrpll(clock, &p, &n2, &r2);
877
878 val = WRPLL_PLL_ENABLE | WRPLL_PLL_SELECT_LCPLL_2700 |
879 WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) |
880 WRPLL_DIVIDER_POST(p);
881
882 } else if (type == INTEL_OUTPUT_ANALOG) {
883 if (plls->spll_refcount == 0) {
884 DRM_DEBUG_KMS("Using SPLL on pipe %c\n",
885 pipe_name(pipe));
886 plls->spll_refcount++;
887 reg = SPLL_CTL;
888 intel_crtc->ddi_pll_sel = PORT_CLK_SEL_SPLL;
00037c2e
DL		 889 } else {
890 DRM_ERROR("SPLL already in use\n");
891 return false;
6441ab5f
PZ		 892 }
893
894 WARN(I915_READ(reg) & SPLL_PLL_ENABLE,
895 "SPLL already enabled\n");
896
39bc66c9 897 val = SPLL_PLL_ENABLE | SPLL_PLL_FREQ_1350MHz | SPLL_PLL_SSC;
6441ab5f
PZ		 898
899 } else {
900 WARN(1, "Invalid DDI encoder type %d\n", type);
901 return false;
902 }
903
904 I915_WRITE(reg, val);
905 udelay(20);
906
907 return true;
908}
909
dae84799
PZ		 910void intel_ddi_set_pipe_settings(struct drm_crtc *crtc)
911{
912 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
913 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
914 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
3b117c8f 915 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
dae84799
PZ		 916 int type = intel_encoder->type;
917 uint32_t temp;
918
919 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
920
c9809791 921 temp = TRANS_MSA_SYNC_CLK;
965e0c48 922 switch (intel_crtc->config.pipe_bpp) {
dae84799 923 case 18:
c9809791 924 temp |= TRANS_MSA_6_BPC;
dae84799
PZ		 925 break;
926 case 24:
c9809791 927 temp |= TRANS_MSA_8_BPC;
dae84799
PZ		 928 break;
929 case 30:
c9809791 930 temp |= TRANS_MSA_10_BPC;
dae84799
PZ		 931 break;
932 case 36:
c9809791 933 temp |= TRANS_MSA_12_BPC;
dae84799
PZ		 934 break;
935 default:
4e53c2e0 936 BUG();
dae84799 937 }
c9809791 938 I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
dae84799
PZ		 939 }
940}
941
8228c251 942void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc)
8d9ddbcb
PZ		 943{
944 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
945 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
7739c33b 946 struct drm_encoder *encoder = &intel_encoder->base;
8d9ddbcb
PZ		 947 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
948 enum pipe pipe = intel_crtc->pipe;
3b117c8f 949 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
174edf1f 950 enum port port = intel_ddi_get_encoder_port(intel_encoder);
7739c33b 951 int type = intel_encoder->type;
8d9ddbcb
PZ		 952 uint32_t temp;
953
ad80a810
PZ		 954 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
955 temp = TRANS_DDI_FUNC_ENABLE;
174edf1f 956 temp |= TRANS_DDI_SELECT_PORT(port);
dfcef252 957
965e0c48 958 switch (intel_crtc->config.pipe_bpp) {
dfcef252 959 case 18:
ad80a810 960 temp |= TRANS_DDI_BPC_6;
dfcef252
PZ		 961 break;
962 case 24:
ad80a810 963 temp |= TRANS_DDI_BPC_8;
dfcef252
PZ		 964 break;
965 case 30:
ad80a810 966 temp |= TRANS_DDI_BPC_10;
dfcef252
PZ		 967 break;
968 case 36:
ad80a810 969 temp |= TRANS_DDI_BPC_12;
dfcef252
PZ		 970 break;
971 default:
4e53c2e0 972 BUG();
dfcef252 973 }
72662e10 974
8d9ddbcb 975 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
ad80a810 976 temp |= TRANS_DDI_PVSYNC;
8d9ddbcb 977 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
ad80a810 978 temp |= TRANS_DDI_PHSYNC;
f63eb7c4 979
e6f0bfc4
PZ		 980 if (cpu_transcoder == TRANSCODER_EDP) {
981 switch (pipe) {
982 case PIPE_A:
d6dd9eb1
DV		 983 /* Can only use the always-on power well for eDP when
984 * not using the panel fitter, and when not using motion
985 * blur mitigation (which we don't support). */
b074cec8 986 if (intel_crtc->config.pch_pfit.size)
d6dd9eb1
DV		 987 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
988 else
989 temp |= TRANS_DDI_EDP_INPUT_A_ON;
e6f0bfc4
PZ		 990 break;
991 case PIPE_B:
992 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
993 break;
994 case PIPE_C:
995 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
996 break;
997 default:
998 BUG();
999 break;
1000 }
1001 }
1002
7739c33b
PZ		 1003 if (type == INTEL_OUTPUT_HDMI) {
1004 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
8d9ddbcb
PZ		 1005
1006 if (intel_hdmi->has_hdmi_sink)
ad80a810 1007 temp |= TRANS_DDI_MODE_SELECT_HDMI;
8d9ddbcb 1008 else
ad80a810 1009 temp |= TRANS_DDI_MODE_SELECT_DVI;
8d9ddbcb 1010
7739c33b 1011 } else if (type == INTEL_OUTPUT_ANALOG) {
ad80a810 1012 temp |= TRANS_DDI_MODE_SELECT_FDI;
33d29b14 1013 temp |= (intel_crtc->config.fdi_lanes - 1) << 1;
7739c33b
PZ		 1014
1015 } else if (type == INTEL_OUTPUT_DISPLAYPORT ||
1016 type == INTEL_OUTPUT_EDP) {
1017 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1018
ad80a810 1019 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
7739c33b 1020
17aa6be9 1021 temp |= DDI_PORT_WIDTH(intel_dp->lane_count);
8d9ddbcb 1022 } else {
84f44ce7
VS		 1023 WARN(1, "Invalid encoder type %d for pipe %c\n",
1024 intel_encoder->type, pipe_name(pipe));
8d9ddbcb
PZ		 1025 }
1026
ad80a810 1027 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
8d9ddbcb 1028}
72662e10 1029
ad80a810
PZ		 1030void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
1031 enum transcoder cpu_transcoder)
8d9ddbcb 1032{
ad80a810 1033 uint32_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
8d9ddbcb
PZ		 1034 uint32_t val = I915_READ(reg);
1035
ad80a810
PZ		 1036 val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK);
1037 val |= TRANS_DDI_PORT_NONE;
8d9ddbcb 1038 I915_WRITE(reg, val);
72662e10
ED		 1039}
1040
bcbc889b
PZ		 1041bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
1042{
1043 struct drm_device *dev = intel_connector->base.dev;
1044 struct drm_i915_private *dev_priv = dev->dev_private;
1045 struct intel_encoder *intel_encoder = intel_connector->encoder;
1046 int type = intel_connector->base.connector_type;
1047 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1048 enum pipe pipe = 0;
1049 enum transcoder cpu_transcoder;
1050 uint32_t tmp;
1051
1052 if (!intel_encoder->get_hw_state(intel_encoder, &pipe))
1053 return false;
1054
1055 if (port == PORT_A)
1056 cpu_transcoder = TRANSCODER_EDP;
1057 else
1a240d4d 1058 cpu_transcoder = (enum transcoder) pipe;
bcbc889b
PZ		 1059
1060 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1061
1062 switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
1063 case TRANS_DDI_MODE_SELECT_HDMI:
1064 case TRANS_DDI_MODE_SELECT_DVI:
1065 return (type == DRM_MODE_CONNECTOR_HDMIA);
1066
1067 case TRANS_DDI_MODE_SELECT_DP_SST:
1068 if (type == DRM_MODE_CONNECTOR_eDP)
1069 return true;
1070 case TRANS_DDI_MODE_SELECT_DP_MST:
1071 return (type == DRM_MODE_CONNECTOR_DisplayPort);
1072
1073 case TRANS_DDI_MODE_SELECT_FDI:
1074 return (type == DRM_MODE_CONNECTOR_VGA);
1075
1076 default:
1077 return false;
1078 }
1079}
1080
85234cdc
DV		 1081bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
1082 enum pipe *pipe)
1083{
1084 struct drm_device *dev = encoder->base.dev;
1085 struct drm_i915_private *dev_priv = dev->dev_private;
fe43d3f5 1086 enum port port = intel_ddi_get_encoder_port(encoder);
85234cdc
DV		 1087 u32 tmp;
1088 int i;
1089
fe43d3f5 1090 tmp = I915_READ(DDI_BUF_CTL(port));
85234cdc
DV		 1091
1092 if (!(tmp & DDI_BUF_CTL_ENABLE))
1093 return false;
1094
ad80a810
PZ		 1095 if (port == PORT_A) {
1096 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
85234cdc 1097
ad80a810
PZ		 1098 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
1099 case TRANS_DDI_EDP_INPUT_A_ON:
1100 case TRANS_DDI_EDP_INPUT_A_ONOFF:
1101 *pipe = PIPE_A;
1102 break;
1103 case TRANS_DDI_EDP_INPUT_B_ONOFF:
1104 *pipe = PIPE_B;
1105 break;
1106 case TRANS_DDI_EDP_INPUT_C_ONOFF:
1107 *pipe = PIPE_C;
1108 break;
1109 }
1110
1111 return true;
1112 } else {
1113 for (i = TRANSCODER_A; i <= TRANSCODER_C; i++) {
1114 tmp = I915_READ(TRANS_DDI_FUNC_CTL(i));
1115
1116 if ((tmp & TRANS_DDI_PORT_MASK)
1117 == TRANS_DDI_SELECT_PORT(port)) {
1118 *pipe = i;
1119 return true;
1120 }
85234cdc
DV		 1121 }
1122 }
1123
84f44ce7 1124 DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port));
85234cdc 1125
22f9fe50 1126 return false;
85234cdc
DV		 1127}
1128
6441ab5f
PZ		 1129static uint32_t intel_ddi_get_crtc_pll(struct drm_i915_private *dev_priv,
1130 enum pipe pipe)
1131{
1132 uint32_t temp, ret;
a42f704b 1133 enum port port = I915_MAX_PORTS;
ad80a810
PZ		 1134 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1135 pipe);
6441ab5f
PZ		 1136 int i;
1137
ad80a810
PZ		 1138 if (cpu_transcoder == TRANSCODER_EDP) {
1139 port = PORT_A;
1140 } else {
1141 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1142 temp &= TRANS_DDI_PORT_MASK;
1143
1144 for (i = PORT_B; i <= PORT_E; i++)
1145 if (temp == TRANS_DDI_SELECT_PORT(i))
1146 port = i;
1147 }
6441ab5f 1148
a42f704b
DL		 1149 if (port == I915_MAX_PORTS) {
1150 WARN(1, "Pipe %c enabled on an unknown port\n",
1151 pipe_name(pipe));
1152 ret = PORT_CLK_SEL_NONE;
1153 } else {
1154 ret = I915_READ(PORT_CLK_SEL(port));
1155 DRM_DEBUG_KMS("Pipe %c connected to port %c using clock "
1156 "0x%08x\n", pipe_name(pipe), port_name(port),
1157 ret);
1158 }
6441ab5f
PZ		 1159
1160 return ret;
1161}
1162
1163void intel_ddi_setup_hw_pll_state(struct drm_device *dev)
1164{
1165 struct drm_i915_private *dev_priv = dev->dev_private;
1166 enum pipe pipe;
1167 struct intel_crtc *intel_crtc;
1168
1169 for_each_pipe(pipe) {
1170 intel_crtc =
1171 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
1172
1173 if (!intel_crtc->active)
1174 continue;
1175
1176 intel_crtc->ddi_pll_sel = intel_ddi_get_crtc_pll(dev_priv,
1177 pipe);
1178
1179 switch (intel_crtc->ddi_pll_sel) {
1180 case PORT_CLK_SEL_SPLL:
1181 dev_priv->ddi_plls.spll_refcount++;
1182 break;
1183 case PORT_CLK_SEL_WRPLL1:
1184 dev_priv->ddi_plls.wrpll1_refcount++;
1185 break;
1186 case PORT_CLK_SEL_WRPLL2:
1187 dev_priv->ddi_plls.wrpll2_refcount++;
1188 break;
1189 }
1190 }
1191}
1192
fc914639
PZ		 1193void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc)
1194{
1195 struct drm_crtc *crtc = &intel_crtc->base;
1196 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1197 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
1198 enum port port = intel_ddi_get_encoder_port(intel_encoder);
3b117c8f 1199 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
fc914639 1200
bb523fc0
PZ		 1201 if (cpu_transcoder != TRANSCODER_EDP)
1202 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
1203 TRANS_CLK_SEL_PORT(port));
fc914639
PZ		 1204}
1205
1206void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc)
1207{
1208 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3b117c8f 1209 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
fc914639 1210
bb523fc0
PZ		 1211 if (cpu_transcoder != TRANSCODER_EDP)
1212 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
1213 TRANS_CLK_SEL_DISABLED);
fc914639
PZ		 1214}
1215
00c09d70 1216static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder)
6441ab5f 1217{
c19b0669
PZ		 1218 struct drm_encoder *encoder = &intel_encoder->base;
1219 struct drm_crtc *crtc = encoder->crtc;
1220 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
6441ab5f
PZ		 1221 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1222 enum port port = intel_ddi_get_encoder_port(intel_encoder);
82a4d9c0 1223 int type = intel_encoder->type;
6441ab5f 1224
82a4d9c0
PZ		 1225 if (type == INTEL_OUTPUT_EDP) {
1226 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1227 ironlake_edp_panel_vdd_on(intel_dp);
1228 ironlake_edp_panel_on(intel_dp);
1229 ironlake_edp_panel_vdd_off(intel_dp, true);
1230 }
6441ab5f 1231
82a4d9c0 1232 WARN_ON(intel_crtc->ddi_pll_sel == PORT_CLK_SEL_NONE);
6441ab5f 1233 I915_WRITE(PORT_CLK_SEL(port), intel_crtc->ddi_pll_sel);
c19b0669 1234
82a4d9c0 1235 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
c19b0669
PZ		 1236 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1237
1238 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1239 intel_dp_start_link_train(intel_dp);
1240 intel_dp_complete_link_train(intel_dp);
1241 }
6441ab5f
PZ		 1242}
1243
00c09d70 1244static void intel_ddi_post_disable(struct intel_encoder *intel_encoder)
6441ab5f
PZ		 1245{
1246 struct drm_encoder *encoder = &intel_encoder->base;
1247 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
1248 enum port port = intel_ddi_get_encoder_port(intel_encoder);
82a4d9c0 1249 int type = intel_encoder->type;
2886e93f 1250 uint32_t val;
a836bdf9 1251 bool wait = false;
2886e93f
PZ		 1252
1253 val = I915_READ(DDI_BUF_CTL(port));
1254 if (val & DDI_BUF_CTL_ENABLE) {
1255 val &= ~DDI_BUF_CTL_ENABLE;
1256 I915_WRITE(DDI_BUF_CTL(port), val);
a836bdf9 1257 wait = true;
2886e93f 1258 }
6441ab5f 1259
a836bdf9
PZ		 1260 val = I915_READ(DP_TP_CTL(port));
1261 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
1262 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
1263 I915_WRITE(DP_TP_CTL(port), val);
1264
1265 if (wait)
1266 intel_wait_ddi_buf_idle(dev_priv, port);
1267
82a4d9c0
PZ		 1268 if (type == INTEL_OUTPUT_EDP) {
1269 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1270 ironlake_edp_panel_vdd_on(intel_dp);
1271 ironlake_edp_panel_off(intel_dp);
1272 }
1273
6441ab5f
PZ		 1274 I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
1275}
1276
00c09d70 1277static void intel_enable_ddi(struct intel_encoder *intel_encoder)
72662e10 1278{
6547fef8 1279 struct drm_encoder *encoder = &intel_encoder->base;
7b9f35a6
WX		 1280 struct drm_crtc *crtc = encoder->crtc;
1281 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1282 int pipe = intel_crtc->pipe;
6547fef8 1283 struct drm_device *dev = encoder->dev;
72662e10 1284 struct drm_i915_private *dev_priv = dev->dev_private;
6547fef8
PZ		 1285 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1286 int type = intel_encoder->type;
7b9f35a6 1287 uint32_t tmp;
72662e10 1288
6547fef8 1289 if (type == INTEL_OUTPUT_HDMI) {
876a8cdf
DL		 1290 struct intel_digital_port *intel_dig_port =
1291 enc_to_dig_port(encoder);
1292
6547fef8
PZ		 1293 /* In HDMI/DVI mode, the port width, and swing/emphasis values
1294 * are ignored so nothing special needs to be done besides
1295 * enabling the port.
1296 */
876a8cdf
DL		 1297 I915_WRITE(DDI_BUF_CTL(port),
1298 intel_dig_port->port_reversal | DDI_BUF_CTL_ENABLE);
d6c50ff8
PZ		 1299 } else if (type == INTEL_OUTPUT_EDP) {
1300 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1301
1302 ironlake_edp_backlight_on(intel_dp);
6547fef8 1303 }
7b9f35a6 1304
c77bf565 1305 if (intel_crtc->eld_vld && type != INTEL_OUTPUT_EDP) {
7b9f35a6
WX		 1306 tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
1307 tmp |= ((AUDIO_OUTPUT_ENABLE_A | AUDIO_ELD_VALID_A) << (pipe * 4));
1308 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
1309 }
5ab432ef
DV		 1310}
1311
00c09d70 1312static void intel_disable_ddi(struct intel_encoder *intel_encoder)
5ab432ef 1313{
d6c50ff8 1314 struct drm_encoder *encoder = &intel_encoder->base;
7b9f35a6
WX		 1315 struct drm_crtc *crtc = encoder->crtc;
1316 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1317 int pipe = intel_crtc->pipe;
d6c50ff8 1318 int type = intel_encoder->type;
7b9f35a6
WX		 1319 struct drm_device *dev = encoder->dev;
1320 struct drm_i915_private *dev_priv = dev->dev_private;
1321 uint32_t tmp;
d6c50ff8 1322
c77bf565
PZ		 1323 if (intel_crtc->eld_vld && type != INTEL_OUTPUT_EDP) {
1324 tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
1325 tmp &= ~((AUDIO_OUTPUT_ENABLE_A | AUDIO_ELD_VALID_A) <<
1326 (pipe * 4));
1327 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
1328 }
2831d842 1329
d6c50ff8
PZ		 1330 if (type == INTEL_OUTPUT_EDP) {
1331 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1332
1333 ironlake_edp_backlight_off(intel_dp);
1334 }
72662e10 1335}
79f689aa 1336
b8fc2f6a 1337int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv)
79f689aa
PZ		 1338{
1339 if (I915_READ(HSW_FUSE_STRAP) & HSW_CDCLK_LIMIT)
1340 return 450;
1341 else if ((I915_READ(LCPLL_CTL) & LCPLL_CLK_FREQ_MASK) ==
1342 LCPLL_CLK_FREQ_450)
1343 return 450;
d567b07f
PZ		 1344 else if (IS_ULT(dev_priv->dev))
1345 return 338;
79f689aa
PZ		 1346 else
1347 return 540;
1348}
1349
1350void intel_ddi_pll_init(struct drm_device *dev)
1351{
1352 struct drm_i915_private *dev_priv = dev->dev_private;
1353 uint32_t val = I915_READ(LCPLL_CTL);
1354
1355 /* The LCPLL register should be turned on by the BIOS. For now let's
1356 * just check its state and print errors in case something is wrong.
1357 * Don't even try to turn it on.
1358 */
1359
1360 DRM_DEBUG_KMS("CDCLK running at %dMHz\n",
1361 intel_ddi_get_cdclk_freq(dev_priv));
1362
1363 if (val & LCPLL_CD_SOURCE_FCLK)
1364 DRM_ERROR("CDCLK source is not LCPLL\n");
1365
1366 if (val & LCPLL_PLL_DISABLE)
1367 DRM_ERROR("LCPLL is disabled\n");
1368}
c19b0669
PZ		 1369
1370void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder)
1371{
174edf1f
PZ		 1372 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
1373 struct intel_dp *intel_dp = &intel_dig_port->dp;
c19b0669 1374 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
174edf1f 1375 enum port port = intel_dig_port->port;
c19b0669 1376 uint32_t val;
f3e227df 1377 bool wait = false;
c19b0669
PZ		 1378
1379 if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
1380 val = I915_READ(DDI_BUF_CTL(port));
1381 if (val & DDI_BUF_CTL_ENABLE) {
1382 val &= ~DDI_BUF_CTL_ENABLE;
1383 I915_WRITE(DDI_BUF_CTL(port), val);
1384 wait = true;
1385 }
1386
1387 val = I915_READ(DP_TP_CTL(port));
1388 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
1389 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
1390 I915_WRITE(DP_TP_CTL(port), val);
1391 POSTING_READ(DP_TP_CTL(port));
1392
1393 if (wait)
1394 intel_wait_ddi_buf_idle(dev_priv, port);
1395 }
1396
1397 val = DP_TP_CTL_ENABLE | DP_TP_CTL_MODE_SST |
1398 DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
1399 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
1400 val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
1401 I915_WRITE(DP_TP_CTL(port), val);
1402 POSTING_READ(DP_TP_CTL(port));
1403
1404 intel_dp->DP |= DDI_BUF_CTL_ENABLE;
1405 I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
1406 POSTING_READ(DDI_BUF_CTL(port));
1407
1408 udelay(600);
1409}
00c09d70 1410
1ad960f2
PZ		 1411void intel_ddi_fdi_disable(struct drm_crtc *crtc)
1412{
1413 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1414 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
1415 uint32_t val;
1416
1417 intel_ddi_post_disable(intel_encoder);
1418
1419 val = I915_READ(_FDI_RXA_CTL);
1420 val &= ~FDI_RX_ENABLE;
1421 I915_WRITE(_FDI_RXA_CTL, val);
1422
1423 val = I915_READ(_FDI_RXA_MISC);
1424 val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
1425 val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
1426 I915_WRITE(_FDI_RXA_MISC, val);
1427
1428 val = I915_READ(_FDI_RXA_CTL);
1429 val &= ~FDI_PCDCLK;
1430 I915_WRITE(_FDI_RXA_CTL, val);
1431
1432 val = I915_READ(_FDI_RXA_CTL);
1433 val &= ~FDI_RX_PLL_ENABLE;
1434 I915_WRITE(_FDI_RXA_CTL, val);
1435}
1436
00c09d70
PZ		 1437static void intel_ddi_hot_plug(struct intel_encoder *intel_encoder)
1438{
1439 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
1440 int type = intel_encoder->type;
1441
1442 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP)
1443 intel_dp_check_link_status(intel_dp);
1444}
1445
1446static void intel_ddi_destroy(struct drm_encoder *encoder)
1447{
1448 /* HDMI has nothing special to destroy, so we can go with this. */
1449 intel_dp_encoder_destroy(encoder);
1450}
1451
5bfe2ac0
DV		 1452static bool intel_ddi_compute_config(struct intel_encoder *encoder,
1453 struct intel_crtc_config *pipe_config)
00c09d70 1454{
5bfe2ac0 1455 int type = encoder->type;
00c09d70 1456
5bfe2ac0 1457 WARN(type == INTEL_OUTPUT_UNKNOWN, "compute_config() on unknown output!\n");
00c09d70
PZ		 1458
1459 if (type == INTEL_OUTPUT_HDMI)
5bfe2ac0 1460 return intel_hdmi_compute_config(encoder, pipe_config);
00c09d70 1461 else
5bfe2ac0 1462 return intel_dp_compute_config(encoder, pipe_config);
00c09d70
PZ		 1463}
1464
1465static const struct drm_encoder_funcs intel_ddi_funcs = {
1466 .destroy = intel_ddi_destroy,
1467};
1468
1469static const struct drm_encoder_helper_funcs intel_ddi_helper_funcs = {
00c09d70 1470 .mode_set = intel_ddi_mode_set,
00c09d70
PZ		 1471};
1472
1473void intel_ddi_init(struct drm_device *dev, enum port port)
1474{
876a8cdf 1475 struct drm_i915_private *dev_priv = dev->dev_private;
00c09d70
PZ		 1476 struct intel_digital_port *intel_dig_port;
1477 struct intel_encoder *intel_encoder;
1478 struct drm_encoder *encoder;
1479 struct intel_connector *hdmi_connector = NULL;
1480 struct intel_connector *dp_connector = NULL;
1481
1482 intel_dig_port = kzalloc(sizeof(struct intel_digital_port), GFP_KERNEL);
1483 if (!intel_dig_port)
1484 return;
1485
1486 dp_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
1487 if (!dp_connector) {
1488 kfree(intel_dig_port);
1489 return;
1490 }
1491
00c09d70
PZ		 1492 intel_encoder = &intel_dig_port->base;
1493 encoder = &intel_encoder->base;
1494
1495 drm_encoder_init(dev, encoder, &intel_ddi_funcs,
1496 DRM_MODE_ENCODER_TMDS);
1497 drm_encoder_helper_add(encoder, &intel_ddi_helper_funcs);
1498
5bfe2ac0 1499 intel_encoder->compute_config = intel_ddi_compute_config;
00c09d70
PZ		 1500 intel_encoder->enable = intel_enable_ddi;
1501 intel_encoder->pre_enable = intel_ddi_pre_enable;
1502 intel_encoder->disable = intel_disable_ddi;
1503 intel_encoder->post_disable = intel_ddi_post_disable;
1504 intel_encoder->get_hw_state = intel_ddi_get_hw_state;
1505
1506 intel_dig_port->port = port;
876a8cdf
DL		 1507 intel_dig_port->port_reversal = I915_READ(DDI_BUF_CTL(port)) &
1508 DDI_BUF_PORT_REVERSAL;
00c09d70
PZ		 1509 intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
1510
1511 intel_encoder->type = INTEL_OUTPUT_UNKNOWN;
1512 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
1513 intel_encoder->cloneable = false;
1514 intel_encoder->hot_plug = intel_ddi_hot_plug;
1515
00c09d70 1516 intel_dp_init_connector(intel_dig_port, dp_connector);
21a8e6a4
DV		 1517
1518 if (intel_encoder->type != INTEL_OUTPUT_EDP) {
1519 hdmi_connector = kzalloc(sizeof(struct intel_connector),
1520 GFP_KERNEL);
1521 if (!hdmi_connector) {
1522 return;
1523 }
1524
1525 intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
1526 intel_hdmi_init_connector(intel_dig_port, hdmi_connector);
1527 }
00c09d70 1528}
Linux kernel - Deliverables
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