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drm/i915: remove Haswell code from ironlake_enable_pch_transcoder
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
760285e7
DH		 40#include <drm/drm_dp_helper.h>
41#include <drm/drm_crtc_helper.h>
c0f372b3 42#include <linux/dma_remapping.h>
79e53945 43
32f9d658
ZW		 44#define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
45
0206e353 46bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
3dec0095 47static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 48static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945
JB		 49
50typedef struct {
0206e353
AJ		 51 /* given values */
52 int n;
53 int m1, m2;
54 int p1, p2;
55 /* derived values */
56 int dot;
57 int vco;
58 int m;
59 int p;
79e53945
JB		 60} intel_clock_t;
61
62typedef struct {
0206e353 63 int min, max;
79e53945
JB		 64} intel_range_t;
65
66typedef struct {
0206e353
AJ		 67 int dot_limit;
68 int p2_slow, p2_fast;
79e53945
JB		 69} intel_p2_t;
70
71#define INTEL_P2_NUM 2
d4906093
ML		 72typedef struct intel_limit intel_limit_t;
73struct intel_limit {
0206e353
AJ		 74 intel_range_t dot, vco, n, m, m1, m2, p, p1;
75 intel_p2_t p2;
76 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
cec2f356 77 int, int, intel_clock_t *, intel_clock_t *);
d4906093 78};
79e53945 79
2377b741
JB		 80/* FDI */
81#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
82
d2acd215
DV		 83int
84intel_pch_rawclk(struct drm_device *dev)
85{
86 struct drm_i915_private *dev_priv = dev->dev_private;
87
88 WARN_ON(!HAS_PCH_SPLIT(dev));
89
90 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
91}
92
d4906093
ML		 93static bool
94intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 95 int target, int refclk, intel_clock_t *match_clock,
96 intel_clock_t *best_clock);
d4906093
ML		 97static bool
98intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 99 int target, int refclk, intel_clock_t *match_clock,
100 intel_clock_t *best_clock);
79e53945 101
a4fc5ed6
KP		 102static bool
103intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
cec2f356
SP		 104 int target, int refclk, intel_clock_t *match_clock,
105 intel_clock_t *best_clock);
5eb08b69 106static bool
f2b115e6 107intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
cec2f356
SP		 108 int target, int refclk, intel_clock_t *match_clock,
109 intel_clock_t *best_clock);
a4fc5ed6 110
a0c4da24
JB		 111static bool
112intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
113 int target, int refclk, intel_clock_t *match_clock,
114 intel_clock_t *best_clock);
115
021357ac
CW		 116static inline u32 /* units of 100MHz */
117intel_fdi_link_freq(struct drm_device *dev)
118{
8b99e68c
CW		 119 if (IS_GEN5(dev)) {
120 struct drm_i915_private *dev_priv = dev->dev_private;
121 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
122 } else
123 return 27;
021357ac
CW		 124}
125
e4b36699 126static const intel_limit_t intel_limits_i8xx_dvo = {
0206e353
AJ		 127 .dot = { .min = 25000, .max = 350000 },
128 .vco = { .min = 930000, .max = 1400000 },
129 .n = { .min = 3, .max = 16 },
130 .m = { .min = 96, .max = 140 },
131 .m1 = { .min = 18, .max = 26 },
132 .m2 = { .min = 6, .max = 16 },
133 .p = { .min = 4, .max = 128 },
134 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 135 .p2 = { .dot_limit = 165000,
136 .p2_slow = 4, .p2_fast = 2 },
d4906093 137 .find_pll = intel_find_best_PLL,
e4b36699
KP		 138};
139
140static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353
AJ		 141 .dot = { .min = 25000, .max = 350000 },
142 .vco = { .min = 930000, .max = 1400000 },
143 .n = { .min = 3, .max = 16 },
144 .m = { .min = 96, .max = 140 },
145 .m1 = { .min = 18, .max = 26 },
146 .m2 = { .min = 6, .max = 16 },
147 .p = { .min = 4, .max = 128 },
148 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 149 .p2 = { .dot_limit = 165000,
150 .p2_slow = 14, .p2_fast = 7 },
d4906093 151 .find_pll = intel_find_best_PLL,
e4b36699 152};
273e27ca 153
e4b36699 154static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 155 .dot = { .min = 20000, .max = 400000 },
156 .vco = { .min = 1400000, .max = 2800000 },
157 .n = { .min = 1, .max = 6 },
158 .m = { .min = 70, .max = 120 },
159 .m1 = { .min = 10, .max = 22 },
160 .m2 = { .min = 5, .max = 9 },
161 .p = { .min = 5, .max = 80 },
162 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 163 .p2 = { .dot_limit = 200000,
164 .p2_slow = 10, .p2_fast = 5 },
d4906093 165 .find_pll = intel_find_best_PLL,
e4b36699
KP		 166};
167
168static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 169 .dot = { .min = 20000, .max = 400000 },
170 .vco = { .min = 1400000, .max = 2800000 },
171 .n = { .min = 1, .max = 6 },
172 .m = { .min = 70, .max = 120 },
173 .m1 = { .min = 10, .max = 22 },
174 .m2 = { .min = 5, .max = 9 },
175 .p = { .min = 7, .max = 98 },
176 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 177 .p2 = { .dot_limit = 112000,
178 .p2_slow = 14, .p2_fast = 7 },
d4906093 179 .find_pll = intel_find_best_PLL,
e4b36699
KP		 180};
181
273e27ca 182
e4b36699 183static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 184 .dot = { .min = 25000, .max = 270000 },
185 .vco = { .min = 1750000, .max = 3500000},
186 .n = { .min = 1, .max = 4 },
187 .m = { .min = 104, .max = 138 },
188 .m1 = { .min = 17, .max = 23 },
189 .m2 = { .min = 5, .max = 11 },
190 .p = { .min = 10, .max = 30 },
191 .p1 = { .min = 1, .max = 3},
192 .p2 = { .dot_limit = 270000,
193 .p2_slow = 10,
194 .p2_fast = 10
044c7c41 195 },
d4906093 196 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 197};
198
199static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 200 .dot = { .min = 22000, .max = 400000 },
201 .vco = { .min = 1750000, .max = 3500000},
202 .n = { .min = 1, .max = 4 },
203 .m = { .min = 104, .max = 138 },
204 .m1 = { .min = 16, .max = 23 },
205 .m2 = { .min = 5, .max = 11 },
206 .p = { .min = 5, .max = 80 },
207 .p1 = { .min = 1, .max = 8},
208 .p2 = { .dot_limit = 165000,
209 .p2_slow = 10, .p2_fast = 5 },
d4906093 210 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 211};
212
213static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 214 .dot = { .min = 20000, .max = 115000 },
215 .vco = { .min = 1750000, .max = 3500000 },
216 .n = { .min = 1, .max = 3 },
217 .m = { .min = 104, .max = 138 },
218 .m1 = { .min = 17, .max = 23 },
219 .m2 = { .min = 5, .max = 11 },
220 .p = { .min = 28, .max = 112 },
221 .p1 = { .min = 2, .max = 8 },
222 .p2 = { .dot_limit = 0,
223 .p2_slow = 14, .p2_fast = 14
044c7c41 224 },
d4906093 225 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 226};
227
228static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 229 .dot = { .min = 80000, .max = 224000 },
230 .vco = { .min = 1750000, .max = 3500000 },
231 .n = { .min = 1, .max = 3 },
232 .m = { .min = 104, .max = 138 },
233 .m1 = { .min = 17, .max = 23 },
234 .m2 = { .min = 5, .max = 11 },
235 .p = { .min = 14, .max = 42 },
236 .p1 = { .min = 2, .max = 6 },
237 .p2 = { .dot_limit = 0,
238 .p2_slow = 7, .p2_fast = 7
044c7c41 239 },
d4906093 240 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 241};
242
243static const intel_limit_t intel_limits_g4x_display_port = {
0206e353
AJ		 244 .dot = { .min = 161670, .max = 227000 },
245 .vco = { .min = 1750000, .max = 3500000},
246 .n = { .min = 1, .max = 2 },
247 .m = { .min = 97, .max = 108 },
248 .m1 = { .min = 0x10, .max = 0x12 },
249 .m2 = { .min = 0x05, .max = 0x06 },
250 .p = { .min = 10, .max = 20 },
251 .p1 = { .min = 1, .max = 2},
252 .p2 = { .dot_limit = 0,
273e27ca 253 .p2_slow = 10, .p2_fast = 10 },
0206e353 254 .find_pll = intel_find_pll_g4x_dp,
e4b36699
KP		 255};
256
f2b115e6 257static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 258 .dot = { .min = 20000, .max = 400000},
259 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 260 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 261 .n = { .min = 3, .max = 6 },
262 .m = { .min = 2, .max = 256 },
273e27ca 263 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 264 .m1 = { .min = 0, .max = 0 },
265 .m2 = { .min = 0, .max = 254 },
266 .p = { .min = 5, .max = 80 },
267 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 268 .p2 = { .dot_limit = 200000,
269 .p2_slow = 10, .p2_fast = 5 },
6115707b 270 .find_pll = intel_find_best_PLL,
e4b36699
KP		 271};
272
f2b115e6 273static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 274 .dot = { .min = 20000, .max = 400000 },
275 .vco = { .min = 1700000, .max = 3500000 },
276 .n = { .min = 3, .max = 6 },
277 .m = { .min = 2, .max = 256 },
278 .m1 = { .min = 0, .max = 0 },
279 .m2 = { .min = 0, .max = 254 },
280 .p = { .min = 7, .max = 112 },
281 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 282 .p2 = { .dot_limit = 112000,
283 .p2_slow = 14, .p2_fast = 14 },
6115707b 284 .find_pll = intel_find_best_PLL,
e4b36699
KP		 285};
286
273e27ca
EA		 287/* Ironlake / Sandybridge
288 *
289 * We calculate clock using (register_value + 2) for N/M1/M2, so here
290 * the range value for them is (actual_value - 2).
291 */
b91ad0ec 292static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 293 .dot = { .min = 25000, .max = 350000 },
294 .vco = { .min = 1760000, .max = 3510000 },
295 .n = { .min = 1, .max = 5 },
296 .m = { .min = 79, .max = 127 },
297 .m1 = { .min = 12, .max = 22 },
298 .m2 = { .min = 5, .max = 9 },
299 .p = { .min = 5, .max = 80 },
300 .p1 = { .min = 1, .max = 8 },
301 .p2 = { .dot_limit = 225000,
302 .p2_slow = 10, .p2_fast = 5 },
4547668a 303 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 304};
305
b91ad0ec 306static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 307 .dot = { .min = 25000, .max = 350000 },
308 .vco = { .min = 1760000, .max = 3510000 },
309 .n = { .min = 1, .max = 3 },
310 .m = { .min = 79, .max = 118 },
311 .m1 = { .min = 12, .max = 22 },
312 .m2 = { .min = 5, .max = 9 },
313 .p = { .min = 28, .max = 112 },
314 .p1 = { .min = 2, .max = 8 },
315 .p2 = { .dot_limit = 225000,
316 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 317 .find_pll = intel_g4x_find_best_PLL,
318};
319
320static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 321 .dot = { .min = 25000, .max = 350000 },
322 .vco = { .min = 1760000, .max = 3510000 },
323 .n = { .min = 1, .max = 3 },
324 .m = { .min = 79, .max = 127 },
325 .m1 = { .min = 12, .max = 22 },
326 .m2 = { .min = 5, .max = 9 },
327 .p = { .min = 14, .max = 56 },
328 .p1 = { .min = 2, .max = 8 },
329 .p2 = { .dot_limit = 225000,
330 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 331 .find_pll = intel_g4x_find_best_PLL,
332};
333
273e27ca 334/* LVDS 100mhz refclk limits. */
b91ad0ec 335static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 336 .dot = { .min = 25000, .max = 350000 },
337 .vco = { .min = 1760000, .max = 3510000 },
338 .n = { .min = 1, .max = 2 },
339 .m = { .min = 79, .max = 126 },
340 .m1 = { .min = 12, .max = 22 },
341 .m2 = { .min = 5, .max = 9 },
342 .p = { .min = 28, .max = 112 },
0206e353 343 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 344 .p2 = { .dot_limit = 225000,
345 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 346 .find_pll = intel_g4x_find_best_PLL,
347};
348
349static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 350 .dot = { .min = 25000, .max = 350000 },
351 .vco = { .min = 1760000, .max = 3510000 },
352 .n = { .min = 1, .max = 3 },
353 .m = { .min = 79, .max = 126 },
354 .m1 = { .min = 12, .max = 22 },
355 .m2 = { .min = 5, .max = 9 },
356 .p = { .min = 14, .max = 42 },
0206e353 357 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 358 .p2 = { .dot_limit = 225000,
359 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 360 .find_pll = intel_g4x_find_best_PLL,
361};
362
363static const intel_limit_t intel_limits_ironlake_display_port = {
0206e353
AJ		 364 .dot = { .min = 25000, .max = 350000 },
365 .vco = { .min = 1760000, .max = 3510000},
366 .n = { .min = 1, .max = 2 },
367 .m = { .min = 81, .max = 90 },
368 .m1 = { .min = 12, .max = 22 },
369 .m2 = { .min = 5, .max = 9 },
370 .p = { .min = 10, .max = 20 },
371 .p1 = { .min = 1, .max = 2},
372 .p2 = { .dot_limit = 0,
273e27ca 373 .p2_slow = 10, .p2_fast = 10 },
0206e353 374 .find_pll = intel_find_pll_ironlake_dp,
79e53945
JB		 375};
376
a0c4da24
JB		 377static const intel_limit_t intel_limits_vlv_dac = {
378 .dot = { .min = 25000, .max = 270000 },
379 .vco = { .min = 4000000, .max = 6000000 },
380 .n = { .min = 1, .max = 7 },
381 .m = { .min = 22, .max = 450 }, /* guess */
382 .m1 = { .min = 2, .max = 3 },
383 .m2 = { .min = 11, .max = 156 },
384 .p = { .min = 10, .max = 30 },
385 .p1 = { .min = 2, .max = 3 },
386 .p2 = { .dot_limit = 270000,
387 .p2_slow = 2, .p2_fast = 20 },
388 .find_pll = intel_vlv_find_best_pll,
389};
390
391static const intel_limit_t intel_limits_vlv_hdmi = {
392 .dot = { .min = 20000, .max = 165000 },
17dc9257 393 .vco = { .min = 4000000, .max = 5994000},
a0c4da24
JB		 394 .n = { .min = 1, .max = 7 },
395 .m = { .min = 60, .max = 300 }, /* guess */
396 .m1 = { .min = 2, .max = 3 },
397 .m2 = { .min = 11, .max = 156 },
398 .p = { .min = 10, .max = 30 },
399 .p1 = { .min = 2, .max = 3 },
400 .p2 = { .dot_limit = 270000,
401 .p2_slow = 2, .p2_fast = 20 },
402 .find_pll = intel_vlv_find_best_pll,
403};
404
405static const intel_limit_t intel_limits_vlv_dp = {
74a4dd2e
VP		 406 .dot = { .min = 25000, .max = 270000 },
407 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24 408 .n = { .min = 1, .max = 7 },
74a4dd2e 409 .m = { .min = 22, .max = 450 },
a0c4da24
JB		 410 .m1 = { .min = 2, .max = 3 },
411 .m2 = { .min = 11, .max = 156 },
412 .p = { .min = 10, .max = 30 },
413 .p1 = { .min = 2, .max = 3 },
414 .p2 = { .dot_limit = 270000,
415 .p2_slow = 2, .p2_fast = 20 },
416 .find_pll = intel_vlv_find_best_pll,
417};
418
57f350b6
JB		 419u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
420{
421 unsigned long flags;
422 u32 val = 0;
423
424 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
425 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
426 DRM_ERROR("DPIO idle wait timed out\n");
427 goto out_unlock;
428 }
429
430 I915_WRITE(DPIO_REG, reg);
431 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
432 DPIO_BYTE);
433 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
434 DRM_ERROR("DPIO read wait timed out\n");
435 goto out_unlock;
436 }
437 val = I915_READ(DPIO_DATA);
438
439out_unlock:
440 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
441 return val;
442}
443
a0c4da24
JB		 444static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
445 u32 val)
446{
447 unsigned long flags;
448
449 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
450 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
451 DRM_ERROR("DPIO idle wait timed out\n");
452 goto out_unlock;
453 }
454
455 I915_WRITE(DPIO_DATA, val);
456 I915_WRITE(DPIO_REG, reg);
457 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
458 DPIO_BYTE);
459 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
460 DRM_ERROR("DPIO write wait timed out\n");
461
462out_unlock:
463 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
464}
465
57f350b6
JB		 466static void vlv_init_dpio(struct drm_device *dev)
467{
468 struct drm_i915_private *dev_priv = dev->dev_private;
469
470 /* Reset the DPIO config */
471 I915_WRITE(DPIO_CTL, 0);
472 POSTING_READ(DPIO_CTL);
473 I915_WRITE(DPIO_CTL, 1);
474 POSTING_READ(DPIO_CTL);
475}
476
618563e3
DV		 477static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
478{
479 DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
480 return 1;
481}
482
483static const struct dmi_system_id intel_dual_link_lvds[] = {
484 {
485 .callback = intel_dual_link_lvds_callback,
486 .ident = "Apple MacBook Pro (Core i5/i7 Series)",
487 .matches = {
488 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
489 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
490 },
491 },
492 { } /* terminating entry */
493};
494
b0354385
TI		 495static bool is_dual_link_lvds(struct drm_i915_private *dev_priv,
496 unsigned int reg)
497{
498 unsigned int val;
499
121d527a
TI		 500 /* use the module option value if specified */
501 if (i915_lvds_channel_mode > 0)
502 return i915_lvds_channel_mode == 2;
503
618563e3
DV		 504 if (dmi_check_system(intel_dual_link_lvds))
505 return true;
506
b0354385
TI		 507 if (dev_priv->lvds_val)
508 val = dev_priv->lvds_val;
509 else {
510 /* BIOS should set the proper LVDS register value at boot, but
511 * in reality, it doesn't set the value when the lid is closed;
512 * we need to check "the value to be set" in VBT when LVDS
513 * register is uninitialized.
514 */
515 val = I915_READ(reg);
14d94a3d 516 if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED)))
b0354385
TI		 517 val = dev_priv->bios_lvds_val;
518 dev_priv->lvds_val = val;
519 }
520 return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
521}
522
1b894b59
CW		 523static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
524 int refclk)
2c07245f 525{
b91ad0ec
ZW		 526 struct drm_device *dev = crtc->dev;
527 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 528 const intel_limit_t *limit;
b91ad0ec
ZW		 529
530 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
b0354385 531 if (is_dual_link_lvds(dev_priv, PCH_LVDS)) {
b91ad0ec 532 /* LVDS dual channel */
1b894b59 533 if (refclk == 100000)
b91ad0ec
ZW		 534 limit = &intel_limits_ironlake_dual_lvds_100m;
535 else
536 limit = &intel_limits_ironlake_dual_lvds;
537 } else {
1b894b59 538 if (refclk == 100000)
b91ad0ec
ZW		 539 limit = &intel_limits_ironlake_single_lvds_100m;
540 else
541 limit = &intel_limits_ironlake_single_lvds;
542 }
543 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
4547668a
ZY		 544 HAS_eDP)
545 limit = &intel_limits_ironlake_display_port;
2c07245f 546 else
b91ad0ec 547 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 548
549 return limit;
550}
551
044c7c41
ML		 552static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
553{
554 struct drm_device *dev = crtc->dev;
555 struct drm_i915_private *dev_priv = dev->dev_private;
556 const intel_limit_t *limit;
557
558 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
b0354385 559 if (is_dual_link_lvds(dev_priv, LVDS))
044c7c41 560 /* LVDS with dual channel */
e4b36699 561 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41
ML		 562 else
563 /* LVDS with dual channel */
e4b36699 564 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 565 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
566 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 567 limit = &intel_limits_g4x_hdmi;
044c7c41 568 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 569 limit = &intel_limits_g4x_sdvo;
0206e353 570 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
e4b36699 571 limit = &intel_limits_g4x_display_port;
044c7c41 572 } else /* The option is for other outputs */
e4b36699 573 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 574
575 return limit;
576}
577
1b894b59 578static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 579{
580 struct drm_device *dev = crtc->dev;
581 const intel_limit_t *limit;
582
bad720ff 583 if (HAS_PCH_SPLIT(dev))
1b894b59 584 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 585 else if (IS_G4X(dev)) {
044c7c41 586 limit = intel_g4x_limit(crtc);
f2b115e6 587 } else if (IS_PINEVIEW(dev)) {
2177832f 588 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 589 limit = &intel_limits_pineview_lvds;
2177832f 590 else
f2b115e6 591 limit = &intel_limits_pineview_sdvo;
a0c4da24
JB		 592 } else if (IS_VALLEYVIEW(dev)) {
593 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
594 limit = &intel_limits_vlv_dac;
595 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
596 limit = &intel_limits_vlv_hdmi;
597 else
598 limit = &intel_limits_vlv_dp;
a6c45cf0
CW		 599 } else if (!IS_GEN2(dev)) {
600 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
601 limit = &intel_limits_i9xx_lvds;
602 else
603 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 604 } else {
605 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 606 limit = &intel_limits_i8xx_lvds;
79e53945 607 else
e4b36699 608 limit = &intel_limits_i8xx_dvo;
79e53945
JB		 609 }
610 return limit;
611}
612
f2b115e6
AJ		 613/* m1 is reserved as 0 in Pineview, n is a ring counter */
614static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 615{
2177832f
SL		 616 clock->m = clock->m2 + 2;
617 clock->p = clock->p1 * clock->p2;
618 clock->vco = refclk * clock->m / clock->n;
619 clock->dot = clock->vco / clock->p;
620}
621
622static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
623{
f2b115e6
AJ		 624 if (IS_PINEVIEW(dev)) {
625 pineview_clock(refclk, clock);
2177832f
SL		 626 return;
627 }
79e53945
JB		 628 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
629 clock->p = clock->p1 * clock->p2;
630 clock->vco = refclk * clock->m / (clock->n + 2);
631 clock->dot = clock->vco / clock->p;
632}
633
79e53945
JB		 634/**
635 * Returns whether any output on the specified pipe is of the specified type
636 */
4ef69c7a 637bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
79e53945 638{
4ef69c7a 639 struct drm_device *dev = crtc->dev;
4ef69c7a
CW		 640 struct intel_encoder *encoder;
641
6c2b7c12
DV		 642 for_each_encoder_on_crtc(dev, crtc, encoder)
643 if (encoder->type == type)
4ef69c7a
CW		 644 return true;
645
646 return false;
79e53945
JB		 647}
648
7c04d1d9 649#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 650/**
651 * Returns whether the given set of divisors are valid for a given refclk with
652 * the given connectors.
653 */
654
1b894b59
CW		 655static bool intel_PLL_is_valid(struct drm_device *dev,
656 const intel_limit_t *limit,
657 const intel_clock_t *clock)
79e53945 658{
79e53945 659 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 660 INTELPllInvalid("p1 out of range\n");
79e53945 661 if (clock->p < limit->p.min || limit->p.max < clock->p)
0206e353 662 INTELPllInvalid("p out of range\n");
79e53945 663 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 664 INTELPllInvalid("m2 out of range\n");
79e53945 665 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 666 INTELPllInvalid("m1 out of range\n");
f2b115e6 667 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
0206e353 668 INTELPllInvalid("m1 <= m2\n");
79e53945 669 if (clock->m < limit->m.min || limit->m.max < clock->m)
0206e353 670 INTELPllInvalid("m out of range\n");
79e53945 671 if (clock->n < limit->n.min || limit->n.max < clock->n)
0206e353 672 INTELPllInvalid("n out of range\n");
79e53945 673 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 674 INTELPllInvalid("vco out of range\n");
79e53945
JB		 675 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
676 * connector, etc., rather than just a single range.
677 */
678 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 679 INTELPllInvalid("dot out of range\n");
79e53945
JB		 680
681 return true;
682}
683
d4906093
ML		 684static bool
685intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 686 int target, int refclk, intel_clock_t *match_clock,
687 intel_clock_t *best_clock)
d4906093 688
79e53945
JB		 689{
690 struct drm_device *dev = crtc->dev;
691 struct drm_i915_private *dev_priv = dev->dev_private;
692 intel_clock_t clock;
79e53945
JB		 693 int err = target;
694
bc5e5718 695 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
832cc28d 696 (I915_READ(LVDS)) != 0) {
79e53945
JB		 697 /*
698 * For LVDS, if the panel is on, just rely on its current
699 * settings for dual-channel. We haven't figured out how to
700 * reliably set up different single/dual channel state, if we
701 * even can.
702 */
b0354385 703 if (is_dual_link_lvds(dev_priv, LVDS))
79e53945
JB		 704 clock.p2 = limit->p2.p2_fast;
705 else
706 clock.p2 = limit->p2.p2_slow;
707 } else {
708 if (target < limit->p2.dot_limit)
709 clock.p2 = limit->p2.p2_slow;
710 else
711 clock.p2 = limit->p2.p2_fast;
712 }
713
0206e353 714 memset(best_clock, 0, sizeof(*best_clock));
79e53945 715
42158660
ZY		 716 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
717 clock.m1++) {
718 for (clock.m2 = limit->m2.min;
719 clock.m2 <= limit->m2.max; clock.m2++) {
f2b115e6
AJ		 720 /* m1 is always 0 in Pineview */
721 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
42158660
ZY		 722 break;
723 for (clock.n = limit->n.min;
724 clock.n <= limit->n.max; clock.n++) {
725 for (clock.p1 = limit->p1.min;
726 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 727 int this_err;
728
2177832f 729 intel_clock(dev, refclk, &clock);
1b894b59
CW		 730 if (!intel_PLL_is_valid(dev, limit,
731 &clock))
79e53945 732 continue;
cec2f356
SP		 733 if (match_clock &&
734 clock.p != match_clock->p)
735 continue;
79e53945
JB		 736
737 this_err = abs(clock.dot - target);
738 if (this_err < err) {
739 *best_clock = clock;
740 err = this_err;
741 }
742 }
743 }
744 }
745 }
746
747 return (err != target);
748}
749
d4906093
ML		 750static bool
751intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 752 int target, int refclk, intel_clock_t *match_clock,
753 intel_clock_t *best_clock)
d4906093
ML		 754{
755 struct drm_device *dev = crtc->dev;
756 struct drm_i915_private *dev_priv = dev->dev_private;
757 intel_clock_t clock;
758 int max_n;
759 bool found;
6ba770dc
AJ		 760 /* approximately equals target * 0.00585 */
761 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 762 found = false;
763
764 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4547668a
ZY		 765 int lvds_reg;
766
c619eed4 767 if (HAS_PCH_SPLIT(dev))
4547668a
ZY		 768 lvds_reg = PCH_LVDS;
769 else
770 lvds_reg = LVDS;
771 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
d4906093
ML		 772 LVDS_CLKB_POWER_UP)
773 clock.p2 = limit->p2.p2_fast;
774 else
775 clock.p2 = limit->p2.p2_slow;
776 } else {
777 if (target < limit->p2.dot_limit)
778 clock.p2 = limit->p2.p2_slow;
779 else
780 clock.p2 = limit->p2.p2_fast;
781 }
782
783 memset(best_clock, 0, sizeof(*best_clock));
784 max_n = limit->n.max;
f77f13e2 785 /* based on hardware requirement, prefer smaller n to precision */
d4906093 786 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 787 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 788 for (clock.m1 = limit->m1.max;
789 clock.m1 >= limit->m1.min; clock.m1--) {
790 for (clock.m2 = limit->m2.max;
791 clock.m2 >= limit->m2.min; clock.m2--) {
792 for (clock.p1 = limit->p1.max;
793 clock.p1 >= limit->p1.min; clock.p1--) {
794 int this_err;
795
2177832f 796 intel_clock(dev, refclk, &clock);
1b894b59
CW		 797 if (!intel_PLL_is_valid(dev, limit,
798 &clock))
d4906093 799 continue;
cec2f356
SP		 800 if (match_clock &&
801 clock.p != match_clock->p)
802 continue;
1b894b59
CW		 803
804 this_err = abs(clock.dot - target);
d4906093
ML		 805 if (this_err < err_most) {
806 *best_clock = clock;
807 err_most = this_err;
808 max_n = clock.n;
809 found = true;
810 }
811 }
812 }
813 }
814 }
2c07245f
ZW		 815 return found;
816}
817
5eb08b69 818static bool
f2b115e6 819intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 820 int target, int refclk, intel_clock_t *match_clock,
821 intel_clock_t *best_clock)
5eb08b69
ZW		 822{
823 struct drm_device *dev = crtc->dev;
824 intel_clock_t clock;
4547668a 825
5eb08b69
ZW		 826 if (target < 200000) {
827 clock.n = 1;
828 clock.p1 = 2;
829 clock.p2 = 10;
830 clock.m1 = 12;
831 clock.m2 = 9;
832 } else {
833 clock.n = 2;
834 clock.p1 = 1;
835 clock.p2 = 10;
836 clock.m1 = 14;
837 clock.m2 = 8;
838 }
839 intel_clock(dev, refclk, &clock);
840 memcpy(best_clock, &clock, sizeof(intel_clock_t));
841 return true;
842}
843
a4fc5ed6
KP		 844/* DisplayPort has only two frequencies, 162MHz and 270MHz */
845static bool
846intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 847 int target, int refclk, intel_clock_t *match_clock,
848 intel_clock_t *best_clock)
a4fc5ed6 849{
5eddb70b
CW		 850 intel_clock_t clock;
851 if (target < 200000) {
852 clock.p1 = 2;
853 clock.p2 = 10;
854 clock.n = 2;
855 clock.m1 = 23;
856 clock.m2 = 8;
857 } else {
858 clock.p1 = 1;
859 clock.p2 = 10;
860 clock.n = 1;
861 clock.m1 = 14;
862 clock.m2 = 2;
863 }
864 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
865 clock.p = (clock.p1 * clock.p2);
866 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
867 clock.vco = 0;
868 memcpy(best_clock, &clock, sizeof(intel_clock_t));
869 return true;
a4fc5ed6 870}
a0c4da24
JB		 871static bool
872intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
873 int target, int refclk, intel_clock_t *match_clock,
874 intel_clock_t *best_clock)
875{
876 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
877 u32 m, n, fastclk;
878 u32 updrate, minupdate, fracbits, p;
879 unsigned long bestppm, ppm, absppm;
880 int dotclk, flag;
881
af447bd3 882 flag = 0;
a0c4da24
JB		 883 dotclk = target * 1000;
884 bestppm = 1000000;
885 ppm = absppm = 0;
886 fastclk = dotclk / (2*100);
887 updrate = 0;
888 minupdate = 19200;
889 fracbits = 1;
890 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
891 bestm1 = bestm2 = bestp1 = bestp2 = 0;
892
893 /* based on hardware requirement, prefer smaller n to precision */
894 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
895 updrate = refclk / n;
896 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
897 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
898 if (p2 > 10)
899 p2 = p2 - 1;
900 p = p1 * p2;
901 /* based on hardware requirement, prefer bigger m1,m2 values */
902 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
903 m2 = (((2*(fastclk * p * n / m1 )) +
904 refclk) / (2*refclk));
905 m = m1 * m2;
906 vco = updrate * m;
907 if (vco >= limit->vco.min && vco < limit->vco.max) {
908 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
909 absppm = (ppm > 0) ? ppm : (-ppm);
910 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
911 bestppm = 0;
912 flag = 1;
913 }
914 if (absppm < bestppm - 10) {
915 bestppm = absppm;
916 flag = 1;
917 }
918 if (flag) {
919 bestn = n;
920 bestm1 = m1;
921 bestm2 = m2;
922 bestp1 = p1;
923 bestp2 = p2;
924 flag = 0;
925 }
926 }
927 }
928 }
929 }
930 }
931 best_clock->n = bestn;
932 best_clock->m1 = bestm1;
933 best_clock->m2 = bestm2;
934 best_clock->p1 = bestp1;
935 best_clock->p2 = bestp2;
936
937 return true;
938}
a4fc5ed6 939
a5c961d1
PZ		 940enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
941 enum pipe pipe)
942{
943 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
944 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
945
946 return intel_crtc->cpu_transcoder;
947}
948
a928d536
PZ		 949static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
950{
951 struct drm_i915_private *dev_priv = dev->dev_private;
952 u32 frame, frame_reg = PIPEFRAME(pipe);
953
954 frame = I915_READ(frame_reg);
955
956 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
957 DRM_DEBUG_KMS("vblank wait timed out\n");
958}
959
9d0498a2
JB		 960/**
961 * intel_wait_for_vblank - wait for vblank on a given pipe
962 * @dev: drm device
963 * @pipe: pipe to wait for
964 *
965 * Wait for vblank to occur on a given pipe. Needed for various bits of
966 * mode setting code.
967 */
968void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 969{
9d0498a2 970 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 971 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 972
a928d536
PZ		 973 if (INTEL_INFO(dev)->gen >= 5) {
974 ironlake_wait_for_vblank(dev, pipe);
975 return;
976 }
977
300387c0
CW		 978 /* Clear existing vblank status. Note this will clear any other
979 * sticky status fields as well.
980 *
981 * This races with i915_driver_irq_handler() with the result
982 * that either function could miss a vblank event. Here it is not
983 * fatal, as we will either wait upon the next vblank interrupt or
984 * timeout. Generally speaking intel_wait_for_vblank() is only
985 * called during modeset at which time the GPU should be idle and
986 * should *not* be performing page flips and thus not waiting on
987 * vblanks...
988 * Currently, the result of us stealing a vblank from the irq
989 * handler is that a single frame will be skipped during swapbuffers.
990 */
991 I915_WRITE(pipestat_reg,
992 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
993
9d0498a2 994 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 995 if (wait_for(I915_READ(pipestat_reg) &
996 PIPE_VBLANK_INTERRUPT_STATUS,
997 50))
9d0498a2
JB		 998 DRM_DEBUG_KMS("vblank wait timed out\n");
999}
1000
ab7ad7f6
KP		 1001/*
1002 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 1003 * @dev: drm device
1004 * @pipe: pipe to wait for
1005 *
1006 * After disabling a pipe, we can't wait for vblank in the usual way,
1007 * spinning on the vblank interrupt status bit, since we won't actually
1008 * see an interrupt when the pipe is disabled.
1009 *
ab7ad7f6
KP		 1010 * On Gen4 and above:
1011 * wait for the pipe register state bit to turn off
1012 *
1013 * Otherwise:
1014 * wait for the display line value to settle (it usually
1015 * ends up stopping at the start of the next frame).
58e10eb9 1016 *
9d0498a2 1017 */
58e10eb9 1018void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 1019{
1020 struct drm_i915_private *dev_priv = dev->dev_private;
702e7a56
PZ		 1021 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1022 pipe);
ab7ad7f6
KP		 1023
1024 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 1025 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 1026
1027 /* Wait for the Pipe State to go off */
58e10eb9
CW		 1028 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1029 100))
284637d9 1030 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1031 } else {
837ba00f 1032 u32 last_line, line_mask;
58e10eb9 1033 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 1034 unsigned long timeout = jiffies + msecs_to_jiffies(100);
1035
837ba00f
PZ		 1036 if (IS_GEN2(dev))
1037 line_mask = DSL_LINEMASK_GEN2;
1038 else
1039 line_mask = DSL_LINEMASK_GEN3;
1040
ab7ad7f6
KP		 1041 /* Wait for the display line to settle */
1042 do {
837ba00f 1043 last_line = I915_READ(reg) & line_mask;
ab7ad7f6 1044 mdelay(5);
837ba00f 1045 } while (((I915_READ(reg) & line_mask) != last_line) &&
ab7ad7f6
KP		 1046 time_after(timeout, jiffies));
1047 if (time_after(jiffies, timeout))
284637d9 1048 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1049 }
79e53945
JB		 1050}
1051
b24e7179
JB		 1052static const char *state_string(bool enabled)
1053{
1054 return enabled ? "on" : "off";
1055}
1056
1057/* Only for pre-ILK configs */
1058static void assert_pll(struct drm_i915_private *dev_priv,
1059 enum pipe pipe, bool state)
1060{
1061 int reg;
1062 u32 val;
1063 bool cur_state;
1064
1065 reg = DPLL(pipe);
1066 val = I915_READ(reg);
1067 cur_state = !!(val & DPLL_VCO_ENABLE);
1068 WARN(cur_state != state,
1069 "PLL state assertion failure (expected %s, current %s)\n",
1070 state_string(state), state_string(cur_state));
1071}
1072#define assert_pll_enabled(d, p) assert_pll(d, p, true)
1073#define assert_pll_disabled(d, p) assert_pll(d, p, false)
1074
040484af
JB		 1075/* For ILK+ */
1076static void assert_pch_pll(struct drm_i915_private *dev_priv,
92b27b08
CW		 1077 struct intel_pch_pll *pll,
1078 struct intel_crtc *crtc,
1079 bool state)
040484af 1080{
040484af
JB		 1081 u32 val;
1082 bool cur_state;
1083
9d82aa17
ED		 1084 if (HAS_PCH_LPT(dev_priv->dev)) {
1085 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1086 return;
1087 }
1088
92b27b08
CW		 1089 if (WARN (!pll,
1090 "asserting PCH PLL %s with no PLL\n", state_string(state)))
ee7b9f93 1091 return;
ee7b9f93 1092
92b27b08
CW		 1093 val = I915_READ(pll->pll_reg);
1094 cur_state = !!(val & DPLL_VCO_ENABLE);
1095 WARN(cur_state != state,
1096 "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1097 pll->pll_reg, state_string(state), state_string(cur_state), val);
1098
1099 /* Make sure the selected PLL is correctly attached to the transcoder */
1100 if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
d3ccbe86
JB		 1101 u32 pch_dpll;
1102
1103 pch_dpll = I915_READ(PCH_DPLL_SEL);
92b27b08
CW		 1104 cur_state = pll->pll_reg == _PCH_DPLL_B;
1105 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
1106 "PLL[%d] not attached to this transcoder %d: %08x\n",
1107 cur_state, crtc->pipe, pch_dpll)) {
1108 cur_state = !!(val >> (4*crtc->pipe + 3));
1109 WARN(cur_state != state,
1110 "PLL[%d] not %s on this transcoder %d: %08x\n",
1111 pll->pll_reg == _PCH_DPLL_B,
1112 state_string(state),
1113 crtc->pipe,
1114 val);
1115 }
d3ccbe86 1116 }
040484af 1117}
92b27b08
CW		 1118#define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1119#define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
040484af
JB		 1120
1121static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1122 enum pipe pipe, bool state)
1123{
1124 int reg;
1125 u32 val;
1126 bool cur_state;
ad80a810
PZ		 1127 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1128 pipe);
040484af 1129
bf507ef7
ED		 1130 if (IS_HASWELL(dev_priv->dev)) {
1131 /* On Haswell, DDI is used instead of FDI_TX_CTL */
ad80a810 1132 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 1133 val = I915_READ(reg);
ad80a810 1134 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 1135 } else {
1136 reg = FDI_TX_CTL(pipe);
1137 val = I915_READ(reg);
1138 cur_state = !!(val & FDI_TX_ENABLE);
1139 }
040484af
JB		 1140 WARN(cur_state != state,
1141 "FDI TX state assertion failure (expected %s, current %s)\n",
1142 state_string(state), state_string(cur_state));
1143}
1144#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1145#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1146
1147static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1148 enum pipe pipe, bool state)
1149{
1150 int reg;
1151 u32 val;
1152 bool cur_state;
1153
59c859d6
ED		 1154 if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1155 DRM_ERROR("Attempting to enable FDI_RX on Haswell pipe > 0\n");
1156 return;
1157 } else {
1158 reg = FDI_RX_CTL(pipe);
1159 val = I915_READ(reg);
1160 cur_state = !!(val & FDI_RX_ENABLE);
1161 }
040484af
JB		 1162 WARN(cur_state != state,
1163 "FDI RX state assertion failure (expected %s, current %s)\n",
1164 state_string(state), state_string(cur_state));
1165}
1166#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1167#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1168
1169static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1170 enum pipe pipe)
1171{
1172 int reg;
1173 u32 val;
1174
1175 /* ILK FDI PLL is always enabled */
1176 if (dev_priv->info->gen == 5)
1177 return;
1178
bf507ef7
ED		 1179 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1180 if (IS_HASWELL(dev_priv->dev))
1181 return;
1182
040484af
JB		 1183 reg = FDI_TX_CTL(pipe);
1184 val = I915_READ(reg);
1185 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1186}
1187
1188static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1189 enum pipe pipe)
1190{
1191 int reg;
1192 u32 val;
1193
59c859d6
ED		 1194 if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1195 DRM_ERROR("Attempting to enable FDI on Haswell with pipe > 0\n");
1196 return;
1197 }
040484af
JB		 1198 reg = FDI_RX_CTL(pipe);
1199 val = I915_READ(reg);
1200 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1201}
1202
ea0760cf
JB		 1203static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1204 enum pipe pipe)
1205{
1206 int pp_reg, lvds_reg;
1207 u32 val;
1208 enum pipe panel_pipe = PIPE_A;
0de3b485 1209 bool locked = true;
ea0760cf
JB		 1210
1211 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1212 pp_reg = PCH_PP_CONTROL;
1213 lvds_reg = PCH_LVDS;
1214 } else {
1215 pp_reg = PP_CONTROL;
1216 lvds_reg = LVDS;
1217 }
1218
1219 val = I915_READ(pp_reg);
1220 if (!(val & PANEL_POWER_ON) ||
1221 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1222 locked = false;
1223
1224 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1225 panel_pipe = PIPE_B;
1226
1227 WARN(panel_pipe == pipe && locked,
1228 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1229 pipe_name(pipe));
ea0760cf
JB		 1230}
1231
b840d907
JB		 1232void assert_pipe(struct drm_i915_private *dev_priv,
1233 enum pipe pipe, bool state)
b24e7179
JB		 1234{
1235 int reg;
1236 u32 val;
63d7bbe9 1237 bool cur_state;
702e7a56
PZ		 1238 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1239 pipe);
b24e7179 1240
8e636784
DV		 1241 /* if we need the pipe A quirk it must be always on */
1242 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1243 state = true;
1244
702e7a56 1245 reg = PIPECONF(cpu_transcoder);
b24e7179 1246 val = I915_READ(reg);
63d7bbe9
JB		 1247 cur_state = !!(val & PIPECONF_ENABLE);
1248 WARN(cur_state != state,
1249 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1250 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1251}
1252
931872fc
CW		 1253static void assert_plane(struct drm_i915_private *dev_priv,
1254 enum plane plane, bool state)
b24e7179
JB		 1255{
1256 int reg;
1257 u32 val;
931872fc 1258 bool cur_state;
b24e7179
JB		 1259
1260 reg = DSPCNTR(plane);
1261 val = I915_READ(reg);
931872fc
CW		 1262 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1263 WARN(cur_state != state,
1264 "plane %c assertion failure (expected %s, current %s)\n",
1265 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1266}
1267
931872fc
CW		 1268#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1269#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1270
b24e7179
JB		 1271static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1272 enum pipe pipe)
1273{
1274 int reg, i;
1275 u32 val;
1276 int cur_pipe;
1277
19ec1358 1278 /* Planes are fixed to pipes on ILK+ */
28c05794
AJ		 1279 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1280 reg = DSPCNTR(pipe);
1281 val = I915_READ(reg);
1282 WARN((val & DISPLAY_PLANE_ENABLE),
1283 "plane %c assertion failure, should be disabled but not\n",
1284 plane_name(pipe));
19ec1358 1285 return;
28c05794 1286 }
19ec1358 1287
b24e7179
JB		 1288 /* Need to check both planes against the pipe */
1289 for (i = 0; i < 2; i++) {
1290 reg = DSPCNTR(i);
1291 val = I915_READ(reg);
1292 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1293 DISPPLANE_SEL_PIPE_SHIFT;
1294 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1295 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1296 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1297 }
1298}
1299
92f2584a
JB		 1300static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1301{
1302 u32 val;
1303 bool enabled;
1304
9d82aa17
ED		 1305 if (HAS_PCH_LPT(dev_priv->dev)) {
1306 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1307 return;
1308 }
1309
92f2584a
JB		 1310 val = I915_READ(PCH_DREF_CONTROL);
1311 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1312 DREF_SUPERSPREAD_SOURCE_MASK));
1313 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1314}
1315
1316static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1317 enum pipe pipe)
1318{
1319 int reg;
1320 u32 val;
1321 bool enabled;
1322
1323 reg = TRANSCONF(pipe);
1324 val = I915_READ(reg);
1325 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 1326 WARN(enabled,
1327 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1328 pipe_name(pipe));
92f2584a
JB		 1329}
1330
4e634389
KP		 1331static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1332 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1333{
1334 if ((val & DP_PORT_EN) == 0)
1335 return false;
1336
1337 if (HAS_PCH_CPT(dev_priv->dev)) {
1338 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1339 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1340 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1341 return false;
1342 } else {
1343 if ((val & DP_PIPE_MASK) != (pipe << 30))
1344 return false;
1345 }
1346 return true;
1347}
1348
1519b995
KP		 1349static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1350 enum pipe pipe, u32 val)
1351{
1352 if ((val & PORT_ENABLE) == 0)
1353 return false;
1354
1355 if (HAS_PCH_CPT(dev_priv->dev)) {
1356 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1357 return false;
1358 } else {
1359 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1360 return false;
1361 }
1362 return true;
1363}
1364
1365static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1366 enum pipe pipe, u32 val)
1367{
1368 if ((val & LVDS_PORT_EN) == 0)
1369 return false;
1370
1371 if (HAS_PCH_CPT(dev_priv->dev)) {
1372 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1373 return false;
1374 } else {
1375 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1376 return false;
1377 }
1378 return true;
1379}
1380
1381static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1382 enum pipe pipe, u32 val)
1383{
1384 if ((val & ADPA_DAC_ENABLE) == 0)
1385 return false;
1386 if (HAS_PCH_CPT(dev_priv->dev)) {
1387 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1388 return false;
1389 } else {
1390 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1391 return false;
1392 }
1393 return true;
1394}
1395
291906f1 1396static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1397 enum pipe pipe, int reg, u32 port_sel)
291906f1 1398{
47a05eca 1399 u32 val = I915_READ(reg);
4e634389 1400 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1401 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1402 reg, pipe_name(pipe));
de9a35ab 1403
75c5da27
DV		 1404 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1405 && (val & DP_PIPEB_SELECT),
de9a35ab 1406 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1407}
1408
1409static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1410 enum pipe pipe, int reg)
1411{
47a05eca 1412 u32 val = I915_READ(reg);
e9a851ed 1413 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1414 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1415 reg, pipe_name(pipe));
de9a35ab 1416
75c5da27
DV		 1417 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & PORT_ENABLE) == 0
1418 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1419 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1420}
1421
1422static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1423 enum pipe pipe)
1424{
1425 int reg;
1426 u32 val;
291906f1 1427
f0575e92
KP		 1428 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1429 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1430 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1431
1432 reg = PCH_ADPA;
1433 val = I915_READ(reg);
e9a851ed 1434 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1435 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1436 pipe_name(pipe));
291906f1
JB		 1437
1438 reg = PCH_LVDS;
1439 val = I915_READ(reg);
e9a851ed 1440 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1441 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1442 pipe_name(pipe));
291906f1
JB		 1443
1444 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1445 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1446 assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1447}
1448
63d7bbe9
JB		 1449/**
1450 * intel_enable_pll - enable a PLL
1451 * @dev_priv: i915 private structure
1452 * @pipe: pipe PLL to enable
1453 *
1454 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1455 * make sure the PLL reg is writable first though, since the panel write
1456 * protect mechanism may be enabled.
1457 *
1458 * Note! This is for pre-ILK only.
7434a255
TR		 1459 *
1460 * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
63d7bbe9 1461 */
a37b9b34 1462static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
63d7bbe9
JB		 1463{
1464 int reg;
1465 u32 val;
1466
1467 /* No really, not for ILK+ */
a0c4da24 1468 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
63d7bbe9
JB		 1469
1470 /* PLL is protected by panel, make sure we can write it */
1471 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1472 assert_panel_unlocked(dev_priv, pipe);
1473
1474 reg = DPLL(pipe);
1475 val = I915_READ(reg);
1476 val |= DPLL_VCO_ENABLE;
1477
1478 /* We do this three times for luck */
1479 I915_WRITE(reg, val);
1480 POSTING_READ(reg);
1481 udelay(150); /* wait for warmup */
1482 I915_WRITE(reg, val);
1483 POSTING_READ(reg);
1484 udelay(150); /* wait for warmup */
1485 I915_WRITE(reg, val);
1486 POSTING_READ(reg);
1487 udelay(150); /* wait for warmup */
1488}
1489
1490/**
1491 * intel_disable_pll - disable a PLL
1492 * @dev_priv: i915 private structure
1493 * @pipe: pipe PLL to disable
1494 *
1495 * Disable the PLL for @pipe, making sure the pipe is off first.
1496 *
1497 * Note! This is for pre-ILK only.
1498 */
1499static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1500{
1501 int reg;
1502 u32 val;
1503
1504 /* Don't disable pipe A or pipe A PLLs if needed */
1505 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1506 return;
1507
1508 /* Make sure the pipe isn't still relying on us */
1509 assert_pipe_disabled(dev_priv, pipe);
1510
1511 reg = DPLL(pipe);
1512 val = I915_READ(reg);
1513 val &= ~DPLL_VCO_ENABLE;
1514 I915_WRITE(reg, val);
1515 POSTING_READ(reg);
1516}
1517
a416edef
ED		 1518/* SBI access */
1519static void
1520intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value)
1521{
1522 unsigned long flags;
1523
1524 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
39fb50f6 1525 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
a416edef
ED		 1526 100)) {
1527 DRM_ERROR("timeout waiting for SBI to become ready\n");
1528 goto out_unlock;
1529 }
1530
1531 I915_WRITE(SBI_ADDR,
1532 (reg << 16));
1533 I915_WRITE(SBI_DATA,
1534 value);
1535 I915_WRITE(SBI_CTL_STAT,
1536 SBI_BUSY |
1537 SBI_CTL_OP_CRWR);
1538
39fb50f6 1539 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
a416edef
ED		 1540 100)) {
1541 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1542 goto out_unlock;
1543 }
1544
1545out_unlock:
1546 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1547}
1548
1549static u32
1550intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg)
1551{
1552 unsigned long flags;
39fb50f6 1553 u32 value = 0;
a416edef
ED		 1554
1555 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
39fb50f6 1556 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
a416edef
ED		 1557 100)) {
1558 DRM_ERROR("timeout waiting for SBI to become ready\n");
1559 goto out_unlock;
1560 }
1561
1562 I915_WRITE(SBI_ADDR,
1563 (reg << 16));
1564 I915_WRITE(SBI_CTL_STAT,
1565 SBI_BUSY |
1566 SBI_CTL_OP_CRRD);
1567
39fb50f6 1568 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
a416edef
ED		 1569 100)) {
1570 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1571 goto out_unlock;
1572 }
1573
1574 value = I915_READ(SBI_DATA);
1575
1576out_unlock:
1577 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1578 return value;
1579}
1580
92f2584a 1581/**
b6b4e185 1582 * ironlake_enable_pch_pll - enable PCH PLL
92f2584a
JB		 1583 * @dev_priv: i915 private structure
1584 * @pipe: pipe PLL to enable
1585 *
1586 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1587 * drives the transcoder clock.
1588 */
b6b4e185 1589static void ironlake_enable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1590{
ee7b9f93 1591 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
48da64a8 1592 struct intel_pch_pll *pll;
92f2584a
JB		 1593 int reg;
1594 u32 val;
1595
48da64a8 1596 /* PCH PLLs only available on ILK, SNB and IVB */
92f2584a 1597 BUG_ON(dev_priv->info->gen < 5);
48da64a8
CW		 1598 pll = intel_crtc->pch_pll;
1599 if (pll == NULL)
1600 return;
1601
1602 if (WARN_ON(pll->refcount == 0))
1603 return;
ee7b9f93
JB		 1604
1605 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1606 pll->pll_reg, pll->active, pll->on,
1607 intel_crtc->base.base.id);
92f2584a
JB		 1608
1609 /* PCH refclock must be enabled first */
1610 assert_pch_refclk_enabled(dev_priv);
1611
ee7b9f93 1612 if (pll->active++ && pll->on) {
92b27b08 1613 assert_pch_pll_enabled(dev_priv, pll, NULL);
ee7b9f93
JB		 1614 return;
1615 }
1616
1617 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1618
1619 reg = pll->pll_reg;
92f2584a
JB		 1620 val = I915_READ(reg);
1621 val |= DPLL_VCO_ENABLE;
1622 I915_WRITE(reg, val);
1623 POSTING_READ(reg);
1624 udelay(200);
ee7b9f93
JB		 1625
1626 pll->on = true;
92f2584a
JB		 1627}
1628
ee7b9f93 1629static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1630{
ee7b9f93
JB		 1631 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1632 struct intel_pch_pll *pll = intel_crtc->pch_pll;
92f2584a 1633 int reg;
ee7b9f93 1634 u32 val;
4c609cb8 1635
92f2584a
JB		 1636 /* PCH only available on ILK+ */
1637 BUG_ON(dev_priv->info->gen < 5);
ee7b9f93
JB		 1638 if (pll == NULL)
1639 return;
92f2584a 1640
48da64a8
CW		 1641 if (WARN_ON(pll->refcount == 0))
1642 return;
7a419866 1643
ee7b9f93
JB		 1644 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1645 pll->pll_reg, pll->active, pll->on,
1646 intel_crtc->base.base.id);
7a419866 1647
48da64a8 1648 if (WARN_ON(pll->active == 0)) {
92b27b08 1649 assert_pch_pll_disabled(dev_priv, pll, NULL);
48da64a8
CW		 1650 return;
1651 }
1652
ee7b9f93 1653 if (--pll->active) {
92b27b08 1654 assert_pch_pll_enabled(dev_priv, pll, NULL);
7a419866 1655 return;
ee7b9f93
JB		 1656 }
1657
1658 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1659
1660 /* Make sure transcoder isn't still depending on us */
1661 assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
7a419866 1662
ee7b9f93 1663 reg = pll->pll_reg;
92f2584a
JB		 1664 val = I915_READ(reg);
1665 val &= ~DPLL_VCO_ENABLE;
1666 I915_WRITE(reg, val);
1667 POSTING_READ(reg);
1668 udelay(200);
ee7b9f93
JB		 1669
1670 pll->on = false;
92f2584a
JB		 1671}
1672
b8a4f404
PZ		 1673static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1674 enum pipe pipe)
040484af
JB		 1675{
1676 int reg;
5f7f726d 1677 u32 val, pipeconf_val;
7c26e5c6 1678 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
040484af
JB		 1679
1680 /* PCH only available on ILK+ */
1681 BUG_ON(dev_priv->info->gen < 5);
1682
1683 /* Make sure PCH DPLL is enabled */
92b27b08
CW		 1684 assert_pch_pll_enabled(dev_priv,
1685 to_intel_crtc(crtc)->pch_pll,
1686 to_intel_crtc(crtc));
040484af
JB		 1687
1688 /* FDI must be feeding us bits for PCH ports */
1689 assert_fdi_tx_enabled(dev_priv, pipe);
1690 assert_fdi_rx_enabled(dev_priv, pipe);
1691
1692 reg = TRANSCONF(pipe);
1693 val = I915_READ(reg);
5f7f726d 1694 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1695
1696 if (HAS_PCH_IBX(dev_priv->dev)) {
1697 /*
1698 * make the BPC in transcoder be consistent with
1699 * that in pipeconf reg.
1700 */
1701 val &= ~PIPE_BPC_MASK;
5f7f726d 1702 val |= pipeconf_val & PIPE_BPC_MASK;
e9bcff5c 1703 }
5f7f726d
PZ		 1704
1705 val &= ~TRANS_INTERLACE_MASK;
1706 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6
PZ		 1707 if (HAS_PCH_IBX(dev_priv->dev) &&
1708 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1709 val |= TRANS_LEGACY_INTERLACED_ILK;
1710 else
1711 val |= TRANS_INTERLACED;
5f7f726d
PZ		 1712 else
1713 val |= TRANS_PROGRESSIVE;
1714
040484af
JB		 1715 I915_WRITE(reg, val | TRANS_ENABLE);
1716 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1717 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1718}
1719
8fb033d7
PZ		 1720static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1721 enum pipe pipe)
1722{
1723 int reg;
1724 u32 val, pipeconf_val;
1725 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1726
1727 /* PCH only available on ILK+ */
1728 BUG_ON(dev_priv->info->gen < 5);
1729
1730 /* Make sure PCH DPLL is enabled */
1731 assert_pch_pll_enabled(dev_priv,
1732 to_intel_crtc(crtc)->pch_pll,
1733 to_intel_crtc(crtc));
1734
1735 /* FDI must be feeding us bits for PCH ports */
1736 assert_fdi_tx_enabled(dev_priv, pipe);
1737 assert_fdi_rx_enabled(dev_priv, pipe);
1738
1739 if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1740 DRM_ERROR("Attempting to enable transcoder on Haswell with pipe > 0\n");
1741 return;
1742 }
1743 reg = TRANSCONF(pipe);
1744 val = I915_READ(reg);
1745 pipeconf_val = I915_READ(PIPECONF(pipe));
1746
1747 if (HAS_PCH_IBX(dev_priv->dev)) {
1748 /*
1749 * make the BPC in transcoder be consistent with
1750 * that in pipeconf reg.
1751 */
1752 val &= ~PIPE_BPC_MASK;
1753 val |= pipeconf_val & PIPE_BPC_MASK;
1754 }
1755
1756 val &= ~TRANS_INTERLACE_MASK;
1757 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1758 if (HAS_PCH_IBX(dev_priv->dev) &&
1759 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1760 val |= TRANS_LEGACY_INTERLACED_ILK;
1761 else
1762 val |= TRANS_INTERLACED;
1763 else
1764 val |= TRANS_PROGRESSIVE;
1765
1766 I915_WRITE(reg, val | TRANS_ENABLE);
1767 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1768 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1769}
1770
b8a4f404
PZ		 1771static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1772 enum pipe pipe)
040484af
JB		 1773{
1774 int reg;
1775 u32 val;
1776
1777 /* FDI relies on the transcoder */
1778 assert_fdi_tx_disabled(dev_priv, pipe);
1779 assert_fdi_rx_disabled(dev_priv, pipe);
1780
291906f1
JB		 1781 /* Ports must be off as well */
1782 assert_pch_ports_disabled(dev_priv, pipe);
1783
040484af
JB		 1784 reg = TRANSCONF(pipe);
1785 val = I915_READ(reg);
1786 val &= ~TRANS_ENABLE;
1787 I915_WRITE(reg, val);
1788 /* wait for PCH transcoder off, transcoder state */
1789 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4c9c18c2 1790 DRM_ERROR("failed to disable transcoder %d\n", pipe);
040484af
JB		 1791}
1792
8fb033d7
PZ		 1793static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1794 enum pipe pipe)
1795{
1796 int reg;
1797 u32 val;
1798
1799 /* FDI relies on the transcoder */
1800 assert_fdi_tx_disabled(dev_priv, pipe);
1801 assert_fdi_rx_disabled(dev_priv, pipe);
1802
1803 /* Ports must be off as well */
1804 assert_pch_ports_disabled(dev_priv, pipe);
1805
1806 reg = TRANSCONF(pipe);
1807 val = I915_READ(reg);
1808 val &= ~TRANS_ENABLE;
1809 I915_WRITE(reg, val);
1810 /* wait for PCH transcoder off, transcoder state */
1811 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1812 DRM_ERROR("failed to disable transcoder %d\n", pipe);
1813}
1814
b24e7179 1815/**
309cfea8 1816 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1817 * @dev_priv: i915 private structure
1818 * @pipe: pipe to enable
040484af 1819 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1820 *
1821 * Enable @pipe, making sure that various hardware specific requirements
1822 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1823 *
1824 * @pipe should be %PIPE_A or %PIPE_B.
1825 *
1826 * Will wait until the pipe is actually running (i.e. first vblank) before
1827 * returning.
1828 */
040484af
JB		 1829static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1830 bool pch_port)
b24e7179 1831{
702e7a56
PZ		 1832 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1833 pipe);
b24e7179
JB		 1834 int reg;
1835 u32 val;
1836
1837 /*
1838 * A pipe without a PLL won't actually be able to drive bits from
1839 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1840 * need the check.
1841 */
1842 if (!HAS_PCH_SPLIT(dev_priv->dev))
1843 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1844 else {
1845 if (pch_port) {
1846 /* if driving the PCH, we need FDI enabled */
1847 assert_fdi_rx_pll_enabled(dev_priv, pipe);
1848 assert_fdi_tx_pll_enabled(dev_priv, pipe);
1849 }
1850 /* FIXME: assert CPU port conditions for SNB+ */
1851 }
b24e7179 1852
702e7a56 1853 reg = PIPECONF(cpu_transcoder);
b24e7179 1854 val = I915_READ(reg);
00d70b15
CW		 1855 if (val & PIPECONF_ENABLE)
1856 return;
1857
1858 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1859 intel_wait_for_vblank(dev_priv->dev, pipe);
1860}
1861
1862/**
309cfea8 1863 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1864 * @dev_priv: i915 private structure
1865 * @pipe: pipe to disable
1866 *
1867 * Disable @pipe, making sure that various hardware specific requirements
1868 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1869 *
1870 * @pipe should be %PIPE_A or %PIPE_B.
1871 *
1872 * Will wait until the pipe has shut down before returning.
1873 */
1874static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1875 enum pipe pipe)
1876{
702e7a56
PZ		 1877 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1878 pipe);
b24e7179
JB		 1879 int reg;
1880 u32 val;
1881
1882 /*
1883 * Make sure planes won't keep trying to pump pixels to us,
1884 * or we might hang the display.
1885 */
1886 assert_planes_disabled(dev_priv, pipe);
1887
1888 /* Don't disable pipe A or pipe A PLLs if needed */
1889 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1890 return;
1891
702e7a56 1892 reg = PIPECONF(cpu_transcoder);
b24e7179 1893 val = I915_READ(reg);
00d70b15
CW		 1894 if ((val & PIPECONF_ENABLE) == 0)
1895 return;
1896
1897 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1898 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1899}
1900
d74362c9
KP		 1901/*
1902 * Plane regs are double buffered, going from enabled->disabled needs a
1903 * trigger in order to latch. The display address reg provides this.
1904 */
6f1d69b0 1905void intel_flush_display_plane(struct drm_i915_private *dev_priv,
d74362c9
KP		 1906 enum plane plane)
1907{
14f86147
DL		 1908 if (dev_priv->info->gen >= 4)
1909 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1910 else
1911 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
d74362c9
KP		 1912}
1913
b24e7179
JB		 1914/**
1915 * intel_enable_plane - enable a display plane on a given pipe
1916 * @dev_priv: i915 private structure
1917 * @plane: plane to enable
1918 * @pipe: pipe being fed
1919 *
1920 * Enable @plane on @pipe, making sure that @pipe is running first.
1921 */
1922static void intel_enable_plane(struct drm_i915_private *dev_priv,
1923 enum plane plane, enum pipe pipe)
1924{
1925 int reg;
1926 u32 val;
1927
1928 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1929 assert_pipe_enabled(dev_priv, pipe);
1930
1931 reg = DSPCNTR(plane);
1932 val = I915_READ(reg);
00d70b15
CW		 1933 if (val & DISPLAY_PLANE_ENABLE)
1934 return;
1935
1936 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
d74362c9 1937 intel_flush_display_plane(dev_priv, plane);
b24e7179
JB		 1938 intel_wait_for_vblank(dev_priv->dev, pipe);
1939}
1940
b24e7179
JB		 1941/**
1942 * intel_disable_plane - disable a display plane
1943 * @dev_priv: i915 private structure
1944 * @plane: plane to disable
1945 * @pipe: pipe consuming the data
1946 *
1947 * Disable @plane; should be an independent operation.
1948 */
1949static void intel_disable_plane(struct drm_i915_private *dev_priv,
1950 enum plane plane, enum pipe pipe)
1951{
1952 int reg;
1953 u32 val;
1954
1955 reg = DSPCNTR(plane);
1956 val = I915_READ(reg);
00d70b15
CW		 1957 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1958 return;
1959
1960 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1961 intel_flush_display_plane(dev_priv, plane);
1962 intel_wait_for_vblank(dev_priv->dev, pipe);
1963}
1964
127bd2ac 1965int
48b956c5 1966intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1967 struct drm_i915_gem_object *obj,
919926ae 1968 struct intel_ring_buffer *pipelined)
6b95a207 1969{
ce453d81 1970 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 1971 u32 alignment;
1972 int ret;
1973
05394f39 1974 switch (obj->tiling_mode) {
6b95a207 1975 case I915_TILING_NONE:
534843da
CW		 1976 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1977 alignment = 128 * 1024;
a6c45cf0 1978 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 1979 alignment = 4 * 1024;
1980 else
1981 alignment = 64 * 1024;
6b95a207
KH		 1982 break;
1983 case I915_TILING_X:
1984 /* pin() will align the object as required by fence */
1985 alignment = 0;
1986 break;
1987 case I915_TILING_Y:
1988 /* FIXME: Is this true? */
1989 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1990 return -EINVAL;
1991 default:
1992 BUG();
1993 }
1994
ce453d81 1995 dev_priv->mm.interruptible = false;
2da3b9b9 1996 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 1997 if (ret)
ce453d81 1998 goto err_interruptible;
6b95a207
KH		 1999
2000 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2001 * fence, whereas 965+ only requires a fence if using
2002 * framebuffer compression. For simplicity, we always install
2003 * a fence as the cost is not that onerous.
2004 */
06d98131 2005 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 2006 if (ret)
2007 goto err_unpin;
1690e1eb 2008
9a5a53b3 2009 i915_gem_object_pin_fence(obj);
6b95a207 2010
ce453d81 2011 dev_priv->mm.interruptible = true;
6b95a207 2012 return 0;
48b956c5
CW		 2013
2014err_unpin:
2015 i915_gem_object_unpin(obj);
ce453d81
CW		 2016err_interruptible:
2017 dev_priv->mm.interruptible = true;
48b956c5 2018 return ret;
6b95a207
KH		 2019}
2020
1690e1eb
CW		 2021void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2022{
2023 i915_gem_object_unpin_fence(obj);
2024 i915_gem_object_unpin(obj);
2025}
2026
c2c75131
DV		 2027/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2028 * is assumed to be a power-of-two. */
5a35e99e
DL		 2029unsigned long intel_gen4_compute_offset_xtiled(int *x, int *y,
2030 unsigned int bpp,
2031 unsigned int pitch)
c2c75131
DV		 2032{
2033 int tile_rows, tiles;
2034
2035 tile_rows = *y / 8;
2036 *y %= 8;
2037 tiles = *x / (512/bpp);
2038 *x %= 512/bpp;
2039
2040 return tile_rows * pitch * 8 + tiles * 4096;
2041}
2042
17638cd6
JB		 2043static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2044 int x, int y)
81255565
JB		 2045{
2046 struct drm_device *dev = crtc->dev;
2047 struct drm_i915_private *dev_priv = dev->dev_private;
2048 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2049 struct intel_framebuffer *intel_fb;
05394f39 2050 struct drm_i915_gem_object *obj;
81255565 2051 int plane = intel_crtc->plane;
e506a0c6 2052 unsigned long linear_offset;
81255565 2053 u32 dspcntr;
5eddb70b 2054 u32 reg;
81255565
JB		 2055
2056 switch (plane) {
2057 case 0:
2058 case 1:
2059 break;
2060 default:
2061 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2062 return -EINVAL;
2063 }
2064
2065 intel_fb = to_intel_framebuffer(fb);
2066 obj = intel_fb->obj;
81255565 2067
5eddb70b
CW		 2068 reg = DSPCNTR(plane);
2069 dspcntr = I915_READ(reg);
81255565
JB		 2070 /* Mask out pixel format bits in case we change it */
2071 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2072 switch (fb->pixel_format) {
2073 case DRM_FORMAT_C8:
81255565
JB		 2074 dspcntr |= DISPPLANE_8BPP;
2075 break;
57779d06
VS		 2076 case DRM_FORMAT_XRGB1555:
2077 case DRM_FORMAT_ARGB1555:
2078 dspcntr |= DISPPLANE_BGRX555;
81255565 2079 break;
57779d06
VS		 2080 case DRM_FORMAT_RGB565:
2081 dspcntr |= DISPPLANE_BGRX565;
2082 break;
2083 case DRM_FORMAT_XRGB8888:
2084 case DRM_FORMAT_ARGB8888:
2085 dspcntr |= DISPPLANE_BGRX888;
2086 break;
2087 case DRM_FORMAT_XBGR8888:
2088 case DRM_FORMAT_ABGR8888:
2089 dspcntr |= DISPPLANE_RGBX888;
2090 break;
2091 case DRM_FORMAT_XRGB2101010:
2092 case DRM_FORMAT_ARGB2101010:
2093 dspcntr |= DISPPLANE_BGRX101010;
2094 break;
2095 case DRM_FORMAT_XBGR2101010:
2096 case DRM_FORMAT_ABGR2101010:
2097 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 2098 break;
2099 default:
57779d06 2100 DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format);
81255565
JB		 2101 return -EINVAL;
2102 }
57779d06 2103
a6c45cf0 2104 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 2105 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 2106 dspcntr |= DISPPLANE_TILED;
2107 else
2108 dspcntr &= ~DISPPLANE_TILED;
2109 }
2110
5eddb70b 2111 I915_WRITE(reg, dspcntr);
81255565 2112
e506a0c6 2113 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
81255565 2114
c2c75131
DV		 2115 if (INTEL_INFO(dev)->gen >= 4) {
2116 intel_crtc->dspaddr_offset =
5a35e99e
DL		 2117 intel_gen4_compute_offset_xtiled(&x, &y,
2118 fb->bits_per_pixel / 8,
2119 fb->pitches[0]);
c2c75131
DV		 2120 linear_offset -= intel_crtc->dspaddr_offset;
2121 } else {
e506a0c6 2122 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2123 }
e506a0c6
DV		 2124
2125 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2126 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2127 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2128 if (INTEL_INFO(dev)->gen >= 4) {
c2c75131
DV		 2129 I915_MODIFY_DISPBASE(DSPSURF(plane),
2130 obj->gtt_offset + intel_crtc->dspaddr_offset);
5eddb70b 2131 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2132 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2133 } else
e506a0c6 2134 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
5eddb70b 2135 POSTING_READ(reg);
81255565 2136
17638cd6
JB		 2137 return 0;
2138}
2139
2140static int ironlake_update_plane(struct drm_crtc *crtc,
2141 struct drm_framebuffer *fb, int x, int y)
2142{
2143 struct drm_device *dev = crtc->dev;
2144 struct drm_i915_private *dev_priv = dev->dev_private;
2145 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2146 struct intel_framebuffer *intel_fb;
2147 struct drm_i915_gem_object *obj;
2148 int plane = intel_crtc->plane;
e506a0c6 2149 unsigned long linear_offset;
17638cd6
JB		 2150 u32 dspcntr;
2151 u32 reg;
2152
2153 switch (plane) {
2154 case 0:
2155 case 1:
27f8227b 2156 case 2:
17638cd6
JB		 2157 break;
2158 default:
2159 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2160 return -EINVAL;
2161 }
2162
2163 intel_fb = to_intel_framebuffer(fb);
2164 obj = intel_fb->obj;
2165
2166 reg = DSPCNTR(plane);
2167 dspcntr = I915_READ(reg);
2168 /* Mask out pixel format bits in case we change it */
2169 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2170 switch (fb->pixel_format) {
2171 case DRM_FORMAT_C8:
17638cd6
JB		 2172 dspcntr |= DISPPLANE_8BPP;
2173 break;
57779d06
VS		 2174 case DRM_FORMAT_RGB565:
2175 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2176 break;
57779d06
VS		 2177 case DRM_FORMAT_XRGB8888:
2178 case DRM_FORMAT_ARGB8888:
2179 dspcntr |= DISPPLANE_BGRX888;
2180 break;
2181 case DRM_FORMAT_XBGR8888:
2182 case DRM_FORMAT_ABGR8888:
2183 dspcntr |= DISPPLANE_RGBX888;
2184 break;
2185 case DRM_FORMAT_XRGB2101010:
2186 case DRM_FORMAT_ARGB2101010:
2187 dspcntr |= DISPPLANE_BGRX101010;
2188 break;
2189 case DRM_FORMAT_XBGR2101010:
2190 case DRM_FORMAT_ABGR2101010:
2191 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2192 break;
2193 default:
57779d06 2194 DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format);
17638cd6
JB		 2195 return -EINVAL;
2196 }
2197
2198 if (obj->tiling_mode != I915_TILING_NONE)
2199 dspcntr |= DISPPLANE_TILED;
2200 else
2201 dspcntr &= ~DISPPLANE_TILED;
2202
2203 /* must disable */
2204 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2205
2206 I915_WRITE(reg, dspcntr);
2207
e506a0c6 2208 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
c2c75131 2209 intel_crtc->dspaddr_offset =
5a35e99e
DL		 2210 intel_gen4_compute_offset_xtiled(&x, &y,
2211 fb->bits_per_pixel / 8,
2212 fb->pitches[0]);
c2c75131 2213 linear_offset -= intel_crtc->dspaddr_offset;
17638cd6 2214
e506a0c6
DV		 2215 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2216 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2217 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
c2c75131
DV		 2218 I915_MODIFY_DISPBASE(DSPSURF(plane),
2219 obj->gtt_offset + intel_crtc->dspaddr_offset);
bc1c91eb
DL		 2220 if (IS_HASWELL(dev)) {
2221 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2222 } else {
2223 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2224 I915_WRITE(DSPLINOFF(plane), linear_offset);
2225 }
17638cd6
JB		 2226 POSTING_READ(reg);
2227
2228 return 0;
2229}
2230
2231/* Assume fb object is pinned & idle & fenced and just update base pointers */
2232static int
2233intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2234 int x, int y, enum mode_set_atomic state)
2235{
2236 struct drm_device *dev = crtc->dev;
2237 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 2238
6b8e6ed0
CW		 2239 if (dev_priv->display.disable_fbc)
2240 dev_priv->display.disable_fbc(dev);
3dec0095 2241 intel_increase_pllclock(crtc);
81255565 2242
6b8e6ed0 2243 return dev_priv->display.update_plane(crtc, fb, x, y);
81255565
JB		 2244}
2245
14667a4b
CW		 2246static int
2247intel_finish_fb(struct drm_framebuffer *old_fb)
2248{
2249 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2250 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2251 bool was_interruptible = dev_priv->mm.interruptible;
2252 int ret;
2253
2254 wait_event(dev_priv->pending_flip_queue,
2255 atomic_read(&dev_priv->mm.wedged) ||
2256 atomic_read(&obj->pending_flip) == 0);
2257
2258 /* Big Hammer, we also need to ensure that any pending
2259 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2260 * current scanout is retired before unpinning the old
2261 * framebuffer.
2262 *
2263 * This should only fail upon a hung GPU, in which case we
2264 * can safely continue.
2265 */
2266 dev_priv->mm.interruptible = false;
2267 ret = i915_gem_object_finish_gpu(obj);
2268 dev_priv->mm.interruptible = was_interruptible;
2269
2270 return ret;
2271}
2272
198598d0
VS		 2273static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2274{
2275 struct drm_device *dev = crtc->dev;
2276 struct drm_i915_master_private *master_priv;
2277 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2278
2279 if (!dev->primary->master)
2280 return;
2281
2282 master_priv = dev->primary->master->driver_priv;
2283 if (!master_priv->sarea_priv)
2284 return;
2285
2286 switch (intel_crtc->pipe) {
2287 case 0:
2288 master_priv->sarea_priv->pipeA_x = x;
2289 master_priv->sarea_priv->pipeA_y = y;
2290 break;
2291 case 1:
2292 master_priv->sarea_priv->pipeB_x = x;
2293 master_priv->sarea_priv->pipeB_y = y;
2294 break;
2295 default:
2296 break;
2297 }
2298}
2299
5c3b82e2 2300static int
3c4fdcfb 2301intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
94352cf9 2302 struct drm_framebuffer *fb)
79e53945
JB		 2303{
2304 struct drm_device *dev = crtc->dev;
6b8e6ed0 2305 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 2306 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
94352cf9 2307 struct drm_framebuffer *old_fb;
5c3b82e2 2308 int ret;
79e53945
JB		 2309
2310 /* no fb bound */
94352cf9 2311 if (!fb) {
a5071c2f 2312 DRM_ERROR("No FB bound\n");
5c3b82e2
CW		 2313 return 0;
2314 }
2315
5826eca5
ED		 2316 if(intel_crtc->plane > dev_priv->num_pipe) {
2317 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2318 intel_crtc->plane,
2319 dev_priv->num_pipe);
5c3b82e2 2320 return -EINVAL;
79e53945
JB		 2321 }
2322
5c3b82e2 2323 mutex_lock(&dev->struct_mutex);
265db958 2324 ret = intel_pin_and_fence_fb_obj(dev,
94352cf9 2325 to_intel_framebuffer(fb)->obj,
919926ae 2326 NULL);
5c3b82e2
CW		 2327 if (ret != 0) {
2328 mutex_unlock(&dev->struct_mutex);
a5071c2f 2329 DRM_ERROR("pin & fence failed\n");
5c3b82e2
CW		 2330 return ret;
2331 }
79e53945 2332
94352cf9
DV		 2333 if (crtc->fb)
2334 intel_finish_fb(crtc->fb);
265db958 2335
94352cf9 2336 ret = dev_priv->display.update_plane(crtc, fb, x, y);
4e6cfefc 2337 if (ret) {
94352cf9 2338 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
5c3b82e2 2339 mutex_unlock(&dev->struct_mutex);
a5071c2f 2340 DRM_ERROR("failed to update base address\n");
4e6cfefc 2341 return ret;
79e53945 2342 }
3c4fdcfb 2343
94352cf9
DV		 2344 old_fb = crtc->fb;
2345 crtc->fb = fb;
6c4c86f5
DV		 2346 crtc->x = x;
2347 crtc->y = y;
94352cf9 2348
b7f1de28
CW		 2349 if (old_fb) {
2350 intel_wait_for_vblank(dev, intel_crtc->pipe);
1690e1eb 2351 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
b7f1de28 2352 }
652c393a 2353
6b8e6ed0 2354 intel_update_fbc(dev);
5c3b82e2 2355 mutex_unlock(&dev->struct_mutex);
79e53945 2356
198598d0 2357 intel_crtc_update_sarea_pos(crtc, x, y);
5c3b82e2
CW		 2358
2359 return 0;
79e53945
JB		 2360}
2361
5eddb70b 2362static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
32f9d658
ZW		 2363{
2364 struct drm_device *dev = crtc->dev;
2365 struct drm_i915_private *dev_priv = dev->dev_private;
2366 u32 dpa_ctl;
2367
28c97730 2368 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
32f9d658
ZW		 2369 dpa_ctl = I915_READ(DP_A);
2370 dpa_ctl &= ~DP_PLL_FREQ_MASK;
2371
2372 if (clock < 200000) {
2373 u32 temp;
2374 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2375 /* workaround for 160Mhz:
2376 1) program 0x4600c bits 15:0 = 0x8124
2377 2) program 0x46010 bit 0 = 1
2378 3) program 0x46034 bit 24 = 1
2379 4) program 0x64000 bit 14 = 1
2380 */
2381 temp = I915_READ(0x4600c);
2382 temp &= 0xffff0000;
2383 I915_WRITE(0x4600c, temp | 0x8124);
2384
2385 temp = I915_READ(0x46010);
2386 I915_WRITE(0x46010, temp | 1);
2387
2388 temp = I915_READ(0x46034);
2389 I915_WRITE(0x46034, temp | (1 << 24));
2390 } else {
2391 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2392 }
2393 I915_WRITE(DP_A, dpa_ctl);
2394
5eddb70b 2395 POSTING_READ(DP_A);
32f9d658
ZW		 2396 udelay(500);
2397}
2398
5e84e1a4
ZW		 2399static void intel_fdi_normal_train(struct drm_crtc *crtc)
2400{
2401 struct drm_device *dev = crtc->dev;
2402 struct drm_i915_private *dev_priv = dev->dev_private;
2403 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2404 int pipe = intel_crtc->pipe;
2405 u32 reg, temp;
2406
2407 /* enable normal train */
2408 reg = FDI_TX_CTL(pipe);
2409 temp = I915_READ(reg);
61e499bf 2410 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2411 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2412 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2413 } else {
2414 temp &= ~FDI_LINK_TRAIN_NONE;
2415 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2416 }
5e84e1a4
ZW		 2417 I915_WRITE(reg, temp);
2418
2419 reg = FDI_RX_CTL(pipe);
2420 temp = I915_READ(reg);
2421 if (HAS_PCH_CPT(dev)) {
2422 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2423 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2424 } else {
2425 temp &= ~FDI_LINK_TRAIN_NONE;
2426 temp |= FDI_LINK_TRAIN_NONE;
2427 }
2428 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2429
2430 /* wait one idle pattern time */
2431 POSTING_READ(reg);
2432 udelay(1000);
357555c0
JB		 2433
2434 /* IVB wants error correction enabled */
2435 if (IS_IVYBRIDGE(dev))
2436 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2437 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2438}
2439
291427f5
JB		 2440static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2441{
2442 struct drm_i915_private *dev_priv = dev->dev_private;
2443 u32 flags = I915_READ(SOUTH_CHICKEN1);
2444
2445 flags |= FDI_PHASE_SYNC_OVR(pipe);
2446 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2447 flags |= FDI_PHASE_SYNC_EN(pipe);
2448 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2449 POSTING_READ(SOUTH_CHICKEN1);
2450}
2451
01a415fd
DV		 2452static void ivb_modeset_global_resources(struct drm_device *dev)
2453{
2454 struct drm_i915_private *dev_priv = dev->dev_private;
2455 struct intel_crtc *pipe_B_crtc =
2456 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2457 struct intel_crtc *pipe_C_crtc =
2458 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2459 uint32_t temp;
2460
2461 /* When everything is off disable fdi C so that we could enable fdi B
2462 * with all lanes. XXX: This misses the case where a pipe is not using
2463 * any pch resources and so doesn't need any fdi lanes. */
2464 if (!pipe_B_crtc->base.enabled && !pipe_C_crtc->base.enabled) {
2465 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2466 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2467
2468 temp = I915_READ(SOUTH_CHICKEN1);
2469 temp &= ~FDI_BC_BIFURCATION_SELECT;
2470 DRM_DEBUG_KMS("disabling fdi C rx\n");
2471 I915_WRITE(SOUTH_CHICKEN1, temp);
2472 }
2473}
2474
8db9d77b
ZW		 2475/* The FDI link training functions for ILK/Ibexpeak. */
2476static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2477{
2478 struct drm_device *dev = crtc->dev;
2479 struct drm_i915_private *dev_priv = dev->dev_private;
2480 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2481 int pipe = intel_crtc->pipe;
0fc932b8 2482 int plane = intel_crtc->plane;
5eddb70b 2483 u32 reg, temp, tries;
8db9d77b 2484
0fc932b8
JB		 2485 /* FDI needs bits from pipe & plane first */
2486 assert_pipe_enabled(dev_priv, pipe);
2487 assert_plane_enabled(dev_priv, plane);
2488
e1a44743
AJ		 2489 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2490 for train result */
5eddb70b
CW		 2491 reg = FDI_RX_IMR(pipe);
2492 temp = I915_READ(reg);
e1a44743
AJ		 2493 temp &= ~FDI_RX_SYMBOL_LOCK;
2494 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2495 I915_WRITE(reg, temp);
2496 I915_READ(reg);
e1a44743
AJ		 2497 udelay(150);
2498
8db9d77b 2499 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2500 reg = FDI_TX_CTL(pipe);
2501 temp = I915_READ(reg);
77ffb597
AJ		 2502 temp &= ~(7 << 19);
2503 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2504 temp &= ~FDI_LINK_TRAIN_NONE;
2505 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2506 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2507
5eddb70b
CW		 2508 reg = FDI_RX_CTL(pipe);
2509 temp = I915_READ(reg);
8db9d77b
ZW		 2510 temp &= ~FDI_LINK_TRAIN_NONE;
2511 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2512 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2513
2514 POSTING_READ(reg);
8db9d77b
ZW		 2515 udelay(150);
2516
5b2adf89 2517 /* Ironlake workaround, enable clock pointer after FDI enable*/
6f06ce18
JB		 2518 if (HAS_PCH_IBX(dev)) {
2519 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2520 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2521 FDI_RX_PHASE_SYNC_POINTER_EN);
2522 }
5b2adf89 2523
5eddb70b 2524 reg = FDI_RX_IIR(pipe);
e1a44743 2525 for (tries = 0; tries < 5; tries++) {
5eddb70b 2526 temp = I915_READ(reg);
8db9d77b
ZW		 2527 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2528
2529 if ((temp & FDI_RX_BIT_LOCK)) {
2530 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2531 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2532 break;
2533 }
8db9d77b 2534 }
e1a44743 2535 if (tries == 5)
5eddb70b 2536 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2537
2538 /* Train 2 */
5eddb70b
CW		 2539 reg = FDI_TX_CTL(pipe);
2540 temp = I915_READ(reg);
8db9d77b
ZW		 2541 temp &= ~FDI_LINK_TRAIN_NONE;
2542 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2543 I915_WRITE(reg, temp);
8db9d77b 2544
5eddb70b
CW		 2545 reg = FDI_RX_CTL(pipe);
2546 temp = I915_READ(reg);
8db9d77b
ZW		 2547 temp &= ~FDI_LINK_TRAIN_NONE;
2548 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2549 I915_WRITE(reg, temp);
8db9d77b 2550
5eddb70b
CW		 2551 POSTING_READ(reg);
2552 udelay(150);
8db9d77b 2553
5eddb70b 2554 reg = FDI_RX_IIR(pipe);
e1a44743 2555 for (tries = 0; tries < 5; tries++) {
5eddb70b 2556 temp = I915_READ(reg);
8db9d77b
ZW		 2557 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2558
2559 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2560 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2561 DRM_DEBUG_KMS("FDI train 2 done.\n");
2562 break;
2563 }
8db9d77b 2564 }
e1a44743 2565 if (tries == 5)
5eddb70b 2566 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2567
2568 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2569
8db9d77b
ZW		 2570}
2571
0206e353 2572static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 2573 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2574 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2575 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2576 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2577};
2578
2579/* The FDI link training functions for SNB/Cougarpoint. */
2580static void gen6_fdi_link_train(struct drm_crtc *crtc)
2581{
2582 struct drm_device *dev = crtc->dev;
2583 struct drm_i915_private *dev_priv = dev->dev_private;
2584 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2585 int pipe = intel_crtc->pipe;
fa37d39e 2586 u32 reg, temp, i, retry;
8db9d77b 2587
e1a44743
AJ		 2588 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2589 for train result */
5eddb70b
CW		 2590 reg = FDI_RX_IMR(pipe);
2591 temp = I915_READ(reg);
e1a44743
AJ		 2592 temp &= ~FDI_RX_SYMBOL_LOCK;
2593 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2594 I915_WRITE(reg, temp);
2595
2596 POSTING_READ(reg);
e1a44743
AJ		 2597 udelay(150);
2598
8db9d77b 2599 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2600 reg = FDI_TX_CTL(pipe);
2601 temp = I915_READ(reg);
77ffb597
AJ		 2602 temp &= ~(7 << 19);
2603 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2604 temp &= ~FDI_LINK_TRAIN_NONE;
2605 temp |= FDI_LINK_TRAIN_PATTERN_1;
2606 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2607 /* SNB-B */
2608 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2609 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2610
d74cf324
DV		 2611 I915_WRITE(FDI_RX_MISC(pipe),
2612 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2613
5eddb70b
CW		 2614 reg = FDI_RX_CTL(pipe);
2615 temp = I915_READ(reg);
8db9d77b
ZW		 2616 if (HAS_PCH_CPT(dev)) {
2617 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2618 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2619 } else {
2620 temp &= ~FDI_LINK_TRAIN_NONE;
2621 temp |= FDI_LINK_TRAIN_PATTERN_1;
2622 }
5eddb70b
CW		 2623 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2624
2625 POSTING_READ(reg);
8db9d77b
ZW		 2626 udelay(150);
2627
291427f5
JB		 2628 if (HAS_PCH_CPT(dev))
2629 cpt_phase_pointer_enable(dev, pipe);
2630
0206e353 2631 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2632 reg = FDI_TX_CTL(pipe);
2633 temp = I915_READ(reg);
8db9d77b
ZW		 2634 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2635 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2636 I915_WRITE(reg, temp);
2637
2638 POSTING_READ(reg);
8db9d77b
ZW		 2639 udelay(500);
2640
fa37d39e
SP		 2641 for (retry = 0; retry < 5; retry++) {
2642 reg = FDI_RX_IIR(pipe);
2643 temp = I915_READ(reg);
2644 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2645 if (temp & FDI_RX_BIT_LOCK) {
2646 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2647 DRM_DEBUG_KMS("FDI train 1 done.\n");
2648 break;
2649 }
2650 udelay(50);
8db9d77b 2651 }
fa37d39e
SP		 2652 if (retry < 5)
2653 break;
8db9d77b
ZW		 2654 }
2655 if (i == 4)
5eddb70b 2656 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2657
2658 /* Train 2 */
5eddb70b
CW		 2659 reg = FDI_TX_CTL(pipe);
2660 temp = I915_READ(reg);
8db9d77b
ZW		 2661 temp &= ~FDI_LINK_TRAIN_NONE;
2662 temp |= FDI_LINK_TRAIN_PATTERN_2;
2663 if (IS_GEN6(dev)) {
2664 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2665 /* SNB-B */
2666 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2667 }
5eddb70b 2668 I915_WRITE(reg, temp);
8db9d77b 2669
5eddb70b
CW		 2670 reg = FDI_RX_CTL(pipe);
2671 temp = I915_READ(reg);
8db9d77b
ZW		 2672 if (HAS_PCH_CPT(dev)) {
2673 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2674 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2675 } else {
2676 temp &= ~FDI_LINK_TRAIN_NONE;
2677 temp |= FDI_LINK_TRAIN_PATTERN_2;
2678 }
5eddb70b
CW		 2679 I915_WRITE(reg, temp);
2680
2681 POSTING_READ(reg);
8db9d77b
ZW		 2682 udelay(150);
2683
0206e353 2684 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2685 reg = FDI_TX_CTL(pipe);
2686 temp = I915_READ(reg);
8db9d77b
ZW		 2687 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2688 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2689 I915_WRITE(reg, temp);
2690
2691 POSTING_READ(reg);
8db9d77b
ZW		 2692 udelay(500);
2693
fa37d39e
SP		 2694 for (retry = 0; retry < 5; retry++) {
2695 reg = FDI_RX_IIR(pipe);
2696 temp = I915_READ(reg);
2697 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2698 if (temp & FDI_RX_SYMBOL_LOCK) {
2699 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2700 DRM_DEBUG_KMS("FDI train 2 done.\n");
2701 break;
2702 }
2703 udelay(50);
8db9d77b 2704 }
fa37d39e
SP		 2705 if (retry < 5)
2706 break;
8db9d77b
ZW		 2707 }
2708 if (i == 4)
5eddb70b 2709 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2710
2711 DRM_DEBUG_KMS("FDI train done.\n");
2712}
2713
357555c0
JB		 2714/* Manual link training for Ivy Bridge A0 parts */
2715static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2716{
2717 struct drm_device *dev = crtc->dev;
2718 struct drm_i915_private *dev_priv = dev->dev_private;
2719 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2720 int pipe = intel_crtc->pipe;
2721 u32 reg, temp, i;
2722
2723 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2724 for train result */
2725 reg = FDI_RX_IMR(pipe);
2726 temp = I915_READ(reg);
2727 temp &= ~FDI_RX_SYMBOL_LOCK;
2728 temp &= ~FDI_RX_BIT_LOCK;
2729 I915_WRITE(reg, temp);
2730
2731 POSTING_READ(reg);
2732 udelay(150);
2733
01a415fd
DV		 2734 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2735 I915_READ(FDI_RX_IIR(pipe)));
2736
357555c0
JB		 2737 /* enable CPU FDI TX and PCH FDI RX */
2738 reg = FDI_TX_CTL(pipe);
2739 temp = I915_READ(reg);
2740 temp &= ~(7 << 19);
2741 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2742 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2743 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2744 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2745 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
c4f9c4c2 2746 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2747 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2748
d74cf324
DV		 2749 I915_WRITE(FDI_RX_MISC(pipe),
2750 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2751
357555c0
JB		 2752 reg = FDI_RX_CTL(pipe);
2753 temp = I915_READ(reg);
2754 temp &= ~FDI_LINK_TRAIN_AUTO;
2755 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2756 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
c4f9c4c2 2757 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2758 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2759
2760 POSTING_READ(reg);
2761 udelay(150);
2762
291427f5
JB		 2763 if (HAS_PCH_CPT(dev))
2764 cpt_phase_pointer_enable(dev, pipe);
2765
0206e353 2766 for (i = 0; i < 4; i++) {
357555c0
JB		 2767 reg = FDI_TX_CTL(pipe);
2768 temp = I915_READ(reg);
2769 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2770 temp |= snb_b_fdi_train_param[i];
2771 I915_WRITE(reg, temp);
2772
2773 POSTING_READ(reg);
2774 udelay(500);
2775
2776 reg = FDI_RX_IIR(pipe);
2777 temp = I915_READ(reg);
2778 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2779
2780 if (temp & FDI_RX_BIT_LOCK ||
2781 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2782 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
01a415fd 2783 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
357555c0
JB		 2784 break;
2785 }
2786 }
2787 if (i == 4)
2788 DRM_ERROR("FDI train 1 fail!\n");
2789
2790 /* Train 2 */
2791 reg = FDI_TX_CTL(pipe);
2792 temp = I915_READ(reg);
2793 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2794 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2795 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2796 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2797 I915_WRITE(reg, temp);
2798
2799 reg = FDI_RX_CTL(pipe);
2800 temp = I915_READ(reg);
2801 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2802 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2803 I915_WRITE(reg, temp);
2804
2805 POSTING_READ(reg);
2806 udelay(150);
2807
0206e353 2808 for (i = 0; i < 4; i++) {
357555c0
JB		 2809 reg = FDI_TX_CTL(pipe);
2810 temp = I915_READ(reg);
2811 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2812 temp |= snb_b_fdi_train_param[i];
2813 I915_WRITE(reg, temp);
2814
2815 POSTING_READ(reg);
2816 udelay(500);
2817
2818 reg = FDI_RX_IIR(pipe);
2819 temp = I915_READ(reg);
2820 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2821
2822 if (temp & FDI_RX_SYMBOL_LOCK) {
2823 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
01a415fd 2824 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
357555c0
JB		 2825 break;
2826 }
2827 }
2828 if (i == 4)
2829 DRM_ERROR("FDI train 2 fail!\n");
2830
2831 DRM_DEBUG_KMS("FDI train done.\n");
2832}
2833
88cefb6c 2834static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 2835{
88cefb6c 2836 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 2837 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 2838 int pipe = intel_crtc->pipe;
5eddb70b 2839 u32 reg, temp;
79e53945 2840
c64e311e 2841
c98e9dcf 2842 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2843 reg = FDI_RX_CTL(pipe);
2844 temp = I915_READ(reg);
2845 temp &= ~((0x7 << 19) | (0x7 << 16));
c98e9dcf 2846 temp |= (intel_crtc->fdi_lanes - 1) << 19;
5eddb70b
CW		 2847 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2848 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2849
2850 POSTING_READ(reg);
c98e9dcf
JB		 2851 udelay(200);
2852
2853 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2854 temp = I915_READ(reg);
2855 I915_WRITE(reg, temp | FDI_PCDCLK);
2856
2857 POSTING_READ(reg);
c98e9dcf
JB		 2858 udelay(200);
2859
bf507ef7
ED		 2860 /* On Haswell, the PLL configuration for ports and pipes is handled
2861 * separately, as part of DDI setup */
2862 if (!IS_HASWELL(dev)) {
2863 /* Enable CPU FDI TX PLL, always on for Ironlake */
2864 reg = FDI_TX_CTL(pipe);
2865 temp = I915_READ(reg);
2866 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2867 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 2868
bf507ef7
ED		 2869 POSTING_READ(reg);
2870 udelay(100);
2871 }
6be4a607 2872 }
0e23b99d
JB		 2873}
2874
88cefb6c
DV		 2875static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2876{
2877 struct drm_device *dev = intel_crtc->base.dev;
2878 struct drm_i915_private *dev_priv = dev->dev_private;
2879 int pipe = intel_crtc->pipe;
2880 u32 reg, temp;
2881
2882 /* Switch from PCDclk to Rawclk */
2883 reg = FDI_RX_CTL(pipe);
2884 temp = I915_READ(reg);
2885 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2886
2887 /* Disable CPU FDI TX PLL */
2888 reg = FDI_TX_CTL(pipe);
2889 temp = I915_READ(reg);
2890 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2891
2892 POSTING_READ(reg);
2893 udelay(100);
2894
2895 reg = FDI_RX_CTL(pipe);
2896 temp = I915_READ(reg);
2897 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2898
2899 /* Wait for the clocks to turn off. */
2900 POSTING_READ(reg);
2901 udelay(100);
2902}
2903
291427f5
JB		 2904static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2905{
2906 struct drm_i915_private *dev_priv = dev->dev_private;
2907 u32 flags = I915_READ(SOUTH_CHICKEN1);
2908
2909 flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2910 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2911 flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2912 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2913 POSTING_READ(SOUTH_CHICKEN1);
2914}
0fc932b8
JB		 2915static void ironlake_fdi_disable(struct drm_crtc *crtc)
2916{
2917 struct drm_device *dev = crtc->dev;
2918 struct drm_i915_private *dev_priv = dev->dev_private;
2919 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2920 int pipe = intel_crtc->pipe;
2921 u32 reg, temp;
2922
2923 /* disable CPU FDI tx and PCH FDI rx */
2924 reg = FDI_TX_CTL(pipe);
2925 temp = I915_READ(reg);
2926 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2927 POSTING_READ(reg);
2928
2929 reg = FDI_RX_CTL(pipe);
2930 temp = I915_READ(reg);
2931 temp &= ~(0x7 << 16);
2932 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2933 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2934
2935 POSTING_READ(reg);
2936 udelay(100);
2937
2938 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2939 if (HAS_PCH_IBX(dev)) {
2940 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
0fc932b8
JB		 2941 I915_WRITE(FDI_RX_CHICKEN(pipe),
2942 I915_READ(FDI_RX_CHICKEN(pipe) &
6f06ce18 2943 ~FDI_RX_PHASE_SYNC_POINTER_EN));
291427f5
JB		 2944 } else if (HAS_PCH_CPT(dev)) {
2945 cpt_phase_pointer_disable(dev, pipe);
6f06ce18 2946 }
0fc932b8
JB		 2947
2948 /* still set train pattern 1 */
2949 reg = FDI_TX_CTL(pipe);
2950 temp = I915_READ(reg);
2951 temp &= ~FDI_LINK_TRAIN_NONE;
2952 temp |= FDI_LINK_TRAIN_PATTERN_1;
2953 I915_WRITE(reg, temp);
2954
2955 reg = FDI_RX_CTL(pipe);
2956 temp = I915_READ(reg);
2957 if (HAS_PCH_CPT(dev)) {
2958 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2959 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2960 } else {
2961 temp &= ~FDI_LINK_TRAIN_NONE;
2962 temp |= FDI_LINK_TRAIN_PATTERN_1;
2963 }
2964 /* BPC in FDI rx is consistent with that in PIPECONF */
2965 temp &= ~(0x07 << 16);
2966 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2967 I915_WRITE(reg, temp);
2968
2969 POSTING_READ(reg);
2970 udelay(100);
2971}
2972
5bb61643
CW		 2973static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2974{
2975 struct drm_device *dev = crtc->dev;
2976 struct drm_i915_private *dev_priv = dev->dev_private;
2977 unsigned long flags;
2978 bool pending;
2979
2980 if (atomic_read(&dev_priv->mm.wedged))
2981 return false;
2982
2983 spin_lock_irqsave(&dev->event_lock, flags);
2984 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2985 spin_unlock_irqrestore(&dev->event_lock, flags);
2986
2987 return pending;
2988}
2989
e6c3a2a6
CW		 2990static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2991{
0f91128d 2992 struct drm_device *dev = crtc->dev;
5bb61643 2993 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6
CW		 2994
2995 if (crtc->fb == NULL)
2996 return;
2997
5bb61643
CW		 2998 wait_event(dev_priv->pending_flip_queue,
2999 !intel_crtc_has_pending_flip(crtc));
3000
0f91128d
CW		 3001 mutex_lock(&dev->struct_mutex);
3002 intel_finish_fb(crtc->fb);
3003 mutex_unlock(&dev->struct_mutex);
e6c3a2a6
CW		 3004}
3005
fc316cbe 3006static bool ironlake_crtc_driving_pch(struct drm_crtc *crtc)
040484af
JB		 3007{
3008 struct drm_device *dev = crtc->dev;
228d3e36 3009 struct intel_encoder *intel_encoder;
040484af
JB		 3010
3011 /*
3012 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
3013 * must be driven by its own crtc; no sharing is possible.
3014 */
228d3e36 3015 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
228d3e36 3016 switch (intel_encoder->type) {
040484af 3017 case INTEL_OUTPUT_EDP:
228d3e36 3018 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
040484af
JB		 3019 return false;
3020 continue;
3021 }
3022 }
3023
3024 return true;
3025}
3026
fc316cbe
PZ		 3027static bool haswell_crtc_driving_pch(struct drm_crtc *crtc)
3028{
3029 return intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG);
3030}
3031
e615efe4
ED		 3032/* Program iCLKIP clock to the desired frequency */
3033static void lpt_program_iclkip(struct drm_crtc *crtc)
3034{
3035 struct drm_device *dev = crtc->dev;
3036 struct drm_i915_private *dev_priv = dev->dev_private;
3037 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3038 u32 temp;
3039
3040 /* It is necessary to ungate the pixclk gate prior to programming
3041 * the divisors, and gate it back when it is done.
3042 */
3043 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3044
3045 /* Disable SSCCTL */
3046 intel_sbi_write(dev_priv, SBI_SSCCTL6,
3047 intel_sbi_read(dev_priv, SBI_SSCCTL6) |
3048 SBI_SSCCTL_DISABLE);
3049
3050 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3051 if (crtc->mode.clock == 20000) {
3052 auxdiv = 1;
3053 divsel = 0x41;
3054 phaseinc = 0x20;
3055 } else {
3056 /* The iCLK virtual clock root frequency is in MHz,
3057 * but the crtc->mode.clock in in KHz. To get the divisors,
3058 * it is necessary to divide one by another, so we
3059 * convert the virtual clock precision to KHz here for higher
3060 * precision.
3061 */
3062 u32 iclk_virtual_root_freq = 172800 * 1000;
3063 u32 iclk_pi_range = 64;
3064 u32 desired_divisor, msb_divisor_value, pi_value;
3065
3066 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
3067 msb_divisor_value = desired_divisor / iclk_pi_range;
3068 pi_value = desired_divisor % iclk_pi_range;
3069
3070 auxdiv = 0;
3071 divsel = msb_divisor_value - 2;
3072 phaseinc = pi_value;
3073 }
3074
3075 /* This should not happen with any sane values */
3076 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3077 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3078 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3079 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3080
3081 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3082 crtc->mode.clock,
3083 auxdiv,
3084 divsel,
3085 phasedir,
3086 phaseinc);
3087
3088 /* Program SSCDIVINTPHASE6 */
3089 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6);
3090 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3091 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3092 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3093 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3094 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3095 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3096
3097 intel_sbi_write(dev_priv,
3098 SBI_SSCDIVINTPHASE6,
3099 temp);
3100
3101 /* Program SSCAUXDIV */
3102 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6);
3103 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3104 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3105 intel_sbi_write(dev_priv,
3106 SBI_SSCAUXDIV6,
3107 temp);
3108
3109
3110 /* Enable modulator and associated divider */
3111 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6);
3112 temp &= ~SBI_SSCCTL_DISABLE;
3113 intel_sbi_write(dev_priv,
3114 SBI_SSCCTL6,
3115 temp);
3116
3117 /* Wait for initialization time */
3118 udelay(24);
3119
3120 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3121}
3122
f67a559d
JB		 3123/*
3124 * Enable PCH resources required for PCH ports:
3125 * - PCH PLLs
3126 * - FDI training & RX/TX
3127 * - update transcoder timings
3128 * - DP transcoding bits
3129 * - transcoder
3130 */
3131static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 3132{
3133 struct drm_device *dev = crtc->dev;
3134 struct drm_i915_private *dev_priv = dev->dev_private;
3135 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3136 int pipe = intel_crtc->pipe;
ee7b9f93 3137 u32 reg, temp;
2c07245f 3138
e7e164db
CW		 3139 assert_transcoder_disabled(dev_priv, pipe);
3140
cd986abb
DV		 3141 /* Write the TU size bits before fdi link training, so that error
3142 * detection works. */
3143 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3144 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3145
c98e9dcf 3146 /* For PCH output, training FDI link */
674cf967 3147 dev_priv->display.fdi_link_train(crtc);
2c07245f 3148
572deb37
DV		 3149 /* XXX: pch pll's can be enabled any time before we enable the PCH
3150 * transcoder, and we actually should do this to not upset any PCH
3151 * transcoder that already use the clock when we share it.
3152 *
3153 * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
3154 * unconditionally resets the pll - we need that to have the right LVDS
3155 * enable sequence. */
b6b4e185 3156 ironlake_enable_pch_pll(intel_crtc);
6f13b7b5 3157
303b81e0 3158 if (HAS_PCH_CPT(dev)) {
ee7b9f93 3159 u32 sel;
4b645f14 3160
c98e9dcf 3161 temp = I915_READ(PCH_DPLL_SEL);
ee7b9f93
JB		 3162 switch (pipe) {
3163 default:
3164 case 0:
3165 temp |= TRANSA_DPLL_ENABLE;
3166 sel = TRANSA_DPLLB_SEL;
3167 break;
3168 case 1:
3169 temp |= TRANSB_DPLL_ENABLE;
3170 sel = TRANSB_DPLLB_SEL;
3171 break;
3172 case 2:
3173 temp |= TRANSC_DPLL_ENABLE;
3174 sel = TRANSC_DPLLB_SEL;
3175 break;
d64311ab 3176 }
ee7b9f93
JB		 3177 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3178 temp |= sel;
3179 else
3180 temp &= ~sel;
c98e9dcf 3181 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 3182 }
5eddb70b 3183
d9b6cb56
JB		 3184 /* set transcoder timing, panel must allow it */
3185 assert_panel_unlocked(dev_priv, pipe);
5eddb70b
CW		 3186 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3187 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3188 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
8db9d77b 3189
5eddb70b
CW		 3190 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3191 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3192 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
0529a0d9 3193 I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe)));
8db9d77b 3194
303b81e0 3195 intel_fdi_normal_train(crtc);
5e84e1a4 3196
c98e9dcf
JB		 3197 /* For PCH DP, enable TRANS_DP_CTL */
3198 if (HAS_PCH_CPT(dev) &&
417e822d
KP		 3199 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3200 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
9325c9f0 3201 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
5eddb70b
CW		 3202 reg = TRANS_DP_CTL(pipe);
3203 temp = I915_READ(reg);
3204 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 3205 TRANS_DP_SYNC_MASK |
3206 TRANS_DP_BPC_MASK);
5eddb70b
CW		 3207 temp |= (TRANS_DP_OUTPUT_ENABLE |
3208 TRANS_DP_ENH_FRAMING);
9325c9f0 3209 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 3210
3211 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 3212 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 3213 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 3214 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 3215
3216 switch (intel_trans_dp_port_sel(crtc)) {
3217 case PCH_DP_B:
5eddb70b 3218 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 3219 break;
3220 case PCH_DP_C:
5eddb70b 3221 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 3222 break;
3223 case PCH_DP_D:
5eddb70b 3224 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 3225 break;
3226 default:
e95d41e1 3227 BUG();
32f9d658 3228 }
2c07245f 3229
5eddb70b 3230 I915_WRITE(reg, temp);
6be4a607 3231 }
b52eb4dc 3232
b8a4f404 3233 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 3234}
3235
1507e5bd
PZ		 3236static void lpt_pch_enable(struct drm_crtc *crtc)
3237{
3238 struct drm_device *dev = crtc->dev;
3239 struct drm_i915_private *dev_priv = dev->dev_private;
3240 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3241 int pipe = intel_crtc->pipe;
daed2dbb 3242 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
1507e5bd 3243
daed2dbb 3244 assert_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd
PZ		 3245
3246 /* Write the TU size bits before fdi link training, so that error
3247 * detection works. */
3248 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3249 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3250
3251 /* For PCH output, training FDI link */
3252 dev_priv->display.fdi_link_train(crtc);
3253
8c52b5e8 3254 lpt_program_iclkip(crtc);
1507e5bd 3255
0540e488 3256 /* Set transcoder timing. */
daed2dbb
PZ		 3257 I915_WRITE(_TRANS_HTOTAL_A, I915_READ(HTOTAL(cpu_transcoder)));
3258 I915_WRITE(_TRANS_HBLANK_A, I915_READ(HBLANK(cpu_transcoder)));
3259 I915_WRITE(_TRANS_HSYNC_A, I915_READ(HSYNC(cpu_transcoder)));
1507e5bd 3260
daed2dbb
PZ		 3261 I915_WRITE(_TRANS_VTOTAL_A, I915_READ(VTOTAL(cpu_transcoder)));
3262 I915_WRITE(_TRANS_VBLANK_A, I915_READ(VBLANK(cpu_transcoder)));
3263 I915_WRITE(_TRANS_VSYNC_A, I915_READ(VSYNC(cpu_transcoder)));
3264 I915_WRITE(_TRANS_VSYNCSHIFT_A, I915_READ(VSYNCSHIFT(cpu_transcoder)));
1507e5bd 3265
8fb033d7 3266 lpt_enable_pch_transcoder(dev_priv, intel_crtc->pipe);
1507e5bd
PZ		 3267}
3268
ee7b9f93
JB		 3269static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3270{
3271 struct intel_pch_pll *pll = intel_crtc->pch_pll;
3272
3273 if (pll == NULL)
3274 return;
3275
3276 if (pll->refcount == 0) {
3277 WARN(1, "bad PCH PLL refcount\n");
3278 return;
3279 }
3280
3281 --pll->refcount;
3282 intel_crtc->pch_pll = NULL;
3283}
3284
3285static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3286{
3287 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3288 struct intel_pch_pll *pll;
3289 int i;
3290
3291 pll = intel_crtc->pch_pll;
3292 if (pll) {
3293 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3294 intel_crtc->base.base.id, pll->pll_reg);
3295 goto prepare;
3296 }
3297
98b6bd99
DV		 3298 if (HAS_PCH_IBX(dev_priv->dev)) {
3299 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3300 i = intel_crtc->pipe;
3301 pll = &dev_priv->pch_plls[i];
3302
3303 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3304 intel_crtc->base.base.id, pll->pll_reg);
3305
3306 goto found;
3307 }
3308
ee7b9f93
JB		 3309 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3310 pll = &dev_priv->pch_plls[i];
3311
3312 /* Only want to check enabled timings first */
3313 if (pll->refcount == 0)
3314 continue;
3315
3316 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3317 fp == I915_READ(pll->fp0_reg)) {
3318 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3319 intel_crtc->base.base.id,
3320 pll->pll_reg, pll->refcount, pll->active);
3321
3322 goto found;
3323 }
3324 }
3325
3326 /* Ok no matching timings, maybe there's a free one? */
3327 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3328 pll = &dev_priv->pch_plls[i];
3329 if (pll->refcount == 0) {
3330 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3331 intel_crtc->base.base.id, pll->pll_reg);
3332 goto found;
3333 }
3334 }
3335
3336 return NULL;
3337
3338found:
3339 intel_crtc->pch_pll = pll;
3340 pll->refcount++;
3341 DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
3342prepare: /* separate function? */
3343 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
ee7b9f93 3344
e04c7350
CW		 3345 /* Wait for the clocks to stabilize before rewriting the regs */
3346 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 3347 POSTING_READ(pll->pll_reg);
3348 udelay(150);
e04c7350
CW		 3349
3350 I915_WRITE(pll->fp0_reg, fp);
3351 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 3352 pll->on = false;
3353 return pll;
3354}
3355
d4270e57
JB		 3356void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3357{
3358 struct drm_i915_private *dev_priv = dev->dev_private;
3359 int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe);
3360 u32 temp;
3361
3362 temp = I915_READ(dslreg);
3363 udelay(500);
3364 if (wait_for(I915_READ(dslreg) != temp, 5)) {
3365 /* Without this, mode sets may fail silently on FDI */
3366 I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS);
3367 udelay(250);
3368 I915_WRITE(tc2reg, 0);
3369 if (wait_for(I915_READ(dslreg) != temp, 5))
3370 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3371 }
3372}
3373
f67a559d
JB		 3374static void ironlake_crtc_enable(struct drm_crtc *crtc)
3375{
3376 struct drm_device *dev = crtc->dev;
3377 struct drm_i915_private *dev_priv = dev->dev_private;
3378 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3379 struct intel_encoder *encoder;
f67a559d
JB		 3380 int pipe = intel_crtc->pipe;
3381 int plane = intel_crtc->plane;
3382 u32 temp;
3383 bool is_pch_port;
3384
08a48469
DV		 3385 WARN_ON(!crtc->enabled);
3386
f67a559d
JB		 3387 if (intel_crtc->active)
3388 return;
3389
3390 intel_crtc->active = true;
3391 intel_update_watermarks(dev);
3392
3393 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3394 temp = I915_READ(PCH_LVDS);
3395 if ((temp & LVDS_PORT_EN) == 0)
3396 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3397 }
3398
fc316cbe 3399 is_pch_port = ironlake_crtc_driving_pch(crtc);
f67a559d 3400
46b6f814 3401 if (is_pch_port) {
fff367c7
DV		 3402 /* Note: FDI PLL enabling _must_ be done before we enable the
3403 * cpu pipes, hence this is separate from all the other fdi/pch
3404 * enabling. */
88cefb6c 3405 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 3406 } else {
3407 assert_fdi_tx_disabled(dev_priv, pipe);
3408 assert_fdi_rx_disabled(dev_priv, pipe);
3409 }
f67a559d 3410
bf49ec8c
DV		 3411 for_each_encoder_on_crtc(dev, crtc, encoder)
3412 if (encoder->pre_enable)
3413 encoder->pre_enable(encoder);
3414
f67a559d
JB		 3415 /* Enable panel fitting for LVDS */
3416 if (dev_priv->pch_pf_size &&
3417 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
3418 /* Force use of hard-coded filter coefficients
3419 * as some pre-programmed values are broken,
3420 * e.g. x201.
3421 */
9db4a9c7
JB		 3422 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3423 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3424 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
f67a559d
JB		 3425 }
3426
9c54c0dd
JB		 3427 /*
3428 * On ILK+ LUT must be loaded before the pipe is running but with
3429 * clocks enabled
3430 */
3431 intel_crtc_load_lut(crtc);
3432
f67a559d
JB		 3433 intel_enable_pipe(dev_priv, pipe, is_pch_port);
3434 intel_enable_plane(dev_priv, plane, pipe);
3435
3436 if (is_pch_port)
3437 ironlake_pch_enable(crtc);
c98e9dcf 3438
d1ebd816 3439 mutex_lock(&dev->struct_mutex);
bed4a673 3440 intel_update_fbc(dev);
d1ebd816
BW		 3441 mutex_unlock(&dev->struct_mutex);
3442
6b383a7f 3443 intel_crtc_update_cursor(crtc, true);
ef9c3aee 3444
fa5c73b1
DV		 3445 for_each_encoder_on_crtc(dev, crtc, encoder)
3446 encoder->enable(encoder);
61b77ddd
DV		 3447
3448 if (HAS_PCH_CPT(dev))
3449 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
6ce94100
DV		 3450
3451 /*
3452 * There seems to be a race in PCH platform hw (at least on some
3453 * outputs) where an enabled pipe still completes any pageflip right
3454 * away (as if the pipe is off) instead of waiting for vblank. As soon
3455 * as the first vblank happend, everything works as expected. Hence just
3456 * wait for one vblank before returning to avoid strange things
3457 * happening.
3458 */
3459 intel_wait_for_vblank(dev, intel_crtc->pipe);
6be4a607
JB		 3460}
3461
4f771f10
PZ		 3462static void haswell_crtc_enable(struct drm_crtc *crtc)
3463{
3464 struct drm_device *dev = crtc->dev;
3465 struct drm_i915_private *dev_priv = dev->dev_private;
3466 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3467 struct intel_encoder *encoder;
3468 int pipe = intel_crtc->pipe;
3469 int plane = intel_crtc->plane;
4f771f10
PZ		 3470 bool is_pch_port;
3471
3472 WARN_ON(!crtc->enabled);
3473
3474 if (intel_crtc->active)
3475 return;
3476
3477 intel_crtc->active = true;
3478 intel_update_watermarks(dev);
3479
fc316cbe 3480 is_pch_port = haswell_crtc_driving_pch(crtc);
4f771f10 3481
83616634 3482 if (is_pch_port)
4f771f10 3483 ironlake_fdi_pll_enable(intel_crtc);
4f771f10
PZ		 3484
3485 for_each_encoder_on_crtc(dev, crtc, encoder)
3486 if (encoder->pre_enable)
3487 encoder->pre_enable(encoder);
3488
1f544388 3489 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 3490
1f544388
PZ		 3491 /* Enable panel fitting for eDP */
3492 if (dev_priv->pch_pf_size && HAS_eDP) {
4f771f10
PZ		 3493 /* Force use of hard-coded filter coefficients
3494 * as some pre-programmed values are broken,
3495 * e.g. x201.
3496 */
3497 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3498 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3499 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3500 }
3501
3502 /*
3503 * On ILK+ LUT must be loaded before the pipe is running but with
3504 * clocks enabled
3505 */
3506 intel_crtc_load_lut(crtc);
3507
1f544388
PZ		 3508 intel_ddi_set_pipe_settings(crtc);
3509 intel_ddi_enable_pipe_func(crtc);
4f771f10
PZ		 3510
3511 intel_enable_pipe(dev_priv, pipe, is_pch_port);
3512 intel_enable_plane(dev_priv, plane, pipe);
3513
3514 if (is_pch_port)
1507e5bd 3515 lpt_pch_enable(crtc);
4f771f10
PZ		 3516
3517 mutex_lock(&dev->struct_mutex);
3518 intel_update_fbc(dev);
3519 mutex_unlock(&dev->struct_mutex);
3520
3521 intel_crtc_update_cursor(crtc, true);
3522
3523 for_each_encoder_on_crtc(dev, crtc, encoder)
3524 encoder->enable(encoder);
3525
4f771f10
PZ		 3526 /*
3527 * There seems to be a race in PCH platform hw (at least on some
3528 * outputs) where an enabled pipe still completes any pageflip right
3529 * away (as if the pipe is off) instead of waiting for vblank. As soon
3530 * as the first vblank happend, everything works as expected. Hence just
3531 * wait for one vblank before returning to avoid strange things
3532 * happening.
3533 */
3534 intel_wait_for_vblank(dev, intel_crtc->pipe);
3535}
3536
6be4a607
JB		 3537static void ironlake_crtc_disable(struct drm_crtc *crtc)
3538{
3539 struct drm_device *dev = crtc->dev;
3540 struct drm_i915_private *dev_priv = dev->dev_private;
3541 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3542 struct intel_encoder *encoder;
6be4a607
JB		 3543 int pipe = intel_crtc->pipe;
3544 int plane = intel_crtc->plane;
5eddb70b 3545 u32 reg, temp;
b52eb4dc 3546
ef9c3aee 3547
f7abfe8b
CW		 3548 if (!intel_crtc->active)
3549 return;
3550
ea9d758d
DV		 3551 for_each_encoder_on_crtc(dev, crtc, encoder)
3552 encoder->disable(encoder);
3553
e6c3a2a6 3554 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 3555 drm_vblank_off(dev, pipe);
6b383a7f 3556 intel_crtc_update_cursor(crtc, false);
5eddb70b 3557
b24e7179 3558 intel_disable_plane(dev_priv, plane, pipe);
913d8d11 3559
973d04f9
CW		 3560 if (dev_priv->cfb_plane == plane)
3561 intel_disable_fbc(dev);
2c07245f 3562
b24e7179 3563 intel_disable_pipe(dev_priv, pipe);
32f9d658 3564
6be4a607 3565 /* Disable PF */
9db4a9c7
JB		 3566 I915_WRITE(PF_CTL(pipe), 0);
3567 I915_WRITE(PF_WIN_SZ(pipe), 0);
2c07245f 3568
bf49ec8c
DV		 3569 for_each_encoder_on_crtc(dev, crtc, encoder)
3570 if (encoder->post_disable)
3571 encoder->post_disable(encoder);
3572
0fc932b8 3573 ironlake_fdi_disable(crtc);
2c07245f 3574
b8a4f404 3575 ironlake_disable_pch_transcoder(dev_priv, pipe);
913d8d11 3576
6be4a607
JB		 3577 if (HAS_PCH_CPT(dev)) {
3578 /* disable TRANS_DP_CTL */
5eddb70b
CW		 3579 reg = TRANS_DP_CTL(pipe);
3580 temp = I915_READ(reg);
3581 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
cb3543c6 3582 temp |= TRANS_DP_PORT_SEL_NONE;
5eddb70b 3583 I915_WRITE(reg, temp);
6be4a607
JB		 3584
3585 /* disable DPLL_SEL */
3586 temp = I915_READ(PCH_DPLL_SEL);
9db4a9c7
JB		 3587 switch (pipe) {
3588 case 0:
d64311ab 3589 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
9db4a9c7
JB		 3590 break;
3591 case 1:
6be4a607 3592 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
9db4a9c7
JB		 3593 break;
3594 case 2:
4b645f14 3595 /* C shares PLL A or B */
d64311ab 3596 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
9db4a9c7
JB		 3597 break;
3598 default:
3599 BUG(); /* wtf */
3600 }
6be4a607 3601 I915_WRITE(PCH_DPLL_SEL, temp);
6be4a607 3602 }
e3421a18 3603
6be4a607 3604 /* disable PCH DPLL */
ee7b9f93 3605 intel_disable_pch_pll(intel_crtc);
8db9d77b 3606
88cefb6c 3607 ironlake_fdi_pll_disable(intel_crtc);
6b383a7f 3608
f7abfe8b 3609 intel_crtc->active = false;
6b383a7f 3610 intel_update_watermarks(dev);
d1ebd816
BW		 3611
3612 mutex_lock(&dev->struct_mutex);
6b383a7f 3613 intel_update_fbc(dev);
d1ebd816 3614 mutex_unlock(&dev->struct_mutex);
6be4a607 3615}
1b3c7a47 3616
4f771f10
PZ		 3617static void haswell_crtc_disable(struct drm_crtc *crtc)
3618{
3619 struct drm_device *dev = crtc->dev;
3620 struct drm_i915_private *dev_priv = dev->dev_private;
3621 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3622 struct intel_encoder *encoder;
3623 int pipe = intel_crtc->pipe;
3624 int plane = intel_crtc->plane;
ad80a810 3625 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
83616634 3626 bool is_pch_port;
4f771f10
PZ		 3627
3628 if (!intel_crtc->active)
3629 return;
3630
83616634
PZ		 3631 is_pch_port = haswell_crtc_driving_pch(crtc);
3632
4f771f10
PZ		 3633 for_each_encoder_on_crtc(dev, crtc, encoder)
3634 encoder->disable(encoder);
3635
3636 intel_crtc_wait_for_pending_flips(crtc);
3637 drm_vblank_off(dev, pipe);
3638 intel_crtc_update_cursor(crtc, false);
3639
3640 intel_disable_plane(dev_priv, plane, pipe);
3641
3642 if (dev_priv->cfb_plane == plane)
3643 intel_disable_fbc(dev);
3644
3645 intel_disable_pipe(dev_priv, pipe);
3646
ad80a810 3647 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10
PZ		 3648
3649 /* Disable PF */
3650 I915_WRITE(PF_CTL(pipe), 0);
3651 I915_WRITE(PF_WIN_SZ(pipe), 0);
3652
1f544388 3653 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10
PZ		 3654
3655 for_each_encoder_on_crtc(dev, crtc, encoder)
3656 if (encoder->post_disable)
3657 encoder->post_disable(encoder);
3658
83616634
PZ		 3659 if (is_pch_port) {
3660 ironlake_fdi_disable(crtc);
8fb033d7 3661 lpt_disable_pch_transcoder(dev_priv, pipe);
83616634
PZ		 3662 intel_disable_pch_pll(intel_crtc);
3663 ironlake_fdi_pll_disable(intel_crtc);
3664 }
4f771f10
PZ		 3665
3666 intel_crtc->active = false;
3667 intel_update_watermarks(dev);
3668
3669 mutex_lock(&dev->struct_mutex);
3670 intel_update_fbc(dev);
3671 mutex_unlock(&dev->struct_mutex);
3672}
3673
ee7b9f93
JB		 3674static void ironlake_crtc_off(struct drm_crtc *crtc)
3675{
3676 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3677 intel_put_pch_pll(intel_crtc);
3678}
3679
6441ab5f
PZ		 3680static void haswell_crtc_off(struct drm_crtc *crtc)
3681{
a5c961d1
PZ		 3682 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3683
3684 /* Stop saying we're using TRANSCODER_EDP because some other CRTC might
3685 * start using it. */
3686 intel_crtc->cpu_transcoder = intel_crtc->pipe;
3687
6441ab5f
PZ		 3688 intel_ddi_put_crtc_pll(crtc);
3689}
3690
02e792fb
DV		 3691static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3692{
02e792fb 3693 if (!enable && intel_crtc->overlay) {
23f09ce3 3694 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 3695 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 3696
23f09ce3 3697 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 3698 dev_priv->mm.interruptible = false;
3699 (void) intel_overlay_switch_off(intel_crtc->overlay);
3700 dev_priv->mm.interruptible = true;
23f09ce3 3701 mutex_unlock(&dev->struct_mutex);
02e792fb 3702 }
02e792fb 3703
5dcdbcb0
CW		 3704 /* Let userspace switch the overlay on again. In most cases userspace
3705 * has to recompute where to put it anyway.
3706 */
02e792fb
DV		 3707}
3708
0b8765c6 3709static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 3710{
3711 struct drm_device *dev = crtc->dev;
79e53945
JB		 3712 struct drm_i915_private *dev_priv = dev->dev_private;
3713 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3714 struct intel_encoder *encoder;
79e53945 3715 int pipe = intel_crtc->pipe;
80824003 3716 int plane = intel_crtc->plane;
79e53945 3717
08a48469
DV		 3718 WARN_ON(!crtc->enabled);
3719
f7abfe8b
CW		 3720 if (intel_crtc->active)
3721 return;
3722
3723 intel_crtc->active = true;
6b383a7f
CW		 3724 intel_update_watermarks(dev);
3725
63d7bbe9 3726 intel_enable_pll(dev_priv, pipe);
040484af 3727 intel_enable_pipe(dev_priv, pipe, false);
b24e7179 3728 intel_enable_plane(dev_priv, plane, pipe);
79e53945 3729
0b8765c6 3730 intel_crtc_load_lut(crtc);
bed4a673 3731 intel_update_fbc(dev);
79e53945 3732
0b8765c6
JB		 3733 /* Give the overlay scaler a chance to enable if it's on this pipe */
3734 intel_crtc_dpms_overlay(intel_crtc, true);
6b383a7f 3735 intel_crtc_update_cursor(crtc, true);
ef9c3aee 3736
fa5c73b1
DV		 3737 for_each_encoder_on_crtc(dev, crtc, encoder)
3738 encoder->enable(encoder);
0b8765c6 3739}
79e53945 3740
0b8765c6
JB		 3741static void i9xx_crtc_disable(struct drm_crtc *crtc)
3742{
3743 struct drm_device *dev = crtc->dev;
3744 struct drm_i915_private *dev_priv = dev->dev_private;
3745 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3746 struct intel_encoder *encoder;
0b8765c6
JB		 3747 int pipe = intel_crtc->pipe;
3748 int plane = intel_crtc->plane;
b690e96c 3749
ef9c3aee 3750
f7abfe8b
CW		 3751 if (!intel_crtc->active)
3752 return;
3753
ea9d758d
DV		 3754 for_each_encoder_on_crtc(dev, crtc, encoder)
3755 encoder->disable(encoder);
3756
0b8765c6 3757 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 3758 intel_crtc_wait_for_pending_flips(crtc);
3759 drm_vblank_off(dev, pipe);
0b8765c6 3760 intel_crtc_dpms_overlay(intel_crtc, false);
6b383a7f 3761 intel_crtc_update_cursor(crtc, false);
0b8765c6 3762
973d04f9
CW		 3763 if (dev_priv->cfb_plane == plane)
3764 intel_disable_fbc(dev);
79e53945 3765
b24e7179 3766 intel_disable_plane(dev_priv, plane, pipe);
b24e7179 3767 intel_disable_pipe(dev_priv, pipe);
63d7bbe9 3768 intel_disable_pll(dev_priv, pipe);
0b8765c6 3769
f7abfe8b 3770 intel_crtc->active = false;
6b383a7f
CW		 3771 intel_update_fbc(dev);
3772 intel_update_watermarks(dev);
0b8765c6
JB		 3773}
3774
ee7b9f93
JB		 3775static void i9xx_crtc_off(struct drm_crtc *crtc)
3776{
3777}
3778
976f8a20
DV		 3779static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3780 bool enabled)
2c07245f
ZW		 3781{
3782 struct drm_device *dev = crtc->dev;
3783 struct drm_i915_master_private *master_priv;
3784 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3785 int pipe = intel_crtc->pipe;
79e53945
JB		 3786
3787 if (!dev->primary->master)
3788 return;
3789
3790 master_priv = dev->primary->master->driver_priv;
3791 if (!master_priv->sarea_priv)
3792 return;
3793
79e53945
JB		 3794 switch (pipe) {
3795 case 0:
3796 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3797 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3798 break;
3799 case 1:
3800 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3801 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3802 break;
3803 default:
9db4a9c7 3804 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 3805 break;
3806 }
79e53945
JB		 3807}
3808
976f8a20
DV		 3809/**
3810 * Sets the power management mode of the pipe and plane.
3811 */
3812void intel_crtc_update_dpms(struct drm_crtc *crtc)
3813{
3814 struct drm_device *dev = crtc->dev;
3815 struct drm_i915_private *dev_priv = dev->dev_private;
3816 struct intel_encoder *intel_encoder;
3817 bool enable = false;
3818
3819 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3820 enable |= intel_encoder->connectors_active;
3821
3822 if (enable)
3823 dev_priv->display.crtc_enable(crtc);
3824 else
3825 dev_priv->display.crtc_disable(crtc);
3826
3827 intel_crtc_update_sarea(crtc, enable);
3828}
3829
3830static void intel_crtc_noop(struct drm_crtc *crtc)
3831{
3832}
3833
cdd59983
CW		 3834static void intel_crtc_disable(struct drm_crtc *crtc)
3835{
cdd59983 3836 struct drm_device *dev = crtc->dev;
976f8a20 3837 struct drm_connector *connector;
ee7b9f93 3838 struct drm_i915_private *dev_priv = dev->dev_private;
cdd59983 3839
976f8a20
DV		 3840 /* crtc should still be enabled when we disable it. */
3841 WARN_ON(!crtc->enabled);
3842
3843 dev_priv->display.crtc_disable(crtc);
3844 intel_crtc_update_sarea(crtc, false);
ee7b9f93
JB		 3845 dev_priv->display.off(crtc);
3846
931872fc
CW		 3847 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3848 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
cdd59983
CW		 3849
3850 if (crtc->fb) {
3851 mutex_lock(&dev->struct_mutex);
1690e1eb 3852 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
cdd59983 3853 mutex_unlock(&dev->struct_mutex);
976f8a20
DV		 3854 crtc->fb = NULL;
3855 }
3856
3857 /* Update computed state. */
3858 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3859 if (!connector->encoder || !connector->encoder->crtc)
3860 continue;
3861
3862 if (connector->encoder->crtc != crtc)
3863 continue;
3864
3865 connector->dpms = DRM_MODE_DPMS_OFF;
3866 to_intel_encoder(connector->encoder)->connectors_active = false;
cdd59983
CW		 3867 }
3868}
3869
a261b246 3870void intel_modeset_disable(struct drm_device *dev)
79e53945 3871{
a261b246
DV		 3872 struct drm_crtc *crtc;
3873
3874 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3875 if (crtc->enabled)
3876 intel_crtc_disable(crtc);
3877 }
79e53945
JB		 3878}
3879
1f703855 3880void intel_encoder_noop(struct drm_encoder *encoder)
79e53945 3881{
7e7d76c3
JB		 3882}
3883
ea5b213a 3884void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 3885{
4ef69c7a 3886 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 3887
ea5b213a
CW		 3888 drm_encoder_cleanup(encoder);
3889 kfree(intel_encoder);
7e7d76c3
JB		 3890}
3891
5ab432ef
DV		 3892/* Simple dpms helper for encodres with just one connector, no cloning and only
3893 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3894 * state of the entire output pipe. */
3895void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 3896{
5ab432ef
DV		 3897 if (mode == DRM_MODE_DPMS_ON) {
3898 encoder->connectors_active = true;
3899
b2cabb0e 3900 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 3901 } else {
3902 encoder->connectors_active = false;
3903
b2cabb0e 3904 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 3905 }
79e53945
JB		 3906}
3907
0a91ca29
DV		 3908/* Cross check the actual hw state with our own modeset state tracking (and it's
3909 * internal consistency). */
b980514c 3910static void intel_connector_check_state(struct intel_connector *connector)
79e53945 3911{
0a91ca29
DV		 3912 if (connector->get_hw_state(connector)) {
3913 struct intel_encoder *encoder = connector->encoder;
3914 struct drm_crtc *crtc;
3915 bool encoder_enabled;
3916 enum pipe pipe;
3917
3918 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3919 connector->base.base.id,
3920 drm_get_connector_name(&connector->base));
3921
3922 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3923 "wrong connector dpms state\n");
3924 WARN(connector->base.encoder != &encoder->base,
3925 "active connector not linked to encoder\n");
3926 WARN(!encoder->connectors_active,
3927 "encoder->connectors_active not set\n");
3928
3929 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3930 WARN(!encoder_enabled, "encoder not enabled\n");
3931 if (WARN_ON(!encoder->base.crtc))
3932 return;
3933
3934 crtc = encoder->base.crtc;
3935
3936 WARN(!crtc->enabled, "crtc not enabled\n");
3937 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3938 WARN(pipe != to_intel_crtc(crtc)->pipe,
3939 "encoder active on the wrong pipe\n");
3940 }
79e53945
JB		 3941}
3942
5ab432ef
DV		 3943/* Even simpler default implementation, if there's really no special case to
3944 * consider. */
3945void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 3946{
5ab432ef 3947 struct intel_encoder *encoder = intel_attached_encoder(connector);
d4270e57 3948
5ab432ef
DV		 3949 /* All the simple cases only support two dpms states. */
3950 if (mode != DRM_MODE_DPMS_ON)
3951 mode = DRM_MODE_DPMS_OFF;
d4270e57 3952
5ab432ef
DV		 3953 if (mode == connector->dpms)
3954 return;
3955
3956 connector->dpms = mode;
3957
3958 /* Only need to change hw state when actually enabled */
3959 if (encoder->base.crtc)
3960 intel_encoder_dpms(encoder, mode);
3961 else
8af6cf88 3962 WARN_ON(encoder->connectors_active != false);
0a91ca29 3963
b980514c 3964 intel_modeset_check_state(connector->dev);
79e53945
JB		 3965}
3966
f0947c37
DV		 3967/* Simple connector->get_hw_state implementation for encoders that support only
3968 * one connector and no cloning and hence the encoder state determines the state
3969 * of the connector. */
3970bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 3971{
24929352 3972 enum pipe pipe = 0;
f0947c37 3973 struct intel_encoder *encoder = connector->encoder;
ea5b213a 3974
f0947c37 3975 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 3976}
3977
79e53945 3978static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
35313cde 3979 const struct drm_display_mode *mode,
79e53945
JB		 3980 struct drm_display_mode *adjusted_mode)
3981{
2c07245f 3982 struct drm_device *dev = crtc->dev;
89749350 3983
bad720ff 3984 if (HAS_PCH_SPLIT(dev)) {
2c07245f 3985 /* FDI link clock is fixed at 2.7G */
2377b741
JB		 3986 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3987 return false;
2c07245f 3988 }
89749350 3989
f9bef081
DV		 3990 /* All interlaced capable intel hw wants timings in frames. Note though
3991 * that intel_lvds_mode_fixup does some funny tricks with the crtc
3992 * timings, so we need to be careful not to clobber these.*/
3993 if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET))
3994 drm_mode_set_crtcinfo(adjusted_mode, 0);
89749350 3995
44f46b42
CW		 3996 /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes
3997 * with a hsync front porch of 0.
3998 */
3999 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4000 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
4001 return false;
4002
79e53945
JB		 4003 return true;
4004}
4005
25eb05fc
JB		 4006static int valleyview_get_display_clock_speed(struct drm_device *dev)
4007{
4008 return 400000; /* FIXME */
4009}
4010
e70236a8
JB		 4011static int i945_get_display_clock_speed(struct drm_device *dev)
4012{
4013 return 400000;
4014}
79e53945 4015
e70236a8 4016static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 4017{
e70236a8
JB		 4018 return 333000;
4019}
79e53945 4020
e70236a8
JB		 4021static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4022{
4023 return 200000;
4024}
79e53945 4025
e70236a8
JB		 4026static int i915gm_get_display_clock_speed(struct drm_device *dev)
4027{
4028 u16 gcfgc = 0;
79e53945 4029
e70236a8
JB		 4030 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4031
4032 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4033 return 133000;
4034 else {
4035 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4036 case GC_DISPLAY_CLOCK_333_MHZ:
4037 return 333000;
4038 default:
4039 case GC_DISPLAY_CLOCK_190_200_MHZ:
4040 return 190000;
79e53945 4041 }
e70236a8
JB		 4042 }
4043}
4044
4045static int i865_get_display_clock_speed(struct drm_device *dev)
4046{
4047 return 266000;
4048}
4049
4050static int i855_get_display_clock_speed(struct drm_device *dev)
4051{
4052 u16 hpllcc = 0;
4053 /* Assume that the hardware is in the high speed state. This
4054 * should be the default.
4055 */
4056 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4057 case GC_CLOCK_133_200:
4058 case GC_CLOCK_100_200:
4059 return 200000;
4060 case GC_CLOCK_166_250:
4061 return 250000;
4062 case GC_CLOCK_100_133:
79e53945 4063 return 133000;
e70236a8 4064 }
79e53945 4065
e70236a8
JB		 4066 /* Shouldn't happen */
4067 return 0;
4068}
79e53945 4069
e70236a8
JB		 4070static int i830_get_display_clock_speed(struct drm_device *dev)
4071{
4072 return 133000;
79e53945
JB		 4073}
4074
2c07245f
ZW		 4075struct fdi_m_n {
4076 u32 tu;
4077 u32 gmch_m;
4078 u32 gmch_n;
4079 u32 link_m;
4080 u32 link_n;
4081};
4082
4083static void
4084fdi_reduce_ratio(u32 *num, u32 *den)
4085{
4086 while (*num > 0xffffff || *den > 0xffffff) {
4087 *num >>= 1;
4088 *den >>= 1;
4089 }
4090}
4091
2c07245f 4092static void
f2b115e6
AJ		 4093ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
4094 int link_clock, struct fdi_m_n *m_n)
2c07245f 4095{
2c07245f
ZW		 4096 m_n->tu = 64; /* default size */
4097
22ed1113
CW		 4098 /* BUG_ON(pixel_clock > INT_MAX / 36); */
4099 m_n->gmch_m = bits_per_pixel * pixel_clock;
4100 m_n->gmch_n = link_clock * nlanes * 8;
2c07245f
ZW		 4101 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
4102
22ed1113
CW		 4103 m_n->link_m = pixel_clock;
4104 m_n->link_n = link_clock;
2c07245f
ZW		 4105 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
4106}
4107
a7615030
CW		 4108static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4109{
72bbe58c
KP		 4110 if (i915_panel_use_ssc >= 0)
4111 return i915_panel_use_ssc != 0;
4112 return dev_priv->lvds_use_ssc
435793df 4113 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 4114}
4115
5a354204
JB		 4116/**
4117 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
4118 * @crtc: CRTC structure
3b5c78a3 4119 * @mode: requested mode
5a354204
JB		 4120 *
4121 * A pipe may be connected to one or more outputs. Based on the depth of the
4122 * attached framebuffer, choose a good color depth to use on the pipe.
4123 *
4124 * If possible, match the pipe depth to the fb depth. In some cases, this
4125 * isn't ideal, because the connected output supports a lesser or restricted
4126 * set of depths. Resolve that here:
4127 * LVDS typically supports only 6bpc, so clamp down in that case
4128 * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
4129 * Displays may support a restricted set as well, check EDID and clamp as
4130 * appropriate.
3b5c78a3 4131 * DP may want to dither down to 6bpc to fit larger modes
5a354204
JB		 4132 *
4133 * RETURNS:
4134 * Dithering requirement (i.e. false if display bpc and pipe bpc match,
4135 * true if they don't match).
4136 */
4137static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
94352cf9 4138 struct drm_framebuffer *fb,
3b5c78a3
AJ		 4139 unsigned int *pipe_bpp,
4140 struct drm_display_mode *mode)
5a354204
JB		 4141{
4142 struct drm_device *dev = crtc->dev;
4143 struct drm_i915_private *dev_priv = dev->dev_private;
5a354204 4144 struct drm_connector *connector;
6c2b7c12 4145 struct intel_encoder *intel_encoder;
5a354204
JB		 4146 unsigned int display_bpc = UINT_MAX, bpc;
4147
4148 /* Walk the encoders & connectors on this crtc, get min bpc */
6c2b7c12 4149 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5a354204
JB		 4150
4151 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
4152 unsigned int lvds_bpc;
4153
4154 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
4155 LVDS_A3_POWER_UP)
4156 lvds_bpc = 8;
4157 else
4158 lvds_bpc = 6;
4159
4160 if (lvds_bpc < display_bpc) {
82820490 4161 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
5a354204
JB		 4162 display_bpc = lvds_bpc;
4163 }
4164 continue;
4165 }
4166
5a354204
JB		 4167 /* Not one of the known troublemakers, check the EDID */
4168 list_for_each_entry(connector, &dev->mode_config.connector_list,
4169 head) {
6c2b7c12 4170 if (connector->encoder != &intel_encoder->base)
5a354204
JB		 4171 continue;
4172
62ac41a6
JB		 4173 /* Don't use an invalid EDID bpc value */
4174 if (connector->display_info.bpc &&
4175 connector->display_info.bpc < display_bpc) {
82820490 4176 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
5a354204
JB		 4177 display_bpc = connector->display_info.bpc;
4178 }
4179 }
4180
4181 /*
4182 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
4183 * through, clamp it down. (Note: >12bpc will be caught below.)
4184 */
4185 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
4186 if (display_bpc > 8 && display_bpc < 12) {
82820490 4187 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
5a354204
JB		 4188 display_bpc = 12;
4189 } else {
82820490 4190 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
5a354204
JB		 4191 display_bpc = 8;
4192 }
4193 }
4194 }
4195
3b5c78a3
AJ		 4196 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4197 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
4198 display_bpc = 6;
4199 }
4200
5a354204
JB		 4201 /*
4202 * We could just drive the pipe at the highest bpc all the time and
4203 * enable dithering as needed, but that costs bandwidth. So choose
4204 * the minimum value that expresses the full color range of the fb but
4205 * also stays within the max display bpc discovered above.
4206 */
4207
94352cf9 4208 switch (fb->depth) {
5a354204
JB		 4209 case 8:
4210 bpc = 8; /* since we go through a colormap */
4211 break;
4212 case 15:
4213 case 16:
4214 bpc = 6; /* min is 18bpp */
4215 break;
4216 case 24:
578393cd 4217 bpc = 8;
5a354204
JB		 4218 break;
4219 case 30:
578393cd 4220 bpc = 10;
5a354204
JB		 4221 break;
4222 case 48:
578393cd 4223 bpc = 12;
5a354204
JB		 4224 break;
4225 default:
4226 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
4227 bpc = min((unsigned int)8, display_bpc);
4228 break;
4229 }
4230
578393cd
KP		 4231 display_bpc = min(display_bpc, bpc);
4232
82820490
AJ		 4233 DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
4234 bpc, display_bpc);
5a354204 4235
578393cd 4236 *pipe_bpp = display_bpc * 3;
5a354204
JB		 4237
4238 return display_bpc != bpc;
4239}
4240
a0c4da24
JB		 4241static int vlv_get_refclk(struct drm_crtc *crtc)
4242{
4243 struct drm_device *dev = crtc->dev;
4244 struct drm_i915_private *dev_priv = dev->dev_private;
4245 int refclk = 27000; /* for DP & HDMI */
4246
4247 return 100000; /* only one validated so far */
4248
4249 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4250 refclk = 96000;
4251 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4252 if (intel_panel_use_ssc(dev_priv))
4253 refclk = 100000;
4254 else
4255 refclk = 96000;
4256 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4257 refclk = 100000;
4258 }
4259
4260 return refclk;
4261}
4262
c65d77d8
JB		 4263static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4264{
4265 struct drm_device *dev = crtc->dev;
4266 struct drm_i915_private *dev_priv = dev->dev_private;
4267 int refclk;
4268
a0c4da24
JB		 4269 if (IS_VALLEYVIEW(dev)) {
4270 refclk = vlv_get_refclk(crtc);
4271 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
c65d77d8
JB		 4272 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4273 refclk = dev_priv->lvds_ssc_freq * 1000;
4274 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4275 refclk / 1000);
4276 } else if (!IS_GEN2(dev)) {
4277 refclk = 96000;
4278 } else {
4279 refclk = 48000;
4280 }
4281
4282 return refclk;
4283}
4284
4285static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
4286 intel_clock_t *clock)
4287{
4288 /* SDVO TV has fixed PLL values depend on its clock range,
4289 this mirrors vbios setting. */
4290 if (adjusted_mode->clock >= 100000
4291 && adjusted_mode->clock < 140500) {
4292 clock->p1 = 2;
4293 clock->p2 = 10;
4294 clock->n = 3;
4295 clock->m1 = 16;
4296 clock->m2 = 8;
4297 } else if (adjusted_mode->clock >= 140500
4298 && adjusted_mode->clock <= 200000) {
4299 clock->p1 = 1;
4300 clock->p2 = 10;
4301 clock->n = 6;
4302 clock->m1 = 12;
4303 clock->m2 = 8;
4304 }
4305}
4306
a7516a05
JB		 4307static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
4308 intel_clock_t *clock,
4309 intel_clock_t *reduced_clock)
4310{
4311 struct drm_device *dev = crtc->dev;
4312 struct drm_i915_private *dev_priv = dev->dev_private;
4313 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4314 int pipe = intel_crtc->pipe;
4315 u32 fp, fp2 = 0;
4316
4317 if (IS_PINEVIEW(dev)) {
4318 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
4319 if (reduced_clock)
4320 fp2 = (1 << reduced_clock->n) << 16 |
4321 reduced_clock->m1 << 8 | reduced_clock->m2;
4322 } else {
4323 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
4324 if (reduced_clock)
4325 fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
4326 reduced_clock->m2;
4327 }
4328
4329 I915_WRITE(FP0(pipe), fp);
4330
4331 intel_crtc->lowfreq_avail = false;
4332 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4333 reduced_clock && i915_powersave) {
4334 I915_WRITE(FP1(pipe), fp2);
4335 intel_crtc->lowfreq_avail = true;
4336 } else {
4337 I915_WRITE(FP1(pipe), fp);
4338 }
4339}
4340
93e537a1
DV		 4341static void intel_update_lvds(struct drm_crtc *crtc, intel_clock_t *clock,
4342 struct drm_display_mode *adjusted_mode)
4343{
4344 struct drm_device *dev = crtc->dev;
4345 struct drm_i915_private *dev_priv = dev->dev_private;
4346 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4347 int pipe = intel_crtc->pipe;
284d5df5 4348 u32 temp;
93e537a1
DV		 4349
4350 temp = I915_READ(LVDS);
4351 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
4352 if (pipe == 1) {
4353 temp |= LVDS_PIPEB_SELECT;
4354 } else {
4355 temp &= ~LVDS_PIPEB_SELECT;
4356 }
4357 /* set the corresponsding LVDS_BORDER bit */
4358 temp |= dev_priv->lvds_border_bits;
4359 /* Set the B0-B3 data pairs corresponding to whether we're going to
4360 * set the DPLLs for dual-channel mode or not.
4361 */
4362 if (clock->p2 == 7)
4363 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4364 else
4365 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4366
4367 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4368 * appropriately here, but we need to look more thoroughly into how
4369 * panels behave in the two modes.
4370 */
4371 /* set the dithering flag on LVDS as needed */
4372 if (INTEL_INFO(dev)->gen >= 4) {
4373 if (dev_priv->lvds_dither)
4374 temp |= LVDS_ENABLE_DITHER;
4375 else
4376 temp &= ~LVDS_ENABLE_DITHER;
4377 }
284d5df5 4378 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
93e537a1 4379 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
284d5df5 4380 temp |= LVDS_HSYNC_POLARITY;
93e537a1 4381 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
284d5df5 4382 temp |= LVDS_VSYNC_POLARITY;
93e537a1
DV		 4383 I915_WRITE(LVDS, temp);
4384}
4385
a0c4da24
JB		 4386static void vlv_update_pll(struct drm_crtc *crtc,
4387 struct drm_display_mode *mode,
4388 struct drm_display_mode *adjusted_mode,
4389 intel_clock_t *clock, intel_clock_t *reduced_clock,
2a8f64ca 4390 int num_connectors)
a0c4da24
JB		 4391{
4392 struct drm_device *dev = crtc->dev;
4393 struct drm_i915_private *dev_priv = dev->dev_private;
4394 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4395 int pipe = intel_crtc->pipe;
4396 u32 dpll, mdiv, pdiv;
4397 u32 bestn, bestm1, bestm2, bestp1, bestp2;
2a8f64ca
VP		 4398 bool is_sdvo;
4399 u32 temp;
4400
4401 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4402 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
a0c4da24 4403
2a8f64ca
VP		 4404 dpll = DPLL_VGA_MODE_DIS;
4405 dpll |= DPLL_EXT_BUFFER_ENABLE_VLV;
4406 dpll |= DPLL_REFA_CLK_ENABLE_VLV;
4407 dpll |= DPLL_INTEGRATED_CLOCK_VLV;
4408
4409 I915_WRITE(DPLL(pipe), dpll);
4410 POSTING_READ(DPLL(pipe));
a0c4da24
JB		 4411
4412 bestn = clock->n;
4413 bestm1 = clock->m1;
4414 bestm2 = clock->m2;
4415 bestp1 = clock->p1;
4416 bestp2 = clock->p2;
4417
2a8f64ca
VP		 4418 /*
4419 * In Valleyview PLL and program lane counter registers are exposed
4420 * through DPIO interface
4421 */
a0c4da24
JB		 4422 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4423 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4424 mdiv |= ((bestn << DPIO_N_SHIFT));
4425 mdiv |= (1 << DPIO_POST_DIV_SHIFT);
4426 mdiv |= (1 << DPIO_K_SHIFT);
4427 mdiv |= DPIO_ENABLE_CALIBRATION;
4428 intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4429
4430 intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
4431
2a8f64ca 4432 pdiv = (1 << DPIO_REFSEL_OVERRIDE) | (5 << DPIO_PLL_MODESEL_SHIFT) |
a0c4da24 4433 (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
2a8f64ca
VP		 4434 (7 << DPIO_PLL_REFCLK_SEL_SHIFT) | (8 << DPIO_DRIVER_CTL_SHIFT) |
4435 (5 << DPIO_CLK_BIAS_CTL_SHIFT);
a0c4da24
JB		 4436 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
4437
2a8f64ca 4438 intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x005f003b);
a0c4da24
JB		 4439
4440 dpll |= DPLL_VCO_ENABLE;
4441 I915_WRITE(DPLL(pipe), dpll);
4442 POSTING_READ(DPLL(pipe));
4443 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4444 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4445
2a8f64ca
VP		 4446 intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x620);
4447
4448 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4449 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4450
4451 I915_WRITE(DPLL(pipe), dpll);
4452
4453 /* Wait for the clocks to stabilize. */
4454 POSTING_READ(DPLL(pipe));
4455 udelay(150);
a0c4da24 4456
2a8f64ca
VP		 4457 temp = 0;
4458 if (is_sdvo) {
4459 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
a0c4da24
JB		 4460 if (temp > 1)
4461 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4462 else
4463 temp = 0;
a0c4da24 4464 }
2a8f64ca
VP		 4465 I915_WRITE(DPLL_MD(pipe), temp);
4466 POSTING_READ(DPLL_MD(pipe));
a0c4da24 4467
2a8f64ca
VP		 4468 /* Now program lane control registers */
4469 if(intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)
4470 || intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
4471 {
4472 temp = 0x1000C4;
4473 if(pipe == 1)
4474 temp |= (1 << 21);
4475 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL1, temp);
4476 }
4477 if(intel_pipe_has_type(crtc,INTEL_OUTPUT_EDP))
4478 {
4479 temp = 0x1000C4;
4480 if(pipe == 1)
4481 temp |= (1 << 21);
4482 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL2, temp);
4483 }
a0c4da24
JB		 4484}
4485
eb1cbe48
DV		 4486static void i9xx_update_pll(struct drm_crtc *crtc,
4487 struct drm_display_mode *mode,
4488 struct drm_display_mode *adjusted_mode,
4489 intel_clock_t *clock, intel_clock_t *reduced_clock,
4490 int num_connectors)
4491{
4492 struct drm_device *dev = crtc->dev;
4493 struct drm_i915_private *dev_priv = dev->dev_private;
4494 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4495 int pipe = intel_crtc->pipe;
4496 u32 dpll;
4497 bool is_sdvo;
4498
2a8f64ca
VP		 4499 i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4500
eb1cbe48
DV		 4501 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4502 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4503
4504 dpll = DPLL_VGA_MODE_DIS;
4505
4506 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4507 dpll |= DPLLB_MODE_LVDS;
4508 else
4509 dpll |= DPLLB_MODE_DAC_SERIAL;
4510 if (is_sdvo) {
4511 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4512 if (pixel_multiplier > 1) {
4513 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4514 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4515 }
4516 dpll |= DPLL_DVO_HIGH_SPEED;
4517 }
4518 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4519 dpll |= DPLL_DVO_HIGH_SPEED;
4520
4521 /* compute bitmask from p1 value */
4522 if (IS_PINEVIEW(dev))
4523 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4524 else {
4525 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4526 if (IS_G4X(dev) && reduced_clock)
4527 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4528 }
4529 switch (clock->p2) {
4530 case 5:
4531 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4532 break;
4533 case 7:
4534 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4535 break;
4536 case 10:
4537 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4538 break;
4539 case 14:
4540 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4541 break;
4542 }
4543 if (INTEL_INFO(dev)->gen >= 4)
4544 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4545
4546 if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4547 dpll |= PLL_REF_INPUT_TVCLKINBC;
4548 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4549 /* XXX: just matching BIOS for now */
4550 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4551 dpll |= 3;
4552 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4553 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4554 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4555 else
4556 dpll |= PLL_REF_INPUT_DREFCLK;
4557
4558 dpll |= DPLL_VCO_ENABLE;
4559 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4560 POSTING_READ(DPLL(pipe));
4561 udelay(150);
4562
4563 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4564 * This is an exception to the general rule that mode_set doesn't turn
4565 * things on.
4566 */
4567 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4568 intel_update_lvds(crtc, clock, adjusted_mode);
4569
4570 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4571 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4572
4573 I915_WRITE(DPLL(pipe), dpll);
4574
4575 /* Wait for the clocks to stabilize. */
4576 POSTING_READ(DPLL(pipe));
4577 udelay(150);
4578
4579 if (INTEL_INFO(dev)->gen >= 4) {
4580 u32 temp = 0;
4581 if (is_sdvo) {
4582 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4583 if (temp > 1)
4584 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4585 else
4586 temp = 0;
4587 }
4588 I915_WRITE(DPLL_MD(pipe), temp);
4589 } else {
4590 /* The pixel multiplier can only be updated once the
4591 * DPLL is enabled and the clocks are stable.
4592 *
4593 * So write it again.
4594 */
4595 I915_WRITE(DPLL(pipe), dpll);
4596 }
4597}
4598
4599static void i8xx_update_pll(struct drm_crtc *crtc,
4600 struct drm_display_mode *adjusted_mode,
2a8f64ca 4601 intel_clock_t *clock, intel_clock_t *reduced_clock,
eb1cbe48
DV		 4602 int num_connectors)
4603{
4604 struct drm_device *dev = crtc->dev;
4605 struct drm_i915_private *dev_priv = dev->dev_private;
4606 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4607 int pipe = intel_crtc->pipe;
4608 u32 dpll;
4609
2a8f64ca
VP		 4610 i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4611
eb1cbe48
DV		 4612 dpll = DPLL_VGA_MODE_DIS;
4613
4614 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4615 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4616 } else {
4617 if (clock->p1 == 2)
4618 dpll |= PLL_P1_DIVIDE_BY_TWO;
4619 else
4620 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4621 if (clock->p2 == 4)
4622 dpll |= PLL_P2_DIVIDE_BY_4;
4623 }
4624
4625 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4626 /* XXX: just matching BIOS for now */
4627 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4628 dpll |= 3;
4629 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4630 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4631 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4632 else
4633 dpll |= PLL_REF_INPUT_DREFCLK;
4634
4635 dpll |= DPLL_VCO_ENABLE;
4636 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4637 POSTING_READ(DPLL(pipe));
4638 udelay(150);
4639
eb1cbe48
DV		 4640 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4641 * This is an exception to the general rule that mode_set doesn't turn
4642 * things on.
4643 */
4644 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4645 intel_update_lvds(crtc, clock, adjusted_mode);
4646
5b5896e4
DV		 4647 I915_WRITE(DPLL(pipe), dpll);
4648
4649 /* Wait for the clocks to stabilize. */
4650 POSTING_READ(DPLL(pipe));
4651 udelay(150);
4652
eb1cbe48
DV		 4653 /* The pixel multiplier can only be updated once the
4654 * DPLL is enabled and the clocks are stable.
4655 *
4656 * So write it again.
4657 */
4658 I915_WRITE(DPLL(pipe), dpll);
4659}
4660
b0e77b9c
PZ		 4661static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
4662 struct drm_display_mode *mode,
4663 struct drm_display_mode *adjusted_mode)
4664{
4665 struct drm_device *dev = intel_crtc->base.dev;
4666 struct drm_i915_private *dev_priv = dev->dev_private;
4667 enum pipe pipe = intel_crtc->pipe;
fe2b8f9d 4668 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
b0e77b9c
PZ		 4669 uint32_t vsyncshift;
4670
4671 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4672 /* the chip adds 2 halflines automatically */
4673 adjusted_mode->crtc_vtotal -= 1;
4674 adjusted_mode->crtc_vblank_end -= 1;
4675 vsyncshift = adjusted_mode->crtc_hsync_start
4676 - adjusted_mode->crtc_htotal / 2;
4677 } else {
4678 vsyncshift = 0;
4679 }
4680
4681 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 4682 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 4683
fe2b8f9d 4684 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4685 (adjusted_mode->crtc_hdisplay - 1) |
4686 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 4687 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 4688 (adjusted_mode->crtc_hblank_start - 1) |
4689 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 4690 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 4691 (adjusted_mode->crtc_hsync_start - 1) |
4692 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4693
fe2b8f9d 4694 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4695 (adjusted_mode->crtc_vdisplay - 1) |
4696 ((adjusted_mode->crtc_vtotal - 1) << 16));
fe2b8f9d 4697 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c
PZ		 4698 (adjusted_mode->crtc_vblank_start - 1) |
4699 ((adjusted_mode->crtc_vblank_end - 1) << 16));
fe2b8f9d 4700 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 4701 (adjusted_mode->crtc_vsync_start - 1) |
4702 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4703
b5e508d4
PZ		 4704 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4705 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4706 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4707 * bits. */
4708 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4709 (pipe == PIPE_B || pipe == PIPE_C))
4710 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4711
b0e77b9c
PZ		 4712 /* pipesrc controls the size that is scaled from, which should
4713 * always be the user's requested size.
4714 */
4715 I915_WRITE(PIPESRC(pipe),
4716 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4717}
4718
f564048e
EA		 4719static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4720 struct drm_display_mode *mode,
4721 struct drm_display_mode *adjusted_mode,
4722 int x, int y,
94352cf9 4723 struct drm_framebuffer *fb)
79e53945
JB		 4724{
4725 struct drm_device *dev = crtc->dev;
4726 struct drm_i915_private *dev_priv = dev->dev_private;
4727 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4728 int pipe = intel_crtc->pipe;
80824003 4729 int plane = intel_crtc->plane;
c751ce4f 4730 int refclk, num_connectors = 0;
652c393a 4731 intel_clock_t clock, reduced_clock;
b0e77b9c 4732 u32 dspcntr, pipeconf;
eb1cbe48
DV		 4733 bool ok, has_reduced_clock = false, is_sdvo = false;
4734 bool is_lvds = false, is_tv = false, is_dp = false;
5eddb70b 4735 struct intel_encoder *encoder;
d4906093 4736 const intel_limit_t *limit;
5c3b82e2 4737 int ret;
79e53945 4738
6c2b7c12 4739 for_each_encoder_on_crtc(dev, crtc, encoder) {
5eddb70b 4740 switch (encoder->type) {
79e53945
JB		 4741 case INTEL_OUTPUT_LVDS:
4742 is_lvds = true;
4743 break;
4744 case INTEL_OUTPUT_SDVO:
7d57382e 4745 case INTEL_OUTPUT_HDMI:
79e53945 4746 is_sdvo = true;
5eddb70b 4747 if (encoder->needs_tv_clock)
e2f0ba97 4748 is_tv = true;
79e53945 4749 break;
79e53945
JB		 4750 case INTEL_OUTPUT_TVOUT:
4751 is_tv = true;
4752 break;
a4fc5ed6
KP		 4753 case INTEL_OUTPUT_DISPLAYPORT:
4754 is_dp = true;
4755 break;
79e53945 4756 }
43565a06 4757
c751ce4f 4758 num_connectors++;
79e53945
JB		 4759 }
4760
c65d77d8 4761 refclk = i9xx_get_refclk(crtc, num_connectors);
79e53945 4762
d4906093
ML		 4763 /*
4764 * Returns a set of divisors for the desired target clock with the given
4765 * refclk, or FALSE. The returned values represent the clock equation:
4766 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4767 */
1b894b59 4768 limit = intel_limit(crtc, refclk);
cec2f356
SP		 4769 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4770 &clock);
79e53945
JB		 4771 if (!ok) {
4772 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 4773 return -EINVAL;
79e53945
JB		 4774 }
4775
cda4b7d3 4776 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 4777 intel_crtc_update_cursor(crtc, true);
cda4b7d3 4778
ddc9003c 4779 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 4780 /*
4781 * Ensure we match the reduced clock's P to the target clock.
4782 * If the clocks don't match, we can't switch the display clock
4783 * by using the FP0/FP1. In such case we will disable the LVDS
4784 * downclock feature.
4785 */
ddc9003c 4786 has_reduced_clock = limit->find_pll(limit, crtc,
5eddb70b
CW		 4787 dev_priv->lvds_downclock,
4788 refclk,
cec2f356 4789 &clock,
5eddb70b 4790 &reduced_clock);
7026d4ac
ZW		 4791 }
4792
c65d77d8
JB		 4793 if (is_sdvo && is_tv)
4794 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
7026d4ac 4795
eb1cbe48 4796 if (IS_GEN2(dev))
2a8f64ca
VP		 4797 i8xx_update_pll(crtc, adjusted_mode, &clock,
4798 has_reduced_clock ? &reduced_clock : NULL,
4799 num_connectors);
a0c4da24 4800 else if (IS_VALLEYVIEW(dev))
2a8f64ca
VP		 4801 vlv_update_pll(crtc, mode, adjusted_mode, &clock,
4802 has_reduced_clock ? &reduced_clock : NULL,
4803 num_connectors);
79e53945 4804 else
eb1cbe48
DV		 4805 i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
4806 has_reduced_clock ? &reduced_clock : NULL,
4807 num_connectors);
79e53945
JB		 4808
4809 /* setup pipeconf */
5eddb70b 4810 pipeconf = I915_READ(PIPECONF(pipe));
79e53945
JB		 4811
4812 /* Set up the display plane register */
4813 dspcntr = DISPPLANE_GAMMA_ENABLE;
4814
929c77fb
EA		 4815 if (pipe == 0)
4816 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4817 else
4818 dspcntr |= DISPPLANE_SEL_PIPE_B;
79e53945 4819
a6c45cf0 4820 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
79e53945
JB		 4821 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4822 * core speed.
4823 *
4824 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4825 * pipe == 0 check?
4826 */
e70236a8
JB		 4827 if (mode->clock >
4828 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
5eddb70b 4829 pipeconf |= PIPECONF_DOUBLE_WIDE;
79e53945 4830 else
5eddb70b 4831 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
79e53945
JB		 4832 }
4833
3b5c78a3
AJ		 4834 /* default to 8bpc */
4835 pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
4836 if (is_dp) {
0c96c65b 4837 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
3b5c78a3
AJ		 4838 pipeconf |= PIPECONF_BPP_6 |
4839 PIPECONF_DITHER_EN |
4840 PIPECONF_DITHER_TYPE_SP;
4841 }
4842 }
4843
19c03924
GB		 4844 if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4845 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4846 pipeconf |= PIPECONF_BPP_6 |
4847 PIPECONF_ENABLE |
4848 I965_PIPECONF_ACTIVE;
4849 }
4850 }
4851
28c97730 4852 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
79e53945
JB		 4853 drm_mode_debug_printmodeline(mode);
4854
a7516a05
JB		 4855 if (HAS_PIPE_CXSR(dev)) {
4856 if (intel_crtc->lowfreq_avail) {
28c97730 4857 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
652c393a 4858 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
a7516a05 4859 } else {
28c97730 4860 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
652c393a
JB		 4861 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4862 }
4863 }
4864
617cf884 4865 pipeconf &= ~PIPECONF_INTERLACE_MASK;
dbb02575 4866 if (!IS_GEN2(dev) &&
b0e77b9c 4867 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
734b4157 4868 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
b0e77b9c 4869 else
617cf884 4870 pipeconf |= PIPECONF_PROGRESSIVE;
734b4157 4871
b0e77b9c 4872 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5eddb70b
CW		 4873
4874 /* pipesrc and dspsize control the size that is scaled from,
4875 * which should always be the user's requested size.
79e53945 4876 */
929c77fb
EA		 4877 I915_WRITE(DSPSIZE(plane),
4878 ((mode->vdisplay - 1) << 16) |
4879 (mode->hdisplay - 1));
4880 I915_WRITE(DSPPOS(plane), 0);
2c07245f 4881
f564048e
EA		 4882 I915_WRITE(PIPECONF(pipe), pipeconf);
4883 POSTING_READ(PIPECONF(pipe));
929c77fb 4884 intel_enable_pipe(dev_priv, pipe, false);
f564048e
EA		 4885
4886 intel_wait_for_vblank(dev, pipe);
4887
f564048e
EA		 4888 I915_WRITE(DSPCNTR(plane), dspcntr);
4889 POSTING_READ(DSPCNTR(plane));
4890
94352cf9 4891 ret = intel_pipe_set_base(crtc, x, y, fb);
f564048e
EA		 4892
4893 intel_update_watermarks(dev);
4894
f564048e
EA		 4895 return ret;
4896}
4897
9fb526db
KP		 4898/*
4899 * Initialize reference clocks when the driver loads
4900 */
4901void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 4902{
4903 struct drm_i915_private *dev_priv = dev->dev_private;
4904 struct drm_mode_config *mode_config = &dev->mode_config;
13d83a67 4905 struct intel_encoder *encoder;
13d83a67
JB		 4906 u32 temp;
4907 bool has_lvds = false;
199e5d79
KP		 4908 bool has_cpu_edp = false;
4909 bool has_pch_edp = false;
4910 bool has_panel = false;
99eb6a01
KP		 4911 bool has_ck505 = false;
4912 bool can_ssc = false;
13d83a67
JB		 4913
4914 /* We need to take the global config into account */
199e5d79
KP		 4915 list_for_each_entry(encoder, &mode_config->encoder_list,
4916 base.head) {
4917 switch (encoder->type) {
4918 case INTEL_OUTPUT_LVDS:
4919 has_panel = true;
4920 has_lvds = true;
4921 break;
4922 case INTEL_OUTPUT_EDP:
4923 has_panel = true;
4924 if (intel_encoder_is_pch_edp(&encoder->base))
4925 has_pch_edp = true;
4926 else
4927 has_cpu_edp = true;
4928 break;
13d83a67
JB		 4929 }
4930 }
4931
99eb6a01
KP		 4932 if (HAS_PCH_IBX(dev)) {
4933 has_ck505 = dev_priv->display_clock_mode;
4934 can_ssc = has_ck505;
4935 } else {
4936 has_ck505 = false;
4937 can_ssc = true;
4938 }
4939
4940 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4941 has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4942 has_ck505);
13d83a67
JB		 4943
4944 /* Ironlake: try to setup display ref clock before DPLL
4945 * enabling. This is only under driver's control after
4946 * PCH B stepping, previous chipset stepping should be
4947 * ignoring this setting.
4948 */
4949 temp = I915_READ(PCH_DREF_CONTROL);
4950 /* Always enable nonspread source */
4951 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 4952
99eb6a01
KP		 4953 if (has_ck505)
4954 temp |= DREF_NONSPREAD_CK505_ENABLE;
4955 else
4956 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 4957
199e5d79
KP		 4958 if (has_panel) {
4959 temp &= ~DREF_SSC_SOURCE_MASK;
4960 temp |= DREF_SSC_SOURCE_ENABLE;
13d83a67 4961
199e5d79 4962 /* SSC must be turned on before enabling the CPU output */
99eb6a01 4963 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 4964 DRM_DEBUG_KMS("Using SSC on panel\n");
13d83a67 4965 temp |= DREF_SSC1_ENABLE;
e77166b5
DV		 4966 } else
4967 temp &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 4968
4969 /* Get SSC going before enabling the outputs */
4970 I915_WRITE(PCH_DREF_CONTROL, temp);
4971 POSTING_READ(PCH_DREF_CONTROL);
4972 udelay(200);
4973
13d83a67
JB		 4974 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4975
4976 /* Enable CPU source on CPU attached eDP */
199e5d79 4977 if (has_cpu_edp) {
99eb6a01 4978 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 4979 DRM_DEBUG_KMS("Using SSC on eDP\n");
13d83a67 4980 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
199e5d79 4981 }
13d83a67
JB		 4982 else
4983 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79
KP		 4984 } else
4985 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4986
4987 I915_WRITE(PCH_DREF_CONTROL, temp);
4988 POSTING_READ(PCH_DREF_CONTROL);
4989 udelay(200);
4990 } else {
4991 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4992
4993 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4994
4995 /* Turn off CPU output */
4996 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4997
4998 I915_WRITE(PCH_DREF_CONTROL, temp);
4999 POSTING_READ(PCH_DREF_CONTROL);
5000 udelay(200);
5001
5002 /* Turn off the SSC source */
5003 temp &= ~DREF_SSC_SOURCE_MASK;
5004 temp |= DREF_SSC_SOURCE_DISABLE;
5005
5006 /* Turn off SSC1 */
5007 temp &= ~ DREF_SSC1_ENABLE;
5008
13d83a67
JB		 5009 I915_WRITE(PCH_DREF_CONTROL, temp);
5010 POSTING_READ(PCH_DREF_CONTROL);
5011 udelay(200);
5012 }
5013}
5014
d9d444cb
JB		 5015static int ironlake_get_refclk(struct drm_crtc *crtc)
5016{
5017 struct drm_device *dev = crtc->dev;
5018 struct drm_i915_private *dev_priv = dev->dev_private;
5019 struct intel_encoder *encoder;
d9d444cb
JB		 5020 struct intel_encoder *edp_encoder = NULL;
5021 int num_connectors = 0;
5022 bool is_lvds = false;
5023
6c2b7c12 5024 for_each_encoder_on_crtc(dev, crtc, encoder) {
d9d444cb
JB		 5025 switch (encoder->type) {
5026 case INTEL_OUTPUT_LVDS:
5027 is_lvds = true;
5028 break;
5029 case INTEL_OUTPUT_EDP:
5030 edp_encoder = encoder;
5031 break;
5032 }
5033 num_connectors++;
5034 }
5035
5036 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5037 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5038 dev_priv->lvds_ssc_freq);
5039 return dev_priv->lvds_ssc_freq * 1000;
5040 }
5041
5042 return 120000;
5043}
5044
c8203565
PZ		 5045static void ironlake_set_pipeconf(struct drm_crtc *crtc,
5046 struct drm_display_mode *adjusted_mode,
5047 bool dither)
5048{
5049 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5050 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5051 int pipe = intel_crtc->pipe;
5052 uint32_t val;
5053
5054 val = I915_READ(PIPECONF(pipe));
5055
5056 val &= ~PIPE_BPC_MASK;
5057 switch (intel_crtc->bpp) {
5058 case 18:
5059 val |= PIPE_6BPC;
5060 break;
5061 case 24:
5062 val |= PIPE_8BPC;
5063 break;
5064 case 30:
5065 val |= PIPE_10BPC;
5066 break;
5067 case 36:
5068 val |= PIPE_12BPC;
5069 break;
5070 default:
cc769b62
PZ		 5071 /* Case prevented by intel_choose_pipe_bpp_dither. */
5072 BUG();
c8203565
PZ		 5073 }
5074
5075 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5076 if (dither)
5077 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5078
5079 val &= ~PIPECONF_INTERLACE_MASK;
5080 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5081 val |= PIPECONF_INTERLACED_ILK;
5082 else
5083 val |= PIPECONF_PROGRESSIVE;
5084
5085 I915_WRITE(PIPECONF(pipe), val);
5086 POSTING_READ(PIPECONF(pipe));
5087}
5088
ee2b0b38
PZ		 5089static void haswell_set_pipeconf(struct drm_crtc *crtc,
5090 struct drm_display_mode *adjusted_mode,
5091 bool dither)
5092{
5093 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5094 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
702e7a56 5095 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
ee2b0b38
PZ		 5096 uint32_t val;
5097
702e7a56 5098 val = I915_READ(PIPECONF(cpu_transcoder));
ee2b0b38
PZ		 5099
5100 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5101 if (dither)
5102 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5103
5104 val &= ~PIPECONF_INTERLACE_MASK_HSW;
5105 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5106 val |= PIPECONF_INTERLACED_ILK;
5107 else
5108 val |= PIPECONF_PROGRESSIVE;
5109
702e7a56
PZ		 5110 I915_WRITE(PIPECONF(cpu_transcoder), val);
5111 POSTING_READ(PIPECONF(cpu_transcoder));
ee2b0b38
PZ		 5112}
5113
6591c6e4
PZ		 5114static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5115 struct drm_display_mode *adjusted_mode,
5116 intel_clock_t *clock,
5117 bool *has_reduced_clock,
5118 intel_clock_t *reduced_clock)
5119{
5120 struct drm_device *dev = crtc->dev;
5121 struct drm_i915_private *dev_priv = dev->dev_private;
5122 struct intel_encoder *intel_encoder;
5123 int refclk;
5124 const intel_limit_t *limit;
5125 bool ret, is_sdvo = false, is_tv = false, is_lvds = false;
5126
5127 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5128 switch (intel_encoder->type) {
5129 case INTEL_OUTPUT_LVDS:
5130 is_lvds = true;
5131 break;
5132 case INTEL_OUTPUT_SDVO:
5133 case INTEL_OUTPUT_HDMI:
5134 is_sdvo = true;
5135 if (intel_encoder->needs_tv_clock)
5136 is_tv = true;
5137 break;
5138 case INTEL_OUTPUT_TVOUT:
5139 is_tv = true;
5140 break;
5141 }
5142 }
5143
5144 refclk = ironlake_get_refclk(crtc);
5145
5146 /*
5147 * Returns a set of divisors for the desired target clock with the given
5148 * refclk, or FALSE. The returned values represent the clock equation:
5149 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5150 */
5151 limit = intel_limit(crtc, refclk);
5152 ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5153 clock);
5154 if (!ret)
5155 return false;
5156
5157 if (is_lvds && dev_priv->lvds_downclock_avail) {
5158 /*
5159 * Ensure we match the reduced clock's P to the target clock.
5160 * If the clocks don't match, we can't switch the display clock
5161 * by using the FP0/FP1. In such case we will disable the LVDS
5162 * downclock feature.
5163 */
5164 *has_reduced_clock = limit->find_pll(limit, crtc,
5165 dev_priv->lvds_downclock,
5166 refclk,
5167 clock,
5168 reduced_clock);
5169 }
5170
5171 if (is_sdvo && is_tv)
5172 i9xx_adjust_sdvo_tv_clock(adjusted_mode, clock);
5173
5174 return true;
5175}
5176
01a415fd
DV		 5177static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5178{
5179 struct drm_i915_private *dev_priv = dev->dev_private;
5180 uint32_t temp;
5181
5182 temp = I915_READ(SOUTH_CHICKEN1);
5183 if (temp & FDI_BC_BIFURCATION_SELECT)
5184 return;
5185
5186 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5187 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5188
5189 temp |= FDI_BC_BIFURCATION_SELECT;
5190 DRM_DEBUG_KMS("enabling fdi C rx\n");
5191 I915_WRITE(SOUTH_CHICKEN1, temp);
5192 POSTING_READ(SOUTH_CHICKEN1);
5193}
5194
5195static bool ironlake_check_fdi_lanes(struct intel_crtc *intel_crtc)
5196{
5197 struct drm_device *dev = intel_crtc->base.dev;
5198 struct drm_i915_private *dev_priv = dev->dev_private;
5199 struct intel_crtc *pipe_B_crtc =
5200 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5201
5202 DRM_DEBUG_KMS("checking fdi config on pipe %i, lanes %i\n",
5203 intel_crtc->pipe, intel_crtc->fdi_lanes);
5204 if (intel_crtc->fdi_lanes > 4) {
5205 DRM_DEBUG_KMS("invalid fdi lane config on pipe %i: %i lanes\n",
5206 intel_crtc->pipe, intel_crtc->fdi_lanes);
5207 /* Clamp lanes to avoid programming the hw with bogus values. */
5208 intel_crtc->fdi_lanes = 4;
5209
5210 return false;
5211 }
5212
5213 if (dev_priv->num_pipe == 2)
5214 return true;
5215
5216 switch (intel_crtc->pipe) {
5217 case PIPE_A:
5218 return true;
5219 case PIPE_B:
5220 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5221 intel_crtc->fdi_lanes > 2) {
5222 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5223 intel_crtc->pipe, intel_crtc->fdi_lanes);
5224 /* Clamp lanes to avoid programming the hw with bogus values. */
5225 intel_crtc->fdi_lanes = 2;
5226
5227 return false;
5228 }
5229
5230 if (intel_crtc->fdi_lanes > 2)
5231 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5232 else
5233 cpt_enable_fdi_bc_bifurcation(dev);
5234
5235 return true;
5236 case PIPE_C:
5237 if (!pipe_B_crtc->base.enabled || pipe_B_crtc->fdi_lanes <= 2) {
5238 if (intel_crtc->fdi_lanes > 2) {
5239 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5240 intel_crtc->pipe, intel_crtc->fdi_lanes);
5241 /* Clamp lanes to avoid programming the hw with bogus values. */
5242 intel_crtc->fdi_lanes = 2;
5243
5244 return false;
5245 }
5246 } else {
5247 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5248 return false;
5249 }
5250
5251 cpt_enable_fdi_bc_bifurcation(dev);
5252
5253 return true;
5254 default:
5255 BUG();
5256 }
5257}
5258
f48d8f23
PZ		 5259static void ironlake_set_m_n(struct drm_crtc *crtc,
5260 struct drm_display_mode *mode,
5261 struct drm_display_mode *adjusted_mode)
5262{
5263 struct drm_device *dev = crtc->dev;
5264 struct drm_i915_private *dev_priv = dev->dev_private;
5265 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
afe2fcf5 5266 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
f48d8f23
PZ		 5267 struct intel_encoder *intel_encoder, *edp_encoder = NULL;
5268 struct fdi_m_n m_n = {0};
5269 int target_clock, pixel_multiplier, lane, link_bw;
5270 bool is_dp = false, is_cpu_edp = false;
5271
5272 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5273 switch (intel_encoder->type) {
5274 case INTEL_OUTPUT_DISPLAYPORT:
5275 is_dp = true;
5276 break;
5277 case INTEL_OUTPUT_EDP:
5278 is_dp = true;
5279 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
5280 is_cpu_edp = true;
5281 edp_encoder = intel_encoder;
5282 break;
5283 }
5284 }
5285
5286 /* FDI link */
5287 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5288 lane = 0;
5289 /* CPU eDP doesn't require FDI link, so just set DP M/N
5290 according to current link config */
5291 if (is_cpu_edp) {
5292 intel_edp_link_config(edp_encoder, &lane, &link_bw);
5293 } else {
5294 /* FDI is a binary signal running at ~2.7GHz, encoding
5295 * each output octet as 10 bits. The actual frequency
5296 * is stored as a divider into a 100MHz clock, and the
5297 * mode pixel clock is stored in units of 1KHz.
5298 * Hence the bw of each lane in terms of the mode signal
5299 * is:
5300 */
5301 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5302 }
5303
5304 /* [e]DP over FDI requires target mode clock instead of link clock. */
5305 if (edp_encoder)
5306 target_clock = intel_edp_target_clock(edp_encoder, mode);
5307 else if (is_dp)
5308 target_clock = mode->clock;
5309 else
5310 target_clock = adjusted_mode->clock;
5311
5312 if (!lane) {
5313 /*
5314 * Account for spread spectrum to avoid
5315 * oversubscribing the link. Max center spread
5316 * is 2.5%; use 5% for safety's sake.
5317 */
5318 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
5319 lane = bps / (link_bw * 8) + 1;
5320 }
5321
5322 intel_crtc->fdi_lanes = lane;
5323
5324 if (pixel_multiplier > 1)
5325 link_bw *= pixel_multiplier;
5326 ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
5327 &m_n);
5328
afe2fcf5
PZ		 5329 I915_WRITE(PIPE_DATA_M1(cpu_transcoder), TU_SIZE(m_n.tu) | m_n.gmch_m);
5330 I915_WRITE(PIPE_DATA_N1(cpu_transcoder), m_n.gmch_n);
5331 I915_WRITE(PIPE_LINK_M1(cpu_transcoder), m_n.link_m);
5332 I915_WRITE(PIPE_LINK_N1(cpu_transcoder), m_n.link_n);
f48d8f23
PZ		 5333}
5334
de13a2e3
PZ		 5335static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5336 struct drm_display_mode *adjusted_mode,
5337 intel_clock_t *clock, u32 fp)
79e53945 5338{
de13a2e3 5339 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 5340 struct drm_device *dev = crtc->dev;
5341 struct drm_i915_private *dev_priv = dev->dev_private;
de13a2e3
PZ		 5342 struct intel_encoder *intel_encoder;
5343 uint32_t dpll;
5344 int factor, pixel_multiplier, num_connectors = 0;
5345 bool is_lvds = false, is_sdvo = false, is_tv = false;
5346 bool is_dp = false, is_cpu_edp = false;
79e53945 5347
de13a2e3
PZ		 5348 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5349 switch (intel_encoder->type) {
79e53945
JB		 5350 case INTEL_OUTPUT_LVDS:
5351 is_lvds = true;
5352 break;
5353 case INTEL_OUTPUT_SDVO:
7d57382e 5354 case INTEL_OUTPUT_HDMI:
79e53945 5355 is_sdvo = true;
de13a2e3 5356 if (intel_encoder->needs_tv_clock)
e2f0ba97 5357 is_tv = true;
79e53945 5358 break;
79e53945
JB		 5359 case INTEL_OUTPUT_TVOUT:
5360 is_tv = true;
5361 break;
a4fc5ed6
KP		 5362 case INTEL_OUTPUT_DISPLAYPORT:
5363 is_dp = true;
5364 break;
32f9d658 5365 case INTEL_OUTPUT_EDP:
e3aef172 5366 is_dp = true;
de13a2e3 5367 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
e3aef172 5368 is_cpu_edp = true;
32f9d658 5369 break;
79e53945 5370 }
43565a06 5371
c751ce4f 5372 num_connectors++;
79e53945
JB		 5373 }
5374
c1858123 5375 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 5376 factor = 21;
5377 if (is_lvds) {
5378 if ((intel_panel_use_ssc(dev_priv) &&
5379 dev_priv->lvds_ssc_freq == 100) ||
5380 (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
5381 factor = 25;
5382 } else if (is_sdvo && is_tv)
5383 factor = 20;
c1858123 5384
de13a2e3 5385 if (clock->m < factor * clock->n)
8febb297 5386 fp |= FP_CB_TUNE;
2c07245f 5387
5eddb70b 5388 dpll = 0;
2c07245f 5389
a07d6787
EA		 5390 if (is_lvds)
5391 dpll |= DPLLB_MODE_LVDS;
5392 else
5393 dpll |= DPLLB_MODE_DAC_SERIAL;
5394 if (is_sdvo) {
de13a2e3 5395 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
a07d6787
EA		 5396 if (pixel_multiplier > 1) {
5397 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
79e53945 5398 }
a07d6787
EA		 5399 dpll |= DPLL_DVO_HIGH_SPEED;
5400 }
e3aef172 5401 if (is_dp && !is_cpu_edp)
a07d6787 5402 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945 5403
a07d6787 5404 /* compute bitmask from p1 value */
de13a2e3 5405 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 5406 /* also FPA1 */
de13a2e3 5407 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 5408
de13a2e3 5409 switch (clock->p2) {
a07d6787
EA		 5410 case 5:
5411 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5412 break;
5413 case 7:
5414 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5415 break;
5416 case 10:
5417 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5418 break;
5419 case 14:
5420 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5421 break;
79e53945
JB		 5422 }
5423
43565a06
KH		 5424 if (is_sdvo && is_tv)
5425 dpll |= PLL_REF_INPUT_TVCLKINBC;
5426 else if (is_tv)
79e53945 5427 /* XXX: just matching BIOS for now */
43565a06 5428 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
79e53945 5429 dpll |= 3;
a7615030 5430 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 5431 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 5432 else
5433 dpll |= PLL_REF_INPUT_DREFCLK;
5434
de13a2e3
PZ		 5435 return dpll;
5436}
5437
5438static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5439 struct drm_display_mode *mode,
5440 struct drm_display_mode *adjusted_mode,
5441 int x, int y,
5442 struct drm_framebuffer *fb)
5443{
5444 struct drm_device *dev = crtc->dev;
5445 struct drm_i915_private *dev_priv = dev->dev_private;
5446 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5447 int pipe = intel_crtc->pipe;
5448 int plane = intel_crtc->plane;
5449 int num_connectors = 0;
5450 intel_clock_t clock, reduced_clock;
5451 u32 dpll, fp = 0, fp2 = 0;
e2f12b07
PZ		 5452 bool ok, has_reduced_clock = false;
5453 bool is_lvds = false, is_dp = false, is_cpu_edp = false;
de13a2e3
PZ		 5454 struct intel_encoder *encoder;
5455 u32 temp;
5456 int ret;
01a415fd 5457 bool dither, fdi_config_ok;
de13a2e3
PZ		 5458
5459 for_each_encoder_on_crtc(dev, crtc, encoder) {
5460 switch (encoder->type) {
5461 case INTEL_OUTPUT_LVDS:
5462 is_lvds = true;
5463 break;
de13a2e3
PZ		 5464 case INTEL_OUTPUT_DISPLAYPORT:
5465 is_dp = true;
5466 break;
5467 case INTEL_OUTPUT_EDP:
5468 is_dp = true;
e2f12b07 5469 if (!intel_encoder_is_pch_edp(&encoder->base))
de13a2e3
PZ		 5470 is_cpu_edp = true;
5471 break;
5472 }
5473
5474 num_connectors++;
5475 }
5476
5dc5298b
PZ		 5477 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5478 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
5479
de13a2e3
PZ		 5480 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5481 &has_reduced_clock, &reduced_clock);
5482 if (!ok) {
5483 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5484 return -EINVAL;
5485 }
5486
5487 /* Ensure that the cursor is valid for the new mode before changing... */
5488 intel_crtc_update_cursor(crtc, true);
5489
5490 /* determine panel color depth */
c8241969
JN		 5491 dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp,
5492 adjusted_mode);
de13a2e3
PZ		 5493 if (is_lvds && dev_priv->lvds_dither)
5494 dither = true;
5495
5496 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5497 if (has_reduced_clock)
5498 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5499 reduced_clock.m2;
5500
5501 dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock, fp);
5502
f7cb34d4 5503 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
79e53945
JB		 5504 drm_mode_debug_printmodeline(mode);
5505
5dc5298b
PZ		 5506 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5507 if (!is_cpu_edp) {
ee7b9f93 5508 struct intel_pch_pll *pll;
4b645f14 5509
ee7b9f93
JB		 5510 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5511 if (pll == NULL) {
5512 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5513 pipe);
4b645f14
JB		 5514 return -EINVAL;
5515 }
ee7b9f93
JB		 5516 } else
5517 intel_put_pch_pll(intel_crtc);
79e53945
JB		 5518
5519 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5520 * This is an exception to the general rule that mode_set doesn't turn
5521 * things on.
5522 */
5523 if (is_lvds) {
fae14981 5524 temp = I915_READ(PCH_LVDS);
5eddb70b 5525 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
7885d205
JB		 5526 if (HAS_PCH_CPT(dev)) {
5527 temp &= ~PORT_TRANS_SEL_MASK;
4b645f14 5528 temp |= PORT_TRANS_SEL_CPT(pipe);
7885d205
JB		 5529 } else {
5530 if (pipe == 1)
5531 temp |= LVDS_PIPEB_SELECT;
5532 else
5533 temp &= ~LVDS_PIPEB_SELECT;
5534 }
4b645f14 5535
a3e17eb8 5536 /* set the corresponsding LVDS_BORDER bit */
5eddb70b 5537 temp |= dev_priv->lvds_border_bits;
79e53945
JB		 5538 /* Set the B0-B3 data pairs corresponding to whether we're going to
5539 * set the DPLLs for dual-channel mode or not.
5540 */
5541 if (clock.p2 == 7)
5eddb70b 5542 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
79e53945 5543 else
5eddb70b 5544 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
79e53945
JB		 5545
5546 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5547 * appropriately here, but we need to look more thoroughly into how
5548 * panels behave in the two modes.
5549 */
284d5df5 5550 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
aa9b500d 5551 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
284d5df5 5552 temp |= LVDS_HSYNC_POLARITY;
aa9b500d 5553 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
284d5df5 5554 temp |= LVDS_VSYNC_POLARITY;
fae14981 5555 I915_WRITE(PCH_LVDS, temp);
79e53945 5556 }
434ed097 5557
e3aef172 5558 if (is_dp && !is_cpu_edp) {
a4fc5ed6 5559 intel_dp_set_m_n(crtc, mode, adjusted_mode);
8febb297 5560 } else {
8db9d77b 5561 /* For non-DP output, clear any trans DP clock recovery setting.*/
9db4a9c7
JB		 5562 I915_WRITE(TRANSDATA_M1(pipe), 0);
5563 I915_WRITE(TRANSDATA_N1(pipe), 0);
5564 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5565 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
8db9d77b 5566 }
79e53945 5567
ee7b9f93
JB		 5568 if (intel_crtc->pch_pll) {
5569 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5eddb70b 5570
32f9d658 5571 /* Wait for the clocks to stabilize. */
ee7b9f93 5572 POSTING_READ(intel_crtc->pch_pll->pll_reg);
32f9d658
ZW		 5573 udelay(150);
5574
8febb297
EA		 5575 /* The pixel multiplier can only be updated once the
5576 * DPLL is enabled and the clocks are stable.
5577 *
5578 * So write it again.
5579 */
ee7b9f93 5580 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
79e53945 5581 }
79e53945 5582
5eddb70b 5583 intel_crtc->lowfreq_avail = false;
ee7b9f93 5584 if (intel_crtc->pch_pll) {
4b645f14 5585 if (is_lvds && has_reduced_clock && i915_powersave) {
ee7b9f93 5586 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
4b645f14 5587 intel_crtc->lowfreq_avail = true;
4b645f14 5588 } else {
ee7b9f93 5589 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
652c393a
JB		 5590 }
5591 }
5592
b0e77b9c 5593 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
2c07245f 5594
01a415fd
DV		 5595 /* Note, this also computes intel_crtc->fdi_lanes which is used below in
5596 * ironlake_check_fdi_lanes. */
f48d8f23 5597 ironlake_set_m_n(crtc, mode, adjusted_mode);
2c07245f 5598
01a415fd
DV		 5599 fdi_config_ok = ironlake_check_fdi_lanes(intel_crtc);
5600
e3aef172 5601 if (is_cpu_edp)
8febb297 5602 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
2c07245f 5603
c8203565 5604 ironlake_set_pipeconf(crtc, adjusted_mode, dither);
79e53945 5605
9d0498a2 5606 intel_wait_for_vblank(dev, pipe);
79e53945 5607
a1f9e77e
PZ		 5608 /* Set up the display plane register */
5609 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
b24e7179 5610 POSTING_READ(DSPCNTR(plane));
79e53945 5611
94352cf9 5612 ret = intel_pipe_set_base(crtc, x, y, fb);
7662c8bd
SL		 5613
5614 intel_update_watermarks(dev);
5615
1f8eeabf
ED		 5616 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5617
01a415fd 5618 return fdi_config_ok ? ret : -EINVAL;
79e53945
JB		 5619}
5620
09b4ddf9
PZ		 5621static int haswell_crtc_mode_set(struct drm_crtc *crtc,
5622 struct drm_display_mode *mode,
5623 struct drm_display_mode *adjusted_mode,
5624 int x, int y,
5625 struct drm_framebuffer *fb)
5626{
5627 struct drm_device *dev = crtc->dev;
5628 struct drm_i915_private *dev_priv = dev->dev_private;
5629 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5630 int pipe = intel_crtc->pipe;
5631 int plane = intel_crtc->plane;
5632 int num_connectors = 0;
5633 intel_clock_t clock, reduced_clock;
5dc5298b 5634 u32 dpll = 0, fp = 0, fp2 = 0;
09b4ddf9
PZ		 5635 bool ok, has_reduced_clock = false;
5636 bool is_lvds = false, is_dp = false, is_cpu_edp = false;
5637 struct intel_encoder *encoder;
5638 u32 temp;
5639 int ret;
5640 bool dither;
5641
5642 for_each_encoder_on_crtc(dev, crtc, encoder) {
5643 switch (encoder->type) {
5644 case INTEL_OUTPUT_LVDS:
5645 is_lvds = true;
5646 break;
5647 case INTEL_OUTPUT_DISPLAYPORT:
5648 is_dp = true;
5649 break;
5650 case INTEL_OUTPUT_EDP:
5651 is_dp = true;
5652 if (!intel_encoder_is_pch_edp(&encoder->base))
5653 is_cpu_edp = true;
5654 break;
5655 }
5656
5657 num_connectors++;
5658 }
5659
a5c961d1
PZ		 5660 if (is_cpu_edp)
5661 intel_crtc->cpu_transcoder = TRANSCODER_EDP;
5662 else
5663 intel_crtc->cpu_transcoder = pipe;
5664
5dc5298b
PZ		 5665 /* We are not sure yet this won't happen. */
5666 WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n",
5667 INTEL_PCH_TYPE(dev));
5668
5669 WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
5670 num_connectors, pipe_name(pipe));
5671
702e7a56 5672 WARN_ON(I915_READ(PIPECONF(intel_crtc->cpu_transcoder)) &
1ce42920
PZ		 5673 (PIPECONF_ENABLE | I965_PIPECONF_ACTIVE));
5674
5675 WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE);
5676
6441ab5f
PZ		 5677 if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock))
5678 return -EINVAL;
5679
5dc5298b
PZ		 5680 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5681 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5682 &has_reduced_clock,
5683 &reduced_clock);
5684 if (!ok) {
5685 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5686 return -EINVAL;
5687 }
09b4ddf9
PZ		 5688 }
5689
5690 /* Ensure that the cursor is valid for the new mode before changing... */
5691 intel_crtc_update_cursor(crtc, true);
5692
5693 /* determine panel color depth */
c8241969
JN		 5694 dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp,
5695 adjusted_mode);
09b4ddf9
PZ		 5696 if (is_lvds && dev_priv->lvds_dither)
5697 dither = true;
5698
09b4ddf9
PZ		 5699 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5700 drm_mode_debug_printmodeline(mode);
5701
5dc5298b
PZ		 5702 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5703 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5704 if (has_reduced_clock)
5705 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5706 reduced_clock.m2;
5707
5708 dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock,
5709 fp);
5710
5711 /* CPU eDP is the only output that doesn't need a PCH PLL of its
5712 * own on pre-Haswell/LPT generation */
5713 if (!is_cpu_edp) {
5714 struct intel_pch_pll *pll;
5715
5716 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5717 if (pll == NULL) {
5718 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5719 pipe);
5720 return -EINVAL;
5721 }
5722 } else
5723 intel_put_pch_pll(intel_crtc);
09b4ddf9 5724
5dc5298b
PZ		 5725 /* The LVDS pin pair needs to be on before the DPLLs are
5726 * enabled. This is an exception to the general rule that
5727 * mode_set doesn't turn things on.
5728 */
5729 if (is_lvds) {
5730 temp = I915_READ(PCH_LVDS);
5731 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5732 if (HAS_PCH_CPT(dev)) {
5733 temp &= ~PORT_TRANS_SEL_MASK;
5734 temp |= PORT_TRANS_SEL_CPT(pipe);
5735 } else {
5736 if (pipe == 1)
5737 temp |= LVDS_PIPEB_SELECT;
5738 else
5739 temp &= ~LVDS_PIPEB_SELECT;
5740 }
09b4ddf9 5741
5dc5298b
PZ		 5742 /* set the corresponsding LVDS_BORDER bit */
5743 temp |= dev_priv->lvds_border_bits;
5744 /* Set the B0-B3 data pairs corresponding to whether
5745 * we're going to set the DPLLs for dual-channel mode or
5746 * not.
5747 */
5748 if (clock.p2 == 7)
5749 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
09b4ddf9 5750 else
5dc5298b
PZ		 5751 temp &= ~(LVDS_B0B3_POWER_UP |
5752 LVDS_CLKB_POWER_UP);
5753
5754 /* It would be nice to set 24 vs 18-bit mode
5755 * (LVDS_A3_POWER_UP) appropriately here, but we need to
5756 * look more thoroughly into how panels behave in the
5757 * two modes.
5758 */
5759 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5760 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5761 temp |= LVDS_HSYNC_POLARITY;
5762 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5763 temp |= LVDS_VSYNC_POLARITY;
5764 I915_WRITE(PCH_LVDS, temp);
09b4ddf9 5765 }
09b4ddf9
PZ		 5766 }
5767
5768 if (is_dp && !is_cpu_edp) {
5769 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5770 } else {
5dc5298b
PZ		 5771 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5772 /* For non-DP output, clear any trans DP clock recovery
5773 * setting.*/
5774 I915_WRITE(TRANSDATA_M1(pipe), 0);
5775 I915_WRITE(TRANSDATA_N1(pipe), 0);
5776 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5777 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
5778 }
09b4ddf9
PZ		 5779 }
5780
5781 intel_crtc->lowfreq_avail = false;
5dc5298b
PZ		 5782 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5783 if (intel_crtc->pch_pll) {
5784 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5785
5786 /* Wait for the clocks to stabilize. */
5787 POSTING_READ(intel_crtc->pch_pll->pll_reg);
5788 udelay(150);
5789
5790 /* The pixel multiplier can only be updated once the
5791 * DPLL is enabled and the clocks are stable.
5792 *
5793 * So write it again.
5794 */
5795 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5796 }
5797
5798 if (intel_crtc->pch_pll) {
5799 if (is_lvds && has_reduced_clock && i915_powersave) {
5800 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
5801 intel_crtc->lowfreq_avail = true;
5802 } else {
5803 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
5804 }
09b4ddf9
PZ		 5805 }
5806 }
5807
5808 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5809
1eb8dfec
PZ		 5810 if (!is_dp || is_cpu_edp)
5811 ironlake_set_m_n(crtc, mode, adjusted_mode);
09b4ddf9 5812
5dc5298b
PZ		 5813 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5814 if (is_cpu_edp)
5815 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
09b4ddf9 5816
ee2b0b38 5817 haswell_set_pipeconf(crtc, adjusted_mode, dither);
09b4ddf9 5818
09b4ddf9
PZ		 5819 /* Set up the display plane register */
5820 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5821 POSTING_READ(DSPCNTR(plane));
5822
5823 ret = intel_pipe_set_base(crtc, x, y, fb);
5824
5825 intel_update_watermarks(dev);
5826
5827 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5828
5829 return ret;
5830}
5831
f564048e
EA		 5832static int intel_crtc_mode_set(struct drm_crtc *crtc,
5833 struct drm_display_mode *mode,
5834 struct drm_display_mode *adjusted_mode,
5835 int x, int y,
94352cf9 5836 struct drm_framebuffer *fb)
f564048e
EA		 5837{
5838 struct drm_device *dev = crtc->dev;
5839 struct drm_i915_private *dev_priv = dev->dev_private;
9256aa19
DV		 5840 struct drm_encoder_helper_funcs *encoder_funcs;
5841 struct intel_encoder *encoder;
0b701d27
EA		 5842 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5843 int pipe = intel_crtc->pipe;
f564048e
EA		 5844 int ret;
5845
0b701d27 5846 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 5847
f564048e 5848 ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
94352cf9 5849 x, y, fb);
79e53945 5850 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 5851
9256aa19
DV		 5852 if (ret != 0)
5853 return ret;
5854
5855 for_each_encoder_on_crtc(dev, crtc, encoder) {
5856 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
5857 encoder->base.base.id,
5858 drm_get_encoder_name(&encoder->base),
5859 mode->base.id, mode->name);
5860 encoder_funcs = encoder->base.helper_private;
5861 encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
5862 }
5863
5864 return 0;
79e53945
JB		 5865}
5866
3a9627f4
WF		 5867static bool intel_eld_uptodate(struct drm_connector *connector,
5868 int reg_eldv, uint32_t bits_eldv,
5869 int reg_elda, uint32_t bits_elda,
5870 int reg_edid)
5871{
5872 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5873 uint8_t *eld = connector->eld;
5874 uint32_t i;
5875
5876 i = I915_READ(reg_eldv);
5877 i &= bits_eldv;
5878
5879 if (!eld[0])
5880 return !i;
5881
5882 if (!i)
5883 return false;
5884
5885 i = I915_READ(reg_elda);
5886 i &= ~bits_elda;
5887 I915_WRITE(reg_elda, i);
5888
5889 for (i = 0; i < eld[2]; i++)
5890 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
5891 return false;
5892
5893 return true;
5894}
5895
e0dac65e
WF		 5896static void g4x_write_eld(struct drm_connector *connector,
5897 struct drm_crtc *crtc)
5898{
5899 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5900 uint8_t *eld = connector->eld;
5901 uint32_t eldv;
5902 uint32_t len;
5903 uint32_t i;
5904
5905 i = I915_READ(G4X_AUD_VID_DID);
5906
5907 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
5908 eldv = G4X_ELDV_DEVCL_DEVBLC;
5909 else
5910 eldv = G4X_ELDV_DEVCTG;
5911
3a9627f4
WF		 5912 if (intel_eld_uptodate(connector,
5913 G4X_AUD_CNTL_ST, eldv,
5914 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
5915 G4X_HDMIW_HDMIEDID))
5916 return;
5917
e0dac65e
WF		 5918 i = I915_READ(G4X_AUD_CNTL_ST);
5919 i &= ~(eldv | G4X_ELD_ADDR);
5920 len = (i >> 9) & 0x1f; /* ELD buffer size */
5921 I915_WRITE(G4X_AUD_CNTL_ST, i);
5922
5923 if (!eld[0])
5924 return;
5925
5926 len = min_t(uint8_t, eld[2], len);
5927 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5928 for (i = 0; i < len; i++)
5929 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
5930
5931 i = I915_READ(G4X_AUD_CNTL_ST);
5932 i |= eldv;
5933 I915_WRITE(G4X_AUD_CNTL_ST, i);
5934}
5935
83358c85
WX		 5936static void haswell_write_eld(struct drm_connector *connector,
5937 struct drm_crtc *crtc)
5938{
5939 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5940 uint8_t *eld = connector->eld;
5941 struct drm_device *dev = crtc->dev;
5942 uint32_t eldv;
5943 uint32_t i;
5944 int len;
5945 int pipe = to_intel_crtc(crtc)->pipe;
5946 int tmp;
5947
5948 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
5949 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
5950 int aud_config = HSW_AUD_CFG(pipe);
5951 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
5952
5953
5954 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
5955
5956 /* Audio output enable */
5957 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
5958 tmp = I915_READ(aud_cntrl_st2);
5959 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
5960 I915_WRITE(aud_cntrl_st2, tmp);
5961
5962 /* Wait for 1 vertical blank */
5963 intel_wait_for_vblank(dev, pipe);
5964
5965 /* Set ELD valid state */
5966 tmp = I915_READ(aud_cntrl_st2);
5967 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
5968 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
5969 I915_WRITE(aud_cntrl_st2, tmp);
5970 tmp = I915_READ(aud_cntrl_st2);
5971 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
5972
5973 /* Enable HDMI mode */
5974 tmp = I915_READ(aud_config);
5975 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
5976 /* clear N_programing_enable and N_value_index */
5977 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
5978 I915_WRITE(aud_config, tmp);
5979
5980 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
5981
5982 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
5983
5984 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5985 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5986 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
5987 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5988 } else
5989 I915_WRITE(aud_config, 0);
5990
5991 if (intel_eld_uptodate(connector,
5992 aud_cntrl_st2, eldv,
5993 aud_cntl_st, IBX_ELD_ADDRESS,
5994 hdmiw_hdmiedid))
5995 return;
5996
5997 i = I915_READ(aud_cntrl_st2);
5998 i &= ~eldv;
5999 I915_WRITE(aud_cntrl_st2, i);
6000
6001 if (!eld[0])
6002 return;
6003
6004 i = I915_READ(aud_cntl_st);
6005 i &= ~IBX_ELD_ADDRESS;
6006 I915_WRITE(aud_cntl_st, i);
6007 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6008 DRM_DEBUG_DRIVER("port num:%d\n", i);
6009
6010 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6011 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6012 for (i = 0; i < len; i++)
6013 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6014
6015 i = I915_READ(aud_cntrl_st2);
6016 i |= eldv;
6017 I915_WRITE(aud_cntrl_st2, i);
6018
6019}
6020
e0dac65e
WF		 6021static void ironlake_write_eld(struct drm_connector *connector,
6022 struct drm_crtc *crtc)
6023{
6024 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6025 uint8_t *eld = connector->eld;
6026 uint32_t eldv;
6027 uint32_t i;
6028 int len;
6029 int hdmiw_hdmiedid;
b6daa025 6030 int aud_config;
e0dac65e
WF		 6031 int aud_cntl_st;
6032 int aud_cntrl_st2;
9b138a83 6033 int pipe = to_intel_crtc(crtc)->pipe;
e0dac65e 6034
b3f33cbf 6035 if (HAS_PCH_IBX(connector->dev)) {
9b138a83
WX		 6036 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6037 aud_config = IBX_AUD_CFG(pipe);
6038 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
1202b4c6 6039 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
e0dac65e 6040 } else {
9b138a83
WX		 6041 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6042 aud_config = CPT_AUD_CFG(pipe);
6043 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
1202b4c6 6044 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
e0dac65e
WF		 6045 }
6046
9b138a83 6047 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
e0dac65e
WF		 6048
6049 i = I915_READ(aud_cntl_st);
9b138a83 6050 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
e0dac65e
WF		 6051 if (!i) {
6052 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6053 /* operate blindly on all ports */
1202b4c6
WF		 6054 eldv = IBX_ELD_VALIDB;
6055 eldv |= IBX_ELD_VALIDB << 4;
6056 eldv |= IBX_ELD_VALIDB << 8;
e0dac65e
WF		 6057 } else {
6058 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
1202b4c6 6059 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
e0dac65e
WF		 6060 }
6061
3a9627f4
WF		 6062 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6063 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6064 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
b6daa025
WF		 6065 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6066 } else
6067 I915_WRITE(aud_config, 0);
e0dac65e 6068
3a9627f4
WF		 6069 if (intel_eld_uptodate(connector,
6070 aud_cntrl_st2, eldv,
6071 aud_cntl_st, IBX_ELD_ADDRESS,
6072 hdmiw_hdmiedid))
6073 return;
6074
e0dac65e
WF		 6075 i = I915_READ(aud_cntrl_st2);
6076 i &= ~eldv;
6077 I915_WRITE(aud_cntrl_st2, i);
6078
6079 if (!eld[0])
6080 return;
6081
e0dac65e 6082 i = I915_READ(aud_cntl_st);
1202b4c6 6083 i &= ~IBX_ELD_ADDRESS;
e0dac65e
WF		 6084 I915_WRITE(aud_cntl_st, i);
6085
6086 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6087 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6088 for (i = 0; i < len; i++)
6089 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6090
6091 i = I915_READ(aud_cntrl_st2);
6092 i |= eldv;
6093 I915_WRITE(aud_cntrl_st2, i);
6094}
6095
6096void intel_write_eld(struct drm_encoder *encoder,
6097 struct drm_display_mode *mode)
6098{
6099 struct drm_crtc *crtc = encoder->crtc;
6100 struct drm_connector *connector;
6101 struct drm_device *dev = encoder->dev;
6102 struct drm_i915_private *dev_priv = dev->dev_private;
6103
6104 connector = drm_select_eld(encoder, mode);
6105 if (!connector)
6106 return;
6107
6108 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6109 connector->base.id,
6110 drm_get_connector_name(connector),
6111 connector->encoder->base.id,
6112 drm_get_encoder_name(connector->encoder));
6113
6114 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6115
6116 if (dev_priv->display.write_eld)
6117 dev_priv->display.write_eld(connector, crtc);
6118}
6119
79e53945
JB		 6120/** Loads the palette/gamma unit for the CRTC with the prepared values */
6121void intel_crtc_load_lut(struct drm_crtc *crtc)
6122{
6123 struct drm_device *dev = crtc->dev;
6124 struct drm_i915_private *dev_priv = dev->dev_private;
6125 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9db4a9c7 6126 int palreg = PALETTE(intel_crtc->pipe);
79e53945
JB		 6127 int i;
6128
6129 /* The clocks have to be on to load the palette. */
aed3f09d 6130 if (!crtc->enabled || !intel_crtc->active)
79e53945
JB		 6131 return;
6132
f2b115e6 6133 /* use legacy palette for Ironlake */
bad720ff 6134 if (HAS_PCH_SPLIT(dev))
9db4a9c7 6135 palreg = LGC_PALETTE(intel_crtc->pipe);
2c07245f 6136
79e53945
JB		 6137 for (i = 0; i < 256; i++) {
6138 I915_WRITE(palreg + 4 * i,
6139 (intel_crtc->lut_r[i] << 16) |
6140 (intel_crtc->lut_g[i] << 8) |
6141 intel_crtc->lut_b[i]);
6142 }
6143}
6144
560b85bb
CW		 6145static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6146{
6147 struct drm_device *dev = crtc->dev;
6148 struct drm_i915_private *dev_priv = dev->dev_private;
6149 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6150 bool visible = base != 0;
6151 u32 cntl;
6152
6153 if (intel_crtc->cursor_visible == visible)
6154 return;
6155
9db4a9c7 6156 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 6157 if (visible) {
6158 /* On these chipsets we can only modify the base whilst
6159 * the cursor is disabled.
6160 */
9db4a9c7 6161 I915_WRITE(_CURABASE, base);
560b85bb
CW		 6162
6163 cntl &= ~(CURSOR_FORMAT_MASK);
6164 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6165 cntl |= CURSOR_ENABLE |
6166 CURSOR_GAMMA_ENABLE |
6167 CURSOR_FORMAT_ARGB;
6168 } else
6169 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 6170 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 6171
6172 intel_crtc->cursor_visible = visible;
6173}
6174
6175static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6176{
6177 struct drm_device *dev = crtc->dev;
6178 struct drm_i915_private *dev_priv = dev->dev_private;
6179 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6180 int pipe = intel_crtc->pipe;
6181 bool visible = base != 0;
6182
6183 if (intel_crtc->cursor_visible != visible) {
548f245b 6184 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 6185 if (base) {
6186 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6187 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6188 cntl |= pipe << 28; /* Connect to correct pipe */
6189 } else {
6190 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6191 cntl |= CURSOR_MODE_DISABLE;
6192 }
9db4a9c7 6193 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 6194
6195 intel_crtc->cursor_visible = visible;
6196 }
6197 /* and commit changes on next vblank */
9db4a9c7 6198 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 6199}
6200
65a21cd6
JB		 6201static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6202{
6203 struct drm_device *dev = crtc->dev;
6204 struct drm_i915_private *dev_priv = dev->dev_private;
6205 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6206 int pipe = intel_crtc->pipe;
6207 bool visible = base != 0;
6208
6209 if (intel_crtc->cursor_visible != visible) {
6210 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6211 if (base) {
6212 cntl &= ~CURSOR_MODE;
6213 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6214 } else {
6215 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6216 cntl |= CURSOR_MODE_DISABLE;
6217 }
6218 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6219
6220 intel_crtc->cursor_visible = visible;
6221 }
6222 /* and commit changes on next vblank */
6223 I915_WRITE(CURBASE_IVB(pipe), base);
6224}
6225
cda4b7d3 6226/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 6227static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6228 bool on)
cda4b7d3
CW		 6229{
6230 struct drm_device *dev = crtc->dev;
6231 struct drm_i915_private *dev_priv = dev->dev_private;
6232 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6233 int pipe = intel_crtc->pipe;
6234 int x = intel_crtc->cursor_x;
6235 int y = intel_crtc->cursor_y;
560b85bb 6236 u32 base, pos;
cda4b7d3
CW		 6237 bool visible;
6238
6239 pos = 0;
6240
6b383a7f 6241 if (on && crtc->enabled && crtc->fb) {
cda4b7d3
CW		 6242 base = intel_crtc->cursor_addr;
6243 if (x > (int) crtc->fb->width)
6244 base = 0;
6245
6246 if (y > (int) crtc->fb->height)
6247 base = 0;
6248 } else
6249 base = 0;
6250
6251 if (x < 0) {
6252 if (x + intel_crtc->cursor_width < 0)
6253 base = 0;
6254
6255 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6256 x = -x;
6257 }
6258 pos |= x << CURSOR_X_SHIFT;
6259
6260 if (y < 0) {
6261 if (y + intel_crtc->cursor_height < 0)
6262 base = 0;
6263
6264 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6265 y = -y;
6266 }
6267 pos |= y << CURSOR_Y_SHIFT;
6268
6269 visible = base != 0;
560b85bb 6270 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 6271 return;
6272
0cd83aa9 6273 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
65a21cd6
JB		 6274 I915_WRITE(CURPOS_IVB(pipe), pos);
6275 ivb_update_cursor(crtc, base);
6276 } else {
6277 I915_WRITE(CURPOS(pipe), pos);
6278 if (IS_845G(dev) || IS_I865G(dev))
6279 i845_update_cursor(crtc, base);
6280 else
6281 i9xx_update_cursor(crtc, base);
6282 }
cda4b7d3
CW		 6283}
6284
79e53945 6285static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 6286 struct drm_file *file,
79e53945
JB		 6287 uint32_t handle,
6288 uint32_t width, uint32_t height)
6289{
6290 struct drm_device *dev = crtc->dev;
6291 struct drm_i915_private *dev_priv = dev->dev_private;
6292 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 6293 struct drm_i915_gem_object *obj;
cda4b7d3 6294 uint32_t addr;
3f8bc370 6295 int ret;
79e53945 6296
79e53945
JB		 6297 /* if we want to turn off the cursor ignore width and height */
6298 if (!handle) {
28c97730 6299 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 6300 addr = 0;
05394f39 6301 obj = NULL;
5004417d 6302 mutex_lock(&dev->struct_mutex);
3f8bc370 6303 goto finish;
79e53945
JB		 6304 }
6305
6306 /* Currently we only support 64x64 cursors */
6307 if (width != 64 || height != 64) {
6308 DRM_ERROR("we currently only support 64x64 cursors\n");
6309 return -EINVAL;
6310 }
6311
05394f39 6312 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 6313 if (&obj->base == NULL)
79e53945
JB		 6314 return -ENOENT;
6315
05394f39 6316 if (obj->base.size < width * height * 4) {
79e53945 6317 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 6318 ret = -ENOMEM;
6319 goto fail;
79e53945
JB		 6320 }
6321
71acb5eb 6322 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 6323 mutex_lock(&dev->struct_mutex);
b295d1b6 6324 if (!dev_priv->info->cursor_needs_physical) {
d9e86c0e
CW		 6325 if (obj->tiling_mode) {
6326 DRM_ERROR("cursor cannot be tiled\n");
6327 ret = -EINVAL;
6328 goto fail_locked;
6329 }
6330
2da3b9b9 6331 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
e7b526bb
CW		 6332 if (ret) {
6333 DRM_ERROR("failed to move cursor bo into the GTT\n");
2da3b9b9 6334 goto fail_locked;
e7b526bb
CW		 6335 }
6336
d9e86c0e
CW		 6337 ret = i915_gem_object_put_fence(obj);
6338 if (ret) {
2da3b9b9 6339 DRM_ERROR("failed to release fence for cursor");
d9e86c0e
CW		 6340 goto fail_unpin;
6341 }
6342
05394f39 6343 addr = obj->gtt_offset;
71acb5eb 6344 } else {
6eeefaf3 6345 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 6346 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 6347 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6348 align);
71acb5eb
DA		 6349 if (ret) {
6350 DRM_ERROR("failed to attach phys object\n");
7f9872e0 6351 goto fail_locked;
71acb5eb 6352 }
05394f39 6353 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 6354 }
6355
a6c45cf0 6356 if (IS_GEN2(dev))
14b60391
JB		 6357 I915_WRITE(CURSIZE, (height << 12) | width);
6358
3f8bc370 6359 finish:
3f8bc370 6360 if (intel_crtc->cursor_bo) {
b295d1b6 6361 if (dev_priv->info->cursor_needs_physical) {
05394f39 6362 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 6363 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6364 } else
6365 i915_gem_object_unpin(intel_crtc->cursor_bo);
05394f39 6366 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 6367 }
80824003 6368
7f9872e0 6369 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 6370
6371 intel_crtc->cursor_addr = addr;
05394f39 6372 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 6373 intel_crtc->cursor_width = width;
6374 intel_crtc->cursor_height = height;
6375
6b383a7f 6376 intel_crtc_update_cursor(crtc, true);
3f8bc370 6377
79e53945 6378 return 0;
e7b526bb 6379fail_unpin:
05394f39 6380 i915_gem_object_unpin(obj);
7f9872e0 6381fail_locked:
34b8686e 6382 mutex_unlock(&dev->struct_mutex);
bc9025bd 6383fail:
05394f39 6384 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 6385 return ret;
79e53945
JB		 6386}
6387
6388static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6389{
79e53945 6390 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6391
cda4b7d3
CW		 6392 intel_crtc->cursor_x = x;
6393 intel_crtc->cursor_y = y;
652c393a 6394
6b383a7f 6395 intel_crtc_update_cursor(crtc, true);
79e53945
JB		 6396
6397 return 0;
6398}
6399
6400/** Sets the color ramps on behalf of RandR */
6401void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6402 u16 blue, int regno)
6403{
6404 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6405
6406 intel_crtc->lut_r[regno] = red >> 8;
6407 intel_crtc->lut_g[regno] = green >> 8;
6408 intel_crtc->lut_b[regno] = blue >> 8;
6409}
6410
b8c00ac5
DA		 6411void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6412 u16 *blue, int regno)
6413{
6414 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6415
6416 *red = intel_crtc->lut_r[regno] << 8;
6417 *green = intel_crtc->lut_g[regno] << 8;
6418 *blue = intel_crtc->lut_b[regno] << 8;
6419}
6420
79e53945 6421static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 6422 u16 *blue, uint32_t start, uint32_t size)
79e53945 6423{
7203425a 6424 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 6425 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6426
7203425a 6427 for (i = start; i < end; i++) {
79e53945
JB		 6428 intel_crtc->lut_r[i] = red[i] >> 8;
6429 intel_crtc->lut_g[i] = green[i] >> 8;
6430 intel_crtc->lut_b[i] = blue[i] >> 8;
6431 }
6432
6433 intel_crtc_load_lut(crtc);
6434}
6435
6436/**
6437 * Get a pipe with a simple mode set on it for doing load-based monitor
6438 * detection.
6439 *
6440 * It will be up to the load-detect code to adjust the pipe as appropriate for
c751ce4f 6441 * its requirements. The pipe will be connected to no other encoders.
79e53945 6442 *
c751ce4f 6443 * Currently this code will only succeed if there is a pipe with no encoders
79e53945
JB		 6444 * configured for it. In the future, it could choose to temporarily disable
6445 * some outputs to free up a pipe for its use.
6446 *
6447 * \return crtc, or NULL if no pipes are available.
6448 */
6449
6450/* VESA 640x480x72Hz mode to set on the pipe */
6451static struct drm_display_mode load_detect_mode = {
6452 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6453 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6454};
6455
d2dff872
CW		 6456static struct drm_framebuffer *
6457intel_framebuffer_create(struct drm_device *dev,
308e5bcb 6458 struct drm_mode_fb_cmd2 *mode_cmd,
d2dff872
CW		 6459 struct drm_i915_gem_object *obj)
6460{
6461 struct intel_framebuffer *intel_fb;
6462 int ret;
6463
6464 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6465 if (!intel_fb) {
6466 drm_gem_object_unreference_unlocked(&obj->base);
6467 return ERR_PTR(-ENOMEM);
6468 }
6469
6470 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6471 if (ret) {
6472 drm_gem_object_unreference_unlocked(&obj->base);
6473 kfree(intel_fb);
6474 return ERR_PTR(ret);
6475 }
6476
6477 return &intel_fb->base;
6478}
6479
6480static u32
6481intel_framebuffer_pitch_for_width(int width, int bpp)
6482{
6483 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6484 return ALIGN(pitch, 64);
6485}
6486
6487static u32
6488intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6489{
6490 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6491 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6492}
6493
6494static struct drm_framebuffer *
6495intel_framebuffer_create_for_mode(struct drm_device *dev,
6496 struct drm_display_mode *mode,
6497 int depth, int bpp)
6498{
6499 struct drm_i915_gem_object *obj;
308e5bcb 6500 struct drm_mode_fb_cmd2 mode_cmd;
d2dff872
CW		 6501
6502 obj = i915_gem_alloc_object(dev,
6503 intel_framebuffer_size_for_mode(mode, bpp));
6504 if (obj == NULL)
6505 return ERR_PTR(-ENOMEM);
6506
6507 mode_cmd.width = mode->hdisplay;
6508 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 6509 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6510 bpp);
5ca0c34a 6511 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 6512
6513 return intel_framebuffer_create(dev, &mode_cmd, obj);
6514}
6515
6516static struct drm_framebuffer *
6517mode_fits_in_fbdev(struct drm_device *dev,
6518 struct drm_display_mode *mode)
6519{
6520 struct drm_i915_private *dev_priv = dev->dev_private;
6521 struct drm_i915_gem_object *obj;
6522 struct drm_framebuffer *fb;
6523
6524 if (dev_priv->fbdev == NULL)
6525 return NULL;
6526
6527 obj = dev_priv->fbdev->ifb.obj;
6528 if (obj == NULL)
6529 return NULL;
6530
6531 fb = &dev_priv->fbdev->ifb.base;
01f2c773
VS		 6532 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6533 fb->bits_per_pixel))
d2dff872
CW		 6534 return NULL;
6535
01f2c773 6536 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 6537 return NULL;
6538
6539 return fb;
6540}
6541
d2434ab7 6542bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 6543 struct drm_display_mode *mode,
8261b191 6544 struct intel_load_detect_pipe *old)
79e53945
JB		 6545{
6546 struct intel_crtc *intel_crtc;
d2434ab7
DV		 6547 struct intel_encoder *intel_encoder =
6548 intel_attached_encoder(connector);
79e53945 6549 struct drm_crtc *possible_crtc;
4ef69c7a 6550 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 6551 struct drm_crtc *crtc = NULL;
6552 struct drm_device *dev = encoder->dev;
94352cf9 6553 struct drm_framebuffer *fb;
79e53945
JB		 6554 int i = -1;
6555
d2dff872
CW		 6556 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6557 connector->base.id, drm_get_connector_name(connector),
6558 encoder->base.id, drm_get_encoder_name(encoder));
6559
79e53945
JB		 6560 /*
6561 * Algorithm gets a little messy:
7a5e4805 6562 *
79e53945
JB		 6563 * - if the connector already has an assigned crtc, use it (but make
6564 * sure it's on first)
7a5e4805 6565 *
79e53945
JB		 6566 * - try to find the first unused crtc that can drive this connector,
6567 * and use that if we find one
79e53945
JB		 6568 */
6569
6570 /* See if we already have a CRTC for this connector */
6571 if (encoder->crtc) {
6572 crtc = encoder->crtc;
8261b191 6573
24218aac 6574 old->dpms_mode = connector->dpms;
8261b191
CW		 6575 old->load_detect_temp = false;
6576
6577 /* Make sure the crtc and connector are running */
24218aac
DV		 6578 if (connector->dpms != DRM_MODE_DPMS_ON)
6579 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 6580
7173188d 6581 return true;
79e53945
JB		 6582 }
6583
6584 /* Find an unused one (if possible) */
6585 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6586 i++;
6587 if (!(encoder->possible_crtcs & (1 << i)))
6588 continue;
6589 if (!possible_crtc->enabled) {
6590 crtc = possible_crtc;
6591 break;
6592 }
79e53945
JB		 6593 }
6594
6595 /*
6596 * If we didn't find an unused CRTC, don't use any.
6597 */
6598 if (!crtc) {
7173188d
CW		 6599 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6600 return false;
79e53945
JB		 6601 }
6602
fc303101
DV		 6603 intel_encoder->new_crtc = to_intel_crtc(crtc);
6604 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB		 6605
6606 intel_crtc = to_intel_crtc(crtc);
24218aac 6607 old->dpms_mode = connector->dpms;
8261b191 6608 old->load_detect_temp = true;
d2dff872 6609 old->release_fb = NULL;
79e53945 6610
6492711d
CW		 6611 if (!mode)
6612 mode = &load_detect_mode;
79e53945 6613
d2dff872
CW		 6614 /* We need a framebuffer large enough to accommodate all accesses
6615 * that the plane may generate whilst we perform load detection.
6616 * We can not rely on the fbcon either being present (we get called
6617 * during its initialisation to detect all boot displays, or it may
6618 * not even exist) or that it is large enough to satisfy the
6619 * requested mode.
6620 */
94352cf9
DV		 6621 fb = mode_fits_in_fbdev(dev, mode);
6622 if (fb == NULL) {
d2dff872 6623 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 6624 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6625 old->release_fb = fb;
d2dff872
CW		 6626 } else
6627 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 6628 if (IS_ERR(fb)) {
d2dff872 6629 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
24218aac 6630 goto fail;
79e53945 6631 }
79e53945 6632
94352cf9 6633 if (!intel_set_mode(crtc, mode, 0, 0, fb)) {
6492711d 6634 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 6635 if (old->release_fb)
6636 old->release_fb->funcs->destroy(old->release_fb);
24218aac 6637 goto fail;
79e53945 6638 }
7173188d 6639
79e53945 6640 /* let the connector get through one full cycle before testing */
9d0498a2 6641 intel_wait_for_vblank(dev, intel_crtc->pipe);
79e53945 6642
7173188d 6643 return true;
24218aac
DV		 6644fail:
6645 connector->encoder = NULL;
6646 encoder->crtc = NULL;
24218aac 6647 return false;
79e53945
JB		 6648}
6649
d2434ab7 6650void intel_release_load_detect_pipe(struct drm_connector *connector,
8261b191 6651 struct intel_load_detect_pipe *old)
79e53945 6652{
d2434ab7
DV		 6653 struct intel_encoder *intel_encoder =
6654 intel_attached_encoder(connector);
4ef69c7a 6655 struct drm_encoder *encoder = &intel_encoder->base;
79e53945 6656
d2dff872
CW		 6657 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6658 connector->base.id, drm_get_connector_name(connector),
6659 encoder->base.id, drm_get_encoder_name(encoder));
6660
8261b191 6661 if (old->load_detect_temp) {
fc303101
DV		 6662 struct drm_crtc *crtc = encoder->crtc;
6663
6664 to_intel_connector(connector)->new_encoder = NULL;
6665 intel_encoder->new_crtc = NULL;
6666 intel_set_mode(crtc, NULL, 0, 0, NULL);
d2dff872
CW		 6667
6668 if (old->release_fb)
6669 old->release_fb->funcs->destroy(old->release_fb);
6670
0622a53c 6671 return;
79e53945
JB		 6672 }
6673
c751ce4f 6674 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 6675 if (old->dpms_mode != DRM_MODE_DPMS_ON)
6676 connector->funcs->dpms(connector, old->dpms_mode);
79e53945
JB		 6677}
6678
6679/* Returns the clock of the currently programmed mode of the given pipe. */
6680static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6681{
6682 struct drm_i915_private *dev_priv = dev->dev_private;
6683 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6684 int pipe = intel_crtc->pipe;
548f245b 6685 u32 dpll = I915_READ(DPLL(pipe));
79e53945
JB		 6686 u32 fp;
6687 intel_clock_t clock;
6688
6689 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
39adb7a5 6690 fp = I915_READ(FP0(pipe));
79e53945 6691 else
39adb7a5 6692 fp = I915_READ(FP1(pipe));
79e53945
JB		 6693
6694 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 6695 if (IS_PINEVIEW(dev)) {
6696 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6697 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 6698 } else {
6699 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6700 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6701 }
6702
a6c45cf0 6703 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 6704 if (IS_PINEVIEW(dev))
6705 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6706 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 6707 else
6708 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 6709 DPLL_FPA01_P1_POST_DIV_SHIFT);
6710
6711 switch (dpll & DPLL_MODE_MASK) {
6712 case DPLLB_MODE_DAC_SERIAL:
6713 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6714 5 : 10;
6715 break;
6716 case DPLLB_MODE_LVDS:
6717 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6718 7 : 14;
6719 break;
6720 default:
28c97730 6721 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945
JB		 6722 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6723 return 0;
6724 }
6725
6726 /* XXX: Handle the 100Mhz refclk */
2177832f 6727 intel_clock(dev, 96000, &clock);
79e53945
JB		 6728 } else {
6729 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6730
6731 if (is_lvds) {
6732 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6733 DPLL_FPA01_P1_POST_DIV_SHIFT);
6734 clock.p2 = 14;
6735
6736 if ((dpll & PLL_REF_INPUT_MASK) ==
6737 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6738 /* XXX: might not be 66MHz */
2177832f 6739 intel_clock(dev, 66000, &clock);
79e53945 6740 } else
2177832f 6741 intel_clock(dev, 48000, &clock);
79e53945
JB		 6742 } else {
6743 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6744 clock.p1 = 2;
6745 else {
6746 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6747 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6748 }
6749 if (dpll & PLL_P2_DIVIDE_BY_4)
6750 clock.p2 = 4;
6751 else
6752 clock.p2 = 2;
6753
2177832f 6754 intel_clock(dev, 48000, &clock);
79e53945
JB		 6755 }
6756 }
6757
6758 /* XXX: It would be nice to validate the clocks, but we can't reuse
6759 * i830PllIsValid() because it relies on the xf86_config connector
6760 * configuration being accurate, which it isn't necessarily.
6761 */
6762
6763 return clock.dot;
6764}
6765
6766/** Returns the currently programmed mode of the given pipe. */
6767struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6768 struct drm_crtc *crtc)
6769{
548f245b 6770 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 6771 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
fe2b8f9d 6772 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
79e53945 6773 struct drm_display_mode *mode;
fe2b8f9d
PZ		 6774 int htot = I915_READ(HTOTAL(cpu_transcoder));
6775 int hsync = I915_READ(HSYNC(cpu_transcoder));
6776 int vtot = I915_READ(VTOTAL(cpu_transcoder));
6777 int vsync = I915_READ(VSYNC(cpu_transcoder));
79e53945
JB		 6778
6779 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6780 if (!mode)
6781 return NULL;
6782
6783 mode->clock = intel_crtc_clock_get(dev, crtc);
6784 mode->hdisplay = (htot & 0xffff) + 1;
6785 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6786 mode->hsync_start = (hsync & 0xffff) + 1;
6787 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6788 mode->vdisplay = (vtot & 0xffff) + 1;
6789 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6790 mode->vsync_start = (vsync & 0xffff) + 1;
6791 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6792
6793 drm_mode_set_name(mode);
79e53945
JB		 6794
6795 return mode;
6796}
6797
3dec0095 6798static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 6799{
6800 struct drm_device *dev = crtc->dev;
6801 drm_i915_private_t *dev_priv = dev->dev_private;
6802 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6803 int pipe = intel_crtc->pipe;
dbdc6479
JB		 6804 int dpll_reg = DPLL(pipe);
6805 int dpll;
652c393a 6806
bad720ff 6807 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 6808 return;
6809
6810 if (!dev_priv->lvds_downclock_avail)
6811 return;
6812
dbdc6479 6813 dpll = I915_READ(dpll_reg);
652c393a 6814 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 6815 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a 6816
8ac5a6d5 6817 assert_panel_unlocked(dev_priv, pipe);
652c393a
JB		 6818
6819 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6820 I915_WRITE(dpll_reg, dpll);
9d0498a2 6821 intel_wait_for_vblank(dev, pipe);
dbdc6479 6822
652c393a
JB		 6823 dpll = I915_READ(dpll_reg);
6824 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 6825 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a 6826 }
652c393a
JB		 6827}
6828
6829static void intel_decrease_pllclock(struct drm_crtc *crtc)
6830{
6831 struct drm_device *dev = crtc->dev;
6832 drm_i915_private_t *dev_priv = dev->dev_private;
6833 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 6834
bad720ff 6835 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 6836 return;
6837
6838 if (!dev_priv->lvds_downclock_avail)
6839 return;
6840
6841 /*
6842 * Since this is called by a timer, we should never get here in
6843 * the manual case.
6844 */
6845 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 6846 int pipe = intel_crtc->pipe;
6847 int dpll_reg = DPLL(pipe);
6848 int dpll;
f6e5b160 6849
44d98a61 6850 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 6851
8ac5a6d5 6852 assert_panel_unlocked(dev_priv, pipe);
652c393a 6853
dc257cf1 6854 dpll = I915_READ(dpll_reg);
652c393a
JB		 6855 dpll |= DISPLAY_RATE_SELECT_FPA1;
6856 I915_WRITE(dpll_reg, dpll);
9d0498a2 6857 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 6858 dpll = I915_READ(dpll_reg);
6859 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 6860 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 6861 }
6862
6863}
6864
f047e395
CW		 6865void intel_mark_busy(struct drm_device *dev)
6866{
f047e395
CW		 6867 i915_update_gfx_val(dev->dev_private);
6868}
6869
6870void intel_mark_idle(struct drm_device *dev)
652c393a 6871{
f047e395
CW		 6872}
6873
6874void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
6875{
6876 struct drm_device *dev = obj->base.dev;
652c393a 6877 struct drm_crtc *crtc;
652c393a
JB		 6878
6879 if (!i915_powersave)
6880 return;
6881
652c393a 6882 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
652c393a
JB		 6883 if (!crtc->fb)
6884 continue;
6885
f047e395
CW		 6886 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6887 intel_increase_pllclock(crtc);
652c393a 6888 }
652c393a
JB		 6889}
6890
f047e395 6891void intel_mark_fb_idle(struct drm_i915_gem_object *obj)
652c393a 6892{
f047e395
CW		 6893 struct drm_device *dev = obj->base.dev;
6894 struct drm_crtc *crtc;
652c393a 6895
f047e395 6896 if (!i915_powersave)
acb87dfb
CW		 6897 return;
6898
652c393a
JB		 6899 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6900 if (!crtc->fb)
6901 continue;
6902
f047e395
CW		 6903 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6904 intel_decrease_pllclock(crtc);
652c393a
JB		 6905 }
6906}
6907
79e53945
JB		 6908static void intel_crtc_destroy(struct drm_crtc *crtc)
6909{
6910 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 6911 struct drm_device *dev = crtc->dev;
6912 struct intel_unpin_work *work;
6913 unsigned long flags;
6914
6915 spin_lock_irqsave(&dev->event_lock, flags);
6916 work = intel_crtc->unpin_work;
6917 intel_crtc->unpin_work = NULL;
6918 spin_unlock_irqrestore(&dev->event_lock, flags);
6919
6920 if (work) {
6921 cancel_work_sync(&work->work);
6922 kfree(work);
6923 }
79e53945
JB		 6924
6925 drm_crtc_cleanup(crtc);
67e77c5a 6926
79e53945
JB		 6927 kfree(intel_crtc);
6928}
6929
6b95a207
KH		 6930static void intel_unpin_work_fn(struct work_struct *__work)
6931{
6932 struct intel_unpin_work *work =
6933 container_of(__work, struct intel_unpin_work, work);
6934
6935 mutex_lock(&work->dev->struct_mutex);
1690e1eb 6936 intel_unpin_fb_obj(work->old_fb_obj);
05394f39
CW		 6937 drm_gem_object_unreference(&work->pending_flip_obj->base);
6938 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 6939
7782de3b 6940 intel_update_fbc(work->dev);
6b95a207
KH		 6941 mutex_unlock(&work->dev->struct_mutex);
6942 kfree(work);
6943}
6944
1afe3e9d 6945static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 6946 struct drm_crtc *crtc)
6b95a207
KH		 6947{
6948 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 6949 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6950 struct intel_unpin_work *work;
05394f39 6951 struct drm_i915_gem_object *obj;
6b95a207 6952 struct drm_pending_vblank_event *e;
95cb1b02 6953 struct timeval tvbl;
6b95a207
KH		 6954 unsigned long flags;
6955
6956 /* Ignore early vblank irqs */
6957 if (intel_crtc == NULL)
6958 return;
6959
6960 spin_lock_irqsave(&dev->event_lock, flags);
6961 work = intel_crtc->unpin_work;
6962 if (work == NULL || !work->pending) {
6963 spin_unlock_irqrestore(&dev->event_lock, flags);
6964 return;
6965 }
6966
6967 intel_crtc->unpin_work = NULL;
6b95a207
KH		 6968
6969 if (work->event) {
6970 e = work->event;
49b14a5c 6971 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
0af7e4df 6972
49b14a5c
MK		 6973 e->event.tv_sec = tvbl.tv_sec;
6974 e->event.tv_usec = tvbl.tv_usec;
0af7e4df 6975
6b95a207
KH		 6976 list_add_tail(&e->base.link,
6977 &e->base.file_priv->event_list);
6978 wake_up_interruptible(&e->base.file_priv->event_wait);
6979 }
6980
0af7e4df
MK		 6981 drm_vblank_put(dev, intel_crtc->pipe);
6982
6b95a207
KH		 6983 spin_unlock_irqrestore(&dev->event_lock, flags);
6984
05394f39 6985 obj = work->old_fb_obj;
d9e86c0e 6986
e59f2bac 6987 atomic_clear_mask(1 << intel_crtc->plane,
05394f39 6988 &obj->pending_flip.counter);
d9e86c0e 6989
5bb61643 6990 wake_up(&dev_priv->pending_flip_queue);
6b95a207 6991 schedule_work(&work->work);
e5510fac
JB		 6992
6993 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 6994}
6995
1afe3e9d
JB		 6996void intel_finish_page_flip(struct drm_device *dev, int pipe)
6997{
6998 drm_i915_private_t *dev_priv = dev->dev_private;
6999 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7000
49b14a5c 7001 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7002}
7003
7004void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7005{
7006 drm_i915_private_t *dev_priv = dev->dev_private;
7007 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7008
49b14a5c 7009 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7010}
7011
6b95a207
KH		 7012void intel_prepare_page_flip(struct drm_device *dev, int plane)
7013{
7014 drm_i915_private_t *dev_priv = dev->dev_private;
7015 struct intel_crtc *intel_crtc =
7016 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7017 unsigned long flags;
7018
7019 spin_lock_irqsave(&dev->event_lock, flags);
de3f440f 7020 if (intel_crtc->unpin_work) {
4e5359cd
SF		 7021 if ((++intel_crtc->unpin_work->pending) > 1)
7022 DRM_ERROR("Prepared flip multiple times\n");
de3f440f
JB		 7023 } else {
7024 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
7025 }
6b95a207
KH		 7026 spin_unlock_irqrestore(&dev->event_lock, flags);
7027}
7028
8c9f3aaf
JB		 7029static int intel_gen2_queue_flip(struct drm_device *dev,
7030 struct drm_crtc *crtc,
7031 struct drm_framebuffer *fb,
7032 struct drm_i915_gem_object *obj)
7033{
7034 struct drm_i915_private *dev_priv = dev->dev_private;
7035 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7036 u32 flip_mask;
6d90c952 7037 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7038 int ret;
7039
6d90c952 7040 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7041 if (ret)
83d4092b 7042 goto err;
8c9f3aaf 7043
6d90c952 7044 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7045 if (ret)
83d4092b 7046 goto err_unpin;
8c9f3aaf
JB		 7047
7048 /* Can't queue multiple flips, so wait for the previous
7049 * one to finish before executing the next.
7050 */
7051 if (intel_crtc->plane)
7052 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7053 else
7054 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7055 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7056 intel_ring_emit(ring, MI_NOOP);
7057 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7058 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7059 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 7060 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952
DV		 7061 intel_ring_emit(ring, 0); /* aux display base address, unused */
7062 intel_ring_advance(ring);
83d4092b
CW		 7063 return 0;
7064
7065err_unpin:
7066 intel_unpin_fb_obj(obj);
7067err:
8c9f3aaf
JB		 7068 return ret;
7069}
7070
7071static int intel_gen3_queue_flip(struct drm_device *dev,
7072 struct drm_crtc *crtc,
7073 struct drm_framebuffer *fb,
7074 struct drm_i915_gem_object *obj)
7075{
7076 struct drm_i915_private *dev_priv = dev->dev_private;
7077 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7078 u32 flip_mask;
6d90c952 7079 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7080 int ret;
7081
6d90c952 7082 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7083 if (ret)
83d4092b 7084 goto err;
8c9f3aaf 7085
6d90c952 7086 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7087 if (ret)
83d4092b 7088 goto err_unpin;
8c9f3aaf
JB		 7089
7090 if (intel_crtc->plane)
7091 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7092 else
7093 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7094 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7095 intel_ring_emit(ring, MI_NOOP);
7096 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7097 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7098 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 7099 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952
DV		 7100 intel_ring_emit(ring, MI_NOOP);
7101
7102 intel_ring_advance(ring);
83d4092b
CW		 7103 return 0;
7104
7105err_unpin:
7106 intel_unpin_fb_obj(obj);
7107err:
8c9f3aaf
JB		 7108 return ret;
7109}
7110
7111static int intel_gen4_queue_flip(struct drm_device *dev,
7112 struct drm_crtc *crtc,
7113 struct drm_framebuffer *fb,
7114 struct drm_i915_gem_object *obj)
7115{
7116 struct drm_i915_private *dev_priv = dev->dev_private;
7117 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7118 uint32_t pf, pipesrc;
6d90c952 7119 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7120 int ret;
7121
6d90c952 7122 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7123 if (ret)
83d4092b 7124 goto err;
8c9f3aaf 7125
6d90c952 7126 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7127 if (ret)
83d4092b 7128 goto err_unpin;
8c9f3aaf
JB		 7129
7130 /* i965+ uses the linear or tiled offsets from the
7131 * Display Registers (which do not change across a page-flip)
7132 * so we need only reprogram the base address.
7133 */
6d90c952
DV		 7134 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7135 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7136 intel_ring_emit(ring, fb->pitches[0]);
c2c75131
DV		 7137 intel_ring_emit(ring,
7138 (obj->gtt_offset + intel_crtc->dspaddr_offset) |
7139 obj->tiling_mode);
8c9f3aaf
JB		 7140
7141 /* XXX Enabling the panel-fitter across page-flip is so far
7142 * untested on non-native modes, so ignore it for now.
7143 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7144 */
7145 pf = 0;
7146 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952
DV		 7147 intel_ring_emit(ring, pf | pipesrc);
7148 intel_ring_advance(ring);
83d4092b
CW		 7149 return 0;
7150
7151err_unpin:
7152 intel_unpin_fb_obj(obj);
7153err:
8c9f3aaf
JB		 7154 return ret;
7155}
7156
7157static int intel_gen6_queue_flip(struct drm_device *dev,
7158 struct drm_crtc *crtc,
7159 struct drm_framebuffer *fb,
7160 struct drm_i915_gem_object *obj)
7161{
7162 struct drm_i915_private *dev_priv = dev->dev_private;
7163 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6d90c952 7164 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7165 uint32_t pf, pipesrc;
7166 int ret;
7167
6d90c952 7168 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7169 if (ret)
83d4092b 7170 goto err;
8c9f3aaf 7171
6d90c952 7172 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7173 if (ret)
83d4092b 7174 goto err_unpin;
8c9f3aaf 7175
6d90c952
DV		 7176 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7177 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7178 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
c2c75131 7179 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
8c9f3aaf 7180
dc257cf1
DV		 7181 /* Contrary to the suggestions in the documentation,
7182 * "Enable Panel Fitter" does not seem to be required when page
7183 * flipping with a non-native mode, and worse causes a normal
7184 * modeset to fail.
7185 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7186 */
7187 pf = 0;
8c9f3aaf 7188 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952
DV		 7189 intel_ring_emit(ring, pf | pipesrc);
7190 intel_ring_advance(ring);
83d4092b
CW		 7191 return 0;
7192
7193err_unpin:
7194 intel_unpin_fb_obj(obj);
7195err:
8c9f3aaf
JB		 7196 return ret;
7197}
7198
7c9017e5
JB		 7199/*
7200 * On gen7 we currently use the blit ring because (in early silicon at least)
7201 * the render ring doesn't give us interrpts for page flip completion, which
7202 * means clients will hang after the first flip is queued. Fortunately the
7203 * blit ring generates interrupts properly, so use it instead.
7204 */
7205static int intel_gen7_queue_flip(struct drm_device *dev,
7206 struct drm_crtc *crtc,
7207 struct drm_framebuffer *fb,
7208 struct drm_i915_gem_object *obj)
7209{
7210 struct drm_i915_private *dev_priv = dev->dev_private;
7211 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7212 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
cb05d8de 7213 uint32_t plane_bit = 0;
7c9017e5
JB		 7214 int ret;
7215
7216 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7217 if (ret)
83d4092b 7218 goto err;
7c9017e5 7219
cb05d8de
DV		 7220 switch(intel_crtc->plane) {
7221 case PLANE_A:
7222 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7223 break;
7224 case PLANE_B:
7225 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7226 break;
7227 case PLANE_C:
7228 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7229 break;
7230 default:
7231 WARN_ONCE(1, "unknown plane in flip command\n");
7232 ret = -ENODEV;
ab3951eb 7233 goto err_unpin;
cb05d8de
DV		 7234 }
7235
7c9017e5
JB		 7236 ret = intel_ring_begin(ring, 4);
7237 if (ret)
83d4092b 7238 goto err_unpin;
7c9017e5 7239
cb05d8de 7240 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 7241 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
c2c75131 7242 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7c9017e5
JB		 7243 intel_ring_emit(ring, (MI_NOOP));
7244 intel_ring_advance(ring);
83d4092b
CW		 7245 return 0;
7246
7247err_unpin:
7248 intel_unpin_fb_obj(obj);
7249err:
7c9017e5
JB		 7250 return ret;
7251}
7252
8c9f3aaf
JB		 7253static int intel_default_queue_flip(struct drm_device *dev,
7254 struct drm_crtc *crtc,
7255 struct drm_framebuffer *fb,
7256 struct drm_i915_gem_object *obj)
7257{
7258 return -ENODEV;
7259}
7260
6b95a207
KH		 7261static int intel_crtc_page_flip(struct drm_crtc *crtc,
7262 struct drm_framebuffer *fb,
7263 struct drm_pending_vblank_event *event)
7264{
7265 struct drm_device *dev = crtc->dev;
7266 struct drm_i915_private *dev_priv = dev->dev_private;
7267 struct intel_framebuffer *intel_fb;
05394f39 7268 struct drm_i915_gem_object *obj;
6b95a207
KH		 7269 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7270 struct intel_unpin_work *work;
8c9f3aaf 7271 unsigned long flags;
52e68630 7272 int ret;
6b95a207 7273
e6a595d2
VS		 7274 /* Can't change pixel format via MI display flips. */
7275 if (fb->pixel_format != crtc->fb->pixel_format)
7276 return -EINVAL;
7277
7278 /*
7279 * TILEOFF/LINOFF registers can't be changed via MI display flips.
7280 * Note that pitch changes could also affect these register.
7281 */
7282 if (INTEL_INFO(dev)->gen > 3 &&
7283 (fb->offsets[0] != crtc->fb->offsets[0] ||
7284 fb->pitches[0] != crtc->fb->pitches[0]))
7285 return -EINVAL;
7286
6b95a207
KH		 7287 work = kzalloc(sizeof *work, GFP_KERNEL);
7288 if (work == NULL)
7289 return -ENOMEM;
7290
6b95a207
KH		 7291 work->event = event;
7292 work->dev = crtc->dev;
7293 intel_fb = to_intel_framebuffer(crtc->fb);
b1b87f6b 7294 work->old_fb_obj = intel_fb->obj;
6b95a207
KH		 7295 INIT_WORK(&work->work, intel_unpin_work_fn);
7296
7317c75e
JB		 7297 ret = drm_vblank_get(dev, intel_crtc->pipe);
7298 if (ret)
7299 goto free_work;
7300
6b95a207
KH		 7301 /* We borrow the event spin lock for protecting unpin_work */
7302 spin_lock_irqsave(&dev->event_lock, flags);
7303 if (intel_crtc->unpin_work) {
7304 spin_unlock_irqrestore(&dev->event_lock, flags);
7305 kfree(work);
7317c75e 7306 drm_vblank_put(dev, intel_crtc->pipe);
468f0b44
CW		 7307
7308 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 7309 return -EBUSY;
7310 }
7311 intel_crtc->unpin_work = work;
7312 spin_unlock_irqrestore(&dev->event_lock, flags);
7313
7314 intel_fb = to_intel_framebuffer(fb);
7315 obj = intel_fb->obj;
7316
79158103
CW		 7317 ret = i915_mutex_lock_interruptible(dev);
7318 if (ret)
7319 goto cleanup;
6b95a207 7320
75dfca80 7321 /* Reference the objects for the scheduled work. */
05394f39
CW		 7322 drm_gem_object_reference(&work->old_fb_obj->base);
7323 drm_gem_object_reference(&obj->base);
6b95a207
KH		 7324
7325 crtc->fb = fb;
96b099fd 7326
e1f99ce6 7327 work->pending_flip_obj = obj;
e1f99ce6 7328
4e5359cd
SF		 7329 work->enable_stall_check = true;
7330
e1f99ce6
CW		 7331 /* Block clients from rendering to the new back buffer until
7332 * the flip occurs and the object is no longer visible.
7333 */
05394f39 7334 atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
e1f99ce6 7335
8c9f3aaf
JB		 7336 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7337 if (ret)
7338 goto cleanup_pending;
6b95a207 7339
7782de3b 7340 intel_disable_fbc(dev);
f047e395 7341 intel_mark_fb_busy(obj);
6b95a207
KH		 7342 mutex_unlock(&dev->struct_mutex);
7343
e5510fac
JB		 7344 trace_i915_flip_request(intel_crtc->plane, obj);
7345
6b95a207 7346 return 0;
96b099fd 7347
8c9f3aaf
JB		 7348cleanup_pending:
7349 atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
05394f39
CW		 7350 drm_gem_object_unreference(&work->old_fb_obj->base);
7351 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 7352 mutex_unlock(&dev->struct_mutex);
7353
79158103 7354cleanup:
96b099fd
CW		 7355 spin_lock_irqsave(&dev->event_lock, flags);
7356 intel_crtc->unpin_work = NULL;
7357 spin_unlock_irqrestore(&dev->event_lock, flags);
7358
7317c75e
JB		 7359 drm_vblank_put(dev, intel_crtc->pipe);
7360free_work:
96b099fd
CW		 7361 kfree(work);
7362
7363 return ret;
6b95a207
KH		 7364}
7365
f6e5b160 7366static struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 7367 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7368 .load_lut = intel_crtc_load_lut,
976f8a20 7369 .disable = intel_crtc_noop,
f6e5b160
CW		 7370};
7371
6ed0f796 7372bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
47f1c6c9 7373{
6ed0f796
DV		 7374 struct intel_encoder *other_encoder;
7375 struct drm_crtc *crtc = &encoder->new_crtc->base;
47f1c6c9 7376
6ed0f796
DV		 7377 if (WARN_ON(!crtc))
7378 return false;
7379
7380 list_for_each_entry(other_encoder,
7381 &crtc->dev->mode_config.encoder_list,
7382 base.head) {
7383
7384 if (&other_encoder->new_crtc->base != crtc ||
7385 encoder == other_encoder)
7386 continue;
7387 else
7388 return true;
f47166d2
CW		 7389 }
7390
6ed0f796
DV		 7391 return false;
7392}
47f1c6c9 7393
50f56119
DV		 7394static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7395 struct drm_crtc *crtc)
7396{
7397 struct drm_device *dev;
7398 struct drm_crtc *tmp;
7399 int crtc_mask = 1;
47f1c6c9 7400
50f56119 7401 WARN(!crtc, "checking null crtc?\n");
47f1c6c9 7402
50f56119 7403 dev = crtc->dev;
47f1c6c9 7404
50f56119
DV		 7405 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7406 if (tmp == crtc)
7407 break;
7408 crtc_mask <<= 1;
7409 }
47f1c6c9 7410
50f56119
DV		 7411 if (encoder->possible_crtcs & crtc_mask)
7412 return true;
7413 return false;
47f1c6c9 7414}
79e53945 7415
9a935856
DV		 7416/**
7417 * intel_modeset_update_staged_output_state
7418 *
7419 * Updates the staged output configuration state, e.g. after we've read out the
7420 * current hw state.
7421 */
7422static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 7423{
9a935856
DV		 7424 struct intel_encoder *encoder;
7425 struct intel_connector *connector;
f6e5b160 7426
9a935856
DV		 7427 list_for_each_entry(connector, &dev->mode_config.connector_list,
7428 base.head) {
7429 connector->new_encoder =
7430 to_intel_encoder(connector->base.encoder);
7431 }
f6e5b160 7432
9a935856
DV		 7433 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7434 base.head) {
7435 encoder->new_crtc =
7436 to_intel_crtc(encoder->base.crtc);
7437 }
f6e5b160
CW		 7438}
7439
9a935856
DV		 7440/**
7441 * intel_modeset_commit_output_state
7442 *
7443 * This function copies the stage display pipe configuration to the real one.
7444 */
7445static void intel_modeset_commit_output_state(struct drm_device *dev)
7446{
7447 struct intel_encoder *encoder;
7448 struct intel_connector *connector;
f6e5b160 7449
9a935856
DV		 7450 list_for_each_entry(connector, &dev->mode_config.connector_list,
7451 base.head) {
7452 connector->base.encoder = &connector->new_encoder->base;
7453 }
f6e5b160 7454
9a935856
DV		 7455 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7456 base.head) {
7457 encoder->base.crtc = &encoder->new_crtc->base;
7458 }
7459}
7460
7758a113
DV		 7461static struct drm_display_mode *
7462intel_modeset_adjusted_mode(struct drm_crtc *crtc,
7463 struct drm_display_mode *mode)
ee7b9f93 7464{
7758a113
DV		 7465 struct drm_device *dev = crtc->dev;
7466 struct drm_display_mode *adjusted_mode;
7467 struct drm_encoder_helper_funcs *encoder_funcs;
7468 struct intel_encoder *encoder;
ee7b9f93 7469
7758a113
DV		 7470 adjusted_mode = drm_mode_duplicate(dev, mode);
7471 if (!adjusted_mode)
7472 return ERR_PTR(-ENOMEM);
7473
7474 /* Pass our mode to the connectors and the CRTC to give them a chance to
7475 * adjust it according to limitations or connector properties, and also
7476 * a chance to reject the mode entirely.
7477 */
7478 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7479 base.head) {
7480
7481 if (&encoder->new_crtc->base != crtc)
7482 continue;
7483 encoder_funcs = encoder->base.helper_private;
7484 if (!(encoder_funcs->mode_fixup(&encoder->base, mode,
7485 adjusted_mode))) {
7486 DRM_DEBUG_KMS("Encoder fixup failed\n");
7487 goto fail;
7488 }
ee7b9f93
JB		 7489 }
7490
7758a113
DV		 7491 if (!(intel_crtc_mode_fixup(crtc, mode, adjusted_mode))) {
7492 DRM_DEBUG_KMS("CRTC fixup failed\n");
7493 goto fail;
ee7b9f93 7494 }
7758a113
DV		 7495 DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
7496
7497 return adjusted_mode;
7498fail:
7499 drm_mode_destroy(dev, adjusted_mode);
7500 return ERR_PTR(-EINVAL);
ee7b9f93
JB		 7501}
7502
e2e1ed41
DV		 7503/* Computes which crtcs are affected and sets the relevant bits in the mask. For
7504 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7505static void
7506intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7507 unsigned *prepare_pipes, unsigned *disable_pipes)
79e53945
JB		 7508{
7509 struct intel_crtc *intel_crtc;
e2e1ed41
DV		 7510 struct drm_device *dev = crtc->dev;
7511 struct intel_encoder *encoder;
7512 struct intel_connector *connector;
7513 struct drm_crtc *tmp_crtc;
79e53945 7514
e2e1ed41 7515 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
79e53945 7516
e2e1ed41
DV		 7517 /* Check which crtcs have changed outputs connected to them, these need
7518 * to be part of the prepare_pipes mask. We don't (yet) support global
7519 * modeset across multiple crtcs, so modeset_pipes will only have one
7520 * bit set at most. */
7521 list_for_each_entry(connector, &dev->mode_config.connector_list,
7522 base.head) {
7523 if (connector->base.encoder == &connector->new_encoder->base)
7524 continue;
79e53945 7525
e2e1ed41
DV		 7526 if (connector->base.encoder) {
7527 tmp_crtc = connector->base.encoder->crtc;
7528
7529 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7530 }
7531
7532 if (connector->new_encoder)
7533 *prepare_pipes |=
7534 1 << connector->new_encoder->new_crtc->pipe;
79e53945
JB		 7535 }
7536
e2e1ed41
DV		 7537 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7538 base.head) {
7539 if (encoder->base.crtc == &encoder->new_crtc->base)
7540 continue;
7541
7542 if (encoder->base.crtc) {
7543 tmp_crtc = encoder->base.crtc;
7544
7545 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7546 }
7547
7548 if (encoder->new_crtc)
7549 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
80824003
JB		 7550 }
7551
e2e1ed41
DV		 7552 /* Check for any pipes that will be fully disabled ... */
7553 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7554 base.head) {
7555 bool used = false;
22fd0fab 7556
e2e1ed41
DV		 7557 /* Don't try to disable disabled crtcs. */
7558 if (!intel_crtc->base.enabled)
7559 continue;
7e7d76c3 7560
e2e1ed41
DV		 7561 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7562 base.head) {
7563 if (encoder->new_crtc == intel_crtc)
7564 used = true;
7565 }
7566
7567 if (!used)
7568 *disable_pipes |= 1 << intel_crtc->pipe;
7e7d76c3
JB		 7569 }
7570
e2e1ed41
DV		 7571
7572 /* set_mode is also used to update properties on life display pipes. */
7573 intel_crtc = to_intel_crtc(crtc);
7574 if (crtc->enabled)
7575 *prepare_pipes |= 1 << intel_crtc->pipe;
7576
7577 /* We only support modeset on one single crtc, hence we need to do that
7578 * only for the passed in crtc iff we change anything else than just
7579 * disable crtcs.
7580 *
7581 * This is actually not true, to be fully compatible with the old crtc
7582 * helper we automatically disable _any_ output (i.e. doesn't need to be
7583 * connected to the crtc we're modesetting on) if it's disconnected.
7584 * Which is a rather nutty api (since changed the output configuration
7585 * without userspace's explicit request can lead to confusion), but
7586 * alas. Hence we currently need to modeset on all pipes we prepare. */
7587 if (*prepare_pipes)
7588 *modeset_pipes = *prepare_pipes;
7589
7590 /* ... and mask these out. */
7591 *modeset_pipes &= ~(*disable_pipes);
7592 *prepare_pipes &= ~(*disable_pipes);
7593}
7594
ea9d758d
DV		 7595static bool intel_crtc_in_use(struct drm_crtc *crtc)
7596{
7597 struct drm_encoder *encoder;
7598 struct drm_device *dev = crtc->dev;
7599
7600 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7601 if (encoder->crtc == crtc)
7602 return true;
7603
7604 return false;
7605}
7606
7607static void
7608intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
7609{
7610 struct intel_encoder *intel_encoder;
7611 struct intel_crtc *intel_crtc;
7612 struct drm_connector *connector;
7613
7614 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
7615 base.head) {
7616 if (!intel_encoder->base.crtc)
7617 continue;
7618
7619 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
7620
7621 if (prepare_pipes & (1 << intel_crtc->pipe))
7622 intel_encoder->connectors_active = false;
7623 }
7624
7625 intel_modeset_commit_output_state(dev);
7626
7627 /* Update computed state. */
7628 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7629 base.head) {
7630 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
7631 }
7632
7633 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7634 if (!connector->encoder || !connector->encoder->crtc)
7635 continue;
7636
7637 intel_crtc = to_intel_crtc(connector->encoder->crtc);
7638
7639 if (prepare_pipes & (1 << intel_crtc->pipe)) {
68d34720
DV		 7640 struct drm_property *dpms_property =
7641 dev->mode_config.dpms_property;
7642
ea9d758d 7643 connector->dpms = DRM_MODE_DPMS_ON;
68d34720
DV		 7644 drm_connector_property_set_value(connector,
7645 dpms_property,
7646 DRM_MODE_DPMS_ON);
ea9d758d
DV		 7647
7648 intel_encoder = to_intel_encoder(connector->encoder);
7649 intel_encoder->connectors_active = true;
7650 }
7651 }
7652
7653}
7654
25c5b266
DV		 7655#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
7656 list_for_each_entry((intel_crtc), \
7657 &(dev)->mode_config.crtc_list, \
7658 base.head) \
7659 if (mask & (1 <<(intel_crtc)->pipe)) \
7660
b980514c 7661void
8af6cf88
DV		 7662intel_modeset_check_state(struct drm_device *dev)
7663{
7664 struct intel_crtc *crtc;
7665 struct intel_encoder *encoder;
7666 struct intel_connector *connector;
7667
7668 list_for_each_entry(connector, &dev->mode_config.connector_list,
7669 base.head) {
7670 /* This also checks the encoder/connector hw state with the
7671 * ->get_hw_state callbacks. */
7672 intel_connector_check_state(connector);
7673
7674 WARN(&connector->new_encoder->base != connector->base.encoder,
7675 "connector's staged encoder doesn't match current encoder\n");
7676 }
7677
7678 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7679 base.head) {
7680 bool enabled = false;
7681 bool active = false;
7682 enum pipe pipe, tracked_pipe;
7683
7684 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
7685 encoder->base.base.id,
7686 drm_get_encoder_name(&encoder->base));
7687
7688 WARN(&encoder->new_crtc->base != encoder->base.crtc,
7689 "encoder's stage crtc doesn't match current crtc\n");
7690 WARN(encoder->connectors_active && !encoder->base.crtc,
7691 "encoder's active_connectors set, but no crtc\n");
7692
7693 list_for_each_entry(connector, &dev->mode_config.connector_list,
7694 base.head) {
7695 if (connector->base.encoder != &encoder->base)
7696 continue;
7697 enabled = true;
7698 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
7699 active = true;
7700 }
7701 WARN(!!encoder->base.crtc != enabled,
7702 "encoder's enabled state mismatch "
7703 "(expected %i, found %i)\n",
7704 !!encoder->base.crtc, enabled);
7705 WARN(active && !encoder->base.crtc,
7706 "active encoder with no crtc\n");
7707
7708 WARN(encoder->connectors_active != active,
7709 "encoder's computed active state doesn't match tracked active state "
7710 "(expected %i, found %i)\n", active, encoder->connectors_active);
7711
7712 active = encoder->get_hw_state(encoder, &pipe);
7713 WARN(active != encoder->connectors_active,
7714 "encoder's hw state doesn't match sw tracking "
7715 "(expected %i, found %i)\n",
7716 encoder->connectors_active, active);
7717
7718 if (!encoder->base.crtc)
7719 continue;
7720
7721 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
7722 WARN(active && pipe != tracked_pipe,
7723 "active encoder's pipe doesn't match"
7724 "(expected %i, found %i)\n",
7725 tracked_pipe, pipe);
7726
7727 }
7728
7729 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
7730 base.head) {
7731 bool enabled = false;
7732 bool active = false;
7733
7734 DRM_DEBUG_KMS("[CRTC:%d]\n",
7735 crtc->base.base.id);
7736
7737 WARN(crtc->active && !crtc->base.enabled,
7738 "active crtc, but not enabled in sw tracking\n");
7739
7740 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7741 base.head) {
7742 if (encoder->base.crtc != &crtc->base)
7743 continue;
7744 enabled = true;
7745 if (encoder->connectors_active)
7746 active = true;
7747 }
7748 WARN(active != crtc->active,
7749 "crtc's computed active state doesn't match tracked active state "
7750 "(expected %i, found %i)\n", active, crtc->active);
7751 WARN(enabled != crtc->base.enabled,
7752 "crtc's computed enabled state doesn't match tracked enabled state "
7753 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
7754
7755 assert_pipe(dev->dev_private, crtc->pipe, crtc->active);
7756 }
7757}
7758
a6778b3c
DV		 7759bool intel_set_mode(struct drm_crtc *crtc,
7760 struct drm_display_mode *mode,
94352cf9 7761 int x, int y, struct drm_framebuffer *fb)
a6778b3c
DV		 7762{
7763 struct drm_device *dev = crtc->dev;
dbf2b54e 7764 drm_i915_private_t *dev_priv = dev->dev_private;
a6778b3c 7765 struct drm_display_mode *adjusted_mode, saved_mode, saved_hwmode;
25c5b266
DV		 7766 struct intel_crtc *intel_crtc;
7767 unsigned disable_pipes, prepare_pipes, modeset_pipes;
a6778b3c
DV		 7768 bool ret = true;
7769
e2e1ed41 7770 intel_modeset_affected_pipes(crtc, &modeset_pipes,
25c5b266
DV		 7771 &prepare_pipes, &disable_pipes);
7772
7773 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7774 modeset_pipes, prepare_pipes, disable_pipes);
e2e1ed41 7775
976f8a20
DV		 7776 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
7777 intel_crtc_disable(&intel_crtc->base);
87f1faa6 7778
a6778b3c
DV		 7779 saved_hwmode = crtc->hwmode;
7780 saved_mode = crtc->mode;
a6778b3c 7781
25c5b266
DV		 7782 /* Hack: Because we don't (yet) support global modeset on multiple
7783 * crtcs, we don't keep track of the new mode for more than one crtc.
7784 * Hence simply check whether any bit is set in modeset_pipes in all the
7785 * pieces of code that are not yet converted to deal with mutliple crtcs
7786 * changing their mode at the same time. */
7787 adjusted_mode = NULL;
7788 if (modeset_pipes) {
7789 adjusted_mode = intel_modeset_adjusted_mode(crtc, mode);
7790 if (IS_ERR(adjusted_mode)) {
7791 return false;
7792 }
25c5b266 7793 }
a6778b3c 7794
ea9d758d
DV		 7795 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
7796 if (intel_crtc->base.enabled)
7797 dev_priv->display.crtc_disable(&intel_crtc->base);
7798 }
a6778b3c 7799
6c4c86f5
DV		 7800 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
7801 * to set it here already despite that we pass it down the callchain.
7802 */
7803 if (modeset_pipes)
25c5b266 7804 crtc->mode = *mode;
7758a113 7805
ea9d758d
DV		 7806 /* Only after disabling all output pipelines that will be changed can we
7807 * update the the output configuration. */
7808 intel_modeset_update_state(dev, prepare_pipes);
7809
47fab737
DV		 7810 if (dev_priv->display.modeset_global_resources)
7811 dev_priv->display.modeset_global_resources(dev);
7812
a6778b3c
DV		 7813 /* Set up the DPLL and any encoders state that needs to adjust or depend
7814 * on the DPLL.
7815 */
25c5b266
DV		 7816 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
7817 ret = !intel_crtc_mode_set(&intel_crtc->base,
7818 mode, adjusted_mode,
7819 x, y, fb);
7820 if (!ret)
7821 goto done;
a6778b3c
DV		 7822 }
7823
7824 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
25c5b266
DV		 7825 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
7826 dev_priv->display.crtc_enable(&intel_crtc->base);
a6778b3c 7827
25c5b266
DV		 7828 if (modeset_pipes) {
7829 /* Store real post-adjustment hardware mode. */
7830 crtc->hwmode = *adjusted_mode;
a6778b3c 7831
25c5b266
DV		 7832 /* Calculate and store various constants which
7833 * are later needed by vblank and swap-completion
7834 * timestamping. They are derived from true hwmode.
7835 */
7836 drm_calc_timestamping_constants(crtc);
7837 }
a6778b3c
DV		 7838
7839 /* FIXME: add subpixel order */
7840done:
7841 drm_mode_destroy(dev, adjusted_mode);
25c5b266 7842 if (!ret && crtc->enabled) {
a6778b3c
DV		 7843 crtc->hwmode = saved_hwmode;
7844 crtc->mode = saved_mode;
8af6cf88
DV		 7845 } else {
7846 intel_modeset_check_state(dev);
a6778b3c
DV		 7847 }
7848
7849 return ret;
7850}
7851
25c5b266
DV		 7852#undef for_each_intel_crtc_masked
7853
d9e55608
DV		 7854static void intel_set_config_free(struct intel_set_config *config)
7855{
7856 if (!config)
7857 return;
7858
1aa4b628
DV		 7859 kfree(config->save_connector_encoders);
7860 kfree(config->save_encoder_crtcs);
d9e55608
DV		 7861 kfree(config);
7862}
7863
85f9eb71
DV		 7864static int intel_set_config_save_state(struct drm_device *dev,
7865 struct intel_set_config *config)
7866{
85f9eb71
DV		 7867 struct drm_encoder *encoder;
7868 struct drm_connector *connector;
7869 int count;
7870
1aa4b628
DV		 7871 config->save_encoder_crtcs =
7872 kcalloc(dev->mode_config.num_encoder,
7873 sizeof(struct drm_crtc *), GFP_KERNEL);
7874 if (!config->save_encoder_crtcs)
85f9eb71
DV		 7875 return -ENOMEM;
7876
1aa4b628
DV		 7877 config->save_connector_encoders =
7878 kcalloc(dev->mode_config.num_connector,
7879 sizeof(struct drm_encoder *), GFP_KERNEL);
7880 if (!config->save_connector_encoders)
85f9eb71
DV		 7881 return -ENOMEM;
7882
7883 /* Copy data. Note that driver private data is not affected.
7884 * Should anything bad happen only the expected state is
7885 * restored, not the drivers personal bookkeeping.
7886 */
85f9eb71
DV		 7887 count = 0;
7888 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1aa4b628 7889 config->save_encoder_crtcs[count++] = encoder->crtc;
85f9eb71
DV		 7890 }
7891
7892 count = 0;
7893 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1aa4b628 7894 config->save_connector_encoders[count++] = connector->encoder;
85f9eb71
DV		 7895 }
7896
7897 return 0;
7898}
7899
7900static void intel_set_config_restore_state(struct drm_device *dev,
7901 struct intel_set_config *config)
7902{
9a935856
DV		 7903 struct intel_encoder *encoder;
7904 struct intel_connector *connector;
85f9eb71
DV		 7905 int count;
7906
85f9eb71 7907 count = 0;
9a935856
DV		 7908 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7909 encoder->new_crtc =
7910 to_intel_crtc(config->save_encoder_crtcs[count++]);
85f9eb71
DV		 7911 }
7912
7913 count = 0;
9a935856
DV		 7914 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
7915 connector->new_encoder =
7916 to_intel_encoder(config->save_connector_encoders[count++]);
85f9eb71
DV		 7917 }
7918}
7919
5e2b584e
DV		 7920static void
7921intel_set_config_compute_mode_changes(struct drm_mode_set *set,
7922 struct intel_set_config *config)
7923{
7924
7925 /* We should be able to check here if the fb has the same properties
7926 * and then just flip_or_move it */
7927 if (set->crtc->fb != set->fb) {
7928 /* If we have no fb then treat it as a full mode set */
7929 if (set->crtc->fb == NULL) {
7930 DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
7931 config->mode_changed = true;
7932 } else if (set->fb == NULL) {
7933 config->mode_changed = true;
7934 } else if (set->fb->depth != set->crtc->fb->depth) {
7935 config->mode_changed = true;
7936 } else if (set->fb->bits_per_pixel !=
7937 set->crtc->fb->bits_per_pixel) {
7938 config->mode_changed = true;
7939 } else
7940 config->fb_changed = true;
7941 }
7942
835c5873 7943 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
5e2b584e
DV		 7944 config->fb_changed = true;
7945
7946 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
7947 DRM_DEBUG_KMS("modes are different, full mode set\n");
7948 drm_mode_debug_printmodeline(&set->crtc->mode);
7949 drm_mode_debug_printmodeline(set->mode);
7950 config->mode_changed = true;
7951 }
7952}
7953
2e431051 7954static int
9a935856
DV		 7955intel_modeset_stage_output_state(struct drm_device *dev,
7956 struct drm_mode_set *set,
7957 struct intel_set_config *config)
50f56119 7958{
85f9eb71 7959 struct drm_crtc *new_crtc;
9a935856
DV		 7960 struct intel_connector *connector;
7961 struct intel_encoder *encoder;
2e431051 7962 int count, ro;
50f56119 7963
9a935856
DV		 7964 /* The upper layers ensure that we either disabl a crtc or have a list
7965 * of connectors. For paranoia, double-check this. */
7966 WARN_ON(!set->fb && (set->num_connectors != 0));
7967 WARN_ON(set->fb && (set->num_connectors == 0));
7968
50f56119 7969 count = 0;
9a935856
DV		 7970 list_for_each_entry(connector, &dev->mode_config.connector_list,
7971 base.head) {
7972 /* Otherwise traverse passed in connector list and get encoders
7973 * for them. */
50f56119 7974 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856
DV		 7975 if (set->connectors[ro] == &connector->base) {
7976 connector->new_encoder = connector->encoder;
50f56119
DV		 7977 break;
7978 }
7979 }
7980
9a935856
DV		 7981 /* If we disable the crtc, disable all its connectors. Also, if
7982 * the connector is on the changing crtc but not on the new
7983 * connector list, disable it. */
7984 if ((!set->fb || ro == set->num_connectors) &&
7985 connector->base.encoder &&
7986 connector->base.encoder->crtc == set->crtc) {
7987 connector->new_encoder = NULL;
7988
7989 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
7990 connector->base.base.id,
7991 drm_get_connector_name(&connector->base));
7992 }
7993
7994
7995 if (&connector->new_encoder->base != connector->base.encoder) {
50f56119 7996 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
5e2b584e 7997 config->mode_changed = true;
50f56119 7998 }
9a935856
DV		 7999
8000 /* Disable all disconnected encoders. */
8001 if (connector->base.status == connector_status_disconnected)
8002 connector->new_encoder = NULL;
50f56119 8003 }
9a935856 8004 /* connector->new_encoder is now updated for all connectors. */
50f56119 8005
9a935856 8006 /* Update crtc of enabled connectors. */
50f56119 8007 count = 0;
9a935856
DV		 8008 list_for_each_entry(connector, &dev->mode_config.connector_list,
8009 base.head) {
8010 if (!connector->new_encoder)
50f56119
DV		 8011 continue;
8012
9a935856 8013 new_crtc = connector->new_encoder->base.crtc;
50f56119
DV		 8014
8015 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856 8016 if (set->connectors[ro] == &connector->base)
50f56119
DV		 8017 new_crtc = set->crtc;
8018 }
8019
8020 /* Make sure the new CRTC will work with the encoder */
9a935856
DV		 8021 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
8022 new_crtc)) {
5e2b584e 8023 return -EINVAL;
50f56119 8024 }
9a935856
DV		 8025 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
8026
8027 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8028 connector->base.base.id,
8029 drm_get_connector_name(&connector->base),
8030 new_crtc->base.id);
8031 }
8032
8033 /* Check for any encoders that needs to be disabled. */
8034 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8035 base.head) {
8036 list_for_each_entry(connector,
8037 &dev->mode_config.connector_list,
8038 base.head) {
8039 if (connector->new_encoder == encoder) {
8040 WARN_ON(!connector->new_encoder->new_crtc);
8041
8042 goto next_encoder;
8043 }
8044 }
8045 encoder->new_crtc = NULL;
8046next_encoder:
8047 /* Only now check for crtc changes so we don't miss encoders
8048 * that will be disabled. */
8049 if (&encoder->new_crtc->base != encoder->base.crtc) {
50f56119 8050 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
5e2b584e 8051 config->mode_changed = true;
50f56119
DV		 8052 }
8053 }
9a935856 8054 /* Now we've also updated encoder->new_crtc for all encoders. */
50f56119 8055
2e431051
DV		 8056 return 0;
8057}
8058
8059static int intel_crtc_set_config(struct drm_mode_set *set)
8060{
8061 struct drm_device *dev;
2e431051
DV		 8062 struct drm_mode_set save_set;
8063 struct intel_set_config *config;
8064 int ret;
2e431051 8065
8d3e375e
DV		 8066 BUG_ON(!set);
8067 BUG_ON(!set->crtc);
8068 BUG_ON(!set->crtc->helper_private);
2e431051
DV		 8069
8070 if (!set->mode)
8071 set->fb = NULL;
8072
431e50f7
DV		 8073 /* The fb helper likes to play gross jokes with ->mode_set_config.
8074 * Unfortunately the crtc helper doesn't do much at all for this case,
8075 * so we have to cope with this madness until the fb helper is fixed up. */
8076 if (set->fb && set->num_connectors == 0)
8077 return 0;
8078
2e431051
DV		 8079 if (set->fb) {
8080 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8081 set->crtc->base.id, set->fb->base.id,
8082 (int)set->num_connectors, set->x, set->y);
8083 } else {
8084 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV		 8085 }
8086
8087 dev = set->crtc->dev;
8088
8089 ret = -ENOMEM;
8090 config = kzalloc(sizeof(*config), GFP_KERNEL);
8091 if (!config)
8092 goto out_config;
8093
8094 ret = intel_set_config_save_state(dev, config);
8095 if (ret)
8096 goto out_config;
8097
8098 save_set.crtc = set->crtc;
8099 save_set.mode = &set->crtc->mode;
8100 save_set.x = set->crtc->x;
8101 save_set.y = set->crtc->y;
8102 save_set.fb = set->crtc->fb;
8103
8104 /* Compute whether we need a full modeset, only an fb base update or no
8105 * change at all. In the future we might also check whether only the
8106 * mode changed, e.g. for LVDS where we only change the panel fitter in
8107 * such cases. */
8108 intel_set_config_compute_mode_changes(set, config);
8109
9a935856 8110 ret = intel_modeset_stage_output_state(dev, set, config);
2e431051
DV		 8111 if (ret)
8112 goto fail;
8113
5e2b584e 8114 if (config->mode_changed) {
87f1faa6 8115 if (set->mode) {
50f56119
DV		 8116 DRM_DEBUG_KMS("attempting to set mode from"
8117 " userspace\n");
8118 drm_mode_debug_printmodeline(set->mode);
87f1faa6
DV		 8119 }
8120
8121 if (!intel_set_mode(set->crtc, set->mode,
8122 set->x, set->y, set->fb)) {
8123 DRM_ERROR("failed to set mode on [CRTC:%d]\n",
8124 set->crtc->base.id);
8125 ret = -EINVAL;
8126 goto fail;
8127 }
5e2b584e 8128 } else if (config->fb_changed) {
4f660f49 8129 ret = intel_pipe_set_base(set->crtc,
94352cf9 8130 set->x, set->y, set->fb);
50f56119
DV		 8131 }
8132
d9e55608
DV		 8133 intel_set_config_free(config);
8134
50f56119
DV		 8135 return 0;
8136
8137fail:
85f9eb71 8138 intel_set_config_restore_state(dev, config);
50f56119
DV		 8139
8140 /* Try to restore the config */
5e2b584e 8141 if (config->mode_changed &&
a6778b3c
DV		 8142 !intel_set_mode(save_set.crtc, save_set.mode,
8143 save_set.x, save_set.y, save_set.fb))
50f56119
DV		 8144 DRM_ERROR("failed to restore config after modeset failure\n");
8145
d9e55608
DV		 8146out_config:
8147 intel_set_config_free(config);
50f56119
DV		 8148 return ret;
8149}
8150
f6e5b160 8151static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160
CW		 8152 .cursor_set = intel_crtc_cursor_set,
8153 .cursor_move = intel_crtc_cursor_move,
8154 .gamma_set = intel_crtc_gamma_set,
50f56119 8155 .set_config = intel_crtc_set_config,
f6e5b160
CW		 8156 .destroy = intel_crtc_destroy,
8157 .page_flip = intel_crtc_page_flip,
8158};
8159
79f689aa
PZ		 8160static void intel_cpu_pll_init(struct drm_device *dev)
8161{
8162 if (IS_HASWELL(dev))
8163 intel_ddi_pll_init(dev);
8164}
8165
ee7b9f93
JB		 8166static void intel_pch_pll_init(struct drm_device *dev)
8167{
8168 drm_i915_private_t *dev_priv = dev->dev_private;
8169 int i;
8170
8171 if (dev_priv->num_pch_pll == 0) {
8172 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
8173 return;
8174 }
8175
8176 for (i = 0; i < dev_priv->num_pch_pll; i++) {
8177 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
8178 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
8179 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
8180 }
8181}
8182
b358d0a6 8183static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 8184{
22fd0fab 8185 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 8186 struct intel_crtc *intel_crtc;
8187 int i;
8188
8189 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
8190 if (intel_crtc == NULL)
8191 return;
8192
8193 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8194
8195 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 8196 for (i = 0; i < 256; i++) {
8197 intel_crtc->lut_r[i] = i;
8198 intel_crtc->lut_g[i] = i;
8199 intel_crtc->lut_b[i] = i;
8200 }
8201
80824003
JB		 8202 /* Swap pipes & planes for FBC on pre-965 */
8203 intel_crtc->pipe = pipe;
8204 intel_crtc->plane = pipe;
a5c961d1 8205 intel_crtc->cpu_transcoder = pipe;
e2e767ab 8206 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 8207 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 8208 intel_crtc->plane = !pipe;
80824003
JB		 8209 }
8210
22fd0fab
JB		 8211 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8212 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8213 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8214 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8215
5a354204 8216 intel_crtc->bpp = 24; /* default for pre-Ironlake */
7e7d76c3 8217
79e53945 8218 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
79e53945
JB		 8219}
8220
08d7b3d1 8221int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 8222 struct drm_file *file)
08d7b3d1 8223{
08d7b3d1 8224 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 8225 struct drm_mode_object *drmmode_obj;
8226 struct intel_crtc *crtc;
08d7b3d1 8227
1cff8f6b
DV		 8228 if (!drm_core_check_feature(dev, DRIVER_MODESET))
8229 return -ENODEV;
08d7b3d1 8230
c05422d5
DV		 8231 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
8232 DRM_MODE_OBJECT_CRTC);
08d7b3d1 8233
c05422d5 8234 if (!drmmode_obj) {
08d7b3d1
CW		 8235 DRM_ERROR("no such CRTC id\n");
8236 return -EINVAL;
8237 }
8238
c05422d5
DV		 8239 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
8240 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 8241
c05422d5 8242 return 0;
08d7b3d1
CW		 8243}
8244
66a9278e 8245static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 8246{
66a9278e
DV		 8247 struct drm_device *dev = encoder->base.dev;
8248 struct intel_encoder *source_encoder;
79e53945 8249 int index_mask = 0;
79e53945
JB		 8250 int entry = 0;
8251
66a9278e
DV		 8252 list_for_each_entry(source_encoder,
8253 &dev->mode_config.encoder_list, base.head) {
8254
8255 if (encoder == source_encoder)
79e53945 8256 index_mask |= (1 << entry);
66a9278e
DV		 8257
8258 /* Intel hw has only one MUX where enocoders could be cloned. */
8259 if (encoder->cloneable && source_encoder->cloneable)
8260 index_mask |= (1 << entry);
8261
79e53945
JB		 8262 entry++;
8263 }
4ef69c7a 8264
79e53945
JB		 8265 return index_mask;
8266}
8267
4d302442
CW		 8268static bool has_edp_a(struct drm_device *dev)
8269{
8270 struct drm_i915_private *dev_priv = dev->dev_private;
8271
8272 if (!IS_MOBILE(dev))
8273 return false;
8274
8275 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8276 return false;
8277
8278 if (IS_GEN5(dev) &&
8279 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8280 return false;
8281
8282 return true;
8283}
8284
79e53945
JB		 8285static void intel_setup_outputs(struct drm_device *dev)
8286{
725e30ad 8287 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 8288 struct intel_encoder *encoder;
cb0953d7 8289 bool dpd_is_edp = false;
f3cfcba6 8290 bool has_lvds;
79e53945 8291
f3cfcba6 8292 has_lvds = intel_lvds_init(dev);
c5d1b51d
CW		 8293 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
8294 /* disable the panel fitter on everything but LVDS */
8295 I915_WRITE(PFIT_CONTROL, 0);
8296 }
79e53945 8297
bad720ff 8298 if (HAS_PCH_SPLIT(dev)) {
cb0953d7 8299 dpd_is_edp = intel_dpd_is_edp(dev);
30ad48b7 8300
4d302442 8301 if (has_edp_a(dev))
ab9d7c30 8302 intel_dp_init(dev, DP_A, PORT_A);
32f9d658 8303
cb0953d7 8304 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
ab9d7c30 8305 intel_dp_init(dev, PCH_DP_D, PORT_D);
cb0953d7
AJ		 8306 }
8307
8308 intel_crt_init(dev);
8309
0e72a5b5
ED		 8310 if (IS_HASWELL(dev)) {
8311 int found;
8312
8313 /* Haswell uses DDI functions to detect digital outputs */
8314 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8315 /* DDI A only supports eDP */
8316 if (found)
8317 intel_ddi_init(dev, PORT_A);
8318
8319 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8320 * register */
8321 found = I915_READ(SFUSE_STRAP);
8322
8323 if (found & SFUSE_STRAP_DDIB_DETECTED)
8324 intel_ddi_init(dev, PORT_B);
8325 if (found & SFUSE_STRAP_DDIC_DETECTED)
8326 intel_ddi_init(dev, PORT_C);
8327 if (found & SFUSE_STRAP_DDID_DETECTED)
8328 intel_ddi_init(dev, PORT_D);
8329 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7
AJ		 8330 int found;
8331
30ad48b7 8332 if (I915_READ(HDMIB) & PORT_DETECTED) {
461ed3ca 8333 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 8334 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 8335 if (!found)
08d644ad 8336 intel_hdmi_init(dev, HDMIB, PORT_B);
5eb08b69 8337 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 8338 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 8339 }
8340
8341 if (I915_READ(HDMIC) & PORT_DETECTED)
08d644ad 8342 intel_hdmi_init(dev, HDMIC, PORT_C);
30ad48b7 8343
b708a1d5 8344 if (!dpd_is_edp && I915_READ(HDMID) & PORT_DETECTED)
08d644ad 8345 intel_hdmi_init(dev, HDMID, PORT_D);
30ad48b7 8346
5eb08b69 8347 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 8348 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 8349
cb0953d7 8350 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
ab9d7c30 8351 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d
JB		 8352 } else if (IS_VALLEYVIEW(dev)) {
8353 int found;
8354
19c03924
GB		 8355 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
8356 if (I915_READ(DP_C) & DP_DETECTED)
8357 intel_dp_init(dev, DP_C, PORT_C);
8358
4a87d65d
JB		 8359 if (I915_READ(SDVOB) & PORT_DETECTED) {
8360 /* SDVOB multiplex with HDMIB */
8361 found = intel_sdvo_init(dev, SDVOB, true);
8362 if (!found)
08d644ad 8363 intel_hdmi_init(dev, SDVOB, PORT_B);
4a87d65d 8364 if (!found && (I915_READ(DP_B) & DP_DETECTED))
ab9d7c30 8365 intel_dp_init(dev, DP_B, PORT_B);
4a87d65d
JB		 8366 }
8367
8368 if (I915_READ(SDVOC) & PORT_DETECTED)
08d644ad 8369 intel_hdmi_init(dev, SDVOC, PORT_C);
5eb08b69 8370
103a196f 8371 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 8372 bool found = false;
7d57382e 8373
725e30ad 8374 if (I915_READ(SDVOB) & SDVO_DETECTED) {
b01f2c3a 8375 DRM_DEBUG_KMS("probing SDVOB\n");
eef4eacb 8376 found = intel_sdvo_init(dev, SDVOB, true);
b01f2c3a
JB		 8377 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
8378 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
08d644ad 8379 intel_hdmi_init(dev, SDVOB, PORT_B);
b01f2c3a 8380 }
27185ae1 8381
b01f2c3a
JB		 8382 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
8383 DRM_DEBUG_KMS("probing DP_B\n");
ab9d7c30 8384 intel_dp_init(dev, DP_B, PORT_B);
b01f2c3a 8385 }
725e30ad 8386 }
13520b05
KH		 8387
8388 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 8389
b01f2c3a
JB		 8390 if (I915_READ(SDVOB) & SDVO_DETECTED) {
8391 DRM_DEBUG_KMS("probing SDVOC\n");
eef4eacb 8392 found = intel_sdvo_init(dev, SDVOC, false);
b01f2c3a 8393 }
27185ae1
ML		 8394
8395 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
8396
b01f2c3a
JB		 8397 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
8398 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
08d644ad 8399 intel_hdmi_init(dev, SDVOC, PORT_C);
b01f2c3a
JB		 8400 }
8401 if (SUPPORTS_INTEGRATED_DP(dev)) {
8402 DRM_DEBUG_KMS("probing DP_C\n");
ab9d7c30 8403 intel_dp_init(dev, DP_C, PORT_C);
b01f2c3a 8404 }
725e30ad 8405 }
27185ae1 8406
b01f2c3a
JB		 8407 if (SUPPORTS_INTEGRATED_DP(dev) &&
8408 (I915_READ(DP_D) & DP_DETECTED)) {
8409 DRM_DEBUG_KMS("probing DP_D\n");
ab9d7c30 8410 intel_dp_init(dev, DP_D, PORT_D);
b01f2c3a 8411 }
bad720ff 8412 } else if (IS_GEN2(dev))
79e53945
JB		 8413 intel_dvo_init(dev);
8414
103a196f 8415 if (SUPPORTS_TV(dev))
79e53945
JB		 8416 intel_tv_init(dev);
8417
4ef69c7a
CW		 8418 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8419 encoder->base.possible_crtcs = encoder->crtc_mask;
8420 encoder->base.possible_clones =
66a9278e 8421 intel_encoder_clones(encoder);
79e53945 8422 }
47356eb6 8423
40579abe 8424 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
9fb526db 8425 ironlake_init_pch_refclk(dev);
79e53945
JB		 8426}
8427
8428static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8429{
8430 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945
JB		 8431
8432 drm_framebuffer_cleanup(fb);
05394f39 8433 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
79e53945
JB		 8434
8435 kfree(intel_fb);
8436}
8437
8438static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 8439 struct drm_file *file,
79e53945
JB		 8440 unsigned int *handle)
8441{
8442 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 8443 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 8444
05394f39 8445 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 8446}
8447
8448static const struct drm_framebuffer_funcs intel_fb_funcs = {
8449 .destroy = intel_user_framebuffer_destroy,
8450 .create_handle = intel_user_framebuffer_create_handle,
8451};
8452
38651674
DA		 8453int intel_framebuffer_init(struct drm_device *dev,
8454 struct intel_framebuffer *intel_fb,
308e5bcb 8455 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 8456 struct drm_i915_gem_object *obj)
79e53945 8457{
79e53945
JB		 8458 int ret;
8459
05394f39 8460 if (obj->tiling_mode == I915_TILING_Y)
57cd6508
CW		 8461 return -EINVAL;
8462
308e5bcb 8463 if (mode_cmd->pitches[0] & 63)
57cd6508
CW		 8464 return -EINVAL;
8465
5d7bd705
VS		 8466 /* FIXME <= Gen4 stride limits are bit unclear */
8467 if (mode_cmd->pitches[0] > 32768)
8468 return -EINVAL;
8469
8470 if (obj->tiling_mode != I915_TILING_NONE &&
8471 mode_cmd->pitches[0] != obj->stride)
8472 return -EINVAL;
8473
57779d06 8474 /* Reject formats not supported by any plane early. */
308e5bcb 8475 switch (mode_cmd->pixel_format) {
57779d06 8476 case DRM_FORMAT_C8:
04b3924d
VS		 8477 case DRM_FORMAT_RGB565:
8478 case DRM_FORMAT_XRGB8888:
8479 case DRM_FORMAT_ARGB8888:
57779d06
VS		 8480 break;
8481 case DRM_FORMAT_XRGB1555:
8482 case DRM_FORMAT_ARGB1555:
8483 if (INTEL_INFO(dev)->gen > 3)
8484 return -EINVAL;
8485 break;
8486 case DRM_FORMAT_XBGR8888:
8487 case DRM_FORMAT_ABGR8888:
04b3924d
VS		 8488 case DRM_FORMAT_XRGB2101010:
8489 case DRM_FORMAT_ARGB2101010:
57779d06
VS		 8490 case DRM_FORMAT_XBGR2101010:
8491 case DRM_FORMAT_ABGR2101010:
8492 if (INTEL_INFO(dev)->gen < 4)
8493 return -EINVAL;
b5626747 8494 break;
04b3924d
VS		 8495 case DRM_FORMAT_YUYV:
8496 case DRM_FORMAT_UYVY:
8497 case DRM_FORMAT_YVYU:
8498 case DRM_FORMAT_VYUY:
57779d06
VS		 8499 if (INTEL_INFO(dev)->gen < 6)
8500 return -EINVAL;
57cd6508
CW		 8501 break;
8502 default:
57779d06 8503 DRM_DEBUG_KMS("unsupported pixel format 0x%08x\n", mode_cmd->pixel_format);
57cd6508
CW		 8504 return -EINVAL;
8505 }
8506
90f9a336
VS		 8507 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
8508 if (mode_cmd->offsets[0] != 0)
8509 return -EINVAL;
8510
79e53945
JB		 8511 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
8512 if (ret) {
8513 DRM_ERROR("framebuffer init failed %d\n", ret);
8514 return ret;
8515 }
8516
8517 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
79e53945 8518 intel_fb->obj = obj;
79e53945
JB		 8519 return 0;
8520}
8521
79e53945
JB		 8522static struct drm_framebuffer *
8523intel_user_framebuffer_create(struct drm_device *dev,
8524 struct drm_file *filp,
308e5bcb 8525 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 8526{
05394f39 8527 struct drm_i915_gem_object *obj;
79e53945 8528
308e5bcb
JB		 8529 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
8530 mode_cmd->handles[0]));
c8725226 8531 if (&obj->base == NULL)
cce13ff7 8532 return ERR_PTR(-ENOENT);
79e53945 8533
d2dff872 8534 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 8535}
8536
79e53945 8537static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 8538 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 8539 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 8540};
8541
e70236a8
JB		 8542/* Set up chip specific display functions */
8543static void intel_init_display(struct drm_device *dev)
8544{
8545 struct drm_i915_private *dev_priv = dev->dev_private;
8546
8547 /* We always want a DPMS function */
09b4ddf9
PZ		 8548 if (IS_HASWELL(dev)) {
8549 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
4f771f10
PZ		 8550 dev_priv->display.crtc_enable = haswell_crtc_enable;
8551 dev_priv->display.crtc_disable = haswell_crtc_disable;
6441ab5f 8552 dev_priv->display.off = haswell_crtc_off;
09b4ddf9
PZ		 8553 dev_priv->display.update_plane = ironlake_update_plane;
8554 } else if (HAS_PCH_SPLIT(dev)) {
f564048e 8555 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
76e5a89c
DV		 8556 dev_priv->display.crtc_enable = ironlake_crtc_enable;
8557 dev_priv->display.crtc_disable = ironlake_crtc_disable;
ee7b9f93 8558 dev_priv->display.off = ironlake_crtc_off;
17638cd6 8559 dev_priv->display.update_plane = ironlake_update_plane;
f564048e 8560 } else {
f564048e 8561 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
76e5a89c
DV		 8562 dev_priv->display.crtc_enable = i9xx_crtc_enable;
8563 dev_priv->display.crtc_disable = i9xx_crtc_disable;
ee7b9f93 8564 dev_priv->display.off = i9xx_crtc_off;
17638cd6 8565 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 8566 }
e70236a8 8567
e70236a8 8568 /* Returns the core display clock speed */
25eb05fc
JB		 8569 if (IS_VALLEYVIEW(dev))
8570 dev_priv->display.get_display_clock_speed =
8571 valleyview_get_display_clock_speed;
8572 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 8573 dev_priv->display.get_display_clock_speed =
8574 i945_get_display_clock_speed;
8575 else if (IS_I915G(dev))
8576 dev_priv->display.get_display_clock_speed =
8577 i915_get_display_clock_speed;
f2b115e6 8578 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
e70236a8
JB		 8579 dev_priv->display.get_display_clock_speed =
8580 i9xx_misc_get_display_clock_speed;
8581 else if (IS_I915GM(dev))
8582 dev_priv->display.get_display_clock_speed =
8583 i915gm_get_display_clock_speed;
8584 else if (IS_I865G(dev))
8585 dev_priv->display.get_display_clock_speed =
8586 i865_get_display_clock_speed;
f0f8a9ce 8587 else if (IS_I85X(dev))
e70236a8
JB		 8588 dev_priv->display.get_display_clock_speed =
8589 i855_get_display_clock_speed;
8590 else /* 852, 830 */
8591 dev_priv->display.get_display_clock_speed =
8592 i830_get_display_clock_speed;
8593
7f8a8569 8594 if (HAS_PCH_SPLIT(dev)) {
f00a3ddf 8595 if (IS_GEN5(dev)) {
674cf967 8596 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
e0dac65e 8597 dev_priv->display.write_eld = ironlake_write_eld;
1398261a 8598 } else if (IS_GEN6(dev)) {
674cf967 8599 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
e0dac65e 8600 dev_priv->display.write_eld = ironlake_write_eld;
357555c0
JB		 8601 } else if (IS_IVYBRIDGE(dev)) {
8602 /* FIXME: detect B0+ stepping and use auto training */
8603 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
e0dac65e 8604 dev_priv->display.write_eld = ironlake_write_eld;
01a415fd
DV		 8605 dev_priv->display.modeset_global_resources =
8606 ivb_modeset_global_resources;
c82e4d26
ED		 8607 } else if (IS_HASWELL(dev)) {
8608 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
83358c85 8609 dev_priv->display.write_eld = haswell_write_eld;
7f8a8569
ZW		 8610 } else
8611 dev_priv->display.update_wm = NULL;
6067aaea 8612 } else if (IS_G4X(dev)) {
e0dac65e 8613 dev_priv->display.write_eld = g4x_write_eld;
e70236a8 8614 }
8c9f3aaf
JB		 8615
8616 /* Default just returns -ENODEV to indicate unsupported */
8617 dev_priv->display.queue_flip = intel_default_queue_flip;
8618
8619 switch (INTEL_INFO(dev)->gen) {
8620 case 2:
8621 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8622 break;
8623
8624 case 3:
8625 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8626 break;
8627
8628 case 4:
8629 case 5:
8630 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8631 break;
8632
8633 case 6:
8634 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8635 break;
7c9017e5
JB		 8636 case 7:
8637 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8638 break;
8c9f3aaf 8639 }
e70236a8
JB		 8640}
8641
b690e96c
JB		 8642/*
8643 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8644 * resume, or other times. This quirk makes sure that's the case for
8645 * affected systems.
8646 */
0206e353 8647static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 8648{
8649 struct drm_i915_private *dev_priv = dev->dev_private;
8650
8651 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 8652 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 8653}
8654
435793df
KP		 8655/*
8656 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8657 */
8658static void quirk_ssc_force_disable(struct drm_device *dev)
8659{
8660 struct drm_i915_private *dev_priv = dev->dev_private;
8661 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 8662 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 8663}
8664
4dca20ef 8665/*
5a15ab5b
CE		 8666 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
8667 * brightness value
4dca20ef
CE		 8668 */
8669static void quirk_invert_brightness(struct drm_device *dev)
8670{
8671 struct drm_i915_private *dev_priv = dev->dev_private;
8672 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 8673 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 8674}
8675
b690e96c
JB		 8676struct intel_quirk {
8677 int device;
8678 int subsystem_vendor;
8679 int subsystem_device;
8680 void (*hook)(struct drm_device *dev);
8681};
8682
c43b5634 8683static struct intel_quirk intel_quirks[] = {
b690e96c 8684 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 8685 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c 8686
b690e96c
JB		 8687 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8688 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
8689
b690e96c
JB		 8690 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8691 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
8692
ccd0d36e 8693 /* 830/845 need to leave pipe A & dpll A up */
b690e96c 8694 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
dcdaed6e 8695 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
435793df
KP		 8696
8697 /* Lenovo U160 cannot use SSC on LVDS */
8698 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 8699
8700 /* Sony Vaio Y cannot use SSC on LVDS */
8701 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b
CE		 8702
8703 /* Acer Aspire 5734Z must invert backlight brightness */
8704 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
b690e96c
JB		 8705};
8706
8707static void intel_init_quirks(struct drm_device *dev)
8708{
8709 struct pci_dev *d = dev->pdev;
8710 int i;
8711
8712 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
8713 struct intel_quirk *q = &intel_quirks[i];
8714
8715 if (d->device == q->device &&
8716 (d->subsystem_vendor == q->subsystem_vendor ||
8717 q->subsystem_vendor == PCI_ANY_ID) &&
8718 (d->subsystem_device == q->subsystem_device ||
8719 q->subsystem_device == PCI_ANY_ID))
8720 q->hook(dev);
8721 }
8722}
8723
9cce37f4
JB		 8724/* Disable the VGA plane that we never use */
8725static void i915_disable_vga(struct drm_device *dev)
8726{
8727 struct drm_i915_private *dev_priv = dev->dev_private;
8728 u8 sr1;
8729 u32 vga_reg;
8730
8731 if (HAS_PCH_SPLIT(dev))
8732 vga_reg = CPU_VGACNTRL;
8733 else
8734 vga_reg = VGACNTRL;
8735
8736 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 8737 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 8738 sr1 = inb(VGA_SR_DATA);
8739 outb(sr1 | 1<<5, VGA_SR_DATA);
8740 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
8741 udelay(300);
8742
8743 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
8744 POSTING_READ(vga_reg);
8745}
8746
f817586c
DV		 8747void intel_modeset_init_hw(struct drm_device *dev)
8748{
0232e927
ED		 8749 /* We attempt to init the necessary power wells early in the initialization
8750 * time, so the subsystems that expect power to be enabled can work.
8751 */
8752 intel_init_power_wells(dev);
8753
a8f78b58
ED		 8754 intel_prepare_ddi(dev);
8755
f817586c
DV		 8756 intel_init_clock_gating(dev);
8757
79f5b2c7 8758 mutex_lock(&dev->struct_mutex);
8090c6b9 8759 intel_enable_gt_powersave(dev);
79f5b2c7 8760 mutex_unlock(&dev->struct_mutex);
f817586c
DV		 8761}
8762
79e53945
JB		 8763void intel_modeset_init(struct drm_device *dev)
8764{
652c393a 8765 struct drm_i915_private *dev_priv = dev->dev_private;
b840d907 8766 int i, ret;
79e53945
JB		 8767
8768 drm_mode_config_init(dev);
8769
8770 dev->mode_config.min_width = 0;
8771 dev->mode_config.min_height = 0;
8772
019d96cb
DA		 8773 dev->mode_config.preferred_depth = 24;
8774 dev->mode_config.prefer_shadow = 1;
8775
e6ecefaa 8776 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 8777
b690e96c
JB		 8778 intel_init_quirks(dev);
8779
1fa61106
ED		 8780 intel_init_pm(dev);
8781
e70236a8
JB		 8782 intel_init_display(dev);
8783
a6c45cf0
CW		 8784 if (IS_GEN2(dev)) {
8785 dev->mode_config.max_width = 2048;
8786 dev->mode_config.max_height = 2048;
8787 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 8788 dev->mode_config.max_width = 4096;
8789 dev->mode_config.max_height = 4096;
79e53945 8790 } else {
a6c45cf0
CW		 8791 dev->mode_config.max_width = 8192;
8792 dev->mode_config.max_height = 8192;
79e53945 8793 }
dd2757f8 8794 dev->mode_config.fb_base = dev_priv->mm.gtt_base_addr;
79e53945 8795
28c97730 8796 DRM_DEBUG_KMS("%d display pipe%s available.\n",
a3524f1b 8797 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
79e53945 8798
a3524f1b 8799 for (i = 0; i < dev_priv->num_pipe; i++) {
79e53945 8800 intel_crtc_init(dev, i);
00c2064b
JB		 8801 ret = intel_plane_init(dev, i);
8802 if (ret)
8803 DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
79e53945
JB		 8804 }
8805
79f689aa 8806 intel_cpu_pll_init(dev);
ee7b9f93
JB		 8807 intel_pch_pll_init(dev);
8808
9cce37f4
JB		 8809 /* Just disable it once at startup */
8810 i915_disable_vga(dev);
79e53945 8811 intel_setup_outputs(dev);
2c7111db
CW		 8812}
8813
24929352
DV		 8814static void
8815intel_connector_break_all_links(struct intel_connector *connector)
8816{
8817 connector->base.dpms = DRM_MODE_DPMS_OFF;
8818 connector->base.encoder = NULL;
8819 connector->encoder->connectors_active = false;
8820 connector->encoder->base.crtc = NULL;
8821}
8822
7fad798e
DV		 8823static void intel_enable_pipe_a(struct drm_device *dev)
8824{
8825 struct intel_connector *connector;
8826 struct drm_connector *crt = NULL;
8827 struct intel_load_detect_pipe load_detect_temp;
8828
8829 /* We can't just switch on the pipe A, we need to set things up with a
8830 * proper mode and output configuration. As a gross hack, enable pipe A
8831 * by enabling the load detect pipe once. */
8832 list_for_each_entry(connector,
8833 &dev->mode_config.connector_list,
8834 base.head) {
8835 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
8836 crt = &connector->base;
8837 break;
8838 }
8839 }
8840
8841 if (!crt)
8842 return;
8843
8844 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
8845 intel_release_load_detect_pipe(crt, &load_detect_temp);
8846
8847
8848}
8849
fa555837
DV		 8850static bool
8851intel_check_plane_mapping(struct intel_crtc *crtc)
8852{
8853 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
8854 u32 reg, val;
8855
8856 if (dev_priv->num_pipe == 1)
8857 return true;
8858
8859 reg = DSPCNTR(!crtc->plane);
8860 val = I915_READ(reg);
8861
8862 if ((val & DISPLAY_PLANE_ENABLE) &&
8863 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
8864 return false;
8865
8866 return true;
8867}
8868
24929352
DV		 8869static void intel_sanitize_crtc(struct intel_crtc *crtc)
8870{
8871 struct drm_device *dev = crtc->base.dev;
8872 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837 8873 u32 reg;
24929352 8874
24929352 8875 /* Clear any frame start delays used for debugging left by the BIOS */
702e7a56 8876 reg = PIPECONF(crtc->cpu_transcoder);
24929352
DV		 8877 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
8878
8879 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 8880 * disable the crtc (and hence change the state) if it is wrong. Note
8881 * that gen4+ has a fixed plane -> pipe mapping. */
8882 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 8883 struct intel_connector *connector;
8884 bool plane;
8885
24929352
DV		 8886 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
8887 crtc->base.base.id);
8888
8889 /* Pipe has the wrong plane attached and the plane is active.
8890 * Temporarily change the plane mapping and disable everything
8891 * ... */
8892 plane = crtc->plane;
8893 crtc->plane = !plane;
8894 dev_priv->display.crtc_disable(&crtc->base);
8895 crtc->plane = plane;
8896
8897 /* ... and break all links. */
8898 list_for_each_entry(connector, &dev->mode_config.connector_list,
8899 base.head) {
8900 if (connector->encoder->base.crtc != &crtc->base)
8901 continue;
8902
8903 intel_connector_break_all_links(connector);
8904 }
8905
8906 WARN_ON(crtc->active);
8907 crtc->base.enabled = false;
8908 }
24929352 8909
7fad798e
DV		 8910 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
8911 crtc->pipe == PIPE_A && !crtc->active) {
8912 /* BIOS forgot to enable pipe A, this mostly happens after
8913 * resume. Force-enable the pipe to fix this, the update_dpms
8914 * call below we restore the pipe to the right state, but leave
8915 * the required bits on. */
8916 intel_enable_pipe_a(dev);
8917 }
8918
24929352
DV		 8919 /* Adjust the state of the output pipe according to whether we
8920 * have active connectors/encoders. */
8921 intel_crtc_update_dpms(&crtc->base);
8922
8923 if (crtc->active != crtc->base.enabled) {
8924 struct intel_encoder *encoder;
8925
8926 /* This can happen either due to bugs in the get_hw_state
8927 * functions or because the pipe is force-enabled due to the
8928 * pipe A quirk. */
8929 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
8930 crtc->base.base.id,
8931 crtc->base.enabled ? "enabled" : "disabled",
8932 crtc->active ? "enabled" : "disabled");
8933
8934 crtc->base.enabled = crtc->active;
8935
8936 /* Because we only establish the connector -> encoder ->
8937 * crtc links if something is active, this means the
8938 * crtc is now deactivated. Break the links. connector
8939 * -> encoder links are only establish when things are
8940 * actually up, hence no need to break them. */
8941 WARN_ON(crtc->active);
8942
8943 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
8944 WARN_ON(encoder->connectors_active);
8945 encoder->base.crtc = NULL;
8946 }
8947 }
8948}
8949
8950static void intel_sanitize_encoder(struct intel_encoder *encoder)
8951{
8952 struct intel_connector *connector;
8953 struct drm_device *dev = encoder->base.dev;
8954
8955 /* We need to check both for a crtc link (meaning that the
8956 * encoder is active and trying to read from a pipe) and the
8957 * pipe itself being active. */
8958 bool has_active_crtc = encoder->base.crtc &&
8959 to_intel_crtc(encoder->base.crtc)->active;
8960
8961 if (encoder->connectors_active && !has_active_crtc) {
8962 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
8963 encoder->base.base.id,
8964 drm_get_encoder_name(&encoder->base));
8965
8966 /* Connector is active, but has no active pipe. This is
8967 * fallout from our resume register restoring. Disable
8968 * the encoder manually again. */
8969 if (encoder->base.crtc) {
8970 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
8971 encoder->base.base.id,
8972 drm_get_encoder_name(&encoder->base));
8973 encoder->disable(encoder);
8974 }
8975
8976 /* Inconsistent output/port/pipe state happens presumably due to
8977 * a bug in one of the get_hw_state functions. Or someplace else
8978 * in our code, like the register restore mess on resume. Clamp
8979 * things to off as a safer default. */
8980 list_for_each_entry(connector,
8981 &dev->mode_config.connector_list,
8982 base.head) {
8983 if (connector->encoder != encoder)
8984 continue;
8985
8986 intel_connector_break_all_links(connector);
8987 }
8988 }
8989 /* Enabled encoders without active connectors will be fixed in
8990 * the crtc fixup. */
8991}
8992
8993/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
8994 * and i915 state tracking structures. */
8995void intel_modeset_setup_hw_state(struct drm_device *dev)
8996{
8997 struct drm_i915_private *dev_priv = dev->dev_private;
8998 enum pipe pipe;
8999 u32 tmp;
9000 struct intel_crtc *crtc;
9001 struct intel_encoder *encoder;
9002 struct intel_connector *connector;
9003
e28d54cb
PZ		 9004 if (IS_HASWELL(dev)) {
9005 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9006
9007 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9008 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9009 case TRANS_DDI_EDP_INPUT_A_ON:
9010 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9011 pipe = PIPE_A;
9012 break;
9013 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9014 pipe = PIPE_B;
9015 break;
9016 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9017 pipe = PIPE_C;
9018 break;
9019 }
9020
9021 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9022 crtc->cpu_transcoder = TRANSCODER_EDP;
9023
9024 DRM_DEBUG_KMS("Pipe %c using transcoder EDP\n",
9025 pipe_name(pipe));
9026 }
9027 }
9028
24929352
DV		 9029 for_each_pipe(pipe) {
9030 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9031
702e7a56 9032 tmp = I915_READ(PIPECONF(crtc->cpu_transcoder));
24929352
DV		 9033 if (tmp & PIPECONF_ENABLE)
9034 crtc->active = true;
9035 else
9036 crtc->active = false;
9037
9038 crtc->base.enabled = crtc->active;
9039
9040 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9041 crtc->base.base.id,
9042 crtc->active ? "enabled" : "disabled");
9043 }
9044
6441ab5f
PZ		 9045 if (IS_HASWELL(dev))
9046 intel_ddi_setup_hw_pll_state(dev);
9047
24929352
DV		 9048 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9049 base.head) {
9050 pipe = 0;
9051
9052 if (encoder->get_hw_state(encoder, &pipe)) {
9053 encoder->base.crtc =
9054 dev_priv->pipe_to_crtc_mapping[pipe];
9055 } else {
9056 encoder->base.crtc = NULL;
9057 }
9058
9059 encoder->connectors_active = false;
9060 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9061 encoder->base.base.id,
9062 drm_get_encoder_name(&encoder->base),
9063 encoder->base.crtc ? "enabled" : "disabled",
9064 pipe);
9065 }
9066
9067 list_for_each_entry(connector, &dev->mode_config.connector_list,
9068 base.head) {
9069 if (connector->get_hw_state(connector)) {
9070 connector->base.dpms = DRM_MODE_DPMS_ON;
9071 connector->encoder->connectors_active = true;
9072 connector->base.encoder = &connector->encoder->base;
9073 } else {
9074 connector->base.dpms = DRM_MODE_DPMS_OFF;
9075 connector->base.encoder = NULL;
9076 }
9077 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9078 connector->base.base.id,
9079 drm_get_connector_name(&connector->base),
9080 connector->base.encoder ? "enabled" : "disabled");
9081 }
9082
9083 /* HW state is read out, now we need to sanitize this mess. */
9084 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9085 base.head) {
9086 intel_sanitize_encoder(encoder);
9087 }
9088
9089 for_each_pipe(pipe) {
9090 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9091 intel_sanitize_crtc(crtc);
9092 }
9a935856
DV		 9093
9094 intel_modeset_update_staged_output_state(dev);
8af6cf88
DV		 9095
9096 intel_modeset_check_state(dev);
2e938892
DV		 9097
9098 drm_mode_config_reset(dev);
24929352
DV		 9099}
9100
2c7111db
CW		 9101void intel_modeset_gem_init(struct drm_device *dev)
9102{
1833b134 9103 intel_modeset_init_hw(dev);
02e792fb
DV		 9104
9105 intel_setup_overlay(dev);
24929352
DV		 9106
9107 intel_modeset_setup_hw_state(dev);
79e53945
JB		 9108}
9109
9110void intel_modeset_cleanup(struct drm_device *dev)
9111{
652c393a
JB		 9112 struct drm_i915_private *dev_priv = dev->dev_private;
9113 struct drm_crtc *crtc;
9114 struct intel_crtc *intel_crtc;
9115
f87ea761 9116 drm_kms_helper_poll_fini(dev);
652c393a
JB		 9117 mutex_lock(&dev->struct_mutex);
9118
723bfd70
JB		 9119 intel_unregister_dsm_handler();
9120
9121
652c393a
JB		 9122 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9123 /* Skip inactive CRTCs */
9124 if (!crtc->fb)
9125 continue;
9126
9127 intel_crtc = to_intel_crtc(crtc);
3dec0095 9128 intel_increase_pllclock(crtc);
652c393a
JB		 9129 }
9130
973d04f9 9131 intel_disable_fbc(dev);
e70236a8 9132
8090c6b9 9133 intel_disable_gt_powersave(dev);
0cdab21f 9134
930ebb46
DV		 9135 ironlake_teardown_rc6(dev);
9136
57f350b6
JB		 9137 if (IS_VALLEYVIEW(dev))
9138 vlv_init_dpio(dev);
9139
69341a5e
KH		 9140 mutex_unlock(&dev->struct_mutex);
9141
6c0d9350
DV		 9142 /* Disable the irq before mode object teardown, for the irq might
9143 * enqueue unpin/hotplug work. */
9144 drm_irq_uninstall(dev);
9145 cancel_work_sync(&dev_priv->hotplug_work);
c6a828d3 9146 cancel_work_sync(&dev_priv->rps.work);
6c0d9350 9147
1630fe75
CW		 9148 /* flush any delayed tasks or pending work */
9149 flush_scheduled_work();
9150
79e53945
JB		 9151 drm_mode_config_cleanup(dev);
9152}
9153
f1c79df3
ZW		 9154/*
9155 * Return which encoder is currently attached for connector.
9156 */
df0e9248 9157struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 9158{
df0e9248
CW		 9159 return &intel_attached_encoder(connector)->base;
9160}
f1c79df3 9161
df0e9248
CW		 9162void intel_connector_attach_encoder(struct intel_connector *connector,
9163 struct intel_encoder *encoder)
9164{
9165 connector->encoder = encoder;
9166 drm_mode_connector_attach_encoder(&connector->base,
9167 &encoder->base);
79e53945 9168}
28d52043
DA		 9169
9170/*
9171 * set vga decode state - true == enable VGA decode
9172 */
9173int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9174{
9175 struct drm_i915_private *dev_priv = dev->dev_private;
9176 u16 gmch_ctrl;
9177
9178 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9179 if (state)
9180 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9181 else
9182 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9183 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9184 return 0;
9185}
c4a1d9e4
CW		 9186
9187#ifdef CONFIG_DEBUG_FS
9188#include <linux/seq_file.h>
9189
9190struct intel_display_error_state {
9191 struct intel_cursor_error_state {
9192 u32 control;
9193 u32 position;
9194 u32 base;
9195 u32 size;
52331309 9196 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 9197
9198 struct intel_pipe_error_state {
9199 u32 conf;
9200 u32 source;
9201
9202 u32 htotal;
9203 u32 hblank;
9204 u32 hsync;
9205 u32 vtotal;
9206 u32 vblank;
9207 u32 vsync;
52331309 9208 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 9209
9210 struct intel_plane_error_state {
9211 u32 control;
9212 u32 stride;
9213 u32 size;
9214 u32 pos;
9215 u32 addr;
9216 u32 surface;
9217 u32 tile_offset;
52331309 9218 } plane[I915_MAX_PIPES];
c4a1d9e4
CW		 9219};
9220
9221struct intel_display_error_state *
9222intel_display_capture_error_state(struct drm_device *dev)
9223{
0206e353 9224 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4 9225 struct intel_display_error_state *error;
702e7a56 9226 enum transcoder cpu_transcoder;
c4a1d9e4
CW		 9227 int i;
9228
9229 error = kmalloc(sizeof(*error), GFP_ATOMIC);
9230 if (error == NULL)
9231 return NULL;
9232
52331309 9233 for_each_pipe(i) {
702e7a56
PZ		 9234 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
9235
c4a1d9e4
CW		 9236 error->cursor[i].control = I915_READ(CURCNTR(i));
9237 error->cursor[i].position = I915_READ(CURPOS(i));
9238 error->cursor[i].base = I915_READ(CURBASE(i));
9239
9240 error->plane[i].control = I915_READ(DSPCNTR(i));
9241 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
9242 error->plane[i].size = I915_READ(DSPSIZE(i));
0206e353 9243 error->plane[i].pos = I915_READ(DSPPOS(i));
c4a1d9e4
CW		 9244 error->plane[i].addr = I915_READ(DSPADDR(i));
9245 if (INTEL_INFO(dev)->gen >= 4) {
9246 error->plane[i].surface = I915_READ(DSPSURF(i));
9247 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9248 }
9249
702e7a56 9250 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
c4a1d9e4 9251 error->pipe[i].source = I915_READ(PIPESRC(i));
fe2b8f9d
PZ		 9252 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
9253 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
9254 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
9255 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
9256 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
9257 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 9258 }
9259
9260 return error;
9261}
9262
9263void
9264intel_display_print_error_state(struct seq_file *m,
9265 struct drm_device *dev,
9266 struct intel_display_error_state *error)
9267{
52331309 9268 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4
CW		 9269 int i;
9270
52331309
DL		 9271 seq_printf(m, "Num Pipes: %d\n", dev_priv->num_pipe);
9272 for_each_pipe(i) {
c4a1d9e4
CW		 9273 seq_printf(m, "Pipe [%d]:\n", i);
9274 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
9275 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
9276 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
9277 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
9278 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
9279 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
9280 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
9281 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
9282
9283 seq_printf(m, "Plane [%d]:\n", i);
9284 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
9285 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
9286 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
9287 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
9288 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
9289 if (INTEL_INFO(dev)->gen >= 4) {
9290 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
9291 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
9292 }
9293
9294 seq_printf(m, "Cursor [%d]:\n", i);
9295 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
9296 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
9297 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
9298 }
9299}
9300#endif
Linux kernel - Deliverables
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