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79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | */ | |
26 | ||
618563e3 | 27 | #include <linux/dmi.h> |
c1c7af60 JB |
28 | #include <linux/module.h> |
29 | #include <linux/input.h> | |
79e53945 | 30 | #include <linux/i2c.h> |
7662c8bd | 31 | #include <linux/kernel.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
9cce37f4 | 33 | #include <linux/vgaarb.h> |
e0dac65e | 34 | #include <drm/drm_edid.h> |
760285e7 | 35 | #include <drm/drmP.h> |
79e53945 | 36 | #include "intel_drv.h" |
760285e7 | 37 | #include <drm/i915_drm.h> |
79e53945 | 38 | #include "i915_drv.h" |
e5510fac | 39 | #include "i915_trace.h" |
760285e7 DH |
40 | #include <drm/drm_dp_helper.h> |
41 | #include <drm/drm_crtc_helper.h> | |
c0f372b3 | 42 | #include <linux/dma_remapping.h> |
79e53945 | 43 | |
0206e353 | 44 | bool intel_pipe_has_type(struct drm_crtc *crtc, int type); |
3dec0095 | 45 | static void intel_increase_pllclock(struct drm_crtc *crtc); |
6b383a7f | 46 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on); |
79e53945 JB |
47 | |
48 | typedef struct { | |
0206e353 AJ |
49 | /* given values */ |
50 | int n; | |
51 | int m1, m2; | |
52 | int p1, p2; | |
53 | /* derived values */ | |
54 | int dot; | |
55 | int vco; | |
56 | int m; | |
57 | int p; | |
79e53945 JB |
58 | } intel_clock_t; |
59 | ||
60 | typedef struct { | |
0206e353 | 61 | int min, max; |
79e53945 JB |
62 | } intel_range_t; |
63 | ||
64 | typedef struct { | |
0206e353 AJ |
65 | int dot_limit; |
66 | int p2_slow, p2_fast; | |
79e53945 JB |
67 | } intel_p2_t; |
68 | ||
69 | #define INTEL_P2_NUM 2 | |
d4906093 ML |
70 | typedef struct intel_limit intel_limit_t; |
71 | struct intel_limit { | |
0206e353 AJ |
72 | intel_range_t dot, vco, n, m, m1, m2, p, p1; |
73 | intel_p2_t p2; | |
74 | bool (* find_pll)(const intel_limit_t *, struct drm_crtc *, | |
cec2f356 | 75 | int, int, intel_clock_t *, intel_clock_t *); |
d4906093 | 76 | }; |
79e53945 | 77 | |
2377b741 JB |
78 | /* FDI */ |
79 | #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */ | |
80 | ||
d2acd215 DV |
81 | int |
82 | intel_pch_rawclk(struct drm_device *dev) | |
83 | { | |
84 | struct drm_i915_private *dev_priv = dev->dev_private; | |
85 | ||
86 | WARN_ON(!HAS_PCH_SPLIT(dev)); | |
87 | ||
88 | return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK; | |
89 | } | |
90 | ||
d4906093 ML |
91 | static bool |
92 | intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, | |
cec2f356 SP |
93 | int target, int refclk, intel_clock_t *match_clock, |
94 | intel_clock_t *best_clock); | |
d4906093 ML |
95 | static bool |
96 | intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, | |
cec2f356 SP |
97 | int target, int refclk, intel_clock_t *match_clock, |
98 | intel_clock_t *best_clock); | |
79e53945 | 99 | |
a4fc5ed6 KP |
100 | static bool |
101 | intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc, | |
cec2f356 SP |
102 | int target, int refclk, intel_clock_t *match_clock, |
103 | intel_clock_t *best_clock); | |
5eb08b69 | 104 | static bool |
f2b115e6 | 105 | intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc, |
cec2f356 SP |
106 | int target, int refclk, intel_clock_t *match_clock, |
107 | intel_clock_t *best_clock); | |
a4fc5ed6 | 108 | |
a0c4da24 JB |
109 | static bool |
110 | intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc, | |
111 | int target, int refclk, intel_clock_t *match_clock, | |
112 | intel_clock_t *best_clock); | |
113 | ||
021357ac CW |
114 | static inline u32 /* units of 100MHz */ |
115 | intel_fdi_link_freq(struct drm_device *dev) | |
116 | { | |
8b99e68c CW |
117 | if (IS_GEN5(dev)) { |
118 | struct drm_i915_private *dev_priv = dev->dev_private; | |
119 | return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2; | |
120 | } else | |
121 | return 27; | |
021357ac CW |
122 | } |
123 | ||
e4b36699 | 124 | static const intel_limit_t intel_limits_i8xx_dvo = { |
0206e353 AJ |
125 | .dot = { .min = 25000, .max = 350000 }, |
126 | .vco = { .min = 930000, .max = 1400000 }, | |
127 | .n = { .min = 3, .max = 16 }, | |
128 | .m = { .min = 96, .max = 140 }, | |
129 | .m1 = { .min = 18, .max = 26 }, | |
130 | .m2 = { .min = 6, .max = 16 }, | |
131 | .p = { .min = 4, .max = 128 }, | |
132 | .p1 = { .min = 2, .max = 33 }, | |
273e27ca EA |
133 | .p2 = { .dot_limit = 165000, |
134 | .p2_slow = 4, .p2_fast = 2 }, | |
d4906093 | 135 | .find_pll = intel_find_best_PLL, |
e4b36699 KP |
136 | }; |
137 | ||
138 | static const intel_limit_t intel_limits_i8xx_lvds = { | |
0206e353 AJ |
139 | .dot = { .min = 25000, .max = 350000 }, |
140 | .vco = { .min = 930000, .max = 1400000 }, | |
141 | .n = { .min = 3, .max = 16 }, | |
142 | .m = { .min = 96, .max = 140 }, | |
143 | .m1 = { .min = 18, .max = 26 }, | |
144 | .m2 = { .min = 6, .max = 16 }, | |
145 | .p = { .min = 4, .max = 128 }, | |
146 | .p1 = { .min = 1, .max = 6 }, | |
273e27ca EA |
147 | .p2 = { .dot_limit = 165000, |
148 | .p2_slow = 14, .p2_fast = 7 }, | |
d4906093 | 149 | .find_pll = intel_find_best_PLL, |
e4b36699 | 150 | }; |
273e27ca | 151 | |
e4b36699 | 152 | static const intel_limit_t intel_limits_i9xx_sdvo = { |
0206e353 AJ |
153 | .dot = { .min = 20000, .max = 400000 }, |
154 | .vco = { .min = 1400000, .max = 2800000 }, | |
155 | .n = { .min = 1, .max = 6 }, | |
156 | .m = { .min = 70, .max = 120 }, | |
157 | .m1 = { .min = 10, .max = 22 }, | |
158 | .m2 = { .min = 5, .max = 9 }, | |
159 | .p = { .min = 5, .max = 80 }, | |
160 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
161 | .p2 = { .dot_limit = 200000, |
162 | .p2_slow = 10, .p2_fast = 5 }, | |
d4906093 | 163 | .find_pll = intel_find_best_PLL, |
e4b36699 KP |
164 | }; |
165 | ||
166 | static const intel_limit_t intel_limits_i9xx_lvds = { | |
0206e353 AJ |
167 | .dot = { .min = 20000, .max = 400000 }, |
168 | .vco = { .min = 1400000, .max = 2800000 }, | |
169 | .n = { .min = 1, .max = 6 }, | |
170 | .m = { .min = 70, .max = 120 }, | |
171 | .m1 = { .min = 10, .max = 22 }, | |
172 | .m2 = { .min = 5, .max = 9 }, | |
173 | .p = { .min = 7, .max = 98 }, | |
174 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
175 | .p2 = { .dot_limit = 112000, |
176 | .p2_slow = 14, .p2_fast = 7 }, | |
d4906093 | 177 | .find_pll = intel_find_best_PLL, |
e4b36699 KP |
178 | }; |
179 | ||
273e27ca | 180 | |
e4b36699 | 181 | static const intel_limit_t intel_limits_g4x_sdvo = { |
273e27ca EA |
182 | .dot = { .min = 25000, .max = 270000 }, |
183 | .vco = { .min = 1750000, .max = 3500000}, | |
184 | .n = { .min = 1, .max = 4 }, | |
185 | .m = { .min = 104, .max = 138 }, | |
186 | .m1 = { .min = 17, .max = 23 }, | |
187 | .m2 = { .min = 5, .max = 11 }, | |
188 | .p = { .min = 10, .max = 30 }, | |
189 | .p1 = { .min = 1, .max = 3}, | |
190 | .p2 = { .dot_limit = 270000, | |
191 | .p2_slow = 10, | |
192 | .p2_fast = 10 | |
044c7c41 | 193 | }, |
d4906093 | 194 | .find_pll = intel_g4x_find_best_PLL, |
e4b36699 KP |
195 | }; |
196 | ||
197 | static const intel_limit_t intel_limits_g4x_hdmi = { | |
273e27ca EA |
198 | .dot = { .min = 22000, .max = 400000 }, |
199 | .vco = { .min = 1750000, .max = 3500000}, | |
200 | .n = { .min = 1, .max = 4 }, | |
201 | .m = { .min = 104, .max = 138 }, | |
202 | .m1 = { .min = 16, .max = 23 }, | |
203 | .m2 = { .min = 5, .max = 11 }, | |
204 | .p = { .min = 5, .max = 80 }, | |
205 | .p1 = { .min = 1, .max = 8}, | |
206 | .p2 = { .dot_limit = 165000, | |
207 | .p2_slow = 10, .p2_fast = 5 }, | |
d4906093 | 208 | .find_pll = intel_g4x_find_best_PLL, |
e4b36699 KP |
209 | }; |
210 | ||
211 | static const intel_limit_t intel_limits_g4x_single_channel_lvds = { | |
273e27ca EA |
212 | .dot = { .min = 20000, .max = 115000 }, |
213 | .vco = { .min = 1750000, .max = 3500000 }, | |
214 | .n = { .min = 1, .max = 3 }, | |
215 | .m = { .min = 104, .max = 138 }, | |
216 | .m1 = { .min = 17, .max = 23 }, | |
217 | .m2 = { .min = 5, .max = 11 }, | |
218 | .p = { .min = 28, .max = 112 }, | |
219 | .p1 = { .min = 2, .max = 8 }, | |
220 | .p2 = { .dot_limit = 0, | |
221 | .p2_slow = 14, .p2_fast = 14 | |
044c7c41 | 222 | }, |
d4906093 | 223 | .find_pll = intel_g4x_find_best_PLL, |
e4b36699 KP |
224 | }; |
225 | ||
226 | static const intel_limit_t intel_limits_g4x_dual_channel_lvds = { | |
273e27ca EA |
227 | .dot = { .min = 80000, .max = 224000 }, |
228 | .vco = { .min = 1750000, .max = 3500000 }, | |
229 | .n = { .min = 1, .max = 3 }, | |
230 | .m = { .min = 104, .max = 138 }, | |
231 | .m1 = { .min = 17, .max = 23 }, | |
232 | .m2 = { .min = 5, .max = 11 }, | |
233 | .p = { .min = 14, .max = 42 }, | |
234 | .p1 = { .min = 2, .max = 6 }, | |
235 | .p2 = { .dot_limit = 0, | |
236 | .p2_slow = 7, .p2_fast = 7 | |
044c7c41 | 237 | }, |
d4906093 | 238 | .find_pll = intel_g4x_find_best_PLL, |
e4b36699 KP |
239 | }; |
240 | ||
241 | static const intel_limit_t intel_limits_g4x_display_port = { | |
0206e353 AJ |
242 | .dot = { .min = 161670, .max = 227000 }, |
243 | .vco = { .min = 1750000, .max = 3500000}, | |
244 | .n = { .min = 1, .max = 2 }, | |
245 | .m = { .min = 97, .max = 108 }, | |
246 | .m1 = { .min = 0x10, .max = 0x12 }, | |
247 | .m2 = { .min = 0x05, .max = 0x06 }, | |
248 | .p = { .min = 10, .max = 20 }, | |
249 | .p1 = { .min = 1, .max = 2}, | |
250 | .p2 = { .dot_limit = 0, | |
273e27ca | 251 | .p2_slow = 10, .p2_fast = 10 }, |
0206e353 | 252 | .find_pll = intel_find_pll_g4x_dp, |
e4b36699 KP |
253 | }; |
254 | ||
f2b115e6 | 255 | static const intel_limit_t intel_limits_pineview_sdvo = { |
0206e353 AJ |
256 | .dot = { .min = 20000, .max = 400000}, |
257 | .vco = { .min = 1700000, .max = 3500000 }, | |
273e27ca | 258 | /* Pineview's Ncounter is a ring counter */ |
0206e353 AJ |
259 | .n = { .min = 3, .max = 6 }, |
260 | .m = { .min = 2, .max = 256 }, | |
273e27ca | 261 | /* Pineview only has one combined m divider, which we treat as m2. */ |
0206e353 AJ |
262 | .m1 = { .min = 0, .max = 0 }, |
263 | .m2 = { .min = 0, .max = 254 }, | |
264 | .p = { .min = 5, .max = 80 }, | |
265 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
266 | .p2 = { .dot_limit = 200000, |
267 | .p2_slow = 10, .p2_fast = 5 }, | |
6115707b | 268 | .find_pll = intel_find_best_PLL, |
e4b36699 KP |
269 | }; |
270 | ||
f2b115e6 | 271 | static const intel_limit_t intel_limits_pineview_lvds = { |
0206e353 AJ |
272 | .dot = { .min = 20000, .max = 400000 }, |
273 | .vco = { .min = 1700000, .max = 3500000 }, | |
274 | .n = { .min = 3, .max = 6 }, | |
275 | .m = { .min = 2, .max = 256 }, | |
276 | .m1 = { .min = 0, .max = 0 }, | |
277 | .m2 = { .min = 0, .max = 254 }, | |
278 | .p = { .min = 7, .max = 112 }, | |
279 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
280 | .p2 = { .dot_limit = 112000, |
281 | .p2_slow = 14, .p2_fast = 14 }, | |
6115707b | 282 | .find_pll = intel_find_best_PLL, |
e4b36699 KP |
283 | }; |
284 | ||
273e27ca EA |
285 | /* Ironlake / Sandybridge |
286 | * | |
287 | * We calculate clock using (register_value + 2) for N/M1/M2, so here | |
288 | * the range value for them is (actual_value - 2). | |
289 | */ | |
b91ad0ec | 290 | static const intel_limit_t intel_limits_ironlake_dac = { |
273e27ca EA |
291 | .dot = { .min = 25000, .max = 350000 }, |
292 | .vco = { .min = 1760000, .max = 3510000 }, | |
293 | .n = { .min = 1, .max = 5 }, | |
294 | .m = { .min = 79, .max = 127 }, | |
295 | .m1 = { .min = 12, .max = 22 }, | |
296 | .m2 = { .min = 5, .max = 9 }, | |
297 | .p = { .min = 5, .max = 80 }, | |
298 | .p1 = { .min = 1, .max = 8 }, | |
299 | .p2 = { .dot_limit = 225000, | |
300 | .p2_slow = 10, .p2_fast = 5 }, | |
4547668a | 301 | .find_pll = intel_g4x_find_best_PLL, |
e4b36699 KP |
302 | }; |
303 | ||
b91ad0ec | 304 | static const intel_limit_t intel_limits_ironlake_single_lvds = { |
273e27ca EA |
305 | .dot = { .min = 25000, .max = 350000 }, |
306 | .vco = { .min = 1760000, .max = 3510000 }, | |
307 | .n = { .min = 1, .max = 3 }, | |
308 | .m = { .min = 79, .max = 118 }, | |
309 | .m1 = { .min = 12, .max = 22 }, | |
310 | .m2 = { .min = 5, .max = 9 }, | |
311 | .p = { .min = 28, .max = 112 }, | |
312 | .p1 = { .min = 2, .max = 8 }, | |
313 | .p2 = { .dot_limit = 225000, | |
314 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
315 | .find_pll = intel_g4x_find_best_PLL, |
316 | }; | |
317 | ||
318 | static const intel_limit_t intel_limits_ironlake_dual_lvds = { | |
273e27ca EA |
319 | .dot = { .min = 25000, .max = 350000 }, |
320 | .vco = { .min = 1760000, .max = 3510000 }, | |
321 | .n = { .min = 1, .max = 3 }, | |
322 | .m = { .min = 79, .max = 127 }, | |
323 | .m1 = { .min = 12, .max = 22 }, | |
324 | .m2 = { .min = 5, .max = 9 }, | |
325 | .p = { .min = 14, .max = 56 }, | |
326 | .p1 = { .min = 2, .max = 8 }, | |
327 | .p2 = { .dot_limit = 225000, | |
328 | .p2_slow = 7, .p2_fast = 7 }, | |
b91ad0ec ZW |
329 | .find_pll = intel_g4x_find_best_PLL, |
330 | }; | |
331 | ||
273e27ca | 332 | /* LVDS 100mhz refclk limits. */ |
b91ad0ec | 333 | static const intel_limit_t intel_limits_ironlake_single_lvds_100m = { |
273e27ca EA |
334 | .dot = { .min = 25000, .max = 350000 }, |
335 | .vco = { .min = 1760000, .max = 3510000 }, | |
336 | .n = { .min = 1, .max = 2 }, | |
337 | .m = { .min = 79, .max = 126 }, | |
338 | .m1 = { .min = 12, .max = 22 }, | |
339 | .m2 = { .min = 5, .max = 9 }, | |
340 | .p = { .min = 28, .max = 112 }, | |
0206e353 | 341 | .p1 = { .min = 2, .max = 8 }, |
273e27ca EA |
342 | .p2 = { .dot_limit = 225000, |
343 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
344 | .find_pll = intel_g4x_find_best_PLL, |
345 | }; | |
346 | ||
347 | static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = { | |
273e27ca EA |
348 | .dot = { .min = 25000, .max = 350000 }, |
349 | .vco = { .min = 1760000, .max = 3510000 }, | |
350 | .n = { .min = 1, .max = 3 }, | |
351 | .m = { .min = 79, .max = 126 }, | |
352 | .m1 = { .min = 12, .max = 22 }, | |
353 | .m2 = { .min = 5, .max = 9 }, | |
354 | .p = { .min = 14, .max = 42 }, | |
0206e353 | 355 | .p1 = { .min = 2, .max = 6 }, |
273e27ca EA |
356 | .p2 = { .dot_limit = 225000, |
357 | .p2_slow = 7, .p2_fast = 7 }, | |
4547668a ZY |
358 | .find_pll = intel_g4x_find_best_PLL, |
359 | }; | |
360 | ||
361 | static const intel_limit_t intel_limits_ironlake_display_port = { | |
0206e353 AJ |
362 | .dot = { .min = 25000, .max = 350000 }, |
363 | .vco = { .min = 1760000, .max = 3510000}, | |
364 | .n = { .min = 1, .max = 2 }, | |
365 | .m = { .min = 81, .max = 90 }, | |
366 | .m1 = { .min = 12, .max = 22 }, | |
367 | .m2 = { .min = 5, .max = 9 }, | |
368 | .p = { .min = 10, .max = 20 }, | |
369 | .p1 = { .min = 1, .max = 2}, | |
370 | .p2 = { .dot_limit = 0, | |
273e27ca | 371 | .p2_slow = 10, .p2_fast = 10 }, |
0206e353 | 372 | .find_pll = intel_find_pll_ironlake_dp, |
79e53945 JB |
373 | }; |
374 | ||
a0c4da24 JB |
375 | static const intel_limit_t intel_limits_vlv_dac = { |
376 | .dot = { .min = 25000, .max = 270000 }, | |
377 | .vco = { .min = 4000000, .max = 6000000 }, | |
378 | .n = { .min = 1, .max = 7 }, | |
379 | .m = { .min = 22, .max = 450 }, /* guess */ | |
380 | .m1 = { .min = 2, .max = 3 }, | |
381 | .m2 = { .min = 11, .max = 156 }, | |
382 | .p = { .min = 10, .max = 30 }, | |
383 | .p1 = { .min = 2, .max = 3 }, | |
384 | .p2 = { .dot_limit = 270000, | |
385 | .p2_slow = 2, .p2_fast = 20 }, | |
386 | .find_pll = intel_vlv_find_best_pll, | |
387 | }; | |
388 | ||
389 | static const intel_limit_t intel_limits_vlv_hdmi = { | |
390 | .dot = { .min = 20000, .max = 165000 }, | |
17dc9257 | 391 | .vco = { .min = 4000000, .max = 5994000}, |
a0c4da24 JB |
392 | .n = { .min = 1, .max = 7 }, |
393 | .m = { .min = 60, .max = 300 }, /* guess */ | |
394 | .m1 = { .min = 2, .max = 3 }, | |
395 | .m2 = { .min = 11, .max = 156 }, | |
396 | .p = { .min = 10, .max = 30 }, | |
397 | .p1 = { .min = 2, .max = 3 }, | |
398 | .p2 = { .dot_limit = 270000, | |
399 | .p2_slow = 2, .p2_fast = 20 }, | |
400 | .find_pll = intel_vlv_find_best_pll, | |
401 | }; | |
402 | ||
403 | static const intel_limit_t intel_limits_vlv_dp = { | |
74a4dd2e VP |
404 | .dot = { .min = 25000, .max = 270000 }, |
405 | .vco = { .min = 4000000, .max = 6000000 }, | |
a0c4da24 | 406 | .n = { .min = 1, .max = 7 }, |
74a4dd2e | 407 | .m = { .min = 22, .max = 450 }, |
a0c4da24 JB |
408 | .m1 = { .min = 2, .max = 3 }, |
409 | .m2 = { .min = 11, .max = 156 }, | |
410 | .p = { .min = 10, .max = 30 }, | |
411 | .p1 = { .min = 2, .max = 3 }, | |
412 | .p2 = { .dot_limit = 270000, | |
413 | .p2_slow = 2, .p2_fast = 20 }, | |
414 | .find_pll = intel_vlv_find_best_pll, | |
415 | }; | |
416 | ||
57f350b6 JB |
417 | u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg) |
418 | { | |
09153000 | 419 | WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock)); |
57f350b6 | 420 | |
57f350b6 JB |
421 | if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) { |
422 | DRM_ERROR("DPIO idle wait timed out\n"); | |
09153000 | 423 | return 0; |
57f350b6 JB |
424 | } |
425 | ||
426 | I915_WRITE(DPIO_REG, reg); | |
427 | I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID | | |
428 | DPIO_BYTE); | |
429 | if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) { | |
430 | DRM_ERROR("DPIO read wait timed out\n"); | |
09153000 | 431 | return 0; |
57f350b6 | 432 | } |
57f350b6 | 433 | |
09153000 | 434 | return I915_READ(DPIO_DATA); |
57f350b6 JB |
435 | } |
436 | ||
a0c4da24 JB |
437 | static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg, |
438 | u32 val) | |
439 | { | |
09153000 | 440 | WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock)); |
a0c4da24 | 441 | |
a0c4da24 JB |
442 | if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) { |
443 | DRM_ERROR("DPIO idle wait timed out\n"); | |
09153000 | 444 | return; |
a0c4da24 JB |
445 | } |
446 | ||
447 | I915_WRITE(DPIO_DATA, val); | |
448 | I915_WRITE(DPIO_REG, reg); | |
449 | I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID | | |
450 | DPIO_BYTE); | |
451 | if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) | |
452 | DRM_ERROR("DPIO write wait timed out\n"); | |
a0c4da24 JB |
453 | } |
454 | ||
57f350b6 JB |
455 | static void vlv_init_dpio(struct drm_device *dev) |
456 | { | |
457 | struct drm_i915_private *dev_priv = dev->dev_private; | |
458 | ||
459 | /* Reset the DPIO config */ | |
460 | I915_WRITE(DPIO_CTL, 0); | |
461 | POSTING_READ(DPIO_CTL); | |
462 | I915_WRITE(DPIO_CTL, 1); | |
463 | POSTING_READ(DPIO_CTL); | |
464 | } | |
465 | ||
1b894b59 CW |
466 | static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc, |
467 | int refclk) | |
2c07245f | 468 | { |
b91ad0ec | 469 | struct drm_device *dev = crtc->dev; |
2c07245f | 470 | const intel_limit_t *limit; |
b91ad0ec ZW |
471 | |
472 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
1974cad0 | 473 | if (intel_is_dual_link_lvds(dev)) { |
b91ad0ec | 474 | /* LVDS dual channel */ |
1b894b59 | 475 | if (refclk == 100000) |
b91ad0ec ZW |
476 | limit = &intel_limits_ironlake_dual_lvds_100m; |
477 | else | |
478 | limit = &intel_limits_ironlake_dual_lvds; | |
479 | } else { | |
1b894b59 | 480 | if (refclk == 100000) |
b91ad0ec ZW |
481 | limit = &intel_limits_ironlake_single_lvds_100m; |
482 | else | |
483 | limit = &intel_limits_ironlake_single_lvds; | |
484 | } | |
485 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) || | |
547dc041 | 486 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) |
4547668a | 487 | limit = &intel_limits_ironlake_display_port; |
2c07245f | 488 | else |
b91ad0ec | 489 | limit = &intel_limits_ironlake_dac; |
2c07245f ZW |
490 | |
491 | return limit; | |
492 | } | |
493 | ||
044c7c41 ML |
494 | static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc) |
495 | { | |
496 | struct drm_device *dev = crtc->dev; | |
044c7c41 ML |
497 | const intel_limit_t *limit; |
498 | ||
499 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
1974cad0 | 500 | if (intel_is_dual_link_lvds(dev)) |
044c7c41 | 501 | /* LVDS with dual channel */ |
e4b36699 | 502 | limit = &intel_limits_g4x_dual_channel_lvds; |
044c7c41 ML |
503 | else |
504 | /* LVDS with dual channel */ | |
e4b36699 | 505 | limit = &intel_limits_g4x_single_channel_lvds; |
044c7c41 ML |
506 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) || |
507 | intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) { | |
e4b36699 | 508 | limit = &intel_limits_g4x_hdmi; |
044c7c41 | 509 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) { |
e4b36699 | 510 | limit = &intel_limits_g4x_sdvo; |
0206e353 | 511 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) { |
e4b36699 | 512 | limit = &intel_limits_g4x_display_port; |
044c7c41 | 513 | } else /* The option is for other outputs */ |
e4b36699 | 514 | limit = &intel_limits_i9xx_sdvo; |
044c7c41 ML |
515 | |
516 | return limit; | |
517 | } | |
518 | ||
1b894b59 | 519 | static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk) |
79e53945 JB |
520 | { |
521 | struct drm_device *dev = crtc->dev; | |
522 | const intel_limit_t *limit; | |
523 | ||
bad720ff | 524 | if (HAS_PCH_SPLIT(dev)) |
1b894b59 | 525 | limit = intel_ironlake_limit(crtc, refclk); |
2c07245f | 526 | else if (IS_G4X(dev)) { |
044c7c41 | 527 | limit = intel_g4x_limit(crtc); |
f2b115e6 | 528 | } else if (IS_PINEVIEW(dev)) { |
2177832f | 529 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) |
f2b115e6 | 530 | limit = &intel_limits_pineview_lvds; |
2177832f | 531 | else |
f2b115e6 | 532 | limit = &intel_limits_pineview_sdvo; |
a0c4da24 JB |
533 | } else if (IS_VALLEYVIEW(dev)) { |
534 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) | |
535 | limit = &intel_limits_vlv_dac; | |
536 | else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) | |
537 | limit = &intel_limits_vlv_hdmi; | |
538 | else | |
539 | limit = &intel_limits_vlv_dp; | |
a6c45cf0 CW |
540 | } else if (!IS_GEN2(dev)) { |
541 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) | |
542 | limit = &intel_limits_i9xx_lvds; | |
543 | else | |
544 | limit = &intel_limits_i9xx_sdvo; | |
79e53945 JB |
545 | } else { |
546 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) | |
e4b36699 | 547 | limit = &intel_limits_i8xx_lvds; |
79e53945 | 548 | else |
e4b36699 | 549 | limit = &intel_limits_i8xx_dvo; |
79e53945 JB |
550 | } |
551 | return limit; | |
552 | } | |
553 | ||
f2b115e6 AJ |
554 | /* m1 is reserved as 0 in Pineview, n is a ring counter */ |
555 | static void pineview_clock(int refclk, intel_clock_t *clock) | |
79e53945 | 556 | { |
2177832f SL |
557 | clock->m = clock->m2 + 2; |
558 | clock->p = clock->p1 * clock->p2; | |
559 | clock->vco = refclk * clock->m / clock->n; | |
560 | clock->dot = clock->vco / clock->p; | |
561 | } | |
562 | ||
563 | static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock) | |
564 | { | |
f2b115e6 AJ |
565 | if (IS_PINEVIEW(dev)) { |
566 | pineview_clock(refclk, clock); | |
2177832f SL |
567 | return; |
568 | } | |
79e53945 JB |
569 | clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2); |
570 | clock->p = clock->p1 * clock->p2; | |
571 | clock->vco = refclk * clock->m / (clock->n + 2); | |
572 | clock->dot = clock->vco / clock->p; | |
573 | } | |
574 | ||
79e53945 JB |
575 | /** |
576 | * Returns whether any output on the specified pipe is of the specified type | |
577 | */ | |
4ef69c7a | 578 | bool intel_pipe_has_type(struct drm_crtc *crtc, int type) |
79e53945 | 579 | { |
4ef69c7a | 580 | struct drm_device *dev = crtc->dev; |
4ef69c7a CW |
581 | struct intel_encoder *encoder; |
582 | ||
6c2b7c12 DV |
583 | for_each_encoder_on_crtc(dev, crtc, encoder) |
584 | if (encoder->type == type) | |
4ef69c7a CW |
585 | return true; |
586 | ||
587 | return false; | |
79e53945 JB |
588 | } |
589 | ||
7c04d1d9 | 590 | #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0) |
79e53945 JB |
591 | /** |
592 | * Returns whether the given set of divisors are valid for a given refclk with | |
593 | * the given connectors. | |
594 | */ | |
595 | ||
1b894b59 CW |
596 | static bool intel_PLL_is_valid(struct drm_device *dev, |
597 | const intel_limit_t *limit, | |
598 | const intel_clock_t *clock) | |
79e53945 | 599 | { |
79e53945 | 600 | if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) |
0206e353 | 601 | INTELPllInvalid("p1 out of range\n"); |
79e53945 | 602 | if (clock->p < limit->p.min || limit->p.max < clock->p) |
0206e353 | 603 | INTELPllInvalid("p out of range\n"); |
79e53945 | 604 | if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) |
0206e353 | 605 | INTELPllInvalid("m2 out of range\n"); |
79e53945 | 606 | if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) |
0206e353 | 607 | INTELPllInvalid("m1 out of range\n"); |
f2b115e6 | 608 | if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev)) |
0206e353 | 609 | INTELPllInvalid("m1 <= m2\n"); |
79e53945 | 610 | if (clock->m < limit->m.min || limit->m.max < clock->m) |
0206e353 | 611 | INTELPllInvalid("m out of range\n"); |
79e53945 | 612 | if (clock->n < limit->n.min || limit->n.max < clock->n) |
0206e353 | 613 | INTELPllInvalid("n out of range\n"); |
79e53945 | 614 | if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) |
0206e353 | 615 | INTELPllInvalid("vco out of range\n"); |
79e53945 JB |
616 | /* XXX: We may need to be checking "Dot clock" depending on the multiplier, |
617 | * connector, etc., rather than just a single range. | |
618 | */ | |
619 | if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) | |
0206e353 | 620 | INTELPllInvalid("dot out of range\n"); |
79e53945 JB |
621 | |
622 | return true; | |
623 | } | |
624 | ||
d4906093 ML |
625 | static bool |
626 | intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, | |
cec2f356 SP |
627 | int target, int refclk, intel_clock_t *match_clock, |
628 | intel_clock_t *best_clock) | |
d4906093 | 629 | |
79e53945 JB |
630 | { |
631 | struct drm_device *dev = crtc->dev; | |
79e53945 | 632 | intel_clock_t clock; |
79e53945 JB |
633 | int err = target; |
634 | ||
a210b028 | 635 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
79e53945 | 636 | /* |
a210b028 DV |
637 | * For LVDS just rely on its current settings for dual-channel. |
638 | * We haven't figured out how to reliably set up different | |
639 | * single/dual channel state, if we even can. | |
79e53945 | 640 | */ |
1974cad0 | 641 | if (intel_is_dual_link_lvds(dev)) |
79e53945 JB |
642 | clock.p2 = limit->p2.p2_fast; |
643 | else | |
644 | clock.p2 = limit->p2.p2_slow; | |
645 | } else { | |
646 | if (target < limit->p2.dot_limit) | |
647 | clock.p2 = limit->p2.p2_slow; | |
648 | else | |
649 | clock.p2 = limit->p2.p2_fast; | |
650 | } | |
651 | ||
0206e353 | 652 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 653 | |
42158660 ZY |
654 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
655 | clock.m1++) { | |
656 | for (clock.m2 = limit->m2.min; | |
657 | clock.m2 <= limit->m2.max; clock.m2++) { | |
f2b115e6 AJ |
658 | /* m1 is always 0 in Pineview */ |
659 | if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev)) | |
42158660 ZY |
660 | break; |
661 | for (clock.n = limit->n.min; | |
662 | clock.n <= limit->n.max; clock.n++) { | |
663 | for (clock.p1 = limit->p1.min; | |
664 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
665 | int this_err; |
666 | ||
2177832f | 667 | intel_clock(dev, refclk, &clock); |
1b894b59 CW |
668 | if (!intel_PLL_is_valid(dev, limit, |
669 | &clock)) | |
79e53945 | 670 | continue; |
cec2f356 SP |
671 | if (match_clock && |
672 | clock.p != match_clock->p) | |
673 | continue; | |
79e53945 JB |
674 | |
675 | this_err = abs(clock.dot - target); | |
676 | if (this_err < err) { | |
677 | *best_clock = clock; | |
678 | err = this_err; | |
679 | } | |
680 | } | |
681 | } | |
682 | } | |
683 | } | |
684 | ||
685 | return (err != target); | |
686 | } | |
687 | ||
d4906093 ML |
688 | static bool |
689 | intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, | |
cec2f356 SP |
690 | int target, int refclk, intel_clock_t *match_clock, |
691 | intel_clock_t *best_clock) | |
d4906093 ML |
692 | { |
693 | struct drm_device *dev = crtc->dev; | |
d4906093 ML |
694 | intel_clock_t clock; |
695 | int max_n; | |
696 | bool found; | |
6ba770dc AJ |
697 | /* approximately equals target * 0.00585 */ |
698 | int err_most = (target >> 8) + (target >> 9); | |
d4906093 ML |
699 | found = false; |
700 | ||
701 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
4547668a ZY |
702 | int lvds_reg; |
703 | ||
c619eed4 | 704 | if (HAS_PCH_SPLIT(dev)) |
4547668a ZY |
705 | lvds_reg = PCH_LVDS; |
706 | else | |
707 | lvds_reg = LVDS; | |
1974cad0 | 708 | if (intel_is_dual_link_lvds(dev)) |
d4906093 ML |
709 | clock.p2 = limit->p2.p2_fast; |
710 | else | |
711 | clock.p2 = limit->p2.p2_slow; | |
712 | } else { | |
713 | if (target < limit->p2.dot_limit) | |
714 | clock.p2 = limit->p2.p2_slow; | |
715 | else | |
716 | clock.p2 = limit->p2.p2_fast; | |
717 | } | |
718 | ||
719 | memset(best_clock, 0, sizeof(*best_clock)); | |
720 | max_n = limit->n.max; | |
f77f13e2 | 721 | /* based on hardware requirement, prefer smaller n to precision */ |
d4906093 | 722 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
f77f13e2 | 723 | /* based on hardware requirement, prefere larger m1,m2 */ |
d4906093 ML |
724 | for (clock.m1 = limit->m1.max; |
725 | clock.m1 >= limit->m1.min; clock.m1--) { | |
726 | for (clock.m2 = limit->m2.max; | |
727 | clock.m2 >= limit->m2.min; clock.m2--) { | |
728 | for (clock.p1 = limit->p1.max; | |
729 | clock.p1 >= limit->p1.min; clock.p1--) { | |
730 | int this_err; | |
731 | ||
2177832f | 732 | intel_clock(dev, refclk, &clock); |
1b894b59 CW |
733 | if (!intel_PLL_is_valid(dev, limit, |
734 | &clock)) | |
d4906093 | 735 | continue; |
cec2f356 SP |
736 | if (match_clock && |
737 | clock.p != match_clock->p) | |
738 | continue; | |
1b894b59 CW |
739 | |
740 | this_err = abs(clock.dot - target); | |
d4906093 ML |
741 | if (this_err < err_most) { |
742 | *best_clock = clock; | |
743 | err_most = this_err; | |
744 | max_n = clock.n; | |
745 | found = true; | |
746 | } | |
747 | } | |
748 | } | |
749 | } | |
750 | } | |
2c07245f ZW |
751 | return found; |
752 | } | |
753 | ||
5eb08b69 | 754 | static bool |
f2b115e6 | 755 | intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc, |
cec2f356 SP |
756 | int target, int refclk, intel_clock_t *match_clock, |
757 | intel_clock_t *best_clock) | |
5eb08b69 ZW |
758 | { |
759 | struct drm_device *dev = crtc->dev; | |
760 | intel_clock_t clock; | |
4547668a | 761 | |
5eb08b69 ZW |
762 | if (target < 200000) { |
763 | clock.n = 1; | |
764 | clock.p1 = 2; | |
765 | clock.p2 = 10; | |
766 | clock.m1 = 12; | |
767 | clock.m2 = 9; | |
768 | } else { | |
769 | clock.n = 2; | |
770 | clock.p1 = 1; | |
771 | clock.p2 = 10; | |
772 | clock.m1 = 14; | |
773 | clock.m2 = 8; | |
774 | } | |
775 | intel_clock(dev, refclk, &clock); | |
776 | memcpy(best_clock, &clock, sizeof(intel_clock_t)); | |
777 | return true; | |
778 | } | |
779 | ||
a4fc5ed6 KP |
780 | /* DisplayPort has only two frequencies, 162MHz and 270MHz */ |
781 | static bool | |
782 | intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc, | |
cec2f356 SP |
783 | int target, int refclk, intel_clock_t *match_clock, |
784 | intel_clock_t *best_clock) | |
a4fc5ed6 | 785 | { |
5eddb70b CW |
786 | intel_clock_t clock; |
787 | if (target < 200000) { | |
788 | clock.p1 = 2; | |
789 | clock.p2 = 10; | |
790 | clock.n = 2; | |
791 | clock.m1 = 23; | |
792 | clock.m2 = 8; | |
793 | } else { | |
794 | clock.p1 = 1; | |
795 | clock.p2 = 10; | |
796 | clock.n = 1; | |
797 | clock.m1 = 14; | |
798 | clock.m2 = 2; | |
799 | } | |
800 | clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2); | |
801 | clock.p = (clock.p1 * clock.p2); | |
802 | clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p; | |
803 | clock.vco = 0; | |
804 | memcpy(best_clock, &clock, sizeof(intel_clock_t)); | |
805 | return true; | |
a4fc5ed6 | 806 | } |
a0c4da24 JB |
807 | static bool |
808 | intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc, | |
809 | int target, int refclk, intel_clock_t *match_clock, | |
810 | intel_clock_t *best_clock) | |
811 | { | |
812 | u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2; | |
813 | u32 m, n, fastclk; | |
814 | u32 updrate, minupdate, fracbits, p; | |
815 | unsigned long bestppm, ppm, absppm; | |
816 | int dotclk, flag; | |
817 | ||
af447bd3 | 818 | flag = 0; |
a0c4da24 JB |
819 | dotclk = target * 1000; |
820 | bestppm = 1000000; | |
821 | ppm = absppm = 0; | |
822 | fastclk = dotclk / (2*100); | |
823 | updrate = 0; | |
824 | minupdate = 19200; | |
825 | fracbits = 1; | |
826 | n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0; | |
827 | bestm1 = bestm2 = bestp1 = bestp2 = 0; | |
828 | ||
829 | /* based on hardware requirement, prefer smaller n to precision */ | |
830 | for (n = limit->n.min; n <= ((refclk) / minupdate); n++) { | |
831 | updrate = refclk / n; | |
832 | for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) { | |
833 | for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) { | |
834 | if (p2 > 10) | |
835 | p2 = p2 - 1; | |
836 | p = p1 * p2; | |
837 | /* based on hardware requirement, prefer bigger m1,m2 values */ | |
838 | for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) { | |
839 | m2 = (((2*(fastclk * p * n / m1 )) + | |
840 | refclk) / (2*refclk)); | |
841 | m = m1 * m2; | |
842 | vco = updrate * m; | |
843 | if (vco >= limit->vco.min && vco < limit->vco.max) { | |
844 | ppm = 1000000 * ((vco / p) - fastclk) / fastclk; | |
845 | absppm = (ppm > 0) ? ppm : (-ppm); | |
846 | if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) { | |
847 | bestppm = 0; | |
848 | flag = 1; | |
849 | } | |
850 | if (absppm < bestppm - 10) { | |
851 | bestppm = absppm; | |
852 | flag = 1; | |
853 | } | |
854 | if (flag) { | |
855 | bestn = n; | |
856 | bestm1 = m1; | |
857 | bestm2 = m2; | |
858 | bestp1 = p1; | |
859 | bestp2 = p2; | |
860 | flag = 0; | |
861 | } | |
862 | } | |
863 | } | |
864 | } | |
865 | } | |
866 | } | |
867 | best_clock->n = bestn; | |
868 | best_clock->m1 = bestm1; | |
869 | best_clock->m2 = bestm2; | |
870 | best_clock->p1 = bestp1; | |
871 | best_clock->p2 = bestp2; | |
872 | ||
873 | return true; | |
874 | } | |
a4fc5ed6 | 875 | |
a5c961d1 PZ |
876 | enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, |
877 | enum pipe pipe) | |
878 | { | |
879 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
880 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
881 | ||
882 | return intel_crtc->cpu_transcoder; | |
883 | } | |
884 | ||
a928d536 PZ |
885 | static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe) |
886 | { | |
887 | struct drm_i915_private *dev_priv = dev->dev_private; | |
888 | u32 frame, frame_reg = PIPEFRAME(pipe); | |
889 | ||
890 | frame = I915_READ(frame_reg); | |
891 | ||
892 | if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50)) | |
893 | DRM_DEBUG_KMS("vblank wait timed out\n"); | |
894 | } | |
895 | ||
9d0498a2 JB |
896 | /** |
897 | * intel_wait_for_vblank - wait for vblank on a given pipe | |
898 | * @dev: drm device | |
899 | * @pipe: pipe to wait for | |
900 | * | |
901 | * Wait for vblank to occur on a given pipe. Needed for various bits of | |
902 | * mode setting code. | |
903 | */ | |
904 | void intel_wait_for_vblank(struct drm_device *dev, int pipe) | |
79e53945 | 905 | { |
9d0498a2 | 906 | struct drm_i915_private *dev_priv = dev->dev_private; |
9db4a9c7 | 907 | int pipestat_reg = PIPESTAT(pipe); |
9d0498a2 | 908 | |
a928d536 PZ |
909 | if (INTEL_INFO(dev)->gen >= 5) { |
910 | ironlake_wait_for_vblank(dev, pipe); | |
911 | return; | |
912 | } | |
913 | ||
300387c0 CW |
914 | /* Clear existing vblank status. Note this will clear any other |
915 | * sticky status fields as well. | |
916 | * | |
917 | * This races with i915_driver_irq_handler() with the result | |
918 | * that either function could miss a vblank event. Here it is not | |
919 | * fatal, as we will either wait upon the next vblank interrupt or | |
920 | * timeout. Generally speaking intel_wait_for_vblank() is only | |
921 | * called during modeset at which time the GPU should be idle and | |
922 | * should *not* be performing page flips and thus not waiting on | |
923 | * vblanks... | |
924 | * Currently, the result of us stealing a vblank from the irq | |
925 | * handler is that a single frame will be skipped during swapbuffers. | |
926 | */ | |
927 | I915_WRITE(pipestat_reg, | |
928 | I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS); | |
929 | ||
9d0498a2 | 930 | /* Wait for vblank interrupt bit to set */ |
481b6af3 CW |
931 | if (wait_for(I915_READ(pipestat_reg) & |
932 | PIPE_VBLANK_INTERRUPT_STATUS, | |
933 | 50)) | |
9d0498a2 JB |
934 | DRM_DEBUG_KMS("vblank wait timed out\n"); |
935 | } | |
936 | ||
ab7ad7f6 KP |
937 | /* |
938 | * intel_wait_for_pipe_off - wait for pipe to turn off | |
9d0498a2 JB |
939 | * @dev: drm device |
940 | * @pipe: pipe to wait for | |
941 | * | |
942 | * After disabling a pipe, we can't wait for vblank in the usual way, | |
943 | * spinning on the vblank interrupt status bit, since we won't actually | |
944 | * see an interrupt when the pipe is disabled. | |
945 | * | |
ab7ad7f6 KP |
946 | * On Gen4 and above: |
947 | * wait for the pipe register state bit to turn off | |
948 | * | |
949 | * Otherwise: | |
950 | * wait for the display line value to settle (it usually | |
951 | * ends up stopping at the start of the next frame). | |
58e10eb9 | 952 | * |
9d0498a2 | 953 | */ |
58e10eb9 | 954 | void intel_wait_for_pipe_off(struct drm_device *dev, int pipe) |
9d0498a2 JB |
955 | { |
956 | struct drm_i915_private *dev_priv = dev->dev_private; | |
702e7a56 PZ |
957 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
958 | pipe); | |
ab7ad7f6 KP |
959 | |
960 | if (INTEL_INFO(dev)->gen >= 4) { | |
702e7a56 | 961 | int reg = PIPECONF(cpu_transcoder); |
ab7ad7f6 KP |
962 | |
963 | /* Wait for the Pipe State to go off */ | |
58e10eb9 CW |
964 | if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0, |
965 | 100)) | |
284637d9 | 966 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 967 | } else { |
837ba00f | 968 | u32 last_line, line_mask; |
58e10eb9 | 969 | int reg = PIPEDSL(pipe); |
ab7ad7f6 KP |
970 | unsigned long timeout = jiffies + msecs_to_jiffies(100); |
971 | ||
837ba00f PZ |
972 | if (IS_GEN2(dev)) |
973 | line_mask = DSL_LINEMASK_GEN2; | |
974 | else | |
975 | line_mask = DSL_LINEMASK_GEN3; | |
976 | ||
ab7ad7f6 KP |
977 | /* Wait for the display line to settle */ |
978 | do { | |
837ba00f | 979 | last_line = I915_READ(reg) & line_mask; |
ab7ad7f6 | 980 | mdelay(5); |
837ba00f | 981 | } while (((I915_READ(reg) & line_mask) != last_line) && |
ab7ad7f6 KP |
982 | time_after(timeout, jiffies)); |
983 | if (time_after(jiffies, timeout)) | |
284637d9 | 984 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 985 | } |
79e53945 JB |
986 | } |
987 | ||
b0ea7d37 DL |
988 | /* |
989 | * ibx_digital_port_connected - is the specified port connected? | |
990 | * @dev_priv: i915 private structure | |
991 | * @port: the port to test | |
992 | * | |
993 | * Returns true if @port is connected, false otherwise. | |
994 | */ | |
995 | bool ibx_digital_port_connected(struct drm_i915_private *dev_priv, | |
996 | struct intel_digital_port *port) | |
997 | { | |
998 | u32 bit; | |
999 | ||
c36346e3 DL |
1000 | if (HAS_PCH_IBX(dev_priv->dev)) { |
1001 | switch(port->port) { | |
1002 | case PORT_B: | |
1003 | bit = SDE_PORTB_HOTPLUG; | |
1004 | break; | |
1005 | case PORT_C: | |
1006 | bit = SDE_PORTC_HOTPLUG; | |
1007 | break; | |
1008 | case PORT_D: | |
1009 | bit = SDE_PORTD_HOTPLUG; | |
1010 | break; | |
1011 | default: | |
1012 | return true; | |
1013 | } | |
1014 | } else { | |
1015 | switch(port->port) { | |
1016 | case PORT_B: | |
1017 | bit = SDE_PORTB_HOTPLUG_CPT; | |
1018 | break; | |
1019 | case PORT_C: | |
1020 | bit = SDE_PORTC_HOTPLUG_CPT; | |
1021 | break; | |
1022 | case PORT_D: | |
1023 | bit = SDE_PORTD_HOTPLUG_CPT; | |
1024 | break; | |
1025 | default: | |
1026 | return true; | |
1027 | } | |
b0ea7d37 DL |
1028 | } |
1029 | ||
1030 | return I915_READ(SDEISR) & bit; | |
1031 | } | |
1032 | ||
b24e7179 JB |
1033 | static const char *state_string(bool enabled) |
1034 | { | |
1035 | return enabled ? "on" : "off"; | |
1036 | } | |
1037 | ||
1038 | /* Only for pre-ILK configs */ | |
1039 | static void assert_pll(struct drm_i915_private *dev_priv, | |
1040 | enum pipe pipe, bool state) | |
1041 | { | |
1042 | int reg; | |
1043 | u32 val; | |
1044 | bool cur_state; | |
1045 | ||
1046 | reg = DPLL(pipe); | |
1047 | val = I915_READ(reg); | |
1048 | cur_state = !!(val & DPLL_VCO_ENABLE); | |
1049 | WARN(cur_state != state, | |
1050 | "PLL state assertion failure (expected %s, current %s)\n", | |
1051 | state_string(state), state_string(cur_state)); | |
1052 | } | |
1053 | #define assert_pll_enabled(d, p) assert_pll(d, p, true) | |
1054 | #define assert_pll_disabled(d, p) assert_pll(d, p, false) | |
1055 | ||
040484af JB |
1056 | /* For ILK+ */ |
1057 | static void assert_pch_pll(struct drm_i915_private *dev_priv, | |
92b27b08 CW |
1058 | struct intel_pch_pll *pll, |
1059 | struct intel_crtc *crtc, | |
1060 | bool state) | |
040484af | 1061 | { |
040484af JB |
1062 | u32 val; |
1063 | bool cur_state; | |
1064 | ||
9d82aa17 ED |
1065 | if (HAS_PCH_LPT(dev_priv->dev)) { |
1066 | DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n"); | |
1067 | return; | |
1068 | } | |
1069 | ||
92b27b08 CW |
1070 | if (WARN (!pll, |
1071 | "asserting PCH PLL %s with no PLL\n", state_string(state))) | |
ee7b9f93 | 1072 | return; |
ee7b9f93 | 1073 | |
92b27b08 CW |
1074 | val = I915_READ(pll->pll_reg); |
1075 | cur_state = !!(val & DPLL_VCO_ENABLE); | |
1076 | WARN(cur_state != state, | |
1077 | "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n", | |
1078 | pll->pll_reg, state_string(state), state_string(cur_state), val); | |
1079 | ||
1080 | /* Make sure the selected PLL is correctly attached to the transcoder */ | |
1081 | if (crtc && HAS_PCH_CPT(dev_priv->dev)) { | |
d3ccbe86 JB |
1082 | u32 pch_dpll; |
1083 | ||
1084 | pch_dpll = I915_READ(PCH_DPLL_SEL); | |
92b27b08 CW |
1085 | cur_state = pll->pll_reg == _PCH_DPLL_B; |
1086 | if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state, | |
1087 | "PLL[%d] not attached to this transcoder %d: %08x\n", | |
1088 | cur_state, crtc->pipe, pch_dpll)) { | |
1089 | cur_state = !!(val >> (4*crtc->pipe + 3)); | |
1090 | WARN(cur_state != state, | |
1091 | "PLL[%d] not %s on this transcoder %d: %08x\n", | |
1092 | pll->pll_reg == _PCH_DPLL_B, | |
1093 | state_string(state), | |
1094 | crtc->pipe, | |
1095 | val); | |
1096 | } | |
d3ccbe86 | 1097 | } |
040484af | 1098 | } |
92b27b08 CW |
1099 | #define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true) |
1100 | #define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false) | |
040484af JB |
1101 | |
1102 | static void assert_fdi_tx(struct drm_i915_private *dev_priv, | |
1103 | enum pipe pipe, bool state) | |
1104 | { | |
1105 | int reg; | |
1106 | u32 val; | |
1107 | bool cur_state; | |
ad80a810 PZ |
1108 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1109 | pipe); | |
040484af | 1110 | |
affa9354 PZ |
1111 | if (HAS_DDI(dev_priv->dev)) { |
1112 | /* DDI does not have a specific FDI_TX register */ | |
ad80a810 | 1113 | reg = TRANS_DDI_FUNC_CTL(cpu_transcoder); |
bf507ef7 | 1114 | val = I915_READ(reg); |
ad80a810 | 1115 | cur_state = !!(val & TRANS_DDI_FUNC_ENABLE); |
bf507ef7 ED |
1116 | } else { |
1117 | reg = FDI_TX_CTL(pipe); | |
1118 | val = I915_READ(reg); | |
1119 | cur_state = !!(val & FDI_TX_ENABLE); | |
1120 | } | |
040484af JB |
1121 | WARN(cur_state != state, |
1122 | "FDI TX state assertion failure (expected %s, current %s)\n", | |
1123 | state_string(state), state_string(cur_state)); | |
1124 | } | |
1125 | #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true) | |
1126 | #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false) | |
1127 | ||
1128 | static void assert_fdi_rx(struct drm_i915_private *dev_priv, | |
1129 | enum pipe pipe, bool state) | |
1130 | { | |
1131 | int reg; | |
1132 | u32 val; | |
1133 | bool cur_state; | |
1134 | ||
d63fa0dc PZ |
1135 | reg = FDI_RX_CTL(pipe); |
1136 | val = I915_READ(reg); | |
1137 | cur_state = !!(val & FDI_RX_ENABLE); | |
040484af JB |
1138 | WARN(cur_state != state, |
1139 | "FDI RX state assertion failure (expected %s, current %s)\n", | |
1140 | state_string(state), state_string(cur_state)); | |
1141 | } | |
1142 | #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true) | |
1143 | #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false) | |
1144 | ||
1145 | static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv, | |
1146 | enum pipe pipe) | |
1147 | { | |
1148 | int reg; | |
1149 | u32 val; | |
1150 | ||
1151 | /* ILK FDI PLL is always enabled */ | |
1152 | if (dev_priv->info->gen == 5) | |
1153 | return; | |
1154 | ||
bf507ef7 | 1155 | /* On Haswell, DDI ports are responsible for the FDI PLL setup */ |
affa9354 | 1156 | if (HAS_DDI(dev_priv->dev)) |
bf507ef7 ED |
1157 | return; |
1158 | ||
040484af JB |
1159 | reg = FDI_TX_CTL(pipe); |
1160 | val = I915_READ(reg); | |
1161 | WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n"); | |
1162 | } | |
1163 | ||
1164 | static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv, | |
1165 | enum pipe pipe) | |
1166 | { | |
1167 | int reg; | |
1168 | u32 val; | |
1169 | ||
1170 | reg = FDI_RX_CTL(pipe); | |
1171 | val = I915_READ(reg); | |
1172 | WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n"); | |
1173 | } | |
1174 | ||
ea0760cf JB |
1175 | static void assert_panel_unlocked(struct drm_i915_private *dev_priv, |
1176 | enum pipe pipe) | |
1177 | { | |
1178 | int pp_reg, lvds_reg; | |
1179 | u32 val; | |
1180 | enum pipe panel_pipe = PIPE_A; | |
0de3b485 | 1181 | bool locked = true; |
ea0760cf JB |
1182 | |
1183 | if (HAS_PCH_SPLIT(dev_priv->dev)) { | |
1184 | pp_reg = PCH_PP_CONTROL; | |
1185 | lvds_reg = PCH_LVDS; | |
1186 | } else { | |
1187 | pp_reg = PP_CONTROL; | |
1188 | lvds_reg = LVDS; | |
1189 | } | |
1190 | ||
1191 | val = I915_READ(pp_reg); | |
1192 | if (!(val & PANEL_POWER_ON) || | |
1193 | ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS)) | |
1194 | locked = false; | |
1195 | ||
1196 | if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT) | |
1197 | panel_pipe = PIPE_B; | |
1198 | ||
1199 | WARN(panel_pipe == pipe && locked, | |
1200 | "panel assertion failure, pipe %c regs locked\n", | |
9db4a9c7 | 1201 | pipe_name(pipe)); |
ea0760cf JB |
1202 | } |
1203 | ||
b840d907 JB |
1204 | void assert_pipe(struct drm_i915_private *dev_priv, |
1205 | enum pipe pipe, bool state) | |
b24e7179 JB |
1206 | { |
1207 | int reg; | |
1208 | u32 val; | |
63d7bbe9 | 1209 | bool cur_state; |
702e7a56 PZ |
1210 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1211 | pipe); | |
b24e7179 | 1212 | |
8e636784 DV |
1213 | /* if we need the pipe A quirk it must be always on */ |
1214 | if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) | |
1215 | state = true; | |
1216 | ||
702e7a56 | 1217 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 1218 | val = I915_READ(reg); |
63d7bbe9 JB |
1219 | cur_state = !!(val & PIPECONF_ENABLE); |
1220 | WARN(cur_state != state, | |
1221 | "pipe %c assertion failure (expected %s, current %s)\n", | |
9db4a9c7 | 1222 | pipe_name(pipe), state_string(state), state_string(cur_state)); |
b24e7179 JB |
1223 | } |
1224 | ||
931872fc CW |
1225 | static void assert_plane(struct drm_i915_private *dev_priv, |
1226 | enum plane plane, bool state) | |
b24e7179 JB |
1227 | { |
1228 | int reg; | |
1229 | u32 val; | |
931872fc | 1230 | bool cur_state; |
b24e7179 JB |
1231 | |
1232 | reg = DSPCNTR(plane); | |
1233 | val = I915_READ(reg); | |
931872fc CW |
1234 | cur_state = !!(val & DISPLAY_PLANE_ENABLE); |
1235 | WARN(cur_state != state, | |
1236 | "plane %c assertion failure (expected %s, current %s)\n", | |
1237 | plane_name(plane), state_string(state), state_string(cur_state)); | |
b24e7179 JB |
1238 | } |
1239 | ||
931872fc CW |
1240 | #define assert_plane_enabled(d, p) assert_plane(d, p, true) |
1241 | #define assert_plane_disabled(d, p) assert_plane(d, p, false) | |
1242 | ||
b24e7179 JB |
1243 | static void assert_planes_disabled(struct drm_i915_private *dev_priv, |
1244 | enum pipe pipe) | |
1245 | { | |
1246 | int reg, i; | |
1247 | u32 val; | |
1248 | int cur_pipe; | |
1249 | ||
19ec1358 | 1250 | /* Planes are fixed to pipes on ILK+ */ |
28c05794 AJ |
1251 | if (HAS_PCH_SPLIT(dev_priv->dev)) { |
1252 | reg = DSPCNTR(pipe); | |
1253 | val = I915_READ(reg); | |
1254 | WARN((val & DISPLAY_PLANE_ENABLE), | |
1255 | "plane %c assertion failure, should be disabled but not\n", | |
1256 | plane_name(pipe)); | |
19ec1358 | 1257 | return; |
28c05794 | 1258 | } |
19ec1358 | 1259 | |
b24e7179 JB |
1260 | /* Need to check both planes against the pipe */ |
1261 | for (i = 0; i < 2; i++) { | |
1262 | reg = DSPCNTR(i); | |
1263 | val = I915_READ(reg); | |
1264 | cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >> | |
1265 | DISPPLANE_SEL_PIPE_SHIFT; | |
1266 | WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe, | |
9db4a9c7 JB |
1267 | "plane %c assertion failure, should be off on pipe %c but is still active\n", |
1268 | plane_name(i), pipe_name(pipe)); | |
b24e7179 JB |
1269 | } |
1270 | } | |
1271 | ||
92f2584a JB |
1272 | static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv) |
1273 | { | |
1274 | u32 val; | |
1275 | bool enabled; | |
1276 | ||
9d82aa17 ED |
1277 | if (HAS_PCH_LPT(dev_priv->dev)) { |
1278 | DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n"); | |
1279 | return; | |
1280 | } | |
1281 | ||
92f2584a JB |
1282 | val = I915_READ(PCH_DREF_CONTROL); |
1283 | enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK | | |
1284 | DREF_SUPERSPREAD_SOURCE_MASK)); | |
1285 | WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n"); | |
1286 | } | |
1287 | ||
1288 | static void assert_transcoder_disabled(struct drm_i915_private *dev_priv, | |
1289 | enum pipe pipe) | |
1290 | { | |
1291 | int reg; | |
1292 | u32 val; | |
1293 | bool enabled; | |
1294 | ||
1295 | reg = TRANSCONF(pipe); | |
1296 | val = I915_READ(reg); | |
1297 | enabled = !!(val & TRANS_ENABLE); | |
9db4a9c7 JB |
1298 | WARN(enabled, |
1299 | "transcoder assertion failed, should be off on pipe %c but is still active\n", | |
1300 | pipe_name(pipe)); | |
92f2584a JB |
1301 | } |
1302 | ||
4e634389 KP |
1303 | static bool dp_pipe_enabled(struct drm_i915_private *dev_priv, |
1304 | enum pipe pipe, u32 port_sel, u32 val) | |
f0575e92 KP |
1305 | { |
1306 | if ((val & DP_PORT_EN) == 0) | |
1307 | return false; | |
1308 | ||
1309 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1310 | u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe); | |
1311 | u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg); | |
1312 | if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel) | |
1313 | return false; | |
1314 | } else { | |
1315 | if ((val & DP_PIPE_MASK) != (pipe << 30)) | |
1316 | return false; | |
1317 | } | |
1318 | return true; | |
1319 | } | |
1320 | ||
1519b995 KP |
1321 | static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv, |
1322 | enum pipe pipe, u32 val) | |
1323 | { | |
1324 | if ((val & PORT_ENABLE) == 0) | |
1325 | return false; | |
1326 | ||
1327 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1328 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1329 | return false; | |
1330 | } else { | |
1331 | if ((val & TRANSCODER_MASK) != TRANSCODER(pipe)) | |
1332 | return false; | |
1333 | } | |
1334 | return true; | |
1335 | } | |
1336 | ||
1337 | static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv, | |
1338 | enum pipe pipe, u32 val) | |
1339 | { | |
1340 | if ((val & LVDS_PORT_EN) == 0) | |
1341 | return false; | |
1342 | ||
1343 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1344 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1345 | return false; | |
1346 | } else { | |
1347 | if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe)) | |
1348 | return false; | |
1349 | } | |
1350 | return true; | |
1351 | } | |
1352 | ||
1353 | static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv, | |
1354 | enum pipe pipe, u32 val) | |
1355 | { | |
1356 | if ((val & ADPA_DAC_ENABLE) == 0) | |
1357 | return false; | |
1358 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1359 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1360 | return false; | |
1361 | } else { | |
1362 | if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe)) | |
1363 | return false; | |
1364 | } | |
1365 | return true; | |
1366 | } | |
1367 | ||
291906f1 | 1368 | static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv, |
f0575e92 | 1369 | enum pipe pipe, int reg, u32 port_sel) |
291906f1 | 1370 | { |
47a05eca | 1371 | u32 val = I915_READ(reg); |
4e634389 | 1372 | WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val), |
291906f1 | 1373 | "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1374 | reg, pipe_name(pipe)); |
de9a35ab | 1375 | |
75c5da27 DV |
1376 | WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0 |
1377 | && (val & DP_PIPEB_SELECT), | |
de9a35ab | 1378 | "IBX PCH dp port still using transcoder B\n"); |
291906f1 JB |
1379 | } |
1380 | ||
1381 | static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv, | |
1382 | enum pipe pipe, int reg) | |
1383 | { | |
47a05eca | 1384 | u32 val = I915_READ(reg); |
b70ad586 | 1385 | WARN(hdmi_pipe_enabled(dev_priv, pipe, val), |
23c99e77 | 1386 | "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1387 | reg, pipe_name(pipe)); |
de9a35ab | 1388 | |
75c5da27 DV |
1389 | WARN(HAS_PCH_IBX(dev_priv->dev) && (val & PORT_ENABLE) == 0 |
1390 | && (val & SDVO_PIPE_B_SELECT), | |
de9a35ab | 1391 | "IBX PCH hdmi port still using transcoder B\n"); |
291906f1 JB |
1392 | } |
1393 | ||
1394 | static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv, | |
1395 | enum pipe pipe) | |
1396 | { | |
1397 | int reg; | |
1398 | u32 val; | |
291906f1 | 1399 | |
f0575e92 KP |
1400 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B); |
1401 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C); | |
1402 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D); | |
291906f1 JB |
1403 | |
1404 | reg = PCH_ADPA; | |
1405 | val = I915_READ(reg); | |
b70ad586 | 1406 | WARN(adpa_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1407 | "PCH VGA enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1408 | pipe_name(pipe)); |
291906f1 JB |
1409 | |
1410 | reg = PCH_LVDS; | |
1411 | val = I915_READ(reg); | |
b70ad586 | 1412 | WARN(lvds_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1413 | "PCH LVDS enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1414 | pipe_name(pipe)); |
291906f1 JB |
1415 | |
1416 | assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB); | |
1417 | assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC); | |
1418 | assert_pch_hdmi_disabled(dev_priv, pipe, HDMID); | |
1419 | } | |
1420 | ||
63d7bbe9 JB |
1421 | /** |
1422 | * intel_enable_pll - enable a PLL | |
1423 | * @dev_priv: i915 private structure | |
1424 | * @pipe: pipe PLL to enable | |
1425 | * | |
1426 | * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to | |
1427 | * make sure the PLL reg is writable first though, since the panel write | |
1428 | * protect mechanism may be enabled. | |
1429 | * | |
1430 | * Note! This is for pre-ILK only. | |
7434a255 TR |
1431 | * |
1432 | * Unfortunately needed by dvo_ns2501 since the dvo depends on it running. | |
63d7bbe9 JB |
1433 | */ |
1434 | static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) | |
1435 | { | |
1436 | int reg; | |
1437 | u32 val; | |
1438 | ||
1439 | /* No really, not for ILK+ */ | |
a0c4da24 | 1440 | BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5); |
63d7bbe9 JB |
1441 | |
1442 | /* PLL is protected by panel, make sure we can write it */ | |
1443 | if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev)) | |
1444 | assert_panel_unlocked(dev_priv, pipe); | |
1445 | ||
1446 | reg = DPLL(pipe); | |
1447 | val = I915_READ(reg); | |
1448 | val |= DPLL_VCO_ENABLE; | |
1449 | ||
1450 | /* We do this three times for luck */ | |
1451 | I915_WRITE(reg, val); | |
1452 | POSTING_READ(reg); | |
1453 | udelay(150); /* wait for warmup */ | |
1454 | I915_WRITE(reg, val); | |
1455 | POSTING_READ(reg); | |
1456 | udelay(150); /* wait for warmup */ | |
1457 | I915_WRITE(reg, val); | |
1458 | POSTING_READ(reg); | |
1459 | udelay(150); /* wait for warmup */ | |
1460 | } | |
1461 | ||
1462 | /** | |
1463 | * intel_disable_pll - disable a PLL | |
1464 | * @dev_priv: i915 private structure | |
1465 | * @pipe: pipe PLL to disable | |
1466 | * | |
1467 | * Disable the PLL for @pipe, making sure the pipe is off first. | |
1468 | * | |
1469 | * Note! This is for pre-ILK only. | |
1470 | */ | |
1471 | static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) | |
1472 | { | |
1473 | int reg; | |
1474 | u32 val; | |
1475 | ||
1476 | /* Don't disable pipe A or pipe A PLLs if needed */ | |
1477 | if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE)) | |
1478 | return; | |
1479 | ||
1480 | /* Make sure the pipe isn't still relying on us */ | |
1481 | assert_pipe_disabled(dev_priv, pipe); | |
1482 | ||
1483 | reg = DPLL(pipe); | |
1484 | val = I915_READ(reg); | |
1485 | val &= ~DPLL_VCO_ENABLE; | |
1486 | I915_WRITE(reg, val); | |
1487 | POSTING_READ(reg); | |
1488 | } | |
1489 | ||
a416edef ED |
1490 | /* SBI access */ |
1491 | static void | |
988d6ee8 PZ |
1492 | intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value, |
1493 | enum intel_sbi_destination destination) | |
a416edef | 1494 | { |
988d6ee8 | 1495 | u32 tmp; |
a416edef | 1496 | |
09153000 | 1497 | WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock)); |
a416edef | 1498 | |
39fb50f6 | 1499 | if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0, |
a416edef ED |
1500 | 100)) { |
1501 | DRM_ERROR("timeout waiting for SBI to become ready\n"); | |
09153000 | 1502 | return; |
a416edef ED |
1503 | } |
1504 | ||
988d6ee8 PZ |
1505 | I915_WRITE(SBI_ADDR, (reg << 16)); |
1506 | I915_WRITE(SBI_DATA, value); | |
1507 | ||
1508 | if (destination == SBI_ICLK) | |
1509 | tmp = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRWR; | |
1510 | else | |
1511 | tmp = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IOWR; | |
1512 | I915_WRITE(SBI_CTL_STAT, SBI_BUSY | tmp); | |
a416edef | 1513 | |
39fb50f6 | 1514 | if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0, |
a416edef ED |
1515 | 100)) { |
1516 | DRM_ERROR("timeout waiting for SBI to complete write transaction\n"); | |
09153000 | 1517 | return; |
a416edef | 1518 | } |
a416edef ED |
1519 | } |
1520 | ||
1521 | static u32 | |
988d6ee8 PZ |
1522 | intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg, |
1523 | enum intel_sbi_destination destination) | |
a416edef | 1524 | { |
39fb50f6 | 1525 | u32 value = 0; |
09153000 | 1526 | WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock)); |
a416edef | 1527 | |
39fb50f6 | 1528 | if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0, |
a416edef ED |
1529 | 100)) { |
1530 | DRM_ERROR("timeout waiting for SBI to become ready\n"); | |
09153000 | 1531 | return 0; |
a416edef ED |
1532 | } |
1533 | ||
988d6ee8 PZ |
1534 | I915_WRITE(SBI_ADDR, (reg << 16)); |
1535 | ||
1536 | if (destination == SBI_ICLK) | |
1537 | value = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRRD; | |
1538 | else | |
1539 | value = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IORD; | |
1540 | I915_WRITE(SBI_CTL_STAT, value | SBI_BUSY); | |
a416edef | 1541 | |
39fb50f6 | 1542 | if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0, |
a416edef ED |
1543 | 100)) { |
1544 | DRM_ERROR("timeout waiting for SBI to complete read transaction\n"); | |
09153000 | 1545 | return 0; |
a416edef ED |
1546 | } |
1547 | ||
09153000 | 1548 | return I915_READ(SBI_DATA); |
a416edef ED |
1549 | } |
1550 | ||
92f2584a | 1551 | /** |
b6b4e185 | 1552 | * ironlake_enable_pch_pll - enable PCH PLL |
92f2584a JB |
1553 | * @dev_priv: i915 private structure |
1554 | * @pipe: pipe PLL to enable | |
1555 | * | |
1556 | * The PCH PLL needs to be enabled before the PCH transcoder, since it | |
1557 | * drives the transcoder clock. | |
1558 | */ | |
b6b4e185 | 1559 | static void ironlake_enable_pch_pll(struct intel_crtc *intel_crtc) |
92f2584a | 1560 | { |
ee7b9f93 | 1561 | struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private; |
48da64a8 | 1562 | struct intel_pch_pll *pll; |
92f2584a JB |
1563 | int reg; |
1564 | u32 val; | |
1565 | ||
48da64a8 | 1566 | /* PCH PLLs only available on ILK, SNB and IVB */ |
92f2584a | 1567 | BUG_ON(dev_priv->info->gen < 5); |
48da64a8 CW |
1568 | pll = intel_crtc->pch_pll; |
1569 | if (pll == NULL) | |
1570 | return; | |
1571 | ||
1572 | if (WARN_ON(pll->refcount == 0)) | |
1573 | return; | |
ee7b9f93 JB |
1574 | |
1575 | DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n", | |
1576 | pll->pll_reg, pll->active, pll->on, | |
1577 | intel_crtc->base.base.id); | |
92f2584a JB |
1578 | |
1579 | /* PCH refclock must be enabled first */ | |
1580 | assert_pch_refclk_enabled(dev_priv); | |
1581 | ||
ee7b9f93 | 1582 | if (pll->active++ && pll->on) { |
92b27b08 | 1583 | assert_pch_pll_enabled(dev_priv, pll, NULL); |
ee7b9f93 JB |
1584 | return; |
1585 | } | |
1586 | ||
1587 | DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg); | |
1588 | ||
1589 | reg = pll->pll_reg; | |
92f2584a JB |
1590 | val = I915_READ(reg); |
1591 | val |= DPLL_VCO_ENABLE; | |
1592 | I915_WRITE(reg, val); | |
1593 | POSTING_READ(reg); | |
1594 | udelay(200); | |
ee7b9f93 JB |
1595 | |
1596 | pll->on = true; | |
92f2584a JB |
1597 | } |
1598 | ||
ee7b9f93 | 1599 | static void intel_disable_pch_pll(struct intel_crtc *intel_crtc) |
92f2584a | 1600 | { |
ee7b9f93 JB |
1601 | struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private; |
1602 | struct intel_pch_pll *pll = intel_crtc->pch_pll; | |
92f2584a | 1603 | int reg; |
ee7b9f93 | 1604 | u32 val; |
4c609cb8 | 1605 | |
92f2584a JB |
1606 | /* PCH only available on ILK+ */ |
1607 | BUG_ON(dev_priv->info->gen < 5); | |
ee7b9f93 JB |
1608 | if (pll == NULL) |
1609 | return; | |
92f2584a | 1610 | |
48da64a8 CW |
1611 | if (WARN_ON(pll->refcount == 0)) |
1612 | return; | |
7a419866 | 1613 | |
ee7b9f93 JB |
1614 | DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n", |
1615 | pll->pll_reg, pll->active, pll->on, | |
1616 | intel_crtc->base.base.id); | |
7a419866 | 1617 | |
48da64a8 | 1618 | if (WARN_ON(pll->active == 0)) { |
92b27b08 | 1619 | assert_pch_pll_disabled(dev_priv, pll, NULL); |
48da64a8 CW |
1620 | return; |
1621 | } | |
1622 | ||
ee7b9f93 | 1623 | if (--pll->active) { |
92b27b08 | 1624 | assert_pch_pll_enabled(dev_priv, pll, NULL); |
7a419866 | 1625 | return; |
ee7b9f93 JB |
1626 | } |
1627 | ||
1628 | DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg); | |
1629 | ||
1630 | /* Make sure transcoder isn't still depending on us */ | |
1631 | assert_transcoder_disabled(dev_priv, intel_crtc->pipe); | |
7a419866 | 1632 | |
ee7b9f93 | 1633 | reg = pll->pll_reg; |
92f2584a JB |
1634 | val = I915_READ(reg); |
1635 | val &= ~DPLL_VCO_ENABLE; | |
1636 | I915_WRITE(reg, val); | |
1637 | POSTING_READ(reg); | |
1638 | udelay(200); | |
ee7b9f93 JB |
1639 | |
1640 | pll->on = false; | |
92f2584a JB |
1641 | } |
1642 | ||
b8a4f404 PZ |
1643 | static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
1644 | enum pipe pipe) | |
040484af | 1645 | { |
23670b32 | 1646 | struct drm_device *dev = dev_priv->dev; |
7c26e5c6 | 1647 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
23670b32 | 1648 | uint32_t reg, val, pipeconf_val; |
040484af JB |
1649 | |
1650 | /* PCH only available on ILK+ */ | |
1651 | BUG_ON(dev_priv->info->gen < 5); | |
1652 | ||
1653 | /* Make sure PCH DPLL is enabled */ | |
92b27b08 CW |
1654 | assert_pch_pll_enabled(dev_priv, |
1655 | to_intel_crtc(crtc)->pch_pll, | |
1656 | to_intel_crtc(crtc)); | |
040484af JB |
1657 | |
1658 | /* FDI must be feeding us bits for PCH ports */ | |
1659 | assert_fdi_tx_enabled(dev_priv, pipe); | |
1660 | assert_fdi_rx_enabled(dev_priv, pipe); | |
1661 | ||
23670b32 DV |
1662 | if (HAS_PCH_CPT(dev)) { |
1663 | /* Workaround: Set the timing override bit before enabling the | |
1664 | * pch transcoder. */ | |
1665 | reg = TRANS_CHICKEN2(pipe); | |
1666 | val = I915_READ(reg); | |
1667 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; | |
1668 | I915_WRITE(reg, val); | |
59c859d6 | 1669 | } |
23670b32 | 1670 | |
040484af JB |
1671 | reg = TRANSCONF(pipe); |
1672 | val = I915_READ(reg); | |
5f7f726d | 1673 | pipeconf_val = I915_READ(PIPECONF(pipe)); |
e9bcff5c JB |
1674 | |
1675 | if (HAS_PCH_IBX(dev_priv->dev)) { | |
1676 | /* | |
1677 | * make the BPC in transcoder be consistent with | |
1678 | * that in pipeconf reg. | |
1679 | */ | |
dfd07d72 DV |
1680 | val &= ~PIPECONF_BPC_MASK; |
1681 | val |= pipeconf_val & PIPECONF_BPC_MASK; | |
e9bcff5c | 1682 | } |
5f7f726d PZ |
1683 | |
1684 | val &= ~TRANS_INTERLACE_MASK; | |
1685 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) | |
7c26e5c6 PZ |
1686 | if (HAS_PCH_IBX(dev_priv->dev) && |
1687 | intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) | |
1688 | val |= TRANS_LEGACY_INTERLACED_ILK; | |
1689 | else | |
1690 | val |= TRANS_INTERLACED; | |
5f7f726d PZ |
1691 | else |
1692 | val |= TRANS_PROGRESSIVE; | |
1693 | ||
040484af JB |
1694 | I915_WRITE(reg, val | TRANS_ENABLE); |
1695 | if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100)) | |
1696 | DRM_ERROR("failed to enable transcoder %d\n", pipe); | |
1697 | } | |
1698 | ||
8fb033d7 | 1699 | static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
937bb610 | 1700 | enum transcoder cpu_transcoder) |
040484af | 1701 | { |
8fb033d7 | 1702 | u32 val, pipeconf_val; |
8fb033d7 PZ |
1703 | |
1704 | /* PCH only available on ILK+ */ | |
1705 | BUG_ON(dev_priv->info->gen < 5); | |
1706 | ||
8fb033d7 | 1707 | /* FDI must be feeding us bits for PCH ports */ |
1a240d4d | 1708 | assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder); |
937bb610 | 1709 | assert_fdi_rx_enabled(dev_priv, TRANSCODER_A); |
8fb033d7 | 1710 | |
223a6fdf PZ |
1711 | /* Workaround: set timing override bit. */ |
1712 | val = I915_READ(_TRANSA_CHICKEN2); | |
23670b32 | 1713 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; |
223a6fdf PZ |
1714 | I915_WRITE(_TRANSA_CHICKEN2, val); |
1715 | ||
25f3ef11 | 1716 | val = TRANS_ENABLE; |
937bb610 | 1717 | pipeconf_val = I915_READ(PIPECONF(cpu_transcoder)); |
8fb033d7 | 1718 | |
9a76b1c6 PZ |
1719 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) == |
1720 | PIPECONF_INTERLACED_ILK) | |
a35f2679 | 1721 | val |= TRANS_INTERLACED; |
8fb033d7 PZ |
1722 | else |
1723 | val |= TRANS_PROGRESSIVE; | |
1724 | ||
25f3ef11 | 1725 | I915_WRITE(TRANSCONF(TRANSCODER_A), val); |
937bb610 PZ |
1726 | if (wait_for(I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE, 100)) |
1727 | DRM_ERROR("Failed to enable PCH transcoder\n"); | |
8fb033d7 PZ |
1728 | } |
1729 | ||
b8a4f404 PZ |
1730 | static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv, |
1731 | enum pipe pipe) | |
040484af | 1732 | { |
23670b32 DV |
1733 | struct drm_device *dev = dev_priv->dev; |
1734 | uint32_t reg, val; | |
040484af JB |
1735 | |
1736 | /* FDI relies on the transcoder */ | |
1737 | assert_fdi_tx_disabled(dev_priv, pipe); | |
1738 | assert_fdi_rx_disabled(dev_priv, pipe); | |
1739 | ||
291906f1 JB |
1740 | /* Ports must be off as well */ |
1741 | assert_pch_ports_disabled(dev_priv, pipe); | |
1742 | ||
040484af JB |
1743 | reg = TRANSCONF(pipe); |
1744 | val = I915_READ(reg); | |
1745 | val &= ~TRANS_ENABLE; | |
1746 | I915_WRITE(reg, val); | |
1747 | /* wait for PCH transcoder off, transcoder state */ | |
1748 | if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50)) | |
4c9c18c2 | 1749 | DRM_ERROR("failed to disable transcoder %d\n", pipe); |
23670b32 DV |
1750 | |
1751 | if (!HAS_PCH_IBX(dev)) { | |
1752 | /* Workaround: Clear the timing override chicken bit again. */ | |
1753 | reg = TRANS_CHICKEN2(pipe); | |
1754 | val = I915_READ(reg); | |
1755 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; | |
1756 | I915_WRITE(reg, val); | |
1757 | } | |
040484af JB |
1758 | } |
1759 | ||
ab4d966c | 1760 | static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv) |
8fb033d7 | 1761 | { |
8fb033d7 PZ |
1762 | u32 val; |
1763 | ||
8a52fd9f | 1764 | val = I915_READ(_TRANSACONF); |
8fb033d7 | 1765 | val &= ~TRANS_ENABLE; |
8a52fd9f | 1766 | I915_WRITE(_TRANSACONF, val); |
8fb033d7 | 1767 | /* wait for PCH transcoder off, transcoder state */ |
8a52fd9f PZ |
1768 | if (wait_for((I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE) == 0, 50)) |
1769 | DRM_ERROR("Failed to disable PCH transcoder\n"); | |
223a6fdf PZ |
1770 | |
1771 | /* Workaround: clear timing override bit. */ | |
1772 | val = I915_READ(_TRANSA_CHICKEN2); | |
23670b32 | 1773 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; |
223a6fdf | 1774 | I915_WRITE(_TRANSA_CHICKEN2, val); |
040484af JB |
1775 | } |
1776 | ||
b24e7179 | 1777 | /** |
309cfea8 | 1778 | * intel_enable_pipe - enable a pipe, asserting requirements |
b24e7179 JB |
1779 | * @dev_priv: i915 private structure |
1780 | * @pipe: pipe to enable | |
040484af | 1781 | * @pch_port: on ILK+, is this pipe driving a PCH port or not |
b24e7179 JB |
1782 | * |
1783 | * Enable @pipe, making sure that various hardware specific requirements | |
1784 | * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc. | |
1785 | * | |
1786 | * @pipe should be %PIPE_A or %PIPE_B. | |
1787 | * | |
1788 | * Will wait until the pipe is actually running (i.e. first vblank) before | |
1789 | * returning. | |
1790 | */ | |
040484af JB |
1791 | static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, |
1792 | bool pch_port) | |
b24e7179 | 1793 | { |
702e7a56 PZ |
1794 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1795 | pipe); | |
1a240d4d | 1796 | enum pipe pch_transcoder; |
b24e7179 JB |
1797 | int reg; |
1798 | u32 val; | |
1799 | ||
681e5811 | 1800 | if (HAS_PCH_LPT(dev_priv->dev)) |
cc391bbb PZ |
1801 | pch_transcoder = TRANSCODER_A; |
1802 | else | |
1803 | pch_transcoder = pipe; | |
1804 | ||
b24e7179 JB |
1805 | /* |
1806 | * A pipe without a PLL won't actually be able to drive bits from | |
1807 | * a plane. On ILK+ the pipe PLLs are integrated, so we don't | |
1808 | * need the check. | |
1809 | */ | |
1810 | if (!HAS_PCH_SPLIT(dev_priv->dev)) | |
1811 | assert_pll_enabled(dev_priv, pipe); | |
040484af JB |
1812 | else { |
1813 | if (pch_port) { | |
1814 | /* if driving the PCH, we need FDI enabled */ | |
cc391bbb | 1815 | assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder); |
1a240d4d DV |
1816 | assert_fdi_tx_pll_enabled(dev_priv, |
1817 | (enum pipe) cpu_transcoder); | |
040484af JB |
1818 | } |
1819 | /* FIXME: assert CPU port conditions for SNB+ */ | |
1820 | } | |
b24e7179 | 1821 | |
702e7a56 | 1822 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 1823 | val = I915_READ(reg); |
00d70b15 CW |
1824 | if (val & PIPECONF_ENABLE) |
1825 | return; | |
1826 | ||
1827 | I915_WRITE(reg, val | PIPECONF_ENABLE); | |
b24e7179 JB |
1828 | intel_wait_for_vblank(dev_priv->dev, pipe); |
1829 | } | |
1830 | ||
1831 | /** | |
309cfea8 | 1832 | * intel_disable_pipe - disable a pipe, asserting requirements |
b24e7179 JB |
1833 | * @dev_priv: i915 private structure |
1834 | * @pipe: pipe to disable | |
1835 | * | |
1836 | * Disable @pipe, making sure that various hardware specific requirements | |
1837 | * are met, if applicable, e.g. plane disabled, panel fitter off, etc. | |
1838 | * | |
1839 | * @pipe should be %PIPE_A or %PIPE_B. | |
1840 | * | |
1841 | * Will wait until the pipe has shut down before returning. | |
1842 | */ | |
1843 | static void intel_disable_pipe(struct drm_i915_private *dev_priv, | |
1844 | enum pipe pipe) | |
1845 | { | |
702e7a56 PZ |
1846 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1847 | pipe); | |
b24e7179 JB |
1848 | int reg; |
1849 | u32 val; | |
1850 | ||
1851 | /* | |
1852 | * Make sure planes won't keep trying to pump pixels to us, | |
1853 | * or we might hang the display. | |
1854 | */ | |
1855 | assert_planes_disabled(dev_priv, pipe); | |
1856 | ||
1857 | /* Don't disable pipe A or pipe A PLLs if needed */ | |
1858 | if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE)) | |
1859 | return; | |
1860 | ||
702e7a56 | 1861 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 1862 | val = I915_READ(reg); |
00d70b15 CW |
1863 | if ((val & PIPECONF_ENABLE) == 0) |
1864 | return; | |
1865 | ||
1866 | I915_WRITE(reg, val & ~PIPECONF_ENABLE); | |
b24e7179 JB |
1867 | intel_wait_for_pipe_off(dev_priv->dev, pipe); |
1868 | } | |
1869 | ||
d74362c9 KP |
1870 | /* |
1871 | * Plane regs are double buffered, going from enabled->disabled needs a | |
1872 | * trigger in order to latch. The display address reg provides this. | |
1873 | */ | |
6f1d69b0 | 1874 | void intel_flush_display_plane(struct drm_i915_private *dev_priv, |
d74362c9 KP |
1875 | enum plane plane) |
1876 | { | |
14f86147 DL |
1877 | if (dev_priv->info->gen >= 4) |
1878 | I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane))); | |
1879 | else | |
1880 | I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane))); | |
d74362c9 KP |
1881 | } |
1882 | ||
b24e7179 JB |
1883 | /** |
1884 | * intel_enable_plane - enable a display plane on a given pipe | |
1885 | * @dev_priv: i915 private structure | |
1886 | * @plane: plane to enable | |
1887 | * @pipe: pipe being fed | |
1888 | * | |
1889 | * Enable @plane on @pipe, making sure that @pipe is running first. | |
1890 | */ | |
1891 | static void intel_enable_plane(struct drm_i915_private *dev_priv, | |
1892 | enum plane plane, enum pipe pipe) | |
1893 | { | |
1894 | int reg; | |
1895 | u32 val; | |
1896 | ||
1897 | /* If the pipe isn't enabled, we can't pump pixels and may hang */ | |
1898 | assert_pipe_enabled(dev_priv, pipe); | |
1899 | ||
1900 | reg = DSPCNTR(plane); | |
1901 | val = I915_READ(reg); | |
00d70b15 CW |
1902 | if (val & DISPLAY_PLANE_ENABLE) |
1903 | return; | |
1904 | ||
1905 | I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE); | |
d74362c9 | 1906 | intel_flush_display_plane(dev_priv, plane); |
b24e7179 JB |
1907 | intel_wait_for_vblank(dev_priv->dev, pipe); |
1908 | } | |
1909 | ||
b24e7179 JB |
1910 | /** |
1911 | * intel_disable_plane - disable a display plane | |
1912 | * @dev_priv: i915 private structure | |
1913 | * @plane: plane to disable | |
1914 | * @pipe: pipe consuming the data | |
1915 | * | |
1916 | * Disable @plane; should be an independent operation. | |
1917 | */ | |
1918 | static void intel_disable_plane(struct drm_i915_private *dev_priv, | |
1919 | enum plane plane, enum pipe pipe) | |
1920 | { | |
1921 | int reg; | |
1922 | u32 val; | |
1923 | ||
1924 | reg = DSPCNTR(plane); | |
1925 | val = I915_READ(reg); | |
00d70b15 CW |
1926 | if ((val & DISPLAY_PLANE_ENABLE) == 0) |
1927 | return; | |
1928 | ||
1929 | I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE); | |
b24e7179 JB |
1930 | intel_flush_display_plane(dev_priv, plane); |
1931 | intel_wait_for_vblank(dev_priv->dev, pipe); | |
1932 | } | |
1933 | ||
127bd2ac | 1934 | int |
48b956c5 | 1935 | intel_pin_and_fence_fb_obj(struct drm_device *dev, |
05394f39 | 1936 | struct drm_i915_gem_object *obj, |
919926ae | 1937 | struct intel_ring_buffer *pipelined) |
6b95a207 | 1938 | { |
ce453d81 | 1939 | struct drm_i915_private *dev_priv = dev->dev_private; |
6b95a207 KH |
1940 | u32 alignment; |
1941 | int ret; | |
1942 | ||
05394f39 | 1943 | switch (obj->tiling_mode) { |
6b95a207 | 1944 | case I915_TILING_NONE: |
534843da CW |
1945 | if (IS_BROADWATER(dev) || IS_CRESTLINE(dev)) |
1946 | alignment = 128 * 1024; | |
a6c45cf0 | 1947 | else if (INTEL_INFO(dev)->gen >= 4) |
534843da CW |
1948 | alignment = 4 * 1024; |
1949 | else | |
1950 | alignment = 64 * 1024; | |
6b95a207 KH |
1951 | break; |
1952 | case I915_TILING_X: | |
1953 | /* pin() will align the object as required by fence */ | |
1954 | alignment = 0; | |
1955 | break; | |
1956 | case I915_TILING_Y: | |
1957 | /* FIXME: Is this true? */ | |
1958 | DRM_ERROR("Y tiled not allowed for scan out buffers\n"); | |
1959 | return -EINVAL; | |
1960 | default: | |
1961 | BUG(); | |
1962 | } | |
1963 | ||
ce453d81 | 1964 | dev_priv->mm.interruptible = false; |
2da3b9b9 | 1965 | ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined); |
48b956c5 | 1966 | if (ret) |
ce453d81 | 1967 | goto err_interruptible; |
6b95a207 KH |
1968 | |
1969 | /* Install a fence for tiled scan-out. Pre-i965 always needs a | |
1970 | * fence, whereas 965+ only requires a fence if using | |
1971 | * framebuffer compression. For simplicity, we always install | |
1972 | * a fence as the cost is not that onerous. | |
1973 | */ | |
06d98131 | 1974 | ret = i915_gem_object_get_fence(obj); |
9a5a53b3 CW |
1975 | if (ret) |
1976 | goto err_unpin; | |
1690e1eb | 1977 | |
9a5a53b3 | 1978 | i915_gem_object_pin_fence(obj); |
6b95a207 | 1979 | |
ce453d81 | 1980 | dev_priv->mm.interruptible = true; |
6b95a207 | 1981 | return 0; |
48b956c5 CW |
1982 | |
1983 | err_unpin: | |
1984 | i915_gem_object_unpin(obj); | |
ce453d81 CW |
1985 | err_interruptible: |
1986 | dev_priv->mm.interruptible = true; | |
48b956c5 | 1987 | return ret; |
6b95a207 KH |
1988 | } |
1989 | ||
1690e1eb CW |
1990 | void intel_unpin_fb_obj(struct drm_i915_gem_object *obj) |
1991 | { | |
1992 | i915_gem_object_unpin_fence(obj); | |
1993 | i915_gem_object_unpin(obj); | |
1994 | } | |
1995 | ||
c2c75131 DV |
1996 | /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel |
1997 | * is assumed to be a power-of-two. */ | |
5a35e99e DL |
1998 | unsigned long intel_gen4_compute_offset_xtiled(int *x, int *y, |
1999 | unsigned int bpp, | |
2000 | unsigned int pitch) | |
c2c75131 DV |
2001 | { |
2002 | int tile_rows, tiles; | |
2003 | ||
2004 | tile_rows = *y / 8; | |
2005 | *y %= 8; | |
2006 | tiles = *x / (512/bpp); | |
2007 | *x %= 512/bpp; | |
2008 | ||
2009 | return tile_rows * pitch * 8 + tiles * 4096; | |
2010 | } | |
2011 | ||
17638cd6 JB |
2012 | static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb, |
2013 | int x, int y) | |
81255565 JB |
2014 | { |
2015 | struct drm_device *dev = crtc->dev; | |
2016 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2017 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2018 | struct intel_framebuffer *intel_fb; | |
05394f39 | 2019 | struct drm_i915_gem_object *obj; |
81255565 | 2020 | int plane = intel_crtc->plane; |
e506a0c6 | 2021 | unsigned long linear_offset; |
81255565 | 2022 | u32 dspcntr; |
5eddb70b | 2023 | u32 reg; |
81255565 JB |
2024 | |
2025 | switch (plane) { | |
2026 | case 0: | |
2027 | case 1: | |
2028 | break; | |
2029 | default: | |
2030 | DRM_ERROR("Can't update plane %d in SAREA\n", plane); | |
2031 | return -EINVAL; | |
2032 | } | |
2033 | ||
2034 | intel_fb = to_intel_framebuffer(fb); | |
2035 | obj = intel_fb->obj; | |
81255565 | 2036 | |
5eddb70b CW |
2037 | reg = DSPCNTR(plane); |
2038 | dspcntr = I915_READ(reg); | |
81255565 JB |
2039 | /* Mask out pixel format bits in case we change it */ |
2040 | dspcntr &= ~DISPPLANE_PIXFORMAT_MASK; | |
57779d06 VS |
2041 | switch (fb->pixel_format) { |
2042 | case DRM_FORMAT_C8: | |
81255565 JB |
2043 | dspcntr |= DISPPLANE_8BPP; |
2044 | break; | |
57779d06 VS |
2045 | case DRM_FORMAT_XRGB1555: |
2046 | case DRM_FORMAT_ARGB1555: | |
2047 | dspcntr |= DISPPLANE_BGRX555; | |
81255565 | 2048 | break; |
57779d06 VS |
2049 | case DRM_FORMAT_RGB565: |
2050 | dspcntr |= DISPPLANE_BGRX565; | |
2051 | break; | |
2052 | case DRM_FORMAT_XRGB8888: | |
2053 | case DRM_FORMAT_ARGB8888: | |
2054 | dspcntr |= DISPPLANE_BGRX888; | |
2055 | break; | |
2056 | case DRM_FORMAT_XBGR8888: | |
2057 | case DRM_FORMAT_ABGR8888: | |
2058 | dspcntr |= DISPPLANE_RGBX888; | |
2059 | break; | |
2060 | case DRM_FORMAT_XRGB2101010: | |
2061 | case DRM_FORMAT_ARGB2101010: | |
2062 | dspcntr |= DISPPLANE_BGRX101010; | |
2063 | break; | |
2064 | case DRM_FORMAT_XBGR2101010: | |
2065 | case DRM_FORMAT_ABGR2101010: | |
2066 | dspcntr |= DISPPLANE_RGBX101010; | |
81255565 JB |
2067 | break; |
2068 | default: | |
57779d06 | 2069 | DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format); |
81255565 JB |
2070 | return -EINVAL; |
2071 | } | |
57779d06 | 2072 | |
a6c45cf0 | 2073 | if (INTEL_INFO(dev)->gen >= 4) { |
05394f39 | 2074 | if (obj->tiling_mode != I915_TILING_NONE) |
81255565 JB |
2075 | dspcntr |= DISPPLANE_TILED; |
2076 | else | |
2077 | dspcntr &= ~DISPPLANE_TILED; | |
2078 | } | |
2079 | ||
5eddb70b | 2080 | I915_WRITE(reg, dspcntr); |
81255565 | 2081 | |
e506a0c6 | 2082 | linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8); |
81255565 | 2083 | |
c2c75131 DV |
2084 | if (INTEL_INFO(dev)->gen >= 4) { |
2085 | intel_crtc->dspaddr_offset = | |
5a35e99e DL |
2086 | intel_gen4_compute_offset_xtiled(&x, &y, |
2087 | fb->bits_per_pixel / 8, | |
2088 | fb->pitches[0]); | |
c2c75131 DV |
2089 | linear_offset -= intel_crtc->dspaddr_offset; |
2090 | } else { | |
e506a0c6 | 2091 | intel_crtc->dspaddr_offset = linear_offset; |
c2c75131 | 2092 | } |
e506a0c6 DV |
2093 | |
2094 | DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n", | |
2095 | obj->gtt_offset, linear_offset, x, y, fb->pitches[0]); | |
01f2c773 | 2096 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
a6c45cf0 | 2097 | if (INTEL_INFO(dev)->gen >= 4) { |
c2c75131 DV |
2098 | I915_MODIFY_DISPBASE(DSPSURF(plane), |
2099 | obj->gtt_offset + intel_crtc->dspaddr_offset); | |
5eddb70b | 2100 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); |
e506a0c6 | 2101 | I915_WRITE(DSPLINOFF(plane), linear_offset); |
5eddb70b | 2102 | } else |
e506a0c6 | 2103 | I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset); |
5eddb70b | 2104 | POSTING_READ(reg); |
81255565 | 2105 | |
17638cd6 JB |
2106 | return 0; |
2107 | } | |
2108 | ||
2109 | static int ironlake_update_plane(struct drm_crtc *crtc, | |
2110 | struct drm_framebuffer *fb, int x, int y) | |
2111 | { | |
2112 | struct drm_device *dev = crtc->dev; | |
2113 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2114 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2115 | struct intel_framebuffer *intel_fb; | |
2116 | struct drm_i915_gem_object *obj; | |
2117 | int plane = intel_crtc->plane; | |
e506a0c6 | 2118 | unsigned long linear_offset; |
17638cd6 JB |
2119 | u32 dspcntr; |
2120 | u32 reg; | |
2121 | ||
2122 | switch (plane) { | |
2123 | case 0: | |
2124 | case 1: | |
27f8227b | 2125 | case 2: |
17638cd6 JB |
2126 | break; |
2127 | default: | |
2128 | DRM_ERROR("Can't update plane %d in SAREA\n", plane); | |
2129 | return -EINVAL; | |
2130 | } | |
2131 | ||
2132 | intel_fb = to_intel_framebuffer(fb); | |
2133 | obj = intel_fb->obj; | |
2134 | ||
2135 | reg = DSPCNTR(plane); | |
2136 | dspcntr = I915_READ(reg); | |
2137 | /* Mask out pixel format bits in case we change it */ | |
2138 | dspcntr &= ~DISPPLANE_PIXFORMAT_MASK; | |
57779d06 VS |
2139 | switch (fb->pixel_format) { |
2140 | case DRM_FORMAT_C8: | |
17638cd6 JB |
2141 | dspcntr |= DISPPLANE_8BPP; |
2142 | break; | |
57779d06 VS |
2143 | case DRM_FORMAT_RGB565: |
2144 | dspcntr |= DISPPLANE_BGRX565; | |
17638cd6 | 2145 | break; |
57779d06 VS |
2146 | case DRM_FORMAT_XRGB8888: |
2147 | case DRM_FORMAT_ARGB8888: | |
2148 | dspcntr |= DISPPLANE_BGRX888; | |
2149 | break; | |
2150 | case DRM_FORMAT_XBGR8888: | |
2151 | case DRM_FORMAT_ABGR8888: | |
2152 | dspcntr |= DISPPLANE_RGBX888; | |
2153 | break; | |
2154 | case DRM_FORMAT_XRGB2101010: | |
2155 | case DRM_FORMAT_ARGB2101010: | |
2156 | dspcntr |= DISPPLANE_BGRX101010; | |
2157 | break; | |
2158 | case DRM_FORMAT_XBGR2101010: | |
2159 | case DRM_FORMAT_ABGR2101010: | |
2160 | dspcntr |= DISPPLANE_RGBX101010; | |
17638cd6 JB |
2161 | break; |
2162 | default: | |
57779d06 | 2163 | DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format); |
17638cd6 JB |
2164 | return -EINVAL; |
2165 | } | |
2166 | ||
2167 | if (obj->tiling_mode != I915_TILING_NONE) | |
2168 | dspcntr |= DISPPLANE_TILED; | |
2169 | else | |
2170 | dspcntr &= ~DISPPLANE_TILED; | |
2171 | ||
2172 | /* must disable */ | |
2173 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; | |
2174 | ||
2175 | I915_WRITE(reg, dspcntr); | |
2176 | ||
e506a0c6 | 2177 | linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8); |
c2c75131 | 2178 | intel_crtc->dspaddr_offset = |
5a35e99e DL |
2179 | intel_gen4_compute_offset_xtiled(&x, &y, |
2180 | fb->bits_per_pixel / 8, | |
2181 | fb->pitches[0]); | |
c2c75131 | 2182 | linear_offset -= intel_crtc->dspaddr_offset; |
17638cd6 | 2183 | |
e506a0c6 DV |
2184 | DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n", |
2185 | obj->gtt_offset, linear_offset, x, y, fb->pitches[0]); | |
01f2c773 | 2186 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
c2c75131 DV |
2187 | I915_MODIFY_DISPBASE(DSPSURF(plane), |
2188 | obj->gtt_offset + intel_crtc->dspaddr_offset); | |
bc1c91eb DL |
2189 | if (IS_HASWELL(dev)) { |
2190 | I915_WRITE(DSPOFFSET(plane), (y << 16) | x); | |
2191 | } else { | |
2192 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); | |
2193 | I915_WRITE(DSPLINOFF(plane), linear_offset); | |
2194 | } | |
17638cd6 JB |
2195 | POSTING_READ(reg); |
2196 | ||
2197 | return 0; | |
2198 | } | |
2199 | ||
2200 | /* Assume fb object is pinned & idle & fenced and just update base pointers */ | |
2201 | static int | |
2202 | intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb, | |
2203 | int x, int y, enum mode_set_atomic state) | |
2204 | { | |
2205 | struct drm_device *dev = crtc->dev; | |
2206 | struct drm_i915_private *dev_priv = dev->dev_private; | |
17638cd6 | 2207 | |
6b8e6ed0 CW |
2208 | if (dev_priv->display.disable_fbc) |
2209 | dev_priv->display.disable_fbc(dev); | |
3dec0095 | 2210 | intel_increase_pllclock(crtc); |
81255565 | 2211 | |
6b8e6ed0 | 2212 | return dev_priv->display.update_plane(crtc, fb, x, y); |
81255565 JB |
2213 | } |
2214 | ||
14667a4b CW |
2215 | static int |
2216 | intel_finish_fb(struct drm_framebuffer *old_fb) | |
2217 | { | |
2218 | struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj; | |
2219 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
2220 | bool was_interruptible = dev_priv->mm.interruptible; | |
2221 | int ret; | |
2222 | ||
2c10d571 DV |
2223 | WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue)); |
2224 | ||
14667a4b CW |
2225 | wait_event(dev_priv->pending_flip_queue, |
2226 | atomic_read(&dev_priv->mm.wedged) || | |
2227 | atomic_read(&obj->pending_flip) == 0); | |
2228 | ||
2229 | /* Big Hammer, we also need to ensure that any pending | |
2230 | * MI_WAIT_FOR_EVENT inside a user batch buffer on the | |
2231 | * current scanout is retired before unpinning the old | |
2232 | * framebuffer. | |
2233 | * | |
2234 | * This should only fail upon a hung GPU, in which case we | |
2235 | * can safely continue. | |
2236 | */ | |
2237 | dev_priv->mm.interruptible = false; | |
2238 | ret = i915_gem_object_finish_gpu(obj); | |
2239 | dev_priv->mm.interruptible = was_interruptible; | |
2240 | ||
2241 | return ret; | |
2242 | } | |
2243 | ||
198598d0 VS |
2244 | static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y) |
2245 | { | |
2246 | struct drm_device *dev = crtc->dev; | |
2247 | struct drm_i915_master_private *master_priv; | |
2248 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2249 | ||
2250 | if (!dev->primary->master) | |
2251 | return; | |
2252 | ||
2253 | master_priv = dev->primary->master->driver_priv; | |
2254 | if (!master_priv->sarea_priv) | |
2255 | return; | |
2256 | ||
2257 | switch (intel_crtc->pipe) { | |
2258 | case 0: | |
2259 | master_priv->sarea_priv->pipeA_x = x; | |
2260 | master_priv->sarea_priv->pipeA_y = y; | |
2261 | break; | |
2262 | case 1: | |
2263 | master_priv->sarea_priv->pipeB_x = x; | |
2264 | master_priv->sarea_priv->pipeB_y = y; | |
2265 | break; | |
2266 | default: | |
2267 | break; | |
2268 | } | |
2269 | } | |
2270 | ||
5c3b82e2 | 2271 | static int |
3c4fdcfb | 2272 | intel_pipe_set_base(struct drm_crtc *crtc, int x, int y, |
94352cf9 | 2273 | struct drm_framebuffer *fb) |
79e53945 JB |
2274 | { |
2275 | struct drm_device *dev = crtc->dev; | |
6b8e6ed0 | 2276 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 2277 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
94352cf9 | 2278 | struct drm_framebuffer *old_fb; |
5c3b82e2 | 2279 | int ret; |
79e53945 JB |
2280 | |
2281 | /* no fb bound */ | |
94352cf9 | 2282 | if (!fb) { |
a5071c2f | 2283 | DRM_ERROR("No FB bound\n"); |
5c3b82e2 CW |
2284 | return 0; |
2285 | } | |
2286 | ||
5826eca5 ED |
2287 | if(intel_crtc->plane > dev_priv->num_pipe) { |
2288 | DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n", | |
2289 | intel_crtc->plane, | |
2290 | dev_priv->num_pipe); | |
5c3b82e2 | 2291 | return -EINVAL; |
79e53945 JB |
2292 | } |
2293 | ||
5c3b82e2 | 2294 | mutex_lock(&dev->struct_mutex); |
265db958 | 2295 | ret = intel_pin_and_fence_fb_obj(dev, |
94352cf9 | 2296 | to_intel_framebuffer(fb)->obj, |
919926ae | 2297 | NULL); |
5c3b82e2 CW |
2298 | if (ret != 0) { |
2299 | mutex_unlock(&dev->struct_mutex); | |
a5071c2f | 2300 | DRM_ERROR("pin & fence failed\n"); |
5c3b82e2 CW |
2301 | return ret; |
2302 | } | |
79e53945 | 2303 | |
94352cf9 DV |
2304 | if (crtc->fb) |
2305 | intel_finish_fb(crtc->fb); | |
265db958 | 2306 | |
94352cf9 | 2307 | ret = dev_priv->display.update_plane(crtc, fb, x, y); |
4e6cfefc | 2308 | if (ret) { |
94352cf9 | 2309 | intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj); |
5c3b82e2 | 2310 | mutex_unlock(&dev->struct_mutex); |
a5071c2f | 2311 | DRM_ERROR("failed to update base address\n"); |
4e6cfefc | 2312 | return ret; |
79e53945 | 2313 | } |
3c4fdcfb | 2314 | |
94352cf9 DV |
2315 | old_fb = crtc->fb; |
2316 | crtc->fb = fb; | |
6c4c86f5 DV |
2317 | crtc->x = x; |
2318 | crtc->y = y; | |
94352cf9 | 2319 | |
b7f1de28 CW |
2320 | if (old_fb) { |
2321 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
1690e1eb | 2322 | intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj); |
b7f1de28 | 2323 | } |
652c393a | 2324 | |
6b8e6ed0 | 2325 | intel_update_fbc(dev); |
5c3b82e2 | 2326 | mutex_unlock(&dev->struct_mutex); |
79e53945 | 2327 | |
198598d0 | 2328 | intel_crtc_update_sarea_pos(crtc, x, y); |
5c3b82e2 CW |
2329 | |
2330 | return 0; | |
79e53945 JB |
2331 | } |
2332 | ||
5e84e1a4 ZW |
2333 | static void intel_fdi_normal_train(struct drm_crtc *crtc) |
2334 | { | |
2335 | struct drm_device *dev = crtc->dev; | |
2336 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2337 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2338 | int pipe = intel_crtc->pipe; | |
2339 | u32 reg, temp; | |
2340 | ||
2341 | /* enable normal train */ | |
2342 | reg = FDI_TX_CTL(pipe); | |
2343 | temp = I915_READ(reg); | |
61e499bf | 2344 | if (IS_IVYBRIDGE(dev)) { |
357555c0 JB |
2345 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
2346 | temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE; | |
61e499bf KP |
2347 | } else { |
2348 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2349 | temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE; | |
357555c0 | 2350 | } |
5e84e1a4 ZW |
2351 | I915_WRITE(reg, temp); |
2352 | ||
2353 | reg = FDI_RX_CTL(pipe); | |
2354 | temp = I915_READ(reg); | |
2355 | if (HAS_PCH_CPT(dev)) { | |
2356 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2357 | temp |= FDI_LINK_TRAIN_NORMAL_CPT; | |
2358 | } else { | |
2359 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2360 | temp |= FDI_LINK_TRAIN_NONE; | |
2361 | } | |
2362 | I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE); | |
2363 | ||
2364 | /* wait one idle pattern time */ | |
2365 | POSTING_READ(reg); | |
2366 | udelay(1000); | |
357555c0 JB |
2367 | |
2368 | /* IVB wants error correction enabled */ | |
2369 | if (IS_IVYBRIDGE(dev)) | |
2370 | I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE | | |
2371 | FDI_FE_ERRC_ENABLE); | |
5e84e1a4 ZW |
2372 | } |
2373 | ||
01a415fd DV |
2374 | static void ivb_modeset_global_resources(struct drm_device *dev) |
2375 | { | |
2376 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2377 | struct intel_crtc *pipe_B_crtc = | |
2378 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]); | |
2379 | struct intel_crtc *pipe_C_crtc = | |
2380 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]); | |
2381 | uint32_t temp; | |
2382 | ||
2383 | /* When everything is off disable fdi C so that we could enable fdi B | |
2384 | * with all lanes. XXX: This misses the case where a pipe is not using | |
2385 | * any pch resources and so doesn't need any fdi lanes. */ | |
2386 | if (!pipe_B_crtc->base.enabled && !pipe_C_crtc->base.enabled) { | |
2387 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); | |
2388 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); | |
2389 | ||
2390 | temp = I915_READ(SOUTH_CHICKEN1); | |
2391 | temp &= ~FDI_BC_BIFURCATION_SELECT; | |
2392 | DRM_DEBUG_KMS("disabling fdi C rx\n"); | |
2393 | I915_WRITE(SOUTH_CHICKEN1, temp); | |
2394 | } | |
2395 | } | |
2396 | ||
8db9d77b ZW |
2397 | /* The FDI link training functions for ILK/Ibexpeak. */ |
2398 | static void ironlake_fdi_link_train(struct drm_crtc *crtc) | |
2399 | { | |
2400 | struct drm_device *dev = crtc->dev; | |
2401 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2402 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2403 | int pipe = intel_crtc->pipe; | |
0fc932b8 | 2404 | int plane = intel_crtc->plane; |
5eddb70b | 2405 | u32 reg, temp, tries; |
8db9d77b | 2406 | |
0fc932b8 JB |
2407 | /* FDI needs bits from pipe & plane first */ |
2408 | assert_pipe_enabled(dev_priv, pipe); | |
2409 | assert_plane_enabled(dev_priv, plane); | |
2410 | ||
e1a44743 AJ |
2411 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
2412 | for train result */ | |
5eddb70b CW |
2413 | reg = FDI_RX_IMR(pipe); |
2414 | temp = I915_READ(reg); | |
e1a44743 AJ |
2415 | temp &= ~FDI_RX_SYMBOL_LOCK; |
2416 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
2417 | I915_WRITE(reg, temp); |
2418 | I915_READ(reg); | |
e1a44743 AJ |
2419 | udelay(150); |
2420 | ||
8db9d77b | 2421 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
2422 | reg = FDI_TX_CTL(pipe); |
2423 | temp = I915_READ(reg); | |
77ffb597 AJ |
2424 | temp &= ~(7 << 19); |
2425 | temp |= (intel_crtc->fdi_lanes - 1) << 19; | |
8db9d77b ZW |
2426 | temp &= ~FDI_LINK_TRAIN_NONE; |
2427 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b | 2428 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 2429 | |
5eddb70b CW |
2430 | reg = FDI_RX_CTL(pipe); |
2431 | temp = I915_READ(reg); | |
8db9d77b ZW |
2432 | temp &= ~FDI_LINK_TRAIN_NONE; |
2433 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b CW |
2434 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
2435 | ||
2436 | POSTING_READ(reg); | |
8db9d77b ZW |
2437 | udelay(150); |
2438 | ||
5b2adf89 | 2439 | /* Ironlake workaround, enable clock pointer after FDI enable*/ |
8f5718a6 DV |
2440 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
2441 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR | | |
2442 | FDI_RX_PHASE_SYNC_POINTER_EN); | |
5b2adf89 | 2443 | |
5eddb70b | 2444 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 2445 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 2446 | temp = I915_READ(reg); |
8db9d77b ZW |
2447 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
2448 | ||
2449 | if ((temp & FDI_RX_BIT_LOCK)) { | |
2450 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
5eddb70b | 2451 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
8db9d77b ZW |
2452 | break; |
2453 | } | |
8db9d77b | 2454 | } |
e1a44743 | 2455 | if (tries == 5) |
5eddb70b | 2456 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
2457 | |
2458 | /* Train 2 */ | |
5eddb70b CW |
2459 | reg = FDI_TX_CTL(pipe); |
2460 | temp = I915_READ(reg); | |
8db9d77b ZW |
2461 | temp &= ~FDI_LINK_TRAIN_NONE; |
2462 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 2463 | I915_WRITE(reg, temp); |
8db9d77b | 2464 | |
5eddb70b CW |
2465 | reg = FDI_RX_CTL(pipe); |
2466 | temp = I915_READ(reg); | |
8db9d77b ZW |
2467 | temp &= ~FDI_LINK_TRAIN_NONE; |
2468 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 2469 | I915_WRITE(reg, temp); |
8db9d77b | 2470 | |
5eddb70b CW |
2471 | POSTING_READ(reg); |
2472 | udelay(150); | |
8db9d77b | 2473 | |
5eddb70b | 2474 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 2475 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 2476 | temp = I915_READ(reg); |
8db9d77b ZW |
2477 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
2478 | ||
2479 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
5eddb70b | 2480 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
8db9d77b ZW |
2481 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
2482 | break; | |
2483 | } | |
8db9d77b | 2484 | } |
e1a44743 | 2485 | if (tries == 5) |
5eddb70b | 2486 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
2487 | |
2488 | DRM_DEBUG_KMS("FDI train done\n"); | |
5c5313c8 | 2489 | |
8db9d77b ZW |
2490 | } |
2491 | ||
0206e353 | 2492 | static const int snb_b_fdi_train_param[] = { |
8db9d77b ZW |
2493 | FDI_LINK_TRAIN_400MV_0DB_SNB_B, |
2494 | FDI_LINK_TRAIN_400MV_6DB_SNB_B, | |
2495 | FDI_LINK_TRAIN_600MV_3_5DB_SNB_B, | |
2496 | FDI_LINK_TRAIN_800MV_0DB_SNB_B, | |
2497 | }; | |
2498 | ||
2499 | /* The FDI link training functions for SNB/Cougarpoint. */ | |
2500 | static void gen6_fdi_link_train(struct drm_crtc *crtc) | |
2501 | { | |
2502 | struct drm_device *dev = crtc->dev; | |
2503 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2504 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2505 | int pipe = intel_crtc->pipe; | |
fa37d39e | 2506 | u32 reg, temp, i, retry; |
8db9d77b | 2507 | |
e1a44743 AJ |
2508 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
2509 | for train result */ | |
5eddb70b CW |
2510 | reg = FDI_RX_IMR(pipe); |
2511 | temp = I915_READ(reg); | |
e1a44743 AJ |
2512 | temp &= ~FDI_RX_SYMBOL_LOCK; |
2513 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
2514 | I915_WRITE(reg, temp); |
2515 | ||
2516 | POSTING_READ(reg); | |
e1a44743 AJ |
2517 | udelay(150); |
2518 | ||
8db9d77b | 2519 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
2520 | reg = FDI_TX_CTL(pipe); |
2521 | temp = I915_READ(reg); | |
77ffb597 AJ |
2522 | temp &= ~(7 << 19); |
2523 | temp |= (intel_crtc->fdi_lanes - 1) << 19; | |
8db9d77b ZW |
2524 | temp &= ~FDI_LINK_TRAIN_NONE; |
2525 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
2526 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
2527 | /* SNB-B */ | |
2528 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
5eddb70b | 2529 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 2530 | |
d74cf324 DV |
2531 | I915_WRITE(FDI_RX_MISC(pipe), |
2532 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
2533 | ||
5eddb70b CW |
2534 | reg = FDI_RX_CTL(pipe); |
2535 | temp = I915_READ(reg); | |
8db9d77b ZW |
2536 | if (HAS_PCH_CPT(dev)) { |
2537 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2538 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
2539 | } else { | |
2540 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2541 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
2542 | } | |
5eddb70b CW |
2543 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
2544 | ||
2545 | POSTING_READ(reg); | |
8db9d77b ZW |
2546 | udelay(150); |
2547 | ||
0206e353 | 2548 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
2549 | reg = FDI_TX_CTL(pipe); |
2550 | temp = I915_READ(reg); | |
8db9d77b ZW |
2551 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
2552 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
2553 | I915_WRITE(reg, temp); |
2554 | ||
2555 | POSTING_READ(reg); | |
8db9d77b ZW |
2556 | udelay(500); |
2557 | ||
fa37d39e SP |
2558 | for (retry = 0; retry < 5; retry++) { |
2559 | reg = FDI_RX_IIR(pipe); | |
2560 | temp = I915_READ(reg); | |
2561 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
2562 | if (temp & FDI_RX_BIT_LOCK) { | |
2563 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
2564 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
2565 | break; | |
2566 | } | |
2567 | udelay(50); | |
8db9d77b | 2568 | } |
fa37d39e SP |
2569 | if (retry < 5) |
2570 | break; | |
8db9d77b ZW |
2571 | } |
2572 | if (i == 4) | |
5eddb70b | 2573 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
2574 | |
2575 | /* Train 2 */ | |
5eddb70b CW |
2576 | reg = FDI_TX_CTL(pipe); |
2577 | temp = I915_READ(reg); | |
8db9d77b ZW |
2578 | temp &= ~FDI_LINK_TRAIN_NONE; |
2579 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
2580 | if (IS_GEN6(dev)) { | |
2581 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
2582 | /* SNB-B */ | |
2583 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
2584 | } | |
5eddb70b | 2585 | I915_WRITE(reg, temp); |
8db9d77b | 2586 | |
5eddb70b CW |
2587 | reg = FDI_RX_CTL(pipe); |
2588 | temp = I915_READ(reg); | |
8db9d77b ZW |
2589 | if (HAS_PCH_CPT(dev)) { |
2590 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2591 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
2592 | } else { | |
2593 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2594 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
2595 | } | |
5eddb70b CW |
2596 | I915_WRITE(reg, temp); |
2597 | ||
2598 | POSTING_READ(reg); | |
8db9d77b ZW |
2599 | udelay(150); |
2600 | ||
0206e353 | 2601 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
2602 | reg = FDI_TX_CTL(pipe); |
2603 | temp = I915_READ(reg); | |
8db9d77b ZW |
2604 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
2605 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
2606 | I915_WRITE(reg, temp); |
2607 | ||
2608 | POSTING_READ(reg); | |
8db9d77b ZW |
2609 | udelay(500); |
2610 | ||
fa37d39e SP |
2611 | for (retry = 0; retry < 5; retry++) { |
2612 | reg = FDI_RX_IIR(pipe); | |
2613 | temp = I915_READ(reg); | |
2614 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
2615 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
2616 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
2617 | DRM_DEBUG_KMS("FDI train 2 done.\n"); | |
2618 | break; | |
2619 | } | |
2620 | udelay(50); | |
8db9d77b | 2621 | } |
fa37d39e SP |
2622 | if (retry < 5) |
2623 | break; | |
8db9d77b ZW |
2624 | } |
2625 | if (i == 4) | |
5eddb70b | 2626 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
2627 | |
2628 | DRM_DEBUG_KMS("FDI train done.\n"); | |
2629 | } | |
2630 | ||
357555c0 JB |
2631 | /* Manual link training for Ivy Bridge A0 parts */ |
2632 | static void ivb_manual_fdi_link_train(struct drm_crtc *crtc) | |
2633 | { | |
2634 | struct drm_device *dev = crtc->dev; | |
2635 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2636 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2637 | int pipe = intel_crtc->pipe; | |
2638 | u32 reg, temp, i; | |
2639 | ||
2640 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit | |
2641 | for train result */ | |
2642 | reg = FDI_RX_IMR(pipe); | |
2643 | temp = I915_READ(reg); | |
2644 | temp &= ~FDI_RX_SYMBOL_LOCK; | |
2645 | temp &= ~FDI_RX_BIT_LOCK; | |
2646 | I915_WRITE(reg, temp); | |
2647 | ||
2648 | POSTING_READ(reg); | |
2649 | udelay(150); | |
2650 | ||
01a415fd DV |
2651 | DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n", |
2652 | I915_READ(FDI_RX_IIR(pipe))); | |
2653 | ||
357555c0 JB |
2654 | /* enable CPU FDI TX and PCH FDI RX */ |
2655 | reg = FDI_TX_CTL(pipe); | |
2656 | temp = I915_READ(reg); | |
2657 | temp &= ~(7 << 19); | |
2658 | temp |= (intel_crtc->fdi_lanes - 1) << 19; | |
2659 | temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB); | |
2660 | temp |= FDI_LINK_TRAIN_PATTERN_1_IVB; | |
2661 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
2662 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
c4f9c4c2 | 2663 | temp |= FDI_COMPOSITE_SYNC; |
357555c0 JB |
2664 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
2665 | ||
d74cf324 DV |
2666 | I915_WRITE(FDI_RX_MISC(pipe), |
2667 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
2668 | ||
357555c0 JB |
2669 | reg = FDI_RX_CTL(pipe); |
2670 | temp = I915_READ(reg); | |
2671 | temp &= ~FDI_LINK_TRAIN_AUTO; | |
2672 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2673 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
c4f9c4c2 | 2674 | temp |= FDI_COMPOSITE_SYNC; |
357555c0 JB |
2675 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
2676 | ||
2677 | POSTING_READ(reg); | |
2678 | udelay(150); | |
2679 | ||
0206e353 | 2680 | for (i = 0; i < 4; i++) { |
357555c0 JB |
2681 | reg = FDI_TX_CTL(pipe); |
2682 | temp = I915_READ(reg); | |
2683 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
2684 | temp |= snb_b_fdi_train_param[i]; | |
2685 | I915_WRITE(reg, temp); | |
2686 | ||
2687 | POSTING_READ(reg); | |
2688 | udelay(500); | |
2689 | ||
2690 | reg = FDI_RX_IIR(pipe); | |
2691 | temp = I915_READ(reg); | |
2692 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
2693 | ||
2694 | if (temp & FDI_RX_BIT_LOCK || | |
2695 | (I915_READ(reg) & FDI_RX_BIT_LOCK)) { | |
2696 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
01a415fd | 2697 | DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i); |
357555c0 JB |
2698 | break; |
2699 | } | |
2700 | } | |
2701 | if (i == 4) | |
2702 | DRM_ERROR("FDI train 1 fail!\n"); | |
2703 | ||
2704 | /* Train 2 */ | |
2705 | reg = FDI_TX_CTL(pipe); | |
2706 | temp = I915_READ(reg); | |
2707 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; | |
2708 | temp |= FDI_LINK_TRAIN_PATTERN_2_IVB; | |
2709 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
2710 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
2711 | I915_WRITE(reg, temp); | |
2712 | ||
2713 | reg = FDI_RX_CTL(pipe); | |
2714 | temp = I915_READ(reg); | |
2715 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2716 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
2717 | I915_WRITE(reg, temp); | |
2718 | ||
2719 | POSTING_READ(reg); | |
2720 | udelay(150); | |
2721 | ||
0206e353 | 2722 | for (i = 0; i < 4; i++) { |
357555c0 JB |
2723 | reg = FDI_TX_CTL(pipe); |
2724 | temp = I915_READ(reg); | |
2725 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
2726 | temp |= snb_b_fdi_train_param[i]; | |
2727 | I915_WRITE(reg, temp); | |
2728 | ||
2729 | POSTING_READ(reg); | |
2730 | udelay(500); | |
2731 | ||
2732 | reg = FDI_RX_IIR(pipe); | |
2733 | temp = I915_READ(reg); | |
2734 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
2735 | ||
2736 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
2737 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
01a415fd | 2738 | DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i); |
357555c0 JB |
2739 | break; |
2740 | } | |
2741 | } | |
2742 | if (i == 4) | |
2743 | DRM_ERROR("FDI train 2 fail!\n"); | |
2744 | ||
2745 | DRM_DEBUG_KMS("FDI train done.\n"); | |
2746 | } | |
2747 | ||
88cefb6c | 2748 | static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc) |
2c07245f | 2749 | { |
88cefb6c | 2750 | struct drm_device *dev = intel_crtc->base.dev; |
2c07245f | 2751 | struct drm_i915_private *dev_priv = dev->dev_private; |
2c07245f | 2752 | int pipe = intel_crtc->pipe; |
5eddb70b | 2753 | u32 reg, temp; |
79e53945 | 2754 | |
c64e311e | 2755 | |
c98e9dcf | 2756 | /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ |
5eddb70b CW |
2757 | reg = FDI_RX_CTL(pipe); |
2758 | temp = I915_READ(reg); | |
2759 | temp &= ~((0x7 << 19) | (0x7 << 16)); | |
c98e9dcf | 2760 | temp |= (intel_crtc->fdi_lanes - 1) << 19; |
dfd07d72 | 2761 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
5eddb70b CW |
2762 | I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE); |
2763 | ||
2764 | POSTING_READ(reg); | |
c98e9dcf JB |
2765 | udelay(200); |
2766 | ||
2767 | /* Switch from Rawclk to PCDclk */ | |
5eddb70b CW |
2768 | temp = I915_READ(reg); |
2769 | I915_WRITE(reg, temp | FDI_PCDCLK); | |
2770 | ||
2771 | POSTING_READ(reg); | |
c98e9dcf JB |
2772 | udelay(200); |
2773 | ||
20749730 PZ |
2774 | /* Enable CPU FDI TX PLL, always on for Ironlake */ |
2775 | reg = FDI_TX_CTL(pipe); | |
2776 | temp = I915_READ(reg); | |
2777 | if ((temp & FDI_TX_PLL_ENABLE) == 0) { | |
2778 | I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE); | |
5eddb70b | 2779 | |
20749730 PZ |
2780 | POSTING_READ(reg); |
2781 | udelay(100); | |
6be4a607 | 2782 | } |
0e23b99d JB |
2783 | } |
2784 | ||
88cefb6c DV |
2785 | static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc) |
2786 | { | |
2787 | struct drm_device *dev = intel_crtc->base.dev; | |
2788 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2789 | int pipe = intel_crtc->pipe; | |
2790 | u32 reg, temp; | |
2791 | ||
2792 | /* Switch from PCDclk to Rawclk */ | |
2793 | reg = FDI_RX_CTL(pipe); | |
2794 | temp = I915_READ(reg); | |
2795 | I915_WRITE(reg, temp & ~FDI_PCDCLK); | |
2796 | ||
2797 | /* Disable CPU FDI TX PLL */ | |
2798 | reg = FDI_TX_CTL(pipe); | |
2799 | temp = I915_READ(reg); | |
2800 | I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE); | |
2801 | ||
2802 | POSTING_READ(reg); | |
2803 | udelay(100); | |
2804 | ||
2805 | reg = FDI_RX_CTL(pipe); | |
2806 | temp = I915_READ(reg); | |
2807 | I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE); | |
2808 | ||
2809 | /* Wait for the clocks to turn off. */ | |
2810 | POSTING_READ(reg); | |
2811 | udelay(100); | |
2812 | } | |
2813 | ||
0fc932b8 JB |
2814 | static void ironlake_fdi_disable(struct drm_crtc *crtc) |
2815 | { | |
2816 | struct drm_device *dev = crtc->dev; | |
2817 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2818 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2819 | int pipe = intel_crtc->pipe; | |
2820 | u32 reg, temp; | |
2821 | ||
2822 | /* disable CPU FDI tx and PCH FDI rx */ | |
2823 | reg = FDI_TX_CTL(pipe); | |
2824 | temp = I915_READ(reg); | |
2825 | I915_WRITE(reg, temp & ~FDI_TX_ENABLE); | |
2826 | POSTING_READ(reg); | |
2827 | ||
2828 | reg = FDI_RX_CTL(pipe); | |
2829 | temp = I915_READ(reg); | |
2830 | temp &= ~(0x7 << 16); | |
dfd07d72 | 2831 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
2832 | I915_WRITE(reg, temp & ~FDI_RX_ENABLE); |
2833 | ||
2834 | POSTING_READ(reg); | |
2835 | udelay(100); | |
2836 | ||
2837 | /* Ironlake workaround, disable clock pointer after downing FDI */ | |
6f06ce18 JB |
2838 | if (HAS_PCH_IBX(dev)) { |
2839 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); | |
6f06ce18 | 2840 | } |
0fc932b8 JB |
2841 | |
2842 | /* still set train pattern 1 */ | |
2843 | reg = FDI_TX_CTL(pipe); | |
2844 | temp = I915_READ(reg); | |
2845 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2846 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
2847 | I915_WRITE(reg, temp); | |
2848 | ||
2849 | reg = FDI_RX_CTL(pipe); | |
2850 | temp = I915_READ(reg); | |
2851 | if (HAS_PCH_CPT(dev)) { | |
2852 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2853 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
2854 | } else { | |
2855 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2856 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
2857 | } | |
2858 | /* BPC in FDI rx is consistent with that in PIPECONF */ | |
2859 | temp &= ~(0x07 << 16); | |
dfd07d72 | 2860 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
2861 | I915_WRITE(reg, temp); |
2862 | ||
2863 | POSTING_READ(reg); | |
2864 | udelay(100); | |
2865 | } | |
2866 | ||
5bb61643 CW |
2867 | static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc) |
2868 | { | |
2869 | struct drm_device *dev = crtc->dev; | |
2870 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2871 | unsigned long flags; | |
2872 | bool pending; | |
2873 | ||
2874 | if (atomic_read(&dev_priv->mm.wedged)) | |
2875 | return false; | |
2876 | ||
2877 | spin_lock_irqsave(&dev->event_lock, flags); | |
2878 | pending = to_intel_crtc(crtc)->unpin_work != NULL; | |
2879 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
2880 | ||
2881 | return pending; | |
2882 | } | |
2883 | ||
e6c3a2a6 CW |
2884 | static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc) |
2885 | { | |
0f91128d | 2886 | struct drm_device *dev = crtc->dev; |
5bb61643 | 2887 | struct drm_i915_private *dev_priv = dev->dev_private; |
e6c3a2a6 CW |
2888 | |
2889 | if (crtc->fb == NULL) | |
2890 | return; | |
2891 | ||
2c10d571 DV |
2892 | WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue)); |
2893 | ||
5bb61643 CW |
2894 | wait_event(dev_priv->pending_flip_queue, |
2895 | !intel_crtc_has_pending_flip(crtc)); | |
2896 | ||
0f91128d CW |
2897 | mutex_lock(&dev->struct_mutex); |
2898 | intel_finish_fb(crtc->fb); | |
2899 | mutex_unlock(&dev->struct_mutex); | |
e6c3a2a6 CW |
2900 | } |
2901 | ||
fc316cbe | 2902 | static bool ironlake_crtc_driving_pch(struct drm_crtc *crtc) |
040484af JB |
2903 | { |
2904 | struct drm_device *dev = crtc->dev; | |
228d3e36 | 2905 | struct intel_encoder *intel_encoder; |
040484af JB |
2906 | |
2907 | /* | |
2908 | * If there's a non-PCH eDP on this crtc, it must be DP_A, and that | |
2909 | * must be driven by its own crtc; no sharing is possible. | |
2910 | */ | |
228d3e36 | 2911 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) { |
228d3e36 | 2912 | switch (intel_encoder->type) { |
040484af | 2913 | case INTEL_OUTPUT_EDP: |
228d3e36 | 2914 | if (!intel_encoder_is_pch_edp(&intel_encoder->base)) |
040484af JB |
2915 | return false; |
2916 | continue; | |
2917 | } | |
2918 | } | |
2919 | ||
2920 | return true; | |
2921 | } | |
2922 | ||
fc316cbe PZ |
2923 | static bool haswell_crtc_driving_pch(struct drm_crtc *crtc) |
2924 | { | |
2925 | return intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG); | |
2926 | } | |
2927 | ||
e615efe4 ED |
2928 | /* Program iCLKIP clock to the desired frequency */ |
2929 | static void lpt_program_iclkip(struct drm_crtc *crtc) | |
2930 | { | |
2931 | struct drm_device *dev = crtc->dev; | |
2932 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2933 | u32 divsel, phaseinc, auxdiv, phasedir = 0; | |
2934 | u32 temp; | |
2935 | ||
09153000 DV |
2936 | mutex_lock(&dev_priv->dpio_lock); |
2937 | ||
e615efe4 ED |
2938 | /* It is necessary to ungate the pixclk gate prior to programming |
2939 | * the divisors, and gate it back when it is done. | |
2940 | */ | |
2941 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE); | |
2942 | ||
2943 | /* Disable SSCCTL */ | |
2944 | intel_sbi_write(dev_priv, SBI_SSCCTL6, | |
988d6ee8 PZ |
2945 | intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) | |
2946 | SBI_SSCCTL_DISABLE, | |
2947 | SBI_ICLK); | |
e615efe4 ED |
2948 | |
2949 | /* 20MHz is a corner case which is out of range for the 7-bit divisor */ | |
2950 | if (crtc->mode.clock == 20000) { | |
2951 | auxdiv = 1; | |
2952 | divsel = 0x41; | |
2953 | phaseinc = 0x20; | |
2954 | } else { | |
2955 | /* The iCLK virtual clock root frequency is in MHz, | |
2956 | * but the crtc->mode.clock in in KHz. To get the divisors, | |
2957 | * it is necessary to divide one by another, so we | |
2958 | * convert the virtual clock precision to KHz here for higher | |
2959 | * precision. | |
2960 | */ | |
2961 | u32 iclk_virtual_root_freq = 172800 * 1000; | |
2962 | u32 iclk_pi_range = 64; | |
2963 | u32 desired_divisor, msb_divisor_value, pi_value; | |
2964 | ||
2965 | desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock); | |
2966 | msb_divisor_value = desired_divisor / iclk_pi_range; | |
2967 | pi_value = desired_divisor % iclk_pi_range; | |
2968 | ||
2969 | auxdiv = 0; | |
2970 | divsel = msb_divisor_value - 2; | |
2971 | phaseinc = pi_value; | |
2972 | } | |
2973 | ||
2974 | /* This should not happen with any sane values */ | |
2975 | WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) & | |
2976 | ~SBI_SSCDIVINTPHASE_DIVSEL_MASK); | |
2977 | WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) & | |
2978 | ~SBI_SSCDIVINTPHASE_INCVAL_MASK); | |
2979 | ||
2980 | DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n", | |
2981 | crtc->mode.clock, | |
2982 | auxdiv, | |
2983 | divsel, | |
2984 | phasedir, | |
2985 | phaseinc); | |
2986 | ||
2987 | /* Program SSCDIVINTPHASE6 */ | |
988d6ee8 | 2988 | temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); |
e615efe4 ED |
2989 | temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK; |
2990 | temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel); | |
2991 | temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK; | |
2992 | temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc); | |
2993 | temp |= SBI_SSCDIVINTPHASE_DIR(phasedir); | |
2994 | temp |= SBI_SSCDIVINTPHASE_PROPAGATE; | |
988d6ee8 | 2995 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK); |
e615efe4 ED |
2996 | |
2997 | /* Program SSCAUXDIV */ | |
988d6ee8 | 2998 | temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); |
e615efe4 ED |
2999 | temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1); |
3000 | temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv); | |
988d6ee8 | 3001 | intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK); |
e615efe4 ED |
3002 | |
3003 | /* Enable modulator and associated divider */ | |
988d6ee8 | 3004 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); |
e615efe4 | 3005 | temp &= ~SBI_SSCCTL_DISABLE; |
988d6ee8 | 3006 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); |
e615efe4 ED |
3007 | |
3008 | /* Wait for initialization time */ | |
3009 | udelay(24); | |
3010 | ||
3011 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE); | |
09153000 DV |
3012 | |
3013 | mutex_unlock(&dev_priv->dpio_lock); | |
e615efe4 ED |
3014 | } |
3015 | ||
f67a559d JB |
3016 | /* |
3017 | * Enable PCH resources required for PCH ports: | |
3018 | * - PCH PLLs | |
3019 | * - FDI training & RX/TX | |
3020 | * - update transcoder timings | |
3021 | * - DP transcoding bits | |
3022 | * - transcoder | |
3023 | */ | |
3024 | static void ironlake_pch_enable(struct drm_crtc *crtc) | |
0e23b99d JB |
3025 | { |
3026 | struct drm_device *dev = crtc->dev; | |
3027 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3028 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3029 | int pipe = intel_crtc->pipe; | |
ee7b9f93 | 3030 | u32 reg, temp; |
2c07245f | 3031 | |
e7e164db CW |
3032 | assert_transcoder_disabled(dev_priv, pipe); |
3033 | ||
cd986abb DV |
3034 | /* Write the TU size bits before fdi link training, so that error |
3035 | * detection works. */ | |
3036 | I915_WRITE(FDI_RX_TUSIZE1(pipe), | |
3037 | I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); | |
3038 | ||
c98e9dcf | 3039 | /* For PCH output, training FDI link */ |
674cf967 | 3040 | dev_priv->display.fdi_link_train(crtc); |
2c07245f | 3041 | |
572deb37 DV |
3042 | /* XXX: pch pll's can be enabled any time before we enable the PCH |
3043 | * transcoder, and we actually should do this to not upset any PCH | |
3044 | * transcoder that already use the clock when we share it. | |
3045 | * | |
3046 | * Note that enable_pch_pll tries to do the right thing, but get_pch_pll | |
3047 | * unconditionally resets the pll - we need that to have the right LVDS | |
3048 | * enable sequence. */ | |
b6b4e185 | 3049 | ironlake_enable_pch_pll(intel_crtc); |
6f13b7b5 | 3050 | |
303b81e0 | 3051 | if (HAS_PCH_CPT(dev)) { |
ee7b9f93 | 3052 | u32 sel; |
4b645f14 | 3053 | |
c98e9dcf | 3054 | temp = I915_READ(PCH_DPLL_SEL); |
ee7b9f93 JB |
3055 | switch (pipe) { |
3056 | default: | |
3057 | case 0: | |
3058 | temp |= TRANSA_DPLL_ENABLE; | |
3059 | sel = TRANSA_DPLLB_SEL; | |
3060 | break; | |
3061 | case 1: | |
3062 | temp |= TRANSB_DPLL_ENABLE; | |
3063 | sel = TRANSB_DPLLB_SEL; | |
3064 | break; | |
3065 | case 2: | |
3066 | temp |= TRANSC_DPLL_ENABLE; | |
3067 | sel = TRANSC_DPLLB_SEL; | |
3068 | break; | |
d64311ab | 3069 | } |
ee7b9f93 JB |
3070 | if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B) |
3071 | temp |= sel; | |
3072 | else | |
3073 | temp &= ~sel; | |
c98e9dcf | 3074 | I915_WRITE(PCH_DPLL_SEL, temp); |
c98e9dcf | 3075 | } |
5eddb70b | 3076 | |
d9b6cb56 JB |
3077 | /* set transcoder timing, panel must allow it */ |
3078 | assert_panel_unlocked(dev_priv, pipe); | |
5eddb70b CW |
3079 | I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe))); |
3080 | I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe))); | |
3081 | I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe))); | |
8db9d77b | 3082 | |
5eddb70b CW |
3083 | I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe))); |
3084 | I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe))); | |
3085 | I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe))); | |
0529a0d9 | 3086 | I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe))); |
8db9d77b | 3087 | |
303b81e0 | 3088 | intel_fdi_normal_train(crtc); |
5e84e1a4 | 3089 | |
c98e9dcf JB |
3090 | /* For PCH DP, enable TRANS_DP_CTL */ |
3091 | if (HAS_PCH_CPT(dev) && | |
417e822d KP |
3092 | (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) || |
3093 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) { | |
dfd07d72 | 3094 | u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5; |
5eddb70b CW |
3095 | reg = TRANS_DP_CTL(pipe); |
3096 | temp = I915_READ(reg); | |
3097 | temp &= ~(TRANS_DP_PORT_SEL_MASK | | |
220cad3c EA |
3098 | TRANS_DP_SYNC_MASK | |
3099 | TRANS_DP_BPC_MASK); | |
5eddb70b CW |
3100 | temp |= (TRANS_DP_OUTPUT_ENABLE | |
3101 | TRANS_DP_ENH_FRAMING); | |
9325c9f0 | 3102 | temp |= bpc << 9; /* same format but at 11:9 */ |
c98e9dcf JB |
3103 | |
3104 | if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC) | |
5eddb70b | 3105 | temp |= TRANS_DP_HSYNC_ACTIVE_HIGH; |
c98e9dcf | 3106 | if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC) |
5eddb70b | 3107 | temp |= TRANS_DP_VSYNC_ACTIVE_HIGH; |
c98e9dcf JB |
3108 | |
3109 | switch (intel_trans_dp_port_sel(crtc)) { | |
3110 | case PCH_DP_B: | |
5eddb70b | 3111 | temp |= TRANS_DP_PORT_SEL_B; |
c98e9dcf JB |
3112 | break; |
3113 | case PCH_DP_C: | |
5eddb70b | 3114 | temp |= TRANS_DP_PORT_SEL_C; |
c98e9dcf JB |
3115 | break; |
3116 | case PCH_DP_D: | |
5eddb70b | 3117 | temp |= TRANS_DP_PORT_SEL_D; |
c98e9dcf JB |
3118 | break; |
3119 | default: | |
e95d41e1 | 3120 | BUG(); |
32f9d658 | 3121 | } |
2c07245f | 3122 | |
5eddb70b | 3123 | I915_WRITE(reg, temp); |
6be4a607 | 3124 | } |
b52eb4dc | 3125 | |
b8a4f404 | 3126 | ironlake_enable_pch_transcoder(dev_priv, pipe); |
f67a559d JB |
3127 | } |
3128 | ||
1507e5bd PZ |
3129 | static void lpt_pch_enable(struct drm_crtc *crtc) |
3130 | { | |
3131 | struct drm_device *dev = crtc->dev; | |
3132 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3133 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
daed2dbb | 3134 | enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder; |
1507e5bd | 3135 | |
daed2dbb | 3136 | assert_transcoder_disabled(dev_priv, TRANSCODER_A); |
1507e5bd | 3137 | |
8c52b5e8 | 3138 | lpt_program_iclkip(crtc); |
1507e5bd | 3139 | |
0540e488 | 3140 | /* Set transcoder timing. */ |
daed2dbb PZ |
3141 | I915_WRITE(_TRANS_HTOTAL_A, I915_READ(HTOTAL(cpu_transcoder))); |
3142 | I915_WRITE(_TRANS_HBLANK_A, I915_READ(HBLANK(cpu_transcoder))); | |
3143 | I915_WRITE(_TRANS_HSYNC_A, I915_READ(HSYNC(cpu_transcoder))); | |
1507e5bd | 3144 | |
daed2dbb PZ |
3145 | I915_WRITE(_TRANS_VTOTAL_A, I915_READ(VTOTAL(cpu_transcoder))); |
3146 | I915_WRITE(_TRANS_VBLANK_A, I915_READ(VBLANK(cpu_transcoder))); | |
3147 | I915_WRITE(_TRANS_VSYNC_A, I915_READ(VSYNC(cpu_transcoder))); | |
3148 | I915_WRITE(_TRANS_VSYNCSHIFT_A, I915_READ(VSYNCSHIFT(cpu_transcoder))); | |
1507e5bd | 3149 | |
937bb610 | 3150 | lpt_enable_pch_transcoder(dev_priv, cpu_transcoder); |
f67a559d JB |
3151 | } |
3152 | ||
ee7b9f93 JB |
3153 | static void intel_put_pch_pll(struct intel_crtc *intel_crtc) |
3154 | { | |
3155 | struct intel_pch_pll *pll = intel_crtc->pch_pll; | |
3156 | ||
3157 | if (pll == NULL) | |
3158 | return; | |
3159 | ||
3160 | if (pll->refcount == 0) { | |
3161 | WARN(1, "bad PCH PLL refcount\n"); | |
3162 | return; | |
3163 | } | |
3164 | ||
3165 | --pll->refcount; | |
3166 | intel_crtc->pch_pll = NULL; | |
3167 | } | |
3168 | ||
3169 | static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp) | |
3170 | { | |
3171 | struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private; | |
3172 | struct intel_pch_pll *pll; | |
3173 | int i; | |
3174 | ||
3175 | pll = intel_crtc->pch_pll; | |
3176 | if (pll) { | |
3177 | DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n", | |
3178 | intel_crtc->base.base.id, pll->pll_reg); | |
3179 | goto prepare; | |
3180 | } | |
3181 | ||
98b6bd99 DV |
3182 | if (HAS_PCH_IBX(dev_priv->dev)) { |
3183 | /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */ | |
3184 | i = intel_crtc->pipe; | |
3185 | pll = &dev_priv->pch_plls[i]; | |
3186 | ||
3187 | DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n", | |
3188 | intel_crtc->base.base.id, pll->pll_reg); | |
3189 | ||
3190 | goto found; | |
3191 | } | |
3192 | ||
ee7b9f93 JB |
3193 | for (i = 0; i < dev_priv->num_pch_pll; i++) { |
3194 | pll = &dev_priv->pch_plls[i]; | |
3195 | ||
3196 | /* Only want to check enabled timings first */ | |
3197 | if (pll->refcount == 0) | |
3198 | continue; | |
3199 | ||
3200 | if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) && | |
3201 | fp == I915_READ(pll->fp0_reg)) { | |
3202 | DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n", | |
3203 | intel_crtc->base.base.id, | |
3204 | pll->pll_reg, pll->refcount, pll->active); | |
3205 | ||
3206 | goto found; | |
3207 | } | |
3208 | } | |
3209 | ||
3210 | /* Ok no matching timings, maybe there's a free one? */ | |
3211 | for (i = 0; i < dev_priv->num_pch_pll; i++) { | |
3212 | pll = &dev_priv->pch_plls[i]; | |
3213 | if (pll->refcount == 0) { | |
3214 | DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n", | |
3215 | intel_crtc->base.base.id, pll->pll_reg); | |
3216 | goto found; | |
3217 | } | |
3218 | } | |
3219 | ||
3220 | return NULL; | |
3221 | ||
3222 | found: | |
3223 | intel_crtc->pch_pll = pll; | |
3224 | pll->refcount++; | |
3225 | DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe); | |
3226 | prepare: /* separate function? */ | |
3227 | DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg); | |
ee7b9f93 | 3228 | |
e04c7350 CW |
3229 | /* Wait for the clocks to stabilize before rewriting the regs */ |
3230 | I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE); | |
ee7b9f93 JB |
3231 | POSTING_READ(pll->pll_reg); |
3232 | udelay(150); | |
e04c7350 CW |
3233 | |
3234 | I915_WRITE(pll->fp0_reg, fp); | |
3235 | I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE); | |
ee7b9f93 JB |
3236 | pll->on = false; |
3237 | return pll; | |
3238 | } | |
3239 | ||
d4270e57 JB |
3240 | void intel_cpt_verify_modeset(struct drm_device *dev, int pipe) |
3241 | { | |
3242 | struct drm_i915_private *dev_priv = dev->dev_private; | |
23670b32 | 3243 | int dslreg = PIPEDSL(pipe); |
d4270e57 JB |
3244 | u32 temp; |
3245 | ||
3246 | temp = I915_READ(dslreg); | |
3247 | udelay(500); | |
3248 | if (wait_for(I915_READ(dslreg) != temp, 5)) { | |
d4270e57 JB |
3249 | if (wait_for(I915_READ(dslreg) != temp, 5)) |
3250 | DRM_ERROR("mode set failed: pipe %d stuck\n", pipe); | |
3251 | } | |
3252 | } | |
3253 | ||
f67a559d JB |
3254 | static void ironlake_crtc_enable(struct drm_crtc *crtc) |
3255 | { | |
3256 | struct drm_device *dev = crtc->dev; | |
3257 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3258 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 3259 | struct intel_encoder *encoder; |
f67a559d JB |
3260 | int pipe = intel_crtc->pipe; |
3261 | int plane = intel_crtc->plane; | |
3262 | u32 temp; | |
3263 | bool is_pch_port; | |
3264 | ||
08a48469 DV |
3265 | WARN_ON(!crtc->enabled); |
3266 | ||
f67a559d JB |
3267 | if (intel_crtc->active) |
3268 | return; | |
3269 | ||
3270 | intel_crtc->active = true; | |
3271 | intel_update_watermarks(dev); | |
3272 | ||
3273 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
3274 | temp = I915_READ(PCH_LVDS); | |
3275 | if ((temp & LVDS_PORT_EN) == 0) | |
3276 | I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN); | |
3277 | } | |
3278 | ||
fc316cbe | 3279 | is_pch_port = ironlake_crtc_driving_pch(crtc); |
f67a559d | 3280 | |
46b6f814 | 3281 | if (is_pch_port) { |
fff367c7 DV |
3282 | /* Note: FDI PLL enabling _must_ be done before we enable the |
3283 | * cpu pipes, hence this is separate from all the other fdi/pch | |
3284 | * enabling. */ | |
88cefb6c | 3285 | ironlake_fdi_pll_enable(intel_crtc); |
46b6f814 DV |
3286 | } else { |
3287 | assert_fdi_tx_disabled(dev_priv, pipe); | |
3288 | assert_fdi_rx_disabled(dev_priv, pipe); | |
3289 | } | |
f67a559d | 3290 | |
bf49ec8c DV |
3291 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3292 | if (encoder->pre_enable) | |
3293 | encoder->pre_enable(encoder); | |
f67a559d JB |
3294 | |
3295 | /* Enable panel fitting for LVDS */ | |
3296 | if (dev_priv->pch_pf_size && | |
547dc041 JN |
3297 | (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || |
3298 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) { | |
f67a559d JB |
3299 | /* Force use of hard-coded filter coefficients |
3300 | * as some pre-programmed values are broken, | |
3301 | * e.g. x201. | |
3302 | */ | |
13888d78 PZ |
3303 | if (IS_IVYBRIDGE(dev)) |
3304 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 | | |
3305 | PF_PIPE_SEL_IVB(pipe)); | |
3306 | else | |
3307 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3); | |
9db4a9c7 JB |
3308 | I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos); |
3309 | I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size); | |
f67a559d JB |
3310 | } |
3311 | ||
9c54c0dd JB |
3312 | /* |
3313 | * On ILK+ LUT must be loaded before the pipe is running but with | |
3314 | * clocks enabled | |
3315 | */ | |
3316 | intel_crtc_load_lut(crtc); | |
3317 | ||
f67a559d JB |
3318 | intel_enable_pipe(dev_priv, pipe, is_pch_port); |
3319 | intel_enable_plane(dev_priv, plane, pipe); | |
3320 | ||
3321 | if (is_pch_port) | |
3322 | ironlake_pch_enable(crtc); | |
c98e9dcf | 3323 | |
d1ebd816 | 3324 | mutex_lock(&dev->struct_mutex); |
bed4a673 | 3325 | intel_update_fbc(dev); |
d1ebd816 BW |
3326 | mutex_unlock(&dev->struct_mutex); |
3327 | ||
6b383a7f | 3328 | intel_crtc_update_cursor(crtc, true); |
ef9c3aee | 3329 | |
fa5c73b1 DV |
3330 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3331 | encoder->enable(encoder); | |
61b77ddd DV |
3332 | |
3333 | if (HAS_PCH_CPT(dev)) | |
3334 | intel_cpt_verify_modeset(dev, intel_crtc->pipe); | |
6ce94100 DV |
3335 | |
3336 | /* | |
3337 | * There seems to be a race in PCH platform hw (at least on some | |
3338 | * outputs) where an enabled pipe still completes any pageflip right | |
3339 | * away (as if the pipe is off) instead of waiting for vblank. As soon | |
3340 | * as the first vblank happend, everything works as expected. Hence just | |
3341 | * wait for one vblank before returning to avoid strange things | |
3342 | * happening. | |
3343 | */ | |
3344 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
6be4a607 JB |
3345 | } |
3346 | ||
4f771f10 PZ |
3347 | static void haswell_crtc_enable(struct drm_crtc *crtc) |
3348 | { | |
3349 | struct drm_device *dev = crtc->dev; | |
3350 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3351 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3352 | struct intel_encoder *encoder; | |
3353 | int pipe = intel_crtc->pipe; | |
3354 | int plane = intel_crtc->plane; | |
4f771f10 PZ |
3355 | bool is_pch_port; |
3356 | ||
3357 | WARN_ON(!crtc->enabled); | |
3358 | ||
3359 | if (intel_crtc->active) | |
3360 | return; | |
3361 | ||
3362 | intel_crtc->active = true; | |
3363 | intel_update_watermarks(dev); | |
3364 | ||
fc316cbe | 3365 | is_pch_port = haswell_crtc_driving_pch(crtc); |
4f771f10 | 3366 | |
83616634 | 3367 | if (is_pch_port) |
04945641 | 3368 | dev_priv->display.fdi_link_train(crtc); |
4f771f10 PZ |
3369 | |
3370 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
3371 | if (encoder->pre_enable) | |
3372 | encoder->pre_enable(encoder); | |
3373 | ||
1f544388 | 3374 | intel_ddi_enable_pipe_clock(intel_crtc); |
4f771f10 | 3375 | |
1f544388 | 3376 | /* Enable panel fitting for eDP */ |
547dc041 JN |
3377 | if (dev_priv->pch_pf_size && |
3378 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) { | |
4f771f10 PZ |
3379 | /* Force use of hard-coded filter coefficients |
3380 | * as some pre-programmed values are broken, | |
3381 | * e.g. x201. | |
3382 | */ | |
54075a7d PZ |
3383 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 | |
3384 | PF_PIPE_SEL_IVB(pipe)); | |
4f771f10 PZ |
3385 | I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos); |
3386 | I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size); | |
3387 | } | |
3388 | ||
3389 | /* | |
3390 | * On ILK+ LUT must be loaded before the pipe is running but with | |
3391 | * clocks enabled | |
3392 | */ | |
3393 | intel_crtc_load_lut(crtc); | |
3394 | ||
1f544388 PZ |
3395 | intel_ddi_set_pipe_settings(crtc); |
3396 | intel_ddi_enable_pipe_func(crtc); | |
4f771f10 PZ |
3397 | |
3398 | intel_enable_pipe(dev_priv, pipe, is_pch_port); | |
3399 | intel_enable_plane(dev_priv, plane, pipe); | |
3400 | ||
3401 | if (is_pch_port) | |
1507e5bd | 3402 | lpt_pch_enable(crtc); |
4f771f10 PZ |
3403 | |
3404 | mutex_lock(&dev->struct_mutex); | |
3405 | intel_update_fbc(dev); | |
3406 | mutex_unlock(&dev->struct_mutex); | |
3407 | ||
3408 | intel_crtc_update_cursor(crtc, true); | |
3409 | ||
3410 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
3411 | encoder->enable(encoder); | |
3412 | ||
4f771f10 PZ |
3413 | /* |
3414 | * There seems to be a race in PCH platform hw (at least on some | |
3415 | * outputs) where an enabled pipe still completes any pageflip right | |
3416 | * away (as if the pipe is off) instead of waiting for vblank. As soon | |
3417 | * as the first vblank happend, everything works as expected. Hence just | |
3418 | * wait for one vblank before returning to avoid strange things | |
3419 | * happening. | |
3420 | */ | |
3421 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
3422 | } | |
3423 | ||
6be4a607 JB |
3424 | static void ironlake_crtc_disable(struct drm_crtc *crtc) |
3425 | { | |
3426 | struct drm_device *dev = crtc->dev; | |
3427 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3428 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 3429 | struct intel_encoder *encoder; |
6be4a607 JB |
3430 | int pipe = intel_crtc->pipe; |
3431 | int plane = intel_crtc->plane; | |
5eddb70b | 3432 | u32 reg, temp; |
b52eb4dc | 3433 | |
ef9c3aee | 3434 | |
f7abfe8b CW |
3435 | if (!intel_crtc->active) |
3436 | return; | |
3437 | ||
ea9d758d DV |
3438 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3439 | encoder->disable(encoder); | |
3440 | ||
e6c3a2a6 | 3441 | intel_crtc_wait_for_pending_flips(crtc); |
6be4a607 | 3442 | drm_vblank_off(dev, pipe); |
6b383a7f | 3443 | intel_crtc_update_cursor(crtc, false); |
5eddb70b | 3444 | |
b24e7179 | 3445 | intel_disable_plane(dev_priv, plane, pipe); |
913d8d11 | 3446 | |
973d04f9 CW |
3447 | if (dev_priv->cfb_plane == plane) |
3448 | intel_disable_fbc(dev); | |
2c07245f | 3449 | |
b24e7179 | 3450 | intel_disable_pipe(dev_priv, pipe); |
32f9d658 | 3451 | |
6be4a607 | 3452 | /* Disable PF */ |
9db4a9c7 JB |
3453 | I915_WRITE(PF_CTL(pipe), 0); |
3454 | I915_WRITE(PF_WIN_SZ(pipe), 0); | |
2c07245f | 3455 | |
bf49ec8c DV |
3456 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3457 | if (encoder->post_disable) | |
3458 | encoder->post_disable(encoder); | |
2c07245f | 3459 | |
0fc932b8 | 3460 | ironlake_fdi_disable(crtc); |
249c0e64 | 3461 | |
b8a4f404 | 3462 | ironlake_disable_pch_transcoder(dev_priv, pipe); |
913d8d11 | 3463 | |
6be4a607 JB |
3464 | if (HAS_PCH_CPT(dev)) { |
3465 | /* disable TRANS_DP_CTL */ | |
5eddb70b CW |
3466 | reg = TRANS_DP_CTL(pipe); |
3467 | temp = I915_READ(reg); | |
3468 | temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK); | |
cb3543c6 | 3469 | temp |= TRANS_DP_PORT_SEL_NONE; |
5eddb70b | 3470 | I915_WRITE(reg, temp); |
6be4a607 JB |
3471 | |
3472 | /* disable DPLL_SEL */ | |
3473 | temp = I915_READ(PCH_DPLL_SEL); | |
9db4a9c7 JB |
3474 | switch (pipe) { |
3475 | case 0: | |
d64311ab | 3476 | temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL); |
9db4a9c7 JB |
3477 | break; |
3478 | case 1: | |
6be4a607 | 3479 | temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL); |
9db4a9c7 JB |
3480 | break; |
3481 | case 2: | |
4b645f14 | 3482 | /* C shares PLL A or B */ |
d64311ab | 3483 | temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL); |
9db4a9c7 JB |
3484 | break; |
3485 | default: | |
3486 | BUG(); /* wtf */ | |
3487 | } | |
6be4a607 | 3488 | I915_WRITE(PCH_DPLL_SEL, temp); |
6be4a607 | 3489 | } |
e3421a18 | 3490 | |
6be4a607 | 3491 | /* disable PCH DPLL */ |
ee7b9f93 | 3492 | intel_disable_pch_pll(intel_crtc); |
8db9d77b | 3493 | |
88cefb6c | 3494 | ironlake_fdi_pll_disable(intel_crtc); |
6b383a7f | 3495 | |
f7abfe8b | 3496 | intel_crtc->active = false; |
6b383a7f | 3497 | intel_update_watermarks(dev); |
d1ebd816 BW |
3498 | |
3499 | mutex_lock(&dev->struct_mutex); | |
6b383a7f | 3500 | intel_update_fbc(dev); |
d1ebd816 | 3501 | mutex_unlock(&dev->struct_mutex); |
6be4a607 | 3502 | } |
1b3c7a47 | 3503 | |
4f771f10 | 3504 | static void haswell_crtc_disable(struct drm_crtc *crtc) |
ee7b9f93 | 3505 | { |
4f771f10 PZ |
3506 | struct drm_device *dev = crtc->dev; |
3507 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ee7b9f93 | 3508 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4f771f10 PZ |
3509 | struct intel_encoder *encoder; |
3510 | int pipe = intel_crtc->pipe; | |
3511 | int plane = intel_crtc->plane; | |
ad80a810 | 3512 | enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder; |
83616634 | 3513 | bool is_pch_port; |
ee7b9f93 | 3514 | |
4f771f10 PZ |
3515 | if (!intel_crtc->active) |
3516 | return; | |
3517 | ||
83616634 PZ |
3518 | is_pch_port = haswell_crtc_driving_pch(crtc); |
3519 | ||
4f771f10 PZ |
3520 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3521 | encoder->disable(encoder); | |
3522 | ||
3523 | intel_crtc_wait_for_pending_flips(crtc); | |
3524 | drm_vblank_off(dev, pipe); | |
3525 | intel_crtc_update_cursor(crtc, false); | |
3526 | ||
3527 | intel_disable_plane(dev_priv, plane, pipe); | |
3528 | ||
3529 | if (dev_priv->cfb_plane == plane) | |
3530 | intel_disable_fbc(dev); | |
3531 | ||
3532 | intel_disable_pipe(dev_priv, pipe); | |
3533 | ||
ad80a810 | 3534 | intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder); |
4f771f10 PZ |
3535 | |
3536 | /* Disable PF */ | |
3537 | I915_WRITE(PF_CTL(pipe), 0); | |
3538 | I915_WRITE(PF_WIN_SZ(pipe), 0); | |
3539 | ||
1f544388 | 3540 | intel_ddi_disable_pipe_clock(intel_crtc); |
4f771f10 PZ |
3541 | |
3542 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
3543 | if (encoder->post_disable) | |
3544 | encoder->post_disable(encoder); | |
3545 | ||
83616634 | 3546 | if (is_pch_port) { |
ab4d966c | 3547 | lpt_disable_pch_transcoder(dev_priv); |
1ad960f2 | 3548 | intel_ddi_fdi_disable(crtc); |
83616634 | 3549 | } |
4f771f10 PZ |
3550 | |
3551 | intel_crtc->active = false; | |
3552 | intel_update_watermarks(dev); | |
3553 | ||
3554 | mutex_lock(&dev->struct_mutex); | |
3555 | intel_update_fbc(dev); | |
3556 | mutex_unlock(&dev->struct_mutex); | |
3557 | } | |
3558 | ||
ee7b9f93 JB |
3559 | static void ironlake_crtc_off(struct drm_crtc *crtc) |
3560 | { | |
3561 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3562 | intel_put_pch_pll(intel_crtc); | |
3563 | } | |
3564 | ||
6441ab5f PZ |
3565 | static void haswell_crtc_off(struct drm_crtc *crtc) |
3566 | { | |
a5c961d1 PZ |
3567 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3568 | ||
3569 | /* Stop saying we're using TRANSCODER_EDP because some other CRTC might | |
3570 | * start using it. */ | |
1a240d4d | 3571 | intel_crtc->cpu_transcoder = (enum transcoder) intel_crtc->pipe; |
a5c961d1 | 3572 | |
6441ab5f PZ |
3573 | intel_ddi_put_crtc_pll(crtc); |
3574 | } | |
3575 | ||
02e792fb DV |
3576 | static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable) |
3577 | { | |
02e792fb | 3578 | if (!enable && intel_crtc->overlay) { |
23f09ce3 | 3579 | struct drm_device *dev = intel_crtc->base.dev; |
ce453d81 | 3580 | struct drm_i915_private *dev_priv = dev->dev_private; |
03f77ea5 | 3581 | |
23f09ce3 | 3582 | mutex_lock(&dev->struct_mutex); |
ce453d81 CW |
3583 | dev_priv->mm.interruptible = false; |
3584 | (void) intel_overlay_switch_off(intel_crtc->overlay); | |
3585 | dev_priv->mm.interruptible = true; | |
23f09ce3 | 3586 | mutex_unlock(&dev->struct_mutex); |
02e792fb | 3587 | } |
02e792fb | 3588 | |
5dcdbcb0 CW |
3589 | /* Let userspace switch the overlay on again. In most cases userspace |
3590 | * has to recompute where to put it anyway. | |
3591 | */ | |
02e792fb DV |
3592 | } |
3593 | ||
0b8765c6 | 3594 | static void i9xx_crtc_enable(struct drm_crtc *crtc) |
79e53945 JB |
3595 | { |
3596 | struct drm_device *dev = crtc->dev; | |
79e53945 JB |
3597 | struct drm_i915_private *dev_priv = dev->dev_private; |
3598 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 3599 | struct intel_encoder *encoder; |
79e53945 | 3600 | int pipe = intel_crtc->pipe; |
80824003 | 3601 | int plane = intel_crtc->plane; |
79e53945 | 3602 | |
08a48469 DV |
3603 | WARN_ON(!crtc->enabled); |
3604 | ||
f7abfe8b CW |
3605 | if (intel_crtc->active) |
3606 | return; | |
3607 | ||
3608 | intel_crtc->active = true; | |
6b383a7f CW |
3609 | intel_update_watermarks(dev); |
3610 | ||
63d7bbe9 | 3611 | intel_enable_pll(dev_priv, pipe); |
040484af | 3612 | intel_enable_pipe(dev_priv, pipe, false); |
b24e7179 | 3613 | intel_enable_plane(dev_priv, plane, pipe); |
79e53945 | 3614 | |
0b8765c6 | 3615 | intel_crtc_load_lut(crtc); |
bed4a673 | 3616 | intel_update_fbc(dev); |
79e53945 | 3617 | |
0b8765c6 JB |
3618 | /* Give the overlay scaler a chance to enable if it's on this pipe */ |
3619 | intel_crtc_dpms_overlay(intel_crtc, true); | |
6b383a7f | 3620 | intel_crtc_update_cursor(crtc, true); |
ef9c3aee | 3621 | |
fa5c73b1 DV |
3622 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3623 | encoder->enable(encoder); | |
0b8765c6 | 3624 | } |
79e53945 | 3625 | |
0b8765c6 JB |
3626 | static void i9xx_crtc_disable(struct drm_crtc *crtc) |
3627 | { | |
3628 | struct drm_device *dev = crtc->dev; | |
3629 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3630 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 3631 | struct intel_encoder *encoder; |
0b8765c6 JB |
3632 | int pipe = intel_crtc->pipe; |
3633 | int plane = intel_crtc->plane; | |
b690e96c | 3634 | |
ef9c3aee | 3635 | |
f7abfe8b CW |
3636 | if (!intel_crtc->active) |
3637 | return; | |
3638 | ||
ea9d758d DV |
3639 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3640 | encoder->disable(encoder); | |
3641 | ||
0b8765c6 | 3642 | /* Give the overlay scaler a chance to disable if it's on this pipe */ |
e6c3a2a6 CW |
3643 | intel_crtc_wait_for_pending_flips(crtc); |
3644 | drm_vblank_off(dev, pipe); | |
0b8765c6 | 3645 | intel_crtc_dpms_overlay(intel_crtc, false); |
6b383a7f | 3646 | intel_crtc_update_cursor(crtc, false); |
0b8765c6 | 3647 | |
973d04f9 CW |
3648 | if (dev_priv->cfb_plane == plane) |
3649 | intel_disable_fbc(dev); | |
79e53945 | 3650 | |
b24e7179 | 3651 | intel_disable_plane(dev_priv, plane, pipe); |
b24e7179 | 3652 | intel_disable_pipe(dev_priv, pipe); |
63d7bbe9 | 3653 | intel_disable_pll(dev_priv, pipe); |
0b8765c6 | 3654 | |
f7abfe8b | 3655 | intel_crtc->active = false; |
6b383a7f CW |
3656 | intel_update_fbc(dev); |
3657 | intel_update_watermarks(dev); | |
0b8765c6 JB |
3658 | } |
3659 | ||
ee7b9f93 JB |
3660 | static void i9xx_crtc_off(struct drm_crtc *crtc) |
3661 | { | |
3662 | } | |
3663 | ||
976f8a20 DV |
3664 | static void intel_crtc_update_sarea(struct drm_crtc *crtc, |
3665 | bool enabled) | |
2c07245f ZW |
3666 | { |
3667 | struct drm_device *dev = crtc->dev; | |
3668 | struct drm_i915_master_private *master_priv; | |
3669 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3670 | int pipe = intel_crtc->pipe; | |
79e53945 JB |
3671 | |
3672 | if (!dev->primary->master) | |
3673 | return; | |
3674 | ||
3675 | master_priv = dev->primary->master->driver_priv; | |
3676 | if (!master_priv->sarea_priv) | |
3677 | return; | |
3678 | ||
79e53945 JB |
3679 | switch (pipe) { |
3680 | case 0: | |
3681 | master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0; | |
3682 | master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0; | |
3683 | break; | |
3684 | case 1: | |
3685 | master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0; | |
3686 | master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0; | |
3687 | break; | |
3688 | default: | |
9db4a9c7 | 3689 | DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe)); |
79e53945 JB |
3690 | break; |
3691 | } | |
79e53945 JB |
3692 | } |
3693 | ||
976f8a20 DV |
3694 | /** |
3695 | * Sets the power management mode of the pipe and plane. | |
3696 | */ | |
3697 | void intel_crtc_update_dpms(struct drm_crtc *crtc) | |
3698 | { | |
3699 | struct drm_device *dev = crtc->dev; | |
3700 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3701 | struct intel_encoder *intel_encoder; | |
3702 | bool enable = false; | |
3703 | ||
3704 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) | |
3705 | enable |= intel_encoder->connectors_active; | |
3706 | ||
3707 | if (enable) | |
3708 | dev_priv->display.crtc_enable(crtc); | |
3709 | else | |
3710 | dev_priv->display.crtc_disable(crtc); | |
3711 | ||
3712 | intel_crtc_update_sarea(crtc, enable); | |
3713 | } | |
3714 | ||
3715 | static void intel_crtc_noop(struct drm_crtc *crtc) | |
3716 | { | |
3717 | } | |
3718 | ||
cdd59983 CW |
3719 | static void intel_crtc_disable(struct drm_crtc *crtc) |
3720 | { | |
cdd59983 | 3721 | struct drm_device *dev = crtc->dev; |
976f8a20 | 3722 | struct drm_connector *connector; |
ee7b9f93 | 3723 | struct drm_i915_private *dev_priv = dev->dev_private; |
cdd59983 | 3724 | |
976f8a20 DV |
3725 | /* crtc should still be enabled when we disable it. */ |
3726 | WARN_ON(!crtc->enabled); | |
3727 | ||
3728 | dev_priv->display.crtc_disable(crtc); | |
3729 | intel_crtc_update_sarea(crtc, false); | |
ee7b9f93 JB |
3730 | dev_priv->display.off(crtc); |
3731 | ||
931872fc CW |
3732 | assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane); |
3733 | assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe); | |
cdd59983 CW |
3734 | |
3735 | if (crtc->fb) { | |
3736 | mutex_lock(&dev->struct_mutex); | |
1690e1eb | 3737 | intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj); |
cdd59983 | 3738 | mutex_unlock(&dev->struct_mutex); |
976f8a20 DV |
3739 | crtc->fb = NULL; |
3740 | } | |
3741 | ||
3742 | /* Update computed state. */ | |
3743 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
3744 | if (!connector->encoder || !connector->encoder->crtc) | |
3745 | continue; | |
3746 | ||
3747 | if (connector->encoder->crtc != crtc) | |
3748 | continue; | |
3749 | ||
3750 | connector->dpms = DRM_MODE_DPMS_OFF; | |
3751 | to_intel_encoder(connector->encoder)->connectors_active = false; | |
cdd59983 CW |
3752 | } |
3753 | } | |
3754 | ||
a261b246 | 3755 | void intel_modeset_disable(struct drm_device *dev) |
79e53945 | 3756 | { |
a261b246 DV |
3757 | struct drm_crtc *crtc; |
3758 | ||
3759 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
3760 | if (crtc->enabled) | |
3761 | intel_crtc_disable(crtc); | |
3762 | } | |
79e53945 JB |
3763 | } |
3764 | ||
1f703855 | 3765 | void intel_encoder_noop(struct drm_encoder *encoder) |
79e53945 | 3766 | { |
7e7d76c3 JB |
3767 | } |
3768 | ||
ea5b213a | 3769 | void intel_encoder_destroy(struct drm_encoder *encoder) |
7e7d76c3 | 3770 | { |
4ef69c7a | 3771 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
ea5b213a | 3772 | |
ea5b213a CW |
3773 | drm_encoder_cleanup(encoder); |
3774 | kfree(intel_encoder); | |
7e7d76c3 JB |
3775 | } |
3776 | ||
5ab432ef DV |
3777 | /* Simple dpms helper for encodres with just one connector, no cloning and only |
3778 | * one kind of off state. It clamps all !ON modes to fully OFF and changes the | |
3779 | * state of the entire output pipe. */ | |
3780 | void intel_encoder_dpms(struct intel_encoder *encoder, int mode) | |
7e7d76c3 | 3781 | { |
5ab432ef DV |
3782 | if (mode == DRM_MODE_DPMS_ON) { |
3783 | encoder->connectors_active = true; | |
3784 | ||
b2cabb0e | 3785 | intel_crtc_update_dpms(encoder->base.crtc); |
5ab432ef DV |
3786 | } else { |
3787 | encoder->connectors_active = false; | |
3788 | ||
b2cabb0e | 3789 | intel_crtc_update_dpms(encoder->base.crtc); |
5ab432ef | 3790 | } |
79e53945 JB |
3791 | } |
3792 | ||
0a91ca29 DV |
3793 | /* Cross check the actual hw state with our own modeset state tracking (and it's |
3794 | * internal consistency). */ | |
b980514c | 3795 | static void intel_connector_check_state(struct intel_connector *connector) |
79e53945 | 3796 | { |
0a91ca29 DV |
3797 | if (connector->get_hw_state(connector)) { |
3798 | struct intel_encoder *encoder = connector->encoder; | |
3799 | struct drm_crtc *crtc; | |
3800 | bool encoder_enabled; | |
3801 | enum pipe pipe; | |
3802 | ||
3803 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", | |
3804 | connector->base.base.id, | |
3805 | drm_get_connector_name(&connector->base)); | |
3806 | ||
3807 | WARN(connector->base.dpms == DRM_MODE_DPMS_OFF, | |
3808 | "wrong connector dpms state\n"); | |
3809 | WARN(connector->base.encoder != &encoder->base, | |
3810 | "active connector not linked to encoder\n"); | |
3811 | WARN(!encoder->connectors_active, | |
3812 | "encoder->connectors_active not set\n"); | |
3813 | ||
3814 | encoder_enabled = encoder->get_hw_state(encoder, &pipe); | |
3815 | WARN(!encoder_enabled, "encoder not enabled\n"); | |
3816 | if (WARN_ON(!encoder->base.crtc)) | |
3817 | return; | |
3818 | ||
3819 | crtc = encoder->base.crtc; | |
3820 | ||
3821 | WARN(!crtc->enabled, "crtc not enabled\n"); | |
3822 | WARN(!to_intel_crtc(crtc)->active, "crtc not active\n"); | |
3823 | WARN(pipe != to_intel_crtc(crtc)->pipe, | |
3824 | "encoder active on the wrong pipe\n"); | |
3825 | } | |
79e53945 JB |
3826 | } |
3827 | ||
5ab432ef DV |
3828 | /* Even simpler default implementation, if there's really no special case to |
3829 | * consider. */ | |
3830 | void intel_connector_dpms(struct drm_connector *connector, int mode) | |
79e53945 | 3831 | { |
5ab432ef | 3832 | struct intel_encoder *encoder = intel_attached_encoder(connector); |
d4270e57 | 3833 | |
5ab432ef DV |
3834 | /* All the simple cases only support two dpms states. */ |
3835 | if (mode != DRM_MODE_DPMS_ON) | |
3836 | mode = DRM_MODE_DPMS_OFF; | |
d4270e57 | 3837 | |
5ab432ef DV |
3838 | if (mode == connector->dpms) |
3839 | return; | |
3840 | ||
3841 | connector->dpms = mode; | |
3842 | ||
3843 | /* Only need to change hw state when actually enabled */ | |
3844 | if (encoder->base.crtc) | |
3845 | intel_encoder_dpms(encoder, mode); | |
3846 | else | |
8af6cf88 | 3847 | WARN_ON(encoder->connectors_active != false); |
0a91ca29 | 3848 | |
b980514c | 3849 | intel_modeset_check_state(connector->dev); |
79e53945 JB |
3850 | } |
3851 | ||
f0947c37 DV |
3852 | /* Simple connector->get_hw_state implementation for encoders that support only |
3853 | * one connector and no cloning and hence the encoder state determines the state | |
3854 | * of the connector. */ | |
3855 | bool intel_connector_get_hw_state(struct intel_connector *connector) | |
ea5b213a | 3856 | { |
24929352 | 3857 | enum pipe pipe = 0; |
f0947c37 | 3858 | struct intel_encoder *encoder = connector->encoder; |
ea5b213a | 3859 | |
f0947c37 | 3860 | return encoder->get_hw_state(encoder, &pipe); |
ea5b213a CW |
3861 | } |
3862 | ||
79e53945 | 3863 | static bool intel_crtc_mode_fixup(struct drm_crtc *crtc, |
35313cde | 3864 | const struct drm_display_mode *mode, |
79e53945 JB |
3865 | struct drm_display_mode *adjusted_mode) |
3866 | { | |
2c07245f | 3867 | struct drm_device *dev = crtc->dev; |
89749350 | 3868 | |
bad720ff | 3869 | if (HAS_PCH_SPLIT(dev)) { |
2c07245f | 3870 | /* FDI link clock is fixed at 2.7G */ |
2377b741 JB |
3871 | if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4) |
3872 | return false; | |
2c07245f | 3873 | } |
89749350 | 3874 | |
f9bef081 DV |
3875 | /* All interlaced capable intel hw wants timings in frames. Note though |
3876 | * that intel_lvds_mode_fixup does some funny tricks with the crtc | |
3877 | * timings, so we need to be careful not to clobber these.*/ | |
3878 | if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET)) | |
3879 | drm_mode_set_crtcinfo(adjusted_mode, 0); | |
89749350 | 3880 | |
44f46b42 CW |
3881 | /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes |
3882 | * with a hsync front porch of 0. | |
3883 | */ | |
3884 | if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) && | |
3885 | adjusted_mode->hsync_start == adjusted_mode->hdisplay) | |
3886 | return false; | |
3887 | ||
79e53945 JB |
3888 | return true; |
3889 | } | |
3890 | ||
25eb05fc JB |
3891 | static int valleyview_get_display_clock_speed(struct drm_device *dev) |
3892 | { | |
3893 | return 400000; /* FIXME */ | |
3894 | } | |
3895 | ||
e70236a8 JB |
3896 | static int i945_get_display_clock_speed(struct drm_device *dev) |
3897 | { | |
3898 | return 400000; | |
3899 | } | |
79e53945 | 3900 | |
e70236a8 | 3901 | static int i915_get_display_clock_speed(struct drm_device *dev) |
79e53945 | 3902 | { |
e70236a8 JB |
3903 | return 333000; |
3904 | } | |
79e53945 | 3905 | |
e70236a8 JB |
3906 | static int i9xx_misc_get_display_clock_speed(struct drm_device *dev) |
3907 | { | |
3908 | return 200000; | |
3909 | } | |
79e53945 | 3910 | |
e70236a8 JB |
3911 | static int i915gm_get_display_clock_speed(struct drm_device *dev) |
3912 | { | |
3913 | u16 gcfgc = 0; | |
79e53945 | 3914 | |
e70236a8 JB |
3915 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); |
3916 | ||
3917 | if (gcfgc & GC_LOW_FREQUENCY_ENABLE) | |
3918 | return 133000; | |
3919 | else { | |
3920 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
3921 | case GC_DISPLAY_CLOCK_333_MHZ: | |
3922 | return 333000; | |
3923 | default: | |
3924 | case GC_DISPLAY_CLOCK_190_200_MHZ: | |
3925 | return 190000; | |
79e53945 | 3926 | } |
e70236a8 JB |
3927 | } |
3928 | } | |
3929 | ||
3930 | static int i865_get_display_clock_speed(struct drm_device *dev) | |
3931 | { | |
3932 | return 266000; | |
3933 | } | |
3934 | ||
3935 | static int i855_get_display_clock_speed(struct drm_device *dev) | |
3936 | { | |
3937 | u16 hpllcc = 0; | |
3938 | /* Assume that the hardware is in the high speed state. This | |
3939 | * should be the default. | |
3940 | */ | |
3941 | switch (hpllcc & GC_CLOCK_CONTROL_MASK) { | |
3942 | case GC_CLOCK_133_200: | |
3943 | case GC_CLOCK_100_200: | |
3944 | return 200000; | |
3945 | case GC_CLOCK_166_250: | |
3946 | return 250000; | |
3947 | case GC_CLOCK_100_133: | |
79e53945 | 3948 | return 133000; |
e70236a8 | 3949 | } |
79e53945 | 3950 | |
e70236a8 JB |
3951 | /* Shouldn't happen */ |
3952 | return 0; | |
3953 | } | |
79e53945 | 3954 | |
e70236a8 JB |
3955 | static int i830_get_display_clock_speed(struct drm_device *dev) |
3956 | { | |
3957 | return 133000; | |
79e53945 JB |
3958 | } |
3959 | ||
2c07245f | 3960 | static void |
e69d0bc1 | 3961 | intel_reduce_ratio(uint32_t *num, uint32_t *den) |
2c07245f ZW |
3962 | { |
3963 | while (*num > 0xffffff || *den > 0xffffff) { | |
3964 | *num >>= 1; | |
3965 | *den >>= 1; | |
3966 | } | |
3967 | } | |
3968 | ||
e69d0bc1 DV |
3969 | void |
3970 | intel_link_compute_m_n(int bits_per_pixel, int nlanes, | |
3971 | int pixel_clock, int link_clock, | |
3972 | struct intel_link_m_n *m_n) | |
2c07245f | 3973 | { |
e69d0bc1 | 3974 | m_n->tu = 64; |
22ed1113 CW |
3975 | m_n->gmch_m = bits_per_pixel * pixel_clock; |
3976 | m_n->gmch_n = link_clock * nlanes * 8; | |
e69d0bc1 | 3977 | intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n); |
22ed1113 CW |
3978 | m_n->link_m = pixel_clock; |
3979 | m_n->link_n = link_clock; | |
e69d0bc1 | 3980 | intel_reduce_ratio(&m_n->link_m, &m_n->link_n); |
2c07245f ZW |
3981 | } |
3982 | ||
a7615030 CW |
3983 | static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv) |
3984 | { | |
72bbe58c KP |
3985 | if (i915_panel_use_ssc >= 0) |
3986 | return i915_panel_use_ssc != 0; | |
3987 | return dev_priv->lvds_use_ssc | |
435793df | 3988 | && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE); |
a7615030 CW |
3989 | } |
3990 | ||
5a354204 JB |
3991 | /** |
3992 | * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send | |
3993 | * @crtc: CRTC structure | |
3b5c78a3 | 3994 | * @mode: requested mode |
5a354204 JB |
3995 | * |
3996 | * A pipe may be connected to one or more outputs. Based on the depth of the | |
3997 | * attached framebuffer, choose a good color depth to use on the pipe. | |
3998 | * | |
3999 | * If possible, match the pipe depth to the fb depth. In some cases, this | |
4000 | * isn't ideal, because the connected output supports a lesser or restricted | |
4001 | * set of depths. Resolve that here: | |
4002 | * LVDS typically supports only 6bpc, so clamp down in that case | |
4003 | * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc | |
4004 | * Displays may support a restricted set as well, check EDID and clamp as | |
4005 | * appropriate. | |
3b5c78a3 | 4006 | * DP may want to dither down to 6bpc to fit larger modes |
5a354204 JB |
4007 | * |
4008 | * RETURNS: | |
4009 | * Dithering requirement (i.e. false if display bpc and pipe bpc match, | |
4010 | * true if they don't match). | |
4011 | */ | |
4012 | static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc, | |
94352cf9 | 4013 | struct drm_framebuffer *fb, |
3b5c78a3 AJ |
4014 | unsigned int *pipe_bpp, |
4015 | struct drm_display_mode *mode) | |
5a354204 JB |
4016 | { |
4017 | struct drm_device *dev = crtc->dev; | |
4018 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5a354204 | 4019 | struct drm_connector *connector; |
6c2b7c12 | 4020 | struct intel_encoder *intel_encoder; |
5a354204 JB |
4021 | unsigned int display_bpc = UINT_MAX, bpc; |
4022 | ||
4023 | /* Walk the encoders & connectors on this crtc, get min bpc */ | |
6c2b7c12 | 4024 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) { |
5a354204 JB |
4025 | |
4026 | if (intel_encoder->type == INTEL_OUTPUT_LVDS) { | |
4027 | unsigned int lvds_bpc; | |
4028 | ||
4029 | if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) == | |
4030 | LVDS_A3_POWER_UP) | |
4031 | lvds_bpc = 8; | |
4032 | else | |
4033 | lvds_bpc = 6; | |
4034 | ||
4035 | if (lvds_bpc < display_bpc) { | |
82820490 | 4036 | DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc); |
5a354204 JB |
4037 | display_bpc = lvds_bpc; |
4038 | } | |
4039 | continue; | |
4040 | } | |
4041 | ||
5a354204 JB |
4042 | /* Not one of the known troublemakers, check the EDID */ |
4043 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
4044 | head) { | |
6c2b7c12 | 4045 | if (connector->encoder != &intel_encoder->base) |
5a354204 JB |
4046 | continue; |
4047 | ||
62ac41a6 JB |
4048 | /* Don't use an invalid EDID bpc value */ |
4049 | if (connector->display_info.bpc && | |
4050 | connector->display_info.bpc < display_bpc) { | |
82820490 | 4051 | DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc); |
5a354204 JB |
4052 | display_bpc = connector->display_info.bpc; |
4053 | } | |
4054 | } | |
4055 | ||
2f4f649a JN |
4056 | if (intel_encoder->type == INTEL_OUTPUT_EDP) { |
4057 | /* Use VBT settings if we have an eDP panel */ | |
4058 | unsigned int edp_bpc = dev_priv->edp.bpp / 3; | |
4059 | ||
9a30a61f | 4060 | if (edp_bpc && edp_bpc < display_bpc) { |
2f4f649a JN |
4061 | DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc); |
4062 | display_bpc = edp_bpc; | |
4063 | } | |
4064 | continue; | |
4065 | } | |
4066 | ||
5a354204 JB |
4067 | /* |
4068 | * HDMI is either 12 or 8, so if the display lets 10bpc sneak | |
4069 | * through, clamp it down. (Note: >12bpc will be caught below.) | |
4070 | */ | |
4071 | if (intel_encoder->type == INTEL_OUTPUT_HDMI) { | |
4072 | if (display_bpc > 8 && display_bpc < 12) { | |
82820490 | 4073 | DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n"); |
5a354204 JB |
4074 | display_bpc = 12; |
4075 | } else { | |
82820490 | 4076 | DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n"); |
5a354204 JB |
4077 | display_bpc = 8; |
4078 | } | |
4079 | } | |
4080 | } | |
4081 | ||
3b5c78a3 AJ |
4082 | if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) { |
4083 | DRM_DEBUG_KMS("Dithering DP to 6bpc\n"); | |
4084 | display_bpc = 6; | |
4085 | } | |
4086 | ||
5a354204 JB |
4087 | /* |
4088 | * We could just drive the pipe at the highest bpc all the time and | |
4089 | * enable dithering as needed, but that costs bandwidth. So choose | |
4090 | * the minimum value that expresses the full color range of the fb but | |
4091 | * also stays within the max display bpc discovered above. | |
4092 | */ | |
4093 | ||
94352cf9 | 4094 | switch (fb->depth) { |
5a354204 JB |
4095 | case 8: |
4096 | bpc = 8; /* since we go through a colormap */ | |
4097 | break; | |
4098 | case 15: | |
4099 | case 16: | |
4100 | bpc = 6; /* min is 18bpp */ | |
4101 | break; | |
4102 | case 24: | |
578393cd | 4103 | bpc = 8; |
5a354204 JB |
4104 | break; |
4105 | case 30: | |
578393cd | 4106 | bpc = 10; |
5a354204 JB |
4107 | break; |
4108 | case 48: | |
578393cd | 4109 | bpc = 12; |
5a354204 JB |
4110 | break; |
4111 | default: | |
4112 | DRM_DEBUG("unsupported depth, assuming 24 bits\n"); | |
4113 | bpc = min((unsigned int)8, display_bpc); | |
4114 | break; | |
4115 | } | |
4116 | ||
578393cd KP |
4117 | display_bpc = min(display_bpc, bpc); |
4118 | ||
82820490 AJ |
4119 | DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n", |
4120 | bpc, display_bpc); | |
5a354204 | 4121 | |
578393cd | 4122 | *pipe_bpp = display_bpc * 3; |
5a354204 JB |
4123 | |
4124 | return display_bpc != bpc; | |
4125 | } | |
4126 | ||
a0c4da24 JB |
4127 | static int vlv_get_refclk(struct drm_crtc *crtc) |
4128 | { | |
4129 | struct drm_device *dev = crtc->dev; | |
4130 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4131 | int refclk = 27000; /* for DP & HDMI */ | |
4132 | ||
4133 | return 100000; /* only one validated so far */ | |
4134 | ||
4135 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) { | |
4136 | refclk = 96000; | |
4137 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
4138 | if (intel_panel_use_ssc(dev_priv)) | |
4139 | refclk = 100000; | |
4140 | else | |
4141 | refclk = 96000; | |
4142 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) { | |
4143 | refclk = 100000; | |
4144 | } | |
4145 | ||
4146 | return refclk; | |
4147 | } | |
4148 | ||
c65d77d8 JB |
4149 | static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors) |
4150 | { | |
4151 | struct drm_device *dev = crtc->dev; | |
4152 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4153 | int refclk; | |
4154 | ||
a0c4da24 JB |
4155 | if (IS_VALLEYVIEW(dev)) { |
4156 | refclk = vlv_get_refclk(crtc); | |
4157 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && | |
c65d77d8 JB |
4158 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) { |
4159 | refclk = dev_priv->lvds_ssc_freq * 1000; | |
4160 | DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n", | |
4161 | refclk / 1000); | |
4162 | } else if (!IS_GEN2(dev)) { | |
4163 | refclk = 96000; | |
4164 | } else { | |
4165 | refclk = 48000; | |
4166 | } | |
4167 | ||
4168 | return refclk; | |
4169 | } | |
4170 | ||
4171 | static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode, | |
4172 | intel_clock_t *clock) | |
4173 | { | |
4174 | /* SDVO TV has fixed PLL values depend on its clock range, | |
4175 | this mirrors vbios setting. */ | |
4176 | if (adjusted_mode->clock >= 100000 | |
4177 | && adjusted_mode->clock < 140500) { | |
4178 | clock->p1 = 2; | |
4179 | clock->p2 = 10; | |
4180 | clock->n = 3; | |
4181 | clock->m1 = 16; | |
4182 | clock->m2 = 8; | |
4183 | } else if (adjusted_mode->clock >= 140500 | |
4184 | && adjusted_mode->clock <= 200000) { | |
4185 | clock->p1 = 1; | |
4186 | clock->p2 = 10; | |
4187 | clock->n = 6; | |
4188 | clock->m1 = 12; | |
4189 | clock->m2 = 8; | |
4190 | } | |
4191 | } | |
4192 | ||
a7516a05 JB |
4193 | static void i9xx_update_pll_dividers(struct drm_crtc *crtc, |
4194 | intel_clock_t *clock, | |
4195 | intel_clock_t *reduced_clock) | |
4196 | { | |
4197 | struct drm_device *dev = crtc->dev; | |
4198 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4199 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4200 | int pipe = intel_crtc->pipe; | |
4201 | u32 fp, fp2 = 0; | |
4202 | ||
4203 | if (IS_PINEVIEW(dev)) { | |
4204 | fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2; | |
4205 | if (reduced_clock) | |
4206 | fp2 = (1 << reduced_clock->n) << 16 | | |
4207 | reduced_clock->m1 << 8 | reduced_clock->m2; | |
4208 | } else { | |
4209 | fp = clock->n << 16 | clock->m1 << 8 | clock->m2; | |
4210 | if (reduced_clock) | |
4211 | fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 | | |
4212 | reduced_clock->m2; | |
4213 | } | |
4214 | ||
4215 | I915_WRITE(FP0(pipe), fp); | |
4216 | ||
4217 | intel_crtc->lowfreq_avail = false; | |
4218 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && | |
4219 | reduced_clock && i915_powersave) { | |
4220 | I915_WRITE(FP1(pipe), fp2); | |
4221 | intel_crtc->lowfreq_avail = true; | |
4222 | } else { | |
4223 | I915_WRITE(FP1(pipe), fp); | |
4224 | } | |
4225 | } | |
4226 | ||
a0c4da24 JB |
4227 | static void vlv_update_pll(struct drm_crtc *crtc, |
4228 | struct drm_display_mode *mode, | |
4229 | struct drm_display_mode *adjusted_mode, | |
4230 | intel_clock_t *clock, intel_clock_t *reduced_clock, | |
2a8f64ca | 4231 | int num_connectors) |
a0c4da24 JB |
4232 | { |
4233 | struct drm_device *dev = crtc->dev; | |
4234 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4235 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4236 | int pipe = intel_crtc->pipe; | |
4237 | u32 dpll, mdiv, pdiv; | |
4238 | u32 bestn, bestm1, bestm2, bestp1, bestp2; | |
2a8f64ca VP |
4239 | bool is_sdvo; |
4240 | u32 temp; | |
a0c4da24 | 4241 | |
09153000 DV |
4242 | mutex_lock(&dev_priv->dpio_lock); |
4243 | ||
2a8f64ca VP |
4244 | is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) || |
4245 | intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI); | |
a0c4da24 | 4246 | |
2a8f64ca VP |
4247 | dpll = DPLL_VGA_MODE_DIS; |
4248 | dpll |= DPLL_EXT_BUFFER_ENABLE_VLV; | |
4249 | dpll |= DPLL_REFA_CLK_ENABLE_VLV; | |
4250 | dpll |= DPLL_INTEGRATED_CLOCK_VLV; | |
4251 | ||
4252 | I915_WRITE(DPLL(pipe), dpll); | |
4253 | POSTING_READ(DPLL(pipe)); | |
a0c4da24 JB |
4254 | |
4255 | bestn = clock->n; | |
4256 | bestm1 = clock->m1; | |
4257 | bestm2 = clock->m2; | |
4258 | bestp1 = clock->p1; | |
4259 | bestp2 = clock->p2; | |
4260 | ||
2a8f64ca VP |
4261 | /* |
4262 | * In Valleyview PLL and program lane counter registers are exposed | |
4263 | * through DPIO interface | |
4264 | */ | |
a0c4da24 JB |
4265 | mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK)); |
4266 | mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT)); | |
4267 | mdiv |= ((bestn << DPIO_N_SHIFT)); | |
4268 | mdiv |= (1 << DPIO_POST_DIV_SHIFT); | |
4269 | mdiv |= (1 << DPIO_K_SHIFT); | |
4270 | mdiv |= DPIO_ENABLE_CALIBRATION; | |
4271 | intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv); | |
4272 | ||
4273 | intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000); | |
4274 | ||
2a8f64ca | 4275 | pdiv = (1 << DPIO_REFSEL_OVERRIDE) | (5 << DPIO_PLL_MODESEL_SHIFT) | |
a0c4da24 | 4276 | (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) | |
2a8f64ca VP |
4277 | (7 << DPIO_PLL_REFCLK_SEL_SHIFT) | (8 << DPIO_DRIVER_CTL_SHIFT) | |
4278 | (5 << DPIO_CLK_BIAS_CTL_SHIFT); | |
a0c4da24 JB |
4279 | intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv); |
4280 | ||
2a8f64ca | 4281 | intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x005f003b); |
a0c4da24 JB |
4282 | |
4283 | dpll |= DPLL_VCO_ENABLE; | |
4284 | I915_WRITE(DPLL(pipe), dpll); | |
4285 | POSTING_READ(DPLL(pipe)); | |
4286 | if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) | |
4287 | DRM_ERROR("DPLL %d failed to lock\n", pipe); | |
4288 | ||
2a8f64ca VP |
4289 | intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x620); |
4290 | ||
4291 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) | |
4292 | intel_dp_set_m_n(crtc, mode, adjusted_mode); | |
4293 | ||
4294 | I915_WRITE(DPLL(pipe), dpll); | |
4295 | ||
4296 | /* Wait for the clocks to stabilize. */ | |
4297 | POSTING_READ(DPLL(pipe)); | |
4298 | udelay(150); | |
a0c4da24 | 4299 | |
2a8f64ca VP |
4300 | temp = 0; |
4301 | if (is_sdvo) { | |
4302 | temp = intel_mode_get_pixel_multiplier(adjusted_mode); | |
a0c4da24 JB |
4303 | if (temp > 1) |
4304 | temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
4305 | else | |
4306 | temp = 0; | |
a0c4da24 | 4307 | } |
2a8f64ca VP |
4308 | I915_WRITE(DPLL_MD(pipe), temp); |
4309 | POSTING_READ(DPLL_MD(pipe)); | |
a0c4da24 | 4310 | |
2a8f64ca VP |
4311 | /* Now program lane control registers */ |
4312 | if(intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) | |
4313 | || intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) | |
4314 | { | |
4315 | temp = 0x1000C4; | |
4316 | if(pipe == 1) | |
4317 | temp |= (1 << 21); | |
4318 | intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL1, temp); | |
4319 | } | |
4320 | if(intel_pipe_has_type(crtc,INTEL_OUTPUT_EDP)) | |
4321 | { | |
4322 | temp = 0x1000C4; | |
4323 | if(pipe == 1) | |
4324 | temp |= (1 << 21); | |
4325 | intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL2, temp); | |
4326 | } | |
09153000 DV |
4327 | |
4328 | mutex_unlock(&dev_priv->dpio_lock); | |
a0c4da24 JB |
4329 | } |
4330 | ||
eb1cbe48 DV |
4331 | static void i9xx_update_pll(struct drm_crtc *crtc, |
4332 | struct drm_display_mode *mode, | |
4333 | struct drm_display_mode *adjusted_mode, | |
4334 | intel_clock_t *clock, intel_clock_t *reduced_clock, | |
4335 | int num_connectors) | |
4336 | { | |
4337 | struct drm_device *dev = crtc->dev; | |
4338 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4339 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
dafd226c | 4340 | struct intel_encoder *encoder; |
eb1cbe48 DV |
4341 | int pipe = intel_crtc->pipe; |
4342 | u32 dpll; | |
4343 | bool is_sdvo; | |
4344 | ||
2a8f64ca VP |
4345 | i9xx_update_pll_dividers(crtc, clock, reduced_clock); |
4346 | ||
eb1cbe48 DV |
4347 | is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) || |
4348 | intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI); | |
4349 | ||
4350 | dpll = DPLL_VGA_MODE_DIS; | |
4351 | ||
4352 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) | |
4353 | dpll |= DPLLB_MODE_LVDS; | |
4354 | else | |
4355 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
4356 | if (is_sdvo) { | |
4357 | int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode); | |
4358 | if (pixel_multiplier > 1) { | |
4359 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) | |
4360 | dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES; | |
4361 | } | |
4362 | dpll |= DPLL_DVO_HIGH_SPEED; | |
4363 | } | |
4364 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) | |
4365 | dpll |= DPLL_DVO_HIGH_SPEED; | |
4366 | ||
4367 | /* compute bitmask from p1 value */ | |
4368 | if (IS_PINEVIEW(dev)) | |
4369 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; | |
4370 | else { | |
4371 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
4372 | if (IS_G4X(dev) && reduced_clock) | |
4373 | dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; | |
4374 | } | |
4375 | switch (clock->p2) { | |
4376 | case 5: | |
4377 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
4378 | break; | |
4379 | case 7: | |
4380 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
4381 | break; | |
4382 | case 10: | |
4383 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
4384 | break; | |
4385 | case 14: | |
4386 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
4387 | break; | |
4388 | } | |
4389 | if (INTEL_INFO(dev)->gen >= 4) | |
4390 | dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); | |
4391 | ||
4392 | if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT)) | |
4393 | dpll |= PLL_REF_INPUT_TVCLKINBC; | |
4394 | else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT)) | |
4395 | /* XXX: just matching BIOS for now */ | |
4396 | /* dpll |= PLL_REF_INPUT_TVCLKINBC; */ | |
4397 | dpll |= 3; | |
4398 | else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && | |
4399 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) | |
4400 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; | |
4401 | else | |
4402 | dpll |= PLL_REF_INPUT_DREFCLK; | |
4403 | ||
4404 | dpll |= DPLL_VCO_ENABLE; | |
4405 | I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE); | |
4406 | POSTING_READ(DPLL(pipe)); | |
4407 | udelay(150); | |
4408 | ||
dafd226c DV |
4409 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4410 | if (encoder->pre_pll_enable) | |
4411 | encoder->pre_pll_enable(encoder); | |
eb1cbe48 DV |
4412 | |
4413 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) | |
4414 | intel_dp_set_m_n(crtc, mode, adjusted_mode); | |
4415 | ||
4416 | I915_WRITE(DPLL(pipe), dpll); | |
4417 | ||
4418 | /* Wait for the clocks to stabilize. */ | |
4419 | POSTING_READ(DPLL(pipe)); | |
4420 | udelay(150); | |
4421 | ||
4422 | if (INTEL_INFO(dev)->gen >= 4) { | |
4423 | u32 temp = 0; | |
4424 | if (is_sdvo) { | |
4425 | temp = intel_mode_get_pixel_multiplier(adjusted_mode); | |
4426 | if (temp > 1) | |
4427 | temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
4428 | else | |
4429 | temp = 0; | |
4430 | } | |
4431 | I915_WRITE(DPLL_MD(pipe), temp); | |
4432 | } else { | |
4433 | /* The pixel multiplier can only be updated once the | |
4434 | * DPLL is enabled and the clocks are stable. | |
4435 | * | |
4436 | * So write it again. | |
4437 | */ | |
4438 | I915_WRITE(DPLL(pipe), dpll); | |
4439 | } | |
4440 | } | |
4441 | ||
4442 | static void i8xx_update_pll(struct drm_crtc *crtc, | |
4443 | struct drm_display_mode *adjusted_mode, | |
2a8f64ca | 4444 | intel_clock_t *clock, intel_clock_t *reduced_clock, |
eb1cbe48 DV |
4445 | int num_connectors) |
4446 | { | |
4447 | struct drm_device *dev = crtc->dev; | |
4448 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4449 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
dafd226c | 4450 | struct intel_encoder *encoder; |
eb1cbe48 DV |
4451 | int pipe = intel_crtc->pipe; |
4452 | u32 dpll; | |
4453 | ||
2a8f64ca VP |
4454 | i9xx_update_pll_dividers(crtc, clock, reduced_clock); |
4455 | ||
eb1cbe48 DV |
4456 | dpll = DPLL_VGA_MODE_DIS; |
4457 | ||
4458 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
4459 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
4460 | } else { | |
4461 | if (clock->p1 == 2) | |
4462 | dpll |= PLL_P1_DIVIDE_BY_TWO; | |
4463 | else | |
4464 | dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
4465 | if (clock->p2 == 4) | |
4466 | dpll |= PLL_P2_DIVIDE_BY_4; | |
4467 | } | |
4468 | ||
4469 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT)) | |
4470 | /* XXX: just matching BIOS for now */ | |
4471 | /* dpll |= PLL_REF_INPUT_TVCLKINBC; */ | |
4472 | dpll |= 3; | |
4473 | else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && | |
4474 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) | |
4475 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; | |
4476 | else | |
4477 | dpll |= PLL_REF_INPUT_DREFCLK; | |
4478 | ||
4479 | dpll |= DPLL_VCO_ENABLE; | |
4480 | I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE); | |
4481 | POSTING_READ(DPLL(pipe)); | |
4482 | udelay(150); | |
4483 | ||
dafd226c DV |
4484 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4485 | if (encoder->pre_pll_enable) | |
4486 | encoder->pre_pll_enable(encoder); | |
eb1cbe48 | 4487 | |
5b5896e4 DV |
4488 | I915_WRITE(DPLL(pipe), dpll); |
4489 | ||
4490 | /* Wait for the clocks to stabilize. */ | |
4491 | POSTING_READ(DPLL(pipe)); | |
4492 | udelay(150); | |
4493 | ||
eb1cbe48 DV |
4494 | /* The pixel multiplier can only be updated once the |
4495 | * DPLL is enabled and the clocks are stable. | |
4496 | * | |
4497 | * So write it again. | |
4498 | */ | |
4499 | I915_WRITE(DPLL(pipe), dpll); | |
4500 | } | |
4501 | ||
b0e77b9c PZ |
4502 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc, |
4503 | struct drm_display_mode *mode, | |
4504 | struct drm_display_mode *adjusted_mode) | |
4505 | { | |
4506 | struct drm_device *dev = intel_crtc->base.dev; | |
4507 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4508 | enum pipe pipe = intel_crtc->pipe; | |
fe2b8f9d | 4509 | enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder; |
b0e77b9c PZ |
4510 | uint32_t vsyncshift; |
4511 | ||
4512 | if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { | |
4513 | /* the chip adds 2 halflines automatically */ | |
4514 | adjusted_mode->crtc_vtotal -= 1; | |
4515 | adjusted_mode->crtc_vblank_end -= 1; | |
4516 | vsyncshift = adjusted_mode->crtc_hsync_start | |
4517 | - adjusted_mode->crtc_htotal / 2; | |
4518 | } else { | |
4519 | vsyncshift = 0; | |
4520 | } | |
4521 | ||
4522 | if (INTEL_INFO(dev)->gen > 3) | |
fe2b8f9d | 4523 | I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift); |
b0e77b9c | 4524 | |
fe2b8f9d | 4525 | I915_WRITE(HTOTAL(cpu_transcoder), |
b0e77b9c PZ |
4526 | (adjusted_mode->crtc_hdisplay - 1) | |
4527 | ((adjusted_mode->crtc_htotal - 1) << 16)); | |
fe2b8f9d | 4528 | I915_WRITE(HBLANK(cpu_transcoder), |
b0e77b9c PZ |
4529 | (adjusted_mode->crtc_hblank_start - 1) | |
4530 | ((adjusted_mode->crtc_hblank_end - 1) << 16)); | |
fe2b8f9d | 4531 | I915_WRITE(HSYNC(cpu_transcoder), |
b0e77b9c PZ |
4532 | (adjusted_mode->crtc_hsync_start - 1) | |
4533 | ((adjusted_mode->crtc_hsync_end - 1) << 16)); | |
4534 | ||
fe2b8f9d | 4535 | I915_WRITE(VTOTAL(cpu_transcoder), |
b0e77b9c PZ |
4536 | (adjusted_mode->crtc_vdisplay - 1) | |
4537 | ((adjusted_mode->crtc_vtotal - 1) << 16)); | |
fe2b8f9d | 4538 | I915_WRITE(VBLANK(cpu_transcoder), |
b0e77b9c PZ |
4539 | (adjusted_mode->crtc_vblank_start - 1) | |
4540 | ((adjusted_mode->crtc_vblank_end - 1) << 16)); | |
fe2b8f9d | 4541 | I915_WRITE(VSYNC(cpu_transcoder), |
b0e77b9c PZ |
4542 | (adjusted_mode->crtc_vsync_start - 1) | |
4543 | ((adjusted_mode->crtc_vsync_end - 1) << 16)); | |
4544 | ||
b5e508d4 PZ |
4545 | /* Workaround: when the EDP input selection is B, the VTOTAL_B must be |
4546 | * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is | |
4547 | * documented on the DDI_FUNC_CTL register description, EDP Input Select | |
4548 | * bits. */ | |
4549 | if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP && | |
4550 | (pipe == PIPE_B || pipe == PIPE_C)) | |
4551 | I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder))); | |
4552 | ||
b0e77b9c PZ |
4553 | /* pipesrc controls the size that is scaled from, which should |
4554 | * always be the user's requested size. | |
4555 | */ | |
4556 | I915_WRITE(PIPESRC(pipe), | |
4557 | ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1)); | |
4558 | } | |
4559 | ||
f564048e EA |
4560 | static int i9xx_crtc_mode_set(struct drm_crtc *crtc, |
4561 | struct drm_display_mode *mode, | |
4562 | struct drm_display_mode *adjusted_mode, | |
4563 | int x, int y, | |
94352cf9 | 4564 | struct drm_framebuffer *fb) |
79e53945 JB |
4565 | { |
4566 | struct drm_device *dev = crtc->dev; | |
4567 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4568 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4569 | int pipe = intel_crtc->pipe; | |
80824003 | 4570 | int plane = intel_crtc->plane; |
c751ce4f | 4571 | int refclk, num_connectors = 0; |
652c393a | 4572 | intel_clock_t clock, reduced_clock; |
b0e77b9c | 4573 | u32 dspcntr, pipeconf; |
eb1cbe48 DV |
4574 | bool ok, has_reduced_clock = false, is_sdvo = false; |
4575 | bool is_lvds = false, is_tv = false, is_dp = false; | |
5eddb70b | 4576 | struct intel_encoder *encoder; |
d4906093 | 4577 | const intel_limit_t *limit; |
5c3b82e2 | 4578 | int ret; |
79e53945 | 4579 | |
6c2b7c12 | 4580 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
5eddb70b | 4581 | switch (encoder->type) { |
79e53945 JB |
4582 | case INTEL_OUTPUT_LVDS: |
4583 | is_lvds = true; | |
4584 | break; | |
4585 | case INTEL_OUTPUT_SDVO: | |
7d57382e | 4586 | case INTEL_OUTPUT_HDMI: |
79e53945 | 4587 | is_sdvo = true; |
5eddb70b | 4588 | if (encoder->needs_tv_clock) |
e2f0ba97 | 4589 | is_tv = true; |
79e53945 | 4590 | break; |
79e53945 JB |
4591 | case INTEL_OUTPUT_TVOUT: |
4592 | is_tv = true; | |
4593 | break; | |
a4fc5ed6 KP |
4594 | case INTEL_OUTPUT_DISPLAYPORT: |
4595 | is_dp = true; | |
4596 | break; | |
79e53945 | 4597 | } |
43565a06 | 4598 | |
c751ce4f | 4599 | num_connectors++; |
79e53945 JB |
4600 | } |
4601 | ||
c65d77d8 | 4602 | refclk = i9xx_get_refclk(crtc, num_connectors); |
79e53945 | 4603 | |
d4906093 ML |
4604 | /* |
4605 | * Returns a set of divisors for the desired target clock with the given | |
4606 | * refclk, or FALSE. The returned values represent the clock equation: | |
4607 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
4608 | */ | |
1b894b59 | 4609 | limit = intel_limit(crtc, refclk); |
cec2f356 SP |
4610 | ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL, |
4611 | &clock); | |
79e53945 JB |
4612 | if (!ok) { |
4613 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
5c3b82e2 | 4614 | return -EINVAL; |
79e53945 JB |
4615 | } |
4616 | ||
cda4b7d3 | 4617 | /* Ensure that the cursor is valid for the new mode before changing... */ |
6b383a7f | 4618 | intel_crtc_update_cursor(crtc, true); |
cda4b7d3 | 4619 | |
ddc9003c | 4620 | if (is_lvds && dev_priv->lvds_downclock_avail) { |
cec2f356 SP |
4621 | /* |
4622 | * Ensure we match the reduced clock's P to the target clock. | |
4623 | * If the clocks don't match, we can't switch the display clock | |
4624 | * by using the FP0/FP1. In such case we will disable the LVDS | |
4625 | * downclock feature. | |
4626 | */ | |
ddc9003c | 4627 | has_reduced_clock = limit->find_pll(limit, crtc, |
5eddb70b CW |
4628 | dev_priv->lvds_downclock, |
4629 | refclk, | |
cec2f356 | 4630 | &clock, |
5eddb70b | 4631 | &reduced_clock); |
7026d4ac ZW |
4632 | } |
4633 | ||
c65d77d8 JB |
4634 | if (is_sdvo && is_tv) |
4635 | i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock); | |
7026d4ac | 4636 | |
eb1cbe48 | 4637 | if (IS_GEN2(dev)) |
2a8f64ca VP |
4638 | i8xx_update_pll(crtc, adjusted_mode, &clock, |
4639 | has_reduced_clock ? &reduced_clock : NULL, | |
4640 | num_connectors); | |
a0c4da24 | 4641 | else if (IS_VALLEYVIEW(dev)) |
2a8f64ca VP |
4642 | vlv_update_pll(crtc, mode, adjusted_mode, &clock, |
4643 | has_reduced_clock ? &reduced_clock : NULL, | |
4644 | num_connectors); | |
79e53945 | 4645 | else |
eb1cbe48 DV |
4646 | i9xx_update_pll(crtc, mode, adjusted_mode, &clock, |
4647 | has_reduced_clock ? &reduced_clock : NULL, | |
4648 | num_connectors); | |
79e53945 JB |
4649 | |
4650 | /* setup pipeconf */ | |
5eddb70b | 4651 | pipeconf = I915_READ(PIPECONF(pipe)); |
79e53945 JB |
4652 | |
4653 | /* Set up the display plane register */ | |
4654 | dspcntr = DISPPLANE_GAMMA_ENABLE; | |
4655 | ||
929c77fb EA |
4656 | if (pipe == 0) |
4657 | dspcntr &= ~DISPPLANE_SEL_PIPE_MASK; | |
4658 | else | |
4659 | dspcntr |= DISPPLANE_SEL_PIPE_B; | |
79e53945 | 4660 | |
a6c45cf0 | 4661 | if (pipe == 0 && INTEL_INFO(dev)->gen < 4) { |
79e53945 JB |
4662 | /* Enable pixel doubling when the dot clock is > 90% of the (display) |
4663 | * core speed. | |
4664 | * | |
4665 | * XXX: No double-wide on 915GM pipe B. Is that the only reason for the | |
4666 | * pipe == 0 check? | |
4667 | */ | |
e70236a8 JB |
4668 | if (mode->clock > |
4669 | dev_priv->display.get_display_clock_speed(dev) * 9 / 10) | |
5eddb70b | 4670 | pipeconf |= PIPECONF_DOUBLE_WIDE; |
79e53945 | 4671 | else |
5eddb70b | 4672 | pipeconf &= ~PIPECONF_DOUBLE_WIDE; |
79e53945 JB |
4673 | } |
4674 | ||
3b5c78a3 | 4675 | /* default to 8bpc */ |
dfd07d72 | 4676 | pipeconf &= ~(PIPECONF_BPC_MASK | PIPECONF_DITHER_EN); |
3b5c78a3 | 4677 | if (is_dp) { |
0c96c65b | 4678 | if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) { |
dfd07d72 | 4679 | pipeconf |= PIPECONF_6BPC | |
3b5c78a3 AJ |
4680 | PIPECONF_DITHER_EN | |
4681 | PIPECONF_DITHER_TYPE_SP; | |
4682 | } | |
4683 | } | |
4684 | ||
19c03924 GB |
4685 | if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) { |
4686 | if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) { | |
dfd07d72 | 4687 | pipeconf |= PIPECONF_6BPC | |
19c03924 GB |
4688 | PIPECONF_ENABLE | |
4689 | I965_PIPECONF_ACTIVE; | |
4690 | } | |
4691 | } | |
4692 | ||
28c97730 | 4693 | DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B'); |
79e53945 JB |
4694 | drm_mode_debug_printmodeline(mode); |
4695 | ||
a7516a05 JB |
4696 | if (HAS_PIPE_CXSR(dev)) { |
4697 | if (intel_crtc->lowfreq_avail) { | |
28c97730 | 4698 | DRM_DEBUG_KMS("enabling CxSR downclocking\n"); |
652c393a | 4699 | pipeconf |= PIPECONF_CXSR_DOWNCLOCK; |
a7516a05 | 4700 | } else { |
28c97730 | 4701 | DRM_DEBUG_KMS("disabling CxSR downclocking\n"); |
652c393a JB |
4702 | pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK; |
4703 | } | |
4704 | } | |
4705 | ||
617cf884 | 4706 | pipeconf &= ~PIPECONF_INTERLACE_MASK; |
dbb02575 | 4707 | if (!IS_GEN2(dev) && |
b0e77b9c | 4708 | adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) |
734b4157 | 4709 | pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; |
b0e77b9c | 4710 | else |
617cf884 | 4711 | pipeconf |= PIPECONF_PROGRESSIVE; |
734b4157 | 4712 | |
b0e77b9c | 4713 | intel_set_pipe_timings(intel_crtc, mode, adjusted_mode); |
5eddb70b CW |
4714 | |
4715 | /* pipesrc and dspsize control the size that is scaled from, | |
4716 | * which should always be the user's requested size. | |
79e53945 | 4717 | */ |
929c77fb EA |
4718 | I915_WRITE(DSPSIZE(plane), |
4719 | ((mode->vdisplay - 1) << 16) | | |
4720 | (mode->hdisplay - 1)); | |
4721 | I915_WRITE(DSPPOS(plane), 0); | |
2c07245f | 4722 | |
f564048e EA |
4723 | I915_WRITE(PIPECONF(pipe), pipeconf); |
4724 | POSTING_READ(PIPECONF(pipe)); | |
929c77fb | 4725 | intel_enable_pipe(dev_priv, pipe, false); |
f564048e EA |
4726 | |
4727 | intel_wait_for_vblank(dev, pipe); | |
4728 | ||
f564048e EA |
4729 | I915_WRITE(DSPCNTR(plane), dspcntr); |
4730 | POSTING_READ(DSPCNTR(plane)); | |
4731 | ||
94352cf9 | 4732 | ret = intel_pipe_set_base(crtc, x, y, fb); |
f564048e EA |
4733 | |
4734 | intel_update_watermarks(dev); | |
4735 | ||
f564048e EA |
4736 | return ret; |
4737 | } | |
4738 | ||
dde86e2d | 4739 | static void ironlake_init_pch_refclk(struct drm_device *dev) |
13d83a67 JB |
4740 | { |
4741 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4742 | struct drm_mode_config *mode_config = &dev->mode_config; | |
13d83a67 | 4743 | struct intel_encoder *encoder; |
13d83a67 JB |
4744 | u32 temp; |
4745 | bool has_lvds = false; | |
199e5d79 KP |
4746 | bool has_cpu_edp = false; |
4747 | bool has_pch_edp = false; | |
4748 | bool has_panel = false; | |
99eb6a01 KP |
4749 | bool has_ck505 = false; |
4750 | bool can_ssc = false; | |
13d83a67 JB |
4751 | |
4752 | /* We need to take the global config into account */ | |
199e5d79 KP |
4753 | list_for_each_entry(encoder, &mode_config->encoder_list, |
4754 | base.head) { | |
4755 | switch (encoder->type) { | |
4756 | case INTEL_OUTPUT_LVDS: | |
4757 | has_panel = true; | |
4758 | has_lvds = true; | |
4759 | break; | |
4760 | case INTEL_OUTPUT_EDP: | |
4761 | has_panel = true; | |
4762 | if (intel_encoder_is_pch_edp(&encoder->base)) | |
4763 | has_pch_edp = true; | |
4764 | else | |
4765 | has_cpu_edp = true; | |
4766 | break; | |
13d83a67 JB |
4767 | } |
4768 | } | |
4769 | ||
99eb6a01 KP |
4770 | if (HAS_PCH_IBX(dev)) { |
4771 | has_ck505 = dev_priv->display_clock_mode; | |
4772 | can_ssc = has_ck505; | |
4773 | } else { | |
4774 | has_ck505 = false; | |
4775 | can_ssc = true; | |
4776 | } | |
4777 | ||
4778 | DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n", | |
4779 | has_panel, has_lvds, has_pch_edp, has_cpu_edp, | |
4780 | has_ck505); | |
13d83a67 JB |
4781 | |
4782 | /* Ironlake: try to setup display ref clock before DPLL | |
4783 | * enabling. This is only under driver's control after | |
4784 | * PCH B stepping, previous chipset stepping should be | |
4785 | * ignoring this setting. | |
4786 | */ | |
4787 | temp = I915_READ(PCH_DREF_CONTROL); | |
4788 | /* Always enable nonspread source */ | |
4789 | temp &= ~DREF_NONSPREAD_SOURCE_MASK; | |
13d83a67 | 4790 | |
99eb6a01 KP |
4791 | if (has_ck505) |
4792 | temp |= DREF_NONSPREAD_CK505_ENABLE; | |
4793 | else | |
4794 | temp |= DREF_NONSPREAD_SOURCE_ENABLE; | |
13d83a67 | 4795 | |
199e5d79 KP |
4796 | if (has_panel) { |
4797 | temp &= ~DREF_SSC_SOURCE_MASK; | |
4798 | temp |= DREF_SSC_SOURCE_ENABLE; | |
13d83a67 | 4799 | |
199e5d79 | 4800 | /* SSC must be turned on before enabling the CPU output */ |
99eb6a01 | 4801 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 4802 | DRM_DEBUG_KMS("Using SSC on panel\n"); |
13d83a67 | 4803 | temp |= DREF_SSC1_ENABLE; |
e77166b5 DV |
4804 | } else |
4805 | temp &= ~DREF_SSC1_ENABLE; | |
199e5d79 KP |
4806 | |
4807 | /* Get SSC going before enabling the outputs */ | |
4808 | I915_WRITE(PCH_DREF_CONTROL, temp); | |
4809 | POSTING_READ(PCH_DREF_CONTROL); | |
4810 | udelay(200); | |
4811 | ||
13d83a67 JB |
4812 | temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
4813 | ||
4814 | /* Enable CPU source on CPU attached eDP */ | |
199e5d79 | 4815 | if (has_cpu_edp) { |
99eb6a01 | 4816 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 4817 | DRM_DEBUG_KMS("Using SSC on eDP\n"); |
13d83a67 | 4818 | temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; |
199e5d79 | 4819 | } |
13d83a67 JB |
4820 | else |
4821 | temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; | |
199e5d79 KP |
4822 | } else |
4823 | temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
4824 | ||
4825 | I915_WRITE(PCH_DREF_CONTROL, temp); | |
4826 | POSTING_READ(PCH_DREF_CONTROL); | |
4827 | udelay(200); | |
4828 | } else { | |
4829 | DRM_DEBUG_KMS("Disabling SSC entirely\n"); | |
4830 | ||
4831 | temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK; | |
4832 | ||
4833 | /* Turn off CPU output */ | |
4834 | temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
4835 | ||
4836 | I915_WRITE(PCH_DREF_CONTROL, temp); | |
4837 | POSTING_READ(PCH_DREF_CONTROL); | |
4838 | udelay(200); | |
4839 | ||
4840 | /* Turn off the SSC source */ | |
4841 | temp &= ~DREF_SSC_SOURCE_MASK; | |
4842 | temp |= DREF_SSC_SOURCE_DISABLE; | |
4843 | ||
4844 | /* Turn off SSC1 */ | |
4845 | temp &= ~ DREF_SSC1_ENABLE; | |
4846 | ||
13d83a67 JB |
4847 | I915_WRITE(PCH_DREF_CONTROL, temp); |
4848 | POSTING_READ(PCH_DREF_CONTROL); | |
4849 | udelay(200); | |
4850 | } | |
4851 | } | |
4852 | ||
dde86e2d PZ |
4853 | /* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */ |
4854 | static void lpt_init_pch_refclk(struct drm_device *dev) | |
4855 | { | |
4856 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4857 | struct drm_mode_config *mode_config = &dev->mode_config; | |
4858 | struct intel_encoder *encoder; | |
4859 | bool has_vga = false; | |
4860 | bool is_sdv = false; | |
4861 | u32 tmp; | |
4862 | ||
4863 | list_for_each_entry(encoder, &mode_config->encoder_list, base.head) { | |
4864 | switch (encoder->type) { | |
4865 | case INTEL_OUTPUT_ANALOG: | |
4866 | has_vga = true; | |
4867 | break; | |
4868 | } | |
4869 | } | |
4870 | ||
4871 | if (!has_vga) | |
4872 | return; | |
4873 | ||
4874 | /* XXX: Rip out SDV support once Haswell ships for real. */ | |
4875 | if (IS_HASWELL(dev) && (dev->pci_device & 0xFF00) == 0x0C00) | |
4876 | is_sdv = true; | |
4877 | ||
4878 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
4879 | tmp &= ~SBI_SSCCTL_DISABLE; | |
4880 | tmp |= SBI_SSCCTL_PATHALT; | |
4881 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
4882 | ||
4883 | udelay(24); | |
4884 | ||
4885 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
4886 | tmp &= ~SBI_SSCCTL_PATHALT; | |
4887 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
4888 | ||
4889 | if (!is_sdv) { | |
4890 | tmp = I915_READ(SOUTH_CHICKEN2); | |
4891 | tmp |= FDI_MPHY_IOSFSB_RESET_CTL; | |
4892 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
4893 | ||
4894 | if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) & | |
4895 | FDI_MPHY_IOSFSB_RESET_STATUS, 100)) | |
4896 | DRM_ERROR("FDI mPHY reset assert timeout\n"); | |
4897 | ||
4898 | tmp = I915_READ(SOUTH_CHICKEN2); | |
4899 | tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL; | |
4900 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
4901 | ||
4902 | if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) & | |
4903 | FDI_MPHY_IOSFSB_RESET_STATUS) == 0, | |
4904 | 100)) | |
4905 | DRM_ERROR("FDI mPHY reset de-assert timeout\n"); | |
4906 | } | |
4907 | ||
4908 | tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY); | |
4909 | tmp &= ~(0xFF << 24); | |
4910 | tmp |= (0x12 << 24); | |
4911 | intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY); | |
4912 | ||
4913 | if (!is_sdv) { | |
4914 | tmp = intel_sbi_read(dev_priv, 0x808C, SBI_MPHY); | |
4915 | tmp &= ~(0x3 << 6); | |
4916 | tmp |= (1 << 6) | (1 << 0); | |
4917 | intel_sbi_write(dev_priv, 0x808C, tmp, SBI_MPHY); | |
4918 | } | |
4919 | ||
4920 | if (is_sdv) { | |
4921 | tmp = intel_sbi_read(dev_priv, 0x800C, SBI_MPHY); | |
4922 | tmp |= 0x7FFF; | |
4923 | intel_sbi_write(dev_priv, 0x800C, tmp, SBI_MPHY); | |
4924 | } | |
4925 | ||
4926 | tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY); | |
4927 | tmp |= (1 << 11); | |
4928 | intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY); | |
4929 | ||
4930 | tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY); | |
4931 | tmp |= (1 << 11); | |
4932 | intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY); | |
4933 | ||
4934 | if (is_sdv) { | |
4935 | tmp = intel_sbi_read(dev_priv, 0x2038, SBI_MPHY); | |
4936 | tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16); | |
4937 | intel_sbi_write(dev_priv, 0x2038, tmp, SBI_MPHY); | |
4938 | ||
4939 | tmp = intel_sbi_read(dev_priv, 0x2138, SBI_MPHY); | |
4940 | tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16); | |
4941 | intel_sbi_write(dev_priv, 0x2138, tmp, SBI_MPHY); | |
4942 | ||
4943 | tmp = intel_sbi_read(dev_priv, 0x203C, SBI_MPHY); | |
4944 | tmp |= (0x3F << 8); | |
4945 | intel_sbi_write(dev_priv, 0x203C, tmp, SBI_MPHY); | |
4946 | ||
4947 | tmp = intel_sbi_read(dev_priv, 0x213C, SBI_MPHY); | |
4948 | tmp |= (0x3F << 8); | |
4949 | intel_sbi_write(dev_priv, 0x213C, tmp, SBI_MPHY); | |
4950 | } | |
4951 | ||
4952 | tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY); | |
4953 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
4954 | intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY); | |
4955 | ||
4956 | tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY); | |
4957 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
4958 | intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY); | |
4959 | ||
4960 | if (!is_sdv) { | |
4961 | tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY); | |
4962 | tmp &= ~(7 << 13); | |
4963 | tmp |= (5 << 13); | |
4964 | intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY); | |
4965 | ||
4966 | tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY); | |
4967 | tmp &= ~(7 << 13); | |
4968 | tmp |= (5 << 13); | |
4969 | intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY); | |
4970 | } | |
4971 | ||
4972 | tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY); | |
4973 | tmp &= ~0xFF; | |
4974 | tmp |= 0x1C; | |
4975 | intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY); | |
4976 | ||
4977 | tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY); | |
4978 | tmp &= ~0xFF; | |
4979 | tmp |= 0x1C; | |
4980 | intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY); | |
4981 | ||
4982 | tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY); | |
4983 | tmp &= ~(0xFF << 16); | |
4984 | tmp |= (0x1C << 16); | |
4985 | intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY); | |
4986 | ||
4987 | tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY); | |
4988 | tmp &= ~(0xFF << 16); | |
4989 | tmp |= (0x1C << 16); | |
4990 | intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY); | |
4991 | ||
4992 | if (!is_sdv) { | |
4993 | tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY); | |
4994 | tmp |= (1 << 27); | |
4995 | intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY); | |
4996 | ||
4997 | tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY); | |
4998 | tmp |= (1 << 27); | |
4999 | intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY); | |
5000 | ||
5001 | tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY); | |
5002 | tmp &= ~(0xF << 28); | |
5003 | tmp |= (4 << 28); | |
5004 | intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY); | |
5005 | ||
5006 | tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY); | |
5007 | tmp &= ~(0xF << 28); | |
5008 | tmp |= (4 << 28); | |
5009 | intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY); | |
5010 | } | |
5011 | ||
5012 | /* ULT uses SBI_GEN0, but ULT doesn't have VGA, so we don't care. */ | |
5013 | tmp = intel_sbi_read(dev_priv, SBI_DBUFF0, SBI_ICLK); | |
5014 | tmp |= SBI_DBUFF0_ENABLE; | |
5015 | intel_sbi_write(dev_priv, SBI_DBUFF0, tmp, SBI_ICLK); | |
5016 | } | |
5017 | ||
5018 | /* | |
5019 | * Initialize reference clocks when the driver loads | |
5020 | */ | |
5021 | void intel_init_pch_refclk(struct drm_device *dev) | |
5022 | { | |
5023 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
5024 | ironlake_init_pch_refclk(dev); | |
5025 | else if (HAS_PCH_LPT(dev)) | |
5026 | lpt_init_pch_refclk(dev); | |
5027 | } | |
5028 | ||
d9d444cb JB |
5029 | static int ironlake_get_refclk(struct drm_crtc *crtc) |
5030 | { | |
5031 | struct drm_device *dev = crtc->dev; | |
5032 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5033 | struct intel_encoder *encoder; | |
d9d444cb JB |
5034 | struct intel_encoder *edp_encoder = NULL; |
5035 | int num_connectors = 0; | |
5036 | bool is_lvds = false; | |
5037 | ||
6c2b7c12 | 5038 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
d9d444cb JB |
5039 | switch (encoder->type) { |
5040 | case INTEL_OUTPUT_LVDS: | |
5041 | is_lvds = true; | |
5042 | break; | |
5043 | case INTEL_OUTPUT_EDP: | |
5044 | edp_encoder = encoder; | |
5045 | break; | |
5046 | } | |
5047 | num_connectors++; | |
5048 | } | |
5049 | ||
5050 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) { | |
5051 | DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n", | |
5052 | dev_priv->lvds_ssc_freq); | |
5053 | return dev_priv->lvds_ssc_freq * 1000; | |
5054 | } | |
5055 | ||
5056 | return 120000; | |
5057 | } | |
5058 | ||
c8203565 | 5059 | static void ironlake_set_pipeconf(struct drm_crtc *crtc, |
f564048e | 5060 | struct drm_display_mode *adjusted_mode, |
c8203565 | 5061 | bool dither) |
79e53945 | 5062 | { |
c8203565 | 5063 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
79e53945 JB |
5064 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5065 | int pipe = intel_crtc->pipe; | |
c8203565 PZ |
5066 | uint32_t val; |
5067 | ||
5068 | val = I915_READ(PIPECONF(pipe)); | |
5069 | ||
dfd07d72 | 5070 | val &= ~PIPECONF_BPC_MASK; |
c8203565 PZ |
5071 | switch (intel_crtc->bpp) { |
5072 | case 18: | |
dfd07d72 | 5073 | val |= PIPECONF_6BPC; |
c8203565 PZ |
5074 | break; |
5075 | case 24: | |
dfd07d72 | 5076 | val |= PIPECONF_8BPC; |
c8203565 PZ |
5077 | break; |
5078 | case 30: | |
dfd07d72 | 5079 | val |= PIPECONF_10BPC; |
c8203565 PZ |
5080 | break; |
5081 | case 36: | |
dfd07d72 | 5082 | val |= PIPECONF_12BPC; |
c8203565 PZ |
5083 | break; |
5084 | default: | |
cc769b62 PZ |
5085 | /* Case prevented by intel_choose_pipe_bpp_dither. */ |
5086 | BUG(); | |
c8203565 PZ |
5087 | } |
5088 | ||
5089 | val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK); | |
5090 | if (dither) | |
5091 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); | |
5092 | ||
5093 | val &= ~PIPECONF_INTERLACE_MASK; | |
5094 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) | |
5095 | val |= PIPECONF_INTERLACED_ILK; | |
5096 | else | |
5097 | val |= PIPECONF_PROGRESSIVE; | |
5098 | ||
5099 | I915_WRITE(PIPECONF(pipe), val); | |
5100 | POSTING_READ(PIPECONF(pipe)); | |
5101 | } | |
5102 | ||
ee2b0b38 PZ |
5103 | static void haswell_set_pipeconf(struct drm_crtc *crtc, |
5104 | struct drm_display_mode *adjusted_mode, | |
5105 | bool dither) | |
5106 | { | |
5107 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; | |
5108 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
702e7a56 | 5109 | enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder; |
ee2b0b38 PZ |
5110 | uint32_t val; |
5111 | ||
702e7a56 | 5112 | val = I915_READ(PIPECONF(cpu_transcoder)); |
ee2b0b38 PZ |
5113 | |
5114 | val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK); | |
5115 | if (dither) | |
5116 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); | |
5117 | ||
5118 | val &= ~PIPECONF_INTERLACE_MASK_HSW; | |
5119 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) | |
5120 | val |= PIPECONF_INTERLACED_ILK; | |
5121 | else | |
5122 | val |= PIPECONF_PROGRESSIVE; | |
5123 | ||
702e7a56 PZ |
5124 | I915_WRITE(PIPECONF(cpu_transcoder), val); |
5125 | POSTING_READ(PIPECONF(cpu_transcoder)); | |
ee2b0b38 PZ |
5126 | } |
5127 | ||
6591c6e4 PZ |
5128 | static bool ironlake_compute_clocks(struct drm_crtc *crtc, |
5129 | struct drm_display_mode *adjusted_mode, | |
5130 | intel_clock_t *clock, | |
5131 | bool *has_reduced_clock, | |
5132 | intel_clock_t *reduced_clock) | |
5133 | { | |
5134 | struct drm_device *dev = crtc->dev; | |
5135 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5136 | struct intel_encoder *intel_encoder; | |
5137 | int refclk; | |
d4906093 | 5138 | const intel_limit_t *limit; |
6591c6e4 | 5139 | bool ret, is_sdvo = false, is_tv = false, is_lvds = false; |
79e53945 | 5140 | |
6591c6e4 PZ |
5141 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) { |
5142 | switch (intel_encoder->type) { | |
79e53945 JB |
5143 | case INTEL_OUTPUT_LVDS: |
5144 | is_lvds = true; | |
5145 | break; | |
5146 | case INTEL_OUTPUT_SDVO: | |
7d57382e | 5147 | case INTEL_OUTPUT_HDMI: |
79e53945 | 5148 | is_sdvo = true; |
6591c6e4 | 5149 | if (intel_encoder->needs_tv_clock) |
e2f0ba97 | 5150 | is_tv = true; |
79e53945 | 5151 | break; |
79e53945 JB |
5152 | case INTEL_OUTPUT_TVOUT: |
5153 | is_tv = true; | |
5154 | break; | |
79e53945 JB |
5155 | } |
5156 | } | |
5157 | ||
d9d444cb | 5158 | refclk = ironlake_get_refclk(crtc); |
79e53945 | 5159 | |
d4906093 ML |
5160 | /* |
5161 | * Returns a set of divisors for the desired target clock with the given | |
5162 | * refclk, or FALSE. The returned values represent the clock equation: | |
5163 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
5164 | */ | |
1b894b59 | 5165 | limit = intel_limit(crtc, refclk); |
6591c6e4 PZ |
5166 | ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL, |
5167 | clock); | |
5168 | if (!ret) | |
5169 | return false; | |
cda4b7d3 | 5170 | |
ddc9003c | 5171 | if (is_lvds && dev_priv->lvds_downclock_avail) { |
cec2f356 SP |
5172 | /* |
5173 | * Ensure we match the reduced clock's P to the target clock. | |
5174 | * If the clocks don't match, we can't switch the display clock | |
5175 | * by using the FP0/FP1. In such case we will disable the LVDS | |
5176 | * downclock feature. | |
5177 | */ | |
6591c6e4 PZ |
5178 | *has_reduced_clock = limit->find_pll(limit, crtc, |
5179 | dev_priv->lvds_downclock, | |
5180 | refclk, | |
5181 | clock, | |
5182 | reduced_clock); | |
652c393a | 5183 | } |
61e9653f DV |
5184 | |
5185 | if (is_sdvo && is_tv) | |
6591c6e4 PZ |
5186 | i9xx_adjust_sdvo_tv_clock(adjusted_mode, clock); |
5187 | ||
5188 | return true; | |
5189 | } | |
5190 | ||
01a415fd DV |
5191 | static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev) |
5192 | { | |
5193 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5194 | uint32_t temp; | |
5195 | ||
5196 | temp = I915_READ(SOUTH_CHICKEN1); | |
5197 | if (temp & FDI_BC_BIFURCATION_SELECT) | |
5198 | return; | |
5199 | ||
5200 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); | |
5201 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); | |
5202 | ||
5203 | temp |= FDI_BC_BIFURCATION_SELECT; | |
5204 | DRM_DEBUG_KMS("enabling fdi C rx\n"); | |
5205 | I915_WRITE(SOUTH_CHICKEN1, temp); | |
5206 | POSTING_READ(SOUTH_CHICKEN1); | |
5207 | } | |
5208 | ||
5209 | static bool ironlake_check_fdi_lanes(struct intel_crtc *intel_crtc) | |
5210 | { | |
5211 | struct drm_device *dev = intel_crtc->base.dev; | |
5212 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5213 | struct intel_crtc *pipe_B_crtc = | |
5214 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]); | |
5215 | ||
5216 | DRM_DEBUG_KMS("checking fdi config on pipe %i, lanes %i\n", | |
5217 | intel_crtc->pipe, intel_crtc->fdi_lanes); | |
5218 | if (intel_crtc->fdi_lanes > 4) { | |
5219 | DRM_DEBUG_KMS("invalid fdi lane config on pipe %i: %i lanes\n", | |
5220 | intel_crtc->pipe, intel_crtc->fdi_lanes); | |
5221 | /* Clamp lanes to avoid programming the hw with bogus values. */ | |
5222 | intel_crtc->fdi_lanes = 4; | |
5223 | ||
5224 | return false; | |
5225 | } | |
5226 | ||
5227 | if (dev_priv->num_pipe == 2) | |
5228 | return true; | |
5229 | ||
5230 | switch (intel_crtc->pipe) { | |
5231 | case PIPE_A: | |
5232 | return true; | |
5233 | case PIPE_B: | |
5234 | if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled && | |
5235 | intel_crtc->fdi_lanes > 2) { | |
5236 | DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n", | |
5237 | intel_crtc->pipe, intel_crtc->fdi_lanes); | |
5238 | /* Clamp lanes to avoid programming the hw with bogus values. */ | |
5239 | intel_crtc->fdi_lanes = 2; | |
5240 | ||
5241 | return false; | |
5242 | } | |
5243 | ||
5244 | if (intel_crtc->fdi_lanes > 2) | |
5245 | WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT); | |
5246 | else | |
5247 | cpt_enable_fdi_bc_bifurcation(dev); | |
5248 | ||
5249 | return true; | |
5250 | case PIPE_C: | |
5251 | if (!pipe_B_crtc->base.enabled || pipe_B_crtc->fdi_lanes <= 2) { | |
5252 | if (intel_crtc->fdi_lanes > 2) { | |
5253 | DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n", | |
5254 | intel_crtc->pipe, intel_crtc->fdi_lanes); | |
5255 | /* Clamp lanes to avoid programming the hw with bogus values. */ | |
5256 | intel_crtc->fdi_lanes = 2; | |
5257 | ||
5258 | return false; | |
5259 | } | |
5260 | } else { | |
5261 | DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n"); | |
5262 | return false; | |
5263 | } | |
5264 | ||
5265 | cpt_enable_fdi_bc_bifurcation(dev); | |
5266 | ||
5267 | return true; | |
5268 | default: | |
5269 | BUG(); | |
5270 | } | |
5271 | } | |
5272 | ||
d4b1931c PZ |
5273 | int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp) |
5274 | { | |
5275 | /* | |
5276 | * Account for spread spectrum to avoid | |
5277 | * oversubscribing the link. Max center spread | |
5278 | * is 2.5%; use 5% for safety's sake. | |
5279 | */ | |
5280 | u32 bps = target_clock * bpp * 21 / 20; | |
5281 | return bps / (link_bw * 8) + 1; | |
5282 | } | |
5283 | ||
f48d8f23 PZ |
5284 | static void ironlake_set_m_n(struct drm_crtc *crtc, |
5285 | struct drm_display_mode *mode, | |
5286 | struct drm_display_mode *adjusted_mode) | |
79e53945 JB |
5287 | { |
5288 | struct drm_device *dev = crtc->dev; | |
5289 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5290 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
afe2fcf5 | 5291 | enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder; |
f48d8f23 | 5292 | struct intel_encoder *intel_encoder, *edp_encoder = NULL; |
e69d0bc1 | 5293 | struct intel_link_m_n m_n = {0}; |
f48d8f23 PZ |
5294 | int target_clock, pixel_multiplier, lane, link_bw; |
5295 | bool is_dp = false, is_cpu_edp = false; | |
79e53945 | 5296 | |
f48d8f23 PZ |
5297 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) { |
5298 | switch (intel_encoder->type) { | |
a4fc5ed6 KP |
5299 | case INTEL_OUTPUT_DISPLAYPORT: |
5300 | is_dp = true; | |
5301 | break; | |
32f9d658 | 5302 | case INTEL_OUTPUT_EDP: |
e3aef172 | 5303 | is_dp = true; |
f48d8f23 | 5304 | if (!intel_encoder_is_pch_edp(&intel_encoder->base)) |
e3aef172 | 5305 | is_cpu_edp = true; |
f48d8f23 | 5306 | edp_encoder = intel_encoder; |
32f9d658 | 5307 | break; |
79e53945 | 5308 | } |
79e53945 | 5309 | } |
61e9653f | 5310 | |
2c07245f | 5311 | /* FDI link */ |
8febb297 EA |
5312 | pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode); |
5313 | lane = 0; | |
5314 | /* CPU eDP doesn't require FDI link, so just set DP M/N | |
5315 | according to current link config */ | |
e3aef172 | 5316 | if (is_cpu_edp) { |
e3aef172 | 5317 | intel_edp_link_config(edp_encoder, &lane, &link_bw); |
8febb297 | 5318 | } else { |
8febb297 EA |
5319 | /* FDI is a binary signal running at ~2.7GHz, encoding |
5320 | * each output octet as 10 bits. The actual frequency | |
5321 | * is stored as a divider into a 100MHz clock, and the | |
5322 | * mode pixel clock is stored in units of 1KHz. | |
5323 | * Hence the bw of each lane in terms of the mode signal | |
5324 | * is: | |
5325 | */ | |
5326 | link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10; | |
5327 | } | |
58a27471 | 5328 | |
94bf2ced DV |
5329 | /* [e]DP over FDI requires target mode clock instead of link clock. */ |
5330 | if (edp_encoder) | |
5331 | target_clock = intel_edp_target_clock(edp_encoder, mode); | |
5332 | else if (is_dp) | |
5333 | target_clock = mode->clock; | |
5334 | else | |
5335 | target_clock = adjusted_mode->clock; | |
5336 | ||
d4b1931c PZ |
5337 | if (!lane) |
5338 | lane = ironlake_get_lanes_required(target_clock, link_bw, | |
5339 | intel_crtc->bpp); | |
2c07245f | 5340 | |
8febb297 EA |
5341 | intel_crtc->fdi_lanes = lane; |
5342 | ||
5343 | if (pixel_multiplier > 1) | |
5344 | link_bw *= pixel_multiplier; | |
e69d0bc1 | 5345 | intel_link_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw, &m_n); |
8febb297 | 5346 | |
afe2fcf5 PZ |
5347 | I915_WRITE(PIPE_DATA_M1(cpu_transcoder), TU_SIZE(m_n.tu) | m_n.gmch_m); |
5348 | I915_WRITE(PIPE_DATA_N1(cpu_transcoder), m_n.gmch_n); | |
5349 | I915_WRITE(PIPE_LINK_M1(cpu_transcoder), m_n.link_m); | |
5350 | I915_WRITE(PIPE_LINK_N1(cpu_transcoder), m_n.link_n); | |
f48d8f23 PZ |
5351 | } |
5352 | ||
de13a2e3 PZ |
5353 | static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc, |
5354 | struct drm_display_mode *adjusted_mode, | |
5355 | intel_clock_t *clock, u32 fp) | |
79e53945 | 5356 | { |
de13a2e3 | 5357 | struct drm_crtc *crtc = &intel_crtc->base; |
79e53945 JB |
5358 | struct drm_device *dev = crtc->dev; |
5359 | struct drm_i915_private *dev_priv = dev->dev_private; | |
de13a2e3 PZ |
5360 | struct intel_encoder *intel_encoder; |
5361 | uint32_t dpll; | |
5362 | int factor, pixel_multiplier, num_connectors = 0; | |
5363 | bool is_lvds = false, is_sdvo = false, is_tv = false; | |
5364 | bool is_dp = false, is_cpu_edp = false; | |
79e53945 | 5365 | |
de13a2e3 PZ |
5366 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) { |
5367 | switch (intel_encoder->type) { | |
79e53945 JB |
5368 | case INTEL_OUTPUT_LVDS: |
5369 | is_lvds = true; | |
5370 | break; | |
5371 | case INTEL_OUTPUT_SDVO: | |
7d57382e | 5372 | case INTEL_OUTPUT_HDMI: |
79e53945 | 5373 | is_sdvo = true; |
de13a2e3 | 5374 | if (intel_encoder->needs_tv_clock) |
e2f0ba97 | 5375 | is_tv = true; |
79e53945 | 5376 | break; |
79e53945 JB |
5377 | case INTEL_OUTPUT_TVOUT: |
5378 | is_tv = true; | |
5379 | break; | |
a4fc5ed6 KP |
5380 | case INTEL_OUTPUT_DISPLAYPORT: |
5381 | is_dp = true; | |
5382 | break; | |
32f9d658 | 5383 | case INTEL_OUTPUT_EDP: |
e3aef172 | 5384 | is_dp = true; |
de13a2e3 | 5385 | if (!intel_encoder_is_pch_edp(&intel_encoder->base)) |
e3aef172 | 5386 | is_cpu_edp = true; |
32f9d658 | 5387 | break; |
79e53945 | 5388 | } |
43565a06 | 5389 | |
c751ce4f | 5390 | num_connectors++; |
79e53945 | 5391 | } |
79e53945 | 5392 | |
c1858123 | 5393 | /* Enable autotuning of the PLL clock (if permissible) */ |
8febb297 EA |
5394 | factor = 21; |
5395 | if (is_lvds) { | |
5396 | if ((intel_panel_use_ssc(dev_priv) && | |
5397 | dev_priv->lvds_ssc_freq == 100) || | |
1974cad0 | 5398 | intel_is_dual_link_lvds(dev)) |
8febb297 EA |
5399 | factor = 25; |
5400 | } else if (is_sdvo && is_tv) | |
5401 | factor = 20; | |
c1858123 | 5402 | |
de13a2e3 | 5403 | if (clock->m < factor * clock->n) |
8febb297 | 5404 | fp |= FP_CB_TUNE; |
2c07245f | 5405 | |
5eddb70b | 5406 | dpll = 0; |
2c07245f | 5407 | |
a07d6787 EA |
5408 | if (is_lvds) |
5409 | dpll |= DPLLB_MODE_LVDS; | |
5410 | else | |
5411 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
5412 | if (is_sdvo) { | |
de13a2e3 | 5413 | pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode); |
a07d6787 EA |
5414 | if (pixel_multiplier > 1) { |
5415 | dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; | |
79e53945 | 5416 | } |
a07d6787 EA |
5417 | dpll |= DPLL_DVO_HIGH_SPEED; |
5418 | } | |
e3aef172 | 5419 | if (is_dp && !is_cpu_edp) |
a07d6787 | 5420 | dpll |= DPLL_DVO_HIGH_SPEED; |
79e53945 | 5421 | |
a07d6787 | 5422 | /* compute bitmask from p1 value */ |
de13a2e3 | 5423 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
a07d6787 | 5424 | /* also FPA1 */ |
de13a2e3 | 5425 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
a07d6787 | 5426 | |
de13a2e3 | 5427 | switch (clock->p2) { |
a07d6787 EA |
5428 | case 5: |
5429 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
5430 | break; | |
5431 | case 7: | |
5432 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
5433 | break; | |
5434 | case 10: | |
5435 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
5436 | break; | |
5437 | case 14: | |
5438 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
5439 | break; | |
79e53945 JB |
5440 | } |
5441 | ||
43565a06 KH |
5442 | if (is_sdvo && is_tv) |
5443 | dpll |= PLL_REF_INPUT_TVCLKINBC; | |
5444 | else if (is_tv) | |
79e53945 | 5445 | /* XXX: just matching BIOS for now */ |
43565a06 | 5446 | /* dpll |= PLL_REF_INPUT_TVCLKINBC; */ |
79e53945 | 5447 | dpll |= 3; |
a7615030 | 5448 | else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
43565a06 | 5449 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
79e53945 JB |
5450 | else |
5451 | dpll |= PLL_REF_INPUT_DREFCLK; | |
5452 | ||
de13a2e3 PZ |
5453 | return dpll; |
5454 | } | |
5455 | ||
5456 | static int ironlake_crtc_mode_set(struct drm_crtc *crtc, | |
5457 | struct drm_display_mode *mode, | |
5458 | struct drm_display_mode *adjusted_mode, | |
5459 | int x, int y, | |
5460 | struct drm_framebuffer *fb) | |
5461 | { | |
5462 | struct drm_device *dev = crtc->dev; | |
5463 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5464 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5465 | int pipe = intel_crtc->pipe; | |
5466 | int plane = intel_crtc->plane; | |
5467 | int num_connectors = 0; | |
5468 | intel_clock_t clock, reduced_clock; | |
5469 | u32 dpll, fp = 0, fp2 = 0; | |
e2f12b07 PZ |
5470 | bool ok, has_reduced_clock = false; |
5471 | bool is_lvds = false, is_dp = false, is_cpu_edp = false; | |
de13a2e3 | 5472 | struct intel_encoder *encoder; |
de13a2e3 | 5473 | int ret; |
01a415fd | 5474 | bool dither, fdi_config_ok; |
de13a2e3 PZ |
5475 | |
5476 | for_each_encoder_on_crtc(dev, crtc, encoder) { | |
5477 | switch (encoder->type) { | |
5478 | case INTEL_OUTPUT_LVDS: | |
5479 | is_lvds = true; | |
5480 | break; | |
de13a2e3 PZ |
5481 | case INTEL_OUTPUT_DISPLAYPORT: |
5482 | is_dp = true; | |
5483 | break; | |
5484 | case INTEL_OUTPUT_EDP: | |
5485 | is_dp = true; | |
e2f12b07 | 5486 | if (!intel_encoder_is_pch_edp(&encoder->base)) |
de13a2e3 PZ |
5487 | is_cpu_edp = true; |
5488 | break; | |
5489 | } | |
5490 | ||
5491 | num_connectors++; | |
a07d6787 | 5492 | } |
79e53945 | 5493 | |
5dc5298b PZ |
5494 | WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)), |
5495 | "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev)); | |
a07d6787 | 5496 | |
de13a2e3 PZ |
5497 | ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock, |
5498 | &has_reduced_clock, &reduced_clock); | |
5499 | if (!ok) { | |
5500 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
5501 | return -EINVAL; | |
79e53945 JB |
5502 | } |
5503 | ||
de13a2e3 PZ |
5504 | /* Ensure that the cursor is valid for the new mode before changing... */ |
5505 | intel_crtc_update_cursor(crtc, true); | |
5506 | ||
5507 | /* determine panel color depth */ | |
c8241969 JN |
5508 | dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp, |
5509 | adjusted_mode); | |
de13a2e3 PZ |
5510 | if (is_lvds && dev_priv->lvds_dither) |
5511 | dither = true; | |
5512 | ||
5513 | fp = clock.n << 16 | clock.m1 << 8 | clock.m2; | |
5514 | if (has_reduced_clock) | |
5515 | fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 | | |
5516 | reduced_clock.m2; | |
5517 | ||
5518 | dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock, fp); | |
79e53945 | 5519 | |
f7cb34d4 | 5520 | DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe); |
79e53945 JB |
5521 | drm_mode_debug_printmodeline(mode); |
5522 | ||
5dc5298b PZ |
5523 | /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */ |
5524 | if (!is_cpu_edp) { | |
ee7b9f93 | 5525 | struct intel_pch_pll *pll; |
4b645f14 | 5526 | |
ee7b9f93 JB |
5527 | pll = intel_get_pch_pll(intel_crtc, dpll, fp); |
5528 | if (pll == NULL) { | |
5529 | DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n", | |
5530 | pipe); | |
4b645f14 JB |
5531 | return -EINVAL; |
5532 | } | |
ee7b9f93 JB |
5533 | } else |
5534 | intel_put_pch_pll(intel_crtc); | |
79e53945 | 5535 | |
2f0c2ad1 | 5536 | if (is_dp && !is_cpu_edp) |
a4fc5ed6 | 5537 | intel_dp_set_m_n(crtc, mode, adjusted_mode); |
79e53945 | 5538 | |
dafd226c DV |
5539 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5540 | if (encoder->pre_pll_enable) | |
5541 | encoder->pre_pll_enable(encoder); | |
79e53945 | 5542 | |
ee7b9f93 JB |
5543 | if (intel_crtc->pch_pll) { |
5544 | I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll); | |
5eddb70b | 5545 | |
32f9d658 | 5546 | /* Wait for the clocks to stabilize. */ |
ee7b9f93 | 5547 | POSTING_READ(intel_crtc->pch_pll->pll_reg); |
32f9d658 ZW |
5548 | udelay(150); |
5549 | ||
8febb297 EA |
5550 | /* The pixel multiplier can only be updated once the |
5551 | * DPLL is enabled and the clocks are stable. | |
5552 | * | |
5553 | * So write it again. | |
5554 | */ | |
ee7b9f93 | 5555 | I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll); |
79e53945 | 5556 | } |
79e53945 | 5557 | |
5eddb70b | 5558 | intel_crtc->lowfreq_avail = false; |
ee7b9f93 | 5559 | if (intel_crtc->pch_pll) { |
4b645f14 | 5560 | if (is_lvds && has_reduced_clock && i915_powersave) { |
ee7b9f93 | 5561 | I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2); |
4b645f14 | 5562 | intel_crtc->lowfreq_avail = true; |
4b645f14 | 5563 | } else { |
ee7b9f93 | 5564 | I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp); |
652c393a JB |
5565 | } |
5566 | } | |
5567 | ||
b0e77b9c | 5568 | intel_set_pipe_timings(intel_crtc, mode, adjusted_mode); |
5eddb70b | 5569 | |
01a415fd DV |
5570 | /* Note, this also computes intel_crtc->fdi_lanes which is used below in |
5571 | * ironlake_check_fdi_lanes. */ | |
f48d8f23 | 5572 | ironlake_set_m_n(crtc, mode, adjusted_mode); |
2c07245f | 5573 | |
01a415fd | 5574 | fdi_config_ok = ironlake_check_fdi_lanes(intel_crtc); |
2c07245f | 5575 | |
c8203565 | 5576 | ironlake_set_pipeconf(crtc, adjusted_mode, dither); |
79e53945 | 5577 | |
9d0498a2 | 5578 | intel_wait_for_vblank(dev, pipe); |
79e53945 | 5579 | |
a1f9e77e PZ |
5580 | /* Set up the display plane register */ |
5581 | I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE); | |
b24e7179 | 5582 | POSTING_READ(DSPCNTR(plane)); |
79e53945 | 5583 | |
94352cf9 | 5584 | ret = intel_pipe_set_base(crtc, x, y, fb); |
7662c8bd SL |
5585 | |
5586 | intel_update_watermarks(dev); | |
5587 | ||
1f8eeabf ED |
5588 | intel_update_linetime_watermarks(dev, pipe, adjusted_mode); |
5589 | ||
01a415fd | 5590 | return fdi_config_ok ? ret : -EINVAL; |
79e53945 JB |
5591 | } |
5592 | ||
09b4ddf9 PZ |
5593 | static int haswell_crtc_mode_set(struct drm_crtc *crtc, |
5594 | struct drm_display_mode *mode, | |
5595 | struct drm_display_mode *adjusted_mode, | |
5596 | int x, int y, | |
5597 | struct drm_framebuffer *fb) | |
5598 | { | |
5599 | struct drm_device *dev = crtc->dev; | |
5600 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5601 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5602 | int pipe = intel_crtc->pipe; | |
5603 | int plane = intel_crtc->plane; | |
5604 | int num_connectors = 0; | |
ed7ef439 | 5605 | bool is_dp = false, is_cpu_edp = false; |
09b4ddf9 | 5606 | struct intel_encoder *encoder; |
09b4ddf9 PZ |
5607 | int ret; |
5608 | bool dither; | |
5609 | ||
5610 | for_each_encoder_on_crtc(dev, crtc, encoder) { | |
5611 | switch (encoder->type) { | |
09b4ddf9 PZ |
5612 | case INTEL_OUTPUT_DISPLAYPORT: |
5613 | is_dp = true; | |
5614 | break; | |
5615 | case INTEL_OUTPUT_EDP: | |
5616 | is_dp = true; | |
5617 | if (!intel_encoder_is_pch_edp(&encoder->base)) | |
5618 | is_cpu_edp = true; | |
5619 | break; | |
5620 | } | |
5621 | ||
5622 | num_connectors++; | |
5623 | } | |
5624 | ||
a5c961d1 PZ |
5625 | if (is_cpu_edp) |
5626 | intel_crtc->cpu_transcoder = TRANSCODER_EDP; | |
5627 | else | |
5628 | intel_crtc->cpu_transcoder = pipe; | |
5629 | ||
5dc5298b PZ |
5630 | /* We are not sure yet this won't happen. */ |
5631 | WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n", | |
5632 | INTEL_PCH_TYPE(dev)); | |
5633 | ||
5634 | WARN(num_connectors != 1, "%d connectors attached to pipe %c\n", | |
5635 | num_connectors, pipe_name(pipe)); | |
5636 | ||
702e7a56 | 5637 | WARN_ON(I915_READ(PIPECONF(intel_crtc->cpu_transcoder)) & |
1ce42920 PZ |
5638 | (PIPECONF_ENABLE | I965_PIPECONF_ACTIVE)); |
5639 | ||
5640 | WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE); | |
5641 | ||
6441ab5f PZ |
5642 | if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock)) |
5643 | return -EINVAL; | |
5644 | ||
09b4ddf9 PZ |
5645 | /* Ensure that the cursor is valid for the new mode before changing... */ |
5646 | intel_crtc_update_cursor(crtc, true); | |
5647 | ||
5648 | /* determine panel color depth */ | |
c8241969 JN |
5649 | dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp, |
5650 | adjusted_mode); | |
09b4ddf9 | 5651 | |
09b4ddf9 PZ |
5652 | DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe); |
5653 | drm_mode_debug_printmodeline(mode); | |
5654 | ||
ed7ef439 | 5655 | if (is_dp && !is_cpu_edp) |
09b4ddf9 | 5656 | intel_dp_set_m_n(crtc, mode, adjusted_mode); |
09b4ddf9 PZ |
5657 | |
5658 | intel_crtc->lowfreq_avail = false; | |
09b4ddf9 PZ |
5659 | |
5660 | intel_set_pipe_timings(intel_crtc, mode, adjusted_mode); | |
5661 | ||
1eb8dfec PZ |
5662 | if (!is_dp || is_cpu_edp) |
5663 | ironlake_set_m_n(crtc, mode, adjusted_mode); | |
09b4ddf9 | 5664 | |
ee2b0b38 | 5665 | haswell_set_pipeconf(crtc, adjusted_mode, dither); |
09b4ddf9 | 5666 | |
09b4ddf9 PZ |
5667 | /* Set up the display plane register */ |
5668 | I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE); | |
5669 | POSTING_READ(DSPCNTR(plane)); | |
5670 | ||
5671 | ret = intel_pipe_set_base(crtc, x, y, fb); | |
5672 | ||
5673 | intel_update_watermarks(dev); | |
5674 | ||
5675 | intel_update_linetime_watermarks(dev, pipe, adjusted_mode); | |
5676 | ||
1f803ee5 | 5677 | return ret; |
79e53945 JB |
5678 | } |
5679 | ||
f564048e EA |
5680 | static int intel_crtc_mode_set(struct drm_crtc *crtc, |
5681 | struct drm_display_mode *mode, | |
5682 | struct drm_display_mode *adjusted_mode, | |
5683 | int x, int y, | |
94352cf9 | 5684 | struct drm_framebuffer *fb) |
f564048e EA |
5685 | { |
5686 | struct drm_device *dev = crtc->dev; | |
5687 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9256aa19 DV |
5688 | struct drm_encoder_helper_funcs *encoder_funcs; |
5689 | struct intel_encoder *encoder; | |
0b701d27 EA |
5690 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5691 | int pipe = intel_crtc->pipe; | |
f564048e EA |
5692 | int ret; |
5693 | ||
0b701d27 | 5694 | drm_vblank_pre_modeset(dev, pipe); |
7662c8bd | 5695 | |
f564048e | 5696 | ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode, |
94352cf9 | 5697 | x, y, fb); |
79e53945 | 5698 | drm_vblank_post_modeset(dev, pipe); |
5c3b82e2 | 5699 | |
9256aa19 DV |
5700 | if (ret != 0) |
5701 | return ret; | |
5702 | ||
5703 | for_each_encoder_on_crtc(dev, crtc, encoder) { | |
5704 | DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n", | |
5705 | encoder->base.base.id, | |
5706 | drm_get_encoder_name(&encoder->base), | |
5707 | mode->base.id, mode->name); | |
5708 | encoder_funcs = encoder->base.helper_private; | |
5709 | encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode); | |
5710 | } | |
5711 | ||
5712 | return 0; | |
79e53945 JB |
5713 | } |
5714 | ||
3a9627f4 WF |
5715 | static bool intel_eld_uptodate(struct drm_connector *connector, |
5716 | int reg_eldv, uint32_t bits_eldv, | |
5717 | int reg_elda, uint32_t bits_elda, | |
5718 | int reg_edid) | |
5719 | { | |
5720 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
5721 | uint8_t *eld = connector->eld; | |
5722 | uint32_t i; | |
5723 | ||
5724 | i = I915_READ(reg_eldv); | |
5725 | i &= bits_eldv; | |
5726 | ||
5727 | if (!eld[0]) | |
5728 | return !i; | |
5729 | ||
5730 | if (!i) | |
5731 | return false; | |
5732 | ||
5733 | i = I915_READ(reg_elda); | |
5734 | i &= ~bits_elda; | |
5735 | I915_WRITE(reg_elda, i); | |
5736 | ||
5737 | for (i = 0; i < eld[2]; i++) | |
5738 | if (I915_READ(reg_edid) != *((uint32_t *)eld + i)) | |
5739 | return false; | |
5740 | ||
5741 | return true; | |
5742 | } | |
5743 | ||
e0dac65e WF |
5744 | static void g4x_write_eld(struct drm_connector *connector, |
5745 | struct drm_crtc *crtc) | |
5746 | { | |
5747 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
5748 | uint8_t *eld = connector->eld; | |
5749 | uint32_t eldv; | |
5750 | uint32_t len; | |
5751 | uint32_t i; | |
5752 | ||
5753 | i = I915_READ(G4X_AUD_VID_DID); | |
5754 | ||
5755 | if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL) | |
5756 | eldv = G4X_ELDV_DEVCL_DEVBLC; | |
5757 | else | |
5758 | eldv = G4X_ELDV_DEVCTG; | |
5759 | ||
3a9627f4 WF |
5760 | if (intel_eld_uptodate(connector, |
5761 | G4X_AUD_CNTL_ST, eldv, | |
5762 | G4X_AUD_CNTL_ST, G4X_ELD_ADDR, | |
5763 | G4X_HDMIW_HDMIEDID)) | |
5764 | return; | |
5765 | ||
e0dac65e WF |
5766 | i = I915_READ(G4X_AUD_CNTL_ST); |
5767 | i &= ~(eldv | G4X_ELD_ADDR); | |
5768 | len = (i >> 9) & 0x1f; /* ELD buffer size */ | |
5769 | I915_WRITE(G4X_AUD_CNTL_ST, i); | |
5770 | ||
5771 | if (!eld[0]) | |
5772 | return; | |
5773 | ||
5774 | len = min_t(uint8_t, eld[2], len); | |
5775 | DRM_DEBUG_DRIVER("ELD size %d\n", len); | |
5776 | for (i = 0; i < len; i++) | |
5777 | I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i)); | |
5778 | ||
5779 | i = I915_READ(G4X_AUD_CNTL_ST); | |
5780 | i |= eldv; | |
5781 | I915_WRITE(G4X_AUD_CNTL_ST, i); | |
5782 | } | |
5783 | ||
83358c85 WX |
5784 | static void haswell_write_eld(struct drm_connector *connector, |
5785 | struct drm_crtc *crtc) | |
5786 | { | |
5787 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
5788 | uint8_t *eld = connector->eld; | |
5789 | struct drm_device *dev = crtc->dev; | |
5790 | uint32_t eldv; | |
5791 | uint32_t i; | |
5792 | int len; | |
5793 | int pipe = to_intel_crtc(crtc)->pipe; | |
5794 | int tmp; | |
5795 | ||
5796 | int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe); | |
5797 | int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe); | |
5798 | int aud_config = HSW_AUD_CFG(pipe); | |
5799 | int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD; | |
5800 | ||
5801 | ||
5802 | DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n"); | |
5803 | ||
5804 | /* Audio output enable */ | |
5805 | DRM_DEBUG_DRIVER("HDMI audio: enable codec\n"); | |
5806 | tmp = I915_READ(aud_cntrl_st2); | |
5807 | tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4)); | |
5808 | I915_WRITE(aud_cntrl_st2, tmp); | |
5809 | ||
5810 | /* Wait for 1 vertical blank */ | |
5811 | intel_wait_for_vblank(dev, pipe); | |
5812 | ||
5813 | /* Set ELD valid state */ | |
5814 | tmp = I915_READ(aud_cntrl_st2); | |
5815 | DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp); | |
5816 | tmp |= (AUDIO_ELD_VALID_A << (pipe * 4)); | |
5817 | I915_WRITE(aud_cntrl_st2, tmp); | |
5818 | tmp = I915_READ(aud_cntrl_st2); | |
5819 | DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp); | |
5820 | ||
5821 | /* Enable HDMI mode */ | |
5822 | tmp = I915_READ(aud_config); | |
5823 | DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp); | |
5824 | /* clear N_programing_enable and N_value_index */ | |
5825 | tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE); | |
5826 | I915_WRITE(aud_config, tmp); | |
5827 | ||
5828 | DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe)); | |
5829 | ||
5830 | eldv = AUDIO_ELD_VALID_A << (pipe * 4); | |
5831 | ||
5832 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) { | |
5833 | DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n"); | |
5834 | eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */ | |
5835 | I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */ | |
5836 | } else | |
5837 | I915_WRITE(aud_config, 0); | |
5838 | ||
5839 | if (intel_eld_uptodate(connector, | |
5840 | aud_cntrl_st2, eldv, | |
5841 | aud_cntl_st, IBX_ELD_ADDRESS, | |
5842 | hdmiw_hdmiedid)) | |
5843 | return; | |
5844 | ||
5845 | i = I915_READ(aud_cntrl_st2); | |
5846 | i &= ~eldv; | |
5847 | I915_WRITE(aud_cntrl_st2, i); | |
5848 | ||
5849 | if (!eld[0]) | |
5850 | return; | |
5851 | ||
5852 | i = I915_READ(aud_cntl_st); | |
5853 | i &= ~IBX_ELD_ADDRESS; | |
5854 | I915_WRITE(aud_cntl_st, i); | |
5855 | i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */ | |
5856 | DRM_DEBUG_DRIVER("port num:%d\n", i); | |
5857 | ||
5858 | len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */ | |
5859 | DRM_DEBUG_DRIVER("ELD size %d\n", len); | |
5860 | for (i = 0; i < len; i++) | |
5861 | I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i)); | |
5862 | ||
5863 | i = I915_READ(aud_cntrl_st2); | |
5864 | i |= eldv; | |
5865 | I915_WRITE(aud_cntrl_st2, i); | |
5866 | ||
5867 | } | |
5868 | ||
e0dac65e WF |
5869 | static void ironlake_write_eld(struct drm_connector *connector, |
5870 | struct drm_crtc *crtc) | |
5871 | { | |
5872 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
5873 | uint8_t *eld = connector->eld; | |
5874 | uint32_t eldv; | |
5875 | uint32_t i; | |
5876 | int len; | |
5877 | int hdmiw_hdmiedid; | |
b6daa025 | 5878 | int aud_config; |
e0dac65e WF |
5879 | int aud_cntl_st; |
5880 | int aud_cntrl_st2; | |
9b138a83 | 5881 | int pipe = to_intel_crtc(crtc)->pipe; |
e0dac65e | 5882 | |
b3f33cbf | 5883 | if (HAS_PCH_IBX(connector->dev)) { |
9b138a83 WX |
5884 | hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe); |
5885 | aud_config = IBX_AUD_CFG(pipe); | |
5886 | aud_cntl_st = IBX_AUD_CNTL_ST(pipe); | |
1202b4c6 | 5887 | aud_cntrl_st2 = IBX_AUD_CNTL_ST2; |
e0dac65e | 5888 | } else { |
9b138a83 WX |
5889 | hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe); |
5890 | aud_config = CPT_AUD_CFG(pipe); | |
5891 | aud_cntl_st = CPT_AUD_CNTL_ST(pipe); | |
1202b4c6 | 5892 | aud_cntrl_st2 = CPT_AUD_CNTRL_ST2; |
e0dac65e WF |
5893 | } |
5894 | ||
9b138a83 | 5895 | DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe)); |
e0dac65e WF |
5896 | |
5897 | i = I915_READ(aud_cntl_st); | |
9b138a83 | 5898 | i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */ |
e0dac65e WF |
5899 | if (!i) { |
5900 | DRM_DEBUG_DRIVER("Audio directed to unknown port\n"); | |
5901 | /* operate blindly on all ports */ | |
1202b4c6 WF |
5902 | eldv = IBX_ELD_VALIDB; |
5903 | eldv |= IBX_ELD_VALIDB << 4; | |
5904 | eldv |= IBX_ELD_VALIDB << 8; | |
e0dac65e WF |
5905 | } else { |
5906 | DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i); | |
1202b4c6 | 5907 | eldv = IBX_ELD_VALIDB << ((i - 1) * 4); |
e0dac65e WF |
5908 | } |
5909 | ||
3a9627f4 WF |
5910 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) { |
5911 | DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n"); | |
5912 | eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */ | |
b6daa025 WF |
5913 | I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */ |
5914 | } else | |
5915 | I915_WRITE(aud_config, 0); | |
e0dac65e | 5916 | |
3a9627f4 WF |
5917 | if (intel_eld_uptodate(connector, |
5918 | aud_cntrl_st2, eldv, | |
5919 | aud_cntl_st, IBX_ELD_ADDRESS, | |
5920 | hdmiw_hdmiedid)) | |
5921 | return; | |
5922 | ||
e0dac65e WF |
5923 | i = I915_READ(aud_cntrl_st2); |
5924 | i &= ~eldv; | |
5925 | I915_WRITE(aud_cntrl_st2, i); | |
5926 | ||
5927 | if (!eld[0]) | |
5928 | return; | |
5929 | ||
e0dac65e | 5930 | i = I915_READ(aud_cntl_st); |
1202b4c6 | 5931 | i &= ~IBX_ELD_ADDRESS; |
e0dac65e WF |
5932 | I915_WRITE(aud_cntl_st, i); |
5933 | ||
5934 | len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */ | |
5935 | DRM_DEBUG_DRIVER("ELD size %d\n", len); | |
5936 | for (i = 0; i < len; i++) | |
5937 | I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i)); | |
5938 | ||
5939 | i = I915_READ(aud_cntrl_st2); | |
5940 | i |= eldv; | |
5941 | I915_WRITE(aud_cntrl_st2, i); | |
5942 | } | |
5943 | ||
5944 | void intel_write_eld(struct drm_encoder *encoder, | |
5945 | struct drm_display_mode *mode) | |
5946 | { | |
5947 | struct drm_crtc *crtc = encoder->crtc; | |
5948 | struct drm_connector *connector; | |
5949 | struct drm_device *dev = encoder->dev; | |
5950 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5951 | ||
5952 | connector = drm_select_eld(encoder, mode); | |
5953 | if (!connector) | |
5954 | return; | |
5955 | ||
5956 | DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", | |
5957 | connector->base.id, | |
5958 | drm_get_connector_name(connector), | |
5959 | connector->encoder->base.id, | |
5960 | drm_get_encoder_name(connector->encoder)); | |
5961 | ||
5962 | connector->eld[6] = drm_av_sync_delay(connector, mode) / 2; | |
5963 | ||
5964 | if (dev_priv->display.write_eld) | |
5965 | dev_priv->display.write_eld(connector, crtc); | |
5966 | } | |
5967 | ||
79e53945 JB |
5968 | /** Loads the palette/gamma unit for the CRTC with the prepared values */ |
5969 | void intel_crtc_load_lut(struct drm_crtc *crtc) | |
5970 | { | |
5971 | struct drm_device *dev = crtc->dev; | |
5972 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5973 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
9db4a9c7 | 5974 | int palreg = PALETTE(intel_crtc->pipe); |
79e53945 JB |
5975 | int i; |
5976 | ||
5977 | /* The clocks have to be on to load the palette. */ | |
aed3f09d | 5978 | if (!crtc->enabled || !intel_crtc->active) |
79e53945 JB |
5979 | return; |
5980 | ||
f2b115e6 | 5981 | /* use legacy palette for Ironlake */ |
bad720ff | 5982 | if (HAS_PCH_SPLIT(dev)) |
9db4a9c7 | 5983 | palreg = LGC_PALETTE(intel_crtc->pipe); |
2c07245f | 5984 | |
79e53945 JB |
5985 | for (i = 0; i < 256; i++) { |
5986 | I915_WRITE(palreg + 4 * i, | |
5987 | (intel_crtc->lut_r[i] << 16) | | |
5988 | (intel_crtc->lut_g[i] << 8) | | |
5989 | intel_crtc->lut_b[i]); | |
5990 | } | |
5991 | } | |
5992 | ||
560b85bb CW |
5993 | static void i845_update_cursor(struct drm_crtc *crtc, u32 base) |
5994 | { | |
5995 | struct drm_device *dev = crtc->dev; | |
5996 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5997 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5998 | bool visible = base != 0; | |
5999 | u32 cntl; | |
6000 | ||
6001 | if (intel_crtc->cursor_visible == visible) | |
6002 | return; | |
6003 | ||
9db4a9c7 | 6004 | cntl = I915_READ(_CURACNTR); |
560b85bb CW |
6005 | if (visible) { |
6006 | /* On these chipsets we can only modify the base whilst | |
6007 | * the cursor is disabled. | |
6008 | */ | |
9db4a9c7 | 6009 | I915_WRITE(_CURABASE, base); |
560b85bb CW |
6010 | |
6011 | cntl &= ~(CURSOR_FORMAT_MASK); | |
6012 | /* XXX width must be 64, stride 256 => 0x00 << 28 */ | |
6013 | cntl |= CURSOR_ENABLE | | |
6014 | CURSOR_GAMMA_ENABLE | | |
6015 | CURSOR_FORMAT_ARGB; | |
6016 | } else | |
6017 | cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE); | |
9db4a9c7 | 6018 | I915_WRITE(_CURACNTR, cntl); |
560b85bb CW |
6019 | |
6020 | intel_crtc->cursor_visible = visible; | |
6021 | } | |
6022 | ||
6023 | static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base) | |
6024 | { | |
6025 | struct drm_device *dev = crtc->dev; | |
6026 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6027 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6028 | int pipe = intel_crtc->pipe; | |
6029 | bool visible = base != 0; | |
6030 | ||
6031 | if (intel_crtc->cursor_visible != visible) { | |
548f245b | 6032 | uint32_t cntl = I915_READ(CURCNTR(pipe)); |
560b85bb CW |
6033 | if (base) { |
6034 | cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT); | |
6035 | cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE; | |
6036 | cntl |= pipe << 28; /* Connect to correct pipe */ | |
6037 | } else { | |
6038 | cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE); | |
6039 | cntl |= CURSOR_MODE_DISABLE; | |
6040 | } | |
9db4a9c7 | 6041 | I915_WRITE(CURCNTR(pipe), cntl); |
560b85bb CW |
6042 | |
6043 | intel_crtc->cursor_visible = visible; | |
6044 | } | |
6045 | /* and commit changes on next vblank */ | |
9db4a9c7 | 6046 | I915_WRITE(CURBASE(pipe), base); |
560b85bb CW |
6047 | } |
6048 | ||
65a21cd6 JB |
6049 | static void ivb_update_cursor(struct drm_crtc *crtc, u32 base) |
6050 | { | |
6051 | struct drm_device *dev = crtc->dev; | |
6052 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6053 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6054 | int pipe = intel_crtc->pipe; | |
6055 | bool visible = base != 0; | |
6056 | ||
6057 | if (intel_crtc->cursor_visible != visible) { | |
6058 | uint32_t cntl = I915_READ(CURCNTR_IVB(pipe)); | |
6059 | if (base) { | |
6060 | cntl &= ~CURSOR_MODE; | |
6061 | cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE; | |
6062 | } else { | |
6063 | cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE); | |
6064 | cntl |= CURSOR_MODE_DISABLE; | |
6065 | } | |
6066 | I915_WRITE(CURCNTR_IVB(pipe), cntl); | |
6067 | ||
6068 | intel_crtc->cursor_visible = visible; | |
6069 | } | |
6070 | /* and commit changes on next vblank */ | |
6071 | I915_WRITE(CURBASE_IVB(pipe), base); | |
6072 | } | |
6073 | ||
cda4b7d3 | 6074 | /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */ |
6b383a7f CW |
6075 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, |
6076 | bool on) | |
cda4b7d3 CW |
6077 | { |
6078 | struct drm_device *dev = crtc->dev; | |
6079 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6080 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6081 | int pipe = intel_crtc->pipe; | |
6082 | int x = intel_crtc->cursor_x; | |
6083 | int y = intel_crtc->cursor_y; | |
560b85bb | 6084 | u32 base, pos; |
cda4b7d3 CW |
6085 | bool visible; |
6086 | ||
6087 | pos = 0; | |
6088 | ||
6b383a7f | 6089 | if (on && crtc->enabled && crtc->fb) { |
cda4b7d3 CW |
6090 | base = intel_crtc->cursor_addr; |
6091 | if (x > (int) crtc->fb->width) | |
6092 | base = 0; | |
6093 | ||
6094 | if (y > (int) crtc->fb->height) | |
6095 | base = 0; | |
6096 | } else | |
6097 | base = 0; | |
6098 | ||
6099 | if (x < 0) { | |
6100 | if (x + intel_crtc->cursor_width < 0) | |
6101 | base = 0; | |
6102 | ||
6103 | pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; | |
6104 | x = -x; | |
6105 | } | |
6106 | pos |= x << CURSOR_X_SHIFT; | |
6107 | ||
6108 | if (y < 0) { | |
6109 | if (y + intel_crtc->cursor_height < 0) | |
6110 | base = 0; | |
6111 | ||
6112 | pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT; | |
6113 | y = -y; | |
6114 | } | |
6115 | pos |= y << CURSOR_Y_SHIFT; | |
6116 | ||
6117 | visible = base != 0; | |
560b85bb | 6118 | if (!visible && !intel_crtc->cursor_visible) |
cda4b7d3 CW |
6119 | return; |
6120 | ||
0cd83aa9 | 6121 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) { |
65a21cd6 JB |
6122 | I915_WRITE(CURPOS_IVB(pipe), pos); |
6123 | ivb_update_cursor(crtc, base); | |
6124 | } else { | |
6125 | I915_WRITE(CURPOS(pipe), pos); | |
6126 | if (IS_845G(dev) || IS_I865G(dev)) | |
6127 | i845_update_cursor(crtc, base); | |
6128 | else | |
6129 | i9xx_update_cursor(crtc, base); | |
6130 | } | |
cda4b7d3 CW |
6131 | } |
6132 | ||
79e53945 | 6133 | static int intel_crtc_cursor_set(struct drm_crtc *crtc, |
05394f39 | 6134 | struct drm_file *file, |
79e53945 JB |
6135 | uint32_t handle, |
6136 | uint32_t width, uint32_t height) | |
6137 | { | |
6138 | struct drm_device *dev = crtc->dev; | |
6139 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6140 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
05394f39 | 6141 | struct drm_i915_gem_object *obj; |
cda4b7d3 | 6142 | uint32_t addr; |
3f8bc370 | 6143 | int ret; |
79e53945 | 6144 | |
79e53945 JB |
6145 | /* if we want to turn off the cursor ignore width and height */ |
6146 | if (!handle) { | |
28c97730 | 6147 | DRM_DEBUG_KMS("cursor off\n"); |
3f8bc370 | 6148 | addr = 0; |
05394f39 | 6149 | obj = NULL; |
5004417d | 6150 | mutex_lock(&dev->struct_mutex); |
3f8bc370 | 6151 | goto finish; |
79e53945 JB |
6152 | } |
6153 | ||
6154 | /* Currently we only support 64x64 cursors */ | |
6155 | if (width != 64 || height != 64) { | |
6156 | DRM_ERROR("we currently only support 64x64 cursors\n"); | |
6157 | return -EINVAL; | |
6158 | } | |
6159 | ||
05394f39 | 6160 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle)); |
c8725226 | 6161 | if (&obj->base == NULL) |
79e53945 JB |
6162 | return -ENOENT; |
6163 | ||
05394f39 | 6164 | if (obj->base.size < width * height * 4) { |
79e53945 | 6165 | DRM_ERROR("buffer is to small\n"); |
34b8686e DA |
6166 | ret = -ENOMEM; |
6167 | goto fail; | |
79e53945 JB |
6168 | } |
6169 | ||
71acb5eb | 6170 | /* we only need to pin inside GTT if cursor is non-phy */ |
7f9872e0 | 6171 | mutex_lock(&dev->struct_mutex); |
b295d1b6 | 6172 | if (!dev_priv->info->cursor_needs_physical) { |
d9e86c0e CW |
6173 | if (obj->tiling_mode) { |
6174 | DRM_ERROR("cursor cannot be tiled\n"); | |
6175 | ret = -EINVAL; | |
6176 | goto fail_locked; | |
6177 | } | |
6178 | ||
2da3b9b9 | 6179 | ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL); |
e7b526bb CW |
6180 | if (ret) { |
6181 | DRM_ERROR("failed to move cursor bo into the GTT\n"); | |
2da3b9b9 | 6182 | goto fail_locked; |
e7b526bb CW |
6183 | } |
6184 | ||
d9e86c0e CW |
6185 | ret = i915_gem_object_put_fence(obj); |
6186 | if (ret) { | |
2da3b9b9 | 6187 | DRM_ERROR("failed to release fence for cursor"); |
d9e86c0e CW |
6188 | goto fail_unpin; |
6189 | } | |
6190 | ||
05394f39 | 6191 | addr = obj->gtt_offset; |
71acb5eb | 6192 | } else { |
6eeefaf3 | 6193 | int align = IS_I830(dev) ? 16 * 1024 : 256; |
05394f39 | 6194 | ret = i915_gem_attach_phys_object(dev, obj, |
6eeefaf3 CW |
6195 | (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1, |
6196 | align); | |
71acb5eb DA |
6197 | if (ret) { |
6198 | DRM_ERROR("failed to attach phys object\n"); | |
7f9872e0 | 6199 | goto fail_locked; |
71acb5eb | 6200 | } |
05394f39 | 6201 | addr = obj->phys_obj->handle->busaddr; |
3f8bc370 KH |
6202 | } |
6203 | ||
a6c45cf0 | 6204 | if (IS_GEN2(dev)) |
14b60391 JB |
6205 | I915_WRITE(CURSIZE, (height << 12) | width); |
6206 | ||
3f8bc370 | 6207 | finish: |
3f8bc370 | 6208 | if (intel_crtc->cursor_bo) { |
b295d1b6 | 6209 | if (dev_priv->info->cursor_needs_physical) { |
05394f39 | 6210 | if (intel_crtc->cursor_bo != obj) |
71acb5eb DA |
6211 | i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo); |
6212 | } else | |
6213 | i915_gem_object_unpin(intel_crtc->cursor_bo); | |
05394f39 | 6214 | drm_gem_object_unreference(&intel_crtc->cursor_bo->base); |
3f8bc370 | 6215 | } |
80824003 | 6216 | |
7f9872e0 | 6217 | mutex_unlock(&dev->struct_mutex); |
3f8bc370 KH |
6218 | |
6219 | intel_crtc->cursor_addr = addr; | |
05394f39 | 6220 | intel_crtc->cursor_bo = obj; |
cda4b7d3 CW |
6221 | intel_crtc->cursor_width = width; |
6222 | intel_crtc->cursor_height = height; | |
6223 | ||
6b383a7f | 6224 | intel_crtc_update_cursor(crtc, true); |
3f8bc370 | 6225 | |
79e53945 | 6226 | return 0; |
e7b526bb | 6227 | fail_unpin: |
05394f39 | 6228 | i915_gem_object_unpin(obj); |
7f9872e0 | 6229 | fail_locked: |
34b8686e | 6230 | mutex_unlock(&dev->struct_mutex); |
bc9025bd | 6231 | fail: |
05394f39 | 6232 | drm_gem_object_unreference_unlocked(&obj->base); |
34b8686e | 6233 | return ret; |
79e53945 JB |
6234 | } |
6235 | ||
6236 | static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y) | |
6237 | { | |
79e53945 | 6238 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
79e53945 | 6239 | |
cda4b7d3 CW |
6240 | intel_crtc->cursor_x = x; |
6241 | intel_crtc->cursor_y = y; | |
652c393a | 6242 | |
6b383a7f | 6243 | intel_crtc_update_cursor(crtc, true); |
79e53945 JB |
6244 | |
6245 | return 0; | |
6246 | } | |
6247 | ||
6248 | /** Sets the color ramps on behalf of RandR */ | |
6249 | void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, | |
6250 | u16 blue, int regno) | |
6251 | { | |
6252 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6253 | ||
6254 | intel_crtc->lut_r[regno] = red >> 8; | |
6255 | intel_crtc->lut_g[regno] = green >> 8; | |
6256 | intel_crtc->lut_b[regno] = blue >> 8; | |
6257 | } | |
6258 | ||
b8c00ac5 DA |
6259 | void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, |
6260 | u16 *blue, int regno) | |
6261 | { | |
6262 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6263 | ||
6264 | *red = intel_crtc->lut_r[regno] << 8; | |
6265 | *green = intel_crtc->lut_g[regno] << 8; | |
6266 | *blue = intel_crtc->lut_b[regno] << 8; | |
6267 | } | |
6268 | ||
79e53945 | 6269 | static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, |
7203425a | 6270 | u16 *blue, uint32_t start, uint32_t size) |
79e53945 | 6271 | { |
7203425a | 6272 | int end = (start + size > 256) ? 256 : start + size, i; |
79e53945 | 6273 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
79e53945 | 6274 | |
7203425a | 6275 | for (i = start; i < end; i++) { |
79e53945 JB |
6276 | intel_crtc->lut_r[i] = red[i] >> 8; |
6277 | intel_crtc->lut_g[i] = green[i] >> 8; | |
6278 | intel_crtc->lut_b[i] = blue[i] >> 8; | |
6279 | } | |
6280 | ||
6281 | intel_crtc_load_lut(crtc); | |
6282 | } | |
6283 | ||
6284 | /** | |
6285 | * Get a pipe with a simple mode set on it for doing load-based monitor | |
6286 | * detection. | |
6287 | * | |
6288 | * It will be up to the load-detect code to adjust the pipe as appropriate for | |
c751ce4f | 6289 | * its requirements. The pipe will be connected to no other encoders. |
79e53945 | 6290 | * |
c751ce4f | 6291 | * Currently this code will only succeed if there is a pipe with no encoders |
79e53945 JB |
6292 | * configured for it. In the future, it could choose to temporarily disable |
6293 | * some outputs to free up a pipe for its use. | |
6294 | * | |
6295 | * \return crtc, or NULL if no pipes are available. | |
6296 | */ | |
6297 | ||
6298 | /* VESA 640x480x72Hz mode to set on the pipe */ | |
6299 | static struct drm_display_mode load_detect_mode = { | |
6300 | DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, | |
6301 | 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), | |
6302 | }; | |
6303 | ||
d2dff872 CW |
6304 | static struct drm_framebuffer * |
6305 | intel_framebuffer_create(struct drm_device *dev, | |
308e5bcb | 6306 | struct drm_mode_fb_cmd2 *mode_cmd, |
d2dff872 CW |
6307 | struct drm_i915_gem_object *obj) |
6308 | { | |
6309 | struct intel_framebuffer *intel_fb; | |
6310 | int ret; | |
6311 | ||
6312 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); | |
6313 | if (!intel_fb) { | |
6314 | drm_gem_object_unreference_unlocked(&obj->base); | |
6315 | return ERR_PTR(-ENOMEM); | |
6316 | } | |
6317 | ||
6318 | ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj); | |
6319 | if (ret) { | |
6320 | drm_gem_object_unreference_unlocked(&obj->base); | |
6321 | kfree(intel_fb); | |
6322 | return ERR_PTR(ret); | |
6323 | } | |
6324 | ||
6325 | return &intel_fb->base; | |
6326 | } | |
6327 | ||
6328 | static u32 | |
6329 | intel_framebuffer_pitch_for_width(int width, int bpp) | |
6330 | { | |
6331 | u32 pitch = DIV_ROUND_UP(width * bpp, 8); | |
6332 | return ALIGN(pitch, 64); | |
6333 | } | |
6334 | ||
6335 | static u32 | |
6336 | intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp) | |
6337 | { | |
6338 | u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp); | |
6339 | return ALIGN(pitch * mode->vdisplay, PAGE_SIZE); | |
6340 | } | |
6341 | ||
6342 | static struct drm_framebuffer * | |
6343 | intel_framebuffer_create_for_mode(struct drm_device *dev, | |
6344 | struct drm_display_mode *mode, | |
6345 | int depth, int bpp) | |
6346 | { | |
6347 | struct drm_i915_gem_object *obj; | |
0fed39bd | 6348 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; |
d2dff872 CW |
6349 | |
6350 | obj = i915_gem_alloc_object(dev, | |
6351 | intel_framebuffer_size_for_mode(mode, bpp)); | |
6352 | if (obj == NULL) | |
6353 | return ERR_PTR(-ENOMEM); | |
6354 | ||
6355 | mode_cmd.width = mode->hdisplay; | |
6356 | mode_cmd.height = mode->vdisplay; | |
308e5bcb JB |
6357 | mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width, |
6358 | bpp); | |
5ca0c34a | 6359 | mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth); |
d2dff872 CW |
6360 | |
6361 | return intel_framebuffer_create(dev, &mode_cmd, obj); | |
6362 | } | |
6363 | ||
6364 | static struct drm_framebuffer * | |
6365 | mode_fits_in_fbdev(struct drm_device *dev, | |
6366 | struct drm_display_mode *mode) | |
6367 | { | |
6368 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6369 | struct drm_i915_gem_object *obj; | |
6370 | struct drm_framebuffer *fb; | |
6371 | ||
6372 | if (dev_priv->fbdev == NULL) | |
6373 | return NULL; | |
6374 | ||
6375 | obj = dev_priv->fbdev->ifb.obj; | |
6376 | if (obj == NULL) | |
6377 | return NULL; | |
6378 | ||
6379 | fb = &dev_priv->fbdev->ifb.base; | |
01f2c773 VS |
6380 | if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay, |
6381 | fb->bits_per_pixel)) | |
d2dff872 CW |
6382 | return NULL; |
6383 | ||
01f2c773 | 6384 | if (obj->base.size < mode->vdisplay * fb->pitches[0]) |
d2dff872 CW |
6385 | return NULL; |
6386 | ||
6387 | return fb; | |
6388 | } | |
6389 | ||
d2434ab7 | 6390 | bool intel_get_load_detect_pipe(struct drm_connector *connector, |
7173188d | 6391 | struct drm_display_mode *mode, |
8261b191 | 6392 | struct intel_load_detect_pipe *old) |
79e53945 JB |
6393 | { |
6394 | struct intel_crtc *intel_crtc; | |
d2434ab7 DV |
6395 | struct intel_encoder *intel_encoder = |
6396 | intel_attached_encoder(connector); | |
79e53945 | 6397 | struct drm_crtc *possible_crtc; |
4ef69c7a | 6398 | struct drm_encoder *encoder = &intel_encoder->base; |
79e53945 JB |
6399 | struct drm_crtc *crtc = NULL; |
6400 | struct drm_device *dev = encoder->dev; | |
94352cf9 | 6401 | struct drm_framebuffer *fb; |
79e53945 JB |
6402 | int i = -1; |
6403 | ||
d2dff872 CW |
6404 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
6405 | connector->base.id, drm_get_connector_name(connector), | |
6406 | encoder->base.id, drm_get_encoder_name(encoder)); | |
6407 | ||
79e53945 JB |
6408 | /* |
6409 | * Algorithm gets a little messy: | |
7a5e4805 | 6410 | * |
79e53945 JB |
6411 | * - if the connector already has an assigned crtc, use it (but make |
6412 | * sure it's on first) | |
7a5e4805 | 6413 | * |
79e53945 JB |
6414 | * - try to find the first unused crtc that can drive this connector, |
6415 | * and use that if we find one | |
79e53945 JB |
6416 | */ |
6417 | ||
6418 | /* See if we already have a CRTC for this connector */ | |
6419 | if (encoder->crtc) { | |
6420 | crtc = encoder->crtc; | |
8261b191 | 6421 | |
24218aac | 6422 | old->dpms_mode = connector->dpms; |
8261b191 CW |
6423 | old->load_detect_temp = false; |
6424 | ||
6425 | /* Make sure the crtc and connector are running */ | |
24218aac DV |
6426 | if (connector->dpms != DRM_MODE_DPMS_ON) |
6427 | connector->funcs->dpms(connector, DRM_MODE_DPMS_ON); | |
8261b191 | 6428 | |
7173188d | 6429 | return true; |
79e53945 JB |
6430 | } |
6431 | ||
6432 | /* Find an unused one (if possible) */ | |
6433 | list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) { | |
6434 | i++; | |
6435 | if (!(encoder->possible_crtcs & (1 << i))) | |
6436 | continue; | |
6437 | if (!possible_crtc->enabled) { | |
6438 | crtc = possible_crtc; | |
6439 | break; | |
6440 | } | |
79e53945 JB |
6441 | } |
6442 | ||
6443 | /* | |
6444 | * If we didn't find an unused CRTC, don't use any. | |
6445 | */ | |
6446 | if (!crtc) { | |
7173188d CW |
6447 | DRM_DEBUG_KMS("no pipe available for load-detect\n"); |
6448 | return false; | |
79e53945 JB |
6449 | } |
6450 | ||
fc303101 DV |
6451 | intel_encoder->new_crtc = to_intel_crtc(crtc); |
6452 | to_intel_connector(connector)->new_encoder = intel_encoder; | |
79e53945 JB |
6453 | |
6454 | intel_crtc = to_intel_crtc(crtc); | |
24218aac | 6455 | old->dpms_mode = connector->dpms; |
8261b191 | 6456 | old->load_detect_temp = true; |
d2dff872 | 6457 | old->release_fb = NULL; |
79e53945 | 6458 | |
6492711d CW |
6459 | if (!mode) |
6460 | mode = &load_detect_mode; | |
79e53945 | 6461 | |
d2dff872 CW |
6462 | /* We need a framebuffer large enough to accommodate all accesses |
6463 | * that the plane may generate whilst we perform load detection. | |
6464 | * We can not rely on the fbcon either being present (we get called | |
6465 | * during its initialisation to detect all boot displays, or it may | |
6466 | * not even exist) or that it is large enough to satisfy the | |
6467 | * requested mode. | |
6468 | */ | |
94352cf9 DV |
6469 | fb = mode_fits_in_fbdev(dev, mode); |
6470 | if (fb == NULL) { | |
d2dff872 | 6471 | DRM_DEBUG_KMS("creating tmp fb for load-detection\n"); |
94352cf9 DV |
6472 | fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32); |
6473 | old->release_fb = fb; | |
d2dff872 CW |
6474 | } else |
6475 | DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n"); | |
94352cf9 | 6476 | if (IS_ERR(fb)) { |
d2dff872 | 6477 | DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n"); |
0e8b3d3e | 6478 | return false; |
79e53945 | 6479 | } |
79e53945 | 6480 | |
c0c36b94 | 6481 | if (intel_set_mode(crtc, mode, 0, 0, fb)) { |
6492711d | 6482 | DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n"); |
d2dff872 CW |
6483 | if (old->release_fb) |
6484 | old->release_fb->funcs->destroy(old->release_fb); | |
0e8b3d3e | 6485 | return false; |
79e53945 | 6486 | } |
7173188d | 6487 | |
79e53945 | 6488 | /* let the connector get through one full cycle before testing */ |
9d0498a2 | 6489 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
7173188d | 6490 | return true; |
79e53945 JB |
6491 | } |
6492 | ||
d2434ab7 | 6493 | void intel_release_load_detect_pipe(struct drm_connector *connector, |
8261b191 | 6494 | struct intel_load_detect_pipe *old) |
79e53945 | 6495 | { |
d2434ab7 DV |
6496 | struct intel_encoder *intel_encoder = |
6497 | intel_attached_encoder(connector); | |
4ef69c7a | 6498 | struct drm_encoder *encoder = &intel_encoder->base; |
79e53945 | 6499 | |
d2dff872 CW |
6500 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
6501 | connector->base.id, drm_get_connector_name(connector), | |
6502 | encoder->base.id, drm_get_encoder_name(encoder)); | |
6503 | ||
8261b191 | 6504 | if (old->load_detect_temp) { |
fc303101 DV |
6505 | struct drm_crtc *crtc = encoder->crtc; |
6506 | ||
6507 | to_intel_connector(connector)->new_encoder = NULL; | |
6508 | intel_encoder->new_crtc = NULL; | |
6509 | intel_set_mode(crtc, NULL, 0, 0, NULL); | |
d2dff872 CW |
6510 | |
6511 | if (old->release_fb) | |
6512 | old->release_fb->funcs->destroy(old->release_fb); | |
6513 | ||
0622a53c | 6514 | return; |
79e53945 JB |
6515 | } |
6516 | ||
c751ce4f | 6517 | /* Switch crtc and encoder back off if necessary */ |
24218aac DV |
6518 | if (old->dpms_mode != DRM_MODE_DPMS_ON) |
6519 | connector->funcs->dpms(connector, old->dpms_mode); | |
79e53945 JB |
6520 | } |
6521 | ||
6522 | /* Returns the clock of the currently programmed mode of the given pipe. */ | |
6523 | static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc) | |
6524 | { | |
6525 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6526 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6527 | int pipe = intel_crtc->pipe; | |
548f245b | 6528 | u32 dpll = I915_READ(DPLL(pipe)); |
79e53945 JB |
6529 | u32 fp; |
6530 | intel_clock_t clock; | |
6531 | ||
6532 | if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) | |
39adb7a5 | 6533 | fp = I915_READ(FP0(pipe)); |
79e53945 | 6534 | else |
39adb7a5 | 6535 | fp = I915_READ(FP1(pipe)); |
79e53945 JB |
6536 | |
6537 | clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; | |
f2b115e6 AJ |
6538 | if (IS_PINEVIEW(dev)) { |
6539 | clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; | |
6540 | clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
2177832f SL |
6541 | } else { |
6542 | clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; | |
6543 | clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
6544 | } | |
6545 | ||
a6c45cf0 | 6546 | if (!IS_GEN2(dev)) { |
f2b115e6 AJ |
6547 | if (IS_PINEVIEW(dev)) |
6548 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> | |
6549 | DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); | |
2177832f SL |
6550 | else |
6551 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> | |
79e53945 JB |
6552 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
6553 | ||
6554 | switch (dpll & DPLL_MODE_MASK) { | |
6555 | case DPLLB_MODE_DAC_SERIAL: | |
6556 | clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? | |
6557 | 5 : 10; | |
6558 | break; | |
6559 | case DPLLB_MODE_LVDS: | |
6560 | clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? | |
6561 | 7 : 14; | |
6562 | break; | |
6563 | default: | |
28c97730 | 6564 | DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed " |
79e53945 JB |
6565 | "mode\n", (int)(dpll & DPLL_MODE_MASK)); |
6566 | return 0; | |
6567 | } | |
6568 | ||
6569 | /* XXX: Handle the 100Mhz refclk */ | |
2177832f | 6570 | intel_clock(dev, 96000, &clock); |
79e53945 JB |
6571 | } else { |
6572 | bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN); | |
6573 | ||
6574 | if (is_lvds) { | |
6575 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> | |
6576 | DPLL_FPA01_P1_POST_DIV_SHIFT); | |
6577 | clock.p2 = 14; | |
6578 | ||
6579 | if ((dpll & PLL_REF_INPUT_MASK) == | |
6580 | PLLB_REF_INPUT_SPREADSPECTRUMIN) { | |
6581 | /* XXX: might not be 66MHz */ | |
2177832f | 6582 | intel_clock(dev, 66000, &clock); |
79e53945 | 6583 | } else |
2177832f | 6584 | intel_clock(dev, 48000, &clock); |
79e53945 JB |
6585 | } else { |
6586 | if (dpll & PLL_P1_DIVIDE_BY_TWO) | |
6587 | clock.p1 = 2; | |
6588 | else { | |
6589 | clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> | |
6590 | DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; | |
6591 | } | |
6592 | if (dpll & PLL_P2_DIVIDE_BY_4) | |
6593 | clock.p2 = 4; | |
6594 | else | |
6595 | clock.p2 = 2; | |
6596 | ||
2177832f | 6597 | intel_clock(dev, 48000, &clock); |
79e53945 JB |
6598 | } |
6599 | } | |
6600 | ||
6601 | /* XXX: It would be nice to validate the clocks, but we can't reuse | |
6602 | * i830PllIsValid() because it relies on the xf86_config connector | |
6603 | * configuration being accurate, which it isn't necessarily. | |
6604 | */ | |
6605 | ||
6606 | return clock.dot; | |
6607 | } | |
6608 | ||
6609 | /** Returns the currently programmed mode of the given pipe. */ | |
6610 | struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, | |
6611 | struct drm_crtc *crtc) | |
6612 | { | |
548f245b | 6613 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 6614 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
fe2b8f9d | 6615 | enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder; |
79e53945 | 6616 | struct drm_display_mode *mode; |
fe2b8f9d PZ |
6617 | int htot = I915_READ(HTOTAL(cpu_transcoder)); |
6618 | int hsync = I915_READ(HSYNC(cpu_transcoder)); | |
6619 | int vtot = I915_READ(VTOTAL(cpu_transcoder)); | |
6620 | int vsync = I915_READ(VSYNC(cpu_transcoder)); | |
79e53945 JB |
6621 | |
6622 | mode = kzalloc(sizeof(*mode), GFP_KERNEL); | |
6623 | if (!mode) | |
6624 | return NULL; | |
6625 | ||
6626 | mode->clock = intel_crtc_clock_get(dev, crtc); | |
6627 | mode->hdisplay = (htot & 0xffff) + 1; | |
6628 | mode->htotal = ((htot & 0xffff0000) >> 16) + 1; | |
6629 | mode->hsync_start = (hsync & 0xffff) + 1; | |
6630 | mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; | |
6631 | mode->vdisplay = (vtot & 0xffff) + 1; | |
6632 | mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; | |
6633 | mode->vsync_start = (vsync & 0xffff) + 1; | |
6634 | mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; | |
6635 | ||
6636 | drm_mode_set_name(mode); | |
79e53945 JB |
6637 | |
6638 | return mode; | |
6639 | } | |
6640 | ||
3dec0095 | 6641 | static void intel_increase_pllclock(struct drm_crtc *crtc) |
652c393a JB |
6642 | { |
6643 | struct drm_device *dev = crtc->dev; | |
6644 | drm_i915_private_t *dev_priv = dev->dev_private; | |
6645 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6646 | int pipe = intel_crtc->pipe; | |
dbdc6479 JB |
6647 | int dpll_reg = DPLL(pipe); |
6648 | int dpll; | |
652c393a | 6649 | |
bad720ff | 6650 | if (HAS_PCH_SPLIT(dev)) |
652c393a JB |
6651 | return; |
6652 | ||
6653 | if (!dev_priv->lvds_downclock_avail) | |
6654 | return; | |
6655 | ||
dbdc6479 | 6656 | dpll = I915_READ(dpll_reg); |
652c393a | 6657 | if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) { |
44d98a61 | 6658 | DRM_DEBUG_DRIVER("upclocking LVDS\n"); |
652c393a | 6659 | |
8ac5a6d5 | 6660 | assert_panel_unlocked(dev_priv, pipe); |
652c393a JB |
6661 | |
6662 | dpll &= ~DISPLAY_RATE_SELECT_FPA1; | |
6663 | I915_WRITE(dpll_reg, dpll); | |
9d0498a2 | 6664 | intel_wait_for_vblank(dev, pipe); |
dbdc6479 | 6665 | |
652c393a JB |
6666 | dpll = I915_READ(dpll_reg); |
6667 | if (dpll & DISPLAY_RATE_SELECT_FPA1) | |
44d98a61 | 6668 | DRM_DEBUG_DRIVER("failed to upclock LVDS!\n"); |
652c393a | 6669 | } |
652c393a JB |
6670 | } |
6671 | ||
6672 | static void intel_decrease_pllclock(struct drm_crtc *crtc) | |
6673 | { | |
6674 | struct drm_device *dev = crtc->dev; | |
6675 | drm_i915_private_t *dev_priv = dev->dev_private; | |
6676 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
652c393a | 6677 | |
bad720ff | 6678 | if (HAS_PCH_SPLIT(dev)) |
652c393a JB |
6679 | return; |
6680 | ||
6681 | if (!dev_priv->lvds_downclock_avail) | |
6682 | return; | |
6683 | ||
6684 | /* | |
6685 | * Since this is called by a timer, we should never get here in | |
6686 | * the manual case. | |
6687 | */ | |
6688 | if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) { | |
dc257cf1 DV |
6689 | int pipe = intel_crtc->pipe; |
6690 | int dpll_reg = DPLL(pipe); | |
6691 | int dpll; | |
f6e5b160 | 6692 | |
44d98a61 | 6693 | DRM_DEBUG_DRIVER("downclocking LVDS\n"); |
652c393a | 6694 | |
8ac5a6d5 | 6695 | assert_panel_unlocked(dev_priv, pipe); |
652c393a | 6696 | |
dc257cf1 | 6697 | dpll = I915_READ(dpll_reg); |
652c393a JB |
6698 | dpll |= DISPLAY_RATE_SELECT_FPA1; |
6699 | I915_WRITE(dpll_reg, dpll); | |
9d0498a2 | 6700 | intel_wait_for_vblank(dev, pipe); |
652c393a JB |
6701 | dpll = I915_READ(dpll_reg); |
6702 | if (!(dpll & DISPLAY_RATE_SELECT_FPA1)) | |
44d98a61 | 6703 | DRM_DEBUG_DRIVER("failed to downclock LVDS!\n"); |
652c393a JB |
6704 | } |
6705 | ||
6706 | } | |
6707 | ||
f047e395 CW |
6708 | void intel_mark_busy(struct drm_device *dev) |
6709 | { | |
f047e395 CW |
6710 | i915_update_gfx_val(dev->dev_private); |
6711 | } | |
6712 | ||
6713 | void intel_mark_idle(struct drm_device *dev) | |
652c393a | 6714 | { |
f047e395 CW |
6715 | } |
6716 | ||
6717 | void intel_mark_fb_busy(struct drm_i915_gem_object *obj) | |
6718 | { | |
6719 | struct drm_device *dev = obj->base.dev; | |
652c393a | 6720 | struct drm_crtc *crtc; |
652c393a JB |
6721 | |
6722 | if (!i915_powersave) | |
6723 | return; | |
6724 | ||
652c393a | 6725 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
652c393a JB |
6726 | if (!crtc->fb) |
6727 | continue; | |
6728 | ||
f047e395 CW |
6729 | if (to_intel_framebuffer(crtc->fb)->obj == obj) |
6730 | intel_increase_pllclock(crtc); | |
652c393a | 6731 | } |
652c393a JB |
6732 | } |
6733 | ||
f047e395 | 6734 | void intel_mark_fb_idle(struct drm_i915_gem_object *obj) |
652c393a | 6735 | { |
f047e395 CW |
6736 | struct drm_device *dev = obj->base.dev; |
6737 | struct drm_crtc *crtc; | |
652c393a | 6738 | |
f047e395 | 6739 | if (!i915_powersave) |
acb87dfb CW |
6740 | return; |
6741 | ||
652c393a JB |
6742 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
6743 | if (!crtc->fb) | |
6744 | continue; | |
6745 | ||
f047e395 CW |
6746 | if (to_intel_framebuffer(crtc->fb)->obj == obj) |
6747 | intel_decrease_pllclock(crtc); | |
652c393a JB |
6748 | } |
6749 | } | |
6750 | ||
79e53945 JB |
6751 | static void intel_crtc_destroy(struct drm_crtc *crtc) |
6752 | { | |
6753 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
67e77c5a DV |
6754 | struct drm_device *dev = crtc->dev; |
6755 | struct intel_unpin_work *work; | |
6756 | unsigned long flags; | |
6757 | ||
6758 | spin_lock_irqsave(&dev->event_lock, flags); | |
6759 | work = intel_crtc->unpin_work; | |
6760 | intel_crtc->unpin_work = NULL; | |
6761 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
6762 | ||
6763 | if (work) { | |
6764 | cancel_work_sync(&work->work); | |
6765 | kfree(work); | |
6766 | } | |
79e53945 JB |
6767 | |
6768 | drm_crtc_cleanup(crtc); | |
67e77c5a | 6769 | |
79e53945 JB |
6770 | kfree(intel_crtc); |
6771 | } | |
6772 | ||
6b95a207 KH |
6773 | static void intel_unpin_work_fn(struct work_struct *__work) |
6774 | { | |
6775 | struct intel_unpin_work *work = | |
6776 | container_of(__work, struct intel_unpin_work, work); | |
b4a98e57 | 6777 | struct drm_device *dev = work->crtc->dev; |
6b95a207 | 6778 | |
b4a98e57 | 6779 | mutex_lock(&dev->struct_mutex); |
1690e1eb | 6780 | intel_unpin_fb_obj(work->old_fb_obj); |
05394f39 CW |
6781 | drm_gem_object_unreference(&work->pending_flip_obj->base); |
6782 | drm_gem_object_unreference(&work->old_fb_obj->base); | |
d9e86c0e | 6783 | |
b4a98e57 CW |
6784 | intel_update_fbc(dev); |
6785 | mutex_unlock(&dev->struct_mutex); | |
6786 | ||
6787 | BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0); | |
6788 | atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count); | |
6789 | ||
6b95a207 KH |
6790 | kfree(work); |
6791 | } | |
6792 | ||
1afe3e9d | 6793 | static void do_intel_finish_page_flip(struct drm_device *dev, |
49b14a5c | 6794 | struct drm_crtc *crtc) |
6b95a207 KH |
6795 | { |
6796 | drm_i915_private_t *dev_priv = dev->dev_private; | |
6b95a207 KH |
6797 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6798 | struct intel_unpin_work *work; | |
05394f39 | 6799 | struct drm_i915_gem_object *obj; |
6b95a207 KH |
6800 | unsigned long flags; |
6801 | ||
6802 | /* Ignore early vblank irqs */ | |
6803 | if (intel_crtc == NULL) | |
6804 | return; | |
6805 | ||
6806 | spin_lock_irqsave(&dev->event_lock, flags); | |
6807 | work = intel_crtc->unpin_work; | |
e7d841ca CW |
6808 | |
6809 | /* Ensure we don't miss a work->pending update ... */ | |
6810 | smp_rmb(); | |
6811 | ||
6812 | if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) { | |
6b95a207 KH |
6813 | spin_unlock_irqrestore(&dev->event_lock, flags); |
6814 | return; | |
6815 | } | |
6816 | ||
e7d841ca CW |
6817 | /* and that the unpin work is consistent wrt ->pending. */ |
6818 | smp_rmb(); | |
6819 | ||
6b95a207 | 6820 | intel_crtc->unpin_work = NULL; |
6b95a207 | 6821 | |
45a066eb RC |
6822 | if (work->event) |
6823 | drm_send_vblank_event(dev, intel_crtc->pipe, work->event); | |
6b95a207 | 6824 | |
0af7e4df MK |
6825 | drm_vblank_put(dev, intel_crtc->pipe); |
6826 | ||
6b95a207 KH |
6827 | spin_unlock_irqrestore(&dev->event_lock, flags); |
6828 | ||
05394f39 | 6829 | obj = work->old_fb_obj; |
d9e86c0e | 6830 | |
2c10d571 | 6831 | wake_up_all(&dev_priv->pending_flip_queue); |
b4a98e57 CW |
6832 | |
6833 | queue_work(dev_priv->wq, &work->work); | |
e5510fac JB |
6834 | |
6835 | trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj); | |
6b95a207 KH |
6836 | } |
6837 | ||
1afe3e9d JB |
6838 | void intel_finish_page_flip(struct drm_device *dev, int pipe) |
6839 | { | |
6840 | drm_i915_private_t *dev_priv = dev->dev_private; | |
6841 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
6842 | ||
49b14a5c | 6843 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
6844 | } |
6845 | ||
6846 | void intel_finish_page_flip_plane(struct drm_device *dev, int plane) | |
6847 | { | |
6848 | drm_i915_private_t *dev_priv = dev->dev_private; | |
6849 | struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane]; | |
6850 | ||
49b14a5c | 6851 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
6852 | } |
6853 | ||
6b95a207 KH |
6854 | void intel_prepare_page_flip(struct drm_device *dev, int plane) |
6855 | { | |
6856 | drm_i915_private_t *dev_priv = dev->dev_private; | |
6857 | struct intel_crtc *intel_crtc = | |
6858 | to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]); | |
6859 | unsigned long flags; | |
6860 | ||
e7d841ca CW |
6861 | /* NB: An MMIO update of the plane base pointer will also |
6862 | * generate a page-flip completion irq, i.e. every modeset | |
6863 | * is also accompanied by a spurious intel_prepare_page_flip(). | |
6864 | */ | |
6b95a207 | 6865 | spin_lock_irqsave(&dev->event_lock, flags); |
e7d841ca CW |
6866 | if (intel_crtc->unpin_work) |
6867 | atomic_inc_not_zero(&intel_crtc->unpin_work->pending); | |
6b95a207 KH |
6868 | spin_unlock_irqrestore(&dev->event_lock, flags); |
6869 | } | |
6870 | ||
e7d841ca CW |
6871 | inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc) |
6872 | { | |
6873 | /* Ensure that the work item is consistent when activating it ... */ | |
6874 | smp_wmb(); | |
6875 | atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING); | |
6876 | /* and that it is marked active as soon as the irq could fire. */ | |
6877 | smp_wmb(); | |
6878 | } | |
6879 | ||
8c9f3aaf JB |
6880 | static int intel_gen2_queue_flip(struct drm_device *dev, |
6881 | struct drm_crtc *crtc, | |
6882 | struct drm_framebuffer *fb, | |
6883 | struct drm_i915_gem_object *obj) | |
6884 | { | |
6885 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6886 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
8c9f3aaf | 6887 | u32 flip_mask; |
6d90c952 | 6888 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
8c9f3aaf JB |
6889 | int ret; |
6890 | ||
6d90c952 | 6891 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); |
8c9f3aaf | 6892 | if (ret) |
83d4092b | 6893 | goto err; |
8c9f3aaf | 6894 | |
6d90c952 | 6895 | ret = intel_ring_begin(ring, 6); |
8c9f3aaf | 6896 | if (ret) |
83d4092b | 6897 | goto err_unpin; |
8c9f3aaf JB |
6898 | |
6899 | /* Can't queue multiple flips, so wait for the previous | |
6900 | * one to finish before executing the next. | |
6901 | */ | |
6902 | if (intel_crtc->plane) | |
6903 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
6904 | else | |
6905 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
6d90c952 DV |
6906 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
6907 | intel_ring_emit(ring, MI_NOOP); | |
6908 | intel_ring_emit(ring, MI_DISPLAY_FLIP | | |
6909 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
6910 | intel_ring_emit(ring, fb->pitches[0]); | |
e506a0c6 | 6911 | intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset); |
6d90c952 | 6912 | intel_ring_emit(ring, 0); /* aux display base address, unused */ |
e7d841ca CW |
6913 | |
6914 | intel_mark_page_flip_active(intel_crtc); | |
6d90c952 | 6915 | intel_ring_advance(ring); |
83d4092b CW |
6916 | return 0; |
6917 | ||
6918 | err_unpin: | |
6919 | intel_unpin_fb_obj(obj); | |
6920 | err: | |
8c9f3aaf JB |
6921 | return ret; |
6922 | } | |
6923 | ||
6924 | static int intel_gen3_queue_flip(struct drm_device *dev, | |
6925 | struct drm_crtc *crtc, | |
6926 | struct drm_framebuffer *fb, | |
6927 | struct drm_i915_gem_object *obj) | |
6928 | { | |
6929 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6930 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
8c9f3aaf | 6931 | u32 flip_mask; |
6d90c952 | 6932 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
8c9f3aaf JB |
6933 | int ret; |
6934 | ||
6d90c952 | 6935 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); |
8c9f3aaf | 6936 | if (ret) |
83d4092b | 6937 | goto err; |
8c9f3aaf | 6938 | |
6d90c952 | 6939 | ret = intel_ring_begin(ring, 6); |
8c9f3aaf | 6940 | if (ret) |
83d4092b | 6941 | goto err_unpin; |
8c9f3aaf JB |
6942 | |
6943 | if (intel_crtc->plane) | |
6944 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
6945 | else | |
6946 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
6d90c952 DV |
6947 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
6948 | intel_ring_emit(ring, MI_NOOP); | |
6949 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | | |
6950 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
6951 | intel_ring_emit(ring, fb->pitches[0]); | |
e506a0c6 | 6952 | intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset); |
6d90c952 DV |
6953 | intel_ring_emit(ring, MI_NOOP); |
6954 | ||
e7d841ca | 6955 | intel_mark_page_flip_active(intel_crtc); |
6d90c952 | 6956 | intel_ring_advance(ring); |
83d4092b CW |
6957 | return 0; |
6958 | ||
6959 | err_unpin: | |
6960 | intel_unpin_fb_obj(obj); | |
6961 | err: | |
8c9f3aaf JB |
6962 | return ret; |
6963 | } | |
6964 | ||
6965 | static int intel_gen4_queue_flip(struct drm_device *dev, | |
6966 | struct drm_crtc *crtc, | |
6967 | struct drm_framebuffer *fb, | |
6968 | struct drm_i915_gem_object *obj) | |
6969 | { | |
6970 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6971 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6972 | uint32_t pf, pipesrc; | |
6d90c952 | 6973 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
8c9f3aaf JB |
6974 | int ret; |
6975 | ||
6d90c952 | 6976 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); |
8c9f3aaf | 6977 | if (ret) |
83d4092b | 6978 | goto err; |
8c9f3aaf | 6979 | |
6d90c952 | 6980 | ret = intel_ring_begin(ring, 4); |
8c9f3aaf | 6981 | if (ret) |
83d4092b | 6982 | goto err_unpin; |
8c9f3aaf JB |
6983 | |
6984 | /* i965+ uses the linear or tiled offsets from the | |
6985 | * Display Registers (which do not change across a page-flip) | |
6986 | * so we need only reprogram the base address. | |
6987 | */ | |
6d90c952 DV |
6988 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
6989 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
6990 | intel_ring_emit(ring, fb->pitches[0]); | |
c2c75131 DV |
6991 | intel_ring_emit(ring, |
6992 | (obj->gtt_offset + intel_crtc->dspaddr_offset) | | |
6993 | obj->tiling_mode); | |
8c9f3aaf JB |
6994 | |
6995 | /* XXX Enabling the panel-fitter across page-flip is so far | |
6996 | * untested on non-native modes, so ignore it for now. | |
6997 | * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE; | |
6998 | */ | |
6999 | pf = 0; | |
7000 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; | |
6d90c952 | 7001 | intel_ring_emit(ring, pf | pipesrc); |
e7d841ca CW |
7002 | |
7003 | intel_mark_page_flip_active(intel_crtc); | |
6d90c952 | 7004 | intel_ring_advance(ring); |
83d4092b CW |
7005 | return 0; |
7006 | ||
7007 | err_unpin: | |
7008 | intel_unpin_fb_obj(obj); | |
7009 | err: | |
8c9f3aaf JB |
7010 | return ret; |
7011 | } | |
7012 | ||
7013 | static int intel_gen6_queue_flip(struct drm_device *dev, | |
7014 | struct drm_crtc *crtc, | |
7015 | struct drm_framebuffer *fb, | |
7016 | struct drm_i915_gem_object *obj) | |
7017 | { | |
7018 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7019 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6d90c952 | 7020 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
8c9f3aaf JB |
7021 | uint32_t pf, pipesrc; |
7022 | int ret; | |
7023 | ||
6d90c952 | 7024 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); |
8c9f3aaf | 7025 | if (ret) |
83d4092b | 7026 | goto err; |
8c9f3aaf | 7027 | |
6d90c952 | 7028 | ret = intel_ring_begin(ring, 4); |
8c9f3aaf | 7029 | if (ret) |
83d4092b | 7030 | goto err_unpin; |
8c9f3aaf | 7031 | |
6d90c952 DV |
7032 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
7033 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
7034 | intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode); | |
c2c75131 | 7035 | intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset); |
8c9f3aaf | 7036 | |
dc257cf1 DV |
7037 | /* Contrary to the suggestions in the documentation, |
7038 | * "Enable Panel Fitter" does not seem to be required when page | |
7039 | * flipping with a non-native mode, and worse causes a normal | |
7040 | * modeset to fail. | |
7041 | * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE; | |
7042 | */ | |
7043 | pf = 0; | |
8c9f3aaf | 7044 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; |
6d90c952 | 7045 | intel_ring_emit(ring, pf | pipesrc); |
e7d841ca CW |
7046 | |
7047 | intel_mark_page_flip_active(intel_crtc); | |
6d90c952 | 7048 | intel_ring_advance(ring); |
83d4092b CW |
7049 | return 0; |
7050 | ||
7051 | err_unpin: | |
7052 | intel_unpin_fb_obj(obj); | |
7053 | err: | |
8c9f3aaf JB |
7054 | return ret; |
7055 | } | |
7056 | ||
7c9017e5 JB |
7057 | /* |
7058 | * On gen7 we currently use the blit ring because (in early silicon at least) | |
7059 | * the render ring doesn't give us interrpts for page flip completion, which | |
7060 | * means clients will hang after the first flip is queued. Fortunately the | |
7061 | * blit ring generates interrupts properly, so use it instead. | |
7062 | */ | |
7063 | static int intel_gen7_queue_flip(struct drm_device *dev, | |
7064 | struct drm_crtc *crtc, | |
7065 | struct drm_framebuffer *fb, | |
7066 | struct drm_i915_gem_object *obj) | |
7067 | { | |
7068 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7069 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
7070 | struct intel_ring_buffer *ring = &dev_priv->ring[BCS]; | |
cb05d8de | 7071 | uint32_t plane_bit = 0; |
7c9017e5 JB |
7072 | int ret; |
7073 | ||
7074 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); | |
7075 | if (ret) | |
83d4092b | 7076 | goto err; |
7c9017e5 | 7077 | |
cb05d8de DV |
7078 | switch(intel_crtc->plane) { |
7079 | case PLANE_A: | |
7080 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A; | |
7081 | break; | |
7082 | case PLANE_B: | |
7083 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B; | |
7084 | break; | |
7085 | case PLANE_C: | |
7086 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C; | |
7087 | break; | |
7088 | default: | |
7089 | WARN_ONCE(1, "unknown plane in flip command\n"); | |
7090 | ret = -ENODEV; | |
ab3951eb | 7091 | goto err_unpin; |
cb05d8de DV |
7092 | } |
7093 | ||
7c9017e5 JB |
7094 | ret = intel_ring_begin(ring, 4); |
7095 | if (ret) | |
83d4092b | 7096 | goto err_unpin; |
7c9017e5 | 7097 | |
cb05d8de | 7098 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit); |
01f2c773 | 7099 | intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode)); |
c2c75131 | 7100 | intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset); |
7c9017e5 | 7101 | intel_ring_emit(ring, (MI_NOOP)); |
e7d841ca CW |
7102 | |
7103 | intel_mark_page_flip_active(intel_crtc); | |
7c9017e5 | 7104 | intel_ring_advance(ring); |
83d4092b CW |
7105 | return 0; |
7106 | ||
7107 | err_unpin: | |
7108 | intel_unpin_fb_obj(obj); | |
7109 | err: | |
7c9017e5 JB |
7110 | return ret; |
7111 | } | |
7112 | ||
8c9f3aaf JB |
7113 | static int intel_default_queue_flip(struct drm_device *dev, |
7114 | struct drm_crtc *crtc, | |
7115 | struct drm_framebuffer *fb, | |
7116 | struct drm_i915_gem_object *obj) | |
7117 | { | |
7118 | return -ENODEV; | |
7119 | } | |
7120 | ||
6b95a207 KH |
7121 | static int intel_crtc_page_flip(struct drm_crtc *crtc, |
7122 | struct drm_framebuffer *fb, | |
7123 | struct drm_pending_vblank_event *event) | |
7124 | { | |
7125 | struct drm_device *dev = crtc->dev; | |
7126 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7127 | struct intel_framebuffer *intel_fb; | |
05394f39 | 7128 | struct drm_i915_gem_object *obj; |
6b95a207 KH |
7129 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
7130 | struct intel_unpin_work *work; | |
8c9f3aaf | 7131 | unsigned long flags; |
52e68630 | 7132 | int ret; |
6b95a207 | 7133 | |
e6a595d2 VS |
7134 | /* Can't change pixel format via MI display flips. */ |
7135 | if (fb->pixel_format != crtc->fb->pixel_format) | |
7136 | return -EINVAL; | |
7137 | ||
7138 | /* | |
7139 | * TILEOFF/LINOFF registers can't be changed via MI display flips. | |
7140 | * Note that pitch changes could also affect these register. | |
7141 | */ | |
7142 | if (INTEL_INFO(dev)->gen > 3 && | |
7143 | (fb->offsets[0] != crtc->fb->offsets[0] || | |
7144 | fb->pitches[0] != crtc->fb->pitches[0])) | |
7145 | return -EINVAL; | |
7146 | ||
6b95a207 KH |
7147 | work = kzalloc(sizeof *work, GFP_KERNEL); |
7148 | if (work == NULL) | |
7149 | return -ENOMEM; | |
7150 | ||
6b95a207 | 7151 | work->event = event; |
b4a98e57 | 7152 | work->crtc = crtc; |
6b95a207 | 7153 | intel_fb = to_intel_framebuffer(crtc->fb); |
b1b87f6b | 7154 | work->old_fb_obj = intel_fb->obj; |
6b95a207 KH |
7155 | INIT_WORK(&work->work, intel_unpin_work_fn); |
7156 | ||
7317c75e JB |
7157 | ret = drm_vblank_get(dev, intel_crtc->pipe); |
7158 | if (ret) | |
7159 | goto free_work; | |
7160 | ||
6b95a207 KH |
7161 | /* We borrow the event spin lock for protecting unpin_work */ |
7162 | spin_lock_irqsave(&dev->event_lock, flags); | |
7163 | if (intel_crtc->unpin_work) { | |
7164 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
7165 | kfree(work); | |
7317c75e | 7166 | drm_vblank_put(dev, intel_crtc->pipe); |
468f0b44 CW |
7167 | |
7168 | DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); | |
6b95a207 KH |
7169 | return -EBUSY; |
7170 | } | |
7171 | intel_crtc->unpin_work = work; | |
7172 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
7173 | ||
7174 | intel_fb = to_intel_framebuffer(fb); | |
7175 | obj = intel_fb->obj; | |
7176 | ||
b4a98e57 CW |
7177 | if (atomic_read(&intel_crtc->unpin_work_count) >= 2) |
7178 | flush_workqueue(dev_priv->wq); | |
7179 | ||
79158103 CW |
7180 | ret = i915_mutex_lock_interruptible(dev); |
7181 | if (ret) | |
7182 | goto cleanup; | |
6b95a207 | 7183 | |
75dfca80 | 7184 | /* Reference the objects for the scheduled work. */ |
05394f39 CW |
7185 | drm_gem_object_reference(&work->old_fb_obj->base); |
7186 | drm_gem_object_reference(&obj->base); | |
6b95a207 KH |
7187 | |
7188 | crtc->fb = fb; | |
96b099fd | 7189 | |
e1f99ce6 | 7190 | work->pending_flip_obj = obj; |
e1f99ce6 | 7191 | |
4e5359cd SF |
7192 | work->enable_stall_check = true; |
7193 | ||
b4a98e57 | 7194 | atomic_inc(&intel_crtc->unpin_work_count); |
e1f99ce6 | 7195 | |
8c9f3aaf JB |
7196 | ret = dev_priv->display.queue_flip(dev, crtc, fb, obj); |
7197 | if (ret) | |
7198 | goto cleanup_pending; | |
6b95a207 | 7199 | |
7782de3b | 7200 | intel_disable_fbc(dev); |
f047e395 | 7201 | intel_mark_fb_busy(obj); |
6b95a207 KH |
7202 | mutex_unlock(&dev->struct_mutex); |
7203 | ||
e5510fac JB |
7204 | trace_i915_flip_request(intel_crtc->plane, obj); |
7205 | ||
6b95a207 | 7206 | return 0; |
96b099fd | 7207 | |
8c9f3aaf | 7208 | cleanup_pending: |
b4a98e57 | 7209 | atomic_dec(&intel_crtc->unpin_work_count); |
05394f39 CW |
7210 | drm_gem_object_unreference(&work->old_fb_obj->base); |
7211 | drm_gem_object_unreference(&obj->base); | |
96b099fd CW |
7212 | mutex_unlock(&dev->struct_mutex); |
7213 | ||
79158103 | 7214 | cleanup: |
96b099fd CW |
7215 | spin_lock_irqsave(&dev->event_lock, flags); |
7216 | intel_crtc->unpin_work = NULL; | |
7217 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
7218 | ||
7317c75e JB |
7219 | drm_vblank_put(dev, intel_crtc->pipe); |
7220 | free_work: | |
96b099fd CW |
7221 | kfree(work); |
7222 | ||
7223 | return ret; | |
6b95a207 KH |
7224 | } |
7225 | ||
f6e5b160 | 7226 | static struct drm_crtc_helper_funcs intel_helper_funcs = { |
f6e5b160 CW |
7227 | .mode_set_base_atomic = intel_pipe_set_base_atomic, |
7228 | .load_lut = intel_crtc_load_lut, | |
976f8a20 | 7229 | .disable = intel_crtc_noop, |
f6e5b160 CW |
7230 | }; |
7231 | ||
6ed0f796 | 7232 | bool intel_encoder_check_is_cloned(struct intel_encoder *encoder) |
47f1c6c9 | 7233 | { |
6ed0f796 DV |
7234 | struct intel_encoder *other_encoder; |
7235 | struct drm_crtc *crtc = &encoder->new_crtc->base; | |
47f1c6c9 | 7236 | |
6ed0f796 DV |
7237 | if (WARN_ON(!crtc)) |
7238 | return false; | |
7239 | ||
7240 | list_for_each_entry(other_encoder, | |
7241 | &crtc->dev->mode_config.encoder_list, | |
7242 | base.head) { | |
7243 | ||
7244 | if (&other_encoder->new_crtc->base != crtc || | |
7245 | encoder == other_encoder) | |
7246 | continue; | |
7247 | else | |
7248 | return true; | |
f47166d2 CW |
7249 | } |
7250 | ||
6ed0f796 DV |
7251 | return false; |
7252 | } | |
47f1c6c9 | 7253 | |
50f56119 DV |
7254 | static bool intel_encoder_crtc_ok(struct drm_encoder *encoder, |
7255 | struct drm_crtc *crtc) | |
7256 | { | |
7257 | struct drm_device *dev; | |
7258 | struct drm_crtc *tmp; | |
7259 | int crtc_mask = 1; | |
47f1c6c9 | 7260 | |
50f56119 | 7261 | WARN(!crtc, "checking null crtc?\n"); |
47f1c6c9 | 7262 | |
50f56119 | 7263 | dev = crtc->dev; |
47f1c6c9 | 7264 | |
50f56119 DV |
7265 | list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) { |
7266 | if (tmp == crtc) | |
7267 | break; | |
7268 | crtc_mask <<= 1; | |
7269 | } | |
47f1c6c9 | 7270 | |
50f56119 DV |
7271 | if (encoder->possible_crtcs & crtc_mask) |
7272 | return true; | |
7273 | return false; | |
47f1c6c9 | 7274 | } |
79e53945 | 7275 | |
9a935856 DV |
7276 | /** |
7277 | * intel_modeset_update_staged_output_state | |
7278 | * | |
7279 | * Updates the staged output configuration state, e.g. after we've read out the | |
7280 | * current hw state. | |
7281 | */ | |
7282 | static void intel_modeset_update_staged_output_state(struct drm_device *dev) | |
f6e5b160 | 7283 | { |
9a935856 DV |
7284 | struct intel_encoder *encoder; |
7285 | struct intel_connector *connector; | |
f6e5b160 | 7286 | |
9a935856 DV |
7287 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
7288 | base.head) { | |
7289 | connector->new_encoder = | |
7290 | to_intel_encoder(connector->base.encoder); | |
7291 | } | |
f6e5b160 | 7292 | |
9a935856 DV |
7293 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
7294 | base.head) { | |
7295 | encoder->new_crtc = | |
7296 | to_intel_crtc(encoder->base.crtc); | |
7297 | } | |
f6e5b160 CW |
7298 | } |
7299 | ||
9a935856 DV |
7300 | /** |
7301 | * intel_modeset_commit_output_state | |
7302 | * | |
7303 | * This function copies the stage display pipe configuration to the real one. | |
7304 | */ | |
7305 | static void intel_modeset_commit_output_state(struct drm_device *dev) | |
7306 | { | |
7307 | struct intel_encoder *encoder; | |
7308 | struct intel_connector *connector; | |
f6e5b160 | 7309 | |
9a935856 DV |
7310 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
7311 | base.head) { | |
7312 | connector->base.encoder = &connector->new_encoder->base; | |
7313 | } | |
f6e5b160 | 7314 | |
9a935856 DV |
7315 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
7316 | base.head) { | |
7317 | encoder->base.crtc = &encoder->new_crtc->base; | |
7318 | } | |
7319 | } | |
7320 | ||
7758a113 DV |
7321 | static struct drm_display_mode * |
7322 | intel_modeset_adjusted_mode(struct drm_crtc *crtc, | |
7323 | struct drm_display_mode *mode) | |
ee7b9f93 | 7324 | { |
7758a113 DV |
7325 | struct drm_device *dev = crtc->dev; |
7326 | struct drm_display_mode *adjusted_mode; | |
7327 | struct drm_encoder_helper_funcs *encoder_funcs; | |
7328 | struct intel_encoder *encoder; | |
ee7b9f93 | 7329 | |
7758a113 DV |
7330 | adjusted_mode = drm_mode_duplicate(dev, mode); |
7331 | if (!adjusted_mode) | |
7332 | return ERR_PTR(-ENOMEM); | |
7333 | ||
7334 | /* Pass our mode to the connectors and the CRTC to give them a chance to | |
7335 | * adjust it according to limitations or connector properties, and also | |
7336 | * a chance to reject the mode entirely. | |
47f1c6c9 | 7337 | */ |
7758a113 DV |
7338 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
7339 | base.head) { | |
47f1c6c9 | 7340 | |
7758a113 DV |
7341 | if (&encoder->new_crtc->base != crtc) |
7342 | continue; | |
7343 | encoder_funcs = encoder->base.helper_private; | |
7344 | if (!(encoder_funcs->mode_fixup(&encoder->base, mode, | |
7345 | adjusted_mode))) { | |
7346 | DRM_DEBUG_KMS("Encoder fixup failed\n"); | |
7347 | goto fail; | |
7348 | } | |
ee7b9f93 | 7349 | } |
47f1c6c9 | 7350 | |
7758a113 DV |
7351 | if (!(intel_crtc_mode_fixup(crtc, mode, adjusted_mode))) { |
7352 | DRM_DEBUG_KMS("CRTC fixup failed\n"); | |
7353 | goto fail; | |
ee7b9f93 | 7354 | } |
7758a113 | 7355 | DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id); |
47f1c6c9 | 7356 | |
7758a113 DV |
7357 | return adjusted_mode; |
7358 | fail: | |
7359 | drm_mode_destroy(dev, adjusted_mode); | |
7360 | return ERR_PTR(-EINVAL); | |
ee7b9f93 | 7361 | } |
47f1c6c9 | 7362 | |
e2e1ed41 DV |
7363 | /* Computes which crtcs are affected and sets the relevant bits in the mask. For |
7364 | * simplicity we use the crtc's pipe number (because it's easier to obtain). */ | |
7365 | static void | |
7366 | intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes, | |
7367 | unsigned *prepare_pipes, unsigned *disable_pipes) | |
79e53945 JB |
7368 | { |
7369 | struct intel_crtc *intel_crtc; | |
e2e1ed41 DV |
7370 | struct drm_device *dev = crtc->dev; |
7371 | struct intel_encoder *encoder; | |
7372 | struct intel_connector *connector; | |
7373 | struct drm_crtc *tmp_crtc; | |
79e53945 | 7374 | |
e2e1ed41 | 7375 | *disable_pipes = *modeset_pipes = *prepare_pipes = 0; |
79e53945 | 7376 | |
e2e1ed41 DV |
7377 | /* Check which crtcs have changed outputs connected to them, these need |
7378 | * to be part of the prepare_pipes mask. We don't (yet) support global | |
7379 | * modeset across multiple crtcs, so modeset_pipes will only have one | |
7380 | * bit set at most. */ | |
7381 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
7382 | base.head) { | |
7383 | if (connector->base.encoder == &connector->new_encoder->base) | |
7384 | continue; | |
79e53945 | 7385 | |
e2e1ed41 DV |
7386 | if (connector->base.encoder) { |
7387 | tmp_crtc = connector->base.encoder->crtc; | |
7388 | ||
7389 | *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe; | |
7390 | } | |
7391 | ||
7392 | if (connector->new_encoder) | |
7393 | *prepare_pipes |= | |
7394 | 1 << connector->new_encoder->new_crtc->pipe; | |
79e53945 JB |
7395 | } |
7396 | ||
e2e1ed41 DV |
7397 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
7398 | base.head) { | |
7399 | if (encoder->base.crtc == &encoder->new_crtc->base) | |
7400 | continue; | |
7401 | ||
7402 | if (encoder->base.crtc) { | |
7403 | tmp_crtc = encoder->base.crtc; | |
7404 | ||
7405 | *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe; | |
7406 | } | |
7407 | ||
7408 | if (encoder->new_crtc) | |
7409 | *prepare_pipes |= 1 << encoder->new_crtc->pipe; | |
80824003 JB |
7410 | } |
7411 | ||
e2e1ed41 DV |
7412 | /* Check for any pipes that will be fully disabled ... */ |
7413 | list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, | |
7414 | base.head) { | |
7415 | bool used = false; | |
22fd0fab | 7416 | |
e2e1ed41 DV |
7417 | /* Don't try to disable disabled crtcs. */ |
7418 | if (!intel_crtc->base.enabled) | |
7419 | continue; | |
7e7d76c3 | 7420 | |
e2e1ed41 DV |
7421 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
7422 | base.head) { | |
7423 | if (encoder->new_crtc == intel_crtc) | |
7424 | used = true; | |
7425 | } | |
7426 | ||
7427 | if (!used) | |
7428 | *disable_pipes |= 1 << intel_crtc->pipe; | |
7e7d76c3 JB |
7429 | } |
7430 | ||
e2e1ed41 DV |
7431 | |
7432 | /* set_mode is also used to update properties on life display pipes. */ | |
7433 | intel_crtc = to_intel_crtc(crtc); | |
7434 | if (crtc->enabled) | |
7435 | *prepare_pipes |= 1 << intel_crtc->pipe; | |
7436 | ||
7437 | /* We only support modeset on one single crtc, hence we need to do that | |
7438 | * only for the passed in crtc iff we change anything else than just | |
7439 | * disable crtcs. | |
7440 | * | |
7441 | * This is actually not true, to be fully compatible with the old crtc | |
7442 | * helper we automatically disable _any_ output (i.e. doesn't need to be | |
7443 | * connected to the crtc we're modesetting on) if it's disconnected. | |
7444 | * Which is a rather nutty api (since changed the output configuration | |
7445 | * without userspace's explicit request can lead to confusion), but | |
7446 | * alas. Hence we currently need to modeset on all pipes we prepare. */ | |
7447 | if (*prepare_pipes) | |
7448 | *modeset_pipes = *prepare_pipes; | |
7449 | ||
7450 | /* ... and mask these out. */ | |
7451 | *modeset_pipes &= ~(*disable_pipes); | |
7452 | *prepare_pipes &= ~(*disable_pipes); | |
47f1c6c9 | 7453 | } |
79e53945 | 7454 | |
ea9d758d | 7455 | static bool intel_crtc_in_use(struct drm_crtc *crtc) |
f6e5b160 | 7456 | { |
ea9d758d | 7457 | struct drm_encoder *encoder; |
f6e5b160 | 7458 | struct drm_device *dev = crtc->dev; |
f6e5b160 | 7459 | |
ea9d758d DV |
7460 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) |
7461 | if (encoder->crtc == crtc) | |
7462 | return true; | |
7463 | ||
7464 | return false; | |
7465 | } | |
7466 | ||
7467 | static void | |
7468 | intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes) | |
7469 | { | |
7470 | struct intel_encoder *intel_encoder; | |
7471 | struct intel_crtc *intel_crtc; | |
7472 | struct drm_connector *connector; | |
7473 | ||
7474 | list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list, | |
7475 | base.head) { | |
7476 | if (!intel_encoder->base.crtc) | |
7477 | continue; | |
7478 | ||
7479 | intel_crtc = to_intel_crtc(intel_encoder->base.crtc); | |
7480 | ||
7481 | if (prepare_pipes & (1 << intel_crtc->pipe)) | |
7482 | intel_encoder->connectors_active = false; | |
7483 | } | |
7484 | ||
7485 | intel_modeset_commit_output_state(dev); | |
7486 | ||
7487 | /* Update computed state. */ | |
7488 | list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, | |
7489 | base.head) { | |
7490 | intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base); | |
7491 | } | |
7492 | ||
7493 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
7494 | if (!connector->encoder || !connector->encoder->crtc) | |
7495 | continue; | |
7496 | ||
7497 | intel_crtc = to_intel_crtc(connector->encoder->crtc); | |
7498 | ||
7499 | if (prepare_pipes & (1 << intel_crtc->pipe)) { | |
68d34720 DV |
7500 | struct drm_property *dpms_property = |
7501 | dev->mode_config.dpms_property; | |
7502 | ||
ea9d758d | 7503 | connector->dpms = DRM_MODE_DPMS_ON; |
662595df | 7504 | drm_object_property_set_value(&connector->base, |
68d34720 DV |
7505 | dpms_property, |
7506 | DRM_MODE_DPMS_ON); | |
ea9d758d DV |
7507 | |
7508 | intel_encoder = to_intel_encoder(connector->encoder); | |
7509 | intel_encoder->connectors_active = true; | |
7510 | } | |
7511 | } | |
7512 | ||
7513 | } | |
7514 | ||
25c5b266 DV |
7515 | #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \ |
7516 | list_for_each_entry((intel_crtc), \ | |
7517 | &(dev)->mode_config.crtc_list, \ | |
7518 | base.head) \ | |
7519 | if (mask & (1 <<(intel_crtc)->pipe)) \ | |
7520 | ||
b980514c | 7521 | void |
8af6cf88 DV |
7522 | intel_modeset_check_state(struct drm_device *dev) |
7523 | { | |
7524 | struct intel_crtc *crtc; | |
7525 | struct intel_encoder *encoder; | |
7526 | struct intel_connector *connector; | |
7527 | ||
7528 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
7529 | base.head) { | |
7530 | /* This also checks the encoder/connector hw state with the | |
7531 | * ->get_hw_state callbacks. */ | |
7532 | intel_connector_check_state(connector); | |
7533 | ||
7534 | WARN(&connector->new_encoder->base != connector->base.encoder, | |
7535 | "connector's staged encoder doesn't match current encoder\n"); | |
7536 | } | |
7537 | ||
7538 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, | |
7539 | base.head) { | |
7540 | bool enabled = false; | |
7541 | bool active = false; | |
7542 | enum pipe pipe, tracked_pipe; | |
7543 | ||
7544 | DRM_DEBUG_KMS("[ENCODER:%d:%s]\n", | |
7545 | encoder->base.base.id, | |
7546 | drm_get_encoder_name(&encoder->base)); | |
7547 | ||
7548 | WARN(&encoder->new_crtc->base != encoder->base.crtc, | |
7549 | "encoder's stage crtc doesn't match current crtc\n"); | |
7550 | WARN(encoder->connectors_active && !encoder->base.crtc, | |
7551 | "encoder's active_connectors set, but no crtc\n"); | |
7552 | ||
7553 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
7554 | base.head) { | |
7555 | if (connector->base.encoder != &encoder->base) | |
7556 | continue; | |
7557 | enabled = true; | |
7558 | if (connector->base.dpms != DRM_MODE_DPMS_OFF) | |
7559 | active = true; | |
7560 | } | |
7561 | WARN(!!encoder->base.crtc != enabled, | |
7562 | "encoder's enabled state mismatch " | |
7563 | "(expected %i, found %i)\n", | |
7564 | !!encoder->base.crtc, enabled); | |
7565 | WARN(active && !encoder->base.crtc, | |
7566 | "active encoder with no crtc\n"); | |
7567 | ||
7568 | WARN(encoder->connectors_active != active, | |
7569 | "encoder's computed active state doesn't match tracked active state " | |
7570 | "(expected %i, found %i)\n", active, encoder->connectors_active); | |
7571 | ||
7572 | active = encoder->get_hw_state(encoder, &pipe); | |
7573 | WARN(active != encoder->connectors_active, | |
7574 | "encoder's hw state doesn't match sw tracking " | |
7575 | "(expected %i, found %i)\n", | |
7576 | encoder->connectors_active, active); | |
7577 | ||
7578 | if (!encoder->base.crtc) | |
7579 | continue; | |
7580 | ||
7581 | tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe; | |
7582 | WARN(active && pipe != tracked_pipe, | |
7583 | "active encoder's pipe doesn't match" | |
7584 | "(expected %i, found %i)\n", | |
7585 | tracked_pipe, pipe); | |
7586 | ||
7587 | } | |
7588 | ||
7589 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, | |
7590 | base.head) { | |
7591 | bool enabled = false; | |
7592 | bool active = false; | |
7593 | ||
7594 | DRM_DEBUG_KMS("[CRTC:%d]\n", | |
7595 | crtc->base.base.id); | |
7596 | ||
7597 | WARN(crtc->active && !crtc->base.enabled, | |
7598 | "active crtc, but not enabled in sw tracking\n"); | |
7599 | ||
7600 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, | |
7601 | base.head) { | |
7602 | if (encoder->base.crtc != &crtc->base) | |
7603 | continue; | |
7604 | enabled = true; | |
7605 | if (encoder->connectors_active) | |
7606 | active = true; | |
7607 | } | |
7608 | WARN(active != crtc->active, | |
7609 | "crtc's computed active state doesn't match tracked active state " | |
7610 | "(expected %i, found %i)\n", active, crtc->active); | |
7611 | WARN(enabled != crtc->base.enabled, | |
7612 | "crtc's computed enabled state doesn't match tracked enabled state " | |
7613 | "(expected %i, found %i)\n", enabled, crtc->base.enabled); | |
7614 | ||
7615 | assert_pipe(dev->dev_private, crtc->pipe, crtc->active); | |
7616 | } | |
7617 | } | |
7618 | ||
c0c36b94 CW |
7619 | int intel_set_mode(struct drm_crtc *crtc, |
7620 | struct drm_display_mode *mode, | |
7621 | int x, int y, struct drm_framebuffer *fb) | |
a6778b3c DV |
7622 | { |
7623 | struct drm_device *dev = crtc->dev; | |
dbf2b54e | 7624 | drm_i915_private_t *dev_priv = dev->dev_private; |
3ac18232 | 7625 | struct drm_display_mode *adjusted_mode, *saved_mode, *saved_hwmode; |
25c5b266 DV |
7626 | struct intel_crtc *intel_crtc; |
7627 | unsigned disable_pipes, prepare_pipes, modeset_pipes; | |
c0c36b94 | 7628 | int ret = 0; |
a6778b3c | 7629 | |
3ac18232 | 7630 | saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL); |
c0c36b94 CW |
7631 | if (!saved_mode) |
7632 | return -ENOMEM; | |
3ac18232 | 7633 | saved_hwmode = saved_mode + 1; |
a6778b3c | 7634 | |
e2e1ed41 | 7635 | intel_modeset_affected_pipes(crtc, &modeset_pipes, |
25c5b266 DV |
7636 | &prepare_pipes, &disable_pipes); |
7637 | ||
7638 | DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n", | |
7639 | modeset_pipes, prepare_pipes, disable_pipes); | |
e2e1ed41 | 7640 | |
976f8a20 DV |
7641 | for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc) |
7642 | intel_crtc_disable(&intel_crtc->base); | |
87f1faa6 | 7643 | |
3ac18232 TG |
7644 | *saved_hwmode = crtc->hwmode; |
7645 | *saved_mode = crtc->mode; | |
a6778b3c | 7646 | |
25c5b266 DV |
7647 | /* Hack: Because we don't (yet) support global modeset on multiple |
7648 | * crtcs, we don't keep track of the new mode for more than one crtc. | |
7649 | * Hence simply check whether any bit is set in modeset_pipes in all the | |
7650 | * pieces of code that are not yet converted to deal with mutliple crtcs | |
7651 | * changing their mode at the same time. */ | |
7652 | adjusted_mode = NULL; | |
7653 | if (modeset_pipes) { | |
7654 | adjusted_mode = intel_modeset_adjusted_mode(crtc, mode); | |
7655 | if (IS_ERR(adjusted_mode)) { | |
c0c36b94 | 7656 | ret = PTR_ERR(adjusted_mode); |
3ac18232 | 7657 | goto out; |
25c5b266 | 7658 | } |
25c5b266 | 7659 | } |
a6778b3c | 7660 | |
ea9d758d DV |
7661 | for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) { |
7662 | if (intel_crtc->base.enabled) | |
7663 | dev_priv->display.crtc_disable(&intel_crtc->base); | |
7664 | } | |
a6778b3c | 7665 | |
6c4c86f5 DV |
7666 | /* crtc->mode is already used by the ->mode_set callbacks, hence we need |
7667 | * to set it here already despite that we pass it down the callchain. | |
f6e5b160 | 7668 | */ |
6c4c86f5 | 7669 | if (modeset_pipes) |
25c5b266 | 7670 | crtc->mode = *mode; |
7758a113 | 7671 | |
ea9d758d DV |
7672 | /* Only after disabling all output pipelines that will be changed can we |
7673 | * update the the output configuration. */ | |
7674 | intel_modeset_update_state(dev, prepare_pipes); | |
f6e5b160 | 7675 | |
47fab737 DV |
7676 | if (dev_priv->display.modeset_global_resources) |
7677 | dev_priv->display.modeset_global_resources(dev); | |
7678 | ||
a6778b3c DV |
7679 | /* Set up the DPLL and any encoders state that needs to adjust or depend |
7680 | * on the DPLL. | |
f6e5b160 | 7681 | */ |
25c5b266 | 7682 | for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) { |
c0c36b94 CW |
7683 | ret = intel_crtc_mode_set(&intel_crtc->base, |
7684 | mode, adjusted_mode, | |
7685 | x, y, fb); | |
7686 | if (ret) | |
7687 | goto done; | |
a6778b3c DV |
7688 | } |
7689 | ||
7690 | /* Now enable the clocks, plane, pipe, and connectors that we set up. */ | |
25c5b266 DV |
7691 | for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) |
7692 | dev_priv->display.crtc_enable(&intel_crtc->base); | |
a6778b3c | 7693 | |
25c5b266 DV |
7694 | if (modeset_pipes) { |
7695 | /* Store real post-adjustment hardware mode. */ | |
7696 | crtc->hwmode = *adjusted_mode; | |
a6778b3c | 7697 | |
25c5b266 DV |
7698 | /* Calculate and store various constants which |
7699 | * are later needed by vblank and swap-completion | |
7700 | * timestamping. They are derived from true hwmode. | |
7701 | */ | |
7702 | drm_calc_timestamping_constants(crtc); | |
7703 | } | |
a6778b3c DV |
7704 | |
7705 | /* FIXME: add subpixel order */ | |
7706 | done: | |
7707 | drm_mode_destroy(dev, adjusted_mode); | |
c0c36b94 | 7708 | if (ret && crtc->enabled) { |
3ac18232 TG |
7709 | crtc->hwmode = *saved_hwmode; |
7710 | crtc->mode = *saved_mode; | |
8af6cf88 DV |
7711 | } else { |
7712 | intel_modeset_check_state(dev); | |
a6778b3c DV |
7713 | } |
7714 | ||
3ac18232 TG |
7715 | out: |
7716 | kfree(saved_mode); | |
a6778b3c | 7717 | return ret; |
f6e5b160 CW |
7718 | } |
7719 | ||
c0c36b94 CW |
7720 | void intel_crtc_restore_mode(struct drm_crtc *crtc) |
7721 | { | |
7722 | intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb); | |
7723 | } | |
7724 | ||
25c5b266 DV |
7725 | #undef for_each_intel_crtc_masked |
7726 | ||
d9e55608 DV |
7727 | static void intel_set_config_free(struct intel_set_config *config) |
7728 | { | |
7729 | if (!config) | |
7730 | return; | |
7731 | ||
1aa4b628 DV |
7732 | kfree(config->save_connector_encoders); |
7733 | kfree(config->save_encoder_crtcs); | |
d9e55608 DV |
7734 | kfree(config); |
7735 | } | |
7736 | ||
85f9eb71 DV |
7737 | static int intel_set_config_save_state(struct drm_device *dev, |
7738 | struct intel_set_config *config) | |
7739 | { | |
85f9eb71 DV |
7740 | struct drm_encoder *encoder; |
7741 | struct drm_connector *connector; | |
7742 | int count; | |
7743 | ||
1aa4b628 DV |
7744 | config->save_encoder_crtcs = |
7745 | kcalloc(dev->mode_config.num_encoder, | |
7746 | sizeof(struct drm_crtc *), GFP_KERNEL); | |
7747 | if (!config->save_encoder_crtcs) | |
85f9eb71 DV |
7748 | return -ENOMEM; |
7749 | ||
1aa4b628 DV |
7750 | config->save_connector_encoders = |
7751 | kcalloc(dev->mode_config.num_connector, | |
7752 | sizeof(struct drm_encoder *), GFP_KERNEL); | |
7753 | if (!config->save_connector_encoders) | |
85f9eb71 DV |
7754 | return -ENOMEM; |
7755 | ||
7756 | /* Copy data. Note that driver private data is not affected. | |
7757 | * Should anything bad happen only the expected state is | |
7758 | * restored, not the drivers personal bookkeeping. | |
7759 | */ | |
85f9eb71 DV |
7760 | count = 0; |
7761 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { | |
1aa4b628 | 7762 | config->save_encoder_crtcs[count++] = encoder->crtc; |
85f9eb71 DV |
7763 | } |
7764 | ||
7765 | count = 0; | |
7766 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
1aa4b628 | 7767 | config->save_connector_encoders[count++] = connector->encoder; |
85f9eb71 DV |
7768 | } |
7769 | ||
7770 | return 0; | |
7771 | } | |
7772 | ||
7773 | static void intel_set_config_restore_state(struct drm_device *dev, | |
7774 | struct intel_set_config *config) | |
7775 | { | |
9a935856 DV |
7776 | struct intel_encoder *encoder; |
7777 | struct intel_connector *connector; | |
85f9eb71 DV |
7778 | int count; |
7779 | ||
85f9eb71 | 7780 | count = 0; |
9a935856 DV |
7781 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { |
7782 | encoder->new_crtc = | |
7783 | to_intel_crtc(config->save_encoder_crtcs[count++]); | |
85f9eb71 DV |
7784 | } |
7785 | ||
7786 | count = 0; | |
9a935856 DV |
7787 | list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) { |
7788 | connector->new_encoder = | |
7789 | to_intel_encoder(config->save_connector_encoders[count++]); | |
85f9eb71 DV |
7790 | } |
7791 | } | |
7792 | ||
5e2b584e DV |
7793 | static void |
7794 | intel_set_config_compute_mode_changes(struct drm_mode_set *set, | |
7795 | struct intel_set_config *config) | |
7796 | { | |
7797 | ||
7798 | /* We should be able to check here if the fb has the same properties | |
7799 | * and then just flip_or_move it */ | |
7800 | if (set->crtc->fb != set->fb) { | |
7801 | /* If we have no fb then treat it as a full mode set */ | |
7802 | if (set->crtc->fb == NULL) { | |
7803 | DRM_DEBUG_KMS("crtc has no fb, full mode set\n"); | |
7804 | config->mode_changed = true; | |
7805 | } else if (set->fb == NULL) { | |
7806 | config->mode_changed = true; | |
7807 | } else if (set->fb->depth != set->crtc->fb->depth) { | |
7808 | config->mode_changed = true; | |
7809 | } else if (set->fb->bits_per_pixel != | |
7810 | set->crtc->fb->bits_per_pixel) { | |
7811 | config->mode_changed = true; | |
7812 | } else | |
7813 | config->fb_changed = true; | |
7814 | } | |
7815 | ||
835c5873 | 7816 | if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y)) |
5e2b584e DV |
7817 | config->fb_changed = true; |
7818 | ||
7819 | if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) { | |
7820 | DRM_DEBUG_KMS("modes are different, full mode set\n"); | |
7821 | drm_mode_debug_printmodeline(&set->crtc->mode); | |
7822 | drm_mode_debug_printmodeline(set->mode); | |
7823 | config->mode_changed = true; | |
7824 | } | |
7825 | } | |
7826 | ||
2e431051 | 7827 | static int |
9a935856 DV |
7828 | intel_modeset_stage_output_state(struct drm_device *dev, |
7829 | struct drm_mode_set *set, | |
7830 | struct intel_set_config *config) | |
50f56119 | 7831 | { |
85f9eb71 | 7832 | struct drm_crtc *new_crtc; |
9a935856 DV |
7833 | struct intel_connector *connector; |
7834 | struct intel_encoder *encoder; | |
2e431051 | 7835 | int count, ro; |
50f56119 | 7836 | |
9a935856 DV |
7837 | /* The upper layers ensure that we either disabl a crtc or have a list |
7838 | * of connectors. For paranoia, double-check this. */ | |
7839 | WARN_ON(!set->fb && (set->num_connectors != 0)); | |
7840 | WARN_ON(set->fb && (set->num_connectors == 0)); | |
7841 | ||
50f56119 | 7842 | count = 0; |
9a935856 DV |
7843 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
7844 | base.head) { | |
7845 | /* Otherwise traverse passed in connector list and get encoders | |
7846 | * for them. */ | |
50f56119 | 7847 | for (ro = 0; ro < set->num_connectors; ro++) { |
9a935856 DV |
7848 | if (set->connectors[ro] == &connector->base) { |
7849 | connector->new_encoder = connector->encoder; | |
50f56119 DV |
7850 | break; |
7851 | } | |
7852 | } | |
7853 | ||
9a935856 DV |
7854 | /* If we disable the crtc, disable all its connectors. Also, if |
7855 | * the connector is on the changing crtc but not on the new | |
7856 | * connector list, disable it. */ | |
7857 | if ((!set->fb || ro == set->num_connectors) && | |
7858 | connector->base.encoder && | |
7859 | connector->base.encoder->crtc == set->crtc) { | |
7860 | connector->new_encoder = NULL; | |
7861 | ||
7862 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n", | |
7863 | connector->base.base.id, | |
7864 | drm_get_connector_name(&connector->base)); | |
7865 | } | |
7866 | ||
7867 | ||
7868 | if (&connector->new_encoder->base != connector->base.encoder) { | |
50f56119 | 7869 | DRM_DEBUG_KMS("encoder changed, full mode switch\n"); |
5e2b584e | 7870 | config->mode_changed = true; |
50f56119 DV |
7871 | } |
7872 | } | |
9a935856 | 7873 | /* connector->new_encoder is now updated for all connectors. */ |
50f56119 | 7874 | |
9a935856 | 7875 | /* Update crtc of enabled connectors. */ |
50f56119 | 7876 | count = 0; |
9a935856 DV |
7877 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
7878 | base.head) { | |
7879 | if (!connector->new_encoder) | |
50f56119 DV |
7880 | continue; |
7881 | ||
9a935856 | 7882 | new_crtc = connector->new_encoder->base.crtc; |
50f56119 DV |
7883 | |
7884 | for (ro = 0; ro < set->num_connectors; ro++) { | |
9a935856 | 7885 | if (set->connectors[ro] == &connector->base) |
50f56119 DV |
7886 | new_crtc = set->crtc; |
7887 | } | |
7888 | ||
7889 | /* Make sure the new CRTC will work with the encoder */ | |
9a935856 DV |
7890 | if (!intel_encoder_crtc_ok(&connector->new_encoder->base, |
7891 | new_crtc)) { | |
5e2b584e | 7892 | return -EINVAL; |
50f56119 | 7893 | } |
9a935856 DV |
7894 | connector->encoder->new_crtc = to_intel_crtc(new_crtc); |
7895 | ||
7896 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n", | |
7897 | connector->base.base.id, | |
7898 | drm_get_connector_name(&connector->base), | |
7899 | new_crtc->base.id); | |
7900 | } | |
7901 | ||
7902 | /* Check for any encoders that needs to be disabled. */ | |
7903 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, | |
7904 | base.head) { | |
7905 | list_for_each_entry(connector, | |
7906 | &dev->mode_config.connector_list, | |
7907 | base.head) { | |
7908 | if (connector->new_encoder == encoder) { | |
7909 | WARN_ON(!connector->new_encoder->new_crtc); | |
7910 | ||
7911 | goto next_encoder; | |
7912 | } | |
7913 | } | |
7914 | encoder->new_crtc = NULL; | |
7915 | next_encoder: | |
7916 | /* Only now check for crtc changes so we don't miss encoders | |
7917 | * that will be disabled. */ | |
7918 | if (&encoder->new_crtc->base != encoder->base.crtc) { | |
50f56119 | 7919 | DRM_DEBUG_KMS("crtc changed, full mode switch\n"); |
5e2b584e | 7920 | config->mode_changed = true; |
50f56119 DV |
7921 | } |
7922 | } | |
9a935856 | 7923 | /* Now we've also updated encoder->new_crtc for all encoders. */ |
50f56119 | 7924 | |
2e431051 DV |
7925 | return 0; |
7926 | } | |
7927 | ||
7928 | static int intel_crtc_set_config(struct drm_mode_set *set) | |
7929 | { | |
7930 | struct drm_device *dev; | |
2e431051 DV |
7931 | struct drm_mode_set save_set; |
7932 | struct intel_set_config *config; | |
7933 | int ret; | |
2e431051 | 7934 | |
8d3e375e DV |
7935 | BUG_ON(!set); |
7936 | BUG_ON(!set->crtc); | |
7937 | BUG_ON(!set->crtc->helper_private); | |
2e431051 DV |
7938 | |
7939 | if (!set->mode) | |
7940 | set->fb = NULL; | |
7941 | ||
431e50f7 DV |
7942 | /* The fb helper likes to play gross jokes with ->mode_set_config. |
7943 | * Unfortunately the crtc helper doesn't do much at all for this case, | |
7944 | * so we have to cope with this madness until the fb helper is fixed up. */ | |
7945 | if (set->fb && set->num_connectors == 0) | |
7946 | return 0; | |
7947 | ||
2e431051 DV |
7948 | if (set->fb) { |
7949 | DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n", | |
7950 | set->crtc->base.id, set->fb->base.id, | |
7951 | (int)set->num_connectors, set->x, set->y); | |
7952 | } else { | |
7953 | DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id); | |
2e431051 DV |
7954 | } |
7955 | ||
7956 | dev = set->crtc->dev; | |
7957 | ||
7958 | ret = -ENOMEM; | |
7959 | config = kzalloc(sizeof(*config), GFP_KERNEL); | |
7960 | if (!config) | |
7961 | goto out_config; | |
7962 | ||
7963 | ret = intel_set_config_save_state(dev, config); | |
7964 | if (ret) | |
7965 | goto out_config; | |
7966 | ||
7967 | save_set.crtc = set->crtc; | |
7968 | save_set.mode = &set->crtc->mode; | |
7969 | save_set.x = set->crtc->x; | |
7970 | save_set.y = set->crtc->y; | |
7971 | save_set.fb = set->crtc->fb; | |
7972 | ||
7973 | /* Compute whether we need a full modeset, only an fb base update or no | |
7974 | * change at all. In the future we might also check whether only the | |
7975 | * mode changed, e.g. for LVDS where we only change the panel fitter in | |
7976 | * such cases. */ | |
7977 | intel_set_config_compute_mode_changes(set, config); | |
7978 | ||
9a935856 | 7979 | ret = intel_modeset_stage_output_state(dev, set, config); |
2e431051 DV |
7980 | if (ret) |
7981 | goto fail; | |
7982 | ||
5e2b584e | 7983 | if (config->mode_changed) { |
87f1faa6 | 7984 | if (set->mode) { |
50f56119 DV |
7985 | DRM_DEBUG_KMS("attempting to set mode from" |
7986 | " userspace\n"); | |
7987 | drm_mode_debug_printmodeline(set->mode); | |
87f1faa6 DV |
7988 | } |
7989 | ||
c0c36b94 CW |
7990 | ret = intel_set_mode(set->crtc, set->mode, |
7991 | set->x, set->y, set->fb); | |
7992 | if (ret) { | |
7993 | DRM_ERROR("failed to set mode on [CRTC:%d], err = %d\n", | |
7994 | set->crtc->base.id, ret); | |
87f1faa6 DV |
7995 | goto fail; |
7996 | } | |
5e2b584e | 7997 | } else if (config->fb_changed) { |
4f660f49 | 7998 | ret = intel_pipe_set_base(set->crtc, |
94352cf9 | 7999 | set->x, set->y, set->fb); |
50f56119 DV |
8000 | } |
8001 | ||
d9e55608 DV |
8002 | intel_set_config_free(config); |
8003 | ||
50f56119 DV |
8004 | return 0; |
8005 | ||
8006 | fail: | |
85f9eb71 | 8007 | intel_set_config_restore_state(dev, config); |
50f56119 DV |
8008 | |
8009 | /* Try to restore the config */ | |
5e2b584e | 8010 | if (config->mode_changed && |
c0c36b94 CW |
8011 | intel_set_mode(save_set.crtc, save_set.mode, |
8012 | save_set.x, save_set.y, save_set.fb)) | |
50f56119 DV |
8013 | DRM_ERROR("failed to restore config after modeset failure\n"); |
8014 | ||
d9e55608 DV |
8015 | out_config: |
8016 | intel_set_config_free(config); | |
50f56119 DV |
8017 | return ret; |
8018 | } | |
f6e5b160 CW |
8019 | |
8020 | static const struct drm_crtc_funcs intel_crtc_funcs = { | |
f6e5b160 CW |
8021 | .cursor_set = intel_crtc_cursor_set, |
8022 | .cursor_move = intel_crtc_cursor_move, | |
8023 | .gamma_set = intel_crtc_gamma_set, | |
50f56119 | 8024 | .set_config = intel_crtc_set_config, |
f6e5b160 CW |
8025 | .destroy = intel_crtc_destroy, |
8026 | .page_flip = intel_crtc_page_flip, | |
8027 | }; | |
8028 | ||
79f689aa PZ |
8029 | static void intel_cpu_pll_init(struct drm_device *dev) |
8030 | { | |
affa9354 | 8031 | if (HAS_DDI(dev)) |
79f689aa PZ |
8032 | intel_ddi_pll_init(dev); |
8033 | } | |
8034 | ||
ee7b9f93 JB |
8035 | static void intel_pch_pll_init(struct drm_device *dev) |
8036 | { | |
8037 | drm_i915_private_t *dev_priv = dev->dev_private; | |
8038 | int i; | |
8039 | ||
8040 | if (dev_priv->num_pch_pll == 0) { | |
8041 | DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n"); | |
8042 | return; | |
8043 | } | |
8044 | ||
8045 | for (i = 0; i < dev_priv->num_pch_pll; i++) { | |
8046 | dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i); | |
8047 | dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i); | |
8048 | dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i); | |
8049 | } | |
8050 | } | |
8051 | ||
b358d0a6 | 8052 | static void intel_crtc_init(struct drm_device *dev, int pipe) |
79e53945 | 8053 | { |
22fd0fab | 8054 | drm_i915_private_t *dev_priv = dev->dev_private; |
79e53945 JB |
8055 | struct intel_crtc *intel_crtc; |
8056 | int i; | |
8057 | ||
8058 | intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL); | |
8059 | if (intel_crtc == NULL) | |
8060 | return; | |
8061 | ||
8062 | drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs); | |
8063 | ||
8064 | drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256); | |
79e53945 JB |
8065 | for (i = 0; i < 256; i++) { |
8066 | intel_crtc->lut_r[i] = i; | |
8067 | intel_crtc->lut_g[i] = i; | |
8068 | intel_crtc->lut_b[i] = i; | |
8069 | } | |
8070 | ||
80824003 JB |
8071 | /* Swap pipes & planes for FBC on pre-965 */ |
8072 | intel_crtc->pipe = pipe; | |
8073 | intel_crtc->plane = pipe; | |
a5c961d1 | 8074 | intel_crtc->cpu_transcoder = pipe; |
e2e767ab | 8075 | if (IS_MOBILE(dev) && IS_GEN3(dev)) { |
28c97730 | 8076 | DRM_DEBUG_KMS("swapping pipes & planes for FBC\n"); |
e2e767ab | 8077 | intel_crtc->plane = !pipe; |
80824003 JB |
8078 | } |
8079 | ||
22fd0fab JB |
8080 | BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || |
8081 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL); | |
8082 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base; | |
8083 | dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base; | |
8084 | ||
5a354204 | 8085 | intel_crtc->bpp = 24; /* default for pre-Ironlake */ |
7e7d76c3 | 8086 | |
79e53945 | 8087 | drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); |
79e53945 JB |
8088 | } |
8089 | ||
08d7b3d1 | 8090 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
05394f39 | 8091 | struct drm_file *file) |
08d7b3d1 | 8092 | { |
08d7b3d1 | 8093 | struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; |
c05422d5 DV |
8094 | struct drm_mode_object *drmmode_obj; |
8095 | struct intel_crtc *crtc; | |
08d7b3d1 | 8096 | |
1cff8f6b DV |
8097 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
8098 | return -ENODEV; | |
08d7b3d1 | 8099 | |
c05422d5 DV |
8100 | drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id, |
8101 | DRM_MODE_OBJECT_CRTC); | |
08d7b3d1 | 8102 | |
c05422d5 | 8103 | if (!drmmode_obj) { |
08d7b3d1 CW |
8104 | DRM_ERROR("no such CRTC id\n"); |
8105 | return -EINVAL; | |
8106 | } | |
8107 | ||
c05422d5 DV |
8108 | crtc = to_intel_crtc(obj_to_crtc(drmmode_obj)); |
8109 | pipe_from_crtc_id->pipe = crtc->pipe; | |
08d7b3d1 | 8110 | |
c05422d5 | 8111 | return 0; |
08d7b3d1 CW |
8112 | } |
8113 | ||
66a9278e | 8114 | static int intel_encoder_clones(struct intel_encoder *encoder) |
79e53945 | 8115 | { |
66a9278e DV |
8116 | struct drm_device *dev = encoder->base.dev; |
8117 | struct intel_encoder *source_encoder; | |
79e53945 | 8118 | int index_mask = 0; |
79e53945 JB |
8119 | int entry = 0; |
8120 | ||
66a9278e DV |
8121 | list_for_each_entry(source_encoder, |
8122 | &dev->mode_config.encoder_list, base.head) { | |
8123 | ||
8124 | if (encoder == source_encoder) | |
79e53945 | 8125 | index_mask |= (1 << entry); |
66a9278e DV |
8126 | |
8127 | /* Intel hw has only one MUX where enocoders could be cloned. */ | |
8128 | if (encoder->cloneable && source_encoder->cloneable) | |
8129 | index_mask |= (1 << entry); | |
8130 | ||
79e53945 JB |
8131 | entry++; |
8132 | } | |
4ef69c7a | 8133 | |
79e53945 JB |
8134 | return index_mask; |
8135 | } | |
8136 | ||
4d302442 CW |
8137 | static bool has_edp_a(struct drm_device *dev) |
8138 | { | |
8139 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8140 | ||
8141 | if (!IS_MOBILE(dev)) | |
8142 | return false; | |
8143 | ||
8144 | if ((I915_READ(DP_A) & DP_DETECTED) == 0) | |
8145 | return false; | |
8146 | ||
8147 | if (IS_GEN5(dev) && | |
8148 | (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE)) | |
8149 | return false; | |
8150 | ||
8151 | return true; | |
8152 | } | |
8153 | ||
79e53945 JB |
8154 | static void intel_setup_outputs(struct drm_device *dev) |
8155 | { | |
725e30ad | 8156 | struct drm_i915_private *dev_priv = dev->dev_private; |
4ef69c7a | 8157 | struct intel_encoder *encoder; |
cb0953d7 | 8158 | bool dpd_is_edp = false; |
f3cfcba6 | 8159 | bool has_lvds; |
79e53945 | 8160 | |
f3cfcba6 | 8161 | has_lvds = intel_lvds_init(dev); |
c5d1b51d CW |
8162 | if (!has_lvds && !HAS_PCH_SPLIT(dev)) { |
8163 | /* disable the panel fitter on everything but LVDS */ | |
8164 | I915_WRITE(PFIT_CONTROL, 0); | |
8165 | } | |
79e53945 | 8166 | |
affa9354 | 8167 | if (!(HAS_DDI(dev) && (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES))) |
79935fca | 8168 | intel_crt_init(dev); |
cb0953d7 | 8169 | |
affa9354 | 8170 | if (HAS_DDI(dev)) { |
0e72a5b5 ED |
8171 | int found; |
8172 | ||
8173 | /* Haswell uses DDI functions to detect digital outputs */ | |
8174 | found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED; | |
8175 | /* DDI A only supports eDP */ | |
8176 | if (found) | |
8177 | intel_ddi_init(dev, PORT_A); | |
8178 | ||
8179 | /* DDI B, C and D detection is indicated by the SFUSE_STRAP | |
8180 | * register */ | |
8181 | found = I915_READ(SFUSE_STRAP); | |
8182 | ||
8183 | if (found & SFUSE_STRAP_DDIB_DETECTED) | |
8184 | intel_ddi_init(dev, PORT_B); | |
8185 | if (found & SFUSE_STRAP_DDIC_DETECTED) | |
8186 | intel_ddi_init(dev, PORT_C); | |
8187 | if (found & SFUSE_STRAP_DDID_DETECTED) | |
8188 | intel_ddi_init(dev, PORT_D); | |
8189 | } else if (HAS_PCH_SPLIT(dev)) { | |
cb0953d7 | 8190 | int found; |
270b3042 DV |
8191 | dpd_is_edp = intel_dpd_is_edp(dev); |
8192 | ||
8193 | if (has_edp_a(dev)) | |
8194 | intel_dp_init(dev, DP_A, PORT_A); | |
cb0953d7 | 8195 | |
30ad48b7 | 8196 | if (I915_READ(HDMIB) & PORT_DETECTED) { |
461ed3ca | 8197 | /* PCH SDVOB multiplex with HDMIB */ |
eef4eacb | 8198 | found = intel_sdvo_init(dev, PCH_SDVOB, true); |
30ad48b7 | 8199 | if (!found) |
08d644ad | 8200 | intel_hdmi_init(dev, HDMIB, PORT_B); |
5eb08b69 | 8201 | if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED)) |
ab9d7c30 | 8202 | intel_dp_init(dev, PCH_DP_B, PORT_B); |
30ad48b7 ZW |
8203 | } |
8204 | ||
8205 | if (I915_READ(HDMIC) & PORT_DETECTED) | |
08d644ad | 8206 | intel_hdmi_init(dev, HDMIC, PORT_C); |
30ad48b7 | 8207 | |
b708a1d5 | 8208 | if (!dpd_is_edp && I915_READ(HDMID) & PORT_DETECTED) |
08d644ad | 8209 | intel_hdmi_init(dev, HDMID, PORT_D); |
30ad48b7 | 8210 | |
5eb08b69 | 8211 | if (I915_READ(PCH_DP_C) & DP_DETECTED) |
ab9d7c30 | 8212 | intel_dp_init(dev, PCH_DP_C, PORT_C); |
5eb08b69 | 8213 | |
270b3042 | 8214 | if (I915_READ(PCH_DP_D) & DP_DETECTED) |
ab9d7c30 | 8215 | intel_dp_init(dev, PCH_DP_D, PORT_D); |
4a87d65d JB |
8216 | } else if (IS_VALLEYVIEW(dev)) { |
8217 | int found; | |
8218 | ||
19c03924 GB |
8219 | /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */ |
8220 | if (I915_READ(DP_C) & DP_DETECTED) | |
8221 | intel_dp_init(dev, DP_C, PORT_C); | |
8222 | ||
4a87d65d JB |
8223 | if (I915_READ(SDVOB) & PORT_DETECTED) { |
8224 | /* SDVOB multiplex with HDMIB */ | |
8225 | found = intel_sdvo_init(dev, SDVOB, true); | |
8226 | if (!found) | |
08d644ad | 8227 | intel_hdmi_init(dev, SDVOB, PORT_B); |
4a87d65d | 8228 | if (!found && (I915_READ(DP_B) & DP_DETECTED)) |
ab9d7c30 | 8229 | intel_dp_init(dev, DP_B, PORT_B); |
4a87d65d JB |
8230 | } |
8231 | ||
8232 | if (I915_READ(SDVOC) & PORT_DETECTED) | |
08d644ad | 8233 | intel_hdmi_init(dev, SDVOC, PORT_C); |
5eb08b69 | 8234 | |
103a196f | 8235 | } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) { |
27185ae1 | 8236 | bool found = false; |
7d57382e | 8237 | |
725e30ad | 8238 | if (I915_READ(SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 8239 | DRM_DEBUG_KMS("probing SDVOB\n"); |
eef4eacb | 8240 | found = intel_sdvo_init(dev, SDVOB, true); |
b01f2c3a JB |
8241 | if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) { |
8242 | DRM_DEBUG_KMS("probing HDMI on SDVOB\n"); | |
08d644ad | 8243 | intel_hdmi_init(dev, SDVOB, PORT_B); |
b01f2c3a | 8244 | } |
27185ae1 | 8245 | |
b01f2c3a JB |
8246 | if (!found && SUPPORTS_INTEGRATED_DP(dev)) { |
8247 | DRM_DEBUG_KMS("probing DP_B\n"); | |
ab9d7c30 | 8248 | intel_dp_init(dev, DP_B, PORT_B); |
b01f2c3a | 8249 | } |
725e30ad | 8250 | } |
13520b05 KH |
8251 | |
8252 | /* Before G4X SDVOC doesn't have its own detect register */ | |
13520b05 | 8253 | |
b01f2c3a JB |
8254 | if (I915_READ(SDVOB) & SDVO_DETECTED) { |
8255 | DRM_DEBUG_KMS("probing SDVOC\n"); | |
eef4eacb | 8256 | found = intel_sdvo_init(dev, SDVOC, false); |
b01f2c3a | 8257 | } |
27185ae1 ML |
8258 | |
8259 | if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) { | |
8260 | ||
b01f2c3a JB |
8261 | if (SUPPORTS_INTEGRATED_HDMI(dev)) { |
8262 | DRM_DEBUG_KMS("probing HDMI on SDVOC\n"); | |
08d644ad | 8263 | intel_hdmi_init(dev, SDVOC, PORT_C); |
b01f2c3a JB |
8264 | } |
8265 | if (SUPPORTS_INTEGRATED_DP(dev)) { | |
8266 | DRM_DEBUG_KMS("probing DP_C\n"); | |
ab9d7c30 | 8267 | intel_dp_init(dev, DP_C, PORT_C); |
b01f2c3a | 8268 | } |
725e30ad | 8269 | } |
27185ae1 | 8270 | |
b01f2c3a JB |
8271 | if (SUPPORTS_INTEGRATED_DP(dev) && |
8272 | (I915_READ(DP_D) & DP_DETECTED)) { | |
8273 | DRM_DEBUG_KMS("probing DP_D\n"); | |
ab9d7c30 | 8274 | intel_dp_init(dev, DP_D, PORT_D); |
b01f2c3a | 8275 | } |
bad720ff | 8276 | } else if (IS_GEN2(dev)) |
79e53945 JB |
8277 | intel_dvo_init(dev); |
8278 | ||
103a196f | 8279 | if (SUPPORTS_TV(dev)) |
79e53945 JB |
8280 | intel_tv_init(dev); |
8281 | ||
4ef69c7a CW |
8282 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { |
8283 | encoder->base.possible_crtcs = encoder->crtc_mask; | |
8284 | encoder->base.possible_clones = | |
66a9278e | 8285 | intel_encoder_clones(encoder); |
79e53945 | 8286 | } |
47356eb6 | 8287 | |
dde86e2d | 8288 | intel_init_pch_refclk(dev); |
270b3042 DV |
8289 | |
8290 | drm_helper_move_panel_connectors_to_head(dev); | |
79e53945 JB |
8291 | } |
8292 | ||
8293 | static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb) | |
8294 | { | |
8295 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
79e53945 JB |
8296 | |
8297 | drm_framebuffer_cleanup(fb); | |
05394f39 | 8298 | drm_gem_object_unreference_unlocked(&intel_fb->obj->base); |
79e53945 JB |
8299 | |
8300 | kfree(intel_fb); | |
8301 | } | |
8302 | ||
8303 | static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb, | |
05394f39 | 8304 | struct drm_file *file, |
79e53945 JB |
8305 | unsigned int *handle) |
8306 | { | |
8307 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
05394f39 | 8308 | struct drm_i915_gem_object *obj = intel_fb->obj; |
79e53945 | 8309 | |
05394f39 | 8310 | return drm_gem_handle_create(file, &obj->base, handle); |
79e53945 JB |
8311 | } |
8312 | ||
8313 | static const struct drm_framebuffer_funcs intel_fb_funcs = { | |
8314 | .destroy = intel_user_framebuffer_destroy, | |
8315 | .create_handle = intel_user_framebuffer_create_handle, | |
8316 | }; | |
8317 | ||
38651674 DA |
8318 | int intel_framebuffer_init(struct drm_device *dev, |
8319 | struct intel_framebuffer *intel_fb, | |
308e5bcb | 8320 | struct drm_mode_fb_cmd2 *mode_cmd, |
05394f39 | 8321 | struct drm_i915_gem_object *obj) |
79e53945 | 8322 | { |
79e53945 JB |
8323 | int ret; |
8324 | ||
05394f39 | 8325 | if (obj->tiling_mode == I915_TILING_Y) |
57cd6508 CW |
8326 | return -EINVAL; |
8327 | ||
308e5bcb | 8328 | if (mode_cmd->pitches[0] & 63) |
57cd6508 CW |
8329 | return -EINVAL; |
8330 | ||
5d7bd705 VS |
8331 | /* FIXME <= Gen4 stride limits are bit unclear */ |
8332 | if (mode_cmd->pitches[0] > 32768) | |
8333 | return -EINVAL; | |
8334 | ||
8335 | if (obj->tiling_mode != I915_TILING_NONE && | |
8336 | mode_cmd->pitches[0] != obj->stride) | |
8337 | return -EINVAL; | |
8338 | ||
57779d06 | 8339 | /* Reject formats not supported by any plane early. */ |
308e5bcb | 8340 | switch (mode_cmd->pixel_format) { |
57779d06 | 8341 | case DRM_FORMAT_C8: |
04b3924d VS |
8342 | case DRM_FORMAT_RGB565: |
8343 | case DRM_FORMAT_XRGB8888: | |
8344 | case DRM_FORMAT_ARGB8888: | |
57779d06 VS |
8345 | break; |
8346 | case DRM_FORMAT_XRGB1555: | |
8347 | case DRM_FORMAT_ARGB1555: | |
8348 | if (INTEL_INFO(dev)->gen > 3) | |
8349 | return -EINVAL; | |
8350 | break; | |
8351 | case DRM_FORMAT_XBGR8888: | |
8352 | case DRM_FORMAT_ABGR8888: | |
04b3924d VS |
8353 | case DRM_FORMAT_XRGB2101010: |
8354 | case DRM_FORMAT_ARGB2101010: | |
57779d06 VS |
8355 | case DRM_FORMAT_XBGR2101010: |
8356 | case DRM_FORMAT_ABGR2101010: | |
8357 | if (INTEL_INFO(dev)->gen < 4) | |
8358 | return -EINVAL; | |
b5626747 | 8359 | break; |
04b3924d VS |
8360 | case DRM_FORMAT_YUYV: |
8361 | case DRM_FORMAT_UYVY: | |
8362 | case DRM_FORMAT_YVYU: | |
8363 | case DRM_FORMAT_VYUY: | |
57779d06 VS |
8364 | if (INTEL_INFO(dev)->gen < 6) |
8365 | return -EINVAL; | |
57cd6508 CW |
8366 | break; |
8367 | default: | |
57779d06 | 8368 | DRM_DEBUG_KMS("unsupported pixel format 0x%08x\n", mode_cmd->pixel_format); |
57cd6508 CW |
8369 | return -EINVAL; |
8370 | } | |
8371 | ||
90f9a336 VS |
8372 | /* FIXME need to adjust LINOFF/TILEOFF accordingly. */ |
8373 | if (mode_cmd->offsets[0] != 0) | |
8374 | return -EINVAL; | |
8375 | ||
79e53945 JB |
8376 | ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs); |
8377 | if (ret) { | |
8378 | DRM_ERROR("framebuffer init failed %d\n", ret); | |
8379 | return ret; | |
8380 | } | |
8381 | ||
8382 | drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd); | |
79e53945 | 8383 | intel_fb->obj = obj; |
79e53945 JB |
8384 | return 0; |
8385 | } | |
8386 | ||
79e53945 JB |
8387 | static struct drm_framebuffer * |
8388 | intel_user_framebuffer_create(struct drm_device *dev, | |
8389 | struct drm_file *filp, | |
308e5bcb | 8390 | struct drm_mode_fb_cmd2 *mode_cmd) |
79e53945 | 8391 | { |
05394f39 | 8392 | struct drm_i915_gem_object *obj; |
79e53945 | 8393 | |
308e5bcb JB |
8394 | obj = to_intel_bo(drm_gem_object_lookup(dev, filp, |
8395 | mode_cmd->handles[0])); | |
c8725226 | 8396 | if (&obj->base == NULL) |
cce13ff7 | 8397 | return ERR_PTR(-ENOENT); |
79e53945 | 8398 | |
d2dff872 | 8399 | return intel_framebuffer_create(dev, mode_cmd, obj); |
79e53945 JB |
8400 | } |
8401 | ||
79e53945 | 8402 | static const struct drm_mode_config_funcs intel_mode_funcs = { |
79e53945 | 8403 | .fb_create = intel_user_framebuffer_create, |
eb1f8e4f | 8404 | .output_poll_changed = intel_fb_output_poll_changed, |
79e53945 JB |
8405 | }; |
8406 | ||
e70236a8 JB |
8407 | /* Set up chip specific display functions */ |
8408 | static void intel_init_display(struct drm_device *dev) | |
8409 | { | |
8410 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8411 | ||
8412 | /* We always want a DPMS function */ | |
affa9354 | 8413 | if (HAS_DDI(dev)) { |
09b4ddf9 | 8414 | dev_priv->display.crtc_mode_set = haswell_crtc_mode_set; |
4f771f10 PZ |
8415 | dev_priv->display.crtc_enable = haswell_crtc_enable; |
8416 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
6441ab5f | 8417 | dev_priv->display.off = haswell_crtc_off; |
09b4ddf9 PZ |
8418 | dev_priv->display.update_plane = ironlake_update_plane; |
8419 | } else if (HAS_PCH_SPLIT(dev)) { | |
f564048e | 8420 | dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set; |
76e5a89c DV |
8421 | dev_priv->display.crtc_enable = ironlake_crtc_enable; |
8422 | dev_priv->display.crtc_disable = ironlake_crtc_disable; | |
ee7b9f93 | 8423 | dev_priv->display.off = ironlake_crtc_off; |
17638cd6 | 8424 | dev_priv->display.update_plane = ironlake_update_plane; |
f564048e | 8425 | } else { |
f564048e | 8426 | dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set; |
76e5a89c DV |
8427 | dev_priv->display.crtc_enable = i9xx_crtc_enable; |
8428 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
ee7b9f93 | 8429 | dev_priv->display.off = i9xx_crtc_off; |
17638cd6 | 8430 | dev_priv->display.update_plane = i9xx_update_plane; |
f564048e | 8431 | } |
e70236a8 | 8432 | |
e70236a8 | 8433 | /* Returns the core display clock speed */ |
25eb05fc JB |
8434 | if (IS_VALLEYVIEW(dev)) |
8435 | dev_priv->display.get_display_clock_speed = | |
8436 | valleyview_get_display_clock_speed; | |
8437 | else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev))) | |
e70236a8 JB |
8438 | dev_priv->display.get_display_clock_speed = |
8439 | i945_get_display_clock_speed; | |
8440 | else if (IS_I915G(dev)) | |
8441 | dev_priv->display.get_display_clock_speed = | |
8442 | i915_get_display_clock_speed; | |
f2b115e6 | 8443 | else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev)) |
e70236a8 JB |
8444 | dev_priv->display.get_display_clock_speed = |
8445 | i9xx_misc_get_display_clock_speed; | |
8446 | else if (IS_I915GM(dev)) | |
8447 | dev_priv->display.get_display_clock_speed = | |
8448 | i915gm_get_display_clock_speed; | |
8449 | else if (IS_I865G(dev)) | |
8450 | dev_priv->display.get_display_clock_speed = | |
8451 | i865_get_display_clock_speed; | |
f0f8a9ce | 8452 | else if (IS_I85X(dev)) |
e70236a8 JB |
8453 | dev_priv->display.get_display_clock_speed = |
8454 | i855_get_display_clock_speed; | |
8455 | else /* 852, 830 */ | |
8456 | dev_priv->display.get_display_clock_speed = | |
8457 | i830_get_display_clock_speed; | |
8458 | ||
7f8a8569 | 8459 | if (HAS_PCH_SPLIT(dev)) { |
f00a3ddf | 8460 | if (IS_GEN5(dev)) { |
674cf967 | 8461 | dev_priv->display.fdi_link_train = ironlake_fdi_link_train; |
e0dac65e | 8462 | dev_priv->display.write_eld = ironlake_write_eld; |
1398261a | 8463 | } else if (IS_GEN6(dev)) { |
674cf967 | 8464 | dev_priv->display.fdi_link_train = gen6_fdi_link_train; |
e0dac65e | 8465 | dev_priv->display.write_eld = ironlake_write_eld; |
357555c0 JB |
8466 | } else if (IS_IVYBRIDGE(dev)) { |
8467 | /* FIXME: detect B0+ stepping and use auto training */ | |
8468 | dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train; | |
e0dac65e | 8469 | dev_priv->display.write_eld = ironlake_write_eld; |
01a415fd DV |
8470 | dev_priv->display.modeset_global_resources = |
8471 | ivb_modeset_global_resources; | |
c82e4d26 ED |
8472 | } else if (IS_HASWELL(dev)) { |
8473 | dev_priv->display.fdi_link_train = hsw_fdi_link_train; | |
83358c85 | 8474 | dev_priv->display.write_eld = haswell_write_eld; |
a0e63c22 | 8475 | } |
6067aaea | 8476 | } else if (IS_G4X(dev)) { |
e0dac65e | 8477 | dev_priv->display.write_eld = g4x_write_eld; |
e70236a8 | 8478 | } |
8c9f3aaf JB |
8479 | |
8480 | /* Default just returns -ENODEV to indicate unsupported */ | |
8481 | dev_priv->display.queue_flip = intel_default_queue_flip; | |
8482 | ||
8483 | switch (INTEL_INFO(dev)->gen) { | |
8484 | case 2: | |
8485 | dev_priv->display.queue_flip = intel_gen2_queue_flip; | |
8486 | break; | |
8487 | ||
8488 | case 3: | |
8489 | dev_priv->display.queue_flip = intel_gen3_queue_flip; | |
8490 | break; | |
8491 | ||
8492 | case 4: | |
8493 | case 5: | |
8494 | dev_priv->display.queue_flip = intel_gen4_queue_flip; | |
8495 | break; | |
8496 | ||
8497 | case 6: | |
8498 | dev_priv->display.queue_flip = intel_gen6_queue_flip; | |
8499 | break; | |
7c9017e5 JB |
8500 | case 7: |
8501 | dev_priv->display.queue_flip = intel_gen7_queue_flip; | |
8502 | break; | |
8c9f3aaf | 8503 | } |
e70236a8 JB |
8504 | } |
8505 | ||
b690e96c JB |
8506 | /* |
8507 | * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend, | |
8508 | * resume, or other times. This quirk makes sure that's the case for | |
8509 | * affected systems. | |
8510 | */ | |
0206e353 | 8511 | static void quirk_pipea_force(struct drm_device *dev) |
b690e96c JB |
8512 | { |
8513 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8514 | ||
8515 | dev_priv->quirks |= QUIRK_PIPEA_FORCE; | |
bc0daf48 | 8516 | DRM_INFO("applying pipe a force quirk\n"); |
b690e96c JB |
8517 | } |
8518 | ||
435793df KP |
8519 | /* |
8520 | * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason | |
8521 | */ | |
8522 | static void quirk_ssc_force_disable(struct drm_device *dev) | |
8523 | { | |
8524 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8525 | dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE; | |
bc0daf48 | 8526 | DRM_INFO("applying lvds SSC disable quirk\n"); |
435793df KP |
8527 | } |
8528 | ||
4dca20ef | 8529 | /* |
5a15ab5b CE |
8530 | * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight |
8531 | * brightness value | |
4dca20ef CE |
8532 | */ |
8533 | static void quirk_invert_brightness(struct drm_device *dev) | |
8534 | { | |
8535 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8536 | dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS; | |
bc0daf48 | 8537 | DRM_INFO("applying inverted panel brightness quirk\n"); |
435793df KP |
8538 | } |
8539 | ||
b690e96c JB |
8540 | struct intel_quirk { |
8541 | int device; | |
8542 | int subsystem_vendor; | |
8543 | int subsystem_device; | |
8544 | void (*hook)(struct drm_device *dev); | |
8545 | }; | |
8546 | ||
5f85f176 EE |
8547 | /* For systems that don't have a meaningful PCI subdevice/subvendor ID */ |
8548 | struct intel_dmi_quirk { | |
8549 | void (*hook)(struct drm_device *dev); | |
8550 | const struct dmi_system_id (*dmi_id_list)[]; | |
8551 | }; | |
8552 | ||
8553 | static int intel_dmi_reverse_brightness(const struct dmi_system_id *id) | |
8554 | { | |
8555 | DRM_INFO("Backlight polarity reversed on %s\n", id->ident); | |
8556 | return 1; | |
8557 | } | |
8558 | ||
8559 | static const struct intel_dmi_quirk intel_dmi_quirks[] = { | |
8560 | { | |
8561 | .dmi_id_list = &(const struct dmi_system_id[]) { | |
8562 | { | |
8563 | .callback = intel_dmi_reverse_brightness, | |
8564 | .ident = "NCR Corporation", | |
8565 | .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"), | |
8566 | DMI_MATCH(DMI_PRODUCT_NAME, ""), | |
8567 | }, | |
8568 | }, | |
8569 | { } /* terminating entry */ | |
8570 | }, | |
8571 | .hook = quirk_invert_brightness, | |
8572 | }, | |
8573 | }; | |
8574 | ||
c43b5634 | 8575 | static struct intel_quirk intel_quirks[] = { |
b690e96c | 8576 | /* HP Mini needs pipe A force quirk (LP: #322104) */ |
0206e353 | 8577 | { 0x27ae, 0x103c, 0x361a, quirk_pipea_force }, |
b690e96c | 8578 | |
b690e96c JB |
8579 | /* Toshiba Protege R-205, S-209 needs pipe A force quirk */ |
8580 | { 0x2592, 0x1179, 0x0001, quirk_pipea_force }, | |
8581 | ||
b690e96c JB |
8582 | /* ThinkPad T60 needs pipe A force quirk (bug #16494) */ |
8583 | { 0x2782, 0x17aa, 0x201a, quirk_pipea_force }, | |
8584 | ||
ccd0d36e | 8585 | /* 830/845 need to leave pipe A & dpll A up */ |
b690e96c | 8586 | { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, |
dcdaed6e | 8587 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, |
435793df KP |
8588 | |
8589 | /* Lenovo U160 cannot use SSC on LVDS */ | |
8590 | { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable }, | |
070d329a MAS |
8591 | |
8592 | /* Sony Vaio Y cannot use SSC on LVDS */ | |
8593 | { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable }, | |
5a15ab5b CE |
8594 | |
8595 | /* Acer Aspire 5734Z must invert backlight brightness */ | |
8596 | { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness }, | |
b690e96c JB |
8597 | }; |
8598 | ||
8599 | static void intel_init_quirks(struct drm_device *dev) | |
8600 | { | |
8601 | struct pci_dev *d = dev->pdev; | |
8602 | int i; | |
8603 | ||
8604 | for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) { | |
8605 | struct intel_quirk *q = &intel_quirks[i]; | |
8606 | ||
8607 | if (d->device == q->device && | |
8608 | (d->subsystem_vendor == q->subsystem_vendor || | |
8609 | q->subsystem_vendor == PCI_ANY_ID) && | |
8610 | (d->subsystem_device == q->subsystem_device || | |
8611 | q->subsystem_device == PCI_ANY_ID)) | |
8612 | q->hook(dev); | |
8613 | } | |
5f85f176 EE |
8614 | for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) { |
8615 | if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0) | |
8616 | intel_dmi_quirks[i].hook(dev); | |
8617 | } | |
b690e96c JB |
8618 | } |
8619 | ||
9cce37f4 JB |
8620 | /* Disable the VGA plane that we never use */ |
8621 | static void i915_disable_vga(struct drm_device *dev) | |
8622 | { | |
8623 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8624 | u8 sr1; | |
8625 | u32 vga_reg; | |
8626 | ||
8627 | if (HAS_PCH_SPLIT(dev)) | |
8628 | vga_reg = CPU_VGACNTRL; | |
8629 | else | |
8630 | vga_reg = VGACNTRL; | |
8631 | ||
8632 | vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); | |
3fdcf431 | 8633 | outb(SR01, VGA_SR_INDEX); |
9cce37f4 JB |
8634 | sr1 = inb(VGA_SR_DATA); |
8635 | outb(sr1 | 1<<5, VGA_SR_DATA); | |
8636 | vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); | |
8637 | udelay(300); | |
8638 | ||
8639 | I915_WRITE(vga_reg, VGA_DISP_DISABLE); | |
8640 | POSTING_READ(vga_reg); | |
8641 | } | |
8642 | ||
f817586c DV |
8643 | void intel_modeset_init_hw(struct drm_device *dev) |
8644 | { | |
0232e927 ED |
8645 | /* We attempt to init the necessary power wells early in the initialization |
8646 | * time, so the subsystems that expect power to be enabled can work. | |
8647 | */ | |
8648 | intel_init_power_wells(dev); | |
8649 | ||
a8f78b58 ED |
8650 | intel_prepare_ddi(dev); |
8651 | ||
f817586c DV |
8652 | intel_init_clock_gating(dev); |
8653 | ||
79f5b2c7 | 8654 | mutex_lock(&dev->struct_mutex); |
8090c6b9 | 8655 | intel_enable_gt_powersave(dev); |
79f5b2c7 | 8656 | mutex_unlock(&dev->struct_mutex); |
f817586c DV |
8657 | } |
8658 | ||
79e53945 JB |
8659 | void intel_modeset_init(struct drm_device *dev) |
8660 | { | |
652c393a | 8661 | struct drm_i915_private *dev_priv = dev->dev_private; |
b840d907 | 8662 | int i, ret; |
79e53945 JB |
8663 | |
8664 | drm_mode_config_init(dev); | |
8665 | ||
8666 | dev->mode_config.min_width = 0; | |
8667 | dev->mode_config.min_height = 0; | |
8668 | ||
019d96cb DA |
8669 | dev->mode_config.preferred_depth = 24; |
8670 | dev->mode_config.prefer_shadow = 1; | |
8671 | ||
e6ecefaa | 8672 | dev->mode_config.funcs = &intel_mode_funcs; |
79e53945 | 8673 | |
b690e96c JB |
8674 | intel_init_quirks(dev); |
8675 | ||
1fa61106 ED |
8676 | intel_init_pm(dev); |
8677 | ||
e70236a8 JB |
8678 | intel_init_display(dev); |
8679 | ||
a6c45cf0 CW |
8680 | if (IS_GEN2(dev)) { |
8681 | dev->mode_config.max_width = 2048; | |
8682 | dev->mode_config.max_height = 2048; | |
8683 | } else if (IS_GEN3(dev)) { | |
5e4d6fa7 KP |
8684 | dev->mode_config.max_width = 4096; |
8685 | dev->mode_config.max_height = 4096; | |
79e53945 | 8686 | } else { |
a6c45cf0 CW |
8687 | dev->mode_config.max_width = 8192; |
8688 | dev->mode_config.max_height = 8192; | |
79e53945 | 8689 | } |
5d4545ae | 8690 | dev->mode_config.fb_base = dev_priv->gtt.mappable_base; |
79e53945 | 8691 | |
28c97730 | 8692 | DRM_DEBUG_KMS("%d display pipe%s available.\n", |
a3524f1b | 8693 | dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : ""); |
79e53945 | 8694 | |
a3524f1b | 8695 | for (i = 0; i < dev_priv->num_pipe; i++) { |
79e53945 | 8696 | intel_crtc_init(dev, i); |
00c2064b JB |
8697 | ret = intel_plane_init(dev, i); |
8698 | if (ret) | |
8699 | DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret); | |
79e53945 JB |
8700 | } |
8701 | ||
79f689aa | 8702 | intel_cpu_pll_init(dev); |
ee7b9f93 JB |
8703 | intel_pch_pll_init(dev); |
8704 | ||
9cce37f4 JB |
8705 | /* Just disable it once at startup */ |
8706 | i915_disable_vga(dev); | |
79e53945 | 8707 | intel_setup_outputs(dev); |
11be49eb CW |
8708 | |
8709 | /* Just in case the BIOS is doing something questionable. */ | |
8710 | intel_disable_fbc(dev); | |
2c7111db CW |
8711 | } |
8712 | ||
24929352 DV |
8713 | static void |
8714 | intel_connector_break_all_links(struct intel_connector *connector) | |
8715 | { | |
8716 | connector->base.dpms = DRM_MODE_DPMS_OFF; | |
8717 | connector->base.encoder = NULL; | |
8718 | connector->encoder->connectors_active = false; | |
8719 | connector->encoder->base.crtc = NULL; | |
8720 | } | |
8721 | ||
7fad798e DV |
8722 | static void intel_enable_pipe_a(struct drm_device *dev) |
8723 | { | |
8724 | struct intel_connector *connector; | |
8725 | struct drm_connector *crt = NULL; | |
8726 | struct intel_load_detect_pipe load_detect_temp; | |
8727 | ||
8728 | /* We can't just switch on the pipe A, we need to set things up with a | |
8729 | * proper mode and output configuration. As a gross hack, enable pipe A | |
8730 | * by enabling the load detect pipe once. */ | |
8731 | list_for_each_entry(connector, | |
8732 | &dev->mode_config.connector_list, | |
8733 | base.head) { | |
8734 | if (connector->encoder->type == INTEL_OUTPUT_ANALOG) { | |
8735 | crt = &connector->base; | |
8736 | break; | |
8737 | } | |
8738 | } | |
8739 | ||
8740 | if (!crt) | |
8741 | return; | |
8742 | ||
8743 | if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp)) | |
8744 | intel_release_load_detect_pipe(crt, &load_detect_temp); | |
8745 | ||
652c393a | 8746 | |
7fad798e DV |
8747 | } |
8748 | ||
fa555837 DV |
8749 | static bool |
8750 | intel_check_plane_mapping(struct intel_crtc *crtc) | |
8751 | { | |
8752 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
8753 | u32 reg, val; | |
8754 | ||
8755 | if (dev_priv->num_pipe == 1) | |
8756 | return true; | |
8757 | ||
8758 | reg = DSPCNTR(!crtc->plane); | |
8759 | val = I915_READ(reg); | |
8760 | ||
8761 | if ((val & DISPLAY_PLANE_ENABLE) && | |
8762 | (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe)) | |
8763 | return false; | |
8764 | ||
8765 | return true; | |
8766 | } | |
8767 | ||
24929352 DV |
8768 | static void intel_sanitize_crtc(struct intel_crtc *crtc) |
8769 | { | |
8770 | struct drm_device *dev = crtc->base.dev; | |
8771 | struct drm_i915_private *dev_priv = dev->dev_private; | |
fa555837 | 8772 | u32 reg; |
24929352 | 8773 | |
24929352 | 8774 | /* Clear any frame start delays used for debugging left by the BIOS */ |
702e7a56 | 8775 | reg = PIPECONF(crtc->cpu_transcoder); |
24929352 DV |
8776 | I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK); |
8777 | ||
8778 | /* We need to sanitize the plane -> pipe mapping first because this will | |
fa555837 DV |
8779 | * disable the crtc (and hence change the state) if it is wrong. Note |
8780 | * that gen4+ has a fixed plane -> pipe mapping. */ | |
8781 | if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) { | |
24929352 DV |
8782 | struct intel_connector *connector; |
8783 | bool plane; | |
8784 | ||
24929352 DV |
8785 | DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n", |
8786 | crtc->base.base.id); | |
8787 | ||
8788 | /* Pipe has the wrong plane attached and the plane is active. | |
8789 | * Temporarily change the plane mapping and disable everything | |
8790 | * ... */ | |
8791 | plane = crtc->plane; | |
8792 | crtc->plane = !plane; | |
8793 | dev_priv->display.crtc_disable(&crtc->base); | |
8794 | crtc->plane = plane; | |
8795 | ||
8796 | /* ... and break all links. */ | |
8797 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
8798 | base.head) { | |
8799 | if (connector->encoder->base.crtc != &crtc->base) | |
8800 | continue; | |
8801 | ||
8802 | intel_connector_break_all_links(connector); | |
8803 | } | |
8804 | ||
8805 | WARN_ON(crtc->active); | |
8806 | crtc->base.enabled = false; | |
8807 | } | |
24929352 | 8808 | |
7fad798e DV |
8809 | if (dev_priv->quirks & QUIRK_PIPEA_FORCE && |
8810 | crtc->pipe == PIPE_A && !crtc->active) { | |
8811 | /* BIOS forgot to enable pipe A, this mostly happens after | |
8812 | * resume. Force-enable the pipe to fix this, the update_dpms | |
8813 | * call below we restore the pipe to the right state, but leave | |
8814 | * the required bits on. */ | |
8815 | intel_enable_pipe_a(dev); | |
8816 | } | |
8817 | ||
24929352 DV |
8818 | /* Adjust the state of the output pipe according to whether we |
8819 | * have active connectors/encoders. */ | |
8820 | intel_crtc_update_dpms(&crtc->base); | |
8821 | ||
8822 | if (crtc->active != crtc->base.enabled) { | |
8823 | struct intel_encoder *encoder; | |
8824 | ||
8825 | /* This can happen either due to bugs in the get_hw_state | |
8826 | * functions or because the pipe is force-enabled due to the | |
8827 | * pipe A quirk. */ | |
8828 | DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n", | |
8829 | crtc->base.base.id, | |
8830 | crtc->base.enabled ? "enabled" : "disabled", | |
8831 | crtc->active ? "enabled" : "disabled"); | |
8832 | ||
8833 | crtc->base.enabled = crtc->active; | |
8834 | ||
8835 | /* Because we only establish the connector -> encoder -> | |
8836 | * crtc links if something is active, this means the | |
8837 | * crtc is now deactivated. Break the links. connector | |
8838 | * -> encoder links are only establish when things are | |
8839 | * actually up, hence no need to break them. */ | |
8840 | WARN_ON(crtc->active); | |
8841 | ||
8842 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) { | |
8843 | WARN_ON(encoder->connectors_active); | |
8844 | encoder->base.crtc = NULL; | |
8845 | } | |
8846 | } | |
8847 | } | |
8848 | ||
8849 | static void intel_sanitize_encoder(struct intel_encoder *encoder) | |
8850 | { | |
8851 | struct intel_connector *connector; | |
8852 | struct drm_device *dev = encoder->base.dev; | |
8853 | ||
8854 | /* We need to check both for a crtc link (meaning that the | |
8855 | * encoder is active and trying to read from a pipe) and the | |
8856 | * pipe itself being active. */ | |
8857 | bool has_active_crtc = encoder->base.crtc && | |
8858 | to_intel_crtc(encoder->base.crtc)->active; | |
8859 | ||
8860 | if (encoder->connectors_active && !has_active_crtc) { | |
8861 | DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n", | |
8862 | encoder->base.base.id, | |
8863 | drm_get_encoder_name(&encoder->base)); | |
8864 | ||
8865 | /* Connector is active, but has no active pipe. This is | |
8866 | * fallout from our resume register restoring. Disable | |
8867 | * the encoder manually again. */ | |
8868 | if (encoder->base.crtc) { | |
8869 | DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n", | |
8870 | encoder->base.base.id, | |
8871 | drm_get_encoder_name(&encoder->base)); | |
8872 | encoder->disable(encoder); | |
8873 | } | |
8874 | ||
8875 | /* Inconsistent output/port/pipe state happens presumably due to | |
8876 | * a bug in one of the get_hw_state functions. Or someplace else | |
8877 | * in our code, like the register restore mess on resume. Clamp | |
8878 | * things to off as a safer default. */ | |
8879 | list_for_each_entry(connector, | |
8880 | &dev->mode_config.connector_list, | |
8881 | base.head) { | |
8882 | if (connector->encoder != encoder) | |
8883 | continue; | |
8884 | ||
8885 | intel_connector_break_all_links(connector); | |
8886 | } | |
8887 | } | |
8888 | /* Enabled encoders without active connectors will be fixed in | |
8889 | * the crtc fixup. */ | |
8890 | } | |
8891 | ||
0fde901f KM |
8892 | static void i915_redisable_vga(struct drm_device *dev) |
8893 | { | |
8894 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8895 | u32 vga_reg; | |
8896 | ||
8897 | if (HAS_PCH_SPLIT(dev)) | |
8898 | vga_reg = CPU_VGACNTRL; | |
8899 | else | |
8900 | vga_reg = VGACNTRL; | |
8901 | ||
8902 | if (I915_READ(vga_reg) != VGA_DISP_DISABLE) { | |
8903 | DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n"); | |
8904 | I915_WRITE(vga_reg, VGA_DISP_DISABLE); | |
8905 | POSTING_READ(vga_reg); | |
8906 | } | |
8907 | } | |
8908 | ||
24929352 DV |
8909 | /* Scan out the current hw modeset state, sanitizes it and maps it into the drm |
8910 | * and i915 state tracking structures. */ | |
45e2b5f6 DV |
8911 | void intel_modeset_setup_hw_state(struct drm_device *dev, |
8912 | bool force_restore) | |
24929352 DV |
8913 | { |
8914 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8915 | enum pipe pipe; | |
8916 | u32 tmp; | |
8917 | struct intel_crtc *crtc; | |
8918 | struct intel_encoder *encoder; | |
8919 | struct intel_connector *connector; | |
8920 | ||
affa9354 | 8921 | if (HAS_DDI(dev)) { |
e28d54cb PZ |
8922 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); |
8923 | ||
8924 | if (tmp & TRANS_DDI_FUNC_ENABLE) { | |
8925 | switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { | |
8926 | case TRANS_DDI_EDP_INPUT_A_ON: | |
8927 | case TRANS_DDI_EDP_INPUT_A_ONOFF: | |
8928 | pipe = PIPE_A; | |
8929 | break; | |
8930 | case TRANS_DDI_EDP_INPUT_B_ONOFF: | |
8931 | pipe = PIPE_B; | |
8932 | break; | |
8933 | case TRANS_DDI_EDP_INPUT_C_ONOFF: | |
8934 | pipe = PIPE_C; | |
8935 | break; | |
8936 | } | |
8937 | ||
8938 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); | |
8939 | crtc->cpu_transcoder = TRANSCODER_EDP; | |
8940 | ||
8941 | DRM_DEBUG_KMS("Pipe %c using transcoder EDP\n", | |
8942 | pipe_name(pipe)); | |
8943 | } | |
8944 | } | |
8945 | ||
24929352 DV |
8946 | for_each_pipe(pipe) { |
8947 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); | |
8948 | ||
702e7a56 | 8949 | tmp = I915_READ(PIPECONF(crtc->cpu_transcoder)); |
24929352 DV |
8950 | if (tmp & PIPECONF_ENABLE) |
8951 | crtc->active = true; | |
8952 | else | |
8953 | crtc->active = false; | |
8954 | ||
8955 | crtc->base.enabled = crtc->active; | |
8956 | ||
8957 | DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n", | |
8958 | crtc->base.base.id, | |
8959 | crtc->active ? "enabled" : "disabled"); | |
8960 | } | |
8961 | ||
affa9354 | 8962 | if (HAS_DDI(dev)) |
6441ab5f PZ |
8963 | intel_ddi_setup_hw_pll_state(dev); |
8964 | ||
24929352 DV |
8965 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
8966 | base.head) { | |
8967 | pipe = 0; | |
8968 | ||
8969 | if (encoder->get_hw_state(encoder, &pipe)) { | |
8970 | encoder->base.crtc = | |
8971 | dev_priv->pipe_to_crtc_mapping[pipe]; | |
8972 | } else { | |
8973 | encoder->base.crtc = NULL; | |
8974 | } | |
8975 | ||
8976 | encoder->connectors_active = false; | |
8977 | DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n", | |
8978 | encoder->base.base.id, | |
8979 | drm_get_encoder_name(&encoder->base), | |
8980 | encoder->base.crtc ? "enabled" : "disabled", | |
8981 | pipe); | |
8982 | } | |
8983 | ||
8984 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
8985 | base.head) { | |
8986 | if (connector->get_hw_state(connector)) { | |
8987 | connector->base.dpms = DRM_MODE_DPMS_ON; | |
8988 | connector->encoder->connectors_active = true; | |
8989 | connector->base.encoder = &connector->encoder->base; | |
8990 | } else { | |
8991 | connector->base.dpms = DRM_MODE_DPMS_OFF; | |
8992 | connector->base.encoder = NULL; | |
8993 | } | |
8994 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n", | |
8995 | connector->base.base.id, | |
8996 | drm_get_connector_name(&connector->base), | |
8997 | connector->base.encoder ? "enabled" : "disabled"); | |
8998 | } | |
8999 | ||
9000 | /* HW state is read out, now we need to sanitize this mess. */ | |
9001 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, | |
9002 | base.head) { | |
9003 | intel_sanitize_encoder(encoder); | |
9004 | } | |
9005 | ||
9006 | for_each_pipe(pipe) { | |
9007 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); | |
9008 | intel_sanitize_crtc(crtc); | |
9009 | } | |
9a935856 | 9010 | |
45e2b5f6 DV |
9011 | if (force_restore) { |
9012 | for_each_pipe(pipe) { | |
c0c36b94 | 9013 | intel_crtc_restore_mode(dev_priv->pipe_to_crtc_mapping[pipe]); |
45e2b5f6 | 9014 | } |
0fde901f KM |
9015 | |
9016 | i915_redisable_vga(dev); | |
45e2b5f6 DV |
9017 | } else { |
9018 | intel_modeset_update_staged_output_state(dev); | |
9019 | } | |
8af6cf88 DV |
9020 | |
9021 | intel_modeset_check_state(dev); | |
2e938892 DV |
9022 | |
9023 | drm_mode_config_reset(dev); | |
2c7111db CW |
9024 | } |
9025 | ||
9026 | void intel_modeset_gem_init(struct drm_device *dev) | |
9027 | { | |
1833b134 | 9028 | intel_modeset_init_hw(dev); |
02e792fb DV |
9029 | |
9030 | intel_setup_overlay(dev); | |
24929352 | 9031 | |
45e2b5f6 | 9032 | intel_modeset_setup_hw_state(dev, false); |
79e53945 JB |
9033 | } |
9034 | ||
9035 | void intel_modeset_cleanup(struct drm_device *dev) | |
9036 | { | |
652c393a JB |
9037 | struct drm_i915_private *dev_priv = dev->dev_private; |
9038 | struct drm_crtc *crtc; | |
9039 | struct intel_crtc *intel_crtc; | |
9040 | ||
f87ea761 | 9041 | drm_kms_helper_poll_fini(dev); |
652c393a JB |
9042 | mutex_lock(&dev->struct_mutex); |
9043 | ||
723bfd70 JB |
9044 | intel_unregister_dsm_handler(); |
9045 | ||
9046 | ||
652c393a JB |
9047 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
9048 | /* Skip inactive CRTCs */ | |
9049 | if (!crtc->fb) | |
9050 | continue; | |
9051 | ||
9052 | intel_crtc = to_intel_crtc(crtc); | |
3dec0095 | 9053 | intel_increase_pllclock(crtc); |
652c393a JB |
9054 | } |
9055 | ||
973d04f9 | 9056 | intel_disable_fbc(dev); |
e70236a8 | 9057 | |
8090c6b9 | 9058 | intel_disable_gt_powersave(dev); |
0cdab21f | 9059 | |
930ebb46 DV |
9060 | ironlake_teardown_rc6(dev); |
9061 | ||
57f350b6 JB |
9062 | if (IS_VALLEYVIEW(dev)) |
9063 | vlv_init_dpio(dev); | |
9064 | ||
69341a5e KH |
9065 | mutex_unlock(&dev->struct_mutex); |
9066 | ||
6c0d9350 DV |
9067 | /* Disable the irq before mode object teardown, for the irq might |
9068 | * enqueue unpin/hotplug work. */ | |
9069 | drm_irq_uninstall(dev); | |
9070 | cancel_work_sync(&dev_priv->hotplug_work); | |
c6a828d3 | 9071 | cancel_work_sync(&dev_priv->rps.work); |
6c0d9350 | 9072 | |
1630fe75 CW |
9073 | /* flush any delayed tasks or pending work */ |
9074 | flush_scheduled_work(); | |
9075 | ||
79e53945 | 9076 | drm_mode_config_cleanup(dev); |
4d7bb011 DV |
9077 | |
9078 | intel_cleanup_overlay(dev); | |
79e53945 JB |
9079 | } |
9080 | ||
f1c79df3 ZW |
9081 | /* |
9082 | * Return which encoder is currently attached for connector. | |
9083 | */ | |
df0e9248 | 9084 | struct drm_encoder *intel_best_encoder(struct drm_connector *connector) |
79e53945 | 9085 | { |
df0e9248 CW |
9086 | return &intel_attached_encoder(connector)->base; |
9087 | } | |
f1c79df3 | 9088 | |
df0e9248 CW |
9089 | void intel_connector_attach_encoder(struct intel_connector *connector, |
9090 | struct intel_encoder *encoder) | |
9091 | { | |
9092 | connector->encoder = encoder; | |
9093 | drm_mode_connector_attach_encoder(&connector->base, | |
9094 | &encoder->base); | |
79e53945 | 9095 | } |
28d52043 DA |
9096 | |
9097 | /* | |
9098 | * set vga decode state - true == enable VGA decode | |
9099 | */ | |
9100 | int intel_modeset_vga_set_state(struct drm_device *dev, bool state) | |
9101 | { | |
9102 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9103 | u16 gmch_ctrl; | |
9104 | ||
9105 | pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl); | |
9106 | if (state) | |
9107 | gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE; | |
9108 | else | |
9109 | gmch_ctrl |= INTEL_GMCH_VGA_DISABLE; | |
9110 | pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl); | |
9111 | return 0; | |
9112 | } | |
c4a1d9e4 CW |
9113 | |
9114 | #ifdef CONFIG_DEBUG_FS | |
9115 | #include <linux/seq_file.h> | |
9116 | ||
9117 | struct intel_display_error_state { | |
9118 | struct intel_cursor_error_state { | |
9119 | u32 control; | |
9120 | u32 position; | |
9121 | u32 base; | |
9122 | u32 size; | |
52331309 | 9123 | } cursor[I915_MAX_PIPES]; |
c4a1d9e4 CW |
9124 | |
9125 | struct intel_pipe_error_state { | |
9126 | u32 conf; | |
9127 | u32 source; | |
9128 | ||
9129 | u32 htotal; | |
9130 | u32 hblank; | |
9131 | u32 hsync; | |
9132 | u32 vtotal; | |
9133 | u32 vblank; | |
9134 | u32 vsync; | |
52331309 | 9135 | } pipe[I915_MAX_PIPES]; |
c4a1d9e4 CW |
9136 | |
9137 | struct intel_plane_error_state { | |
9138 | u32 control; | |
9139 | u32 stride; | |
9140 | u32 size; | |
9141 | u32 pos; | |
9142 | u32 addr; | |
9143 | u32 surface; | |
9144 | u32 tile_offset; | |
52331309 | 9145 | } plane[I915_MAX_PIPES]; |
c4a1d9e4 CW |
9146 | }; |
9147 | ||
9148 | struct intel_display_error_state * | |
9149 | intel_display_capture_error_state(struct drm_device *dev) | |
9150 | { | |
0206e353 | 9151 | drm_i915_private_t *dev_priv = dev->dev_private; |
c4a1d9e4 | 9152 | struct intel_display_error_state *error; |
702e7a56 | 9153 | enum transcoder cpu_transcoder; |
c4a1d9e4 CW |
9154 | int i; |
9155 | ||
9156 | error = kmalloc(sizeof(*error), GFP_ATOMIC); | |
9157 | if (error == NULL) | |
9158 | return NULL; | |
9159 | ||
52331309 | 9160 | for_each_pipe(i) { |
702e7a56 PZ |
9161 | cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i); |
9162 | ||
c4a1d9e4 CW |
9163 | error->cursor[i].control = I915_READ(CURCNTR(i)); |
9164 | error->cursor[i].position = I915_READ(CURPOS(i)); | |
9165 | error->cursor[i].base = I915_READ(CURBASE(i)); | |
9166 | ||
9167 | error->plane[i].control = I915_READ(DSPCNTR(i)); | |
9168 | error->plane[i].stride = I915_READ(DSPSTRIDE(i)); | |
9169 | error->plane[i].size = I915_READ(DSPSIZE(i)); | |
0206e353 | 9170 | error->plane[i].pos = I915_READ(DSPPOS(i)); |
c4a1d9e4 CW |
9171 | error->plane[i].addr = I915_READ(DSPADDR(i)); |
9172 | if (INTEL_INFO(dev)->gen >= 4) { | |
9173 | error->plane[i].surface = I915_READ(DSPSURF(i)); | |
9174 | error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i)); | |
9175 | } | |
9176 | ||
702e7a56 | 9177 | error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder)); |
c4a1d9e4 | 9178 | error->pipe[i].source = I915_READ(PIPESRC(i)); |
fe2b8f9d PZ |
9179 | error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder)); |
9180 | error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder)); | |
9181 | error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder)); | |
9182 | error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder)); | |
9183 | error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder)); | |
9184 | error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder)); | |
c4a1d9e4 CW |
9185 | } |
9186 | ||
9187 | return error; | |
9188 | } | |
9189 | ||
9190 | void | |
9191 | intel_display_print_error_state(struct seq_file *m, | |
9192 | struct drm_device *dev, | |
9193 | struct intel_display_error_state *error) | |
9194 | { | |
52331309 | 9195 | drm_i915_private_t *dev_priv = dev->dev_private; |
c4a1d9e4 CW |
9196 | int i; |
9197 | ||
52331309 DL |
9198 | seq_printf(m, "Num Pipes: %d\n", dev_priv->num_pipe); |
9199 | for_each_pipe(i) { | |
c4a1d9e4 CW |
9200 | seq_printf(m, "Pipe [%d]:\n", i); |
9201 | seq_printf(m, " CONF: %08x\n", error->pipe[i].conf); | |
9202 | seq_printf(m, " SRC: %08x\n", error->pipe[i].source); | |
9203 | seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal); | |
9204 | seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank); | |
9205 | seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync); | |
9206 | seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal); | |
9207 | seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank); | |
9208 | seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync); | |
9209 | ||
9210 | seq_printf(m, "Plane [%d]:\n", i); | |
9211 | seq_printf(m, " CNTR: %08x\n", error->plane[i].control); | |
9212 | seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride); | |
9213 | seq_printf(m, " SIZE: %08x\n", error->plane[i].size); | |
9214 | seq_printf(m, " POS: %08x\n", error->plane[i].pos); | |
9215 | seq_printf(m, " ADDR: %08x\n", error->plane[i].addr); | |
9216 | if (INTEL_INFO(dev)->gen >= 4) { | |
9217 | seq_printf(m, " SURF: %08x\n", error->plane[i].surface); | |
9218 | seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset); | |
9219 | } | |
9220 | ||
9221 | seq_printf(m, "Cursor [%d]:\n", i); | |
9222 | seq_printf(m, " CNTR: %08x\n", error->cursor[i].control); | |
9223 | seq_printf(m, " POS: %08x\n", error->cursor[i].position); | |
9224 | seq_printf(m, " BASE: %08x\n", error->cursor[i].base); | |
9225 | } | |
9226 | } | |
9227 | #endif |