projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drm/i915: remove ACPI related DRM_ERRORs
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
23b2f8bb 27#include <linux/cpufreq.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
79e53945
JB		 35#include "drmP.h"
36#include "intel_drv.h"
37#include "i915_drm.h"
38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
ab2c0672 40#include "drm_dp_helper.h"
79e53945 41#include "drm_crtc_helper.h"
c0f372b3 42#include <linux/dma_remapping.h>
79e53945 43
32f9d658
ZW		 44#define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
45
0206e353 46bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
7662c8bd 47static void intel_update_watermarks(struct drm_device *dev);
3dec0095 48static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 49static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945
JB		 50
51typedef struct {
0206e353
AJ		 52 /* given values */
53 int n;
54 int m1, m2;
55 int p1, p2;
56 /* derived values */
57 int dot;
58 int vco;
59 int m;
60 int p;
79e53945
JB		 61} intel_clock_t;
62
63typedef struct {
0206e353 64 int min, max;
79e53945
JB		 65} intel_range_t;
66
67typedef struct {
0206e353
AJ		 68 int dot_limit;
69 int p2_slow, p2_fast;
79e53945
JB		 70} intel_p2_t;
71
72#define INTEL_P2_NUM 2
d4906093
ML		 73typedef struct intel_limit intel_limit_t;
74struct intel_limit {
0206e353
AJ		 75 intel_range_t dot, vco, n, m, m1, m2, p, p1;
76 intel_p2_t p2;
77 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
cec2f356 78 int, int, intel_clock_t *, intel_clock_t *);
d4906093 79};
79e53945 80
2377b741
JB		 81/* FDI */
82#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
83
d4906093
ML		 84static bool
85intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 86 int target, int refclk, intel_clock_t *match_clock,
87 intel_clock_t *best_clock);
d4906093
ML		 88static bool
89intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 90 int target, int refclk, intel_clock_t *match_clock,
91 intel_clock_t *best_clock);
79e53945 92
a4fc5ed6
KP		 93static bool
94intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
cec2f356
SP		 95 int target, int refclk, intel_clock_t *match_clock,
96 intel_clock_t *best_clock);
5eb08b69 97static bool
f2b115e6 98intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
cec2f356
SP		 99 int target, int refclk, intel_clock_t *match_clock,
100 intel_clock_t *best_clock);
a4fc5ed6 101
021357ac
CW		 102static inline u32 /* units of 100MHz */
103intel_fdi_link_freq(struct drm_device *dev)
104{
8b99e68c
CW		 105 if (IS_GEN5(dev)) {
106 struct drm_i915_private *dev_priv = dev->dev_private;
107 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
108 } else
109 return 27;
021357ac
CW		 110}
111
e4b36699 112static const intel_limit_t intel_limits_i8xx_dvo = {
0206e353
AJ		 113 .dot = { .min = 25000, .max = 350000 },
114 .vco = { .min = 930000, .max = 1400000 },
115 .n = { .min = 3, .max = 16 },
116 .m = { .min = 96, .max = 140 },
117 .m1 = { .min = 18, .max = 26 },
118 .m2 = { .min = 6, .max = 16 },
119 .p = { .min = 4, .max = 128 },
120 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 121 .p2 = { .dot_limit = 165000,
122 .p2_slow = 4, .p2_fast = 2 },
d4906093 123 .find_pll = intel_find_best_PLL,
e4b36699
KP		 124};
125
126static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353
AJ		 127 .dot = { .min = 25000, .max = 350000 },
128 .vco = { .min = 930000, .max = 1400000 },
129 .n = { .min = 3, .max = 16 },
130 .m = { .min = 96, .max = 140 },
131 .m1 = { .min = 18, .max = 26 },
132 .m2 = { .min = 6, .max = 16 },
133 .p = { .min = 4, .max = 128 },
134 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 135 .p2 = { .dot_limit = 165000,
136 .p2_slow = 14, .p2_fast = 7 },
d4906093 137 .find_pll = intel_find_best_PLL,
e4b36699 138};
273e27ca 139
e4b36699 140static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 141 .dot = { .min = 20000, .max = 400000 },
142 .vco = { .min = 1400000, .max = 2800000 },
143 .n = { .min = 1, .max = 6 },
144 .m = { .min = 70, .max = 120 },
145 .m1 = { .min = 10, .max = 22 },
146 .m2 = { .min = 5, .max = 9 },
147 .p = { .min = 5, .max = 80 },
148 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 149 .p2 = { .dot_limit = 200000,
150 .p2_slow = 10, .p2_fast = 5 },
d4906093 151 .find_pll = intel_find_best_PLL,
e4b36699
KP		 152};
153
154static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 155 .dot = { .min = 20000, .max = 400000 },
156 .vco = { .min = 1400000, .max = 2800000 },
157 .n = { .min = 1, .max = 6 },
158 .m = { .min = 70, .max = 120 },
159 .m1 = { .min = 10, .max = 22 },
160 .m2 = { .min = 5, .max = 9 },
161 .p = { .min = 7, .max = 98 },
162 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 163 .p2 = { .dot_limit = 112000,
164 .p2_slow = 14, .p2_fast = 7 },
d4906093 165 .find_pll = intel_find_best_PLL,
e4b36699
KP		 166};
167
273e27ca 168
e4b36699 169static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 170 .dot = { .min = 25000, .max = 270000 },
171 .vco = { .min = 1750000, .max = 3500000},
172 .n = { .min = 1, .max = 4 },
173 .m = { .min = 104, .max = 138 },
174 .m1 = { .min = 17, .max = 23 },
175 .m2 = { .min = 5, .max = 11 },
176 .p = { .min = 10, .max = 30 },
177 .p1 = { .min = 1, .max = 3},
178 .p2 = { .dot_limit = 270000,
179 .p2_slow = 10,
180 .p2_fast = 10
044c7c41 181 },
d4906093 182 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 183};
184
185static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 186 .dot = { .min = 22000, .max = 400000 },
187 .vco = { .min = 1750000, .max = 3500000},
188 .n = { .min = 1, .max = 4 },
189 .m = { .min = 104, .max = 138 },
190 .m1 = { .min = 16, .max = 23 },
191 .m2 = { .min = 5, .max = 11 },
192 .p = { .min = 5, .max = 80 },
193 .p1 = { .min = 1, .max = 8},
194 .p2 = { .dot_limit = 165000,
195 .p2_slow = 10, .p2_fast = 5 },
d4906093 196 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 197};
198
199static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 200 .dot = { .min = 20000, .max = 115000 },
201 .vco = { .min = 1750000, .max = 3500000 },
202 .n = { .min = 1, .max = 3 },
203 .m = { .min = 104, .max = 138 },
204 .m1 = { .min = 17, .max = 23 },
205 .m2 = { .min = 5, .max = 11 },
206 .p = { .min = 28, .max = 112 },
207 .p1 = { .min = 2, .max = 8 },
208 .p2 = { .dot_limit = 0,
209 .p2_slow = 14, .p2_fast = 14
044c7c41 210 },
d4906093 211 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 212};
213
214static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 215 .dot = { .min = 80000, .max = 224000 },
216 .vco = { .min = 1750000, .max = 3500000 },
217 .n = { .min = 1, .max = 3 },
218 .m = { .min = 104, .max = 138 },
219 .m1 = { .min = 17, .max = 23 },
220 .m2 = { .min = 5, .max = 11 },
221 .p = { .min = 14, .max = 42 },
222 .p1 = { .min = 2, .max = 6 },
223 .p2 = { .dot_limit = 0,
224 .p2_slow = 7, .p2_fast = 7
044c7c41 225 },
d4906093 226 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 227};
228
229static const intel_limit_t intel_limits_g4x_display_port = {
0206e353
AJ		 230 .dot = { .min = 161670, .max = 227000 },
231 .vco = { .min = 1750000, .max = 3500000},
232 .n = { .min = 1, .max = 2 },
233 .m = { .min = 97, .max = 108 },
234 .m1 = { .min = 0x10, .max = 0x12 },
235 .m2 = { .min = 0x05, .max = 0x06 },
236 .p = { .min = 10, .max = 20 },
237 .p1 = { .min = 1, .max = 2},
238 .p2 = { .dot_limit = 0,
273e27ca 239 .p2_slow = 10, .p2_fast = 10 },
0206e353 240 .find_pll = intel_find_pll_g4x_dp,
e4b36699
KP		 241};
242
f2b115e6 243static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 244 .dot = { .min = 20000, .max = 400000},
245 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 246 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 247 .n = { .min = 3, .max = 6 },
248 .m = { .min = 2, .max = 256 },
273e27ca 249 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 250 .m1 = { .min = 0, .max = 0 },
251 .m2 = { .min = 0, .max = 254 },
252 .p = { .min = 5, .max = 80 },
253 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 254 .p2 = { .dot_limit = 200000,
255 .p2_slow = 10, .p2_fast = 5 },
6115707b 256 .find_pll = intel_find_best_PLL,
e4b36699
KP		 257};
258
f2b115e6 259static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 260 .dot = { .min = 20000, .max = 400000 },
261 .vco = { .min = 1700000, .max = 3500000 },
262 .n = { .min = 3, .max = 6 },
263 .m = { .min = 2, .max = 256 },
264 .m1 = { .min = 0, .max = 0 },
265 .m2 = { .min = 0, .max = 254 },
266 .p = { .min = 7, .max = 112 },
267 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 268 .p2 = { .dot_limit = 112000,
269 .p2_slow = 14, .p2_fast = 14 },
6115707b 270 .find_pll = intel_find_best_PLL,
e4b36699
KP		 271};
272
273e27ca
EA		 273/* Ironlake / Sandybridge
274 *
275 * We calculate clock using (register_value + 2) for N/M1/M2, so here
276 * the range value for them is (actual_value - 2).
277 */
b91ad0ec 278static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 279 .dot = { .min = 25000, .max = 350000 },
280 .vco = { .min = 1760000, .max = 3510000 },
281 .n = { .min = 1, .max = 5 },
282 .m = { .min = 79, .max = 127 },
283 .m1 = { .min = 12, .max = 22 },
284 .m2 = { .min = 5, .max = 9 },
285 .p = { .min = 5, .max = 80 },
286 .p1 = { .min = 1, .max = 8 },
287 .p2 = { .dot_limit = 225000,
288 .p2_slow = 10, .p2_fast = 5 },
4547668a 289 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 290};
291
b91ad0ec 292static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 293 .dot = { .min = 25000, .max = 350000 },
294 .vco = { .min = 1760000, .max = 3510000 },
295 .n = { .min = 1, .max = 3 },
296 .m = { .min = 79, .max = 118 },
297 .m1 = { .min = 12, .max = 22 },
298 .m2 = { .min = 5, .max = 9 },
299 .p = { .min = 28, .max = 112 },
300 .p1 = { .min = 2, .max = 8 },
301 .p2 = { .dot_limit = 225000,
302 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 303 .find_pll = intel_g4x_find_best_PLL,
304};
305
306static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 307 .dot = { .min = 25000, .max = 350000 },
308 .vco = { .min = 1760000, .max = 3510000 },
309 .n = { .min = 1, .max = 3 },
310 .m = { .min = 79, .max = 127 },
311 .m1 = { .min = 12, .max = 22 },
312 .m2 = { .min = 5, .max = 9 },
313 .p = { .min = 14, .max = 56 },
314 .p1 = { .min = 2, .max = 8 },
315 .p2 = { .dot_limit = 225000,
316 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 317 .find_pll = intel_g4x_find_best_PLL,
318};
319
273e27ca 320/* LVDS 100mhz refclk limits. */
b91ad0ec 321static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 322 .dot = { .min = 25000, .max = 350000 },
323 .vco = { .min = 1760000, .max = 3510000 },
324 .n = { .min = 1, .max = 2 },
325 .m = { .min = 79, .max = 126 },
326 .m1 = { .min = 12, .max = 22 },
327 .m2 = { .min = 5, .max = 9 },
328 .p = { .min = 28, .max = 112 },
0206e353 329 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 330 .p2 = { .dot_limit = 225000,
331 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 332 .find_pll = intel_g4x_find_best_PLL,
333};
334
335static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 336 .dot = { .min = 25000, .max = 350000 },
337 .vco = { .min = 1760000, .max = 3510000 },
338 .n = { .min = 1, .max = 3 },
339 .m = { .min = 79, .max = 126 },
340 .m1 = { .min = 12, .max = 22 },
341 .m2 = { .min = 5, .max = 9 },
342 .p = { .min = 14, .max = 42 },
0206e353 343 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 344 .p2 = { .dot_limit = 225000,
345 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 346 .find_pll = intel_g4x_find_best_PLL,
347};
348
349static const intel_limit_t intel_limits_ironlake_display_port = {
0206e353
AJ		 350 .dot = { .min = 25000, .max = 350000 },
351 .vco = { .min = 1760000, .max = 3510000},
352 .n = { .min = 1, .max = 2 },
353 .m = { .min = 81, .max = 90 },
354 .m1 = { .min = 12, .max = 22 },
355 .m2 = { .min = 5, .max = 9 },
356 .p = { .min = 10, .max = 20 },
357 .p1 = { .min = 1, .max = 2},
358 .p2 = { .dot_limit = 0,
273e27ca 359 .p2_slow = 10, .p2_fast = 10 },
0206e353 360 .find_pll = intel_find_pll_ironlake_dp,
79e53945
JB		 361};
362
1b894b59
CW		 363static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
364 int refclk)
2c07245f 365{
b91ad0ec
ZW		 366 struct drm_device *dev = crtc->dev;
367 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 368 const intel_limit_t *limit;
b91ad0ec
ZW		 369
370 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
b91ad0ec
ZW		 371 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
372 LVDS_CLKB_POWER_UP) {
373 /* LVDS dual channel */
1b894b59 374 if (refclk == 100000)
b91ad0ec
ZW		 375 limit = &intel_limits_ironlake_dual_lvds_100m;
376 else
377 limit = &intel_limits_ironlake_dual_lvds;
378 } else {
1b894b59 379 if (refclk == 100000)
b91ad0ec
ZW		 380 limit = &intel_limits_ironlake_single_lvds_100m;
381 else
382 limit = &intel_limits_ironlake_single_lvds;
383 }
384 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
4547668a
ZY		 385 HAS_eDP)
386 limit = &intel_limits_ironlake_display_port;
2c07245f 387 else
b91ad0ec 388 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 389
390 return limit;
391}
392
044c7c41
ML		 393static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
394{
395 struct drm_device *dev = crtc->dev;
396 struct drm_i915_private *dev_priv = dev->dev_private;
397 const intel_limit_t *limit;
398
399 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
400 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
401 LVDS_CLKB_POWER_UP)
402 /* LVDS with dual channel */
e4b36699 403 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41
ML		 404 else
405 /* LVDS with dual channel */
e4b36699 406 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 407 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
408 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 409 limit = &intel_limits_g4x_hdmi;
044c7c41 410 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 411 limit = &intel_limits_g4x_sdvo;
0206e353 412 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
e4b36699 413 limit = &intel_limits_g4x_display_port;
044c7c41 414 } else /* The option is for other outputs */
e4b36699 415 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 416
417 return limit;
418}
419
1b894b59 420static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 421{
422 struct drm_device *dev = crtc->dev;
423 const intel_limit_t *limit;
424
bad720ff 425 if (HAS_PCH_SPLIT(dev))
1b894b59 426 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 427 else if (IS_G4X(dev)) {
044c7c41 428 limit = intel_g4x_limit(crtc);
f2b115e6 429 } else if (IS_PINEVIEW(dev)) {
2177832f 430 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 431 limit = &intel_limits_pineview_lvds;
2177832f 432 else
f2b115e6 433 limit = &intel_limits_pineview_sdvo;
a6c45cf0
CW		 434 } else if (!IS_GEN2(dev)) {
435 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
436 limit = &intel_limits_i9xx_lvds;
437 else
438 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 439 } else {
440 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 441 limit = &intel_limits_i8xx_lvds;
79e53945 442 else
e4b36699 443 limit = &intel_limits_i8xx_dvo;
79e53945
JB		 444 }
445 return limit;
446}
447
f2b115e6
AJ		 448/* m1 is reserved as 0 in Pineview, n is a ring counter */
449static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 450{
2177832f
SL		 451 clock->m = clock->m2 + 2;
452 clock->p = clock->p1 * clock->p2;
453 clock->vco = refclk * clock->m / clock->n;
454 clock->dot = clock->vco / clock->p;
455}
456
457static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
458{
f2b115e6
AJ		 459 if (IS_PINEVIEW(dev)) {
460 pineview_clock(refclk, clock);
2177832f
SL		 461 return;
462 }
79e53945
JB		 463 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
464 clock->p = clock->p1 * clock->p2;
465 clock->vco = refclk * clock->m / (clock->n + 2);
466 clock->dot = clock->vco / clock->p;
467}
468
79e53945
JB		 469/**
470 * Returns whether any output on the specified pipe is of the specified type
471 */
4ef69c7a 472bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
79e53945 473{
4ef69c7a
CW		 474 struct drm_device *dev = crtc->dev;
475 struct drm_mode_config *mode_config = &dev->mode_config;
476 struct intel_encoder *encoder;
477
478 list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
479 if (encoder->base.crtc == crtc && encoder->type == type)
480 return true;
481
482 return false;
79e53945
JB		 483}
484
7c04d1d9 485#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 486/**
487 * Returns whether the given set of divisors are valid for a given refclk with
488 * the given connectors.
489 */
490
1b894b59
CW		 491static bool intel_PLL_is_valid(struct drm_device *dev,
492 const intel_limit_t *limit,
493 const intel_clock_t *clock)
79e53945 494{
79e53945 495 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 496 INTELPllInvalid("p1 out of range\n");
79e53945 497 if (clock->p < limit->p.min || limit->p.max < clock->p)
0206e353 498 INTELPllInvalid("p out of range\n");
79e53945 499 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 500 INTELPllInvalid("m2 out of range\n");
79e53945 501 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 502 INTELPllInvalid("m1 out of range\n");
f2b115e6 503 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
0206e353 504 INTELPllInvalid("m1 <= m2\n");
79e53945 505 if (clock->m < limit->m.min || limit->m.max < clock->m)
0206e353 506 INTELPllInvalid("m out of range\n");
79e53945 507 if (clock->n < limit->n.min || limit->n.max < clock->n)
0206e353 508 INTELPllInvalid("n out of range\n");
79e53945 509 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 510 INTELPllInvalid("vco out of range\n");
79e53945
JB		 511 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
512 * connector, etc., rather than just a single range.
513 */
514 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 515 INTELPllInvalid("dot out of range\n");
79e53945
JB		 516
517 return true;
518}
519
d4906093
ML		 520static bool
521intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 522 int target, int refclk, intel_clock_t *match_clock,
523 intel_clock_t *best_clock)
d4906093 524
79e53945
JB		 525{
526 struct drm_device *dev = crtc->dev;
527 struct drm_i915_private *dev_priv = dev->dev_private;
528 intel_clock_t clock;
79e53945
JB		 529 int err = target;
530
bc5e5718 531 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
832cc28d 532 (I915_READ(LVDS)) != 0) {
79e53945
JB		 533 /*
534 * For LVDS, if the panel is on, just rely on its current
535 * settings for dual-channel. We haven't figured out how to
536 * reliably set up different single/dual channel state, if we
537 * even can.
538 */
539 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
540 LVDS_CLKB_POWER_UP)
541 clock.p2 = limit->p2.p2_fast;
542 else
543 clock.p2 = limit->p2.p2_slow;
544 } else {
545 if (target < limit->p2.dot_limit)
546 clock.p2 = limit->p2.p2_slow;
547 else
548 clock.p2 = limit->p2.p2_fast;
549 }
550
0206e353 551 memset(best_clock, 0, sizeof(*best_clock));
79e53945 552
42158660
ZY		 553 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
554 clock.m1++) {
555 for (clock.m2 = limit->m2.min;
556 clock.m2 <= limit->m2.max; clock.m2++) {
f2b115e6
AJ		 557 /* m1 is always 0 in Pineview */
558 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
42158660
ZY		 559 break;
560 for (clock.n = limit->n.min;
561 clock.n <= limit->n.max; clock.n++) {
562 for (clock.p1 = limit->p1.min;
563 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 564 int this_err;
565
2177832f 566 intel_clock(dev, refclk, &clock);
1b894b59
CW		 567 if (!intel_PLL_is_valid(dev, limit,
568 &clock))
79e53945 569 continue;
cec2f356
SP		 570 if (match_clock &&
571 clock.p != match_clock->p)
572 continue;
79e53945
JB		 573
574 this_err = abs(clock.dot - target);
575 if (this_err < err) {
576 *best_clock = clock;
577 err = this_err;
578 }
579 }
580 }
581 }
582 }
583
584 return (err != target);
585}
586
d4906093
ML		 587static bool
588intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 589 int target, int refclk, intel_clock_t *match_clock,
590 intel_clock_t *best_clock)
d4906093
ML		 591{
592 struct drm_device *dev = crtc->dev;
593 struct drm_i915_private *dev_priv = dev->dev_private;
594 intel_clock_t clock;
595 int max_n;
596 bool found;
6ba770dc
AJ		 597 /* approximately equals target * 0.00585 */
598 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 599 found = false;
600
601 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4547668a
ZY		 602 int lvds_reg;
603
c619eed4 604 if (HAS_PCH_SPLIT(dev))
4547668a
ZY		 605 lvds_reg = PCH_LVDS;
606 else
607 lvds_reg = LVDS;
608 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
d4906093
ML		 609 LVDS_CLKB_POWER_UP)
610 clock.p2 = limit->p2.p2_fast;
611 else
612 clock.p2 = limit->p2.p2_slow;
613 } else {
614 if (target < limit->p2.dot_limit)
615 clock.p2 = limit->p2.p2_slow;
616 else
617 clock.p2 = limit->p2.p2_fast;
618 }
619
620 memset(best_clock, 0, sizeof(*best_clock));
621 max_n = limit->n.max;
f77f13e2 622 /* based on hardware requirement, prefer smaller n to precision */
d4906093 623 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 624 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 625 for (clock.m1 = limit->m1.max;
626 clock.m1 >= limit->m1.min; clock.m1--) {
627 for (clock.m2 = limit->m2.max;
628 clock.m2 >= limit->m2.min; clock.m2--) {
629 for (clock.p1 = limit->p1.max;
630 clock.p1 >= limit->p1.min; clock.p1--) {
631 int this_err;
632
2177832f 633 intel_clock(dev, refclk, &clock);
1b894b59
CW		 634 if (!intel_PLL_is_valid(dev, limit,
635 &clock))
d4906093 636 continue;
cec2f356
SP		 637 if (match_clock &&
638 clock.p != match_clock->p)
639 continue;
1b894b59
CW		 640
641 this_err = abs(clock.dot - target);
d4906093
ML		 642 if (this_err < err_most) {
643 *best_clock = clock;
644 err_most = this_err;
645 max_n = clock.n;
646 found = true;
647 }
648 }
649 }
650 }
651 }
2c07245f
ZW		 652 return found;
653}
654
5eb08b69 655static bool
f2b115e6 656intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 657 int target, int refclk, intel_clock_t *match_clock,
658 intel_clock_t *best_clock)
5eb08b69
ZW		 659{
660 struct drm_device *dev = crtc->dev;
661 intel_clock_t clock;
4547668a 662
5eb08b69
ZW		 663 if (target < 200000) {
664 clock.n = 1;
665 clock.p1 = 2;
666 clock.p2 = 10;
667 clock.m1 = 12;
668 clock.m2 = 9;
669 } else {
670 clock.n = 2;
671 clock.p1 = 1;
672 clock.p2 = 10;
673 clock.m1 = 14;
674 clock.m2 = 8;
675 }
676 intel_clock(dev, refclk, &clock);
677 memcpy(best_clock, &clock, sizeof(intel_clock_t));
678 return true;
679}
680
a4fc5ed6
KP		 681/* DisplayPort has only two frequencies, 162MHz and 270MHz */
682static bool
683intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 684 int target, int refclk, intel_clock_t *match_clock,
685 intel_clock_t *best_clock)
a4fc5ed6 686{
5eddb70b
CW		 687 intel_clock_t clock;
688 if (target < 200000) {
689 clock.p1 = 2;
690 clock.p2 = 10;
691 clock.n = 2;
692 clock.m1 = 23;
693 clock.m2 = 8;
694 } else {
695 clock.p1 = 1;
696 clock.p2 = 10;
697 clock.n = 1;
698 clock.m1 = 14;
699 clock.m2 = 2;
700 }
701 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
702 clock.p = (clock.p1 * clock.p2);
703 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
704 clock.vco = 0;
705 memcpy(best_clock, &clock, sizeof(intel_clock_t));
706 return true;
a4fc5ed6
KP		 707}
708
9d0498a2
JB		 709/**
710 * intel_wait_for_vblank - wait for vblank on a given pipe
711 * @dev: drm device
712 * @pipe: pipe to wait for
713 *
714 * Wait for vblank to occur on a given pipe. Needed for various bits of
715 * mode setting code.
716 */
717void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 718{
9d0498a2 719 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 720 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 721
300387c0
CW		 722 /* Clear existing vblank status. Note this will clear any other
723 * sticky status fields as well.
724 *
725 * This races with i915_driver_irq_handler() with the result
726 * that either function could miss a vblank event. Here it is not
727 * fatal, as we will either wait upon the next vblank interrupt or
728 * timeout. Generally speaking intel_wait_for_vblank() is only
729 * called during modeset at which time the GPU should be idle and
730 * should *not* be performing page flips and thus not waiting on
731 * vblanks...
732 * Currently, the result of us stealing a vblank from the irq
733 * handler is that a single frame will be skipped during swapbuffers.
734 */
735 I915_WRITE(pipestat_reg,
736 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
737
9d0498a2 738 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 739 if (wait_for(I915_READ(pipestat_reg) &
740 PIPE_VBLANK_INTERRUPT_STATUS,
741 50))
9d0498a2
JB		 742 DRM_DEBUG_KMS("vblank wait timed out\n");
743}
744
ab7ad7f6
KP		 745/*
746 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 747 * @dev: drm device
748 * @pipe: pipe to wait for
749 *
750 * After disabling a pipe, we can't wait for vblank in the usual way,
751 * spinning on the vblank interrupt status bit, since we won't actually
752 * see an interrupt when the pipe is disabled.
753 *
ab7ad7f6
KP		 754 * On Gen4 and above:
755 * wait for the pipe register state bit to turn off
756 *
757 * Otherwise:
758 * wait for the display line value to settle (it usually
759 * ends up stopping at the start of the next frame).
58e10eb9 760 *
9d0498a2 761 */
58e10eb9 762void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 763{
764 struct drm_i915_private *dev_priv = dev->dev_private;
ab7ad7f6
KP		 765
766 if (INTEL_INFO(dev)->gen >= 4) {
58e10eb9 767 int reg = PIPECONF(pipe);
ab7ad7f6
KP		 768
769 /* Wait for the Pipe State to go off */
58e10eb9
CW		 770 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
771 100))
ab7ad7f6
KP		 772 DRM_DEBUG_KMS("pipe_off wait timed out\n");
773 } else {
774 u32 last_line;
58e10eb9 775 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 776 unsigned long timeout = jiffies + msecs_to_jiffies(100);
777
778 /* Wait for the display line to settle */
779 do {
58e10eb9 780 last_line = I915_READ(reg) & DSL_LINEMASK;
ab7ad7f6 781 mdelay(5);
58e10eb9 782 } while (((I915_READ(reg) & DSL_LINEMASK) != last_line) &&
ab7ad7f6
KP		 783 time_after(timeout, jiffies));
784 if (time_after(jiffies, timeout))
785 DRM_DEBUG_KMS("pipe_off wait timed out\n");
786 }
79e53945
JB		 787}
788
b24e7179
JB		 789static const char *state_string(bool enabled)
790{
791 return enabled ? "on" : "off";
792}
793
794/* Only for pre-ILK configs */
795static void assert_pll(struct drm_i915_private *dev_priv,
796 enum pipe pipe, bool state)
797{
798 int reg;
799 u32 val;
800 bool cur_state;
801
802 reg = DPLL(pipe);
803 val = I915_READ(reg);
804 cur_state = !!(val & DPLL_VCO_ENABLE);
805 WARN(cur_state != state,
806 "PLL state assertion failure (expected %s, current %s)\n",
807 state_string(state), state_string(cur_state));
808}
809#define assert_pll_enabled(d, p) assert_pll(d, p, true)
810#define assert_pll_disabled(d, p) assert_pll(d, p, false)
811
040484af
JB		 812/* For ILK+ */
813static void assert_pch_pll(struct drm_i915_private *dev_priv,
814 enum pipe pipe, bool state)
815{
816 int reg;
817 u32 val;
818 bool cur_state;
819
d3ccbe86
JB		 820 if (HAS_PCH_CPT(dev_priv->dev)) {
821 u32 pch_dpll;
822
823 pch_dpll = I915_READ(PCH_DPLL_SEL);
824
825 /* Make sure the selected PLL is enabled to the transcoder */
826 WARN(!((pch_dpll >> (4 * pipe)) & 8),
827 "transcoder %d PLL not enabled\n", pipe);
828
829 /* Convert the transcoder pipe number to a pll pipe number */
830 pipe = (pch_dpll >> (4 * pipe)) & 1;
831 }
832
040484af
JB		 833 reg = PCH_DPLL(pipe);
834 val = I915_READ(reg);
835 cur_state = !!(val & DPLL_VCO_ENABLE);
836 WARN(cur_state != state,
837 "PCH PLL state assertion failure (expected %s, current %s)\n",
838 state_string(state), state_string(cur_state));
839}
840#define assert_pch_pll_enabled(d, p) assert_pch_pll(d, p, true)
841#define assert_pch_pll_disabled(d, p) assert_pch_pll(d, p, false)
842
843static void assert_fdi_tx(struct drm_i915_private *dev_priv,
844 enum pipe pipe, bool state)
845{
846 int reg;
847 u32 val;
848 bool cur_state;
849
850 reg = FDI_TX_CTL(pipe);
851 val = I915_READ(reg);
852 cur_state = !!(val & FDI_TX_ENABLE);
853 WARN(cur_state != state,
854 "FDI TX state assertion failure (expected %s, current %s)\n",
855 state_string(state), state_string(cur_state));
856}
857#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
858#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
859
860static void assert_fdi_rx(struct drm_i915_private *dev_priv,
861 enum pipe pipe, bool state)
862{
863 int reg;
864 u32 val;
865 bool cur_state;
866
867 reg = FDI_RX_CTL(pipe);
868 val = I915_READ(reg);
869 cur_state = !!(val & FDI_RX_ENABLE);
870 WARN(cur_state != state,
871 "FDI RX state assertion failure (expected %s, current %s)\n",
872 state_string(state), state_string(cur_state));
873}
874#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
875#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
876
877static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
878 enum pipe pipe)
879{
880 int reg;
881 u32 val;
882
883 /* ILK FDI PLL is always enabled */
884 if (dev_priv->info->gen == 5)
885 return;
886
887 reg = FDI_TX_CTL(pipe);
888 val = I915_READ(reg);
889 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
890}
891
892static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
893 enum pipe pipe)
894{
895 int reg;
896 u32 val;
897
898 reg = FDI_RX_CTL(pipe);
899 val = I915_READ(reg);
900 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
901}
902
ea0760cf
JB		 903static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
904 enum pipe pipe)
905{
906 int pp_reg, lvds_reg;
907 u32 val;
908 enum pipe panel_pipe = PIPE_A;
0de3b485 909 bool locked = true;
ea0760cf
JB		 910
911 if (HAS_PCH_SPLIT(dev_priv->dev)) {
912 pp_reg = PCH_PP_CONTROL;
913 lvds_reg = PCH_LVDS;
914 } else {
915 pp_reg = PP_CONTROL;
916 lvds_reg = LVDS;
917 }
918
919 val = I915_READ(pp_reg);
920 if (!(val & PANEL_POWER_ON) ||
921 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
922 locked = false;
923
924 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
925 panel_pipe = PIPE_B;
926
927 WARN(panel_pipe == pipe && locked,
928 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 929 pipe_name(pipe));
ea0760cf
JB		 930}
931
b840d907
JB		 932void assert_pipe(struct drm_i915_private *dev_priv,
933 enum pipe pipe, bool state)
b24e7179
JB		 934{
935 int reg;
936 u32 val;
63d7bbe9 937 bool cur_state;
b24e7179 938
8e636784
DV		 939 /* if we need the pipe A quirk it must be always on */
940 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
941 state = true;
942
b24e7179
JB		 943 reg = PIPECONF(pipe);
944 val = I915_READ(reg);
63d7bbe9
JB		 945 cur_state = !!(val & PIPECONF_ENABLE);
946 WARN(cur_state != state,
947 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 948 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 949}
950
931872fc
CW		 951static void assert_plane(struct drm_i915_private *dev_priv,
952 enum plane plane, bool state)
b24e7179
JB		 953{
954 int reg;
955 u32 val;
931872fc 956 bool cur_state;
b24e7179
JB		 957
958 reg = DSPCNTR(plane);
959 val = I915_READ(reg);
931872fc
CW		 960 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
961 WARN(cur_state != state,
962 "plane %c assertion failure (expected %s, current %s)\n",
963 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 964}
965
931872fc
CW		 966#define assert_plane_enabled(d, p) assert_plane(d, p, true)
967#define assert_plane_disabled(d, p) assert_plane(d, p, false)
968
b24e7179
JB		 969static void assert_planes_disabled(struct drm_i915_private *dev_priv,
970 enum pipe pipe)
971{
972 int reg, i;
973 u32 val;
974 int cur_pipe;
975
19ec1358 976 /* Planes are fixed to pipes on ILK+ */
28c05794
AJ		 977 if (HAS_PCH_SPLIT(dev_priv->dev)) {
978 reg = DSPCNTR(pipe);
979 val = I915_READ(reg);
980 WARN((val & DISPLAY_PLANE_ENABLE),
981 "plane %c assertion failure, should be disabled but not\n",
982 plane_name(pipe));
19ec1358 983 return;
28c05794 984 }
19ec1358 985
b24e7179
JB		 986 /* Need to check both planes against the pipe */
987 for (i = 0; i < 2; i++) {
988 reg = DSPCNTR(i);
989 val = I915_READ(reg);
990 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
991 DISPPLANE_SEL_PIPE_SHIFT;
992 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 993 "plane %c assertion failure, should be off on pipe %c but is still active\n",
994 plane_name(i), pipe_name(pipe));
b24e7179
JB		 995 }
996}
997
92f2584a
JB		 998static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
999{
1000 u32 val;
1001 bool enabled;
1002
1003 val = I915_READ(PCH_DREF_CONTROL);
1004 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1005 DREF_SUPERSPREAD_SOURCE_MASK));
1006 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1007}
1008
1009static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1010 enum pipe pipe)
1011{
1012 int reg;
1013 u32 val;
1014 bool enabled;
1015
1016 reg = TRANSCONF(pipe);
1017 val = I915_READ(reg);
1018 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 1019 WARN(enabled,
1020 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1021 pipe_name(pipe));
92f2584a
JB		 1022}
1023
4e634389
KP		 1024static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1025 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1026{
1027 if ((val & DP_PORT_EN) == 0)
1028 return false;
1029
1030 if (HAS_PCH_CPT(dev_priv->dev)) {
1031 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1032 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1033 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1034 return false;
1035 } else {
1036 if ((val & DP_PIPE_MASK) != (pipe << 30))
1037 return false;
1038 }
1039 return true;
1040}
1041
1519b995
KP		 1042static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1043 enum pipe pipe, u32 val)
1044{
1045 if ((val & PORT_ENABLE) == 0)
1046 return false;
1047
1048 if (HAS_PCH_CPT(dev_priv->dev)) {
1049 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1050 return false;
1051 } else {
1052 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1053 return false;
1054 }
1055 return true;
1056}
1057
1058static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1059 enum pipe pipe, u32 val)
1060{
1061 if ((val & LVDS_PORT_EN) == 0)
1062 return false;
1063
1064 if (HAS_PCH_CPT(dev_priv->dev)) {
1065 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1066 return false;
1067 } else {
1068 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1069 return false;
1070 }
1071 return true;
1072}
1073
1074static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1075 enum pipe pipe, u32 val)
1076{
1077 if ((val & ADPA_DAC_ENABLE) == 0)
1078 return false;
1079 if (HAS_PCH_CPT(dev_priv->dev)) {
1080 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1081 return false;
1082 } else {
1083 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1084 return false;
1085 }
1086 return true;
1087}
1088
291906f1 1089static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1090 enum pipe pipe, int reg, u32 port_sel)
291906f1 1091{
47a05eca 1092 u32 val = I915_READ(reg);
4e634389 1093 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1094 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1095 reg, pipe_name(pipe));
291906f1
JB		 1096}
1097
1098static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1099 enum pipe pipe, int reg)
1100{
47a05eca 1101 u32 val = I915_READ(reg);
1519b995 1102 WARN(hdmi_pipe_enabled(dev_priv, val, pipe),
23c99e77 1103 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1104 reg, pipe_name(pipe));
291906f1
JB		 1105}
1106
1107static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1108 enum pipe pipe)
1109{
1110 int reg;
1111 u32 val;
291906f1 1112
f0575e92
KP		 1113 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1114 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1115 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1116
1117 reg = PCH_ADPA;
1118 val = I915_READ(reg);
1519b995 1119 WARN(adpa_pipe_enabled(dev_priv, val, pipe),
291906f1 1120 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1121 pipe_name(pipe));
291906f1
JB		 1122
1123 reg = PCH_LVDS;
1124 val = I915_READ(reg);
1519b995 1125 WARN(lvds_pipe_enabled(dev_priv, val, pipe),
291906f1 1126 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1127 pipe_name(pipe));
291906f1
JB		 1128
1129 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1130 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1131 assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1132}
1133
63d7bbe9
JB		 1134/**
1135 * intel_enable_pll - enable a PLL
1136 * @dev_priv: i915 private structure
1137 * @pipe: pipe PLL to enable
1138 *
1139 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1140 * make sure the PLL reg is writable first though, since the panel write
1141 * protect mechanism may be enabled.
1142 *
1143 * Note! This is for pre-ILK only.
1144 */
1145static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1146{
1147 int reg;
1148 u32 val;
1149
1150 /* No really, not for ILK+ */
1151 BUG_ON(dev_priv->info->gen >= 5);
1152
1153 /* PLL is protected by panel, make sure we can write it */
1154 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1155 assert_panel_unlocked(dev_priv, pipe);
1156
1157 reg = DPLL(pipe);
1158 val = I915_READ(reg);
1159 val |= DPLL_VCO_ENABLE;
1160
1161 /* We do this three times for luck */
1162 I915_WRITE(reg, val);
1163 POSTING_READ(reg);
1164 udelay(150); /* wait for warmup */
1165 I915_WRITE(reg, val);
1166 POSTING_READ(reg);
1167 udelay(150); /* wait for warmup */
1168 I915_WRITE(reg, val);
1169 POSTING_READ(reg);
1170 udelay(150); /* wait for warmup */
1171}
1172
1173/**
1174 * intel_disable_pll - disable a PLL
1175 * @dev_priv: i915 private structure
1176 * @pipe: pipe PLL to disable
1177 *
1178 * Disable the PLL for @pipe, making sure the pipe is off first.
1179 *
1180 * Note! This is for pre-ILK only.
1181 */
1182static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1183{
1184 int reg;
1185 u32 val;
1186
1187 /* Don't disable pipe A or pipe A PLLs if needed */
1188 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1189 return;
1190
1191 /* Make sure the pipe isn't still relying on us */
1192 assert_pipe_disabled(dev_priv, pipe);
1193
1194 reg = DPLL(pipe);
1195 val = I915_READ(reg);
1196 val &= ~DPLL_VCO_ENABLE;
1197 I915_WRITE(reg, val);
1198 POSTING_READ(reg);
1199}
1200
92f2584a
JB		 1201/**
1202 * intel_enable_pch_pll - enable PCH PLL
1203 * @dev_priv: i915 private structure
1204 * @pipe: pipe PLL to enable
1205 *
1206 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1207 * drives the transcoder clock.
1208 */
1209static void intel_enable_pch_pll(struct drm_i915_private *dev_priv,
1210 enum pipe pipe)
1211{
1212 int reg;
1213 u32 val;
1214
4c609cb8
JB		 1215 if (pipe > 1)
1216 return;
1217
92f2584a
JB		 1218 /* PCH only available on ILK+ */
1219 BUG_ON(dev_priv->info->gen < 5);
1220
1221 /* PCH refclock must be enabled first */
1222 assert_pch_refclk_enabled(dev_priv);
1223
1224 reg = PCH_DPLL(pipe);
1225 val = I915_READ(reg);
1226 val |= DPLL_VCO_ENABLE;
1227 I915_WRITE(reg, val);
1228 POSTING_READ(reg);
1229 udelay(200);
1230}
1231
1232static void intel_disable_pch_pll(struct drm_i915_private *dev_priv,
1233 enum pipe pipe)
1234{
1235 int reg;
7a419866
JB		 1236 u32 val, pll_mask = TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL,
1237 pll_sel = TRANSC_DPLL_ENABLE;
92f2584a 1238
4c609cb8
JB		 1239 if (pipe > 1)
1240 return;
1241
92f2584a
JB		 1242 /* PCH only available on ILK+ */
1243 BUG_ON(dev_priv->info->gen < 5);
1244
1245 /* Make sure transcoder isn't still depending on us */
1246 assert_transcoder_disabled(dev_priv, pipe);
1247
7a419866
JB		 1248 if (pipe == 0)
1249 pll_sel |= TRANSC_DPLLA_SEL;
1250 else if (pipe == 1)
1251 pll_sel |= TRANSC_DPLLB_SEL;
1252
1253
1254 if ((I915_READ(PCH_DPLL_SEL) & pll_mask) == pll_sel)
1255 return;
1256
92f2584a
JB		 1257 reg = PCH_DPLL(pipe);
1258 val = I915_READ(reg);
1259 val &= ~DPLL_VCO_ENABLE;
1260 I915_WRITE(reg, val);
1261 POSTING_READ(reg);
1262 udelay(200);
1263}
1264
040484af
JB		 1265static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1266 enum pipe pipe)
1267{
1268 int reg;
5f7f726d 1269 u32 val, pipeconf_val;
7c26e5c6 1270 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
040484af
JB		 1271
1272 /* PCH only available on ILK+ */
1273 BUG_ON(dev_priv->info->gen < 5);
1274
1275 /* Make sure PCH DPLL is enabled */
1276 assert_pch_pll_enabled(dev_priv, pipe);
1277
1278 /* FDI must be feeding us bits for PCH ports */
1279 assert_fdi_tx_enabled(dev_priv, pipe);
1280 assert_fdi_rx_enabled(dev_priv, pipe);
1281
1282 reg = TRANSCONF(pipe);
1283 val = I915_READ(reg);
5f7f726d 1284 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1285
1286 if (HAS_PCH_IBX(dev_priv->dev)) {
1287 /*
1288 * make the BPC in transcoder be consistent with
1289 * that in pipeconf reg.
1290 */
1291 val &= ~PIPE_BPC_MASK;
5f7f726d 1292 val |= pipeconf_val & PIPE_BPC_MASK;
e9bcff5c 1293 }
5f7f726d
PZ		 1294
1295 val &= ~TRANS_INTERLACE_MASK;
1296 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6
PZ		 1297 if (HAS_PCH_IBX(dev_priv->dev) &&
1298 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1299 val |= TRANS_LEGACY_INTERLACED_ILK;
1300 else
1301 val |= TRANS_INTERLACED;
5f7f726d
PZ		 1302 else
1303 val |= TRANS_PROGRESSIVE;
1304
040484af
JB		 1305 I915_WRITE(reg, val | TRANS_ENABLE);
1306 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1307 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1308}
1309
1310static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1311 enum pipe pipe)
1312{
1313 int reg;
1314 u32 val;
1315
1316 /* FDI relies on the transcoder */
1317 assert_fdi_tx_disabled(dev_priv, pipe);
1318 assert_fdi_rx_disabled(dev_priv, pipe);
1319
291906f1
JB		 1320 /* Ports must be off as well */
1321 assert_pch_ports_disabled(dev_priv, pipe);
1322
040484af
JB		 1323 reg = TRANSCONF(pipe);
1324 val = I915_READ(reg);
1325 val &= ~TRANS_ENABLE;
1326 I915_WRITE(reg, val);
1327 /* wait for PCH transcoder off, transcoder state */
1328 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4c9c18c2 1329 DRM_ERROR("failed to disable transcoder %d\n", pipe);
040484af
JB		 1330}
1331
b24e7179 1332/**
309cfea8 1333 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1334 * @dev_priv: i915 private structure
1335 * @pipe: pipe to enable
040484af 1336 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1337 *
1338 * Enable @pipe, making sure that various hardware specific requirements
1339 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1340 *
1341 * @pipe should be %PIPE_A or %PIPE_B.
1342 *
1343 * Will wait until the pipe is actually running (i.e. first vblank) before
1344 * returning.
1345 */
040484af
JB		 1346static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1347 bool pch_port)
b24e7179
JB		 1348{
1349 int reg;
1350 u32 val;
1351
1352 /*
1353 * A pipe without a PLL won't actually be able to drive bits from
1354 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1355 * need the check.
1356 */
1357 if (!HAS_PCH_SPLIT(dev_priv->dev))
1358 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1359 else {
1360 if (pch_port) {
1361 /* if driving the PCH, we need FDI enabled */
1362 assert_fdi_rx_pll_enabled(dev_priv, pipe);
1363 assert_fdi_tx_pll_enabled(dev_priv, pipe);
1364 }
1365 /* FIXME: assert CPU port conditions for SNB+ */
1366 }
b24e7179
JB		 1367
1368 reg = PIPECONF(pipe);
1369 val = I915_READ(reg);
00d70b15
CW		 1370 if (val & PIPECONF_ENABLE)
1371 return;
1372
1373 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1374 intel_wait_for_vblank(dev_priv->dev, pipe);
1375}
1376
1377/**
309cfea8 1378 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1379 * @dev_priv: i915 private structure
1380 * @pipe: pipe to disable
1381 *
1382 * Disable @pipe, making sure that various hardware specific requirements
1383 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1384 *
1385 * @pipe should be %PIPE_A or %PIPE_B.
1386 *
1387 * Will wait until the pipe has shut down before returning.
1388 */
1389static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1390 enum pipe pipe)
1391{
1392 int reg;
1393 u32 val;
1394
1395 /*
1396 * Make sure planes won't keep trying to pump pixels to us,
1397 * or we might hang the display.
1398 */
1399 assert_planes_disabled(dev_priv, pipe);
1400
1401 /* Don't disable pipe A or pipe A PLLs if needed */
1402 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1403 return;
1404
1405 reg = PIPECONF(pipe);
1406 val = I915_READ(reg);
00d70b15
CW		 1407 if ((val & PIPECONF_ENABLE) == 0)
1408 return;
1409
1410 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1411 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1412}
1413
d74362c9
KP		 1414/*
1415 * Plane regs are double buffered, going from enabled->disabled needs a
1416 * trigger in order to latch. The display address reg provides this.
1417 */
1418static void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1419 enum plane plane)
1420{
1421 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1422 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1423}
1424
b24e7179
JB		 1425/**
1426 * intel_enable_plane - enable a display plane on a given pipe
1427 * @dev_priv: i915 private structure
1428 * @plane: plane to enable
1429 * @pipe: pipe being fed
1430 *
1431 * Enable @plane on @pipe, making sure that @pipe is running first.
1432 */
1433static void intel_enable_plane(struct drm_i915_private *dev_priv,
1434 enum plane plane, enum pipe pipe)
1435{
1436 int reg;
1437 u32 val;
1438
1439 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1440 assert_pipe_enabled(dev_priv, pipe);
1441
1442 reg = DSPCNTR(plane);
1443 val = I915_READ(reg);
00d70b15
CW		 1444 if (val & DISPLAY_PLANE_ENABLE)
1445 return;
1446
1447 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
d74362c9 1448 intel_flush_display_plane(dev_priv, plane);
b24e7179
JB		 1449 intel_wait_for_vblank(dev_priv->dev, pipe);
1450}
1451
b24e7179
JB		 1452/**
1453 * intel_disable_plane - disable a display plane
1454 * @dev_priv: i915 private structure
1455 * @plane: plane to disable
1456 * @pipe: pipe consuming the data
1457 *
1458 * Disable @plane; should be an independent operation.
1459 */
1460static void intel_disable_plane(struct drm_i915_private *dev_priv,
1461 enum plane plane, enum pipe pipe)
1462{
1463 int reg;
1464 u32 val;
1465
1466 reg = DSPCNTR(plane);
1467 val = I915_READ(reg);
00d70b15
CW		 1468 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1469 return;
1470
1471 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1472 intel_flush_display_plane(dev_priv, plane);
1473 intel_wait_for_vblank(dev_priv->dev, pipe);
1474}
1475
47a05eca 1476static void disable_pch_dp(struct drm_i915_private *dev_priv,
f0575e92 1477 enum pipe pipe, int reg, u32 port_sel)
47a05eca
JB		 1478{
1479 u32 val = I915_READ(reg);
4e634389 1480 if (dp_pipe_enabled(dev_priv, pipe, port_sel, val)) {
f0575e92 1481 DRM_DEBUG_KMS("Disabling pch dp %x on pipe %d\n", reg, pipe);
47a05eca 1482 I915_WRITE(reg, val & ~DP_PORT_EN);
f0575e92 1483 }
47a05eca
JB		 1484}
1485
1486static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
1487 enum pipe pipe, int reg)
1488{
1489 u32 val = I915_READ(reg);
1519b995 1490 if (hdmi_pipe_enabled(dev_priv, val, pipe)) {
f0575e92
KP		 1491 DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n",
1492 reg, pipe);
47a05eca 1493 I915_WRITE(reg, val & ~PORT_ENABLE);
f0575e92 1494 }
47a05eca
JB		 1495}
1496
1497/* Disable any ports connected to this transcoder */
1498static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
1499 enum pipe pipe)
1500{
1501 u32 reg, val;
1502
1503 val = I915_READ(PCH_PP_CONTROL);
1504 I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS);
1505
f0575e92
KP		 1506 disable_pch_dp(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1507 disable_pch_dp(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1508 disable_pch_dp(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
47a05eca
JB		 1509
1510 reg = PCH_ADPA;
1511 val = I915_READ(reg);
1519b995 1512 if (adpa_pipe_enabled(dev_priv, val, pipe))
47a05eca
JB		 1513 I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);
1514
1515 reg = PCH_LVDS;
1516 val = I915_READ(reg);
1519b995
KP		 1517 if (lvds_pipe_enabled(dev_priv, val, pipe)) {
1518 DRM_DEBUG_KMS("disable lvds on pipe %d val 0x%08x\n", pipe, val);
47a05eca
JB		 1519 I915_WRITE(reg, val & ~LVDS_PORT_EN);
1520 POSTING_READ(reg);
1521 udelay(100);
1522 }
1523
1524 disable_pch_hdmi(dev_priv, pipe, HDMIB);
1525 disable_pch_hdmi(dev_priv, pipe, HDMIC);
1526 disable_pch_hdmi(dev_priv, pipe, HDMID);
1527}
1528
43a9539f
CW		 1529static void i8xx_disable_fbc(struct drm_device *dev)
1530{
1531 struct drm_i915_private *dev_priv = dev->dev_private;
1532 u32 fbc_ctl;
1533
1534 /* Disable compression */
1535 fbc_ctl = I915_READ(FBC_CONTROL);
1536 if ((fbc_ctl & FBC_CTL_EN) == 0)
1537 return;
1538
1539 fbc_ctl &= ~FBC_CTL_EN;
1540 I915_WRITE(FBC_CONTROL, fbc_ctl);
1541
1542 /* Wait for compressing bit to clear */
1543 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
1544 DRM_DEBUG_KMS("FBC idle timed out\n");
1545 return;
1546 }
1547
1548 DRM_DEBUG_KMS("disabled FBC\n");
1549}
1550
80824003
JB		 1551static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1552{
1553 struct drm_device *dev = crtc->dev;
1554 struct drm_i915_private *dev_priv = dev->dev_private;
1555 struct drm_framebuffer *fb = crtc->fb;
1556 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 1557 struct drm_i915_gem_object *obj = intel_fb->obj;
80824003 1558 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
016b9b61 1559 int cfb_pitch;
80824003
JB		 1560 int plane, i;
1561 u32 fbc_ctl, fbc_ctl2;
1562
016b9b61 1563 cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
01f2c773
VS		 1564 if (fb->pitches[0] < cfb_pitch)
1565 cfb_pitch = fb->pitches[0];
80824003
JB		 1566
1567 /* FBC_CTL wants 64B units */
016b9b61
CW		 1568 cfb_pitch = (cfb_pitch / 64) - 1;
1569 plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
80824003
JB		 1570
1571 /* Clear old tags */
1572 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1573 I915_WRITE(FBC_TAG + (i * 4), 0);
1574
1575 /* Set it up... */
de568510
CW		 1576 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
1577 fbc_ctl2 |= plane;
80824003
JB		 1578 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1579 I915_WRITE(FBC_FENCE_OFF, crtc->y);
1580
1581 /* enable it... */
1582 fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
ee25df2b 1583 if (IS_I945GM(dev))
49677901 1584 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
016b9b61 1585 fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
80824003 1586 fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
016b9b61 1587 fbc_ctl |= obj->fence_reg;
80824003
JB		 1588 I915_WRITE(FBC_CONTROL, fbc_ctl);
1589
016b9b61
CW		 1590 DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %d, ",
1591 cfb_pitch, crtc->y, intel_crtc->plane);
80824003
JB		 1592}
1593
ee5382ae 1594static bool i8xx_fbc_enabled(struct drm_device *dev)
80824003 1595{
80824003
JB		 1596 struct drm_i915_private *dev_priv = dev->dev_private;
1597
1598 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1599}
1600
74dff282
JB		 1601static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1602{
1603 struct drm_device *dev = crtc->dev;
1604 struct drm_i915_private *dev_priv = dev->dev_private;
1605 struct drm_framebuffer *fb = crtc->fb;
1606 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 1607 struct drm_i915_gem_object *obj = intel_fb->obj;
74dff282 1608 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5eddb70b 1609 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
74dff282
JB		 1610 unsigned long stall_watermark = 200;
1611 u32 dpfc_ctl;
1612
74dff282 1613 dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
016b9b61 1614 dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
de568510 1615 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
74dff282 1616
74dff282
JB		 1617 I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1618 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1619 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1620 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1621
1622 /* enable it... */
1623 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1624
28c97730 1625 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
74dff282
JB		 1626}
1627
43a9539f 1628static void g4x_disable_fbc(struct drm_device *dev)
74dff282
JB		 1629{
1630 struct drm_i915_private *dev_priv = dev->dev_private;
1631 u32 dpfc_ctl;
1632
1633 /* Disable compression */
1634 dpfc_ctl = I915_READ(DPFC_CONTROL);
bed4a673
CW		 1635 if (dpfc_ctl & DPFC_CTL_EN) {
1636 dpfc_ctl &= ~DPFC_CTL_EN;
1637 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
74dff282 1638
bed4a673
CW		 1639 DRM_DEBUG_KMS("disabled FBC\n");
1640 }
74dff282
JB		 1641}
1642
ee5382ae 1643static bool g4x_fbc_enabled(struct drm_device *dev)
74dff282 1644{
74dff282
JB		 1645 struct drm_i915_private *dev_priv = dev->dev_private;
1646
1647 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1648}
1649
4efe0708
JB		 1650static void sandybridge_blit_fbc_update(struct drm_device *dev)
1651{
1652 struct drm_i915_private *dev_priv = dev->dev_private;
1653 u32 blt_ecoskpd;
1654
1655 /* Make sure blitter notifies FBC of writes */
fcca7926 1656 gen6_gt_force_wake_get(dev_priv);
4efe0708
JB		 1657 blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
1658 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
1659 GEN6_BLITTER_LOCK_SHIFT;
1660 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1661 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
1662 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1663 blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
1664 GEN6_BLITTER_LOCK_SHIFT);
1665 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1666 POSTING_READ(GEN6_BLITTER_ECOSKPD);
fcca7926 1667 gen6_gt_force_wake_put(dev_priv);
4efe0708
JB		 1668}
1669
b52eb4dc
ZY		 1670static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1671{
1672 struct drm_device *dev = crtc->dev;
1673 struct drm_i915_private *dev_priv = dev->dev_private;
1674 struct drm_framebuffer *fb = crtc->fb;
1675 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 1676 struct drm_i915_gem_object *obj = intel_fb->obj;
b52eb4dc 1677 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5eddb70b 1678 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
b52eb4dc
ZY		 1679 unsigned long stall_watermark = 200;
1680 u32 dpfc_ctl;
1681
bed4a673 1682 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
b52eb4dc
ZY		 1683 dpfc_ctl &= DPFC_RESERVED;
1684 dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
9ce9d069
CW		 1685 /* Set persistent mode for front-buffer rendering, ala X. */
1686 dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE;
016b9b61 1687 dpfc_ctl |= (DPFC_CTL_FENCE_EN | obj->fence_reg);
de568510 1688 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
b52eb4dc 1689
b52eb4dc
ZY		 1690 I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1691 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1692 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1693 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
05394f39 1694 I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
b52eb4dc 1695 /* enable it... */
bed4a673 1696 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
b52eb4dc 1697
9c04f015
YL		 1698 if (IS_GEN6(dev)) {
1699 I915_WRITE(SNB_DPFC_CTL_SA,
016b9b61 1700 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
9c04f015 1701 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
4efe0708 1702 sandybridge_blit_fbc_update(dev);
9c04f015
YL		 1703 }
1704
b52eb4dc
ZY		 1705 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1706}
1707
43a9539f 1708static void ironlake_disable_fbc(struct drm_device *dev)
b52eb4dc
ZY		 1709{
1710 struct drm_i915_private *dev_priv = dev->dev_private;
1711 u32 dpfc_ctl;
1712
1713 /* Disable compression */
1714 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
bed4a673
CW		 1715 if (dpfc_ctl & DPFC_CTL_EN) {
1716 dpfc_ctl &= ~DPFC_CTL_EN;
1717 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
b52eb4dc 1718
bed4a673
CW		 1719 DRM_DEBUG_KMS("disabled FBC\n");
1720 }
b52eb4dc
ZY		 1721}
1722
1723static bool ironlake_fbc_enabled(struct drm_device *dev)
1724{
1725 struct drm_i915_private *dev_priv = dev->dev_private;
1726
1727 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
1728}
1729
ee5382ae
AJ		 1730bool intel_fbc_enabled(struct drm_device *dev)
1731{
1732 struct drm_i915_private *dev_priv = dev->dev_private;
1733
1734 if (!dev_priv->display.fbc_enabled)
1735 return false;
1736
1737 return dev_priv->display.fbc_enabled(dev);
1738}
1739
1630fe75
CW		 1740static void intel_fbc_work_fn(struct work_struct *__work)
1741{
1742 struct intel_fbc_work *work =
1743 container_of(to_delayed_work(__work),
1744 struct intel_fbc_work, work);
1745 struct drm_device *dev = work->crtc->dev;
1746 struct drm_i915_private *dev_priv = dev->dev_private;
1747
1748 mutex_lock(&dev->struct_mutex);
1749 if (work == dev_priv->fbc_work) {
1750 /* Double check that we haven't switched fb without cancelling
1751 * the prior work.
1752 */
016b9b61 1753 if (work->crtc->fb == work->fb) {
1630fe75
CW		 1754 dev_priv->display.enable_fbc(work->crtc,
1755 work->interval);
1756
016b9b61
CW		 1757 dev_priv->cfb_plane = to_intel_crtc(work->crtc)->plane;
1758 dev_priv->cfb_fb = work->crtc->fb->base.id;
1759 dev_priv->cfb_y = work->crtc->y;
1760 }
1761
1630fe75
CW		 1762 dev_priv->fbc_work = NULL;
1763 }
1764 mutex_unlock(&dev->struct_mutex);
1765
1766 kfree(work);
1767}
1768
1769static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
1770{
1771 if (dev_priv->fbc_work == NULL)
1772 return;
1773
1774 DRM_DEBUG_KMS("cancelling pending FBC enable\n");
1775
1776 /* Synchronisation is provided by struct_mutex and checking of
1777 * dev_priv->fbc_work, so we can perform the cancellation
1778 * entirely asynchronously.
1779 */
1780 if (cancel_delayed_work(&dev_priv->fbc_work->work))
1781 /* tasklet was killed before being run, clean up */
1782 kfree(dev_priv->fbc_work);
1783
1784 /* Mark the work as no longer wanted so that if it does
1785 * wake-up (because the work was already running and waiting
1786 * for our mutex), it will discover that is no longer
1787 * necessary to run.
1788 */
1789 dev_priv->fbc_work = NULL;
1790}
1791
43a9539f 1792static void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
ee5382ae 1793{
1630fe75
CW		 1794 struct intel_fbc_work *work;
1795 struct drm_device *dev = crtc->dev;
1796 struct drm_i915_private *dev_priv = dev->dev_private;
ee5382ae
AJ		 1797
1798 if (!dev_priv->display.enable_fbc)
1799 return;
1800
1630fe75
CW		 1801 intel_cancel_fbc_work(dev_priv);
1802
1803 work = kzalloc(sizeof *work, GFP_KERNEL);
1804 if (work == NULL) {
1805 dev_priv->display.enable_fbc(crtc, interval);
1806 return;
1807 }
1808
1809 work->crtc = crtc;
1810 work->fb = crtc->fb;
1811 work->interval = interval;
1812 INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
1813
1814 dev_priv->fbc_work = work;
1815
1816 DRM_DEBUG_KMS("scheduling delayed FBC enable\n");
1817
1818 /* Delay the actual enabling to let pageflipping cease and the
016b9b61
CW		 1819 * display to settle before starting the compression. Note that
1820 * this delay also serves a second purpose: it allows for a
1821 * vblank to pass after disabling the FBC before we attempt
1822 * to modify the control registers.
1630fe75
CW		 1823 *
1824 * A more complicated solution would involve tracking vblanks
1825 * following the termination of the page-flipping sequence
1826 * and indeed performing the enable as a co-routine and not
1827 * waiting synchronously upon the vblank.
1828 */
1829 schedule_delayed_work(&work->work, msecs_to_jiffies(50));
ee5382ae
AJ		 1830}
1831
1832void intel_disable_fbc(struct drm_device *dev)
1833{
1834 struct drm_i915_private *dev_priv = dev->dev_private;
1835
1630fe75
CW		 1836 intel_cancel_fbc_work(dev_priv);
1837
ee5382ae
AJ		 1838 if (!dev_priv->display.disable_fbc)
1839 return;
1840
1841 dev_priv->display.disable_fbc(dev);
016b9b61 1842 dev_priv->cfb_plane = -1;
ee5382ae
AJ		 1843}
1844
80824003
JB		 1845/**
1846 * intel_update_fbc - enable/disable FBC as needed
bed4a673 1847 * @dev: the drm_device
80824003
JB		 1848 *
1849 * Set up the framebuffer compression hardware at mode set time. We
1850 * enable it if possible:
1851 * - plane A only (on pre-965)
1852 * - no pixel mulitply/line duplication
1853 * - no alpha buffer discard
1854 * - no dual wide
1855 * - framebuffer <= 2048 in width, 1536 in height
1856 *
1857 * We can't assume that any compression will take place (worst case),
1858 * so the compressed buffer has to be the same size as the uncompressed
1859 * one. It also must reside (along with the line length buffer) in
1860 * stolen memory.
1861 *
1862 * We need to enable/disable FBC on a global basis.
1863 */
bed4a673 1864static void intel_update_fbc(struct drm_device *dev)
80824003 1865{
80824003 1866 struct drm_i915_private *dev_priv = dev->dev_private;
bed4a673
CW		 1867 struct drm_crtc *crtc = NULL, *tmp_crtc;
1868 struct intel_crtc *intel_crtc;
1869 struct drm_framebuffer *fb;
80824003 1870 struct intel_framebuffer *intel_fb;
05394f39 1871 struct drm_i915_gem_object *obj;
cd0de039 1872 int enable_fbc;
9c928d16
JB		 1873
1874 DRM_DEBUG_KMS("\n");
80824003
JB		 1875
1876 if (!i915_powersave)
1877 return;
1878
ee5382ae 1879 if (!I915_HAS_FBC(dev))
e70236a8
JB		 1880 return;
1881
80824003
JB		 1882 /*
1883 * If FBC is already on, we just have to verify that we can
1884 * keep it that way...
1885 * Need to disable if:
9c928d16 1886 * - more than one pipe is active
80824003
JB		 1887 * - changing FBC params (stride, fence, mode)
1888 * - new fb is too large to fit in compressed buffer
1889 * - going to an unsupported config (interlace, pixel multiply, etc.)
1890 */
9c928d16 1891 list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
d210246a 1892 if (tmp_crtc->enabled && tmp_crtc->fb) {
bed4a673
CW		 1893 if (crtc) {
1894 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1895 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
1896 goto out_disable;
1897 }
1898 crtc = tmp_crtc;
1899 }
9c928d16 1900 }
bed4a673
CW		 1901
1902 if (!crtc || crtc->fb == NULL) {
1903 DRM_DEBUG_KMS("no output, disabling\n");
1904 dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
9c928d16
JB		 1905 goto out_disable;
1906 }
bed4a673
CW		 1907
1908 intel_crtc = to_intel_crtc(crtc);
1909 fb = crtc->fb;
1910 intel_fb = to_intel_framebuffer(fb);
05394f39 1911 obj = intel_fb->obj;
bed4a673 1912
cd0de039
KP		 1913 enable_fbc = i915_enable_fbc;
1914 if (enable_fbc < 0) {
1915 DRM_DEBUG_KMS("fbc set to per-chip default\n");
1916 enable_fbc = 1;
d56d8b28 1917 if (INTEL_INFO(dev)->gen <= 6)
cd0de039
KP		 1918 enable_fbc = 0;
1919 }
1920 if (!enable_fbc) {
1921 DRM_DEBUG_KMS("fbc disabled per module param\n");
c1a9f047
JB		 1922 dev_priv->no_fbc_reason = FBC_MODULE_PARAM;
1923 goto out_disable;
1924 }
05394f39 1925 if (intel_fb->obj->base.size > dev_priv->cfb_size) {
28c97730 1926 DRM_DEBUG_KMS("framebuffer too large, disabling "
5eddb70b 1927 "compression\n");
b5e50c3f 1928 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
80824003
JB		 1929 goto out_disable;
1930 }
bed4a673
CW		 1931 if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
1932 (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
28c97730 1933 DRM_DEBUG_KMS("mode incompatible with compression, "
5eddb70b 1934 "disabling\n");
b5e50c3f 1935 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
80824003
JB		 1936 goto out_disable;
1937 }
bed4a673
CW		 1938 if ((crtc->mode.hdisplay > 2048) ||
1939 (crtc->mode.vdisplay > 1536)) {
28c97730 1940 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
b5e50c3f 1941 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
80824003
JB		 1942 goto out_disable;
1943 }
bed4a673 1944 if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
28c97730 1945 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
b5e50c3f 1946 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
80824003
JB		 1947 goto out_disable;
1948 }
de568510
CW		 1949
1950 /* The use of a CPU fence is mandatory in order to detect writes
1951 * by the CPU to the scanout and trigger updates to the FBC.
1952 */
1953 if (obj->tiling_mode != I915_TILING_X ||
1954 obj->fence_reg == I915_FENCE_REG_NONE) {
1955 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
b5e50c3f 1956 dev_priv->no_fbc_reason = FBC_NOT_TILED;
80824003
JB		 1957 goto out_disable;
1958 }
1959
c924b934
JW		 1960 /* If the kernel debugger is active, always disable compression */
1961 if (in_dbg_master())
1962 goto out_disable;
1963
016b9b61
CW		 1964 /* If the scanout has not changed, don't modify the FBC settings.
1965 * Note that we make the fundamental assumption that the fb->obj
1966 * cannot be unpinned (and have its GTT offset and fence revoked)
1967 * without first being decoupled from the scanout and FBC disabled.
1968 */
1969 if (dev_priv->cfb_plane == intel_crtc->plane &&
1970 dev_priv->cfb_fb == fb->base.id &&
1971 dev_priv->cfb_y == crtc->y)
1972 return;
1973
1974 if (intel_fbc_enabled(dev)) {
1975 /* We update FBC along two paths, after changing fb/crtc
1976 * configuration (modeswitching) and after page-flipping
1977 * finishes. For the latter, we know that not only did
1978 * we disable the FBC at the start of the page-flip
1979 * sequence, but also more than one vblank has passed.
1980 *
1981 * For the former case of modeswitching, it is possible
1982 * to switch between two FBC valid configurations
1983 * instantaneously so we do need to disable the FBC
1984 * before we can modify its control registers. We also
1985 * have to wait for the next vblank for that to take
1986 * effect. However, since we delay enabling FBC we can
1987 * assume that a vblank has passed since disabling and
1988 * that we can safely alter the registers in the deferred
1989 * callback.
1990 *
1991 * In the scenario that we go from a valid to invalid
1992 * and then back to valid FBC configuration we have
1993 * no strict enforcement that a vblank occurred since
1994 * disabling the FBC. However, along all current pipe
1995 * disabling paths we do need to wait for a vblank at
1996 * some point. And we wait before enabling FBC anyway.
1997 */
1998 DRM_DEBUG_KMS("disabling active FBC for update\n");
1999 intel_disable_fbc(dev);
2000 }
2001
bed4a673 2002 intel_enable_fbc(crtc, 500);
80824003
JB		 2003 return;
2004
2005out_disable:
80824003 2006 /* Multiple disables should be harmless */
a939406f
CW		 2007 if (intel_fbc_enabled(dev)) {
2008 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
ee5382ae 2009 intel_disable_fbc(dev);
a939406f 2010 }
80824003
JB		 2011}
2012
127bd2ac 2013int
48b956c5 2014intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 2015 struct drm_i915_gem_object *obj,
919926ae 2016 struct intel_ring_buffer *pipelined)
6b95a207 2017{
ce453d81 2018 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 2019 u32 alignment;
2020 int ret;
2021
05394f39 2022 switch (obj->tiling_mode) {
6b95a207 2023 case I915_TILING_NONE:
534843da
CW		 2024 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2025 alignment = 128 * 1024;
a6c45cf0 2026 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 2027 alignment = 4 * 1024;
2028 else
2029 alignment = 64 * 1024;
6b95a207
KH		 2030 break;
2031 case I915_TILING_X:
2032 /* pin() will align the object as required by fence */
2033 alignment = 0;
2034 break;
2035 case I915_TILING_Y:
2036 /* FIXME: Is this true? */
2037 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
2038 return -EINVAL;
2039 default:
2040 BUG();
2041 }
2042
ce453d81 2043 dev_priv->mm.interruptible = false;
2da3b9b9 2044 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 2045 if (ret)
ce453d81 2046 goto err_interruptible;
6b95a207
KH		 2047
2048 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2049 * fence, whereas 965+ only requires a fence if using
2050 * framebuffer compression. For simplicity, we always install
2051 * a fence as the cost is not that onerous.
2052 */
05394f39 2053 if (obj->tiling_mode != I915_TILING_NONE) {
ce453d81 2054 ret = i915_gem_object_get_fence(obj, pipelined);
48b956c5
CW		 2055 if (ret)
2056 goto err_unpin;
1690e1eb
CW		 2057
2058 i915_gem_object_pin_fence(obj);
6b95a207
KH		 2059 }
2060
ce453d81 2061 dev_priv->mm.interruptible = true;
6b95a207 2062 return 0;
48b956c5
CW		 2063
2064err_unpin:
2065 i915_gem_object_unpin(obj);
ce453d81
CW		 2066err_interruptible:
2067 dev_priv->mm.interruptible = true;
48b956c5 2068 return ret;
6b95a207
KH		 2069}
2070
1690e1eb
CW		 2071void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2072{
2073 i915_gem_object_unpin_fence(obj);
2074 i915_gem_object_unpin(obj);
2075}
2076
17638cd6
JB		 2077static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2078 int x, int y)
81255565
JB		 2079{
2080 struct drm_device *dev = crtc->dev;
2081 struct drm_i915_private *dev_priv = dev->dev_private;
2082 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2083 struct intel_framebuffer *intel_fb;
05394f39 2084 struct drm_i915_gem_object *obj;
81255565
JB		 2085 int plane = intel_crtc->plane;
2086 unsigned long Start, Offset;
81255565 2087 u32 dspcntr;
5eddb70b 2088 u32 reg;
81255565
JB		 2089
2090 switch (plane) {
2091 case 0:
2092 case 1:
2093 break;
2094 default:
2095 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2096 return -EINVAL;
2097 }
2098
2099 intel_fb = to_intel_framebuffer(fb);
2100 obj = intel_fb->obj;
81255565 2101
5eddb70b
CW		 2102 reg = DSPCNTR(plane);
2103 dspcntr = I915_READ(reg);
81255565
JB		 2104 /* Mask out pixel format bits in case we change it */
2105 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2106 switch (fb->bits_per_pixel) {
2107 case 8:
2108 dspcntr |= DISPPLANE_8BPP;
2109 break;
2110 case 16:
2111 if (fb->depth == 15)
2112 dspcntr |= DISPPLANE_15_16BPP;
2113 else
2114 dspcntr |= DISPPLANE_16BPP;
2115 break;
2116 case 24:
2117 case 32:
2118 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2119 break;
2120 default:
17638cd6 2121 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
81255565
JB		 2122 return -EINVAL;
2123 }
a6c45cf0 2124 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 2125 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 2126 dspcntr |= DISPPLANE_TILED;
2127 else
2128 dspcntr &= ~DISPPLANE_TILED;
2129 }
2130
5eddb70b 2131 I915_WRITE(reg, dspcntr);
81255565 2132
05394f39 2133 Start = obj->gtt_offset;
01f2c773 2134 Offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
81255565 2135
4e6cfefc 2136 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
01f2c773
VS		 2137 Start, Offset, x, y, fb->pitches[0]);
2138 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2139 if (INTEL_INFO(dev)->gen >= 4) {
5eddb70b
CW		 2140 I915_WRITE(DSPSURF(plane), Start);
2141 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2142 I915_WRITE(DSPADDR(plane), Offset);
2143 } else
2144 I915_WRITE(DSPADDR(plane), Start + Offset);
2145 POSTING_READ(reg);
81255565 2146
17638cd6
JB		 2147 return 0;
2148}
2149
2150static int ironlake_update_plane(struct drm_crtc *crtc,
2151 struct drm_framebuffer *fb, int x, int y)
2152{
2153 struct drm_device *dev = crtc->dev;
2154 struct drm_i915_private *dev_priv = dev->dev_private;
2155 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2156 struct intel_framebuffer *intel_fb;
2157 struct drm_i915_gem_object *obj;
2158 int plane = intel_crtc->plane;
2159 unsigned long Start, Offset;
2160 u32 dspcntr;
2161 u32 reg;
2162
2163 switch (plane) {
2164 case 0:
2165 case 1:
27f8227b 2166 case 2:
17638cd6
JB		 2167 break;
2168 default:
2169 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2170 return -EINVAL;
2171 }
2172
2173 intel_fb = to_intel_framebuffer(fb);
2174 obj = intel_fb->obj;
2175
2176 reg = DSPCNTR(plane);
2177 dspcntr = I915_READ(reg);
2178 /* Mask out pixel format bits in case we change it */
2179 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2180 switch (fb->bits_per_pixel) {
2181 case 8:
2182 dspcntr |= DISPPLANE_8BPP;
2183 break;
2184 case 16:
2185 if (fb->depth != 16)
2186 return -EINVAL;
2187
2188 dspcntr |= DISPPLANE_16BPP;
2189 break;
2190 case 24:
2191 case 32:
2192 if (fb->depth == 24)
2193 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2194 else if (fb->depth == 30)
2195 dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
2196 else
2197 return -EINVAL;
2198 break;
2199 default:
2200 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2201 return -EINVAL;
2202 }
2203
2204 if (obj->tiling_mode != I915_TILING_NONE)
2205 dspcntr |= DISPPLANE_TILED;
2206 else
2207 dspcntr &= ~DISPPLANE_TILED;
2208
2209 /* must disable */
2210 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2211
2212 I915_WRITE(reg, dspcntr);
2213
2214 Start = obj->gtt_offset;
01f2c773 2215 Offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
17638cd6
JB		 2216
2217 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
01f2c773
VS		 2218 Start, Offset, x, y, fb->pitches[0]);
2219 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
17638cd6
JB		 2220 I915_WRITE(DSPSURF(plane), Start);
2221 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2222 I915_WRITE(DSPADDR(plane), Offset);
2223 POSTING_READ(reg);
2224
2225 return 0;
2226}
2227
2228/* Assume fb object is pinned & idle & fenced and just update base pointers */
2229static int
2230intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2231 int x, int y, enum mode_set_atomic state)
2232{
2233 struct drm_device *dev = crtc->dev;
2234 struct drm_i915_private *dev_priv = dev->dev_private;
2235 int ret;
2236
2237 ret = dev_priv->display.update_plane(crtc, fb, x, y);
2238 if (ret)
2239 return ret;
2240
bed4a673 2241 intel_update_fbc(dev);
3dec0095 2242 intel_increase_pllclock(crtc);
81255565
JB		 2243
2244 return 0;
2245}
2246
5c3b82e2 2247static int
3c4fdcfb
KH		 2248intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2249 struct drm_framebuffer *old_fb)
79e53945
JB		 2250{
2251 struct drm_device *dev = crtc->dev;
79e53945
JB		 2252 struct drm_i915_master_private *master_priv;
2253 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5c3b82e2 2254 int ret;
79e53945
JB		 2255
2256 /* no fb bound */
2257 if (!crtc->fb) {
a5071c2f 2258 DRM_ERROR("No FB bound\n");
5c3b82e2
CW		 2259 return 0;
2260 }
2261
265db958 2262 switch (intel_crtc->plane) {
5c3b82e2
CW		 2263 case 0:
2264 case 1:
2265 break;
27f8227b
JB		 2266 case 2:
2267 if (IS_IVYBRIDGE(dev))
2268 break;
2269 /* fall through otherwise */
5c3b82e2 2270 default:
a5071c2f 2271 DRM_ERROR("no plane for crtc\n");
5c3b82e2 2272 return -EINVAL;
79e53945
JB		 2273 }
2274
5c3b82e2 2275 mutex_lock(&dev->struct_mutex);
265db958
CW		 2276 ret = intel_pin_and_fence_fb_obj(dev,
2277 to_intel_framebuffer(crtc->fb)->obj,
919926ae 2278 NULL);
5c3b82e2
CW		 2279 if (ret != 0) {
2280 mutex_unlock(&dev->struct_mutex);
a5071c2f 2281 DRM_ERROR("pin & fence failed\n");
5c3b82e2
CW		 2282 return ret;
2283 }
79e53945 2284
265db958 2285 if (old_fb) {
e6c3a2a6 2286 struct drm_i915_private *dev_priv = dev->dev_private;
05394f39 2287 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
265db958 2288
e6c3a2a6 2289 wait_event(dev_priv->pending_flip_queue,
01eec727 2290 atomic_read(&dev_priv->mm.wedged) ||
05394f39 2291 atomic_read(&obj->pending_flip) == 0);
85345517
CW		 2292
2293 /* Big Hammer, we also need to ensure that any pending
2294 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2295 * current scanout is retired before unpinning the old
2296 * framebuffer.
01eec727
CW		 2297 *
2298 * This should only fail upon a hung GPU, in which case we
2299 * can safely continue.
85345517 2300 */
a8198eea 2301 ret = i915_gem_object_finish_gpu(obj);
01eec727 2302 (void) ret;
265db958
CW		 2303 }
2304
21c74a8e
JW		 2305 ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y,
2306 LEAVE_ATOMIC_MODE_SET);
4e6cfefc 2307 if (ret) {
1690e1eb 2308 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
5c3b82e2 2309 mutex_unlock(&dev->struct_mutex);
a5071c2f 2310 DRM_ERROR("failed to update base address\n");
4e6cfefc 2311 return ret;
79e53945 2312 }
3c4fdcfb 2313
b7f1de28
CW		 2314 if (old_fb) {
2315 intel_wait_for_vblank(dev, intel_crtc->pipe);
1690e1eb 2316 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
b7f1de28 2317 }
652c393a 2318
5c3b82e2 2319 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 2320
2321 if (!dev->primary->master)
5c3b82e2 2322 return 0;
79e53945
JB		 2323
2324 master_priv = dev->primary->master->driver_priv;
2325 if (!master_priv->sarea_priv)
5c3b82e2 2326 return 0;
79e53945 2327
265db958 2328 if (intel_crtc->pipe) {
79e53945
JB		 2329 master_priv->sarea_priv->pipeB_x = x;
2330 master_priv->sarea_priv->pipeB_y = y;
5c3b82e2
CW		 2331 } else {
2332 master_priv->sarea_priv->pipeA_x = x;
2333 master_priv->sarea_priv->pipeA_y = y;
79e53945 2334 }
5c3b82e2
CW		 2335
2336 return 0;
79e53945
JB		 2337}
2338
5eddb70b 2339static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
32f9d658
ZW		 2340{
2341 struct drm_device *dev = crtc->dev;
2342 struct drm_i915_private *dev_priv = dev->dev_private;
2343 u32 dpa_ctl;
2344
28c97730 2345 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
32f9d658
ZW		 2346 dpa_ctl = I915_READ(DP_A);
2347 dpa_ctl &= ~DP_PLL_FREQ_MASK;
2348
2349 if (clock < 200000) {
2350 u32 temp;
2351 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2352 /* workaround for 160Mhz:
2353 1) program 0x4600c bits 15:0 = 0x8124
2354 2) program 0x46010 bit 0 = 1
2355 3) program 0x46034 bit 24 = 1
2356 4) program 0x64000 bit 14 = 1
2357 */
2358 temp = I915_READ(0x4600c);
2359 temp &= 0xffff0000;
2360 I915_WRITE(0x4600c, temp | 0x8124);
2361
2362 temp = I915_READ(0x46010);
2363 I915_WRITE(0x46010, temp | 1);
2364
2365 temp = I915_READ(0x46034);
2366 I915_WRITE(0x46034, temp | (1 << 24));
2367 } else {
2368 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2369 }
2370 I915_WRITE(DP_A, dpa_ctl);
2371
5eddb70b 2372 POSTING_READ(DP_A);
32f9d658
ZW		 2373 udelay(500);
2374}
2375
5e84e1a4
ZW		 2376static void intel_fdi_normal_train(struct drm_crtc *crtc)
2377{
2378 struct drm_device *dev = crtc->dev;
2379 struct drm_i915_private *dev_priv = dev->dev_private;
2380 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2381 int pipe = intel_crtc->pipe;
2382 u32 reg, temp;
2383
2384 /* enable normal train */
2385 reg = FDI_TX_CTL(pipe);
2386 temp = I915_READ(reg);
61e499bf 2387 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2388 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2389 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2390 } else {
2391 temp &= ~FDI_LINK_TRAIN_NONE;
2392 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2393 }
5e84e1a4
ZW		 2394 I915_WRITE(reg, temp);
2395
2396 reg = FDI_RX_CTL(pipe);
2397 temp = I915_READ(reg);
2398 if (HAS_PCH_CPT(dev)) {
2399 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2400 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2401 } else {
2402 temp &= ~FDI_LINK_TRAIN_NONE;
2403 temp |= FDI_LINK_TRAIN_NONE;
2404 }
2405 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2406
2407 /* wait one idle pattern time */
2408 POSTING_READ(reg);
2409 udelay(1000);
357555c0
JB		 2410
2411 /* IVB wants error correction enabled */
2412 if (IS_IVYBRIDGE(dev))
2413 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2414 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2415}
2416
291427f5
JB		 2417static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2418{
2419 struct drm_i915_private *dev_priv = dev->dev_private;
2420 u32 flags = I915_READ(SOUTH_CHICKEN1);
2421
2422 flags |= FDI_PHASE_SYNC_OVR(pipe);
2423 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2424 flags |= FDI_PHASE_SYNC_EN(pipe);
2425 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2426 POSTING_READ(SOUTH_CHICKEN1);
2427}
2428
8db9d77b
ZW		 2429/* The FDI link training functions for ILK/Ibexpeak. */
2430static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2431{
2432 struct drm_device *dev = crtc->dev;
2433 struct drm_i915_private *dev_priv = dev->dev_private;
2434 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2435 int pipe = intel_crtc->pipe;
0fc932b8 2436 int plane = intel_crtc->plane;
5eddb70b 2437 u32 reg, temp, tries;
8db9d77b 2438
0fc932b8
JB		 2439 /* FDI needs bits from pipe & plane first */
2440 assert_pipe_enabled(dev_priv, pipe);
2441 assert_plane_enabled(dev_priv, plane);
2442
e1a44743
AJ		 2443 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2444 for train result */
5eddb70b
CW		 2445 reg = FDI_RX_IMR(pipe);
2446 temp = I915_READ(reg);
e1a44743
AJ		 2447 temp &= ~FDI_RX_SYMBOL_LOCK;
2448 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2449 I915_WRITE(reg, temp);
2450 I915_READ(reg);
e1a44743
AJ		 2451 udelay(150);
2452
8db9d77b 2453 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2454 reg = FDI_TX_CTL(pipe);
2455 temp = I915_READ(reg);
77ffb597
AJ		 2456 temp &= ~(7 << 19);
2457 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2458 temp &= ~FDI_LINK_TRAIN_NONE;
2459 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2460 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2461
5eddb70b
CW		 2462 reg = FDI_RX_CTL(pipe);
2463 temp = I915_READ(reg);
8db9d77b
ZW		 2464 temp &= ~FDI_LINK_TRAIN_NONE;
2465 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2466 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2467
2468 POSTING_READ(reg);
8db9d77b
ZW		 2469 udelay(150);
2470
5b2adf89 2471 /* Ironlake workaround, enable clock pointer after FDI enable*/
6f06ce18
JB		 2472 if (HAS_PCH_IBX(dev)) {
2473 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2474 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2475 FDI_RX_PHASE_SYNC_POINTER_EN);
2476 }
5b2adf89 2477
5eddb70b 2478 reg = FDI_RX_IIR(pipe);
e1a44743 2479 for (tries = 0; tries < 5; tries++) {
5eddb70b 2480 temp = I915_READ(reg);
8db9d77b
ZW		 2481 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2482
2483 if ((temp & FDI_RX_BIT_LOCK)) {
2484 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2485 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2486 break;
2487 }
8db9d77b 2488 }
e1a44743 2489 if (tries == 5)
5eddb70b 2490 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2491
2492 /* Train 2 */
5eddb70b
CW		 2493 reg = FDI_TX_CTL(pipe);
2494 temp = I915_READ(reg);
8db9d77b
ZW		 2495 temp &= ~FDI_LINK_TRAIN_NONE;
2496 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2497 I915_WRITE(reg, temp);
8db9d77b 2498
5eddb70b
CW		 2499 reg = FDI_RX_CTL(pipe);
2500 temp = I915_READ(reg);
8db9d77b
ZW		 2501 temp &= ~FDI_LINK_TRAIN_NONE;
2502 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2503 I915_WRITE(reg, temp);
8db9d77b 2504
5eddb70b
CW		 2505 POSTING_READ(reg);
2506 udelay(150);
8db9d77b 2507
5eddb70b 2508 reg = FDI_RX_IIR(pipe);
e1a44743 2509 for (tries = 0; tries < 5; tries++) {
5eddb70b 2510 temp = I915_READ(reg);
8db9d77b
ZW		 2511 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2512
2513 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2514 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2515 DRM_DEBUG_KMS("FDI train 2 done.\n");
2516 break;
2517 }
8db9d77b 2518 }
e1a44743 2519 if (tries == 5)
5eddb70b 2520 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2521
2522 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2523
8db9d77b
ZW		 2524}
2525
0206e353 2526static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 2527 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2528 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2529 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2530 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2531};
2532
2533/* The FDI link training functions for SNB/Cougarpoint. */
2534static void gen6_fdi_link_train(struct drm_crtc *crtc)
2535{
2536 struct drm_device *dev = crtc->dev;
2537 struct drm_i915_private *dev_priv = dev->dev_private;
2538 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2539 int pipe = intel_crtc->pipe;
5eddb70b 2540 u32 reg, temp, i;
8db9d77b 2541
e1a44743
AJ		 2542 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2543 for train result */
5eddb70b
CW		 2544 reg = FDI_RX_IMR(pipe);
2545 temp = I915_READ(reg);
e1a44743
AJ		 2546 temp &= ~FDI_RX_SYMBOL_LOCK;
2547 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2548 I915_WRITE(reg, temp);
2549
2550 POSTING_READ(reg);
e1a44743
AJ		 2551 udelay(150);
2552
8db9d77b 2553 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2554 reg = FDI_TX_CTL(pipe);
2555 temp = I915_READ(reg);
77ffb597
AJ		 2556 temp &= ~(7 << 19);
2557 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2558 temp &= ~FDI_LINK_TRAIN_NONE;
2559 temp |= FDI_LINK_TRAIN_PATTERN_1;
2560 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2561 /* SNB-B */
2562 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2563 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2564
5eddb70b
CW		 2565 reg = FDI_RX_CTL(pipe);
2566 temp = I915_READ(reg);
8db9d77b
ZW		 2567 if (HAS_PCH_CPT(dev)) {
2568 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2569 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2570 } else {
2571 temp &= ~FDI_LINK_TRAIN_NONE;
2572 temp |= FDI_LINK_TRAIN_PATTERN_1;
2573 }
5eddb70b
CW		 2574 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2575
2576 POSTING_READ(reg);
8db9d77b
ZW		 2577 udelay(150);
2578
291427f5
JB		 2579 if (HAS_PCH_CPT(dev))
2580 cpt_phase_pointer_enable(dev, pipe);
2581
0206e353 2582 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2583 reg = FDI_TX_CTL(pipe);
2584 temp = I915_READ(reg);
8db9d77b
ZW		 2585 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2586 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2587 I915_WRITE(reg, temp);
2588
2589 POSTING_READ(reg);
8db9d77b
ZW		 2590 udelay(500);
2591
5eddb70b
CW		 2592 reg = FDI_RX_IIR(pipe);
2593 temp = I915_READ(reg);
8db9d77b
ZW		 2594 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2595
2596 if (temp & FDI_RX_BIT_LOCK) {
5eddb70b 2597 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2598 DRM_DEBUG_KMS("FDI train 1 done.\n");
2599 break;
2600 }
2601 }
2602 if (i == 4)
5eddb70b 2603 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2604
2605 /* Train 2 */
5eddb70b
CW		 2606 reg = FDI_TX_CTL(pipe);
2607 temp = I915_READ(reg);
8db9d77b
ZW		 2608 temp &= ~FDI_LINK_TRAIN_NONE;
2609 temp |= FDI_LINK_TRAIN_PATTERN_2;
2610 if (IS_GEN6(dev)) {
2611 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2612 /* SNB-B */
2613 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2614 }
5eddb70b 2615 I915_WRITE(reg, temp);
8db9d77b 2616
5eddb70b
CW		 2617 reg = FDI_RX_CTL(pipe);
2618 temp = I915_READ(reg);
8db9d77b
ZW		 2619 if (HAS_PCH_CPT(dev)) {
2620 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2621 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2622 } else {
2623 temp &= ~FDI_LINK_TRAIN_NONE;
2624 temp |= FDI_LINK_TRAIN_PATTERN_2;
2625 }
5eddb70b
CW		 2626 I915_WRITE(reg, temp);
2627
2628 POSTING_READ(reg);
8db9d77b
ZW		 2629 udelay(150);
2630
0206e353 2631 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2632 reg = FDI_TX_CTL(pipe);
2633 temp = I915_READ(reg);
8db9d77b
ZW		 2634 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2635 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2636 I915_WRITE(reg, temp);
2637
2638 POSTING_READ(reg);
8db9d77b
ZW		 2639 udelay(500);
2640
5eddb70b
CW		 2641 reg = FDI_RX_IIR(pipe);
2642 temp = I915_READ(reg);
8db9d77b
ZW		 2643 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2644
2645 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2646 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2647 DRM_DEBUG_KMS("FDI train 2 done.\n");
2648 break;
2649 }
2650 }
2651 if (i == 4)
5eddb70b 2652 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2653
2654 DRM_DEBUG_KMS("FDI train done.\n");
2655}
2656
357555c0
JB		 2657/* Manual link training for Ivy Bridge A0 parts */
2658static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2659{
2660 struct drm_device *dev = crtc->dev;
2661 struct drm_i915_private *dev_priv = dev->dev_private;
2662 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2663 int pipe = intel_crtc->pipe;
2664 u32 reg, temp, i;
2665
2666 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2667 for train result */
2668 reg = FDI_RX_IMR(pipe);
2669 temp = I915_READ(reg);
2670 temp &= ~FDI_RX_SYMBOL_LOCK;
2671 temp &= ~FDI_RX_BIT_LOCK;
2672 I915_WRITE(reg, temp);
2673
2674 POSTING_READ(reg);
2675 udelay(150);
2676
2677 /* enable CPU FDI TX and PCH FDI RX */
2678 reg = FDI_TX_CTL(pipe);
2679 temp = I915_READ(reg);
2680 temp &= ~(7 << 19);
2681 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2682 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2683 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2684 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2685 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
c4f9c4c2 2686 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2687 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2688
2689 reg = FDI_RX_CTL(pipe);
2690 temp = I915_READ(reg);
2691 temp &= ~FDI_LINK_TRAIN_AUTO;
2692 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2693 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
c4f9c4c2 2694 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2695 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2696
2697 POSTING_READ(reg);
2698 udelay(150);
2699
291427f5
JB		 2700 if (HAS_PCH_CPT(dev))
2701 cpt_phase_pointer_enable(dev, pipe);
2702
0206e353 2703 for (i = 0; i < 4; i++) {
357555c0
JB		 2704 reg = FDI_TX_CTL(pipe);
2705 temp = I915_READ(reg);
2706 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2707 temp |= snb_b_fdi_train_param[i];
2708 I915_WRITE(reg, temp);
2709
2710 POSTING_READ(reg);
2711 udelay(500);
2712
2713 reg = FDI_RX_IIR(pipe);
2714 temp = I915_READ(reg);
2715 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2716
2717 if (temp & FDI_RX_BIT_LOCK ||
2718 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2719 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2720 DRM_DEBUG_KMS("FDI train 1 done.\n");
2721 break;
2722 }
2723 }
2724 if (i == 4)
2725 DRM_ERROR("FDI train 1 fail!\n");
2726
2727 /* Train 2 */
2728 reg = FDI_TX_CTL(pipe);
2729 temp = I915_READ(reg);
2730 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2731 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2732 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2733 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2734 I915_WRITE(reg, temp);
2735
2736 reg = FDI_RX_CTL(pipe);
2737 temp = I915_READ(reg);
2738 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2739 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2740 I915_WRITE(reg, temp);
2741
2742 POSTING_READ(reg);
2743 udelay(150);
2744
0206e353 2745 for (i = 0; i < 4; i++) {
357555c0
JB		 2746 reg = FDI_TX_CTL(pipe);
2747 temp = I915_READ(reg);
2748 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2749 temp |= snb_b_fdi_train_param[i];
2750 I915_WRITE(reg, temp);
2751
2752 POSTING_READ(reg);
2753 udelay(500);
2754
2755 reg = FDI_RX_IIR(pipe);
2756 temp = I915_READ(reg);
2757 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2758
2759 if (temp & FDI_RX_SYMBOL_LOCK) {
2760 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2761 DRM_DEBUG_KMS("FDI train 2 done.\n");
2762 break;
2763 }
2764 }
2765 if (i == 4)
2766 DRM_ERROR("FDI train 2 fail!\n");
2767
2768 DRM_DEBUG_KMS("FDI train done.\n");
2769}
2770
2771static void ironlake_fdi_pll_enable(struct drm_crtc *crtc)
2c07245f
ZW		 2772{
2773 struct drm_device *dev = crtc->dev;
2774 struct drm_i915_private *dev_priv = dev->dev_private;
2775 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2776 int pipe = intel_crtc->pipe;
5eddb70b 2777 u32 reg, temp;
79e53945 2778
c64e311e 2779 /* Write the TU size bits so error detection works */
5eddb70b
CW		 2780 I915_WRITE(FDI_RX_TUSIZE1(pipe),
2781 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
c64e311e 2782
c98e9dcf 2783 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2784 reg = FDI_RX_CTL(pipe);
2785 temp = I915_READ(reg);
2786 temp &= ~((0x7 << 19) | (0x7 << 16));
c98e9dcf 2787 temp |= (intel_crtc->fdi_lanes - 1) << 19;
5eddb70b
CW		 2788 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2789 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2790
2791 POSTING_READ(reg);
c98e9dcf
JB		 2792 udelay(200);
2793
2794 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2795 temp = I915_READ(reg);
2796 I915_WRITE(reg, temp | FDI_PCDCLK);
2797
2798 POSTING_READ(reg);
c98e9dcf
JB		 2799 udelay(200);
2800
2801 /* Enable CPU FDI TX PLL, always on for Ironlake */
5eddb70b
CW		 2802 reg = FDI_TX_CTL(pipe);
2803 temp = I915_READ(reg);
c98e9dcf 2804 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
5eddb70b
CW		 2805 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2806
2807 POSTING_READ(reg);
c98e9dcf 2808 udelay(100);
6be4a607 2809 }
0e23b99d
JB		 2810}
2811
291427f5
JB		 2812static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2813{
2814 struct drm_i915_private *dev_priv = dev->dev_private;
2815 u32 flags = I915_READ(SOUTH_CHICKEN1);
2816
2817 flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2818 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2819 flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2820 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2821 POSTING_READ(SOUTH_CHICKEN1);
2822}
0fc932b8
JB		 2823static void ironlake_fdi_disable(struct drm_crtc *crtc)
2824{
2825 struct drm_device *dev = crtc->dev;
2826 struct drm_i915_private *dev_priv = dev->dev_private;
2827 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2828 int pipe = intel_crtc->pipe;
2829 u32 reg, temp;
2830
2831 /* disable CPU FDI tx and PCH FDI rx */
2832 reg = FDI_TX_CTL(pipe);
2833 temp = I915_READ(reg);
2834 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2835 POSTING_READ(reg);
2836
2837 reg = FDI_RX_CTL(pipe);
2838 temp = I915_READ(reg);
2839 temp &= ~(0x7 << 16);
2840 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2841 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2842
2843 POSTING_READ(reg);
2844 udelay(100);
2845
2846 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2847 if (HAS_PCH_IBX(dev)) {
2848 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
0fc932b8
JB		 2849 I915_WRITE(FDI_RX_CHICKEN(pipe),
2850 I915_READ(FDI_RX_CHICKEN(pipe) &
6f06ce18 2851 ~FDI_RX_PHASE_SYNC_POINTER_EN));
291427f5
JB		 2852 } else if (HAS_PCH_CPT(dev)) {
2853 cpt_phase_pointer_disable(dev, pipe);
6f06ce18 2854 }
0fc932b8
JB		 2855
2856 /* still set train pattern 1 */
2857 reg = FDI_TX_CTL(pipe);
2858 temp = I915_READ(reg);
2859 temp &= ~FDI_LINK_TRAIN_NONE;
2860 temp |= FDI_LINK_TRAIN_PATTERN_1;
2861 I915_WRITE(reg, temp);
2862
2863 reg = FDI_RX_CTL(pipe);
2864 temp = I915_READ(reg);
2865 if (HAS_PCH_CPT(dev)) {
2866 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2867 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2868 } else {
2869 temp &= ~FDI_LINK_TRAIN_NONE;
2870 temp |= FDI_LINK_TRAIN_PATTERN_1;
2871 }
2872 /* BPC in FDI rx is consistent with that in PIPECONF */
2873 temp &= ~(0x07 << 16);
2874 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2875 I915_WRITE(reg, temp);
2876
2877 POSTING_READ(reg);
2878 udelay(100);
2879}
2880
6b383a7f
CW		 2881/*
2882 * When we disable a pipe, we need to clear any pending scanline wait events
2883 * to avoid hanging the ring, which we assume we are waiting on.
2884 */
2885static void intel_clear_scanline_wait(struct drm_device *dev)
2886{
2887 struct drm_i915_private *dev_priv = dev->dev_private;
8168bd48 2888 struct intel_ring_buffer *ring;
6b383a7f
CW		 2889 u32 tmp;
2890
2891 if (IS_GEN2(dev))
2892 /* Can't break the hang on i8xx */
2893 return;
2894
1ec14ad3 2895 ring = LP_RING(dev_priv);
8168bd48
CW		 2896 tmp = I915_READ_CTL(ring);
2897 if (tmp & RING_WAIT)
2898 I915_WRITE_CTL(ring, tmp);
6b383a7f
CW		 2899}
2900
e6c3a2a6
CW		 2901static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2902{
05394f39 2903 struct drm_i915_gem_object *obj;
e6c3a2a6
CW		 2904 struct drm_i915_private *dev_priv;
2905
2906 if (crtc->fb == NULL)
2907 return;
2908
05394f39 2909 obj = to_intel_framebuffer(crtc->fb)->obj;
e6c3a2a6
CW		 2910 dev_priv = crtc->dev->dev_private;
2911 wait_event(dev_priv->pending_flip_queue,
05394f39 2912 atomic_read(&obj->pending_flip) == 0);
e6c3a2a6
CW		 2913}
2914
040484af
JB		 2915static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2916{
2917 struct drm_device *dev = crtc->dev;
2918 struct drm_mode_config *mode_config = &dev->mode_config;
2919 struct intel_encoder *encoder;
2920
2921 /*
2922 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2923 * must be driven by its own crtc; no sharing is possible.
2924 */
2925 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
2926 if (encoder->base.crtc != crtc)
2927 continue;
2928
2929 switch (encoder->type) {
2930 case INTEL_OUTPUT_EDP:
2931 if (!intel_encoder_is_pch_edp(&encoder->base))
2932 return false;
2933 continue;
2934 }
2935 }
2936
2937 return true;
2938}
2939
f67a559d
JB		 2940/*
2941 * Enable PCH resources required for PCH ports:
2942 * - PCH PLLs
2943 * - FDI training & RX/TX
2944 * - update transcoder timings
2945 * - DP transcoding bits
2946 * - transcoder
2947 */
2948static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 2949{
2950 struct drm_device *dev = crtc->dev;
2951 struct drm_i915_private *dev_priv = dev->dev_private;
2952 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2953 int pipe = intel_crtc->pipe;
4b645f14 2954 u32 reg, temp, transc_sel;
2c07245f 2955
c98e9dcf 2956 /* For PCH output, training FDI link */
674cf967 2957 dev_priv->display.fdi_link_train(crtc);
2c07245f 2958
92f2584a 2959 intel_enable_pch_pll(dev_priv, pipe);
8db9d77b 2960
c98e9dcf 2961 if (HAS_PCH_CPT(dev)) {
4b645f14
JB		 2962 transc_sel = intel_crtc->use_pll_a ? TRANSC_DPLLA_SEL :
2963 TRANSC_DPLLB_SEL;
2964
c98e9dcf
JB		 2965 /* Be sure PCH DPLL SEL is set */
2966 temp = I915_READ(PCH_DPLL_SEL);
d64311ab
JB		 2967 if (pipe == 0) {
2968 temp &= ~(TRANSA_DPLLB_SEL);
c98e9dcf 2969 temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
d64311ab
JB		 2970 } else if (pipe == 1) {
2971 temp &= ~(TRANSB_DPLLB_SEL);
c98e9dcf 2972 temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
d64311ab
JB		 2973 } else if (pipe == 2) {
2974 temp &= ~(TRANSC_DPLLB_SEL);
4b645f14 2975 temp |= (TRANSC_DPLL_ENABLE | transc_sel);
d64311ab 2976 }
c98e9dcf 2977 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 2978 }
5eddb70b 2979
d9b6cb56
JB		 2980 /* set transcoder timing, panel must allow it */
2981 assert_panel_unlocked(dev_priv, pipe);
5eddb70b
CW		 2982 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
2983 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
2984 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
8db9d77b 2985
5eddb70b
CW		 2986 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
2987 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
2988 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
0529a0d9 2989 I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe)));
8db9d77b 2990
5e84e1a4
ZW		 2991 intel_fdi_normal_train(crtc);
2992
c98e9dcf
JB		 2993 /* For PCH DP, enable TRANS_DP_CTL */
2994 if (HAS_PCH_CPT(dev) &&
417e822d
KP		 2995 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
2996 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
9325c9f0 2997 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
5eddb70b
CW		 2998 reg = TRANS_DP_CTL(pipe);
2999 temp = I915_READ(reg);
3000 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 3001 TRANS_DP_SYNC_MASK |
3002 TRANS_DP_BPC_MASK);
5eddb70b
CW		 3003 temp |= (TRANS_DP_OUTPUT_ENABLE |
3004 TRANS_DP_ENH_FRAMING);
9325c9f0 3005 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 3006
3007 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 3008 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 3009 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 3010 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 3011
3012 switch (intel_trans_dp_port_sel(crtc)) {
3013 case PCH_DP_B:
5eddb70b 3014 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 3015 break;
3016 case PCH_DP_C:
5eddb70b 3017 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 3018 break;
3019 case PCH_DP_D:
5eddb70b 3020 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 3021 break;
3022 default:
3023 DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
5eddb70b 3024 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf 3025 break;
32f9d658 3026 }
2c07245f 3027
5eddb70b 3028 I915_WRITE(reg, temp);
6be4a607 3029 }
b52eb4dc 3030
040484af 3031 intel_enable_transcoder(dev_priv, pipe);
f67a559d
JB		 3032}
3033
d4270e57
JB		 3034void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3035{
3036 struct drm_i915_private *dev_priv = dev->dev_private;
3037 int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe);
3038 u32 temp;
3039
3040 temp = I915_READ(dslreg);
3041 udelay(500);
3042 if (wait_for(I915_READ(dslreg) != temp, 5)) {
3043 /* Without this, mode sets may fail silently on FDI */
3044 I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS);
3045 udelay(250);
3046 I915_WRITE(tc2reg, 0);
3047 if (wait_for(I915_READ(dslreg) != temp, 5))
3048 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3049 }
3050}
3051
f67a559d
JB		 3052static void ironlake_crtc_enable(struct drm_crtc *crtc)
3053{
3054 struct drm_device *dev = crtc->dev;
3055 struct drm_i915_private *dev_priv = dev->dev_private;
3056 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3057 int pipe = intel_crtc->pipe;
3058 int plane = intel_crtc->plane;
3059 u32 temp;
3060 bool is_pch_port;
3061
3062 if (intel_crtc->active)
3063 return;
3064
3065 intel_crtc->active = true;
3066 intel_update_watermarks(dev);
3067
3068 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3069 temp = I915_READ(PCH_LVDS);
3070 if ((temp & LVDS_PORT_EN) == 0)
3071 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3072 }
3073
3074 is_pch_port = intel_crtc_driving_pch(crtc);
3075
3076 if (is_pch_port)
357555c0 3077 ironlake_fdi_pll_enable(crtc);
f67a559d
JB		 3078 else
3079 ironlake_fdi_disable(crtc);
3080
3081 /* Enable panel fitting for LVDS */
3082 if (dev_priv->pch_pf_size &&
3083 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
3084 /* Force use of hard-coded filter coefficients
3085 * as some pre-programmed values are broken,
3086 * e.g. x201.
3087 */
9db4a9c7
JB		 3088 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3089 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3090 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
f67a559d
JB		 3091 }
3092
9c54c0dd
JB		 3093 /*
3094 * On ILK+ LUT must be loaded before the pipe is running but with
3095 * clocks enabled
3096 */
3097 intel_crtc_load_lut(crtc);
3098
f67a559d
JB		 3099 intel_enable_pipe(dev_priv, pipe, is_pch_port);
3100 intel_enable_plane(dev_priv, plane, pipe);
3101
3102 if (is_pch_port)
3103 ironlake_pch_enable(crtc);
c98e9dcf 3104
d1ebd816 3105 mutex_lock(&dev->struct_mutex);
bed4a673 3106 intel_update_fbc(dev);
d1ebd816
BW		 3107 mutex_unlock(&dev->struct_mutex);
3108
6b383a7f 3109 intel_crtc_update_cursor(crtc, true);
6be4a607
JB		 3110}
3111
3112static void ironlake_crtc_disable(struct drm_crtc *crtc)
3113{
3114 struct drm_device *dev = crtc->dev;
3115 struct drm_i915_private *dev_priv = dev->dev_private;
3116 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3117 int pipe = intel_crtc->pipe;
3118 int plane = intel_crtc->plane;
5eddb70b 3119 u32 reg, temp;
b52eb4dc 3120
f7abfe8b
CW		 3121 if (!intel_crtc->active)
3122 return;
3123
e6c3a2a6 3124 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 3125 drm_vblank_off(dev, pipe);
6b383a7f 3126 intel_crtc_update_cursor(crtc, false);
5eddb70b 3127
b24e7179 3128 intel_disable_plane(dev_priv, plane, pipe);
913d8d11 3129
973d04f9
CW		 3130 if (dev_priv->cfb_plane == plane)
3131 intel_disable_fbc(dev);
2c07245f 3132
b24e7179 3133 intel_disable_pipe(dev_priv, pipe);
32f9d658 3134
6be4a607 3135 /* Disable PF */
9db4a9c7
JB		 3136 I915_WRITE(PF_CTL(pipe), 0);
3137 I915_WRITE(PF_WIN_SZ(pipe), 0);
2c07245f 3138
0fc932b8 3139 ironlake_fdi_disable(crtc);
2c07245f 3140
47a05eca
JB		 3141 /* This is a horrible layering violation; we should be doing this in
3142 * the connector/encoder ->prepare instead, but we don't always have
3143 * enough information there about the config to know whether it will
3144 * actually be necessary or just cause undesired flicker.
3145 */
3146 intel_disable_pch_ports(dev_priv, pipe);
249c0e64 3147
040484af 3148 intel_disable_transcoder(dev_priv, pipe);
913d8d11 3149
6be4a607
JB		 3150 if (HAS_PCH_CPT(dev)) {
3151 /* disable TRANS_DP_CTL */
5eddb70b
CW		 3152 reg = TRANS_DP_CTL(pipe);
3153 temp = I915_READ(reg);
3154 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
cb3543c6 3155 temp |= TRANS_DP_PORT_SEL_NONE;
5eddb70b 3156 I915_WRITE(reg, temp);
6be4a607
JB		 3157
3158 /* disable DPLL_SEL */
3159 temp = I915_READ(PCH_DPLL_SEL);
9db4a9c7
JB		 3160 switch (pipe) {
3161 case 0:
d64311ab 3162 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
9db4a9c7
JB		 3163 break;
3164 case 1:
6be4a607 3165 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
9db4a9c7
JB		 3166 break;
3167 case 2:
4b645f14 3168 /* C shares PLL A or B */
d64311ab 3169 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
9db4a9c7
JB		 3170 break;
3171 default:
3172 BUG(); /* wtf */
3173 }
6be4a607 3174 I915_WRITE(PCH_DPLL_SEL, temp);
6be4a607 3175 }
e3421a18 3176
6be4a607 3177 /* disable PCH DPLL */
4b645f14
JB		 3178 if (!intel_crtc->no_pll)
3179 intel_disable_pch_pll(dev_priv, pipe);
8db9d77b 3180
6be4a607 3181 /* Switch from PCDclk to Rawclk */
5eddb70b
CW		 3182 reg = FDI_RX_CTL(pipe);
3183 temp = I915_READ(reg);
3184 I915_WRITE(reg, temp & ~FDI_PCDCLK);
8db9d77b 3185
6be4a607 3186 /* Disable CPU FDI TX PLL */
5eddb70b
CW		 3187 reg = FDI_TX_CTL(pipe);
3188 temp = I915_READ(reg);
3189 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3190
3191 POSTING_READ(reg);
6be4a607 3192 udelay(100);
8db9d77b 3193
5eddb70b
CW		 3194 reg = FDI_RX_CTL(pipe);
3195 temp = I915_READ(reg);
3196 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2c07245f 3197
6be4a607 3198 /* Wait for the clocks to turn off. */
5eddb70b 3199 POSTING_READ(reg);
6be4a607 3200 udelay(100);
6b383a7f 3201
f7abfe8b 3202 intel_crtc->active = false;
6b383a7f 3203 intel_update_watermarks(dev);
d1ebd816
BW		 3204
3205 mutex_lock(&dev->struct_mutex);
6b383a7f
CW		 3206 intel_update_fbc(dev);
3207 intel_clear_scanline_wait(dev);
d1ebd816 3208 mutex_unlock(&dev->struct_mutex);
6be4a607 3209}
1b3c7a47 3210
6be4a607
JB		 3211static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
3212{
3213 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3214 int pipe = intel_crtc->pipe;
3215 int plane = intel_crtc->plane;
8db9d77b 3216
6be4a607
JB		 3217 /* XXX: When our outputs are all unaware of DPMS modes other than off
3218 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3219 */
3220 switch (mode) {
3221 case DRM_MODE_DPMS_ON:
3222 case DRM_MODE_DPMS_STANDBY:
3223 case DRM_MODE_DPMS_SUSPEND:
3224 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
3225 ironlake_crtc_enable(crtc);
3226 break;
1b3c7a47 3227
6be4a607
JB		 3228 case DRM_MODE_DPMS_OFF:
3229 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
3230 ironlake_crtc_disable(crtc);
2c07245f
ZW		 3231 break;
3232 }
3233}
3234
02e792fb
DV		 3235static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3236{
02e792fb 3237 if (!enable && intel_crtc->overlay) {
23f09ce3 3238 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 3239 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 3240
23f09ce3 3241 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 3242 dev_priv->mm.interruptible = false;
3243 (void) intel_overlay_switch_off(intel_crtc->overlay);
3244 dev_priv->mm.interruptible = true;
23f09ce3 3245 mutex_unlock(&dev->struct_mutex);
02e792fb 3246 }
02e792fb 3247
5dcdbcb0
CW		 3248 /* Let userspace switch the overlay on again. In most cases userspace
3249 * has to recompute where to put it anyway.
3250 */
02e792fb
DV		 3251}
3252
0b8765c6 3253static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 3254{
3255 struct drm_device *dev = crtc->dev;
79e53945
JB		 3256 struct drm_i915_private *dev_priv = dev->dev_private;
3257 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3258 int pipe = intel_crtc->pipe;
80824003 3259 int plane = intel_crtc->plane;
79e53945 3260
f7abfe8b
CW		 3261 if (intel_crtc->active)
3262 return;
3263
3264 intel_crtc->active = true;
6b383a7f
CW		 3265 intel_update_watermarks(dev);
3266
63d7bbe9 3267 intel_enable_pll(dev_priv, pipe);
040484af 3268 intel_enable_pipe(dev_priv, pipe, false);
b24e7179 3269 intel_enable_plane(dev_priv, plane, pipe);
79e53945 3270
0b8765c6 3271 intel_crtc_load_lut(crtc);
bed4a673 3272 intel_update_fbc(dev);
79e53945 3273
0b8765c6
JB		 3274 /* Give the overlay scaler a chance to enable if it's on this pipe */
3275 intel_crtc_dpms_overlay(intel_crtc, true);
6b383a7f 3276 intel_crtc_update_cursor(crtc, true);
0b8765c6 3277}
79e53945 3278
0b8765c6
JB		 3279static void i9xx_crtc_disable(struct drm_crtc *crtc)
3280{
3281 struct drm_device *dev = crtc->dev;
3282 struct drm_i915_private *dev_priv = dev->dev_private;
3283 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3284 int pipe = intel_crtc->pipe;
3285 int plane = intel_crtc->plane;
b690e96c 3286
f7abfe8b
CW		 3287 if (!intel_crtc->active)
3288 return;
3289
0b8765c6 3290 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 3291 intel_crtc_wait_for_pending_flips(crtc);
3292 drm_vblank_off(dev, pipe);
0b8765c6 3293 intel_crtc_dpms_overlay(intel_crtc, false);
6b383a7f 3294 intel_crtc_update_cursor(crtc, false);
0b8765c6 3295
973d04f9
CW		 3296 if (dev_priv->cfb_plane == plane)
3297 intel_disable_fbc(dev);
79e53945 3298
b24e7179 3299 intel_disable_plane(dev_priv, plane, pipe);
b24e7179 3300 intel_disable_pipe(dev_priv, pipe);
63d7bbe9 3301 intel_disable_pll(dev_priv, pipe);
0b8765c6 3302
f7abfe8b 3303 intel_crtc->active = false;
6b383a7f
CW		 3304 intel_update_fbc(dev);
3305 intel_update_watermarks(dev);
3306 intel_clear_scanline_wait(dev);
0b8765c6
JB		 3307}
3308
3309static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
3310{
3311 /* XXX: When our outputs are all unaware of DPMS modes other than off
3312 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3313 */
3314 switch (mode) {
3315 case DRM_MODE_DPMS_ON:
3316 case DRM_MODE_DPMS_STANDBY:
3317 case DRM_MODE_DPMS_SUSPEND:
3318 i9xx_crtc_enable(crtc);
3319 break;
3320 case DRM_MODE_DPMS_OFF:
3321 i9xx_crtc_disable(crtc);
79e53945
JB		 3322 break;
3323 }
2c07245f
ZW		 3324}
3325
3326/**
3327 * Sets the power management mode of the pipe and plane.
2c07245f
ZW		 3328 */
3329static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
3330{
3331 struct drm_device *dev = crtc->dev;
e70236a8 3332 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f
ZW		 3333 struct drm_i915_master_private *master_priv;
3334 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3335 int pipe = intel_crtc->pipe;
3336 bool enabled;
3337
032d2a0d
CW		 3338 if (intel_crtc->dpms_mode == mode)
3339 return;
3340
65655d4a 3341 intel_crtc->dpms_mode = mode;
debcaddc 3342
e70236a8 3343 dev_priv->display.dpms(crtc, mode);
79e53945
JB		 3344
3345 if (!dev->primary->master)
3346 return;
3347
3348 master_priv = dev->primary->master->driver_priv;
3349 if (!master_priv->sarea_priv)
3350 return;
3351
3352 enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
3353
3354 switch (pipe) {
3355 case 0:
3356 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3357 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3358 break;
3359 case 1:
3360 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3361 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3362 break;
3363 default:
9db4a9c7 3364 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 3365 break;
3366 }
79e53945
JB		 3367}
3368
cdd59983
CW		 3369static void intel_crtc_disable(struct drm_crtc *crtc)
3370{
3371 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
3372 struct drm_device *dev = crtc->dev;
3373
3374 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
931872fc
CW		 3375 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3376 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
cdd59983
CW		 3377
3378 if (crtc->fb) {
3379 mutex_lock(&dev->struct_mutex);
1690e1eb 3380 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
cdd59983
CW		 3381 mutex_unlock(&dev->struct_mutex);
3382 }
3383}
3384
7e7d76c3
JB		 3385/* Prepare for a mode set.
3386 *
3387 * Note we could be a lot smarter here. We need to figure out which outputs
3388 * will be enabled, which disabled (in short, how the config will changes)
3389 * and perform the minimum necessary steps to accomplish that, e.g. updating
3390 * watermarks, FBC configuration, making sure PLLs are programmed correctly,
3391 * panel fitting is in the proper state, etc.
3392 */
3393static void i9xx_crtc_prepare(struct drm_crtc *crtc)
79e53945 3394{
7e7d76c3 3395 i9xx_crtc_disable(crtc);
79e53945
JB		 3396}
3397
7e7d76c3 3398static void i9xx_crtc_commit(struct drm_crtc *crtc)
79e53945 3399{
7e7d76c3 3400 i9xx_crtc_enable(crtc);
7e7d76c3
JB		 3401}
3402
3403static void ironlake_crtc_prepare(struct drm_crtc *crtc)
3404{
7e7d76c3 3405 ironlake_crtc_disable(crtc);
7e7d76c3
JB		 3406}
3407
3408static void ironlake_crtc_commit(struct drm_crtc *crtc)
3409{
7e7d76c3 3410 ironlake_crtc_enable(crtc);
79e53945
JB		 3411}
3412
0206e353 3413void intel_encoder_prepare(struct drm_encoder *encoder)
79e53945
JB		 3414{
3415 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3416 /* lvds has its own version of prepare see intel_lvds_prepare */
3417 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
3418}
3419
0206e353 3420void intel_encoder_commit(struct drm_encoder *encoder)
79e53945
JB		 3421{
3422 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
d4270e57
JB		 3423 struct drm_device *dev = encoder->dev;
3424 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3425 struct intel_crtc *intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
3426
79e53945
JB		 3427 /* lvds has its own version of commit see intel_lvds_commit */
3428 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
d4270e57
JB		 3429
3430 if (HAS_PCH_CPT(dev))
3431 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
79e53945
JB		 3432}
3433
ea5b213a
CW		 3434void intel_encoder_destroy(struct drm_encoder *encoder)
3435{
4ef69c7a 3436 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 3437
ea5b213a
CW		 3438 drm_encoder_cleanup(encoder);
3439 kfree(intel_encoder);
3440}
3441
79e53945
JB		 3442static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3443 struct drm_display_mode *mode,
3444 struct drm_display_mode *adjusted_mode)
3445{
2c07245f 3446 struct drm_device *dev = crtc->dev;
89749350 3447
bad720ff 3448 if (HAS_PCH_SPLIT(dev)) {
2c07245f 3449 /* FDI link clock is fixed at 2.7G */
2377b741
JB		 3450 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3451 return false;
2c07245f 3452 }
89749350 3453
ca9bfa7e
DV		 3454 /* All interlaced capable intel hw wants timings in frames. */
3455 drm_mode_set_crtcinfo(adjusted_mode, 0);
89749350 3456
79e53945
JB		 3457 return true;
3458}
3459
e70236a8
JB		 3460static int i945_get_display_clock_speed(struct drm_device *dev)
3461{
3462 return 400000;
3463}
79e53945 3464
e70236a8 3465static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 3466{
e70236a8
JB		 3467 return 333000;
3468}
79e53945 3469
e70236a8
JB		 3470static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3471{
3472 return 200000;
3473}
79e53945 3474
e70236a8
JB		 3475static int i915gm_get_display_clock_speed(struct drm_device *dev)
3476{
3477 u16 gcfgc = 0;
79e53945 3478
e70236a8
JB		 3479 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3480
3481 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3482 return 133000;
3483 else {
3484 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3485 case GC_DISPLAY_CLOCK_333_MHZ:
3486 return 333000;
3487 default:
3488 case GC_DISPLAY_CLOCK_190_200_MHZ:
3489 return 190000;
79e53945 3490 }
e70236a8
JB		 3491 }
3492}
3493
3494static int i865_get_display_clock_speed(struct drm_device *dev)
3495{
3496 return 266000;
3497}
3498
3499static int i855_get_display_clock_speed(struct drm_device *dev)
3500{
3501 u16 hpllcc = 0;
3502 /* Assume that the hardware is in the high speed state. This
3503 * should be the default.
3504 */
3505 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3506 case GC_CLOCK_133_200:
3507 case GC_CLOCK_100_200:
3508 return 200000;
3509 case GC_CLOCK_166_250:
3510 return 250000;
3511 case GC_CLOCK_100_133:
79e53945 3512 return 133000;
e70236a8 3513 }
79e53945 3514
e70236a8
JB		 3515 /* Shouldn't happen */
3516 return 0;
3517}
79e53945 3518
e70236a8
JB		 3519static int i830_get_display_clock_speed(struct drm_device *dev)
3520{
3521 return 133000;
79e53945
JB		 3522}
3523
2c07245f
ZW		 3524struct fdi_m_n {
3525 u32 tu;
3526 u32 gmch_m;
3527 u32 gmch_n;
3528 u32 link_m;
3529 u32 link_n;
3530};
3531
3532static void
3533fdi_reduce_ratio(u32 *num, u32 *den)
3534{
3535 while (*num > 0xffffff || *den > 0xffffff) {
3536 *num >>= 1;
3537 *den >>= 1;
3538 }
3539}
3540
2c07245f 3541static void
f2b115e6
AJ		 3542ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3543 int link_clock, struct fdi_m_n *m_n)
2c07245f 3544{
2c07245f
ZW		 3545 m_n->tu = 64; /* default size */
3546
22ed1113
CW		 3547 /* BUG_ON(pixel_clock > INT_MAX / 36); */
3548 m_n->gmch_m = bits_per_pixel * pixel_clock;
3549 m_n->gmch_n = link_clock * nlanes * 8;
2c07245f
ZW		 3550 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3551
22ed1113
CW		 3552 m_n->link_m = pixel_clock;
3553 m_n->link_n = link_clock;
2c07245f
ZW		 3554 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3555}
3556
3557
7662c8bd
SL		 3558struct intel_watermark_params {
3559 unsigned long fifo_size;
3560 unsigned long max_wm;
3561 unsigned long default_wm;
3562 unsigned long guard_size;
3563 unsigned long cacheline_size;
3564};
3565
f2b115e6 3566/* Pineview has different values for various configs */
d210246a 3567static const struct intel_watermark_params pineview_display_wm = {
f2b115e6
AJ		 3568 PINEVIEW_DISPLAY_FIFO,
3569 PINEVIEW_MAX_WM,
3570 PINEVIEW_DFT_WM,
3571 PINEVIEW_GUARD_WM,
3572 PINEVIEW_FIFO_LINE_SIZE
7662c8bd 3573};
d210246a 3574static const struct intel_watermark_params pineview_display_hplloff_wm = {
f2b115e6
AJ		 3575 PINEVIEW_DISPLAY_FIFO,
3576 PINEVIEW_MAX_WM,
3577 PINEVIEW_DFT_HPLLOFF_WM,
3578 PINEVIEW_GUARD_WM,
3579 PINEVIEW_FIFO_LINE_SIZE
7662c8bd 3580};
d210246a 3581static const struct intel_watermark_params pineview_cursor_wm = {
f2b115e6
AJ		 3582 PINEVIEW_CURSOR_FIFO,
3583 PINEVIEW_CURSOR_MAX_WM,
3584 PINEVIEW_CURSOR_DFT_WM,
3585 PINEVIEW_CURSOR_GUARD_WM,
3586 PINEVIEW_FIFO_LINE_SIZE,
7662c8bd 3587};
d210246a 3588static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
f2b115e6
AJ		 3589 PINEVIEW_CURSOR_FIFO,
3590 PINEVIEW_CURSOR_MAX_WM,
3591 PINEVIEW_CURSOR_DFT_WM,
3592 PINEVIEW_CURSOR_GUARD_WM,
3593 PINEVIEW_FIFO_LINE_SIZE
7662c8bd 3594};
d210246a 3595static const struct intel_watermark_params g4x_wm_info = {
0e442c60
JB		 3596 G4X_FIFO_SIZE,
3597 G4X_MAX_WM,
3598 G4X_MAX_WM,
3599 2,
3600 G4X_FIFO_LINE_SIZE,
3601};
d210246a 3602static const struct intel_watermark_params g4x_cursor_wm_info = {
4fe5e611
ZY		 3603 I965_CURSOR_FIFO,
3604 I965_CURSOR_MAX_WM,
3605 I965_CURSOR_DFT_WM,
3606 2,
3607 G4X_FIFO_LINE_SIZE,
3608};
d210246a 3609static const struct intel_watermark_params i965_cursor_wm_info = {
4fe5e611
ZY		 3610 I965_CURSOR_FIFO,
3611 I965_CURSOR_MAX_WM,
3612 I965_CURSOR_DFT_WM,
3613 2,
3614 I915_FIFO_LINE_SIZE,
3615};
d210246a 3616static const struct intel_watermark_params i945_wm_info = {
dff33cfc 3617 I945_FIFO_SIZE,
7662c8bd
SL		 3618 I915_MAX_WM,
3619 1,
dff33cfc
JB		 3620 2,
3621 I915_FIFO_LINE_SIZE
7662c8bd 3622};
d210246a 3623static const struct intel_watermark_params i915_wm_info = {
dff33cfc 3624 I915_FIFO_SIZE,
7662c8bd
SL		 3625 I915_MAX_WM,
3626 1,
dff33cfc 3627 2,
7662c8bd
SL		 3628 I915_FIFO_LINE_SIZE
3629};
d210246a 3630static const struct intel_watermark_params i855_wm_info = {
7662c8bd
SL		 3631 I855GM_FIFO_SIZE,
3632 I915_MAX_WM,
3633 1,
dff33cfc 3634 2,
7662c8bd
SL		 3635 I830_FIFO_LINE_SIZE
3636};
d210246a 3637static const struct intel_watermark_params i830_wm_info = {
7662c8bd
SL		 3638 I830_FIFO_SIZE,
3639 I915_MAX_WM,
3640 1,
dff33cfc 3641 2,
7662c8bd
SL		 3642 I830_FIFO_LINE_SIZE
3643};
3644
d210246a 3645static const struct intel_watermark_params ironlake_display_wm_info = {
7f8a8569
ZW		 3646 ILK_DISPLAY_FIFO,
3647 ILK_DISPLAY_MAXWM,
3648 ILK_DISPLAY_DFTWM,
3649 2,
3650 ILK_FIFO_LINE_SIZE
3651};
d210246a 3652static const struct intel_watermark_params ironlake_cursor_wm_info = {
c936f44d
ZY		 3653 ILK_CURSOR_FIFO,
3654 ILK_CURSOR_MAXWM,
3655 ILK_CURSOR_DFTWM,
3656 2,
3657 ILK_FIFO_LINE_SIZE
3658};
d210246a 3659static const struct intel_watermark_params ironlake_display_srwm_info = {
7f8a8569
ZW		 3660 ILK_DISPLAY_SR_FIFO,
3661 ILK_DISPLAY_MAX_SRWM,
3662 ILK_DISPLAY_DFT_SRWM,
3663 2,
3664 ILK_FIFO_LINE_SIZE
3665};
d210246a 3666static const struct intel_watermark_params ironlake_cursor_srwm_info = {
7f8a8569
ZW		 3667 ILK_CURSOR_SR_FIFO,
3668 ILK_CURSOR_MAX_SRWM,
3669 ILK_CURSOR_DFT_SRWM,
3670 2,
3671 ILK_FIFO_LINE_SIZE
3672};
3673
d210246a 3674static const struct intel_watermark_params sandybridge_display_wm_info = {
1398261a
YL		 3675 SNB_DISPLAY_FIFO,
3676 SNB_DISPLAY_MAXWM,
3677 SNB_DISPLAY_DFTWM,
3678 2,
3679 SNB_FIFO_LINE_SIZE
3680};
d210246a 3681static const struct intel_watermark_params sandybridge_cursor_wm_info = {
1398261a
YL		 3682 SNB_CURSOR_FIFO,
3683 SNB_CURSOR_MAXWM,
3684 SNB_CURSOR_DFTWM,
3685 2,
3686 SNB_FIFO_LINE_SIZE
3687};
d210246a 3688static const struct intel_watermark_params sandybridge_display_srwm_info = {
1398261a
YL		 3689 SNB_DISPLAY_SR_FIFO,
3690 SNB_DISPLAY_MAX_SRWM,
3691 SNB_DISPLAY_DFT_SRWM,
3692 2,
3693 SNB_FIFO_LINE_SIZE
3694};
d210246a 3695static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
1398261a
YL		 3696 SNB_CURSOR_SR_FIFO,
3697 SNB_CURSOR_MAX_SRWM,
3698 SNB_CURSOR_DFT_SRWM,
3699 2,
3700 SNB_FIFO_LINE_SIZE
3701};
3702
3703
dff33cfc
JB		 3704/**
3705 * intel_calculate_wm - calculate watermark level
3706 * @clock_in_khz: pixel clock
3707 * @wm: chip FIFO params
3708 * @pixel_size: display pixel size
3709 * @latency_ns: memory latency for the platform
3710 *
3711 * Calculate the watermark level (the level at which the display plane will
3712 * start fetching from memory again). Each chip has a different display
3713 * FIFO size and allocation, so the caller needs to figure that out and pass
3714 * in the correct intel_watermark_params structure.
3715 *
3716 * As the pixel clock runs, the FIFO will be drained at a rate that depends
3717 * on the pixel size. When it reaches the watermark level, it'll start
3718 * fetching FIFO line sized based chunks from memory until the FIFO fills
3719 * past the watermark point. If the FIFO drains completely, a FIFO underrun
3720 * will occur, and a display engine hang could result.
3721 */
7662c8bd 3722static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
d210246a
CW		 3723 const struct intel_watermark_params *wm,
3724 int fifo_size,
7662c8bd
SL		 3725 int pixel_size,
3726 unsigned long latency_ns)
3727{
390c4dd4 3728 long entries_required, wm_size;
dff33cfc 3729
d660467c
JB		 3730 /*
3731 * Note: we need to make sure we don't overflow for various clock &
3732 * latency values.
3733 * clocks go from a few thousand to several hundred thousand.
3734 * latency is usually a few thousand
3735 */
3736 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
3737 1000;
8de9b311 3738 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
7662c8bd 3739
bbb0aef5 3740 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
dff33cfc 3741
d210246a 3742 wm_size = fifo_size - (entries_required + wm->guard_size);
dff33cfc 3743
bbb0aef5 3744 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
7662c8bd 3745
390c4dd4
JB		 3746 /* Don't promote wm_size to unsigned... */
3747 if (wm_size > (long)wm->max_wm)
7662c8bd 3748 wm_size = wm->max_wm;
c3add4b6 3749 if (wm_size <= 0)
7662c8bd
SL		 3750 wm_size = wm->default_wm;
3751 return wm_size;
3752}
3753
3754struct cxsr_latency {
3755 int is_desktop;
95534263 3756 int is_ddr3;
7662c8bd
SL		 3757 unsigned long fsb_freq;
3758 unsigned long mem_freq;
3759 unsigned long display_sr;
3760 unsigned long display_hpll_disable;
3761 unsigned long cursor_sr;
3762 unsigned long cursor_hpll_disable;
3763};
3764
403c89ff 3765static const struct cxsr_latency cxsr_latency_table[] = {
95534263
LP		 3766 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
3767 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
3768 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
3769 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
3770 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
3771
3772 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
3773 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
3774 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
3775 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
3776 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
3777
3778 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
3779 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
3780 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
3781 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
3782 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
3783
3784 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
3785 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
3786 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
3787 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
3788 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
3789
3790 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
3791 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
3792 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
3793 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
3794 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
3795
3796 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
3797 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
3798 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
3799 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
3800 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
7662c8bd
SL		 3801};
3802
403c89ff
CW		 3803static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
3804 int is_ddr3,
3805 int fsb,
3806 int mem)
7662c8bd 3807{
403c89ff 3808 const struct cxsr_latency *latency;
7662c8bd 3809 int i;
7662c8bd
SL		 3810
3811 if (fsb == 0 || mem == 0)
3812 return NULL;
3813
3814 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
3815 latency = &cxsr_latency_table[i];
3816 if (is_desktop == latency->is_desktop &&
95534263 3817 is_ddr3 == latency->is_ddr3 &&
decbbcda
JSR		 3818 fsb == latency->fsb_freq && mem == latency->mem_freq)
3819 return latency;
7662c8bd 3820 }
decbbcda 3821
28c97730 3822 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
decbbcda
JSR		 3823
3824 return NULL;
7662c8bd
SL		 3825}
3826
f2b115e6 3827static void pineview_disable_cxsr(struct drm_device *dev)
7662c8bd
SL		 3828{
3829 struct drm_i915_private *dev_priv = dev->dev_private;
7662c8bd
SL		 3830
3831 /* deactivate cxsr */
3e33d94d 3832 I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
7662c8bd
SL		 3833}
3834
bcc24fb4
JB		 3835/*
3836 * Latency for FIFO fetches is dependent on several factors:
3837 * - memory configuration (speed, channels)
3838 * - chipset
3839 * - current MCH state
3840 * It can be fairly high in some situations, so here we assume a fairly
3841 * pessimal value. It's a tradeoff between extra memory fetches (if we
3842 * set this value too high, the FIFO will fetch frequently to stay full)
3843 * and power consumption (set it too low to save power and we might see
3844 * FIFO underruns and display "flicker").
3845 *
3846 * A value of 5us seems to be a good balance; safe for very low end
3847 * platforms but not overly aggressive on lower latency configs.
3848 */
69e302a9 3849static const int latency_ns = 5000;
7662c8bd 3850
e70236a8 3851static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
dff33cfc
JB		 3852{
3853 struct drm_i915_private *dev_priv = dev->dev_private;
3854 uint32_t dsparb = I915_READ(DSPARB);
3855 int size;
3856
8de9b311
CW		 3857 size = dsparb & 0x7f;
3858 if (plane)
3859 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
dff33cfc 3860
28c97730 3861 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
5eddb70b 3862 plane ? "B" : "A", size);
dff33cfc
JB		 3863
3864 return size;
3865}
7662c8bd 3866
e70236a8
JB		 3867static int i85x_get_fifo_size(struct drm_device *dev, int plane)
3868{
3869 struct drm_i915_private *dev_priv = dev->dev_private;
3870 uint32_t dsparb = I915_READ(DSPARB);
3871 int size;
3872
8de9b311
CW		 3873 size = dsparb & 0x1ff;
3874 if (plane)
3875 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
e70236a8 3876 size >>= 1; /* Convert to cachelines */
dff33cfc 3877
28c97730 3878 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
5eddb70b 3879 plane ? "B" : "A", size);
dff33cfc
JB		 3880
3881 return size;
3882}
7662c8bd 3883
e70236a8
JB		 3884static int i845_get_fifo_size(struct drm_device *dev, int plane)
3885{
3886 struct drm_i915_private *dev_priv = dev->dev_private;
3887 uint32_t dsparb = I915_READ(DSPARB);
3888 int size;
3889
3890 size = dsparb & 0x7f;
3891 size >>= 2; /* Convert to cachelines */
3892
28c97730 3893 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
5eddb70b
CW		 3894 plane ? "B" : "A",
3895 size);
e70236a8
JB		 3896
3897 return size;
3898}
3899
3900static int i830_get_fifo_size(struct drm_device *dev, int plane)
3901{
3902 struct drm_i915_private *dev_priv = dev->dev_private;
3903 uint32_t dsparb = I915_READ(DSPARB);
3904 int size;
3905
3906 size = dsparb & 0x7f;
3907 size >>= 1; /* Convert to cachelines */
3908
28c97730 3909 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
5eddb70b 3910 plane ? "B" : "A", size);
e70236a8
JB		 3911
3912 return size;
3913}
3914
d210246a
CW		 3915static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
3916{
3917 struct drm_crtc *crtc, *enabled = NULL;
3918
3919 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3920 if (crtc->enabled && crtc->fb) {
3921 if (enabled)
3922 return NULL;
3923 enabled = crtc;
3924 }
3925 }
3926
3927 return enabled;
3928}
3929
3930static void pineview_update_wm(struct drm_device *dev)
d4294342
ZY		 3931{
3932 struct drm_i915_private *dev_priv = dev->dev_private;
d210246a 3933 struct drm_crtc *crtc;
403c89ff 3934 const struct cxsr_latency *latency;
d4294342
ZY		 3935 u32 reg;
3936 unsigned long wm;
d4294342 3937
403c89ff 3938 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
95534263 3939 dev_priv->fsb_freq, dev_priv->mem_freq);
d4294342
ZY		 3940 if (!latency) {
3941 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3942 pineview_disable_cxsr(dev);
3943 return;
3944 }
3945
d210246a
CW		 3946 crtc = single_enabled_crtc(dev);
3947 if (crtc) {
3948 int clock = crtc->mode.clock;
3949 int pixel_size = crtc->fb->bits_per_pixel / 8;
d4294342
ZY		 3950
3951 /* Display SR */
d210246a
CW		 3952 wm = intel_calculate_wm(clock, &pineview_display_wm,
3953 pineview_display_wm.fifo_size,
d4294342
ZY		 3954 pixel_size, latency->display_sr);
3955 reg = I915_READ(DSPFW1);
3956 reg &= ~DSPFW_SR_MASK;
3957 reg |= wm << DSPFW_SR_SHIFT;
3958 I915_WRITE(DSPFW1, reg);
3959 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
3960
3961 /* cursor SR */
d210246a
CW		 3962 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
3963 pineview_display_wm.fifo_size,
d4294342
ZY		 3964 pixel_size, latency->cursor_sr);
3965 reg = I915_READ(DSPFW3);
3966 reg &= ~DSPFW_CURSOR_SR_MASK;
3967 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
3968 I915_WRITE(DSPFW3, reg);
3969
3970 /* Display HPLL off SR */
d210246a
CW		 3971 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
3972 pineview_display_hplloff_wm.fifo_size,
d4294342
ZY		 3973 pixel_size, latency->display_hpll_disable);
3974 reg = I915_READ(DSPFW3);
3975 reg &= ~DSPFW_HPLL_SR_MASK;
3976 reg |= wm & DSPFW_HPLL_SR_MASK;
3977 I915_WRITE(DSPFW3, reg);
3978
3979 /* cursor HPLL off SR */
d210246a
CW		 3980 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
3981 pineview_display_hplloff_wm.fifo_size,
d4294342
ZY		 3982 pixel_size, latency->cursor_hpll_disable);
3983 reg = I915_READ(DSPFW3);
3984 reg &= ~DSPFW_HPLL_CURSOR_MASK;
3985 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
3986 I915_WRITE(DSPFW3, reg);
3987 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
3988
3989 /* activate cxsr */
3e33d94d
CW		 3990 I915_WRITE(DSPFW3,
3991 I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
d4294342
ZY		 3992 DRM_DEBUG_KMS("Self-refresh is enabled\n");
3993 } else {
3994 pineview_disable_cxsr(dev);
3995 DRM_DEBUG_KMS("Self-refresh is disabled\n");
3996 }
3997}
3998
417ae147
CW		 3999static bool g4x_compute_wm0(struct drm_device *dev,
4000 int plane,
4001 const struct intel_watermark_params *display,
4002 int display_latency_ns,
4003 const struct intel_watermark_params *cursor,
4004 int cursor_latency_ns,
4005 int *plane_wm,
4006 int *cursor_wm)
4007{
4008 struct drm_crtc *crtc;
4009 int htotal, hdisplay, clock, pixel_size;
4010 int line_time_us, line_count;
4011 int entries, tlb_miss;
4012
4013 crtc = intel_get_crtc_for_plane(dev, plane);
5c72d064
CW		 4014 if (crtc->fb == NULL || !crtc->enabled) {
4015 *cursor_wm = cursor->guard_size;
4016 *plane_wm = display->guard_size;
417ae147 4017 return false;
5c72d064 4018 }
417ae147
CW		 4019
4020 htotal = crtc->mode.htotal;
4021 hdisplay = crtc->mode.hdisplay;
4022 clock = crtc->mode.clock;
4023 pixel_size = crtc->fb->bits_per_pixel / 8;
4024
4025 /* Use the small buffer method to calculate plane watermark */
4026 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
4027 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
4028 if (tlb_miss > 0)
4029 entries += tlb_miss;
4030 entries = DIV_ROUND_UP(entries, display->cacheline_size);
4031 *plane_wm = entries + display->guard_size;
4032 if (*plane_wm > (int)display->max_wm)
4033 *plane_wm = display->max_wm;
4034
4035 /* Use the large buffer method to calculate cursor watermark */
4036 line_time_us = ((htotal * 1000) / clock);
4037 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
4038 entries = line_count * 64 * pixel_size;
4039 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
4040 if (tlb_miss > 0)
4041 entries += tlb_miss;
4042 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4043 *cursor_wm = entries + cursor->guard_size;
4044 if (*cursor_wm > (int)cursor->max_wm)
4045 *cursor_wm = (int)cursor->max_wm;
4046
4047 return true;
4048}
4049
4050/*
4051 * Check the wm result.
4052 *
4053 * If any calculated watermark values is larger than the maximum value that
4054 * can be programmed into the associated watermark register, that watermark
4055 * must be disabled.
4056 */
4057static bool g4x_check_srwm(struct drm_device *dev,
4058 int display_wm, int cursor_wm,
4059 const struct intel_watermark_params *display,
4060 const struct intel_watermark_params *cursor)
652c393a 4061{
417ae147
CW		 4062 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
4063 display_wm, cursor_wm);
652c393a 4064
417ae147 4065 if (display_wm > display->max_wm) {
bbb0aef5 4066 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
417ae147
CW		 4067 display_wm, display->max_wm);
4068 return false;
4069 }
0e442c60 4070
417ae147 4071 if (cursor_wm > cursor->max_wm) {
bbb0aef5 4072 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
417ae147
CW		 4073 cursor_wm, cursor->max_wm);
4074 return false;
4075 }
0e442c60 4076
417ae147
CW		 4077 if (!(display_wm || cursor_wm)) {
4078 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
4079 return false;
4080 }
0e442c60 4081
417ae147
CW		 4082 return true;
4083}
0e442c60 4084
417ae147 4085static bool g4x_compute_srwm(struct drm_device *dev,
d210246a
CW		 4086 int plane,
4087 int latency_ns,
417ae147
CW		 4088 const struct intel_watermark_params *display,
4089 const struct intel_watermark_params *cursor,
4090 int *display_wm, int *cursor_wm)
4091{
d210246a
CW		 4092 struct drm_crtc *crtc;
4093 int hdisplay, htotal, pixel_size, clock;
417ae147
CW		 4094 unsigned long line_time_us;
4095 int line_count, line_size;
4096 int small, large;
4097 int entries;
0e442c60 4098
417ae147
CW		 4099 if (!latency_ns) {
4100 *display_wm = *cursor_wm = 0;
4101 return false;
4102 }
0e442c60 4103
d210246a
CW		 4104 crtc = intel_get_crtc_for_plane(dev, plane);
4105 hdisplay = crtc->mode.hdisplay;
4106 htotal = crtc->mode.htotal;
4107 clock = crtc->mode.clock;
4108 pixel_size = crtc->fb->bits_per_pixel / 8;
4109
417ae147
CW		 4110 line_time_us = (htotal * 1000) / clock;
4111 line_count = (latency_ns / line_time_us + 1000) / 1000;
4112 line_size = hdisplay * pixel_size;
0e442c60 4113
417ae147
CW		 4114 /* Use the minimum of the small and large buffer method for primary */
4115 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4116 large = line_count * line_size;
0e442c60 4117
417ae147
CW		 4118 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4119 *display_wm = entries + display->guard_size;
4fe5e611 4120
417ae147
CW		 4121 /* calculate the self-refresh watermark for display cursor */
4122 entries = line_count * pixel_size * 64;
4123 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4124 *cursor_wm = entries + cursor->guard_size;
4fe5e611 4125
417ae147
CW		 4126 return g4x_check_srwm(dev,
4127 *display_wm, *cursor_wm,
4128 display, cursor);
4129}
4fe5e611 4130
7ccb4a53 4131#define single_plane_enabled(mask) is_power_of_2(mask)
d210246a
CW		 4132
4133static void g4x_update_wm(struct drm_device *dev)
417ae147
CW		 4134{
4135 static const int sr_latency_ns = 12000;
4136 struct drm_i915_private *dev_priv = dev->dev_private;
4137 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
d210246a
CW		 4138 int plane_sr, cursor_sr;
4139 unsigned int enabled = 0;
417ae147
CW		 4140
4141 if (g4x_compute_wm0(dev, 0,
4142 &g4x_wm_info, latency_ns,
4143 &g4x_cursor_wm_info, latency_ns,
4144 &planea_wm, &cursora_wm))
d210246a 4145 enabled |= 1;
417ae147
CW		 4146
4147 if (g4x_compute_wm0(dev, 1,
4148 &g4x_wm_info, latency_ns,
4149 &g4x_cursor_wm_info, latency_ns,
4150 &planeb_wm, &cursorb_wm))
d210246a 4151 enabled |= 2;
417ae147
CW		 4152
4153 plane_sr = cursor_sr = 0;
d210246a
CW		 4154 if (single_plane_enabled(enabled) &&
4155 g4x_compute_srwm(dev, ffs(enabled) - 1,
4156 sr_latency_ns,
417ae147
CW		 4157 &g4x_wm_info,
4158 &g4x_cursor_wm_info,
4159 &plane_sr, &cursor_sr))
0e442c60 4160 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
417ae147
CW		 4161 else
4162 I915_WRITE(FW_BLC_SELF,
4163 I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
0e442c60 4164
308977ac
CW		 4165 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
4166 planea_wm, cursora_wm,
4167 planeb_wm, cursorb_wm,
4168 plane_sr, cursor_sr);
0e442c60 4169
417ae147
CW		 4170 I915_WRITE(DSPFW1,
4171 (plane_sr << DSPFW_SR_SHIFT) |
0e442c60 4172 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
417ae147
CW		 4173 (planeb_wm << DSPFW_PLANEB_SHIFT) |
4174 planea_wm);
4175 I915_WRITE(DSPFW2,
4176 (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
0e442c60
JB		 4177 (cursora_wm << DSPFW_CURSORA_SHIFT));
4178 /* HPLL off in SR has some issues on G4x... disable it */
417ae147
CW		 4179 I915_WRITE(DSPFW3,
4180 (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
0e442c60 4181 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
652c393a
JB		 4182}
4183
d210246a 4184static void i965_update_wm(struct drm_device *dev)
7662c8bd
SL		 4185{
4186 struct drm_i915_private *dev_priv = dev->dev_private;
d210246a
CW		 4187 struct drm_crtc *crtc;
4188 int srwm = 1;
4fe5e611 4189 int cursor_sr = 16;
1dc7546d
JB		 4190
4191 /* Calc sr entries for one plane configs */
d210246a
CW		 4192 crtc = single_enabled_crtc(dev);
4193 if (crtc) {
1dc7546d 4194 /* self-refresh has much higher latency */
69e302a9 4195 static const int sr_latency_ns = 12000;
d210246a
CW		 4196 int clock = crtc->mode.clock;
4197 int htotal = crtc->mode.htotal;
4198 int hdisplay = crtc->mode.hdisplay;
4199 int pixel_size = crtc->fb->bits_per_pixel / 8;
4200 unsigned long line_time_us;
4201 int entries;
1dc7546d 4202
d210246a 4203 line_time_us = ((htotal * 1000) / clock);
1dc7546d
JB		 4204
4205 /* Use ns/us then divide to preserve precision */
d210246a
CW		 4206 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4207 pixel_size * hdisplay;
4208 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
d210246a 4209 srwm = I965_FIFO_SIZE - entries;
1dc7546d
JB		 4210 if (srwm < 0)
4211 srwm = 1;
1b07e04e 4212 srwm &= 0x1ff;
308977ac
CW		 4213 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
4214 entries, srwm);
4fe5e611 4215
d210246a 4216 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
5eddb70b 4217 pixel_size * 64;
d210246a 4218 entries = DIV_ROUND_UP(entries,
8de9b311 4219 i965_cursor_wm_info.cacheline_size);
4fe5e611 4220 cursor_sr = i965_cursor_wm_info.fifo_size -
d210246a 4221 (entries + i965_cursor_wm_info.guard_size);
4fe5e611
ZY		 4222
4223 if (cursor_sr > i965_cursor_wm_info.max_wm)
4224 cursor_sr = i965_cursor_wm_info.max_wm;
4225
4226 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
4227 "cursor %d\n", srwm, cursor_sr);
4228
a6c45cf0 4229 if (IS_CRESTLINE(dev))
adcdbc66 4230 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
33c5fd12
DJ		 4231 } else {
4232 /* Turn off self refresh if both pipes are enabled */
a6c45cf0 4233 if (IS_CRESTLINE(dev))
adcdbc66
JB		 4234 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
4235 & ~FW_BLC_SELF_EN);
1dc7546d 4236 }
7662c8bd 4237
1dc7546d
JB		 4238 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
4239 srwm);
7662c8bd
SL		 4240
4241 /* 965 has limitations... */
417ae147
CW		 4242 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
4243 (8 << 16) | (8 << 8) | (8 << 0));
7662c8bd 4244 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
4fe5e611
ZY		 4245 /* update cursor SR watermark */
4246 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
7662c8bd
SL		 4247}
4248
d210246a 4249static void i9xx_update_wm(struct drm_device *dev)
7662c8bd
SL		 4250{
4251 struct drm_i915_private *dev_priv = dev->dev_private;
d210246a 4252 const struct intel_watermark_params *wm_info;
dff33cfc
JB		 4253 uint32_t fwater_lo;
4254 uint32_t fwater_hi;
d210246a
CW		 4255 int cwm, srwm = 1;
4256 int fifo_size;
dff33cfc 4257 int planea_wm, planeb_wm;
d210246a 4258 struct drm_crtc *crtc, *enabled = NULL;
7662c8bd 4259
72557b4f 4260 if (IS_I945GM(dev))
d210246a 4261 wm_info = &i945_wm_info;
a6c45cf0 4262 else if (!IS_GEN2(dev))
d210246a 4263 wm_info = &i915_wm_info;
7662c8bd 4264 else
d210246a
CW		 4265 wm_info = &i855_wm_info;
4266
4267 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
4268 crtc = intel_get_crtc_for_plane(dev, 0);
4269 if (crtc->enabled && crtc->fb) {
4270 planea_wm = intel_calculate_wm(crtc->mode.clock,
4271 wm_info, fifo_size,
4272 crtc->fb->bits_per_pixel / 8,
4273 latency_ns);
4274 enabled = crtc;
4275 } else
4276 planea_wm = fifo_size - wm_info->guard_size;
4277
4278 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
4279 crtc = intel_get_crtc_for_plane(dev, 1);
4280 if (crtc->enabled && crtc->fb) {
4281 planeb_wm = intel_calculate_wm(crtc->mode.clock,
4282 wm_info, fifo_size,
4283 crtc->fb->bits_per_pixel / 8,
4284 latency_ns);
4285 if (enabled == NULL)
4286 enabled = crtc;
4287 else
4288 enabled = NULL;
4289 } else
4290 planeb_wm = fifo_size - wm_info->guard_size;
7662c8bd 4291
28c97730 4292 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
7662c8bd
SL		 4293
4294 /*
4295 * Overlay gets an aggressive default since video jitter is bad.
4296 */
4297 cwm = 2;
4298
18b2190c
AL		 4299 /* Play safe and disable self-refresh before adjusting watermarks. */
4300 if (IS_I945G(dev) || IS_I945GM(dev))
4301 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
4302 else if (IS_I915GM(dev))
4303 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
4304
dff33cfc 4305 /* Calc sr entries for one plane configs */
d210246a 4306 if (HAS_FW_BLC(dev) && enabled) {
dff33cfc 4307 /* self-refresh has much higher latency */
69e302a9 4308 static const int sr_latency_ns = 6000;
d210246a
CW		 4309 int clock = enabled->mode.clock;
4310 int htotal = enabled->mode.htotal;
4311 int hdisplay = enabled->mode.hdisplay;
4312 int pixel_size = enabled->fb->bits_per_pixel / 8;
4313 unsigned long line_time_us;
4314 int entries;
dff33cfc 4315
d210246a 4316 line_time_us = (htotal * 1000) / clock;
dff33cfc
JB		 4317
4318 /* Use ns/us then divide to preserve precision */
d210246a
CW		 4319 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4320 pixel_size * hdisplay;
4321 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
4322 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
4323 srwm = wm_info->fifo_size - entries;
dff33cfc
JB		 4324 if (srwm < 0)
4325 srwm = 1;
ee980b80
LP		 4326
4327 if (IS_I945G(dev) || IS_I945GM(dev))
18b2190c
AL		 4328 I915_WRITE(FW_BLC_SELF,
4329 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
4330 else if (IS_I915GM(dev))
ee980b80 4331 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
7662c8bd
SL		 4332 }
4333
28c97730 4334 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
5eddb70b 4335 planea_wm, planeb_wm, cwm, srwm);
7662c8bd 4336
dff33cfc
JB		 4337 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
4338 fwater_hi = (cwm & 0x1f);
4339
4340 /* Set request length to 8 cachelines per fetch */
4341 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
4342 fwater_hi = fwater_hi | (1 << 8);
7662c8bd
SL		 4343
4344 I915_WRITE(FW_BLC, fwater_lo);
4345 I915_WRITE(FW_BLC2, fwater_hi);
18b2190c 4346
d210246a
CW		 4347 if (HAS_FW_BLC(dev)) {
4348 if (enabled) {
4349 if (IS_I945G(dev) || IS_I945GM(dev))
4350 I915_WRITE(FW_BLC_SELF,
4351 FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
4352 else if (IS_I915GM(dev))
4353 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
4354 DRM_DEBUG_KMS("memory self refresh enabled\n");
4355 } else
4356 DRM_DEBUG_KMS("memory self refresh disabled\n");
4357 }
7662c8bd
SL		 4358}
4359
d210246a 4360static void i830_update_wm(struct drm_device *dev)
7662c8bd
SL		 4361{
4362 struct drm_i915_private *dev_priv = dev->dev_private;
d210246a
CW		 4363 struct drm_crtc *crtc;
4364 uint32_t fwater_lo;
dff33cfc 4365 int planea_wm;
7662c8bd 4366
d210246a
CW		 4367 crtc = single_enabled_crtc(dev);
4368 if (crtc == NULL)
4369 return;
7662c8bd 4370
d210246a
CW		 4371 planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info,
4372 dev_priv->display.get_fifo_size(dev, 0),
4373 crtc->fb->bits_per_pixel / 8,
4374 latency_ns);
4375 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
f3601326
JB		 4376 fwater_lo |= (3<<8) | planea_wm;
4377
28c97730 4378 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
7662c8bd
SL		 4379
4380 I915_WRITE(FW_BLC, fwater_lo);
4381}
4382
7f8a8569 4383#define ILK_LP0_PLANE_LATENCY 700
c936f44d 4384#define ILK_LP0_CURSOR_LATENCY 1300
7f8a8569 4385
1398261a
YL		 4386/*
4387 * Check the wm result.
4388 *
4389 * If any calculated watermark values is larger than the maximum value that
4390 * can be programmed into the associated watermark register, that watermark
4391 * must be disabled.
1398261a 4392 */
b79d4990
JB		 4393static bool ironlake_check_srwm(struct drm_device *dev, int level,
4394 int fbc_wm, int display_wm, int cursor_wm,
4395 const struct intel_watermark_params *display,
4396 const struct intel_watermark_params *cursor)
1398261a
YL		 4397{
4398 struct drm_i915_private *dev_priv = dev->dev_private;
4399
4400 DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
4401 " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
4402
4403 if (fbc_wm > SNB_FBC_MAX_SRWM) {
4404 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
b79d4990 4405 fbc_wm, SNB_FBC_MAX_SRWM, level);
1398261a
YL		 4406
4407 /* fbc has it's own way to disable FBC WM */
4408 I915_WRITE(DISP_ARB_CTL,
4409 I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
4410 return false;
4411 }
4412
b79d4990 4413 if (display_wm > display->max_wm) {
1398261a 4414 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
b79d4990 4415 display_wm, SNB_DISPLAY_MAX_SRWM, level);
1398261a
YL		 4416 return false;
4417 }
4418
b79d4990 4419 if (cursor_wm > cursor->max_wm) {
1398261a 4420 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
b79d4990 4421 cursor_wm, SNB_CURSOR_MAX_SRWM, level);
1398261a
YL		 4422 return false;
4423 }
4424
4425 if (!(fbc_wm || display_wm || cursor_wm)) {
4426 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
4427 return false;
4428 }
4429
4430 return true;
4431}
4432
4433/*
4434 * Compute watermark values of WM[1-3],
4435 */
d210246a
CW		 4436static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
4437 int latency_ns,
b79d4990
JB		 4438 const struct intel_watermark_params *display,
4439 const struct intel_watermark_params *cursor,
4440 int *fbc_wm, int *display_wm, int *cursor_wm)
1398261a 4441{
d210246a 4442 struct drm_crtc *crtc;
1398261a 4443 unsigned long line_time_us;
d210246a 4444 int hdisplay, htotal, pixel_size, clock;
b79d4990 4445 int line_count, line_size;
1398261a
YL		 4446 int small, large;
4447 int entries;
1398261a
YL		 4448
4449 if (!latency_ns) {
4450 *fbc_wm = *display_wm = *cursor_wm = 0;
4451 return false;
4452 }
4453
d210246a
CW		 4454 crtc = intel_get_crtc_for_plane(dev, plane);
4455 hdisplay = crtc->mode.hdisplay;
4456 htotal = crtc->mode.htotal;
4457 clock = crtc->mode.clock;
4458 pixel_size = crtc->fb->bits_per_pixel / 8;
4459
1398261a
YL		 4460 line_time_us = (htotal * 1000) / clock;
4461 line_count = (latency_ns / line_time_us + 1000) / 1000;
4462 line_size = hdisplay * pixel_size;
4463
4464 /* Use the minimum of the small and large buffer method for primary */
4465 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4466 large = line_count * line_size;
4467
b79d4990
JB		 4468 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4469 *display_wm = entries + display->guard_size;
1398261a
YL		 4470
4471 /*
b79d4990 4472 * Spec says:
1398261a
YL		 4473 * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
4474 */
4475 *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
4476
4477 /* calculate the self-refresh watermark for display cursor */
4478 entries = line_count * pixel_size * 64;
b79d4990
JB		 4479 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4480 *cursor_wm = entries + cursor->guard_size;
1398261a 4481
b79d4990
JB		 4482 return ironlake_check_srwm(dev, level,
4483 *fbc_wm, *display_wm, *cursor_wm,
4484 display, cursor);
4485}
4486
d210246a 4487static void ironlake_update_wm(struct drm_device *dev)
b79d4990
JB		 4488{
4489 struct drm_i915_private *dev_priv = dev->dev_private;
d210246a
CW		 4490 int fbc_wm, plane_wm, cursor_wm;
4491 unsigned int enabled;
b79d4990
JB		 4492
4493 enabled = 0;
9f405100
CW		 4494 if (g4x_compute_wm0(dev, 0,
4495 &ironlake_display_wm_info,
4496 ILK_LP0_PLANE_LATENCY,
4497 &ironlake_cursor_wm_info,
4498 ILK_LP0_CURSOR_LATENCY,
4499 &plane_wm, &cursor_wm)) {
b79d4990
JB		 4500 I915_WRITE(WM0_PIPEA_ILK,
4501 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4502 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4503 " plane %d, " "cursor: %d\n",
4504 plane_wm, cursor_wm);
d210246a 4505 enabled |= 1;
b79d4990
JB		 4506 }
4507
9f405100
CW		 4508 if (g4x_compute_wm0(dev, 1,
4509 &ironlake_display_wm_info,
4510 ILK_LP0_PLANE_LATENCY,
4511 &ironlake_cursor_wm_info,
4512 ILK_LP0_CURSOR_LATENCY,
4513 &plane_wm, &cursor_wm)) {
b79d4990
JB		 4514 I915_WRITE(WM0_PIPEB_ILK,
4515 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4516 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4517 " plane %d, cursor: %d\n",
4518 plane_wm, cursor_wm);
d210246a 4519 enabled |= 2;
b79d4990
JB		 4520 }
4521
4522 /*
4523 * Calculate and update the self-refresh watermark only when one
4524 * display plane is used.
4525 */
4526 I915_WRITE(WM3_LP_ILK, 0);
4527 I915_WRITE(WM2_LP_ILK, 0);
4528 I915_WRITE(WM1_LP_ILK, 0);
4529
d210246a 4530 if (!single_plane_enabled(enabled))
b79d4990 4531 return;
d210246a 4532 enabled = ffs(enabled) - 1;
b79d4990
JB		 4533
4534 /* WM1 */
d210246a
CW		 4535 if (!ironlake_compute_srwm(dev, 1, enabled,
4536 ILK_READ_WM1_LATENCY() * 500,
b79d4990
JB		 4537 &ironlake_display_srwm_info,
4538 &ironlake_cursor_srwm_info,
4539 &fbc_wm, &plane_wm, &cursor_wm))
4540 return;
4541
4542 I915_WRITE(WM1_LP_ILK,
4543 WM1_LP_SR_EN |
4544 (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4545 (fbc_wm << WM1_LP_FBC_SHIFT) |
4546 (plane_wm << WM1_LP_SR_SHIFT) |
4547 cursor_wm);
4548
4549 /* WM2 */
d210246a
CW		 4550 if (!ironlake_compute_srwm(dev, 2, enabled,
4551 ILK_READ_WM2_LATENCY() * 500,
b79d4990
JB		 4552 &ironlake_display_srwm_info,
4553 &ironlake_cursor_srwm_info,
4554 &fbc_wm, &plane_wm, &cursor_wm))
4555 return;
4556
4557 I915_WRITE(WM2_LP_ILK,
4558 WM2_LP_EN |
4559 (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4560 (fbc_wm << WM1_LP_FBC_SHIFT) |
4561 (plane_wm << WM1_LP_SR_SHIFT) |
4562 cursor_wm);
4563
4564 /*
4565 * WM3 is unsupported on ILK, probably because we don't have latency
4566 * data for that power state
4567 */
1398261a
YL		 4568}
4569
b840d907 4570void sandybridge_update_wm(struct drm_device *dev)
1398261a
YL		 4571{
4572 struct drm_i915_private *dev_priv = dev->dev_private;
a0fa62d3 4573 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
47842649 4574 u32 val;
d210246a
CW		 4575 int fbc_wm, plane_wm, cursor_wm;
4576 unsigned int enabled;
1398261a
YL		 4577
4578 enabled = 0;
9f405100
CW		 4579 if (g4x_compute_wm0(dev, 0,
4580 &sandybridge_display_wm_info, latency,
4581 &sandybridge_cursor_wm_info, latency,
4582 &plane_wm, &cursor_wm)) {
47842649
JB		 4583 val = I915_READ(WM0_PIPEA_ILK);
4584 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
4585 I915_WRITE(WM0_PIPEA_ILK, val |
4586 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1398261a
YL		 4587 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4588 " plane %d, " "cursor: %d\n",
4589 plane_wm, cursor_wm);
d210246a 4590 enabled |= 1;
1398261a
YL		 4591 }
4592
9f405100
CW		 4593 if (g4x_compute_wm0(dev, 1,
4594 &sandybridge_display_wm_info, latency,
4595 &sandybridge_cursor_wm_info, latency,
4596 &plane_wm, &cursor_wm)) {
47842649
JB		 4597 val = I915_READ(WM0_PIPEB_ILK);
4598 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
4599 I915_WRITE(WM0_PIPEB_ILK, val |
4600 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1398261a
YL		 4601 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4602 " plane %d, cursor: %d\n",
4603 plane_wm, cursor_wm);
d210246a 4604 enabled |= 2;
1398261a
YL		 4605 }
4606
d6c892df
JB		 4607 /* IVB has 3 pipes */
4608 if (IS_IVYBRIDGE(dev) &&
4609 g4x_compute_wm0(dev, 2,
4610 &sandybridge_display_wm_info, latency,
4611 &sandybridge_cursor_wm_info, latency,
4612 &plane_wm, &cursor_wm)) {
47842649
JB		 4613 val = I915_READ(WM0_PIPEC_IVB);
4614 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
4615 I915_WRITE(WM0_PIPEC_IVB, val |
4616 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
d6c892df
JB		 4617 DRM_DEBUG_KMS("FIFO watermarks For pipe C -"
4618 " plane %d, cursor: %d\n",
4619 plane_wm, cursor_wm);
4620 enabled |= 3;
4621 }
4622
1398261a
YL		 4623 /*
4624 * Calculate and update the self-refresh watermark only when one
4625 * display plane is used.
4626 *
4627 * SNB support 3 levels of watermark.
4628 *
4629 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
4630 * and disabled in the descending order
4631 *
4632 */
4633 I915_WRITE(WM3_LP_ILK, 0);
4634 I915_WRITE(WM2_LP_ILK, 0);
4635 I915_WRITE(WM1_LP_ILK, 0);
4636
b840d907
JB		 4637 if (!single_plane_enabled(enabled) ||
4638 dev_priv->sprite_scaling_enabled)
1398261a 4639 return;
d210246a 4640 enabled = ffs(enabled) - 1;
1398261a
YL		 4641
4642 /* WM1 */
d210246a
CW		 4643 if (!ironlake_compute_srwm(dev, 1, enabled,
4644 SNB_READ_WM1_LATENCY() * 500,
b79d4990
JB		 4645 &sandybridge_display_srwm_info,
4646 &sandybridge_cursor_srwm_info,
4647 &fbc_wm, &plane_wm, &cursor_wm))
1398261a
YL		 4648 return;
4649
4650 I915_WRITE(WM1_LP_ILK,
4651 WM1_LP_SR_EN |
4652 (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4653 (fbc_wm << WM1_LP_FBC_SHIFT) |
4654 (plane_wm << WM1_LP_SR_SHIFT) |
4655 cursor_wm);
4656
4657 /* WM2 */
d210246a
CW		 4658 if (!ironlake_compute_srwm(dev, 2, enabled,
4659 SNB_READ_WM2_LATENCY() * 500,
b79d4990
JB		 4660 &sandybridge_display_srwm_info,
4661 &sandybridge_cursor_srwm_info,
4662 &fbc_wm, &plane_wm, &cursor_wm))
1398261a
YL		 4663 return;
4664
4665 I915_WRITE(WM2_LP_ILK,
4666 WM2_LP_EN |
4667 (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4668 (fbc_wm << WM1_LP_FBC_SHIFT) |
4669 (plane_wm << WM1_LP_SR_SHIFT) |
4670 cursor_wm);
4671
4672 /* WM3 */
d210246a
CW		 4673 if (!ironlake_compute_srwm(dev, 3, enabled,
4674 SNB_READ_WM3_LATENCY() * 500,
b79d4990
JB		 4675 &sandybridge_display_srwm_info,
4676 &sandybridge_cursor_srwm_info,
4677 &fbc_wm, &plane_wm, &cursor_wm))
1398261a
YL		 4678 return;
4679
4680 I915_WRITE(WM3_LP_ILK,
4681 WM3_LP_EN |
4682 (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4683 (fbc_wm << WM1_LP_FBC_SHIFT) |
4684 (plane_wm << WM1_LP_SR_SHIFT) |
4685 cursor_wm);
4686}
4687
b840d907
JB		 4688static bool
4689sandybridge_compute_sprite_wm(struct drm_device *dev, int plane,
4690 uint32_t sprite_width, int pixel_size,
4691 const struct intel_watermark_params *display,
4692 int display_latency_ns, int *sprite_wm)
4693{
4694 struct drm_crtc *crtc;
4695 int clock;
4696 int entries, tlb_miss;
4697
4698 crtc = intel_get_crtc_for_plane(dev, plane);
4699 if (crtc->fb == NULL || !crtc->enabled) {
4700 *sprite_wm = display->guard_size;
4701 return false;
4702 }
4703
4704 clock = crtc->mode.clock;
4705
4706 /* Use the small buffer method to calculate the sprite watermark */
4707 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
4708 tlb_miss = display->fifo_size*display->cacheline_size -
4709 sprite_width * 8;
4710 if (tlb_miss > 0)
4711 entries += tlb_miss;
4712 entries = DIV_ROUND_UP(entries, display->cacheline_size);
4713 *sprite_wm = entries + display->guard_size;
4714 if (*sprite_wm > (int)display->max_wm)
4715 *sprite_wm = display->max_wm;
4716
4717 return true;
4718}
4719
4720static bool
4721sandybridge_compute_sprite_srwm(struct drm_device *dev, int plane,
4722 uint32_t sprite_width, int pixel_size,
4723 const struct intel_watermark_params *display,
4724 int latency_ns, int *sprite_wm)
4725{
4726 struct drm_crtc *crtc;
4727 unsigned long line_time_us;
4728 int clock;
4729 int line_count, line_size;
4730 int small, large;
4731 int entries;
4732
4733 if (!latency_ns) {
4734 *sprite_wm = 0;
4735 return false;
4736 }
4737
4738 crtc = intel_get_crtc_for_plane(dev, plane);
4739 clock = crtc->mode.clock;
4740
4741 line_time_us = (sprite_width * 1000) / clock;
4742 line_count = (latency_ns / line_time_us + 1000) / 1000;
4743 line_size = sprite_width * pixel_size;
4744
4745 /* Use the minimum of the small and large buffer method for primary */
4746 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4747 large = line_count * line_size;
4748
4749 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4750 *sprite_wm = entries + display->guard_size;
4751
4752 return *sprite_wm > 0x3ff ? false : true;
4753}
4754
4755static void sandybridge_update_sprite_wm(struct drm_device *dev, int pipe,
4756 uint32_t sprite_width, int pixel_size)
4757{
4758 struct drm_i915_private *dev_priv = dev->dev_private;
4759 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
47842649 4760 u32 val;
b840d907
JB		 4761 int sprite_wm, reg;
4762 int ret;
4763
4764 switch (pipe) {
4765 case 0:
4766 reg = WM0_PIPEA_ILK;
4767 break;
4768 case 1:
4769 reg = WM0_PIPEB_ILK;
4770 break;
4771 case 2:
4772 reg = WM0_PIPEC_IVB;
4773 break;
4774 default:
4775 return; /* bad pipe */
4776 }
4777
4778 ret = sandybridge_compute_sprite_wm(dev, pipe, sprite_width, pixel_size,
4779 &sandybridge_display_wm_info,
4780 latency, &sprite_wm);
4781 if (!ret) {
4782 DRM_DEBUG_KMS("failed to compute sprite wm for pipe %d\n",
4783 pipe);
4784 return;
4785 }
4786
47842649
JB		 4787 val = I915_READ(reg);
4788 val &= ~WM0_PIPE_SPRITE_MASK;
4789 I915_WRITE(reg, val | (sprite_wm << WM0_PIPE_SPRITE_SHIFT));
b840d907
JB		 4790 DRM_DEBUG_KMS("sprite watermarks For pipe %d - %d\n", pipe, sprite_wm);
4791
4792
4793 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
4794 pixel_size,
4795 &sandybridge_display_srwm_info,
4796 SNB_READ_WM1_LATENCY() * 500,
4797 &sprite_wm);
4798 if (!ret) {
4799 DRM_DEBUG_KMS("failed to compute sprite lp1 wm on pipe %d\n",
4800 pipe);
4801 return;
4802 }
4803 I915_WRITE(WM1S_LP_ILK, sprite_wm);
4804
4805 /* Only IVB has two more LP watermarks for sprite */
4806 if (!IS_IVYBRIDGE(dev))
4807 return;
4808
4809 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
4810 pixel_size,
4811 &sandybridge_display_srwm_info,
4812 SNB_READ_WM2_LATENCY() * 500,
4813 &sprite_wm);
4814 if (!ret) {
4815 DRM_DEBUG_KMS("failed to compute sprite lp2 wm on pipe %d\n",
4816 pipe);
4817 return;
4818 }
4819 I915_WRITE(WM2S_LP_IVB, sprite_wm);
4820
4821 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
4822 pixel_size,
4823 &sandybridge_display_srwm_info,
4824 SNB_READ_WM3_LATENCY() * 500,
4825 &sprite_wm);
4826 if (!ret) {
4827 DRM_DEBUG_KMS("failed to compute sprite lp3 wm on pipe %d\n",
4828 pipe);
4829 return;
4830 }
4831 I915_WRITE(WM3S_LP_IVB, sprite_wm);
4832}
4833
7662c8bd
SL		 4834/**
4835 * intel_update_watermarks - update FIFO watermark values based on current modes
4836 *
4837 * Calculate watermark values for the various WM regs based on current mode
4838 * and plane configuration.
4839 *
4840 * There are several cases to deal with here:
4841 * - normal (i.e. non-self-refresh)
4842 * - self-refresh (SR) mode
4843 * - lines are large relative to FIFO size (buffer can hold up to 2)
4844 * - lines are small relative to FIFO size (buffer can hold more than 2
4845 * lines), so need to account for TLB latency
4846 *
4847 * The normal calculation is:
4848 * watermark = dotclock * bytes per pixel * latency
4849 * where latency is platform & configuration dependent (we assume pessimal
4850 * values here).
4851 *
4852 * The SR calculation is:
4853 * watermark = (trunc(latency/line time)+1) * surface width *
4854 * bytes per pixel
4855 * where
4856 * line time = htotal / dotclock
fa143215 4857 * surface width = hdisplay for normal plane and 64 for cursor
7662c8bd
SL		 4858 * and latency is assumed to be high, as above.
4859 *
4860 * The final value programmed to the register should always be rounded up,
4861 * and include an extra 2 entries to account for clock crossings.
4862 *
4863 * We don't use the sprite, so we can ignore that. And on Crestline we have
4864 * to set the non-SR watermarks to 8.
5eddb70b 4865 */
7662c8bd
SL		 4866static void intel_update_watermarks(struct drm_device *dev)
4867{
e70236a8 4868 struct drm_i915_private *dev_priv = dev->dev_private;
7662c8bd 4869
d210246a
CW		 4870 if (dev_priv->display.update_wm)
4871 dev_priv->display.update_wm(dev);
7662c8bd
SL		 4872}
4873
b840d907
JB		 4874void intel_update_sprite_watermarks(struct drm_device *dev, int pipe,
4875 uint32_t sprite_width, int pixel_size)
4876{
4877 struct drm_i915_private *dev_priv = dev->dev_private;
4878
4879 if (dev_priv->display.update_sprite_wm)
4880 dev_priv->display.update_sprite_wm(dev, pipe, sprite_width,
4881 pixel_size);
4882}
4883
a7615030
CW		 4884static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4885{
72bbe58c
KP		 4886 if (i915_panel_use_ssc >= 0)
4887 return i915_panel_use_ssc != 0;
4888 return dev_priv->lvds_use_ssc
435793df 4889 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 4890}
4891
5a354204
JB		 4892/**
4893 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
4894 * @crtc: CRTC structure
3b5c78a3 4895 * @mode: requested mode
5a354204
JB		 4896 *
4897 * A pipe may be connected to one or more outputs. Based on the depth of the
4898 * attached framebuffer, choose a good color depth to use on the pipe.
4899 *
4900 * If possible, match the pipe depth to the fb depth. In some cases, this
4901 * isn't ideal, because the connected output supports a lesser or restricted
4902 * set of depths. Resolve that here:
4903 * LVDS typically supports only 6bpc, so clamp down in that case
4904 * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
4905 * Displays may support a restricted set as well, check EDID and clamp as
4906 * appropriate.
3b5c78a3 4907 * DP may want to dither down to 6bpc to fit larger modes
5a354204
JB		 4908 *
4909 * RETURNS:
4910 * Dithering requirement (i.e. false if display bpc and pipe bpc match,
4911 * true if they don't match).
4912 */
4913static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
3b5c78a3
AJ		 4914 unsigned int *pipe_bpp,
4915 struct drm_display_mode *mode)
5a354204
JB		 4916{
4917 struct drm_device *dev = crtc->dev;
4918 struct drm_i915_private *dev_priv = dev->dev_private;
4919 struct drm_encoder *encoder;
4920 struct drm_connector *connector;
4921 unsigned int display_bpc = UINT_MAX, bpc;
4922
4923 /* Walk the encoders & connectors on this crtc, get min bpc */
4924 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
4925 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
4926
4927 if (encoder->crtc != crtc)
4928 continue;
4929
4930 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
4931 unsigned int lvds_bpc;
4932
4933 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
4934 LVDS_A3_POWER_UP)
4935 lvds_bpc = 8;
4936 else
4937 lvds_bpc = 6;
4938
4939 if (lvds_bpc < display_bpc) {
82820490 4940 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
5a354204
JB		 4941 display_bpc = lvds_bpc;
4942 }
4943 continue;
4944 }
4945
4946 if (intel_encoder->type == INTEL_OUTPUT_EDP) {
4947 /* Use VBT settings if we have an eDP panel */
4948 unsigned int edp_bpc = dev_priv->edp.bpp / 3;
4949
4950 if (edp_bpc < display_bpc) {
82820490 4951 DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc);
5a354204
JB		 4952 display_bpc = edp_bpc;
4953 }
4954 continue;
4955 }
4956
4957 /* Not one of the known troublemakers, check the EDID */
4958 list_for_each_entry(connector, &dev->mode_config.connector_list,
4959 head) {
4960 if (connector->encoder != encoder)
4961 continue;
4962
62ac41a6
JB		 4963 /* Don't use an invalid EDID bpc value */
4964 if (connector->display_info.bpc &&
4965 connector->display_info.bpc < display_bpc) {
82820490 4966 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
5a354204
JB		 4967 display_bpc = connector->display_info.bpc;
4968 }
4969 }
4970
4971 /*
4972 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
4973 * through, clamp it down. (Note: >12bpc will be caught below.)
4974 */
4975 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
4976 if (display_bpc > 8 && display_bpc < 12) {
82820490 4977 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
5a354204
JB		 4978 display_bpc = 12;
4979 } else {
82820490 4980 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
5a354204
JB		 4981 display_bpc = 8;
4982 }
4983 }
4984 }
4985
3b5c78a3
AJ		 4986 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4987 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
4988 display_bpc = 6;
4989 }
4990
5a354204
JB		 4991 /*
4992 * We could just drive the pipe at the highest bpc all the time and
4993 * enable dithering as needed, but that costs bandwidth. So choose
4994 * the minimum value that expresses the full color range of the fb but
4995 * also stays within the max display bpc discovered above.
4996 */
4997
4998 switch (crtc->fb->depth) {
4999 case 8:
5000 bpc = 8; /* since we go through a colormap */
5001 break;
5002 case 15:
5003 case 16:
5004 bpc = 6; /* min is 18bpp */
5005 break;
5006 case 24:
578393cd 5007 bpc = 8;
5a354204
JB		 5008 break;
5009 case 30:
578393cd 5010 bpc = 10;
5a354204
JB		 5011 break;
5012 case 48:
578393cd 5013 bpc = 12;
5a354204
JB		 5014 break;
5015 default:
5016 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
5017 bpc = min((unsigned int)8, display_bpc);
5018 break;
5019 }
5020
578393cd
KP		 5021 display_bpc = min(display_bpc, bpc);
5022
82820490
AJ		 5023 DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
5024 bpc, display_bpc);
5a354204 5025
578393cd 5026 *pipe_bpp = display_bpc * 3;
5a354204
JB		 5027
5028 return display_bpc != bpc;
5029}
5030
c65d77d8
JB		 5031static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
5032{
5033 struct drm_device *dev = crtc->dev;
5034 struct drm_i915_private *dev_priv = dev->dev_private;
5035 int refclk;
5036
5037 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5038 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5039 refclk = dev_priv->lvds_ssc_freq * 1000;
5040 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5041 refclk / 1000);
5042 } else if (!IS_GEN2(dev)) {
5043 refclk = 96000;
5044 } else {
5045 refclk = 48000;
5046 }
5047
5048 return refclk;
5049}
5050
5051static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
5052 intel_clock_t *clock)
5053{
5054 /* SDVO TV has fixed PLL values depend on its clock range,
5055 this mirrors vbios setting. */
5056 if (adjusted_mode->clock >= 100000
5057 && adjusted_mode->clock < 140500) {
5058 clock->p1 = 2;
5059 clock->p2 = 10;
5060 clock->n = 3;
5061 clock->m1 = 16;
5062 clock->m2 = 8;
5063 } else if (adjusted_mode->clock >= 140500
5064 && adjusted_mode->clock <= 200000) {
5065 clock->p1 = 1;
5066 clock->p2 = 10;
5067 clock->n = 6;
5068 clock->m1 = 12;
5069 clock->m2 = 8;
5070 }
5071}
5072
a7516a05
JB		 5073static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
5074 intel_clock_t *clock,
5075 intel_clock_t *reduced_clock)
5076{
5077 struct drm_device *dev = crtc->dev;
5078 struct drm_i915_private *dev_priv = dev->dev_private;
5079 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5080 int pipe = intel_crtc->pipe;
5081 u32 fp, fp2 = 0;
5082
5083 if (IS_PINEVIEW(dev)) {
5084 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
5085 if (reduced_clock)
5086 fp2 = (1 << reduced_clock->n) << 16 |
5087 reduced_clock->m1 << 8 | reduced_clock->m2;
5088 } else {
5089 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
5090 if (reduced_clock)
5091 fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
5092 reduced_clock->m2;
5093 }
5094
5095 I915_WRITE(FP0(pipe), fp);
5096
5097 intel_crtc->lowfreq_avail = false;
5098 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5099 reduced_clock && i915_powersave) {
5100 I915_WRITE(FP1(pipe), fp2);
5101 intel_crtc->lowfreq_avail = true;
5102 } else {
5103 I915_WRITE(FP1(pipe), fp);
5104 }
5105}
5106
f564048e
EA		 5107static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
5108 struct drm_display_mode *mode,
5109 struct drm_display_mode *adjusted_mode,
5110 int x, int y,
5111 struct drm_framebuffer *old_fb)
79e53945
JB		 5112{
5113 struct drm_device *dev = crtc->dev;
5114 struct drm_i915_private *dev_priv = dev->dev_private;
5115 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5116 int pipe = intel_crtc->pipe;
80824003 5117 int plane = intel_crtc->plane;
c751ce4f 5118 int refclk, num_connectors = 0;
652c393a 5119 intel_clock_t clock, reduced_clock;
0529a0d9 5120 u32 dpll, dspcntr, pipeconf, vsyncshift;
652c393a 5121 bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
a4fc5ed6 5122 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
79e53945 5123 struct drm_mode_config *mode_config = &dev->mode_config;
5eddb70b 5124 struct intel_encoder *encoder;
d4906093 5125 const intel_limit_t *limit;
5c3b82e2 5126 int ret;
fae14981 5127 u32 temp;
aa9b500d 5128 u32 lvds_sync = 0;
79e53945 5129
5eddb70b
CW		 5130 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5131 if (encoder->base.crtc != crtc)
79e53945
JB		 5132 continue;
5133
5eddb70b 5134 switch (encoder->type) {
79e53945
JB		 5135 case INTEL_OUTPUT_LVDS:
5136 is_lvds = true;
5137 break;
5138 case INTEL_OUTPUT_SDVO:
7d57382e 5139 case INTEL_OUTPUT_HDMI:
79e53945 5140 is_sdvo = true;
5eddb70b 5141 if (encoder->needs_tv_clock)
e2f0ba97 5142 is_tv = true;
79e53945
JB		 5143 break;
5144 case INTEL_OUTPUT_DVO:
5145 is_dvo = true;
5146 break;
5147 case INTEL_OUTPUT_TVOUT:
5148 is_tv = true;
5149 break;
5150 case INTEL_OUTPUT_ANALOG:
5151 is_crt = true;
5152 break;
a4fc5ed6
KP		 5153 case INTEL_OUTPUT_DISPLAYPORT:
5154 is_dp = true;
5155 break;
79e53945 5156 }
43565a06 5157
c751ce4f 5158 num_connectors++;
79e53945
JB		 5159 }
5160
c65d77d8 5161 refclk = i9xx_get_refclk(crtc, num_connectors);
79e53945 5162
d4906093
ML		 5163 /*
5164 * Returns a set of divisors for the desired target clock with the given
5165 * refclk, or FALSE. The returned values represent the clock equation:
5166 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5167 */
1b894b59 5168 limit = intel_limit(crtc, refclk);
cec2f356
SP		 5169 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5170 &clock);
79e53945
JB		 5171 if (!ok) {
5172 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 5173 return -EINVAL;
79e53945
JB		 5174 }
5175
cda4b7d3 5176 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 5177 intel_crtc_update_cursor(crtc, true);
cda4b7d3 5178
ddc9003c 5179 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 5180 /*
5181 * Ensure we match the reduced clock's P to the target clock.
5182 * If the clocks don't match, we can't switch the display clock
5183 * by using the FP0/FP1. In such case we will disable the LVDS
5184 * downclock feature.
5185 */
ddc9003c 5186 has_reduced_clock = limit->find_pll(limit, crtc,
5eddb70b
CW		 5187 dev_priv->lvds_downclock,
5188 refclk,
cec2f356 5189 &clock,
5eddb70b 5190 &reduced_clock);
652c393a 5191 }
c65d77d8
JB		 5192
5193 if (is_sdvo && is_tv)
5194 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
7026d4ac 5195
a7516a05
JB		 5196 i9xx_update_pll_dividers(crtc, &clock, has_reduced_clock ?
5197 &reduced_clock : NULL);
79e53945 5198
929c77fb 5199 dpll = DPLL_VGA_MODE_DIS;
2c07245f 5200
a6c45cf0 5201 if (!IS_GEN2(dev)) {
79e53945
JB		 5202 if (is_lvds)
5203 dpll |= DPLLB_MODE_LVDS;
5204 else
5205 dpll |= DPLLB_MODE_DAC_SERIAL;
5206 if (is_sdvo) {
6c9547ff
CW		 5207 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5208 if (pixel_multiplier > 1) {
5209 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
5210 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
6c9547ff 5211 }
79e53945 5212 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945 5213 }
929c77fb 5214 if (is_dp)
a4fc5ed6 5215 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945
JB		 5216
5217 /* compute bitmask from p1 value */
f2b115e6
AJ		 5218 if (IS_PINEVIEW(dev))
5219 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
2c07245f 5220 else {
2177832f 5221 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
652c393a
JB		 5222 if (IS_G4X(dev) && has_reduced_clock)
5223 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
2c07245f 5224 }
79e53945
JB		 5225 switch (clock.p2) {
5226 case 5:
5227 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5228 break;
5229 case 7:
5230 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5231 break;
5232 case 10:
5233 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5234 break;
5235 case 14:
5236 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5237 break;
5238 }
929c77fb 5239 if (INTEL_INFO(dev)->gen >= 4)
79e53945
JB		 5240 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
5241 } else {
5242 if (is_lvds) {
5243 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5244 } else {
5245 if (clock.p1 == 2)
5246 dpll |= PLL_P1_DIVIDE_BY_TWO;
5247 else
5248 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5249 if (clock.p2 == 4)
5250 dpll |= PLL_P2_DIVIDE_BY_4;
5251 }
5252 }
5253
43565a06
KH		 5254 if (is_sdvo && is_tv)
5255 dpll |= PLL_REF_INPUT_TVCLKINBC;
5256 else if (is_tv)
79e53945 5257 /* XXX: just matching BIOS for now */
43565a06 5258 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
79e53945 5259 dpll |= 3;
a7615030 5260 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 5261 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 5262 else
5263 dpll |= PLL_REF_INPUT_DREFCLK;
5264
5265 /* setup pipeconf */
5eddb70b 5266 pipeconf = I915_READ(PIPECONF(pipe));
79e53945
JB		 5267
5268 /* Set up the display plane register */
5269 dspcntr = DISPPLANE_GAMMA_ENABLE;
5270
929c77fb
EA		 5271 if (pipe == 0)
5272 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
5273 else
5274 dspcntr |= DISPPLANE_SEL_PIPE_B;
79e53945 5275
a6c45cf0 5276 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
79e53945
JB		 5277 /* Enable pixel doubling when the dot clock is > 90% of the (display)
5278 * core speed.
5279 *
5280 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
5281 * pipe == 0 check?
5282 */
e70236a8
JB		 5283 if (mode->clock >
5284 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
5eddb70b 5285 pipeconf |= PIPECONF_DOUBLE_WIDE;
79e53945 5286 else
5eddb70b 5287 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
79e53945
JB		 5288 }
5289
3b5c78a3
AJ		 5290 /* default to 8bpc */
5291 pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
5292 if (is_dp) {
5293 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
5294 pipeconf |= PIPECONF_BPP_6 |
5295 PIPECONF_DITHER_EN |
5296 PIPECONF_DITHER_TYPE_SP;
5297 }
5298 }
5299
929c77fb 5300 dpll |= DPLL_VCO_ENABLE;
8d86dc6a 5301
28c97730 5302 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
79e53945
JB		 5303 drm_mode_debug_printmodeline(mode);
5304
fae14981 5305 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
5eddb70b 5306
fae14981 5307 POSTING_READ(DPLL(pipe));
c713bb08 5308 udelay(150);
8db9d77b 5309
79e53945
JB		 5310 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5311 * This is an exception to the general rule that mode_set doesn't turn
5312 * things on.
5313 */
5314 if (is_lvds) {
fae14981 5315 temp = I915_READ(LVDS);
5eddb70b 5316 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
b3b095b3 5317 if (pipe == 1) {
929c77fb 5318 temp |= LVDS_PIPEB_SELECT;
b3b095b3 5319 } else {
929c77fb 5320 temp &= ~LVDS_PIPEB_SELECT;
b3b095b3 5321 }
a3e17eb8 5322 /* set the corresponsding LVDS_BORDER bit */
5eddb70b 5323 temp |= dev_priv->lvds_border_bits;
79e53945
JB		 5324 /* Set the B0-B3 data pairs corresponding to whether we're going to
5325 * set the DPLLs for dual-channel mode or not.
5326 */
5327 if (clock.p2 == 7)
5eddb70b 5328 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
79e53945 5329 else
5eddb70b 5330 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
79e53945
JB		 5331
5332 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5333 * appropriately here, but we need to look more thoroughly into how
5334 * panels behave in the two modes.
5335 */
929c77fb
EA		 5336 /* set the dithering flag on LVDS as needed */
5337 if (INTEL_INFO(dev)->gen >= 4) {
434ed097 5338 if (dev_priv->lvds_dither)
5eddb70b 5339 temp |= LVDS_ENABLE_DITHER;
434ed097 5340 else
5eddb70b 5341 temp &= ~LVDS_ENABLE_DITHER;
898822ce 5342 }
aa9b500d
BF		 5343 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5344 lvds_sync |= LVDS_HSYNC_POLARITY;
5345 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5346 lvds_sync |= LVDS_VSYNC_POLARITY;
5347 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
5348 != lvds_sync) {
5349 char flags[2] = "-+";
5350 DRM_INFO("Changing LVDS panel from "
5351 "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
5352 flags[!(temp & LVDS_HSYNC_POLARITY)],
5353 flags[!(temp & LVDS_VSYNC_POLARITY)],
5354 flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
5355 flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
5356 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5357 temp |= lvds_sync;
5358 }
fae14981 5359 I915_WRITE(LVDS, temp);
79e53945 5360 }
434ed097 5361
929c77fb 5362 if (is_dp) {
a4fc5ed6 5363 intel_dp_set_m_n(crtc, mode, adjusted_mode);
434ed097
JB		 5364 }
5365
fae14981 5366 I915_WRITE(DPLL(pipe), dpll);
5eddb70b 5367
c713bb08 5368 /* Wait for the clocks to stabilize. */
fae14981 5369 POSTING_READ(DPLL(pipe));
c713bb08 5370 udelay(150);
32f9d658 5371
c713bb08
EA		 5372 if (INTEL_INFO(dev)->gen >= 4) {
5373 temp = 0;
5374 if (is_sdvo) {
5375 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
5376 if (temp > 1)
5377 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5378 else
5379 temp = 0;
32f9d658 5380 }
c713bb08
EA		 5381 I915_WRITE(DPLL_MD(pipe), temp);
5382 } else {
5383 /* The pixel multiplier can only be updated once the
5384 * DPLL is enabled and the clocks are stable.
5385 *
5386 * So write it again.
5387 */
fae14981 5388 I915_WRITE(DPLL(pipe), dpll);
79e53945 5389 }
79e53945 5390
a7516a05
JB		 5391 if (HAS_PIPE_CXSR(dev)) {
5392 if (intel_crtc->lowfreq_avail) {
28c97730 5393 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
652c393a 5394 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
a7516a05 5395 } else {
28c97730 5396 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
652c393a
JB		 5397 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
5398 }
5399 }
5400
617cf884 5401 pipeconf &= ~PIPECONF_INTERLACE_MASK;
dbb02575
DV		 5402 if (!IS_GEN2(dev) &&
5403 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
734b4157
KH		 5404 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5405 /* the chip adds 2 halflines automatically */
734b4157 5406 adjusted_mode->crtc_vtotal -= 1;
734b4157 5407 adjusted_mode->crtc_vblank_end -= 1;
0529a0d9
DV		 5408 vsyncshift = adjusted_mode->crtc_hsync_start
5409 - adjusted_mode->crtc_htotal/2;
5410 } else {
617cf884 5411 pipeconf |= PIPECONF_PROGRESSIVE;
0529a0d9
DV		 5412 vsyncshift = 0;
5413 }
5414
5415 if (!IS_GEN3(dev))
5416 I915_WRITE(VSYNCSHIFT(pipe), vsyncshift);
734b4157 5417
5eddb70b
CW		 5418 I915_WRITE(HTOTAL(pipe),
5419 (adjusted_mode->crtc_hdisplay - 1) |
79e53945 5420 ((adjusted_mode->crtc_htotal - 1) << 16));
5eddb70b
CW		 5421 I915_WRITE(HBLANK(pipe),
5422 (adjusted_mode->crtc_hblank_start - 1) |
79e53945 5423 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5eddb70b
CW		 5424 I915_WRITE(HSYNC(pipe),
5425 (adjusted_mode->crtc_hsync_start - 1) |
79e53945 5426 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5eddb70b
CW		 5427
5428 I915_WRITE(VTOTAL(pipe),
5429 (adjusted_mode->crtc_vdisplay - 1) |
79e53945 5430 ((adjusted_mode->crtc_vtotal - 1) << 16));
5eddb70b
CW		 5431 I915_WRITE(VBLANK(pipe),
5432 (adjusted_mode->crtc_vblank_start - 1) |
79e53945 5433 ((adjusted_mode->crtc_vblank_end - 1) << 16));
5eddb70b
CW		 5434 I915_WRITE(VSYNC(pipe),
5435 (adjusted_mode->crtc_vsync_start - 1) |
79e53945 5436 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5eddb70b
CW		 5437
5438 /* pipesrc and dspsize control the size that is scaled from,
5439 * which should always be the user's requested size.
79e53945 5440 */
929c77fb
EA		 5441 I915_WRITE(DSPSIZE(plane),
5442 ((mode->vdisplay - 1) << 16) |
5443 (mode->hdisplay - 1));
5444 I915_WRITE(DSPPOS(plane), 0);
5eddb70b
CW		 5445 I915_WRITE(PIPESRC(pipe),
5446 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
2c07245f 5447
f564048e
EA		 5448 I915_WRITE(PIPECONF(pipe), pipeconf);
5449 POSTING_READ(PIPECONF(pipe));
929c77fb 5450 intel_enable_pipe(dev_priv, pipe, false);
f564048e
EA		 5451
5452 intel_wait_for_vblank(dev, pipe);
5453
f564048e
EA		 5454 I915_WRITE(DSPCNTR(plane), dspcntr);
5455 POSTING_READ(DSPCNTR(plane));
284d9529 5456 intel_enable_plane(dev_priv, plane, pipe);
f564048e
EA		 5457
5458 ret = intel_pipe_set_base(crtc, x, y, old_fb);
5459
5460 intel_update_watermarks(dev);
5461
f564048e
EA		 5462 return ret;
5463}
5464
9fb526db
KP		 5465/*
5466 * Initialize reference clocks when the driver loads
5467 */
5468void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 5469{
5470 struct drm_i915_private *dev_priv = dev->dev_private;
5471 struct drm_mode_config *mode_config = &dev->mode_config;
13d83a67 5472 struct intel_encoder *encoder;
13d83a67
JB		 5473 u32 temp;
5474 bool has_lvds = false;
199e5d79
KP		 5475 bool has_cpu_edp = false;
5476 bool has_pch_edp = false;
5477 bool has_panel = false;
99eb6a01
KP		 5478 bool has_ck505 = false;
5479 bool can_ssc = false;
13d83a67
JB		 5480
5481 /* We need to take the global config into account */
199e5d79
KP		 5482 list_for_each_entry(encoder, &mode_config->encoder_list,
5483 base.head) {
5484 switch (encoder->type) {
5485 case INTEL_OUTPUT_LVDS:
5486 has_panel = true;
5487 has_lvds = true;
5488 break;
5489 case INTEL_OUTPUT_EDP:
5490 has_panel = true;
5491 if (intel_encoder_is_pch_edp(&encoder->base))
5492 has_pch_edp = true;
5493 else
5494 has_cpu_edp = true;
5495 break;
13d83a67
JB		 5496 }
5497 }
5498
99eb6a01
KP		 5499 if (HAS_PCH_IBX(dev)) {
5500 has_ck505 = dev_priv->display_clock_mode;
5501 can_ssc = has_ck505;
5502 } else {
5503 has_ck505 = false;
5504 can_ssc = true;
5505 }
5506
5507 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
5508 has_panel, has_lvds, has_pch_edp, has_cpu_edp,
5509 has_ck505);
13d83a67
JB		 5510
5511 /* Ironlake: try to setup display ref clock before DPLL
5512 * enabling. This is only under driver's control after
5513 * PCH B stepping, previous chipset stepping should be
5514 * ignoring this setting.
5515 */
5516 temp = I915_READ(PCH_DREF_CONTROL);
5517 /* Always enable nonspread source */
5518 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 5519
99eb6a01
KP		 5520 if (has_ck505)
5521 temp |= DREF_NONSPREAD_CK505_ENABLE;
5522 else
5523 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 5524
199e5d79
KP		 5525 if (has_panel) {
5526 temp &= ~DREF_SSC_SOURCE_MASK;
5527 temp |= DREF_SSC_SOURCE_ENABLE;
13d83a67 5528
199e5d79 5529 /* SSC must be turned on before enabling the CPU output */
99eb6a01 5530 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5531 DRM_DEBUG_KMS("Using SSC on panel\n");
13d83a67 5532 temp |= DREF_SSC1_ENABLE;
13d83a67 5533 }
199e5d79
KP		 5534
5535 /* Get SSC going before enabling the outputs */
5536 I915_WRITE(PCH_DREF_CONTROL, temp);
5537 POSTING_READ(PCH_DREF_CONTROL);
5538 udelay(200);
5539
13d83a67
JB		 5540 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5541
5542 /* Enable CPU source on CPU attached eDP */
199e5d79 5543 if (has_cpu_edp) {
99eb6a01 5544 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5545 DRM_DEBUG_KMS("Using SSC on eDP\n");
13d83a67 5546 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
199e5d79 5547 }
13d83a67
JB		 5548 else
5549 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79
KP		 5550 } else
5551 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5552
5553 I915_WRITE(PCH_DREF_CONTROL, temp);
5554 POSTING_READ(PCH_DREF_CONTROL);
5555 udelay(200);
5556 } else {
5557 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5558
5559 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5560
5561 /* Turn off CPU output */
5562 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5563
5564 I915_WRITE(PCH_DREF_CONTROL, temp);
5565 POSTING_READ(PCH_DREF_CONTROL);
5566 udelay(200);
5567
5568 /* Turn off the SSC source */
5569 temp &= ~DREF_SSC_SOURCE_MASK;
5570 temp |= DREF_SSC_SOURCE_DISABLE;
5571
5572 /* Turn off SSC1 */
5573 temp &= ~ DREF_SSC1_ENABLE;
5574
13d83a67
JB		 5575 I915_WRITE(PCH_DREF_CONTROL, temp);
5576 POSTING_READ(PCH_DREF_CONTROL);
5577 udelay(200);
5578 }
5579}
5580
d9d444cb
JB		 5581static int ironlake_get_refclk(struct drm_crtc *crtc)
5582{
5583 struct drm_device *dev = crtc->dev;
5584 struct drm_i915_private *dev_priv = dev->dev_private;
5585 struct intel_encoder *encoder;
5586 struct drm_mode_config *mode_config = &dev->mode_config;
5587 struct intel_encoder *edp_encoder = NULL;
5588 int num_connectors = 0;
5589 bool is_lvds = false;
5590
5591 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5592 if (encoder->base.crtc != crtc)
5593 continue;
5594
5595 switch (encoder->type) {
5596 case INTEL_OUTPUT_LVDS:
5597 is_lvds = true;
5598 break;
5599 case INTEL_OUTPUT_EDP:
5600 edp_encoder = encoder;
5601 break;
5602 }
5603 num_connectors++;
5604 }
5605
5606 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5607 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5608 dev_priv->lvds_ssc_freq);
5609 return dev_priv->lvds_ssc_freq * 1000;
5610 }
5611
5612 return 120000;
5613}
5614
f564048e
EA		 5615static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5616 struct drm_display_mode *mode,
5617 struct drm_display_mode *adjusted_mode,
5618 int x, int y,
5619 struct drm_framebuffer *old_fb)
79e53945
JB		 5620{
5621 struct drm_device *dev = crtc->dev;
5622 struct drm_i915_private *dev_priv = dev->dev_private;
5623 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5624 int pipe = intel_crtc->pipe;
80824003 5625 int plane = intel_crtc->plane;
c751ce4f 5626 int refclk, num_connectors = 0;
652c393a 5627 intel_clock_t clock, reduced_clock;
5eddb70b 5628 u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
a07d6787 5629 bool ok, has_reduced_clock = false, is_sdvo = false;
a4fc5ed6 5630 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
8e647a27 5631 struct intel_encoder *has_edp_encoder = NULL;
79e53945 5632 struct drm_mode_config *mode_config = &dev->mode_config;
5eddb70b 5633 struct intel_encoder *encoder;
d4906093 5634 const intel_limit_t *limit;
5c3b82e2 5635 int ret;
2c07245f 5636 struct fdi_m_n m_n = {0};
fae14981 5637 u32 temp;
aa9b500d 5638 u32 lvds_sync = 0;
5a354204
JB		 5639 int target_clock, pixel_multiplier, lane, link_bw, factor;
5640 unsigned int pipe_bpp;
5641 bool dither;
79e53945 5642
5eddb70b
CW		 5643 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5644 if (encoder->base.crtc != crtc)
79e53945
JB		 5645 continue;
5646
5eddb70b 5647 switch (encoder->type) {
79e53945
JB		 5648 case INTEL_OUTPUT_LVDS:
5649 is_lvds = true;
5650 break;
5651 case INTEL_OUTPUT_SDVO:
7d57382e 5652 case INTEL_OUTPUT_HDMI:
79e53945 5653 is_sdvo = true;
5eddb70b 5654 if (encoder->needs_tv_clock)
e2f0ba97 5655 is_tv = true;
79e53945 5656 break;
79e53945
JB		 5657 case INTEL_OUTPUT_TVOUT:
5658 is_tv = true;
5659 break;
5660 case INTEL_OUTPUT_ANALOG:
5661 is_crt = true;
5662 break;
a4fc5ed6
KP		 5663 case INTEL_OUTPUT_DISPLAYPORT:
5664 is_dp = true;
5665 break;
32f9d658 5666 case INTEL_OUTPUT_EDP:
5eddb70b 5667 has_edp_encoder = encoder;
32f9d658 5668 break;
79e53945 5669 }
43565a06 5670
c751ce4f 5671 num_connectors++;
79e53945
JB		 5672 }
5673
d9d444cb 5674 refclk = ironlake_get_refclk(crtc);
79e53945 5675
d4906093
ML		 5676 /*
5677 * Returns a set of divisors for the desired target clock with the given
5678 * refclk, or FALSE. The returned values represent the clock equation:
5679 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5680 */
1b894b59 5681 limit = intel_limit(crtc, refclk);
cec2f356
SP		 5682 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5683 &clock);
79e53945
JB		 5684 if (!ok) {
5685 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 5686 return -EINVAL;
79e53945
JB		 5687 }
5688
cda4b7d3 5689 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 5690 intel_crtc_update_cursor(crtc, true);
cda4b7d3 5691
ddc9003c 5692 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 5693 /*
5694 * Ensure we match the reduced clock's P to the target clock.
5695 * If the clocks don't match, we can't switch the display clock
5696 * by using the FP0/FP1. In such case we will disable the LVDS
5697 * downclock feature.
5698 */
ddc9003c 5699 has_reduced_clock = limit->find_pll(limit, crtc,
5eddb70b
CW		 5700 dev_priv->lvds_downclock,
5701 refclk,
cec2f356 5702 &clock,
5eddb70b 5703 &reduced_clock);
652c393a 5704 }
7026d4ac
ZW		 5705 /* SDVO TV has fixed PLL values depend on its clock range,
5706 this mirrors vbios setting. */
5707 if (is_sdvo && is_tv) {
5708 if (adjusted_mode->clock >= 100000
5eddb70b 5709 && adjusted_mode->clock < 140500) {
7026d4ac
ZW		 5710 clock.p1 = 2;
5711 clock.p2 = 10;
5712 clock.n = 3;
5713 clock.m1 = 16;
5714 clock.m2 = 8;
5715 } else if (adjusted_mode->clock >= 140500
5eddb70b 5716 && adjusted_mode->clock <= 200000) {
7026d4ac
ZW		 5717 clock.p1 = 1;
5718 clock.p2 = 10;
5719 clock.n = 6;
5720 clock.m1 = 12;
5721 clock.m2 = 8;
5722 }
5723 }
5724
2c07245f 5725 /* FDI link */
8febb297
EA		 5726 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5727 lane = 0;
5728 /* CPU eDP doesn't require FDI link, so just set DP M/N
5729 according to current link config */
5730 if (has_edp_encoder &&
5731 !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5732 target_clock = mode->clock;
5733 intel_edp_link_config(has_edp_encoder,
5734 &lane, &link_bw);
5735 } else {
5736 /* [e]DP over FDI requires target mode clock
5737 instead of link clock */
5738 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
5eb08b69 5739 target_clock = mode->clock;
8febb297
EA		 5740 else
5741 target_clock = adjusted_mode->clock;
5742
5743 /* FDI is a binary signal running at ~2.7GHz, encoding
5744 * each output octet as 10 bits. The actual frequency
5745 * is stored as a divider into a 100MHz clock, and the
5746 * mode pixel clock is stored in units of 1KHz.
5747 * Hence the bw of each lane in terms of the mode signal
5748 * is:
5749 */
5750 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5751 }
58a27471 5752
8febb297
EA		 5753 /* determine panel color depth */
5754 temp = I915_READ(PIPECONF(pipe));
5755 temp &= ~PIPE_BPC_MASK;
3b5c78a3 5756 dither = intel_choose_pipe_bpp_dither(crtc, &pipe_bpp, mode);
5a354204
JB		 5757 switch (pipe_bpp) {
5758 case 18:
5759 temp |= PIPE_6BPC;
8febb297 5760 break;
5a354204
JB		 5761 case 24:
5762 temp |= PIPE_8BPC;
8febb297 5763 break;
5a354204
JB		 5764 case 30:
5765 temp |= PIPE_10BPC;
8febb297 5766 break;
5a354204
JB		 5767 case 36:
5768 temp |= PIPE_12BPC;
8febb297
EA		 5769 break;
5770 default:
62ac41a6
JB		 5771 WARN(1, "intel_choose_pipe_bpp returned invalid value %d\n",
5772 pipe_bpp);
5a354204
JB		 5773 temp |= PIPE_8BPC;
5774 pipe_bpp = 24;
5775 break;
8febb297 5776 }
77ffb597 5777
5a354204
JB		 5778 intel_crtc->bpp = pipe_bpp;
5779 I915_WRITE(PIPECONF(pipe), temp);
5780
8febb297
EA		 5781 if (!lane) {
5782 /*
5783 * Account for spread spectrum to avoid
5784 * oversubscribing the link. Max center spread
5785 * is 2.5%; use 5% for safety's sake.
5786 */
5a354204 5787 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
8febb297 5788 lane = bps / (link_bw * 8) + 1;
5eb08b69 5789 }
2c07245f 5790
8febb297
EA		 5791 intel_crtc->fdi_lanes = lane;
5792
5793 if (pixel_multiplier > 1)
5794 link_bw *= pixel_multiplier;
5a354204
JB		 5795 ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
5796 &m_n);
8febb297 5797
a07d6787
EA		 5798 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5799 if (has_reduced_clock)
5800 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5801 reduced_clock.m2;
79e53945 5802
c1858123 5803 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 5804 factor = 21;
5805 if (is_lvds) {
5806 if ((intel_panel_use_ssc(dev_priv) &&
5807 dev_priv->lvds_ssc_freq == 100) ||
5808 (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
5809 factor = 25;
5810 } else if (is_sdvo && is_tv)
5811 factor = 20;
c1858123 5812
cb0e0931 5813 if (clock.m < factor * clock.n)
8febb297 5814 fp |= FP_CB_TUNE;
2c07245f 5815
5eddb70b 5816 dpll = 0;
2c07245f 5817
a07d6787
EA		 5818 if (is_lvds)
5819 dpll |= DPLLB_MODE_LVDS;
5820 else
5821 dpll |= DPLLB_MODE_DAC_SERIAL;
5822 if (is_sdvo) {
5823 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5824 if (pixel_multiplier > 1) {
5825 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
79e53945 5826 }
a07d6787
EA		 5827 dpll |= DPLL_DVO_HIGH_SPEED;
5828 }
5829 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
5830 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945 5831
a07d6787
EA		 5832 /* compute bitmask from p1 value */
5833 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5834 /* also FPA1 */
5835 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5836
5837 switch (clock.p2) {
5838 case 5:
5839 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5840 break;
5841 case 7:
5842 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5843 break;
5844 case 10:
5845 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5846 break;
5847 case 14:
5848 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5849 break;
79e53945
JB		 5850 }
5851
43565a06
KH		 5852 if (is_sdvo && is_tv)
5853 dpll |= PLL_REF_INPUT_TVCLKINBC;
5854 else if (is_tv)
79e53945 5855 /* XXX: just matching BIOS for now */
43565a06 5856 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
79e53945 5857 dpll |= 3;
a7615030 5858 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 5859 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 5860 else
5861 dpll |= PLL_REF_INPUT_DREFCLK;
5862
5863 /* setup pipeconf */
5eddb70b 5864 pipeconf = I915_READ(PIPECONF(pipe));
79e53945
JB		 5865
5866 /* Set up the display plane register */
5867 dspcntr = DISPPLANE_GAMMA_ENABLE;
5868
f7cb34d4 5869 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
79e53945
JB		 5870 drm_mode_debug_printmodeline(mode);
5871
5c5313c8 5872 /* PCH eDP needs FDI, but CPU eDP does not */
4b645f14
JB		 5873 if (!intel_crtc->no_pll) {
5874 if (!has_edp_encoder ||
5875 intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5876 I915_WRITE(PCH_FP0(pipe), fp);
5877 I915_WRITE(PCH_DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
5878
5879 POSTING_READ(PCH_DPLL(pipe));
5880 udelay(150);
5881 }
5882 } else {
5883 if (dpll == (I915_READ(PCH_DPLL(0)) & 0x7fffffff) &&
5884 fp == I915_READ(PCH_FP0(0))) {
5885 intel_crtc->use_pll_a = true;
5886 DRM_DEBUG_KMS("using pipe a dpll\n");
5887 } else if (dpll == (I915_READ(PCH_DPLL(1)) & 0x7fffffff) &&
5888 fp == I915_READ(PCH_FP0(1))) {
5889 intel_crtc->use_pll_a = false;
5890 DRM_DEBUG_KMS("using pipe b dpll\n");
5891 } else {
5892 DRM_DEBUG_KMS("no matching PLL configuration for pipe 2\n");
5893 return -EINVAL;
5894 }
79e53945
JB		 5895 }
5896
5897 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5898 * This is an exception to the general rule that mode_set doesn't turn
5899 * things on.
5900 */
5901 if (is_lvds) {
fae14981 5902 temp = I915_READ(PCH_LVDS);
5eddb70b 5903 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
7885d205
JB		 5904 if (HAS_PCH_CPT(dev)) {
5905 temp &= ~PORT_TRANS_SEL_MASK;
4b645f14 5906 temp |= PORT_TRANS_SEL_CPT(pipe);
7885d205
JB		 5907 } else {
5908 if (pipe == 1)
5909 temp |= LVDS_PIPEB_SELECT;
5910 else
5911 temp &= ~LVDS_PIPEB_SELECT;
5912 }
4b645f14 5913
a3e17eb8 5914 /* set the corresponsding LVDS_BORDER bit */
5eddb70b 5915 temp |= dev_priv->lvds_border_bits;
79e53945
JB		 5916 /* Set the B0-B3 data pairs corresponding to whether we're going to
5917 * set the DPLLs for dual-channel mode or not.
5918 */
5919 if (clock.p2 == 7)
5eddb70b 5920 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
79e53945 5921 else
5eddb70b 5922 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
79e53945
JB		 5923
5924 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5925 * appropriately here, but we need to look more thoroughly into how
5926 * panels behave in the two modes.
5927 */
aa9b500d
BF		 5928 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5929 lvds_sync |= LVDS_HSYNC_POLARITY;
5930 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5931 lvds_sync |= LVDS_VSYNC_POLARITY;
5932 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
5933 != lvds_sync) {
5934 char flags[2] = "-+";
5935 DRM_INFO("Changing LVDS panel from "
5936 "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
5937 flags[!(temp & LVDS_HSYNC_POLARITY)],
5938 flags[!(temp & LVDS_VSYNC_POLARITY)],
5939 flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
5940 flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
5941 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5942 temp |= lvds_sync;
5943 }
fae14981 5944 I915_WRITE(PCH_LVDS, temp);
79e53945 5945 }
434ed097 5946
8febb297
EA		 5947 pipeconf &= ~PIPECONF_DITHER_EN;
5948 pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
5a354204 5949 if ((is_lvds && dev_priv->lvds_dither) || dither) {
8febb297 5950 pipeconf |= PIPECONF_DITHER_EN;
f74974c7 5951 pipeconf |= PIPECONF_DITHER_TYPE_SP;
434ed097 5952 }
5c5313c8 5953 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
a4fc5ed6 5954 intel_dp_set_m_n(crtc, mode, adjusted_mode);
8febb297 5955 } else {
8db9d77b 5956 /* For non-DP output, clear any trans DP clock recovery setting.*/
9db4a9c7
JB		 5957 I915_WRITE(TRANSDATA_M1(pipe), 0);
5958 I915_WRITE(TRANSDATA_N1(pipe), 0);
5959 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5960 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
8db9d77b 5961 }
79e53945 5962
4b645f14
JB		 5963 if (!intel_crtc->no_pll &&
5964 (!has_edp_encoder ||
5965 intel_encoder_is_pch_edp(&has_edp_encoder->base))) {
fae14981 5966 I915_WRITE(PCH_DPLL(pipe), dpll);
5eddb70b 5967
32f9d658 5968 /* Wait for the clocks to stabilize. */
fae14981 5969 POSTING_READ(PCH_DPLL(pipe));
32f9d658
ZW		 5970 udelay(150);
5971
8febb297
EA		 5972 /* The pixel multiplier can only be updated once the
5973 * DPLL is enabled and the clocks are stable.
5974 *
5975 * So write it again.
5976 */
fae14981 5977 I915_WRITE(PCH_DPLL(pipe), dpll);
79e53945 5978 }
79e53945 5979
5eddb70b 5980 intel_crtc->lowfreq_avail = false;
4b645f14
JB		 5981 if (!intel_crtc->no_pll) {
5982 if (is_lvds && has_reduced_clock && i915_powersave) {
5983 I915_WRITE(PCH_FP1(pipe), fp2);
5984 intel_crtc->lowfreq_avail = true;
5985 if (HAS_PIPE_CXSR(dev)) {
5986 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5987 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5988 }
5989 } else {
5990 I915_WRITE(PCH_FP1(pipe), fp);
5991 if (HAS_PIPE_CXSR(dev)) {
5992 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5993 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
5994 }
652c393a
JB		 5995 }
5996 }
5997
617cf884 5998 pipeconf &= ~PIPECONF_INTERLACE_MASK;
734b4157 5999 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5def474e 6000 pipeconf |= PIPECONF_INTERLACED_ILK;
734b4157 6001 /* the chip adds 2 halflines automatically */
734b4157 6002 adjusted_mode->crtc_vtotal -= 1;
734b4157 6003 adjusted_mode->crtc_vblank_end -= 1;
0529a0d9
DV		 6004 I915_WRITE(VSYNCSHIFT(pipe),
6005 adjusted_mode->crtc_hsync_start
6006 - adjusted_mode->crtc_htotal/2);
6007 } else {
617cf884 6008 pipeconf |= PIPECONF_PROGRESSIVE;
0529a0d9
DV		 6009 I915_WRITE(VSYNCSHIFT(pipe), 0);
6010 }
734b4157 6011
5eddb70b
CW		 6012 I915_WRITE(HTOTAL(pipe),
6013 (adjusted_mode->crtc_hdisplay - 1) |
79e53945 6014 ((adjusted_mode->crtc_htotal - 1) << 16));
5eddb70b
CW		 6015 I915_WRITE(HBLANK(pipe),
6016 (adjusted_mode->crtc_hblank_start - 1) |
79e53945 6017 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5eddb70b
CW		 6018 I915_WRITE(HSYNC(pipe),
6019 (adjusted_mode->crtc_hsync_start - 1) |
79e53945 6020 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5eddb70b
CW		 6021
6022 I915_WRITE(VTOTAL(pipe),
6023 (adjusted_mode->crtc_vdisplay - 1) |
79e53945 6024 ((adjusted_mode->crtc_vtotal - 1) << 16));
5eddb70b
CW		 6025 I915_WRITE(VBLANK(pipe),
6026 (adjusted_mode->crtc_vblank_start - 1) |
79e53945 6027 ((adjusted_mode->crtc_vblank_end - 1) << 16));
5eddb70b
CW		 6028 I915_WRITE(VSYNC(pipe),
6029 (adjusted_mode->crtc_vsync_start - 1) |
79e53945 6030 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5eddb70b 6031
8febb297
EA		 6032 /* pipesrc controls the size that is scaled from, which should
6033 * always be the user's requested size.
79e53945 6034 */
5eddb70b
CW		 6035 I915_WRITE(PIPESRC(pipe),
6036 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
2c07245f 6037
8febb297
EA		 6038 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
6039 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
6040 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
6041 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
2c07245f 6042
8febb297
EA		 6043 if (has_edp_encoder &&
6044 !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
6045 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
2c07245f
ZW		 6046 }
6047
5eddb70b
CW		 6048 I915_WRITE(PIPECONF(pipe), pipeconf);
6049 POSTING_READ(PIPECONF(pipe));
79e53945 6050
9d0498a2 6051 intel_wait_for_vblank(dev, pipe);
79e53945 6052
5eddb70b 6053 I915_WRITE(DSPCNTR(plane), dspcntr);
b24e7179 6054 POSTING_READ(DSPCNTR(plane));
79e53945 6055
5c3b82e2 6056 ret = intel_pipe_set_base(crtc, x, y, old_fb);
7662c8bd
SL		 6057
6058 intel_update_watermarks(dev);
6059
1f803ee5 6060 return ret;
79e53945
JB		 6061}
6062
f564048e
EA		 6063static int intel_crtc_mode_set(struct drm_crtc *crtc,
6064 struct drm_display_mode *mode,
6065 struct drm_display_mode *adjusted_mode,
6066 int x, int y,
6067 struct drm_framebuffer *old_fb)
6068{
6069 struct drm_device *dev = crtc->dev;
6070 struct drm_i915_private *dev_priv = dev->dev_private;
0b701d27
EA		 6071 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6072 int pipe = intel_crtc->pipe;
f564048e
EA		 6073 int ret;
6074
0b701d27 6075 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 6076
f564048e
EA		 6077 ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
6078 x, y, old_fb);
79e53945 6079 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 6080
d8e70a25
JB		 6081 if (ret)
6082 intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
6083 else
6084 intel_crtc->dpms_mode = DRM_MODE_DPMS_ON;
120eced9 6085
1f803ee5 6086 return ret;
79e53945
JB		 6087}
6088
3a9627f4
WF		 6089static bool intel_eld_uptodate(struct drm_connector *connector,
6090 int reg_eldv, uint32_t bits_eldv,
6091 int reg_elda, uint32_t bits_elda,
6092 int reg_edid)
6093{
6094 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6095 uint8_t *eld = connector->eld;
6096 uint32_t i;
6097
6098 i = I915_READ(reg_eldv);
6099 i &= bits_eldv;
6100
6101 if (!eld[0])
6102 return !i;
6103
6104 if (!i)
6105 return false;
6106
6107 i = I915_READ(reg_elda);
6108 i &= ~bits_elda;
6109 I915_WRITE(reg_elda, i);
6110
6111 for (i = 0; i < eld[2]; i++)
6112 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6113 return false;
6114
6115 return true;
6116}
6117
e0dac65e
WF		 6118static void g4x_write_eld(struct drm_connector *connector,
6119 struct drm_crtc *crtc)
6120{
6121 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6122 uint8_t *eld = connector->eld;
6123 uint32_t eldv;
6124 uint32_t len;
6125 uint32_t i;
6126
6127 i = I915_READ(G4X_AUD_VID_DID);
6128
6129 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6130 eldv = G4X_ELDV_DEVCL_DEVBLC;
6131 else
6132 eldv = G4X_ELDV_DEVCTG;
6133
3a9627f4
WF		 6134 if (intel_eld_uptodate(connector,
6135 G4X_AUD_CNTL_ST, eldv,
6136 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6137 G4X_HDMIW_HDMIEDID))
6138 return;
6139
e0dac65e
WF		 6140 i = I915_READ(G4X_AUD_CNTL_ST);
6141 i &= ~(eldv | G4X_ELD_ADDR);
6142 len = (i >> 9) & 0x1f; /* ELD buffer size */
6143 I915_WRITE(G4X_AUD_CNTL_ST, i);
6144
6145 if (!eld[0])
6146 return;
6147
6148 len = min_t(uint8_t, eld[2], len);
6149 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6150 for (i = 0; i < len; i++)
6151 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6152
6153 i = I915_READ(G4X_AUD_CNTL_ST);
6154 i |= eldv;
6155 I915_WRITE(G4X_AUD_CNTL_ST, i);
6156}
6157
6158static void ironlake_write_eld(struct drm_connector *connector,
6159 struct drm_crtc *crtc)
6160{
6161 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6162 uint8_t *eld = connector->eld;
6163 uint32_t eldv;
6164 uint32_t i;
6165 int len;
6166 int hdmiw_hdmiedid;
b6daa025 6167 int aud_config;
e0dac65e
WF		 6168 int aud_cntl_st;
6169 int aud_cntrl_st2;
6170
b3f33cbf 6171 if (HAS_PCH_IBX(connector->dev)) {
1202b4c6 6172 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID_A;
b6daa025 6173 aud_config = IBX_AUD_CONFIG_A;
1202b4c6
WF		 6174 aud_cntl_st = IBX_AUD_CNTL_ST_A;
6175 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
e0dac65e 6176 } else {
1202b4c6 6177 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID_A;
b6daa025 6178 aud_config = CPT_AUD_CONFIG_A;
1202b4c6
WF		 6179 aud_cntl_st = CPT_AUD_CNTL_ST_A;
6180 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
e0dac65e
WF		 6181 }
6182
6183 i = to_intel_crtc(crtc)->pipe;
6184 hdmiw_hdmiedid += i * 0x100;
6185 aud_cntl_st += i * 0x100;
b6daa025 6186 aud_config += i * 0x100;
e0dac65e
WF		 6187
6188 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(i));
6189
6190 i = I915_READ(aud_cntl_st);
6191 i = (i >> 29) & 0x3; /* DIP_Port_Select, 0x1 = PortB */
6192 if (!i) {
6193 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6194 /* operate blindly on all ports */
1202b4c6
WF		 6195 eldv = IBX_ELD_VALIDB;
6196 eldv |= IBX_ELD_VALIDB << 4;
6197 eldv |= IBX_ELD_VALIDB << 8;
e0dac65e
WF		 6198 } else {
6199 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
1202b4c6 6200 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
e0dac65e
WF		 6201 }
6202
3a9627f4
WF		 6203 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6204 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6205 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
b6daa025
WF		 6206 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6207 } else
6208 I915_WRITE(aud_config, 0);
e0dac65e 6209
3a9627f4
WF		 6210 if (intel_eld_uptodate(connector,
6211 aud_cntrl_st2, eldv,
6212 aud_cntl_st, IBX_ELD_ADDRESS,
6213 hdmiw_hdmiedid))
6214 return;
6215
e0dac65e
WF		 6216 i = I915_READ(aud_cntrl_st2);
6217 i &= ~eldv;
6218 I915_WRITE(aud_cntrl_st2, i);
6219
6220 if (!eld[0])
6221 return;
6222
e0dac65e 6223 i = I915_READ(aud_cntl_st);
1202b4c6 6224 i &= ~IBX_ELD_ADDRESS;
e0dac65e
WF		 6225 I915_WRITE(aud_cntl_st, i);
6226
6227 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6228 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6229 for (i = 0; i < len; i++)
6230 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6231
6232 i = I915_READ(aud_cntrl_st2);
6233 i |= eldv;
6234 I915_WRITE(aud_cntrl_st2, i);
6235}
6236
6237void intel_write_eld(struct drm_encoder *encoder,
6238 struct drm_display_mode *mode)
6239{
6240 struct drm_crtc *crtc = encoder->crtc;
6241 struct drm_connector *connector;
6242 struct drm_device *dev = encoder->dev;
6243 struct drm_i915_private *dev_priv = dev->dev_private;
6244
6245 connector = drm_select_eld(encoder, mode);
6246 if (!connector)
6247 return;
6248
6249 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6250 connector->base.id,
6251 drm_get_connector_name(connector),
6252 connector->encoder->base.id,
6253 drm_get_encoder_name(connector->encoder));
6254
6255 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6256
6257 if (dev_priv->display.write_eld)
6258 dev_priv->display.write_eld(connector, crtc);
6259}
6260
79e53945
JB		 6261/** Loads the palette/gamma unit for the CRTC with the prepared values */
6262void intel_crtc_load_lut(struct drm_crtc *crtc)
6263{
6264 struct drm_device *dev = crtc->dev;
6265 struct drm_i915_private *dev_priv = dev->dev_private;
6266 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9db4a9c7 6267 int palreg = PALETTE(intel_crtc->pipe);
79e53945
JB		 6268 int i;
6269
6270 /* The clocks have to be on to load the palette. */
6271 if (!crtc->enabled)
6272 return;
6273
f2b115e6 6274 /* use legacy palette for Ironlake */
bad720ff 6275 if (HAS_PCH_SPLIT(dev))
9db4a9c7 6276 palreg = LGC_PALETTE(intel_crtc->pipe);
2c07245f 6277
79e53945
JB		 6278 for (i = 0; i < 256; i++) {
6279 I915_WRITE(palreg + 4 * i,
6280 (intel_crtc->lut_r[i] << 16) |
6281 (intel_crtc->lut_g[i] << 8) |
6282 intel_crtc->lut_b[i]);
6283 }
6284}
6285
560b85bb
CW		 6286static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6287{
6288 struct drm_device *dev = crtc->dev;
6289 struct drm_i915_private *dev_priv = dev->dev_private;
6290 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6291 bool visible = base != 0;
6292 u32 cntl;
6293
6294 if (intel_crtc->cursor_visible == visible)
6295 return;
6296
9db4a9c7 6297 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 6298 if (visible) {
6299 /* On these chipsets we can only modify the base whilst
6300 * the cursor is disabled.
6301 */
9db4a9c7 6302 I915_WRITE(_CURABASE, base);
560b85bb
CW		 6303
6304 cntl &= ~(CURSOR_FORMAT_MASK);
6305 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6306 cntl |= CURSOR_ENABLE |
6307 CURSOR_GAMMA_ENABLE |
6308 CURSOR_FORMAT_ARGB;
6309 } else
6310 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 6311 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 6312
6313 intel_crtc->cursor_visible = visible;
6314}
6315
6316static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6317{
6318 struct drm_device *dev = crtc->dev;
6319 struct drm_i915_private *dev_priv = dev->dev_private;
6320 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6321 int pipe = intel_crtc->pipe;
6322 bool visible = base != 0;
6323
6324 if (intel_crtc->cursor_visible != visible) {
548f245b 6325 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 6326 if (base) {
6327 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6328 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6329 cntl |= pipe << 28; /* Connect to correct pipe */
6330 } else {
6331 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6332 cntl |= CURSOR_MODE_DISABLE;
6333 }
9db4a9c7 6334 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 6335
6336 intel_crtc->cursor_visible = visible;
6337 }
6338 /* and commit changes on next vblank */
9db4a9c7 6339 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 6340}
6341
65a21cd6
JB		 6342static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6343{
6344 struct drm_device *dev = crtc->dev;
6345 struct drm_i915_private *dev_priv = dev->dev_private;
6346 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6347 int pipe = intel_crtc->pipe;
6348 bool visible = base != 0;
6349
6350 if (intel_crtc->cursor_visible != visible) {
6351 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6352 if (base) {
6353 cntl &= ~CURSOR_MODE;
6354 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6355 } else {
6356 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6357 cntl |= CURSOR_MODE_DISABLE;
6358 }
6359 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6360
6361 intel_crtc->cursor_visible = visible;
6362 }
6363 /* and commit changes on next vblank */
6364 I915_WRITE(CURBASE_IVB(pipe), base);
6365}
6366
cda4b7d3 6367/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 6368static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6369 bool on)
cda4b7d3
CW		 6370{
6371 struct drm_device *dev = crtc->dev;
6372 struct drm_i915_private *dev_priv = dev->dev_private;
6373 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6374 int pipe = intel_crtc->pipe;
6375 int x = intel_crtc->cursor_x;
6376 int y = intel_crtc->cursor_y;
560b85bb 6377 u32 base, pos;
cda4b7d3
CW		 6378 bool visible;
6379
6380 pos = 0;
6381
6b383a7f 6382 if (on && crtc->enabled && crtc->fb) {
cda4b7d3
CW		 6383 base = intel_crtc->cursor_addr;
6384 if (x > (int) crtc->fb->width)
6385 base = 0;
6386
6387 if (y > (int) crtc->fb->height)
6388 base = 0;
6389 } else
6390 base = 0;
6391
6392 if (x < 0) {
6393 if (x + intel_crtc->cursor_width < 0)
6394 base = 0;
6395
6396 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6397 x = -x;
6398 }
6399 pos |= x << CURSOR_X_SHIFT;
6400
6401 if (y < 0) {
6402 if (y + intel_crtc->cursor_height < 0)
6403 base = 0;
6404
6405 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6406 y = -y;
6407 }
6408 pos |= y << CURSOR_Y_SHIFT;
6409
6410 visible = base != 0;
560b85bb 6411 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 6412 return;
6413
65a21cd6
JB		 6414 if (IS_IVYBRIDGE(dev)) {
6415 I915_WRITE(CURPOS_IVB(pipe), pos);
6416 ivb_update_cursor(crtc, base);
6417 } else {
6418 I915_WRITE(CURPOS(pipe), pos);
6419 if (IS_845G(dev) || IS_I865G(dev))
6420 i845_update_cursor(crtc, base);
6421 else
6422 i9xx_update_cursor(crtc, base);
6423 }
cda4b7d3
CW		 6424
6425 if (visible)
6426 intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);
6427}
6428
79e53945 6429static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 6430 struct drm_file *file,
79e53945
JB		 6431 uint32_t handle,
6432 uint32_t width, uint32_t height)
6433{
6434 struct drm_device *dev = crtc->dev;
6435 struct drm_i915_private *dev_priv = dev->dev_private;
6436 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 6437 struct drm_i915_gem_object *obj;
cda4b7d3 6438 uint32_t addr;
3f8bc370 6439 int ret;
79e53945 6440
28c97730 6441 DRM_DEBUG_KMS("\n");
79e53945
JB		 6442
6443 /* if we want to turn off the cursor ignore width and height */
6444 if (!handle) {
28c97730 6445 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 6446 addr = 0;
05394f39 6447 obj = NULL;
5004417d 6448 mutex_lock(&dev->struct_mutex);
3f8bc370 6449 goto finish;
79e53945
JB		 6450 }
6451
6452 /* Currently we only support 64x64 cursors */
6453 if (width != 64 || height != 64) {
6454 DRM_ERROR("we currently only support 64x64 cursors\n");
6455 return -EINVAL;
6456 }
6457
05394f39 6458 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 6459 if (&obj->base == NULL)
79e53945
JB		 6460 return -ENOENT;
6461
05394f39 6462 if (obj->base.size < width * height * 4) {
79e53945 6463 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 6464 ret = -ENOMEM;
6465 goto fail;
79e53945
JB		 6466 }
6467
71acb5eb 6468 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 6469 mutex_lock(&dev->struct_mutex);
b295d1b6 6470 if (!dev_priv->info->cursor_needs_physical) {
d9e86c0e
CW		 6471 if (obj->tiling_mode) {
6472 DRM_ERROR("cursor cannot be tiled\n");
6473 ret = -EINVAL;
6474 goto fail_locked;
6475 }
6476
2da3b9b9 6477 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
e7b526bb
CW		 6478 if (ret) {
6479 DRM_ERROR("failed to move cursor bo into the GTT\n");
2da3b9b9 6480 goto fail_locked;
e7b526bb
CW		 6481 }
6482
d9e86c0e
CW		 6483 ret = i915_gem_object_put_fence(obj);
6484 if (ret) {
2da3b9b9 6485 DRM_ERROR("failed to release fence for cursor");
d9e86c0e
CW		 6486 goto fail_unpin;
6487 }
6488
05394f39 6489 addr = obj->gtt_offset;
71acb5eb 6490 } else {
6eeefaf3 6491 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 6492 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 6493 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6494 align);
71acb5eb
DA		 6495 if (ret) {
6496 DRM_ERROR("failed to attach phys object\n");
7f9872e0 6497 goto fail_locked;
71acb5eb 6498 }
05394f39 6499 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 6500 }
6501
a6c45cf0 6502 if (IS_GEN2(dev))
14b60391
JB		 6503 I915_WRITE(CURSIZE, (height << 12) | width);
6504
3f8bc370 6505 finish:
3f8bc370 6506 if (intel_crtc->cursor_bo) {
b295d1b6 6507 if (dev_priv->info->cursor_needs_physical) {
05394f39 6508 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 6509 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6510 } else
6511 i915_gem_object_unpin(intel_crtc->cursor_bo);
05394f39 6512 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 6513 }
80824003 6514
7f9872e0 6515 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 6516
6517 intel_crtc->cursor_addr = addr;
05394f39 6518 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 6519 intel_crtc->cursor_width = width;
6520 intel_crtc->cursor_height = height;
6521
6b383a7f 6522 intel_crtc_update_cursor(crtc, true);
3f8bc370 6523
79e53945 6524 return 0;
e7b526bb 6525fail_unpin:
05394f39 6526 i915_gem_object_unpin(obj);
7f9872e0 6527fail_locked:
34b8686e 6528 mutex_unlock(&dev->struct_mutex);
bc9025bd 6529fail:
05394f39 6530 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 6531 return ret;
79e53945
JB		 6532}
6533
6534static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6535{
79e53945 6536 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6537
cda4b7d3
CW		 6538 intel_crtc->cursor_x = x;
6539 intel_crtc->cursor_y = y;
652c393a 6540
6b383a7f 6541 intel_crtc_update_cursor(crtc, true);
79e53945
JB		 6542
6543 return 0;
6544}
6545
6546/** Sets the color ramps on behalf of RandR */
6547void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6548 u16 blue, int regno)
6549{
6550 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6551
6552 intel_crtc->lut_r[regno] = red >> 8;
6553 intel_crtc->lut_g[regno] = green >> 8;
6554 intel_crtc->lut_b[regno] = blue >> 8;
6555}
6556
b8c00ac5
DA		 6557void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6558 u16 *blue, int regno)
6559{
6560 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6561
6562 *red = intel_crtc->lut_r[regno] << 8;
6563 *green = intel_crtc->lut_g[regno] << 8;
6564 *blue = intel_crtc->lut_b[regno] << 8;
6565}
6566
79e53945 6567static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 6568 u16 *blue, uint32_t start, uint32_t size)
79e53945 6569{
7203425a 6570 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 6571 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6572
7203425a 6573 for (i = start; i < end; i++) {
79e53945
JB		 6574 intel_crtc->lut_r[i] = red[i] >> 8;
6575 intel_crtc->lut_g[i] = green[i] >> 8;
6576 intel_crtc->lut_b[i] = blue[i] >> 8;
6577 }
6578
6579 intel_crtc_load_lut(crtc);
6580}
6581
6582/**
6583 * Get a pipe with a simple mode set on it for doing load-based monitor
6584 * detection.
6585 *
6586 * It will be up to the load-detect code to adjust the pipe as appropriate for
c751ce4f 6587 * its requirements. The pipe will be connected to no other encoders.
79e53945 6588 *
c751ce4f 6589 * Currently this code will only succeed if there is a pipe with no encoders
79e53945
JB		 6590 * configured for it. In the future, it could choose to temporarily disable
6591 * some outputs to free up a pipe for its use.
6592 *
6593 * \return crtc, or NULL if no pipes are available.
6594 */
6595
6596/* VESA 640x480x72Hz mode to set on the pipe */
6597static struct drm_display_mode load_detect_mode = {
6598 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6599 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6600};
6601
d2dff872
CW		 6602static struct drm_framebuffer *
6603intel_framebuffer_create(struct drm_device *dev,
308e5bcb 6604 struct drm_mode_fb_cmd2 *mode_cmd,
d2dff872
CW		 6605 struct drm_i915_gem_object *obj)
6606{
6607 struct intel_framebuffer *intel_fb;
6608 int ret;
6609
6610 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6611 if (!intel_fb) {
6612 drm_gem_object_unreference_unlocked(&obj->base);
6613 return ERR_PTR(-ENOMEM);
6614 }
6615
6616 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6617 if (ret) {
6618 drm_gem_object_unreference_unlocked(&obj->base);
6619 kfree(intel_fb);
6620 return ERR_PTR(ret);
6621 }
6622
6623 return &intel_fb->base;
6624}
6625
6626static u32
6627intel_framebuffer_pitch_for_width(int width, int bpp)
6628{
6629 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6630 return ALIGN(pitch, 64);
6631}
6632
6633static u32
6634intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6635{
6636 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6637 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6638}
6639
6640static struct drm_framebuffer *
6641intel_framebuffer_create_for_mode(struct drm_device *dev,
6642 struct drm_display_mode *mode,
6643 int depth, int bpp)
6644{
6645 struct drm_i915_gem_object *obj;
308e5bcb 6646 struct drm_mode_fb_cmd2 mode_cmd;
d2dff872
CW		 6647
6648 obj = i915_gem_alloc_object(dev,
6649 intel_framebuffer_size_for_mode(mode, bpp));
6650 if (obj == NULL)
6651 return ERR_PTR(-ENOMEM);
6652
6653 mode_cmd.width = mode->hdisplay;
6654 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 6655 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6656 bpp);
6657 mode_cmd.pixel_format = 0;
d2dff872
CW		 6658
6659 return intel_framebuffer_create(dev, &mode_cmd, obj);
6660}
6661
6662static struct drm_framebuffer *
6663mode_fits_in_fbdev(struct drm_device *dev,
6664 struct drm_display_mode *mode)
6665{
6666 struct drm_i915_private *dev_priv = dev->dev_private;
6667 struct drm_i915_gem_object *obj;
6668 struct drm_framebuffer *fb;
6669
6670 if (dev_priv->fbdev == NULL)
6671 return NULL;
6672
6673 obj = dev_priv->fbdev->ifb.obj;
6674 if (obj == NULL)
6675 return NULL;
6676
6677 fb = &dev_priv->fbdev->ifb.base;
01f2c773
VS		 6678 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6679 fb->bits_per_pixel))
d2dff872
CW		 6680 return NULL;
6681
01f2c773 6682 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 6683 return NULL;
6684
6685 return fb;
6686}
6687
7173188d
CW		 6688bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
6689 struct drm_connector *connector,
6690 struct drm_display_mode *mode,
8261b191 6691 struct intel_load_detect_pipe *old)
79e53945
JB		 6692{
6693 struct intel_crtc *intel_crtc;
6694 struct drm_crtc *possible_crtc;
4ef69c7a 6695 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 6696 struct drm_crtc *crtc = NULL;
6697 struct drm_device *dev = encoder->dev;
d2dff872 6698 struct drm_framebuffer *old_fb;
79e53945
JB		 6699 int i = -1;
6700
d2dff872
CW		 6701 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6702 connector->base.id, drm_get_connector_name(connector),
6703 encoder->base.id, drm_get_encoder_name(encoder));
6704
79e53945
JB		 6705 /*
6706 * Algorithm gets a little messy:
7a5e4805 6707 *
79e53945
JB		 6708 * - if the connector already has an assigned crtc, use it (but make
6709 * sure it's on first)
7a5e4805 6710 *
79e53945
JB		 6711 * - try to find the first unused crtc that can drive this connector,
6712 * and use that if we find one
79e53945
JB		 6713 */
6714
6715 /* See if we already have a CRTC for this connector */
6716 if (encoder->crtc) {
6717 crtc = encoder->crtc;
8261b191 6718
79e53945 6719 intel_crtc = to_intel_crtc(crtc);
8261b191
CW		 6720 old->dpms_mode = intel_crtc->dpms_mode;
6721 old->load_detect_temp = false;
6722
6723 /* Make sure the crtc and connector are running */
79e53945 6724 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
6492711d
CW		 6725 struct drm_encoder_helper_funcs *encoder_funcs;
6726 struct drm_crtc_helper_funcs *crtc_funcs;
6727
79e53945
JB		 6728 crtc_funcs = crtc->helper_private;
6729 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
6492711d
CW		 6730
6731 encoder_funcs = encoder->helper_private;
79e53945
JB		 6732 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
6733 }
8261b191 6734
7173188d 6735 return true;
79e53945
JB		 6736 }
6737
6738 /* Find an unused one (if possible) */
6739 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6740 i++;
6741 if (!(encoder->possible_crtcs & (1 << i)))
6742 continue;
6743 if (!possible_crtc->enabled) {
6744 crtc = possible_crtc;
6745 break;
6746 }
79e53945
JB		 6747 }
6748
6749 /*
6750 * If we didn't find an unused CRTC, don't use any.
6751 */
6752 if (!crtc) {
7173188d
CW		 6753 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6754 return false;
79e53945
JB		 6755 }
6756
6757 encoder->crtc = crtc;
c1c43977 6758 connector->encoder = encoder;
79e53945
JB		 6759
6760 intel_crtc = to_intel_crtc(crtc);
8261b191
CW		 6761 old->dpms_mode = intel_crtc->dpms_mode;
6762 old->load_detect_temp = true;
d2dff872 6763 old->release_fb = NULL;
79e53945 6764
6492711d
CW		 6765 if (!mode)
6766 mode = &load_detect_mode;
79e53945 6767
d2dff872
CW		 6768 old_fb = crtc->fb;
6769
6770 /* We need a framebuffer large enough to accommodate all accesses
6771 * that the plane may generate whilst we perform load detection.
6772 * We can not rely on the fbcon either being present (we get called
6773 * during its initialisation to detect all boot displays, or it may
6774 * not even exist) or that it is large enough to satisfy the
6775 * requested mode.
6776 */
6777 crtc->fb = mode_fits_in_fbdev(dev, mode);
6778 if (crtc->fb == NULL) {
6779 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6780 crtc->fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6781 old->release_fb = crtc->fb;
6782 } else
6783 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6784 if (IS_ERR(crtc->fb)) {
6785 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6786 crtc->fb = old_fb;
6787 return false;
79e53945 6788 }
79e53945 6789
d2dff872 6790 if (!drm_crtc_helper_set_mode(crtc, mode, 0, 0, old_fb)) {
6492711d 6791 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 6792 if (old->release_fb)
6793 old->release_fb->funcs->destroy(old->release_fb);
6794 crtc->fb = old_fb;
6492711d 6795 return false;
79e53945 6796 }
7173188d 6797
79e53945 6798 /* let the connector get through one full cycle before testing */
9d0498a2 6799 intel_wait_for_vblank(dev, intel_crtc->pipe);
79e53945 6800
7173188d 6801 return true;
79e53945
JB		 6802}
6803
c1c43977 6804void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
8261b191
CW		 6805 struct drm_connector *connector,
6806 struct intel_load_detect_pipe *old)
79e53945 6807{
4ef69c7a 6808 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 6809 struct drm_device *dev = encoder->dev;
6810 struct drm_crtc *crtc = encoder->crtc;
6811 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
6812 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
6813
d2dff872
CW		 6814 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6815 connector->base.id, drm_get_connector_name(connector),
6816 encoder->base.id, drm_get_encoder_name(encoder));
6817
8261b191 6818 if (old->load_detect_temp) {
c1c43977 6819 connector->encoder = NULL;
79e53945 6820 drm_helper_disable_unused_functions(dev);
d2dff872
CW		 6821
6822 if (old->release_fb)
6823 old->release_fb->funcs->destroy(old->release_fb);
6824
0622a53c 6825 return;
79e53945
JB		 6826 }
6827
c751ce4f 6828 /* Switch crtc and encoder back off if necessary */
0622a53c
CW		 6829 if (old->dpms_mode != DRM_MODE_DPMS_ON) {
6830 encoder_funcs->dpms(encoder, old->dpms_mode);
8261b191 6831 crtc_funcs->dpms(crtc, old->dpms_mode);
79e53945
JB		 6832 }
6833}
6834
6835/* Returns the clock of the currently programmed mode of the given pipe. */
6836static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6837{
6838 struct drm_i915_private *dev_priv = dev->dev_private;
6839 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6840 int pipe = intel_crtc->pipe;
548f245b 6841 u32 dpll = I915_READ(DPLL(pipe));
79e53945
JB		 6842 u32 fp;
6843 intel_clock_t clock;
6844
6845 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
39adb7a5 6846 fp = I915_READ(FP0(pipe));
79e53945 6847 else
39adb7a5 6848 fp = I915_READ(FP1(pipe));
79e53945
JB		 6849
6850 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 6851 if (IS_PINEVIEW(dev)) {
6852 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6853 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 6854 } else {
6855 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6856 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6857 }
6858
a6c45cf0 6859 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 6860 if (IS_PINEVIEW(dev))
6861 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6862 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 6863 else
6864 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 6865 DPLL_FPA01_P1_POST_DIV_SHIFT);
6866
6867 switch (dpll & DPLL_MODE_MASK) {
6868 case DPLLB_MODE_DAC_SERIAL:
6869 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6870 5 : 10;
6871 break;
6872 case DPLLB_MODE_LVDS:
6873 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6874 7 : 14;
6875 break;
6876 default:
28c97730 6877 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945
JB		 6878 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6879 return 0;
6880 }
6881
6882 /* XXX: Handle the 100Mhz refclk */
2177832f 6883 intel_clock(dev, 96000, &clock);
79e53945
JB		 6884 } else {
6885 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6886
6887 if (is_lvds) {
6888 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6889 DPLL_FPA01_P1_POST_DIV_SHIFT);
6890 clock.p2 = 14;
6891
6892 if ((dpll & PLL_REF_INPUT_MASK) ==
6893 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6894 /* XXX: might not be 66MHz */
2177832f 6895 intel_clock(dev, 66000, &clock);
79e53945 6896 } else
2177832f 6897 intel_clock(dev, 48000, &clock);
79e53945
JB		 6898 } else {
6899 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6900 clock.p1 = 2;
6901 else {
6902 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6903 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6904 }
6905 if (dpll & PLL_P2_DIVIDE_BY_4)
6906 clock.p2 = 4;
6907 else
6908 clock.p2 = 2;
6909
2177832f 6910 intel_clock(dev, 48000, &clock);
79e53945
JB		 6911 }
6912 }
6913
6914 /* XXX: It would be nice to validate the clocks, but we can't reuse
6915 * i830PllIsValid() because it relies on the xf86_config connector
6916 * configuration being accurate, which it isn't necessarily.
6917 */
6918
6919 return clock.dot;
6920}
6921
6922/** Returns the currently programmed mode of the given pipe. */
6923struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6924 struct drm_crtc *crtc)
6925{
548f245b 6926 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945
JB		 6927 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6928 int pipe = intel_crtc->pipe;
6929 struct drm_display_mode *mode;
548f245b
JB		 6930 int htot = I915_READ(HTOTAL(pipe));
6931 int hsync = I915_READ(HSYNC(pipe));
6932 int vtot = I915_READ(VTOTAL(pipe));
6933 int vsync = I915_READ(VSYNC(pipe));
79e53945
JB		 6934
6935 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6936 if (!mode)
6937 return NULL;
6938
6939 mode->clock = intel_crtc_clock_get(dev, crtc);
6940 mode->hdisplay = (htot & 0xffff) + 1;
6941 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6942 mode->hsync_start = (hsync & 0xffff) + 1;
6943 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6944 mode->vdisplay = (vtot & 0xffff) + 1;
6945 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6946 mode->vsync_start = (vsync & 0xffff) + 1;
6947 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6948
6949 drm_mode_set_name(mode);
6950 drm_mode_set_crtcinfo(mode, 0);
6951
6952 return mode;
6953}
6954
652c393a
JB		 6955#define GPU_IDLE_TIMEOUT 500 /* ms */
6956
6957/* When this timer fires, we've been idle for awhile */
6958static void intel_gpu_idle_timer(unsigned long arg)
6959{
6960 struct drm_device *dev = (struct drm_device *)arg;
6961 drm_i915_private_t *dev_priv = dev->dev_private;
6962
ff7ea4c0
CW		 6963 if (!list_empty(&dev_priv->mm.active_list)) {
6964 /* Still processing requests, so just re-arm the timer. */
6965 mod_timer(&dev_priv->idle_timer, jiffies +
6966 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
6967 return;
6968 }
652c393a 6969
ff7ea4c0 6970 dev_priv->busy = false;
01dfba93 6971 queue_work(dev_priv->wq, &dev_priv->idle_work);
652c393a
JB		 6972}
6973
652c393a
JB		 6974#define CRTC_IDLE_TIMEOUT 1000 /* ms */
6975
6976static void intel_crtc_idle_timer(unsigned long arg)
6977{
6978 struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
6979 struct drm_crtc *crtc = &intel_crtc->base;
6980 drm_i915_private_t *dev_priv = crtc->dev->dev_private;
ff7ea4c0 6981 struct intel_framebuffer *intel_fb;
652c393a 6982
ff7ea4c0
CW		 6983 intel_fb = to_intel_framebuffer(crtc->fb);
6984 if (intel_fb && intel_fb->obj->active) {
6985 /* The framebuffer is still being accessed by the GPU. */
6986 mod_timer(&intel_crtc->idle_timer, jiffies +
6987 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
6988 return;
6989 }
652c393a 6990
ff7ea4c0 6991 intel_crtc->busy = false;
01dfba93 6992 queue_work(dev_priv->wq, &dev_priv->idle_work);
652c393a
JB		 6993}
6994
3dec0095 6995static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 6996{
6997 struct drm_device *dev = crtc->dev;
6998 drm_i915_private_t *dev_priv = dev->dev_private;
6999 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7000 int pipe = intel_crtc->pipe;
dbdc6479
JB		 7001 int dpll_reg = DPLL(pipe);
7002 int dpll;
652c393a 7003
bad720ff 7004 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 7005 return;
7006
7007 if (!dev_priv->lvds_downclock_avail)
7008 return;
7009
dbdc6479 7010 dpll = I915_READ(dpll_reg);
652c393a 7011 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 7012 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a 7013
8ac5a6d5 7014 assert_panel_unlocked(dev_priv, pipe);
652c393a
JB		 7015
7016 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
7017 I915_WRITE(dpll_reg, dpll);
9d0498a2 7018 intel_wait_for_vblank(dev, pipe);
dbdc6479 7019
652c393a
JB		 7020 dpll = I915_READ(dpll_reg);
7021 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 7022 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a
JB		 7023 }
7024
7025 /* Schedule downclock */
3dec0095
DV		 7026 mod_timer(&intel_crtc->idle_timer, jiffies +
7027 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
652c393a
JB		 7028}
7029
7030static void intel_decrease_pllclock(struct drm_crtc *crtc)
7031{
7032 struct drm_device *dev = crtc->dev;
7033 drm_i915_private_t *dev_priv = dev->dev_private;
7034 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7035 int pipe = intel_crtc->pipe;
9db4a9c7 7036 int dpll_reg = DPLL(pipe);
652c393a
JB		 7037 int dpll = I915_READ(dpll_reg);
7038
bad720ff 7039 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 7040 return;
7041
7042 if (!dev_priv->lvds_downclock_avail)
7043 return;
7044
7045 /*
7046 * Since this is called by a timer, we should never get here in
7047 * the manual case.
7048 */
7049 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
44d98a61 7050 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 7051
8ac5a6d5 7052 assert_panel_unlocked(dev_priv, pipe);
652c393a
JB		 7053
7054 dpll |= DISPLAY_RATE_SELECT_FPA1;
7055 I915_WRITE(dpll_reg, dpll);
9d0498a2 7056 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 7057 dpll = I915_READ(dpll_reg);
7058 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 7059 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 7060 }
7061
7062}
7063
7064/**
7065 * intel_idle_update - adjust clocks for idleness
7066 * @work: work struct
7067 *
7068 * Either the GPU or display (or both) went idle. Check the busy status
7069 * here and adjust the CRTC and GPU clocks as necessary.
7070 */
7071static void intel_idle_update(struct work_struct *work)
7072{
7073 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
7074 idle_work);
7075 struct drm_device *dev = dev_priv->dev;
7076 struct drm_crtc *crtc;
7077 struct intel_crtc *intel_crtc;
7078
7079 if (!i915_powersave)
7080 return;
7081
7082 mutex_lock(&dev->struct_mutex);
7083
7648fa99
JB		 7084 i915_update_gfx_val(dev_priv);
7085
652c393a
JB		 7086 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7087 /* Skip inactive CRTCs */
7088 if (!crtc->fb)
7089 continue;
7090
7091 intel_crtc = to_intel_crtc(crtc);
7092 if (!intel_crtc->busy)
7093 intel_decrease_pllclock(crtc);
7094 }
7095
45ac22c8 7096
652c393a
JB		 7097 mutex_unlock(&dev->struct_mutex);
7098}
7099
7100/**
7101 * intel_mark_busy - mark the GPU and possibly the display busy
7102 * @dev: drm device
7103 * @obj: object we're operating on
7104 *
7105 * Callers can use this function to indicate that the GPU is busy processing
7106 * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout
7107 * buffer), we'll also mark the display as busy, so we know to increase its
7108 * clock frequency.
7109 */
05394f39 7110void intel_mark_busy(struct drm_device *dev, struct drm_i915_gem_object *obj)
652c393a
JB		 7111{
7112 drm_i915_private_t *dev_priv = dev->dev_private;
7113 struct drm_crtc *crtc = NULL;
7114 struct intel_framebuffer *intel_fb;
7115 struct intel_crtc *intel_crtc;
7116
5e17ee74
ZW		 7117 if (!drm_core_check_feature(dev, DRIVER_MODESET))
7118 return;
7119
18b2190c 7120 if (!dev_priv->busy)
28cf798f 7121 dev_priv->busy = true;
18b2190c 7122 else
28cf798f
CW		 7123 mod_timer(&dev_priv->idle_timer, jiffies +
7124 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
652c393a
JB		 7125
7126 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7127 if (!crtc->fb)
7128 continue;
7129
7130 intel_crtc = to_intel_crtc(crtc);
7131 intel_fb = to_intel_framebuffer(crtc->fb);
7132 if (intel_fb->obj == obj) {
7133 if (!intel_crtc->busy) {
7134 /* Non-busy -> busy, upclock */
3dec0095 7135 intel_increase_pllclock(crtc);
652c393a
JB		 7136 intel_crtc->busy = true;
7137 } else {
7138 /* Busy -> busy, put off timer */
7139 mod_timer(&intel_crtc->idle_timer, jiffies +
7140 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
7141 }
7142 }
7143 }
7144}
7145
79e53945
JB		 7146static void intel_crtc_destroy(struct drm_crtc *crtc)
7147{
7148 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 7149 struct drm_device *dev = crtc->dev;
7150 struct intel_unpin_work *work;
7151 unsigned long flags;
7152
7153 spin_lock_irqsave(&dev->event_lock, flags);
7154 work = intel_crtc->unpin_work;
7155 intel_crtc->unpin_work = NULL;
7156 spin_unlock_irqrestore(&dev->event_lock, flags);
7157
7158 if (work) {
7159 cancel_work_sync(&work->work);
7160 kfree(work);
7161 }
79e53945
JB		 7162
7163 drm_crtc_cleanup(crtc);
67e77c5a 7164
79e53945
JB		 7165 kfree(intel_crtc);
7166}
7167
6b95a207
KH		 7168static void intel_unpin_work_fn(struct work_struct *__work)
7169{
7170 struct intel_unpin_work *work =
7171 container_of(__work, struct intel_unpin_work, work);
7172
7173 mutex_lock(&work->dev->struct_mutex);
1690e1eb 7174 intel_unpin_fb_obj(work->old_fb_obj);
05394f39
CW		 7175 drm_gem_object_unreference(&work->pending_flip_obj->base);
7176 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 7177
7782de3b 7178 intel_update_fbc(work->dev);
6b95a207
KH		 7179 mutex_unlock(&work->dev->struct_mutex);
7180 kfree(work);
7181}
7182
1afe3e9d 7183static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 7184 struct drm_crtc *crtc)
6b95a207
KH		 7185{
7186 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 7187 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7188 struct intel_unpin_work *work;
05394f39 7189 struct drm_i915_gem_object *obj;
6b95a207 7190 struct drm_pending_vblank_event *e;
49b14a5c 7191 struct timeval tnow, tvbl;
6b95a207
KH		 7192 unsigned long flags;
7193
7194 /* Ignore early vblank irqs */
7195 if (intel_crtc == NULL)
7196 return;
7197
49b14a5c
MK		 7198 do_gettimeofday(&tnow);
7199
6b95a207
KH		 7200 spin_lock_irqsave(&dev->event_lock, flags);
7201 work = intel_crtc->unpin_work;
7202 if (work == NULL || !work->pending) {
7203 spin_unlock_irqrestore(&dev->event_lock, flags);
7204 return;
7205 }
7206
7207 intel_crtc->unpin_work = NULL;
6b95a207
KH		 7208
7209 if (work->event) {
7210 e = work->event;
49b14a5c 7211 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
0af7e4df
MK		 7212
7213 /* Called before vblank count and timestamps have
7214 * been updated for the vblank interval of flip
7215 * completion? Need to increment vblank count and
7216 * add one videorefresh duration to returned timestamp
49b14a5c
MK		 7217 * to account for this. We assume this happened if we
7218 * get called over 0.9 frame durations after the last
7219 * timestamped vblank.
7220 *
7221 * This calculation can not be used with vrefresh rates
7222 * below 5Hz (10Hz to be on the safe side) without
7223 * promoting to 64 integers.
0af7e4df 7224 */
49b14a5c
MK		 7225 if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
7226 9 * crtc->framedur_ns) {
0af7e4df 7227 e->event.sequence++;
49b14a5c
MK		 7228 tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
7229 crtc->framedur_ns);
0af7e4df
MK		 7230 }
7231
49b14a5c
MK		 7232 e->event.tv_sec = tvbl.tv_sec;
7233 e->event.tv_usec = tvbl.tv_usec;
0af7e4df 7234
6b95a207
KH		 7235 list_add_tail(&e->base.link,
7236 &e->base.file_priv->event_list);
7237 wake_up_interruptible(&e->base.file_priv->event_wait);
7238 }
7239
0af7e4df
MK		 7240 drm_vblank_put(dev, intel_crtc->pipe);
7241
6b95a207
KH		 7242 spin_unlock_irqrestore(&dev->event_lock, flags);
7243
05394f39 7244 obj = work->old_fb_obj;
d9e86c0e 7245
e59f2bac 7246 atomic_clear_mask(1 << intel_crtc->plane,
05394f39
CW		 7247 &obj->pending_flip.counter);
7248 if (atomic_read(&obj->pending_flip) == 0)
f787a5f5 7249 wake_up(&dev_priv->pending_flip_queue);
d9e86c0e 7250
6b95a207 7251 schedule_work(&work->work);
e5510fac
JB		 7252
7253 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 7254}
7255
1afe3e9d
JB		 7256void intel_finish_page_flip(struct drm_device *dev, int pipe)
7257{
7258 drm_i915_private_t *dev_priv = dev->dev_private;
7259 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7260
49b14a5c 7261 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7262}
7263
7264void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7265{
7266 drm_i915_private_t *dev_priv = dev->dev_private;
7267 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7268
49b14a5c 7269 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7270}
7271
6b95a207
KH		 7272void intel_prepare_page_flip(struct drm_device *dev, int plane)
7273{
7274 drm_i915_private_t *dev_priv = dev->dev_private;
7275 struct intel_crtc *intel_crtc =
7276 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7277 unsigned long flags;
7278
7279 spin_lock_irqsave(&dev->event_lock, flags);
de3f440f 7280 if (intel_crtc->unpin_work) {
4e5359cd
SF		 7281 if ((++intel_crtc->unpin_work->pending) > 1)
7282 DRM_ERROR("Prepared flip multiple times\n");
de3f440f
JB		 7283 } else {
7284 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
7285 }
6b95a207
KH		 7286 spin_unlock_irqrestore(&dev->event_lock, flags);
7287}
7288
8c9f3aaf
JB		 7289static int intel_gen2_queue_flip(struct drm_device *dev,
7290 struct drm_crtc *crtc,
7291 struct drm_framebuffer *fb,
7292 struct drm_i915_gem_object *obj)
7293{
7294 struct drm_i915_private *dev_priv = dev->dev_private;
7295 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7296 unsigned long offset;
7297 u32 flip_mask;
7298 int ret;
7299
7300 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7301 if (ret)
7302 goto out;
7303
7304 /* Offset into the new buffer for cases of shared fbs between CRTCs */
01f2c773 7305 offset = crtc->y * fb->pitches[0] + crtc->x * fb->bits_per_pixel/8;
8c9f3aaf
JB		 7306
7307 ret = BEGIN_LP_RING(6);
7308 if (ret)
7309 goto out;
7310
7311 /* Can't queue multiple flips, so wait for the previous
7312 * one to finish before executing the next.
7313 */
7314 if (intel_crtc->plane)
7315 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7316 else
7317 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7318 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
7319 OUT_RING(MI_NOOP);
7320 OUT_RING(MI_DISPLAY_FLIP |
7321 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
01f2c773 7322 OUT_RING(fb->pitches[0]);
8c9f3aaf 7323 OUT_RING(obj->gtt_offset + offset);
c6a32fcb 7324 OUT_RING(0); /* aux display base address, unused */
8c9f3aaf
JB		 7325 ADVANCE_LP_RING();
7326out:
7327 return ret;
7328}
7329
7330static int intel_gen3_queue_flip(struct drm_device *dev,
7331 struct drm_crtc *crtc,
7332 struct drm_framebuffer *fb,
7333 struct drm_i915_gem_object *obj)
7334{
7335 struct drm_i915_private *dev_priv = dev->dev_private;
7336 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7337 unsigned long offset;
7338 u32 flip_mask;
7339 int ret;
7340
7341 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7342 if (ret)
7343 goto out;
7344
7345 /* Offset into the new buffer for cases of shared fbs between CRTCs */
01f2c773 7346 offset = crtc->y * fb->pitches[0] + crtc->x * fb->bits_per_pixel/8;
8c9f3aaf
JB		 7347
7348 ret = BEGIN_LP_RING(6);
7349 if (ret)
7350 goto out;
7351
7352 if (intel_crtc->plane)
7353 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7354 else
7355 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7356 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
7357 OUT_RING(MI_NOOP);
7358 OUT_RING(MI_DISPLAY_FLIP_I915 |
7359 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
01f2c773 7360 OUT_RING(fb->pitches[0]);
8c9f3aaf
JB		 7361 OUT_RING(obj->gtt_offset + offset);
7362 OUT_RING(MI_NOOP);
7363
7364 ADVANCE_LP_RING();
7365out:
7366 return ret;
7367}
7368
7369static int intel_gen4_queue_flip(struct drm_device *dev,
7370 struct drm_crtc *crtc,
7371 struct drm_framebuffer *fb,
7372 struct drm_i915_gem_object *obj)
7373{
7374 struct drm_i915_private *dev_priv = dev->dev_private;
7375 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7376 uint32_t pf, pipesrc;
7377 int ret;
7378
7379 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7380 if (ret)
7381 goto out;
7382
7383 ret = BEGIN_LP_RING(4);
7384 if (ret)
7385 goto out;
7386
7387 /* i965+ uses the linear or tiled offsets from the
7388 * Display Registers (which do not change across a page-flip)
7389 * so we need only reprogram the base address.
7390 */
7391 OUT_RING(MI_DISPLAY_FLIP |
7392 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
01f2c773 7393 OUT_RING(fb->pitches[0]);
8c9f3aaf
JB		 7394 OUT_RING(obj->gtt_offset | obj->tiling_mode);
7395
7396 /* XXX Enabling the panel-fitter across page-flip is so far
7397 * untested on non-native modes, so ignore it for now.
7398 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7399 */
7400 pf = 0;
7401 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7402 OUT_RING(pf | pipesrc);
7403 ADVANCE_LP_RING();
7404out:
7405 return ret;
7406}
7407
7408static int intel_gen6_queue_flip(struct drm_device *dev,
7409 struct drm_crtc *crtc,
7410 struct drm_framebuffer *fb,
7411 struct drm_i915_gem_object *obj)
7412{
7413 struct drm_i915_private *dev_priv = dev->dev_private;
7414 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7415 uint32_t pf, pipesrc;
7416 int ret;
7417
7418 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7419 if (ret)
7420 goto out;
7421
7422 ret = BEGIN_LP_RING(4);
7423 if (ret)
7424 goto out;
7425
7426 OUT_RING(MI_DISPLAY_FLIP |
7427 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
01f2c773 7428 OUT_RING(fb->pitches[0] | obj->tiling_mode);
8c9f3aaf
JB		 7429 OUT_RING(obj->gtt_offset);
7430
7431 pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7432 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7433 OUT_RING(pf | pipesrc);
7434 ADVANCE_LP_RING();
7435out:
7436 return ret;
7437}
7438
7c9017e5
JB		 7439/*
7440 * On gen7 we currently use the blit ring because (in early silicon at least)
7441 * the render ring doesn't give us interrpts for page flip completion, which
7442 * means clients will hang after the first flip is queued. Fortunately the
7443 * blit ring generates interrupts properly, so use it instead.
7444 */
7445static int intel_gen7_queue_flip(struct drm_device *dev,
7446 struct drm_crtc *crtc,
7447 struct drm_framebuffer *fb,
7448 struct drm_i915_gem_object *obj)
7449{
7450 struct drm_i915_private *dev_priv = dev->dev_private;
7451 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7452 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
7453 int ret;
7454
7455 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7456 if (ret)
7457 goto out;
7458
7459 ret = intel_ring_begin(ring, 4);
7460 if (ret)
7461 goto out;
7462
7463 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | (intel_crtc->plane << 19));
01f2c773 7464 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
7c9017e5
JB		 7465 intel_ring_emit(ring, (obj->gtt_offset));
7466 intel_ring_emit(ring, (MI_NOOP));
7467 intel_ring_advance(ring);
7468out:
7469 return ret;
7470}
7471
8c9f3aaf
JB		 7472static int intel_default_queue_flip(struct drm_device *dev,
7473 struct drm_crtc *crtc,
7474 struct drm_framebuffer *fb,
7475 struct drm_i915_gem_object *obj)
7476{
7477 return -ENODEV;
7478}
7479
6b95a207
KH		 7480static int intel_crtc_page_flip(struct drm_crtc *crtc,
7481 struct drm_framebuffer *fb,
7482 struct drm_pending_vblank_event *event)
7483{
7484 struct drm_device *dev = crtc->dev;
7485 struct drm_i915_private *dev_priv = dev->dev_private;
7486 struct intel_framebuffer *intel_fb;
05394f39 7487 struct drm_i915_gem_object *obj;
6b95a207
KH		 7488 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7489 struct intel_unpin_work *work;
8c9f3aaf 7490 unsigned long flags;
52e68630 7491 int ret;
6b95a207
KH		 7492
7493 work = kzalloc(sizeof *work, GFP_KERNEL);
7494 if (work == NULL)
7495 return -ENOMEM;
7496
6b95a207
KH		 7497 work->event = event;
7498 work->dev = crtc->dev;
7499 intel_fb = to_intel_framebuffer(crtc->fb);
b1b87f6b 7500 work->old_fb_obj = intel_fb->obj;
6b95a207
KH		 7501 INIT_WORK(&work->work, intel_unpin_work_fn);
7502
7317c75e
JB		 7503 ret = drm_vblank_get(dev, intel_crtc->pipe);
7504 if (ret)
7505 goto free_work;
7506
6b95a207
KH		 7507 /* We borrow the event spin lock for protecting unpin_work */
7508 spin_lock_irqsave(&dev->event_lock, flags);
7509 if (intel_crtc->unpin_work) {
7510 spin_unlock_irqrestore(&dev->event_lock, flags);
7511 kfree(work);
7317c75e 7512 drm_vblank_put(dev, intel_crtc->pipe);
468f0b44
CW		 7513
7514 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 7515 return -EBUSY;
7516 }
7517 intel_crtc->unpin_work = work;
7518 spin_unlock_irqrestore(&dev->event_lock, flags);
7519
7520 intel_fb = to_intel_framebuffer(fb);
7521 obj = intel_fb->obj;
7522
468f0b44 7523 mutex_lock(&dev->struct_mutex);
6b95a207 7524
75dfca80 7525 /* Reference the objects for the scheduled work. */
05394f39
CW		 7526 drm_gem_object_reference(&work->old_fb_obj->base);
7527 drm_gem_object_reference(&obj->base);
6b95a207
KH		 7528
7529 crtc->fb = fb;
96b099fd 7530
e1f99ce6 7531 work->pending_flip_obj = obj;
e1f99ce6 7532
4e5359cd
SF		 7533 work->enable_stall_check = true;
7534
e1f99ce6
CW		 7535 /* Block clients from rendering to the new back buffer until
7536 * the flip occurs and the object is no longer visible.
7537 */
05394f39 7538 atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
e1f99ce6 7539
8c9f3aaf
JB		 7540 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7541 if (ret)
7542 goto cleanup_pending;
6b95a207 7543
7782de3b 7544 intel_disable_fbc(dev);
6b95a207
KH		 7545 mutex_unlock(&dev->struct_mutex);
7546
e5510fac
JB		 7547 trace_i915_flip_request(intel_crtc->plane, obj);
7548
6b95a207 7549 return 0;
96b099fd 7550
8c9f3aaf
JB		 7551cleanup_pending:
7552 atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
05394f39
CW		 7553 drm_gem_object_unreference(&work->old_fb_obj->base);
7554 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 7555 mutex_unlock(&dev->struct_mutex);
7556
7557 spin_lock_irqsave(&dev->event_lock, flags);
7558 intel_crtc->unpin_work = NULL;
7559 spin_unlock_irqrestore(&dev->event_lock, flags);
7560
7317c75e
JB		 7561 drm_vblank_put(dev, intel_crtc->pipe);
7562free_work:
96b099fd
CW		 7563 kfree(work);
7564
7565 return ret;
6b95a207
KH		 7566}
7567
47f1c6c9
CW		 7568static void intel_sanitize_modesetting(struct drm_device *dev,
7569 int pipe, int plane)
7570{
7571 struct drm_i915_private *dev_priv = dev->dev_private;
7572 u32 reg, val;
7573
7574 if (HAS_PCH_SPLIT(dev))
7575 return;
7576
7577 /* Who knows what state these registers were left in by the BIOS or
7578 * grub?
7579 *
7580 * If we leave the registers in a conflicting state (e.g. with the
7581 * display plane reading from the other pipe than the one we intend
7582 * to use) then when we attempt to teardown the active mode, we will
7583 * not disable the pipes and planes in the correct order -- leaving
7584 * a plane reading from a disabled pipe and possibly leading to
7585 * undefined behaviour.
7586 */
7587
7588 reg = DSPCNTR(plane);
7589 val = I915_READ(reg);
7590
7591 if ((val & DISPLAY_PLANE_ENABLE) == 0)
7592 return;
7593 if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe)
7594 return;
7595
7596 /* This display plane is active and attached to the other CPU pipe. */
7597 pipe = !pipe;
7598
7599 /* Disable the plane and wait for it to stop reading from the pipe. */
b24e7179
JB		 7600 intel_disable_plane(dev_priv, plane, pipe);
7601 intel_disable_pipe(dev_priv, pipe);
47f1c6c9 7602}
79e53945 7603
f6e5b160
CW		 7604static void intel_crtc_reset(struct drm_crtc *crtc)
7605{
7606 struct drm_device *dev = crtc->dev;
7607 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7608
7609 /* Reset flags back to the 'unknown' status so that they
7610 * will be correctly set on the initial modeset.
7611 */
7612 intel_crtc->dpms_mode = -1;
7613
7614 /* We need to fix up any BIOS configuration that conflicts with
7615 * our expectations.
7616 */
7617 intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane);
7618}
7619
7620static struct drm_crtc_helper_funcs intel_helper_funcs = {
7621 .dpms = intel_crtc_dpms,
7622 .mode_fixup = intel_crtc_mode_fixup,
7623 .mode_set = intel_crtc_mode_set,
7624 .mode_set_base = intel_pipe_set_base,
7625 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7626 .load_lut = intel_crtc_load_lut,
7627 .disable = intel_crtc_disable,
7628};
7629
7630static const struct drm_crtc_funcs intel_crtc_funcs = {
7631 .reset = intel_crtc_reset,
7632 .cursor_set = intel_crtc_cursor_set,
7633 .cursor_move = intel_crtc_cursor_move,
7634 .gamma_set = intel_crtc_gamma_set,
7635 .set_config = drm_crtc_helper_set_config,
7636 .destroy = intel_crtc_destroy,
7637 .page_flip = intel_crtc_page_flip,
7638};
7639
b358d0a6 7640static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 7641{
22fd0fab 7642 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 7643 struct intel_crtc *intel_crtc;
7644 int i;
7645
7646 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
7647 if (intel_crtc == NULL)
7648 return;
7649
7650 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
7651
7652 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 7653 for (i = 0; i < 256; i++) {
7654 intel_crtc->lut_r[i] = i;
7655 intel_crtc->lut_g[i] = i;
7656 intel_crtc->lut_b[i] = i;
7657 }
7658
80824003
JB		 7659 /* Swap pipes & planes for FBC on pre-965 */
7660 intel_crtc->pipe = pipe;
7661 intel_crtc->plane = pipe;
e2e767ab 7662 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 7663 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 7664 intel_crtc->plane = !pipe;
80824003
JB		 7665 }
7666
22fd0fab
JB		 7667 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
7668 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
7669 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
7670 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
7671
5d1d0cc8 7672 intel_crtc_reset(&intel_crtc->base);
04dbff52 7673 intel_crtc->active = true; /* force the pipe off on setup_init_config */
5a354204 7674 intel_crtc->bpp = 24; /* default for pre-Ironlake */
7e7d76c3
JB		 7675
7676 if (HAS_PCH_SPLIT(dev)) {
4b645f14
JB		 7677 if (pipe == 2 && IS_IVYBRIDGE(dev))
7678 intel_crtc->no_pll = true;
7e7d76c3
JB		 7679 intel_helper_funcs.prepare = ironlake_crtc_prepare;
7680 intel_helper_funcs.commit = ironlake_crtc_commit;
7681 } else {
7682 intel_helper_funcs.prepare = i9xx_crtc_prepare;
7683 intel_helper_funcs.commit = i9xx_crtc_commit;
7684 }
7685
79e53945
JB		 7686 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
7687
652c393a
JB		 7688 intel_crtc->busy = false;
7689
7690 setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
7691 (unsigned long)intel_crtc);
79e53945
JB		 7692}
7693
08d7b3d1 7694int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 7695 struct drm_file *file)
08d7b3d1
CW		 7696{
7697 drm_i915_private_t *dev_priv = dev->dev_private;
7698 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 7699 struct drm_mode_object *drmmode_obj;
7700 struct intel_crtc *crtc;
08d7b3d1
CW		 7701
7702 if (!dev_priv) {
7703 DRM_ERROR("called with no initialization\n");
7704 return -EINVAL;
7705 }
7706
c05422d5
DV		 7707 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
7708 DRM_MODE_OBJECT_CRTC);
08d7b3d1 7709
c05422d5 7710 if (!drmmode_obj) {
08d7b3d1
CW		 7711 DRM_ERROR("no such CRTC id\n");
7712 return -EINVAL;
7713 }
7714
c05422d5
DV		 7715 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
7716 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 7717
c05422d5 7718 return 0;
08d7b3d1
CW		 7719}
7720
c5e4df33 7721static int intel_encoder_clones(struct drm_device *dev, int type_mask)
79e53945 7722{
4ef69c7a 7723 struct intel_encoder *encoder;
79e53945 7724 int index_mask = 0;
79e53945
JB		 7725 int entry = 0;
7726
4ef69c7a
CW		 7727 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7728 if (type_mask & encoder->clone_mask)
79e53945
JB		 7729 index_mask |= (1 << entry);
7730 entry++;
7731 }
4ef69c7a 7732
79e53945
JB		 7733 return index_mask;
7734}
7735
4d302442
CW		 7736static bool has_edp_a(struct drm_device *dev)
7737{
7738 struct drm_i915_private *dev_priv = dev->dev_private;
7739
7740 if (!IS_MOBILE(dev))
7741 return false;
7742
7743 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
7744 return false;
7745
7746 if (IS_GEN5(dev) &&
7747 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
7748 return false;
7749
7750 return true;
7751}
7752
79e53945
JB		 7753static void intel_setup_outputs(struct drm_device *dev)
7754{
725e30ad 7755 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 7756 struct intel_encoder *encoder;
cb0953d7 7757 bool dpd_is_edp = false;
f3cfcba6 7758 bool has_lvds;
79e53945 7759
f3cfcba6 7760 has_lvds = intel_lvds_init(dev);
c5d1b51d
CW		 7761 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
7762 /* disable the panel fitter on everything but LVDS */
7763 I915_WRITE(PFIT_CONTROL, 0);
7764 }
79e53945 7765
bad720ff 7766 if (HAS_PCH_SPLIT(dev)) {
cb0953d7 7767 dpd_is_edp = intel_dpd_is_edp(dev);
30ad48b7 7768
4d302442 7769 if (has_edp_a(dev))
32f9d658
ZW		 7770 intel_dp_init(dev, DP_A);
7771
cb0953d7
AJ		 7772 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
7773 intel_dp_init(dev, PCH_DP_D);
7774 }
7775
7776 intel_crt_init(dev);
7777
7778 if (HAS_PCH_SPLIT(dev)) {
7779 int found;
7780
30ad48b7 7781 if (I915_READ(HDMIB) & PORT_DETECTED) {
461ed3ca
ZY		 7782 /* PCH SDVOB multiplex with HDMIB */
7783 found = intel_sdvo_init(dev, PCH_SDVOB);
30ad48b7
ZW		 7784 if (!found)
7785 intel_hdmi_init(dev, HDMIB);
5eb08b69
ZW		 7786 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
7787 intel_dp_init(dev, PCH_DP_B);
30ad48b7
ZW		 7788 }
7789
7790 if (I915_READ(HDMIC) & PORT_DETECTED)
7791 intel_hdmi_init(dev, HDMIC);
7792
7793 if (I915_READ(HDMID) & PORT_DETECTED)
7794 intel_hdmi_init(dev, HDMID);
7795
5eb08b69
ZW		 7796 if (I915_READ(PCH_DP_C) & DP_DETECTED)
7797 intel_dp_init(dev, PCH_DP_C);
7798
cb0953d7 7799 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
5eb08b69
ZW		 7800 intel_dp_init(dev, PCH_DP_D);
7801
103a196f 7802 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 7803 bool found = false;
7d57382e 7804
725e30ad 7805 if (I915_READ(SDVOB) & SDVO_DETECTED) {
b01f2c3a 7806 DRM_DEBUG_KMS("probing SDVOB\n");
725e30ad 7807 found = intel_sdvo_init(dev, SDVOB);
b01f2c3a
JB		 7808 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
7809 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
725e30ad 7810 intel_hdmi_init(dev, SDVOB);
b01f2c3a 7811 }
27185ae1 7812
b01f2c3a
JB		 7813 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
7814 DRM_DEBUG_KMS("probing DP_B\n");
a4fc5ed6 7815 intel_dp_init(dev, DP_B);
b01f2c3a 7816 }
725e30ad 7817 }
13520b05
KH		 7818
7819 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 7820
b01f2c3a
JB		 7821 if (I915_READ(SDVOB) & SDVO_DETECTED) {
7822 DRM_DEBUG_KMS("probing SDVOC\n");
725e30ad 7823 found = intel_sdvo_init(dev, SDVOC);
b01f2c3a 7824 }
27185ae1
ML		 7825
7826 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
7827
b01f2c3a
JB		 7828 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
7829 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
725e30ad 7830 intel_hdmi_init(dev, SDVOC);
b01f2c3a
JB		 7831 }
7832 if (SUPPORTS_INTEGRATED_DP(dev)) {
7833 DRM_DEBUG_KMS("probing DP_C\n");
a4fc5ed6 7834 intel_dp_init(dev, DP_C);
b01f2c3a 7835 }
725e30ad 7836 }
27185ae1 7837
b01f2c3a
JB		 7838 if (SUPPORTS_INTEGRATED_DP(dev) &&
7839 (I915_READ(DP_D) & DP_DETECTED)) {
7840 DRM_DEBUG_KMS("probing DP_D\n");
a4fc5ed6 7841 intel_dp_init(dev, DP_D);
b01f2c3a 7842 }
bad720ff 7843 } else if (IS_GEN2(dev))
79e53945
JB		 7844 intel_dvo_init(dev);
7845
103a196f 7846 if (SUPPORTS_TV(dev))
79e53945
JB		 7847 intel_tv_init(dev);
7848
4ef69c7a
CW		 7849 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7850 encoder->base.possible_crtcs = encoder->crtc_mask;
7851 encoder->base.possible_clones =
7852 intel_encoder_clones(dev, encoder->clone_mask);
79e53945 7853 }
47356eb6 7854
2c7111db
CW		 7855 /* disable all the possible outputs/crtcs before entering KMS mode */
7856 drm_helper_disable_unused_functions(dev);
9fb526db
KP		 7857
7858 if (HAS_PCH_SPLIT(dev))
7859 ironlake_init_pch_refclk(dev);
79e53945
JB		 7860}
7861
7862static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
7863{
7864 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945
JB		 7865
7866 drm_framebuffer_cleanup(fb);
05394f39 7867 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
79e53945
JB		 7868
7869 kfree(intel_fb);
7870}
7871
7872static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 7873 struct drm_file *file,
79e53945
JB		 7874 unsigned int *handle)
7875{
7876 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 7877 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 7878
05394f39 7879 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 7880}
7881
7882static const struct drm_framebuffer_funcs intel_fb_funcs = {
7883 .destroy = intel_user_framebuffer_destroy,
7884 .create_handle = intel_user_framebuffer_create_handle,
7885};
7886
38651674
DA		 7887int intel_framebuffer_init(struct drm_device *dev,
7888 struct intel_framebuffer *intel_fb,
308e5bcb 7889 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 7890 struct drm_i915_gem_object *obj)
79e53945 7891{
79e53945
JB		 7892 int ret;
7893
05394f39 7894 if (obj->tiling_mode == I915_TILING_Y)
57cd6508
CW		 7895 return -EINVAL;
7896
308e5bcb 7897 if (mode_cmd->pitches[0] & 63)
57cd6508
CW		 7898 return -EINVAL;
7899
308e5bcb 7900 switch (mode_cmd->pixel_format) {
04b3924d
VS		 7901 case DRM_FORMAT_RGB332:
7902 case DRM_FORMAT_RGB565:
7903 case DRM_FORMAT_XRGB8888:
7904 case DRM_FORMAT_ARGB8888:
7905 case DRM_FORMAT_XRGB2101010:
7906 case DRM_FORMAT_ARGB2101010:
308e5bcb 7907 /* RGB formats are common across chipsets */
b5626747 7908 break;
04b3924d
VS		 7909 case DRM_FORMAT_YUYV:
7910 case DRM_FORMAT_UYVY:
7911 case DRM_FORMAT_YVYU:
7912 case DRM_FORMAT_VYUY:
57cd6508
CW		 7913 break;
7914 default:
aca25848
ED		 7915 DRM_DEBUG_KMS("unsupported pixel format %u\n",
7916 mode_cmd->pixel_format);
57cd6508
CW		 7917 return -EINVAL;
7918 }
7919
79e53945
JB		 7920 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
7921 if (ret) {
7922 DRM_ERROR("framebuffer init failed %d\n", ret);
7923 return ret;
7924 }
7925
7926 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
79e53945 7927 intel_fb->obj = obj;
79e53945
JB		 7928 return 0;
7929}
7930
79e53945
JB		 7931static struct drm_framebuffer *
7932intel_user_framebuffer_create(struct drm_device *dev,
7933 struct drm_file *filp,
308e5bcb 7934 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 7935{
05394f39 7936 struct drm_i915_gem_object *obj;
79e53945 7937
308e5bcb
JB		 7938 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
7939 mode_cmd->handles[0]));
c8725226 7940 if (&obj->base == NULL)
cce13ff7 7941 return ERR_PTR(-ENOENT);
79e53945 7942
d2dff872 7943 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 7944}
7945
79e53945 7946static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 7947 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 7948 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 7949};
7950
05394f39 7951static struct drm_i915_gem_object *
aa40d6bb 7952intel_alloc_context_page(struct drm_device *dev)
9ea8d059 7953{
05394f39 7954 struct drm_i915_gem_object *ctx;
9ea8d059
CW		 7955 int ret;
7956
2c34b850
BW		 7957 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
7958
aa40d6bb
ZN		 7959 ctx = i915_gem_alloc_object(dev, 4096);
7960 if (!ctx) {
9ea8d059
CW		 7961 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
7962 return NULL;
7963 }
7964
75e9e915 7965 ret = i915_gem_object_pin(ctx, 4096, true);
9ea8d059
CW		 7966 if (ret) {
7967 DRM_ERROR("failed to pin power context: %d\n", ret);
7968 goto err_unref;
7969 }
7970
aa40d6bb 7971 ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
9ea8d059
CW		 7972 if (ret) {
7973 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
7974 goto err_unpin;
7975 }
9ea8d059 7976
aa40d6bb 7977 return ctx;
9ea8d059
CW		 7978
7979err_unpin:
aa40d6bb 7980 i915_gem_object_unpin(ctx);
9ea8d059 7981err_unref:
05394f39 7982 drm_gem_object_unreference(&ctx->base);
9ea8d059
CW		 7983 mutex_unlock(&dev->struct_mutex);
7984 return NULL;
7985}
7986
7648fa99
JB		 7987bool ironlake_set_drps(struct drm_device *dev, u8 val)
7988{
7989 struct drm_i915_private *dev_priv = dev->dev_private;
7990 u16 rgvswctl;
7991
7992 rgvswctl = I915_READ16(MEMSWCTL);
7993 if (rgvswctl & MEMCTL_CMD_STS) {
7994 DRM_DEBUG("gpu busy, RCS change rejected\n");
7995 return false; /* still busy with another command */
7996 }
7997
7998 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
7999 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
8000 I915_WRITE16(MEMSWCTL, rgvswctl);
8001 POSTING_READ16(MEMSWCTL);
8002
8003 rgvswctl |= MEMCTL_CMD_STS;
8004 I915_WRITE16(MEMSWCTL, rgvswctl);
8005
8006 return true;
8007}
8008
f97108d1
JB		 8009void ironlake_enable_drps(struct drm_device *dev)
8010{
8011 struct drm_i915_private *dev_priv = dev->dev_private;
7648fa99 8012 u32 rgvmodectl = I915_READ(MEMMODECTL);
f97108d1 8013 u8 fmax, fmin, fstart, vstart;
f97108d1 8014
ea056c14
JB		 8015 /* Enable temp reporting */
8016 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
8017 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
8018
f97108d1
JB		 8019 /* 100ms RC evaluation intervals */
8020 I915_WRITE(RCUPEI, 100000);
8021 I915_WRITE(RCDNEI, 100000);
8022
8023 /* Set max/min thresholds to 90ms and 80ms respectively */
8024 I915_WRITE(RCBMAXAVG, 90000);
8025 I915_WRITE(RCBMINAVG, 80000);
8026
8027 I915_WRITE(MEMIHYST, 1);
8028
8029 /* Set up min, max, and cur for interrupt handling */
8030 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
8031 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
8032 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
8033 MEMMODE_FSTART_SHIFT;
7648fa99 8034
f97108d1
JB		 8035 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
8036 PXVFREQ_PX_SHIFT;
8037
80dbf4b7 8038 dev_priv->fmax = fmax; /* IPS callback will increase this */
7648fa99
JB		 8039 dev_priv->fstart = fstart;
8040
80dbf4b7 8041 dev_priv->max_delay = fstart;
f97108d1
JB		 8042 dev_priv->min_delay = fmin;
8043 dev_priv->cur_delay = fstart;
8044
80dbf4b7
JB		 8045 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
8046 fmax, fmin, fstart);
7648fa99 8047
f97108d1
JB		 8048 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
8049
8050 /*
8051 * Interrupts will be enabled in ironlake_irq_postinstall
8052 */
8053
8054 I915_WRITE(VIDSTART, vstart);
8055 POSTING_READ(VIDSTART);
8056
8057 rgvmodectl |= MEMMODE_SWMODE_EN;
8058 I915_WRITE(MEMMODECTL, rgvmodectl);
8059
481b6af3 8060 if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
913d8d11 8061 DRM_ERROR("stuck trying to change perf mode\n");
f97108d1
JB		 8062 msleep(1);
8063
7648fa99 8064 ironlake_set_drps(dev, fstart);
f97108d1 8065
7648fa99
JB		 8066 dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
8067 I915_READ(0x112e0);
8068 dev_priv->last_time1 = jiffies_to_msecs(jiffies);
8069 dev_priv->last_count2 = I915_READ(0x112f4);
8070 getrawmonotonic(&dev_priv->last_time2);
f97108d1
JB		 8071}
8072
8073void ironlake_disable_drps(struct drm_device *dev)
8074{
8075 struct drm_i915_private *dev_priv = dev->dev_private;
7648fa99 8076 u16 rgvswctl = I915_READ16(MEMSWCTL);
f97108d1
JB		 8077
8078 /* Ack interrupts, disable EFC interrupt */
8079 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
8080 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
8081 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
8082 I915_WRITE(DEIIR, DE_PCU_EVENT);
8083 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
8084
8085 /* Go back to the starting frequency */
7648fa99 8086 ironlake_set_drps(dev, dev_priv->fstart);
f97108d1
JB		 8087 msleep(1);
8088 rgvswctl |= MEMCTL_CMD_STS;
8089 I915_WRITE(MEMSWCTL, rgvswctl);
8090 msleep(1);
8091
8092}
8093
3b8d8d91
JB		 8094void gen6_set_rps(struct drm_device *dev, u8 val)
8095{
8096 struct drm_i915_private *dev_priv = dev->dev_private;
8097 u32 swreq;
8098
8099 swreq = (val & 0x3ff) << 25;
8100 I915_WRITE(GEN6_RPNSWREQ, swreq);
8101}
8102
8103void gen6_disable_rps(struct drm_device *dev)
8104{
8105 struct drm_i915_private *dev_priv = dev->dev_private;
8106
8107 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
8108 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
8109 I915_WRITE(GEN6_PMIER, 0);
6fdd4d98
DV		 8110 /* Complete PM interrupt masking here doesn't race with the rps work
8111 * item again unmasking PM interrupts because that is using a different
8112 * register (PMIMR) to mask PM interrupts. The only risk is in leaving
8113 * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
4912d041
BW		 8114
8115 spin_lock_irq(&dev_priv->rps_lock);
8116 dev_priv->pm_iir = 0;
8117 spin_unlock_irq(&dev_priv->rps_lock);
8118
3b8d8d91
JB		 8119 I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
8120}
8121
7648fa99
JB		 8122static unsigned long intel_pxfreq(u32 vidfreq)
8123{
8124 unsigned long freq;
8125 int div = (vidfreq & 0x3f0000) >> 16;
8126 int post = (vidfreq & 0x3000) >> 12;
8127 int pre = (vidfreq & 0x7);
8128
8129 if (!pre)
8130 return 0;
8131
8132 freq = ((div * 133333) / ((1<<post) * pre));
8133
8134 return freq;
8135}
8136
8137void intel_init_emon(struct drm_device *dev)
8138{
8139 struct drm_i915_private *dev_priv = dev->dev_private;
8140 u32 lcfuse;
8141 u8 pxw[16];
8142 int i;
8143
8144 /* Disable to program */
8145 I915_WRITE(ECR, 0);
8146 POSTING_READ(ECR);
8147
8148 /* Program energy weights for various events */
8149 I915_WRITE(SDEW, 0x15040d00);
8150 I915_WRITE(CSIEW0, 0x007f0000);
8151 I915_WRITE(CSIEW1, 0x1e220004);
8152 I915_WRITE(CSIEW2, 0x04000004);
8153
8154 for (i = 0; i < 5; i++)
8155 I915_WRITE(PEW + (i * 4), 0);
8156 for (i = 0; i < 3; i++)
8157 I915_WRITE(DEW + (i * 4), 0);
8158
8159 /* Program P-state weights to account for frequency power adjustment */
8160 for (i = 0; i < 16; i++) {
8161 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
8162 unsigned long freq = intel_pxfreq(pxvidfreq);
8163 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
8164 PXVFREQ_PX_SHIFT;
8165 unsigned long val;
8166
8167 val = vid * vid;
8168 val *= (freq / 1000);
8169 val *= 255;
8170 val /= (127*127*900);
8171 if (val > 0xff)
8172 DRM_ERROR("bad pxval: %ld\n", val);
8173 pxw[i] = val;
8174 }
8175 /* Render standby states get 0 weight */
8176 pxw[14] = 0;
8177 pxw[15] = 0;
8178
8179 for (i = 0; i < 4; i++) {
8180 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
8181 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
8182 I915_WRITE(PXW + (i * 4), val);
8183 }
8184
8185 /* Adjust magic regs to magic values (more experimental results) */
8186 I915_WRITE(OGW0, 0);
8187 I915_WRITE(OGW1, 0);
8188 I915_WRITE(EG0, 0x00007f00);
8189 I915_WRITE(EG1, 0x0000000e);
8190 I915_WRITE(EG2, 0x000e0000);
8191 I915_WRITE(EG3, 0x68000300);
8192 I915_WRITE(EG4, 0x42000000);
8193 I915_WRITE(EG5, 0x00140031);
8194 I915_WRITE(EG6, 0);
8195 I915_WRITE(EG7, 0);
8196
8197 for (i = 0; i < 8; i++)
8198 I915_WRITE(PXWL + (i * 4), 0);
8199
8200 /* Enable PMON + select events */
8201 I915_WRITE(ECR, 0x80000019);
8202
8203 lcfuse = I915_READ(LCFUSE02);
8204
8205 dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
8206}
8207
c0f372b3
KP		 8208static bool intel_enable_rc6(struct drm_device *dev)
8209{
8210 /*
8211 * Respect the kernel parameter if it is set
8212 */
8213 if (i915_enable_rc6 >= 0)
8214 return i915_enable_rc6;
8215
8216 /*
8217 * Disable RC6 on Ironlake
8218 */
8219 if (INTEL_INFO(dev)->gen == 5)
8220 return 0;
8221
8222 /*
371de6e4 8223 * Disable rc6 on Sandybridge
c0f372b3
KP		 8224 */
8225 if (INTEL_INFO(dev)->gen == 6) {
371de6e4
KP		 8226 DRM_DEBUG_DRIVER("Sandybridge: RC6 disabled\n");
8227 return 0;
c0f372b3
KP		 8228 }
8229 DRM_DEBUG_DRIVER("RC6 enabled\n");
8230 return 1;
8231}
8232
3b8d8d91 8233void gen6_enable_rps(struct drm_i915_private *dev_priv)
8fd26859 8234{
a6044e23
JB		 8235 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
8236 u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
7df8721b 8237 u32 pcu_mbox, rc6_mask = 0;
dd202c6d 8238 u32 gtfifodbg;
a6044e23 8239 int cur_freq, min_freq, max_freq;
8fd26859
CW		 8240 int i;
8241
8242 /* Here begins a magic sequence of register writes to enable
8243 * auto-downclocking.
8244 *
8245 * Perhaps there might be some value in exposing these to
8246 * userspace...
8247 */
8248 I915_WRITE(GEN6_RC_STATE, 0);
d1ebd816 8249 mutex_lock(&dev_priv->dev->struct_mutex);
dd202c6d
BW		 8250
8251 /* Clear the DBG now so we don't confuse earlier errors */
8252 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
8253 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
8254 I915_WRITE(GTFIFODBG, gtfifodbg);
8255 }
8256
fcca7926 8257 gen6_gt_force_wake_get(dev_priv);
8fd26859 8258
3b8d8d91 8259 /* disable the counters and set deterministic thresholds */
8fd26859
CW		 8260 I915_WRITE(GEN6_RC_CONTROL, 0);
8261
8262 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
8263 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
8264 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
8265 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
8266 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
8267
8268 for (i = 0; i < I915_NUM_RINGS; i++)
8269 I915_WRITE(RING_MAX_IDLE(dev_priv->ring[i].mmio_base), 10);
8270
8271 I915_WRITE(GEN6_RC_SLEEP, 0);
8272 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
8273 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
8274 I915_WRITE(GEN6_RC6p_THRESHOLD, 100000);
8275 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
8276
c0f372b3 8277 if (intel_enable_rc6(dev_priv->dev))
7df8721b
JB		 8278 rc6_mask = GEN6_RC_CTL_RC6p_ENABLE |
8279 GEN6_RC_CTL_RC6_ENABLE;
8280
8fd26859 8281 I915_WRITE(GEN6_RC_CONTROL,
7df8721b 8282 rc6_mask |
9c3d2f7f 8283 GEN6_RC_CTL_EI_MODE(1) |
8fd26859
CW		 8284 GEN6_RC_CTL_HW_ENABLE);
8285
3b8d8d91 8286 I915_WRITE(GEN6_RPNSWREQ,
8fd26859
CW		 8287 GEN6_FREQUENCY(10) |
8288 GEN6_OFFSET(0) |
8289 GEN6_AGGRESSIVE_TURBO);
8290 I915_WRITE(GEN6_RC_VIDEO_FREQ,
8291 GEN6_FREQUENCY(12));
8292
8293 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
8294 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
8295 18 << 24 |
8296 6 << 16);
ccab5c82
JB		 8297 I915_WRITE(GEN6_RP_UP_THRESHOLD, 10000);
8298 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 1000000);
8fd26859 8299 I915_WRITE(GEN6_RP_UP_EI, 100000);
ccab5c82 8300 I915_WRITE(GEN6_RP_DOWN_EI, 5000000);
8fd26859
CW		 8301 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
8302 I915_WRITE(GEN6_RP_CONTROL,
8303 GEN6_RP_MEDIA_TURBO |
6ed55ee7 8304 GEN6_RP_MEDIA_HW_MODE |
8fd26859
CW		 8305 GEN6_RP_MEDIA_IS_GFX |
8306 GEN6_RP_ENABLE |
ccab5c82
JB		 8307 GEN6_RP_UP_BUSY_AVG |
8308 GEN6_RP_DOWN_IDLE_CONT);
8fd26859
CW		 8309
8310 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
8311 500))
8312 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
8313
8314 I915_WRITE(GEN6_PCODE_DATA, 0);
8315 I915_WRITE(GEN6_PCODE_MAILBOX,
8316 GEN6_PCODE_READY |
8317 GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
8318 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
8319 500))
8320 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
8321
a6044e23
JB		 8322 min_freq = (rp_state_cap & 0xff0000) >> 16;
8323 max_freq = rp_state_cap & 0xff;
8324 cur_freq = (gt_perf_status & 0xff00) >> 8;
8325
8326 /* Check for overclock support */
8327 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
8328 500))
8329 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
8330 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_READ_OC_PARAMS);
8331 pcu_mbox = I915_READ(GEN6_PCODE_DATA);
8332 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
8333 500))
8334 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
8335 if (pcu_mbox & (1<<31)) { /* OC supported */
8336 max_freq = pcu_mbox & 0xff;
e281fcaa 8337 DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 50);
a6044e23
JB		 8338 }
8339
8340 /* In units of 100MHz */
8341 dev_priv->max_delay = max_freq;
8342 dev_priv->min_delay = min_freq;
8343 dev_priv->cur_delay = cur_freq;
8344
8fd26859
CW		 8345 /* requires MSI enabled */
8346 I915_WRITE(GEN6_PMIER,
8347 GEN6_PM_MBOX_EVENT |
8348 GEN6_PM_THERMAL_EVENT |
8349 GEN6_PM_RP_DOWN_TIMEOUT |
8350 GEN6_PM_RP_UP_THRESHOLD |
8351 GEN6_PM_RP_DOWN_THRESHOLD |
8352 GEN6_PM_RP_UP_EI_EXPIRED |
8353 GEN6_PM_RP_DOWN_EI_EXPIRED);
4912d041
BW		 8354 spin_lock_irq(&dev_priv->rps_lock);
8355 WARN_ON(dev_priv->pm_iir != 0);
3b8d8d91 8356 I915_WRITE(GEN6_PMIMR, 0);
4912d041 8357 spin_unlock_irq(&dev_priv->rps_lock);
3b8d8d91
JB		 8358 /* enable all PM interrupts */
8359 I915_WRITE(GEN6_PMINTRMSK, 0);
8fd26859 8360
fcca7926 8361 gen6_gt_force_wake_put(dev_priv);
d1ebd816 8362 mutex_unlock(&dev_priv->dev->struct_mutex);
8fd26859
CW		 8363}
8364
23b2f8bb
JB		 8365void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
8366{
8367 int min_freq = 15;
8368 int gpu_freq, ia_freq, max_ia_freq;
8369 int scaling_factor = 180;
8370
8371 max_ia_freq = cpufreq_quick_get_max(0);
8372 /*
8373 * Default to measured freq if none found, PCU will ensure we don't go
8374 * over
8375 */
8376 if (!max_ia_freq)
8377 max_ia_freq = tsc_khz;
8378
8379 /* Convert from kHz to MHz */
8380 max_ia_freq /= 1000;
8381
8382 mutex_lock(&dev_priv->dev->struct_mutex);
8383
8384 /*
8385 * For each potential GPU frequency, load a ring frequency we'd like
8386 * to use for memory access. We do this by specifying the IA frequency
8387 * the PCU should use as a reference to determine the ring frequency.
8388 */
8389 for (gpu_freq = dev_priv->max_delay; gpu_freq >= dev_priv->min_delay;
8390 gpu_freq--) {
8391 int diff = dev_priv->max_delay - gpu_freq;
8392
8393 /*
8394 * For GPU frequencies less than 750MHz, just use the lowest
8395 * ring freq.
8396 */
8397 if (gpu_freq < min_freq)
8398 ia_freq = 800;
8399 else
8400 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
8401 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
8402
8403 I915_WRITE(GEN6_PCODE_DATA,
8404 (ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT) |
8405 gpu_freq);
8406 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY |
8407 GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
8408 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) &
8409 GEN6_PCODE_READY) == 0, 10)) {
8410 DRM_ERROR("pcode write of freq table timed out\n");
8411 continue;
8412 }
8413 }
8414
8415 mutex_unlock(&dev_priv->dev->struct_mutex);
8416}
8417
6067aaea
JB		 8418static void ironlake_init_clock_gating(struct drm_device *dev)
8419{
8420 struct drm_i915_private *dev_priv = dev->dev_private;
8421 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
8422
8423 /* Required for FBC */
8424 dspclk_gate |= DPFCUNIT_CLOCK_GATE_DISABLE |
8425 DPFCRUNIT_CLOCK_GATE_DISABLE |
8426 DPFDUNIT_CLOCK_GATE_DISABLE;
8427 /* Required for CxSR */
8428 dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
8429
8430 I915_WRITE(PCH_3DCGDIS0,
8431 MARIUNIT_CLOCK_GATE_DISABLE |
8432 SVSMUNIT_CLOCK_GATE_DISABLE);
8433 I915_WRITE(PCH_3DCGDIS1,
8434 VFMUNIT_CLOCK_GATE_DISABLE);
8435
8436 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
8437
6067aaea
JB		 8438 /*
8439 * According to the spec the following bits should be set in
8440 * order to enable memory self-refresh
8441 * The bit 22/21 of 0x42004
8442 * The bit 5 of 0x42020
8443 * The bit 15 of 0x45000
8444 */
8445 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8446 (I915_READ(ILK_DISPLAY_CHICKEN2) |
8447 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
8448 I915_WRITE(ILK_DSPCLK_GATE,
8449 (I915_READ(ILK_DSPCLK_GATE) |
8450 ILK_DPARB_CLK_GATE));
8451 I915_WRITE(DISP_ARB_CTL,
8452 (I915_READ(DISP_ARB_CTL) |
8453 DISP_FBC_WM_DIS));
8454 I915_WRITE(WM3_LP_ILK, 0);
8455 I915_WRITE(WM2_LP_ILK, 0);
8456 I915_WRITE(WM1_LP_ILK, 0);
8457
8458 /*
8459 * Based on the document from hardware guys the following bits
8460 * should be set unconditionally in order to enable FBC.
8461 * The bit 22 of 0x42000
8462 * The bit 22 of 0x42004
8463 * The bit 7,8,9 of 0x42020.
8464 */
8465 if (IS_IRONLAKE_M(dev)) {
8466 I915_WRITE(ILK_DISPLAY_CHICKEN1,
8467 I915_READ(ILK_DISPLAY_CHICKEN1) |
8468 ILK_FBCQ_DIS);
8469 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8470 I915_READ(ILK_DISPLAY_CHICKEN2) |
8471 ILK_DPARB_GATE);
8472 I915_WRITE(ILK_DSPCLK_GATE,
8473 I915_READ(ILK_DSPCLK_GATE) |
8474 ILK_DPFC_DIS1 |
8475 ILK_DPFC_DIS2 |
8476 ILK_CLK_FBC);
8477 }
8478
8479 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8480 I915_READ(ILK_DISPLAY_CHICKEN2) |
8481 ILK_ELPIN_409_SELECT);
8482 I915_WRITE(_3D_CHICKEN2,
8483 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
8484 _3D_CHICKEN2_WM_READ_PIPELINED);
8fd26859
CW		 8485}
8486
6067aaea 8487static void gen6_init_clock_gating(struct drm_device *dev)
652c393a
JB		 8488{
8489 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 8490 int pipe;
6067aaea
JB		 8491 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
8492
8493 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
652c393a 8494
6067aaea
JB		 8495 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8496 I915_READ(ILK_DISPLAY_CHICKEN2) |
8497 ILK_ELPIN_409_SELECT);
8956c8bb 8498
6067aaea
JB		 8499 I915_WRITE(WM3_LP_ILK, 0);
8500 I915_WRITE(WM2_LP_ILK, 0);
8501 I915_WRITE(WM1_LP_ILK, 0);
652c393a 8502
406478dc
EA		 8503 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
8504 * gating disable must be set. Failure to set it results in
8505 * flickering pixels due to Z write ordering failures after
8506 * some amount of runtime in the Mesa "fire" demo, and Unigine
8507 * Sanctuary and Tropics, and apparently anything else with
8508 * alpha test or pixel discard.
9ca1d10d
EA		 8509 *
8510 * According to the spec, bit 11 (RCCUNIT) must also be set,
8511 * but we didn't debug actual testcases to find it out.
406478dc 8512 */
9ca1d10d
EA		 8513 I915_WRITE(GEN6_UCGCTL2,
8514 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
8515 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
406478dc 8516
652c393a 8517 /*
6067aaea
JB		 8518 * According to the spec the following bits should be
8519 * set in order to enable memory self-refresh and fbc:
8520 * The bit21 and bit22 of 0x42000
8521 * The bit21 and bit22 of 0x42004
8522 * The bit5 and bit7 of 0x42020
8523 * The bit14 of 0x70180
8524 * The bit14 of 0x71180
652c393a 8525 */
6067aaea
JB		 8526 I915_WRITE(ILK_DISPLAY_CHICKEN1,
8527 I915_READ(ILK_DISPLAY_CHICKEN1) |
8528 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
8529 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8530 I915_READ(ILK_DISPLAY_CHICKEN2) |
8531 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
8532 I915_WRITE(ILK_DSPCLK_GATE,
8533 I915_READ(ILK_DSPCLK_GATE) |
8534 ILK_DPARB_CLK_GATE |
8535 ILK_DPFD_CLK_GATE);
8956c8bb 8536
d74362c9 8537 for_each_pipe(pipe) {
6067aaea
JB		 8538 I915_WRITE(DSPCNTR(pipe),
8539 I915_READ(DSPCNTR(pipe)) |
8540 DISPPLANE_TRICKLE_FEED_DISABLE);
d74362c9
KP		 8541 intel_flush_display_plane(dev_priv, pipe);
8542 }
6067aaea 8543}
8956c8bb 8544
28963a3e
JB		 8545static void ivybridge_init_clock_gating(struct drm_device *dev)
8546{
8547 struct drm_i915_private *dev_priv = dev->dev_private;
8548 int pipe;
8549 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
7f8a8569 8550
28963a3e 8551 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
382b0936 8552
28963a3e
JB		 8553 I915_WRITE(WM3_LP_ILK, 0);
8554 I915_WRITE(WM2_LP_ILK, 0);
8555 I915_WRITE(WM1_LP_ILK, 0);
de6e2eaf 8556
28963a3e 8557 I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE);
67e92af0 8558
116ac8d2
EA		 8559 I915_WRITE(IVB_CHICKEN3,
8560 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
8561 CHICKEN3_DGMG_DONE_FIX_DISABLE);
8562
d74362c9 8563 for_each_pipe(pipe) {
28963a3e
JB		 8564 I915_WRITE(DSPCNTR(pipe),
8565 I915_READ(DSPCNTR(pipe)) |
8566 DISPPLANE_TRICKLE_FEED_DISABLE);
d74362c9
KP		 8567 intel_flush_display_plane(dev_priv, pipe);
8568 }
28963a3e
JB		 8569}
8570
6067aaea
JB		 8571static void g4x_init_clock_gating(struct drm_device *dev)
8572{
8573 struct drm_i915_private *dev_priv = dev->dev_private;
8574 uint32_t dspclk_gate;
8fd26859 8575
6067aaea
JB		 8576 I915_WRITE(RENCLK_GATE_D1, 0);
8577 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
8578 GS_UNIT_CLOCK_GATE_DISABLE |
8579 CL_UNIT_CLOCK_GATE_DISABLE);
8580 I915_WRITE(RAMCLK_GATE_D, 0);
8581 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
8582 OVRUNIT_CLOCK_GATE_DISABLE |
8583 OVCUNIT_CLOCK_GATE_DISABLE;
8584 if (IS_GM45(dev))
8585 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
8586 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
8587}
1398261a 8588
6067aaea
JB		 8589static void crestline_init_clock_gating(struct drm_device *dev)
8590{
8591 struct drm_i915_private *dev_priv = dev->dev_private;
652c393a 8592
6067aaea
JB		 8593 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
8594 I915_WRITE(RENCLK_GATE_D2, 0);
8595 I915_WRITE(DSPCLK_GATE_D, 0);
8596 I915_WRITE(RAMCLK_GATE_D, 0);
8597 I915_WRITE16(DEUC, 0);
8598}
652c393a 8599
6067aaea
JB		 8600static void broadwater_init_clock_gating(struct drm_device *dev)
8601{
8602 struct drm_i915_private *dev_priv = dev->dev_private;
8603
8604 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
8605 I965_RCC_CLOCK_GATE_DISABLE |
8606 I965_RCPB_CLOCK_GATE_DISABLE |
8607 I965_ISC_CLOCK_GATE_DISABLE |
8608 I965_FBC_CLOCK_GATE_DISABLE);
8609 I915_WRITE(RENCLK_GATE_D2, 0);
8610}
8611
8612static void gen3_init_clock_gating(struct drm_device *dev)
8613{
8614 struct drm_i915_private *dev_priv = dev->dev_private;
8615 u32 dstate = I915_READ(D_STATE);
8616
8617 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
8618 DSTATE_DOT_CLOCK_GATING;
8619 I915_WRITE(D_STATE, dstate);
8620}
8621
8622static void i85x_init_clock_gating(struct drm_device *dev)
8623{
8624 struct drm_i915_private *dev_priv = dev->dev_private;
8625
8626 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
8627}
8628
8629static void i830_init_clock_gating(struct drm_device *dev)
8630{
8631 struct drm_i915_private *dev_priv = dev->dev_private;
8632
8633 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
652c393a
JB		 8634}
8635
645c62a5
JB		 8636static void ibx_init_clock_gating(struct drm_device *dev)
8637{
8638 struct drm_i915_private *dev_priv = dev->dev_private;
8639
8640 /*
8641 * On Ibex Peak and Cougar Point, we need to disable clock
8642 * gating for the panel power sequencer or it will fail to
8643 * start up when no ports are active.
8644 */
8645 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
8646}
8647
8648static void cpt_init_clock_gating(struct drm_device *dev)
8649{
8650 struct drm_i915_private *dev_priv = dev->dev_private;
3bcf603f 8651 int pipe;
645c62a5
JB		 8652
8653 /*
8654 * On Ibex Peak and Cougar Point, we need to disable clock
8655 * gating for the panel power sequencer or it will fail to
8656 * start up when no ports are active.
8657 */
8658 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
8659 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
8660 DPLS_EDP_PPS_FIX_DIS);
3bcf603f
JB		 8661 /* Without this, mode sets may fail silently on FDI */
8662 for_each_pipe(pipe)
8663 I915_WRITE(TRANS_CHICKEN2(pipe), TRANS_AUTOTRAIN_GEN_STALL_DIS);
652c393a
JB		 8664}
8665
ac668088 8666static void ironlake_teardown_rc6(struct drm_device *dev)
0cdab21f
CW		 8667{
8668 struct drm_i915_private *dev_priv = dev->dev_private;
8669
8670 if (dev_priv->renderctx) {
ac668088
CW		 8671 i915_gem_object_unpin(dev_priv->renderctx);
8672 drm_gem_object_unreference(&dev_priv->renderctx->base);
0cdab21f
CW		 8673 dev_priv->renderctx = NULL;
8674 }
8675
8676 if (dev_priv->pwrctx) {
ac668088
CW		 8677 i915_gem_object_unpin(dev_priv->pwrctx);
8678 drm_gem_object_unreference(&dev_priv->pwrctx->base);
8679 dev_priv->pwrctx = NULL;
8680 }
8681}
8682
8683static void ironlake_disable_rc6(struct drm_device *dev)
8684{
8685 struct drm_i915_private *dev_priv = dev->dev_private;
8686
8687 if (I915_READ(PWRCTXA)) {
8688 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
8689 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
8690 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
8691 50);
0cdab21f
CW		 8692
8693 I915_WRITE(PWRCTXA, 0);
8694 POSTING_READ(PWRCTXA);
8695
ac668088
CW		 8696 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
8697 POSTING_READ(RSTDBYCTL);
0cdab21f 8698 }
ac668088 8699
99507307 8700 ironlake_teardown_rc6(dev);
0cdab21f
CW		 8701}
8702
ac668088 8703static int ironlake_setup_rc6(struct drm_device *dev)
d5bb081b
JB		 8704{
8705 struct drm_i915_private *dev_priv = dev->dev_private;
8706
ac668088
CW		 8707 if (dev_priv->renderctx == NULL)
8708 dev_priv->renderctx = intel_alloc_context_page(dev);
8709 if (!dev_priv->renderctx)
8710 return -ENOMEM;
8711
8712 if (dev_priv->pwrctx == NULL)
8713 dev_priv->pwrctx = intel_alloc_context_page(dev);
8714 if (!dev_priv->pwrctx) {
8715 ironlake_teardown_rc6(dev);
8716 return -ENOMEM;
8717 }
8718
8719 return 0;
d5bb081b
JB		 8720}
8721
8722void ironlake_enable_rc6(struct drm_device *dev)
8723{
8724 struct drm_i915_private *dev_priv = dev->dev_private;
8725 int ret;
8726
ac668088
CW		 8727 /* rc6 disabled by default due to repeated reports of hanging during
8728 * boot and resume.
8729 */
c0f372b3 8730 if (!intel_enable_rc6(dev))
ac668088
CW		 8731 return;
8732
2c34b850 8733 mutex_lock(&dev->struct_mutex);
ac668088 8734 ret = ironlake_setup_rc6(dev);
2c34b850
BW		 8735 if (ret) {
8736 mutex_unlock(&dev->struct_mutex);
ac668088 8737 return;
2c34b850 8738 }
ac668088 8739
d5bb081b
JB		 8740 /*
8741 * GPU can automatically power down the render unit if given a page
8742 * to save state.
8743 */
8744 ret = BEGIN_LP_RING(6);
8745 if (ret) {
ac668088 8746 ironlake_teardown_rc6(dev);
2c34b850 8747 mutex_unlock(&dev->struct_mutex);
d5bb081b
JB		 8748 return;
8749 }
ac668088 8750
d5bb081b
JB		 8751 OUT_RING(MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
8752 OUT_RING(MI_SET_CONTEXT);
8753 OUT_RING(dev_priv->renderctx->gtt_offset |
8754 MI_MM_SPACE_GTT |
8755 MI_SAVE_EXT_STATE_EN |
8756 MI_RESTORE_EXT_STATE_EN |
8757 MI_RESTORE_INHIBIT);
8758 OUT_RING(MI_SUSPEND_FLUSH);
8759 OUT_RING(MI_NOOP);
8760 OUT_RING(MI_FLUSH);
8761 ADVANCE_LP_RING();
8762
4a246cfc
BW		 8763 /*
8764 * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
8765 * does an implicit flush, combined with MI_FLUSH above, it should be
8766 * safe to assume that renderctx is valid
8767 */
8768 ret = intel_wait_ring_idle(LP_RING(dev_priv));
8769 if (ret) {
8770 DRM_ERROR("failed to enable ironlake power power savings\n");
8771 ironlake_teardown_rc6(dev);
8772 mutex_unlock(&dev->struct_mutex);
8773 return;
8774 }
8775
d5bb081b
JB		 8776 I915_WRITE(PWRCTXA, dev_priv->pwrctx->gtt_offset | PWRCTX_EN);
8777 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
2c34b850 8778 mutex_unlock(&dev->struct_mutex);
d5bb081b
JB		 8779}
8780
645c62a5
JB		 8781void intel_init_clock_gating(struct drm_device *dev)
8782{
8783 struct drm_i915_private *dev_priv = dev->dev_private;
8784
8785 dev_priv->display.init_clock_gating(dev);
8786
8787 if (dev_priv->display.init_pch_clock_gating)
8788 dev_priv->display.init_pch_clock_gating(dev);
8789}
ac668088 8790
e70236a8
JB		 8791/* Set up chip specific display functions */
8792static void intel_init_display(struct drm_device *dev)
8793{
8794 struct drm_i915_private *dev_priv = dev->dev_private;
8795
8796 /* We always want a DPMS function */
f564048e 8797 if (HAS_PCH_SPLIT(dev)) {
f2b115e6 8798 dev_priv->display.dpms = ironlake_crtc_dpms;
f564048e 8799 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
17638cd6 8800 dev_priv->display.update_plane = ironlake_update_plane;
f564048e 8801 } else {
e70236a8 8802 dev_priv->display.dpms = i9xx_crtc_dpms;
f564048e 8803 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
17638cd6 8804 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 8805 }
e70236a8 8806
ee5382ae 8807 if (I915_HAS_FBC(dev)) {
9c04f015 8808 if (HAS_PCH_SPLIT(dev)) {
b52eb4dc
ZY		 8809 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
8810 dev_priv->display.enable_fbc = ironlake_enable_fbc;
8811 dev_priv->display.disable_fbc = ironlake_disable_fbc;
8812 } else if (IS_GM45(dev)) {
74dff282
JB		 8813 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
8814 dev_priv->display.enable_fbc = g4x_enable_fbc;
8815 dev_priv->display.disable_fbc = g4x_disable_fbc;
a6c45cf0 8816 } else if (IS_CRESTLINE(dev)) {
e70236a8
JB		 8817 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
8818 dev_priv->display.enable_fbc = i8xx_enable_fbc;
8819 dev_priv->display.disable_fbc = i8xx_disable_fbc;
8820 }
74dff282 8821 /* 855GM needs testing */
e70236a8
JB		 8822 }
8823
8824 /* Returns the core display clock speed */
0206e353 8825 if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 8826 dev_priv->display.get_display_clock_speed =
8827 i945_get_display_clock_speed;
8828 else if (IS_I915G(dev))
8829 dev_priv->display.get_display_clock_speed =
8830 i915_get_display_clock_speed;
f2b115e6 8831 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
e70236a8
JB		 8832 dev_priv->display.get_display_clock_speed =
8833 i9xx_misc_get_display_clock_speed;
8834 else if (IS_I915GM(dev))
8835 dev_priv->display.get_display_clock_speed =
8836 i915gm_get_display_clock_speed;
8837 else if (IS_I865G(dev))
8838 dev_priv->display.get_display_clock_speed =
8839 i865_get_display_clock_speed;
f0f8a9ce 8840 else if (IS_I85X(dev))
e70236a8
JB		 8841 dev_priv->display.get_display_clock_speed =
8842 i855_get_display_clock_speed;
8843 else /* 852, 830 */
8844 dev_priv->display.get_display_clock_speed =
8845 i830_get_display_clock_speed;
8846
8847 /* For FIFO watermark updates */
7f8a8569 8848 if (HAS_PCH_SPLIT(dev)) {
8d715f00
KP		 8849 dev_priv->display.force_wake_get = __gen6_gt_force_wake_get;
8850 dev_priv->display.force_wake_put = __gen6_gt_force_wake_put;
8851
8852 /* IVB configs may use multi-threaded forcewake */
8853 if (IS_IVYBRIDGE(dev)) {
8854 u32 ecobus;
8855
c7dffff7
KP		 8856 /* A small trick here - if the bios hasn't configured MT forcewake,
8857 * and if the device is in RC6, then force_wake_mt_get will not wake
8858 * the device and the ECOBUS read will return zero. Which will be
8859 * (correctly) interpreted by the test below as MT forcewake being
8860 * disabled.
8861 */
8d715f00
KP		 8862 mutex_lock(&dev->struct_mutex);
8863 __gen6_gt_force_wake_mt_get(dev_priv);
c7dffff7 8864 ecobus = I915_READ_NOTRACE(ECOBUS);
8d715f00
KP		 8865 __gen6_gt_force_wake_mt_put(dev_priv);
8866 mutex_unlock(&dev->struct_mutex);
8867
8868 if (ecobus & FORCEWAKE_MT_ENABLE) {
8869 DRM_DEBUG_KMS("Using MT version of forcewake\n");
8870 dev_priv->display.force_wake_get =
8871 __gen6_gt_force_wake_mt_get;
8872 dev_priv->display.force_wake_put =
8873 __gen6_gt_force_wake_mt_put;
8874 }
8875 }
8876
645c62a5
JB		 8877 if (HAS_PCH_IBX(dev))
8878 dev_priv->display.init_pch_clock_gating = ibx_init_clock_gating;
8879 else if (HAS_PCH_CPT(dev))
8880 dev_priv->display.init_pch_clock_gating = cpt_init_clock_gating;
8881
f00a3ddf 8882 if (IS_GEN5(dev)) {
7f8a8569
ZW		 8883 if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
8884 dev_priv->display.update_wm = ironlake_update_wm;
8885 else {
8886 DRM_DEBUG_KMS("Failed to get proper latency. "
8887 "Disable CxSR\n");
8888 dev_priv->display.update_wm = NULL;
1398261a 8889 }
674cf967 8890 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
6067aaea 8891 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
e0dac65e 8892 dev_priv->display.write_eld = ironlake_write_eld;
1398261a
YL		 8893 } else if (IS_GEN6(dev)) {
8894 if (SNB_READ_WM0_LATENCY()) {
8895 dev_priv->display.update_wm = sandybridge_update_wm;
b840d907 8896 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
1398261a
YL		 8897 } else {
8898 DRM_DEBUG_KMS("Failed to read display plane latency. "
8899 "Disable CxSR\n");
8900 dev_priv->display.update_wm = NULL;
7f8a8569 8901 }
674cf967 8902 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
6067aaea 8903 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
e0dac65e 8904 dev_priv->display.write_eld = ironlake_write_eld;
357555c0
JB		 8905 } else if (IS_IVYBRIDGE(dev)) {
8906 /* FIXME: detect B0+ stepping and use auto training */
8907 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
fe100d4d
JB		 8908 if (SNB_READ_WM0_LATENCY()) {
8909 dev_priv->display.update_wm = sandybridge_update_wm;
b840d907 8910 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
fe100d4d
JB		 8911 } else {
8912 DRM_DEBUG_KMS("Failed to read display plane latency. "
8913 "Disable CxSR\n");
8914 dev_priv->display.update_wm = NULL;
8915 }
28963a3e 8916 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
e0dac65e 8917 dev_priv->display.write_eld = ironlake_write_eld;
7f8a8569
ZW		 8918 } else
8919 dev_priv->display.update_wm = NULL;
8920 } else if (IS_PINEVIEW(dev)) {
d4294342 8921 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
95534263 8922 dev_priv->is_ddr3,
d4294342
ZY		 8923 dev_priv->fsb_freq,
8924 dev_priv->mem_freq)) {
8925 DRM_INFO("failed to find known CxSR latency "
95534263 8926 "(found ddr%s fsb freq %d, mem freq %d), "
d4294342 8927 "disabling CxSR\n",
0206e353 8928 (dev_priv->is_ddr3 == 1) ? "3" : "2",
d4294342
ZY		 8929 dev_priv->fsb_freq, dev_priv->mem_freq);
8930 /* Disable CxSR and never update its watermark again */
8931 pineview_disable_cxsr(dev);
8932 dev_priv->display.update_wm = NULL;
8933 } else
8934 dev_priv->display.update_wm = pineview_update_wm;
95e0ee92 8935 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
6067aaea 8936 } else if (IS_G4X(dev)) {
e0dac65e 8937 dev_priv->display.write_eld = g4x_write_eld;
e70236a8 8938 dev_priv->display.update_wm = g4x_update_wm;
6067aaea
JB		 8939 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
8940 } else if (IS_GEN4(dev)) {
e70236a8 8941 dev_priv->display.update_wm = i965_update_wm;
6067aaea
JB		 8942 if (IS_CRESTLINE(dev))
8943 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
8944 else if (IS_BROADWATER(dev))
8945 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
8946 } else if (IS_GEN3(dev)) {
e70236a8
JB		 8947 dev_priv->display.update_wm = i9xx_update_wm;
8948 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
6067aaea
JB		 8949 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
8950 } else if (IS_I865G(dev)) {
8951 dev_priv->display.update_wm = i830_update_wm;
8952 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
8953 dev_priv->display.get_fifo_size = i830_get_fifo_size;
8f4695ed
AJ		 8954 } else if (IS_I85X(dev)) {
8955 dev_priv->display.update_wm = i9xx_update_wm;
8956 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
6067aaea 8957 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
e70236a8 8958 } else {
8f4695ed 8959 dev_priv->display.update_wm = i830_update_wm;
6067aaea 8960 dev_priv->display.init_clock_gating = i830_init_clock_gating;
8f4695ed 8961 if (IS_845G(dev))
e70236a8
JB		 8962 dev_priv->display.get_fifo_size = i845_get_fifo_size;
8963 else
8964 dev_priv->display.get_fifo_size = i830_get_fifo_size;
e70236a8 8965 }
8c9f3aaf
JB		 8966
8967 /* Default just returns -ENODEV to indicate unsupported */
8968 dev_priv->display.queue_flip = intel_default_queue_flip;
8969
8970 switch (INTEL_INFO(dev)->gen) {
8971 case 2:
8972 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8973 break;
8974
8975 case 3:
8976 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8977 break;
8978
8979 case 4:
8980 case 5:
8981 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8982 break;
8983
8984 case 6:
8985 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8986 break;
7c9017e5
JB		 8987 case 7:
8988 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8989 break;
8c9f3aaf 8990 }
e70236a8
JB		 8991}
8992
b690e96c
JB		 8993/*
8994 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8995 * resume, or other times. This quirk makes sure that's the case for
8996 * affected systems.
8997 */
0206e353 8998static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 8999{
9000 struct drm_i915_private *dev_priv = dev->dev_private;
9001
9002 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
9003 DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
9004}
9005
435793df
KP		 9006/*
9007 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
9008 */
9009static void quirk_ssc_force_disable(struct drm_device *dev)
9010{
9011 struct drm_i915_private *dev_priv = dev->dev_private;
9012 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
9013}
9014
b690e96c
JB		 9015struct intel_quirk {
9016 int device;
9017 int subsystem_vendor;
9018 int subsystem_device;
9019 void (*hook)(struct drm_device *dev);
9020};
9021
9022struct intel_quirk intel_quirks[] = {
b690e96c 9023 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 9024 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c
JB		 9025
9026 /* Thinkpad R31 needs pipe A force quirk */
9027 { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
9028 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
9029 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
9030
9031 /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
9032 { 0x3577, 0x1014, 0x0513, quirk_pipea_force },
9033 /* ThinkPad X40 needs pipe A force quirk */
9034
9035 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
9036 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
9037
9038 /* 855 & before need to leave pipe A & dpll A up */
9039 { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
9040 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
435793df
KP		 9041
9042 /* Lenovo U160 cannot use SSC on LVDS */
9043 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 9044
9045 /* Sony Vaio Y cannot use SSC on LVDS */
9046 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
b690e96c
JB		 9047};
9048
9049static void intel_init_quirks(struct drm_device *dev)
9050{
9051 struct pci_dev *d = dev->pdev;
9052 int i;
9053
9054 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
9055 struct intel_quirk *q = &intel_quirks[i];
9056
9057 if (d->device == q->device &&
9058 (d->subsystem_vendor == q->subsystem_vendor ||
9059 q->subsystem_vendor == PCI_ANY_ID) &&
9060 (d->subsystem_device == q->subsystem_device ||
9061 q->subsystem_device == PCI_ANY_ID))
9062 q->hook(dev);
9063 }
9064}
9065
9cce37f4
JB		 9066/* Disable the VGA plane that we never use */
9067static void i915_disable_vga(struct drm_device *dev)
9068{
9069 struct drm_i915_private *dev_priv = dev->dev_private;
9070 u8 sr1;
9071 u32 vga_reg;
9072
9073 if (HAS_PCH_SPLIT(dev))
9074 vga_reg = CPU_VGACNTRL;
9075 else
9076 vga_reg = VGACNTRL;
9077
9078 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
9079 outb(1, VGA_SR_INDEX);
9080 sr1 = inb(VGA_SR_DATA);
9081 outb(sr1 | 1<<5, VGA_SR_DATA);
9082 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
9083 udelay(300);
9084
9085 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9086 POSTING_READ(vga_reg);
9087}
9088
79e53945
JB		 9089void intel_modeset_init(struct drm_device *dev)
9090{
652c393a 9091 struct drm_i915_private *dev_priv = dev->dev_private;
b840d907 9092 int i, ret;
79e53945
JB		 9093
9094 drm_mode_config_init(dev);
9095
9096 dev->mode_config.min_width = 0;
9097 dev->mode_config.min_height = 0;
9098
019d96cb
DA		 9099 dev->mode_config.preferred_depth = 24;
9100 dev->mode_config.prefer_shadow = 1;
9101
79e53945
JB		 9102 dev->mode_config.funcs = (void *)&intel_mode_funcs;
9103
b690e96c
JB		 9104 intel_init_quirks(dev);
9105
e70236a8
JB		 9106 intel_init_display(dev);
9107
a6c45cf0
CW		 9108 if (IS_GEN2(dev)) {
9109 dev->mode_config.max_width = 2048;
9110 dev->mode_config.max_height = 2048;
9111 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 9112 dev->mode_config.max_width = 4096;
9113 dev->mode_config.max_height = 4096;
79e53945 9114 } else {
a6c45cf0
CW		 9115 dev->mode_config.max_width = 8192;
9116 dev->mode_config.max_height = 8192;
79e53945 9117 }
35c3047a 9118 dev->mode_config.fb_base = dev->agp->base;
79e53945 9119
28c97730 9120 DRM_DEBUG_KMS("%d display pipe%s available.\n",
a3524f1b 9121 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
79e53945 9122
a3524f1b 9123 for (i = 0; i < dev_priv->num_pipe; i++) {
79e53945 9124 intel_crtc_init(dev, i);
00c2064b
JB		 9125 ret = intel_plane_init(dev, i);
9126 if (ret)
9127 DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
79e53945
JB		 9128 }
9129
9cce37f4
JB		 9130 /* Just disable it once at startup */
9131 i915_disable_vga(dev);
79e53945 9132 intel_setup_outputs(dev);
652c393a 9133
645c62a5 9134 intel_init_clock_gating(dev);
9cce37f4 9135
7648fa99 9136 if (IS_IRONLAKE_M(dev)) {
f97108d1 9137 ironlake_enable_drps(dev);
7648fa99
JB		 9138 intel_init_emon(dev);
9139 }
f97108d1 9140
1c70c0ce 9141 if (IS_GEN6(dev) || IS_GEN7(dev)) {
3b8d8d91 9142 gen6_enable_rps(dev_priv);
23b2f8bb
JB		 9143 gen6_update_ring_freq(dev_priv);
9144 }
3b8d8d91 9145
652c393a
JB		 9146 INIT_WORK(&dev_priv->idle_work, intel_idle_update);
9147 setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
9148 (unsigned long)dev);
2c7111db
CW		 9149}
9150
9151void intel_modeset_gem_init(struct drm_device *dev)
9152{
9153 if (IS_IRONLAKE_M(dev))
9154 ironlake_enable_rc6(dev);
02e792fb
DV		 9155
9156 intel_setup_overlay(dev);
79e53945
JB		 9157}
9158
9159void intel_modeset_cleanup(struct drm_device *dev)
9160{
652c393a
JB		 9161 struct drm_i915_private *dev_priv = dev->dev_private;
9162 struct drm_crtc *crtc;
9163 struct intel_crtc *intel_crtc;
9164
f87ea761 9165 drm_kms_helper_poll_fini(dev);
652c393a
JB		 9166 mutex_lock(&dev->struct_mutex);
9167
723bfd70
JB		 9168 intel_unregister_dsm_handler();
9169
9170
652c393a
JB		 9171 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9172 /* Skip inactive CRTCs */
9173 if (!crtc->fb)
9174 continue;
9175
9176 intel_crtc = to_intel_crtc(crtc);
3dec0095 9177 intel_increase_pllclock(crtc);
652c393a
JB		 9178 }
9179
973d04f9 9180 intel_disable_fbc(dev);
e70236a8 9181
f97108d1
JB		 9182 if (IS_IRONLAKE_M(dev))
9183 ironlake_disable_drps(dev);
1c70c0ce 9184 if (IS_GEN6(dev) || IS_GEN7(dev))
3b8d8d91 9185 gen6_disable_rps(dev);
f97108d1 9186
d5bb081b
JB		 9187 if (IS_IRONLAKE_M(dev))
9188 ironlake_disable_rc6(dev);
0cdab21f 9189
69341a5e
KH		 9190 mutex_unlock(&dev->struct_mutex);
9191
6c0d9350
DV		 9192 /* Disable the irq before mode object teardown, for the irq might
9193 * enqueue unpin/hotplug work. */
9194 drm_irq_uninstall(dev);
9195 cancel_work_sync(&dev_priv->hotplug_work);
6fdd4d98 9196 cancel_work_sync(&dev_priv->rps_work);
6c0d9350 9197
1630fe75
CW		 9198 /* flush any delayed tasks or pending work */
9199 flush_scheduled_work();
9200
3dec0095
DV		 9201 /* Shut off idle work before the crtcs get freed. */
9202 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9203 intel_crtc = to_intel_crtc(crtc);
9204 del_timer_sync(&intel_crtc->idle_timer);
9205 }
9206 del_timer_sync(&dev_priv->idle_timer);
9207 cancel_work_sync(&dev_priv->idle_work);
9208
79e53945
JB		 9209 drm_mode_config_cleanup(dev);
9210}
9211
f1c79df3
ZW		 9212/*
9213 * Return which encoder is currently attached for connector.
9214 */
df0e9248 9215struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 9216{
df0e9248
CW		 9217 return &intel_attached_encoder(connector)->base;
9218}
f1c79df3 9219
df0e9248
CW		 9220void intel_connector_attach_encoder(struct intel_connector *connector,
9221 struct intel_encoder *encoder)
9222{
9223 connector->encoder = encoder;
9224 drm_mode_connector_attach_encoder(&connector->base,
9225 &encoder->base);
79e53945 9226}
28d52043
DA		 9227
9228/*
9229 * set vga decode state - true == enable VGA decode
9230 */
9231int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9232{
9233 struct drm_i915_private *dev_priv = dev->dev_private;
9234 u16 gmch_ctrl;
9235
9236 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9237 if (state)
9238 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9239 else
9240 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9241 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9242 return 0;
9243}
c4a1d9e4
CW		 9244
9245#ifdef CONFIG_DEBUG_FS
9246#include <linux/seq_file.h>
9247
9248struct intel_display_error_state {
9249 struct intel_cursor_error_state {
9250 u32 control;
9251 u32 position;
9252 u32 base;
9253 u32 size;
9254 } cursor[2];
9255
9256 struct intel_pipe_error_state {
9257 u32 conf;
9258 u32 source;
9259
9260 u32 htotal;
9261 u32 hblank;
9262 u32 hsync;
9263 u32 vtotal;
9264 u32 vblank;
9265 u32 vsync;
9266 } pipe[2];
9267
9268 struct intel_plane_error_state {
9269 u32 control;
9270 u32 stride;
9271 u32 size;
9272 u32 pos;
9273 u32 addr;
9274 u32 surface;
9275 u32 tile_offset;
9276 } plane[2];
9277};
9278
9279struct intel_display_error_state *
9280intel_display_capture_error_state(struct drm_device *dev)
9281{
0206e353 9282 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4
CW		 9283 struct intel_display_error_state *error;
9284 int i;
9285
9286 error = kmalloc(sizeof(*error), GFP_ATOMIC);
9287 if (error == NULL)
9288 return NULL;
9289
9290 for (i = 0; i < 2; i++) {
9291 error->cursor[i].control = I915_READ(CURCNTR(i));
9292 error->cursor[i].position = I915_READ(CURPOS(i));
9293 error->cursor[i].base = I915_READ(CURBASE(i));
9294
9295 error->plane[i].control = I915_READ(DSPCNTR(i));
9296 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
9297 error->plane[i].size = I915_READ(DSPSIZE(i));
0206e353 9298 error->plane[i].pos = I915_READ(DSPPOS(i));
c4a1d9e4
CW		 9299 error->plane[i].addr = I915_READ(DSPADDR(i));
9300 if (INTEL_INFO(dev)->gen >= 4) {
9301 error->plane[i].surface = I915_READ(DSPSURF(i));
9302 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9303 }
9304
9305 error->pipe[i].conf = I915_READ(PIPECONF(i));
9306 error->pipe[i].source = I915_READ(PIPESRC(i));
9307 error->pipe[i].htotal = I915_READ(HTOTAL(i));
9308 error->pipe[i].hblank = I915_READ(HBLANK(i));
9309 error->pipe[i].hsync = I915_READ(HSYNC(i));
9310 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
9311 error->pipe[i].vblank = I915_READ(VBLANK(i));
9312 error->pipe[i].vsync = I915_READ(VSYNC(i));
9313 }
9314
9315 return error;
9316}
9317
9318void
9319intel_display_print_error_state(struct seq_file *m,
9320 struct drm_device *dev,
9321 struct intel_display_error_state *error)
9322{
9323 int i;
9324
9325 for (i = 0; i < 2; i++) {
9326 seq_printf(m, "Pipe [%d]:\n", i);
9327 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
9328 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
9329 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
9330 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
9331 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
9332 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
9333 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
9334 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
9335
9336 seq_printf(m, "Plane [%d]:\n", i);
9337 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
9338 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
9339 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
9340 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
9341 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
9342 if (INTEL_INFO(dev)->gen >= 4) {
9343 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
9344 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
9345 }
9346
9347 seq_printf(m, "Cursor [%d]:\n", i);
9348 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
9349 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
9350 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
9351 }
9352}
9353#endif
Linux kernel - Deliverables
This page took 1.032665 seconds and 5 git commands to generate.