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drm/i915: propagate errors from intel_dp_init_connector
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_dp.c
CommitLineData
a4fc5ed6
KP		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
2d1a8a48 30#include <linux/export.h>
760285e7
DH		 31#include <drm/drmP.h>
32#include <drm/drm_crtc.h>
33#include <drm/drm_crtc_helper.h>
34#include <drm/drm_edid.h>
a4fc5ed6 35#include "intel_drv.h"
760285e7 36#include <drm/i915_drm.h>
a4fc5ed6 37#include "i915_drv.h"
a4fc5ed6 38
a4fc5ed6
KP		 39#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
40
cfcb0fc9
JB		 41/**
42 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
43 * @intel_dp: DP struct
44 *
45 * If a CPU or PCH DP output is attached to an eDP panel, this function
46 * will return true, and false otherwise.
47 */
48static bool is_edp(struct intel_dp *intel_dp)
49{
da63a9f2
PZ		 50 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
51
52 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
cfcb0fc9
JB		 53}
54
68b4d824 55static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
cfcb0fc9 56{
68b4d824
ID		 57 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
58
59 return intel_dig_port->base.base.dev;
cfcb0fc9
JB		 60}
61
df0e9248
CW		 62static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
63{
fa90ecef 64 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
df0e9248
CW		 65}
66
ea5b213a 67static void intel_dp_link_down(struct intel_dp *intel_dp);
a4fc5ed6 68
a4fc5ed6 69static int
ea5b213a 70intel_dp_max_link_bw(struct intel_dp *intel_dp)
a4fc5ed6 71{
7183dc29 72 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
a4fc5ed6
KP		 73
74 switch (max_link_bw) {
75 case DP_LINK_BW_1_62:
76 case DP_LINK_BW_2_7:
77 break;
78 default:
79 max_link_bw = DP_LINK_BW_1_62;
80 break;
81 }
82 return max_link_bw;
83}
84
cd9dde44
AJ		 85/*
86 * The units on the numbers in the next two are... bizarre. Examples will
87 * make it clearer; this one parallels an example in the eDP spec.
88 *
89 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
90 *
91 * 270000 * 1 * 8 / 10 == 216000
92 *
93 * The actual data capacity of that configuration is 2.16Gbit/s, so the
94 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
95 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
96 * 119000. At 18bpp that's 2142000 kilobits per second.
97 *
98 * Thus the strange-looking division by 10 in intel_dp_link_required, to
99 * get the result in decakilobits instead of kilobits.
100 */
101
a4fc5ed6 102static int
c898261c 103intel_dp_link_required(int pixel_clock, int bpp)
a4fc5ed6 104{
cd9dde44 105 return (pixel_clock * bpp + 9) / 10;
a4fc5ed6
KP		 106}
107
fe27d53e
DA		 108static int
109intel_dp_max_data_rate(int max_link_clock, int max_lanes)
110{
111 return (max_link_clock * max_lanes * 8) / 10;
112}
113
a4fc5ed6
KP		 114static int
115intel_dp_mode_valid(struct drm_connector *connector,
116 struct drm_display_mode *mode)
117{
df0e9248 118 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e
JN		 119 struct intel_connector *intel_connector = to_intel_connector(connector);
120 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
36008365
DV		 121 int target_clock = mode->clock;
122 int max_rate, mode_rate, max_lanes, max_link_clock;
a4fc5ed6 123
dd06f90e
JN		 124 if (is_edp(intel_dp) && fixed_mode) {
125 if (mode->hdisplay > fixed_mode->hdisplay)
7de56f43
ZY		 126 return MODE_PANEL;
127
dd06f90e 128 if (mode->vdisplay > fixed_mode->vdisplay)
7de56f43 129 return MODE_PANEL;
03afc4a2
DV		 130
131 target_clock = fixed_mode->clock;
7de56f43
ZY		 132 }
133
36008365
DV		 134 max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
135 max_lanes = drm_dp_max_lane_count(intel_dp->dpcd);
136
137 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
138 mode_rate = intel_dp_link_required(target_clock, 18);
139
140 if (mode_rate > max_rate)
c4867936 141 return MODE_CLOCK_HIGH;
a4fc5ed6
KP		 142
143 if (mode->clock < 10000)
144 return MODE_CLOCK_LOW;
145
0af78a2b
DV		 146 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
147 return MODE_H_ILLEGAL;
148
a4fc5ed6
KP		 149 return MODE_OK;
150}
151
152static uint32_t
153pack_aux(uint8_t *src, int src_bytes)
154{
155 int i;
156 uint32_t v = 0;
157
158 if (src_bytes > 4)
159 src_bytes = 4;
160 for (i = 0; i < src_bytes; i++)
161 v |= ((uint32_t) src[i]) << ((3-i) * 8);
162 return v;
163}
164
165static void
166unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
167{
168 int i;
169 if (dst_bytes > 4)
170 dst_bytes = 4;
171 for (i = 0; i < dst_bytes; i++)
172 dst[i] = src >> ((3-i) * 8);
173}
174
fb0f8fbf
KP		 175/* hrawclock is 1/4 the FSB frequency */
176static int
177intel_hrawclk(struct drm_device *dev)
178{
179 struct drm_i915_private *dev_priv = dev->dev_private;
180 uint32_t clkcfg;
181
9473c8f4
VP		 182 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
183 if (IS_VALLEYVIEW(dev))
184 return 200;
185
fb0f8fbf
KP		 186 clkcfg = I915_READ(CLKCFG);
187 switch (clkcfg & CLKCFG_FSB_MASK) {
188 case CLKCFG_FSB_400:
189 return 100;
190 case CLKCFG_FSB_533:
191 return 133;
192 case CLKCFG_FSB_667:
193 return 166;
194 case CLKCFG_FSB_800:
195 return 200;
196 case CLKCFG_FSB_1067:
197 return 266;
198 case CLKCFG_FSB_1333:
199 return 333;
200 /* these two are just a guess; one of them might be right */
201 case CLKCFG_FSB_1600:
202 case CLKCFG_FSB_1600_ALT:
203 return 400;
204 default:
205 return 133;
206 }
207}
208
ebf33b18
KP		 209static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
210{
30add22d 211 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18 212 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420 213 u32 pp_stat_reg;
ebf33b18 214
453c5420
JB		 215 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
216 return (I915_READ(pp_stat_reg) & PP_ON) != 0;
ebf33b18
KP		 217}
218
219static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
220{
30add22d 221 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18 222 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420 223 u32 pp_ctrl_reg;
ebf33b18 224
453c5420
JB		 225 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
226 return (I915_READ(pp_ctrl_reg) & EDP_FORCE_VDD) != 0;
ebf33b18
KP		 227}
228
9b984dae
KP		 229static void
230intel_dp_check_edp(struct intel_dp *intel_dp)
231{
30add22d 232 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9b984dae 233 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420 234 u32 pp_stat_reg, pp_ctrl_reg;
ebf33b18 235
9b984dae
KP		 236 if (!is_edp(intel_dp))
237 return;
453c5420
JB		 238
239 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
240 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
241
ebf33b18 242 if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
9b984dae
KP		 243 WARN(1, "eDP powered off while attempting aux channel communication.\n");
244 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
453c5420
JB		 245 I915_READ(pp_stat_reg),
246 I915_READ(pp_ctrl_reg));
9b984dae
KP		 247 }
248}
249
9ee32fea
DV		 250static uint32_t
251intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
252{
253 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
254 struct drm_device *dev = intel_dig_port->base.base.dev;
255 struct drm_i915_private *dev_priv = dev->dev_private;
9ed35ab1 256 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
9ee32fea
DV		 257 uint32_t status;
258 bool done;
259
ef04f00d 260#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
9ee32fea 261 if (has_aux_irq)
b18ac466 262 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
3598706b 263 msecs_to_jiffies_timeout(10));
9ee32fea
DV		 264 else
265 done = wait_for_atomic(C, 10) == 0;
266 if (!done)
267 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
268 has_aux_irq);
269#undef C
270
271 return status;
272}
273
a4fc5ed6 274static int
ea5b213a 275intel_dp_aux_ch(struct intel_dp *intel_dp,
a4fc5ed6
KP		 276 uint8_t *send, int send_bytes,
277 uint8_t *recv, int recv_size)
278{
174edf1f
PZ		 279 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
280 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 281 struct drm_i915_private *dev_priv = dev->dev_private;
9ed35ab1 282 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
a4fc5ed6 283 uint32_t ch_data = ch_ctl + 4;
9ee32fea 284 int i, ret, recv_bytes;
a4fc5ed6 285 uint32_t status;
fb0f8fbf 286 uint32_t aux_clock_divider;
6b4e0a93 287 int try, precharge;
9ee32fea
DV		 288 bool has_aux_irq = INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev);
289
290 /* dp aux is extremely sensitive to irq latency, hence request the
291 * lowest possible wakeup latency and so prevent the cpu from going into
292 * deep sleep states.
293 */
294 pm_qos_update_request(&dev_priv->pm_qos, 0);
a4fc5ed6 295
9b984dae 296 intel_dp_check_edp(intel_dp);
a4fc5ed6 297 /* The clock divider is based off the hrawclk,
fb0f8fbf
KP		 298 * and would like to run at 2MHz. So, take the
299 * hrawclk value and divide by 2 and use that
6176b8f9
JB		 300 *
301 * Note that PCH attached eDP panels should use a 125MHz input
302 * clock divider.
a4fc5ed6 303 */
a62d0834
ID		 304 if (IS_VALLEYVIEW(dev)) {
305 aux_clock_divider = 100;
306 } else if (intel_dig_port->port == PORT_A) {
affa9354 307 if (HAS_DDI(dev))
b2b877ff
PZ		 308 aux_clock_divider = DIV_ROUND_CLOSEST(
309 intel_ddi_get_cdclk_freq(dev_priv), 2000);
9473c8f4 310 else if (IS_GEN6(dev) || IS_GEN7(dev))
1a2eb460 311 aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */
e3421a18
ZW		 312 else
313 aux_clock_divider = 225; /* eDP input clock at 450Mhz */
2c55c336
JN		 314 } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
315 /* Workaround for non-ULT HSW */
316 aux_clock_divider = 74;
317 } else if (HAS_PCH_SPLIT(dev)) {
6b3ec1c9 318 aux_clock_divider = DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
2c55c336 319 } else {
5eb08b69 320 aux_clock_divider = intel_hrawclk(dev) / 2;
2c55c336 321 }
5eb08b69 322
6b4e0a93
DV		 323 if (IS_GEN6(dev))
324 precharge = 3;
325 else
326 precharge = 5;
327
11bee43e
JB		 328 /* Try to wait for any previous AUX channel activity */
329 for (try = 0; try < 3; try++) {
ef04f00d 330 status = I915_READ_NOTRACE(ch_ctl);
11bee43e
JB		 331 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
332 break;
333 msleep(1);
334 }
335
336 if (try == 3) {
337 WARN(1, "dp_aux_ch not started status 0x%08x\n",
338 I915_READ(ch_ctl));
9ee32fea
DV		 339 ret = -EBUSY;
340 goto out;
4f7f7b7e
CW		 341 }
342
fb0f8fbf
KP		 343 /* Must try at least 3 times according to DP spec */
344 for (try = 0; try < 5; try++) {
345 /* Load the send data into the aux channel data registers */
4f7f7b7e
CW		 346 for (i = 0; i < send_bytes; i += 4)
347 I915_WRITE(ch_data + i,
348 pack_aux(send + i, send_bytes - i));
0206e353 349
fb0f8fbf 350 /* Send the command and wait for it to complete */
4f7f7b7e
CW		 351 I915_WRITE(ch_ctl,
352 DP_AUX_CH_CTL_SEND_BUSY |
9ee32fea 353 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
4f7f7b7e
CW		 354 DP_AUX_CH_CTL_TIME_OUT_400us |
355 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
356 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
357 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
358 DP_AUX_CH_CTL_DONE |
359 DP_AUX_CH_CTL_TIME_OUT_ERROR |
360 DP_AUX_CH_CTL_RECEIVE_ERROR);
9ee32fea
DV		 361
362 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
0206e353 363
fb0f8fbf 364 /* Clear done status and any errors */
4f7f7b7e
CW		 365 I915_WRITE(ch_ctl,
366 status |
367 DP_AUX_CH_CTL_DONE |
368 DP_AUX_CH_CTL_TIME_OUT_ERROR |
369 DP_AUX_CH_CTL_RECEIVE_ERROR);
d7e96fea
AJ		 370
371 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
372 DP_AUX_CH_CTL_RECEIVE_ERROR))
373 continue;
4f7f7b7e 374 if (status & DP_AUX_CH_CTL_DONE)
a4fc5ed6
KP		 375 break;
376 }
377
a4fc5ed6 378 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1ae8c0a5 379 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
9ee32fea
DV		 380 ret = -EBUSY;
381 goto out;
a4fc5ed6
KP		 382 }
383
384 /* Check for timeout or receive error.
385 * Timeouts occur when the sink is not connected
386 */
a5b3da54 387 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1ae8c0a5 388 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
9ee32fea
DV		 389 ret = -EIO;
390 goto out;
a5b3da54 391 }
1ae8c0a5
KP		 392
393 /* Timeouts occur when the device isn't connected, so they're
394 * "normal" -- don't fill the kernel log with these */
a5b3da54 395 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
28c97730 396 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
9ee32fea
DV		 397 ret = -ETIMEDOUT;
398 goto out;
a4fc5ed6
KP		 399 }
400
401 /* Unload any bytes sent back from the other side */
402 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
403 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
a4fc5ed6
KP		 404 if (recv_bytes > recv_size)
405 recv_bytes = recv_size;
0206e353 406
4f7f7b7e
CW		 407 for (i = 0; i < recv_bytes; i += 4)
408 unpack_aux(I915_READ(ch_data + i),
409 recv + i, recv_bytes - i);
a4fc5ed6 410
9ee32fea
DV		 411 ret = recv_bytes;
412out:
413 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
414
415 return ret;
a4fc5ed6
KP		 416}
417
418/* Write data to the aux channel in native mode */
419static int
ea5b213a 420intel_dp_aux_native_write(struct intel_dp *intel_dp,
a4fc5ed6
KP		 421 uint16_t address, uint8_t *send, int send_bytes)
422{
423 int ret;
424 uint8_t msg[20];
425 int msg_bytes;
426 uint8_t ack;
427
9b984dae 428 intel_dp_check_edp(intel_dp);
a4fc5ed6
KP		 429 if (send_bytes > 16)
430 return -1;
431 msg[0] = AUX_NATIVE_WRITE << 4;
432 msg[1] = address >> 8;
eebc863e 433 msg[2] = address & 0xff;
a4fc5ed6
KP		 434 msg[3] = send_bytes - 1;
435 memcpy(&msg[4], send, send_bytes);
436 msg_bytes = send_bytes + 4;
437 for (;;) {
ea5b213a 438 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
a4fc5ed6
KP		 439 if (ret < 0)
440 return ret;
441 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
442 break;
443 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
444 udelay(100);
445 else
a5b3da54 446 return -EIO;
a4fc5ed6
KP		 447 }
448 return send_bytes;
449}
450
451/* Write a single byte to the aux channel in native mode */
452static int
ea5b213a 453intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
a4fc5ed6
KP		 454 uint16_t address, uint8_t byte)
455{
ea5b213a 456 return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
a4fc5ed6
KP		 457}
458
459/* read bytes from a native aux channel */
460static int
ea5b213a 461intel_dp_aux_native_read(struct intel_dp *intel_dp,
a4fc5ed6
KP		 462 uint16_t address, uint8_t *recv, int recv_bytes)
463{
464 uint8_t msg[4];
465 int msg_bytes;
466 uint8_t reply[20];
467 int reply_bytes;
468 uint8_t ack;
469 int ret;
470
9b984dae 471 intel_dp_check_edp(intel_dp);
a4fc5ed6
KP		 472 msg[0] = AUX_NATIVE_READ << 4;
473 msg[1] = address >> 8;
474 msg[2] = address & 0xff;
475 msg[3] = recv_bytes - 1;
476
477 msg_bytes = 4;
478 reply_bytes = recv_bytes + 1;
479
480 for (;;) {
ea5b213a 481 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
a4fc5ed6 482 reply, reply_bytes);
a5b3da54
KP		 483 if (ret == 0)
484 return -EPROTO;
485 if (ret < 0)
a4fc5ed6
KP		 486 return ret;
487 ack = reply[0];
488 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
489 memcpy(recv, reply + 1, ret - 1);
490 return ret - 1;
491 }
492 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
493 udelay(100);
494 else
a5b3da54 495 return -EIO;
a4fc5ed6
KP		 496 }
497}
498
499static int
ab2c0672
DA		 500intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
501 uint8_t write_byte, uint8_t *read_byte)
a4fc5ed6 502{
ab2c0672 503 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
ea5b213a
CW		 504 struct intel_dp *intel_dp = container_of(adapter,
505 struct intel_dp,
506 adapter);
ab2c0672
DA		 507 uint16_t address = algo_data->address;
508 uint8_t msg[5];
509 uint8_t reply[2];
8316f337 510 unsigned retry;
ab2c0672
DA		 511 int msg_bytes;
512 int reply_bytes;
513 int ret;
514
9b984dae 515 intel_dp_check_edp(intel_dp);
ab2c0672
DA		 516 /* Set up the command byte */
517 if (mode & MODE_I2C_READ)
518 msg[0] = AUX_I2C_READ << 4;
519 else
520 msg[0] = AUX_I2C_WRITE << 4;
521
522 if (!(mode & MODE_I2C_STOP))
523 msg[0] |= AUX_I2C_MOT << 4;
a4fc5ed6 524
ab2c0672
DA		 525 msg[1] = address >> 8;
526 msg[2] = address;
527
528 switch (mode) {
529 case MODE_I2C_WRITE:
530 msg[3] = 0;
531 msg[4] = write_byte;
532 msg_bytes = 5;
533 reply_bytes = 1;
534 break;
535 case MODE_I2C_READ:
536 msg[3] = 0;
537 msg_bytes = 4;
538 reply_bytes = 2;
539 break;
540 default:
541 msg_bytes = 3;
542 reply_bytes = 1;
543 break;
544 }
545
8316f337
DF		 546 for (retry = 0; retry < 5; retry++) {
547 ret = intel_dp_aux_ch(intel_dp,
548 msg, msg_bytes,
549 reply, reply_bytes);
ab2c0672 550 if (ret < 0) {
3ff99164 551 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
ab2c0672
DA		 552 return ret;
553 }
8316f337
DF		 554
555 switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
556 case AUX_NATIVE_REPLY_ACK:
557 /* I2C-over-AUX Reply field is only valid
558 * when paired with AUX ACK.
559 */
560 break;
561 case AUX_NATIVE_REPLY_NACK:
562 DRM_DEBUG_KMS("aux_ch native nack\n");
563 return -EREMOTEIO;
564 case AUX_NATIVE_REPLY_DEFER:
565 udelay(100);
566 continue;
567 default:
568 DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
569 reply[0]);
570 return -EREMOTEIO;
571 }
572
ab2c0672
DA		 573 switch (reply[0] & AUX_I2C_REPLY_MASK) {
574 case AUX_I2C_REPLY_ACK:
575 if (mode == MODE_I2C_READ) {
576 *read_byte = reply[1];
577 }
578 return reply_bytes - 1;
579 case AUX_I2C_REPLY_NACK:
8316f337 580 DRM_DEBUG_KMS("aux_i2c nack\n");
ab2c0672
DA		 581 return -EREMOTEIO;
582 case AUX_I2C_REPLY_DEFER:
8316f337 583 DRM_DEBUG_KMS("aux_i2c defer\n");
ab2c0672
DA		 584 udelay(100);
585 break;
586 default:
8316f337 587 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
ab2c0672
DA		 588 return -EREMOTEIO;
589 }
590 }
8316f337
DF		 591
592 DRM_ERROR("too many retries, giving up\n");
593 return -EREMOTEIO;
a4fc5ed6
KP		 594}
595
596static int
ea5b213a 597intel_dp_i2c_init(struct intel_dp *intel_dp,
55f78c43 598 struct intel_connector *intel_connector, const char *name)
a4fc5ed6 599{
0b5c541b
KP		 600 int ret;
601
d54e9d28 602 DRM_DEBUG_KMS("i2c_init %s\n", name);
ea5b213a
CW		 603 intel_dp->algo.running = false;
604 intel_dp->algo.address = 0;
605 intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
606
0206e353 607 memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
ea5b213a
CW		 608 intel_dp->adapter.owner = THIS_MODULE;
609 intel_dp->adapter.class = I2C_CLASS_DDC;
0206e353 610 strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
ea5b213a
CW		 611 intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
612 intel_dp->adapter.algo_data = &intel_dp->algo;
613 intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
614
0b5c541b
KP		 615 ironlake_edp_panel_vdd_on(intel_dp);
616 ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
bd943159 617 ironlake_edp_panel_vdd_off(intel_dp, false);
0b5c541b 618 return ret;
a4fc5ed6
KP		 619}
620
c6bb3538
DV		 621static void
622intel_dp_set_clock(struct intel_encoder *encoder,
623 struct intel_crtc_config *pipe_config, int link_bw)
624{
625 struct drm_device *dev = encoder->base.dev;
626
627 if (IS_G4X(dev)) {
628 if (link_bw == DP_LINK_BW_1_62) {
629 pipe_config->dpll.p1 = 2;
630 pipe_config->dpll.p2 = 10;
631 pipe_config->dpll.n = 2;
632 pipe_config->dpll.m1 = 23;
633 pipe_config->dpll.m2 = 8;
634 } else {
635 pipe_config->dpll.p1 = 1;
636 pipe_config->dpll.p2 = 10;
637 pipe_config->dpll.n = 1;
638 pipe_config->dpll.m1 = 14;
639 pipe_config->dpll.m2 = 2;
640 }
641 pipe_config->clock_set = true;
642 } else if (IS_HASWELL(dev)) {
643 /* Haswell has special-purpose DP DDI clocks. */
644 } else if (HAS_PCH_SPLIT(dev)) {
645 if (link_bw == DP_LINK_BW_1_62) {
646 pipe_config->dpll.n = 1;
647 pipe_config->dpll.p1 = 2;
648 pipe_config->dpll.p2 = 10;
649 pipe_config->dpll.m1 = 12;
650 pipe_config->dpll.m2 = 9;
651 } else {
652 pipe_config->dpll.n = 2;
653 pipe_config->dpll.p1 = 1;
654 pipe_config->dpll.p2 = 10;
655 pipe_config->dpll.m1 = 14;
656 pipe_config->dpll.m2 = 8;
657 }
658 pipe_config->clock_set = true;
659 } else if (IS_VALLEYVIEW(dev)) {
660 /* FIXME: Need to figure out optimized DP clocks for vlv. */
661 }
662}
663
00c09d70 664bool
5bfe2ac0
DV		 665intel_dp_compute_config(struct intel_encoder *encoder,
666 struct intel_crtc_config *pipe_config)
a4fc5ed6 667{
5bfe2ac0 668 struct drm_device *dev = encoder->base.dev;
36008365 669 struct drm_i915_private *dev_priv = dev->dev_private;
5bfe2ac0 670 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5bfe2ac0 671 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 672 enum port port = dp_to_dig_port(intel_dp)->port;
2dd24552 673 struct intel_crtc *intel_crtc = encoder->new_crtc;
dd06f90e 674 struct intel_connector *intel_connector = intel_dp->attached_connector;
a4fc5ed6 675 int lane_count, clock;
397fe157 676 int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
ea5b213a 677 int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
083f9560 678 int bpp, mode_rate;
a4fc5ed6 679 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
ff9a6750 680 int link_avail, link_clock;
a4fc5ed6 681
bc7d38a4 682 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
5bfe2ac0
DV		 683 pipe_config->has_pch_encoder = true;
684
03afc4a2 685 pipe_config->has_dp_encoder = true;
a4fc5ed6 686
dd06f90e
JN		 687 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
688 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
689 adjusted_mode);
2dd24552
JB		 690 if (!HAS_PCH_SPLIT(dev))
691 intel_gmch_panel_fitting(intel_crtc, pipe_config,
692 intel_connector->panel.fitting_mode);
693 else
b074cec8
JB		 694 intel_pch_panel_fitting(intel_crtc, pipe_config,
695 intel_connector->panel.fitting_mode);
0d3a1bee
ZY		 696 }
697
cb1793ce 698 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
0af78a2b
DV		 699 return false;
700
083f9560
DV		 701 DRM_DEBUG_KMS("DP link computation with max lane count %i "
702 "max bw %02x pixel clock %iKHz\n",
71244653 703 max_lane_count, bws[max_clock], adjusted_mode->clock);
083f9560 704
36008365
DV		 705 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
706 * bpc in between. */
3e7ca985 707 bpp = pipe_config->pipe_bpp;
e1b73cba
DV		 708 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp)
709 bpp = min_t(int, bpp, dev_priv->vbt.edp_bpp);
657445fe 710
36008365 711 for (; bpp >= 6*3; bpp -= 2*3) {
ff9a6750 712 mode_rate = intel_dp_link_required(adjusted_mode->clock, bpp);
36008365
DV		 713
714 for (clock = 0; clock <= max_clock; clock++) {
715 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
716 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
717 link_avail = intel_dp_max_data_rate(link_clock,
718 lane_count);
719
720 if (mode_rate <= link_avail) {
721 goto found;
722 }
723 }
724 }
725 }
c4867936 726
36008365 727 return false;
3685a8f3 728
36008365 729found:
55bc60db
VS		 730 if (intel_dp->color_range_auto) {
731 /*
732 * See:
733 * CEA-861-E - 5.1 Default Encoding Parameters
734 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
735 */
18316c8c 736 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
55bc60db
VS		 737 intel_dp->color_range = DP_COLOR_RANGE_16_235;
738 else
739 intel_dp->color_range = 0;
740 }
741
3685a8f3 742 if (intel_dp->color_range)
50f3b016 743 pipe_config->limited_color_range = true;
a4fc5ed6 744
36008365
DV		 745 intel_dp->link_bw = bws[clock];
746 intel_dp->lane_count = lane_count;
657445fe 747 pipe_config->pipe_bpp = bpp;
ff9a6750 748 pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
a4fc5ed6 749
36008365
DV		 750 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
751 intel_dp->link_bw, intel_dp->lane_count,
ff9a6750 752 pipe_config->port_clock, bpp);
36008365
DV		 753 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
754 mode_rate, link_avail);
a4fc5ed6 755
03afc4a2 756 intel_link_compute_m_n(bpp, lane_count,
ff9a6750 757 adjusted_mode->clock, pipe_config->port_clock,
03afc4a2 758 &pipe_config->dp_m_n);
9d1a455b 759
c6bb3538
DV		 760 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
761
03afc4a2 762 return true;
a4fc5ed6
KP		 763}
764
247d89f6
PZ		 765void intel_dp_init_link_config(struct intel_dp *intel_dp)
766{
767 memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
768 intel_dp->link_configuration[0] = intel_dp->link_bw;
769 intel_dp->link_configuration[1] = intel_dp->lane_count;
770 intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B;
771 /*
772 * Check for DPCD version > 1.1 and enhanced framing support
773 */
774 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
775 (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
776 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
777 }
778}
779
7c62a164 780static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
ea9b6006 781{
7c62a164
DV		 782 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
783 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
784 struct drm_device *dev = crtc->base.dev;
ea9b6006
DV		 785 struct drm_i915_private *dev_priv = dev->dev_private;
786 u32 dpa_ctl;
787
ff9a6750 788 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock);
ea9b6006
DV		 789 dpa_ctl = I915_READ(DP_A);
790 dpa_ctl &= ~DP_PLL_FREQ_MASK;
791
ff9a6750 792 if (crtc->config.port_clock == 162000) {
1ce17038
DV		 793 /* For a long time we've carried around a ILK-DevA w/a for the
794 * 160MHz clock. If we're really unlucky, it's still required.
795 */
796 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
ea9b6006 797 dpa_ctl |= DP_PLL_FREQ_160MHZ;
7c62a164 798 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
ea9b6006
DV		 799 } else {
800 dpa_ctl |= DP_PLL_FREQ_270MHZ;
7c62a164 801 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
ea9b6006 802 }
1ce17038 803
ea9b6006
DV		 804 I915_WRITE(DP_A, dpa_ctl);
805
806 POSTING_READ(DP_A);
807 udelay(500);
808}
809
a4fc5ed6
KP		 810static void
811intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
812 struct drm_display_mode *adjusted_mode)
813{
e3421a18 814 struct drm_device *dev = encoder->dev;
417e822d 815 struct drm_i915_private *dev_priv = dev->dev_private;
ea5b213a 816 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
bc7d38a4 817 enum port port = dp_to_dig_port(intel_dp)->port;
7c62a164 818 struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
a4fc5ed6 819
417e822d 820 /*
1a2eb460 821 * There are four kinds of DP registers:
417e822d
KP		 822 *
823 * IBX PCH
1a2eb460
KP		 824 * SNB CPU
825 * IVB CPU
417e822d
KP		 826 * CPT PCH
827 *
828 * IBX PCH and CPU are the same for almost everything,
829 * except that the CPU DP PLL is configured in this
830 * register
831 *
832 * CPT PCH is quite different, having many bits moved
833 * to the TRANS_DP_CTL register instead. That
834 * configuration happens (oddly) in ironlake_pch_enable
835 */
9c9e7927 836
417e822d
KP		 837 /* Preserve the BIOS-computed detected bit. This is
838 * supposed to be read-only.
839 */
840 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
a4fc5ed6 841
417e822d 842 /* Handle DP bits in common between all three register formats */
417e822d 843 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
17aa6be9 844 intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
a4fc5ed6 845
e0dac65e
WF		 846 if (intel_dp->has_audio) {
847 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
7c62a164 848 pipe_name(crtc->pipe));
ea5b213a 849 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
e0dac65e
WF		 850 intel_write_eld(encoder, adjusted_mode);
851 }
247d89f6
PZ		 852
853 intel_dp_init_link_config(intel_dp);
a4fc5ed6 854
417e822d 855 /* Split out the IBX/CPU vs CPT settings */
32f9d658 856
bc7d38a4 857 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1a2eb460
KP		 858 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
859 intel_dp->DP |= DP_SYNC_HS_HIGH;
860 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
861 intel_dp->DP |= DP_SYNC_VS_HIGH;
862 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
863
864 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
865 intel_dp->DP |= DP_ENHANCED_FRAMING;
866
7c62a164 867 intel_dp->DP |= crtc->pipe << 29;
bc7d38a4 868 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
b2634017 869 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
3685a8f3 870 intel_dp->DP |= intel_dp->color_range;
417e822d
KP		 871
872 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
873 intel_dp->DP |= DP_SYNC_HS_HIGH;
874 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
875 intel_dp->DP |= DP_SYNC_VS_HIGH;
876 intel_dp->DP |= DP_LINK_TRAIN_OFF;
877
878 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
879 intel_dp->DP |= DP_ENHANCED_FRAMING;
880
7c62a164 881 if (crtc->pipe == 1)
417e822d 882 intel_dp->DP |= DP_PIPEB_SELECT;
417e822d
KP		 883 } else {
884 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
32f9d658 885 }
ea9b6006 886
bc7d38a4 887 if (port == PORT_A && !IS_VALLEYVIEW(dev))
7c62a164 888 ironlake_set_pll_cpu_edp(intel_dp);
a4fc5ed6
KP		 889}
890
99ea7127
KP		 891#define IDLE_ON_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
892#define IDLE_ON_VALUE (PP_ON | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
893
894#define IDLE_OFF_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
895#define IDLE_OFF_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
896
897#define IDLE_CYCLE_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
898#define IDLE_CYCLE_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
899
900static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
901 u32 mask,
902 u32 value)
bd943159 903{
30add22d 904 struct drm_device *dev = intel_dp_to_dev(intel_dp);
99ea7127 905 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 906 u32 pp_stat_reg, pp_ctrl_reg;
907
908 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
909 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
32ce697c 910
99ea7127 911 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
453c5420
JB		 912 mask, value,
913 I915_READ(pp_stat_reg),
914 I915_READ(pp_ctrl_reg));
32ce697c 915
453c5420 916 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
99ea7127 917 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
453c5420
JB		 918 I915_READ(pp_stat_reg),
919 I915_READ(pp_ctrl_reg));
32ce697c 920 }
99ea7127 921}
32ce697c 922
99ea7127
KP		 923static void ironlake_wait_panel_on(struct intel_dp *intel_dp)
924{
925 DRM_DEBUG_KMS("Wait for panel power on\n");
926 ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
bd943159
KP		 927}
928
99ea7127
KP		 929static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
930{
931 DRM_DEBUG_KMS("Wait for panel power off time\n");
932 ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
933}
934
935static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp)
936{
937 DRM_DEBUG_KMS("Wait for panel power cycle\n");
938 ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
939}
940
941
832dd3c1
KP		 942/* Read the current pp_control value, unlocking the register if it
943 * is locked
944 */
945
453c5420 946static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
832dd3c1 947{
453c5420
JB		 948 struct drm_device *dev = intel_dp_to_dev(intel_dp);
949 struct drm_i915_private *dev_priv = dev->dev_private;
950 u32 control;
951 u32 pp_ctrl_reg;
952
953 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
954 control = I915_READ(pp_ctrl_reg);
832dd3c1
KP		 955
956 control &= ~PANEL_UNLOCK_MASK;
957 control |= PANEL_UNLOCK_REGS;
958 return control;
bd943159
KP		 959}
960
82a4d9c0 961void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
5d613501 962{
30add22d 963 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5d613501
JB		 964 struct drm_i915_private *dev_priv = dev->dev_private;
965 u32 pp;
453c5420 966 u32 pp_stat_reg, pp_ctrl_reg;
5d613501 967
97af61f5
KP		 968 if (!is_edp(intel_dp))
969 return;
f01eca2e 970 DRM_DEBUG_KMS("Turn eDP VDD on\n");
5d613501 971
bd943159
KP		 972 WARN(intel_dp->want_panel_vdd,
973 "eDP VDD already requested on\n");
974
975 intel_dp->want_panel_vdd = true;
99ea7127 976
bd943159
KP		 977 if (ironlake_edp_have_panel_vdd(intel_dp)) {
978 DRM_DEBUG_KMS("eDP VDD already on\n");
979 return;
980 }
981
99ea7127
KP		 982 if (!ironlake_edp_have_panel_power(intel_dp))
983 ironlake_wait_panel_power_cycle(intel_dp);
984
453c5420 985 pp = ironlake_get_pp_control(intel_dp);
5d613501 986 pp |= EDP_FORCE_VDD;
ebf33b18 987
453c5420
JB		 988 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
989 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
990
991 I915_WRITE(pp_ctrl_reg, pp);
992 POSTING_READ(pp_ctrl_reg);
993 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
994 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
ebf33b18
KP		 995 /*
996 * If the panel wasn't on, delay before accessing aux channel
997 */
998 if (!ironlake_edp_have_panel_power(intel_dp)) {
bd943159 999 DRM_DEBUG_KMS("eDP was not running\n");
f01eca2e 1000 msleep(intel_dp->panel_power_up_delay);
f01eca2e 1001 }
5d613501
JB		 1002}
1003
bd943159 1004static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
5d613501 1005{
30add22d 1006 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5d613501
JB		 1007 struct drm_i915_private *dev_priv = dev->dev_private;
1008 u32 pp;
453c5420 1009 u32 pp_stat_reg, pp_ctrl_reg;
5d613501 1010
a0e99e68
DV		 1011 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
1012
bd943159 1013 if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
453c5420 1014 pp = ironlake_get_pp_control(intel_dp);
bd943159 1015 pp &= ~EDP_FORCE_VDD;
bd943159 1016
453c5420
JB		 1017 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
1018 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1019
1020 I915_WRITE(pp_ctrl_reg, pp);
1021 POSTING_READ(pp_ctrl_reg);
99ea7127 1022
453c5420
JB		 1023 /* Make sure sequencer is idle before allowing subsequent activity */
1024 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1025 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
99ea7127 1026 msleep(intel_dp->panel_power_down_delay);
bd943159
KP		 1027 }
1028}
5d613501 1029
bd943159
KP		 1030static void ironlake_panel_vdd_work(struct work_struct *__work)
1031{
1032 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1033 struct intel_dp, panel_vdd_work);
30add22d 1034 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bd943159 1035
627f7675 1036 mutex_lock(&dev->mode_config.mutex);
bd943159 1037 ironlake_panel_vdd_off_sync(intel_dp);
627f7675 1038 mutex_unlock(&dev->mode_config.mutex);
bd943159
KP		 1039}
1040
82a4d9c0 1041void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
bd943159 1042{
97af61f5
KP		 1043 if (!is_edp(intel_dp))
1044 return;
5d613501 1045
bd943159
KP		 1046 DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd);
1047 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
f2e8b18a 1048
bd943159
KP		 1049 intel_dp->want_panel_vdd = false;
1050
1051 if (sync) {
1052 ironlake_panel_vdd_off_sync(intel_dp);
1053 } else {
1054 /*
1055 * Queue the timer to fire a long
1056 * time from now (relative to the power down delay)
1057 * to keep the panel power up across a sequence of operations
1058 */
1059 schedule_delayed_work(&intel_dp->panel_vdd_work,
1060 msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1061 }
5d613501
JB		 1062}
1063
82a4d9c0 1064void ironlake_edp_panel_on(struct intel_dp *intel_dp)
9934c132 1065{
30add22d 1066 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1067 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1068 u32 pp;
453c5420 1069 u32 pp_ctrl_reg;
9934c132 1070
97af61f5 1071 if (!is_edp(intel_dp))
bd943159 1072 return;
99ea7127
KP		 1073
1074 DRM_DEBUG_KMS("Turn eDP power on\n");
1075
1076 if (ironlake_edp_have_panel_power(intel_dp)) {
1077 DRM_DEBUG_KMS("eDP power already on\n");
7d639f35 1078 return;
99ea7127 1079 }
9934c132 1080
99ea7127 1081 ironlake_wait_panel_power_cycle(intel_dp);
37c6c9b0 1082
453c5420 1083 pp = ironlake_get_pp_control(intel_dp);
05ce1a49
KP		 1084 if (IS_GEN5(dev)) {
1085 /* ILK workaround: disable reset around power sequence */
1086 pp &= ~PANEL_POWER_RESET;
1087 I915_WRITE(PCH_PP_CONTROL, pp);
1088 POSTING_READ(PCH_PP_CONTROL);
1089 }
37c6c9b0 1090
1c0ae80a 1091 pp |= POWER_TARGET_ON;
99ea7127
KP		 1092 if (!IS_GEN5(dev))
1093 pp |= PANEL_POWER_RESET;
1094
453c5420
JB		 1095 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1096
1097 I915_WRITE(pp_ctrl_reg, pp);
1098 POSTING_READ(pp_ctrl_reg);
9934c132 1099
99ea7127 1100 ironlake_wait_panel_on(intel_dp);
9934c132 1101
05ce1a49
KP		 1102 if (IS_GEN5(dev)) {
1103 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1104 I915_WRITE(PCH_PP_CONTROL, pp);
1105 POSTING_READ(PCH_PP_CONTROL);
1106 }
9934c132
JB		 1107}
1108
82a4d9c0 1109void ironlake_edp_panel_off(struct intel_dp *intel_dp)
9934c132 1110{
30add22d 1111 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1112 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1113 u32 pp;
453c5420 1114 u32 pp_ctrl_reg;
9934c132 1115
97af61f5
KP		 1116 if (!is_edp(intel_dp))
1117 return;
37c6c9b0 1118
99ea7127 1119 DRM_DEBUG_KMS("Turn eDP power off\n");
37c6c9b0 1120
6cb49835 1121 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
37c6c9b0 1122
453c5420 1123 pp = ironlake_get_pp_control(intel_dp);
35a38556
DV		 1124 /* We need to switch off panel power _and_ force vdd, for otherwise some
1125 * panels get very unhappy and cease to work. */
1126 pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE);
453c5420
JB		 1127
1128 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1129
1130 I915_WRITE(pp_ctrl_reg, pp);
1131 POSTING_READ(pp_ctrl_reg);
9934c132 1132
35a38556
DV		 1133 intel_dp->want_panel_vdd = false;
1134
99ea7127 1135 ironlake_wait_panel_off(intel_dp);
9934c132
JB		 1136}
1137
d6c50ff8 1138void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
32f9d658 1139{
da63a9f2
PZ		 1140 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1141 struct drm_device *dev = intel_dig_port->base.base.dev;
32f9d658 1142 struct drm_i915_private *dev_priv = dev->dev_private;
da63a9f2 1143 int pipe = to_intel_crtc(intel_dig_port->base.base.crtc)->pipe;
32f9d658 1144 u32 pp;
453c5420 1145 u32 pp_ctrl_reg;
32f9d658 1146
f01eca2e
KP		 1147 if (!is_edp(intel_dp))
1148 return;
1149
28c97730 1150 DRM_DEBUG_KMS("\n");
01cb9ea6
JB		 1151 /*
1152 * If we enable the backlight right away following a panel power
1153 * on, we may see slight flicker as the panel syncs with the eDP
1154 * link. So delay a bit to make sure the image is solid before
1155 * allowing it to appear.
1156 */
f01eca2e 1157 msleep(intel_dp->backlight_on_delay);
453c5420 1158 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1159 pp |= EDP_BLC_ENABLE;
453c5420
JB		 1160
1161 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1162
1163 I915_WRITE(pp_ctrl_reg, pp);
1164 POSTING_READ(pp_ctrl_reg);
035aa3de
DV		 1165
1166 intel_panel_enable_backlight(dev, pipe);
32f9d658
ZW		 1167}
1168
d6c50ff8 1169void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
32f9d658 1170{
30add22d 1171 struct drm_device *dev = intel_dp_to_dev(intel_dp);
32f9d658
ZW		 1172 struct drm_i915_private *dev_priv = dev->dev_private;
1173 u32 pp;
453c5420 1174 u32 pp_ctrl_reg;
32f9d658 1175
f01eca2e
KP		 1176 if (!is_edp(intel_dp))
1177 return;
1178
035aa3de
DV		 1179 intel_panel_disable_backlight(dev);
1180
28c97730 1181 DRM_DEBUG_KMS("\n");
453c5420 1182 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1183 pp &= ~EDP_BLC_ENABLE;
453c5420
JB		 1184
1185 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1186
1187 I915_WRITE(pp_ctrl_reg, pp);
1188 POSTING_READ(pp_ctrl_reg);
f01eca2e 1189 msleep(intel_dp->backlight_off_delay);
32f9d658 1190}
a4fc5ed6 1191
2bd2ad64 1192static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
d240f20f 1193{
da63a9f2
PZ		 1194 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1195 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1196 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1197 struct drm_i915_private *dev_priv = dev->dev_private;
1198 u32 dpa_ctl;
1199
2bd2ad64
DV		 1200 assert_pipe_disabled(dev_priv,
1201 to_intel_crtc(crtc)->pipe);
1202
d240f20f
JB		 1203 DRM_DEBUG_KMS("\n");
1204 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1205 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1206 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1207
1208 /* We don't adjust intel_dp->DP while tearing down the link, to
1209 * facilitate link retraining (e.g. after hotplug). Hence clear all
1210 * enable bits here to ensure that we don't enable too much. */
1211 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1212 intel_dp->DP |= DP_PLL_ENABLE;
1213 I915_WRITE(DP_A, intel_dp->DP);
298b0b39
JB		 1214 POSTING_READ(DP_A);
1215 udelay(200);
d240f20f
JB		 1216}
1217
2bd2ad64 1218static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
d240f20f 1219{
da63a9f2
PZ		 1220 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1221 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1222 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1223 struct drm_i915_private *dev_priv = dev->dev_private;
1224 u32 dpa_ctl;
1225
2bd2ad64
DV		 1226 assert_pipe_disabled(dev_priv,
1227 to_intel_crtc(crtc)->pipe);
1228
d240f20f 1229 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1230 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1231 "dp pll off, should be on\n");
1232 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1233
1234 /* We can't rely on the value tracked for the DP register in
1235 * intel_dp->DP because link_down must not change that (otherwise link
1236 * re-training will fail. */
298b0b39 1237 dpa_ctl &= ~DP_PLL_ENABLE;
d240f20f 1238 I915_WRITE(DP_A, dpa_ctl);
1af5fa1b 1239 POSTING_READ(DP_A);
d240f20f
JB		 1240 udelay(200);
1241}
1242
c7ad3810 1243/* If the sink supports it, try to set the power state appropriately */
c19b0669 1244void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
c7ad3810
JB		 1245{
1246 int ret, i;
1247
1248 /* Should have a valid DPCD by this point */
1249 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1250 return;
1251
1252 if (mode != DRM_MODE_DPMS_ON) {
1253 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
1254 DP_SET_POWER_D3);
1255 if (ret != 1)
1256 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1257 } else {
1258 /*
1259 * When turning on, we need to retry for 1ms to give the sink
1260 * time to wake up.
1261 */
1262 for (i = 0; i < 3; i++) {
1263 ret = intel_dp_aux_native_write_1(intel_dp,
1264 DP_SET_POWER,
1265 DP_SET_POWER_D0);
1266 if (ret == 1)
1267 break;
1268 msleep(1);
1269 }
1270 }
1271}
1272
19d8fe15
DV		 1273static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1274 enum pipe *pipe)
d240f20f 1275{
19d8fe15 1276 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1277 enum port port = dp_to_dig_port(intel_dp)->port;
19d8fe15
DV		 1278 struct drm_device *dev = encoder->base.dev;
1279 struct drm_i915_private *dev_priv = dev->dev_private;
1280 u32 tmp = I915_READ(intel_dp->output_reg);
1281
1282 if (!(tmp & DP_PORT_EN))
1283 return false;
1284
bc7d38a4 1285 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
19d8fe15 1286 *pipe = PORT_TO_PIPE_CPT(tmp);
bc7d38a4 1287 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
19d8fe15
DV		 1288 *pipe = PORT_TO_PIPE(tmp);
1289 } else {
1290 u32 trans_sel;
1291 u32 trans_dp;
1292 int i;
1293
1294 switch (intel_dp->output_reg) {
1295 case PCH_DP_B:
1296 trans_sel = TRANS_DP_PORT_SEL_B;
1297 break;
1298 case PCH_DP_C:
1299 trans_sel = TRANS_DP_PORT_SEL_C;
1300 break;
1301 case PCH_DP_D:
1302 trans_sel = TRANS_DP_PORT_SEL_D;
1303 break;
1304 default:
1305 return true;
1306 }
1307
1308 for_each_pipe(i) {
1309 trans_dp = I915_READ(TRANS_DP_CTL(i));
1310 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1311 *pipe = i;
1312 return true;
1313 }
1314 }
19d8fe15 1315
4a0833ec
DV		 1316 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1317 intel_dp->output_reg);
1318 }
d240f20f 1319
19d8fe15
DV		 1320 return true;
1321}
d240f20f 1322
045ac3b5
JB		 1323static void intel_dp_get_config(struct intel_encoder *encoder,
1324 struct intel_crtc_config *pipe_config)
1325{
1326 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1327 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
1328 u32 tmp, flags = 0;
1329
1330 tmp = I915_READ(intel_dp->output_reg);
1331
1332 if (tmp & DP_SYNC_HS_HIGH)
1333 flags |= DRM_MODE_FLAG_PHSYNC;
1334 else
1335 flags |= DRM_MODE_FLAG_NHSYNC;
1336
1337 if (tmp & DP_SYNC_VS_HIGH)
1338 flags |= DRM_MODE_FLAG_PVSYNC;
1339 else
1340 flags |= DRM_MODE_FLAG_NVSYNC;
1341
1342 pipe_config->adjusted_mode.flags |= flags;
1343}
1344
e8cb4558 1345static void intel_disable_dp(struct intel_encoder *encoder)
d240f20f 1346{
e8cb4558 1347 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866
ID		 1348 enum port port = dp_to_dig_port(intel_dp)->port;
1349 struct drm_device *dev = encoder->base.dev;
6cb49835
DV		 1350
1351 /* Make sure the panel is off before trying to change the mode. But also
1352 * ensure that we have vdd while we switch off the panel. */
1353 ironlake_edp_panel_vdd_on(intel_dp);
21264c63 1354 ironlake_edp_backlight_off(intel_dp);
c7ad3810 1355 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
35a38556 1356 ironlake_edp_panel_off(intel_dp);
3739850b
DV		 1357
1358 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
982a3866 1359 if (!(port == PORT_A || IS_VALLEYVIEW(dev)))
3739850b 1360 intel_dp_link_down(intel_dp);
d240f20f
JB		 1361}
1362
2bd2ad64 1363static void intel_post_disable_dp(struct intel_encoder *encoder)
d240f20f 1364{
2bd2ad64 1365 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866 1366 enum port port = dp_to_dig_port(intel_dp)->port;
b2634017 1367 struct drm_device *dev = encoder->base.dev;
2bd2ad64 1368
982a3866 1369 if (port == PORT_A || IS_VALLEYVIEW(dev)) {
3739850b 1370 intel_dp_link_down(intel_dp);
b2634017
JB		 1371 if (!IS_VALLEYVIEW(dev))
1372 ironlake_edp_pll_off(intel_dp);
3739850b 1373 }
2bd2ad64
DV		 1374}
1375
e8cb4558 1376static void intel_enable_dp(struct intel_encoder *encoder)
d240f20f 1377{
e8cb4558
DV		 1378 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1379 struct drm_device *dev = encoder->base.dev;
1380 struct drm_i915_private *dev_priv = dev->dev_private;
1381 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
5d613501 1382
0c33d8d7
DV		 1383 if (WARN_ON(dp_reg & DP_PORT_EN))
1384 return;
5d613501 1385
97af61f5 1386 ironlake_edp_panel_vdd_on(intel_dp);
f01eca2e 1387 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
33a34e4e 1388 intel_dp_start_link_train(intel_dp);
97af61f5 1389 ironlake_edp_panel_on(intel_dp);
bd943159 1390 ironlake_edp_panel_vdd_off(intel_dp, true);
33a34e4e 1391 intel_dp_complete_link_train(intel_dp);
3ab9c637 1392 intel_dp_stop_link_train(intel_dp);
f01eca2e 1393 ironlake_edp_backlight_on(intel_dp);
89b667f8
JB		 1394
1395 if (IS_VALLEYVIEW(dev)) {
1396 struct intel_digital_port *dport =
1397 enc_to_dig_port(&encoder->base);
1398 int channel = vlv_dport_to_channel(dport);
1399
1400 vlv_wait_port_ready(dev_priv, channel);
1401 }
d240f20f
JB		 1402}
1403
2bd2ad64 1404static void intel_pre_enable_dp(struct intel_encoder *encoder)
a4fc5ed6 1405{
2bd2ad64 1406 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1407 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
b2634017 1408 struct drm_device *dev = encoder->base.dev;
89b667f8 1409 struct drm_i915_private *dev_priv = dev->dev_private;
a4fc5ed6 1410
bc7d38a4 1411 if (dport->port == PORT_A && !IS_VALLEYVIEW(dev))
2bd2ad64 1412 ironlake_edp_pll_on(intel_dp);
89b667f8
JB		 1413
1414 if (IS_VALLEYVIEW(dev)) {
89b667f8
JB		 1415 struct intel_crtc *intel_crtc =
1416 to_intel_crtc(encoder->base.crtc);
1417 int port = vlv_dport_to_channel(dport);
1418 int pipe = intel_crtc->pipe;
1419 u32 val;
1420
ae99258f 1421 val = vlv_dpio_read(dev_priv, DPIO_DATA_LANE_A(port));
89b667f8
JB		 1422 val = 0;
1423 if (pipe)
1424 val |= (1<<21);
1425 else
1426 val &= ~(1<<21);
1427 val |= 0x001000c4;
ae99258f 1428 vlv_dpio_write(dev_priv, DPIO_DATA_CHANNEL(port), val);
89b667f8 1429
ae99258f 1430 vlv_dpio_write(dev_priv, DPIO_PCS_CLOCKBUF0(port),
89b667f8 1431 0x00760018);
ae99258f 1432 vlv_dpio_write(dev_priv, DPIO_PCS_CLOCKBUF8(port),
89b667f8
JB		 1433 0x00400888);
1434 }
1435}
1436
1437static void intel_dp_pre_pll_enable(struct intel_encoder *encoder)
1438{
1439 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1440 struct drm_device *dev = encoder->base.dev;
1441 struct drm_i915_private *dev_priv = dev->dev_private;
1442 int port = vlv_dport_to_channel(dport);
1443
1444 if (!IS_VALLEYVIEW(dev))
1445 return;
1446
89b667f8 1447 /* Program Tx lane resets to default */
ae99258f 1448 vlv_dpio_write(dev_priv, DPIO_PCS_TX(port),
89b667f8
JB		 1449 DPIO_PCS_TX_LANE2_RESET |
1450 DPIO_PCS_TX_LANE1_RESET);
ae99258f 1451 vlv_dpio_write(dev_priv, DPIO_PCS_CLK(port),
89b667f8
JB		 1452 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
1453 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
1454 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
1455 DPIO_PCS_CLK_SOFT_RESET);
1456
1457 /* Fix up inter-pair skew failure */
ae99258f
JN		 1458 vlv_dpio_write(dev_priv, DPIO_PCS_STAGGER1(port), 0x00750f00);
1459 vlv_dpio_write(dev_priv, DPIO_TX_CTL(port), 0x00001500);
1460 vlv_dpio_write(dev_priv, DPIO_TX_LANE(port), 0x40400000);
a4fc5ed6
KP		 1461}
1462
1463/*
df0c237d
JB		 1464 * Native read with retry for link status and receiver capability reads for
1465 * cases where the sink may still be asleep.
a4fc5ed6
KP		 1466 */
1467static bool
df0c237d
JB		 1468intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
1469 uint8_t *recv, int recv_bytes)
a4fc5ed6 1470{
61da5fab
JB		 1471 int ret, i;
1472
df0c237d
JB		 1473 /*
1474 * Sinks are *supposed* to come up within 1ms from an off state,
1475 * but we're also supposed to retry 3 times per the spec.
1476 */
61da5fab 1477 for (i = 0; i < 3; i++) {
df0c237d
JB		 1478 ret = intel_dp_aux_native_read(intel_dp, address, recv,
1479 recv_bytes);
1480 if (ret == recv_bytes)
61da5fab
JB		 1481 return true;
1482 msleep(1);
1483 }
a4fc5ed6 1484
61da5fab 1485 return false;
a4fc5ed6
KP		 1486}
1487
1488/*
1489 * Fetch AUX CH registers 0x202 - 0x207 which contain
1490 * link status information
1491 */
1492static bool
93f62dad 1493intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6 1494{
df0c237d
JB		 1495 return intel_dp_aux_native_read_retry(intel_dp,
1496 DP_LANE0_1_STATUS,
93f62dad 1497 link_status,
df0c237d 1498 DP_LINK_STATUS_SIZE);
a4fc5ed6
KP		 1499}
1500
a4fc5ed6
KP		 1501#if 0
1502static char *voltage_names[] = {
1503 "0.4V", "0.6V", "0.8V", "1.2V"
1504};
1505static char *pre_emph_names[] = {
1506 "0dB", "3.5dB", "6dB", "9.5dB"
1507};
1508static char *link_train_names[] = {
1509 "pattern 1", "pattern 2", "idle", "off"
1510};
1511#endif
1512
1513/*
1514 * These are source-specific values; current Intel hardware supports
1515 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1516 */
a4fc5ed6
KP		 1517
1518static uint8_t
1a2eb460 1519intel_dp_voltage_max(struct intel_dp *intel_dp)
a4fc5ed6 1520{
30add22d 1521 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 1522 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 1523
e2fa6fba
P		 1524 if (IS_VALLEYVIEW(dev))
1525 return DP_TRAIN_VOLTAGE_SWING_1200;
bc7d38a4 1526 else if (IS_GEN7(dev) && port == PORT_A)
1a2eb460 1527 return DP_TRAIN_VOLTAGE_SWING_800;
bc7d38a4 1528 else if (HAS_PCH_CPT(dev) && port != PORT_A)
1a2eb460
KP		 1529 return DP_TRAIN_VOLTAGE_SWING_1200;
1530 else
1531 return DP_TRAIN_VOLTAGE_SWING_800;
1532}
1533
1534static uint8_t
1535intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
1536{
30add22d 1537 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 1538 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 1539
22b8bf17 1540 if (HAS_DDI(dev)) {
d6c0d722
PZ		 1541 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1542 case DP_TRAIN_VOLTAGE_SWING_400:
1543 return DP_TRAIN_PRE_EMPHASIS_9_5;
1544 case DP_TRAIN_VOLTAGE_SWING_600:
1545 return DP_TRAIN_PRE_EMPHASIS_6;
1546 case DP_TRAIN_VOLTAGE_SWING_800:
1547 return DP_TRAIN_PRE_EMPHASIS_3_5;
1548 case DP_TRAIN_VOLTAGE_SWING_1200:
1549 default:
1550 return DP_TRAIN_PRE_EMPHASIS_0;
1551 }
e2fa6fba
P		 1552 } else if (IS_VALLEYVIEW(dev)) {
1553 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1554 case DP_TRAIN_VOLTAGE_SWING_400:
1555 return DP_TRAIN_PRE_EMPHASIS_9_5;
1556 case DP_TRAIN_VOLTAGE_SWING_600:
1557 return DP_TRAIN_PRE_EMPHASIS_6;
1558 case DP_TRAIN_VOLTAGE_SWING_800:
1559 return DP_TRAIN_PRE_EMPHASIS_3_5;
1560 case DP_TRAIN_VOLTAGE_SWING_1200:
1561 default:
1562 return DP_TRAIN_PRE_EMPHASIS_0;
1563 }
bc7d38a4 1564 } else if (IS_GEN7(dev) && port == PORT_A) {
1a2eb460
KP		 1565 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1566 case DP_TRAIN_VOLTAGE_SWING_400:
1567 return DP_TRAIN_PRE_EMPHASIS_6;
1568 case DP_TRAIN_VOLTAGE_SWING_600:
1569 case DP_TRAIN_VOLTAGE_SWING_800:
1570 return DP_TRAIN_PRE_EMPHASIS_3_5;
1571 default:
1572 return DP_TRAIN_PRE_EMPHASIS_0;
1573 }
1574 } else {
1575 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1576 case DP_TRAIN_VOLTAGE_SWING_400:
1577 return DP_TRAIN_PRE_EMPHASIS_6;
1578 case DP_TRAIN_VOLTAGE_SWING_600:
1579 return DP_TRAIN_PRE_EMPHASIS_6;
1580 case DP_TRAIN_VOLTAGE_SWING_800:
1581 return DP_TRAIN_PRE_EMPHASIS_3_5;
1582 case DP_TRAIN_VOLTAGE_SWING_1200:
1583 default:
1584 return DP_TRAIN_PRE_EMPHASIS_0;
1585 }
a4fc5ed6
KP		 1586 }
1587}
1588
e2fa6fba
P		 1589static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
1590{
1591 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1592 struct drm_i915_private *dev_priv = dev->dev_private;
1593 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1594 unsigned long demph_reg_value, preemph_reg_value,
1595 uniqtranscale_reg_value;
1596 uint8_t train_set = intel_dp->train_set[0];
cece5d58 1597 int port = vlv_dport_to_channel(dport);
e2fa6fba
P		 1598
1599 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
1600 case DP_TRAIN_PRE_EMPHASIS_0:
1601 preemph_reg_value = 0x0004000;
1602 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1603 case DP_TRAIN_VOLTAGE_SWING_400:
1604 demph_reg_value = 0x2B405555;
1605 uniqtranscale_reg_value = 0x552AB83A;
1606 break;
1607 case DP_TRAIN_VOLTAGE_SWING_600:
1608 demph_reg_value = 0x2B404040;
1609 uniqtranscale_reg_value = 0x5548B83A;
1610 break;
1611 case DP_TRAIN_VOLTAGE_SWING_800:
1612 demph_reg_value = 0x2B245555;
1613 uniqtranscale_reg_value = 0x5560B83A;
1614 break;
1615 case DP_TRAIN_VOLTAGE_SWING_1200:
1616 demph_reg_value = 0x2B405555;
1617 uniqtranscale_reg_value = 0x5598DA3A;
1618 break;
1619 default:
1620 return 0;
1621 }
1622 break;
1623 case DP_TRAIN_PRE_EMPHASIS_3_5:
1624 preemph_reg_value = 0x0002000;
1625 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1626 case DP_TRAIN_VOLTAGE_SWING_400:
1627 demph_reg_value = 0x2B404040;
1628 uniqtranscale_reg_value = 0x5552B83A;
1629 break;
1630 case DP_TRAIN_VOLTAGE_SWING_600:
1631 demph_reg_value = 0x2B404848;
1632 uniqtranscale_reg_value = 0x5580B83A;
1633 break;
1634 case DP_TRAIN_VOLTAGE_SWING_800:
1635 demph_reg_value = 0x2B404040;
1636 uniqtranscale_reg_value = 0x55ADDA3A;
1637 break;
1638 default:
1639 return 0;
1640 }
1641 break;
1642 case DP_TRAIN_PRE_EMPHASIS_6:
1643 preemph_reg_value = 0x0000000;
1644 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1645 case DP_TRAIN_VOLTAGE_SWING_400:
1646 demph_reg_value = 0x2B305555;
1647 uniqtranscale_reg_value = 0x5570B83A;
1648 break;
1649 case DP_TRAIN_VOLTAGE_SWING_600:
1650 demph_reg_value = 0x2B2B4040;
1651 uniqtranscale_reg_value = 0x55ADDA3A;
1652 break;
1653 default:
1654 return 0;
1655 }
1656 break;
1657 case DP_TRAIN_PRE_EMPHASIS_9_5:
1658 preemph_reg_value = 0x0006000;
1659 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1660 case DP_TRAIN_VOLTAGE_SWING_400:
1661 demph_reg_value = 0x1B405555;
1662 uniqtranscale_reg_value = 0x55ADDA3A;
1663 break;
1664 default:
1665 return 0;
1666 }
1667 break;
1668 default:
1669 return 0;
1670 }
1671
ae99258f
JN		 1672 vlv_dpio_write(dev_priv, DPIO_TX_OCALINIT(port), 0x00000000);
1673 vlv_dpio_write(dev_priv, DPIO_TX_SWING_CTL4(port), demph_reg_value);
1674 vlv_dpio_write(dev_priv, DPIO_TX_SWING_CTL2(port),
e2fa6fba 1675 uniqtranscale_reg_value);
ae99258f
JN		 1676 vlv_dpio_write(dev_priv, DPIO_TX_SWING_CTL3(port), 0x0C782040);
1677 vlv_dpio_write(dev_priv, DPIO_PCS_STAGGER0(port), 0x00030000);
1678 vlv_dpio_write(dev_priv, DPIO_PCS_CTL_OVER1(port), preemph_reg_value);
1679 vlv_dpio_write(dev_priv, DPIO_TX_OCALINIT(port), 0x80000000);
e2fa6fba
P		 1680
1681 return 0;
1682}
1683
a4fc5ed6 1684static void
93f62dad 1685intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6
KP		 1686{
1687 uint8_t v = 0;
1688 uint8_t p = 0;
1689 int lane;
1a2eb460
KP		 1690 uint8_t voltage_max;
1691 uint8_t preemph_max;
a4fc5ed6 1692
33a34e4e 1693 for (lane = 0; lane < intel_dp->lane_count; lane++) {
0f037bde
DV		 1694 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
1695 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
a4fc5ed6
KP		 1696
1697 if (this_v > v)
1698 v = this_v;
1699 if (this_p > p)
1700 p = this_p;
1701 }
1702
1a2eb460 1703 voltage_max = intel_dp_voltage_max(intel_dp);
417e822d
KP		 1704 if (v >= voltage_max)
1705 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
a4fc5ed6 1706
1a2eb460
KP		 1707 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
1708 if (p >= preemph_max)
1709 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
a4fc5ed6
KP		 1710
1711 for (lane = 0; lane < 4; lane++)
33a34e4e 1712 intel_dp->train_set[lane] = v | p;
a4fc5ed6
KP		 1713}
1714
1715static uint32_t
f0a3424e 1716intel_gen4_signal_levels(uint8_t train_set)
a4fc5ed6 1717{
3cf2efb1 1718 uint32_t signal_levels = 0;
a4fc5ed6 1719
3cf2efb1 1720 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
a4fc5ed6
KP		 1721 case DP_TRAIN_VOLTAGE_SWING_400:
1722 default:
1723 signal_levels |= DP_VOLTAGE_0_4;
1724 break;
1725 case DP_TRAIN_VOLTAGE_SWING_600:
1726 signal_levels |= DP_VOLTAGE_0_6;
1727 break;
1728 case DP_TRAIN_VOLTAGE_SWING_800:
1729 signal_levels |= DP_VOLTAGE_0_8;
1730 break;
1731 case DP_TRAIN_VOLTAGE_SWING_1200:
1732 signal_levels |= DP_VOLTAGE_1_2;
1733 break;
1734 }
3cf2efb1 1735 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
a4fc5ed6
KP		 1736 case DP_TRAIN_PRE_EMPHASIS_0:
1737 default:
1738 signal_levels |= DP_PRE_EMPHASIS_0;
1739 break;
1740 case DP_TRAIN_PRE_EMPHASIS_3_5:
1741 signal_levels |= DP_PRE_EMPHASIS_3_5;
1742 break;
1743 case DP_TRAIN_PRE_EMPHASIS_6:
1744 signal_levels |= DP_PRE_EMPHASIS_6;
1745 break;
1746 case DP_TRAIN_PRE_EMPHASIS_9_5:
1747 signal_levels |= DP_PRE_EMPHASIS_9_5;
1748 break;
1749 }
1750 return signal_levels;
1751}
1752
e3421a18
ZW		 1753/* Gen6's DP voltage swing and pre-emphasis control */
1754static uint32_t
1755intel_gen6_edp_signal_levels(uint8_t train_set)
1756{
3c5a62b5
YL		 1757 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1758 DP_TRAIN_PRE_EMPHASIS_MASK);
1759 switch (signal_levels) {
e3421a18 1760 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 1761 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1762 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1763 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1764 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
e3421a18 1765 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
3c5a62b5
YL		 1766 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1767 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
e3421a18 1768 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
3c5a62b5
YL		 1769 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1770 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
e3421a18 1771 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 1772 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
1773 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
e3421a18 1774 default:
3c5a62b5
YL		 1775 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1776 "0x%x\n", signal_levels);
1777 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
e3421a18
ZW		 1778 }
1779}
1780
1a2eb460
KP		 1781/* Gen7's DP voltage swing and pre-emphasis control */
1782static uint32_t
1783intel_gen7_edp_signal_levels(uint8_t train_set)
1784{
1785 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1786 DP_TRAIN_PRE_EMPHASIS_MASK);
1787 switch (signal_levels) {
1788 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1789 return EDP_LINK_TRAIN_400MV_0DB_IVB;
1790 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1791 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
1792 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1793 return EDP_LINK_TRAIN_400MV_6DB_IVB;
1794
1795 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1796 return EDP_LINK_TRAIN_600MV_0DB_IVB;
1797 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1798 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
1799
1800 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1801 return EDP_LINK_TRAIN_800MV_0DB_IVB;
1802 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1803 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
1804
1805 default:
1806 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1807 "0x%x\n", signal_levels);
1808 return EDP_LINK_TRAIN_500MV_0DB_IVB;
1809 }
1810}
1811
d6c0d722
PZ		 1812/* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
1813static uint32_t
f0a3424e 1814intel_hsw_signal_levels(uint8_t train_set)
a4fc5ed6 1815{
d6c0d722
PZ		 1816 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1817 DP_TRAIN_PRE_EMPHASIS_MASK);
1818 switch (signal_levels) {
1819 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1820 return DDI_BUF_EMP_400MV_0DB_HSW;
1821 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1822 return DDI_BUF_EMP_400MV_3_5DB_HSW;
1823 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1824 return DDI_BUF_EMP_400MV_6DB_HSW;
1825 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
1826 return DDI_BUF_EMP_400MV_9_5DB_HSW;
a4fc5ed6 1827
d6c0d722
PZ		 1828 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1829 return DDI_BUF_EMP_600MV_0DB_HSW;
1830 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1831 return DDI_BUF_EMP_600MV_3_5DB_HSW;
1832 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1833 return DDI_BUF_EMP_600MV_6DB_HSW;
a4fc5ed6 1834
d6c0d722
PZ		 1835 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1836 return DDI_BUF_EMP_800MV_0DB_HSW;
1837 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1838 return DDI_BUF_EMP_800MV_3_5DB_HSW;
1839 default:
1840 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1841 "0x%x\n", signal_levels);
1842 return DDI_BUF_EMP_400MV_0DB_HSW;
a4fc5ed6 1843 }
a4fc5ed6
KP		 1844}
1845
f0a3424e
PZ		 1846/* Properly updates "DP" with the correct signal levels. */
1847static void
1848intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
1849{
1850 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 1851 enum port port = intel_dig_port->port;
f0a3424e
PZ		 1852 struct drm_device *dev = intel_dig_port->base.base.dev;
1853 uint32_t signal_levels, mask;
1854 uint8_t train_set = intel_dp->train_set[0];
1855
22b8bf17 1856 if (HAS_DDI(dev)) {
f0a3424e
PZ		 1857 signal_levels = intel_hsw_signal_levels(train_set);
1858 mask = DDI_BUF_EMP_MASK;
e2fa6fba
P		 1859 } else if (IS_VALLEYVIEW(dev)) {
1860 signal_levels = intel_vlv_signal_levels(intel_dp);
1861 mask = 0;
bc7d38a4 1862 } else if (IS_GEN7(dev) && port == PORT_A) {
f0a3424e
PZ		 1863 signal_levels = intel_gen7_edp_signal_levels(train_set);
1864 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
bc7d38a4 1865 } else if (IS_GEN6(dev) && port == PORT_A) {
f0a3424e
PZ		 1866 signal_levels = intel_gen6_edp_signal_levels(train_set);
1867 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
1868 } else {
1869 signal_levels = intel_gen4_signal_levels(train_set);
1870 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
1871 }
1872
1873 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
1874
1875 *DP = (*DP & ~mask) | signal_levels;
1876}
1877
a4fc5ed6 1878static bool
ea5b213a 1879intel_dp_set_link_train(struct intel_dp *intel_dp,
a4fc5ed6 1880 uint32_t dp_reg_value,
58e10eb9 1881 uint8_t dp_train_pat)
a4fc5ed6 1882{
174edf1f
PZ		 1883 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1884 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 1885 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 1886 enum port port = intel_dig_port->port;
a4fc5ed6
KP		 1887 int ret;
1888
22b8bf17 1889 if (HAS_DDI(dev)) {
3ab9c637 1890 uint32_t temp = I915_READ(DP_TP_CTL(port));
d6c0d722
PZ		 1891
1892 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
1893 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
1894 else
1895 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
1896
1897 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
1898 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1899 case DP_TRAINING_PATTERN_DISABLE:
d6c0d722
PZ		 1900 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
1901
1902 break;
1903 case DP_TRAINING_PATTERN_1:
1904 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
1905 break;
1906 case DP_TRAINING_PATTERN_2:
1907 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
1908 break;
1909 case DP_TRAINING_PATTERN_3:
1910 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
1911 break;
1912 }
174edf1f 1913 I915_WRITE(DP_TP_CTL(port), temp);
d6c0d722 1914
bc7d38a4 1915 } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
47ea7542
PZ		 1916 dp_reg_value &= ~DP_LINK_TRAIN_MASK_CPT;
1917
1918 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1919 case DP_TRAINING_PATTERN_DISABLE:
1920 dp_reg_value |= DP_LINK_TRAIN_OFF_CPT;
1921 break;
1922 case DP_TRAINING_PATTERN_1:
1923 dp_reg_value |= DP_LINK_TRAIN_PAT_1_CPT;
1924 break;
1925 case DP_TRAINING_PATTERN_2:
1926 dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
1927 break;
1928 case DP_TRAINING_PATTERN_3:
1929 DRM_ERROR("DP training pattern 3 not supported\n");
1930 dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
1931 break;
1932 }
1933
1934 } else {
1935 dp_reg_value &= ~DP_LINK_TRAIN_MASK;
1936
1937 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1938 case DP_TRAINING_PATTERN_DISABLE:
1939 dp_reg_value |= DP_LINK_TRAIN_OFF;
1940 break;
1941 case DP_TRAINING_PATTERN_1:
1942 dp_reg_value |= DP_LINK_TRAIN_PAT_1;
1943 break;
1944 case DP_TRAINING_PATTERN_2:
1945 dp_reg_value |= DP_LINK_TRAIN_PAT_2;
1946 break;
1947 case DP_TRAINING_PATTERN_3:
1948 DRM_ERROR("DP training pattern 3 not supported\n");
1949 dp_reg_value |= DP_LINK_TRAIN_PAT_2;
1950 break;
1951 }
1952 }
1953
ea5b213a
CW		 1954 I915_WRITE(intel_dp->output_reg, dp_reg_value);
1955 POSTING_READ(intel_dp->output_reg);
a4fc5ed6 1956
ea5b213a 1957 intel_dp_aux_native_write_1(intel_dp,
a4fc5ed6
KP		 1958 DP_TRAINING_PATTERN_SET,
1959 dp_train_pat);
1960
47ea7542
PZ		 1961 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) !=
1962 DP_TRAINING_PATTERN_DISABLE) {
1963 ret = intel_dp_aux_native_write(intel_dp,
1964 DP_TRAINING_LANE0_SET,
1965 intel_dp->train_set,
1966 intel_dp->lane_count);
1967 if (ret != intel_dp->lane_count)
1968 return false;
1969 }
a4fc5ed6
KP		 1970
1971 return true;
1972}
1973
3ab9c637
ID		 1974static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
1975{
1976 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1977 struct drm_device *dev = intel_dig_port->base.base.dev;
1978 struct drm_i915_private *dev_priv = dev->dev_private;
1979 enum port port = intel_dig_port->port;
1980 uint32_t val;
1981
1982 if (!HAS_DDI(dev))
1983 return;
1984
1985 val = I915_READ(DP_TP_CTL(port));
1986 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
1987 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
1988 I915_WRITE(DP_TP_CTL(port), val);
1989
1990 /*
1991 * On PORT_A we can have only eDP in SST mode. There the only reason
1992 * we need to set idle transmission mode is to work around a HW issue
1993 * where we enable the pipe while not in idle link-training mode.
1994 * In this case there is requirement to wait for a minimum number of
1995 * idle patterns to be sent.
1996 */
1997 if (port == PORT_A)
1998 return;
1999
2000 if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
2001 1))
2002 DRM_ERROR("Timed out waiting for DP idle patterns\n");
2003}
2004
33a34e4e 2005/* Enable corresponding port and start training pattern 1 */
c19b0669 2006void
33a34e4e 2007intel_dp_start_link_train(struct intel_dp *intel_dp)
a4fc5ed6 2008{
da63a9f2 2009 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
c19b0669 2010 struct drm_device *dev = encoder->dev;
a4fc5ed6
KP		 2011 int i;
2012 uint8_t voltage;
2013 bool clock_recovery = false;
cdb0e95b 2014 int voltage_tries, loop_tries;
ea5b213a 2015 uint32_t DP = intel_dp->DP;
a4fc5ed6 2016
affa9354 2017 if (HAS_DDI(dev))
c19b0669
PZ		 2018 intel_ddi_prepare_link_retrain(encoder);
2019
3cf2efb1
CW		 2020 /* Write the link configuration data */
2021 intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
2022 intel_dp->link_configuration,
2023 DP_LINK_CONFIGURATION_SIZE);
a4fc5ed6
KP		 2024
2025 DP |= DP_PORT_EN;
1a2eb460 2026
33a34e4e 2027 memset(intel_dp->train_set, 0, 4);
a4fc5ed6 2028 voltage = 0xff;
cdb0e95b
KP		 2029 voltage_tries = 0;
2030 loop_tries = 0;
a4fc5ed6
KP		 2031 clock_recovery = false;
2032 for (;;) {
33a34e4e 2033 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
93f62dad 2034 uint8_t link_status[DP_LINK_STATUS_SIZE];
f0a3424e
PZ		 2035
2036 intel_dp_set_signal_levels(intel_dp, &DP);
a4fc5ed6 2037
a7c9655f 2038 /* Set training pattern 1 */
47ea7542 2039 if (!intel_dp_set_link_train(intel_dp, DP,
81055854
AJ		 2040 DP_TRAINING_PATTERN_1 |
2041 DP_LINK_SCRAMBLING_DISABLE))
a4fc5ed6 2042 break;
a4fc5ed6 2043
a7c9655f 2044 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
93f62dad
KP		 2045 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2046 DRM_ERROR("failed to get link status\n");
a4fc5ed6 2047 break;
93f62dad 2048 }
a4fc5ed6 2049
01916270 2050 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
93f62dad 2051 DRM_DEBUG_KMS("clock recovery OK\n");
3cf2efb1
CW		 2052 clock_recovery = true;
2053 break;
2054 }
2055
2056 /* Check to see if we've tried the max voltage */
2057 for (i = 0; i < intel_dp->lane_count; i++)
2058 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
a4fc5ed6 2059 break;
3b4f819d 2060 if (i == intel_dp->lane_count) {
b06fbda3
DV		 2061 ++loop_tries;
2062 if (loop_tries == 5) {
cdb0e95b
KP		 2063 DRM_DEBUG_KMS("too many full retries, give up\n");
2064 break;
2065 }
2066 memset(intel_dp->train_set, 0, 4);
2067 voltage_tries = 0;
2068 continue;
2069 }
a4fc5ed6 2070
3cf2efb1 2071 /* Check to see if we've tried the same voltage 5 times */
b06fbda3 2072 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
24773670 2073 ++voltage_tries;
b06fbda3
DV		 2074 if (voltage_tries == 5) {
2075 DRM_DEBUG_KMS("too many voltage retries, give up\n");
2076 break;
2077 }
2078 } else
2079 voltage_tries = 0;
2080 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
a4fc5ed6 2081
3cf2efb1 2082 /* Compute new intel_dp->train_set as requested by target */
93f62dad 2083 intel_get_adjust_train(intel_dp, link_status);
a4fc5ed6
KP		 2084 }
2085
33a34e4e
JB		 2086 intel_dp->DP = DP;
2087}
2088
c19b0669 2089void
33a34e4e
JB		 2090intel_dp_complete_link_train(struct intel_dp *intel_dp)
2091{
33a34e4e 2092 bool channel_eq = false;
37f80975 2093 int tries, cr_tries;
33a34e4e
JB		 2094 uint32_t DP = intel_dp->DP;
2095
a4fc5ed6
KP		 2096 /* channel equalization */
2097 tries = 0;
37f80975 2098 cr_tries = 0;
a4fc5ed6
KP		 2099 channel_eq = false;
2100 for (;;) {
93f62dad 2101 uint8_t link_status[DP_LINK_STATUS_SIZE];
e3421a18 2102
37f80975
JB		 2103 if (cr_tries > 5) {
2104 DRM_ERROR("failed to train DP, aborting\n");
2105 intel_dp_link_down(intel_dp);
2106 break;
2107 }
2108
f0a3424e 2109 intel_dp_set_signal_levels(intel_dp, &DP);
e3421a18 2110
a4fc5ed6 2111 /* channel eq pattern */
47ea7542 2112 if (!intel_dp_set_link_train(intel_dp, DP,
81055854
AJ		 2113 DP_TRAINING_PATTERN_2 |
2114 DP_LINK_SCRAMBLING_DISABLE))
a4fc5ed6
KP		 2115 break;
2116
a7c9655f 2117 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
93f62dad 2118 if (!intel_dp_get_link_status(intel_dp, link_status))
a4fc5ed6 2119 break;
a4fc5ed6 2120
37f80975 2121 /* Make sure clock is still ok */
01916270 2122 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
37f80975
JB		 2123 intel_dp_start_link_train(intel_dp);
2124 cr_tries++;
2125 continue;
2126 }
2127
1ffdff13 2128 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3cf2efb1
CW		 2129 channel_eq = true;
2130 break;
2131 }
a4fc5ed6 2132
37f80975
JB		 2133 /* Try 5 times, then try clock recovery if that fails */
2134 if (tries > 5) {
2135 intel_dp_link_down(intel_dp);
2136 intel_dp_start_link_train(intel_dp);
2137 tries = 0;
2138 cr_tries++;
2139 continue;
2140 }
a4fc5ed6 2141
3cf2efb1 2142 /* Compute new intel_dp->train_set as requested by target */
93f62dad 2143 intel_get_adjust_train(intel_dp, link_status);
3cf2efb1 2144 ++tries;
869184a6 2145 }
3cf2efb1 2146
3ab9c637
ID		 2147 intel_dp_set_idle_link_train(intel_dp);
2148
2149 intel_dp->DP = DP;
2150
d6c0d722 2151 if (channel_eq)
07f42258 2152 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
d6c0d722 2153
3ab9c637
ID		 2154}
2155
2156void intel_dp_stop_link_train(struct intel_dp *intel_dp)
2157{
2158 intel_dp_set_link_train(intel_dp, intel_dp->DP,
2159 DP_TRAINING_PATTERN_DISABLE);
a4fc5ed6
KP		 2160}
2161
2162static void
ea5b213a 2163intel_dp_link_down(struct intel_dp *intel_dp)
a4fc5ed6 2164{
da63a9f2 2165 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 2166 enum port port = intel_dig_port->port;
da63a9f2 2167 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 2168 struct drm_i915_private *dev_priv = dev->dev_private;
ab527efc
DV		 2169 struct intel_crtc *intel_crtc =
2170 to_intel_crtc(intel_dig_port->base.base.crtc);
ea5b213a 2171 uint32_t DP = intel_dp->DP;
a4fc5ed6 2172
c19b0669
PZ		 2173 /*
2174 * DDI code has a strict mode set sequence and we should try to respect
2175 * it, otherwise we might hang the machine in many different ways. So we
2176 * really should be disabling the port only on a complete crtc_disable
2177 * sequence. This function is just called under two conditions on DDI
2178 * code:
2179 * - Link train failed while doing crtc_enable, and on this case we
2180 * really should respect the mode set sequence and wait for a
2181 * crtc_disable.
2182 * - Someone turned the monitor off and intel_dp_check_link_status
2183 * called us. We don't need to disable the whole port on this case, so
2184 * when someone turns the monitor on again,
2185 * intel_ddi_prepare_link_retrain will take care of redoing the link
2186 * train.
2187 */
affa9354 2188 if (HAS_DDI(dev))
c19b0669
PZ		 2189 return;
2190
0c33d8d7 2191 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
1b39d6f3
CW		 2192 return;
2193
28c97730 2194 DRM_DEBUG_KMS("\n");
32f9d658 2195
bc7d38a4 2196 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
e3421a18 2197 DP &= ~DP_LINK_TRAIN_MASK_CPT;
ea5b213a 2198 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
e3421a18
ZW		 2199 } else {
2200 DP &= ~DP_LINK_TRAIN_MASK;
ea5b213a 2201 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
e3421a18 2202 }
fe255d00 2203 POSTING_READ(intel_dp->output_reg);
5eb08b69 2204
ab527efc
DV		 2205 /* We don't really know why we're doing this */
2206 intel_wait_for_vblank(dev, intel_crtc->pipe);
5eb08b69 2207
493a7081 2208 if (HAS_PCH_IBX(dev) &&
1b39d6f3 2209 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
da63a9f2 2210 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
31acbcc4 2211
5bddd17f
EA		 2212 /* Hardware workaround: leaving our transcoder select
2213 * set to transcoder B while it's off will prevent the
2214 * corresponding HDMI output on transcoder A.
2215 *
2216 * Combine this with another hardware workaround:
2217 * transcoder select bit can only be cleared while the
2218 * port is enabled.
2219 */
2220 DP &= ~DP_PIPEB_SELECT;
2221 I915_WRITE(intel_dp->output_reg, DP);
2222
2223 /* Changes to enable or select take place the vblank
2224 * after being written.
2225 */
ff50afe9
DV		 2226 if (WARN_ON(crtc == NULL)) {
2227 /* We should never try to disable a port without a crtc
2228 * attached. For paranoia keep the code around for a
2229 * bit. */
31acbcc4
CW		 2230 POSTING_READ(intel_dp->output_reg);
2231 msleep(50);
2232 } else
ab527efc 2233 intel_wait_for_vblank(dev, intel_crtc->pipe);
5bddd17f
EA		 2234 }
2235
832afda6 2236 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
ea5b213a
CW		 2237 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
2238 POSTING_READ(intel_dp->output_reg);
f01eca2e 2239 msleep(intel_dp->panel_power_down_delay);
a4fc5ed6
KP		 2240}
2241
26d61aad
KP		 2242static bool
2243intel_dp_get_dpcd(struct intel_dp *intel_dp)
92fd8fd1 2244{
577c7a50
DL		 2245 char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];
2246
92fd8fd1 2247 if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
edb39244
AJ		 2248 sizeof(intel_dp->dpcd)) == 0)
2249 return false; /* aux transfer failed */
92fd8fd1 2250
577c7a50
DL		 2251 hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd),
2252 32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
2253 DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
2254
edb39244
AJ		 2255 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
2256 return false; /* DPCD not present */
2257
2258 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
2259 DP_DWN_STRM_PORT_PRESENT))
2260 return true; /* native DP sink */
2261
2262 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
2263 return true; /* no per-port downstream info */
2264
2265 if (intel_dp_aux_native_read_retry(intel_dp, DP_DOWNSTREAM_PORT_0,
2266 intel_dp->downstream_ports,
2267 DP_MAX_DOWNSTREAM_PORTS) == 0)
2268 return false; /* downstream port status fetch failed */
2269
2270 return true;
92fd8fd1
KP		 2271}
2272
0d198328
AJ		 2273static void
2274intel_dp_probe_oui(struct intel_dp *intel_dp)
2275{
2276 u8 buf[3];
2277
2278 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
2279 return;
2280
351cfc34
DV		 2281 ironlake_edp_panel_vdd_on(intel_dp);
2282
0d198328
AJ		 2283 if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3))
2284 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
2285 buf[0], buf[1], buf[2]);
2286
2287 if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3))
2288 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
2289 buf[0], buf[1], buf[2]);
351cfc34
DV		 2290
2291 ironlake_edp_panel_vdd_off(intel_dp, false);
0d198328
AJ		 2292}
2293
a60f0e38
JB		 2294static bool
2295intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
2296{
2297 int ret;
2298
2299 ret = intel_dp_aux_native_read_retry(intel_dp,
2300 DP_DEVICE_SERVICE_IRQ_VECTOR,
2301 sink_irq_vector, 1);
2302 if (!ret)
2303 return false;
2304
2305 return true;
2306}
2307
2308static void
2309intel_dp_handle_test_request(struct intel_dp *intel_dp)
2310{
2311 /* NAK by default */
9324cf7f 2312 intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_NAK);
a60f0e38
JB		 2313}
2314
a4fc5ed6
KP		 2315/*
2316 * According to DP spec
2317 * 5.1.2:
2318 * 1. Read DPCD
2319 * 2. Configure link according to Receiver Capabilities
2320 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
2321 * 4. Check link status on receipt of hot-plug interrupt
2322 */
2323
00c09d70 2324void
ea5b213a 2325intel_dp_check_link_status(struct intel_dp *intel_dp)
a4fc5ed6 2326{
da63a9f2 2327 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
a60f0e38 2328 u8 sink_irq_vector;
93f62dad 2329 u8 link_status[DP_LINK_STATUS_SIZE];
a60f0e38 2330
da63a9f2 2331 if (!intel_encoder->connectors_active)
d2b996ac 2332 return;
59cd09e1 2333
da63a9f2 2334 if (WARN_ON(!intel_encoder->base.crtc))
a4fc5ed6
KP		 2335 return;
2336
92fd8fd1 2337 /* Try to read receiver status if the link appears to be up */
93f62dad 2338 if (!intel_dp_get_link_status(intel_dp, link_status)) {
ea5b213a 2339 intel_dp_link_down(intel_dp);
a4fc5ed6
KP		 2340 return;
2341 }
2342
92fd8fd1 2343 /* Now read the DPCD to see if it's actually running */
26d61aad 2344 if (!intel_dp_get_dpcd(intel_dp)) {
59cd09e1
JB		 2345 intel_dp_link_down(intel_dp);
2346 return;
2347 }
2348
a60f0e38
JB		 2349 /* Try to read the source of the interrupt */
2350 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2351 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
2352 /* Clear interrupt source */
2353 intel_dp_aux_native_write_1(intel_dp,
2354 DP_DEVICE_SERVICE_IRQ_VECTOR,
2355 sink_irq_vector);
2356
2357 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
2358 intel_dp_handle_test_request(intel_dp);
2359 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
2360 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
2361 }
2362
1ffdff13 2363 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
92fd8fd1 2364 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
da63a9f2 2365 drm_get_encoder_name(&intel_encoder->base));
33a34e4e
JB		 2366 intel_dp_start_link_train(intel_dp);
2367 intel_dp_complete_link_train(intel_dp);
3ab9c637 2368 intel_dp_stop_link_train(intel_dp);
33a34e4e 2369 }
a4fc5ed6 2370}
a4fc5ed6 2371
caf9ab24 2372/* XXX this is probably wrong for multiple downstream ports */
71ba9000 2373static enum drm_connector_status
26d61aad 2374intel_dp_detect_dpcd(struct intel_dp *intel_dp)
71ba9000 2375{
caf9ab24
AJ		 2376 uint8_t *dpcd = intel_dp->dpcd;
2377 bool hpd;
2378 uint8_t type;
2379
2380 if (!intel_dp_get_dpcd(intel_dp))
2381 return connector_status_disconnected;
2382
2383 /* if there's no downstream port, we're done */
2384 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
26d61aad 2385 return connector_status_connected;
caf9ab24
AJ		 2386
2387 /* If we're HPD-aware, SINK_COUNT changes dynamically */
2388 hpd = !!(intel_dp->downstream_ports[0] & DP_DS_PORT_HPD);
2389 if (hpd) {
23235177 2390 uint8_t reg;
caf9ab24 2391 if (!intel_dp_aux_native_read_retry(intel_dp, DP_SINK_COUNT,
23235177 2392 &reg, 1))
caf9ab24 2393 return connector_status_unknown;
23235177
AJ		 2394 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
2395 : connector_status_disconnected;
caf9ab24
AJ		 2396 }
2397
2398 /* If no HPD, poke DDC gently */
2399 if (drm_probe_ddc(&intel_dp->adapter))
26d61aad 2400 return connector_status_connected;
caf9ab24
AJ		 2401
2402 /* Well we tried, say unknown for unreliable port types */
2403 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
2404 if (type == DP_DS_PORT_TYPE_VGA || type == DP_DS_PORT_TYPE_NON_EDID)
2405 return connector_status_unknown;
2406
2407 /* Anything else is out of spec, warn and ignore */
2408 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
26d61aad 2409 return connector_status_disconnected;
71ba9000
AJ		 2410}
2411
5eb08b69 2412static enum drm_connector_status
a9756bb5 2413ironlake_dp_detect(struct intel_dp *intel_dp)
5eb08b69 2414{
30add22d 2415 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1b469639
DL		 2416 struct drm_i915_private *dev_priv = dev->dev_private;
2417 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
5eb08b69
ZW		 2418 enum drm_connector_status status;
2419
fe16d949
CW		 2420 /* Can't disconnect eDP, but you can close the lid... */
2421 if (is_edp(intel_dp)) {
30add22d 2422 status = intel_panel_detect(dev);
fe16d949
CW		 2423 if (status == connector_status_unknown)
2424 status = connector_status_connected;
2425 return status;
2426 }
01cb9ea6 2427
1b469639
DL		 2428 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
2429 return connector_status_disconnected;
2430
26d61aad 2431 return intel_dp_detect_dpcd(intel_dp);
5eb08b69
ZW		 2432}
2433
a4fc5ed6 2434static enum drm_connector_status
a9756bb5 2435g4x_dp_detect(struct intel_dp *intel_dp)
a4fc5ed6 2436{
30add22d 2437 struct drm_device *dev = intel_dp_to_dev(intel_dp);
a4fc5ed6 2438 struct drm_i915_private *dev_priv = dev->dev_private;
34f2be46 2439 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
10f76a38 2440 uint32_t bit;
5eb08b69 2441
35aad75f
JB		 2442 /* Can't disconnect eDP, but you can close the lid... */
2443 if (is_edp(intel_dp)) {
2444 enum drm_connector_status status;
2445
2446 status = intel_panel_detect(dev);
2447 if (status == connector_status_unknown)
2448 status = connector_status_connected;
2449 return status;
2450 }
2451
34f2be46
VS		 2452 switch (intel_dig_port->port) {
2453 case PORT_B:
26739f12 2454 bit = PORTB_HOTPLUG_LIVE_STATUS;
a4fc5ed6 2455 break;
34f2be46 2456 case PORT_C:
26739f12 2457 bit = PORTC_HOTPLUG_LIVE_STATUS;
a4fc5ed6 2458 break;
34f2be46 2459 case PORT_D:
26739f12 2460 bit = PORTD_HOTPLUG_LIVE_STATUS;
a4fc5ed6
KP		 2461 break;
2462 default:
2463 return connector_status_unknown;
2464 }
2465
10f76a38 2466 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
a4fc5ed6
KP		 2467 return connector_status_disconnected;
2468
26d61aad 2469 return intel_dp_detect_dpcd(intel_dp);
a9756bb5
ZW		 2470}
2471
8c241fef
KP		 2472static struct edid *
2473intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
2474{
9cd300e0 2475 struct intel_connector *intel_connector = to_intel_connector(connector);
d6f24d0f 2476
9cd300e0
JN		 2477 /* use cached edid if we have one */
2478 if (intel_connector->edid) {
2479 struct edid *edid;
2480 int size;
2481
2482 /* invalid edid */
2483 if (IS_ERR(intel_connector->edid))
d6f24d0f
JB		 2484 return NULL;
2485
9cd300e0 2486 size = (intel_connector->edid->extensions + 1) * EDID_LENGTH;
edbe1581 2487 edid = kmemdup(intel_connector->edid, size, GFP_KERNEL);
d6f24d0f
JB		 2488 if (!edid)
2489 return NULL;
2490
d6f24d0f
JB		 2491 return edid;
2492 }
8c241fef 2493
9cd300e0 2494 return drm_get_edid(connector, adapter);
8c241fef
KP		 2495}
2496
2497static int
2498intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
2499{
9cd300e0 2500 struct intel_connector *intel_connector = to_intel_connector(connector);
8c241fef 2501
9cd300e0
JN		 2502 /* use cached edid if we have one */
2503 if (intel_connector->edid) {
2504 /* invalid edid */
2505 if (IS_ERR(intel_connector->edid))
2506 return 0;
2507
2508 return intel_connector_update_modes(connector,
2509 intel_connector->edid);
d6f24d0f
JB		 2510 }
2511
9cd300e0 2512 return intel_ddc_get_modes(connector, adapter);
8c241fef
KP		 2513}
2514
a9756bb5
ZW		 2515static enum drm_connector_status
2516intel_dp_detect(struct drm_connector *connector, bool force)
2517{
2518 struct intel_dp *intel_dp = intel_attached_dp(connector);
d63885da
PZ		 2519 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2520 struct intel_encoder *intel_encoder = &intel_dig_port->base;
fa90ecef 2521 struct drm_device *dev = connector->dev;
a9756bb5
ZW		 2522 enum drm_connector_status status;
2523 struct edid *edid = NULL;
2524
2525 intel_dp->has_audio = false;
2526
2527 if (HAS_PCH_SPLIT(dev))
2528 status = ironlake_dp_detect(intel_dp);
2529 else
2530 status = g4x_dp_detect(intel_dp);
1b9be9d0 2531
a9756bb5
ZW		 2532 if (status != connector_status_connected)
2533 return status;
2534
0d198328
AJ		 2535 intel_dp_probe_oui(intel_dp);
2536
c3e5f67b
DV		 2537 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
2538 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
f684960e 2539 } else {
8c241fef 2540 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
f684960e
CW		 2541 if (edid) {
2542 intel_dp->has_audio = drm_detect_monitor_audio(edid);
f684960e
CW		 2543 kfree(edid);
2544 }
a9756bb5
ZW		 2545 }
2546
d63885da
PZ		 2547 if (intel_encoder->type != INTEL_OUTPUT_EDP)
2548 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
a9756bb5 2549 return connector_status_connected;
a4fc5ed6
KP		 2550}
2551
2552static int intel_dp_get_modes(struct drm_connector *connector)
2553{
df0e9248 2554 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e 2555 struct intel_connector *intel_connector = to_intel_connector(connector);
fa90ecef 2556 struct drm_device *dev = connector->dev;
32f9d658 2557 int ret;
a4fc5ed6
KP		 2558
2559 /* We should parse the EDID data and find out if it has an audio sink
2560 */
2561
8c241fef 2562 ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
f8779fda 2563 if (ret)
32f9d658
ZW		 2564 return ret;
2565
f8779fda 2566 /* if eDP has no EDID, fall back to fixed mode */
dd06f90e 2567 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
f8779fda 2568 struct drm_display_mode *mode;
dd06f90e
JN		 2569 mode = drm_mode_duplicate(dev,
2570 intel_connector->panel.fixed_mode);
f8779fda 2571 if (mode) {
32f9d658
ZW		 2572 drm_mode_probed_add(connector, mode);
2573 return 1;
2574 }
2575 }
2576 return 0;
a4fc5ed6
KP		 2577}
2578
1aad7ac0
CW		 2579static bool
2580intel_dp_detect_audio(struct drm_connector *connector)
2581{
2582 struct intel_dp *intel_dp = intel_attached_dp(connector);
2583 struct edid *edid;
2584 bool has_audio = false;
2585
8c241fef 2586 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
1aad7ac0
CW		 2587 if (edid) {
2588 has_audio = drm_detect_monitor_audio(edid);
1aad7ac0
CW		 2589 kfree(edid);
2590 }
2591
2592 return has_audio;
2593}
2594
f684960e
CW		 2595static int
2596intel_dp_set_property(struct drm_connector *connector,
2597 struct drm_property *property,
2598 uint64_t val)
2599{
e953fd7b 2600 struct drm_i915_private *dev_priv = connector->dev->dev_private;
53b41837 2601 struct intel_connector *intel_connector = to_intel_connector(connector);
da63a9f2
PZ		 2602 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
2603 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
f684960e
CW		 2604 int ret;
2605
662595df 2606 ret = drm_object_property_set_value(&connector->base, property, val);
f684960e
CW		 2607 if (ret)
2608 return ret;
2609
3f43c48d 2610 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 2611 int i = val;
2612 bool has_audio;
2613
2614 if (i == intel_dp->force_audio)
f684960e
CW		 2615 return 0;
2616
1aad7ac0 2617 intel_dp->force_audio = i;
f684960e 2618
c3e5f67b 2619 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 2620 has_audio = intel_dp_detect_audio(connector);
2621 else
c3e5f67b 2622 has_audio = (i == HDMI_AUDIO_ON);
1aad7ac0
CW		 2623
2624 if (has_audio == intel_dp->has_audio)
f684960e
CW		 2625 return 0;
2626
1aad7ac0 2627 intel_dp->has_audio = has_audio;
f684960e
CW		 2628 goto done;
2629 }
2630
e953fd7b 2631 if (property == dev_priv->broadcast_rgb_property) {
ae4edb80
DV		 2632 bool old_auto = intel_dp->color_range_auto;
2633 uint32_t old_range = intel_dp->color_range;
2634
55bc60db
VS		 2635 switch (val) {
2636 case INTEL_BROADCAST_RGB_AUTO:
2637 intel_dp->color_range_auto = true;
2638 break;
2639 case INTEL_BROADCAST_RGB_FULL:
2640 intel_dp->color_range_auto = false;
2641 intel_dp->color_range = 0;
2642 break;
2643 case INTEL_BROADCAST_RGB_LIMITED:
2644 intel_dp->color_range_auto = false;
2645 intel_dp->color_range = DP_COLOR_RANGE_16_235;
2646 break;
2647 default:
2648 return -EINVAL;
2649 }
ae4edb80
DV		 2650
2651 if (old_auto == intel_dp->color_range_auto &&
2652 old_range == intel_dp->color_range)
2653 return 0;
2654
e953fd7b
CW		 2655 goto done;
2656 }
2657
53b41837
YN		 2658 if (is_edp(intel_dp) &&
2659 property == connector->dev->mode_config.scaling_mode_property) {
2660 if (val == DRM_MODE_SCALE_NONE) {
2661 DRM_DEBUG_KMS("no scaling not supported\n");
2662 return -EINVAL;
2663 }
2664
2665 if (intel_connector->panel.fitting_mode == val) {
2666 /* the eDP scaling property is not changed */
2667 return 0;
2668 }
2669 intel_connector->panel.fitting_mode = val;
2670
2671 goto done;
2672 }
2673
f684960e
CW		 2674 return -EINVAL;
2675
2676done:
c0c36b94
CW		 2677 if (intel_encoder->base.crtc)
2678 intel_crtc_restore_mode(intel_encoder->base.crtc);
f684960e
CW		 2679
2680 return 0;
2681}
2682
a4fc5ed6 2683static void
0206e353 2684intel_dp_destroy(struct drm_connector *connector)
a4fc5ed6 2685{
1d508706 2686 struct intel_connector *intel_connector = to_intel_connector(connector);
aaa6fd2a 2687
9cd300e0
JN		 2688 if (!IS_ERR_OR_NULL(intel_connector->edid))
2689 kfree(intel_connector->edid);
2690
acd8db10
PZ		 2691 /* Can't call is_edp() since the encoder may have been destroyed
2692 * already. */
2693 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
1d508706 2694 intel_panel_fini(&intel_connector->panel);
aaa6fd2a 2695
a4fc5ed6
KP		 2696 drm_sysfs_connector_remove(connector);
2697 drm_connector_cleanup(connector);
55f78c43 2698 kfree(connector);
a4fc5ed6
KP		 2699}
2700
00c09d70 2701void intel_dp_encoder_destroy(struct drm_encoder *encoder)
24d05927 2702{
da63a9f2
PZ		 2703 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
2704 struct intel_dp *intel_dp = &intel_dig_port->dp;
bd173813 2705 struct drm_device *dev = intel_dp_to_dev(intel_dp);
24d05927
DV		 2706
2707 i2c_del_adapter(&intel_dp->adapter);
2708 drm_encoder_cleanup(encoder);
bd943159
KP		 2709 if (is_edp(intel_dp)) {
2710 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
bd173813 2711 mutex_lock(&dev->mode_config.mutex);
bd943159 2712 ironlake_panel_vdd_off_sync(intel_dp);
bd173813 2713 mutex_unlock(&dev->mode_config.mutex);
bd943159 2714 }
da63a9f2 2715 kfree(intel_dig_port);
24d05927
DV		 2716}
2717
a4fc5ed6 2718static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
a4fc5ed6 2719 .mode_set = intel_dp_mode_set,
a4fc5ed6
KP		 2720};
2721
2722static const struct drm_connector_funcs intel_dp_connector_funcs = {
2bd2ad64 2723 .dpms = intel_connector_dpms,
a4fc5ed6
KP		 2724 .detect = intel_dp_detect,
2725 .fill_modes = drm_helper_probe_single_connector_modes,
f684960e 2726 .set_property = intel_dp_set_property,
a4fc5ed6
KP		 2727 .destroy = intel_dp_destroy,
2728};
2729
2730static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
2731 .get_modes = intel_dp_get_modes,
2732 .mode_valid = intel_dp_mode_valid,
df0e9248 2733 .best_encoder = intel_best_encoder,
a4fc5ed6
KP		 2734};
2735
a4fc5ed6 2736static const struct drm_encoder_funcs intel_dp_enc_funcs = {
24d05927 2737 .destroy = intel_dp_encoder_destroy,
a4fc5ed6
KP		 2738};
2739
995b6762 2740static void
21d40d37 2741intel_dp_hot_plug(struct intel_encoder *intel_encoder)
c8110e52 2742{
fa90ecef 2743 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
c8110e52 2744
885a5014 2745 intel_dp_check_link_status(intel_dp);
c8110e52 2746}
6207937d 2747
e3421a18
ZW		 2748/* Return which DP Port should be selected for Transcoder DP control */
2749int
0206e353 2750intel_trans_dp_port_sel(struct drm_crtc *crtc)
e3421a18
ZW		 2751{
2752 struct drm_device *dev = crtc->dev;
fa90ecef
PZ		 2753 struct intel_encoder *intel_encoder;
2754 struct intel_dp *intel_dp;
e3421a18 2755
fa90ecef
PZ		 2756 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
2757 intel_dp = enc_to_intel_dp(&intel_encoder->base);
e3421a18 2758
fa90ecef
PZ		 2759 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
2760 intel_encoder->type == INTEL_OUTPUT_EDP)
ea5b213a 2761 return intel_dp->output_reg;
e3421a18 2762 }
ea5b213a 2763
e3421a18
ZW		 2764 return -1;
2765}
2766
36e83a18 2767/* check the VBT to see whether the eDP is on DP-D port */
cb0953d7 2768bool intel_dpd_is_edp(struct drm_device *dev)
36e83a18
ZY		 2769{
2770 struct drm_i915_private *dev_priv = dev->dev_private;
2771 struct child_device_config *p_child;
2772 int i;
2773
41aa3448 2774 if (!dev_priv->vbt.child_dev_num)
36e83a18
ZY		 2775 return false;
2776
41aa3448
RV		 2777 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
2778 p_child = dev_priv->vbt.child_dev + i;
36e83a18
ZY		 2779
2780 if (p_child->dvo_port == PORT_IDPD &&
2781 p_child->device_type == DEVICE_TYPE_eDP)
2782 return true;
2783 }
2784 return false;
2785}
2786
f684960e
CW		 2787static void
2788intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
2789{
53b41837
YN		 2790 struct intel_connector *intel_connector = to_intel_connector(connector);
2791
3f43c48d 2792 intel_attach_force_audio_property(connector);
e953fd7b 2793 intel_attach_broadcast_rgb_property(connector);
55bc60db 2794 intel_dp->color_range_auto = true;
53b41837
YN		 2795
2796 if (is_edp(intel_dp)) {
2797 drm_mode_create_scaling_mode_property(connector->dev);
6de6d846
RC		 2798 drm_object_attach_property(
2799 &connector->base,
53b41837 2800 connector->dev->mode_config.scaling_mode_property,
8e740cd1
YN		 2801 DRM_MODE_SCALE_ASPECT);
2802 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
53b41837 2803 }
f684960e
CW		 2804}
2805
67a54566
DV		 2806static void
2807intel_dp_init_panel_power_sequencer(struct drm_device *dev,
f30d26e4
JN		 2808 struct intel_dp *intel_dp,
2809 struct edp_power_seq *out)
67a54566
DV		 2810{
2811 struct drm_i915_private *dev_priv = dev->dev_private;
2812 struct edp_power_seq cur, vbt, spec, final;
2813 u32 pp_on, pp_off, pp_div, pp;
453c5420
JB		 2814 int pp_control_reg, pp_on_reg, pp_off_reg, pp_div_reg;
2815
2816 if (HAS_PCH_SPLIT(dev)) {
2817 pp_control_reg = PCH_PP_CONTROL;
2818 pp_on_reg = PCH_PP_ON_DELAYS;
2819 pp_off_reg = PCH_PP_OFF_DELAYS;
2820 pp_div_reg = PCH_PP_DIVISOR;
2821 } else {
2822 pp_control_reg = PIPEA_PP_CONTROL;
2823 pp_on_reg = PIPEA_PP_ON_DELAYS;
2824 pp_off_reg = PIPEA_PP_OFF_DELAYS;
2825 pp_div_reg = PIPEA_PP_DIVISOR;
2826 }
67a54566
DV		 2827
2828 /* Workaround: Need to write PP_CONTROL with the unlock key as
2829 * the very first thing. */
453c5420
JB		 2830 pp = ironlake_get_pp_control(intel_dp);
2831 I915_WRITE(pp_control_reg, pp);
67a54566 2832
453c5420
JB		 2833 pp_on = I915_READ(pp_on_reg);
2834 pp_off = I915_READ(pp_off_reg);
2835 pp_div = I915_READ(pp_div_reg);
67a54566
DV		 2836
2837 /* Pull timing values out of registers */
2838 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
2839 PANEL_POWER_UP_DELAY_SHIFT;
2840
2841 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
2842 PANEL_LIGHT_ON_DELAY_SHIFT;
2843
2844 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
2845 PANEL_LIGHT_OFF_DELAY_SHIFT;
2846
2847 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
2848 PANEL_POWER_DOWN_DELAY_SHIFT;
2849
2850 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
2851 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
2852
2853 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2854 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
2855
41aa3448 2856 vbt = dev_priv->vbt.edp_pps;
67a54566
DV		 2857
2858 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
2859 * our hw here, which are all in 100usec. */
2860 spec.t1_t3 = 210 * 10;
2861 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
2862 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
2863 spec.t10 = 500 * 10;
2864 /* This one is special and actually in units of 100ms, but zero
2865 * based in the hw (so we need to add 100 ms). But the sw vbt
2866 * table multiplies it with 1000 to make it in units of 100usec,
2867 * too. */
2868 spec.t11_t12 = (510 + 100) * 10;
2869
2870 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2871 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
2872
2873 /* Use the max of the register settings and vbt. If both are
2874 * unset, fall back to the spec limits. */
2875#define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
2876 spec.field : \
2877 max(cur.field, vbt.field))
2878 assign_final(t1_t3);
2879 assign_final(t8);
2880 assign_final(t9);
2881 assign_final(t10);
2882 assign_final(t11_t12);
2883#undef assign_final
2884
2885#define get_delay(field) (DIV_ROUND_UP(final.field, 10))
2886 intel_dp->panel_power_up_delay = get_delay(t1_t3);
2887 intel_dp->backlight_on_delay = get_delay(t8);
2888 intel_dp->backlight_off_delay = get_delay(t9);
2889 intel_dp->panel_power_down_delay = get_delay(t10);
2890 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
2891#undef get_delay
2892
f30d26e4
JN		 2893 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
2894 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
2895 intel_dp->panel_power_cycle_delay);
2896
2897 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
2898 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
2899
2900 if (out)
2901 *out = final;
2902}
2903
2904static void
2905intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
2906 struct intel_dp *intel_dp,
2907 struct edp_power_seq *seq)
2908{
2909 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 2910 u32 pp_on, pp_off, pp_div, port_sel = 0;
2911 int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
2912 int pp_on_reg, pp_off_reg, pp_div_reg;
2913
2914 if (HAS_PCH_SPLIT(dev)) {
2915 pp_on_reg = PCH_PP_ON_DELAYS;
2916 pp_off_reg = PCH_PP_OFF_DELAYS;
2917 pp_div_reg = PCH_PP_DIVISOR;
2918 } else {
2919 pp_on_reg = PIPEA_PP_ON_DELAYS;
2920 pp_off_reg = PIPEA_PP_OFF_DELAYS;
2921 pp_div_reg = PIPEA_PP_DIVISOR;
2922 }
2923
67a54566 2924 /* And finally store the new values in the power sequencer. */
f30d26e4
JN		 2925 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
2926 (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
2927 pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
2928 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
67a54566
DV		 2929 /* Compute the divisor for the pp clock, simply match the Bspec
2930 * formula. */
453c5420 2931 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
f30d26e4 2932 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
67a54566
DV		 2933 << PANEL_POWER_CYCLE_DELAY_SHIFT);
2934
2935 /* Haswell doesn't have any port selection bits for the panel
2936 * power sequencer any more. */
bc7d38a4
ID		 2937 if (IS_VALLEYVIEW(dev)) {
2938 port_sel = I915_READ(pp_on_reg) & 0xc0000000;
2939 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
2940 if (dp_to_dig_port(intel_dp)->port == PORT_A)
453c5420 2941 port_sel = PANEL_POWER_PORT_DP_A;
67a54566 2942 else
453c5420 2943 port_sel = PANEL_POWER_PORT_DP_D;
67a54566
DV		 2944 }
2945
453c5420
JB		 2946 pp_on |= port_sel;
2947
2948 I915_WRITE(pp_on_reg, pp_on);
2949 I915_WRITE(pp_off_reg, pp_off);
2950 I915_WRITE(pp_div_reg, pp_div);
67a54566 2951
67a54566 2952 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
453c5420
JB		 2953 I915_READ(pp_on_reg),
2954 I915_READ(pp_off_reg),
2955 I915_READ(pp_div_reg));
f684960e
CW		 2956}
2957
ed92f0b2
PZ		 2958static bool intel_edp_init_connector(struct intel_dp *intel_dp,
2959 struct intel_connector *intel_connector)
2960{
2961 struct drm_connector *connector = &intel_connector->base;
2962 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2963 struct drm_device *dev = intel_dig_port->base.base.dev;
2964 struct drm_i915_private *dev_priv = dev->dev_private;
2965 struct drm_display_mode *fixed_mode = NULL;
2966 struct edp_power_seq power_seq = { 0 };
2967 bool has_dpcd;
2968 struct drm_display_mode *scan;
2969 struct edid *edid;
2970
2971 if (!is_edp(intel_dp))
2972 return true;
2973
2974 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
2975
2976 /* Cache DPCD and EDID for edp. */
2977 ironlake_edp_panel_vdd_on(intel_dp);
2978 has_dpcd = intel_dp_get_dpcd(intel_dp);
2979 ironlake_edp_panel_vdd_off(intel_dp, false);
2980
2981 if (has_dpcd) {
2982 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
2983 dev_priv->no_aux_handshake =
2984 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
2985 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
2986 } else {
2987 /* if this fails, presume the device is a ghost */
2988 DRM_INFO("failed to retrieve link info, disabling eDP\n");
2989 intel_dp_encoder_destroy(&intel_dig_port->base.base);
2990 intel_dp_destroy(connector);
2991 return false;
2992 }
2993
2994 /* We now know it's not a ghost, init power sequence regs. */
2995 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
2996 &power_seq);
2997
2998 ironlake_edp_panel_vdd_on(intel_dp);
2999 edid = drm_get_edid(connector, &intel_dp->adapter);
3000 if (edid) {
3001 if (drm_add_edid_modes(connector, edid)) {
3002 drm_mode_connector_update_edid_property(connector,
3003 edid);
3004 drm_edid_to_eld(connector, edid);
3005 } else {
3006 kfree(edid);
3007 edid = ERR_PTR(-EINVAL);
3008 }
3009 } else {
3010 edid = ERR_PTR(-ENOENT);
3011 }
3012 intel_connector->edid = edid;
3013
3014 /* prefer fixed mode from EDID if available */
3015 list_for_each_entry(scan, &connector->probed_modes, head) {
3016 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
3017 fixed_mode = drm_mode_duplicate(dev, scan);
3018 break;
3019 }
3020 }
3021
3022 /* fallback to VBT if available for eDP */
3023 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
3024 fixed_mode = drm_mode_duplicate(dev,
3025 dev_priv->vbt.lfp_lvds_vbt_mode);
3026 if (fixed_mode)
3027 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
3028 }
3029
3030 ironlake_edp_panel_vdd_off(intel_dp, false);
3031
3032 intel_panel_init(&intel_connector->panel, fixed_mode);
3033 intel_panel_setup_backlight(connector);
3034
3035 return true;
3036}
3037
16c25533 3038bool
f0fec3f2
PZ		 3039intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
3040 struct intel_connector *intel_connector)
a4fc5ed6 3041{
f0fec3f2
PZ		 3042 struct drm_connector *connector = &intel_connector->base;
3043 struct intel_dp *intel_dp = &intel_dig_port->dp;
3044 struct intel_encoder *intel_encoder = &intel_dig_port->base;
3045 struct drm_device *dev = intel_encoder->base.dev;
a4fc5ed6 3046 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 3047 enum port port = intel_dig_port->port;
5eb08b69 3048 const char *name = NULL;
b329530c 3049 int type;
a4fc5ed6 3050
0767935e
DV		 3051 /* Preserve the current hw state. */
3052 intel_dp->DP = I915_READ(intel_dp->output_reg);
dd06f90e 3053 intel_dp->attached_connector = intel_connector;
3d3dc149 3054
f7d24902 3055 type = DRM_MODE_CONNECTOR_DisplayPort;
19c03924
GB		 3056 /*
3057 * FIXME : We need to initialize built-in panels before external panels.
3058 * For X0, DP_C is fixed as eDP. Revisit this as part of VLV eDP cleanup
3059 */
f7d24902
ID		 3060 switch (port) {
3061 case PORT_A:
b329530c 3062 type = DRM_MODE_CONNECTOR_eDP;
f7d24902
ID		 3063 break;
3064 case PORT_C:
3065 if (IS_VALLEYVIEW(dev))
3066 type = DRM_MODE_CONNECTOR_eDP;
3067 break;
3068 case PORT_D:
3069 if (HAS_PCH_SPLIT(dev) && intel_dpd_is_edp(dev))
3070 type = DRM_MODE_CONNECTOR_eDP;
3071 break;
3072 default: /* silence GCC warning */
3073 break;
b329530c
AJ		 3074 }
3075
f7d24902
ID		 3076 /*
3077 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
3078 * for DP the encoder type can be set by the caller to
3079 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
3080 */
3081 if (type == DRM_MODE_CONNECTOR_eDP)
3082 intel_encoder->type = INTEL_OUTPUT_EDP;
3083
e7281eab
ID		 3084 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
3085 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
3086 port_name(port));
3087
b329530c 3088 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
a4fc5ed6
KP		 3089 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
3090
a4fc5ed6
KP		 3091 connector->interlace_allowed = true;
3092 connector->doublescan_allowed = 0;
3093
f0fec3f2
PZ		 3094 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
3095 ironlake_panel_vdd_work);
a4fc5ed6 3096
df0e9248 3097 intel_connector_attach_encoder(intel_connector, intel_encoder);
a4fc5ed6
KP		 3098 drm_sysfs_connector_add(connector);
3099
affa9354 3100 if (HAS_DDI(dev))
bcbc889b
PZ		 3101 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
3102 else
3103 intel_connector->get_hw_state = intel_connector_get_hw_state;
3104
9ed35ab1
PZ		 3105 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
3106 if (HAS_DDI(dev)) {
3107 switch (intel_dig_port->port) {
3108 case PORT_A:
3109 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
3110 break;
3111 case PORT_B:
3112 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
3113 break;
3114 case PORT_C:
3115 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
3116 break;
3117 case PORT_D:
3118 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
3119 break;
3120 default:
3121 BUG();
3122 }
3123 }
e8cb4558 3124
a4fc5ed6 3125 /* Set up the DDC bus. */
ab9d7c30
PZ		 3126 switch (port) {
3127 case PORT_A:
1d843f9d 3128 intel_encoder->hpd_pin = HPD_PORT_A;
ab9d7c30
PZ		 3129 name = "DPDDC-A";
3130 break;
3131 case PORT_B:
1d843f9d 3132 intel_encoder->hpd_pin = HPD_PORT_B;
ab9d7c30
PZ		 3133 name = "DPDDC-B";
3134 break;
3135 case PORT_C:
1d843f9d 3136 intel_encoder->hpd_pin = HPD_PORT_C;
ab9d7c30
PZ		 3137 name = "DPDDC-C";
3138 break;
3139 case PORT_D:
1d843f9d 3140 intel_encoder->hpd_pin = HPD_PORT_D;
ab9d7c30
PZ		 3141 name = "DPDDC-D";
3142 break;
3143 default:
ad1c0b19 3144 BUG();
5eb08b69
ZW		 3145 }
3146
c1f05264
DA		 3147 intel_dp_i2c_init(intel_dp, intel_connector, name);
3148
ed92f0b2 3149 if (!intel_edp_init_connector(intel_dp, intel_connector))
16c25533 3150 return false;
32f9d658 3151
f684960e
CW		 3152 intel_dp_add_properties(intel_dp, connector);
3153
a4fc5ed6
KP		 3154 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
3155 * 0xd. Failure to do so will result in spurious interrupts being
3156 * generated on the port when a cable is not attached.
3157 */
3158 if (IS_G4X(dev) && !IS_GM45(dev)) {
3159 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
3160 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
3161 }
16c25533
PZ		 3162
3163 return true;
a4fc5ed6 3164}
f0fec3f2
PZ		 3165
3166void
3167intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
3168{
3169 struct intel_digital_port *intel_dig_port;
3170 struct intel_encoder *intel_encoder;
3171 struct drm_encoder *encoder;
3172 struct intel_connector *intel_connector;
3173
3174 intel_dig_port = kzalloc(sizeof(struct intel_digital_port), GFP_KERNEL);
3175 if (!intel_dig_port)
3176 return;
3177
3178 intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
3179 if (!intel_connector) {
3180 kfree(intel_dig_port);
3181 return;
3182 }
3183
3184 intel_encoder = &intel_dig_port->base;
3185 encoder = &intel_encoder->base;
3186
3187 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
3188 DRM_MODE_ENCODER_TMDS);
00c09d70 3189 drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs);
f0fec3f2 3190
5bfe2ac0 3191 intel_encoder->compute_config = intel_dp_compute_config;
00c09d70
PZ		 3192 intel_encoder->enable = intel_enable_dp;
3193 intel_encoder->pre_enable = intel_pre_enable_dp;
3194 intel_encoder->disable = intel_disable_dp;
3195 intel_encoder->post_disable = intel_post_disable_dp;
3196 intel_encoder->get_hw_state = intel_dp_get_hw_state;
045ac3b5 3197 intel_encoder->get_config = intel_dp_get_config;
89b667f8
JB		 3198 if (IS_VALLEYVIEW(dev))
3199 intel_encoder->pre_pll_enable = intel_dp_pre_pll_enable;
f0fec3f2 3200
174edf1f 3201 intel_dig_port->port = port;
f0fec3f2
PZ		 3202 intel_dig_port->dp.output_reg = output_reg;
3203
00c09d70 3204 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
f0fec3f2
PZ		 3205 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
3206 intel_encoder->cloneable = false;
3207 intel_encoder->hot_plug = intel_dp_hot_plug;
3208
3209 intel_dp_init_connector(intel_dig_port, intel_connector);
3210}
Linux kernel - Deliverables
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