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radeon/audio: consolidate audio_mode_set() functions
[deliverable/linux.git] / drivers / gpu / drm / radeon / atombios_encoders.c
CommitLineData
3f03ced8
AD		 1/*
2 * Copyright 2007-11 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
760285e7
DH		 26#include <drm/drmP.h>
27#include <drm/drm_crtc_helper.h>
28#include <drm/radeon_drm.h>
3f03ced8 29#include "radeon.h"
6e72376d 30#include "radeon_audio.h"
3f03ced8 31#include "atom.h"
f3728734 32#include <linux/backlight.h>
3f03ced8
AD		 33
34extern int atom_debug;
35
f3728734
AD		 36static u8
37radeon_atom_get_backlight_level_from_reg(struct radeon_device *rdev)
38{
39 u8 backlight_level;
40 u32 bios_2_scratch;
41
42 if (rdev->family >= CHIP_R600)
43 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
44 else
45 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
46
47 backlight_level = ((bios_2_scratch & ATOM_S2_CURRENT_BL_LEVEL_MASK) >>
48 ATOM_S2_CURRENT_BL_LEVEL_SHIFT);
49
50 return backlight_level;
51}
52
53static void
54radeon_atom_set_backlight_level_to_reg(struct radeon_device *rdev,
55 u8 backlight_level)
56{
57 u32 bios_2_scratch;
58
59 if (rdev->family >= CHIP_R600)
60 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
61 else
62 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
63
64 bios_2_scratch &= ~ATOM_S2_CURRENT_BL_LEVEL_MASK;
65 bios_2_scratch |= ((backlight_level << ATOM_S2_CURRENT_BL_LEVEL_SHIFT) &
66 ATOM_S2_CURRENT_BL_LEVEL_MASK);
67
68 if (rdev->family >= CHIP_R600)
69 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
70 else
71 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
72}
73
6d92f81d
AD		 74u8
75atombios_get_backlight_level(struct radeon_encoder *radeon_encoder)
76{
77 struct drm_device *dev = radeon_encoder->base.dev;
78 struct radeon_device *rdev = dev->dev_private;
79
80 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
81 return 0;
82
83 return radeon_atom_get_backlight_level_from_reg(rdev);
84}
85
fda4b25c 86void
37e9b6a6 87atombios_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level)
f3728734
AD		 88{
89 struct drm_encoder *encoder = &radeon_encoder->base;
90 struct drm_device *dev = radeon_encoder->base.dev;
91 struct radeon_device *rdev = dev->dev_private;
92 struct radeon_encoder_atom_dig *dig;
93 DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
94 int index;
95
37e9b6a6
AD		 96 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
97 return;
98
99 if ((radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) &&
100 radeon_encoder->enc_priv) {
f3728734 101 dig = radeon_encoder->enc_priv;
37e9b6a6 102 dig->backlight_level = level;
f3728734
AD		 103 radeon_atom_set_backlight_level_to_reg(rdev, dig->backlight_level);
104
105 switch (radeon_encoder->encoder_id) {
106 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
107 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
108 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
109 if (dig->backlight_level == 0) {
110 args.ucAction = ATOM_LCD_BLOFF;
111 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
112 } else {
113 args.ucAction = ATOM_LCD_BL_BRIGHTNESS_CONTROL;
114 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
115 args.ucAction = ATOM_LCD_BLON;
116 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
117 }
118 break;
119 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
120 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
121 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
122 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
123 if (dig->backlight_level == 0)
124 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0);
125 else {
126 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL, 0, 0);
127 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0);
128 }
129 break;
130 default:
131 break;
132 }
133 }
134}
135
bced76f2
AD		 136#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
137
f3728734
AD		 138static u8 radeon_atom_bl_level(struct backlight_device *bd)
139{
140 u8 level;
141
142 /* Convert brightness to hardware level */
143 if (bd->props.brightness < 0)
144 level = 0;
145 else if (bd->props.brightness > RADEON_MAX_BL_LEVEL)
146 level = RADEON_MAX_BL_LEVEL;
147 else
148 level = bd->props.brightness;
149
150 return level;
151}
152
153static int radeon_atom_backlight_update_status(struct backlight_device *bd)
154{
155 struct radeon_backlight_privdata *pdata = bl_get_data(bd);
156 struct radeon_encoder *radeon_encoder = pdata->encoder;
157
37e9b6a6 158 atombios_set_backlight_level(radeon_encoder, radeon_atom_bl_level(bd));
f3728734
AD		 159
160 return 0;
161}
162
163static int radeon_atom_backlight_get_brightness(struct backlight_device *bd)
164{
165 struct radeon_backlight_privdata *pdata = bl_get_data(bd);
166 struct radeon_encoder *radeon_encoder = pdata->encoder;
167 struct drm_device *dev = radeon_encoder->base.dev;
168 struct radeon_device *rdev = dev->dev_private;
169
170 return radeon_atom_get_backlight_level_from_reg(rdev);
171}
172
173static const struct backlight_ops radeon_atom_backlight_ops = {
174 .get_brightness = radeon_atom_backlight_get_brightness,
175 .update_status = radeon_atom_backlight_update_status,
176};
177
178void radeon_atom_backlight_init(struct radeon_encoder *radeon_encoder,
179 struct drm_connector *drm_connector)
180{
181 struct drm_device *dev = radeon_encoder->base.dev;
182 struct radeon_device *rdev = dev->dev_private;
183 struct backlight_device *bd;
184 struct backlight_properties props;
185 struct radeon_backlight_privdata *pdata;
186 struct radeon_encoder_atom_dig *dig;
614499b4 187 char bl_name[16];
f3728734 188
80101790
AD		 189 /* Mac laptops with multiple GPUs use the gmux driver for backlight
190 * so don't register a backlight device
191 */
192 if ((rdev->pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE) &&
193 (rdev->pdev->device == 0x6741))
194 return;
195
f3728734
AD		 196 if (!radeon_encoder->enc_priv)
197 return;
198
199 if (!rdev->is_atom_bios)
200 return;
201
202 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
203 return;
204
205 pdata = kmalloc(sizeof(struct radeon_backlight_privdata), GFP_KERNEL);
206 if (!pdata) {
207 DRM_ERROR("Memory allocation failed\n");
208 goto error;
209 }
210
211 memset(&props, 0, sizeof(props));
212 props.max_brightness = RADEON_MAX_BL_LEVEL;
213 props.type = BACKLIGHT_RAW;
614499b4
AD		 214 snprintf(bl_name, sizeof(bl_name),
215 "radeon_bl%d", dev->primary->index);
5bdebb18 216 bd = backlight_device_register(bl_name, drm_connector->kdev,
f3728734
AD		 217 pdata, &radeon_atom_backlight_ops, &props);
218 if (IS_ERR(bd)) {
219 DRM_ERROR("Backlight registration failed\n");
220 goto error;
221 }
222
223 pdata->encoder = radeon_encoder;
224
f3728734
AD		 225 dig = radeon_encoder->enc_priv;
226 dig->bl_dev = bd;
227
228 bd->props.brightness = radeon_atom_backlight_get_brightness(bd);
201bb624
AD		 229 /* Set a reasonable default here if the level is 0 otherwise
230 * fbdev will attempt to turn the backlight on after console
231 * unblanking and it will try and restore 0 which turns the backlight
232 * off again.
233 */
234 if (bd->props.brightness == 0)
235 bd->props.brightness = RADEON_MAX_BL_LEVEL;
f3728734
AD		 236 bd->props.power = FB_BLANK_UNBLANK;
237 backlight_update_status(bd);
238
239 DRM_INFO("radeon atom DIG backlight initialized\n");
240
241 return;
242
243error:
244 kfree(pdata);
245 return;
246}
247
248static void radeon_atom_backlight_exit(struct radeon_encoder *radeon_encoder)
249{
250 struct drm_device *dev = radeon_encoder->base.dev;
251 struct radeon_device *rdev = dev->dev_private;
252 struct backlight_device *bd = NULL;
253 struct radeon_encoder_atom_dig *dig;
254
255 if (!radeon_encoder->enc_priv)
256 return;
257
258 if (!rdev->is_atom_bios)
259 return;
260
261 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
262 return;
263
264 dig = radeon_encoder->enc_priv;
265 bd = dig->bl_dev;
266 dig->bl_dev = NULL;
267
268 if (bd) {
269 struct radeon_legacy_backlight_privdata *pdata;
270
271 pdata = bl_get_data(bd);
272 backlight_device_unregister(bd);
273 kfree(pdata);
274
275 DRM_INFO("radeon atom LVDS backlight unloaded\n");
276 }
277}
278
279#else /* !CONFIG_BACKLIGHT_CLASS_DEVICE */
280
281void radeon_atom_backlight_init(struct radeon_encoder *encoder)
282{
283}
284
285static void radeon_atom_backlight_exit(struct radeon_encoder *encoder)
286{
287}
288
289#endif
290
3f03ced8
AD		 291/* evil but including atombios.h is much worse */
292bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
293 struct drm_display_mode *mode);
294
3f03ced8 295static bool radeon_atom_mode_fixup(struct drm_encoder *encoder,
e811f5ae 296 const struct drm_display_mode *mode,
3f03ced8
AD		 297 struct drm_display_mode *adjusted_mode)
298{
299 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
300 struct drm_device *dev = encoder->dev;
301 struct radeon_device *rdev = dev->dev_private;
302
303 /* set the active encoder to connector routing */
304 radeon_encoder_set_active_device(encoder);
305 drm_mode_set_crtcinfo(adjusted_mode, 0);
306
307 /* hw bug */
308 if ((mode->flags & DRM_MODE_FLAG_INTERLACE)
309 && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2)))
310 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2;
311
da997620
AD		 312 /* get the native mode for scaling */
313 if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT)) {
3f03ced8 314 radeon_panel_mode_fixup(encoder, adjusted_mode);
da997620 315 } else if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) {
3f03ced8
AD		 316 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
317 if (tv_dac) {
318 if (tv_dac->tv_std == TV_STD_NTSC ||
319 tv_dac->tv_std == TV_STD_NTSC_J ||
320 tv_dac->tv_std == TV_STD_PAL_M)
321 radeon_atom_get_tv_timings(rdev, 0, adjusted_mode);
322 else
323 radeon_atom_get_tv_timings(rdev, 1, adjusted_mode);
324 }
da997620
AD		 325 } else if (radeon_encoder->rmx_type != RMX_OFF) {
326 radeon_panel_mode_fixup(encoder, adjusted_mode);
3f03ced8
AD		 327 }
328
329 if (ASIC_IS_DCE3(rdev) &&
330 ((radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
331 (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE))) {
332 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
93927f9c 333 radeon_dp_set_link_config(connector, adjusted_mode);
3f03ced8
AD		 334 }
335
336 return true;
337}
338
339static void
340atombios_dac_setup(struct drm_encoder *encoder, int action)
341{
342 struct drm_device *dev = encoder->dev;
343 struct radeon_device *rdev = dev->dev_private;
344 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
345 DAC_ENCODER_CONTROL_PS_ALLOCATION args;
346 int index = 0;
347 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
348
349 memset(&args, 0, sizeof(args));
350
351 switch (radeon_encoder->encoder_id) {
352 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
353 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
354 index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl);
355 break;
356 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
357 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
358 index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl);
359 break;
360 }
361
362 args.ucAction = action;
363
364 if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT))
365 args.ucDacStandard = ATOM_DAC1_PS2;
366 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
367 args.ucDacStandard = ATOM_DAC1_CV;
368 else {
369 switch (dac_info->tv_std) {
370 case TV_STD_PAL:
371 case TV_STD_PAL_M:
372 case TV_STD_SCART_PAL:
373 case TV_STD_SECAM:
374 case TV_STD_PAL_CN:
375 args.ucDacStandard = ATOM_DAC1_PAL;
376 break;
377 case TV_STD_NTSC:
378 case TV_STD_NTSC_J:
379 case TV_STD_PAL_60:
380 default:
381 args.ucDacStandard = ATOM_DAC1_NTSC;
382 break;
383 }
384 }
385 args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
386
387 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
388
389}
390
391static void
392atombios_tv_setup(struct drm_encoder *encoder, int action)
393{
394 struct drm_device *dev = encoder->dev;
395 struct radeon_device *rdev = dev->dev_private;
396 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
397 TV_ENCODER_CONTROL_PS_ALLOCATION args;
398 int index = 0;
399 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
400
401 memset(&args, 0, sizeof(args));
402
403 index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl);
404
405 args.sTVEncoder.ucAction = action;
406
407 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
408 args.sTVEncoder.ucTvStandard = ATOM_TV_CV;
409 else {
410 switch (dac_info->tv_std) {
411 case TV_STD_NTSC:
412 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
413 break;
414 case TV_STD_PAL:
415 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL;
416 break;
417 case TV_STD_PAL_M:
418 args.sTVEncoder.ucTvStandard = ATOM_TV_PALM;
419 break;
420 case TV_STD_PAL_60:
421 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60;
422 break;
423 case TV_STD_NTSC_J:
424 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ;
425 break;
426 case TV_STD_SCART_PAL:
427 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */
428 break;
429 case TV_STD_SECAM:
430 args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM;
431 break;
432 case TV_STD_PAL_CN:
433 args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN;
434 break;
435 default:
436 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
437 break;
438 }
439 }
440
441 args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
442
443 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
444
445}
446
1f0e2943
AD		 447static u8 radeon_atom_get_bpc(struct drm_encoder *encoder)
448{
1f0e2943
AD		 449 int bpc = 8;
450
7d5a33b0
AD		 451 if (encoder->crtc) {
452 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
453 bpc = radeon_crtc->bpc;
454 }
1f0e2943
AD		 455
456 switch (bpc) {
457 case 0:
458 return PANEL_BPC_UNDEFINE;
459 case 6:
460 return PANEL_6BIT_PER_COLOR;
461 case 8:
462 default:
463 return PANEL_8BIT_PER_COLOR;
464 case 10:
465 return PANEL_10BIT_PER_COLOR;
466 case 12:
467 return PANEL_12BIT_PER_COLOR;
468 case 16:
469 return PANEL_16BIT_PER_COLOR;
470 }
471}
472
3f03ced8
AD		 473union dvo_encoder_control {
474 ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION ext_tmds;
475 DVO_ENCODER_CONTROL_PS_ALLOCATION dvo;
476 DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 dvo_v3;
aea65641 477 DVO_ENCODER_CONTROL_PS_ALLOCATION_V1_4 dvo_v4;
3f03ced8
AD		 478};
479
480void
481atombios_dvo_setup(struct drm_encoder *encoder, int action)
482{
483 struct drm_device *dev = encoder->dev;
484 struct radeon_device *rdev = dev->dev_private;
485 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
486 union dvo_encoder_control args;
487 int index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
24153dd3 488 uint8_t frev, crev;
3f03ced8
AD		 489
490 memset(&args, 0, sizeof(args));
491
24153dd3
AD		 492 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
493 return;
494
afceb931
AD		 495 /* some R4xx chips have the wrong frev */
496 if (rdev->family <= CHIP_RV410)
497 frev = 1;
498
24153dd3
AD		 499 switch (frev) {
500 case 1:
501 switch (crev) {
502 case 1:
503 /* R4xx, R5xx */
504 args.ext_tmds.sXTmdsEncoder.ucEnable = action;
505
9aa59993 506 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
24153dd3
AD		 507 args.ext_tmds.sXTmdsEncoder.ucMisc |= PANEL_ENCODER_MISC_DUAL;
508
509 args.ext_tmds.sXTmdsEncoder.ucMisc |= ATOM_PANEL_MISC_888RGB;
510 break;
511 case 2:
512 /* RS600/690/740 */
513 args.dvo.sDVOEncoder.ucAction = action;
514 args.dvo.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
515 /* DFP1, CRT1, TV1 depending on the type of port */
516 args.dvo.sDVOEncoder.ucDeviceType = ATOM_DEVICE_DFP1_INDEX;
517
9aa59993 518 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
24153dd3
AD		 519 args.dvo.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute |= PANEL_ENCODER_MISC_DUAL;
520 break;
521 case 3:
522 /* R6xx */
523 args.dvo_v3.ucAction = action;
524 args.dvo_v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
525 args.dvo_v3.ucDVOConfig = 0; /* XXX */
526 break;
aea65641
AD		 527 case 4:
528 /* DCE8 */
529 args.dvo_v4.ucAction = action;
530 args.dvo_v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
531 args.dvo_v4.ucDVOConfig = 0; /* XXX */
532 args.dvo_v4.ucBitPerColor = radeon_atom_get_bpc(encoder);
533 break;
24153dd3
AD		 534 default:
535 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
536 break;
537 }
538 break;
539 default:
540 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
541 break;
3f03ced8
AD		 542 }
543
544 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
545}
546
547union lvds_encoder_control {
548 LVDS_ENCODER_CONTROL_PS_ALLOCATION v1;
549 LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2;
550};
551
552void
553atombios_digital_setup(struct drm_encoder *encoder, int action)
554{
555 struct drm_device *dev = encoder->dev;
556 struct radeon_device *rdev = dev->dev_private;
557 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
558 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
559 union lvds_encoder_control args;
560 int index = 0;
561 int hdmi_detected = 0;
562 uint8_t frev, crev;
563
564 if (!dig)
565 return;
566
567 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
568 hdmi_detected = 1;
569
570 memset(&args, 0, sizeof(args));
571
572 switch (radeon_encoder->encoder_id) {
573 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
574 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
575 break;
576 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
577 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
578 index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl);
579 break;
580 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
581 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
582 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
583 else
584 index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl);
585 break;
586 }
587
588 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
589 return;
590
591 switch (frev) {
592 case 1:
593 case 2:
594 switch (crev) {
595 case 1:
596 args.v1.ucMisc = 0;
597 args.v1.ucAction = action;
598 if (hdmi_detected)
599 args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
600 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
601 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
602 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
603 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
604 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
605 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
606 } else {
607 if (dig->linkb)
608 args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
9aa59993 609 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
3f03ced8
AD		 610 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
611 /*if (pScrn->rgbBits == 8) */
612 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
613 }
614 break;
615 case 2:
616 case 3:
617 args.v2.ucMisc = 0;
618 args.v2.ucAction = action;
619 if (crev == 3) {
620 if (dig->coherent_mode)
621 args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT;
622 }
623 if (hdmi_detected)
624 args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
625 args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
626 args.v2.ucTruncate = 0;
627 args.v2.ucSpatial = 0;
628 args.v2.ucTemporal = 0;
629 args.v2.ucFRC = 0;
630 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
631 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
632 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
633 if (dig->lcd_misc & ATOM_PANEL_MISC_SPATIAL) {
634 args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN;
635 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
636 args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH;
637 }
638 if (dig->lcd_misc & ATOM_PANEL_MISC_TEMPORAL) {
639 args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN;
640 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
641 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH;
642 if (((dig->lcd_misc >> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT) & 0x3) == 2)
643 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4;
644 }
645 } else {
646 if (dig->linkb)
647 args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
9aa59993 648 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
3f03ced8
AD		 649 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
650 }
651 break;
652 default:
653 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
654 break;
655 }
656 break;
657 default:
658 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
659 break;
660 }
661
662 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
663}
664
665int
666atombios_get_encoder_mode(struct drm_encoder *encoder)
667{
668 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3f03ced8
AD		 669 struct drm_connector *connector;
670 struct radeon_connector *radeon_connector;
671 struct radeon_connector_atom_dig *dig_connector;
672
673 /* dp bridges are always DP */
674 if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE)
675 return ATOM_ENCODER_MODE_DP;
676
677 /* DVO is always DVO */
a59fbb8e
AD		 678 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DVO1) ||
679 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1))
3f03ced8
AD		 680 return ATOM_ENCODER_MODE_DVO;
681
682 connector = radeon_get_connector_for_encoder(encoder);
683 /* if we don't have an active device yet, just use one of
684 * the connectors tied to the encoder.
685 */
686 if (!connector)
687 connector = radeon_get_connector_for_encoder_init(encoder);
688 radeon_connector = to_radeon_connector(connector);
689
690 switch (connector->connector_type) {
691 case DRM_MODE_CONNECTOR_DVII:
692 case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */
108dc8e8
AD		 693 if (radeon_audio != 0) {
694 if (radeon_connector->use_digital &&
695 (radeon_connector->audio == RADEON_AUDIO_ENABLE))
696 return ATOM_ENCODER_MODE_HDMI;
377bd8a9 697 else if (drm_detect_hdmi_monitor(radeon_connector_edid(connector)) &&
108dc8e8
AD		 698 (radeon_connector->audio == RADEON_AUDIO_AUTO))
699 return ATOM_ENCODER_MODE_HDMI;
700 else if (radeon_connector->use_digital)
701 return ATOM_ENCODER_MODE_DVI;
702 else
703 return ATOM_ENCODER_MODE_CRT;
704 } else if (radeon_connector->use_digital) {
3f03ced8 705 return ATOM_ENCODER_MODE_DVI;
108dc8e8 706 } else {
3f03ced8 707 return ATOM_ENCODER_MODE_CRT;
108dc8e8 708 }
3f03ced8
AD		 709 break;
710 case DRM_MODE_CONNECTOR_DVID:
711 case DRM_MODE_CONNECTOR_HDMIA:
712 default:
108dc8e8
AD		 713 if (radeon_audio != 0) {
714 if (radeon_connector->audio == RADEON_AUDIO_ENABLE)
715 return ATOM_ENCODER_MODE_HDMI;
377bd8a9 716 else if (drm_detect_hdmi_monitor(radeon_connector_edid(connector)) &&
108dc8e8
AD		 717 (radeon_connector->audio == RADEON_AUDIO_AUTO))
718 return ATOM_ENCODER_MODE_HDMI;
719 else
720 return ATOM_ENCODER_MODE_DVI;
721 } else {
3f03ced8 722 return ATOM_ENCODER_MODE_DVI;
108dc8e8 723 }
3f03ced8
AD		 724 break;
725 case DRM_MODE_CONNECTOR_LVDS:
726 return ATOM_ENCODER_MODE_LVDS;
727 break;
728 case DRM_MODE_CONNECTOR_DisplayPort:
729 dig_connector = radeon_connector->con_priv;
730 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
108dc8e8 731 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) {
3f03ced8 732 return ATOM_ENCODER_MODE_DP;
108dc8e8
AD		 733 } else if (radeon_audio != 0) {
734 if (radeon_connector->audio == RADEON_AUDIO_ENABLE)
735 return ATOM_ENCODER_MODE_HDMI;
377bd8a9 736 else if (drm_detect_hdmi_monitor(radeon_connector_edid(connector)) &&
108dc8e8
AD		 737 (radeon_connector->audio == RADEON_AUDIO_AUTO))
738 return ATOM_ENCODER_MODE_HDMI;
739 else
740 return ATOM_ENCODER_MODE_DVI;
741 } else {
3f03ced8 742 return ATOM_ENCODER_MODE_DVI;
108dc8e8 743 }
3f03ced8
AD		 744 break;
745 case DRM_MODE_CONNECTOR_eDP:
746 return ATOM_ENCODER_MODE_DP;
747 case DRM_MODE_CONNECTOR_DVIA:
748 case DRM_MODE_CONNECTOR_VGA:
749 return ATOM_ENCODER_MODE_CRT;
750 break;
751 case DRM_MODE_CONNECTOR_Composite:
752 case DRM_MODE_CONNECTOR_SVIDEO:
753 case DRM_MODE_CONNECTOR_9PinDIN:
754 /* fix me */
755 return ATOM_ENCODER_MODE_TV;
756 /*return ATOM_ENCODER_MODE_CV;*/
757 break;
758 }
759}
760
761/*
762 * DIG Encoder/Transmitter Setup
763 *
764 * DCE 3.0/3.1
765 * - 2 DIG transmitter blocks. UNIPHY (links A and B) and LVTMA.
766 * Supports up to 3 digital outputs
767 * - 2 DIG encoder blocks.
768 * DIG1 can drive UNIPHY link A or link B
769 * DIG2 can drive UNIPHY link B or LVTMA
770 *
771 * DCE 3.2
772 * - 3 DIG transmitter blocks. UNIPHY0/1/2 (links A and B).
773 * Supports up to 5 digital outputs
774 * - 2 DIG encoder blocks.
775 * DIG1/2 can drive UNIPHY0/1/2 link A or link B
776 *
2d415869 777 * DCE 4.0/5.0/6.0
3f03ced8
AD		 778 * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
779 * Supports up to 6 digital outputs
780 * - 6 DIG encoder blocks.
781 * - DIG to PHY mapping is hardcoded
782 * DIG1 drives UNIPHY0 link A, A+B
783 * DIG2 drives UNIPHY0 link B
784 * DIG3 drives UNIPHY1 link A, A+B
785 * DIG4 drives UNIPHY1 link B
786 * DIG5 drives UNIPHY2 link A, A+B
787 * DIG6 drives UNIPHY2 link B
788 *
789 * DCE 4.1
790 * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
791 * Supports up to 6 digital outputs
792 * - 2 DIG encoder blocks.
2d415869 793 * llano
3f03ced8 794 * DIG1/2 can drive UNIPHY0/1/2 link A or link B
2d415869
AD		 795 * ontario
796 * DIG1 drives UNIPHY0/1/2 link A
797 * DIG2 drives UNIPHY0/1/2 link B
3f03ced8
AD		 798 *
799 * Routing
800 * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links)
801 * Examples:
802 * crtc0 -> dig2 -> LVTMA links A+B -> TMDS/HDMI
803 * crtc1 -> dig1 -> UNIPHY0 link B -> DP
804 * crtc0 -> dig1 -> UNIPHY2 link A -> LVDS
805 * crtc1 -> dig2 -> UNIPHY1 link B+A -> TMDS/HDMI
806 */
807
808union dig_encoder_control {
809 DIG_ENCODER_CONTROL_PS_ALLOCATION v1;
810 DIG_ENCODER_CONTROL_PARAMETERS_V2 v2;
811 DIG_ENCODER_CONTROL_PARAMETERS_V3 v3;
812 DIG_ENCODER_CONTROL_PARAMETERS_V4 v4;
813};
814
815void
816atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode)
817{
818 struct drm_device *dev = encoder->dev;
819 struct radeon_device *rdev = dev->dev_private;
820 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
821 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
822 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
823 union dig_encoder_control args;
824 int index = 0;
825 uint8_t frev, crev;
826 int dp_clock = 0;
827 int dp_lane_count = 0;
828 int hpd_id = RADEON_HPD_NONE;
3f03ced8
AD		 829
830 if (connector) {
831 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
832 struct radeon_connector_atom_dig *dig_connector =
833 radeon_connector->con_priv;
834
835 dp_clock = dig_connector->dp_clock;
836 dp_lane_count = dig_connector->dp_lane_count;
837 hpd_id = radeon_connector->hpd.hpd;
3f03ced8
AD		 838 }
839
840 /* no dig encoder assigned */
841 if (dig->dig_encoder == -1)
842 return;
843
844 memset(&args, 0, sizeof(args));
845
846 if (ASIC_IS_DCE4(rdev))
847 index = GetIndexIntoMasterTable(COMMAND, DIGxEncoderControl);
848 else {
849 if (dig->dig_encoder)
850 index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl);
851 else
852 index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl);
853 }
854
855 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
856 return;
857
58cdcb8b
AD		 858 switch (frev) {
859 case 1:
860 switch (crev) {
861 case 1:
862 args.v1.ucAction = action;
863 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
864 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
865 args.v3.ucPanelMode = panel_mode;
866 else
867 args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder);
868
869 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode))
870 args.v1.ucLaneNum = dp_lane_count;
9aa59993 871 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
58cdcb8b
AD		 872 args.v1.ucLaneNum = 8;
873 else
874 args.v1.ucLaneNum = 4;
875
876 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode) && (dp_clock == 270000))
877 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
878 switch (radeon_encoder->encoder_id) {
879 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
880 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1;
881 break;
882 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
883 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
884 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2;
885 break;
886 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
887 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3;
888 break;
889 }
890 if (dig->linkb)
891 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB;
892 else
893 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKA;
3f03ced8 894 break;
58cdcb8b
AD		 895 case 2:
896 case 3:
897 args.v3.ucAction = action;
898 args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
899 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
900 args.v3.ucPanelMode = panel_mode;
901 else
902 args.v3.ucEncoderMode = atombios_get_encoder_mode(encoder);
903
2f6fa79a 904 if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode))
58cdcb8b 905 args.v3.ucLaneNum = dp_lane_count;
9aa59993 906 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
58cdcb8b
AD		 907 args.v3.ucLaneNum = 8;
908 else
909 args.v3.ucLaneNum = 4;
910
2f6fa79a 911 if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode) && (dp_clock == 270000))
58cdcb8b
AD		 912 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
913 args.v3.acConfig.ucDigSel = dig->dig_encoder;
1f0e2943 914 args.v3.ucBitPerColor = radeon_atom_get_bpc(encoder);
3f03ced8 915 break;
58cdcb8b
AD		 916 case 4:
917 args.v4.ucAction = action;
918 args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
919 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
920 args.v4.ucPanelMode = panel_mode;
921 else
922 args.v4.ucEncoderMode = atombios_get_encoder_mode(encoder);
923
2f6fa79a 924 if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode))
58cdcb8b 925 args.v4.ucLaneNum = dp_lane_count;
9aa59993 926 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
58cdcb8b
AD		 927 args.v4.ucLaneNum = 8;
928 else
929 args.v4.ucLaneNum = 4;
930
2f6fa79a 931 if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode)) {
e68adef8 932 if (dp_clock == 540000)
58cdcb8b 933 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ;
e68adef8
AD		 934 else if (dp_clock == 324000)
935 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_3_24GHZ;
936 else if (dp_clock == 270000)
937 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ;
938 else
939 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_1_62GHZ;
58cdcb8b
AD		 940 }
941 args.v4.acConfig.ucDigSel = dig->dig_encoder;
1f0e2943 942 args.v4.ucBitPerColor = radeon_atom_get_bpc(encoder);
58cdcb8b
AD		 943 if (hpd_id == RADEON_HPD_NONE)
944 args.v4.ucHPD_ID = 0;
945 else
946 args.v4.ucHPD_ID = hpd_id + 1;
3f03ced8 947 break;
3f03ced8 948 default:
58cdcb8b 949 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3f03ced8
AD		 950 break;
951 }
58cdcb8b
AD		 952 break;
953 default:
954 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
955 break;
3f03ced8
AD		 956 }
957
958 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
959
960}
961
962union dig_transmitter_control {
963 DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1;
964 DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2;
965 DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3;
966 DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 v4;
47aef7a8 967 DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5 v5;
3f03ced8
AD		 968};
969
970void
971atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set)
972{
973 struct drm_device *dev = encoder->dev;
974 struct radeon_device *rdev = dev->dev_private;
975 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
976 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
977 struct drm_connector *connector;
978 union dig_transmitter_control args;
979 int index = 0;
980 uint8_t frev, crev;
981 bool is_dp = false;
982 int pll_id = 0;
983 int dp_clock = 0;
984 int dp_lane_count = 0;
985 int connector_object_id = 0;
986 int igp_lane_info = 0;
987 int dig_encoder = dig->dig_encoder;
47aef7a8 988 int hpd_id = RADEON_HPD_NONE;
3f03ced8
AD		 989
990 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
991 connector = radeon_get_connector_for_encoder_init(encoder);
992 /* just needed to avoid bailing in the encoder check. the encoder
993 * isn't used for init
994 */
995 dig_encoder = 0;
996 } else
997 connector = radeon_get_connector_for_encoder(encoder);
998
999 if (connector) {
1000 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1001 struct radeon_connector_atom_dig *dig_connector =
1002 radeon_connector->con_priv;
1003
47aef7a8 1004 hpd_id = radeon_connector->hpd.hpd;
3f03ced8
AD		 1005 dp_clock = dig_connector->dp_clock;
1006 dp_lane_count = dig_connector->dp_lane_count;
1007 connector_object_id =
1008 (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
1009 igp_lane_info = dig_connector->igp_lane_info;
1010 }
1011
a3b08294
AD		 1012 if (encoder->crtc) {
1013 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1014 pll_id = radeon_crtc->pll_id;
1015 }
1016
3f03ced8
AD		 1017 /* no dig encoder assigned */
1018 if (dig_encoder == -1)
1019 return;
1020
1021 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)))
1022 is_dp = true;
1023
1024 memset(&args, 0, sizeof(args));
1025
1026 switch (radeon_encoder->encoder_id) {
1027 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1028 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1029 break;
1030 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1031 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1032 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
e68adef8 1033 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
3f03ced8
AD		 1034 index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
1035 break;
1036 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1037 index = GetIndexIntoMasterTable(COMMAND, LVTMATransmitterControl);
1038 break;
1039 }
1040
1041 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1042 return;
1043
a3b08294
AD		 1044 switch (frev) {
1045 case 1:
1046 switch (crev) {
1047 case 1:
1048 args.v1.ucAction = action;
1049 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1050 args.v1.usInitInfo = cpu_to_le16(connector_object_id);
1051 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1052 args.v1.asMode.ucLaneSel = lane_num;
1053 args.v1.asMode.ucLaneSet = lane_set;
1054 } else {
1055 if (is_dp)
6e76a2df 1056 args.v1.usPixelClock = cpu_to_le16(dp_clock / 10);
9aa59993 1057 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
a3b08294
AD		 1058 args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1059 else
1060 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1061 }
3f03ced8 1062
a3b08294 1063 args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL;
3f03ced8 1064
a3b08294
AD		 1065 if (dig_encoder)
1066 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER;
1067 else
1068 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER;
1069
1070 if ((rdev->flags & RADEON_IS_IGP) &&
1071 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY)) {
9aa59993
AD		 1072 if (is_dp ||
1073 !radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) {
a3b08294
AD		 1074 if (igp_lane_info & 0x1)
1075 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3;
1076 else if (igp_lane_info & 0x2)
1077 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7;
1078 else if (igp_lane_info & 0x4)
1079 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11;
1080 else if (igp_lane_info & 0x8)
1081 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15;
1082 } else {
1083 if (igp_lane_info & 0x3)
1084 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7;
1085 else if (igp_lane_info & 0xc)
1086 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15;
1087 }
1088 }
1089
1090 if (dig->linkb)
1091 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB;
1092 else
1093 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA;
1094
1095 if (is_dp)
1096 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
1097 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1098 if (dig->coherent_mode)
1099 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
9aa59993 1100 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
a3b08294
AD		 1101 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK;
1102 }
1103 break;
1104 case 2:
1105 args.v2.ucAction = action;
1106 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1107 args.v2.usInitInfo = cpu_to_le16(connector_object_id);
1108 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1109 args.v2.asMode.ucLaneSel = lane_num;
1110 args.v2.asMode.ucLaneSet = lane_set;
1111 } else {
1112 if (is_dp)
6e76a2df 1113 args.v2.usPixelClock = cpu_to_le16(dp_clock / 10);
9aa59993 1114 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
a3b08294
AD		 1115 args.v2.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1116 else
1117 args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1118 }
1119
1120 args.v2.acConfig.ucEncoderSel = dig_encoder;
1121 if (dig->linkb)
1122 args.v2.acConfig.ucLinkSel = 1;
1123
1124 switch (radeon_encoder->encoder_id) {
1125 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1126 args.v2.acConfig.ucTransmitterSel = 0;
1127 break;
1128 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1129 args.v2.acConfig.ucTransmitterSel = 1;
1130 break;
1131 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1132 args.v2.acConfig.ucTransmitterSel = 2;
1133 break;
1134 }
3f03ced8 1135
3f03ced8 1136 if (is_dp) {
a3b08294
AD		 1137 args.v2.acConfig.fCoherentMode = 1;
1138 args.v2.acConfig.fDPConnector = 1;
1139 } else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1140 if (dig->coherent_mode)
1141 args.v2.acConfig.fCoherentMode = 1;
9aa59993 1142 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
a3b08294
AD		 1143 args.v2.acConfig.fDualLinkConnector = 1;
1144 }
1145 break;
1146 case 3:
1147 args.v3.ucAction = action;
1148 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1149 args.v3.usInitInfo = cpu_to_le16(connector_object_id);
1150 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1151 args.v3.asMode.ucLaneSel = lane_num;
1152 args.v3.asMode.ucLaneSet = lane_set;
1153 } else {
1154 if (is_dp)
6e76a2df 1155 args.v3.usPixelClock = cpu_to_le16(dp_clock / 10);
9aa59993 1156 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
a3b08294 1157 args.v3.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
3f03ced8 1158 else
a3b08294
AD		 1159 args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1160 }
1161
1162 if (is_dp)
1163 args.v3.ucLaneNum = dp_lane_count;
9aa59993 1164 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
a3b08294
AD		 1165 args.v3.ucLaneNum = 8;
1166 else
1167 args.v3.ucLaneNum = 4;
1168
1169 if (dig->linkb)
1170 args.v3.acConfig.ucLinkSel = 1;
1171 if (dig_encoder & 1)
1172 args.v3.acConfig.ucEncoderSel = 1;
1173
1174 /* Select the PLL for the PHY
1175 * DP PHY should be clocked from external src if there is
1176 * one.
1177 */
3f03ced8
AD		 1178 /* On DCE4, if there is an external clock, it generates the DP ref clock */
1179 if (is_dp && rdev->clock.dp_extclk)
1180 args.v3.acConfig.ucRefClkSource = 2; /* external src */
1181 else
1182 args.v3.acConfig.ucRefClkSource = pll_id;
3f03ced8 1183
a3b08294
AD		 1184 switch (radeon_encoder->encoder_id) {
1185 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1186 args.v3.acConfig.ucTransmitterSel = 0;
1187 break;
1188 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1189 args.v3.acConfig.ucTransmitterSel = 1;
1190 break;
1191 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1192 args.v3.acConfig.ucTransmitterSel = 2;
1193 break;
1194 }
3f03ced8 1195
a3b08294
AD		 1196 if (is_dp)
1197 args.v3.acConfig.fCoherentMode = 1; /* DP requires coherent */
1198 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1199 if (dig->coherent_mode)
1200 args.v3.acConfig.fCoherentMode = 1;
9aa59993 1201 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
a3b08294
AD		 1202 args.v3.acConfig.fDualLinkConnector = 1;
1203 }
3f03ced8 1204 break;
a3b08294
AD		 1205 case 4:
1206 args.v4.ucAction = action;
1207 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1208 args.v4.usInitInfo = cpu_to_le16(connector_object_id);
1209 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1210 args.v4.asMode.ucLaneSel = lane_num;
1211 args.v4.asMode.ucLaneSet = lane_set;
3f03ced8 1212 } else {
a3b08294 1213 if (is_dp)
6e76a2df 1214 args.v4.usPixelClock = cpu_to_le16(dp_clock / 10);
9aa59993 1215 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
a3b08294
AD		 1216 args.v4.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1217 else
1218 args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
3f03ced8 1219 }
3f03ced8 1220
a3b08294
AD		 1221 if (is_dp)
1222 args.v4.ucLaneNum = dp_lane_count;
9aa59993 1223 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
a3b08294
AD		 1224 args.v4.ucLaneNum = 8;
1225 else
1226 args.v4.ucLaneNum = 4;
3f03ced8 1227
a3b08294
AD		 1228 if (dig->linkb)
1229 args.v4.acConfig.ucLinkSel = 1;
1230 if (dig_encoder & 1)
1231 args.v4.acConfig.ucEncoderSel = 1;
1232
1233 /* Select the PLL for the PHY
1234 * DP PHY should be clocked from external src if there is
1235 * one.
1236 */
1237 /* On DCE5 DCPLL usually generates the DP ref clock */
1238 if (is_dp) {
1239 if (rdev->clock.dp_extclk)
1240 args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_EXTCLK;
1241 else
1242 args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_DCPLL;
1243 } else
1244 args.v4.acConfig.ucRefClkSource = pll_id;
1245
1246 switch (radeon_encoder->encoder_id) {
1247 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1248 args.v4.acConfig.ucTransmitterSel = 0;
1249 break;
1250 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1251 args.v4.acConfig.ucTransmitterSel = 1;
1252 break;
1253 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1254 args.v4.acConfig.ucTransmitterSel = 2;
1255 break;
1256 }
1257
1258 if (is_dp)
1259 args.v4.acConfig.fCoherentMode = 1; /* DP requires coherent */
1260 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1261 if (dig->coherent_mode)
1262 args.v4.acConfig.fCoherentMode = 1;
9aa59993 1263 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
a3b08294
AD		 1264 args.v4.acConfig.fDualLinkConnector = 1;
1265 }
1266 break;
47aef7a8
AD		 1267 case 5:
1268 args.v5.ucAction = action;
1269 if (is_dp)
1270 args.v5.usSymClock = cpu_to_le16(dp_clock / 10);
1271 else
1272 args.v5.usSymClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1273
1274 switch (radeon_encoder->encoder_id) {
1275 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1276 if (dig->linkb)
1277 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYB;
1278 else
1279 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYA;
1280 break;
1281 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1282 if (dig->linkb)
1283 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYD;
1284 else
1285 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYC;
1286 break;
1287 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1288 if (dig->linkb)
1289 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYF;
1290 else
1291 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYE;
1292 break;
e68adef8
AD		 1293 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
1294 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYG;
1295 break;
47aef7a8
AD		 1296 }
1297 if (is_dp)
1298 args.v5.ucLaneNum = dp_lane_count;
d03874c8 1299 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
47aef7a8
AD		 1300 args.v5.ucLaneNum = 8;
1301 else
1302 args.v5.ucLaneNum = 4;
1303 args.v5.ucConnObjId = connector_object_id;
1304 args.v5.ucDigMode = atombios_get_encoder_mode(encoder);
1305
1306 if (is_dp && rdev->clock.dp_extclk)
1307 args.v5.asConfig.ucPhyClkSrcId = ENCODER_REFCLK_SRC_EXTCLK;
1308 else
1309 args.v5.asConfig.ucPhyClkSrcId = pll_id;
1310
1311 if (is_dp)
1312 args.v5.asConfig.ucCoherentMode = 1; /* DP requires coherent */
1313 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1314 if (dig->coherent_mode)
1315 args.v5.asConfig.ucCoherentMode = 1;
1316 }
1317 if (hpd_id == RADEON_HPD_NONE)
1318 args.v5.asConfig.ucHPDSel = 0;
1319 else
1320 args.v5.asConfig.ucHPDSel = hpd_id + 1;
1321 args.v5.ucDigEncoderSel = 1 << dig_encoder;
1322 args.v5.ucDPLaneSet = lane_set;
1323 break;
a3b08294
AD		 1324 default:
1325 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1326 break;
3f03ced8 1327 }
a3b08294
AD		 1328 break;
1329 default:
1330 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1331 break;
3f03ced8
AD		 1332 }
1333
1334 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1335}
1336
1337bool
1338atombios_set_edp_panel_power(struct drm_connector *connector, int action)
1339{
1340 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1341 struct drm_device *dev = radeon_connector->base.dev;
1342 struct radeon_device *rdev = dev->dev_private;
1343 union dig_transmitter_control args;
1344 int index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
1345 uint8_t frev, crev;
1346
1347 if (connector->connector_type != DRM_MODE_CONNECTOR_eDP)
1348 goto done;
1349
1350 if (!ASIC_IS_DCE4(rdev))
1351 goto done;
1352
1353 if ((action != ATOM_TRANSMITTER_ACTION_POWER_ON) &&
1354 (action != ATOM_TRANSMITTER_ACTION_POWER_OFF))
1355 goto done;
1356
1357 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1358 goto done;
1359
1360 memset(&args, 0, sizeof(args));
1361
1362 args.v1.ucAction = action;
1363
1364 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1365
1366 /* wait for the panel to power up */
1367 if (action == ATOM_TRANSMITTER_ACTION_POWER_ON) {
1368 int i;
1369
1370 for (i = 0; i < 300; i++) {
1371 if (radeon_hpd_sense(rdev, radeon_connector->hpd.hpd))
1372 return true;
1373 mdelay(1);
1374 }
1375 return false;
1376 }
1377done:
1378 return true;
1379}
1380
1381union external_encoder_control {
1382 EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION v1;
1383 EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3 v3;
1384};
1385
1386static void
1387atombios_external_encoder_setup(struct drm_encoder *encoder,
1388 struct drm_encoder *ext_encoder,
1389 int action)
1390{
1391 struct drm_device *dev = encoder->dev;
1392 struct radeon_device *rdev = dev->dev_private;
1393 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1394 struct radeon_encoder *ext_radeon_encoder = to_radeon_encoder(ext_encoder);
1395 union external_encoder_control args;
1396 struct drm_connector *connector;
1397 int index = GetIndexIntoMasterTable(COMMAND, ExternalEncoderControl);
1398 u8 frev, crev;
1399 int dp_clock = 0;
1400 int dp_lane_count = 0;
1401 int connector_object_id = 0;
1402 u32 ext_enum = (ext_radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
3f03ced8
AD		 1403
1404 if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)
1405 connector = radeon_get_connector_for_encoder_init(encoder);
1406 else
1407 connector = radeon_get_connector_for_encoder(encoder);
1408
1409 if (connector) {
1410 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1411 struct radeon_connector_atom_dig *dig_connector =
1412 radeon_connector->con_priv;
1413
1414 dp_clock = dig_connector->dp_clock;
1415 dp_lane_count = dig_connector->dp_lane_count;
1416 connector_object_id =
1417 (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
3f03ced8
AD		 1418 }
1419
1420 memset(&args, 0, sizeof(args));
1421
1422 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1423 return;
1424
1425 switch (frev) {
1426 case 1:
1427 /* no params on frev 1 */
1428 break;
1429 case 2:
1430 switch (crev) {
1431 case 1:
1432 case 2:
1433 args.v1.sDigEncoder.ucAction = action;
1434 args.v1.sDigEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1435 args.v1.sDigEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1436
1437 if (ENCODER_MODE_IS_DP(args.v1.sDigEncoder.ucEncoderMode)) {
1438 if (dp_clock == 270000)
1439 args.v1.sDigEncoder.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
1440 args.v1.sDigEncoder.ucLaneNum = dp_lane_count;
9aa59993 1441 } else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
3f03ced8
AD		 1442 args.v1.sDigEncoder.ucLaneNum = 8;
1443 else
1444 args.v1.sDigEncoder.ucLaneNum = 4;
1445 break;
1446 case 3:
1447 args.v3.sExtEncoder.ucAction = action;
1448 if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)
1449 args.v3.sExtEncoder.usConnectorId = cpu_to_le16(connector_object_id);
1450 else
1451 args.v3.sExtEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1452 args.v3.sExtEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1453
1454 if (ENCODER_MODE_IS_DP(args.v3.sExtEncoder.ucEncoderMode)) {
1455 if (dp_clock == 270000)
1456 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
1457 else if (dp_clock == 540000)
1458 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ;
1459 args.v3.sExtEncoder.ucLaneNum = dp_lane_count;
9aa59993 1460 } else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
3f03ced8
AD		 1461 args.v3.sExtEncoder.ucLaneNum = 8;
1462 else
1463 args.v3.sExtEncoder.ucLaneNum = 4;
1464 switch (ext_enum) {
1465 case GRAPH_OBJECT_ENUM_ID1:
1466 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER1;
1467 break;
1468 case GRAPH_OBJECT_ENUM_ID2:
1469 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER2;
1470 break;
1471 case GRAPH_OBJECT_ENUM_ID3:
1472 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER3;
1473 break;
1474 }
1f0e2943 1475 args.v3.sExtEncoder.ucBitPerColor = radeon_atom_get_bpc(encoder);
3f03ced8
AD		 1476 break;
1477 default:
1478 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1479 return;
1480 }
1481 break;
1482 default:
1483 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1484 return;
1485 }
1486 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1487}
1488
1489static void
1490atombios_yuv_setup(struct drm_encoder *encoder, bool enable)
1491{
1492 struct drm_device *dev = encoder->dev;
1493 struct radeon_device *rdev = dev->dev_private;
1494 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1495 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1496 ENABLE_YUV_PS_ALLOCATION args;
1497 int index = GetIndexIntoMasterTable(COMMAND, EnableYUV);
1498 uint32_t temp, reg;
1499
1500 memset(&args, 0, sizeof(args));
1501
1502 if (rdev->family >= CHIP_R600)
1503 reg = R600_BIOS_3_SCRATCH;
1504 else
1505 reg = RADEON_BIOS_3_SCRATCH;
1506
1507 /* XXX: fix up scratch reg handling */
1508 temp = RREG32(reg);
1509 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1510 WREG32(reg, (ATOM_S3_TV1_ACTIVE |
1511 (radeon_crtc->crtc_id << 18)));
1512 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1513 WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24)));
1514 else
1515 WREG32(reg, 0);
1516
1517 if (enable)
1518 args.ucEnable = ATOM_ENABLE;
1519 args.ucCRTC = radeon_crtc->crtc_id;
1520
1521 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1522
1523 WREG32(reg, temp);
1524}
1525
1526static void
1527radeon_atom_encoder_dpms_avivo(struct drm_encoder *encoder, int mode)
1528{
1529 struct drm_device *dev = encoder->dev;
1530 struct radeon_device *rdev = dev->dev_private;
1531 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1532 DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
1533 int index = 0;
1534
1535 memset(&args, 0, sizeof(args));
1536
1537 switch (radeon_encoder->encoder_id) {
1538 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1539 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1540 index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl);
1541 break;
1542 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1543 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1544 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1545 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1546 break;
1547 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1548 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1549 break;
1550 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1551 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1552 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1553 else
1554 index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl);
1555 break;
1556 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1557 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1558 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1559 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1560 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1561 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1562 else
1563 index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl);
1564 break;
1565 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1566 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1567 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1568 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1569 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1570 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1571 else
1572 index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl);
1573 break;
1574 default:
1575 return;
1576 }
1577
1578 switch (mode) {
1579 case DRM_MODE_DPMS_ON:
1580 args.ucAction = ATOM_ENABLE;
1581 /* workaround for DVOOutputControl on some RS690 systems */
1582 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DDI) {
1583 u32 reg = RREG32(RADEON_BIOS_3_SCRATCH);
1584 WREG32(RADEON_BIOS_3_SCRATCH, reg & ~ATOM_S3_DFP2I_ACTIVE);
1585 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1586 WREG32(RADEON_BIOS_3_SCRATCH, reg);
1587 } else
1588 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1589 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1590 args.ucAction = ATOM_LCD_BLON;
1591 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1592 }
1593 break;
1594 case DRM_MODE_DPMS_STANDBY:
1595 case DRM_MODE_DPMS_SUSPEND:
1596 case DRM_MODE_DPMS_OFF:
1597 args.ucAction = ATOM_DISABLE;
1598 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1599 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1600 args.ucAction = ATOM_LCD_BLOFF;
1601 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1602 }
1603 break;
1604 }
1605}
1606
1607static void
1608radeon_atom_encoder_dpms_dig(struct drm_encoder *encoder, int mode)
1609{
1610 struct drm_device *dev = encoder->dev;
1611 struct radeon_device *rdev = dev->dev_private;
1612 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
8d1af57a
AD		 1613 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
1614 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
3f03ced8
AD		 1615 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1616 struct radeon_connector *radeon_connector = NULL;
1617 struct radeon_connector_atom_dig *radeon_dig_connector = NULL;
6f50e075 1618 bool travis_quirk = false;
3f03ced8
AD		 1619
1620 if (connector) {
1621 radeon_connector = to_radeon_connector(connector);
1622 radeon_dig_connector = radeon_connector->con_priv;
6f50e075
AD		 1623 if ((radeon_connector_encoder_get_dp_bridge_encoder_id(connector) ==
1624 ENCODER_OBJECT_ID_TRAVIS) &&
1625 (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) &&
1626 !ASIC_IS_DCE5(rdev))
1627 travis_quirk = true;
3f03ced8
AD		 1628 }
1629
1630 switch (mode) {
1631 case DRM_MODE_DPMS_ON:
8d1af57a
AD		 1632 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) {
1633 if (!connector)
1634 dig->panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
1635 else
1636 dig->panel_mode = radeon_dp_get_panel_mode(encoder, connector);
1637
1638 /* setup and enable the encoder */
1639 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);
1640 atombios_dig_encoder_setup(encoder,
1641 ATOM_ENCODER_CMD_SETUP_PANEL_MODE,
1642 dig->panel_mode);
1643 if (ext_encoder) {
1644 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev))
1645 atombios_external_encoder_setup(encoder, ext_encoder,
1646 EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP);
fcedac67 1647 }
8d1af57a
AD		 1648 } else if (ASIC_IS_DCE4(rdev)) {
1649 /* setup and enable the encoder */
1650 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);
8d1af57a
AD		 1651 } else {
1652 /* setup and enable the encoder and transmitter */
1653 atombios_dig_encoder_setup(encoder, ATOM_ENABLE, 0);
1654 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0);
fcedac67 1655 }
3f03ced8
AD		 1656 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
1657 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1658 atombios_set_edp_panel_power(connector,
1659 ATOM_TRANSMITTER_ACTION_POWER_ON);
1660 radeon_dig_connector->edp_on = true;
1661 }
6f50e075
AD		 1662 }
1663 /* enable the transmitter */
1664 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1665 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
1666 /* DP_SET_POWER_D0 is set in radeon_dp_link_train */
3f03ced8
AD		 1667 radeon_dp_link_train(encoder, connector);
1668 if (ASIC_IS_DCE4(rdev))
1669 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON, 0);
1670 }
1671 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
6f50e075
AD		 1672 atombios_dig_transmitter_setup(encoder,
1673 ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0);
1674 if (ext_encoder)
1675 atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE);
3f03ced8
AD		 1676 break;
1677 case DRM_MODE_DPMS_STANDBY:
1678 case DRM_MODE_DPMS_SUSPEND:
1679 case DRM_MODE_DPMS_OFF:
6f50e075
AD		 1680 if (ASIC_IS_DCE4(rdev)) {
1681 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector)
1682 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0);
1683 }
1684 if (ext_encoder)
1685 atombios_external_encoder_setup(encoder, ext_encoder, ATOM_DISABLE);
1686 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1687 atombios_dig_transmitter_setup(encoder,
1688 ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0);
1689
1690 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) &&
1691 connector && !travis_quirk)
1692 radeon_dp_set_rx_power_state(connector, DP_SET_POWER_D3);
40390961 1693 if (ASIC_IS_DCE4(rdev)) {
8d1af57a 1694 /* disable the transmitter */
6f50e075
AD		 1695 atombios_dig_transmitter_setup(encoder,
1696 ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
8d1af57a
AD		 1697 } else {
1698 /* disable the encoder and transmitter */
6f50e075
AD		 1699 atombios_dig_transmitter_setup(encoder,
1700 ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
8d1af57a
AD		 1701 atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0);
1702 }
3f03ced8 1703 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
6f50e075
AD		 1704 if (travis_quirk)
1705 radeon_dp_set_rx_power_state(connector, DP_SET_POWER_D3);
3f03ced8
AD		 1706 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1707 atombios_set_edp_panel_power(connector,
1708 ATOM_TRANSMITTER_ACTION_POWER_OFF);
1709 radeon_dig_connector->edp_on = false;
1710 }
1711 }
3f03ced8
AD		 1712 break;
1713 }
1714}
1715
1716static void
1717radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
1718{
1719 struct drm_device *dev = encoder->dev;
1720 struct radeon_device *rdev = dev->dev_private;
1721 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3f03ced8
AD		 1722
1723 DRM_DEBUG_KMS("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n",
1724 radeon_encoder->encoder_id, mode, radeon_encoder->devices,
1725 radeon_encoder->active_device);
1726 switch (radeon_encoder->encoder_id) {
1727 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1728 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1729 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1730 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1731 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1732 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1733 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1734 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1735 radeon_atom_encoder_dpms_avivo(encoder, mode);
1736 break;
1737 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1738 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1739 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
e68adef8 1740 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
3f03ced8
AD		 1741 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1742 radeon_atom_encoder_dpms_dig(encoder, mode);
1743 break;
1744 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1745 if (ASIC_IS_DCE5(rdev)) {
1746 switch (mode) {
1747 case DRM_MODE_DPMS_ON:
1748 atombios_dvo_setup(encoder, ATOM_ENABLE);
1749 break;
1750 case DRM_MODE_DPMS_STANDBY:
1751 case DRM_MODE_DPMS_SUSPEND:
1752 case DRM_MODE_DPMS_OFF:
1753 atombios_dvo_setup(encoder, ATOM_DISABLE);
1754 break;
1755 }
1756 } else if (ASIC_IS_DCE3(rdev))
1757 radeon_atom_encoder_dpms_dig(encoder, mode);
1758 else
1759 radeon_atom_encoder_dpms_avivo(encoder, mode);
1760 break;
1761 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1762 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1763 if (ASIC_IS_DCE5(rdev)) {
1764 switch (mode) {
1765 case DRM_MODE_DPMS_ON:
1766 atombios_dac_setup(encoder, ATOM_ENABLE);
1767 break;
1768 case DRM_MODE_DPMS_STANDBY:
1769 case DRM_MODE_DPMS_SUSPEND:
1770 case DRM_MODE_DPMS_OFF:
1771 atombios_dac_setup(encoder, ATOM_DISABLE);
1772 break;
1773 }
1774 } else
1775 radeon_atom_encoder_dpms_avivo(encoder, mode);
1776 break;
1777 default:
1778 return;
1779 }
1780
3f03ced8
AD		 1781 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
1782
1783}
1784
1785union crtc_source_param {
1786 SELECT_CRTC_SOURCE_PS_ALLOCATION v1;
1787 SELECT_CRTC_SOURCE_PARAMETERS_V2 v2;
1788};
1789
1790static void
1791atombios_set_encoder_crtc_source(struct drm_encoder *encoder)
1792{
1793 struct drm_device *dev = encoder->dev;
1794 struct radeon_device *rdev = dev->dev_private;
1795 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1796 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1797 union crtc_source_param args;
1798 int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source);
1799 uint8_t frev, crev;
1800 struct radeon_encoder_atom_dig *dig;
1801
1802 memset(&args, 0, sizeof(args));
1803
1804 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1805 return;
1806
1807 switch (frev) {
1808 case 1:
1809 switch (crev) {
1810 case 1:
1811 default:
1812 if (ASIC_IS_AVIVO(rdev))
1813 args.v1.ucCRTC = radeon_crtc->crtc_id;
1814 else {
1815 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) {
1816 args.v1.ucCRTC = radeon_crtc->crtc_id;
1817 } else {
1818 args.v1.ucCRTC = radeon_crtc->crtc_id << 2;
1819 }
1820 }
1821 switch (radeon_encoder->encoder_id) {
1822 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1823 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1824 args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX;
1825 break;
1826 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1827 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1828 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT)
1829 args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX;
1830 else
1831 args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX;
1832 break;
1833 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1834 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1835 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1836 args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX;
1837 break;
1838 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1839 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1840 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1841 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1842 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1843 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1844 else
1845 args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX;
1846 break;
1847 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1848 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1849 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1850 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1851 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1852 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1853 else
1854 args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX;
1855 break;
1856 }
1857 break;
1858 case 2:
1859 args.v2.ucCRTC = radeon_crtc->crtc_id;
1860 if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE) {
1861 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1862
1863 if (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)
1864 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS;
1865 else if (connector->connector_type == DRM_MODE_CONNECTOR_VGA)
1866 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_CRT;
1867 else
1868 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
64252835
AD		 1869 } else if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1870 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS;
1871 } else {
3f03ced8 1872 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
64252835 1873 }
3f03ced8
AD		 1874 switch (radeon_encoder->encoder_id) {
1875 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1876 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1877 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
e68adef8 1878 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
3f03ced8
AD		 1879 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1880 dig = radeon_encoder->enc_priv;
1881 switch (dig->dig_encoder) {
1882 case 0:
1883 args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
1884 break;
1885 case 1:
1886 args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
1887 break;
1888 case 2:
1889 args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID;
1890 break;
1891 case 3:
1892 args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID;
1893 break;
1894 case 4:
1895 args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID;
1896 break;
1897 case 5:
1898 args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID;
1899 break;
e68adef8
AD		 1900 case 6:
1901 args.v2.ucEncoderID = ASIC_INT_DIG7_ENCODER_ID;
1902 break;
3f03ced8
AD		 1903 }
1904 break;
1905 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1906 args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID;
1907 break;
1908 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1909 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1910 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1911 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1912 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1913 else
1914 args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID;
1915 break;
1916 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1917 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1918 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1919 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1920 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1921 else
1922 args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID;
1923 break;
1924 }
1925 break;
1926 }
1927 break;
1928 default:
1929 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1930 return;
1931 }
1932
1933 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1934
1935 /* update scratch regs with new routing */
1936 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
1937}
1938
1939static void
1940atombios_apply_encoder_quirks(struct drm_encoder *encoder,
1941 struct drm_display_mode *mode)
1942{
1943 struct drm_device *dev = encoder->dev;
1944 struct radeon_device *rdev = dev->dev_private;
1945 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1946 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1947
1948 /* Funky macbooks */
1949 if ((dev->pdev->device == 0x71C5) &&
1950 (dev->pdev->subsystem_vendor == 0x106b) &&
1951 (dev->pdev->subsystem_device == 0x0080)) {
1952 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
1953 uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL);
1954
1955 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN;
1956 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN;
1957
1958 WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control);
1959 }
1960 }
1961
1962 /* set scaler clears this on some chips */
1963 if (ASIC_IS_AVIVO(rdev) &&
1964 (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)))) {
d798f2f2
AD		 1965 if (ASIC_IS_DCE8(rdev)) {
1966 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1967 WREG32(CIK_LB_DATA_FORMAT + radeon_crtc->crtc_offset,
1968 CIK_INTERLEAVE_EN);
1969 else
1970 WREG32(CIK_LB_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
1971 } else if (ASIC_IS_DCE4(rdev)) {
3f03ced8
AD		 1972 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1973 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset,
1974 EVERGREEN_INTERLEAVE_EN);
1975 else
1976 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
1977 } else {
1978 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1979 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
1980 AVIVO_D1MODE_INTERLEAVE_EN);
1981 else
1982 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
1983 }
1984 }
1985}
1986
1987static int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder)
1988{
1989 struct drm_device *dev = encoder->dev;
1990 struct radeon_device *rdev = dev->dev_private;
1991 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1992 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1993 struct drm_encoder *test_encoder;
41fa5437 1994 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
3f03ced8
AD		 1995 uint32_t dig_enc_in_use = 0;
1996
41fa5437
AD		 1997 if (ASIC_IS_DCE6(rdev)) {
1998 /* DCE6 */
1999 switch (radeon_encoder->encoder_id) {
2000 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2001 if (dig->linkb)
2002 return 1;
2003 else
2004 return 0;
2005 break;
2006 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2007 if (dig->linkb)
2008 return 3;
2009 else
2010 return 2;
2011 break;
2012 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2013 if (dig->linkb)
2014 return 5;
2015 else
2016 return 4;
2017 break;
e68adef8
AD		 2018 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2019 return 6;
2020 break;
41fa5437
AD		 2021 }
2022 } else if (ASIC_IS_DCE4(rdev)) {
2023 /* DCE4/5 */
2024 if (ASIC_IS_DCE41(rdev) && !ASIC_IS_DCE61(rdev)) {
3f03ced8
AD		 2025 /* ontario follows DCE4 */
2026 if (rdev->family == CHIP_PALM) {
2027 if (dig->linkb)
2028 return 1;
2029 else
2030 return 0;
2031 } else
2032 /* llano follows DCE3.2 */
2033 return radeon_crtc->crtc_id;
2034 } else {
2035 switch (radeon_encoder->encoder_id) {
2036 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2037 if (dig->linkb)
2038 return 1;
2039 else
2040 return 0;
2041 break;
2042 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2043 if (dig->linkb)
2044 return 3;
2045 else
2046 return 2;
2047 break;
2048 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2049 if (dig->linkb)
2050 return 5;
2051 else
2052 return 4;
2053 break;
2054 }
2055 }
2056 }
2057
2058 /* on DCE32 and encoder can driver any block so just crtc id */
2059 if (ASIC_IS_DCE32(rdev)) {
2060 return radeon_crtc->crtc_id;
2061 }
2062
2063 /* on DCE3 - LVTMA can only be driven by DIGB */
2064 list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
2065 struct radeon_encoder *radeon_test_encoder;
2066
2067 if (encoder == test_encoder)
2068 continue;
2069
2070 if (!radeon_encoder_is_digital(test_encoder))
2071 continue;
2072
2073 radeon_test_encoder = to_radeon_encoder(test_encoder);
2074 dig = radeon_test_encoder->enc_priv;
2075
2076 if (dig->dig_encoder >= 0)
2077 dig_enc_in_use |= (1 << dig->dig_encoder);
2078 }
2079
2080 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA) {
2081 if (dig_enc_in_use & 0x2)
2082 DRM_ERROR("LVDS required digital encoder 2 but it was in use - stealing\n");
2083 return 1;
2084 }
2085 if (!(dig_enc_in_use & 1))
2086 return 0;
2087 return 1;
2088}
2089
2090/* This only needs to be called once at startup */
2091void
2092radeon_atom_encoder_init(struct radeon_device *rdev)
2093{
2094 struct drm_device *dev = rdev->ddev;
2095 struct drm_encoder *encoder;
2096
2097 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2098 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2099 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
2100
2101 switch (radeon_encoder->encoder_id) {
2102 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2103 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2104 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
e68adef8 2105 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
3f03ced8
AD		 2106 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2107 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0);
2108 break;
2109 default:
2110 break;
2111 }
2112
1d3949c4 2113 if (ext_encoder && (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)))
3f03ced8
AD		 2114 atombios_external_encoder_setup(encoder, ext_encoder,
2115 EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT);
2116 }
2117}
2118
2119static void
2120radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
2121 struct drm_display_mode *mode,
2122 struct drm_display_mode *adjusted_mode)
2123{
2124 struct drm_device *dev = encoder->dev;
2125 struct radeon_device *rdev = dev->dev_private;
2126 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3f03ced8
AD		 2127
2128 radeon_encoder->pixel_clock = adjusted_mode->clock;
2129
8d1af57a
AD		 2130 /* need to call this here rather than in prepare() since we need some crtc info */
2131 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
2132
3f03ced8
AD		 2133 if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE4(rdev)) {
2134 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT))
2135 atombios_yuv_setup(encoder, true);
2136 else
2137 atombios_yuv_setup(encoder, false);
2138 }
2139
2140 switch (radeon_encoder->encoder_id) {
2141 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2142 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2143 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2144 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2145 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE);
2146 break;
2147 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2148 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2149 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
e68adef8 2150 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
3f03ced8 2151 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
8d1af57a 2152 /* handled in dpms */
3f03ced8
AD		 2153 break;
2154 case ENCODER_OBJECT_ID_INTERNAL_DDI:
2155 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2156 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2157 atombios_dvo_setup(encoder, ATOM_ENABLE);
2158 break;
2159 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2160 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2161 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2162 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2163 atombios_dac_setup(encoder, ATOM_ENABLE);
2164 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) {
2165 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
2166 atombios_tv_setup(encoder, ATOM_ENABLE);
2167 else
2168 atombios_tv_setup(encoder, ATOM_DISABLE);
2169 }
2170 break;
2171 }
2172
3f03ced8
AD		 2173 atombios_apply_encoder_quirks(encoder, adjusted_mode);
2174
2175 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
a973bea1
AD		 2176 if (rdev->asic->display.hdmi_enable)
2177 radeon_hdmi_enable(rdev, encoder, true);
6e72376d 2178 radeon_audio_mode_set(encoder, adjusted_mode);
3f03ced8
AD		 2179 }
2180}
2181
2182static bool
2183atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2184{
2185 struct drm_device *dev = encoder->dev;
2186 struct radeon_device *rdev = dev->dev_private;
2187 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2188 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2189
2190 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT |
2191 ATOM_DEVICE_CV_SUPPORT |
2192 ATOM_DEVICE_CRT_SUPPORT)) {
2193 DAC_LOAD_DETECTION_PS_ALLOCATION args;
2194 int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection);
2195 uint8_t frev, crev;
2196
2197 memset(&args, 0, sizeof(args));
2198
2199 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2200 return false;
2201
2202 args.sDacload.ucMisc = 0;
2203
2204 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) ||
2205 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1))
2206 args.sDacload.ucDacType = ATOM_DAC_A;
2207 else
2208 args.sDacload.ucDacType = ATOM_DAC_B;
2209
2210 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)
2211 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT);
2212 else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)
2213 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT);
2214 else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2215 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT);
2216 if (crev >= 3)
2217 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
2218 } else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2219 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT);
2220 if (crev >= 3)
2221 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
2222 }
2223
2224 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2225
2226 return true;
2227 } else
2228 return false;
2229}
2230
2231static enum drm_connector_status
2232radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2233{
2234 struct drm_device *dev = encoder->dev;
2235 struct radeon_device *rdev = dev->dev_private;
2236 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2237 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2238 uint32_t bios_0_scratch;
2239
2240 if (!atombios_dac_load_detect(encoder, connector)) {
2241 DRM_DEBUG_KMS("detect returned false \n");
2242 return connector_status_unknown;
2243 }
2244
2245 if (rdev->family >= CHIP_R600)
2246 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2247 else
2248 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
2249
2250 DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
2251 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2252 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
2253 return connector_status_connected;
2254 }
2255 if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2256 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
2257 return connector_status_connected;
2258 }
2259 if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2260 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
2261 return connector_status_connected;
2262 }
2263 if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2264 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
2265 return connector_status_connected; /* CTV */
2266 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
2267 return connector_status_connected; /* STV */
2268 }
2269 return connector_status_disconnected;
2270}
2271
2272static enum drm_connector_status
2273radeon_atom_dig_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2274{
2275 struct drm_device *dev = encoder->dev;
2276 struct radeon_device *rdev = dev->dev_private;
2277 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2278 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2279 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
2280 u32 bios_0_scratch;
2281
2282 if (!ASIC_IS_DCE4(rdev))
2283 return connector_status_unknown;
2284
2285 if (!ext_encoder)
2286 return connector_status_unknown;
2287
2288 if ((radeon_connector->devices & ATOM_DEVICE_CRT_SUPPORT) == 0)
2289 return connector_status_unknown;
2290
2291 /* load detect on the dp bridge */
2292 atombios_external_encoder_setup(encoder, ext_encoder,
2293 EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION);
2294
2295 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2296
2297 DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
2298 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2299 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
2300 return connector_status_connected;
2301 }
2302 if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2303 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
2304 return connector_status_connected;
2305 }
2306 if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2307 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
2308 return connector_status_connected;
2309 }
2310 if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2311 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
2312 return connector_status_connected; /* CTV */
2313 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
2314 return connector_status_connected; /* STV */
2315 }
2316 return connector_status_disconnected;
2317}
2318
2319void
2320radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder)
2321{
2322 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
2323
2324 if (ext_encoder)
2325 /* ddc_setup on the dp bridge */
2326 atombios_external_encoder_setup(encoder, ext_encoder,
2327 EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP);
2328
2329}
2330
2331static void radeon_atom_encoder_prepare(struct drm_encoder *encoder)
2332{
cfcbd6d3 2333 struct radeon_device *rdev = encoder->dev->dev_private;
3f03ced8
AD		 2334 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2335 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
2336
2337 if ((radeon_encoder->active_device &
2338 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
2339 (radeon_encoder_get_dp_bridge_encoder_id(encoder) !=
2340 ENCODER_OBJECT_ID_NONE)) {
2341 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
cfcbd6d3 2342 if (dig) {
3f03ced8 2343 dig->dig_encoder = radeon_atom_pick_dig_encoder(encoder);
cfcbd6d3
RM		 2344 if (radeon_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT) {
2345 if (rdev->family >= CHIP_R600)
2346 dig->afmt = rdev->mode_info.afmt[dig->dig_encoder];
2347 else
2348 /* RS600/690/740 have only 1 afmt block */
2349 dig->afmt = rdev->mode_info.afmt[0];
2350 }
2351 }
3f03ced8
AD		 2352 }
2353
2354 radeon_atom_output_lock(encoder, true);
3f03ced8
AD		 2355
2356 if (connector) {
2357 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2358
2359 /* select the clock/data port if it uses a router */
2360 if (radeon_connector->router.cd_valid)
2361 radeon_router_select_cd_port(radeon_connector);
2362
2363 /* turn eDP panel on for mode set */
2364 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
2365 atombios_set_edp_panel_power(connector,
2366 ATOM_TRANSMITTER_ACTION_POWER_ON);
2367 }
2368
2369 /* this is needed for the pll/ss setup to work correctly in some cases */
2370 atombios_set_encoder_crtc_source(encoder);
134b480f
AD		 2371 /* set up the FMT blocks */
2372 if (ASIC_IS_DCE8(rdev))
2373 dce8_program_fmt(encoder);
2374 else if (ASIC_IS_DCE4(rdev))
2375 dce4_program_fmt(encoder);
2376 else if (ASIC_IS_DCE3(rdev))
2377 dce3_program_fmt(encoder);
2378 else if (ASIC_IS_AVIVO(rdev))
2379 avivo_program_fmt(encoder);
3f03ced8
AD		 2380}
2381
2382static void radeon_atom_encoder_commit(struct drm_encoder *encoder)
2383{
8d1af57a 2384 /* need to call this here as we need the crtc set up */
3f03ced8
AD		 2385 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
2386 radeon_atom_output_lock(encoder, false);
2387}
2388
2389static void radeon_atom_encoder_disable(struct drm_encoder *encoder)
2390{
2391 struct drm_device *dev = encoder->dev;
2392 struct radeon_device *rdev = dev->dev_private;
2393 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2394 struct radeon_encoder_atom_dig *dig;
2395
2396 /* check for pre-DCE3 cards with shared encoders;
2397 * can't really use the links individually, so don't disable
2398 * the encoder if it's in use by another connector
2399 */
2400 if (!ASIC_IS_DCE3(rdev)) {
2401 struct drm_encoder *other_encoder;
2402 struct radeon_encoder *other_radeon_encoder;
2403
2404 list_for_each_entry(other_encoder, &dev->mode_config.encoder_list, head) {
2405 other_radeon_encoder = to_radeon_encoder(other_encoder);
2406 if ((radeon_encoder->encoder_id == other_radeon_encoder->encoder_id) &&
2407 drm_helper_encoder_in_use(other_encoder))
2408 goto disable_done;
2409 }
2410 }
2411
2412 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
2413
2414 switch (radeon_encoder->encoder_id) {
2415 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2416 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2417 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2418 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2419 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_DISABLE);
2420 break;
2421 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2422 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2423 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
e68adef8 2424 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
3f03ced8 2425 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
8d1af57a 2426 /* handled in dpms */
3f03ced8
AD		 2427 break;
2428 case ENCODER_OBJECT_ID_INTERNAL_DDI:
2429 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2430 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2431 atombios_dvo_setup(encoder, ATOM_DISABLE);
2432 break;
2433 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2434 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2435 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2436 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2437 atombios_dac_setup(encoder, ATOM_DISABLE);
2438 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
2439 atombios_tv_setup(encoder, ATOM_DISABLE);
2440 break;
2441 }
2442
2443disable_done:
2444 if (radeon_encoder_is_digital(encoder)) {
a973bea1
AD		 2445 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
2446 if (rdev->asic->display.hdmi_enable)
2447 radeon_hdmi_enable(rdev, encoder, false);
2448 }
3f03ced8
AD		 2449 dig = radeon_encoder->enc_priv;
2450 dig->dig_encoder = -1;
2451 }
2452 radeon_encoder->active_device = 0;
2453}
2454
2455/* these are handled by the primary encoders */
2456static void radeon_atom_ext_prepare(struct drm_encoder *encoder)
2457{
2458
2459}
2460
2461static void radeon_atom_ext_commit(struct drm_encoder *encoder)
2462{
2463
2464}
2465
2466static void
2467radeon_atom_ext_mode_set(struct drm_encoder *encoder,
2468 struct drm_display_mode *mode,
2469 struct drm_display_mode *adjusted_mode)
2470{
2471
2472}
2473
2474static void radeon_atom_ext_disable(struct drm_encoder *encoder)
2475{
2476
2477}
2478
2479static void
2480radeon_atom_ext_dpms(struct drm_encoder *encoder, int mode)
2481{
2482
2483}
2484
2485static bool radeon_atom_ext_mode_fixup(struct drm_encoder *encoder,
e811f5ae 2486 const struct drm_display_mode *mode,
3f03ced8
AD		 2487 struct drm_display_mode *adjusted_mode)
2488{
2489 return true;
2490}
2491
2492static const struct drm_encoder_helper_funcs radeon_atom_ext_helper_funcs = {
2493 .dpms = radeon_atom_ext_dpms,
2494 .mode_fixup = radeon_atom_ext_mode_fixup,
2495 .prepare = radeon_atom_ext_prepare,
2496 .mode_set = radeon_atom_ext_mode_set,
2497 .commit = radeon_atom_ext_commit,
2498 .disable = radeon_atom_ext_disable,
2499 /* no detect for TMDS/LVDS yet */
2500};
2501
2502static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = {
2503 .dpms = radeon_atom_encoder_dpms,
2504 .mode_fixup = radeon_atom_mode_fixup,
2505 .prepare = radeon_atom_encoder_prepare,
2506 .mode_set = radeon_atom_encoder_mode_set,
2507 .commit = radeon_atom_encoder_commit,
2508 .disable = radeon_atom_encoder_disable,
2509 .detect = radeon_atom_dig_detect,
2510};
2511
2512static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = {
2513 .dpms = radeon_atom_encoder_dpms,
2514 .mode_fixup = radeon_atom_mode_fixup,
2515 .prepare = radeon_atom_encoder_prepare,
2516 .mode_set = radeon_atom_encoder_mode_set,
2517 .commit = radeon_atom_encoder_commit,
2518 .detect = radeon_atom_dac_detect,
2519};
2520
2521void radeon_enc_destroy(struct drm_encoder *encoder)
2522{
2523 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
f3728734
AD		 2524 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
2525 radeon_atom_backlight_exit(radeon_encoder);
3f03ced8
AD		 2526 kfree(radeon_encoder->enc_priv);
2527 drm_encoder_cleanup(encoder);
2528 kfree(radeon_encoder);
2529}
2530
2531static const struct drm_encoder_funcs radeon_atom_enc_funcs = {
2532 .destroy = radeon_enc_destroy,
2533};
2534
1109ca09 2535static struct radeon_encoder_atom_dac *
3f03ced8
AD		 2536radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder)
2537{
2538 struct drm_device *dev = radeon_encoder->base.dev;
2539 struct radeon_device *rdev = dev->dev_private;
2540 struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL);
2541
2542 if (!dac)
2543 return NULL;
2544
2545 dac->tv_std = radeon_atombios_get_tv_info(rdev);
2546 return dac;
2547}
2548
1109ca09 2549static struct radeon_encoder_atom_dig *
3f03ced8
AD		 2550radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder)
2551{
2552 int encoder_enum = (radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
2553 struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
2554
2555 if (!dig)
2556 return NULL;
2557
2558 /* coherent mode by default */
2559 dig->coherent_mode = true;
2560 dig->dig_encoder = -1;
2561
2562 if (encoder_enum == 2)
2563 dig->linkb = true;
2564 else
2565 dig->linkb = false;
2566
2567 return dig;
2568}
2569
2570void
2571radeon_add_atom_encoder(struct drm_device *dev,
2572 uint32_t encoder_enum,
2573 uint32_t supported_device,
2574 u16 caps)
2575{
2576 struct radeon_device *rdev = dev->dev_private;
2577 struct drm_encoder *encoder;
2578 struct radeon_encoder *radeon_encoder;
2579
2580 /* see if we already added it */
2581 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2582 radeon_encoder = to_radeon_encoder(encoder);
2583 if (radeon_encoder->encoder_enum == encoder_enum) {
2584 radeon_encoder->devices |= supported_device;
2585 return;
2586 }
2587
2588 }
2589
2590 /* add a new one */
2591 radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
2592 if (!radeon_encoder)
2593 return;
2594
2595 encoder = &radeon_encoder->base;
2596 switch (rdev->num_crtc) {
2597 case 1:
2598 encoder->possible_crtcs = 0x1;
2599 break;
2600 case 2:
2601 default:
2602 encoder->possible_crtcs = 0x3;
2603 break;
2604 case 4:
2605 encoder->possible_crtcs = 0xf;
2606 break;
2607 case 6:
2608 encoder->possible_crtcs = 0x3f;
2609 break;
2610 }
2611
2612 radeon_encoder->enc_priv = NULL;
2613
2614 radeon_encoder->encoder_enum = encoder_enum;
2615 radeon_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
2616 radeon_encoder->devices = supported_device;
2617 radeon_encoder->rmx_type = RMX_OFF;
2618 radeon_encoder->underscan_type = UNDERSCAN_OFF;
2619 radeon_encoder->is_ext_encoder = false;
2620 radeon_encoder->caps = caps;
2621
2622 switch (radeon_encoder->encoder_id) {
2623 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2624 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2625 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2626 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2627 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2628 radeon_encoder->rmx_type = RMX_FULL;
2629 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2630 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
2631 } else {
2632 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2633 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2634 }
2635 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
2636 break;
2637 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2638 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2639 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
2640 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
2641 break;
2642 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2643 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2644 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2645 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TVDAC);
2646 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
2647 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
2648 break;
2649 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2650 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2651 case ENCODER_OBJECT_ID_INTERNAL_DDI:
2652 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2653 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2654 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2655 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
e68adef8 2656 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
3f03ced8
AD		 2657 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2658 radeon_encoder->rmx_type = RMX_FULL;
2659 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2660 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
2661 } else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
2662 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2663 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2664 } else {
2665 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2666 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2667 }
2668 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
2669 break;
2670 case ENCODER_OBJECT_ID_SI170B:
2671 case ENCODER_OBJECT_ID_CH7303:
2672 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
2673 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
2674 case ENCODER_OBJECT_ID_TITFP513:
2675 case ENCODER_OBJECT_ID_VT1623:
2676 case ENCODER_OBJECT_ID_HDMI_SI1930:
2677 case ENCODER_OBJECT_ID_TRAVIS:
2678 case ENCODER_OBJECT_ID_NUTMEG:
2679 /* these are handled by the primary encoders */
2680 radeon_encoder->is_ext_encoder = true;
2681 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
2682 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2683 else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
2684 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2685 else
2686 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2687 drm_encoder_helper_add(encoder, &radeon_atom_ext_helper_funcs);
2688 break;
2689 }
2690}
Linux kernel - Deliverables
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