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staging: crystalhd: remove use of __devexit_p
[deliverable/linux.git] / drivers / staging / imx-drm / ipu-v3 / ipu-common.c
CommitLineData
aecfbdb1
SH		 1/*
2 * Copyright (c) 2010 Sascha Hauer <s.hauer@pengutronix.de>
3 * Copyright (C) 2005-2009 Freescale Semiconductor, Inc.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
12 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * for more details.
14 */
15#include <linux/module.h>
16#include <linux/export.h>
17#include <linux/types.h>
18#include <linux/init.h>
19#include <linux/platform_device.h>
20#include <linux/err.h>
21#include <linux/spinlock.h>
22#include <linux/delay.h>
23#include <linux/interrupt.h>
24#include <linux/io.h>
25#include <linux/clk.h>
26#include <linux/list.h>
27#include <linux/irq.h>
28#include <linux/of_device.h>
29#include <asm/mach/irq.h>
30
31#include "imx-ipu-v3.h"
32#include "ipu-prv.h"
33
34static inline u32 ipu_cm_read(struct ipu_soc *ipu, unsigned offset)
35{
36 return readl(ipu->cm_reg + offset);
37}
38
39static inline void ipu_cm_write(struct ipu_soc *ipu, u32 value, unsigned offset)
40{
41 writel(value, ipu->cm_reg + offset);
42}
43
44static inline u32 ipu_idmac_read(struct ipu_soc *ipu, unsigned offset)
45{
46 return readl(ipu->idmac_reg + offset);
47}
48
49static inline void ipu_idmac_write(struct ipu_soc *ipu, u32 value,
50 unsigned offset)
51{
52 writel(value, ipu->idmac_reg + offset);
53}
54
55void ipu_srm_dp_sync_update(struct ipu_soc *ipu)
56{
57 u32 val;
58
59 val = ipu_cm_read(ipu, IPU_SRM_PRI2);
60 val |= 0x8;
61 ipu_cm_write(ipu, val, IPU_SRM_PRI2);
62}
63EXPORT_SYMBOL_GPL(ipu_srm_dp_sync_update);
64
65struct ipu_ch_param __iomem *ipu_get_cpmem(struct ipuv3_channel *channel)
66{
67 struct ipu_soc *ipu = channel->ipu;
68
69 return ipu->cpmem_base + channel->num;
70}
71EXPORT_SYMBOL_GPL(ipu_get_cpmem);
72
73void ipu_cpmem_set_high_priority(struct ipuv3_channel *channel)
74{
75 struct ipu_soc *ipu = channel->ipu;
76 struct ipu_ch_param __iomem *p = ipu_get_cpmem(channel);
77 u32 val;
78
79 if (ipu->ipu_type == IPUV3EX)
80 ipu_ch_param_write_field(p, IPU_FIELD_ID, 1);
81
82 val = ipu_idmac_read(ipu, IDMAC_CHA_PRI(channel->num));
83 val |= 1 << (channel->num % 32);
84 ipu_idmac_write(ipu, val, IDMAC_CHA_PRI(channel->num));
85};
86EXPORT_SYMBOL_GPL(ipu_cpmem_set_high_priority);
87
88void ipu_ch_param_write_field(struct ipu_ch_param __iomem *base, u32 wbs, u32 v)
89{
90 u32 bit = (wbs >> 8) % 160;
91 u32 size = wbs & 0xff;
92 u32 word = (wbs >> 8) / 160;
93 u32 i = bit / 32;
94 u32 ofs = bit % 32;
95 u32 mask = (1 << size) - 1;
96 u32 val;
97
98 pr_debug("%s %d %d %d\n", __func__, word, bit , size);
99
100 val = readl(&base->word[word].data[i]);
101 val &= ~(mask << ofs);
102 val |= v << ofs;
103 writel(val, &base->word[word].data[i]);
104
105 if ((bit + size - 1) / 32 > i) {
106 val = readl(&base->word[word].data[i + 1]);
107 val &= ~(mask >> (ofs ? (32 - ofs) : 0));
108 val |= v >> (ofs ? (32 - ofs) : 0);
109 writel(val, &base->word[word].data[i + 1]);
110 }
111}
112EXPORT_SYMBOL_GPL(ipu_ch_param_write_field);
113
114u32 ipu_ch_param_read_field(struct ipu_ch_param __iomem *base, u32 wbs)
115{
116 u32 bit = (wbs >> 8) % 160;
117 u32 size = wbs & 0xff;
118 u32 word = (wbs >> 8) / 160;
119 u32 i = bit / 32;
120 u32 ofs = bit % 32;
121 u32 mask = (1 << size) - 1;
122 u32 val = 0;
123
124 pr_debug("%s %d %d %d\n", __func__, word, bit , size);
125
126 val = (readl(&base->word[word].data[i]) >> ofs) & mask;
127
128 if ((bit + size - 1) / 32 > i) {
129 u32 tmp;
130 tmp = readl(&base->word[word].data[i + 1]);
131 tmp &= mask >> (ofs ? (32 - ofs) : 0);
132 val |= tmp << (ofs ? (32 - ofs) : 0);
133 }
134
135 return val;
136}
137EXPORT_SYMBOL_GPL(ipu_ch_param_read_field);
138
139int ipu_cpmem_set_format_rgb(struct ipu_ch_param __iomem *p,
140 struct ipu_rgb *rgb)
141{
142 int bpp = 0, npb = 0, ro, go, bo, to;
143
144 ro = rgb->bits_per_pixel - rgb->red.length - rgb->red.offset;
145 go = rgb->bits_per_pixel - rgb->green.length - rgb->green.offset;
146 bo = rgb->bits_per_pixel - rgb->blue.length - rgb->blue.offset;
147 to = rgb->bits_per_pixel - rgb->transp.length - rgb->transp.offset;
148
149 ipu_ch_param_write_field(p, IPU_FIELD_WID0, rgb->red.length - 1);
150 ipu_ch_param_write_field(p, IPU_FIELD_OFS0, ro);
151 ipu_ch_param_write_field(p, IPU_FIELD_WID1, rgb->green.length - 1);
152 ipu_ch_param_write_field(p, IPU_FIELD_OFS1, go);
153 ipu_ch_param_write_field(p, IPU_FIELD_WID2, rgb->blue.length - 1);
154 ipu_ch_param_write_field(p, IPU_FIELD_OFS2, bo);
155
156 if (rgb->transp.length) {
157 ipu_ch_param_write_field(p, IPU_FIELD_WID3,
158 rgb->transp.length - 1);
159 ipu_ch_param_write_field(p, IPU_FIELD_OFS3, to);
160 } else {
161 ipu_ch_param_write_field(p, IPU_FIELD_WID3, 7);
162 ipu_ch_param_write_field(p, IPU_FIELD_OFS3,
163 rgb->bits_per_pixel);
164 }
165
166 switch (rgb->bits_per_pixel) {
167 case 32:
168 bpp = 0;
169 npb = 15;
170 break;
171 case 24:
172 bpp = 1;
173 npb = 19;
174 break;
175 case 16:
176 bpp = 3;
177 npb = 31;
178 break;
179 case 8:
180 bpp = 5;
181 npb = 63;
182 break;
183 default:
184 return -EINVAL;
185 }
186 ipu_ch_param_write_field(p, IPU_FIELD_BPP, bpp);
187 ipu_ch_param_write_field(p, IPU_FIELD_NPB, npb);
188 ipu_ch_param_write_field(p, IPU_FIELD_PFS, 7); /* rgb mode */
189
190 return 0;
191}
192EXPORT_SYMBOL_GPL(ipu_cpmem_set_format_rgb);
193
194int ipu_cpmem_set_format_passthrough(struct ipu_ch_param __iomem *p,
195 int width)
196{
197 int bpp = 0, npb = 0;
198
199 switch (width) {
200 case 32:
201 bpp = 0;
202 npb = 15;
203 break;
204 case 24:
205 bpp = 1;
206 npb = 19;
207 break;
208 case 16:
209 bpp = 3;
210 npb = 31;
211 break;
212 case 8:
213 bpp = 5;
214 npb = 63;
215 break;
216 default:
217 return -EINVAL;
218 }
219
220 ipu_ch_param_write_field(p, IPU_FIELD_BPP, bpp);
221 ipu_ch_param_write_field(p, IPU_FIELD_NPB, npb);
222 ipu_ch_param_write_field(p, IPU_FIELD_PFS, 6); /* raw mode */
223
224 return 0;
225}
226EXPORT_SYMBOL_GPL(ipu_cpmem_set_format_passthrough);
227
0125f21b
PZ		 228void ipu_cpmem_set_yuv_interleaved(struct ipu_ch_param *p, u32 pixel_format)
229{
230 switch (pixel_format) {
231 case V4L2_PIX_FMT_UYVY:
232 ipu_ch_param_write_field(p, IPU_FIELD_BPP, 3); /* bits/pixel */
233 ipu_ch_param_write_field(p, IPU_FIELD_PFS, 0xA); /* pix format */
234 ipu_ch_param_write_field(p, IPU_FIELD_NPB, 31); /* burst size */
235 break;
236 case V4L2_PIX_FMT_YUYV:
237 ipu_ch_param_write_field(p, IPU_FIELD_BPP, 3); /* bits/pixel */
238 ipu_ch_param_write_field(p, IPU_FIELD_PFS, 0x8); /* pix format */
239 ipu_ch_param_write_field(p, IPU_FIELD_NPB, 31); /* burst size */
240 break;
241 }
242}
243EXPORT_SYMBOL_GPL(ipu_cpmem_set_yuv_interleaved);
244
aecfbdb1
SH		 245void ipu_cpmem_set_yuv_planar_full(struct ipu_ch_param __iomem *p,
246 u32 pixel_format, int stride, int u_offset, int v_offset)
247{
248 switch (pixel_format) {
249 case V4L2_PIX_FMT_YUV420:
250 ipu_ch_param_write_field(p, IPU_FIELD_SLUV, (stride / 2) - 1);
251 ipu_ch_param_write_field(p, IPU_FIELD_UBO, u_offset / 8);
252 ipu_ch_param_write_field(p, IPU_FIELD_VBO, v_offset / 8);
253 break;
d3e4e610
PZ		 254 case V4L2_PIX_FMT_YVU420:
255 ipu_ch_param_write_field(p, IPU_FIELD_SLUV, (stride / 2) - 1);
256 ipu_ch_param_write_field(p, IPU_FIELD_UBO, v_offset / 8);
257 ipu_ch_param_write_field(p, IPU_FIELD_VBO, u_offset / 8);
258 break;
aecfbdb1
SH		 259 }
260}
261EXPORT_SYMBOL_GPL(ipu_cpmem_set_yuv_planar_full);
262
263void ipu_cpmem_set_yuv_planar(struct ipu_ch_param __iomem *p, u32 pixel_format,
264 int stride, int height)
265{
266 int u_offset, v_offset;
267 int uv_stride = 0;
268
269 switch (pixel_format) {
270 case V4L2_PIX_FMT_YUV420:
d3e4e610 271 case V4L2_PIX_FMT_YVU420:
aecfbdb1
SH		 272 uv_stride = stride / 2;
273 u_offset = stride * height;
274 v_offset = u_offset + (uv_stride * height / 2);
d3e4e610 275 ipu_cpmem_set_yuv_planar_full(p, pixel_format, stride,
aecfbdb1
SH		 276 u_offset, v_offset);
277 break;
278 }
279}
280EXPORT_SYMBOL_GPL(ipu_cpmem_set_yuv_planar);
281
282static struct ipu_rgb def_rgb_32 = {
283 .red = { .offset = 16, .length = 8, },
284 .green = { .offset = 8, .length = 8, },
285 .blue = { .offset = 0, .length = 8, },
286 .transp = { .offset = 24, .length = 8, },
287 .bits_per_pixel = 32,
288};
289
290static struct ipu_rgb def_bgr_32 = {
291 .red = { .offset = 16, .length = 8, },
292 .green = { .offset = 8, .length = 8, },
293 .blue = { .offset = 0, .length = 8, },
294 .transp = { .offset = 24, .length = 8, },
295 .bits_per_pixel = 32,
296};
297
298static struct ipu_rgb def_rgb_24 = {
299 .red = { .offset = 0, .length = 8, },
300 .green = { .offset = 8, .length = 8, },
301 .blue = { .offset = 16, .length = 8, },
302 .transp = { .offset = 0, .length = 0, },
303 .bits_per_pixel = 24,
304};
305
306static struct ipu_rgb def_bgr_24 = {
307 .red = { .offset = 16, .length = 8, },
308 .green = { .offset = 8, .length = 8, },
309 .blue = { .offset = 0, .length = 8, },
310 .transp = { .offset = 0, .length = 0, },
311 .bits_per_pixel = 24,
312};
313
314static struct ipu_rgb def_rgb_16 = {
315 .red = { .offset = 11, .length = 5, },
316 .green = { .offset = 5, .length = 6, },
317 .blue = { .offset = 0, .length = 5, },
318 .transp = { .offset = 0, .length = 0, },
319 .bits_per_pixel = 16,
320};
321
322#define Y_OFFSET(pix, x, y) ((x) + pix->width * (y))
323#define U_OFFSET(pix, x, y) ((pix->width * pix->height) + \
324 (pix->width * (y) / 4) + (x) / 2)
325#define V_OFFSET(pix, x, y) ((pix->width * pix->height) + \
326 (pix->width * pix->height / 4) + \
327 (pix->width * (y) / 4) + (x) / 2)
328
329int ipu_cpmem_set_fmt(struct ipu_ch_param __iomem *cpmem, u32 pixelformat)
330{
331 switch (pixelformat) {
332 case V4L2_PIX_FMT_YUV420:
d3e4e610 333 case V4L2_PIX_FMT_YVU420:
aecfbdb1
SH		 334 /* pix format */
335 ipu_ch_param_write_field(cpmem, IPU_FIELD_PFS, 2);
336 /* burst size */
337 ipu_ch_param_write_field(cpmem, IPU_FIELD_NPB, 63);
338 break;
339 case V4L2_PIX_FMT_UYVY:
340 /* bits/pixel */
341 ipu_ch_param_write_field(cpmem, IPU_FIELD_BPP, 3);
342 /* pix format */
343 ipu_ch_param_write_field(cpmem, IPU_FIELD_PFS, 0xA);
344 /* burst size */
345 ipu_ch_param_write_field(cpmem, IPU_FIELD_NPB, 31);
346 break;
347 case V4L2_PIX_FMT_YUYV:
348 /* bits/pixel */
349 ipu_ch_param_write_field(cpmem, IPU_FIELD_BPP, 3);
350 /* pix format */
351 ipu_ch_param_write_field(cpmem, IPU_FIELD_PFS, 0x8);
352 /* burst size */
353 ipu_ch_param_write_field(cpmem, IPU_FIELD_NPB, 31);
354 break;
355 case V4L2_PIX_FMT_RGB32:
356 ipu_cpmem_set_format_rgb(cpmem, &def_rgb_32);
357 break;
358 case V4L2_PIX_FMT_RGB565:
359 ipu_cpmem_set_format_rgb(cpmem, &def_rgb_16);
360 break;
361 case V4L2_PIX_FMT_BGR32:
362 ipu_cpmem_set_format_rgb(cpmem, &def_bgr_32);
363 break;
364 case V4L2_PIX_FMT_RGB24:
365 ipu_cpmem_set_format_rgb(cpmem, &def_rgb_24);
366 break;
367 case V4L2_PIX_FMT_BGR24:
368 ipu_cpmem_set_format_rgb(cpmem, &def_bgr_24);
369 break;
370 default:
371 return -EINVAL;
372 }
373
374 return 0;
375}
376EXPORT_SYMBOL_GPL(ipu_cpmem_set_fmt);
377
378int ipu_cpmem_set_image(struct ipu_ch_param __iomem *cpmem,
379 struct ipu_image *image)
380{
381 struct v4l2_pix_format *pix = &image->pix;
382 int y_offset, u_offset, v_offset;
383
384 pr_debug("%s: resolution: %dx%d stride: %d\n",
385 __func__, pix->width, pix->height,
386 pix->bytesperline);
387
388 ipu_cpmem_set_resolution(cpmem, image->rect.width,
389 image->rect.height);
390 ipu_cpmem_set_stride(cpmem, pix->bytesperline);
391
392 ipu_cpmem_set_fmt(cpmem, pix->pixelformat);
393
394 switch (pix->pixelformat) {
395 case V4L2_PIX_FMT_YUV420:
d3e4e610 396 case V4L2_PIX_FMT_YVU420:
aecfbdb1
SH		 397 y_offset = Y_OFFSET(pix, image->rect.left, image->rect.top);
398 u_offset = U_OFFSET(pix, image->rect.left,
399 image->rect.top) - y_offset;
400 v_offset = V_OFFSET(pix, image->rect.left,
401 image->rect.top) - y_offset;
402
403 ipu_cpmem_set_yuv_planar_full(cpmem, pix->pixelformat,
404 pix->bytesperline, u_offset, v_offset);
405 ipu_cpmem_set_buffer(cpmem, 0, image->phys + y_offset);
406 break;
407 case V4L2_PIX_FMT_UYVY:
c096ae13 408 case V4L2_PIX_FMT_YUYV:
aecfbdb1
SH		 409 ipu_cpmem_set_buffer(cpmem, 0, image->phys +
410 image->rect.left * 2 +
411 image->rect.top * image->pix.bytesperline);
412 break;
413 case V4L2_PIX_FMT_RGB32:
414 case V4L2_PIX_FMT_BGR32:
415 ipu_cpmem_set_buffer(cpmem, 0, image->phys +
416 image->rect.left * 4 +
417 image->rect.top * image->pix.bytesperline);
418 break;
419 case V4L2_PIX_FMT_RGB565:
420 ipu_cpmem_set_buffer(cpmem, 0, image->phys +
421 image->rect.left * 2 +
422 image->rect.top * image->pix.bytesperline);
423 break;
424 case V4L2_PIX_FMT_RGB24:
425 case V4L2_PIX_FMT_BGR24:
426 ipu_cpmem_set_buffer(cpmem, 0, image->phys +
427 image->rect.left * 3 +
428 image->rect.top * image->pix.bytesperline);
429 break;
430 default:
431 return -EINVAL;
432 }
433
434 return 0;
435}
436EXPORT_SYMBOL_GPL(ipu_cpmem_set_image);
437
438enum ipu_color_space ipu_pixelformat_to_colorspace(u32 pixelformat)
439{
440 switch (pixelformat) {
441 case V4L2_PIX_FMT_YUV420:
d3e4e610 442 case V4L2_PIX_FMT_YVU420:
aecfbdb1 443 case V4L2_PIX_FMT_UYVY:
c096ae13 444 case V4L2_PIX_FMT_YUYV:
aecfbdb1
SH		 445 return IPUV3_COLORSPACE_YUV;
446 case V4L2_PIX_FMT_RGB32:
447 case V4L2_PIX_FMT_BGR32:
448 case V4L2_PIX_FMT_RGB24:
449 case V4L2_PIX_FMT_BGR24:
450 case V4L2_PIX_FMT_RGB565:
451 return IPUV3_COLORSPACE_RGB;
452 default:
453 return IPUV3_COLORSPACE_UNKNOWN;
454 }
455}
456EXPORT_SYMBOL_GPL(ipu_pixelformat_to_colorspace);
457
458struct ipuv3_channel *ipu_idmac_get(struct ipu_soc *ipu, unsigned num)
459{
460 struct ipuv3_channel *channel;
461
462 dev_dbg(ipu->dev, "%s %d\n", __func__, num);
463
464 if (num > 63)
465 return ERR_PTR(-ENODEV);
466
467 mutex_lock(&ipu->channel_lock);
468
469 channel = &ipu->channel[num];
470
471 if (channel->busy) {
472 channel = ERR_PTR(-EBUSY);
473 goto out;
474 }
475
476 channel->busy = 1;
477 channel->num = num;
478
479out:
480 mutex_unlock(&ipu->channel_lock);
481
482 return channel;
483}
484EXPORT_SYMBOL_GPL(ipu_idmac_get);
485
486void ipu_idmac_put(struct ipuv3_channel *channel)
487{
488 struct ipu_soc *ipu = channel->ipu;
489
490 dev_dbg(ipu->dev, "%s %d\n", __func__, channel->num);
491
492 mutex_lock(&ipu->channel_lock);
493
494 channel->busy = 0;
495
496 mutex_unlock(&ipu->channel_lock);
497}
498EXPORT_SYMBOL_GPL(ipu_idmac_put);
499
500#define idma_mask(ch) (1 << (ch & 0x1f))
501
502void ipu_idmac_set_double_buffer(struct ipuv3_channel *channel,
503 bool doublebuffer)
504{
505 struct ipu_soc *ipu = channel->ipu;
506 unsigned long flags;
507 u32 reg;
508
509 spin_lock_irqsave(&ipu->lock, flags);
510
511 reg = ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(channel->num));
512 if (doublebuffer)
513 reg |= idma_mask(channel->num);
514 else
515 reg &= ~idma_mask(channel->num);
516 ipu_cm_write(ipu, reg, IPU_CHA_DB_MODE_SEL(channel->num));
517
518 spin_unlock_irqrestore(&ipu->lock, flags);
519}
520EXPORT_SYMBOL_GPL(ipu_idmac_set_double_buffer);
521
522int ipu_module_enable(struct ipu_soc *ipu, u32 mask)
523{
524 unsigned long lock_flags;
525 u32 val;
526
527 spin_lock_irqsave(&ipu->lock, lock_flags);
528
529 val = ipu_cm_read(ipu, IPU_DISP_GEN);
530
531 if (mask & IPU_CONF_DI0_EN)
532 val |= IPU_DI0_COUNTER_RELEASE;
533 if (mask & IPU_CONF_DI1_EN)
534 val |= IPU_DI1_COUNTER_RELEASE;
535
536 ipu_cm_write(ipu, val, IPU_DISP_GEN);
537
538 val = ipu_cm_read(ipu, IPU_CONF);
539 val |= mask;
540 ipu_cm_write(ipu, val, IPU_CONF);
541
542 spin_unlock_irqrestore(&ipu->lock, lock_flags);
543
544 return 0;
545}
546EXPORT_SYMBOL_GPL(ipu_module_enable);
547
548int ipu_module_disable(struct ipu_soc *ipu, u32 mask)
549{
550 unsigned long lock_flags;
551 u32 val;
552
553 spin_lock_irqsave(&ipu->lock, lock_flags);
554
555 val = ipu_cm_read(ipu, IPU_CONF);
556 val &= ~mask;
557 ipu_cm_write(ipu, val, IPU_CONF);
558
559 val = ipu_cm_read(ipu, IPU_DISP_GEN);
560
561 if (mask & IPU_CONF_DI0_EN)
562 val &= ~IPU_DI0_COUNTER_RELEASE;
563 if (mask & IPU_CONF_DI1_EN)
564 val &= ~IPU_DI1_COUNTER_RELEASE;
565
566 ipu_cm_write(ipu, val, IPU_DISP_GEN);
567
568 spin_unlock_irqrestore(&ipu->lock, lock_flags);
569
570 return 0;
571}
572EXPORT_SYMBOL_GPL(ipu_module_disable);
573
574void ipu_idmac_select_buffer(struct ipuv3_channel *channel, u32 buf_num)
575{
576 struct ipu_soc *ipu = channel->ipu;
577 unsigned int chno = channel->num;
578 unsigned long flags;
579
580 spin_lock_irqsave(&ipu->lock, flags);
581
582 /* Mark buffer as ready. */
583 if (buf_num == 0)
584 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF0_RDY(chno));
585 else
586 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF1_RDY(chno));
587
588 spin_unlock_irqrestore(&ipu->lock, flags);
589}
590EXPORT_SYMBOL_GPL(ipu_idmac_select_buffer);
591
592int ipu_idmac_enable_channel(struct ipuv3_channel *channel)
593{
594 struct ipu_soc *ipu = channel->ipu;
595 u32 val;
596 unsigned long flags;
597
598 spin_lock_irqsave(&ipu->lock, flags);
599
600 val = ipu_idmac_read(ipu, IDMAC_CHA_EN(channel->num));
601 val |= idma_mask(channel->num);
602 ipu_idmac_write(ipu, val, IDMAC_CHA_EN(channel->num));
603
604 spin_unlock_irqrestore(&ipu->lock, flags);
605
606 return 0;
607}
608EXPORT_SYMBOL_GPL(ipu_idmac_enable_channel);
609
610int ipu_idmac_disable_channel(struct ipuv3_channel *channel)
611{
612 struct ipu_soc *ipu = channel->ipu;
613 u32 val;
614 unsigned long flags;
615 unsigned long timeout;
616
617 timeout = jiffies + msecs_to_jiffies(50);
618 while (ipu_idmac_read(ipu, IDMAC_CHA_BUSY(channel->num)) &
619 idma_mask(channel->num)) {
620 if (time_after(jiffies, timeout)) {
621 dev_warn(ipu->dev, "disabling busy idmac channel %d\n",
622 channel->num);
623 break;
624 }
625 cpu_relax();
626 }
627
628 spin_lock_irqsave(&ipu->lock, flags);
629
630 /* Disable DMA channel(s) */
631 val = ipu_idmac_read(ipu, IDMAC_CHA_EN(channel->num));
632 val &= ~idma_mask(channel->num);
633 ipu_idmac_write(ipu, val, IDMAC_CHA_EN(channel->num));
634
635 /* Set channel buffers NOT to be ready */
636 ipu_cm_write(ipu, 0xf0000000, IPU_GPR); /* write one to clear */
637
638 if (ipu_cm_read(ipu, IPU_CHA_BUF0_RDY(channel->num)) &
639 idma_mask(channel->num)) {
640 ipu_cm_write(ipu, idma_mask(channel->num),
641 IPU_CHA_BUF0_RDY(channel->num));
642 }
643
644 if (ipu_cm_read(ipu, IPU_CHA_BUF1_RDY(channel->num)) &
645 idma_mask(channel->num)) {
646 ipu_cm_write(ipu, idma_mask(channel->num),
647 IPU_CHA_BUF1_RDY(channel->num));
648 }
649
650 ipu_cm_write(ipu, 0x0, IPU_GPR); /* write one to set */
651
652 /* Reset the double buffer */
653 val = ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(channel->num));
654 val &= ~idma_mask(channel->num);
655 ipu_cm_write(ipu, val, IPU_CHA_DB_MODE_SEL(channel->num));
656
657 spin_unlock_irqrestore(&ipu->lock, flags);
658
659 return 0;
660}
661EXPORT_SYMBOL_GPL(ipu_idmac_disable_channel);
662
663static int ipu_reset(struct ipu_soc *ipu)
664{
665 unsigned long timeout;
666
667 ipu_cm_write(ipu, 0x807FFFFF, IPU_MEM_RST);
668
669 timeout = jiffies + msecs_to_jiffies(1000);
670 while (ipu_cm_read(ipu, IPU_MEM_RST) & 0x80000000) {
671 if (time_after(jiffies, timeout))
672 return -ETIME;
673 cpu_relax();
674 }
675
aecfbdb1
SH		 676 return 0;
677}
678
679struct ipu_devtype {
680 const char *name;
681 unsigned long cm_ofs;
682 unsigned long cpmem_ofs;
683 unsigned long srm_ofs;
684 unsigned long tpm_ofs;
685 unsigned long disp0_ofs;
686 unsigned long disp1_ofs;
687 unsigned long dc_tmpl_ofs;
688 unsigned long vdi_ofs;
689 enum ipuv3_type type;
690};
691
692static struct ipu_devtype ipu_type_imx51 = {
693 .name = "IPUv3EX",
694 .cm_ofs = 0x1e000000,
695 .cpmem_ofs = 0x1f000000,
696 .srm_ofs = 0x1f040000,
697 .tpm_ofs = 0x1f060000,
698 .disp0_ofs = 0x1e040000,
699 .disp1_ofs = 0x1e048000,
700 .dc_tmpl_ofs = 0x1f080000,
701 .vdi_ofs = 0x1e068000,
702 .type = IPUV3EX,
703};
704
705static struct ipu_devtype ipu_type_imx53 = {
706 .name = "IPUv3M",
707 .cm_ofs = 0x06000000,
708 .cpmem_ofs = 0x07000000,
709 .srm_ofs = 0x07040000,
710 .tpm_ofs = 0x07060000,
711 .disp0_ofs = 0x06040000,
712 .disp1_ofs = 0x06048000,
713 .dc_tmpl_ofs = 0x07080000,
714 .vdi_ofs = 0x06068000,
715 .type = IPUV3M,
716};
717
718static struct ipu_devtype ipu_type_imx6q = {
719 .name = "IPUv3H",
720 .cm_ofs = 0x00200000,
721 .cpmem_ofs = 0x00300000,
722 .srm_ofs = 0x00340000,
723 .tpm_ofs = 0x00360000,
724 .disp0_ofs = 0x00240000,
725 .disp1_ofs = 0x00248000,
726 .dc_tmpl_ofs = 0x00380000,
727 .vdi_ofs = 0x00268000,
728 .type = IPUV3H,
729};
730
731static const struct of_device_id imx_ipu_dt_ids[] = {
732 { .compatible = "fsl,imx51-ipu", .data = &ipu_type_imx51, },
733 { .compatible = "fsl,imx53-ipu", .data = &ipu_type_imx53, },
734 { .compatible = "fsl,imx6q-ipu", .data = &ipu_type_imx6q, },
735 { /* sentinel */ }
736};
737MODULE_DEVICE_TABLE(of, imx_ipu_dt_ids);
738
739static int ipu_submodules_init(struct ipu_soc *ipu,
740 struct platform_device *pdev, unsigned long ipu_base,
741 struct clk *ipu_clk)
742{
743 char *unit;
744 int ret;
745 struct device *dev = &pdev->dev;
746 const struct ipu_devtype *devtype = ipu->devtype;
747
748 ret = ipu_di_init(ipu, dev, 0, ipu_base + devtype->disp0_ofs,
749 IPU_CONF_DI0_EN, ipu_clk);
750 if (ret) {
751 unit = "di0";
752 goto err_di_0;
753 }
754
755 ret = ipu_di_init(ipu, dev, 1, ipu_base + devtype->disp1_ofs,
756 IPU_CONF_DI1_EN, ipu_clk);
757 if (ret) {
758 unit = "di1";
759 goto err_di_1;
760 }
761
762 ret = ipu_dc_init(ipu, dev, ipu_base + devtype->cm_ofs +
763 IPU_CM_DC_REG_OFS, ipu_base + devtype->dc_tmpl_ofs);
764 if (ret) {
765 unit = "dc_template";
766 goto err_dc;
767 }
768
769 ret = ipu_dmfc_init(ipu, dev, ipu_base +
770 devtype->cm_ofs + IPU_CM_DMFC_REG_OFS, ipu_clk);
771 if (ret) {
772 unit = "dmfc";
773 goto err_dmfc;
774 }
775
776 ret = ipu_dp_init(ipu, dev, ipu_base + devtype->srm_ofs);
777 if (ret) {
778 unit = "dp";
779 goto err_dp;
780 }
781
782 return 0;
783
784err_dp:
785 ipu_dmfc_exit(ipu);
786err_dmfc:
787 ipu_dc_exit(ipu);
788err_dc:
789 ipu_di_exit(ipu, 1);
790err_di_1:
791 ipu_di_exit(ipu, 0);
792err_di_0:
793 dev_err(&pdev->dev, "init %s failed with %d\n", unit, ret);
794 return ret;
795}
796
797static void ipu_irq_handle(struct ipu_soc *ipu, const int *regs, int num_regs)
798{
799 unsigned long status;
800 int i, bit, irq_base;
801
802 for (i = 0; i < num_regs; i++) {
803
804 status = ipu_cm_read(ipu, IPU_INT_STAT(regs[i]));
805 status &= ipu_cm_read(ipu, IPU_INT_CTRL(regs[i]));
806
807 irq_base = ipu->irq_start + regs[i] * 32;
808 for_each_set_bit(bit, &status, 32)
809 generic_handle_irq(irq_base + bit);
810 }
811}
812
813static void ipu_irq_handler(unsigned int irq, struct irq_desc *desc)
814{
815 struct ipu_soc *ipu = irq_desc_get_handler_data(desc);
816 const int int_reg[] = { 0, 1, 2, 3, 10, 11, 12, 13, 14};
817 struct irq_chip *chip = irq_get_chip(irq);
818
819 chained_irq_enter(chip, desc);
820
821 ipu_irq_handle(ipu, int_reg, ARRAY_SIZE(int_reg));
822
823 chained_irq_exit(chip, desc);
824}
825
826static void ipu_err_irq_handler(unsigned int irq, struct irq_desc *desc)
827{
828 struct ipu_soc *ipu = irq_desc_get_handler_data(desc);
829 const int int_reg[] = { 4, 5, 8, 9};
830 struct irq_chip *chip = irq_get_chip(irq);
831
832 chained_irq_enter(chip, desc);
833
834 ipu_irq_handle(ipu, int_reg, ARRAY_SIZE(int_reg));
835
836 chained_irq_exit(chip, desc);
837}
838
839static void ipu_ack_irq(struct irq_data *d)
840{
841 struct ipu_soc *ipu = irq_data_get_irq_chip_data(d);
842 unsigned int irq = d->irq - ipu->irq_start;
843
844 ipu_cm_write(ipu, 1 << (irq % 32), IPU_INT_STAT(irq / 32));
845}
846
847static void ipu_unmask_irq(struct irq_data *d)
848{
849 struct ipu_soc *ipu = irq_data_get_irq_chip_data(d);
850 unsigned int irq = d->irq - ipu->irq_start;
851 unsigned long flags;
852 u32 reg;
853
854 spin_lock_irqsave(&ipu->lock, flags);
855
856 reg = ipu_cm_read(ipu, IPU_INT_CTRL(irq / 32));
857 reg |= 1 << (irq % 32);
858 ipu_cm_write(ipu, reg, IPU_INT_CTRL(irq / 32));
859
860 spin_unlock_irqrestore(&ipu->lock, flags);
861}
862
863static void ipu_mask_irq(struct irq_data *d)
864{
865 struct ipu_soc *ipu = irq_data_get_irq_chip_data(d);
866 unsigned int irq = d->irq - ipu->irq_start;
867 unsigned long flags;
868 u32 reg;
869
870 spin_lock_irqsave(&ipu->lock, flags);
871
872 reg = ipu_cm_read(ipu, IPU_INT_CTRL(irq / 32));
873 reg &= ~(1 << (irq % 32));
874 ipu_cm_write(ipu, reg, IPU_INT_CTRL(irq / 32));
875
876 spin_unlock_irqrestore(&ipu->lock, flags);
877}
878
879static struct irq_chip ipu_irq_chip = {
880 .name = "IPU",
881 .irq_ack = ipu_ack_irq,
882 .irq_mask = ipu_mask_irq,
883 .irq_unmask = ipu_unmask_irq,
884};
885
886int ipu_idmac_channel_irq(struct ipu_soc *ipu, struct ipuv3_channel *channel,
887 enum ipu_channel_irq irq_type)
888{
889 return ipu->irq_start + irq_type + channel->num;
890}
891EXPORT_SYMBOL_GPL(ipu_idmac_channel_irq);
892
893static void ipu_submodules_exit(struct ipu_soc *ipu)
894{
895 ipu_dp_exit(ipu);
896 ipu_dmfc_exit(ipu);
897 ipu_dc_exit(ipu);
898 ipu_di_exit(ipu, 1);
899 ipu_di_exit(ipu, 0);
900}
901
902static int platform_remove_devices_fn(struct device *dev, void *unused)
903{
904 struct platform_device *pdev = to_platform_device(dev);
905
906 platform_device_unregister(pdev);
907
908 return 0;
909}
910
911static void platform_device_unregister_children(struct platform_device *pdev)
912{
913 device_for_each_child(&pdev->dev, NULL, platform_remove_devices_fn);
914}
915
916struct ipu_platform_reg {
917 struct ipu_client_platformdata pdata;
918 const char *name;
919};
920
921static const struct ipu_platform_reg client_reg[] = {
922 {
923 .pdata = {
924 .di = 0,
925 .dc = 5,
926 .dp = IPU_DP_FLOW_SYNC_BG,
927 .dma[0] = IPUV3_CHANNEL_MEM_BG_SYNC,
928 .dma[1] = -EINVAL,
929 },
930 .name = "imx-ipuv3-crtc",
931 }, {
932 .pdata = {
933 .di = 1,
934 .dc = 1,
935 .dp = -EINVAL,
936 .dma[0] = IPUV3_CHANNEL_MEM_DC_SYNC,
937 .dma[1] = -EINVAL,
938 },
939 .name = "imx-ipuv3-crtc",
940 },
941};
942
943static int ipu_client_id;
944
945static int ipu_add_subdevice_pdata(struct device *dev,
946 const struct ipu_platform_reg *reg)
947{
948 struct platform_device *pdev;
949
950 pdev = platform_device_register_data(dev, reg->name, ipu_client_id++,
951 &reg->pdata, sizeof(struct ipu_platform_reg));
952
953 return pdev ? 0 : -EINVAL;
954}
955
956static int ipu_add_client_devices(struct ipu_soc *ipu)
957{
958 int ret;
959 int i;
960
961 for (i = 0; i < ARRAY_SIZE(client_reg); i++) {
962 const struct ipu_platform_reg *reg = &client_reg[i];
963 ret = ipu_add_subdevice_pdata(ipu->dev, reg);
964 if (ret)
965 goto err_register;
966 }
967
968 return 0;
969
970err_register:
971 platform_device_unregister_children(to_platform_device(ipu->dev));
972
973 return ret;
974}
975
976static int ipu_irq_init(struct ipu_soc *ipu)
977{
978 int i;
979
980 ipu->irq_start = irq_alloc_descs(-1, 0, IPU_NUM_IRQS, 0);
981 if (ipu->irq_start < 0)
982 return ipu->irq_start;
983
984 for (i = ipu->irq_start; i < ipu->irq_start + IPU_NUM_IRQS; i++) {
985 irq_set_chip_and_handler(i, &ipu_irq_chip, handle_level_irq);
986 set_irq_flags(i, IRQF_VALID);
987 irq_set_chip_data(i, ipu);
988 }
989
990 irq_set_chained_handler(ipu->irq_sync, ipu_irq_handler);
991 irq_set_handler_data(ipu->irq_sync, ipu);
992 irq_set_chained_handler(ipu->irq_err, ipu_err_irq_handler);
993 irq_set_handler_data(ipu->irq_err, ipu);
994
995 return 0;
996}
997
998static void ipu_irq_exit(struct ipu_soc *ipu)
999{
1000 int i;
1001
1002 irq_set_chained_handler(ipu->irq_err, NULL);
1003 irq_set_handler_data(ipu->irq_err, NULL);
1004 irq_set_chained_handler(ipu->irq_sync, NULL);
1005 irq_set_handler_data(ipu->irq_sync, NULL);
1006
1007 for (i = ipu->irq_start; i < ipu->irq_start + IPU_NUM_IRQS; i++) {
1008 set_irq_flags(i, 0);
1009 irq_set_chip(i, NULL);
1010 irq_set_chip_data(i, NULL);
1011 }
1012
1013 irq_free_descs(ipu->irq_start, IPU_NUM_IRQS);
1014}
1015
1016static int __devinit ipu_probe(struct platform_device *pdev)
1017{
1018 const struct of_device_id *of_id =
1019 of_match_device(imx_ipu_dt_ids, &pdev->dev);
1020 struct ipu_soc *ipu;
1021 struct resource *res;
1022 unsigned long ipu_base;
1023 int i, ret, irq_sync, irq_err;
1024 const struct ipu_devtype *devtype;
1025
1026 devtype = of_id->data;
1027
aecfbdb1
SH		 1028 irq_sync = platform_get_irq(pdev, 0);
1029 irq_err = platform_get_irq(pdev, 1);
1030 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1031
fd563dbb 1032 dev_dbg(&pdev->dev, "irq_sync: %d irq_err: %d\n",
aecfbdb1
SH		 1033 irq_sync, irq_err);
1034
1035 if (!res || irq_sync < 0 || irq_err < 0)
1036 return -ENODEV;
1037
1038 ipu_base = res->start;
1039
1040 ipu = devm_kzalloc(&pdev->dev, sizeof(*ipu), GFP_KERNEL);
1041 if (!ipu)
1042 return -ENODEV;
1043
1044 for (i = 0; i < 64; i++)
1045 ipu->channel[i].ipu = ipu;
1046 ipu->devtype = devtype;
1047 ipu->ipu_type = devtype->type;
1048
1049 spin_lock_init(&ipu->lock);
1050 mutex_init(&ipu->channel_lock);
1051
fd563dbb 1052 dev_dbg(&pdev->dev, "cm_reg: 0x%08lx\n",
aecfbdb1 1053 ipu_base + devtype->cm_ofs);
fd563dbb 1054 dev_dbg(&pdev->dev, "idmac: 0x%08lx\n",
aecfbdb1 1055 ipu_base + devtype->cm_ofs + IPU_CM_IDMAC_REG_OFS);
fd563dbb 1056 dev_dbg(&pdev->dev, "cpmem: 0x%08lx\n",
aecfbdb1 1057 ipu_base + devtype->cpmem_ofs);
fd563dbb 1058 dev_dbg(&pdev->dev, "disp0: 0x%08lx\n",
aecfbdb1 1059 ipu_base + devtype->disp0_ofs);
fd563dbb 1060 dev_dbg(&pdev->dev, "disp1: 0x%08lx\n",
aecfbdb1 1061 ipu_base + devtype->disp1_ofs);
fd563dbb 1062 dev_dbg(&pdev->dev, "srm: 0x%08lx\n",
aecfbdb1 1063 ipu_base + devtype->srm_ofs);
fd563dbb 1064 dev_dbg(&pdev->dev, "tpm: 0x%08lx\n",
aecfbdb1 1065 ipu_base + devtype->tpm_ofs);
fd563dbb 1066 dev_dbg(&pdev->dev, "dc: 0x%08lx\n",
aecfbdb1 1067 ipu_base + devtype->cm_ofs + IPU_CM_DC_REG_OFS);
fd563dbb 1068 dev_dbg(&pdev->dev, "ic: 0x%08lx\n",
aecfbdb1 1069 ipu_base + devtype->cm_ofs + IPU_CM_IC_REG_OFS);
fd563dbb 1070 dev_dbg(&pdev->dev, "dmfc: 0x%08lx\n",
aecfbdb1 1071 ipu_base + devtype->cm_ofs + IPU_CM_DMFC_REG_OFS);
fd563dbb 1072 dev_dbg(&pdev->dev, "vdi: 0x%08lx\n",
aecfbdb1
SH		 1073 ipu_base + devtype->vdi_ofs);
1074
1075 ipu->cm_reg = devm_ioremap(&pdev->dev,
1076 ipu_base + devtype->cm_ofs, PAGE_SIZE);
1077 ipu->idmac_reg = devm_ioremap(&pdev->dev,
1078 ipu_base + devtype->cm_ofs + IPU_CM_IDMAC_REG_OFS,
1079 PAGE_SIZE);
1080 ipu->cpmem_base = devm_ioremap(&pdev->dev,
1081 ipu_base + devtype->cpmem_ofs, PAGE_SIZE);
1082
1083 if (!ipu->cm_reg || !ipu->idmac_reg || !ipu->cpmem_base) {
1084 ret = -ENOMEM;
1085 goto failed_ioremap;
1086 }
1087
1088 ipu->clk = devm_clk_get(&pdev->dev, "bus");
1089 if (IS_ERR(ipu->clk)) {
1090 ret = PTR_ERR(ipu->clk);
1091 dev_err(&pdev->dev, "clk_get failed with %d", ret);
1092 goto failed_clk_get;
1093 }
1094
1095 platform_set_drvdata(pdev, ipu);
1096
1097 clk_prepare_enable(ipu->clk);
1098
1099 ipu->dev = &pdev->dev;
1100 ipu->irq_sync = irq_sync;
1101 ipu->irq_err = irq_err;
1102
1103 ret = ipu_irq_init(ipu);
1104 if (ret)
1105 goto out_failed_irq;
1106
1107 ipu_reset(ipu);
1108
1109 /* Set MCU_T to divide MCU access window into 2 */
1110 ipu_cm_write(ipu, 0x00400000L | (IPU_MCU_T_DEFAULT << 18),
1111 IPU_DISP_GEN);
1112
1113 ret = ipu_submodules_init(ipu, pdev, ipu_base, ipu->clk);
1114 if (ret)
1115 goto failed_submodules_init;
1116
1117 ret = ipu_add_client_devices(ipu);
1118 if (ret) {
1119 dev_err(&pdev->dev, "adding client devices failed with %d\n",
1120 ret);
1121 goto failed_add_clients;
1122 }
1123
9c2c438c
FE		 1124 dev_info(&pdev->dev, "%s probed\n", devtype->name);
1125
aecfbdb1
SH		 1126 return 0;
1127
1128failed_add_clients:
1129 ipu_submodules_exit(ipu);
1130failed_submodules_init:
1131 ipu_irq_exit(ipu);
1132out_failed_irq:
1133 clk_disable_unprepare(ipu->clk);
1134failed_clk_get:
1135failed_ioremap:
1136 return ret;
1137}
1138
1139static int __devexit ipu_remove(struct platform_device *pdev)
1140{
1141 struct ipu_soc *ipu = platform_get_drvdata(pdev);
1142 struct resource *res;
1143
1144 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1145
1146 platform_device_unregister_children(pdev);
1147 ipu_submodules_exit(ipu);
1148 ipu_irq_exit(ipu);
1149
1150 clk_disable_unprepare(ipu->clk);
1151
1152 return 0;
1153}
1154
1155static struct platform_driver imx_ipu_driver = {
1156 .driver = {
1157 .name = "imx-ipuv3",
1158 .of_match_table = imx_ipu_dt_ids,
1159 },
1160 .probe = ipu_probe,
1161 .remove = __devexit_p(ipu_remove),
1162};
1163
1164module_platform_driver(imx_ipu_driver);
1165
1166MODULE_DESCRIPTION("i.MX IPU v3 driver");
1167MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
1168MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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