projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 3b86baf2 | 1 | #include <dt-bindings/clock/tegra124-car.h> |
| 0a9375d1 | 2 | #include <dt-bindings/gpio/tegra-gpio.h> |
| 5b605d44 | 3 | #include <dt-bindings/memory/tegra124-mc.h> |
| 4b20bcbe | 4 | #include <dt-bindings/pinctrl/pinctrl-tegra.h> |
| ad03b1a7 | 5 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
| bf9d0267 | 6 | #include <dt-bindings/reset/tegra124-car.h> |
| 26b76f80 | 7 | #include <dt-bindings/thermal/tegra124-soctherm.h> |
| ad03b1a7 JL |
8 | |
| 9 | #include "skeleton.dtsi" | |
| 10 | ||
| 11 | / { | |
| 12 | compatible = "nvidia,tegra124"; | |
| 870c81a4 | 13 | interrupt-parent = <&lic>; |
| e30cb238 SW |
14 | #address-cells = <2>; |
| 15 | #size-cells = <2>; | |
| ad03b1a7 | 16 | |
| b5896f67 | 17 | pcie-controller@01003000 { |
| ee588e2a TR |
18 | compatible = "nvidia,tegra124-pcie"; |
| 19 | device_type = "pci"; | |
| 20 | reg = <0x0 0x01003000 0x0 0x00000800 /* PADS registers */ | |
| 21 | 0x0 0x01003800 0x0 0x00000800 /* AFI registers */ | |
| 22 | 0x0 0x02000000 0x0 0x10000000>; /* configuration space */ | |
| 23 | reg-names = "pads", "afi", "cs"; | |
| 24 | interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ | |
| 25 | <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ | |
| 26 | interrupt-names = "intr", "msi"; | |
| 27 | ||
| 28 | #interrupt-cells = <1>; | |
| 29 | interrupt-map-mask = <0 0 0 0>; | |
| 30 | interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; | |
| 31 | ||
| 32 | bus-range = <0x00 0xff>; | |
| 33 | #address-cells = <3>; | |
| 34 | #size-cells = <2>; | |
| 35 | ||
| 36 | ranges = <0x82000000 0 0x01000000 0x0 0x01000000 0 0x00001000 /* port 0 configuration space */ | |
| 37 | 0x82000000 0 0x01001000 0x0 0x01001000 0 0x00001000 /* port 1 configuration space */ | |
| 38 | 0x81000000 0 0x0 0x0 0x12000000 0 0x00010000 /* downstream I/O (64 KiB) */ | |
| 39 | 0x82000000 0 0x13000000 0x0 0x13000000 0 0x0d000000 /* non-prefetchable memory (208 MiB) */ | |
| 40 | 0xc2000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */ | |
| 41 | ||
| 42 | clocks = <&tegra_car TEGRA124_CLK_PCIE>, | |
| 43 | <&tegra_car TEGRA124_CLK_AFI>, | |
| 44 | <&tegra_car TEGRA124_CLK_PLL_E>, | |
| 45 | <&tegra_car TEGRA124_CLK_CML0>; | |
| 46 | clock-names = "pex", "afi", "pll_e", "cml"; | |
| 47 | resets = <&tegra_car 70>, | |
| 48 | <&tegra_car 72>, | |
| 49 | <&tegra_car 74>; | |
| 50 | reset-names = "pex", "afi", "pcie_x"; | |
| 51 | status = "disabled"; | |
| 52 | ||
| ee588e2a TR |
53 | pci@1,0 { |
| 54 | device_type = "pci"; | |
| 55 | assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>; | |
| 56 | reg = <0x000800 0 0 0 0>; | |
| 57 | status = "disabled"; | |
| 58 | ||
| 59 | #address-cells = <3>; | |
| 60 | #size-cells = <2>; | |
| 61 | ranges; | |
| 62 | ||
| 63 | nvidia,num-lanes = <2>; | |
| 64 | }; | |
| 65 | ||
| 66 | pci@2,0 { | |
| 67 | device_type = "pci"; | |
| 68 | assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>; | |
| 69 | reg = <0x001000 0 0 0 0>; | |
| 70 | status = "disabled"; | |
| 71 | ||
| 72 | #address-cells = <3>; | |
| 73 | #size-cells = <2>; | |
| 74 | ranges; | |
| 75 | ||
| 76 | nvidia,num-lanes = <1>; | |
| 77 | }; | |
| 78 | }; | |
| 79 | ||
| b5896f67 | 80 | host1x@50000000 { |
| ad6be7d1 | 81 | compatible = "nvidia,tegra124-host1x", "simple-bus"; |
| e30cb238 | 82 | reg = <0x0 0x50000000 0x0 0x00034000>; |
| ad6be7d1 TR |
83 | interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */ |
| 84 | <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */ | |
| 85 | clocks = <&tegra_car TEGRA124_CLK_HOST1X>; | |
| 86 | resets = <&tegra_car 28>; | |
| 87 | reset-names = "host1x"; | |
| 88 | ||
| e30cb238 SW |
89 | #address-cells = <2>; |
| 90 | #size-cells = <2>; | |
| ad6be7d1 | 91 | |
| e30cb238 | 92 | ranges = <0 0x54000000 0 0x54000000 0 0x01000000>; |
| ad6be7d1 | 93 | |
| b5896f67 | 94 | dc@54200000 { |
| ad6be7d1 | 95 | compatible = "nvidia,tegra124-dc"; |
| e30cb238 | 96 | reg = <0x0 0x54200000 0x0 0x00040000>; |
| ad6be7d1 TR |
97 | interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; |
| 98 | clocks = <&tegra_car TEGRA124_CLK_DISP1>, | |
| 99 | <&tegra_car TEGRA124_CLK_PLL_P>; | |
| 100 | clock-names = "dc", "parent"; | |
| 101 | resets = <&tegra_car 27>; | |
| 102 | reset-names = "dc"; | |
| 103 | ||
| 5b605d44 TR |
104 | iommus = <&mc TEGRA_SWGROUP_DC>; |
| 105 | ||
| ad6be7d1 TR |
106 | nvidia,head = <0>; |
| 107 | }; | |
| 108 | ||
| b5896f67 | 109 | dc@54240000 { |
| ad6be7d1 | 110 | compatible = "nvidia,tegra124-dc"; |
| e30cb238 | 111 | reg = <0x0 0x54240000 0x0 0x00040000>; |
| ad6be7d1 TR |
112 | interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; |
| 113 | clocks = <&tegra_car TEGRA124_CLK_DISP2>, | |
| 114 | <&tegra_car TEGRA124_CLK_PLL_P>; | |
| 115 | clock-names = "dc", "parent"; | |
| 116 | resets = <&tegra_car 26>; | |
| 117 | reset-names = "dc"; | |
| 118 | ||
| 5b605d44 TR |
119 | iommus = <&mc TEGRA_SWGROUP_DCB>; |
| 120 | ||
| ad6be7d1 TR |
121 | nvidia,head = <1>; |
| 122 | }; | |
| d72be031 | 123 | |
| b5896f67 | 124 | hdmi@54280000 { |
| 9dd604df TR |
125 | compatible = "nvidia,tegra124-hdmi"; |
| 126 | reg = <0x0 0x54280000 0x0 0x00040000>; | |
| 127 | interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; | |
| 128 | clocks = <&tegra_car TEGRA124_CLK_HDMI>, | |
| 129 | <&tegra_car TEGRA124_CLK_PLL_D2_OUT0>; | |
| 130 | clock-names = "hdmi", "parent"; | |
| 131 | resets = <&tegra_car 51>; | |
| 132 | reset-names = "hdmi"; | |
| 133 | status = "disabled"; | |
| 134 | }; | |
| 135 | ||
| b5896f67 | 136 | sor@54540000 { |
| d72be031 | 137 | compatible = "nvidia,tegra124-sor"; |
| e30cb238 | 138 | reg = <0x0 0x54540000 0x0 0x00040000>; |
| d72be031 TR |
139 | interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; |
| 140 | clocks = <&tegra_car TEGRA124_CLK_SOR0>, | |
| 141 | <&tegra_car TEGRA124_CLK_PLL_D_OUT0>, | |
| 142 | <&tegra_car TEGRA124_CLK_PLL_DP>, | |
| 143 | <&tegra_car TEGRA124_CLK_CLK_M>; | |
| 144 | clock-names = "sor", "parent", "dp", "safe"; | |
| 145 | resets = <&tegra_car 182>; | |
| 146 | reset-names = "sor"; | |
| 147 | status = "disabled"; | |
| 148 | }; | |
| 149 | ||
| b5896f67 | 150 | dpaux: dpaux@545c0000 { |
| d72be031 | 151 | compatible = "nvidia,tegra124-dpaux"; |
| e30cb238 | 152 | reg = <0x0 0x545c0000 0x0 0x00040000>; |
| d72be031 TR |
153 | interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; |
| 154 | clocks = <&tegra_car TEGRA124_CLK_DPAUX>, | |
| 155 | <&tegra_car TEGRA124_CLK_PLL_DP>; | |
| 156 | clock-names = "dpaux", "parent"; | |
| 157 | resets = <&tegra_car 181>; | |
| 158 | reset-names = "dpaux"; | |
| 159 | status = "disabled"; | |
| 160 | }; | |
| ad6be7d1 TR |
161 | }; |
| 162 | ||
| b5896f67 | 163 | gic: interrupt-controller@50041000 { |
| ad03b1a7 JL |
164 | compatible = "arm,cortex-a15-gic"; |
| 165 | #interrupt-cells = <3>; | |
| 166 | interrupt-controller; | |
| e30cb238 SW |
167 | reg = <0x0 0x50041000 0x0 0x1000>, |
| 168 | <0x0 0x50042000 0x0 0x1000>, | |
| 169 | <0x0 0x50044000 0x0 0x2000>, | |
| 170 | <0x0 0x50046000 0x0 0x2000>; | |
| ad03b1a7 JL |
171 | interrupts = <GIC_PPI 9 |
| 172 | (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; | |
| 870c81a4 | 173 | interrupt-parent = <&gic>; |
| ad03b1a7 JL |
174 | }; |
| 175 | ||
| b5896f67 MZ |
176 | /* |
| 177 | * Please keep the following 0, notation in place as a former mainline | |
| 178 | * U-Boot version was looking for that particular notation in order to | |
| 179 | * perform required fix-ups on that GPU node. | |
| 180 | */ | |
| d86b1e8d TR |
181 | gpu@0,57000000 { |
| 182 | compatible = "nvidia,gk20a"; | |
| 183 | reg = <0x0 0x57000000 0x0 0x01000000>, | |
| 184 | <0x0 0x58000000 0x0 0x01000000>; | |
| 185 | interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, | |
| 186 | <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; | |
| 187 | interrupt-names = "stall", "nonstall"; | |
| 188 | clocks = <&tegra_car TEGRA124_CLK_GPU>, | |
| 189 | <&tegra_car TEGRA124_CLK_PLL_P_OUT5>; | |
| 190 | clock-names = "gpu", "pwr"; | |
| 191 | resets = <&tegra_car 184>; | |
| 192 | reset-names = "gpu"; | |
| c96cd177 AC |
193 | |
| 194 | iommus = <&mc TEGRA_SWGROUP_GPU>; | |
| 195 | ||
| d86b1e8d TR |
196 | status = "disabled"; |
| 197 | }; | |
| 198 | ||
| 870c81a4 MZ |
199 | lic: interrupt-controller@60004000 { |
| 200 | compatible = "nvidia,tegra124-ictlr", "nvidia,tegra30-ictlr"; | |
| 201 | reg = <0x0 0x60004000 0x0 0x100>, | |
| 202 | <0x0 0x60004100 0x0 0x100>, | |
| 203 | <0x0 0x60004200 0x0 0x100>, | |
| 204 | <0x0 0x60004300 0x0 0x100>, | |
| 205 | <0x0 0x60004400 0x0 0x100>; | |
| 206 | interrupt-controller; | |
| 207 | #interrupt-cells = <3>; | |
| 208 | interrupt-parent = <&gic>; | |
| 209 | }; | |
| 210 | ||
| b5896f67 | 211 | timer@60005000 { |
| b6641294 | 212 | compatible = "nvidia,tegra124-timer", "nvidia,tegra30-timer", "nvidia,tegra20-timer"; |
| e30cb238 | 213 | reg = <0x0 0x60005000 0x0 0x400>; |
| ad03b1a7 JL |
214 | interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, |
| 215 | <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, | |
| 216 | <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, | |
| 217 | <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, | |
| 218 | <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, | |
| 219 | <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; | |
| 3b86baf2 JL |
220 | clocks = <&tegra_car TEGRA124_CLK_TIMER>; |
| 221 | }; | |
| 222 | ||
| b5896f67 | 223 | tegra_car: clock@60006000 { |
| 3b86baf2 | 224 | compatible = "nvidia,tegra124-car"; |
| e30cb238 | 225 | reg = <0x0 0x60006000 0x0 0x1000>; |
| 3b86baf2 | 226 | #clock-cells = <1>; |
| f71e4f03 | 227 | #reset-cells = <1>; |
| b273c887 | 228 | nvidia,external-memory-controller = <&emc>; |
| ad03b1a7 JL |
229 | }; |
| 230 | ||
| b5896f67 | 231 | flow-controller@60007000 { |
| b1023134 TR |
232 | compatible = "nvidia,tegra124-flowctrl"; |
| 233 | reg = <0x0 0x60007000 0x0 0x1000>; | |
| 234 | }; | |
| 235 | ||
| b5896f67 | 236 | actmon@6000c800 { |
| c5f8e8ca TV |
237 | compatible = "nvidia,tegra124-actmon"; |
| 238 | reg = <0x0 0x6000c800 0x0 0x400>; | |
| 239 | interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; | |
| 240 | clocks = <&tegra_car TEGRA124_CLK_ACTMON>, | |
| 241 | <&tegra_car TEGRA124_CLK_EMC>; | |
| 242 | clock-names = "actmon", "emc"; | |
| 243 | resets = <&tegra_car 119>; | |
| 244 | reset-names = "actmon"; | |
| 245 | }; | |
| 246 | ||
| b5896f67 | 247 | gpio: gpio@6000d000 { |
| 0a9375d1 | 248 | compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio"; |
| e30cb238 | 249 | reg = <0x0 0x6000d000 0x0 0x1000>; |
| 0a9375d1 SW |
250 | interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, |
| 251 | <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, | |
| 252 | <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, | |
| 253 | <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, | |
| 254 | <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, | |
| 255 | <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, | |
| 256 | <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, | |
| 257 | <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; | |
| 258 | #gpio-cells = <2>; | |
| 259 | gpio-controller; | |
| 260 | #interrupt-cells = <2>; | |
| 261 | interrupt-controller; | |
| 4f1d8414 | 262 | /* |
| 17cdddf0 | 263 | gpio-ranges = <&pinmux 0 0 251>; |
| 4f1d8414 | 264 | */ |
| 0a9375d1 SW |
265 | }; |
| 266 | ||
| b5896f67 | 267 | apbdma: dma@60020000 { |
| 2f5a913e | 268 | compatible = "nvidia,tegra124-apbdma", "nvidia,tegra148-apbdma"; |
| e30cb238 | 269 | reg = <0x0 0x60020000 0x0 0x1400>; |
| 2f5a913e SW |
270 | interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, |
| 271 | <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, | |
| 272 | <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, | |
| 273 | <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, | |
| 274 | <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, | |
| 275 | <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, | |
| 276 | <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, | |
| 277 | <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, | |
| 278 | <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, | |
| 279 | <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, | |
| 280 | <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, | |
| 281 | <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, | |
| 282 | <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, | |
| 283 | <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, | |
| 284 | <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, | |
| 285 | <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, | |
| 286 | <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, | |
| 287 | <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, | |
| 288 | <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, | |
| 289 | <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, | |
| 290 | <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, | |
| 291 | <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, | |
| 292 | <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, | |
| 293 | <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, | |
| 294 | <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, | |
| 295 | <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, | |
| 296 | <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, | |
| 297 | <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, | |
| 298 | <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, | |
| 299 | <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, | |
| 300 | <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, | |
| 301 | <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; | |
| 302 | clocks = <&tegra_car TEGRA124_CLK_APBDMA>; | |
| 303 | resets = <&tegra_car 34>; | |
| 304 | reset-names = "dma"; | |
| 305 | #dma-cells = <1>; | |
| 306 | }; | |
| 307 | ||
| b5896f67 | 308 | apbmisc@70000800 { |
| 155dfc7b PDS |
309 | compatible = "nvidia,tegra124-apbmisc", "nvidia,tegra20-apbmisc"; |
| 310 | reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */ | |
| 5431b0fd | 311 | <0x0 0x7000e864 0x0 0x04>; /* Strapping options */ |
| 155dfc7b PDS |
312 | }; |
| 313 | ||
| b5896f67 | 314 | pinmux: pinmux@70000868 { |
| caefe637 | 315 | compatible = "nvidia,tegra124-pinmux"; |
| e30cb238 | 316 | reg = <0x0 0x70000868 0x0 0x164>, /* Pad control registers */ |
| 49727d30 SP |
317 | <0x0 0x70003000 0x0 0x434>, /* Mux registers */ |
| 318 | <0x0 0x70000820 0x0 0x008>; /* MIPI pad control */ | |
| caefe637 SW |
319 | }; |
| 320 | ||
| ad03b1a7 JL |
321 | /* |
| 322 | * There are two serial driver i.e. 8250 based simple serial | |
| 323 | * driver and APB DMA based serial driver for higher baudrate | |
| 324 | * and performace. To enable the 8250 based driver, the compatible | |
| 325 | * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable | |
| e1098248 | 326 | * the APB DMA based serial driver, the compatible is |
| ad03b1a7 JL |
327 | * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart". |
| 328 | */ | |
| b5896f67 | 329 | uarta: serial@70006000 { |
| ad03b1a7 | 330 | compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; |
| e30cb238 | 331 | reg = <0x0 0x70006000 0x0 0x40>; |
| ad03b1a7 JL |
332 | reg-shift = <2>; |
| 333 | interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; | |
| 3b86baf2 | 334 | clocks = <&tegra_car TEGRA124_CLK_UARTA>; |
| f71e4f03 SW |
335 | resets = <&tegra_car 6>; |
| 336 | reset-names = "serial"; | |
| 2f5a913e SW |
337 | dmas = <&apbdma 8>, <&apbdma 8>; |
| 338 | dma-names = "rx", "tx"; | |
| ad03b1a7 JL |
339 | status = "disabled"; |
| 340 | }; | |
| 341 | ||
| b5896f67 | 342 | uartb: serial@70006040 { |
| ad03b1a7 | 343 | compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; |
| e30cb238 | 344 | reg = <0x0 0x70006040 0x0 0x40>; |
| ad03b1a7 JL |
345 | reg-shift = <2>; |
| 346 | interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; | |
| 3b86baf2 | 347 | clocks = <&tegra_car TEGRA124_CLK_UARTB>; |
| f71e4f03 SW |
348 | resets = <&tegra_car 7>; |
| 349 | reset-names = "serial"; | |
| 2f5a913e SW |
350 | dmas = <&apbdma 9>, <&apbdma 9>; |
| 351 | dma-names = "rx", "tx"; | |
| ad03b1a7 JL |
352 | status = "disabled"; |
| 353 | }; | |
| 354 | ||
| b5896f67 | 355 | uartc: serial@70006200 { |
| ad03b1a7 | 356 | compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; |
| e30cb238 | 357 | reg = <0x0 0x70006200 0x0 0x40>; |
| ad03b1a7 JL |
358 | reg-shift = <2>; |
| 359 | interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; | |
| 3b86baf2 | 360 | clocks = <&tegra_car TEGRA124_CLK_UARTC>; |
| f71e4f03 SW |
361 | resets = <&tegra_car 55>; |
| 362 | reset-names = "serial"; | |
| 2f5a913e SW |
363 | dmas = <&apbdma 10>, <&apbdma 10>; |
| 364 | dma-names = "rx", "tx"; | |
| ad03b1a7 JL |
365 | status = "disabled"; |
| 366 | }; | |
| 367 | ||
| b5896f67 | 368 | uartd: serial@70006300 { |
| ad03b1a7 | 369 | compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; |
| e30cb238 | 370 | reg = <0x0 0x70006300 0x0 0x40>; |
| ad03b1a7 JL |
371 | reg-shift = <2>; |
| 372 | interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; | |
| 3b86baf2 | 373 | clocks = <&tegra_car TEGRA124_CLK_UARTD>; |
| f71e4f03 SW |
374 | resets = <&tegra_car 65>; |
| 375 | reset-names = "serial"; | |
| 2f5a913e SW |
376 | dmas = <&apbdma 19>, <&apbdma 19>; |
| 377 | dma-names = "rx", "tx"; | |
| ad03b1a7 JL |
378 | status = "disabled"; |
| 379 | }; | |
| 380 | ||
| b5896f67 | 381 | pwm: pwm@7000a000 { |
| 111a1fc2 | 382 | compatible = "nvidia,tegra124-pwm", "nvidia,tegra20-pwm"; |
| e30cb238 | 383 | reg = <0x0 0x7000a000 0x0 0x100>; |
| 111a1fc2 TR |
384 | #pwm-cells = <2>; |
| 385 | clocks = <&tegra_car TEGRA124_CLK_PWM>; | |
| 386 | resets = <&tegra_car 17>; | |
| 387 | reset-names = "pwm"; | |
| 388 | status = "disabled"; | |
| 389 | }; | |
| 390 | ||
| b5896f67 | 391 | i2c@7000c000 { |
| 4f607460 | 392 | compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; |
| e30cb238 | 393 | reg = <0x0 0x7000c000 0x0 0x100>; |
| 4f607460 SW |
394 | interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; |
| 395 | #address-cells = <1>; | |
| 396 | #size-cells = <0>; | |
| 397 | clocks = <&tegra_car TEGRA124_CLK_I2C1>; | |
| 398 | clock-names = "div-clk"; | |
| 399 | resets = <&tegra_car 12>; | |
| 400 | reset-names = "i2c"; | |
| 401 | dmas = <&apbdma 21>, <&apbdma 21>; | |
| 402 | dma-names = "rx", "tx"; | |
| 403 | status = "disabled"; | |
| 404 | }; | |
| 405 | ||
| b5896f67 | 406 | i2c@7000c400 { |
| 4f607460 | 407 | compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; |
| e30cb238 | 408 | reg = <0x0 0x7000c400 0x0 0x100>; |
| 4f607460 SW |
409 | interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; |
| 410 | #address-cells = <1>; | |
| 411 | #size-cells = <0>; | |
| 412 | clocks = <&tegra_car TEGRA124_CLK_I2C2>; | |
| 413 | clock-names = "div-clk"; | |
| 414 | resets = <&tegra_car 54>; | |
| 415 | reset-names = "i2c"; | |
| 416 | dmas = <&apbdma 22>, <&apbdma 22>; | |
| 417 | dma-names = "rx", "tx"; | |
| 418 | status = "disabled"; | |
| 419 | }; | |
| 420 | ||
| b5896f67 | 421 | i2c@7000c500 { |
| 4f607460 | 422 | compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; |
| e30cb238 | 423 | reg = <0x0 0x7000c500 0x0 0x100>; |
| 4f607460 SW |
424 | interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; |
| 425 | #address-cells = <1>; | |
| 426 | #size-cells = <0>; | |
| 427 | clocks = <&tegra_car TEGRA124_CLK_I2C3>; | |
| 428 | clock-names = "div-clk"; | |
| 429 | resets = <&tegra_car 67>; | |
| 430 | reset-names = "i2c"; | |
| 431 | dmas = <&apbdma 23>, <&apbdma 23>; | |
| 432 | dma-names = "rx", "tx"; | |
| 433 | status = "disabled"; | |
| 434 | }; | |
| 435 | ||
| b5896f67 | 436 | i2c@7000c700 { |
| 4f607460 | 437 | compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; |
| e30cb238 | 438 | reg = <0x0 0x7000c700 0x0 0x100>; |
| 4f607460 SW |
439 | interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; |
| 440 | #address-cells = <1>; | |
| 441 | #size-cells = <0>; | |
| 442 | clocks = <&tegra_car TEGRA124_CLK_I2C4>; | |
| 443 | clock-names = "div-clk"; | |
| 444 | resets = <&tegra_car 103>; | |
| 445 | reset-names = "i2c"; | |
| 446 | dmas = <&apbdma 26>, <&apbdma 26>; | |
| 447 | dma-names = "rx", "tx"; | |
| 448 | status = "disabled"; | |
| 449 | }; | |
| 450 | ||
| b5896f67 | 451 | i2c@7000d000 { |
| 4f607460 | 452 | compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; |
| e30cb238 | 453 | reg = <0x0 0x7000d000 0x0 0x100>; |
| 4f607460 SW |
454 | interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; |
| 455 | #address-cells = <1>; | |
| 456 | #size-cells = <0>; | |
| 457 | clocks = <&tegra_car TEGRA124_CLK_I2C5>; | |
| 458 | clock-names = "div-clk"; | |
| 459 | resets = <&tegra_car 47>; | |
| 460 | reset-names = "i2c"; | |
| 461 | dmas = <&apbdma 24>, <&apbdma 24>; | |
| 462 | dma-names = "rx", "tx"; | |
| 463 | status = "disabled"; | |
| 464 | }; | |
| 465 | ||
| b5896f67 | 466 | i2c@7000d100 { |
| 4f607460 | 467 | compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; |
| e30cb238 | 468 | reg = <0x0 0x7000d100 0x0 0x100>; |
| 4f607460 SW |
469 | interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; |
| 470 | #address-cells = <1>; | |
| 471 | #size-cells = <0>; | |
| 472 | clocks = <&tegra_car TEGRA124_CLK_I2C6>; | |
| 473 | clock-names = "div-clk"; | |
| 474 | resets = <&tegra_car 166>; | |
| 475 | reset-names = "i2c"; | |
| 476 | dmas = <&apbdma 30>, <&apbdma 30>; | |
| 477 | dma-names = "rx", "tx"; | |
| 478 | status = "disabled"; | |
| 479 | }; | |
| 480 | ||
| b5896f67 | 481 | spi@7000d400 { |
| 9f1ac560 | 482 | compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; |
| e30cb238 | 483 | reg = <0x0 0x7000d400 0x0 0x200>; |
| 9f1ac560 TR |
484 | interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; |
| 485 | #address-cells = <1>; | |
| 486 | #size-cells = <0>; | |
| 487 | clocks = <&tegra_car TEGRA124_CLK_SBC1>; | |
| 488 | clock-names = "spi"; | |
| 489 | resets = <&tegra_car 41>; | |
| 490 | reset-names = "spi"; | |
| 491 | dmas = <&apbdma 15>, <&apbdma 15>; | |
| 492 | dma-names = "rx", "tx"; | |
| 493 | status = "disabled"; | |
| 494 | }; | |
| 495 | ||
| b5896f67 | 496 | spi@7000d600 { |
| 9f1ac560 | 497 | compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; |
| e30cb238 | 498 | reg = <0x0 0x7000d600 0x0 0x200>; |
| 9f1ac560 TR |
499 | interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; |
| 500 | #address-cells = <1>; | |
| 501 | #size-cells = <0>; | |
| 502 | clocks = <&tegra_car TEGRA124_CLK_SBC2>; | |
| 503 | clock-names = "spi"; | |
| 504 | resets = <&tegra_car 44>; | |
| 505 | reset-names = "spi"; | |
| 506 | dmas = <&apbdma 16>, <&apbdma 16>; | |
| 507 | dma-names = "rx", "tx"; | |
| 508 | status = "disabled"; | |
| 509 | }; | |
| 510 | ||
| b5896f67 | 511 | spi@7000d800 { |
| 9f1ac560 | 512 | compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; |
| e30cb238 | 513 | reg = <0x0 0x7000d800 0x0 0x200>; |
| 9f1ac560 TR |
514 | interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; |
| 515 | #address-cells = <1>; | |
| 516 | #size-cells = <0>; | |
| 517 | clocks = <&tegra_car TEGRA124_CLK_SBC3>; | |
| 518 | clock-names = "spi"; | |
| 519 | resets = <&tegra_car 46>; | |
| 520 | reset-names = "spi"; | |
| 521 | dmas = <&apbdma 17>, <&apbdma 17>; | |
| 522 | dma-names = "rx", "tx"; | |
| 523 | status = "disabled"; | |
| 524 | }; | |
| 525 | ||
| b5896f67 | 526 | spi@7000da00 { |
| 9f1ac560 | 527 | compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; |
| e30cb238 | 528 | reg = <0x0 0x7000da00 0x0 0x200>; |
| 9f1ac560 TR |
529 | interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; |
| 530 | #address-cells = <1>; | |
| 531 | #size-cells = <0>; | |
| 532 | clocks = <&tegra_car TEGRA124_CLK_SBC4>; | |
| 533 | clock-names = "spi"; | |
| 534 | resets = <&tegra_car 68>; | |
| 535 | reset-names = "spi"; | |
| 536 | dmas = <&apbdma 18>, <&apbdma 18>; | |
| 537 | dma-names = "rx", "tx"; | |
| 538 | status = "disabled"; | |
| 539 | }; | |
| 540 | ||
| b5896f67 | 541 | spi@7000dc00 { |
| 9f1ac560 | 542 | compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; |
| e30cb238 | 543 | reg = <0x0 0x7000dc00 0x0 0x200>; |
| 9f1ac560 TR |
544 | interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; |
| 545 | #address-cells = <1>; | |
| 546 | #size-cells = <0>; | |
| 547 | clocks = <&tegra_car TEGRA124_CLK_SBC5>; | |
| 548 | clock-names = "spi"; | |
| 549 | resets = <&tegra_car 104>; | |
| 550 | reset-names = "spi"; | |
| 551 | dmas = <&apbdma 27>, <&apbdma 27>; | |
| 552 | dma-names = "rx", "tx"; | |
| 553 | status = "disabled"; | |
| 554 | }; | |
| 555 | ||
| b5896f67 | 556 | spi@7000de00 { |
| 9f1ac560 | 557 | compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; |
| e30cb238 | 558 | reg = <0x0 0x7000de00 0x0 0x200>; |
| 9f1ac560 TR |
559 | interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; |
| 560 | #address-cells = <1>; | |
| 561 | #size-cells = <0>; | |
| 562 | clocks = <&tegra_car TEGRA124_CLK_SBC6>; | |
| 563 | clock-names = "spi"; | |
| 564 | resets = <&tegra_car 105>; | |
| 565 | reset-names = "spi"; | |
| 566 | dmas = <&apbdma 28>, <&apbdma 28>; | |
| 567 | dma-names = "rx", "tx"; | |
| 568 | status = "disabled"; | |
| 569 | }; | |
| 570 | ||
| b5896f67 | 571 | rtc@7000e000 { |
| ad03b1a7 | 572 | compatible = "nvidia,tegra124-rtc", "nvidia,tegra20-rtc"; |
| e30cb238 | 573 | reg = <0x0 0x7000e000 0x0 0x100>; |
| ad03b1a7 | 574 | interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; |
| 3b86baf2 | 575 | clocks = <&tegra_car TEGRA124_CLK_RTC>; |
| ad03b1a7 JL |
576 | }; |
| 577 | ||
| b5896f67 | 578 | pmc@7000e400 { |
| ad03b1a7 | 579 | compatible = "nvidia,tegra124-pmc"; |
| e30cb238 | 580 | reg = <0x0 0x7000e400 0x0 0x400>; |
| 3b86baf2 JL |
581 | clocks = <&tegra_car TEGRA124_CLK_PCLK>, <&clk32k_in>; |
| 582 | clock-names = "pclk", "clk32k_in"; | |
| ad03b1a7 JL |
583 | }; |
| 584 | ||
| b5896f67 | 585 | fuse@7000f800 { |
| 155dfc7b PDS |
586 | compatible = "nvidia,tegra124-efuse"; |
| 587 | reg = <0x0 0x7000f800 0x0 0x400>; | |
| 588 | clocks = <&tegra_car TEGRA124_CLK_FUSE>; | |
| 589 | clock-names = "fuse"; | |
| 590 | resets = <&tegra_car 39>; | |
| 591 | reset-names = "fuse"; | |
| 592 | }; | |
| 593 | ||
| b5896f67 | 594 | mc: memory-controller@70019000 { |
| b26ea06b TR |
595 | compatible = "nvidia,tegra124-mc"; |
| 596 | reg = <0x0 0x70019000 0x0 0x1000>; | |
| 597 | clocks = <&tegra_car TEGRA124_CLK_MC>; | |
| 598 | clock-names = "mc"; | |
| 599 | ||
| 600 | interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; | |
| 601 | ||
| 602 | #iommu-cells = <1>; | |
| 603 | }; | |
| 604 | ||
| b5896f67 | 605 | emc: emc@7001b000 { |
| b273c887 MP |
606 | compatible = "nvidia,tegra124-emc"; |
| 607 | reg = <0x0 0x7001b000 0x0 0x1000>; | |
| 608 | ||
| 609 | nvidia,memory-controller = <&mc>; | |
| 610 | }; | |
| 611 | ||
| b5896f67 | 612 | sata@70020000 { |
| fdd69096 | 613 | compatible = "nvidia,tegra124-ahci"; |
| fdd69096 | 614 | reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */ |
| 481b4f1a | 615 | <0x0 0x70020000 0x0 0x7000>; /* SATA */ |
| fdd69096 | 616 | interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; |
| fdd69096 | 617 | clocks = <&tegra_car TEGRA124_CLK_SATA>, |
| 481b4f1a TR |
618 | <&tegra_car TEGRA124_CLK_SATA_OOB>, |
| 619 | <&tegra_car TEGRA124_CLK_CML1>, | |
| 620 | <&tegra_car TEGRA124_CLK_PLL_E>; | |
| fdd69096 | 621 | clock-names = "sata", "sata-oob", "cml1", "pll_e"; |
| fdd69096 | 622 | resets = <&tegra_car 124>, |
| 481b4f1a TR |
623 | <&tegra_car 123>, |
| 624 | <&tegra_car 129>; | |
| fdd69096 | 625 | reset-names = "sata", "sata-oob", "sata-cold"; |
| fdd69096 MP |
626 | status = "disabled"; |
| 627 | }; | |
| 628 | ||
| b5896f67 | 629 | hda@70030000 { |
| 6389cb3b DR |
630 | compatible = "nvidia,tegra124-hda", "nvidia,tegra30-hda"; |
| 631 | reg = <0x0 0x70030000 0x0 0x10000>; | |
| 632 | interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; | |
| 633 | clocks = <&tegra_car TEGRA124_CLK_HDA>, | |
| d8b316b2 | 634 | <&tegra_car TEGRA124_CLK_HDA2HDMI>, |
| 6389cb3b | 635 | <&tegra_car TEGRA124_CLK_HDA2CODEC_2X>; |
| 869bd180 | 636 | clock-names = "hda", "hda2hdmi", "hda2codec_2x"; |
| 6389cb3b DR |
637 | resets = <&tegra_car 125>, /* hda */ |
| 638 | <&tegra_car 128>, /* hda2hdmi */ | |
| 639 | <&tegra_car 111>; /* hda2codec_2x */ | |
| 869bd180 | 640 | reset-names = "hda", "hda2hdmi", "hda2codec_2x"; |
| 6389cb3b DR |
641 | status = "disabled"; |
| 642 | }; | |
| 643 | ||
| b5896f67 | 644 | usb@70090000 { |
| 2d8a9c9c TR |
645 | compatible = "nvidia,tegra124-xusb"; |
| 646 | reg = <0x0 0x70090000 0x0 0x8000>, | |
| 647 | <0x0 0x70098000 0x0 0x1000>, | |
| 648 | <0x0 0x70099000 0x0 0x1000>; | |
| 649 | reg-names = "hcd", "fpci", "ipfs"; | |
| 650 | ||
| 651 | interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, | |
| 652 | <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; | |
| 653 | ||
| 654 | clocks = <&tegra_car TEGRA124_CLK_XUSB_HOST>, | |
| 655 | <&tegra_car TEGRA124_CLK_XUSB_HOST_SRC>, | |
| 656 | <&tegra_car TEGRA124_CLK_XUSB_FALCON_SRC>, | |
| 657 | <&tegra_car TEGRA124_CLK_XUSB_SS>, | |
| 658 | <&tegra_car TEGRA124_CLK_XUSB_SS_DIV2>, | |
| 659 | <&tegra_car TEGRA124_CLK_XUSB_SS_SRC>, | |
| 660 | <&tegra_car TEGRA124_CLK_XUSB_HS_SRC>, | |
| 661 | <&tegra_car TEGRA124_CLK_XUSB_FS_SRC>, | |
| 662 | <&tegra_car TEGRA124_CLK_PLL_U_480M>, | |
| 663 | <&tegra_car TEGRA124_CLK_CLK_M>, | |
| 664 | <&tegra_car TEGRA124_CLK_PLL_E>; | |
| 665 | clock-names = "xusb_host", "xusb_host_src", | |
| 666 | "xusb_falcon_src", "xusb_ss", | |
| 667 | "xusb_ss_div2", "xusb_ss_src", | |
| 668 | "xusb_hs_src", "xusb_fs_src", | |
| 669 | "pll_u_480m", "clk_m", "pll_e"; | |
| 670 | resets = <&tegra_car 89>, <&tegra_car 156>, | |
| 671 | <&tegra_car 143>; | |
| 672 | reset-names = "xusb_host", "xusb_ss", "xusb_src"; | |
| 673 | ||
| 674 | nvidia,xusb-padctl = <&padctl>; | |
| 675 | ||
| 676 | status = "disabled"; | |
| 677 | }; | |
| 678 | ||
| b5896f67 | 679 | padctl: padctl@7009f000 { |
| ce90d32d TR |
680 | compatible = "nvidia,tegra124-xusb-padctl"; |
| 681 | reg = <0x0 0x7009f000 0x0 0x1000>; | |
| 682 | resets = <&tegra_car 142>; | |
| 683 | reset-names = "padctl"; | |
| 684 | ||
| 50623c59 TR |
685 | pads { |
| 686 | usb2 { | |
| 687 | status = "disabled"; | |
| 688 | ||
| 689 | lanes { | |
| 690 | usb2-0 { | |
| 691 | status = "disabled"; | |
| 692 | #phy-cells = <0>; | |
| 693 | }; | |
| 694 | ||
| 695 | usb2-1 { | |
| 696 | status = "disabled"; | |
| 697 | #phy-cells = <0>; | |
| 698 | }; | |
| 699 | ||
| 700 | usb2-2 { | |
| 701 | status = "disabled"; | |
| 702 | #phy-cells = <0>; | |
| 703 | }; | |
| 704 | }; | |
| 705 | }; | |
| 706 | ||
| 707 | ulpi { | |
| 708 | status = "disabled"; | |
| 709 | ||
| 710 | lanes { | |
| 711 | ulpi-0 { | |
| 712 | status = "disabled"; | |
| 713 | #phy-cells = <0>; | |
| 714 | }; | |
| 715 | }; | |
| 716 | }; | |
| 717 | ||
| 718 | hsic { | |
| 719 | status = "disabled"; | |
| 720 | ||
| 721 | lanes { | |
| 722 | hsic-0 { | |
| 723 | status = "disabled"; | |
| 724 | #phy-cells = <0>; | |
| 725 | }; | |
| 726 | ||
| 727 | hsic-1 { | |
| 728 | status = "disabled"; | |
| 729 | #phy-cells = <0>; | |
| 730 | }; | |
| 731 | }; | |
| 732 | }; | |
| 733 | ||
| 734 | pcie { | |
| 735 | status = "disabled"; | |
| 736 | ||
| 737 | lanes { | |
| 738 | pcie-0 { | |
| 739 | status = "disabled"; | |
| 740 | #phy-cells = <0>; | |
| 741 | }; | |
| 742 | ||
| 743 | pcie-1 { | |
| 744 | status = "disabled"; | |
| 745 | #phy-cells = <0>; | |
| 746 | }; | |
| 747 | ||
| 748 | pcie-2 { | |
| 749 | status = "disabled"; | |
| 750 | #phy-cells = <0>; | |
| 751 | }; | |
| 752 | ||
| 753 | pcie-3 { | |
| 754 | status = "disabled"; | |
| 755 | #phy-cells = <0>; | |
| 756 | }; | |
| 757 | ||
| 758 | pcie-4 { | |
| 759 | status = "disabled"; | |
| 760 | #phy-cells = <0>; | |
| 761 | }; | |
| 762 | }; | |
| 763 | }; | |
| 764 | ||
| 765 | sata { | |
| 766 | status = "disabled"; | |
| 767 | ||
| 768 | lanes { | |
| 769 | sata-0 { | |
| 770 | status = "disabled"; | |
| 771 | #phy-cells = <0>; | |
| 772 | }; | |
| 773 | }; | |
| 774 | }; | |
| 775 | }; | |
| 776 | ||
| 777 | ports { | |
| 778 | usb2-0 { | |
| 779 | status = "disabled"; | |
| 780 | }; | |
| 781 | ||
| 782 | usb2-1 { | |
| 783 | status = "disabled"; | |
| 784 | }; | |
| 785 | ||
| 786 | usb2-2 { | |
| 787 | status = "disabled"; | |
| 788 | }; | |
| 789 | ||
| 790 | ulpi-0 { | |
| 791 | status = "disabled"; | |
| 792 | }; | |
| 793 | ||
| 794 | hsic-0 { | |
| 795 | status = "disabled"; | |
| 796 | }; | |
| 797 | ||
| 798 | hsic-1 { | |
| 799 | status = "disabled"; | |
| 800 | }; | |
| 801 | ||
| 802 | usb3-0 { | |
| 803 | status = "disabled"; | |
| 804 | }; | |
| 805 | ||
| 806 | usb3-1 { | |
| 807 | status = "disabled"; | |
| 808 | }; | |
| 809 | }; | |
| ce90d32d TR |
810 | }; |
| 811 | ||
| b5896f67 | 812 | sdhci@700b0000 { |
| 784c7444 | 813 | compatible = "nvidia,tegra124-sdhci"; |
| e30cb238 | 814 | reg = <0x0 0x700b0000 0x0 0x200>; |
| 784c7444 SW |
815 | interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; |
| 816 | clocks = <&tegra_car TEGRA124_CLK_SDMMC1>; | |
| 817 | resets = <&tegra_car 14>; | |
| 818 | reset-names = "sdhci"; | |
| e2b6d77e | 819 | status = "disabled"; |
| 784c7444 SW |
820 | }; |
| 821 | ||
| b5896f67 | 822 | sdhci@700b0200 { |
| 784c7444 | 823 | compatible = "nvidia,tegra124-sdhci"; |
| e30cb238 | 824 | reg = <0x0 0x700b0200 0x0 0x200>; |
| 784c7444 SW |
825 | interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; |
| 826 | clocks = <&tegra_car TEGRA124_CLK_SDMMC2>; | |
| 827 | resets = <&tegra_car 9>; | |
| 828 | reset-names = "sdhci"; | |
| e2b6d77e | 829 | status = "disabled"; |
| 784c7444 SW |
830 | }; |
| 831 | ||
| b5896f67 | 832 | sdhci@700b0400 { |
| 784c7444 | 833 | compatible = "nvidia,tegra124-sdhci"; |
| e30cb238 | 834 | reg = <0x0 0x700b0400 0x0 0x200>; |
| 784c7444 SW |
835 | interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; |
| 836 | clocks = <&tegra_car TEGRA124_CLK_SDMMC3>; | |
| 837 | resets = <&tegra_car 69>; | |
| 838 | reset-names = "sdhci"; | |
| e2b6d77e | 839 | status = "disabled"; |
| 784c7444 SW |
840 | }; |
| 841 | ||
| b5896f67 | 842 | sdhci@700b0600 { |
| 784c7444 | 843 | compatible = "nvidia,tegra124-sdhci"; |
| e30cb238 | 844 | reg = <0x0 0x700b0600 0x0 0x200>; |
| 784c7444 SW |
845 | interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; |
| 846 | clocks = <&tegra_car TEGRA124_CLK_SDMMC4>; | |
| 847 | resets = <&tegra_car 15>; | |
| 848 | reset-names = "sdhci"; | |
| e2b6d77e | 849 | status = "disabled"; |
| 784c7444 SW |
850 | }; |
| 851 | ||
| b5896f67 | 852 | soctherm: thermal-sensor@700e2000 { |
| 26b76f80 MP |
853 | compatible = "nvidia,tegra124-soctherm"; |
| 854 | reg = <0x0 0x700e2000 0x0 0x1000>; | |
| 855 | interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; | |
| 856 | clocks = <&tegra_car TEGRA124_CLK_TSENSOR>, | |
| 857 | <&tegra_car TEGRA124_CLK_SOC_THERM>; | |
| 858 | clock-names = "tsensor", "soctherm"; | |
| 859 | resets = <&tegra_car 78>; | |
| 860 | reset-names = "soctherm"; | |
| 861 | #thermal-sensor-cells = <1>; | |
| 862 | }; | |
| 863 | ||
| b5896f67 | 864 | dfll: clock@70110000 { |
| bf9d0267 TT |
865 | compatible = "nvidia,tegra124-dfll"; |
| 866 | reg = <0 0x70110000 0 0x100>, /* DFLL control */ | |
| 867 | <0 0x70110000 0 0x100>, /* I2C output control */ | |
| 868 | <0 0x70110100 0 0x100>, /* Integrated I2C controller */ | |
| 869 | <0 0x70110200 0 0x100>; /* Look-up table RAM */ | |
| 870 | interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; | |
| 871 | clocks = <&tegra_car TEGRA124_CLK_DFLL_SOC>, | |
| 872 | <&tegra_car TEGRA124_CLK_DFLL_REF>, | |
| 873 | <&tegra_car TEGRA124_CLK_I2C5>; | |
| 874 | clock-names = "soc", "ref", "i2c"; | |
| 875 | resets = <&tegra_car TEGRA124_RST_DFLL_DVCO>; | |
| 876 | reset-names = "dvco"; | |
| 877 | #clock-cells = <0>; | |
| 878 | clock-output-names = "dfllCPU_out"; | |
| 879 | nvidia,sample-rate = <12500>; | |
| 880 | nvidia,droop-ctrl = <0x00000f00>; | |
| 881 | nvidia,force-mode = <1>; | |
| 882 | nvidia,cf = <10>; | |
| 883 | nvidia,ci = <0>; | |
| 884 | nvidia,cg = <2>; | |
| 885 | status = "disabled"; | |
| 886 | }; | |
| 887 | ||
| b5896f67 | 888 | ahub@70300000 { |
| e6655578 | 889 | compatible = "nvidia,tegra124-ahub"; |
| e30cb238 SW |
890 | reg = <0x0 0x70300000 0x0 0x200>, |
| 891 | <0x0 0x70300800 0x0 0x800>, | |
| 892 | <0x0 0x70300200 0x0 0x600>; | |
| e6655578 SW |
893 | interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; |
| 894 | clocks = <&tegra_car TEGRA124_CLK_D_AUDIO>, | |
| 895 | <&tegra_car TEGRA124_CLK_APBIF>; | |
| 896 | clock-names = "d_audio", "apbif"; | |
| 897 | resets = <&tegra_car 106>, /* d_audio */ | |
| 898 | <&tegra_car 107>, /* apbif */ | |
| 899 | <&tegra_car 30>, /* i2s0 */ | |
| 900 | <&tegra_car 11>, /* i2s1 */ | |
| 901 | <&tegra_car 18>, /* i2s2 */ | |
| 902 | <&tegra_car 101>, /* i2s3 */ | |
| 903 | <&tegra_car 102>, /* i2s4 */ | |
| 904 | <&tegra_car 108>, /* dam0 */ | |
| 905 | <&tegra_car 109>, /* dam1 */ | |
| 906 | <&tegra_car 110>, /* dam2 */ | |
| 907 | <&tegra_car 10>, /* spdif */ | |
| 908 | <&tegra_car 153>, /* amx */ | |
| 909 | <&tegra_car 185>, /* amx1 */ | |
| 910 | <&tegra_car 154>, /* adx */ | |
| 911 | <&tegra_car 180>, /* adx1 */ | |
| 912 | <&tegra_car 186>, /* afc0 */ | |
| 913 | <&tegra_car 187>, /* afc1 */ | |
| 914 | <&tegra_car 188>, /* afc2 */ | |
| 915 | <&tegra_car 189>, /* afc3 */ | |
| 916 | <&tegra_car 190>, /* afc4 */ | |
| 917 | <&tegra_car 191>; /* afc5 */ | |
| 918 | reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2", | |
| 919 | "i2s3", "i2s4", "dam0", "dam1", "dam2", | |
| 920 | "spdif", "amx", "amx1", "adx", "adx1", | |
| 921 | "afc0", "afc1", "afc2", "afc3", "afc4", "afc5"; | |
| 922 | dmas = <&apbdma 1>, <&apbdma 1>, | |
| 923 | <&apbdma 2>, <&apbdma 2>, | |
| 924 | <&apbdma 3>, <&apbdma 3>, | |
| 925 | <&apbdma 4>, <&apbdma 4>, | |
| 926 | <&apbdma 6>, <&apbdma 6>, | |
| 927 | <&apbdma 7>, <&apbdma 7>, | |
| 928 | <&apbdma 12>, <&apbdma 12>, | |
| 929 | <&apbdma 13>, <&apbdma 13>, | |
| 930 | <&apbdma 14>, <&apbdma 14>, | |
| 931 | <&apbdma 29>, <&apbdma 29>; | |
| 932 | dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2", | |
| 933 | "rx3", "tx3", "rx4", "tx4", "rx5", "tx5", | |
| 934 | "rx6", "tx6", "rx7", "tx7", "rx8", "tx8", | |
| 935 | "rx9", "tx9"; | |
| 936 | ranges; | |
| e30cb238 SW |
937 | #address-cells = <2>; |
| 938 | #size-cells = <2>; | |
| e6655578 | 939 | |
| b5896f67 | 940 | tegra_i2s0: i2s@70301000 { |
| e6655578 | 941 | compatible = "nvidia,tegra124-i2s"; |
| e30cb238 | 942 | reg = <0x0 0x70301000 0x0 0x100>; |
| e6655578 SW |
943 | nvidia,ahub-cif-ids = <4 4>; |
| 944 | clocks = <&tegra_car TEGRA124_CLK_I2S0>; | |
| 945 | resets = <&tegra_car 30>; | |
| 946 | reset-names = "i2s"; | |
| 947 | status = "disabled"; | |
| 948 | }; | |
| 949 | ||
| b5896f67 | 950 | tegra_i2s1: i2s@70301100 { |
| e6655578 | 951 | compatible = "nvidia,tegra124-i2s"; |
| e30cb238 | 952 | reg = <0x0 0x70301100 0x0 0x100>; |
| e6655578 SW |
953 | nvidia,ahub-cif-ids = <5 5>; |
| 954 | clocks = <&tegra_car TEGRA124_CLK_I2S1>; | |
| 955 | resets = <&tegra_car 11>; | |
| 956 | reset-names = "i2s"; | |
| 957 | status = "disabled"; | |
| 958 | }; | |
| 959 | ||
| b5896f67 | 960 | tegra_i2s2: i2s@70301200 { |
| e6655578 | 961 | compatible = "nvidia,tegra124-i2s"; |
| e30cb238 | 962 | reg = <0x0 0x70301200 0x0 0x100>; |
| e6655578 SW |
963 | nvidia,ahub-cif-ids = <6 6>; |
| 964 | clocks = <&tegra_car TEGRA124_CLK_I2S2>; | |
| 965 | resets = <&tegra_car 18>; | |
| 966 | reset-names = "i2s"; | |
| 967 | status = "disabled"; | |
| 968 | }; | |
| 969 | ||
| b5896f67 | 970 | tegra_i2s3: i2s@70301300 { |
| e6655578 | 971 | compatible = "nvidia,tegra124-i2s"; |
| e30cb238 | 972 | reg = <0x0 0x70301300 0x0 0x100>; |
| e6655578 SW |
973 | nvidia,ahub-cif-ids = <7 7>; |
| 974 | clocks = <&tegra_car TEGRA124_CLK_I2S3>; | |
| 975 | resets = <&tegra_car 101>; | |
| 976 | reset-names = "i2s"; | |
| 977 | status = "disabled"; | |
| 978 | }; | |
| 979 | ||
| b5896f67 | 980 | tegra_i2s4: i2s@70301400 { |
| e6655578 | 981 | compatible = "nvidia,tegra124-i2s"; |
| e30cb238 | 982 | reg = <0x0 0x70301400 0x0 0x100>; |
| e6655578 SW |
983 | nvidia,ahub-cif-ids = <8 8>; |
| 984 | clocks = <&tegra_car TEGRA124_CLK_I2S4>; | |
| 985 | resets = <&tegra_car 102>; | |
| 986 | reset-names = "i2s"; | |
| 987 | status = "disabled"; | |
| 988 | }; | |
| 989 | }; | |
| 990 | ||
| b5896f67 | 991 | usb@7d000000 { |
| f2d50158 | 992 | compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci"; |
| e30cb238 | 993 | reg = <0x0 0x7d000000 0x0 0x4000>; |
| f2d50158 TR |
994 | interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; |
| 995 | phy_type = "utmi"; | |
| 996 | clocks = <&tegra_car TEGRA124_CLK_USBD>; | |
| 997 | resets = <&tegra_car 22>; | |
| 998 | reset-names = "usb"; | |
| 999 | nvidia,phy = <&phy1>; | |
| 1000 | status = "disabled"; | |
| 1001 | }; | |
| 1002 | ||
| b5896f67 | 1003 | phy1: usb-phy@7d000000 { |
| f2d50158 | 1004 | compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy"; |
| e30cb238 SW |
1005 | reg = <0x0 0x7d000000 0x0 0x4000>, |
| 1006 | <0x0 0x7d000000 0x0 0x4000>; | |
| f2d50158 TR |
1007 | phy_type = "utmi"; |
| 1008 | clocks = <&tegra_car TEGRA124_CLK_USBD>, | |
| 1009 | <&tegra_car TEGRA124_CLK_PLL_U>, | |
| 1010 | <&tegra_car TEGRA124_CLK_USBD>; | |
| 1011 | clock-names = "reg", "pll_u", "utmi-pads"; | |
| a4b6916c | 1012 | resets = <&tegra_car 22>, <&tegra_car 22>; |
| 308efde2 | 1013 | reset-names = "usb", "utmi-pads"; |
| f2d50158 TR |
1014 | nvidia,hssync-start-delay = <0>; |
| 1015 | nvidia,idle-wait-delay = <17>; | |
| 1016 | nvidia,elastic-limit = <16>; | |
| 1017 | nvidia,term-range-adj = <6>; | |
| 1018 | nvidia,xcvr-setup = <9>; | |
| 1019 | nvidia,xcvr-lsfslew = <0>; | |
| 1020 | nvidia,xcvr-lsrslew = <3>; | |
| 1021 | nvidia,hssquelch-level = <2>; | |
| 1022 | nvidia,hsdiscon-level = <5>; | |
| 1023 | nvidia,xcvr-hsslew = <12>; | |
| a4b6916c | 1024 | nvidia,has-utmi-pad-registers; |
| f2d50158 TR |
1025 | status = "disabled"; |
| 1026 | }; | |
| 1027 | ||
| b5896f67 | 1028 | usb@7d004000 { |
| f2d50158 | 1029 | compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci"; |
| e30cb238 | 1030 | reg = <0x0 0x7d004000 0x0 0x4000>; |
| f2d50158 TR |
1031 | interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; |
| 1032 | phy_type = "utmi"; | |
| 1033 | clocks = <&tegra_car TEGRA124_CLK_USB2>; | |
| 1034 | resets = <&tegra_car 58>; | |
| 1035 | reset-names = "usb"; | |
| 1036 | nvidia,phy = <&phy2>; | |
| 1037 | status = "disabled"; | |
| 1038 | }; | |
| 1039 | ||
| b5896f67 | 1040 | phy2: usb-phy@7d004000 { |
| f2d50158 | 1041 | compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy"; |
| e30cb238 SW |
1042 | reg = <0x0 0x7d004000 0x0 0x4000>, |
| 1043 | <0x0 0x7d000000 0x0 0x4000>; | |
| f2d50158 TR |
1044 | phy_type = "utmi"; |
| 1045 | clocks = <&tegra_car TEGRA124_CLK_USB2>, | |
| 1046 | <&tegra_car TEGRA124_CLK_PLL_U>, | |
| 1047 | <&tegra_car TEGRA124_CLK_USBD>; | |
| 1048 | clock-names = "reg", "pll_u", "utmi-pads"; | |
| a4b6916c | 1049 | resets = <&tegra_car 58>, <&tegra_car 22>; |
| 308efde2 | 1050 | reset-names = "usb", "utmi-pads"; |
| f2d50158 TR |
1051 | nvidia,hssync-start-delay = <0>; |
| 1052 | nvidia,idle-wait-delay = <17>; | |
| 1053 | nvidia,elastic-limit = <16>; | |
| 1054 | nvidia,term-range-adj = <6>; | |
| 1055 | nvidia,xcvr-setup = <9>; | |
| 1056 | nvidia,xcvr-lsfslew = <0>; | |
| 1057 | nvidia,xcvr-lsrslew = <3>; | |
| 1058 | nvidia,hssquelch-level = <2>; | |
| 1059 | nvidia,hsdiscon-level = <5>; | |
| 1060 | nvidia,xcvr-hsslew = <12>; | |
| 1061 | status = "disabled"; | |
| 1062 | }; | |
| 1063 | ||
| b5896f67 | 1064 | usb@7d008000 { |
| f2d50158 | 1065 | compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci"; |
| e30cb238 | 1066 | reg = <0x0 0x7d008000 0x0 0x4000>; |
| f2d50158 TR |
1067 | interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; |
| 1068 | phy_type = "utmi"; | |
| 1069 | clocks = <&tegra_car TEGRA124_CLK_USB3>; | |
| 1070 | resets = <&tegra_car 59>; | |
| 1071 | reset-names = "usb"; | |
| 1072 | nvidia,phy = <&phy3>; | |
| 1073 | status = "disabled"; | |
| 1074 | }; | |
| 1075 | ||
| b5896f67 | 1076 | phy3: usb-phy@7d008000 { |
| f2d50158 | 1077 | compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy"; |
| e30cb238 SW |
1078 | reg = <0x0 0x7d008000 0x0 0x4000>, |
| 1079 | <0x0 0x7d000000 0x0 0x4000>; | |
| f2d50158 TR |
1080 | phy_type = "utmi"; |
| 1081 | clocks = <&tegra_car TEGRA124_CLK_USB3>, | |
| 1082 | <&tegra_car TEGRA124_CLK_PLL_U>, | |
| 1083 | <&tegra_car TEGRA124_CLK_USBD>; | |
| 1084 | clock-names = "reg", "pll_u", "utmi-pads"; | |
| a4b6916c | 1085 | resets = <&tegra_car 59>, <&tegra_car 22>; |
| 308efde2 | 1086 | reset-names = "usb", "utmi-pads"; |
| f2d50158 TR |
1087 | nvidia,hssync-start-delay = <0>; |
| 1088 | nvidia,idle-wait-delay = <17>; | |
| 1089 | nvidia,elastic-limit = <16>; | |
| 1090 | nvidia,term-range-adj = <6>; | |
| 1091 | nvidia,xcvr-setup = <9>; | |
| 1092 | nvidia,xcvr-lsfslew = <0>; | |
| 1093 | nvidia,xcvr-lsrslew = <3>; | |
| 1094 | nvidia,hssquelch-level = <2>; | |
| 1095 | nvidia,hsdiscon-level = <5>; | |
| 1096 | nvidia,xcvr-hsslew = <12>; | |
| 1097 | status = "disabled"; | |
| 1098 | }; | |
| 1099 | ||
| ad03b1a7 JL |
1100 | cpus { |
| 1101 | #address-cells = <1>; | |
| 1102 | #size-cells = <0>; | |
| 1103 | ||
| 1104 | cpu@0 { | |
| 1105 | device_type = "cpu"; | |
| 1106 | compatible = "arm,cortex-a15"; | |
| 1107 | reg = <0>; | |
| 0de088cc TT |
1108 | |
| 1109 | clocks = <&tegra_car TEGRA124_CLK_CCLK_G>, | |
| 1110 | <&tegra_car TEGRA124_CLK_CCLK_LP>, | |
| 1111 | <&tegra_car TEGRA124_CLK_PLL_X>, | |
| 1112 | <&tegra_car TEGRA124_CLK_PLL_P>, | |
| 1113 | <&dfll>; | |
| 1114 | clock-names = "cpu_g", "cpu_lp", "pll_x", "pll_p", "dfll"; | |
| 1115 | /* FIXME: what's the actual transition time? */ | |
| 1116 | clock-latency = <300000>; | |
| ad03b1a7 JL |
1117 | }; |
| 1118 | ||
| 1119 | cpu@1 { | |
| 1120 | device_type = "cpu"; | |
| 1121 | compatible = "arm,cortex-a15"; | |
| 1122 | reg = <1>; | |
| 1123 | }; | |
| 1124 | ||
| 1125 | cpu@2 { | |
| 1126 | device_type = "cpu"; | |
| 1127 | compatible = "arm,cortex-a15"; | |
| 1128 | reg = <2>; | |
| 1129 | }; | |
| 1130 | ||
| 1131 | cpu@3 { | |
| 1132 | device_type = "cpu"; | |
| 1133 | compatible = "arm,cortex-a15"; | |
| 1134 | reg = <3>; | |
| 1135 | }; | |
| 1136 | }; | |
| 1137 | ||
| 82fe42f5 KH |
1138 | pmu { |
| 1139 | compatible = "arm,cortex-a15-pmu"; | |
| 1140 | interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, | |
| 1141 | <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, | |
| 1142 | <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, | |
| 1143 | <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; | |
| 1144 | interrupt-affinity = <&{/cpus/cpu@0}>, | |
| 1145 | <&{/cpus/cpu@1}>, | |
| 1146 | <&{/cpus/cpu@2}>, | |
| 1147 | <&{/cpus/cpu@3}>; | |
| 1148 | }; | |
| 1149 | ||
| 26b76f80 MP |
1150 | thermal-zones { |
| 1151 | cpu { | |
| 1152 | polling-delay-passive = <1000>; | |
| 1153 | polling-delay = <1000>; | |
| 1154 | ||
| 1155 | thermal-sensors = | |
| 1156 | <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>; | |
| 1157 | }; | |
| 1158 | ||
| 1159 | mem { | |
| 1160 | polling-delay-passive = <1000>; | |
| 1161 | polling-delay = <1000>; | |
| 1162 | ||
| 1163 | thermal-sensors = | |
| 1164 | <&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>; | |
| 1165 | }; | |
| 1166 | ||
| 1167 | gpu { | |
| 1168 | polling-delay-passive = <1000>; | |
| 1169 | polling-delay = <1000>; | |
| 1170 | ||
| 1171 | thermal-sensors = | |
| 1172 | <&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>; | |
| 1173 | }; | |
| 1174 | ||
| 1175 | pllx { | |
| 1176 | polling-delay-passive = <1000>; | |
| 1177 | polling-delay = <1000>; | |
| 1178 | ||
| 1179 | thermal-sensors = | |
| 1180 | <&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>; | |
| 1181 | }; | |
| 1182 | }; | |
| 1183 | ||
| ad03b1a7 JL |
1184 | timer { |
| 1185 | compatible = "arm,armv7-timer"; | |
| 1186 | interrupts = <GIC_PPI 13 | |
| 1187 | (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, | |
| 1188 | <GIC_PPI 14 | |
| 1189 | (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, | |
| 1190 | <GIC_PPI 11 | |
| 1191 | (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, | |
| 1192 | <GIC_PPI 10 | |
| 1193 | (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; | |
| 870c81a4 | 1194 | interrupt-parent = <&gic>; |
| ad03b1a7 JL |
1195 | }; |
| 1196 | }; |