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gdb: move displaced stepping logic to gdbarch, allow starting concurrent displaced...
[deliverable/binutils-gdb.git] / gdb / amd64-tdep.c
CommitLineData
e53bef9f 1/* Target-dependent code for AMD64.
ce0eebec 2
11bc5fe4 3 Copyright (C) 2001-2020 Free Software Foundation, Inc.
5ae96ec1
MK		 4
5 Contributed by Jiri Smid, SuSE Labs.
53e95fcf
JS		 6
7 This file is part of GDB.
8
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
a9762ec7 11 the Free Software Foundation; either version 3 of the License, or
53e95fcf
JS		 12 (at your option) any later version.
13
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
a9762ec7 20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
53e95fcf
JS		 21
22#include "defs.h"
4de283e4
TT		 23#include "opcode/i386.h"
24#include "dis-asm.h"
c4f35dd8
MK		 25#include "arch-utils.h"
26#include "block.h"
27#include "dummy-frame.h"
4de283e4 28#include "frame.h"
c4f35dd8
MK		 29#include "frame-base.h"
30#include "frame-unwind.h"
d55e5aa6
TT		 31#include "inferior.h"
32#include "infrun.h"
4de283e4
TT		 33#include "gdbcmd.h"
34#include "gdbcore.h"
c4f35dd8 35#include "objfiles.h"
53e95fcf 36#include "regcache.h"
2c261fae 37#include "regset.h"
53e95fcf 38#include "symfile.h"
4de283e4
TT		 39#include "disasm.h"
40#include "amd64-tdep.h"
41#include "i387-tdep.h"
268a13a5 42#include "gdbsupport/x86-xstate.h"
4de283e4 43#include <algorithm>
22916b07 44#include "target-descriptions.h"
4de283e4
TT		 45#include "arch/amd64.h"
46#include "producer.h"
47#include "ax.h"
48#include "ax-gdb.h"
268a13a5 49#include "gdbsupport/byte-vector.h"
4de283e4 50#include "osabi.h"
1d509aa6 51#include "x86-tdep.h"
6710bf39 52
e53bef9f
MK		 53/* Note that the AMD64 architecture was previously known as x86-64.
54 The latter is (forever) engraved into the canonical system name as
90f90721 55 returned by config.guess, and used as the name for the AMD64 port
e53bef9f
MK		 56 of GNU/Linux. The BSD's have renamed their ports to amd64; they
57 don't like to shout. For GDB we prefer the amd64_-prefix over the
58 x86_64_-prefix since it's so much easier to type. */
59
402ecd56 60/* Register information. */
c4f35dd8 61
6707b003 62static const char *amd64_register_names[] =
de220d0f 63{
6707b003 64 "rax", "rbx", "rcx", "rdx", "rsi", "rdi", "rbp", "rsp",
c4f35dd8
MK		 65
66 /* %r8 is indeed register number 8. */
6707b003
UW		 67 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
68 "rip", "eflags", "cs", "ss", "ds", "es", "fs", "gs",
c4f35dd8 69
af233647 70 /* %st0 is register number 24. */
6707b003
UW		 71 "st0", "st1", "st2", "st3", "st4", "st5", "st6", "st7",
72 "fctrl", "fstat", "ftag", "fiseg", "fioff", "foseg", "fooff", "fop",
c4f35dd8 73
af233647 74 /* %xmm0 is register number 40. */
6707b003
UW		 75 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7",
76 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15",
77 "mxcsr",
0e04a514
ML		 78};
79
a055a187
L		 80static const char *amd64_ymm_names[] =
81{
82 "ymm0", "ymm1", "ymm2", "ymm3",
83 "ymm4", "ymm5", "ymm6", "ymm7",
84 "ymm8", "ymm9", "ymm10", "ymm11",
85 "ymm12", "ymm13", "ymm14", "ymm15"
86};
87
01f9f808
MS		 88static const char *amd64_ymm_avx512_names[] =
89{
90 "ymm16", "ymm17", "ymm18", "ymm19",
91 "ymm20", "ymm21", "ymm22", "ymm23",
92 "ymm24", "ymm25", "ymm26", "ymm27",
93 "ymm28", "ymm29", "ymm30", "ymm31"
94};
95
a055a187
L		 96static const char *amd64_ymmh_names[] =
97{
98 "ymm0h", "ymm1h", "ymm2h", "ymm3h",
99 "ymm4h", "ymm5h", "ymm6h", "ymm7h",
100 "ymm8h", "ymm9h", "ymm10h", "ymm11h",
101 "ymm12h", "ymm13h", "ymm14h", "ymm15h"
102};
de220d0f 103
01f9f808
MS		 104static const char *amd64_ymmh_avx512_names[] =
105{
106 "ymm16h", "ymm17h", "ymm18h", "ymm19h",
107 "ymm20h", "ymm21h", "ymm22h", "ymm23h",
108 "ymm24h", "ymm25h", "ymm26h", "ymm27h",
109 "ymm28h", "ymm29h", "ymm30h", "ymm31h"
110};
111
e43e105e
WT		 112static const char *amd64_mpx_names[] =
113{
114 "bnd0raw", "bnd1raw", "bnd2raw", "bnd3raw", "bndcfgu", "bndstatus"
115};
116
01f9f808
MS		 117static const char *amd64_k_names[] =
118{
119 "k0", "k1", "k2", "k3",
120 "k4", "k5", "k6", "k7"
121};
122
123static const char *amd64_zmmh_names[] =
124{
125 "zmm0h", "zmm1h", "zmm2h", "zmm3h",
126 "zmm4h", "zmm5h", "zmm6h", "zmm7h",
127 "zmm8h", "zmm9h", "zmm10h", "zmm11h",
128 "zmm12h", "zmm13h", "zmm14h", "zmm15h",
129 "zmm16h", "zmm17h", "zmm18h", "zmm19h",
130 "zmm20h", "zmm21h", "zmm22h", "zmm23h",
131 "zmm24h", "zmm25h", "zmm26h", "zmm27h",
132 "zmm28h", "zmm29h", "zmm30h", "zmm31h"
133};
134
135static const char *amd64_zmm_names[] =
136{
137 "zmm0", "zmm1", "zmm2", "zmm3",
138 "zmm4", "zmm5", "zmm6", "zmm7",
139 "zmm8", "zmm9", "zmm10", "zmm11",
140 "zmm12", "zmm13", "zmm14", "zmm15",
141 "zmm16", "zmm17", "zmm18", "zmm19",
142 "zmm20", "zmm21", "zmm22", "zmm23",
143 "zmm24", "zmm25", "zmm26", "zmm27",
144 "zmm28", "zmm29", "zmm30", "zmm31"
145};
146
147static const char *amd64_xmm_avx512_names[] = {
148 "xmm16", "xmm17", "xmm18", "xmm19",
149 "xmm20", "xmm21", "xmm22", "xmm23",
150 "xmm24", "xmm25", "xmm26", "xmm27",
151 "xmm28", "xmm29", "xmm30", "xmm31"
152};
153
51547df6
MS		 154static const char *amd64_pkeys_names[] = {
155 "pkru"
156};
157
c4f35dd8
MK		 158/* DWARF Register Number Mapping as defined in the System V psABI,
159 section 3.6. */
53e95fcf 160
e53bef9f 161static int amd64_dwarf_regmap[] =
0e04a514 162{
c4f35dd8 163 /* General Purpose Registers RAX, RDX, RCX, RBX, RSI, RDI. */
90f90721
MK		 164 AMD64_RAX_REGNUM, AMD64_RDX_REGNUM,
165 AMD64_RCX_REGNUM, AMD64_RBX_REGNUM,
166 AMD64_RSI_REGNUM, AMD64_RDI_REGNUM,
c4f35dd8
MK		 167
168 /* Frame Pointer Register RBP. */
90f90721 169 AMD64_RBP_REGNUM,
c4f35dd8
MK		 170
171 /* Stack Pointer Register RSP. */
90f90721 172 AMD64_RSP_REGNUM,
c4f35dd8
MK		 173
174 /* Extended Integer Registers 8 - 15. */
5b856f36
PM		 175 AMD64_R8_REGNUM, /* %r8 */
176 AMD64_R9_REGNUM, /* %r9 */
177 AMD64_R10_REGNUM, /* %r10 */
178 AMD64_R11_REGNUM, /* %r11 */
179 AMD64_R12_REGNUM, /* %r12 */
180 AMD64_R13_REGNUM, /* %r13 */
181 AMD64_R14_REGNUM, /* %r14 */
182 AMD64_R15_REGNUM, /* %r15 */
c4f35dd8 183
59207364 184 /* Return Address RA. Mapped to RIP. */
90f90721 185 AMD64_RIP_REGNUM,
c4f35dd8
MK		 186
187 /* SSE Registers 0 - 7. */
90f90721
MK		 188 AMD64_XMM0_REGNUM + 0, AMD64_XMM1_REGNUM,
189 AMD64_XMM0_REGNUM + 2, AMD64_XMM0_REGNUM + 3,
190 AMD64_XMM0_REGNUM + 4, AMD64_XMM0_REGNUM + 5,
191 AMD64_XMM0_REGNUM + 6, AMD64_XMM0_REGNUM + 7,
c4f35dd8
MK		 192
193 /* Extended SSE Registers 8 - 15. */
90f90721
MK		 194 AMD64_XMM0_REGNUM + 8, AMD64_XMM0_REGNUM + 9,
195 AMD64_XMM0_REGNUM + 10, AMD64_XMM0_REGNUM + 11,
196 AMD64_XMM0_REGNUM + 12, AMD64_XMM0_REGNUM + 13,
197 AMD64_XMM0_REGNUM + 14, AMD64_XMM0_REGNUM + 15,
c4f35dd8
MK		 198
199 /* Floating Point Registers 0-7. */
90f90721
MK		 200 AMD64_ST0_REGNUM + 0, AMD64_ST0_REGNUM + 1,
201 AMD64_ST0_REGNUM + 2, AMD64_ST0_REGNUM + 3,
202 AMD64_ST0_REGNUM + 4, AMD64_ST0_REGNUM + 5,
c6f4c129 203 AMD64_ST0_REGNUM + 6, AMD64_ST0_REGNUM + 7,
f7ca3fcf
PM		 204
205 /* MMX Registers 0 - 7.
206 We have to handle those registers specifically, as their register
207 number within GDB depends on the target (or they may even not be
208 available at all). */
209 -1, -1, -1, -1, -1, -1, -1, -1,
210
c6f4c129
JB		 211 /* Control and Status Flags Register. */
212 AMD64_EFLAGS_REGNUM,
213
214 /* Selector Registers. */
215 AMD64_ES_REGNUM,
216 AMD64_CS_REGNUM,
217 AMD64_SS_REGNUM,
218 AMD64_DS_REGNUM,
219 AMD64_FS_REGNUM,
220 AMD64_GS_REGNUM,
221 -1,
222 -1,
223
224 /* Segment Base Address Registers. */
225 -1,
226 -1,
227 -1,
228 -1,
229
230 /* Special Selector Registers. */
231 -1,
232 -1,
233
234 /* Floating Point Control Registers. */
235 AMD64_MXCSR_REGNUM,
236 AMD64_FCTRL_REGNUM,
237 AMD64_FSTAT_REGNUM
c4f35dd8 238};
0e04a514 239
e53bef9f
MK		 240static const int amd64_dwarf_regmap_len =
241 (sizeof (amd64_dwarf_regmap) / sizeof (amd64_dwarf_regmap[0]));
0e04a514 242
c4f35dd8
MK		 243/* Convert DWARF register number REG to the appropriate register
244 number used by GDB. */
26abbdc4 245
c4f35dd8 246static int
d3f73121 247amd64_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg)
53e95fcf 248{
a055a187
L		 249 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
250 int ymm0_regnum = tdep->ymm0_regnum;
c4f35dd8 251 int regnum = -1;
53e95fcf 252
16aff9a6 253 if (reg >= 0 && reg < amd64_dwarf_regmap_len)
e53bef9f 254 regnum = amd64_dwarf_regmap[reg];
53e95fcf 255
0fde2c53 256 if (ymm0_regnum >= 0
a055a187
L		 257 && i386_xmm_regnum_p (gdbarch, regnum))
258 regnum += ymm0_regnum - I387_XMM0_REGNUM (tdep);
c4f35dd8
MK		 259
260 return regnum;
53e95fcf 261}
d532c08f 262
35669430
DE		 263/* Map architectural register numbers to gdb register numbers. */
264
265static const int amd64_arch_regmap[16] =
266{
267 AMD64_RAX_REGNUM, /* %rax */
268 AMD64_RCX_REGNUM, /* %rcx */
269 AMD64_RDX_REGNUM, /* %rdx */
270 AMD64_RBX_REGNUM, /* %rbx */
271 AMD64_RSP_REGNUM, /* %rsp */
272 AMD64_RBP_REGNUM, /* %rbp */
273 AMD64_RSI_REGNUM, /* %rsi */
274 AMD64_RDI_REGNUM, /* %rdi */
275 AMD64_R8_REGNUM, /* %r8 */
276 AMD64_R9_REGNUM, /* %r9 */
277 AMD64_R10_REGNUM, /* %r10 */
278 AMD64_R11_REGNUM, /* %r11 */
279 AMD64_R12_REGNUM, /* %r12 */
280 AMD64_R13_REGNUM, /* %r13 */
281 AMD64_R14_REGNUM, /* %r14 */
282 AMD64_R15_REGNUM /* %r15 */
283};
284
285static const int amd64_arch_regmap_len =
286 (sizeof (amd64_arch_regmap) / sizeof (amd64_arch_regmap[0]));
287
288/* Convert architectural register number REG to the appropriate register
289 number used by GDB. */
290
291static int
292amd64_arch_reg_to_regnum (int reg)
293{
294 gdb_assert (reg >= 0 && reg < amd64_arch_regmap_len);
295
296 return amd64_arch_regmap[reg];
297}
298
1ba53b71
L		 299/* Register names for byte pseudo-registers. */
300
301static const char *amd64_byte_names[] =
302{
303 "al", "bl", "cl", "dl", "sil", "dil", "bpl", "spl",
fe01d668
L		 304 "r8l", "r9l", "r10l", "r11l", "r12l", "r13l", "r14l", "r15l",
305 "ah", "bh", "ch", "dh"
1ba53b71
L		 306};
307
fe01d668
L		 308/* Number of lower byte registers. */
309#define AMD64_NUM_LOWER_BYTE_REGS 16
310
1ba53b71
L		 311/* Register names for word pseudo-registers. */
312
313static const char *amd64_word_names[] =
314{
9cad29ac 315 "ax", "bx", "cx", "dx", "si", "di", "bp", "",
1ba53b71
L		 316 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
317};
318
319/* Register names for dword pseudo-registers. */
320
321static const char *amd64_dword_names[] =
322{
323 "eax", "ebx", "ecx", "edx", "esi", "edi", "ebp", "esp",
fff4548b
MK		 324 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d",
325 "eip"
1ba53b71
L		 326};
327
328/* Return the name of register REGNUM. */
329
330static const char *
331amd64_pseudo_register_name (struct gdbarch *gdbarch, int regnum)
332{
333 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
334 if (i386_byte_regnum_p (gdbarch, regnum))
335 return amd64_byte_names[regnum - tdep->al_regnum];
01f9f808
MS		 336 else if (i386_zmm_regnum_p (gdbarch, regnum))
337 return amd64_zmm_names[regnum - tdep->zmm0_regnum];
a055a187
L		 338 else if (i386_ymm_regnum_p (gdbarch, regnum))
339 return amd64_ymm_names[regnum - tdep->ymm0_regnum];
01f9f808
MS		 340 else if (i386_ymm_avx512_regnum_p (gdbarch, regnum))
341 return amd64_ymm_avx512_names[regnum - tdep->ymm16_regnum];
1ba53b71
L		 342 else if (i386_word_regnum_p (gdbarch, regnum))
343 return amd64_word_names[regnum - tdep->ax_regnum];
344 else if (i386_dword_regnum_p (gdbarch, regnum))
345 return amd64_dword_names[regnum - tdep->eax_regnum];
346 else
347 return i386_pseudo_register_name (gdbarch, regnum);
348}
349
3543a589
TT		 350static struct value *
351amd64_pseudo_register_read_value (struct gdbarch *gdbarch,
849d0ba8 352 readable_regcache *regcache,
3543a589 353 int regnum)
1ba53b71 354{
1ba53b71 355 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3543a589 356
925047fe 357 value *result_value = allocate_value (register_type (gdbarch, regnum));
3543a589
TT		 358 VALUE_LVAL (result_value) = lval_register;
359 VALUE_REGNUM (result_value) = regnum;
925047fe 360 gdb_byte *buf = value_contents_raw (result_value);
1ba53b71
L		 361
362 if (i386_byte_regnum_p (gdbarch, regnum))
363 {
364 int gpnum = regnum - tdep->al_regnum;
365
366 /* Extract (always little endian). */
fe01d668
L		 367 if (gpnum >= AMD64_NUM_LOWER_BYTE_REGS)
368 {
925047fe
SM		 369 gpnum -= AMD64_NUM_LOWER_BYTE_REGS;
370 gdb_byte raw_buf[register_size (gdbarch, gpnum)];
371
fe01d668 372 /* Special handling for AH, BH, CH, DH. */
925047fe 373 register_status status = regcache->raw_read (gpnum, raw_buf);
05d1431c
PA		 374 if (status == REG_VALID)
375 memcpy (buf, raw_buf + 1, 1);
3543a589
TT		 376 else
377 mark_value_bytes_unavailable (result_value, 0,
378 TYPE_LENGTH (value_type (result_value)));
fe01d668
L		 379 }
380 else
381 {
925047fe
SM		 382 gdb_byte raw_buf[register_size (gdbarch, gpnum)];
383 register_status status = regcache->raw_read (gpnum, raw_buf);
05d1431c
PA		 384 if (status == REG_VALID)
385 memcpy (buf, raw_buf, 1);
3543a589
TT		 386 else
387 mark_value_bytes_unavailable (result_value, 0,
388 TYPE_LENGTH (value_type (result_value)));
fe01d668 389 }
1ba53b71
L		 390 }
391 else if (i386_dword_regnum_p (gdbarch, regnum))
392 {
393 int gpnum = regnum - tdep->eax_regnum;
925047fe 394 gdb_byte raw_buf[register_size (gdbarch, gpnum)];
1ba53b71 395 /* Extract (always little endian). */
925047fe 396 register_status status = regcache->raw_read (gpnum, raw_buf);
05d1431c
PA		 397 if (status == REG_VALID)
398 memcpy (buf, raw_buf, 4);
3543a589
TT		 399 else
400 mark_value_bytes_unavailable (result_value, 0,
401 TYPE_LENGTH (value_type (result_value)));
1ba53b71
L		 402 }
403 else
3543a589
TT		 404 i386_pseudo_register_read_into_value (gdbarch, regcache, regnum,
405 result_value);
406
407 return result_value;
1ba53b71
L		 408}
409
410static void
411amd64_pseudo_register_write (struct gdbarch *gdbarch,
412 struct regcache *regcache,
413 int regnum, const gdb_byte *buf)
414{
1ba53b71
L		 415 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
416
417 if (i386_byte_regnum_p (gdbarch, regnum))
418 {
419 int gpnum = regnum - tdep->al_regnum;
420
fe01d668
L		 421 if (gpnum >= AMD64_NUM_LOWER_BYTE_REGS)
422 {
925047fe
SM		 423 gpnum -= AMD64_NUM_LOWER_BYTE_REGS;
424 gdb_byte raw_buf[register_size (gdbarch, gpnum)];
425
fe01d668 426 /* Read ... AH, BH, CH, DH. */
925047fe 427 regcache->raw_read (gpnum, raw_buf);
fe01d668
L		 428 /* ... Modify ... (always little endian). */
429 memcpy (raw_buf + 1, buf, 1);
430 /* ... Write. */
925047fe 431 regcache->raw_write (gpnum, raw_buf);
fe01d668
L		 432 }
433 else
434 {
925047fe
SM		 435 gdb_byte raw_buf[register_size (gdbarch, gpnum)];
436
fe01d668 437 /* Read ... */
0b883586 438 regcache->raw_read (gpnum, raw_buf);
fe01d668
L		 439 /* ... Modify ... (always little endian). */
440 memcpy (raw_buf, buf, 1);
441 /* ... Write. */
10eaee5f 442 regcache->raw_write (gpnum, raw_buf);
fe01d668 443 }
1ba53b71
L		 444 }
445 else if (i386_dword_regnum_p (gdbarch, regnum))
446 {
447 int gpnum = regnum - tdep->eax_regnum;
925047fe 448 gdb_byte raw_buf[register_size (gdbarch, gpnum)];
1ba53b71
L		 449
450 /* Read ... */
0b883586 451 regcache->raw_read (gpnum, raw_buf);
1ba53b71
L		 452 /* ... Modify ... (always little endian). */
453 memcpy (raw_buf, buf, 4);
454 /* ... Write. */
10eaee5f 455 regcache->raw_write (gpnum, raw_buf);
1ba53b71
L		 456 }
457 else
458 i386_pseudo_register_write (gdbarch, regcache, regnum, buf);
459}
460
62e5fd57
MK		 461/* Implement the 'ax_pseudo_register_collect' gdbarch method. */
462
463static int
464amd64_ax_pseudo_register_collect (struct gdbarch *gdbarch,
465 struct agent_expr *ax, int regnum)
466{
467 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
468
469 if (i386_byte_regnum_p (gdbarch, regnum))
470 {
471 int gpnum = regnum - tdep->al_regnum;
472
473 if (gpnum >= AMD64_NUM_LOWER_BYTE_REGS)
474 ax_reg_mask (ax, gpnum - AMD64_NUM_LOWER_BYTE_REGS);
475 else
476 ax_reg_mask (ax, gpnum);
477 return 0;
478 }
479 else if (i386_dword_regnum_p (gdbarch, regnum))
480 {
481 int gpnum = regnum - tdep->eax_regnum;
482
483 ax_reg_mask (ax, gpnum);
484 return 0;
485 }
486 else
487 return i386_ax_pseudo_register_collect (gdbarch, ax, regnum);
488}
489
53e95fcf
JS		 490\f
491
bf4d6c1c
JB		 492/* Register classes as defined in the psABI. */
493
494enum amd64_reg_class
495{
496 AMD64_INTEGER,
497 AMD64_SSE,
498 AMD64_SSEUP,
499 AMD64_X87,
500 AMD64_X87UP,
501 AMD64_COMPLEX_X87,
502 AMD64_NO_CLASS,
503 AMD64_MEMORY
504};
505
efb1c01c
MK		 506/* Return the union class of CLASS1 and CLASS2. See the psABI for
507 details. */
508
509static enum amd64_reg_class
510amd64_merge_classes (enum amd64_reg_class class1, enum amd64_reg_class class2)
511{
512 /* Rule (a): If both classes are equal, this is the resulting class. */
513 if (class1 == class2)
514 return class1;
515
516 /* Rule (b): If one of the classes is NO_CLASS, the resulting class
517 is the other class. */
518 if (class1 == AMD64_NO_CLASS)
519 return class2;
520 if (class2 == AMD64_NO_CLASS)
521 return class1;
522
523 /* Rule (c): If one of the classes is MEMORY, the result is MEMORY. */
524 if (class1 == AMD64_MEMORY || class2 == AMD64_MEMORY)
525 return AMD64_MEMORY;
526
527 /* Rule (d): If one of the classes is INTEGER, the result is INTEGER. */
528 if (class1 == AMD64_INTEGER || class2 == AMD64_INTEGER)
529 return AMD64_INTEGER;
530
531 /* Rule (e): If one of the classes is X87, X87UP, COMPLEX_X87 class,
532 MEMORY is used as class. */
533 if (class1 == AMD64_X87 || class1 == AMD64_X87UP
534 || class1 == AMD64_COMPLEX_X87 || class2 == AMD64_X87
535 || class2 == AMD64_X87UP || class2 == AMD64_COMPLEX_X87)
536 return AMD64_MEMORY;
537
538 /* Rule (f): Otherwise class SSE is used. */
539 return AMD64_SSE;
540}
541
fe978cb0 542static void amd64_classify (struct type *type, enum amd64_reg_class theclass[2]);
bf4d6c1c 543
4aa866af 544/* Return true if TYPE is a structure or union with unaligned fields. */
79b1ab3d 545
4aa866af
LS		 546static bool
547amd64_has_unaligned_fields (struct type *type)
79b1ab3d 548{
4aa866af
LS		 549 if (TYPE_CODE (type) == TYPE_CODE_STRUCT
550 || TYPE_CODE (type) == TYPE_CODE_UNION)
551 {
552 for (int i = 0; i < TYPE_NFIELDS (type); i++)
553 {
554 struct type *subtype = check_typedef (TYPE_FIELD_TYPE (type, i));
555 int bitpos = TYPE_FIELD_BITPOS (type, i);
556 int align = type_align(subtype);
557
a59240a4
TT		 558 /* Ignore static fields, empty fields (for example nested
559 empty structures), and bitfields (these are handled by
560 the caller). */
4aa866af
LS		 561 if (field_is_static (&TYPE_FIELD (type, i))
562 || (TYPE_FIELD_BITSIZE (type, i) == 0
a59240a4
TT		 563 && TYPE_LENGTH (subtype) == 0)
564 || TYPE_FIELD_PACKED (type, i))
4aa866af
LS		 565 continue;
566
567 if (bitpos % 8 != 0)
568 return true;
569
570 int bytepos = bitpos / 8;
571 if (bytepos % align != 0)
572 return true;
573
a59240a4 574 if (amd64_has_unaligned_fields (subtype))
4aa866af
LS		 575 return true;
576 }
577 }
79b1ab3d 578
4aa866af 579 return false;
79b1ab3d
MK		 580}
581
d10eccaa
TV		 582/* Classify field I of TYPE starting at BITOFFSET according to the rules for
583 structures and union types, and store the result in THECLASS. */
584
585static void
586amd64_classify_aggregate_field (struct type *type, int i,
587 enum amd64_reg_class theclass[2],
588 unsigned int bitoffset)
589{
590 struct type *subtype = check_typedef (TYPE_FIELD_TYPE (type, i));
591 int bitpos = bitoffset + TYPE_FIELD_BITPOS (type, i);
592 int pos = bitpos / 64;
593 enum amd64_reg_class subclass[2];
594 int bitsize = TYPE_FIELD_BITSIZE (type, i);
595 int endpos;
596
597 if (bitsize == 0)
598 bitsize = TYPE_LENGTH (subtype) * 8;
599 endpos = (bitpos + bitsize - 1) / 64;
600
601 /* Ignore static fields, or empty fields, for example nested
602 empty structures.*/
603 if (field_is_static (&TYPE_FIELD (type, i)) || bitsize == 0)
604 return;
605
606 if (TYPE_CODE (subtype) == TYPE_CODE_STRUCT
607 || TYPE_CODE (subtype) == TYPE_CODE_UNION)
608 {
609 /* Each field of an object is classified recursively. */
610 int j;
611 for (j = 0; j < TYPE_NFIELDS (subtype); j++)
612 amd64_classify_aggregate_field (subtype, j, theclass, bitpos);
613 return;
614 }
615
616 gdb_assert (pos == 0 || pos == 1);
617
618 amd64_classify (subtype, subclass);
619 theclass[pos] = amd64_merge_classes (theclass[pos], subclass[0]);
620 if (bitsize <= 64 && pos == 0 && endpos == 1)
621 /* This is a bit of an odd case: We have a field that would
622 normally fit in one of the two eightbytes, except that
623 it is placed in a way that this field straddles them.
624 This has been seen with a structure containing an array.
625
626 The ABI is a bit unclear in this case, but we assume that
627 this field's class (stored in subclass[0]) must also be merged
628 into class[1]. In other words, our field has a piece stored
629 in the second eight-byte, and thus its class applies to
630 the second eight-byte as well.
631
632 In the case where the field length exceeds 8 bytes,
633 it should not be necessary to merge the field class
634 into class[1]. As LEN > 8, subclass[1] is necessarily
635 different from AMD64_NO_CLASS. If subclass[1] is equal
636 to subclass[0], then the normal class[1]/subclass[1]
637 merging will take care of everything. For subclass[1]
638 to be different from subclass[0], I can only see the case
639 where we have a SSE/SSEUP or X87/X87UP pair, which both
640 use up all 16 bytes of the aggregate, and are already
641 handled just fine (because each portion sits on its own
642 8-byte). */
643 theclass[1] = amd64_merge_classes (theclass[1], subclass[0]);
644 if (pos == 0)
645 theclass[1] = amd64_merge_classes (theclass[1], subclass[1]);
646}
647
efb1c01c
MK		 648/* Classify TYPE according to the rules for aggregate (structures and
649 arrays) and union types, and store the result in CLASS. */
c4f35dd8
MK		 650
651static void
fe978cb0 652amd64_classify_aggregate (struct type *type, enum amd64_reg_class theclass[2])
53e95fcf 653{
4aa866af 654 /* 1. If the size of an object is larger than two eightbytes, or it has
efb1c01c 655 unaligned fields, it has class memory. */
4aa866af 656 if (TYPE_LENGTH (type) > 16 || amd64_has_unaligned_fields (type))
53e95fcf 657 {
fe978cb0 658 theclass[0] = theclass[1] = AMD64_MEMORY;
efb1c01c 659 return;
53e95fcf 660 }
efb1c01c
MK		 661
662 /* 2. Both eightbytes get initialized to class NO_CLASS. */
fe978cb0 663 theclass[0] = theclass[1] = AMD64_NO_CLASS;
efb1c01c
MK		 664
665 /* 3. Each field of an object is classified recursively so that
666 always two fields are considered. The resulting class is
667 calculated according to the classes of the fields in the
668 eightbyte: */
669
670 if (TYPE_CODE (type) == TYPE_CODE_ARRAY)
8ffd9b1b 671 {
efb1c01c
MK		 672 struct type *subtype = check_typedef (TYPE_TARGET_TYPE (type));
673
674 /* All fields in an array have the same type. */
fe978cb0
PA		 675 amd64_classify (subtype, theclass);
676 if (TYPE_LENGTH (type) > 8 && theclass[1] == AMD64_NO_CLASS)
677 theclass[1] = theclass[0];
8ffd9b1b 678 }
53e95fcf
JS		 679 else
680 {
efb1c01c 681 int i;
53e95fcf 682
efb1c01c
MK		 683 /* Structure or union. */
684 gdb_assert (TYPE_CODE (type) == TYPE_CODE_STRUCT
685 || TYPE_CODE (type) == TYPE_CODE_UNION);
686
687 for (i = 0; i < TYPE_NFIELDS (type); i++)
d10eccaa 688 amd64_classify_aggregate_field (type, i, theclass, 0);
53e95fcf 689 }
efb1c01c
MK		 690
691 /* 4. Then a post merger cleanup is done: */
692
693 /* Rule (a): If one of the classes is MEMORY, the whole argument is
694 passed in memory. */
fe978cb0
PA		 695 if (theclass[0] == AMD64_MEMORY || theclass[1] == AMD64_MEMORY)
696 theclass[0] = theclass[1] = AMD64_MEMORY;
efb1c01c 697
177b42fe 698 /* Rule (b): If SSEUP is not preceded by SSE, it is converted to
efb1c01c 699 SSE. */
fe978cb0
PA		 700 if (theclass[0] == AMD64_SSEUP)
701 theclass[0] = AMD64_SSE;
702 if (theclass[1] == AMD64_SSEUP && theclass[0] != AMD64_SSE)
703 theclass[1] = AMD64_SSE;
efb1c01c
MK		 704}
705
706/* Classify TYPE, and store the result in CLASS. */
707
bf4d6c1c 708static void
fe978cb0 709amd64_classify (struct type *type, enum amd64_reg_class theclass[2])
efb1c01c
MK		 710{
711 enum type_code code = TYPE_CODE (type);
712 int len = TYPE_LENGTH (type);
713
fe978cb0 714 theclass[0] = theclass[1] = AMD64_NO_CLASS;
efb1c01c
MK		 715
716 /* Arguments of types (signed and unsigned) _Bool, char, short, int,
5a7225ed
JB		 717 long, long long, and pointers are in the INTEGER class. Similarly,
718 range types, used by languages such as Ada, are also in the INTEGER
719 class. */
efb1c01c 720 if ((code == TYPE_CODE_INT || code == TYPE_CODE_ENUM
b929c77f 721 || code == TYPE_CODE_BOOL || code == TYPE_CODE_RANGE
9db13498 722 || code == TYPE_CODE_CHAR
aa006118 723 || code == TYPE_CODE_PTR || TYPE_IS_REFERENCE (type))
efb1c01c 724 && (len == 1 || len == 2 || len == 4 || len == 8))
fe978cb0 725 theclass[0] = AMD64_INTEGER;
efb1c01c 726
5daa78cc
TJB		 727 /* Arguments of types float, double, _Decimal32, _Decimal64 and __m64
728 are in class SSE. */
729 else if ((code == TYPE_CODE_FLT || code == TYPE_CODE_DECFLOAT)
730 && (len == 4 || len == 8))
efb1c01c 731 /* FIXME: __m64 . */
fe978cb0 732 theclass[0] = AMD64_SSE;
efb1c01c 733
5daa78cc
TJB		 734 /* Arguments of types __float128, _Decimal128 and __m128 are split into
735 two halves. The least significant ones belong to class SSE, the most
efb1c01c 736 significant one to class SSEUP. */
5daa78cc
TJB		 737 else if (code == TYPE_CODE_DECFLOAT && len == 16)
738 /* FIXME: __float128, __m128. */
fe978cb0 739 theclass[0] = AMD64_SSE, theclass[1] = AMD64_SSEUP;
efb1c01c
MK		 740
741 /* The 64-bit mantissa of arguments of type long double belongs to
742 class X87, the 16-bit exponent plus 6 bytes of padding belongs to
743 class X87UP. */
744 else if (code == TYPE_CODE_FLT && len == 16)
745 /* Class X87 and X87UP. */
fe978cb0 746 theclass[0] = AMD64_X87, theclass[1] = AMD64_X87UP;
efb1c01c 747
7f7930dd
MK		 748 /* Arguments of complex T where T is one of the types float or
749 double get treated as if they are implemented as:
750
751 struct complexT {
752 T real;
753 T imag;
5f52445b
YQ		 754 };
755
756 */
7f7930dd 757 else if (code == TYPE_CODE_COMPLEX && len == 8)
fe978cb0 758 theclass[0] = AMD64_SSE;
7f7930dd 759 else if (code == TYPE_CODE_COMPLEX && len == 16)
fe978cb0 760 theclass[0] = theclass[1] = AMD64_SSE;
7f7930dd
MK		 761
762 /* A variable of type complex long double is classified as type
763 COMPLEX_X87. */
764 else if (code == TYPE_CODE_COMPLEX && len == 32)
fe978cb0 765 theclass[0] = AMD64_COMPLEX_X87;
7f7930dd 766
efb1c01c
MK		 767 /* Aggregates. */
768 else if (code == TYPE_CODE_ARRAY || code == TYPE_CODE_STRUCT
769 || code == TYPE_CODE_UNION)
fe978cb0 770 amd64_classify_aggregate (type, theclass);
efb1c01c
MK		 771}
772
773static enum return_value_convention
6a3a010b 774amd64_return_value (struct gdbarch *gdbarch, struct value *function,
c055b101 775 struct type *type, struct regcache *regcache,
42835c2b 776 gdb_byte *readbuf, const gdb_byte *writebuf)
efb1c01c 777{
fe978cb0 778 enum amd64_reg_class theclass[2];
efb1c01c 779 int len = TYPE_LENGTH (type);
90f90721
MK		 780 static int integer_regnum[] = { AMD64_RAX_REGNUM, AMD64_RDX_REGNUM };
781 static int sse_regnum[] = { AMD64_XMM0_REGNUM, AMD64_XMM1_REGNUM };
efb1c01c
MK		 782 int integer_reg = 0;
783 int sse_reg = 0;
784 int i;
785
786 gdb_assert (!(readbuf && writebuf));
787
788 /* 1. Classify the return type with the classification algorithm. */
fe978cb0 789 amd64_classify (type, theclass);
efb1c01c
MK		 790
791 /* 2. If the type has class MEMORY, then the caller provides space
6fa57a7d 792 for the return value and passes the address of this storage in
0963b4bd 793 %rdi as if it were the first argument to the function. In effect,
6fa57a7d
MK		 794 this address becomes a hidden first argument.
795
796 On return %rax will contain the address that has been passed in
797 by the caller in %rdi. */
fe978cb0 798 if (theclass[0] == AMD64_MEMORY)
6fa57a7d
MK		 799 {
800 /* As indicated by the comment above, the ABI guarantees that we
801 can always find the return value just after the function has
802 returned. */
803
804 if (readbuf)
805 {
806 ULONGEST addr;
807
808 regcache_raw_read_unsigned (regcache, AMD64_RAX_REGNUM, &addr);
809 read_memory (addr, readbuf, TYPE_LENGTH (type));
810 }
811
812 return RETURN_VALUE_ABI_RETURNS_ADDRESS;
813 }
efb1c01c 814
7f7930dd
MK		 815 /* 8. If the class is COMPLEX_X87, the real part of the value is
816 returned in %st0 and the imaginary part in %st1. */
fe978cb0 817 if (theclass[0] == AMD64_COMPLEX_X87)
7f7930dd
MK		 818 {
819 if (readbuf)
820 {
0b883586
SM		 821 regcache->raw_read (AMD64_ST0_REGNUM, readbuf);
822 regcache->raw_read (AMD64_ST1_REGNUM, readbuf + 16);
7f7930dd
MK		 823 }
824
825 if (writebuf)
826 {
827 i387_return_value (gdbarch, regcache);
10eaee5f
SM		 828 regcache->raw_write (AMD64_ST0_REGNUM, writebuf);
829 regcache->raw_write (AMD64_ST1_REGNUM, writebuf + 16);
7f7930dd
MK		 830
831 /* Fix up the tag word such that both %st(0) and %st(1) are
832 marked as valid. */
833 regcache_raw_write_unsigned (regcache, AMD64_FTAG_REGNUM, 0xfff);
834 }
835
836 return RETURN_VALUE_REGISTER_CONVENTION;
837 }
838
fe978cb0 839 gdb_assert (theclass[1] != AMD64_MEMORY);
bad43aa5 840 gdb_assert (len <= 16);
efb1c01c
MK		 841
842 for (i = 0; len > 0; i++, len -= 8)
843 {
844 int regnum = -1;
845 int offset = 0;
846
fe978cb0 847 switch (theclass[i])
efb1c01c
MK		 848 {
849 case AMD64_INTEGER:
850 /* 3. If the class is INTEGER, the next available register
851 of the sequence %rax, %rdx is used. */
852 regnum = integer_regnum[integer_reg++];
853 break;
854
855 case AMD64_SSE:
856 /* 4. If the class is SSE, the next available SSE register
857 of the sequence %xmm0, %xmm1 is used. */
858 regnum = sse_regnum[sse_reg++];
859 break;
860
861 case AMD64_SSEUP:
862 /* 5. If the class is SSEUP, the eightbyte is passed in the
863 upper half of the last used SSE register. */
864 gdb_assert (sse_reg > 0);
865 regnum = sse_regnum[sse_reg - 1];
866 offset = 8;
867 break;
868
869 case AMD64_X87:
870 /* 6. If the class is X87, the value is returned on the X87
871 stack in %st0 as 80-bit x87 number. */
90f90721 872 regnum = AMD64_ST0_REGNUM;
efb1c01c
MK		 873 if (writebuf)
874 i387_return_value (gdbarch, regcache);
875 break;
876
877 case AMD64_X87UP:
878 /* 7. If the class is X87UP, the value is returned together
879 with the previous X87 value in %st0. */
fe978cb0 880 gdb_assert (i > 0 && theclass[0] == AMD64_X87);
90f90721 881 regnum = AMD64_ST0_REGNUM;
efb1c01c
MK		 882 offset = 8;
883 len = 2;
884 break;
885
886 case AMD64_NO_CLASS:
887 continue;
888
889 default:
890 gdb_assert (!"Unexpected register class.");
891 }
892
893 gdb_assert (regnum != -1);
894
895 if (readbuf)
502fe83e
SM		 896 regcache->raw_read_part (regnum, offset, std::min (len, 8),
897 readbuf + i * 8);
efb1c01c 898 if (writebuf)
4f0420fd
SM		 899 regcache->raw_write_part (regnum, offset, std::min (len, 8),
900 writebuf + i * 8);
efb1c01c
MK		 901 }
902
903 return RETURN_VALUE_REGISTER_CONVENTION;
53e95fcf
JS		 904}
905\f
906
720aa428 907static CORE_ADDR
cf84fa6b
AH		 908amd64_push_arguments (struct regcache *regcache, int nargs, struct value **args,
909 CORE_ADDR sp, function_call_return_method return_method)
720aa428 910{
bf4d6c1c
JB		 911 static int integer_regnum[] =
912 {
913 AMD64_RDI_REGNUM, /* %rdi */
914 AMD64_RSI_REGNUM, /* %rsi */
915 AMD64_RDX_REGNUM, /* %rdx */
916 AMD64_RCX_REGNUM, /* %rcx */
5b856f36
PM		 917 AMD64_R8_REGNUM, /* %r8 */
918 AMD64_R9_REGNUM /* %r9 */
bf4d6c1c 919 };
720aa428
MK		 920 static int sse_regnum[] =
921 {
922 /* %xmm0 ... %xmm7 */
90f90721
MK		 923 AMD64_XMM0_REGNUM + 0, AMD64_XMM1_REGNUM,
924 AMD64_XMM0_REGNUM + 2, AMD64_XMM0_REGNUM + 3,
925 AMD64_XMM0_REGNUM + 4, AMD64_XMM0_REGNUM + 5,
926 AMD64_XMM0_REGNUM + 6, AMD64_XMM0_REGNUM + 7,
720aa428 927 };
224c3ddb 928 struct value **stack_args = XALLOCAVEC (struct value *, nargs);
720aa428
MK		 929 int num_stack_args = 0;
930 int num_elements = 0;
931 int element = 0;
932 int integer_reg = 0;
933 int sse_reg = 0;
934 int i;
935
6470d250 936 /* Reserve a register for the "hidden" argument. */
cf84fa6b 937if (return_method == return_method_struct)
6470d250
MK		 938 integer_reg++;
939
720aa428
MK		 940 for (i = 0; i < nargs; i++)
941 {
4991999e 942 struct type *type = value_type (args[i]);
720aa428 943 int len = TYPE_LENGTH (type);
fe978cb0 944 enum amd64_reg_class theclass[2];
720aa428
MK		 945 int needed_integer_regs = 0;
946 int needed_sse_regs = 0;
947 int j;
948
949 /* Classify argument. */
fe978cb0 950 amd64_classify (type, theclass);
720aa428
MK		 951
952 /* Calculate the number of integer and SSE registers needed for
953 this argument. */
954 for (j = 0; j < 2; j++)
955 {
fe978cb0 956 if (theclass[j] == AMD64_INTEGER)
720aa428 957 needed_integer_regs++;
fe978cb0 958 else if (theclass[j] == AMD64_SSE)
720aa428
MK		 959 needed_sse_regs++;
960 }
961
962 /* Check whether enough registers are available, and if the
963 argument should be passed in registers at all. */
bf4d6c1c 964 if (integer_reg + needed_integer_regs > ARRAY_SIZE (integer_regnum)
720aa428
MK		 965 || sse_reg + needed_sse_regs > ARRAY_SIZE (sse_regnum)
966 || (needed_integer_regs == 0 && needed_sse_regs == 0))
967 {
968 /* The argument will be passed on the stack. */
969 num_elements += ((len + 7) / 8);
849e9755 970 stack_args[num_stack_args++] = args[i];
720aa428
MK		 971 }
972 else
973 {
974 /* The argument will be passed in registers. */
d8de1ef7
MK		 975 const gdb_byte *valbuf = value_contents (args[i]);
976 gdb_byte buf[8];
720aa428
MK		 977
978 gdb_assert (len <= 16);
979
980 for (j = 0; len > 0; j++, len -= 8)
981 {
982 int regnum = -1;
983 int offset = 0;
984
fe978cb0 985 switch (theclass[j])
720aa428
MK		 986 {
987 case AMD64_INTEGER:
bf4d6c1c 988 regnum = integer_regnum[integer_reg++];
720aa428
MK		 989 break;
990
991 case AMD64_SSE:
992 regnum = sse_regnum[sse_reg++];
993 break;
994
995 case AMD64_SSEUP:
996 gdb_assert (sse_reg > 0);
997 regnum = sse_regnum[sse_reg - 1];
998 offset = 8;
999 break;
1000
745ff14e
TV		 1001 case AMD64_NO_CLASS:
1002 continue;
1003
720aa428
MK		 1004 default:
1005 gdb_assert (!"Unexpected register class.");
1006 }
1007
1008 gdb_assert (regnum != -1);
1009 memset (buf, 0, sizeof buf);
325fac50 1010 memcpy (buf, valbuf + j * 8, std::min (len, 8));
4f0420fd 1011 regcache->raw_write_part (regnum, offset, 8, buf);
720aa428
MK		 1012 }
1013 }
1014 }
1015
1016 /* Allocate space for the arguments on the stack. */
1017 sp -= num_elements * 8;
1018
1019 /* The psABI says that "The end of the input argument area shall be
1020 aligned on a 16 byte boundary." */
1021 sp &= ~0xf;
1022
1023 /* Write out the arguments to the stack. */
1024 for (i = 0; i < num_stack_args; i++)
1025 {
4991999e 1026 struct type *type = value_type (stack_args[i]);
d8de1ef7 1027 const gdb_byte *valbuf = value_contents (stack_args[i]);
849e9755
JB		 1028 int len = TYPE_LENGTH (type);
1029
1030 write_memory (sp + element * 8, valbuf, len);
1031 element += ((len + 7) / 8);
720aa428
MK		 1032 }
1033
1034 /* The psABI says that "For calls that may call functions that use
1035 varargs or stdargs (prototype-less calls or calls to functions
1036 containing ellipsis (...) in the declaration) %al is used as
1037 hidden argument to specify the number of SSE registers used. */
90f90721 1038 regcache_raw_write_unsigned (regcache, AMD64_RAX_REGNUM, sse_reg);
720aa428
MK		 1039 return sp;
1040}
1041
c4f35dd8 1042static CORE_ADDR
7d9b040b 1043amd64_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
e53bef9f
MK		 1044 struct regcache *regcache, CORE_ADDR bp_addr,
1045 int nargs, struct value **args, CORE_ADDR sp,
cf84fa6b
AH		 1046 function_call_return_method return_method,
1047 CORE_ADDR struct_addr)
53e95fcf 1048{
e17a4113 1049 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
d8de1ef7 1050 gdb_byte buf[8];
c4f35dd8 1051
4a612d6f
WT		 1052 /* BND registers can be in arbitrary values at the moment of the
1053 inferior call. This can cause boundary violations that are not
1054 due to a real bug or even desired by the user. The best to be done
1055 is set the BND registers to allow access to the whole memory, INIT
1056 state, before pushing the inferior call. */
1057 i387_reset_bnd_regs (gdbarch, regcache);
1058
c4f35dd8 1059 /* Pass arguments. */
cf84fa6b 1060 sp = amd64_push_arguments (regcache, nargs, args, sp, return_method);
c4f35dd8
MK		 1061
1062 /* Pass "hidden" argument". */
cf84fa6b 1063 if (return_method == return_method_struct)
c4f35dd8 1064 {
e17a4113 1065 store_unsigned_integer (buf, 8, byte_order, struct_addr);
b66f5587 1066 regcache->cooked_write (AMD64_RDI_REGNUM, buf);
c4f35dd8
MK		 1067 }
1068
1069 /* Store return address. */
1070 sp -= 8;
e17a4113 1071 store_unsigned_integer (buf, 8, byte_order, bp_addr);
c4f35dd8
MK		 1072 write_memory (sp, buf, 8);
1073
1074 /* Finally, update the stack pointer... */
e17a4113 1075 store_unsigned_integer (buf, 8, byte_order, sp);
b66f5587 1076 regcache->cooked_write (AMD64_RSP_REGNUM, buf);
c4f35dd8
MK		 1077
1078 /* ...and fake a frame pointer. */
b66f5587 1079 regcache->cooked_write (AMD64_RBP_REGNUM, buf);
c4f35dd8 1080
3e210248 1081 return sp + 16;
53e95fcf 1082}
c4f35dd8 1083\f
35669430
DE		 1084/* Displaced instruction handling. */
1085
1086/* A partially decoded instruction.
1087 This contains enough details for displaced stepping purposes. */
1088
1089struct amd64_insn
1090{
1091 /* The number of opcode bytes. */
1092 int opcode_len;
50a1fdd5
PA		 1093 /* The offset of the REX/VEX instruction encoding prefix or -1 if
1094 not present. */
1095 int enc_prefix_offset;
35669430
DE		 1096 /* The offset to the first opcode byte. */
1097 int opcode_offset;
1098 /* The offset to the modrm byte or -1 if not present. */
1099 int modrm_offset;
1100
1101 /* The raw instruction. */
1102 gdb_byte *raw_insn;
1103};
1104
4a3a374c 1105struct amd64_displaced_step_copy_insn_closure : public displaced_step_copy_insn_closure
35669430 1106{
4a3a374c 1107 amd64_displaced_step_copy_insn_closure (int insn_buf_len)
cfba9872
SM		 1108 : insn_buf (insn_buf_len, 0)
1109 {}
1110
35669430 1111 /* For rip-relative insns, saved copy of the reg we use instead of %rip. */
cfba9872 1112 int tmp_used = 0;
35669430
DE		 1113 int tmp_regno;
1114 ULONGEST tmp_save;
1115
1116 /* Details of the instruction. */
1117 struct amd64_insn insn_details;
1118
cfba9872
SM		 1119 /* The possibly modified insn. */
1120 gdb::byte_vector insn_buf;
35669430
DE		 1121};
1122
b93d82bc
SM		 1123typedef std::unique_ptr<amd64_displaced_step_copy_insn_closure>
1124 amd64_displaced_step_copy_insn_closure_up;
1125
35669430
DE		 1126/* WARNING: Keep onebyte_has_modrm, twobyte_has_modrm in sync with
1127 ../opcodes/i386-dis.c (until libopcodes exports them, or an alternative,
1128 at which point delete these in favor of libopcodes' versions). */
1129
1130static const unsigned char onebyte_has_modrm[256] = {
1131 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1132 /* ------------------------------- */
1133 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
1134 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
1135 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
1136 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
1137 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
1138 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
1139 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
1140 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
1141 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
1142 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
1143 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
1144 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
1145 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
1146 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
1147 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
1148 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
1149 /* ------------------------------- */
1150 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1151};
1152
1153static const unsigned char twobyte_has_modrm[256] = {
1154 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1155 /* ------------------------------- */
1156 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
1157 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
1158 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
1159 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
1160 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
1161 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
1162 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
1163 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
1164 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
1165 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
1166 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
1167 /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
1168 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
1169 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
1170 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
1171 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */
1172 /* ------------------------------- */
1173 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1174};
1175
1176static int amd64_syscall_p (const struct amd64_insn *insn, int *lengthp);
1177
1178static int
1179rex_prefix_p (gdb_byte pfx)
1180{
1181 return REX_PREFIX_P (pfx);
1182}
1183
50a1fdd5
PA		 1184/* True if PFX is the start of the 2-byte VEX prefix. */
1185
1186static bool
1187vex2_prefix_p (gdb_byte pfx)
1188{
1189 return pfx == 0xc5;
1190}
1191
1192/* True if PFX is the start of the 3-byte VEX prefix. */
1193
1194static bool
1195vex3_prefix_p (gdb_byte pfx)
1196{
1197 return pfx == 0xc4;
1198}
1199
35669430
DE		 1200/* Skip the legacy instruction prefixes in INSN.
1201 We assume INSN is properly sentineled so we don't have to worry
1202 about falling off the end of the buffer. */
1203
1204static gdb_byte *
1903f0e6 1205amd64_skip_prefixes (gdb_byte *insn)
35669430
DE		 1206{
1207 while (1)
1208 {
1209 switch (*insn)
1210 {
1211 case DATA_PREFIX_OPCODE:
1212 case ADDR_PREFIX_OPCODE:
1213 case CS_PREFIX_OPCODE:
1214 case DS_PREFIX_OPCODE:
1215 case ES_PREFIX_OPCODE:
1216 case FS_PREFIX_OPCODE:
1217 case GS_PREFIX_OPCODE:
1218 case SS_PREFIX_OPCODE:
1219 case LOCK_PREFIX_OPCODE:
1220 case REPE_PREFIX_OPCODE:
1221 case REPNE_PREFIX_OPCODE:
1222 ++insn;
1223 continue;
1224 default:
1225 break;
1226 }
1227 break;
1228 }
1229
1230 return insn;
1231}
1232
35669430
DE		 1233/* Return an integer register (other than RSP) that is unused as an input
1234 operand in INSN.
1235 In order to not require adding a rex prefix if the insn doesn't already
1236 have one, the result is restricted to RAX ... RDI, sans RSP.
1237 The register numbering of the result follows architecture ordering,
1238 e.g. RDI = 7. */
1239
1240static int
1241amd64_get_unused_input_int_reg (const struct amd64_insn *details)
1242{
1243 /* 1 bit for each reg */
1244 int used_regs_mask = 0;
1245
1246 /* There can be at most 3 int regs used as inputs in an insn, and we have
1247 7 to choose from (RAX ... RDI, sans RSP).
1248 This allows us to take a conservative approach and keep things simple.
1249 E.g. By avoiding RAX, we don't have to specifically watch for opcodes
1250 that implicitly specify RAX. */
1251
1252 /* Avoid RAX. */
1253 used_regs_mask |= 1 << EAX_REG_NUM;
1254 /* Similarily avoid RDX, implicit operand in divides. */
1255 used_regs_mask |= 1 << EDX_REG_NUM;
1256 /* Avoid RSP. */
1257 used_regs_mask |= 1 << ESP_REG_NUM;
1258
1259 /* If the opcode is one byte long and there's no ModRM byte,
1260 assume the opcode specifies a register. */
1261 if (details->opcode_len == 1 && details->modrm_offset == -1)
1262 used_regs_mask |= 1 << (details->raw_insn[details->opcode_offset] & 7);
1263
1264 /* Mark used regs in the modrm/sib bytes. */
1265 if (details->modrm_offset != -1)
1266 {
1267 int modrm = details->raw_insn[details->modrm_offset];
1268 int mod = MODRM_MOD_FIELD (modrm);
1269 int reg = MODRM_REG_FIELD (modrm);
1270 int rm = MODRM_RM_FIELD (modrm);
1271 int have_sib = mod != 3 && rm == 4;
1272
1273 /* Assume the reg field of the modrm byte specifies a register. */
1274 used_regs_mask |= 1 << reg;
1275
1276 if (have_sib)
1277 {
1278 int base = SIB_BASE_FIELD (details->raw_insn[details->modrm_offset + 1]);
d48ebb5b 1279 int idx = SIB_INDEX_FIELD (details->raw_insn[details->modrm_offset + 1]);
35669430 1280 used_regs_mask |= 1 << base;
d48ebb5b 1281 used_regs_mask |= 1 << idx;
35669430
DE		 1282 }
1283 else
1284 {
1285 used_regs_mask |= 1 << rm;
1286 }
1287 }
1288
1289 gdb_assert (used_regs_mask < 256);
1290 gdb_assert (used_regs_mask != 255);
1291
1292 /* Finally, find a free reg. */
1293 {
1294 int i;
1295
1296 for (i = 0; i < 8; ++i)
1297 {
1298 if (! (used_regs_mask & (1 << i)))
1299 return i;
1300 }
1301
1302 /* We shouldn't get here. */
1303 internal_error (__FILE__, __LINE__, _("unable to find free reg"));
1304 }
1305}
1306
1307/* Extract the details of INSN that we need. */
1308
1309static void
1310amd64_get_insn_details (gdb_byte *insn, struct amd64_insn *details)
1311{
1312 gdb_byte *start = insn;
1313 int need_modrm;
1314
1315 details->raw_insn = insn;
1316
1317 details->opcode_len = -1;
50a1fdd5 1318 details->enc_prefix_offset = -1;
35669430
DE		 1319 details->opcode_offset = -1;
1320 details->modrm_offset = -1;
1321
1322 /* Skip legacy instruction prefixes. */
1903f0e6 1323 insn = amd64_skip_prefixes (insn);
35669430 1324
50a1fdd5 1325 /* Skip REX/VEX instruction encoding prefixes. */
35669430
DE		 1326 if (rex_prefix_p (*insn))
1327 {
50a1fdd5 1328 details->enc_prefix_offset = insn - start;
35669430
DE		 1329 ++insn;
1330 }
50a1fdd5
PA		 1331 else if (vex2_prefix_p (*insn))
1332 {
1333 /* Don't record the offset in this case because this prefix has
1334 no REX.B equivalent. */
1335 insn += 2;
1336 }
1337 else if (vex3_prefix_p (*insn))
1338 {
1339 details->enc_prefix_offset = insn - start;
1340 insn += 3;
1341 }
35669430
DE		 1342
1343 details->opcode_offset = insn - start;
1344
1345 if (*insn == TWO_BYTE_OPCODE_ESCAPE)
1346 {
1347 /* Two or three-byte opcode. */
1348 ++insn;
1349 need_modrm = twobyte_has_modrm[*insn];
1350
1351 /* Check for three-byte opcode. */
1903f0e6 1352 switch (*insn)
35669430 1353 {
1903f0e6
DE		 1354 case 0x24:
1355 case 0x25:
1356 case 0x38:
1357 case 0x3a:
1358 case 0x7a:
1359 case 0x7b:
35669430
DE		 1360 ++insn;
1361 details->opcode_len = 3;
1903f0e6
DE		 1362 break;
1363 default:
1364 details->opcode_len = 2;
1365 break;
35669430 1366 }
35669430
DE		 1367 }
1368 else
1369 {
1370 /* One-byte opcode. */
1371 need_modrm = onebyte_has_modrm[*insn];
1372 details->opcode_len = 1;
1373 }
1374
1375 if (need_modrm)
1376 {
1377 ++insn;
1378 details->modrm_offset = insn - start;
1379 }
1380}
1381
1382/* Update %rip-relative addressing in INSN.
1383
1384 %rip-relative addressing only uses a 32-bit displacement.
1385 32 bits is not enough to be guaranteed to cover the distance between where
1386 the real instruction is and where its copy is.
1387 Convert the insn to use base+disp addressing.
1388 We set base = pc + insn_length so we can leave disp unchanged. */
c4f35dd8 1389
35669430 1390static void
4a3a374c 1391fixup_riprel (struct gdbarch *gdbarch, amd64_displaced_step_copy_insn_closure *dsc,
35669430
DE		 1392 CORE_ADDR from, CORE_ADDR to, struct regcache *regs)
1393{
1394 const struct amd64_insn *insn_details = &dsc->insn_details;
1395 int modrm_offset = insn_details->modrm_offset;
1396 gdb_byte *insn = insn_details->raw_insn + modrm_offset;
1397 CORE_ADDR rip_base;
35669430
DE		 1398 int insn_length;
1399 int arch_tmp_regno, tmp_regno;
1400 ULONGEST orig_value;
1401
1402 /* %rip+disp32 addressing mode, displacement follows ModRM byte. */
1403 ++insn;
1404
1405 /* Compute the rip-relative address. */
cfba9872
SM		 1406 insn_length = gdb_buffered_insn_length (gdbarch, dsc->insn_buf.data (),
1407 dsc->insn_buf.size (), from);
35669430
DE		 1408 rip_base = from + insn_length;
1409
1410 /* We need a register to hold the address.
1411 Pick one not used in the insn.
1412 NOTE: arch_tmp_regno uses architecture ordering, e.g. RDI = 7. */
1413 arch_tmp_regno = amd64_get_unused_input_int_reg (insn_details);
1414 tmp_regno = amd64_arch_reg_to_regnum (arch_tmp_regno);
1415
50a1fdd5
PA		 1416 /* Position of the not-B bit in the 3-byte VEX prefix (in byte 1). */
1417 static constexpr gdb_byte VEX3_NOT_B = 0x20;
1418
1419 /* REX.B should be unset (VEX.!B set) as we were using rip-relative
1420 addressing, but ensure it's unset (set for VEX) anyway, tmp_regno
1421 is not r8-r15. */
1422 if (insn_details->enc_prefix_offset != -1)
1423 {
1424 gdb_byte *pfx = &dsc->insn_buf[insn_details->enc_prefix_offset];
1425 if (rex_prefix_p (pfx[0]))
1426 pfx[0] &= ~REX_B;
1427 else if (vex3_prefix_p (pfx[0]))
1428 pfx[1] |= VEX3_NOT_B;
1429 else
1430 gdb_assert_not_reached ("unhandled prefix");
1431 }
35669430
DE		 1432
1433 regcache_cooked_read_unsigned (regs, tmp_regno, &orig_value);
1434 dsc->tmp_regno = tmp_regno;
1435 dsc->tmp_save = orig_value;
1436 dsc->tmp_used = 1;
1437
1438 /* Convert the ModRM field to be base+disp. */
1439 dsc->insn_buf[modrm_offset] &= ~0xc7;
1440 dsc->insn_buf[modrm_offset] |= 0x80 + arch_tmp_regno;
1441
1442 regcache_cooked_write_unsigned (regs, tmp_regno, rip_base);
1443
1444 if (debug_displaced)
1445 fprintf_unfiltered (gdb_stdlog, "displaced: %%rip-relative addressing used.\n"
5af949e3
UW		 1446 "displaced: using temp reg %d, old value %s, new value %s\n",
1447 dsc->tmp_regno, paddress (gdbarch, dsc->tmp_save),
1448 paddress (gdbarch, rip_base));
35669430
DE		 1449}
1450
1451static void
1452fixup_displaced_copy (struct gdbarch *gdbarch,
4a3a374c 1453 amd64_displaced_step_copy_insn_closure *dsc,
35669430
DE		 1454 CORE_ADDR from, CORE_ADDR to, struct regcache *regs)
1455{
1456 const struct amd64_insn *details = &dsc->insn_details;
1457
1458 if (details->modrm_offset != -1)
1459 {
1460 gdb_byte modrm = details->raw_insn[details->modrm_offset];
1461
1462 if ((modrm & 0xc7) == 0x05)
1463 {
1464 /* The insn uses rip-relative addressing.
1465 Deal with it. */
1466 fixup_riprel (gdbarch, dsc, from, to, regs);
1467 }
1468 }
1469}
1470
4a3a374c 1471displaced_step_copy_insn_closure_up
35669430
DE		 1472amd64_displaced_step_copy_insn (struct gdbarch *gdbarch,
1473 CORE_ADDR from, CORE_ADDR to,
1474 struct regcache *regs)
1475{
1476 int len = gdbarch_max_insn_length (gdbarch);
741e63d7 1477 /* Extra space for sentinels so fixup_{riprel,displaced_copy} don't have to
35669430
DE		 1478 continually watch for running off the end of the buffer. */
1479 int fixup_sentinel_space = len;
4a3a374c
SM		 1480 std::unique_ptr<amd64_displaced_step_copy_insn_closure> dsc
1481 (new amd64_displaced_step_copy_insn_closure (len + fixup_sentinel_space));
35669430
DE		 1482 gdb_byte *buf = &dsc->insn_buf[0];
1483 struct amd64_insn *details = &dsc->insn_details;
1484
35669430
DE		 1485 read_memory (from, buf, len);
1486
1487 /* Set up the sentinel space so we don't have to worry about running
1488 off the end of the buffer. An excessive number of leading prefixes
1489 could otherwise cause this. */
1490 memset (buf + len, 0, fixup_sentinel_space);
1491
1492 amd64_get_insn_details (buf, details);
1493
1494 /* GDB may get control back after the insn after the syscall.
1495 Presumably this is a kernel bug.
1496 If this is a syscall, make sure there's a nop afterwards. */
1497 {
1498 int syscall_length;
1499
1500 if (amd64_syscall_p (details, &syscall_length))
1501 buf[details->opcode_offset + syscall_length] = NOP_OPCODE;
1502 }
1503
1504 /* Modify the insn to cope with the address where it will be executed from.
1505 In particular, handle any rip-relative addressing. */
18b28e13 1506 fixup_displaced_copy (gdbarch, dsc.get (), from, to, regs);
35669430
DE		 1507
1508 write_memory (to, buf, len);
1509
1510 if (debug_displaced)
1511 {
5af949e3
UW		 1512 fprintf_unfiltered (gdb_stdlog, "displaced: copy %s->%s: ",
1513 paddress (gdbarch, from), paddress (gdbarch, to));
35669430
DE		 1514 displaced_step_dump_bytes (gdb_stdlog, buf, len);
1515 }
1516
4a3a374c
SM		 1517 /* This is a work around for a problem with g++ 4.8. */
1518 return displaced_step_copy_insn_closure_up (dsc.release ());
35669430
DE		 1519}
1520
1521static int
1522amd64_absolute_jmp_p (const struct amd64_insn *details)
1523{
1524 const gdb_byte *insn = &details->raw_insn[details->opcode_offset];
1525
1526 if (insn[0] == 0xff)
1527 {
1528 /* jump near, absolute indirect (/4) */
1529 if ((insn[1] & 0x38) == 0x20)
1530 return 1;
1531
1532 /* jump far, absolute indirect (/5) */
1533 if ((insn[1] & 0x38) == 0x28)
1534 return 1;
1535 }
1536
1537 return 0;
1538}
1539
c2170eef
MM		 1540/* Return non-zero if the instruction DETAILS is a jump, zero otherwise. */
1541
1542static int
1543amd64_jmp_p (const struct amd64_insn *details)
1544{
1545 const gdb_byte *insn = &details->raw_insn[details->opcode_offset];
1546
1547 /* jump short, relative. */
1548 if (insn[0] == 0xeb)
1549 return 1;
1550
1551 /* jump near, relative. */
1552 if (insn[0] == 0xe9)
1553 return 1;
1554
1555 return amd64_absolute_jmp_p (details);
1556}
1557
35669430
DE		 1558static int
1559amd64_absolute_call_p (const struct amd64_insn *details)
1560{
1561 const gdb_byte *insn = &details->raw_insn[details->opcode_offset];
1562
1563 if (insn[0] == 0xff)
1564 {
1565 /* Call near, absolute indirect (/2) */
1566 if ((insn[1] & 0x38) == 0x10)
1567 return 1;
1568
1569 /* Call far, absolute indirect (/3) */
1570 if ((insn[1] & 0x38) == 0x18)
1571 return 1;
1572 }
1573
1574 return 0;
1575}
1576
1577static int
1578amd64_ret_p (const struct amd64_insn *details)
1579{
1580 /* NOTE: gcc can emit "repz ; ret". */
1581 const gdb_byte *insn = &details->raw_insn[details->opcode_offset];
1582
1583 switch (insn[0])
1584 {
1585 case 0xc2: /* ret near, pop N bytes */
1586 case 0xc3: /* ret near */
1587 case 0xca: /* ret far, pop N bytes */
1588 case 0xcb: /* ret far */
1589 case 0xcf: /* iret */
1590 return 1;
1591
1592 default:
1593 return 0;
1594 }
1595}
1596
1597static int
1598amd64_call_p (const struct amd64_insn *details)
1599{
1600 const gdb_byte *insn = &details->raw_insn[details->opcode_offset];
1601
1602 if (amd64_absolute_call_p (details))
1603 return 1;
1604
1605 /* call near, relative */
1606 if (insn[0] == 0xe8)
1607 return 1;
1608
1609 return 0;
1610}
1611
35669430
DE		 1612/* Return non-zero if INSN is a system call, and set *LENGTHP to its
1613 length in bytes. Otherwise, return zero. */
1614
1615static int
1616amd64_syscall_p (const struct amd64_insn *details, int *lengthp)
1617{
1618 const gdb_byte *insn = &details->raw_insn[details->opcode_offset];
1619
1620 if (insn[0] == 0x0f && insn[1] == 0x05)
1621 {
1622 *lengthp = 2;
1623 return 1;
1624 }
1625
1626 return 0;
1627}
1628
c2170eef
MM		 1629/* Classify the instruction at ADDR using PRED.
1630 Throw an error if the memory can't be read. */
1631
1632static int
1633amd64_classify_insn_at (struct gdbarch *gdbarch, CORE_ADDR addr,
1634 int (*pred) (const struct amd64_insn *))
1635{
1636 struct amd64_insn details;
1637 gdb_byte *buf;
1638 int len, classification;
1639
1640 len = gdbarch_max_insn_length (gdbarch);
224c3ddb 1641 buf = (gdb_byte *) alloca (len);
c2170eef
MM		 1642
1643 read_code (addr, buf, len);
1644 amd64_get_insn_details (buf, &details);
1645
1646 classification = pred (&details);
1647
1648 return classification;
1649}
1650
1651/* The gdbarch insn_is_call method. */
1652
1653static int
1654amd64_insn_is_call (struct gdbarch *gdbarch, CORE_ADDR addr)
1655{
1656 return amd64_classify_insn_at (gdbarch, addr, amd64_call_p);
1657}
1658
1659/* The gdbarch insn_is_ret method. */
1660
1661static int
1662amd64_insn_is_ret (struct gdbarch *gdbarch, CORE_ADDR addr)
1663{
1664 return amd64_classify_insn_at (gdbarch, addr, amd64_ret_p);
1665}
1666
1667/* The gdbarch insn_is_jump method. */
1668
1669static int
1670amd64_insn_is_jump (struct gdbarch *gdbarch, CORE_ADDR addr)
1671{
1672 return amd64_classify_insn_at (gdbarch, addr, amd64_jmp_p);
1673}
1674
35669430
DE		 1675/* Fix up the state of registers and memory after having single-stepped
1676 a displaced instruction. */
1677
1678void
1679amd64_displaced_step_fixup (struct gdbarch *gdbarch,
4a3a374c 1680 struct displaced_step_copy_insn_closure *dsc_,
35669430
DE		 1681 CORE_ADDR from, CORE_ADDR to,
1682 struct regcache *regs)
1683{
4a3a374c 1684 amd64_displaced_step_copy_insn_closure *dsc = (amd64_displaced_step_copy_insn_closure *) dsc_;
e17a4113 1685 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
35669430
DE		 1686 /* The offset we applied to the instruction's address. */
1687 ULONGEST insn_offset = to - from;
cfba9872 1688 gdb_byte *insn = dsc->insn_buf.data ();
35669430
DE		 1689 const struct amd64_insn *insn_details = &dsc->insn_details;
1690
1691 if (debug_displaced)
1692 fprintf_unfiltered (gdb_stdlog,
5af949e3 1693 "displaced: fixup (%s, %s), "
35669430 1694 "insn = 0x%02x 0x%02x ...\n",
5af949e3
UW		 1695 paddress (gdbarch, from), paddress (gdbarch, to),
1696 insn[0], insn[1]);
35669430
DE		 1697
1698 /* If we used a tmp reg, restore it. */
1699
1700 if (dsc->tmp_used)
1701 {
1702 if (debug_displaced)
5af949e3
UW		 1703 fprintf_unfiltered (gdb_stdlog, "displaced: restoring reg %d to %s\n",
1704 dsc->tmp_regno, paddress (gdbarch, dsc->tmp_save));
35669430
DE		 1705 regcache_cooked_write_unsigned (regs, dsc->tmp_regno, dsc->tmp_save);
1706 }
1707
1708 /* The list of issues to contend with here is taken from
1709 resume_execution in arch/x86/kernel/kprobes.c, Linux 2.6.28.
1710 Yay for Free Software! */
1711
1712 /* Relocate the %rip back to the program's instruction stream,
1713 if necessary. */
1714
1715 /* Except in the case of absolute or indirect jump or call
1716 instructions, or a return instruction, the new rip is relative to
1717 the displaced instruction; make it relative to the original insn.
1718 Well, signal handler returns don't need relocation either, but we use the
1719 value of %rip to recognize those; see below. */
1720 if (! amd64_absolute_jmp_p (insn_details)
1721 && ! amd64_absolute_call_p (insn_details)
1722 && ! amd64_ret_p (insn_details))
1723 {
1724 ULONGEST orig_rip;
1725 int insn_len;
1726
1727 regcache_cooked_read_unsigned (regs, AMD64_RIP_REGNUM, &orig_rip);
1728
1729 /* A signal trampoline system call changes the %rip, resuming
1730 execution of the main program after the signal handler has
1731 returned. That makes them like 'return' instructions; we
1732 shouldn't relocate %rip.
1733
1734 But most system calls don't, and we do need to relocate %rip.
1735
1736 Our heuristic for distinguishing these cases: if stepping
1737 over the system call instruction left control directly after
1738 the instruction, the we relocate --- control almost certainly
1739 doesn't belong in the displaced copy. Otherwise, we assume
1740 the instruction has put control where it belongs, and leave
1741 it unrelocated. Goodness help us if there are PC-relative
1742 system calls. */
1743 if (amd64_syscall_p (insn_details, &insn_len)
1744 && orig_rip != to + insn_len
1745 /* GDB can get control back after the insn after the syscall.
1746 Presumably this is a kernel bug.
1747 Fixup ensures its a nop, we add one to the length for it. */
1748 && orig_rip != to + insn_len + 1)
1749 {
1750 if (debug_displaced)
1751 fprintf_unfiltered (gdb_stdlog,
1752 "displaced: syscall changed %%rip; "
1753 "not relocating\n");
1754 }
1755 else
1756 {
1757 ULONGEST rip = orig_rip - insn_offset;
1758
1903f0e6
DE		 1759 /* If we just stepped over a breakpoint insn, we don't backup
1760 the pc on purpose; this is to match behaviour without
1761 stepping. */
35669430
DE		 1762
1763 regcache_cooked_write_unsigned (regs, AMD64_RIP_REGNUM, rip);
1764
1765 if (debug_displaced)
1766 fprintf_unfiltered (gdb_stdlog,
1767 "displaced: "
5af949e3
UW		 1768 "relocated %%rip from %s to %s\n",
1769 paddress (gdbarch, orig_rip),
1770 paddress (gdbarch, rip));
35669430
DE		 1771 }
1772 }
1773
1774 /* If the instruction was PUSHFL, then the TF bit will be set in the
1775 pushed value, and should be cleared. We'll leave this for later,
1776 since GDB already messes up the TF flag when stepping over a
1777 pushfl. */
1778
1779 /* If the instruction was a call, the return address now atop the
1780 stack is the address following the copied instruction. We need
1781 to make it the address following the original instruction. */
1782 if (amd64_call_p (insn_details))
1783 {
1784 ULONGEST rsp;
1785 ULONGEST retaddr;
1786 const ULONGEST retaddr_len = 8;
1787
1788 regcache_cooked_read_unsigned (regs, AMD64_RSP_REGNUM, &rsp);
e17a4113 1789 retaddr = read_memory_unsigned_integer (rsp, retaddr_len, byte_order);
4dafcdeb 1790 retaddr = (retaddr - insn_offset) & 0xffffffffffffffffULL;
e17a4113 1791 write_memory_unsigned_integer (rsp, retaddr_len, byte_order, retaddr);
35669430
DE		 1792
1793 if (debug_displaced)
1794 fprintf_unfiltered (gdb_stdlog,
5af949e3
UW		 1795 "displaced: relocated return addr at %s "
1796 "to %s\n",
1797 paddress (gdbarch, rsp),
1798 paddress (gdbarch, retaddr));
35669430
DE		 1799 }
1800}
dde08ee1
PA		 1801
1802/* If the instruction INSN uses RIP-relative addressing, return the
1803 offset into the raw INSN where the displacement to be adjusted is
1804 found. Returns 0 if the instruction doesn't use RIP-relative
1805 addressing. */
1806
1807static int
1808rip_relative_offset (struct amd64_insn *insn)
1809{
1810 if (insn->modrm_offset != -1)
1811 {
1812 gdb_byte modrm = insn->raw_insn[insn->modrm_offset];
1813
1814 if ((modrm & 0xc7) == 0x05)
1815 {
1816 /* The displacement is found right after the ModRM byte. */
1817 return insn->modrm_offset + 1;
1818 }
1819 }
1820
1821 return 0;
1822}
1823
1824static void
1825append_insns (CORE_ADDR *to, ULONGEST len, const gdb_byte *buf)
1826{
1827 target_write_memory (*to, buf, len);
1828 *to += len;
1829}
1830
60965737 1831static void
dde08ee1
PA		 1832amd64_relocate_instruction (struct gdbarch *gdbarch,
1833 CORE_ADDR *to, CORE_ADDR oldloc)
1834{
1835 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1836 int len = gdbarch_max_insn_length (gdbarch);
1837 /* Extra space for sentinels. */
1838 int fixup_sentinel_space = len;
224c3ddb 1839 gdb_byte *buf = (gdb_byte *) xmalloc (len + fixup_sentinel_space);
dde08ee1
PA		 1840 struct amd64_insn insn_details;
1841 int offset = 0;
1842 LONGEST rel32, newrel;
1843 gdb_byte *insn;
1844 int insn_length;
1845
1846 read_memory (oldloc, buf, len);
1847
1848 /* Set up the sentinel space so we don't have to worry about running
1849 off the end of the buffer. An excessive number of leading prefixes
1850 could otherwise cause this. */
1851 memset (buf + len, 0, fixup_sentinel_space);
1852
1853 insn = buf;
1854 amd64_get_insn_details (insn, &insn_details);
1855
1856 insn_length = gdb_buffered_insn_length (gdbarch, insn, len, oldloc);
1857
1858 /* Skip legacy instruction prefixes. */
1859 insn = amd64_skip_prefixes (insn);
1860
1861 /* Adjust calls with 32-bit relative addresses as push/jump, with
1862 the address pushed being the location where the original call in
1863 the user program would return to. */
1864 if (insn[0] == 0xe8)
1865 {
f077e978
PA		 1866 gdb_byte push_buf[32];
1867 CORE_ADDR ret_addr;
1868 int i = 0;
dde08ee1
PA		 1869
1870 /* Where "ret" in the original code will return to. */
1871 ret_addr = oldloc + insn_length;
f077e978
PA		 1872
1873 /* If pushing an address higher than or equal to 0x80000000,
1874 avoid 'pushq', as that sign extends its 32-bit operand, which
1875 would be incorrect. */
1876 if (ret_addr <= 0x7fffffff)
1877 {
1878 push_buf[0] = 0x68; /* pushq $... */
1879 store_unsigned_integer (&push_buf[1], 4, byte_order, ret_addr);
1880 i = 5;
1881 }
1882 else
1883 {
1884 push_buf[i++] = 0x48; /* sub $0x8,%rsp */
1885 push_buf[i++] = 0x83;
1886 push_buf[i++] = 0xec;
1887 push_buf[i++] = 0x08;
1888
1889 push_buf[i++] = 0xc7; /* movl $imm,(%rsp) */
1890 push_buf[i++] = 0x04;
1891 push_buf[i++] = 0x24;
1892 store_unsigned_integer (&push_buf[i], 4, byte_order,
1893 ret_addr & 0xffffffff);
1894 i += 4;
1895
1896 push_buf[i++] = 0xc7; /* movl $imm,4(%rsp) */
1897 push_buf[i++] = 0x44;
1898 push_buf[i++] = 0x24;
1899 push_buf[i++] = 0x04;
1900 store_unsigned_integer (&push_buf[i], 4, byte_order,
1901 ret_addr >> 32);
1902 i += 4;
1903 }
1904 gdb_assert (i <= sizeof (push_buf));
dde08ee1 1905 /* Push the push. */
f077e978 1906 append_insns (to, i, push_buf);
dde08ee1
PA		 1907
1908 /* Convert the relative call to a relative jump. */
1909 insn[0] = 0xe9;
1910
1911 /* Adjust the destination offset. */
1912 rel32 = extract_signed_integer (insn + 1, 4, byte_order);
1913 newrel = (oldloc - *to) + rel32;
f4a1794a
KY		 1914 store_signed_integer (insn + 1, 4, byte_order, newrel);
1915
1916 if (debug_displaced)
1917 fprintf_unfiltered (gdb_stdlog,
1918 "Adjusted insn rel32=%s at %s to"
1919 " rel32=%s at %s\n",
1920 hex_string (rel32), paddress (gdbarch, oldloc),
1921 hex_string (newrel), paddress (gdbarch, *to));
dde08ee1
PA		 1922
1923 /* Write the adjusted jump into its displaced location. */
1924 append_insns (to, 5, insn);
1925 return;
1926 }
1927
1928 offset = rip_relative_offset (&insn_details);
1929 if (!offset)
1930 {
1931 /* Adjust jumps with 32-bit relative addresses. Calls are
1932 already handled above. */
1933 if (insn[0] == 0xe9)
1934 offset = 1;
1935 /* Adjust conditional jumps. */
1936 else if (insn[0] == 0x0f && (insn[1] & 0xf0) == 0x80)
1937 offset = 2;
1938 }
1939
1940 if (offset)
1941 {
1942 rel32 = extract_signed_integer (insn + offset, 4, byte_order);
1943 newrel = (oldloc - *to) + rel32;
f4a1794a 1944 store_signed_integer (insn + offset, 4, byte_order, newrel);
dde08ee1
PA		 1945 if (debug_displaced)
1946 fprintf_unfiltered (gdb_stdlog,
f4a1794a
KY		 1947 "Adjusted insn rel32=%s at %s to"
1948 " rel32=%s at %s\n",
dde08ee1
PA		 1949 hex_string (rel32), paddress (gdbarch, oldloc),
1950 hex_string (newrel), paddress (gdbarch, *to));
1951 }
1952
1953 /* Write the adjusted instruction into its displaced location. */
1954 append_insns (to, insn_length, buf);
1955}
1956
35669430 1957\f
c4f35dd8 1958/* The maximum number of saved registers. This should include %rip. */
90f90721 1959#define AMD64_NUM_SAVED_REGS AMD64_NUM_GREGS
c4f35dd8 1960
e53bef9f 1961struct amd64_frame_cache
c4f35dd8
MK		 1962{
1963 /* Base address. */
1964 CORE_ADDR base;
8fbca658 1965 int base_p;
c4f35dd8
MK		 1966 CORE_ADDR sp_offset;
1967 CORE_ADDR pc;
1968
1969 /* Saved registers. */
e53bef9f 1970 CORE_ADDR saved_regs[AMD64_NUM_SAVED_REGS];
c4f35dd8 1971 CORE_ADDR saved_sp;
e0c62198 1972 int saved_sp_reg;
c4f35dd8
MK		 1973
1974 /* Do we have a frame? */
1975 int frameless_p;
1976};
8dda9770 1977
d2449ee8 1978/* Initialize a frame cache. */
c4f35dd8 1979
d2449ee8
DJ		 1980static void
1981amd64_init_frame_cache (struct amd64_frame_cache *cache)
8dda9770 1982{
c4f35dd8
MK		 1983 int i;
1984
c4f35dd8
MK		 1985 /* Base address. */
1986 cache->base = 0;
8fbca658 1987 cache->base_p = 0;
c4f35dd8
MK		 1988 cache->sp_offset = -8;
1989 cache->pc = 0;
1990
1991 /* Saved registers. We initialize these to -1 since zero is a valid
bba66b87
DE		 1992 offset (that's where %rbp is supposed to be stored).
1993 The values start out as being offsets, and are later converted to
1994 addresses (at which point -1 is interpreted as an address, still meaning
1995 "invalid"). */
e53bef9f 1996 for (i = 0; i < AMD64_NUM_SAVED_REGS; i++)
c4f35dd8
MK		 1997 cache->saved_regs[i] = -1;
1998 cache->saved_sp = 0;
e0c62198 1999 cache->saved_sp_reg = -1;
c4f35dd8
MK		 2000
2001 /* Frameless until proven otherwise. */
2002 cache->frameless_p = 1;
d2449ee8 2003}
c4f35dd8 2004
d2449ee8
DJ		 2005/* Allocate and initialize a frame cache. */
2006
2007static struct amd64_frame_cache *
2008amd64_alloc_frame_cache (void)
2009{
2010 struct amd64_frame_cache *cache;
2011
2012 cache = FRAME_OBSTACK_ZALLOC (struct amd64_frame_cache);
2013 amd64_init_frame_cache (cache);
c4f35dd8 2014 return cache;
8dda9770 2015}
53e95fcf 2016
e0c62198
L		 2017/* GCC 4.4 and later, can put code in the prologue to realign the
2018 stack pointer. Check whether PC points to such code, and update
2019 CACHE accordingly. Return the first instruction after the code
2020 sequence or CURRENT_PC, whichever is smaller. If we don't
2021 recognize the code, return PC. */
2022
2023static CORE_ADDR
2024amd64_analyze_stack_align (CORE_ADDR pc, CORE_ADDR current_pc,
2025 struct amd64_frame_cache *cache)
2026{
2027 /* There are 2 code sequences to re-align stack before the frame
2028 gets set up:
2029
2030 1. Use a caller-saved saved register:
2031
2032 leaq 8(%rsp), %reg
2033 andq $-XXX, %rsp
2034 pushq -8(%reg)
2035
2036 2. Use a callee-saved saved register:
2037
2038 pushq %reg
2039 leaq 16(%rsp), %reg
2040 andq $-XXX, %rsp
2041 pushq -8(%reg)
2042
2043 "andq $-XXX, %rsp" can be either 4 bytes or 7 bytes:
2044
2045 0x48 0x83 0xe4 0xf0 andq $-16, %rsp
2046 0x48 0x81 0xe4 0x00 0xff 0xff 0xff andq $-256, %rsp
2047 */
2048
2049 gdb_byte buf[18];
2050 int reg, r;
2051 int offset, offset_and;
e0c62198 2052
bae8a07a 2053 if (target_read_code (pc, buf, sizeof buf))
e0c62198
L		 2054 return pc;
2055
2056 /* Check caller-saved saved register. The first instruction has
2057 to be "leaq 8(%rsp), %reg". */
2058 if ((buf[0] & 0xfb) == 0x48
2059 && buf[1] == 0x8d
2060 && buf[3] == 0x24
2061 && buf[4] == 0x8)
2062 {
2063 /* MOD must be binary 10 and R/M must be binary 100. */
2064 if ((buf[2] & 0xc7) != 0x44)
2065 return pc;
2066
2067 /* REG has register number. */
2068 reg = (buf[2] >> 3) & 7;
2069
2070 /* Check the REX.R bit. */
2071 if (buf[0] == 0x4c)
2072 reg += 8;
2073
2074 offset = 5;
2075 }
2076 else
2077 {
2078 /* Check callee-saved saved register. The first instruction
2079 has to be "pushq %reg". */
2080 reg = 0;
2081 if ((buf[0] & 0xf8) == 0x50)
2082 offset = 0;
2083 else if ((buf[0] & 0xf6) == 0x40
2084 && (buf[1] & 0xf8) == 0x50)
2085 {
2086 /* Check the REX.B bit. */
2087 if ((buf[0] & 1) != 0)
2088 reg = 8;
2089
2090 offset = 1;
2091 }
2092 else
2093 return pc;
2094
2095 /* Get register. */
2096 reg += buf[offset] & 0x7;
2097
2098 offset++;
2099
2100 /* The next instruction has to be "leaq 16(%rsp), %reg". */
2101 if ((buf[offset] & 0xfb) != 0x48
2102 || buf[offset + 1] != 0x8d
2103 || buf[offset + 3] != 0x24
2104 || buf[offset + 4] != 0x10)
2105 return pc;
2106
2107 /* MOD must be binary 10 and R/M must be binary 100. */
2108 if ((buf[offset + 2] & 0xc7) != 0x44)
2109 return pc;
2110
2111 /* REG has register number. */
2112 r = (buf[offset + 2] >> 3) & 7;
2113
2114 /* Check the REX.R bit. */
2115 if (buf[offset] == 0x4c)
2116 r += 8;
2117
2118 /* Registers in pushq and leaq have to be the same. */
2119 if (reg != r)
2120 return pc;
2121
2122 offset += 5;
2123 }
2124
2125 /* Rigister can't be %rsp nor %rbp. */
2126 if (reg == 4 || reg == 5)
2127 return pc;
2128
2129 /* The next instruction has to be "andq $-XXX, %rsp". */
2130 if (buf[offset] != 0x48
2131 || buf[offset + 2] != 0xe4
2132 || (buf[offset + 1] != 0x81 && buf[offset + 1] != 0x83))
2133 return pc;
2134
2135 offset_and = offset;
2136 offset += buf[offset + 1] == 0x81 ? 7 : 4;
2137
2138 /* The next instruction has to be "pushq -8(%reg)". */
2139 r = 0;
2140 if (buf[offset] == 0xff)
2141 offset++;
2142 else if ((buf[offset] & 0xf6) == 0x40
2143 && buf[offset + 1] == 0xff)
2144 {
2145 /* Check the REX.B bit. */
2146 if ((buf[offset] & 0x1) != 0)
2147 r = 8;
2148 offset += 2;
2149 }
2150 else
2151 return pc;
2152
2153 /* 8bit -8 is 0xf8. REG must be binary 110 and MOD must be binary
2154 01. */
2155 if (buf[offset + 1] != 0xf8
2156 || (buf[offset] & 0xf8) != 0x70)
2157 return pc;
2158
2159 /* R/M has register. */
2160 r += buf[offset] & 7;
2161
2162 /* Registers in leaq and pushq have to be the same. */
2163 if (reg != r)
2164 return pc;
2165
2166 if (current_pc > pc + offset_and)
35669430 2167 cache->saved_sp_reg = amd64_arch_reg_to_regnum (reg);
e0c62198 2168
325fac50 2169 return std::min (pc + offset + 2, current_pc);
e0c62198
L		 2170}
2171
ac142d96
L		 2172/* Similar to amd64_analyze_stack_align for x32. */
2173
2174static CORE_ADDR
2175amd64_x32_analyze_stack_align (CORE_ADDR pc, CORE_ADDR current_pc,
2176 struct amd64_frame_cache *cache)
2177{
2178 /* There are 2 code sequences to re-align stack before the frame
2179 gets set up:
2180
2181 1. Use a caller-saved saved register:
2182
2183 leaq 8(%rsp), %reg
2184 andq $-XXX, %rsp
2185 pushq -8(%reg)
2186
2187 or
2188
2189 [addr32] leal 8(%rsp), %reg
2190 andl $-XXX, %esp
2191 [addr32] pushq -8(%reg)
2192
2193 2. Use a callee-saved saved register:
2194
2195 pushq %reg
2196 leaq 16(%rsp), %reg
2197 andq $-XXX, %rsp
2198 pushq -8(%reg)
2199
2200 or
2201
2202 pushq %reg
2203 [addr32] leal 16(%rsp), %reg
2204 andl $-XXX, %esp
2205 [addr32] pushq -8(%reg)
2206
2207 "andq $-XXX, %rsp" can be either 4 bytes or 7 bytes:
2208
2209 0x48 0x83 0xe4 0xf0 andq $-16, %rsp
2210 0x48 0x81 0xe4 0x00 0xff 0xff 0xff andq $-256, %rsp
2211
2212 "andl $-XXX, %esp" can be either 3 bytes or 6 bytes:
2213
2214 0x83 0xe4 0xf0 andl $-16, %esp
2215 0x81 0xe4 0x00 0xff 0xff 0xff andl $-256, %esp
2216 */
2217
2218 gdb_byte buf[19];
2219 int reg, r;
2220 int offset, offset_and;
2221
2222 if (target_read_memory (pc, buf, sizeof buf))
2223 return pc;
2224
2225 /* Skip optional addr32 prefix. */
2226 offset = buf[0] == 0x67 ? 1 : 0;
2227
2228 /* Check caller-saved saved register. The first instruction has
2229 to be "leaq 8(%rsp), %reg" or "leal 8(%rsp), %reg". */
2230 if (((buf[offset] & 0xfb) == 0x48 || (buf[offset] & 0xfb) == 0x40)
2231 && buf[offset + 1] == 0x8d
2232 && buf[offset + 3] == 0x24
2233 && buf[offset + 4] == 0x8)
2234 {
2235 /* MOD must be binary 10 and R/M must be binary 100. */
2236 if ((buf[offset + 2] & 0xc7) != 0x44)
2237 return pc;
2238
2239 /* REG has register number. */
2240 reg = (buf[offset + 2] >> 3) & 7;
2241
2242 /* Check the REX.R bit. */
2243 if ((buf[offset] & 0x4) != 0)
2244 reg += 8;
2245
2246 offset += 5;
2247 }
2248 else
2249 {
2250 /* Check callee-saved saved register. The first instruction
2251 has to be "pushq %reg". */
2252 reg = 0;
2253 if ((buf[offset] & 0xf6) == 0x40
2254 && (buf[offset + 1] & 0xf8) == 0x50)
2255 {
2256 /* Check the REX.B bit. */
2257 if ((buf[offset] & 1) != 0)
2258 reg = 8;
2259
2260 offset += 1;
2261 }
2262 else if ((buf[offset] & 0xf8) != 0x50)
2263 return pc;
2264
2265 /* Get register. */
2266 reg += buf[offset] & 0x7;
2267
2268 offset++;
2269
2270 /* Skip optional addr32 prefix. */
2271 if (buf[offset] == 0x67)
2272 offset++;
2273
2274 /* The next instruction has to be "leaq 16(%rsp), %reg" or
2275 "leal 16(%rsp), %reg". */
2276 if (((buf[offset] & 0xfb) != 0x48 && (buf[offset] & 0xfb) != 0x40)
2277 || buf[offset + 1] != 0x8d
2278 || buf[offset + 3] != 0x24
2279 || buf[offset + 4] != 0x10)
2280 return pc;
2281
2282 /* MOD must be binary 10 and R/M must be binary 100. */
2283 if ((buf[offset + 2] & 0xc7) != 0x44)
2284 return pc;
2285
2286 /* REG has register number. */
2287 r = (buf[offset + 2] >> 3) & 7;
2288
2289 /* Check the REX.R bit. */
2290 if ((buf[offset] & 0x4) != 0)
2291 r += 8;
2292
2293 /* Registers in pushq and leaq have to be the same. */
2294 if (reg != r)
2295 return pc;
2296
2297 offset += 5;
2298 }
2299
2300 /* Rigister can't be %rsp nor %rbp. */
2301 if (reg == 4 || reg == 5)
2302 return pc;
2303
2304 /* The next instruction may be "andq $-XXX, %rsp" or
2305 "andl $-XXX, %esp". */
2306 if (buf[offset] != 0x48)
2307 offset--;
2308
2309 if (buf[offset + 2] != 0xe4
2310 || (buf[offset + 1] != 0x81 && buf[offset + 1] != 0x83))
2311 return pc;
2312
2313 offset_and = offset;
2314 offset += buf[offset + 1] == 0x81 ? 7 : 4;
2315
2316 /* Skip optional addr32 prefix. */
2317 if (buf[offset] == 0x67)
2318 offset++;
2319
2320 /* The next instruction has to be "pushq -8(%reg)". */
2321 r = 0;
2322 if (buf[offset] == 0xff)
2323 offset++;
2324 else if ((buf[offset] & 0xf6) == 0x40
2325 && buf[offset + 1] == 0xff)
2326 {
2327 /* Check the REX.B bit. */
2328 if ((buf[offset] & 0x1) != 0)
2329 r = 8;
2330 offset += 2;
2331 }
2332 else
2333 return pc;
2334
2335 /* 8bit -8 is 0xf8. REG must be binary 110 and MOD must be binary
2336 01. */
2337 if (buf[offset + 1] != 0xf8
2338 || (buf[offset] & 0xf8) != 0x70)
2339 return pc;
2340
2341 /* R/M has register. */
2342 r += buf[offset] & 7;
2343
2344 /* Registers in leaq and pushq have to be the same. */
2345 if (reg != r)
2346 return pc;
2347
2348 if (current_pc > pc + offset_and)
2349 cache->saved_sp_reg = amd64_arch_reg_to_regnum (reg);
2350
325fac50 2351 return std::min (pc + offset + 2, current_pc);
ac142d96
L		 2352}
2353
c4f35dd8
MK		 2354/* Do a limited analysis of the prologue at PC and update CACHE
2355 accordingly. Bail out early if CURRENT_PC is reached. Return the
2356 address where the analysis stopped.
2357
2358 We will handle only functions beginning with:
2359
2360 pushq %rbp 0x55
50f1ae7b 2361 movq %rsp, %rbp 0x48 0x89 0xe5 (or 0x48 0x8b 0xec)
c4f35dd8 2362
649e6d92
MK		 2363 or (for the X32 ABI):
2364
2365 pushq %rbp 0x55
2366 movl %esp, %ebp 0x89 0xe5 (or 0x8b 0xec)
2367
2368 Any function that doesn't start with one of these sequences will be
2369 assumed to have no prologue and thus no valid frame pointer in
2370 %rbp. */
c4f35dd8
MK		 2371
2372static CORE_ADDR
e17a4113
UW		 2373amd64_analyze_prologue (struct gdbarch *gdbarch,
2374 CORE_ADDR pc, CORE_ADDR current_pc,
e53bef9f 2375 struct amd64_frame_cache *cache)
53e95fcf 2376{
e17a4113 2377 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
50f1ae7b
DE		 2378 /* There are two variations of movq %rsp, %rbp. */
2379 static const gdb_byte mov_rsp_rbp_1[3] = { 0x48, 0x89, 0xe5 };
2380 static const gdb_byte mov_rsp_rbp_2[3] = { 0x48, 0x8b, 0xec };
649e6d92
MK		 2381 /* Ditto for movl %esp, %ebp. */
2382 static const gdb_byte mov_esp_ebp_1[2] = { 0x89, 0xe5 };
2383 static const gdb_byte mov_esp_ebp_2[2] = { 0x8b, 0xec };
2384
d8de1ef7
MK		 2385 gdb_byte buf[3];
2386 gdb_byte op;
c4f35dd8
MK		 2387
2388 if (current_pc <= pc)
2389 return current_pc;
2390
ac142d96
L		 2391 if (gdbarch_ptr_bit (gdbarch) == 32)
2392 pc = amd64_x32_analyze_stack_align (pc, current_pc, cache);
2393 else
2394 pc = amd64_analyze_stack_align (pc, current_pc, cache);
e0c62198 2395
bae8a07a 2396 op = read_code_unsigned_integer (pc, 1, byte_order);
c4f35dd8
MK		 2397
2398 if (op == 0x55) /* pushq %rbp */
2399 {
2400 /* Take into account that we've executed the `pushq %rbp' that
2401 starts this instruction sequence. */
90f90721 2402 cache->saved_regs[AMD64_RBP_REGNUM] = 0;
c4f35dd8
MK		 2403 cache->sp_offset += 8;
2404
2405 /* If that's all, return now. */
2406 if (current_pc <= pc + 1)
2407 return current_pc;
2408
bae8a07a 2409 read_code (pc + 1, buf, 3);
c4f35dd8 2410
649e6d92
MK		 2411 /* Check for `movq %rsp, %rbp'. */
2412 if (memcmp (buf, mov_rsp_rbp_1, 3) == 0
2413 || memcmp (buf, mov_rsp_rbp_2, 3) == 0)
2414 {
2415 /* OK, we actually have a frame. */
2416 cache->frameless_p = 0;
2417 return pc + 4;
2418 }
2419
2420 /* For X32, also check for `movq %esp, %ebp'. */
2421 if (gdbarch_ptr_bit (gdbarch) == 32)
2422 {
2423 if (memcmp (buf, mov_esp_ebp_1, 2) == 0
2424 || memcmp (buf, mov_esp_ebp_2, 2) == 0)
2425 {
2426 /* OK, we actually have a frame. */
2427 cache->frameless_p = 0;
2428 return pc + 3;
2429 }
2430 }
2431
2432 return pc + 1;
c4f35dd8
MK		 2433 }
2434
2435 return pc;
53e95fcf
JS		 2436}
2437
df15bd07
JK		 2438/* Work around false termination of prologue - GCC PR debug/48827.
2439
2440 START_PC is the first instruction of a function, PC is its minimal already
2441 determined advanced address. Function returns PC if it has nothing to do.
2442
2443 84 c0 test %al,%al
2444 74 23 je after
2445 <-- here is 0 lines advance - the false prologue end marker.
2446 0f 29 85 70 ff ff ff movaps %xmm0,-0x90(%rbp)
2447 0f 29 4d 80 movaps %xmm1,-0x80(%rbp)
2448 0f 29 55 90 movaps %xmm2,-0x70(%rbp)
2449 0f 29 5d a0 movaps %xmm3,-0x60(%rbp)
2450 0f 29 65 b0 movaps %xmm4,-0x50(%rbp)
2451 0f 29 6d c0 movaps %xmm5,-0x40(%rbp)
2452 0f 29 75 d0 movaps %xmm6,-0x30(%rbp)
2453 0f 29 7d e0 movaps %xmm7,-0x20(%rbp)
2454 after: */
c4f35dd8
MK		 2455
2456static CORE_ADDR
df15bd07 2457amd64_skip_xmm_prologue (CORE_ADDR pc, CORE_ADDR start_pc)
53e95fcf 2458{
08711b9a
JK		 2459 struct symtab_and_line start_pc_sal, next_sal;
2460 gdb_byte buf[4 + 8 * 7];
2461 int offset, xmmreg;
c4f35dd8 2462
08711b9a
JK		 2463 if (pc == start_pc)
2464 return pc;
2465
2466 start_pc_sal = find_pc_sect_line (start_pc, NULL, 0);
2467 if (start_pc_sal.symtab == NULL
43f3e411
DE		 2468 || producer_is_gcc_ge_4 (COMPUNIT_PRODUCER
2469 (SYMTAB_COMPUNIT (start_pc_sal.symtab))) < 6
08711b9a
JK		 2470 || start_pc_sal.pc != start_pc || pc >= start_pc_sal.end)
2471 return pc;
2472
2473 next_sal = find_pc_sect_line (start_pc_sal.end, NULL, 0);
2474 if (next_sal.line != start_pc_sal.line)
2475 return pc;
2476
2477 /* START_PC can be from overlayed memory, ignored here. */
bae8a07a 2478 if (target_read_code (next_sal.pc - 4, buf, sizeof (buf)) != 0)
08711b9a
JK		 2479 return pc;
2480
2481 /* test %al,%al */
2482 if (buf[0] != 0x84 || buf[1] != 0xc0)
2483 return pc;
2484 /* je AFTER */
2485 if (buf[2] != 0x74)
2486 return pc;
2487
2488 offset = 4;
2489 for (xmmreg = 0; xmmreg < 8; xmmreg++)
2490 {
bede5f5f 2491 /* 0x0f 0x29 0b??000101 movaps %xmmreg?,-0x??(%rbp) */
08711b9a 2492 if (buf[offset] != 0x0f || buf[offset + 1] != 0x29
bede5f5f 2493 || (buf[offset + 2] & 0x3f) != (xmmreg << 3 | 0x5))
08711b9a
JK		 2494 return pc;
2495
bede5f5f
JK		 2496 /* 0b01?????? */
2497 if ((buf[offset + 2] & 0xc0) == 0x40)
08711b9a
JK		 2498 {
2499 /* 8-bit displacement. */
2500 offset += 4;
2501 }
bede5f5f
JK		 2502 /* 0b10?????? */
2503 else if ((buf[offset + 2] & 0xc0) == 0x80)
08711b9a
JK		 2504 {
2505 /* 32-bit displacement. */
2506 offset += 7;
2507 }
2508 else
2509 return pc;
2510 }
2511
2512 /* je AFTER */
2513 if (offset - 4 != buf[3])
2514 return pc;
2515
2516 return next_sal.end;
53e95fcf 2517}
df15bd07
JK		 2518
2519/* Return PC of first real instruction. */
2520
2521static CORE_ADDR
2522amd64_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc)
2523{
2524 struct amd64_frame_cache cache;
2525 CORE_ADDR pc;
56bf0743
KB		 2526 CORE_ADDR func_addr;
2527
2528 if (find_pc_partial_function (start_pc, NULL, &func_addr, NULL))
2529 {
2530 CORE_ADDR post_prologue_pc
2531 = skip_prologue_using_sal (gdbarch, func_addr);
43f3e411 2532 struct compunit_symtab *cust = find_pc_compunit_symtab (func_addr);
56bf0743
KB		 2533
2534 /* Clang always emits a line note before the prologue and another
2535 one after. We trust clang to emit usable line notes. */
2536 if (post_prologue_pc
43f3e411
DE		 2537 && (cust != NULL
2538 && COMPUNIT_PRODUCER (cust) != NULL
61012eef 2539 && startswith (COMPUNIT_PRODUCER (cust), "clang ")))
325fac50 2540 return std::max (start_pc, post_prologue_pc);
56bf0743 2541 }
df15bd07
JK		 2542
2543 amd64_init_frame_cache (&cache);
2544 pc = amd64_analyze_prologue (gdbarch, start_pc, 0xffffffffffffffffLL,
2545 &cache);
2546 if (cache.frameless_p)
2547 return start_pc;
2548
2549 return amd64_skip_xmm_prologue (pc, start_pc);
2550}
c4f35dd8 2551\f
53e95fcf 2552
c4f35dd8
MK		 2553/* Normal frames. */
2554
8fbca658
PA		 2555static void
2556amd64_frame_cache_1 (struct frame_info *this_frame,
2557 struct amd64_frame_cache *cache)
6d686a84 2558{
e17a4113
UW		 2559 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2560 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
d8de1ef7 2561 gdb_byte buf[8];
6d686a84 2562 int i;
6d686a84 2563
10458914 2564 cache->pc = get_frame_func (this_frame);
c4f35dd8 2565 if (cache->pc != 0)
e17a4113
UW		 2566 amd64_analyze_prologue (gdbarch, cache->pc, get_frame_pc (this_frame),
2567 cache);
c4f35dd8
MK		 2568
2569 if (cache->frameless_p)
2570 {
4a28816e
MK		 2571 /* We didn't find a valid frame. If we're at the start of a
2572 function, or somewhere half-way its prologue, the function's
2573 frame probably hasn't been fully setup yet. Try to
2574 reconstruct the base address for the stack frame by looking
2575 at the stack pointer. For truly "frameless" functions this
2576 might work too. */
c4f35dd8 2577
e0c62198
L		 2578 if (cache->saved_sp_reg != -1)
2579 {
8fbca658
PA		 2580 /* Stack pointer has been saved. */
2581 get_frame_register (this_frame, cache->saved_sp_reg, buf);
2582 cache->saved_sp = extract_unsigned_integer (buf, 8, byte_order);
2583
e0c62198
L		 2584 /* We're halfway aligning the stack. */
2585 cache->base = ((cache->saved_sp - 8) & 0xfffffffffffffff0LL) - 8;
2586 cache->saved_regs[AMD64_RIP_REGNUM] = cache->saved_sp - 8;
2587
2588 /* This will be added back below. */
2589 cache->saved_regs[AMD64_RIP_REGNUM] -= cache->base;
2590 }
2591 else
2592 {
2593 get_frame_register (this_frame, AMD64_RSP_REGNUM, buf);
e17a4113
UW		 2594 cache->base = extract_unsigned_integer (buf, 8, byte_order)
2595 + cache->sp_offset;
e0c62198 2596 }
c4f35dd8 2597 }
35883a3f
MK		 2598 else
2599 {
10458914 2600 get_frame_register (this_frame, AMD64_RBP_REGNUM, buf);
e17a4113 2601 cache->base = extract_unsigned_integer (buf, 8, byte_order);
35883a3f 2602 }
c4f35dd8
MK		 2603
2604 /* Now that we have the base address for the stack frame we can
2605 calculate the value of %rsp in the calling frame. */
2606 cache->saved_sp = cache->base + 16;
2607
35883a3f
MK		 2608 /* For normal frames, %rip is stored at 8(%rbp). If we don't have a
2609 frame we find it at the same offset from the reconstructed base
e0c62198
L		 2610 address. If we're halfway aligning the stack, %rip is handled
2611 differently (see above). */
2612 if (!cache->frameless_p || cache->saved_sp_reg == -1)
2613 cache->saved_regs[AMD64_RIP_REGNUM] = 8;
35883a3f 2614
c4f35dd8
MK		 2615 /* Adjust all the saved registers such that they contain addresses
2616 instead of offsets. */
e53bef9f 2617 for (i = 0; i < AMD64_NUM_SAVED_REGS; i++)
c4f35dd8
MK		 2618 if (cache->saved_regs[i] != -1)
2619 cache->saved_regs[i] += cache->base;
2620
8fbca658
PA		 2621 cache->base_p = 1;
2622}
2623
2624static struct amd64_frame_cache *
2625amd64_frame_cache (struct frame_info *this_frame, void **this_cache)
2626{
8fbca658
PA		 2627 struct amd64_frame_cache *cache;
2628
2629 if (*this_cache)
9a3c8263 2630 return (struct amd64_frame_cache *) *this_cache;
8fbca658
PA		 2631
2632 cache = amd64_alloc_frame_cache ();
2633 *this_cache = cache;
2634
a70b8144 2635 try
8fbca658
PA		 2636 {
2637 amd64_frame_cache_1 (this_frame, cache);
2638 }
230d2906 2639 catch (const gdb_exception_error &ex)
7556d4a4
PA		 2640 {
2641 if (ex.error != NOT_AVAILABLE_ERROR)
eedc3f4f 2642 throw;
7556d4a4 2643 }
8fbca658 2644
c4f35dd8 2645 return cache;
6d686a84
ML		 2646}
2647
8fbca658
PA		 2648static enum unwind_stop_reason
2649amd64_frame_unwind_stop_reason (struct frame_info *this_frame,
2650 void **this_cache)
2651{
2652 struct amd64_frame_cache *cache =
2653 amd64_frame_cache (this_frame, this_cache);
2654
2655 if (!cache->base_p)
2656 return UNWIND_UNAVAILABLE;
2657
2658 /* This marks the outermost frame. */
2659 if (cache->base == 0)
2660 return UNWIND_OUTERMOST;
2661
2662 return UNWIND_NO_REASON;
2663}
2664
c4f35dd8 2665static void
10458914 2666amd64_frame_this_id (struct frame_info *this_frame, void **this_cache,
e53bef9f 2667 struct frame_id *this_id)
c4f35dd8 2668{
e53bef9f 2669 struct amd64_frame_cache *cache =
10458914 2670 amd64_frame_cache (this_frame, this_cache);
c4f35dd8 2671
8fbca658 2672 if (!cache->base_p)
5ce0145d
PA		 2673 (*this_id) = frame_id_build_unavailable_stack (cache->pc);
2674 else if (cache->base == 0)
2675 {
2676 /* This marks the outermost frame. */
2677 return;
2678 }
2679 else
2680 (*this_id) = frame_id_build (cache->base + 16, cache->pc);
c4f35dd8 2681}
e76e1718 2682
10458914
DJ		 2683static struct value *
2684amd64_frame_prev_register (struct frame_info *this_frame, void **this_cache,
2685 int regnum)
53e95fcf 2686{
10458914 2687 struct gdbarch *gdbarch = get_frame_arch (this_frame);
e53bef9f 2688 struct amd64_frame_cache *cache =
10458914 2689 amd64_frame_cache (this_frame, this_cache);
e76e1718 2690
c4f35dd8 2691 gdb_assert (regnum >= 0);
b1ab997b 2692
2ae02b47 2693 if (regnum == gdbarch_sp_regnum (gdbarch) && cache->saved_sp)
10458914 2694 return frame_unwind_got_constant (this_frame, regnum, cache->saved_sp);
e76e1718 2695
e53bef9f 2696 if (regnum < AMD64_NUM_SAVED_REGS && cache->saved_regs[regnum] != -1)
10458914
DJ		 2697 return frame_unwind_got_memory (this_frame, regnum,
2698 cache->saved_regs[regnum]);
e76e1718 2699
10458914 2700 return frame_unwind_got_register (this_frame, regnum, regnum);
c4f35dd8 2701}
e76e1718 2702
e53bef9f 2703static const struct frame_unwind amd64_frame_unwind =
c4f35dd8
MK		 2704{
2705 NORMAL_FRAME,
8fbca658 2706 amd64_frame_unwind_stop_reason,
e53bef9f 2707 amd64_frame_this_id,
10458914
DJ		 2708 amd64_frame_prev_register,
2709 NULL,
2710 default_frame_sniffer
c4f35dd8 2711};
c4f35dd8 2712\f
6710bf39
SS		 2713/* Generate a bytecode expression to get the value of the saved PC. */
2714
2715static void
2716amd64_gen_return_address (struct gdbarch *gdbarch,
2717 struct agent_expr *ax, struct axs_value *value,
2718 CORE_ADDR scope)
2719{
2720 /* The following sequence assumes the traditional use of the base
2721 register. */
2722 ax_reg (ax, AMD64_RBP_REGNUM);
2723 ax_const_l (ax, 8);
2724 ax_simple (ax, aop_add);
2725 value->type = register_type (gdbarch, AMD64_RIP_REGNUM);
2726 value->kind = axs_lvalue_memory;
2727}
2728\f
e76e1718 2729
c4f35dd8
MK		 2730/* Signal trampolines. */
2731
2732/* FIXME: kettenis/20030419: Perhaps, we can unify the 32-bit and
2733 64-bit variants. This would require using identical frame caches
2734 on both platforms. */
2735
e53bef9f 2736static struct amd64_frame_cache *
10458914 2737amd64_sigtramp_frame_cache (struct frame_info *this_frame, void **this_cache)
c4f35dd8 2738{
e17a4113
UW		 2739 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2740 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2741 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
e53bef9f 2742 struct amd64_frame_cache *cache;
c4f35dd8 2743 CORE_ADDR addr;
d8de1ef7 2744 gdb_byte buf[8];
2b5e0749 2745 int i;
c4f35dd8
MK		 2746
2747 if (*this_cache)
9a3c8263 2748 return (struct amd64_frame_cache *) *this_cache;
c4f35dd8 2749
e53bef9f 2750 cache = amd64_alloc_frame_cache ();
c4f35dd8 2751
a70b8144 2752 try
8fbca658
PA		 2753 {
2754 get_frame_register (this_frame, AMD64_RSP_REGNUM, buf);
2755 cache->base = extract_unsigned_integer (buf, 8, byte_order) - 8;
2756
2757 addr = tdep->sigcontext_addr (this_frame);
2758 gdb_assert (tdep->sc_reg_offset);
2759 gdb_assert (tdep->sc_num_regs <= AMD64_NUM_SAVED_REGS);
2760 for (i = 0; i < tdep->sc_num_regs; i++)
2761 if (tdep->sc_reg_offset[i] != -1)
2762 cache->saved_regs[i] = addr + tdep->sc_reg_offset[i];
c4f35dd8 2763
8fbca658
PA		 2764 cache->base_p = 1;
2765 }
230d2906 2766 catch (const gdb_exception_error &ex)
7556d4a4
PA		 2767 {
2768 if (ex.error != NOT_AVAILABLE_ERROR)
eedc3f4f 2769 throw;
7556d4a4 2770 }
c4f35dd8
MK		 2771
2772 *this_cache = cache;
2773 return cache;
53e95fcf
JS		 2774}
2775
8fbca658
PA		 2776static enum unwind_stop_reason
2777amd64_sigtramp_frame_unwind_stop_reason (struct frame_info *this_frame,
2778 void **this_cache)
2779{
2780 struct amd64_frame_cache *cache =
2781 amd64_sigtramp_frame_cache (this_frame, this_cache);
2782
2783 if (!cache->base_p)
2784 return UNWIND_UNAVAILABLE;
2785
2786 return UNWIND_NO_REASON;
2787}
2788
c4f35dd8 2789static void
10458914 2790amd64_sigtramp_frame_this_id (struct frame_info *this_frame,
e53bef9f 2791 void **this_cache, struct frame_id *this_id)
c4f35dd8 2792{
e53bef9f 2793 struct amd64_frame_cache *cache =
10458914 2794 amd64_sigtramp_frame_cache (this_frame, this_cache);
c4f35dd8 2795
8fbca658 2796 if (!cache->base_p)
5ce0145d
PA		 2797 (*this_id) = frame_id_build_unavailable_stack (get_frame_pc (this_frame));
2798 else if (cache->base == 0)
2799 {
2800 /* This marks the outermost frame. */
2801 return;
2802 }
2803 else
2804 (*this_id) = frame_id_build (cache->base + 16, get_frame_pc (this_frame));
c4f35dd8
MK		 2805}
2806
10458914
DJ		 2807static struct value *
2808amd64_sigtramp_frame_prev_register (struct frame_info *this_frame,
2809 void **this_cache, int regnum)
c4f35dd8
MK		 2810{
2811 /* Make sure we've initialized the cache. */
10458914 2812 amd64_sigtramp_frame_cache (this_frame, this_cache);
c4f35dd8 2813
10458914 2814 return amd64_frame_prev_register (this_frame, this_cache, regnum);
c4f35dd8
MK		 2815}
2816
10458914
DJ		 2817static int
2818amd64_sigtramp_frame_sniffer (const struct frame_unwind *self,
2819 struct frame_info *this_frame,
2820 void **this_cache)
c4f35dd8 2821{
10458914 2822 struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (this_frame));
911bc6ee
MK		 2823
2824 /* We shouldn't even bother if we don't have a sigcontext_addr
2825 handler. */
2826 if (tdep->sigcontext_addr == NULL)
10458914 2827 return 0;
911bc6ee
MK		 2828
2829 if (tdep->sigtramp_p != NULL)
2830 {
10458914
DJ		 2831 if (tdep->sigtramp_p (this_frame))
2832 return 1;
911bc6ee 2833 }
c4f35dd8 2834
911bc6ee 2835 if (tdep->sigtramp_start != 0)
1c3545ae 2836 {
10458914 2837 CORE_ADDR pc = get_frame_pc (this_frame);
1c3545ae 2838
911bc6ee
MK		 2839 gdb_assert (tdep->sigtramp_end != 0);
2840 if (pc >= tdep->sigtramp_start && pc < tdep->sigtramp_end)
10458914 2841 return 1;
1c3545ae 2842 }
c4f35dd8 2843
10458914 2844 return 0;
c4f35dd8 2845}
10458914
DJ		 2846
2847static const struct frame_unwind amd64_sigtramp_frame_unwind =
2848{
2849 SIGTRAMP_FRAME,
8fbca658 2850 amd64_sigtramp_frame_unwind_stop_reason,
10458914
DJ		 2851 amd64_sigtramp_frame_this_id,
2852 amd64_sigtramp_frame_prev_register,
2853 NULL,
2854 amd64_sigtramp_frame_sniffer
2855};
c4f35dd8
MK		 2856\f
2857
2858static CORE_ADDR
10458914 2859amd64_frame_base_address (struct frame_info *this_frame, void **this_cache)
c4f35dd8 2860{
e53bef9f 2861 struct amd64_frame_cache *cache =
10458914 2862 amd64_frame_cache (this_frame, this_cache);
c4f35dd8
MK		 2863
2864 return cache->base;
2865}
2866
e53bef9f 2867static const struct frame_base amd64_frame_base =
c4f35dd8 2868{
e53bef9f
MK		 2869 &amd64_frame_unwind,
2870 amd64_frame_base_address,
2871 amd64_frame_base_address,
2872 amd64_frame_base_address
c4f35dd8
MK		 2873};
2874
872761f4
MS		 2875/* Normal frames, but in a function epilogue. */
2876
c9cf6e20
MG		 2877/* Implement the stack_frame_destroyed_p gdbarch method.
2878
2879 The epilogue is defined here as the 'ret' instruction, which will
872761f4
MS		 2880 follow any instruction such as 'leave' or 'pop %ebp' that destroys
2881 the function's stack frame. */
2882
2883static int
c9cf6e20 2884amd64_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc)
872761f4
MS		 2885{
2886 gdb_byte insn;
43f3e411 2887 struct compunit_symtab *cust;
e0d00bc7 2888
43f3e411
DE		 2889 cust = find_pc_compunit_symtab (pc);
2890 if (cust != NULL && COMPUNIT_EPILOGUE_UNWIND_VALID (cust))
e0d00bc7 2891 return 0;
872761f4
MS		 2892
2893 if (target_read_memory (pc, &insn, 1))
2894 return 0; /* Can't read memory at pc. */
2895
2896 if (insn != 0xc3) /* 'ret' instruction. */
2897 return 0;
2898
2899 return 1;
2900}
2901
2902static int
2903amd64_epilogue_frame_sniffer (const struct frame_unwind *self,
2904 struct frame_info *this_frame,
2905 void **this_prologue_cache)
2906{
2907 if (frame_relative_level (this_frame) == 0)
c9cf6e20
MG		 2908 return amd64_stack_frame_destroyed_p (get_frame_arch (this_frame),
2909 get_frame_pc (this_frame));
872761f4
MS		 2910 else
2911 return 0;
2912}
2913
2914static struct amd64_frame_cache *
2915amd64_epilogue_frame_cache (struct frame_info *this_frame, void **this_cache)
2916{
2917 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2918 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2919 struct amd64_frame_cache *cache;
6c10c06b 2920 gdb_byte buf[8];
872761f4
MS		 2921
2922 if (*this_cache)
9a3c8263 2923 return (struct amd64_frame_cache *) *this_cache;
872761f4
MS		 2924
2925 cache = amd64_alloc_frame_cache ();
2926 *this_cache = cache;
2927
a70b8144 2928 try
8fbca658
PA		 2929 {
2930 /* Cache base will be %esp plus cache->sp_offset (-8). */
2931 get_frame_register (this_frame, AMD64_RSP_REGNUM, buf);
2932 cache->base = extract_unsigned_integer (buf, 8,
2933 byte_order) + cache->sp_offset;
2934
2935 /* Cache pc will be the frame func. */
2936 cache->pc = get_frame_pc (this_frame);
872761f4 2937
8fbca658
PA		 2938 /* The saved %esp will be at cache->base plus 16. */
2939 cache->saved_sp = cache->base + 16;
872761f4 2940
8fbca658
PA		 2941 /* The saved %eip will be at cache->base plus 8. */
2942 cache->saved_regs[AMD64_RIP_REGNUM] = cache->base + 8;
872761f4 2943
8fbca658
PA		 2944 cache->base_p = 1;
2945 }
230d2906 2946 catch (const gdb_exception_error &ex)
7556d4a4
PA		 2947 {
2948 if (ex.error != NOT_AVAILABLE_ERROR)
eedc3f4f 2949 throw;
7556d4a4 2950 }
872761f4
MS		 2951
2952 return cache;
2953}
2954
8fbca658
PA		 2955static enum unwind_stop_reason
2956amd64_epilogue_frame_unwind_stop_reason (struct frame_info *this_frame,
2957 void **this_cache)
2958{
2959 struct amd64_frame_cache *cache
2960 = amd64_epilogue_frame_cache (this_frame, this_cache);
2961
2962 if (!cache->base_p)
2963 return UNWIND_UNAVAILABLE;
2964
2965 return UNWIND_NO_REASON;
2966}
2967
872761f4
MS		 2968static void
2969amd64_epilogue_frame_this_id (struct frame_info *this_frame,
2970 void **this_cache,
2971 struct frame_id *this_id)
2972{
2973 struct amd64_frame_cache *cache = amd64_epilogue_frame_cache (this_frame,
2974 this_cache);
2975
8fbca658 2976 if (!cache->base_p)
5ce0145d
PA		 2977 (*this_id) = frame_id_build_unavailable_stack (cache->pc);
2978 else
2979 (*this_id) = frame_id_build (cache->base + 8, cache->pc);
872761f4
MS		 2980}
2981
2982static const struct frame_unwind amd64_epilogue_frame_unwind =
2983{
2984 NORMAL_FRAME,
8fbca658 2985 amd64_epilogue_frame_unwind_stop_reason,
872761f4
MS		 2986 amd64_epilogue_frame_this_id,
2987 amd64_frame_prev_register,
2988 NULL,
2989 amd64_epilogue_frame_sniffer
2990};
2991
166f4c7b 2992static struct frame_id
10458914 2993amd64_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
166f4c7b 2994{
c4f35dd8
MK		 2995 CORE_ADDR fp;
2996
10458914 2997 fp = get_frame_register_unsigned (this_frame, AMD64_RBP_REGNUM);
c4f35dd8 2998
10458914 2999 return frame_id_build (fp + 16, get_frame_pc (this_frame));
166f4c7b
ML		 3000}
3001
8b148df9
AC		 3002/* 16 byte align the SP per frame requirements. */
3003
3004static CORE_ADDR
e53bef9f 3005amd64_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
8b148df9
AC		 3006{
3007 return sp & -(CORE_ADDR)16;
3008}
473f17b0
MK		 3009\f
3010
593adc23
MK		 3011/* Supply register REGNUM from the buffer specified by FPREGS and LEN
3012 in the floating-point register set REGSET to register cache
3013 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
473f17b0
MK		 3014
3015static void
e53bef9f
MK		 3016amd64_supply_fpregset (const struct regset *regset, struct regcache *regcache,
3017 int regnum, const void *fpregs, size_t len)
473f17b0 3018{
ac7936df 3019 struct gdbarch *gdbarch = regcache->arch ();
09424cff 3020 const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
473f17b0 3021
1528345d 3022 gdb_assert (len >= tdep->sizeof_fpregset);
90f90721 3023 amd64_supply_fxsave (regcache, regnum, fpregs);
473f17b0 3024}
8b148df9 3025
593adc23
MK		 3026/* Collect register REGNUM from the register cache REGCACHE and store
3027 it in the buffer specified by FPREGS and LEN as described by the
3028 floating-point register set REGSET. If REGNUM is -1, do this for
3029 all registers in REGSET. */
3030
3031static void
3032amd64_collect_fpregset (const struct regset *regset,
3033 const struct regcache *regcache,
3034 int regnum, void *fpregs, size_t len)
3035{
ac7936df 3036 struct gdbarch *gdbarch = regcache->arch ();
09424cff 3037 const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
593adc23 3038
1528345d 3039 gdb_assert (len >= tdep->sizeof_fpregset);
593adc23
MK		 3040 amd64_collect_fxsave (regcache, regnum, fpregs);
3041}
3042
8f0435f7 3043const struct regset amd64_fpregset =
ecc37a5a
AA		 3044 {
3045 NULL, amd64_supply_fpregset, amd64_collect_fpregset
3046 };
c6b33596
MK		 3047\f
3048
436675d3
PA		 3049/* Figure out where the longjmp will land. Slurp the jmp_buf out of
3050 %rdi. We expect its value to be a pointer to the jmp_buf structure
3051 from which we extract the address that we will land at. This
3052 address is copied into PC. This routine returns non-zero on
3053 success. */
3054
3055static int
3056amd64_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc)
3057{
3058 gdb_byte buf[8];
3059 CORE_ADDR jb_addr;
3060 struct gdbarch *gdbarch = get_frame_arch (frame);
3061 int jb_pc_offset = gdbarch_tdep (gdbarch)->jb_pc_offset;
0dfff4cb 3062 int len = TYPE_LENGTH (builtin_type (gdbarch)->builtin_func_ptr);
436675d3
PA		 3063
3064 /* If JB_PC_OFFSET is -1, we have no way to find out where the
3065 longjmp will land. */
3066 if (jb_pc_offset == -1)
3067 return 0;
3068
3069 get_frame_register (frame, AMD64_RDI_REGNUM, buf);
0dfff4cb
UW		 3070 jb_addr= extract_typed_address
3071 (buf, builtin_type (gdbarch)->builtin_data_ptr);
436675d3
PA		 3072 if (target_read_memory (jb_addr + jb_pc_offset, buf, len))
3073 return 0;
3074
0dfff4cb 3075 *pc = extract_typed_address (buf, builtin_type (gdbarch)->builtin_func_ptr);
436675d3
PA		 3076
3077 return 1;
3078}
3079
cf648174
HZ		 3080static const int amd64_record_regmap[] =
3081{
3082 AMD64_RAX_REGNUM, AMD64_RCX_REGNUM, AMD64_RDX_REGNUM, AMD64_RBX_REGNUM,
3083 AMD64_RSP_REGNUM, AMD64_RBP_REGNUM, AMD64_RSI_REGNUM, AMD64_RDI_REGNUM,
3084 AMD64_R8_REGNUM, AMD64_R9_REGNUM, AMD64_R10_REGNUM, AMD64_R11_REGNUM,
3085 AMD64_R12_REGNUM, AMD64_R13_REGNUM, AMD64_R14_REGNUM, AMD64_R15_REGNUM,
3086 AMD64_RIP_REGNUM, AMD64_EFLAGS_REGNUM, AMD64_CS_REGNUM, AMD64_SS_REGNUM,
3087 AMD64_DS_REGNUM, AMD64_ES_REGNUM, AMD64_FS_REGNUM, AMD64_GS_REGNUM
3088};
3089
1d509aa6
MM		 3090/* Implement the "in_indirect_branch_thunk" gdbarch function. */
3091
3092static bool
3093amd64_in_indirect_branch_thunk (struct gdbarch *gdbarch, CORE_ADDR pc)
3094{
3095 return x86_in_indirect_branch_thunk (pc, amd64_register_names,
3096 AMD64_RAX_REGNUM,
3097 AMD64_RIP_REGNUM);
3098}
3099
2213a65d 3100void
c55a47e7 3101amd64_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch,
a04b5337 3102 const target_desc *default_tdesc)
53e95fcf 3103{
0c1a73d6 3104 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
90884b2b 3105 const struct target_desc *tdesc = info.target_desc;
05c0465e
SDJ		 3106 static const char *const stap_integer_prefixes[] = { "$", NULL };
3107 static const char *const stap_register_prefixes[] = { "%", NULL };
3108 static const char *const stap_register_indirection_prefixes[] = { "(",
3109 NULL };
3110 static const char *const stap_register_indirection_suffixes[] = { ")",
3111 NULL };
53e95fcf 3112
473f17b0
MK		 3113 /* AMD64 generally uses `fxsave' instead of `fsave' for saving its
3114 floating-point registers. */
3115 tdep->sizeof_fpregset = I387_SIZEOF_FXSAVE;
8f0435f7 3116 tdep->fpregset = &amd64_fpregset;
473f17b0 3117
90884b2b 3118 if (! tdesc_has_registers (tdesc))
c55a47e7 3119 tdesc = default_tdesc;
90884b2b
L		 3120 tdep->tdesc = tdesc;
3121
3122 tdep->num_core_regs = AMD64_NUM_GREGS + I387_NUM_REGS;
3123 tdep->register_names = amd64_register_names;
3124
01f9f808
MS		 3125 if (tdesc_find_feature (tdesc, "org.gnu.gdb.i386.avx512") != NULL)
3126 {
3127 tdep->zmmh_register_names = amd64_zmmh_names;
3128 tdep->k_register_names = amd64_k_names;
3129 tdep->xmm_avx512_register_names = amd64_xmm_avx512_names;
3130 tdep->ymm16h_register_names = amd64_ymmh_avx512_names;
3131
3132 tdep->num_zmm_regs = 32;
3133 tdep->num_xmm_avx512_regs = 16;
3134 tdep->num_ymm_avx512_regs = 16;
3135
3136 tdep->zmm0h_regnum = AMD64_ZMM0H_REGNUM;
3137 tdep->k0_regnum = AMD64_K0_REGNUM;
3138 tdep->xmm16_regnum = AMD64_XMM16_REGNUM;
3139 tdep->ymm16h_regnum = AMD64_YMM16H_REGNUM;
3140 }
3141
a055a187
L		 3142 if (tdesc_find_feature (tdesc, "org.gnu.gdb.i386.avx") != NULL)
3143 {
3144 tdep->ymmh_register_names = amd64_ymmh_names;
3145 tdep->num_ymm_regs = 16;
3146 tdep->ymm0h_regnum = AMD64_YMM0H_REGNUM;
3147 }
3148
e43e105e
WT		 3149 if (tdesc_find_feature (tdesc, "org.gnu.gdb.i386.mpx") != NULL)
3150 {
3151 tdep->mpx_register_names = amd64_mpx_names;
3152 tdep->bndcfgu_regnum = AMD64_BNDCFGU_REGNUM;
3153 tdep->bnd0r_regnum = AMD64_BND0R_REGNUM;
3154 }
3155
2735833d
WT		 3156 if (tdesc_find_feature (tdesc, "org.gnu.gdb.i386.segments") != NULL)
3157 {
1163a4b7 3158 tdep->fsbase_regnum = AMD64_FSBASE_REGNUM;
2735833d
WT		 3159 }
3160
51547df6
MS		 3161 if (tdesc_find_feature (tdesc, "org.gnu.gdb.i386.pkeys") != NULL)
3162 {
3163 tdep->pkeys_register_names = amd64_pkeys_names;
3164 tdep->pkru_regnum = AMD64_PKRU_REGNUM;
3165 tdep->num_pkeys_regs = 1;
3166 }
3167
fe01d668 3168 tdep->num_byte_regs = 20;
1ba53b71
L		 3169 tdep->num_word_regs = 16;
3170 tdep->num_dword_regs = 16;
3171 /* Avoid wiring in the MMX registers for now. */
3172 tdep->num_mmx_regs = 0;
3173
3543a589
TT		 3174 set_gdbarch_pseudo_register_read_value (gdbarch,
3175 amd64_pseudo_register_read_value);
1ba53b71
L		 3176 set_gdbarch_pseudo_register_write (gdbarch,
3177 amd64_pseudo_register_write);
62e5fd57
MK		 3178 set_gdbarch_ax_pseudo_register_collect (gdbarch,
3179 amd64_ax_pseudo_register_collect);
1ba53b71
L		 3180
3181 set_tdesc_pseudo_register_name (gdbarch, amd64_pseudo_register_name);
3182
5716833c 3183 /* AMD64 has an FPU and 16 SSE registers. */
90f90721 3184 tdep->st0_regnum = AMD64_ST0_REGNUM;
0c1a73d6 3185 tdep->num_xmm_regs = 16;
53e95fcf 3186
0c1a73d6 3187 /* This is what all the fuss is about. */
53e95fcf
JS		 3188 set_gdbarch_long_bit (gdbarch, 64);
3189 set_gdbarch_long_long_bit (gdbarch, 64);
3190 set_gdbarch_ptr_bit (gdbarch, 64);
3191
e53bef9f
MK		 3192 /* In contrast to the i386, on AMD64 a `long double' actually takes
3193 up 128 bits, even though it's still based on the i387 extended
3194 floating-point format which has only 80 significant bits. */
b83b026c
MK		 3195 set_gdbarch_long_double_bit (gdbarch, 128);
3196
e53bef9f 3197 set_gdbarch_num_regs (gdbarch, AMD64_NUM_REGS);
b83b026c
MK		 3198
3199 /* Register numbers of various important registers. */
90f90721
MK		 3200 set_gdbarch_sp_regnum (gdbarch, AMD64_RSP_REGNUM); /* %rsp */
3201 set_gdbarch_pc_regnum (gdbarch, AMD64_RIP_REGNUM); /* %rip */
3202 set_gdbarch_ps_regnum (gdbarch, AMD64_EFLAGS_REGNUM); /* %eflags */
3203 set_gdbarch_fp0_regnum (gdbarch, AMD64_ST0_REGNUM); /* %st(0) */
b83b026c 3204
e53bef9f
MK		 3205 /* The "default" register numbering scheme for AMD64 is referred to
3206 as the "DWARF Register Number Mapping" in the System V psABI.
3207 The preferred debugging format for all known AMD64 targets is
3208 actually DWARF2, and GCC doesn't seem to support DWARF (that is
3209 DWARF-1), but we provide the same mapping just in case. This
3210 mapping is also used for stabs, which GCC does support. */
3211 set_gdbarch_stab_reg_to_regnum (gdbarch, amd64_dwarf_reg_to_regnum);
e53bef9f 3212 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, amd64_dwarf_reg_to_regnum);
de220d0f 3213
c4f35dd8 3214 /* We don't override SDB_REG_RO_REGNUM, since COFF doesn't seem to
e53bef9f 3215 be in use on any of the supported AMD64 targets. */
53e95fcf 3216
c4f35dd8 3217 /* Call dummy code. */
e53bef9f
MK		 3218 set_gdbarch_push_dummy_call (gdbarch, amd64_push_dummy_call);
3219 set_gdbarch_frame_align (gdbarch, amd64_frame_align);
8b148df9 3220 set_gdbarch_frame_red_zone_size (gdbarch, 128);
53e95fcf 3221
83acabca 3222 set_gdbarch_convert_register_p (gdbarch, i387_convert_register_p);
d532c08f
MK		 3223 set_gdbarch_register_to_value (gdbarch, i387_register_to_value);
3224 set_gdbarch_value_to_register (gdbarch, i387_value_to_register);
3225
efb1c01c 3226 set_gdbarch_return_value (gdbarch, amd64_return_value);
53e95fcf 3227
e53bef9f 3228 set_gdbarch_skip_prologue (gdbarch, amd64_skip_prologue);
53e95fcf 3229
cf648174
HZ		 3230 tdep->record_regmap = amd64_record_regmap;
3231
10458914 3232 set_gdbarch_dummy_id (gdbarch, amd64_dummy_id);
53e95fcf 3233
872761f4
MS		 3234 /* Hook the function epilogue frame unwinder. This unwinder is
3235 appended to the list first, so that it supercedes the other
3236 unwinders in function epilogues. */
3237 frame_unwind_prepend_unwinder (gdbarch, &amd64_epilogue_frame_unwind);
3238
3239 /* Hook the prologue-based frame unwinders. */
10458914
DJ		 3240 frame_unwind_append_unwinder (gdbarch, &amd64_sigtramp_frame_unwind);
3241 frame_unwind_append_unwinder (gdbarch, &amd64_frame_unwind);
e53bef9f 3242 frame_base_set_default (gdbarch, &amd64_frame_base);
c6b33596 3243
436675d3 3244 set_gdbarch_get_longjmp_target (gdbarch, amd64_get_longjmp_target);
dde08ee1
PA		 3245
3246 set_gdbarch_relocate_instruction (gdbarch, amd64_relocate_instruction);
6710bf39
SS		 3247
3248 set_gdbarch_gen_return_address (gdbarch, amd64_gen_return_address);
55aa24fb
SDJ		 3249
3250 /* SystemTap variables and functions. */
05c0465e
SDJ		 3251 set_gdbarch_stap_integer_prefixes (gdbarch, stap_integer_prefixes);
3252 set_gdbarch_stap_register_prefixes (gdbarch, stap_register_prefixes);
3253 set_gdbarch_stap_register_indirection_prefixes (gdbarch,
3254 stap_register_indirection_prefixes);
3255 set_gdbarch_stap_register_indirection_suffixes (gdbarch,
3256 stap_register_indirection_suffixes);
55aa24fb
SDJ		 3257 set_gdbarch_stap_is_single_operand (gdbarch,
3258 i386_stap_is_single_operand);
3259 set_gdbarch_stap_parse_special_token (gdbarch,
3260 i386_stap_parse_special_token);
c2170eef
MM		 3261 set_gdbarch_insn_is_call (gdbarch, amd64_insn_is_call);
3262 set_gdbarch_insn_is_ret (gdbarch, amd64_insn_is_ret);
3263 set_gdbarch_insn_is_jump (gdbarch, amd64_insn_is_jump);
1d509aa6
MM		 3264
3265 set_gdbarch_in_indirect_branch_thunk (gdbarch,
3266 amd64_in_indirect_branch_thunk);
c4f35dd8 3267}
c912f608
SM		 3268
3269/* Initialize ARCH for x86-64, no osabi. */
3270
3271static void
3272amd64_none_init_abi (gdbarch_info info, gdbarch *arch)
3273{
de52b960
PA		 3274 amd64_init_abi (info, arch, amd64_target_description (X86_XSTATE_SSE_MASK,
3275 true));
c912f608 3276}
fff4548b
MK		 3277
3278static struct type *
3279amd64_x32_pseudo_register_type (struct gdbarch *gdbarch, int regnum)
3280{
3281 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3282
3283 switch (regnum - tdep->eax_regnum)
3284 {
3285 case AMD64_RBP_REGNUM: /* %ebp */
3286 case AMD64_RSP_REGNUM: /* %esp */
3287 return builtin_type (gdbarch)->builtin_data_ptr;
3288 case AMD64_RIP_REGNUM: /* %eip */
3289 return builtin_type (gdbarch)->builtin_func_ptr;
3290 }
3291
3292 return i386_pseudo_register_type (gdbarch, regnum);
3293}
3294
3295void
c55a47e7 3296amd64_x32_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch,
a04b5337 3297 const target_desc *default_tdesc)
fff4548b
MK		 3298{
3299 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
fff4548b 3300
c55a47e7 3301 amd64_init_abi (info, gdbarch, default_tdesc);
fff4548b
MK		 3302
3303 tdep->num_dword_regs = 17;
3304 set_tdesc_pseudo_register_type (gdbarch, amd64_x32_pseudo_register_type);
3305
3306 set_gdbarch_long_bit (gdbarch, 32);
3307 set_gdbarch_ptr_bit (gdbarch, 32);
3308}
90884b2b 3309
c912f608
SM		 3310/* Initialize ARCH for x64-32, no osabi. */
3311
3312static void
3313amd64_x32_none_init_abi (gdbarch_info info, gdbarch *arch)
3314{
3315 amd64_x32_init_abi (info, arch,
de52b960 3316 amd64_target_description (X86_XSTATE_SSE_MASK, true));
c912f608
SM		 3317}
3318
97de3545
JB		 3319/* Return the target description for a specified XSAVE feature mask. */
3320
3321const struct target_desc *
de52b960 3322amd64_target_description (uint64_t xcr0, bool segments)
97de3545 3323{
22916b07 3324 static target_desc *amd64_tdescs \
de52b960 3325 [2/*AVX*/][2/*MPX*/][2/*AVX512*/][2/*PKRU*/][2/*segments*/] = {};
22916b07
YQ		 3326 target_desc **tdesc;
3327
3328 tdesc = &amd64_tdescs[(xcr0 & X86_XSTATE_AVX) ? 1 : 0]
3329 [(xcr0 & X86_XSTATE_MPX) ? 1 : 0]
3330 [(xcr0 & X86_XSTATE_AVX512) ? 1 : 0]
de52b960
PA		 3331 [(xcr0 & X86_XSTATE_PKRU) ? 1 : 0]
3332 [segments ? 1 : 0];
22916b07
YQ		 3333
3334 if (*tdesc == NULL)
de52b960
PA		 3335 *tdesc = amd64_create_target_description (xcr0, false, false,
3336 segments);
22916b07
YQ		 3337
3338 return *tdesc;
97de3545
JB		 3339}
3340
90884b2b
L		 3341void
3342_initialize_amd64_tdep (void)
3343{
c912f608
SM		 3344 gdbarch_register_osabi (bfd_arch_i386, bfd_mach_x86_64, GDB_OSABI_NONE,
3345 amd64_none_init_abi);
3346 gdbarch_register_osabi (bfd_arch_i386, bfd_mach_x64_32, GDB_OSABI_NONE,
3347 amd64_x32_none_init_abi);
90884b2b 3348}
c4f35dd8
MK		 3349\f
3350
41d041d6
MK		 3351/* The 64-bit FXSAVE format differs from the 32-bit format in the
3352 sense that the instruction pointer and data pointer are simply
3353 64-bit offsets into the code segment and the data segment instead
3354 of a selector offset pair. The functions below store the upper 32
3355 bits of these pointers (instead of just the 16-bits of the segment
3356 selector). */
3357
3358/* Fill register REGNUM in REGCACHE with the appropriate
0485f6ad
MK		 3359 floating-point or SSE register value from *FXSAVE. If REGNUM is
3360 -1, do this for all registers. This function masks off any of the
3361 reserved bits in *FXSAVE. */
c4f35dd8
MK		 3362
3363void
90f90721 3364amd64_supply_fxsave (struct regcache *regcache, int regnum,
20a6ec49 3365 const void *fxsave)
c4f35dd8 3366{
ac7936df 3367 struct gdbarch *gdbarch = regcache->arch ();
20a6ec49
MD		 3368 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3369
41d041d6 3370 i387_supply_fxsave (regcache, regnum, fxsave);
c4f35dd8 3371
233dfcf0
L		 3372 if (fxsave
3373 && gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 64)
c4f35dd8 3374 {
9a3c8263 3375 const gdb_byte *regs = (const gdb_byte *) fxsave;
41d041d6 3376
20a6ec49 3377 if (regnum == -1 || regnum == I387_FISEG_REGNUM (tdep))
73e1c03f 3378 regcache->raw_supply (I387_FISEG_REGNUM (tdep), regs + 12);
20a6ec49 3379 if (regnum == -1 || regnum == I387_FOSEG_REGNUM (tdep))
73e1c03f 3380 regcache->raw_supply (I387_FOSEG_REGNUM (tdep), regs + 20);
c4f35dd8 3381 }
0c1a73d6
MK		 3382}
3383
a055a187
L		 3384/* Similar to amd64_supply_fxsave, but use XSAVE extended state. */
3385
3386void
3387amd64_supply_xsave (struct regcache *regcache, int regnum,
3388 const void *xsave)
3389{
ac7936df 3390 struct gdbarch *gdbarch = regcache->arch ();
a055a187
L		 3391 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3392
3393 i387_supply_xsave (regcache, regnum, xsave);
3394
233dfcf0
L		 3395 if (xsave
3396 && gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 64)
a055a187 3397 {
9a3c8263 3398 const gdb_byte *regs = (const gdb_byte *) xsave;
8ee22052 3399 ULONGEST clear_bv;
a055a187 3400
8ee22052
AB		 3401 clear_bv = i387_xsave_get_clear_bv (gdbarch, xsave);
3402
3403 /* If the FISEG and FOSEG registers have not been initialised yet
3404 (their CLEAR_BV bit is set) then their default values of zero will
3405 have already been setup by I387_SUPPLY_XSAVE. */
3406 if (!(clear_bv & X86_XSTATE_X87))
3407 {
3408 if (regnum == -1 || regnum == I387_FISEG_REGNUM (tdep))
73e1c03f 3409 regcache->raw_supply (I387_FISEG_REGNUM (tdep), regs + 12);
8ee22052 3410 if (regnum == -1 || regnum == I387_FOSEG_REGNUM (tdep))
73e1c03f 3411 regcache->raw_supply (I387_FOSEG_REGNUM (tdep), regs + 20);
8ee22052 3412 }
a055a187
L		 3413 }
3414}
3415
3c017e40
MK		 3416/* Fill register REGNUM (if it is a floating-point or SSE register) in
3417 *FXSAVE with the value from REGCACHE. If REGNUM is -1, do this for
3418 all registers. This function doesn't touch any of the reserved
3419 bits in *FXSAVE. */
3420
3421void
3422amd64_collect_fxsave (const struct regcache *regcache, int regnum,
3423 void *fxsave)
3424{
ac7936df 3425 struct gdbarch *gdbarch = regcache->arch ();
20a6ec49 3426 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
9a3c8263 3427 gdb_byte *regs = (gdb_byte *) fxsave;
3c017e40
MK		 3428
3429 i387_collect_fxsave (regcache, regnum, fxsave);
3430
233dfcf0 3431 if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 64)
f0ef85a5 3432 {
20a6ec49 3433 if (regnum == -1 || regnum == I387_FISEG_REGNUM (tdep))
34a79281 3434 regcache->raw_collect (I387_FISEG_REGNUM (tdep), regs + 12);
20a6ec49 3435 if (regnum == -1 || regnum == I387_FOSEG_REGNUM (tdep))
34a79281 3436 regcache->raw_collect (I387_FOSEG_REGNUM (tdep), regs + 20);
f0ef85a5 3437 }
3c017e40 3438}
a055a187 3439
7a9dd1b2 3440/* Similar to amd64_collect_fxsave, but use XSAVE extended state. */
a055a187
L		 3441
3442void
3443amd64_collect_xsave (const struct regcache *regcache, int regnum,
3444 void *xsave, int gcore)
3445{
ac7936df 3446 struct gdbarch *gdbarch = regcache->arch ();
a055a187 3447 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
9a3c8263 3448 gdb_byte *regs = (gdb_byte *) xsave;
a055a187
L		 3449
3450 i387_collect_xsave (regcache, regnum, xsave, gcore);
3451
233dfcf0 3452 if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 64)
a055a187
L		 3453 {
3454 if (regnum == -1 || regnum == I387_FISEG_REGNUM (tdep))
34a79281 3455 regcache->raw_collect (I387_FISEG_REGNUM (tdep),
a055a187
L		 3456 regs + 12);
3457 if (regnum == -1 || regnum == I387_FOSEG_REGNUM (tdep))
34a79281 3458 regcache->raw_collect (I387_FOSEG_REGNUM (tdep),
a055a187
L		 3459 regs + 20);
3460 }
3461}
GDB Binutils - Deliverables
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