Commit | Line | Data |
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252b5132 | 1 | /* Print i386 instructions for GDB, the GNU debugger. |
b3adc24a | 2 | Copyright (C) 1988-2020 Free Software Foundation, Inc. |
252b5132 | 3 | |
9b201bb5 | 4 | This file is part of the GNU opcodes library. |
20f0a1fc | 5 | |
9b201bb5 | 6 | This library is free software; you can redistribute it and/or modify |
20f0a1fc | 7 | it under the terms of the GNU General Public License as published by |
9b201bb5 NC |
8 | the Free Software Foundation; either version 3, or (at your option) |
9 | any later version. | |
20f0a1fc | 10 | |
9b201bb5 NC |
11 | It is distributed in the hope that it will be useful, but WITHOUT |
12 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
13 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
14 | License for more details. | |
20f0a1fc NC |
15 | |
16 | You should have received a copy of the GNU General Public License | |
17 | along with this program; if not, write to the Free Software | |
9b201bb5 NC |
18 | Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, |
19 | MA 02110-1301, USA. */ | |
20 | ||
20f0a1fc NC |
21 | |
22 | /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu) | |
23 | July 1988 | |
24 | modified by John Hassey (hassey@dg-rtp.dg.com) | |
25 | x86-64 support added by Jan Hubicka (jh@suse.cz) | |
26 | VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */ | |
27 | ||
28 | /* The main tables describing the instructions is essentially a copy | |
29 | of the "Opcode Map" chapter (Appendix A) of the Intel 80386 | |
30 | Programmers Manual. Usually, there is a capital letter, followed | |
31 | by a small letter. The capital letter tell the addressing mode, | |
32 | and the small letter tells about the operand size. Refer to | |
33 | the Intel manual for details. */ | |
252b5132 | 34 | |
252b5132 | 35 | #include "sysdep.h" |
88c1242d | 36 | #include "disassemble.h" |
252b5132 | 37 | #include "opintl.h" |
0b1cf022 | 38 | #include "opcode/i386.h" |
85f10a01 | 39 | #include "libiberty.h" |
5b872f7d | 40 | #include "safe-ctype.h" |
252b5132 RH |
41 | |
42 | #include <setjmp.h> | |
43 | ||
26ca5450 AJ |
44 | static int print_insn (bfd_vma, disassemble_info *); |
45 | static void dofloat (int); | |
46 | static void OP_ST (int, int); | |
47 | static void OP_STi (int, int); | |
48 | static int putop (const char *, int); | |
49 | static void oappend (const char *); | |
50 | static void append_seg (void); | |
51 | static void OP_indirE (int, int); | |
52 | static void print_operand_value (char *, int, bfd_vma); | |
c0f3af97 | 53 | static void OP_E_register (int, int); |
c1e679ec | 54 | static void OP_E_memory (int, int); |
5d669648 | 55 | static void print_displacement (char *, bfd_vma); |
26ca5450 AJ |
56 | static void OP_E (int, int); |
57 | static void OP_G (int, int); | |
58 | static bfd_vma get64 (void); | |
59 | static bfd_signed_vma get32 (void); | |
60 | static bfd_signed_vma get32s (void); | |
61 | static int get16 (void); | |
62 | static void set_op (bfd_vma, int); | |
b844680a | 63 | static void OP_Skip_MODRM (int, int); |
26ca5450 AJ |
64 | static void OP_REG (int, int); |
65 | static void OP_IMREG (int, int); | |
66 | static void OP_I (int, int); | |
67 | static void OP_I64 (int, int); | |
68 | static void OP_sI (int, int); | |
69 | static void OP_J (int, int); | |
70 | static void OP_SEG (int, int); | |
71 | static void OP_DIR (int, int); | |
72 | static void OP_OFF (int, int); | |
73 | static void OP_OFF64 (int, int); | |
74 | static void ptr_reg (int, int); | |
75 | static void OP_ESreg (int, int); | |
76 | static void OP_DSreg (int, int); | |
77 | static void OP_C (int, int); | |
78 | static void OP_D (int, int); | |
79 | static void OP_T (int, int); | |
6f74c397 | 80 | static void OP_R (int, int); |
26ca5450 AJ |
81 | static void OP_MMX (int, int); |
82 | static void OP_XMM (int, int); | |
83 | static void OP_EM (int, int); | |
84 | static void OP_EX (int, int); | |
4d9567e0 MM |
85 | static void OP_EMC (int,int); |
86 | static void OP_MXC (int,int); | |
26ca5450 AJ |
87 | static void OP_MS (int, int); |
88 | static void OP_XS (int, int); | |
cc0ec051 | 89 | static void OP_M (int, int); |
c0f3af97 L |
90 | static void OP_VEX (int, int); |
91 | static void OP_EX_Vex (int, int); | |
922d8de8 | 92 | static void OP_EX_VexW (int, int); |
a683cc34 | 93 | static void OP_EX_VexImmW (int, int); |
c0f3af97 | 94 | static void OP_XMM_Vex (int, int); |
922d8de8 | 95 | static void OP_XMM_VexW (int, int); |
43234a1e | 96 | static void OP_Rounding (int, int); |
c0f3af97 L |
97 | static void OP_REG_VexI4 (int, int); |
98 | static void PCLMUL_Fixup (int, int); | |
c0f3af97 | 99 | static void VCMP_Fixup (int, int); |
43234a1e | 100 | static void VPCMP_Fixup (int, int); |
be92cb14 | 101 | static void VPCOM_Fixup (int, int); |
cc0ec051 | 102 | static void OP_0f07 (int, int); |
b844680a L |
103 | static void OP_Monitor (int, int); |
104 | static void OP_Mwait (int, int); | |
46e883c5 L |
105 | static void NOP_Fixup1 (int, int); |
106 | static void NOP_Fixup2 (int, int); | |
26ca5450 | 107 | static void OP_3DNowSuffix (int, int); |
ad19981d | 108 | static void CMP_Fixup (int, int); |
26ca5450 | 109 | static void BadOp (void); |
35c52694 | 110 | static void REP_Fixup (int, int); |
d835a58b | 111 | static void SEP_Fixup (int, int); |
7e8b059b | 112 | static void BND_Fixup (int, int); |
04ef582a | 113 | static void NOTRACK_Fixup (int, int); |
42164a71 L |
114 | static void HLE_Fixup1 (int, int); |
115 | static void HLE_Fixup2 (int, int); | |
116 | static void HLE_Fixup3 (int, int); | |
f5804c90 | 117 | static void CMPXCHG8B_Fixup (int, int); |
42903f7f | 118 | static void XMM_Fixup (int, int); |
381d071f | 119 | static void CRC32_Fixup (int, int); |
eacc9c89 | 120 | static void FXSAVE_Fixup (int, int); |
15c7c1d8 | 121 | static void PCMPESTR_Fixup (int, int); |
f88c9eb0 SP |
122 | static void OP_LWPCB_E (int, int); |
123 | static void OP_LWP_E (int, int); | |
5dd85c99 SP |
124 | static void OP_Vex_2src_1 (int, int); |
125 | static void OP_Vex_2src_2 (int, int); | |
c1e679ec | 126 | |
f1f8f695 | 127 | static void MOVBE_Fixup (int, int); |
bc31405e | 128 | static void MOVSXD_Fixup (int, int); |
252b5132 | 129 | |
43234a1e L |
130 | static void OP_Mask (int, int); |
131 | ||
6608db57 | 132 | struct dis_private { |
252b5132 RH |
133 | /* Points to first byte not fetched. */ |
134 | bfd_byte *max_fetched; | |
0b1cf022 | 135 | bfd_byte the_buffer[MAX_MNEM_SIZE]; |
252b5132 | 136 | bfd_vma insn_start; |
e396998b | 137 | int orig_sizeflag; |
8df14d78 | 138 | OPCODES_SIGJMP_BUF bailout; |
252b5132 RH |
139 | }; |
140 | ||
cb712a9e L |
141 | enum address_mode |
142 | { | |
143 | mode_16bit, | |
144 | mode_32bit, | |
145 | mode_64bit | |
146 | }; | |
147 | ||
148 | enum address_mode address_mode; | |
52b15da3 | 149 | |
5076851f ILT |
150 | /* Flags for the prefixes for the current instruction. See below. */ |
151 | static int prefixes; | |
152 | ||
52b15da3 JH |
153 | /* REX prefix the current instruction. See below. */ |
154 | static int rex; | |
155 | /* Bits of REX we've already used. */ | |
156 | static int rex_used; | |
52b15da3 JH |
157 | /* Mark parts used in the REX prefix. When we are testing for |
158 | empty prefix (for 8bit register REX extension), just mask it | |
159 | out. Otherwise test for REX bit is excuse for existence of REX | |
160 | only in case value is nonzero. */ | |
161 | #define USED_REX(value) \ | |
162 | { \ | |
163 | if (value) \ | |
161a04f6 L |
164 | { \ |
165 | if ((rex & value)) \ | |
166 | rex_used |= (value) | REX_OPCODE; \ | |
167 | } \ | |
52b15da3 | 168 | else \ |
161a04f6 | 169 | rex_used |= REX_OPCODE; \ |
52b15da3 JH |
170 | } |
171 | ||
7d421014 ILT |
172 | /* Flags for prefixes which we somehow handled when printing the |
173 | current instruction. */ | |
174 | static int used_prefixes; | |
175 | ||
5076851f ILT |
176 | /* Flags stored in PREFIXES. */ |
177 | #define PREFIX_REPZ 1 | |
178 | #define PREFIX_REPNZ 2 | |
179 | #define PREFIX_LOCK 4 | |
180 | #define PREFIX_CS 8 | |
181 | #define PREFIX_SS 0x10 | |
182 | #define PREFIX_DS 0x20 | |
183 | #define PREFIX_ES 0x40 | |
184 | #define PREFIX_FS 0x80 | |
185 | #define PREFIX_GS 0x100 | |
186 | #define PREFIX_DATA 0x200 | |
187 | #define PREFIX_ADDR 0x400 | |
188 | #define PREFIX_FWAIT 0x800 | |
189 | ||
252b5132 RH |
190 | /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive) |
191 | to ADDR (exclusive) are valid. Returns 1 for success, longjmps | |
192 | on error. */ | |
193 | #define FETCH_DATA(info, addr) \ | |
6608db57 | 194 | ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \ |
252b5132 RH |
195 | ? 1 : fetch_data ((info), (addr))) |
196 | ||
197 | static int | |
26ca5450 | 198 | fetch_data (struct disassemble_info *info, bfd_byte *addr) |
252b5132 RH |
199 | { |
200 | int status; | |
6608db57 | 201 | struct dis_private *priv = (struct dis_private *) info->private_data; |
252b5132 RH |
202 | bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer); |
203 | ||
0b1cf022 | 204 | if (addr <= priv->the_buffer + MAX_MNEM_SIZE) |
272c9217 JB |
205 | status = (*info->read_memory_func) (start, |
206 | priv->max_fetched, | |
207 | addr - priv->max_fetched, | |
208 | info); | |
209 | else | |
210 | status = -1; | |
252b5132 RH |
211 | if (status != 0) |
212 | { | |
7d421014 | 213 | /* If we did manage to read at least one byte, then |
db6eb5be AM |
214 | print_insn_i386 will do something sensible. Otherwise, print |
215 | an error. We do that here because this is where we know | |
216 | STATUS. */ | |
7d421014 | 217 | if (priv->max_fetched == priv->the_buffer) |
5076851f | 218 | (*info->memory_error_func) (status, start, info); |
8df14d78 | 219 | OPCODES_SIGLONGJMP (priv->bailout, 1); |
252b5132 RH |
220 | } |
221 | else | |
222 | priv->max_fetched = addr; | |
223 | return 1; | |
224 | } | |
225 | ||
bf890a93 | 226 | /* Possible values for prefix requirement. */ |
507bd325 L |
227 | #define PREFIX_IGNORED_SHIFT 16 |
228 | #define PREFIX_IGNORED_REPZ (PREFIX_REPZ << PREFIX_IGNORED_SHIFT) | |
229 | #define PREFIX_IGNORED_REPNZ (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT) | |
230 | #define PREFIX_IGNORED_DATA (PREFIX_DATA << PREFIX_IGNORED_SHIFT) | |
231 | #define PREFIX_IGNORED_ADDR (PREFIX_ADDR << PREFIX_IGNORED_SHIFT) | |
232 | #define PREFIX_IGNORED_LOCK (PREFIX_LOCK << PREFIX_IGNORED_SHIFT) | |
233 | ||
234 | /* Opcode prefixes. */ | |
235 | #define PREFIX_OPCODE (PREFIX_REPZ \ | |
236 | | PREFIX_REPNZ \ | |
237 | | PREFIX_DATA) | |
238 | ||
239 | /* Prefixes ignored. */ | |
240 | #define PREFIX_IGNORED (PREFIX_IGNORED_REPZ \ | |
241 | | PREFIX_IGNORED_REPNZ \ | |
242 | | PREFIX_IGNORED_DATA) | |
bf890a93 | 243 | |
ce518a5f | 244 | #define XX { NULL, 0 } |
507bd325 | 245 | #define Bad_Opcode NULL, { { NULL, 0 } }, 0 |
ce518a5f L |
246 | |
247 | #define Eb { OP_E, b_mode } | |
7e8b059b | 248 | #define Ebnd { OP_E, bnd_mode } |
b6169b20 | 249 | #define EbS { OP_E, b_swap_mode } |
9f79e886 | 250 | #define EbndS { OP_E, bnd_swap_mode } |
ce518a5f | 251 | #define Ev { OP_E, v_mode } |
de89d0a3 | 252 | #define Eva { OP_E, va_mode } |
7e8b059b | 253 | #define Ev_bnd { OP_E, v_bnd_mode } |
b6169b20 | 254 | #define EvS { OP_E, v_swap_mode } |
ce518a5f L |
255 | #define Ed { OP_E, d_mode } |
256 | #define Edq { OP_E, dq_mode } | |
257 | #define Edqw { OP_E, dqw_mode } | |
42903f7f | 258 | #define Edqb { OP_E, dqb_mode } |
1ba585e8 IT |
259 | #define Edb { OP_E, db_mode } |
260 | #define Edw { OP_E, dw_mode } | |
42903f7f | 261 | #define Edqd { OP_E, dqd_mode } |
09335d05 | 262 | #define Eq { OP_E, q_mode } |
07f5af7d | 263 | #define indirEv { OP_indirE, indir_v_mode } |
ce518a5f L |
264 | #define indirEp { OP_indirE, f_mode } |
265 | #define stackEv { OP_E, stack_v_mode } | |
266 | #define Em { OP_E, m_mode } | |
267 | #define Ew { OP_E, w_mode } | |
268 | #define M { OP_M, 0 } /* lea, lgdt, etc. */ | |
34b772a6 | 269 | #define Ma { OP_M, a_mode } |
b844680a | 270 | #define Mb { OP_M, b_mode } |
d9a5e5e5 | 271 | #define Md { OP_M, d_mode } |
f1f8f695 | 272 | #define Mo { OP_M, o_mode } |
ce518a5f L |
273 | #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */ |
274 | #define Mq { OP_M, q_mode } | |
d276ec69 | 275 | #define Mv_bnd { OP_M, v_bndmk_mode } |
4ee52178 | 276 | #define Mx { OP_M, x_mode } |
c0f3af97 | 277 | #define Mxmm { OP_M, xmm_mode } |
ce518a5f | 278 | #define Gb { OP_G, b_mode } |
7e8b059b | 279 | #define Gbnd { OP_G, bnd_mode } |
ce518a5f L |
280 | #define Gv { OP_G, v_mode } |
281 | #define Gd { OP_G, d_mode } | |
282 | #define Gdq { OP_G, dq_mode } | |
283 | #define Gm { OP_G, m_mode } | |
c0a30a9f | 284 | #define Gva { OP_G, va_mode } |
ce518a5f | 285 | #define Gw { OP_G, w_mode } |
6f74c397 | 286 | #define Rd { OP_R, d_mode } |
43234a1e | 287 | #define Rdq { OP_R, dq_mode } |
6f74c397 | 288 | #define Rm { OP_R, m_mode } |
ce518a5f L |
289 | #define Ib { OP_I, b_mode } |
290 | #define sIb { OP_sI, b_mode } /* sign extened byte */ | |
e3949f17 | 291 | #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */ |
ce518a5f | 292 | #define Iv { OP_I, v_mode } |
7bb15c6f | 293 | #define sIv { OP_sI, v_mode } |
ce518a5f | 294 | #define Iv64 { OP_I64, v_mode } |
c1dc7af5 | 295 | #define Id { OP_I, d_mode } |
ce518a5f L |
296 | #define Iw { OP_I, w_mode } |
297 | #define I1 { OP_I, const_1_mode } | |
298 | #define Jb { OP_J, b_mode } | |
299 | #define Jv { OP_J, v_mode } | |
376cd056 | 300 | #define Jdqw { OP_J, dqw_mode } |
ce518a5f L |
301 | #define Cm { OP_C, m_mode } |
302 | #define Dm { OP_D, m_mode } | |
303 | #define Td { OP_T, d_mode } | |
b844680a | 304 | #define Skip_MODRM { OP_Skip_MODRM, 0 } |
ce518a5f L |
305 | |
306 | #define RMeAX { OP_REG, eAX_reg } | |
307 | #define RMeBX { OP_REG, eBX_reg } | |
308 | #define RMeCX { OP_REG, eCX_reg } | |
309 | #define RMeDX { OP_REG, eDX_reg } | |
310 | #define RMeSP { OP_REG, eSP_reg } | |
311 | #define RMeBP { OP_REG, eBP_reg } | |
312 | #define RMeSI { OP_REG, eSI_reg } | |
313 | #define RMeDI { OP_REG, eDI_reg } | |
314 | #define RMrAX { OP_REG, rAX_reg } | |
315 | #define RMrBX { OP_REG, rBX_reg } | |
316 | #define RMrCX { OP_REG, rCX_reg } | |
317 | #define RMrDX { OP_REG, rDX_reg } | |
318 | #define RMrSP { OP_REG, rSP_reg } | |
319 | #define RMrBP { OP_REG, rBP_reg } | |
320 | #define RMrSI { OP_REG, rSI_reg } | |
321 | #define RMrDI { OP_REG, rDI_reg } | |
322 | #define RMAL { OP_REG, al_reg } | |
ce518a5f L |
323 | #define RMCL { OP_REG, cl_reg } |
324 | #define RMDL { OP_REG, dl_reg } | |
325 | #define RMBL { OP_REG, bl_reg } | |
326 | #define RMAH { OP_REG, ah_reg } | |
327 | #define RMCH { OP_REG, ch_reg } | |
328 | #define RMDH { OP_REG, dh_reg } | |
329 | #define RMBH { OP_REG, bh_reg } | |
330 | #define RMAX { OP_REG, ax_reg } | |
331 | #define RMDX { OP_REG, dx_reg } | |
332 | ||
333 | #define eAX { OP_IMREG, eAX_reg } | |
334 | #define eBX { OP_IMREG, eBX_reg } | |
335 | #define eCX { OP_IMREG, eCX_reg } | |
336 | #define eDX { OP_IMREG, eDX_reg } | |
337 | #define eSP { OP_IMREG, eSP_reg } | |
338 | #define eBP { OP_IMREG, eBP_reg } | |
339 | #define eSI { OP_IMREG, eSI_reg } | |
340 | #define eDI { OP_IMREG, eDI_reg } | |
341 | #define AL { OP_IMREG, al_reg } | |
342 | #define CL { OP_IMREG, cl_reg } | |
343 | #define DL { OP_IMREG, dl_reg } | |
344 | #define BL { OP_IMREG, bl_reg } | |
345 | #define AH { OP_IMREG, ah_reg } | |
346 | #define CH { OP_IMREG, ch_reg } | |
347 | #define DH { OP_IMREG, dh_reg } | |
348 | #define BH { OP_IMREG, bh_reg } | |
349 | #define AX { OP_IMREG, ax_reg } | |
350 | #define DX { OP_IMREG, dx_reg } | |
351 | #define zAX { OP_IMREG, z_mode_ax_reg } | |
352 | #define indirDX { OP_IMREG, indir_dx_reg } | |
353 | ||
354 | #define Sw { OP_SEG, w_mode } | |
355 | #define Sv { OP_SEG, v_mode } | |
356 | #define Ap { OP_DIR, 0 } | |
357 | #define Ob { OP_OFF64, b_mode } | |
358 | #define Ov { OP_OFF64, v_mode } | |
359 | #define Xb { OP_DSreg, eSI_reg } | |
360 | #define Xv { OP_DSreg, eSI_reg } | |
361 | #define Xz { OP_DSreg, eSI_reg } | |
362 | #define Yb { OP_ESreg, eDI_reg } | |
363 | #define Yv { OP_ESreg, eDI_reg } | |
364 | #define DSBX { OP_DSreg, eBX_reg } | |
365 | ||
366 | #define es { OP_REG, es_reg } | |
367 | #define ss { OP_REG, ss_reg } | |
368 | #define cs { OP_REG, cs_reg } | |
369 | #define ds { OP_REG, ds_reg } | |
370 | #define fs { OP_REG, fs_reg } | |
371 | #define gs { OP_REG, gs_reg } | |
372 | ||
373 | #define MX { OP_MMX, 0 } | |
374 | #define XM { OP_XMM, 0 } | |
539f890d | 375 | #define XMScalar { OP_XMM, scalar_mode } |
6c30d220 | 376 | #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode } |
c0f3af97 | 377 | #define XMM { OP_XMM, xmm_mode } |
43234a1e | 378 | #define XMxmmq { OP_XMM, xmmq_mode } |
ce518a5f | 379 | #define EM { OP_EM, v_mode } |
b6169b20 | 380 | #define EMS { OP_EM, v_swap_mode } |
09a2c6cf | 381 | #define EMd { OP_EM, d_mode } |
14051056 | 382 | #define EMx { OP_EM, x_mode } |
53467f57 | 383 | #define EXbScalar { OP_EX, b_scalar_mode } |
8976381e | 384 | #define EXw { OP_EX, w_mode } |
53467f57 | 385 | #define EXwScalar { OP_EX, w_scalar_mode } |
09a2c6cf | 386 | #define EXd { OP_EX, d_mode } |
fa99fab2 | 387 | #define EXdS { OP_EX, d_swap_mode } |
09a2c6cf | 388 | #define EXq { OP_EX, q_mode } |
b6169b20 | 389 | #define EXqS { OP_EX, q_swap_mode } |
09a2c6cf | 390 | #define EXx { OP_EX, x_mode } |
b6169b20 | 391 | #define EXxS { OP_EX, x_swap_mode } |
c0f3af97 | 392 | #define EXxmm { OP_EX, xmm_mode } |
43234a1e | 393 | #define EXymm { OP_EX, ymm_mode } |
c0f3af97 | 394 | #define EXxmmq { OP_EX, xmmq_mode } |
43234a1e | 395 | #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode } |
6c30d220 L |
396 | #define EXxmm_mb { OP_EX, xmm_mb_mode } |
397 | #define EXxmm_mw { OP_EX, xmm_mw_mode } | |
398 | #define EXxmm_md { OP_EX, xmm_md_mode } | |
399 | #define EXxmm_mq { OP_EX, xmm_mq_mode } | |
400 | #define EXxmmdw { OP_EX, xmmdw_mode } | |
401 | #define EXxmmqd { OP_EX, xmmqd_mode } | |
c0f3af97 | 402 | #define EXymmq { OP_EX, ymmq_mode } |
1c480963 | 403 | #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode } |
43234a1e L |
404 | #define EXEvexXGscat { OP_EX, evex_x_gscat_mode } |
405 | #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode } | |
ce518a5f L |
406 | #define MS { OP_MS, v_mode } |
407 | #define XS { OP_XS, v_mode } | |
09335d05 | 408 | #define EMCq { OP_EMC, q_mode } |
ce518a5f | 409 | #define MXC { OP_MXC, 0 } |
ce518a5f | 410 | #define OPSUF { OP_3DNowSuffix, 0 } |
d835a58b | 411 | #define SEP { SEP_Fixup, 0 } |
ad19981d | 412 | #define CMP { CMP_Fixup, 0 } |
42903f7f | 413 | #define XMM0 { XMM_Fixup, 0 } |
eacc9c89 | 414 | #define FXSAVE { FXSAVE_Fixup, 0 } |
5dd85c99 SP |
415 | #define Vex_2src_1 { OP_Vex_2src_1, 0 } |
416 | #define Vex_2src_2 { OP_Vex_2src_2, 0 } | |
252b5132 | 417 | |
c0f3af97 | 418 | #define Vex { OP_VEX, vex_mode } |
539f890d | 419 | #define VexScalar { OP_VEX, vex_scalar_mode } |
6c30d220 | 420 | #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode } |
c0f3af97 L |
421 | #define Vex128 { OP_VEX, vex128_mode } |
422 | #define Vex256 { OP_VEX, vex256_mode } | |
cb21baef | 423 | #define VexGdq { OP_VEX, dq_mode } |
539f890d | 424 | #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode } |
539f890d | 425 | #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode } |
922d8de8 DR |
426 | #define EXVexW { OP_EX_VexW, x_mode } |
427 | #define EXdVexW { OP_EX_VexW, d_mode } | |
428 | #define EXqVexW { OP_EX_VexW, q_mode } | |
a683cc34 | 429 | #define EXVexImmW { OP_EX_VexImmW, x_mode } |
539f890d | 430 | #define XMVexScalar { OP_XMM_Vex, scalar_mode } |
922d8de8 | 431 | #define XMVexW { OP_XMM_VexW, 0 } |
c0f3af97 L |
432 | #define XMVexI4 { OP_REG_VexI4, x_mode } |
433 | #define PCLMUL { PCLMUL_Fixup, 0 } | |
c0f3af97 | 434 | #define VCMP { VCMP_Fixup, 0 } |
43234a1e | 435 | #define VPCMP { VPCMP_Fixup, 0 } |
be92cb14 | 436 | #define VPCOM { VPCOM_Fixup, 0 } |
43234a1e L |
437 | |
438 | #define EXxEVexR { OP_Rounding, evex_rounding_mode } | |
70df6fc9 | 439 | #define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode } |
43234a1e L |
440 | #define EXxEVexS { OP_Rounding, evex_sae_mode } |
441 | ||
442 | #define XMask { OP_Mask, mask_mode } | |
443 | #define MaskG { OP_G, mask_mode } | |
444 | #define MaskE { OP_E, mask_mode } | |
1ba585e8 | 445 | #define MaskBDE { OP_E, mask_bd_mode } |
43234a1e L |
446 | #define MaskR { OP_R, mask_mode } |
447 | #define MaskVex { OP_VEX, mask_mode } | |
c0f3af97 | 448 | |
6c30d220 | 449 | #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode } |
5fc35d96 | 450 | #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode } |
6c30d220 | 451 | #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode } |
5fc35d96 | 452 | #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode } |
6c30d220 | 453 | |
35c52694 | 454 | /* Used handle "rep" prefix for string instructions. */ |
ce518a5f L |
455 | #define Xbr { REP_Fixup, eSI_reg } |
456 | #define Xvr { REP_Fixup, eSI_reg } | |
457 | #define Ybr { REP_Fixup, eDI_reg } | |
458 | #define Yvr { REP_Fixup, eDI_reg } | |
459 | #define Yzr { REP_Fixup, eDI_reg } | |
460 | #define indirDXr { REP_Fixup, indir_dx_reg } | |
461 | #define ALr { REP_Fixup, al_reg } | |
462 | #define eAXr { REP_Fixup, eAX_reg } | |
463 | ||
42164a71 L |
464 | /* Used handle HLE prefix for lockable instructions. */ |
465 | #define Ebh1 { HLE_Fixup1, b_mode } | |
466 | #define Evh1 { HLE_Fixup1, v_mode } | |
467 | #define Ebh2 { HLE_Fixup2, b_mode } | |
468 | #define Evh2 { HLE_Fixup2, v_mode } | |
469 | #define Ebh3 { HLE_Fixup3, b_mode } | |
470 | #define Evh3 { HLE_Fixup3, v_mode } | |
471 | ||
7e8b059b | 472 | #define BND { BND_Fixup, 0 } |
04ef582a | 473 | #define NOTRACK { NOTRACK_Fixup, 0 } |
7e8b059b | 474 | |
ce518a5f L |
475 | #define cond_jump_flag { NULL, cond_jump_mode } |
476 | #define loop_jcxz_flag { NULL, loop_jcxz_mode } | |
3ffd33cf | 477 | |
252b5132 | 478 | /* bits in sizeflag */ |
252b5132 | 479 | #define SUFFIX_ALWAYS 4 |
252b5132 RH |
480 | #define AFLAG 2 |
481 | #define DFLAG 1 | |
482 | ||
51e7da1b L |
483 | enum |
484 | { | |
485 | /* byte operand */ | |
486 | b_mode = 1, | |
487 | /* byte operand with operand swapped */ | |
3873ba12 | 488 | b_swap_mode, |
e3949f17 L |
489 | /* byte operand, sign extend like 'T' suffix */ |
490 | b_T_mode, | |
51e7da1b | 491 | /* operand size depends on prefixes */ |
3873ba12 | 492 | v_mode, |
51e7da1b | 493 | /* operand size depends on prefixes with operand swapped */ |
3873ba12 | 494 | v_swap_mode, |
de89d0a3 IT |
495 | /* operand size depends on address prefix */ |
496 | va_mode, | |
51e7da1b | 497 | /* word operand */ |
3873ba12 | 498 | w_mode, |
51e7da1b | 499 | /* double word operand */ |
3873ba12 | 500 | d_mode, |
51e7da1b | 501 | /* double word operand with operand swapped */ |
3873ba12 | 502 | d_swap_mode, |
51e7da1b | 503 | /* quad word operand */ |
3873ba12 | 504 | q_mode, |
51e7da1b | 505 | /* quad word operand with operand swapped */ |
3873ba12 | 506 | q_swap_mode, |
51e7da1b | 507 | /* ten-byte operand */ |
3873ba12 | 508 | t_mode, |
43234a1e L |
509 | /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand. In EVEX with |
510 | broadcast enabled. */ | |
3873ba12 | 511 | x_mode, |
43234a1e L |
512 | /* Similar to x_mode, but with different EVEX mem shifts. */ |
513 | evex_x_gscat_mode, | |
514 | /* Similar to x_mode, but with disabled broadcast. */ | |
515 | evex_x_nobcst_mode, | |
516 | /* Similar to x_mode, but with operands swapped and disabled broadcast | |
517 | in EVEX. */ | |
3873ba12 | 518 | x_swap_mode, |
51e7da1b | 519 | /* 16-byte XMM operand */ |
3873ba12 | 520 | xmm_mode, |
43234a1e L |
521 | /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword |
522 | memory operand (depending on vector length). Broadcast isn't | |
523 | allowed. */ | |
3873ba12 | 524 | xmmq_mode, |
43234a1e L |
525 | /* Same as xmmq_mode, but broadcast is allowed. */ |
526 | evex_half_bcst_xmmq_mode, | |
6c30d220 L |
527 | /* XMM register or byte memory operand */ |
528 | xmm_mb_mode, | |
529 | /* XMM register or word memory operand */ | |
530 | xmm_mw_mode, | |
531 | /* XMM register or double word memory operand */ | |
532 | xmm_md_mode, | |
533 | /* XMM register or quad word memory operand */ | |
534 | xmm_mq_mode, | |
43234a1e | 535 | /* 16-byte XMM, word, double word or quad word operand. */ |
6c30d220 | 536 | xmmdw_mode, |
43234a1e | 537 | /* 16-byte XMM, double word, quad word operand or xmm word operand. */ |
6c30d220 | 538 | xmmqd_mode, |
43234a1e L |
539 | /* 32-byte YMM operand */ |
540 | ymm_mode, | |
541 | /* quad word, ymmword or zmmword memory operand. */ | |
3873ba12 | 542 | ymmq_mode, |
6c30d220 L |
543 | /* 32-byte YMM or 16-byte word operand */ |
544 | ymmxmm_mode, | |
51e7da1b | 545 | /* d_mode in 32bit, q_mode in 64bit mode. */ |
3873ba12 | 546 | m_mode, |
51e7da1b | 547 | /* pair of v_mode operands */ |
3873ba12 L |
548 | a_mode, |
549 | cond_jump_mode, | |
550 | loop_jcxz_mode, | |
bc31405e | 551 | movsxd_mode, |
7e8b059b | 552 | v_bnd_mode, |
d276ec69 JB |
553 | /* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode. */ |
554 | v_bndmk_mode, | |
51e7da1b | 555 | /* operand size depends on REX prefixes. */ |
3873ba12 | 556 | dq_mode, |
376cd056 JB |
557 | /* registers like dq_mode, memory like w_mode, displacements like |
558 | v_mode without considering Intel64 ISA. */ | |
3873ba12 | 559 | dqw_mode, |
9f79e886 | 560 | /* bounds operand */ |
7e8b059b | 561 | bnd_mode, |
9f79e886 JB |
562 | /* bounds operand with operand swapped */ |
563 | bnd_swap_mode, | |
51e7da1b | 564 | /* 4- or 6-byte pointer operand */ |
3873ba12 L |
565 | f_mode, |
566 | const_1_mode, | |
07f5af7d L |
567 | /* v_mode for indirect branch opcodes. */ |
568 | indir_v_mode, | |
51e7da1b | 569 | /* v_mode for stack-related opcodes. */ |
3873ba12 | 570 | stack_v_mode, |
51e7da1b | 571 | /* non-quad operand size depends on prefixes */ |
3873ba12 | 572 | z_mode, |
51e7da1b | 573 | /* 16-byte operand */ |
3873ba12 | 574 | o_mode, |
51e7da1b | 575 | /* registers like dq_mode, memory like b_mode. */ |
3873ba12 | 576 | dqb_mode, |
1ba585e8 IT |
577 | /* registers like d_mode, memory like b_mode. */ |
578 | db_mode, | |
579 | /* registers like d_mode, memory like w_mode. */ | |
580 | dw_mode, | |
51e7da1b | 581 | /* registers like dq_mode, memory like d_mode. */ |
3873ba12 | 582 | dqd_mode, |
51e7da1b | 583 | /* normal vex mode */ |
3873ba12 | 584 | vex_mode, |
51e7da1b | 585 | /* 128bit vex mode */ |
3873ba12 | 586 | vex128_mode, |
51e7da1b | 587 | /* 256bit vex mode */ |
3873ba12 | 588 | vex256_mode, |
d55ee72f | 589 | |
825bd36c | 590 | /* Operand size depends on the VEX.W bit, with VSIB dword indices. */ |
6c30d220 | 591 | vex_vsib_d_w_dq_mode, |
5fc35d96 IT |
592 | /* Similar to vex_vsib_d_w_dq_mode, with smaller memory. */ |
593 | vex_vsib_d_w_d_mode, | |
825bd36c | 594 | /* Operand size depends on the VEX.W bit, with VSIB qword indices. */ |
6c30d220 | 595 | vex_vsib_q_w_dq_mode, |
5fc35d96 IT |
596 | /* Similar to vex_vsib_q_w_dq_mode, with smaller memory. */ |
597 | vex_vsib_q_w_d_mode, | |
6c30d220 | 598 | |
539f890d L |
599 | /* scalar, ignore vector length. */ |
600 | scalar_mode, | |
53467f57 IT |
601 | /* like b_mode, ignore vector length. */ |
602 | b_scalar_mode, | |
603 | /* like w_mode, ignore vector length. */ | |
604 | w_scalar_mode, | |
539f890d L |
605 | /* like d_swap_mode, ignore vector length. */ |
606 | d_scalar_swap_mode, | |
539f890d L |
607 | /* like q_swap_mode, ignore vector length. */ |
608 | q_scalar_swap_mode, | |
609 | /* like vex_mode, ignore vector length. */ | |
610 | vex_scalar_mode, | |
825bd36c | 611 | /* Operand size depends on the VEX.W bit, ignore vector length. */ |
1c480963 | 612 | vex_scalar_w_dq_mode, |
539f890d | 613 | |
43234a1e L |
614 | /* Static rounding. */ |
615 | evex_rounding_mode, | |
70df6fc9 L |
616 | /* Static rounding, 64-bit mode only. */ |
617 | evex_rounding_64_mode, | |
43234a1e L |
618 | /* Supress all exceptions. */ |
619 | evex_sae_mode, | |
620 | ||
621 | /* Mask register operand. */ | |
622 | mask_mode, | |
1ba585e8 IT |
623 | /* Mask register operand. */ |
624 | mask_bd_mode, | |
43234a1e | 625 | |
3873ba12 L |
626 | es_reg, |
627 | cs_reg, | |
628 | ss_reg, | |
629 | ds_reg, | |
630 | fs_reg, | |
631 | gs_reg, | |
d55ee72f | 632 | |
3873ba12 L |
633 | eAX_reg, |
634 | eCX_reg, | |
635 | eDX_reg, | |
636 | eBX_reg, | |
637 | eSP_reg, | |
638 | eBP_reg, | |
639 | eSI_reg, | |
640 | eDI_reg, | |
d55ee72f | 641 | |
3873ba12 L |
642 | al_reg, |
643 | cl_reg, | |
644 | dl_reg, | |
645 | bl_reg, | |
646 | ah_reg, | |
647 | ch_reg, | |
648 | dh_reg, | |
649 | bh_reg, | |
d55ee72f | 650 | |
3873ba12 L |
651 | ax_reg, |
652 | cx_reg, | |
653 | dx_reg, | |
654 | bx_reg, | |
655 | sp_reg, | |
656 | bp_reg, | |
657 | si_reg, | |
658 | di_reg, | |
d55ee72f | 659 | |
3873ba12 L |
660 | rAX_reg, |
661 | rCX_reg, | |
662 | rDX_reg, | |
663 | rBX_reg, | |
664 | rSP_reg, | |
665 | rBP_reg, | |
666 | rSI_reg, | |
667 | rDI_reg, | |
d55ee72f | 668 | |
3873ba12 L |
669 | z_mode_ax_reg, |
670 | indir_dx_reg | |
51e7da1b | 671 | }; |
252b5132 | 672 | |
51e7da1b L |
673 | enum |
674 | { | |
675 | FLOATCODE = 1, | |
3873ba12 L |
676 | USE_REG_TABLE, |
677 | USE_MOD_TABLE, | |
678 | USE_RM_TABLE, | |
679 | USE_PREFIX_TABLE, | |
680 | USE_X86_64_TABLE, | |
681 | USE_3BYTE_TABLE, | |
f88c9eb0 | 682 | USE_XOP_8F_TABLE, |
3873ba12 L |
683 | USE_VEX_C4_TABLE, |
684 | USE_VEX_C5_TABLE, | |
9e30b8e0 | 685 | USE_VEX_LEN_TABLE, |
43234a1e | 686 | USE_VEX_W_TABLE, |
04e2a182 L |
687 | USE_EVEX_TABLE, |
688 | USE_EVEX_LEN_TABLE | |
51e7da1b | 689 | }; |
6439fc28 | 690 | |
bf890a93 | 691 | #define FLOAT NULL, { { NULL, FLOATCODE } }, 0 |
4efba78c | 692 | |
bf890a93 IT |
693 | #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }, 0 |
694 | #define DIS386_PREFIX(T, I, P) NULL, { { NULL, (T)}, { NULL, (I) } }, P | |
1ceb70f8 L |
695 | #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I)) |
696 | #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I)) | |
697 | #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I)) | |
698 | #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I)) | |
4e7d34a6 L |
699 | #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I)) |
700 | #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I)) | |
bf890a93 | 701 | #define THREE_BYTE_TABLE_PREFIX(I, P) DIS386_PREFIX (USE_3BYTE_TABLE, (I), P) |
f88c9eb0 | 702 | #define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I)) |
c0f3af97 L |
703 | #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I)) |
704 | #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I)) | |
705 | #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I)) | |
9e30b8e0 | 706 | #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I)) |
43234a1e | 707 | #define EVEX_TABLE(I) DIS386 (USE_EVEX_TABLE, (I)) |
04e2a182 | 708 | #define EVEX_LEN_TABLE(I) DIS386 (USE_EVEX_LEN_TABLE, (I)) |
1ceb70f8 | 709 | |
51e7da1b L |
710 | enum |
711 | { | |
712 | REG_80 = 0, | |
3873ba12 | 713 | REG_81, |
7148c369 | 714 | REG_83, |
3873ba12 L |
715 | REG_8F, |
716 | REG_C0, | |
717 | REG_C1, | |
718 | REG_C6, | |
719 | REG_C7, | |
720 | REG_D0, | |
721 | REG_D1, | |
722 | REG_D2, | |
723 | REG_D3, | |
724 | REG_F6, | |
725 | REG_F7, | |
726 | REG_FE, | |
727 | REG_FF, | |
728 | REG_0F00, | |
729 | REG_0F01, | |
730 | REG_0F0D, | |
731 | REG_0F18, | |
f8687e93 JB |
732 | REG_0F1C_P_0_MOD_0, |
733 | REG_0F1E_P_1_MOD_3, | |
3873ba12 L |
734 | REG_0F71, |
735 | REG_0F72, | |
736 | REG_0F73, | |
737 | REG_0FA6, | |
738 | REG_0FA7, | |
739 | REG_0FAE, | |
740 | REG_0FBA, | |
741 | REG_0FC7, | |
592a252b L |
742 | REG_VEX_0F71, |
743 | REG_VEX_0F72, | |
744 | REG_VEX_0F73, | |
745 | REG_VEX_0FAE, | |
f12dc422 | 746 | REG_VEX_0F38F3, |
f88c9eb0 | 747 | REG_XOP_LWPCB, |
2a2a0f38 QN |
748 | REG_XOP_LWP, |
749 | REG_XOP_TBM_01, | |
43234a1e L |
750 | REG_XOP_TBM_02, |
751 | ||
1ba585e8 | 752 | REG_EVEX_0F71, |
43234a1e L |
753 | REG_EVEX_0F72, |
754 | REG_EVEX_0F73, | |
755 | REG_EVEX_0F38C6, | |
756 | REG_EVEX_0F38C7 | |
51e7da1b | 757 | }; |
1ceb70f8 | 758 | |
51e7da1b L |
759 | enum |
760 | { | |
761 | MOD_8D = 0, | |
42164a71 L |
762 | MOD_C6_REG_7, |
763 | MOD_C7_REG_7, | |
4a357820 MZ |
764 | MOD_FF_REG_3, |
765 | MOD_FF_REG_5, | |
3873ba12 L |
766 | MOD_0F01_REG_0, |
767 | MOD_0F01_REG_1, | |
768 | MOD_0F01_REG_2, | |
769 | MOD_0F01_REG_3, | |
8eab4136 | 770 | MOD_0F01_REG_5, |
3873ba12 L |
771 | MOD_0F01_REG_7, |
772 | MOD_0F12_PREFIX_0, | |
18897deb | 773 | MOD_0F12_PREFIX_2, |
3873ba12 L |
774 | MOD_0F13, |
775 | MOD_0F16_PREFIX_0, | |
18897deb | 776 | MOD_0F16_PREFIX_2, |
3873ba12 L |
777 | MOD_0F17, |
778 | MOD_0F18_REG_0, | |
779 | MOD_0F18_REG_1, | |
780 | MOD_0F18_REG_2, | |
781 | MOD_0F18_REG_3, | |
d7189fa5 RM |
782 | MOD_0F18_REG_4, |
783 | MOD_0F18_REG_5, | |
784 | MOD_0F18_REG_6, | |
785 | MOD_0F18_REG_7, | |
7e8b059b L |
786 | MOD_0F1A_PREFIX_0, |
787 | MOD_0F1B_PREFIX_0, | |
788 | MOD_0F1B_PREFIX_1, | |
c48935d7 | 789 | MOD_0F1C_PREFIX_0, |
603555e5 | 790 | MOD_0F1E_PREFIX_1, |
3873ba12 L |
791 | MOD_0F24, |
792 | MOD_0F26, | |
793 | MOD_0F2B_PREFIX_0, | |
794 | MOD_0F2B_PREFIX_1, | |
795 | MOD_0F2B_PREFIX_2, | |
796 | MOD_0F2B_PREFIX_3, | |
a5aaedb9 | 797 | MOD_0F50, |
3873ba12 L |
798 | MOD_0F71_REG_2, |
799 | MOD_0F71_REG_4, | |
800 | MOD_0F71_REG_6, | |
801 | MOD_0F72_REG_2, | |
802 | MOD_0F72_REG_4, | |
803 | MOD_0F72_REG_6, | |
804 | MOD_0F73_REG_2, | |
805 | MOD_0F73_REG_3, | |
806 | MOD_0F73_REG_6, | |
807 | MOD_0F73_REG_7, | |
808 | MOD_0FAE_REG_0, | |
809 | MOD_0FAE_REG_1, | |
810 | MOD_0FAE_REG_2, | |
811 | MOD_0FAE_REG_3, | |
812 | MOD_0FAE_REG_4, | |
813 | MOD_0FAE_REG_5, | |
814 | MOD_0FAE_REG_6, | |
815 | MOD_0FAE_REG_7, | |
816 | MOD_0FB2, | |
817 | MOD_0FB4, | |
818 | MOD_0FB5, | |
a8484f96 | 819 | MOD_0FC3, |
963f3586 IT |
820 | MOD_0FC7_REG_3, |
821 | MOD_0FC7_REG_4, | |
822 | MOD_0FC7_REG_5, | |
3873ba12 L |
823 | MOD_0FC7_REG_6, |
824 | MOD_0FC7_REG_7, | |
825 | MOD_0FD7, | |
826 | MOD_0FE7_PREFIX_2, | |
827 | MOD_0FF0_PREFIX_3, | |
828 | MOD_0F382A_PREFIX_2, | |
603555e5 L |
829 | MOD_0F38F5_PREFIX_2, |
830 | MOD_0F38F6_PREFIX_0, | |
5d79adc4 | 831 | MOD_0F38F8_PREFIX_1, |
c0a30a9f | 832 | MOD_0F38F8_PREFIX_2, |
5d79adc4 | 833 | MOD_0F38F8_PREFIX_3, |
c0a30a9f | 834 | MOD_0F38F9_PREFIX_0, |
3873ba12 L |
835 | MOD_62_32BIT, |
836 | MOD_C4_32BIT, | |
837 | MOD_C5_32BIT, | |
592a252b | 838 | MOD_VEX_0F12_PREFIX_0, |
18897deb | 839 | MOD_VEX_0F12_PREFIX_2, |
592a252b L |
840 | MOD_VEX_0F13, |
841 | MOD_VEX_0F16_PREFIX_0, | |
18897deb | 842 | MOD_VEX_0F16_PREFIX_2, |
592a252b L |
843 | MOD_VEX_0F17, |
844 | MOD_VEX_0F2B, | |
ab4e4ed5 AF |
845 | MOD_VEX_W_0_0F41_P_0_LEN_1, |
846 | MOD_VEX_W_1_0F41_P_0_LEN_1, | |
847 | MOD_VEX_W_0_0F41_P_2_LEN_1, | |
848 | MOD_VEX_W_1_0F41_P_2_LEN_1, | |
849 | MOD_VEX_W_0_0F42_P_0_LEN_1, | |
850 | MOD_VEX_W_1_0F42_P_0_LEN_1, | |
851 | MOD_VEX_W_0_0F42_P_2_LEN_1, | |
852 | MOD_VEX_W_1_0F42_P_2_LEN_1, | |
853 | MOD_VEX_W_0_0F44_P_0_LEN_1, | |
854 | MOD_VEX_W_1_0F44_P_0_LEN_1, | |
855 | MOD_VEX_W_0_0F44_P_2_LEN_1, | |
856 | MOD_VEX_W_1_0F44_P_2_LEN_1, | |
857 | MOD_VEX_W_0_0F45_P_0_LEN_1, | |
858 | MOD_VEX_W_1_0F45_P_0_LEN_1, | |
859 | MOD_VEX_W_0_0F45_P_2_LEN_1, | |
860 | MOD_VEX_W_1_0F45_P_2_LEN_1, | |
861 | MOD_VEX_W_0_0F46_P_0_LEN_1, | |
862 | MOD_VEX_W_1_0F46_P_0_LEN_1, | |
863 | MOD_VEX_W_0_0F46_P_2_LEN_1, | |
864 | MOD_VEX_W_1_0F46_P_2_LEN_1, | |
865 | MOD_VEX_W_0_0F47_P_0_LEN_1, | |
866 | MOD_VEX_W_1_0F47_P_0_LEN_1, | |
867 | MOD_VEX_W_0_0F47_P_2_LEN_1, | |
868 | MOD_VEX_W_1_0F47_P_2_LEN_1, | |
869 | MOD_VEX_W_0_0F4A_P_0_LEN_1, | |
870 | MOD_VEX_W_1_0F4A_P_0_LEN_1, | |
871 | MOD_VEX_W_0_0F4A_P_2_LEN_1, | |
872 | MOD_VEX_W_1_0F4A_P_2_LEN_1, | |
873 | MOD_VEX_W_0_0F4B_P_0_LEN_1, | |
874 | MOD_VEX_W_1_0F4B_P_0_LEN_1, | |
875 | MOD_VEX_W_0_0F4B_P_2_LEN_1, | |
592a252b L |
876 | MOD_VEX_0F50, |
877 | MOD_VEX_0F71_REG_2, | |
878 | MOD_VEX_0F71_REG_4, | |
879 | MOD_VEX_0F71_REG_6, | |
880 | MOD_VEX_0F72_REG_2, | |
881 | MOD_VEX_0F72_REG_4, | |
882 | MOD_VEX_0F72_REG_6, | |
883 | MOD_VEX_0F73_REG_2, | |
884 | MOD_VEX_0F73_REG_3, | |
885 | MOD_VEX_0F73_REG_6, | |
886 | MOD_VEX_0F73_REG_7, | |
ab4e4ed5 AF |
887 | MOD_VEX_W_0_0F91_P_0_LEN_0, |
888 | MOD_VEX_W_1_0F91_P_0_LEN_0, | |
889 | MOD_VEX_W_0_0F91_P_2_LEN_0, | |
890 | MOD_VEX_W_1_0F91_P_2_LEN_0, | |
891 | MOD_VEX_W_0_0F92_P_0_LEN_0, | |
892 | MOD_VEX_W_0_0F92_P_2_LEN_0, | |
58a211d2 | 893 | MOD_VEX_0F92_P_3_LEN_0, |
ab4e4ed5 AF |
894 | MOD_VEX_W_0_0F93_P_0_LEN_0, |
895 | MOD_VEX_W_0_0F93_P_2_LEN_0, | |
58a211d2 | 896 | MOD_VEX_0F93_P_3_LEN_0, |
ab4e4ed5 AF |
897 | MOD_VEX_W_0_0F98_P_0_LEN_0, |
898 | MOD_VEX_W_1_0F98_P_0_LEN_0, | |
899 | MOD_VEX_W_0_0F98_P_2_LEN_0, | |
900 | MOD_VEX_W_1_0F98_P_2_LEN_0, | |
901 | MOD_VEX_W_0_0F99_P_0_LEN_0, | |
902 | MOD_VEX_W_1_0F99_P_0_LEN_0, | |
903 | MOD_VEX_W_0_0F99_P_2_LEN_0, | |
904 | MOD_VEX_W_1_0F99_P_2_LEN_0, | |
592a252b L |
905 | MOD_VEX_0FAE_REG_2, |
906 | MOD_VEX_0FAE_REG_3, | |
907 | MOD_VEX_0FD7_PREFIX_2, | |
908 | MOD_VEX_0FE7_PREFIX_2, | |
909 | MOD_VEX_0FF0_PREFIX_3, | |
592a252b L |
910 | MOD_VEX_0F381A_PREFIX_2, |
911 | MOD_VEX_0F382A_PREFIX_2, | |
912 | MOD_VEX_0F382C_PREFIX_2, | |
913 | MOD_VEX_0F382D_PREFIX_2, | |
914 | MOD_VEX_0F382E_PREFIX_2, | |
6c30d220 L |
915 | MOD_VEX_0F382F_PREFIX_2, |
916 | MOD_VEX_0F385A_PREFIX_2, | |
917 | MOD_VEX_0F388C_PREFIX_2, | |
918 | MOD_VEX_0F388E_PREFIX_2, | |
ab4e4ed5 AF |
919 | MOD_VEX_W_0_0F3A30_P_2_LEN_0, |
920 | MOD_VEX_W_1_0F3A30_P_2_LEN_0, | |
921 | MOD_VEX_W_0_0F3A31_P_2_LEN_0, | |
922 | MOD_VEX_W_1_0F3A31_P_2_LEN_0, | |
923 | MOD_VEX_W_0_0F3A32_P_2_LEN_0, | |
924 | MOD_VEX_W_1_0F3A32_P_2_LEN_0, | |
925 | MOD_VEX_W_0_0F3A33_P_2_LEN_0, | |
926 | MOD_VEX_W_1_0F3A33_P_2_LEN_0, | |
43234a1e | 927 | |
43234a1e | 928 | MOD_EVEX_0F12_PREFIX_0, |
97e6786a JB |
929 | MOD_EVEX_0F12_PREFIX_2, |
930 | MOD_EVEX_0F13, | |
43234a1e | 931 | MOD_EVEX_0F16_PREFIX_0, |
97e6786a JB |
932 | MOD_EVEX_0F16_PREFIX_2, |
933 | MOD_EVEX_0F17, | |
934 | MOD_EVEX_0F2B, | |
bc152a17 JB |
935 | MOD_EVEX_0F381A_P_2_W_0, |
936 | MOD_EVEX_0F381A_P_2_W_1, | |
937 | MOD_EVEX_0F381B_P_2_W_0, | |
938 | MOD_EVEX_0F381B_P_2_W_1, | |
939 | MOD_EVEX_0F385A_P_2_W_0, | |
940 | MOD_EVEX_0F385A_P_2_W_1, | |
941 | MOD_EVEX_0F385B_P_2_W_0, | |
942 | MOD_EVEX_0F385B_P_2_W_1, | |
43234a1e L |
943 | MOD_EVEX_0F38C6_REG_1, |
944 | MOD_EVEX_0F38C6_REG_2, | |
945 | MOD_EVEX_0F38C6_REG_5, | |
946 | MOD_EVEX_0F38C6_REG_6, | |
947 | MOD_EVEX_0F38C7_REG_1, | |
948 | MOD_EVEX_0F38C7_REG_2, | |
949 | MOD_EVEX_0F38C7_REG_5, | |
950 | MOD_EVEX_0F38C7_REG_6 | |
51e7da1b | 951 | }; |
1ceb70f8 | 952 | |
51e7da1b L |
953 | enum |
954 | { | |
42164a71 L |
955 | RM_C6_REG_7 = 0, |
956 | RM_C7_REG_7, | |
957 | RM_0F01_REG_0, | |
3873ba12 L |
958 | RM_0F01_REG_1, |
959 | RM_0F01_REG_2, | |
960 | RM_0F01_REG_3, | |
f8687e93 JB |
961 | RM_0F01_REG_5_MOD_3, |
962 | RM_0F01_REG_7_MOD_3, | |
963 | RM_0F1E_P_1_MOD_3_REG_7, | |
964 | RM_0FAE_REG_6_MOD_3_P_0, | |
965 | RM_0FAE_REG_7_MOD_3, | |
51e7da1b | 966 | }; |
1ceb70f8 | 967 | |
51e7da1b L |
968 | enum |
969 | { | |
970 | PREFIX_90 = 0, | |
a847e322 | 971 | PREFIX_0F01_REG_3_RM_1, |
f8687e93 JB |
972 | PREFIX_0F01_REG_5_MOD_0, |
973 | PREFIX_0F01_REG_5_MOD_3_RM_0, | |
bb651e8b | 974 | PREFIX_0F01_REG_5_MOD_3_RM_1, |
f8687e93 | 975 | PREFIX_0F01_REG_5_MOD_3_RM_2, |
267b8516 JB |
976 | PREFIX_0F01_REG_7_MOD_3_RM_2, |
977 | PREFIX_0F01_REG_7_MOD_3_RM_3, | |
3233d7d0 | 978 | PREFIX_0F09, |
3873ba12 L |
979 | PREFIX_0F10, |
980 | PREFIX_0F11, | |
981 | PREFIX_0F12, | |
982 | PREFIX_0F16, | |
7e8b059b L |
983 | PREFIX_0F1A, |
984 | PREFIX_0F1B, | |
c48935d7 | 985 | PREFIX_0F1C, |
603555e5 | 986 | PREFIX_0F1E, |
3873ba12 L |
987 | PREFIX_0F2A, |
988 | PREFIX_0F2B, | |
989 | PREFIX_0F2C, | |
990 | PREFIX_0F2D, | |
991 | PREFIX_0F2E, | |
992 | PREFIX_0F2F, | |
993 | PREFIX_0F51, | |
994 | PREFIX_0F52, | |
995 | PREFIX_0F53, | |
996 | PREFIX_0F58, | |
997 | PREFIX_0F59, | |
998 | PREFIX_0F5A, | |
999 | PREFIX_0F5B, | |
1000 | PREFIX_0F5C, | |
1001 | PREFIX_0F5D, | |
1002 | PREFIX_0F5E, | |
1003 | PREFIX_0F5F, | |
1004 | PREFIX_0F60, | |
1005 | PREFIX_0F61, | |
1006 | PREFIX_0F62, | |
1007 | PREFIX_0F6C, | |
1008 | PREFIX_0F6D, | |
1009 | PREFIX_0F6F, | |
1010 | PREFIX_0F70, | |
1011 | PREFIX_0F73_REG_3, | |
1012 | PREFIX_0F73_REG_7, | |
1013 | PREFIX_0F78, | |
1014 | PREFIX_0F79, | |
1015 | PREFIX_0F7C, | |
1016 | PREFIX_0F7D, | |
1017 | PREFIX_0F7E, | |
1018 | PREFIX_0F7F, | |
f8687e93 JB |
1019 | PREFIX_0FAE_REG_0_MOD_3, |
1020 | PREFIX_0FAE_REG_1_MOD_3, | |
1021 | PREFIX_0FAE_REG_2_MOD_3, | |
1022 | PREFIX_0FAE_REG_3_MOD_3, | |
1023 | PREFIX_0FAE_REG_4_MOD_0, | |
1024 | PREFIX_0FAE_REG_4_MOD_3, | |
1025 | PREFIX_0FAE_REG_5_MOD_0, | |
1026 | PREFIX_0FAE_REG_5_MOD_3, | |
1027 | PREFIX_0FAE_REG_6_MOD_0, | |
1028 | PREFIX_0FAE_REG_6_MOD_3, | |
1029 | PREFIX_0FAE_REG_7_MOD_0, | |
3873ba12 | 1030 | PREFIX_0FB8, |
f12dc422 | 1031 | PREFIX_0FBC, |
3873ba12 L |
1032 | PREFIX_0FBD, |
1033 | PREFIX_0FC2, | |
f8687e93 JB |
1034 | PREFIX_0FC3_MOD_0, |
1035 | PREFIX_0FC7_REG_6_MOD_0, | |
1036 | PREFIX_0FC7_REG_6_MOD_3, | |
1037 | PREFIX_0FC7_REG_7_MOD_3, | |
3873ba12 L |
1038 | PREFIX_0FD0, |
1039 | PREFIX_0FD6, | |
1040 | PREFIX_0FE6, | |
1041 | PREFIX_0FE7, | |
1042 | PREFIX_0FF0, | |
1043 | PREFIX_0FF7, | |
1044 | PREFIX_0F3810, | |
1045 | PREFIX_0F3814, | |
1046 | PREFIX_0F3815, | |
1047 | PREFIX_0F3817, | |
1048 | PREFIX_0F3820, | |
1049 | PREFIX_0F3821, | |
1050 | PREFIX_0F3822, | |
1051 | PREFIX_0F3823, | |
1052 | PREFIX_0F3824, | |
1053 | PREFIX_0F3825, | |
1054 | PREFIX_0F3828, | |
1055 | PREFIX_0F3829, | |
1056 | PREFIX_0F382A, | |
1057 | PREFIX_0F382B, | |
1058 | PREFIX_0F3830, | |
1059 | PREFIX_0F3831, | |
1060 | PREFIX_0F3832, | |
1061 | PREFIX_0F3833, | |
1062 | PREFIX_0F3834, | |
1063 | PREFIX_0F3835, | |
1064 | PREFIX_0F3837, | |
1065 | PREFIX_0F3838, | |
1066 | PREFIX_0F3839, | |
1067 | PREFIX_0F383A, | |
1068 | PREFIX_0F383B, | |
1069 | PREFIX_0F383C, | |
1070 | PREFIX_0F383D, | |
1071 | PREFIX_0F383E, | |
1072 | PREFIX_0F383F, | |
1073 | PREFIX_0F3840, | |
1074 | PREFIX_0F3841, | |
1075 | PREFIX_0F3880, | |
1076 | PREFIX_0F3881, | |
6c30d220 | 1077 | PREFIX_0F3882, |
a0046408 L |
1078 | PREFIX_0F38C8, |
1079 | PREFIX_0F38C9, | |
1080 | PREFIX_0F38CA, | |
1081 | PREFIX_0F38CB, | |
1082 | PREFIX_0F38CC, | |
1083 | PREFIX_0F38CD, | |
48521003 | 1084 | PREFIX_0F38CF, |
3873ba12 L |
1085 | PREFIX_0F38DB, |
1086 | PREFIX_0F38DC, | |
1087 | PREFIX_0F38DD, | |
1088 | PREFIX_0F38DE, | |
1089 | PREFIX_0F38DF, | |
1090 | PREFIX_0F38F0, | |
1091 | PREFIX_0F38F1, | |
603555e5 | 1092 | PREFIX_0F38F5, |
e2e1fcde | 1093 | PREFIX_0F38F6, |
c0a30a9f L |
1094 | PREFIX_0F38F8, |
1095 | PREFIX_0F38F9, | |
3873ba12 L |
1096 | PREFIX_0F3A08, |
1097 | PREFIX_0F3A09, | |
1098 | PREFIX_0F3A0A, | |
1099 | PREFIX_0F3A0B, | |
1100 | PREFIX_0F3A0C, | |
1101 | PREFIX_0F3A0D, | |
1102 | PREFIX_0F3A0E, | |
1103 | PREFIX_0F3A14, | |
1104 | PREFIX_0F3A15, | |
1105 | PREFIX_0F3A16, | |
1106 | PREFIX_0F3A17, | |
1107 | PREFIX_0F3A20, | |
1108 | PREFIX_0F3A21, | |
1109 | PREFIX_0F3A22, | |
1110 | PREFIX_0F3A40, | |
1111 | PREFIX_0F3A41, | |
1112 | PREFIX_0F3A42, | |
1113 | PREFIX_0F3A44, | |
1114 | PREFIX_0F3A60, | |
1115 | PREFIX_0F3A61, | |
1116 | PREFIX_0F3A62, | |
1117 | PREFIX_0F3A63, | |
a0046408 | 1118 | PREFIX_0F3ACC, |
48521003 IT |
1119 | PREFIX_0F3ACE, |
1120 | PREFIX_0F3ACF, | |
3873ba12 | 1121 | PREFIX_0F3ADF, |
592a252b L |
1122 | PREFIX_VEX_0F10, |
1123 | PREFIX_VEX_0F11, | |
1124 | PREFIX_VEX_0F12, | |
1125 | PREFIX_VEX_0F16, | |
1126 | PREFIX_VEX_0F2A, | |
1127 | PREFIX_VEX_0F2C, | |
1128 | PREFIX_VEX_0F2D, | |
1129 | PREFIX_VEX_0F2E, | |
1130 | PREFIX_VEX_0F2F, | |
43234a1e L |
1131 | PREFIX_VEX_0F41, |
1132 | PREFIX_VEX_0F42, | |
1133 | PREFIX_VEX_0F44, | |
1134 | PREFIX_VEX_0F45, | |
1135 | PREFIX_VEX_0F46, | |
1136 | PREFIX_VEX_0F47, | |
1ba585e8 | 1137 | PREFIX_VEX_0F4A, |
43234a1e | 1138 | PREFIX_VEX_0F4B, |
592a252b L |
1139 | PREFIX_VEX_0F51, |
1140 | PREFIX_VEX_0F52, | |
1141 | PREFIX_VEX_0F53, | |
1142 | PREFIX_VEX_0F58, | |
1143 | PREFIX_VEX_0F59, | |
1144 | PREFIX_VEX_0F5A, | |
1145 | PREFIX_VEX_0F5B, | |
1146 | PREFIX_VEX_0F5C, | |
1147 | PREFIX_VEX_0F5D, | |
1148 | PREFIX_VEX_0F5E, | |
1149 | PREFIX_VEX_0F5F, | |
1150 | PREFIX_VEX_0F60, | |
1151 | PREFIX_VEX_0F61, | |
1152 | PREFIX_VEX_0F62, | |
1153 | PREFIX_VEX_0F63, | |
1154 | PREFIX_VEX_0F64, | |
1155 | PREFIX_VEX_0F65, | |
1156 | PREFIX_VEX_0F66, | |
1157 | PREFIX_VEX_0F67, | |
1158 | PREFIX_VEX_0F68, | |
1159 | PREFIX_VEX_0F69, | |
1160 | PREFIX_VEX_0F6A, | |
1161 | PREFIX_VEX_0F6B, | |
1162 | PREFIX_VEX_0F6C, | |
1163 | PREFIX_VEX_0F6D, | |
1164 | PREFIX_VEX_0F6E, | |
1165 | PREFIX_VEX_0F6F, | |
1166 | PREFIX_VEX_0F70, | |
1167 | PREFIX_VEX_0F71_REG_2, | |
1168 | PREFIX_VEX_0F71_REG_4, | |
1169 | PREFIX_VEX_0F71_REG_6, | |
1170 | PREFIX_VEX_0F72_REG_2, | |
1171 | PREFIX_VEX_0F72_REG_4, | |
1172 | PREFIX_VEX_0F72_REG_6, | |
1173 | PREFIX_VEX_0F73_REG_2, | |
1174 | PREFIX_VEX_0F73_REG_3, | |
1175 | PREFIX_VEX_0F73_REG_6, | |
1176 | PREFIX_VEX_0F73_REG_7, | |
1177 | PREFIX_VEX_0F74, | |
1178 | PREFIX_VEX_0F75, | |
1179 | PREFIX_VEX_0F76, | |
1180 | PREFIX_VEX_0F77, | |
1181 | PREFIX_VEX_0F7C, | |
1182 | PREFIX_VEX_0F7D, | |
1183 | PREFIX_VEX_0F7E, | |
1184 | PREFIX_VEX_0F7F, | |
43234a1e L |
1185 | PREFIX_VEX_0F90, |
1186 | PREFIX_VEX_0F91, | |
1187 | PREFIX_VEX_0F92, | |
1188 | PREFIX_VEX_0F93, | |
1189 | PREFIX_VEX_0F98, | |
1ba585e8 | 1190 | PREFIX_VEX_0F99, |
592a252b L |
1191 | PREFIX_VEX_0FC2, |
1192 | PREFIX_VEX_0FC4, | |
1193 | PREFIX_VEX_0FC5, | |
1194 | PREFIX_VEX_0FD0, | |
1195 | PREFIX_VEX_0FD1, | |
1196 | PREFIX_VEX_0FD2, | |
1197 | PREFIX_VEX_0FD3, | |
1198 | PREFIX_VEX_0FD4, | |
1199 | PREFIX_VEX_0FD5, | |
1200 | PREFIX_VEX_0FD6, | |
1201 | PREFIX_VEX_0FD7, | |
1202 | PREFIX_VEX_0FD8, | |
1203 | PREFIX_VEX_0FD9, | |
1204 | PREFIX_VEX_0FDA, | |
1205 | PREFIX_VEX_0FDB, | |
1206 | PREFIX_VEX_0FDC, | |
1207 | PREFIX_VEX_0FDD, | |
1208 | PREFIX_VEX_0FDE, | |
1209 | PREFIX_VEX_0FDF, | |
1210 | PREFIX_VEX_0FE0, | |
1211 | PREFIX_VEX_0FE1, | |
1212 | PREFIX_VEX_0FE2, | |
1213 | PREFIX_VEX_0FE3, | |
1214 | PREFIX_VEX_0FE4, | |
1215 | PREFIX_VEX_0FE5, | |
1216 | PREFIX_VEX_0FE6, | |
1217 | PREFIX_VEX_0FE7, | |
1218 | PREFIX_VEX_0FE8, | |
1219 | PREFIX_VEX_0FE9, | |
1220 | PREFIX_VEX_0FEA, | |
1221 | PREFIX_VEX_0FEB, | |
1222 | PREFIX_VEX_0FEC, | |
1223 | PREFIX_VEX_0FED, | |
1224 | PREFIX_VEX_0FEE, | |
1225 | PREFIX_VEX_0FEF, | |
1226 | PREFIX_VEX_0FF0, | |
1227 | PREFIX_VEX_0FF1, | |
1228 | PREFIX_VEX_0FF2, | |
1229 | PREFIX_VEX_0FF3, | |
1230 | PREFIX_VEX_0FF4, | |
1231 | PREFIX_VEX_0FF5, | |
1232 | PREFIX_VEX_0FF6, | |
1233 | PREFIX_VEX_0FF7, | |
1234 | PREFIX_VEX_0FF8, | |
1235 | PREFIX_VEX_0FF9, | |
1236 | PREFIX_VEX_0FFA, | |
1237 | PREFIX_VEX_0FFB, | |
1238 | PREFIX_VEX_0FFC, | |
1239 | PREFIX_VEX_0FFD, | |
1240 | PREFIX_VEX_0FFE, | |
1241 | PREFIX_VEX_0F3800, | |
1242 | PREFIX_VEX_0F3801, | |
1243 | PREFIX_VEX_0F3802, | |
1244 | PREFIX_VEX_0F3803, | |
1245 | PREFIX_VEX_0F3804, | |
1246 | PREFIX_VEX_0F3805, | |
1247 | PREFIX_VEX_0F3806, | |
1248 | PREFIX_VEX_0F3807, | |
1249 | PREFIX_VEX_0F3808, | |
1250 | PREFIX_VEX_0F3809, | |
1251 | PREFIX_VEX_0F380A, | |
1252 | PREFIX_VEX_0F380B, | |
1253 | PREFIX_VEX_0F380C, | |
1254 | PREFIX_VEX_0F380D, | |
1255 | PREFIX_VEX_0F380E, | |
1256 | PREFIX_VEX_0F380F, | |
1257 | PREFIX_VEX_0F3813, | |
6c30d220 | 1258 | PREFIX_VEX_0F3816, |
592a252b L |
1259 | PREFIX_VEX_0F3817, |
1260 | PREFIX_VEX_0F3818, | |
1261 | PREFIX_VEX_0F3819, | |
1262 | PREFIX_VEX_0F381A, | |
1263 | PREFIX_VEX_0F381C, | |
1264 | PREFIX_VEX_0F381D, | |
1265 | PREFIX_VEX_0F381E, | |
1266 | PREFIX_VEX_0F3820, | |
1267 | PREFIX_VEX_0F3821, | |
1268 | PREFIX_VEX_0F3822, | |
1269 | PREFIX_VEX_0F3823, | |
1270 | PREFIX_VEX_0F3824, | |
1271 | PREFIX_VEX_0F3825, | |
1272 | PREFIX_VEX_0F3828, | |
1273 | PREFIX_VEX_0F3829, | |
1274 | PREFIX_VEX_0F382A, | |
1275 | PREFIX_VEX_0F382B, | |
1276 | PREFIX_VEX_0F382C, | |
1277 | PREFIX_VEX_0F382D, | |
1278 | PREFIX_VEX_0F382E, | |
1279 | PREFIX_VEX_0F382F, | |
1280 | PREFIX_VEX_0F3830, | |
1281 | PREFIX_VEX_0F3831, | |
1282 | PREFIX_VEX_0F3832, | |
1283 | PREFIX_VEX_0F3833, | |
1284 | PREFIX_VEX_0F3834, | |
1285 | PREFIX_VEX_0F3835, | |
6c30d220 | 1286 | PREFIX_VEX_0F3836, |
592a252b L |
1287 | PREFIX_VEX_0F3837, |
1288 | PREFIX_VEX_0F3838, | |
1289 | PREFIX_VEX_0F3839, | |
1290 | PREFIX_VEX_0F383A, | |
1291 | PREFIX_VEX_0F383B, | |
1292 | PREFIX_VEX_0F383C, | |
1293 | PREFIX_VEX_0F383D, | |
1294 | PREFIX_VEX_0F383E, | |
1295 | PREFIX_VEX_0F383F, | |
1296 | PREFIX_VEX_0F3840, | |
1297 | PREFIX_VEX_0F3841, | |
6c30d220 L |
1298 | PREFIX_VEX_0F3845, |
1299 | PREFIX_VEX_0F3846, | |
1300 | PREFIX_VEX_0F3847, | |
1301 | PREFIX_VEX_0F3858, | |
1302 | PREFIX_VEX_0F3859, | |
1303 | PREFIX_VEX_0F385A, | |
1304 | PREFIX_VEX_0F3878, | |
1305 | PREFIX_VEX_0F3879, | |
1306 | PREFIX_VEX_0F388C, | |
1307 | PREFIX_VEX_0F388E, | |
1308 | PREFIX_VEX_0F3890, | |
1309 | PREFIX_VEX_0F3891, | |
1310 | PREFIX_VEX_0F3892, | |
1311 | PREFIX_VEX_0F3893, | |
592a252b L |
1312 | PREFIX_VEX_0F3896, |
1313 | PREFIX_VEX_0F3897, | |
1314 | PREFIX_VEX_0F3898, | |
1315 | PREFIX_VEX_0F3899, | |
1316 | PREFIX_VEX_0F389A, | |
1317 | PREFIX_VEX_0F389B, | |
1318 | PREFIX_VEX_0F389C, | |
1319 | PREFIX_VEX_0F389D, | |
1320 | PREFIX_VEX_0F389E, | |
1321 | PREFIX_VEX_0F389F, | |
1322 | PREFIX_VEX_0F38A6, | |
1323 | PREFIX_VEX_0F38A7, | |
1324 | PREFIX_VEX_0F38A8, | |
1325 | PREFIX_VEX_0F38A9, | |
1326 | PREFIX_VEX_0F38AA, | |
1327 | PREFIX_VEX_0F38AB, | |
1328 | PREFIX_VEX_0F38AC, | |
1329 | PREFIX_VEX_0F38AD, | |
1330 | PREFIX_VEX_0F38AE, | |
1331 | PREFIX_VEX_0F38AF, | |
1332 | PREFIX_VEX_0F38B6, | |
1333 | PREFIX_VEX_0F38B7, | |
1334 | PREFIX_VEX_0F38B8, | |
1335 | PREFIX_VEX_0F38B9, | |
1336 | PREFIX_VEX_0F38BA, | |
1337 | PREFIX_VEX_0F38BB, | |
1338 | PREFIX_VEX_0F38BC, | |
1339 | PREFIX_VEX_0F38BD, | |
1340 | PREFIX_VEX_0F38BE, | |
1341 | PREFIX_VEX_0F38BF, | |
48521003 | 1342 | PREFIX_VEX_0F38CF, |
592a252b L |
1343 | PREFIX_VEX_0F38DB, |
1344 | PREFIX_VEX_0F38DC, | |
1345 | PREFIX_VEX_0F38DD, | |
1346 | PREFIX_VEX_0F38DE, | |
1347 | PREFIX_VEX_0F38DF, | |
f12dc422 L |
1348 | PREFIX_VEX_0F38F2, |
1349 | PREFIX_VEX_0F38F3_REG_1, | |
1350 | PREFIX_VEX_0F38F3_REG_2, | |
1351 | PREFIX_VEX_0F38F3_REG_3, | |
6c30d220 L |
1352 | PREFIX_VEX_0F38F5, |
1353 | PREFIX_VEX_0F38F6, | |
f12dc422 | 1354 | PREFIX_VEX_0F38F7, |
6c30d220 L |
1355 | PREFIX_VEX_0F3A00, |
1356 | PREFIX_VEX_0F3A01, | |
1357 | PREFIX_VEX_0F3A02, | |
592a252b L |
1358 | PREFIX_VEX_0F3A04, |
1359 | PREFIX_VEX_0F3A05, | |
1360 | PREFIX_VEX_0F3A06, | |
1361 | PREFIX_VEX_0F3A08, | |
1362 | PREFIX_VEX_0F3A09, | |
1363 | PREFIX_VEX_0F3A0A, | |
1364 | PREFIX_VEX_0F3A0B, | |
1365 | PREFIX_VEX_0F3A0C, | |
1366 | PREFIX_VEX_0F3A0D, | |
1367 | PREFIX_VEX_0F3A0E, | |
1368 | PREFIX_VEX_0F3A0F, | |
1369 | PREFIX_VEX_0F3A14, | |
1370 | PREFIX_VEX_0F3A15, | |
1371 | PREFIX_VEX_0F3A16, | |
1372 | PREFIX_VEX_0F3A17, | |
1373 | PREFIX_VEX_0F3A18, | |
1374 | PREFIX_VEX_0F3A19, | |
1375 | PREFIX_VEX_0F3A1D, | |
1376 | PREFIX_VEX_0F3A20, | |
1377 | PREFIX_VEX_0F3A21, | |
1378 | PREFIX_VEX_0F3A22, | |
43234a1e | 1379 | PREFIX_VEX_0F3A30, |
1ba585e8 | 1380 | PREFIX_VEX_0F3A31, |
43234a1e | 1381 | PREFIX_VEX_0F3A32, |
1ba585e8 | 1382 | PREFIX_VEX_0F3A33, |
6c30d220 L |
1383 | PREFIX_VEX_0F3A38, |
1384 | PREFIX_VEX_0F3A39, | |
592a252b L |
1385 | PREFIX_VEX_0F3A40, |
1386 | PREFIX_VEX_0F3A41, | |
1387 | PREFIX_VEX_0F3A42, | |
1388 | PREFIX_VEX_0F3A44, | |
6c30d220 | 1389 | PREFIX_VEX_0F3A46, |
592a252b L |
1390 | PREFIX_VEX_0F3A48, |
1391 | PREFIX_VEX_0F3A49, | |
1392 | PREFIX_VEX_0F3A4A, | |
1393 | PREFIX_VEX_0F3A4B, | |
1394 | PREFIX_VEX_0F3A4C, | |
1395 | PREFIX_VEX_0F3A5C, | |
1396 | PREFIX_VEX_0F3A5D, | |
1397 | PREFIX_VEX_0F3A5E, | |
1398 | PREFIX_VEX_0F3A5F, | |
1399 | PREFIX_VEX_0F3A60, | |
1400 | PREFIX_VEX_0F3A61, | |
1401 | PREFIX_VEX_0F3A62, | |
1402 | PREFIX_VEX_0F3A63, | |
1403 | PREFIX_VEX_0F3A68, | |
1404 | PREFIX_VEX_0F3A69, | |
1405 | PREFIX_VEX_0F3A6A, | |
1406 | PREFIX_VEX_0F3A6B, | |
1407 | PREFIX_VEX_0F3A6C, | |
1408 | PREFIX_VEX_0F3A6D, | |
1409 | PREFIX_VEX_0F3A6E, | |
1410 | PREFIX_VEX_0F3A6F, | |
1411 | PREFIX_VEX_0F3A78, | |
1412 | PREFIX_VEX_0F3A79, | |
1413 | PREFIX_VEX_0F3A7A, | |
1414 | PREFIX_VEX_0F3A7B, | |
1415 | PREFIX_VEX_0F3A7C, | |
1416 | PREFIX_VEX_0F3A7D, | |
1417 | PREFIX_VEX_0F3A7E, | |
1418 | PREFIX_VEX_0F3A7F, | |
48521003 IT |
1419 | PREFIX_VEX_0F3ACE, |
1420 | PREFIX_VEX_0F3ACF, | |
6c30d220 | 1421 | PREFIX_VEX_0F3ADF, |
43234a1e L |
1422 | PREFIX_VEX_0F3AF0, |
1423 | ||
1424 | PREFIX_EVEX_0F10, | |
1425 | PREFIX_EVEX_0F11, | |
1426 | PREFIX_EVEX_0F12, | |
43234a1e | 1427 | PREFIX_EVEX_0F16, |
43234a1e | 1428 | PREFIX_EVEX_0F2A, |
43234a1e L |
1429 | PREFIX_EVEX_0F2C, |
1430 | PREFIX_EVEX_0F2D, | |
1431 | PREFIX_EVEX_0F2E, | |
1432 | PREFIX_EVEX_0F2F, | |
1433 | PREFIX_EVEX_0F51, | |
1434 | PREFIX_EVEX_0F58, | |
1435 | PREFIX_EVEX_0F59, | |
1436 | PREFIX_EVEX_0F5A, | |
1437 | PREFIX_EVEX_0F5B, | |
1438 | PREFIX_EVEX_0F5C, | |
1439 | PREFIX_EVEX_0F5D, | |
1440 | PREFIX_EVEX_0F5E, | |
1441 | PREFIX_EVEX_0F5F, | |
1ba585e8 IT |
1442 | PREFIX_EVEX_0F64, |
1443 | PREFIX_EVEX_0F65, | |
43234a1e | 1444 | PREFIX_EVEX_0F66, |
43234a1e L |
1445 | PREFIX_EVEX_0F6E, |
1446 | PREFIX_EVEX_0F6F, | |
1447 | PREFIX_EVEX_0F70, | |
1ba585e8 IT |
1448 | PREFIX_EVEX_0F71_REG_2, |
1449 | PREFIX_EVEX_0F71_REG_4, | |
1450 | PREFIX_EVEX_0F71_REG_6, | |
43234a1e L |
1451 | PREFIX_EVEX_0F72_REG_0, |
1452 | PREFIX_EVEX_0F72_REG_1, | |
1453 | PREFIX_EVEX_0F72_REG_2, | |
1454 | PREFIX_EVEX_0F72_REG_4, | |
1455 | PREFIX_EVEX_0F72_REG_6, | |
1456 | PREFIX_EVEX_0F73_REG_2, | |
1ba585e8 | 1457 | PREFIX_EVEX_0F73_REG_3, |
43234a1e | 1458 | PREFIX_EVEX_0F73_REG_6, |
1ba585e8 IT |
1459 | PREFIX_EVEX_0F73_REG_7, |
1460 | PREFIX_EVEX_0F74, | |
1461 | PREFIX_EVEX_0F75, | |
43234a1e L |
1462 | PREFIX_EVEX_0F76, |
1463 | PREFIX_EVEX_0F78, | |
1464 | PREFIX_EVEX_0F79, | |
1465 | PREFIX_EVEX_0F7A, | |
1466 | PREFIX_EVEX_0F7B, | |
1467 | PREFIX_EVEX_0F7E, | |
1468 | PREFIX_EVEX_0F7F, | |
1469 | PREFIX_EVEX_0FC2, | |
1ba585e8 IT |
1470 | PREFIX_EVEX_0FC4, |
1471 | PREFIX_EVEX_0FC5, | |
43234a1e L |
1472 | PREFIX_EVEX_0FD6, |
1473 | PREFIX_EVEX_0FDB, | |
1474 | PREFIX_EVEX_0FDF, | |
1475 | PREFIX_EVEX_0FE2, | |
1476 | PREFIX_EVEX_0FE6, | |
1477 | PREFIX_EVEX_0FE7, | |
1478 | PREFIX_EVEX_0FEB, | |
1479 | PREFIX_EVEX_0FEF, | |
43234a1e | 1480 | PREFIX_EVEX_0F380D, |
1ba585e8 | 1481 | PREFIX_EVEX_0F3810, |
43234a1e L |
1482 | PREFIX_EVEX_0F3811, |
1483 | PREFIX_EVEX_0F3812, | |
1484 | PREFIX_EVEX_0F3813, | |
1485 | PREFIX_EVEX_0F3814, | |
1486 | PREFIX_EVEX_0F3815, | |
1487 | PREFIX_EVEX_0F3816, | |
43234a1e L |
1488 | PREFIX_EVEX_0F3819, |
1489 | PREFIX_EVEX_0F381A, | |
1490 | PREFIX_EVEX_0F381B, | |
1491 | PREFIX_EVEX_0F381E, | |
1492 | PREFIX_EVEX_0F381F, | |
1ba585e8 | 1493 | PREFIX_EVEX_0F3820, |
43234a1e L |
1494 | PREFIX_EVEX_0F3821, |
1495 | PREFIX_EVEX_0F3822, | |
1496 | PREFIX_EVEX_0F3823, | |
1497 | PREFIX_EVEX_0F3824, | |
1498 | PREFIX_EVEX_0F3825, | |
1ba585e8 | 1499 | PREFIX_EVEX_0F3826, |
43234a1e L |
1500 | PREFIX_EVEX_0F3827, |
1501 | PREFIX_EVEX_0F3828, | |
1502 | PREFIX_EVEX_0F3829, | |
1503 | PREFIX_EVEX_0F382A, | |
1504 | PREFIX_EVEX_0F382C, | |
1505 | PREFIX_EVEX_0F382D, | |
1ba585e8 | 1506 | PREFIX_EVEX_0F3830, |
43234a1e L |
1507 | PREFIX_EVEX_0F3831, |
1508 | PREFIX_EVEX_0F3832, | |
1509 | PREFIX_EVEX_0F3833, | |
1510 | PREFIX_EVEX_0F3834, | |
1511 | PREFIX_EVEX_0F3835, | |
1512 | PREFIX_EVEX_0F3836, | |
1513 | PREFIX_EVEX_0F3837, | |
1ba585e8 | 1514 | PREFIX_EVEX_0F3838, |
43234a1e L |
1515 | PREFIX_EVEX_0F3839, |
1516 | PREFIX_EVEX_0F383A, | |
1517 | PREFIX_EVEX_0F383B, | |
1518 | PREFIX_EVEX_0F383D, | |
1519 | PREFIX_EVEX_0F383F, | |
1520 | PREFIX_EVEX_0F3840, | |
1521 | PREFIX_EVEX_0F3842, | |
1522 | PREFIX_EVEX_0F3843, | |
1523 | PREFIX_EVEX_0F3844, | |
1524 | PREFIX_EVEX_0F3845, | |
1525 | PREFIX_EVEX_0F3846, | |
1526 | PREFIX_EVEX_0F3847, | |
1527 | PREFIX_EVEX_0F384C, | |
1528 | PREFIX_EVEX_0F384D, | |
1529 | PREFIX_EVEX_0F384E, | |
1530 | PREFIX_EVEX_0F384F, | |
8cfcb765 IT |
1531 | PREFIX_EVEX_0F3850, |
1532 | PREFIX_EVEX_0F3851, | |
47acf0bd IT |
1533 | PREFIX_EVEX_0F3852, |
1534 | PREFIX_EVEX_0F3853, | |
ee6872be | 1535 | PREFIX_EVEX_0F3854, |
620214f7 | 1536 | PREFIX_EVEX_0F3855, |
43234a1e L |
1537 | PREFIX_EVEX_0F3859, |
1538 | PREFIX_EVEX_0F385A, | |
1539 | PREFIX_EVEX_0F385B, | |
53467f57 IT |
1540 | PREFIX_EVEX_0F3862, |
1541 | PREFIX_EVEX_0F3863, | |
43234a1e L |
1542 | PREFIX_EVEX_0F3864, |
1543 | PREFIX_EVEX_0F3865, | |
1ba585e8 | 1544 | PREFIX_EVEX_0F3866, |
9186c494 | 1545 | PREFIX_EVEX_0F3868, |
53467f57 IT |
1546 | PREFIX_EVEX_0F3870, |
1547 | PREFIX_EVEX_0F3871, | |
1548 | PREFIX_EVEX_0F3872, | |
1549 | PREFIX_EVEX_0F3873, | |
1ba585e8 | 1550 | PREFIX_EVEX_0F3875, |
43234a1e L |
1551 | PREFIX_EVEX_0F3876, |
1552 | PREFIX_EVEX_0F3877, | |
1ba585e8 IT |
1553 | PREFIX_EVEX_0F387A, |
1554 | PREFIX_EVEX_0F387B, | |
43234a1e | 1555 | PREFIX_EVEX_0F387C, |
1ba585e8 | 1556 | PREFIX_EVEX_0F387D, |
43234a1e L |
1557 | PREFIX_EVEX_0F387E, |
1558 | PREFIX_EVEX_0F387F, | |
14f195c9 | 1559 | PREFIX_EVEX_0F3883, |
43234a1e L |
1560 | PREFIX_EVEX_0F3888, |
1561 | PREFIX_EVEX_0F3889, | |
1562 | PREFIX_EVEX_0F388A, | |
1563 | PREFIX_EVEX_0F388B, | |
1ba585e8 | 1564 | PREFIX_EVEX_0F388D, |
ee6872be | 1565 | PREFIX_EVEX_0F388F, |
43234a1e L |
1566 | PREFIX_EVEX_0F3890, |
1567 | PREFIX_EVEX_0F3891, | |
1568 | PREFIX_EVEX_0F3892, | |
1569 | PREFIX_EVEX_0F3893, | |
43234a1e L |
1570 | PREFIX_EVEX_0F389A, |
1571 | PREFIX_EVEX_0F389B, | |
43234a1e L |
1572 | PREFIX_EVEX_0F38A0, |
1573 | PREFIX_EVEX_0F38A1, | |
1574 | PREFIX_EVEX_0F38A2, | |
1575 | PREFIX_EVEX_0F38A3, | |
43234a1e L |
1576 | PREFIX_EVEX_0F38AA, |
1577 | PREFIX_EVEX_0F38AB, | |
2cc1b5aa IT |
1578 | PREFIX_EVEX_0F38B4, |
1579 | PREFIX_EVEX_0F38B5, | |
43234a1e L |
1580 | PREFIX_EVEX_0F38C4, |
1581 | PREFIX_EVEX_0F38C6_REG_1, | |
1582 | PREFIX_EVEX_0F38C6_REG_2, | |
1583 | PREFIX_EVEX_0F38C6_REG_5, | |
1584 | PREFIX_EVEX_0F38C6_REG_6, | |
1585 | PREFIX_EVEX_0F38C7_REG_1, | |
1586 | PREFIX_EVEX_0F38C7_REG_2, | |
1587 | PREFIX_EVEX_0F38C7_REG_5, | |
1588 | PREFIX_EVEX_0F38C7_REG_6, | |
1589 | PREFIX_EVEX_0F38C8, | |
1590 | PREFIX_EVEX_0F38CA, | |
1591 | PREFIX_EVEX_0F38CB, | |
1592 | PREFIX_EVEX_0F38CC, | |
1593 | PREFIX_EVEX_0F38CD, | |
1594 | ||
1595 | PREFIX_EVEX_0F3A00, | |
1596 | PREFIX_EVEX_0F3A01, | |
1597 | PREFIX_EVEX_0F3A03, | |
43234a1e L |
1598 | PREFIX_EVEX_0F3A05, |
1599 | PREFIX_EVEX_0F3A08, | |
1600 | PREFIX_EVEX_0F3A09, | |
1601 | PREFIX_EVEX_0F3A0A, | |
1602 | PREFIX_EVEX_0F3A0B, | |
1ba585e8 IT |
1603 | PREFIX_EVEX_0F3A14, |
1604 | PREFIX_EVEX_0F3A15, | |
90a915bf | 1605 | PREFIX_EVEX_0F3A16, |
43234a1e L |
1606 | PREFIX_EVEX_0F3A17, |
1607 | PREFIX_EVEX_0F3A18, | |
1608 | PREFIX_EVEX_0F3A19, | |
1609 | PREFIX_EVEX_0F3A1A, | |
1610 | PREFIX_EVEX_0F3A1B, | |
43234a1e L |
1611 | PREFIX_EVEX_0F3A1E, |
1612 | PREFIX_EVEX_0F3A1F, | |
1ba585e8 | 1613 | PREFIX_EVEX_0F3A20, |
43234a1e | 1614 | PREFIX_EVEX_0F3A21, |
90a915bf | 1615 | PREFIX_EVEX_0F3A22, |
43234a1e L |
1616 | PREFIX_EVEX_0F3A23, |
1617 | PREFIX_EVEX_0F3A25, | |
1618 | PREFIX_EVEX_0F3A26, | |
1619 | PREFIX_EVEX_0F3A27, | |
1620 | PREFIX_EVEX_0F3A38, | |
1621 | PREFIX_EVEX_0F3A39, | |
1622 | PREFIX_EVEX_0F3A3A, | |
1623 | PREFIX_EVEX_0F3A3B, | |
1ba585e8 IT |
1624 | PREFIX_EVEX_0F3A3E, |
1625 | PREFIX_EVEX_0F3A3F, | |
1626 | PREFIX_EVEX_0F3A42, | |
43234a1e | 1627 | PREFIX_EVEX_0F3A43, |
90a915bf IT |
1628 | PREFIX_EVEX_0F3A50, |
1629 | PREFIX_EVEX_0F3A51, | |
43234a1e | 1630 | PREFIX_EVEX_0F3A54, |
90a915bf IT |
1631 | PREFIX_EVEX_0F3A55, |
1632 | PREFIX_EVEX_0F3A56, | |
1633 | PREFIX_EVEX_0F3A57, | |
1634 | PREFIX_EVEX_0F3A66, | |
53467f57 IT |
1635 | PREFIX_EVEX_0F3A67, |
1636 | PREFIX_EVEX_0F3A70, | |
1637 | PREFIX_EVEX_0F3A71, | |
1638 | PREFIX_EVEX_0F3A72, | |
48521003 | 1639 | PREFIX_EVEX_0F3A73, |
51e7da1b | 1640 | }; |
4e7d34a6 | 1641 | |
51e7da1b L |
1642 | enum |
1643 | { | |
1644 | X86_64_06 = 0, | |
3873ba12 | 1645 | X86_64_07, |
1673df32 | 1646 | X86_64_0E, |
3873ba12 L |
1647 | X86_64_16, |
1648 | X86_64_17, | |
1649 | X86_64_1E, | |
1650 | X86_64_1F, | |
1651 | X86_64_27, | |
1652 | X86_64_2F, | |
1653 | X86_64_37, | |
1654 | X86_64_3F, | |
1655 | X86_64_60, | |
1656 | X86_64_61, | |
1657 | X86_64_62, | |
1658 | X86_64_63, | |
1659 | X86_64_6D, | |
1660 | X86_64_6F, | |
d039fef3 | 1661 | X86_64_82, |
3873ba12 | 1662 | X86_64_9A, |
aeab2b26 JB |
1663 | X86_64_C2, |
1664 | X86_64_C3, | |
3873ba12 L |
1665 | X86_64_C4, |
1666 | X86_64_C5, | |
1667 | X86_64_CE, | |
1668 | X86_64_D4, | |
1669 | X86_64_D5, | |
a72d2af2 L |
1670 | X86_64_E8, |
1671 | X86_64_E9, | |
3873ba12 L |
1672 | X86_64_EA, |
1673 | X86_64_0F01_REG_0, | |
1674 | X86_64_0F01_REG_1, | |
1675 | X86_64_0F01_REG_2, | |
1676 | X86_64_0F01_REG_3 | |
51e7da1b | 1677 | }; |
4e7d34a6 | 1678 | |
51e7da1b L |
1679 | enum |
1680 | { | |
1681 | THREE_BYTE_0F38 = 0, | |
1f334aeb | 1682 | THREE_BYTE_0F3A |
51e7da1b | 1683 | }; |
4e7d34a6 | 1684 | |
f88c9eb0 SP |
1685 | enum |
1686 | { | |
5dd85c99 SP |
1687 | XOP_08 = 0, |
1688 | XOP_09, | |
f88c9eb0 SP |
1689 | XOP_0A |
1690 | }; | |
1691 | ||
51e7da1b L |
1692 | enum |
1693 | { | |
1694 | VEX_0F = 0, | |
3873ba12 L |
1695 | VEX_0F38, |
1696 | VEX_0F3A | |
51e7da1b | 1697 | }; |
c0f3af97 | 1698 | |
43234a1e L |
1699 | enum |
1700 | { | |
1701 | EVEX_0F = 0, | |
1702 | EVEX_0F38, | |
1703 | EVEX_0F3A | |
1704 | }; | |
1705 | ||
51e7da1b L |
1706 | enum |
1707 | { | |
ec6f095a | 1708 | VEX_LEN_0F12_P_0_M_0 = 0, |
592a252b | 1709 | VEX_LEN_0F12_P_0_M_1, |
18897deb | 1710 | #define VEX_LEN_0F12_P_2_M_0 VEX_LEN_0F12_P_0_M_0 |
592a252b L |
1711 | VEX_LEN_0F13_M_0, |
1712 | VEX_LEN_0F16_P_0_M_0, | |
1713 | VEX_LEN_0F16_P_0_M_1, | |
18897deb | 1714 | #define VEX_LEN_0F16_P_2_M_0 VEX_LEN_0F16_P_0_M_0 |
592a252b | 1715 | VEX_LEN_0F17_M_0, |
43234a1e | 1716 | VEX_LEN_0F41_P_0, |
1ba585e8 | 1717 | VEX_LEN_0F41_P_2, |
43234a1e | 1718 | VEX_LEN_0F42_P_0, |
1ba585e8 | 1719 | VEX_LEN_0F42_P_2, |
43234a1e | 1720 | VEX_LEN_0F44_P_0, |
1ba585e8 | 1721 | VEX_LEN_0F44_P_2, |
43234a1e | 1722 | VEX_LEN_0F45_P_0, |
1ba585e8 | 1723 | VEX_LEN_0F45_P_2, |
43234a1e | 1724 | VEX_LEN_0F46_P_0, |
1ba585e8 | 1725 | VEX_LEN_0F46_P_2, |
43234a1e | 1726 | VEX_LEN_0F47_P_0, |
1ba585e8 IT |
1727 | VEX_LEN_0F47_P_2, |
1728 | VEX_LEN_0F4A_P_0, | |
1729 | VEX_LEN_0F4A_P_2, | |
1730 | VEX_LEN_0F4B_P_0, | |
43234a1e | 1731 | VEX_LEN_0F4B_P_2, |
592a252b | 1732 | VEX_LEN_0F6E_P_2, |
ec6f095a | 1733 | VEX_LEN_0F77_P_0, |
592a252b L |
1734 | VEX_LEN_0F7E_P_1, |
1735 | VEX_LEN_0F7E_P_2, | |
43234a1e | 1736 | VEX_LEN_0F90_P_0, |
1ba585e8 | 1737 | VEX_LEN_0F90_P_2, |
43234a1e | 1738 | VEX_LEN_0F91_P_0, |
1ba585e8 | 1739 | VEX_LEN_0F91_P_2, |
43234a1e | 1740 | VEX_LEN_0F92_P_0, |
90a915bf | 1741 | VEX_LEN_0F92_P_2, |
1ba585e8 | 1742 | VEX_LEN_0F92_P_3, |
43234a1e | 1743 | VEX_LEN_0F93_P_0, |
90a915bf | 1744 | VEX_LEN_0F93_P_2, |
1ba585e8 | 1745 | VEX_LEN_0F93_P_3, |
43234a1e | 1746 | VEX_LEN_0F98_P_0, |
1ba585e8 IT |
1747 | VEX_LEN_0F98_P_2, |
1748 | VEX_LEN_0F99_P_0, | |
1749 | VEX_LEN_0F99_P_2, | |
592a252b L |
1750 | VEX_LEN_0FAE_R_2_M_0, |
1751 | VEX_LEN_0FAE_R_3_M_0, | |
592a252b L |
1752 | VEX_LEN_0FC4_P_2, |
1753 | VEX_LEN_0FC5_P_2, | |
592a252b | 1754 | VEX_LEN_0FD6_P_2, |
592a252b | 1755 | VEX_LEN_0FF7_P_2, |
6c30d220 L |
1756 | VEX_LEN_0F3816_P_2, |
1757 | VEX_LEN_0F3819_P_2, | |
592a252b | 1758 | VEX_LEN_0F381A_P_2_M_0, |
6c30d220 | 1759 | VEX_LEN_0F3836_P_2, |
592a252b | 1760 | VEX_LEN_0F3841_P_2, |
6c30d220 | 1761 | VEX_LEN_0F385A_P_2_M_0, |
592a252b | 1762 | VEX_LEN_0F38DB_P_2, |
f12dc422 L |
1763 | VEX_LEN_0F38F2_P_0, |
1764 | VEX_LEN_0F38F3_R_1_P_0, | |
1765 | VEX_LEN_0F38F3_R_2_P_0, | |
1766 | VEX_LEN_0F38F3_R_3_P_0, | |
6c30d220 L |
1767 | VEX_LEN_0F38F5_P_0, |
1768 | VEX_LEN_0F38F5_P_1, | |
1769 | VEX_LEN_0F38F5_P_3, | |
1770 | VEX_LEN_0F38F6_P_3, | |
f12dc422 | 1771 | VEX_LEN_0F38F7_P_0, |
6c30d220 L |
1772 | VEX_LEN_0F38F7_P_1, |
1773 | VEX_LEN_0F38F7_P_2, | |
1774 | VEX_LEN_0F38F7_P_3, | |
1775 | VEX_LEN_0F3A00_P_2, | |
1776 | VEX_LEN_0F3A01_P_2, | |
592a252b | 1777 | VEX_LEN_0F3A06_P_2, |
592a252b L |
1778 | VEX_LEN_0F3A14_P_2, |
1779 | VEX_LEN_0F3A15_P_2, | |
1780 | VEX_LEN_0F3A16_P_2, | |
1781 | VEX_LEN_0F3A17_P_2, | |
1782 | VEX_LEN_0F3A18_P_2, | |
1783 | VEX_LEN_0F3A19_P_2, | |
1784 | VEX_LEN_0F3A20_P_2, | |
1785 | VEX_LEN_0F3A21_P_2, | |
1786 | VEX_LEN_0F3A22_P_2, | |
43234a1e | 1787 | VEX_LEN_0F3A30_P_2, |
1ba585e8 | 1788 | VEX_LEN_0F3A31_P_2, |
43234a1e | 1789 | VEX_LEN_0F3A32_P_2, |
1ba585e8 | 1790 | VEX_LEN_0F3A33_P_2, |
6c30d220 L |
1791 | VEX_LEN_0F3A38_P_2, |
1792 | VEX_LEN_0F3A39_P_2, | |
592a252b | 1793 | VEX_LEN_0F3A41_P_2, |
6c30d220 | 1794 | VEX_LEN_0F3A46_P_2, |
592a252b L |
1795 | VEX_LEN_0F3A60_P_2, |
1796 | VEX_LEN_0F3A61_P_2, | |
1797 | VEX_LEN_0F3A62_P_2, | |
1798 | VEX_LEN_0F3A63_P_2, | |
1799 | VEX_LEN_0F3A6A_P_2, | |
1800 | VEX_LEN_0F3A6B_P_2, | |
1801 | VEX_LEN_0F3A6E_P_2, | |
1802 | VEX_LEN_0F3A6F_P_2, | |
1803 | VEX_LEN_0F3A7A_P_2, | |
1804 | VEX_LEN_0F3A7B_P_2, | |
1805 | VEX_LEN_0F3A7E_P_2, | |
1806 | VEX_LEN_0F3A7F_P_2, | |
1807 | VEX_LEN_0F3ADF_P_2, | |
6c30d220 | 1808 | VEX_LEN_0F3AF0_P_3, |
ff688e1f L |
1809 | VEX_LEN_0FXOP_08_CC, |
1810 | VEX_LEN_0FXOP_08_CD, | |
1811 | VEX_LEN_0FXOP_08_CE, | |
1812 | VEX_LEN_0FXOP_08_CF, | |
1813 | VEX_LEN_0FXOP_08_EC, | |
1814 | VEX_LEN_0FXOP_08_ED, | |
1815 | VEX_LEN_0FXOP_08_EE, | |
1816 | VEX_LEN_0FXOP_08_EF, | |
592a252b L |
1817 | VEX_LEN_0FXOP_09_80, |
1818 | VEX_LEN_0FXOP_09_81 | |
51e7da1b | 1819 | }; |
c0f3af97 | 1820 | |
04e2a182 L |
1821 | enum |
1822 | { | |
1823 | EVEX_LEN_0F6E_P_2 = 0, | |
1824 | EVEX_LEN_0F7E_P_1, | |
1825 | EVEX_LEN_0F7E_P_2, | |
e74d9fa9 JB |
1826 | EVEX_LEN_0FC4_P_2, |
1827 | EVEX_LEN_0FC5_P_2, | |
12efd68d | 1828 | EVEX_LEN_0FD6_P_2, |
3a57774c | 1829 | EVEX_LEN_0F3816_P_2, |
f0a6222e L |
1830 | EVEX_LEN_0F3819_P_2_W_0, |
1831 | EVEX_LEN_0F3819_P_2_W_1, | |
bc152a17 JB |
1832 | EVEX_LEN_0F381A_P_2_W_0_M_0, |
1833 | EVEX_LEN_0F381A_P_2_W_1_M_0, | |
1834 | EVEX_LEN_0F381B_P_2_W_0_M_0, | |
1835 | EVEX_LEN_0F381B_P_2_W_1_M_0, | |
3a57774c | 1836 | EVEX_LEN_0F3836_P_2, |
bc152a17 JB |
1837 | EVEX_LEN_0F385A_P_2_W_0_M_0, |
1838 | EVEX_LEN_0F385A_P_2_W_1_M_0, | |
1839 | EVEX_LEN_0F385B_P_2_W_0_M_0, | |
1840 | EVEX_LEN_0F385B_P_2_W_1_M_0, | |
e395f487 L |
1841 | EVEX_LEN_0F38C6_REG_1_PREFIX_2, |
1842 | EVEX_LEN_0F38C6_REG_2_PREFIX_2, | |
1843 | EVEX_LEN_0F38C6_REG_5_PREFIX_2, | |
1844 | EVEX_LEN_0F38C6_REG_6_PREFIX_2, | |
1845 | EVEX_LEN_0F38C7_R_1_P_2_W_0, | |
1846 | EVEX_LEN_0F38C7_R_1_P_2_W_1, | |
1847 | EVEX_LEN_0F38C7_R_2_P_2_W_0, | |
1848 | EVEX_LEN_0F38C7_R_2_P_2_W_1, | |
1849 | EVEX_LEN_0F38C7_R_5_P_2_W_0, | |
1850 | EVEX_LEN_0F38C7_R_5_P_2_W_1, | |
1851 | EVEX_LEN_0F38C7_R_6_P_2_W_0, | |
1852 | EVEX_LEN_0F38C7_R_6_P_2_W_1, | |
3a57774c JB |
1853 | EVEX_LEN_0F3A00_P_2_W_1, |
1854 | EVEX_LEN_0F3A01_P_2_W_1, | |
e74d9fa9 JB |
1855 | EVEX_LEN_0F3A14_P_2, |
1856 | EVEX_LEN_0F3A15_P_2, | |
1857 | EVEX_LEN_0F3A16_P_2, | |
1858 | EVEX_LEN_0F3A17_P_2, | |
12efd68d L |
1859 | EVEX_LEN_0F3A18_P_2_W_0, |
1860 | EVEX_LEN_0F3A18_P_2_W_1, | |
1861 | EVEX_LEN_0F3A19_P_2_W_0, | |
1862 | EVEX_LEN_0F3A19_P_2_W_1, | |
1863 | EVEX_LEN_0F3A1A_P_2_W_0, | |
1864 | EVEX_LEN_0F3A1A_P_2_W_1, | |
1865 | EVEX_LEN_0F3A1B_P_2_W_0, | |
6e1c90b7 | 1866 | EVEX_LEN_0F3A1B_P_2_W_1, |
e74d9fa9 JB |
1867 | EVEX_LEN_0F3A20_P_2, |
1868 | EVEX_LEN_0F3A21_P_2_W_0, | |
1869 | EVEX_LEN_0F3A22_P_2, | |
6e1c90b7 L |
1870 | EVEX_LEN_0F3A23_P_2_W_0, |
1871 | EVEX_LEN_0F3A23_P_2_W_1, | |
1872 | EVEX_LEN_0F3A38_P_2_W_0, | |
1873 | EVEX_LEN_0F3A38_P_2_W_1, | |
1874 | EVEX_LEN_0F3A39_P_2_W_0, | |
1875 | EVEX_LEN_0F3A39_P_2_W_1, | |
1876 | EVEX_LEN_0F3A3A_P_2_W_0, | |
1877 | EVEX_LEN_0F3A3A_P_2_W_1, | |
1878 | EVEX_LEN_0F3A3B_P_2_W_0, | |
1879 | EVEX_LEN_0F3A3B_P_2_W_1, | |
1880 | EVEX_LEN_0F3A43_P_2_W_0, | |
1881 | EVEX_LEN_0F3A43_P_2_W_1 | |
04e2a182 L |
1882 | }; |
1883 | ||
9e30b8e0 L |
1884 | enum |
1885 | { | |
ec6f095a | 1886 | VEX_W_0F41_P_0_LEN_1 = 0, |
1ba585e8 | 1887 | VEX_W_0F41_P_2_LEN_1, |
43234a1e | 1888 | VEX_W_0F42_P_0_LEN_1, |
1ba585e8 | 1889 | VEX_W_0F42_P_2_LEN_1, |
43234a1e | 1890 | VEX_W_0F44_P_0_LEN_0, |
1ba585e8 | 1891 | VEX_W_0F44_P_2_LEN_0, |
43234a1e | 1892 | VEX_W_0F45_P_0_LEN_1, |
1ba585e8 | 1893 | VEX_W_0F45_P_2_LEN_1, |
43234a1e | 1894 | VEX_W_0F46_P_0_LEN_1, |
1ba585e8 | 1895 | VEX_W_0F46_P_2_LEN_1, |
43234a1e | 1896 | VEX_W_0F47_P_0_LEN_1, |
1ba585e8 IT |
1897 | VEX_W_0F47_P_2_LEN_1, |
1898 | VEX_W_0F4A_P_0_LEN_1, | |
1899 | VEX_W_0F4A_P_2_LEN_1, | |
1900 | VEX_W_0F4B_P_0_LEN_1, | |
43234a1e | 1901 | VEX_W_0F4B_P_2_LEN_1, |
43234a1e | 1902 | VEX_W_0F90_P_0_LEN_0, |
1ba585e8 | 1903 | VEX_W_0F90_P_2_LEN_0, |
43234a1e | 1904 | VEX_W_0F91_P_0_LEN_0, |
1ba585e8 | 1905 | VEX_W_0F91_P_2_LEN_0, |
43234a1e | 1906 | VEX_W_0F92_P_0_LEN_0, |
90a915bf | 1907 | VEX_W_0F92_P_2_LEN_0, |
43234a1e | 1908 | VEX_W_0F93_P_0_LEN_0, |
90a915bf | 1909 | VEX_W_0F93_P_2_LEN_0, |
43234a1e | 1910 | VEX_W_0F98_P_0_LEN_0, |
1ba585e8 IT |
1911 | VEX_W_0F98_P_2_LEN_0, |
1912 | VEX_W_0F99_P_0_LEN_0, | |
1913 | VEX_W_0F99_P_2_LEN_0, | |
592a252b L |
1914 | VEX_W_0F380C_P_2, |
1915 | VEX_W_0F380D_P_2, | |
1916 | VEX_W_0F380E_P_2, | |
1917 | VEX_W_0F380F_P_2, | |
6431c801 | 1918 | VEX_W_0F3813_P_2, |
6c30d220 | 1919 | VEX_W_0F3816_P_2, |
6c30d220 L |
1920 | VEX_W_0F3818_P_2, |
1921 | VEX_W_0F3819_P_2, | |
592a252b | 1922 | VEX_W_0F381A_P_2_M_0, |
592a252b L |
1923 | VEX_W_0F382C_P_2_M_0, |
1924 | VEX_W_0F382D_P_2_M_0, | |
1925 | VEX_W_0F382E_P_2_M_0, | |
1926 | VEX_W_0F382F_P_2_M_0, | |
6c30d220 | 1927 | VEX_W_0F3836_P_2, |
6c30d220 L |
1928 | VEX_W_0F3846_P_2, |
1929 | VEX_W_0F3858_P_2, | |
1930 | VEX_W_0F3859_P_2, | |
1931 | VEX_W_0F385A_P_2_M_0, | |
1932 | VEX_W_0F3878_P_2, | |
1933 | VEX_W_0F3879_P_2, | |
48521003 | 1934 | VEX_W_0F38CF_P_2, |
6c30d220 L |
1935 | VEX_W_0F3A00_P_2, |
1936 | VEX_W_0F3A01_P_2, | |
1937 | VEX_W_0F3A02_P_2, | |
592a252b L |
1938 | VEX_W_0F3A04_P_2, |
1939 | VEX_W_0F3A05_P_2, | |
1940 | VEX_W_0F3A06_P_2, | |
592a252b L |
1941 | VEX_W_0F3A18_P_2, |
1942 | VEX_W_0F3A19_P_2, | |
6431c801 | 1943 | VEX_W_0F3A1D_P_2, |
43234a1e | 1944 | VEX_W_0F3A30_P_2_LEN_0, |
1ba585e8 | 1945 | VEX_W_0F3A31_P_2_LEN_0, |
43234a1e | 1946 | VEX_W_0F3A32_P_2_LEN_0, |
1ba585e8 | 1947 | VEX_W_0F3A33_P_2_LEN_0, |
6c30d220 L |
1948 | VEX_W_0F3A38_P_2, |
1949 | VEX_W_0F3A39_P_2, | |
6c30d220 | 1950 | VEX_W_0F3A46_P_2, |
592a252b L |
1951 | VEX_W_0F3A48_P_2, |
1952 | VEX_W_0F3A49_P_2, | |
1953 | VEX_W_0F3A4A_P_2, | |
1954 | VEX_W_0F3A4B_P_2, | |
1955 | VEX_W_0F3A4C_P_2, | |
48521003 IT |
1956 | VEX_W_0F3ACE_P_2, |
1957 | VEX_W_0F3ACF_P_2, | |
43234a1e | 1958 | |
36cc073e | 1959 | EVEX_W_0F10_P_1, |
36cc073e | 1960 | EVEX_W_0F10_P_3, |
36cc073e | 1961 | EVEX_W_0F11_P_1, |
36cc073e | 1962 | EVEX_W_0F11_P_3, |
43234a1e L |
1963 | EVEX_W_0F12_P_0_M_1, |
1964 | EVEX_W_0F12_P_1, | |
43234a1e | 1965 | EVEX_W_0F12_P_3, |
43234a1e L |
1966 | EVEX_W_0F16_P_0_M_1, |
1967 | EVEX_W_0F16_P_1, | |
43234a1e | 1968 | EVEX_W_0F2A_P_3, |
43234a1e | 1969 | EVEX_W_0F51_P_1, |
43234a1e | 1970 | EVEX_W_0F51_P_3, |
43234a1e | 1971 | EVEX_W_0F58_P_1, |
43234a1e | 1972 | EVEX_W_0F58_P_3, |
43234a1e | 1973 | EVEX_W_0F59_P_1, |
43234a1e L |
1974 | EVEX_W_0F59_P_3, |
1975 | EVEX_W_0F5A_P_0, | |
1976 | EVEX_W_0F5A_P_1, | |
1977 | EVEX_W_0F5A_P_2, | |
1978 | EVEX_W_0F5A_P_3, | |
1979 | EVEX_W_0F5B_P_0, | |
1980 | EVEX_W_0F5B_P_1, | |
1981 | EVEX_W_0F5B_P_2, | |
43234a1e | 1982 | EVEX_W_0F5C_P_1, |
43234a1e | 1983 | EVEX_W_0F5C_P_3, |
43234a1e | 1984 | EVEX_W_0F5D_P_1, |
43234a1e | 1985 | EVEX_W_0F5D_P_3, |
43234a1e | 1986 | EVEX_W_0F5E_P_1, |
43234a1e | 1987 | EVEX_W_0F5E_P_3, |
43234a1e | 1988 | EVEX_W_0F5F_P_1, |
43234a1e | 1989 | EVEX_W_0F5F_P_3, |
fedfb81e | 1990 | EVEX_W_0F62, |
43234a1e | 1991 | EVEX_W_0F66_P_2, |
fedfb81e JB |
1992 | EVEX_W_0F6A, |
1993 | EVEX_W_0F6B, | |
1994 | EVEX_W_0F6C, | |
1995 | EVEX_W_0F6D, | |
43234a1e L |
1996 | EVEX_W_0F6F_P_1, |
1997 | EVEX_W_0F6F_P_2, | |
1ba585e8 | 1998 | EVEX_W_0F6F_P_3, |
43234a1e L |
1999 | EVEX_W_0F70_P_2, |
2000 | EVEX_W_0F72_R_2_P_2, | |
2001 | EVEX_W_0F72_R_6_P_2, | |
2002 | EVEX_W_0F73_R_2_P_2, | |
2003 | EVEX_W_0F73_R_6_P_2, | |
2004 | EVEX_W_0F76_P_2, | |
2005 | EVEX_W_0F78_P_0, | |
90a915bf | 2006 | EVEX_W_0F78_P_2, |
43234a1e | 2007 | EVEX_W_0F79_P_0, |
90a915bf | 2008 | EVEX_W_0F79_P_2, |
43234a1e | 2009 | EVEX_W_0F7A_P_1, |
90a915bf | 2010 | EVEX_W_0F7A_P_2, |
43234a1e | 2011 | EVEX_W_0F7A_P_3, |
90a915bf | 2012 | EVEX_W_0F7B_P_2, |
43234a1e L |
2013 | EVEX_W_0F7B_P_3, |
2014 | EVEX_W_0F7E_P_1, | |
43234a1e L |
2015 | EVEX_W_0F7F_P_1, |
2016 | EVEX_W_0F7F_P_2, | |
1ba585e8 | 2017 | EVEX_W_0F7F_P_3, |
43234a1e | 2018 | EVEX_W_0FC2_P_1, |
43234a1e | 2019 | EVEX_W_0FC2_P_3, |
fedfb81e JB |
2020 | EVEX_W_0FD2, |
2021 | EVEX_W_0FD3, | |
2022 | EVEX_W_0FD4, | |
43234a1e L |
2023 | EVEX_W_0FD6_P_2, |
2024 | EVEX_W_0FE6_P_1, | |
2025 | EVEX_W_0FE6_P_2, | |
2026 | EVEX_W_0FE6_P_3, | |
2027 | EVEX_W_0FE7_P_2, | |
fedfb81e JB |
2028 | EVEX_W_0FF2, |
2029 | EVEX_W_0FF3, | |
2030 | EVEX_W_0FF4, | |
2031 | EVEX_W_0FFA, | |
2032 | EVEX_W_0FFB, | |
2033 | EVEX_W_0FFE, | |
43234a1e | 2034 | EVEX_W_0F380D_P_2, |
1ba585e8 IT |
2035 | EVEX_W_0F3810_P_1, |
2036 | EVEX_W_0F3810_P_2, | |
43234a1e | 2037 | EVEX_W_0F3811_P_1, |
1ba585e8 | 2038 | EVEX_W_0F3811_P_2, |
43234a1e | 2039 | EVEX_W_0F3812_P_1, |
1ba585e8 | 2040 | EVEX_W_0F3812_P_2, |
43234a1e L |
2041 | EVEX_W_0F3813_P_1, |
2042 | EVEX_W_0F3813_P_2, | |
2043 | EVEX_W_0F3814_P_1, | |
2044 | EVEX_W_0F3815_P_1, | |
43234a1e L |
2045 | EVEX_W_0F3819_P_2, |
2046 | EVEX_W_0F381A_P_2, | |
2047 | EVEX_W_0F381B_P_2, | |
2048 | EVEX_W_0F381E_P_2, | |
2049 | EVEX_W_0F381F_P_2, | |
1ba585e8 | 2050 | EVEX_W_0F3820_P_1, |
43234a1e L |
2051 | EVEX_W_0F3821_P_1, |
2052 | EVEX_W_0F3822_P_1, | |
2053 | EVEX_W_0F3823_P_1, | |
2054 | EVEX_W_0F3824_P_1, | |
2055 | EVEX_W_0F3825_P_1, | |
2056 | EVEX_W_0F3825_P_2, | |
1ba585e8 IT |
2057 | EVEX_W_0F3826_P_1, |
2058 | EVEX_W_0F3826_P_2, | |
2059 | EVEX_W_0F3828_P_1, | |
43234a1e | 2060 | EVEX_W_0F3828_P_2, |
1ba585e8 | 2061 | EVEX_W_0F3829_P_1, |
43234a1e L |
2062 | EVEX_W_0F3829_P_2, |
2063 | EVEX_W_0F382A_P_1, | |
2064 | EVEX_W_0F382A_P_2, | |
fedfb81e | 2065 | EVEX_W_0F382B, |
1ba585e8 | 2066 | EVEX_W_0F3830_P_1, |
43234a1e L |
2067 | EVEX_W_0F3831_P_1, |
2068 | EVEX_W_0F3832_P_1, | |
2069 | EVEX_W_0F3833_P_1, | |
2070 | EVEX_W_0F3834_P_1, | |
2071 | EVEX_W_0F3835_P_1, | |
2072 | EVEX_W_0F3835_P_2, | |
2073 | EVEX_W_0F3837_P_2, | |
90a915bf IT |
2074 | EVEX_W_0F3838_P_1, |
2075 | EVEX_W_0F3839_P_1, | |
43234a1e L |
2076 | EVEX_W_0F383A_P_1, |
2077 | EVEX_W_0F3840_P_2, | |
d6aab7a1 | 2078 | EVEX_W_0F3852_P_1, |
ee6872be | 2079 | EVEX_W_0F3854_P_2, |
620214f7 | 2080 | EVEX_W_0F3855_P_2, |
43234a1e L |
2081 | EVEX_W_0F3859_P_2, |
2082 | EVEX_W_0F385A_P_2, | |
2083 | EVEX_W_0F385B_P_2, | |
53467f57 IT |
2084 | EVEX_W_0F3862_P_2, |
2085 | EVEX_W_0F3863_P_2, | |
1ba585e8 | 2086 | EVEX_W_0F3866_P_2, |
9186c494 | 2087 | EVEX_W_0F3868_P_3, |
53467f57 IT |
2088 | EVEX_W_0F3870_P_2, |
2089 | EVEX_W_0F3871_P_2, | |
d6aab7a1 | 2090 | EVEX_W_0F3872_P_1, |
53467f57 | 2091 | EVEX_W_0F3872_P_2, |
d6aab7a1 | 2092 | EVEX_W_0F3872_P_3, |
53467f57 | 2093 | EVEX_W_0F3873_P_2, |
1ba585e8 | 2094 | EVEX_W_0F3875_P_2, |
1ba585e8 IT |
2095 | EVEX_W_0F387A_P_2, |
2096 | EVEX_W_0F387B_P_2, | |
2097 | EVEX_W_0F387D_P_2, | |
14f195c9 | 2098 | EVEX_W_0F3883_P_2, |
1ba585e8 | 2099 | EVEX_W_0F388D_P_2, |
43234a1e L |
2100 | EVEX_W_0F3891_P_2, |
2101 | EVEX_W_0F3893_P_2, | |
2102 | EVEX_W_0F38A1_P_2, | |
2103 | EVEX_W_0F38A3_P_2, | |
2104 | EVEX_W_0F38C7_R_1_P_2, | |
2105 | EVEX_W_0F38C7_R_2_P_2, | |
2106 | EVEX_W_0F38C7_R_5_P_2, | |
2107 | EVEX_W_0F38C7_R_6_P_2, | |
2108 | ||
2109 | EVEX_W_0F3A00_P_2, | |
2110 | EVEX_W_0F3A01_P_2, | |
43234a1e L |
2111 | EVEX_W_0F3A05_P_2, |
2112 | EVEX_W_0F3A08_P_2, | |
2113 | EVEX_W_0F3A09_P_2, | |
2114 | EVEX_W_0F3A0A_P_2, | |
2115 | EVEX_W_0F3A0B_P_2, | |
2116 | EVEX_W_0F3A18_P_2, | |
2117 | EVEX_W_0F3A19_P_2, | |
2118 | EVEX_W_0F3A1A_P_2, | |
2119 | EVEX_W_0F3A1B_P_2, | |
43234a1e L |
2120 | EVEX_W_0F3A21_P_2, |
2121 | EVEX_W_0F3A23_P_2, | |
2122 | EVEX_W_0F3A38_P_2, | |
2123 | EVEX_W_0F3A39_P_2, | |
2124 | EVEX_W_0F3A3A_P_2, | |
2125 | EVEX_W_0F3A3B_P_2, | |
1ba585e8 IT |
2126 | EVEX_W_0F3A3E_P_2, |
2127 | EVEX_W_0F3A3F_P_2, | |
2128 | EVEX_W_0F3A42_P_2, | |
90a915bf IT |
2129 | EVEX_W_0F3A43_P_2, |
2130 | EVEX_W_0F3A50_P_2, | |
2131 | EVEX_W_0F3A51_P_2, | |
2132 | EVEX_W_0F3A56_P_2, | |
2133 | EVEX_W_0F3A57_P_2, | |
2134 | EVEX_W_0F3A66_P_2, | |
53467f57 IT |
2135 | EVEX_W_0F3A67_P_2, |
2136 | EVEX_W_0F3A70_P_2, | |
2137 | EVEX_W_0F3A71_P_2, | |
2138 | EVEX_W_0F3A72_P_2, | |
48521003 | 2139 | EVEX_W_0F3A73_P_2, |
9e30b8e0 L |
2140 | }; |
2141 | ||
26ca5450 | 2142 | typedef void (*op_rtn) (int bytemode, int sizeflag); |
252b5132 RH |
2143 | |
2144 | struct dis386 { | |
2da11e11 | 2145 | const char *name; |
ce518a5f L |
2146 | struct |
2147 | { | |
2148 | op_rtn rtn; | |
2149 | int bytemode; | |
2150 | } op[MAX_OPERANDS]; | |
bf890a93 | 2151 | unsigned int prefix_requirement; |
252b5132 RH |
2152 | }; |
2153 | ||
2154 | /* Upper case letters in the instruction names here are macros. | |
2155 | 'A' => print 'b' if no register operands or suffix_always is true | |
2156 | 'B' => print 'b' if suffix_always is true | |
9306ca4a | 2157 | 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand |
98b528ac | 2158 | size prefix |
ed7841b3 | 2159 | 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if |
98b528ac | 2160 | suffix_always is true |
252b5132 | 2161 | 'E' => print 'e' if 32-bit form of jcxz |
3ffd33cf | 2162 | 'F' => print 'w' or 'l' depending on address size prefix (loop insns) |
52fd6d94 | 2163 | 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns) |
5dd0794d | 2164 | 'H' => print ",pt" or ",pn" branch hint |
d1c36125 | 2165 | 'I' unused. |
8f570d62 | 2166 | 'J' unused. |
42903f7f | 2167 | 'K' => print 'd' or 'q' if rex prefix is present. |
252b5132 | 2168 | 'L' => print 'l' if suffix_always is true |
9d141669 | 2169 | 'M' => print 'r' if intel_mnemonic is false. |
252b5132 | 2170 | 'N' => print 'n' if instruction has no wait "prefix" |
a35ca55a | 2171 | 'O' => print 'd' or 'o' (or 'q' in Intel mode) |
52b15da3 | 2172 | 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix, |
98b528ac L |
2173 | or suffix_always is true. print 'q' if rex prefix is present. |
2174 | 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always | |
2175 | is true | |
a35ca55a | 2176 | 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode) |
52b15da3 | 2177 | 'S' => print 'w', 'l' or 'q' if suffix_always is true |
a72d2af2 L |
2178 | 'T' => print 'q' in 64bit mode if instruction has no operand size |
2179 | prefix and behave as 'P' otherwise | |
2180 | 'U' => print 'q' in 64bit mode if instruction has no operand size | |
2181 | prefix and behave as 'Q' otherwise | |
2182 | 'V' => print 'q' in 64bit mode if instruction has no operand size | |
2183 | prefix and behave as 'S' otherwise | |
a35ca55a | 2184 | 'W' => print 'b', 'w' or 'l' ('d' in Intel mode) |
9306ca4a | 2185 | 'X' => print 's', 'd' depending on data16 prefix (for XMM) |
9646c87b | 2186 | 'Y' unused. |
6dd5059a | 2187 | 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise |
9d141669 | 2188 | '!' => change condition from true to false or from false to true. |
98b528ac | 2189 | '%' => add 1 upper case letter to the macro. |
5990e377 JB |
2190 | '^' => print 'w', 'l', or 'q' (Intel64 ISA only) depending on operand size |
2191 | prefix or suffix_always is true (lcall/ljmp). | |
5db04b09 L |
2192 | '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending |
2193 | on operand size prefix. | |
07f5af7d L |
2194 | '&' => print 'q' in 64bit mode for Intel64 ISA or if instruction |
2195 | has no operand size prefix for AMD64 ISA, behave as 'P' | |
2196 | otherwise | |
98b528ac L |
2197 | |
2198 | 2 upper case letter macros: | |
04d824a4 JB |
2199 | "XY" => print 'x' or 'y' if suffix_always is true or no register |
2200 | operands and no broadcast. | |
2201 | "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no | |
2202 | register operands and no broadcast. | |
4b06377f | 2203 | "XW" => print 's', 'd' depending on the VEX.W bit (for FMA) |
589958d6 JB |
2204 | "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory |
2205 | operand or no operand at all in 64bit mode, or if suffix_always | |
2206 | is true. | |
4b06377f L |
2207 | "LB" => print "abs" in 64bit mode and behave as 'B' otherwise |
2208 | "LS" => print "abs" in 64bit mode and behave as 'S' otherwise | |
2209 | "LV" => print "abs" for 64bit operand and behave as 'S' otherwise | |
6c30d220 | 2210 | "LW" => print 'd', 'q' depending on the VEX.W bit |
4b4c407a L |
2211 | "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has |
2212 | an operand size prefix, or suffix_always is true. print | |
2213 | 'q' if rex prefix is present. | |
52b15da3 | 2214 | |
6439fc28 AM |
2215 | Many of the above letters print nothing in Intel mode. See "putop" |
2216 | for the details. | |
52b15da3 | 2217 | |
6439fc28 | 2218 | Braces '{' and '}', and vertical bars '|', indicate alternative |
7c52e0e8 | 2219 | mnemonic strings for AT&T and Intel. */ |
252b5132 | 2220 | |
6439fc28 | 2221 | static const struct dis386 dis386[] = { |
252b5132 | 2222 | /* 00 */ |
bf890a93 IT |
2223 | { "addB", { Ebh1, Gb }, 0 }, |
2224 | { "addS", { Evh1, Gv }, 0 }, | |
2225 | { "addB", { Gb, EbS }, 0 }, | |
2226 | { "addS", { Gv, EvS }, 0 }, | |
2227 | { "addB", { AL, Ib }, 0 }, | |
2228 | { "addS", { eAX, Iv }, 0 }, | |
4e7d34a6 L |
2229 | { X86_64_TABLE (X86_64_06) }, |
2230 | { X86_64_TABLE (X86_64_07) }, | |
252b5132 | 2231 | /* 08 */ |
bf890a93 IT |
2232 | { "orB", { Ebh1, Gb }, 0 }, |
2233 | { "orS", { Evh1, Gv }, 0 }, | |
2234 | { "orB", { Gb, EbS }, 0 }, | |
2235 | { "orS", { Gv, EvS }, 0 }, | |
2236 | { "orB", { AL, Ib }, 0 }, | |
2237 | { "orS", { eAX, Iv }, 0 }, | |
1673df32 | 2238 | { X86_64_TABLE (X86_64_0E) }, |
592d1631 | 2239 | { Bad_Opcode }, /* 0x0f extended opcode escape */ |
252b5132 | 2240 | /* 10 */ |
bf890a93 IT |
2241 | { "adcB", { Ebh1, Gb }, 0 }, |
2242 | { "adcS", { Evh1, Gv }, 0 }, | |
2243 | { "adcB", { Gb, EbS }, 0 }, | |
2244 | { "adcS", { Gv, EvS }, 0 }, | |
2245 | { "adcB", { AL, Ib }, 0 }, | |
2246 | { "adcS", { eAX, Iv }, 0 }, | |
4e7d34a6 L |
2247 | { X86_64_TABLE (X86_64_16) }, |
2248 | { X86_64_TABLE (X86_64_17) }, | |
252b5132 | 2249 | /* 18 */ |
bf890a93 IT |
2250 | { "sbbB", { Ebh1, Gb }, 0 }, |
2251 | { "sbbS", { Evh1, Gv }, 0 }, | |
2252 | { "sbbB", { Gb, EbS }, 0 }, | |
2253 | { "sbbS", { Gv, EvS }, 0 }, | |
2254 | { "sbbB", { AL, Ib }, 0 }, | |
2255 | { "sbbS", { eAX, Iv }, 0 }, | |
4e7d34a6 L |
2256 | { X86_64_TABLE (X86_64_1E) }, |
2257 | { X86_64_TABLE (X86_64_1F) }, | |
252b5132 | 2258 | /* 20 */ |
bf890a93 IT |
2259 | { "andB", { Ebh1, Gb }, 0 }, |
2260 | { "andS", { Evh1, Gv }, 0 }, | |
2261 | { "andB", { Gb, EbS }, 0 }, | |
2262 | { "andS", { Gv, EvS }, 0 }, | |
2263 | { "andB", { AL, Ib }, 0 }, | |
2264 | { "andS", { eAX, Iv }, 0 }, | |
592d1631 | 2265 | { Bad_Opcode }, /* SEG ES prefix */ |
4e7d34a6 | 2266 | { X86_64_TABLE (X86_64_27) }, |
252b5132 | 2267 | /* 28 */ |
bf890a93 IT |
2268 | { "subB", { Ebh1, Gb }, 0 }, |
2269 | { "subS", { Evh1, Gv }, 0 }, | |
2270 | { "subB", { Gb, EbS }, 0 }, | |
2271 | { "subS", { Gv, EvS }, 0 }, | |
2272 | { "subB", { AL, Ib }, 0 }, | |
2273 | { "subS", { eAX, Iv }, 0 }, | |
592d1631 | 2274 | { Bad_Opcode }, /* SEG CS prefix */ |
4e7d34a6 | 2275 | { X86_64_TABLE (X86_64_2F) }, |
252b5132 | 2276 | /* 30 */ |
bf890a93 IT |
2277 | { "xorB", { Ebh1, Gb }, 0 }, |
2278 | { "xorS", { Evh1, Gv }, 0 }, | |
2279 | { "xorB", { Gb, EbS }, 0 }, | |
2280 | { "xorS", { Gv, EvS }, 0 }, | |
2281 | { "xorB", { AL, Ib }, 0 }, | |
2282 | { "xorS", { eAX, Iv }, 0 }, | |
592d1631 | 2283 | { Bad_Opcode }, /* SEG SS prefix */ |
4e7d34a6 | 2284 | { X86_64_TABLE (X86_64_37) }, |
252b5132 | 2285 | /* 38 */ |
bf890a93 IT |
2286 | { "cmpB", { Eb, Gb }, 0 }, |
2287 | { "cmpS", { Ev, Gv }, 0 }, | |
2288 | { "cmpB", { Gb, EbS }, 0 }, | |
2289 | { "cmpS", { Gv, EvS }, 0 }, | |
2290 | { "cmpB", { AL, Ib }, 0 }, | |
2291 | { "cmpS", { eAX, Iv }, 0 }, | |
592d1631 | 2292 | { Bad_Opcode }, /* SEG DS prefix */ |
4e7d34a6 | 2293 | { X86_64_TABLE (X86_64_3F) }, |
252b5132 | 2294 | /* 40 */ |
bf890a93 IT |
2295 | { "inc{S|}", { RMeAX }, 0 }, |
2296 | { "inc{S|}", { RMeCX }, 0 }, | |
2297 | { "inc{S|}", { RMeDX }, 0 }, | |
2298 | { "inc{S|}", { RMeBX }, 0 }, | |
2299 | { "inc{S|}", { RMeSP }, 0 }, | |
2300 | { "inc{S|}", { RMeBP }, 0 }, | |
2301 | { "inc{S|}", { RMeSI }, 0 }, | |
2302 | { "inc{S|}", { RMeDI }, 0 }, | |
252b5132 | 2303 | /* 48 */ |
bf890a93 IT |
2304 | { "dec{S|}", { RMeAX }, 0 }, |
2305 | { "dec{S|}", { RMeCX }, 0 }, | |
2306 | { "dec{S|}", { RMeDX }, 0 }, | |
2307 | { "dec{S|}", { RMeBX }, 0 }, | |
2308 | { "dec{S|}", { RMeSP }, 0 }, | |
2309 | { "dec{S|}", { RMeBP }, 0 }, | |
2310 | { "dec{S|}", { RMeSI }, 0 }, | |
2311 | { "dec{S|}", { RMeDI }, 0 }, | |
252b5132 | 2312 | /* 50 */ |
bf890a93 IT |
2313 | { "pushV", { RMrAX }, 0 }, |
2314 | { "pushV", { RMrCX }, 0 }, | |
2315 | { "pushV", { RMrDX }, 0 }, | |
2316 | { "pushV", { RMrBX }, 0 }, | |
2317 | { "pushV", { RMrSP }, 0 }, | |
2318 | { "pushV", { RMrBP }, 0 }, | |
2319 | { "pushV", { RMrSI }, 0 }, | |
2320 | { "pushV", { RMrDI }, 0 }, | |
252b5132 | 2321 | /* 58 */ |
bf890a93 IT |
2322 | { "popV", { RMrAX }, 0 }, |
2323 | { "popV", { RMrCX }, 0 }, | |
2324 | { "popV", { RMrDX }, 0 }, | |
2325 | { "popV", { RMrBX }, 0 }, | |
2326 | { "popV", { RMrSP }, 0 }, | |
2327 | { "popV", { RMrBP }, 0 }, | |
2328 | { "popV", { RMrSI }, 0 }, | |
2329 | { "popV", { RMrDI }, 0 }, | |
252b5132 | 2330 | /* 60 */ |
4e7d34a6 L |
2331 | { X86_64_TABLE (X86_64_60) }, |
2332 | { X86_64_TABLE (X86_64_61) }, | |
2333 | { X86_64_TABLE (X86_64_62) }, | |
2334 | { X86_64_TABLE (X86_64_63) }, | |
592d1631 L |
2335 | { Bad_Opcode }, /* seg fs */ |
2336 | { Bad_Opcode }, /* seg gs */ | |
2337 | { Bad_Opcode }, /* op size prefix */ | |
2338 | { Bad_Opcode }, /* adr size prefix */ | |
252b5132 | 2339 | /* 68 */ |
bf890a93 IT |
2340 | { "pushT", { sIv }, 0 }, |
2341 | { "imulS", { Gv, Ev, Iv }, 0 }, | |
2342 | { "pushT", { sIbT }, 0 }, | |
2343 | { "imulS", { Gv, Ev, sIb }, 0 }, | |
2344 | { "ins{b|}", { Ybr, indirDX }, 0 }, | |
4e7d34a6 | 2345 | { X86_64_TABLE (X86_64_6D) }, |
bf890a93 | 2346 | { "outs{b|}", { indirDXr, Xb }, 0 }, |
4e7d34a6 | 2347 | { X86_64_TABLE (X86_64_6F) }, |
252b5132 | 2348 | /* 70 */ |
bf890a93 IT |
2349 | { "joH", { Jb, BND, cond_jump_flag }, 0 }, |
2350 | { "jnoH", { Jb, BND, cond_jump_flag }, 0 }, | |
2351 | { "jbH", { Jb, BND, cond_jump_flag }, 0 }, | |
2352 | { "jaeH", { Jb, BND, cond_jump_flag }, 0 }, | |
2353 | { "jeH", { Jb, BND, cond_jump_flag }, 0 }, | |
2354 | { "jneH", { Jb, BND, cond_jump_flag }, 0 }, | |
2355 | { "jbeH", { Jb, BND, cond_jump_flag }, 0 }, | |
2356 | { "jaH", { Jb, BND, cond_jump_flag }, 0 }, | |
252b5132 | 2357 | /* 78 */ |
bf890a93 IT |
2358 | { "jsH", { Jb, BND, cond_jump_flag }, 0 }, |
2359 | { "jnsH", { Jb, BND, cond_jump_flag }, 0 }, | |
2360 | { "jpH", { Jb, BND, cond_jump_flag }, 0 }, | |
2361 | { "jnpH", { Jb, BND, cond_jump_flag }, 0 }, | |
2362 | { "jlH", { Jb, BND, cond_jump_flag }, 0 }, | |
2363 | { "jgeH", { Jb, BND, cond_jump_flag }, 0 }, | |
2364 | { "jleH", { Jb, BND, cond_jump_flag }, 0 }, | |
2365 | { "jgH", { Jb, BND, cond_jump_flag }, 0 }, | |
252b5132 | 2366 | /* 80 */ |
1ceb70f8 L |
2367 | { REG_TABLE (REG_80) }, |
2368 | { REG_TABLE (REG_81) }, | |
d039fef3 | 2369 | { X86_64_TABLE (X86_64_82) }, |
7148c369 | 2370 | { REG_TABLE (REG_83) }, |
bf890a93 IT |
2371 | { "testB", { Eb, Gb }, 0 }, |
2372 | { "testS", { Ev, Gv }, 0 }, | |
2373 | { "xchgB", { Ebh2, Gb }, 0 }, | |
2374 | { "xchgS", { Evh2, Gv }, 0 }, | |
252b5132 | 2375 | /* 88 */ |
bf890a93 IT |
2376 | { "movB", { Ebh3, Gb }, 0 }, |
2377 | { "movS", { Evh3, Gv }, 0 }, | |
2378 | { "movB", { Gb, EbS }, 0 }, | |
2379 | { "movS", { Gv, EvS }, 0 }, | |
2380 | { "movD", { Sv, Sw }, 0 }, | |
1ceb70f8 | 2381 | { MOD_TABLE (MOD_8D) }, |
bf890a93 | 2382 | { "movD", { Sw, Sv }, 0 }, |
1ceb70f8 | 2383 | { REG_TABLE (REG_8F) }, |
252b5132 | 2384 | /* 90 */ |
1ceb70f8 | 2385 | { PREFIX_TABLE (PREFIX_90) }, |
bf890a93 IT |
2386 | { "xchgS", { RMeCX, eAX }, 0 }, |
2387 | { "xchgS", { RMeDX, eAX }, 0 }, | |
2388 | { "xchgS", { RMeBX, eAX }, 0 }, | |
2389 | { "xchgS", { RMeSP, eAX }, 0 }, | |
2390 | { "xchgS", { RMeBP, eAX }, 0 }, | |
2391 | { "xchgS", { RMeSI, eAX }, 0 }, | |
2392 | { "xchgS", { RMeDI, eAX }, 0 }, | |
252b5132 | 2393 | /* 98 */ |
bf890a93 IT |
2394 | { "cW{t|}R", { XX }, 0 }, |
2395 | { "cR{t|}O", { XX }, 0 }, | |
4e7d34a6 | 2396 | { X86_64_TABLE (X86_64_9A) }, |
592d1631 | 2397 | { Bad_Opcode }, /* fwait */ |
bf890a93 IT |
2398 | { "pushfT", { XX }, 0 }, |
2399 | { "popfT", { XX }, 0 }, | |
2400 | { "sahf", { XX }, 0 }, | |
2401 | { "lahf", { XX }, 0 }, | |
252b5132 | 2402 | /* a0 */ |
bf890a93 IT |
2403 | { "mov%LB", { AL, Ob }, 0 }, |
2404 | { "mov%LS", { eAX, Ov }, 0 }, | |
2405 | { "mov%LB", { Ob, AL }, 0 }, | |
2406 | { "mov%LS", { Ov, eAX }, 0 }, | |
2407 | { "movs{b|}", { Ybr, Xb }, 0 }, | |
2408 | { "movs{R|}", { Yvr, Xv }, 0 }, | |
2409 | { "cmps{b|}", { Xb, Yb }, 0 }, | |
2410 | { "cmps{R|}", { Xv, Yv }, 0 }, | |
252b5132 | 2411 | /* a8 */ |
bf890a93 IT |
2412 | { "testB", { AL, Ib }, 0 }, |
2413 | { "testS", { eAX, Iv }, 0 }, | |
2414 | { "stosB", { Ybr, AL }, 0 }, | |
2415 | { "stosS", { Yvr, eAX }, 0 }, | |
2416 | { "lodsB", { ALr, Xb }, 0 }, | |
2417 | { "lodsS", { eAXr, Xv }, 0 }, | |
2418 | { "scasB", { AL, Yb }, 0 }, | |
2419 | { "scasS", { eAX, Yv }, 0 }, | |
252b5132 | 2420 | /* b0 */ |
bf890a93 IT |
2421 | { "movB", { RMAL, Ib }, 0 }, |
2422 | { "movB", { RMCL, Ib }, 0 }, | |
2423 | { "movB", { RMDL, Ib }, 0 }, | |
2424 | { "movB", { RMBL, Ib }, 0 }, | |
2425 | { "movB", { RMAH, Ib }, 0 }, | |
2426 | { "movB", { RMCH, Ib }, 0 }, | |
2427 | { "movB", { RMDH, Ib }, 0 }, | |
2428 | { "movB", { RMBH, Ib }, 0 }, | |
252b5132 | 2429 | /* b8 */ |
bf890a93 IT |
2430 | { "mov%LV", { RMeAX, Iv64 }, 0 }, |
2431 | { "mov%LV", { RMeCX, Iv64 }, 0 }, | |
2432 | { "mov%LV", { RMeDX, Iv64 }, 0 }, | |
2433 | { "mov%LV", { RMeBX, Iv64 }, 0 }, | |
2434 | { "mov%LV", { RMeSP, Iv64 }, 0 }, | |
2435 | { "mov%LV", { RMeBP, Iv64 }, 0 }, | |
2436 | { "mov%LV", { RMeSI, Iv64 }, 0 }, | |
2437 | { "mov%LV", { RMeDI, Iv64 }, 0 }, | |
252b5132 | 2438 | /* c0 */ |
1ceb70f8 L |
2439 | { REG_TABLE (REG_C0) }, |
2440 | { REG_TABLE (REG_C1) }, | |
aeab2b26 JB |
2441 | { X86_64_TABLE (X86_64_C2) }, |
2442 | { X86_64_TABLE (X86_64_C3) }, | |
4e7d34a6 L |
2443 | { X86_64_TABLE (X86_64_C4) }, |
2444 | { X86_64_TABLE (X86_64_C5) }, | |
1ceb70f8 L |
2445 | { REG_TABLE (REG_C6) }, |
2446 | { REG_TABLE (REG_C7) }, | |
252b5132 | 2447 | /* c8 */ |
bf890a93 IT |
2448 | { "enterT", { Iw, Ib }, 0 }, |
2449 | { "leaveT", { XX }, 0 }, | |
8f570d62 JB |
2450 | { "{l|}ret{|f}P", { Iw }, 0 }, |
2451 | { "{l|}ret{|f}P", { XX }, 0 }, | |
bf890a93 IT |
2452 | { "int3", { XX }, 0 }, |
2453 | { "int", { Ib }, 0 }, | |
4e7d34a6 | 2454 | { X86_64_TABLE (X86_64_CE) }, |
bf890a93 | 2455 | { "iret%LP", { XX }, 0 }, |
252b5132 | 2456 | /* d0 */ |
1ceb70f8 L |
2457 | { REG_TABLE (REG_D0) }, |
2458 | { REG_TABLE (REG_D1) }, | |
2459 | { REG_TABLE (REG_D2) }, | |
2460 | { REG_TABLE (REG_D3) }, | |
4e7d34a6 L |
2461 | { X86_64_TABLE (X86_64_D4) }, |
2462 | { X86_64_TABLE (X86_64_D5) }, | |
592d1631 | 2463 | { Bad_Opcode }, |
bf890a93 | 2464 | { "xlat", { DSBX }, 0 }, |
252b5132 RH |
2465 | /* d8 */ |
2466 | { FLOAT }, | |
2467 | { FLOAT }, | |
2468 | { FLOAT }, | |
2469 | { FLOAT }, | |
2470 | { FLOAT }, | |
2471 | { FLOAT }, | |
2472 | { FLOAT }, | |
2473 | { FLOAT }, | |
2474 | /* e0 */ | |
bf890a93 IT |
2475 | { "loopneFH", { Jb, XX, loop_jcxz_flag }, 0 }, |
2476 | { "loopeFH", { Jb, XX, loop_jcxz_flag }, 0 }, | |
2477 | { "loopFH", { Jb, XX, loop_jcxz_flag }, 0 }, | |
2478 | { "jEcxzH", { Jb, XX, loop_jcxz_flag }, 0 }, | |
2479 | { "inB", { AL, Ib }, 0 }, | |
2480 | { "inG", { zAX, Ib }, 0 }, | |
2481 | { "outB", { Ib, AL }, 0 }, | |
2482 | { "outG", { Ib, zAX }, 0 }, | |
252b5132 | 2483 | /* e8 */ |
a72d2af2 L |
2484 | { X86_64_TABLE (X86_64_E8) }, |
2485 | { X86_64_TABLE (X86_64_E9) }, | |
4e7d34a6 | 2486 | { X86_64_TABLE (X86_64_EA) }, |
bf890a93 IT |
2487 | { "jmp", { Jb, BND }, 0 }, |
2488 | { "inB", { AL, indirDX }, 0 }, | |
2489 | { "inG", { zAX, indirDX }, 0 }, | |
2490 | { "outB", { indirDX, AL }, 0 }, | |
2491 | { "outG", { indirDX, zAX }, 0 }, | |
252b5132 | 2492 | /* f0 */ |
592d1631 | 2493 | { Bad_Opcode }, /* lock prefix */ |
bf890a93 | 2494 | { "icebp", { XX }, 0 }, |
592d1631 L |
2495 | { Bad_Opcode }, /* repne */ |
2496 | { Bad_Opcode }, /* repz */ | |
bf890a93 IT |
2497 | { "hlt", { XX }, 0 }, |
2498 | { "cmc", { XX }, 0 }, | |
1ceb70f8 L |
2499 | { REG_TABLE (REG_F6) }, |
2500 | { REG_TABLE (REG_F7) }, | |
252b5132 | 2501 | /* f8 */ |
bf890a93 IT |
2502 | { "clc", { XX }, 0 }, |
2503 | { "stc", { XX }, 0 }, | |
2504 | { "cli", { XX }, 0 }, | |
2505 | { "sti", { XX }, 0 }, | |
2506 | { "cld", { XX }, 0 }, | |
2507 | { "std", { XX }, 0 }, | |
1ceb70f8 L |
2508 | { REG_TABLE (REG_FE) }, |
2509 | { REG_TABLE (REG_FF) }, | |
252b5132 RH |
2510 | }; |
2511 | ||
6439fc28 | 2512 | static const struct dis386 dis386_twobyte[] = { |
252b5132 | 2513 | /* 00 */ |
1ceb70f8 L |
2514 | { REG_TABLE (REG_0F00 ) }, |
2515 | { REG_TABLE (REG_0F01 ) }, | |
bf890a93 IT |
2516 | { "larS", { Gv, Ew }, 0 }, |
2517 | { "lslS", { Gv, Ew }, 0 }, | |
592d1631 | 2518 | { Bad_Opcode }, |
bf890a93 IT |
2519 | { "syscall", { XX }, 0 }, |
2520 | { "clts", { XX }, 0 }, | |
589958d6 | 2521 | { "sysret%LQ", { XX }, 0 }, |
252b5132 | 2522 | /* 08 */ |
bf890a93 | 2523 | { "invd", { XX }, 0 }, |
3233d7d0 | 2524 | { PREFIX_TABLE (PREFIX_0F09) }, |
592d1631 | 2525 | { Bad_Opcode }, |
bf890a93 | 2526 | { "ud2", { XX }, 0 }, |
592d1631 | 2527 | { Bad_Opcode }, |
b5b1fc4f | 2528 | { REG_TABLE (REG_0F0D) }, |
bf890a93 IT |
2529 | { "femms", { XX }, 0 }, |
2530 | { "", { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix. */ | |
252b5132 | 2531 | /* 10 */ |
1ceb70f8 L |
2532 | { PREFIX_TABLE (PREFIX_0F10) }, |
2533 | { PREFIX_TABLE (PREFIX_0F11) }, | |
2534 | { PREFIX_TABLE (PREFIX_0F12) }, | |
2535 | { MOD_TABLE (MOD_0F13) }, | |
507bd325 L |
2536 | { "unpcklpX", { XM, EXx }, PREFIX_OPCODE }, |
2537 | { "unpckhpX", { XM, EXx }, PREFIX_OPCODE }, | |
1ceb70f8 L |
2538 | { PREFIX_TABLE (PREFIX_0F16) }, |
2539 | { MOD_TABLE (MOD_0F17) }, | |
252b5132 | 2540 | /* 18 */ |
1ceb70f8 | 2541 | { REG_TABLE (REG_0F18) }, |
bf890a93 | 2542 | { "nopQ", { Ev }, 0 }, |
7e8b059b L |
2543 | { PREFIX_TABLE (PREFIX_0F1A) }, |
2544 | { PREFIX_TABLE (PREFIX_0F1B) }, | |
c48935d7 | 2545 | { PREFIX_TABLE (PREFIX_0F1C) }, |
bf890a93 | 2546 | { "nopQ", { Ev }, 0 }, |
603555e5 | 2547 | { PREFIX_TABLE (PREFIX_0F1E) }, |
bf890a93 | 2548 | { "nopQ", { Ev }, 0 }, |
252b5132 | 2549 | /* 20 */ |
bf890a93 IT |
2550 | { "movZ", { Rm, Cm }, 0 }, |
2551 | { "movZ", { Rm, Dm }, 0 }, | |
2552 | { "movZ", { Cm, Rm }, 0 }, | |
2553 | { "movZ", { Dm, Rm }, 0 }, | |
1ceb70f8 | 2554 | { MOD_TABLE (MOD_0F24) }, |
592d1631 | 2555 | { Bad_Opcode }, |
1ceb70f8 | 2556 | { MOD_TABLE (MOD_0F26) }, |
592d1631 | 2557 | { Bad_Opcode }, |
252b5132 | 2558 | /* 28 */ |
507bd325 L |
2559 | { "movapX", { XM, EXx }, PREFIX_OPCODE }, |
2560 | { "movapX", { EXxS, XM }, PREFIX_OPCODE }, | |
1ceb70f8 L |
2561 | { PREFIX_TABLE (PREFIX_0F2A) }, |
2562 | { PREFIX_TABLE (PREFIX_0F2B) }, | |
2563 | { PREFIX_TABLE (PREFIX_0F2C) }, | |
2564 | { PREFIX_TABLE (PREFIX_0F2D) }, | |
2565 | { PREFIX_TABLE (PREFIX_0F2E) }, | |
2566 | { PREFIX_TABLE (PREFIX_0F2F) }, | |
252b5132 | 2567 | /* 30 */ |
bf890a93 IT |
2568 | { "wrmsr", { XX }, 0 }, |
2569 | { "rdtsc", { XX }, 0 }, | |
2570 | { "rdmsr", { XX }, 0 }, | |
2571 | { "rdpmc", { XX }, 0 }, | |
d835a58b JB |
2572 | { "sysenter", { SEP }, 0 }, |
2573 | { "sysexit", { SEP }, 0 }, | |
592d1631 | 2574 | { Bad_Opcode }, |
bf890a93 | 2575 | { "getsec", { XX }, 0 }, |
252b5132 | 2576 | /* 38 */ |
507bd325 | 2577 | { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) }, |
592d1631 | 2578 | { Bad_Opcode }, |
507bd325 | 2579 | { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) }, |
592d1631 L |
2580 | { Bad_Opcode }, |
2581 | { Bad_Opcode }, | |
2582 | { Bad_Opcode }, | |
2583 | { Bad_Opcode }, | |
2584 | { Bad_Opcode }, | |
252b5132 | 2585 | /* 40 */ |
bf890a93 IT |
2586 | { "cmovoS", { Gv, Ev }, 0 }, |
2587 | { "cmovnoS", { Gv, Ev }, 0 }, | |
2588 | { "cmovbS", { Gv, Ev }, 0 }, | |
2589 | { "cmovaeS", { Gv, Ev }, 0 }, | |
2590 | { "cmoveS", { Gv, Ev }, 0 }, | |
2591 | { "cmovneS", { Gv, Ev }, 0 }, | |
2592 | { "cmovbeS", { Gv, Ev }, 0 }, | |
2593 | { "cmovaS", { Gv, Ev }, 0 }, | |
252b5132 | 2594 | /* 48 */ |
bf890a93 IT |
2595 | { "cmovsS", { Gv, Ev }, 0 }, |
2596 | { "cmovnsS", { Gv, Ev }, 0 }, | |
2597 | { "cmovpS", { Gv, Ev }, 0 }, | |
2598 | { "cmovnpS", { Gv, Ev }, 0 }, | |
2599 | { "cmovlS", { Gv, Ev }, 0 }, | |
2600 | { "cmovgeS", { Gv, Ev }, 0 }, | |
2601 | { "cmovleS", { Gv, Ev }, 0 }, | |
2602 | { "cmovgS", { Gv, Ev }, 0 }, | |
252b5132 | 2603 | /* 50 */ |
a5aaedb9 | 2604 | { MOD_TABLE (MOD_0F50) }, |
1ceb70f8 L |
2605 | { PREFIX_TABLE (PREFIX_0F51) }, |
2606 | { PREFIX_TABLE (PREFIX_0F52) }, | |
2607 | { PREFIX_TABLE (PREFIX_0F53) }, | |
507bd325 L |
2608 | { "andpX", { XM, EXx }, PREFIX_OPCODE }, |
2609 | { "andnpX", { XM, EXx }, PREFIX_OPCODE }, | |
2610 | { "orpX", { XM, EXx }, PREFIX_OPCODE }, | |
2611 | { "xorpX", { XM, EXx }, PREFIX_OPCODE }, | |
252b5132 | 2612 | /* 58 */ |
1ceb70f8 L |
2613 | { PREFIX_TABLE (PREFIX_0F58) }, |
2614 | { PREFIX_TABLE (PREFIX_0F59) }, | |
2615 | { PREFIX_TABLE (PREFIX_0F5A) }, | |
2616 | { PREFIX_TABLE (PREFIX_0F5B) }, | |
2617 | { PREFIX_TABLE (PREFIX_0F5C) }, | |
2618 | { PREFIX_TABLE (PREFIX_0F5D) }, | |
2619 | { PREFIX_TABLE (PREFIX_0F5E) }, | |
2620 | { PREFIX_TABLE (PREFIX_0F5F) }, | |
252b5132 | 2621 | /* 60 */ |
1ceb70f8 L |
2622 | { PREFIX_TABLE (PREFIX_0F60) }, |
2623 | { PREFIX_TABLE (PREFIX_0F61) }, | |
2624 | { PREFIX_TABLE (PREFIX_0F62) }, | |
507bd325 L |
2625 | { "packsswb", { MX, EM }, PREFIX_OPCODE }, |
2626 | { "pcmpgtb", { MX, EM }, PREFIX_OPCODE }, | |
2627 | { "pcmpgtw", { MX, EM }, PREFIX_OPCODE }, | |
2628 | { "pcmpgtd", { MX, EM }, PREFIX_OPCODE }, | |
2629 | { "packuswb", { MX, EM }, PREFIX_OPCODE }, | |
252b5132 | 2630 | /* 68 */ |
507bd325 L |
2631 | { "punpckhbw", { MX, EM }, PREFIX_OPCODE }, |
2632 | { "punpckhwd", { MX, EM }, PREFIX_OPCODE }, | |
2633 | { "punpckhdq", { MX, EM }, PREFIX_OPCODE }, | |
2634 | { "packssdw", { MX, EM }, PREFIX_OPCODE }, | |
1ceb70f8 L |
2635 | { PREFIX_TABLE (PREFIX_0F6C) }, |
2636 | { PREFIX_TABLE (PREFIX_0F6D) }, | |
507bd325 | 2637 | { "movK", { MX, Edq }, PREFIX_OPCODE }, |
1ceb70f8 | 2638 | { PREFIX_TABLE (PREFIX_0F6F) }, |
252b5132 | 2639 | /* 70 */ |
1ceb70f8 L |
2640 | { PREFIX_TABLE (PREFIX_0F70) }, |
2641 | { REG_TABLE (REG_0F71) }, | |
2642 | { REG_TABLE (REG_0F72) }, | |
2643 | { REG_TABLE (REG_0F73) }, | |
507bd325 L |
2644 | { "pcmpeqb", { MX, EM }, PREFIX_OPCODE }, |
2645 | { "pcmpeqw", { MX, EM }, PREFIX_OPCODE }, | |
2646 | { "pcmpeqd", { MX, EM }, PREFIX_OPCODE }, | |
2647 | { "emms", { XX }, PREFIX_OPCODE }, | |
252b5132 | 2648 | /* 78 */ |
1ceb70f8 L |
2649 | { PREFIX_TABLE (PREFIX_0F78) }, |
2650 | { PREFIX_TABLE (PREFIX_0F79) }, | |
1f334aeb | 2651 | { Bad_Opcode }, |
592d1631 | 2652 | { Bad_Opcode }, |
1ceb70f8 L |
2653 | { PREFIX_TABLE (PREFIX_0F7C) }, |
2654 | { PREFIX_TABLE (PREFIX_0F7D) }, | |
2655 | { PREFIX_TABLE (PREFIX_0F7E) }, | |
2656 | { PREFIX_TABLE (PREFIX_0F7F) }, | |
252b5132 | 2657 | /* 80 */ |
bf890a93 IT |
2658 | { "joH", { Jv, BND, cond_jump_flag }, 0 }, |
2659 | { "jnoH", { Jv, BND, cond_jump_flag }, 0 }, | |
2660 | { "jbH", { Jv, BND, cond_jump_flag }, 0 }, | |
2661 | { "jaeH", { Jv, BND, cond_jump_flag }, 0 }, | |
2662 | { "jeH", { Jv, BND, cond_jump_flag }, 0 }, | |
2663 | { "jneH", { Jv, BND, cond_jump_flag }, 0 }, | |
2664 | { "jbeH", { Jv, BND, cond_jump_flag }, 0 }, | |
2665 | { "jaH", { Jv, BND, cond_jump_flag }, 0 }, | |
252b5132 | 2666 | /* 88 */ |
bf890a93 IT |
2667 | { "jsH", { Jv, BND, cond_jump_flag }, 0 }, |
2668 | { "jnsH", { Jv, BND, cond_jump_flag }, 0 }, | |
2669 | { "jpH", { Jv, BND, cond_jump_flag }, 0 }, | |
2670 | { "jnpH", { Jv, BND, cond_jump_flag }, 0 }, | |
2671 | { "jlH", { Jv, BND, cond_jump_flag }, 0 }, | |
2672 | { "jgeH", { Jv, BND, cond_jump_flag }, 0 }, | |
2673 | { "jleH", { Jv, BND, cond_jump_flag }, 0 }, | |
2674 | { "jgH", { Jv, BND, cond_jump_flag }, 0 }, | |
252b5132 | 2675 | /* 90 */ |
bf890a93 IT |
2676 | { "seto", { Eb }, 0 }, |
2677 | { "setno", { Eb }, 0 }, | |
2678 | { "setb", { Eb }, 0 }, | |
2679 | { "setae", { Eb }, 0 }, | |
2680 | { "sete", { Eb }, 0 }, | |
2681 | { "setne", { Eb }, 0 }, | |
2682 | { "setbe", { Eb }, 0 }, | |
2683 | { "seta", { Eb }, 0 }, | |
252b5132 | 2684 | /* 98 */ |
bf890a93 IT |
2685 | { "sets", { Eb }, 0 }, |
2686 | { "setns", { Eb }, 0 }, | |
2687 | { "setp", { Eb }, 0 }, | |
2688 | { "setnp", { Eb }, 0 }, | |
2689 | { "setl", { Eb }, 0 }, | |
2690 | { "setge", { Eb }, 0 }, | |
2691 | { "setle", { Eb }, 0 }, | |
2692 | { "setg", { Eb }, 0 }, | |
252b5132 | 2693 | /* a0 */ |
bf890a93 IT |
2694 | { "pushT", { fs }, 0 }, |
2695 | { "popT", { fs }, 0 }, | |
2696 | { "cpuid", { XX }, 0 }, | |
2697 | { "btS", { Ev, Gv }, 0 }, | |
2698 | { "shldS", { Ev, Gv, Ib }, 0 }, | |
2699 | { "shldS", { Ev, Gv, CL }, 0 }, | |
1ceb70f8 L |
2700 | { REG_TABLE (REG_0FA6) }, |
2701 | { REG_TABLE (REG_0FA7) }, | |
252b5132 | 2702 | /* a8 */ |
bf890a93 IT |
2703 | { "pushT", { gs }, 0 }, |
2704 | { "popT", { gs }, 0 }, | |
2705 | { "rsm", { XX }, 0 }, | |
2706 | { "btsS", { Evh1, Gv }, 0 }, | |
2707 | { "shrdS", { Ev, Gv, Ib }, 0 }, | |
2708 | { "shrdS", { Ev, Gv, CL }, 0 }, | |
1ceb70f8 | 2709 | { REG_TABLE (REG_0FAE) }, |
bf890a93 | 2710 | { "imulS", { Gv, Ev }, 0 }, |
252b5132 | 2711 | /* b0 */ |
bf890a93 IT |
2712 | { "cmpxchgB", { Ebh1, Gb }, 0 }, |
2713 | { "cmpxchgS", { Evh1, Gv }, 0 }, | |
1ceb70f8 | 2714 | { MOD_TABLE (MOD_0FB2) }, |
bf890a93 | 2715 | { "btrS", { Evh1, Gv }, 0 }, |
1ceb70f8 L |
2716 | { MOD_TABLE (MOD_0FB4) }, |
2717 | { MOD_TABLE (MOD_0FB5) }, | |
bf890a93 IT |
2718 | { "movz{bR|x}", { Gv, Eb }, 0 }, |
2719 | { "movz{wR|x}", { Gv, Ew }, 0 }, /* yes, there really is movzww ! */ | |
252b5132 | 2720 | /* b8 */ |
1ceb70f8 | 2721 | { PREFIX_TABLE (PREFIX_0FB8) }, |
66f1eba0 | 2722 | { "ud1S", { Gv, Ev }, 0 }, |
1ceb70f8 | 2723 | { REG_TABLE (REG_0FBA) }, |
bf890a93 | 2724 | { "btcS", { Evh1, Gv }, 0 }, |
f12dc422 | 2725 | { PREFIX_TABLE (PREFIX_0FBC) }, |
1ceb70f8 | 2726 | { PREFIX_TABLE (PREFIX_0FBD) }, |
bf890a93 IT |
2727 | { "movs{bR|x}", { Gv, Eb }, 0 }, |
2728 | { "movs{wR|x}", { Gv, Ew }, 0 }, /* yes, there really is movsww ! */ | |
252b5132 | 2729 | /* c0 */ |
bf890a93 IT |
2730 | { "xaddB", { Ebh1, Gb }, 0 }, |
2731 | { "xaddS", { Evh1, Gv }, 0 }, | |
1ceb70f8 | 2732 | { PREFIX_TABLE (PREFIX_0FC2) }, |
a8484f96 | 2733 | { MOD_TABLE (MOD_0FC3) }, |
507bd325 L |
2734 | { "pinsrw", { MX, Edqw, Ib }, PREFIX_OPCODE }, |
2735 | { "pextrw", { Gdq, MS, Ib }, PREFIX_OPCODE }, | |
2736 | { "shufpX", { XM, EXx, Ib }, PREFIX_OPCODE }, | |
1ceb70f8 | 2737 | { REG_TABLE (REG_0FC7) }, |
252b5132 | 2738 | /* c8 */ |
bf890a93 IT |
2739 | { "bswap", { RMeAX }, 0 }, |
2740 | { "bswap", { RMeCX }, 0 }, | |
2741 | { "bswap", { RMeDX }, 0 }, | |
2742 | { "bswap", { RMeBX }, 0 }, | |
2743 | { "bswap", { RMeSP }, 0 }, | |
2744 | { "bswap", { RMeBP }, 0 }, | |
2745 | { "bswap", { RMeSI }, 0 }, | |
2746 | { "bswap", { RMeDI }, 0 }, | |
252b5132 | 2747 | /* d0 */ |
1ceb70f8 | 2748 | { PREFIX_TABLE (PREFIX_0FD0) }, |
507bd325 L |
2749 | { "psrlw", { MX, EM }, PREFIX_OPCODE }, |
2750 | { "psrld", { MX, EM }, PREFIX_OPCODE }, | |
2751 | { "psrlq", { MX, EM }, PREFIX_OPCODE }, | |
2752 | { "paddq", { MX, EM }, PREFIX_OPCODE }, | |
2753 | { "pmullw", { MX, EM }, PREFIX_OPCODE }, | |
1ceb70f8 | 2754 | { PREFIX_TABLE (PREFIX_0FD6) }, |
75c135a8 | 2755 | { MOD_TABLE (MOD_0FD7) }, |
252b5132 | 2756 | /* d8 */ |
507bd325 L |
2757 | { "psubusb", { MX, EM }, PREFIX_OPCODE }, |
2758 | { "psubusw", { MX, EM }, PREFIX_OPCODE }, | |
2759 | { "pminub", { MX, EM }, PREFIX_OPCODE }, | |
2760 | { "pand", { MX, EM }, PREFIX_OPCODE }, | |
2761 | { "paddusb", { MX, EM }, PREFIX_OPCODE }, | |
2762 | { "paddusw", { MX, EM }, PREFIX_OPCODE }, | |
2763 | { "pmaxub", { MX, EM }, PREFIX_OPCODE }, | |
2764 | { "pandn", { MX, EM }, PREFIX_OPCODE }, | |
252b5132 | 2765 | /* e0 */ |
507bd325 L |
2766 | { "pavgb", { MX, EM }, PREFIX_OPCODE }, |
2767 | { "psraw", { MX, EM }, PREFIX_OPCODE }, | |
2768 | { "psrad", { MX, EM }, PREFIX_OPCODE }, | |
2769 | { "pavgw", { MX, EM }, PREFIX_OPCODE }, | |
2770 | { "pmulhuw", { MX, EM }, PREFIX_OPCODE }, | |
2771 | { "pmulhw", { MX, EM }, PREFIX_OPCODE }, | |
1ceb70f8 L |
2772 | { PREFIX_TABLE (PREFIX_0FE6) }, |
2773 | { PREFIX_TABLE (PREFIX_0FE7) }, | |
252b5132 | 2774 | /* e8 */ |
507bd325 L |
2775 | { "psubsb", { MX, EM }, PREFIX_OPCODE }, |
2776 | { "psubsw", { MX, EM }, PREFIX_OPCODE }, | |
2777 | { "pminsw", { MX, EM }, PREFIX_OPCODE }, | |
2778 | { "por", { MX, EM }, PREFIX_OPCODE }, | |
2779 | { "paddsb", { MX, EM }, PREFIX_OPCODE }, | |
2780 | { "paddsw", { MX, EM }, PREFIX_OPCODE }, | |
2781 | { "pmaxsw", { MX, EM }, PREFIX_OPCODE }, | |
2782 | { "pxor", { MX, EM }, PREFIX_OPCODE }, | |
252b5132 | 2783 | /* f0 */ |
1ceb70f8 | 2784 | { PREFIX_TABLE (PREFIX_0FF0) }, |
507bd325 L |
2785 | { "psllw", { MX, EM }, PREFIX_OPCODE }, |
2786 | { "pslld", { MX, EM }, PREFIX_OPCODE }, | |
2787 | { "psllq", { MX, EM }, PREFIX_OPCODE }, | |
2788 | { "pmuludq", { MX, EM }, PREFIX_OPCODE }, | |
2789 | { "pmaddwd", { MX, EM }, PREFIX_OPCODE }, | |
2790 | { "psadbw", { MX, EM }, PREFIX_OPCODE }, | |
1ceb70f8 | 2791 | { PREFIX_TABLE (PREFIX_0FF7) }, |
252b5132 | 2792 | /* f8 */ |
507bd325 L |
2793 | { "psubb", { MX, EM }, PREFIX_OPCODE }, |
2794 | { "psubw", { MX, EM }, PREFIX_OPCODE }, | |
2795 | { "psubd", { MX, EM }, PREFIX_OPCODE }, | |
2796 | { "psubq", { MX, EM }, PREFIX_OPCODE }, | |
2797 | { "paddb", { MX, EM }, PREFIX_OPCODE }, | |
2798 | { "paddw", { MX, EM }, PREFIX_OPCODE }, | |
2799 | { "paddd", { MX, EM }, PREFIX_OPCODE }, | |
66f1eba0 | 2800 | { "ud0S", { Gv, Ev }, 0 }, |
252b5132 RH |
2801 | }; |
2802 | ||
2803 | static const unsigned char onebyte_has_modrm[256] = { | |
c608c12e AM |
2804 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ |
2805 | /* ------------------------------- */ | |
2806 | /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */ | |
2807 | /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */ | |
2808 | /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */ | |
2809 | /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */ | |
2810 | /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */ | |
2811 | /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */ | |
2812 | /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */ | |
2813 | /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */ | |
2814 | /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */ | |
2815 | /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */ | |
2816 | /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */ | |
2817 | /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */ | |
2818 | /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */ | |
2819 | /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */ | |
2820 | /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */ | |
2821 | /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */ | |
2822 | /* ------------------------------- */ | |
2823 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ | |
252b5132 RH |
2824 | }; |
2825 | ||
2826 | static const unsigned char twobyte_has_modrm[256] = { | |
c608c12e AM |
2827 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ |
2828 | /* ------------------------------- */ | |
252b5132 | 2829 | /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */ |
b5b1fc4f | 2830 | /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */ |
85f10a01 | 2831 | /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */ |
331d2d0d | 2832 | /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */ |
252b5132 | 2833 | /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */ |
4bba6815 AM |
2834 | /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */ |
2835 | /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */ | |
85f10a01 | 2836 | /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */ |
252b5132 RH |
2837 | /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */ |
2838 | /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */ | |
30d1c836 | 2839 | /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */ |
66f1eba0 | 2840 | /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */ |
252b5132 | 2841 | /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */ |
ca164297 | 2842 | /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */ |
4bba6815 | 2843 | /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */ |
66f1eba0 | 2844 | /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1 /* ff */ |
c608c12e AM |
2845 | /* ------------------------------- */ |
2846 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ | |
2847 | }; | |
2848 | ||
252b5132 RH |
2849 | static char obuf[100]; |
2850 | static char *obufp; | |
ea397f5b | 2851 | static char *mnemonicendp; |
252b5132 RH |
2852 | static char scratchbuf[100]; |
2853 | static unsigned char *start_codep; | |
2854 | static unsigned char *insn_codep; | |
2855 | static unsigned char *codep; | |
285ca992 | 2856 | static unsigned char *end_codep; |
f16cd0d5 L |
2857 | static int last_lock_prefix; |
2858 | static int last_repz_prefix; | |
2859 | static int last_repnz_prefix; | |
2860 | static int last_data_prefix; | |
2861 | static int last_addr_prefix; | |
2862 | static int last_rex_prefix; | |
2863 | static int last_seg_prefix; | |
d9949a36 | 2864 | static int fwait_prefix; |
285ca992 L |
2865 | /* The active segment register prefix. */ |
2866 | static int active_seg_prefix; | |
f16cd0d5 L |
2867 | #define MAX_CODE_LENGTH 15 |
2868 | /* We can up to 14 prefixes since the maximum instruction length is | |
2869 | 15bytes. */ | |
2870 | static int all_prefixes[MAX_CODE_LENGTH - 1]; | |
252b5132 | 2871 | static disassemble_info *the_info; |
7967e09e L |
2872 | static struct |
2873 | { | |
2874 | int mod; | |
7967e09e | 2875 | int reg; |
484c222e | 2876 | int rm; |
7967e09e L |
2877 | } |
2878 | modrm; | |
4bba6815 | 2879 | static unsigned char need_modrm; |
dfc8cf43 L |
2880 | static struct |
2881 | { | |
2882 | int scale; | |
2883 | int index; | |
2884 | int base; | |
2885 | } | |
2886 | sib; | |
c0f3af97 L |
2887 | static struct |
2888 | { | |
2889 | int register_specifier; | |
2890 | int length; | |
2891 | int prefix; | |
2892 | int w; | |
43234a1e L |
2893 | int evex; |
2894 | int r; | |
2895 | int v; | |
2896 | int mask_register_specifier; | |
2897 | int zeroing; | |
2898 | int ll; | |
2899 | int b; | |
c0f3af97 L |
2900 | } |
2901 | vex; | |
2902 | static unsigned char need_vex; | |
2903 | static unsigned char need_vex_reg; | |
dae39acc | 2904 | static unsigned char vex_w_done; |
252b5132 | 2905 | |
ea397f5b L |
2906 | struct op |
2907 | { | |
2908 | const char *name; | |
2909 | unsigned int len; | |
2910 | }; | |
2911 | ||
4bba6815 AM |
2912 | /* If we are accessing mod/rm/reg without need_modrm set, then the |
2913 | values are stale. Hitting this abort likely indicates that you | |
2914 | need to update onebyte_has_modrm or twobyte_has_modrm. */ | |
2915 | #define MODRM_CHECK if (!need_modrm) abort () | |
2916 | ||
d708bcba AM |
2917 | static const char **names64; |
2918 | static const char **names32; | |
2919 | static const char **names16; | |
2920 | static const char **names8; | |
2921 | static const char **names8rex; | |
2922 | static const char **names_seg; | |
db51cc60 L |
2923 | static const char *index64; |
2924 | static const char *index32; | |
d708bcba | 2925 | static const char **index16; |
7e8b059b | 2926 | static const char **names_bnd; |
d708bcba AM |
2927 | |
2928 | static const char *intel_names64[] = { | |
2929 | "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi", | |
2930 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15" | |
2931 | }; | |
2932 | static const char *intel_names32[] = { | |
2933 | "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi", | |
2934 | "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d" | |
2935 | }; | |
2936 | static const char *intel_names16[] = { | |
2937 | "ax", "cx", "dx", "bx", "sp", "bp", "si", "di", | |
2938 | "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w" | |
2939 | }; | |
2940 | static const char *intel_names8[] = { | |
2941 | "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh", | |
2942 | }; | |
2943 | static const char *intel_names8rex[] = { | |
2944 | "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil", | |
2945 | "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b" | |
2946 | }; | |
2947 | static const char *intel_names_seg[] = { | |
2948 | "es", "cs", "ss", "ds", "fs", "gs", "?", "?", | |
2949 | }; | |
db51cc60 L |
2950 | static const char *intel_index64 = "riz"; |
2951 | static const char *intel_index32 = "eiz"; | |
d708bcba AM |
2952 | static const char *intel_index16[] = { |
2953 | "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx" | |
2954 | }; | |
2955 | ||
2956 | static const char *att_names64[] = { | |
2957 | "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi", | |
52b15da3 JH |
2958 | "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15" |
2959 | }; | |
d708bcba AM |
2960 | static const char *att_names32[] = { |
2961 | "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi", | |
52b15da3 | 2962 | "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d" |
252b5132 | 2963 | }; |
d708bcba AM |
2964 | static const char *att_names16[] = { |
2965 | "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di", | |
52b15da3 | 2966 | "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w" |
252b5132 | 2967 | }; |
d708bcba AM |
2968 | static const char *att_names8[] = { |
2969 | "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh", | |
252b5132 | 2970 | }; |
d708bcba AM |
2971 | static const char *att_names8rex[] = { |
2972 | "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil", | |
52b15da3 JH |
2973 | "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b" |
2974 | }; | |
d708bcba AM |
2975 | static const char *att_names_seg[] = { |
2976 | "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?", | |
252b5132 | 2977 | }; |
db51cc60 L |
2978 | static const char *att_index64 = "%riz"; |
2979 | static const char *att_index32 = "%eiz"; | |
d708bcba AM |
2980 | static const char *att_index16[] = { |
2981 | "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx" | |
252b5132 RH |
2982 | }; |
2983 | ||
b9733481 L |
2984 | static const char **names_mm; |
2985 | static const char *intel_names_mm[] = { | |
2986 | "mm0", "mm1", "mm2", "mm3", | |
2987 | "mm4", "mm5", "mm6", "mm7" | |
2988 | }; | |
2989 | static const char *att_names_mm[] = { | |
2990 | "%mm0", "%mm1", "%mm2", "%mm3", | |
2991 | "%mm4", "%mm5", "%mm6", "%mm7" | |
2992 | }; | |
2993 | ||
7e8b059b L |
2994 | static const char *intel_names_bnd[] = { |
2995 | "bnd0", "bnd1", "bnd2", "bnd3" | |
2996 | }; | |
2997 | ||
2998 | static const char *att_names_bnd[] = { | |
2999 | "%bnd0", "%bnd1", "%bnd2", "%bnd3" | |
3000 | }; | |
3001 | ||
b9733481 L |
3002 | static const char **names_xmm; |
3003 | static const char *intel_names_xmm[] = { | |
3004 | "xmm0", "xmm1", "xmm2", "xmm3", | |
3005 | "xmm4", "xmm5", "xmm6", "xmm7", | |
3006 | "xmm8", "xmm9", "xmm10", "xmm11", | |
43234a1e L |
3007 | "xmm12", "xmm13", "xmm14", "xmm15", |
3008 | "xmm16", "xmm17", "xmm18", "xmm19", | |
3009 | "xmm20", "xmm21", "xmm22", "xmm23", | |
3010 | "xmm24", "xmm25", "xmm26", "xmm27", | |
3011 | "xmm28", "xmm29", "xmm30", "xmm31" | |
b9733481 L |
3012 | }; |
3013 | static const char *att_names_xmm[] = { | |
3014 | "%xmm0", "%xmm1", "%xmm2", "%xmm3", | |
3015 | "%xmm4", "%xmm5", "%xmm6", "%xmm7", | |
3016 | "%xmm8", "%xmm9", "%xmm10", "%xmm11", | |
43234a1e L |
3017 | "%xmm12", "%xmm13", "%xmm14", "%xmm15", |
3018 | "%xmm16", "%xmm17", "%xmm18", "%xmm19", | |
3019 | "%xmm20", "%xmm21", "%xmm22", "%xmm23", | |
3020 | "%xmm24", "%xmm25", "%xmm26", "%xmm27", | |
3021 | "%xmm28", "%xmm29", "%xmm30", "%xmm31" | |
b9733481 L |
3022 | }; |
3023 | ||
3024 | static const char **names_ymm; | |
3025 | static const char *intel_names_ymm[] = { | |
3026 | "ymm0", "ymm1", "ymm2", "ymm3", | |
3027 | "ymm4", "ymm5", "ymm6", "ymm7", | |
3028 | "ymm8", "ymm9", "ymm10", "ymm11", | |
43234a1e L |
3029 | "ymm12", "ymm13", "ymm14", "ymm15", |
3030 | "ymm16", "ymm17", "ymm18", "ymm19", | |
3031 | "ymm20", "ymm21", "ymm22", "ymm23", | |
3032 | "ymm24", "ymm25", "ymm26", "ymm27", | |
3033 | "ymm28", "ymm29", "ymm30", "ymm31" | |
b9733481 L |
3034 | }; |
3035 | static const char *att_names_ymm[] = { | |
3036 | "%ymm0", "%ymm1", "%ymm2", "%ymm3", | |
3037 | "%ymm4", "%ymm5", "%ymm6", "%ymm7", | |
3038 | "%ymm8", "%ymm9", "%ymm10", "%ymm11", | |
43234a1e L |
3039 | "%ymm12", "%ymm13", "%ymm14", "%ymm15", |
3040 | "%ymm16", "%ymm17", "%ymm18", "%ymm19", | |
3041 | "%ymm20", "%ymm21", "%ymm22", "%ymm23", | |
3042 | "%ymm24", "%ymm25", "%ymm26", "%ymm27", | |
3043 | "%ymm28", "%ymm29", "%ymm30", "%ymm31" | |
3044 | }; | |
3045 | ||
3046 | static const char **names_zmm; | |
3047 | static const char *intel_names_zmm[] = { | |
3048 | "zmm0", "zmm1", "zmm2", "zmm3", | |
3049 | "zmm4", "zmm5", "zmm6", "zmm7", | |
3050 | "zmm8", "zmm9", "zmm10", "zmm11", | |
3051 | "zmm12", "zmm13", "zmm14", "zmm15", | |
3052 | "zmm16", "zmm17", "zmm18", "zmm19", | |
3053 | "zmm20", "zmm21", "zmm22", "zmm23", | |
3054 | "zmm24", "zmm25", "zmm26", "zmm27", | |
3055 | "zmm28", "zmm29", "zmm30", "zmm31" | |
3056 | }; | |
3057 | static const char *att_names_zmm[] = { | |
3058 | "%zmm0", "%zmm1", "%zmm2", "%zmm3", | |
3059 | "%zmm4", "%zmm5", "%zmm6", "%zmm7", | |
3060 | "%zmm8", "%zmm9", "%zmm10", "%zmm11", | |
3061 | "%zmm12", "%zmm13", "%zmm14", "%zmm15", | |
3062 | "%zmm16", "%zmm17", "%zmm18", "%zmm19", | |
3063 | "%zmm20", "%zmm21", "%zmm22", "%zmm23", | |
3064 | "%zmm24", "%zmm25", "%zmm26", "%zmm27", | |
3065 | "%zmm28", "%zmm29", "%zmm30", "%zmm31" | |
3066 | }; | |
3067 | ||
3068 | static const char **names_mask; | |
3069 | static const char *intel_names_mask[] = { | |
3070 | "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7" | |
3071 | }; | |
3072 | static const char *att_names_mask[] = { | |
3073 | "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7" | |
3074 | }; | |
3075 | ||
3076 | static const char *names_rounding[] = | |
3077 | { | |
3078 | "{rn-sae}", | |
3079 | "{rd-sae}", | |
3080 | "{ru-sae}", | |
3081 | "{rz-sae}" | |
b9733481 L |
3082 | }; |
3083 | ||
1ceb70f8 L |
3084 | static const struct dis386 reg_table[][8] = { |
3085 | /* REG_80 */ | |
252b5132 | 3086 | { |
bf890a93 IT |
3087 | { "addA", { Ebh1, Ib }, 0 }, |
3088 | { "orA", { Ebh1, Ib }, 0 }, | |
3089 | { "adcA", { Ebh1, Ib }, 0 }, | |
3090 | { "sbbA", { Ebh1, Ib }, 0 }, | |
3091 | { "andA", { Ebh1, Ib }, 0 }, | |
3092 | { "subA", { Ebh1, Ib }, 0 }, | |
3093 | { "xorA", { Ebh1, Ib }, 0 }, | |
3094 | { "cmpA", { Eb, Ib }, 0 }, | |
252b5132 | 3095 | }, |
1ceb70f8 | 3096 | /* REG_81 */ |
252b5132 | 3097 | { |
bf890a93 IT |
3098 | { "addQ", { Evh1, Iv }, 0 }, |
3099 | { "orQ", { Evh1, Iv }, 0 }, | |
3100 | { "adcQ", { Evh1, Iv }, 0 }, | |
3101 | { "sbbQ", { Evh1, Iv }, 0 }, | |
3102 | { "andQ", { Evh1, Iv }, 0 }, | |
3103 | { "subQ", { Evh1, Iv }, 0 }, | |
3104 | { "xorQ", { Evh1, Iv }, 0 }, | |
3105 | { "cmpQ", { Ev, Iv }, 0 }, | |
252b5132 | 3106 | }, |
7148c369 | 3107 | /* REG_83 */ |
252b5132 | 3108 | { |
bf890a93 IT |
3109 | { "addQ", { Evh1, sIb }, 0 }, |
3110 | { "orQ", { Evh1, sIb }, 0 }, | |
3111 | { "adcQ", { Evh1, sIb }, 0 }, | |
3112 | { "sbbQ", { Evh1, sIb }, 0 }, | |
3113 | { "andQ", { Evh1, sIb }, 0 }, | |
3114 | { "subQ", { Evh1, sIb }, 0 }, | |
3115 | { "xorQ", { Evh1, sIb }, 0 }, | |
3116 | { "cmpQ", { Ev, sIb }, 0 }, | |
252b5132 | 3117 | }, |
1ceb70f8 | 3118 | /* REG_8F */ |
4e7d34a6 | 3119 | { |
bf890a93 | 3120 | { "popU", { stackEv }, 0 }, |
c48244a5 | 3121 | { XOP_8F_TABLE (XOP_09) }, |
592d1631 L |
3122 | { Bad_Opcode }, |
3123 | { Bad_Opcode }, | |
3124 | { Bad_Opcode }, | |
f88c9eb0 | 3125 | { XOP_8F_TABLE (XOP_09) }, |
4e7d34a6 | 3126 | }, |
1ceb70f8 | 3127 | /* REG_C0 */ |
252b5132 | 3128 | { |
bf890a93 IT |
3129 | { "rolA", { Eb, Ib }, 0 }, |
3130 | { "rorA", { Eb, Ib }, 0 }, | |
3131 | { "rclA", { Eb, Ib }, 0 }, | |
3132 | { "rcrA", { Eb, Ib }, 0 }, | |
3133 | { "shlA", { Eb, Ib }, 0 }, | |
3134 | { "shrA", { Eb, Ib }, 0 }, | |
e4bdd679 | 3135 | { "shlA", { Eb, Ib }, 0 }, |
bf890a93 | 3136 | { "sarA", { Eb, Ib }, 0 }, |
252b5132 | 3137 | }, |
1ceb70f8 | 3138 | /* REG_C1 */ |
252b5132 | 3139 | { |
bf890a93 IT |
3140 | { "rolQ", { Ev, Ib }, 0 }, |
3141 | { "rorQ", { Ev, Ib }, 0 }, | |
3142 | { "rclQ", { Ev, Ib }, 0 }, | |
3143 | { "rcrQ", { Ev, Ib }, 0 }, | |
3144 | { "shlQ", { Ev, Ib }, 0 }, | |
3145 | { "shrQ", { Ev, Ib }, 0 }, | |
e4bdd679 | 3146 | { "shlQ", { Ev, Ib }, 0 }, |
bf890a93 | 3147 | { "sarQ", { Ev, Ib }, 0 }, |
252b5132 | 3148 | }, |
1ceb70f8 | 3149 | /* REG_C6 */ |
4e7d34a6 | 3150 | { |
bf890a93 | 3151 | { "movA", { Ebh3, Ib }, 0 }, |
42164a71 L |
3152 | { Bad_Opcode }, |
3153 | { Bad_Opcode }, | |
3154 | { Bad_Opcode }, | |
3155 | { Bad_Opcode }, | |
3156 | { Bad_Opcode }, | |
3157 | { Bad_Opcode }, | |
3158 | { MOD_TABLE (MOD_C6_REG_7) }, | |
4e7d34a6 | 3159 | }, |
1ceb70f8 | 3160 | /* REG_C7 */ |
4e7d34a6 | 3161 | { |
bf890a93 | 3162 | { "movQ", { Evh3, Iv }, 0 }, |
42164a71 L |
3163 | { Bad_Opcode }, |
3164 | { Bad_Opcode }, | |
3165 | { Bad_Opcode }, | |
3166 | { Bad_Opcode }, | |
3167 | { Bad_Opcode }, | |
3168 | { Bad_Opcode }, | |
3169 | { MOD_TABLE (MOD_C7_REG_7) }, | |
4e7d34a6 | 3170 | }, |
1ceb70f8 | 3171 | /* REG_D0 */ |
252b5132 | 3172 | { |
bf890a93 IT |
3173 | { "rolA", { Eb, I1 }, 0 }, |
3174 | { "rorA", { Eb, I1 }, 0 }, | |
3175 | { "rclA", { Eb, I1 }, 0 }, | |
3176 | { "rcrA", { Eb, I1 }, 0 }, | |
3177 | { "shlA", { Eb, I1 }, 0 }, | |
3178 | { "shrA", { Eb, I1 }, 0 }, | |
e4bdd679 | 3179 | { "shlA", { Eb, I1 }, 0 }, |
bf890a93 | 3180 | { "sarA", { Eb, I1 }, 0 }, |
252b5132 | 3181 | }, |
1ceb70f8 | 3182 | /* REG_D1 */ |
252b5132 | 3183 | { |
bf890a93 IT |
3184 | { "rolQ", { Ev, I1 }, 0 }, |
3185 | { "rorQ", { Ev, I1 }, 0 }, | |
3186 | { "rclQ", { Ev, I1 }, 0 }, | |
3187 | { "rcrQ", { Ev, I1 }, 0 }, | |
3188 | { "shlQ", { Ev, I1 }, 0 }, | |
3189 | { "shrQ", { Ev, I1 }, 0 }, | |
e4bdd679 | 3190 | { "shlQ", { Ev, I1 }, 0 }, |
bf890a93 | 3191 | { "sarQ", { Ev, I1 }, 0 }, |
252b5132 | 3192 | }, |
1ceb70f8 | 3193 | /* REG_D2 */ |
252b5132 | 3194 | { |
bf890a93 IT |
3195 | { "rolA", { Eb, CL }, 0 }, |
3196 | { "rorA", { Eb, CL }, 0 }, | |
3197 | { "rclA", { Eb, CL }, 0 }, | |
3198 | { "rcrA", { Eb, CL }, 0 }, | |
3199 | { "shlA", { Eb, CL }, 0 }, | |
3200 | { "shrA", { Eb, CL }, 0 }, | |
e4bdd679 | 3201 | { "shlA", { Eb, CL }, 0 }, |
bf890a93 | 3202 | { "sarA", { Eb, CL }, 0 }, |
252b5132 | 3203 | }, |
1ceb70f8 | 3204 | /* REG_D3 */ |
252b5132 | 3205 | { |
bf890a93 IT |
3206 | { "rolQ", { Ev, CL }, 0 }, |
3207 | { "rorQ", { Ev, CL }, 0 }, | |
3208 | { "rclQ", { Ev, CL }, 0 }, | |
3209 | { "rcrQ", { Ev, CL }, 0 }, | |
3210 | { "shlQ", { Ev, CL }, 0 }, | |
3211 | { "shrQ", { Ev, CL }, 0 }, | |
e4bdd679 | 3212 | { "shlQ", { Ev, CL }, 0 }, |
bf890a93 | 3213 | { "sarQ", { Ev, CL }, 0 }, |
252b5132 | 3214 | }, |
1ceb70f8 | 3215 | /* REG_F6 */ |
252b5132 | 3216 | { |
bf890a93 | 3217 | { "testA", { Eb, Ib }, 0 }, |
7db2c588 | 3218 | { "testA", { Eb, Ib }, 0 }, |
bf890a93 IT |
3219 | { "notA", { Ebh1 }, 0 }, |
3220 | { "negA", { Ebh1 }, 0 }, | |
3221 | { "mulA", { Eb }, 0 }, /* Don't print the implicit %al register, */ | |
3222 | { "imulA", { Eb }, 0 }, /* to distinguish these opcodes from other */ | |
3223 | { "divA", { Eb }, 0 }, /* mul/imul opcodes. Do the same for div */ | |
3224 | { "idivA", { Eb }, 0 }, /* and idiv for consistency. */ | |
252b5132 | 3225 | }, |
1ceb70f8 | 3226 | /* REG_F7 */ |
252b5132 | 3227 | { |
bf890a93 | 3228 | { "testQ", { Ev, Iv }, 0 }, |
7db2c588 | 3229 | { "testQ", { Ev, Iv }, 0 }, |
bf890a93 IT |
3230 | { "notQ", { Evh1 }, 0 }, |
3231 | { "negQ", { Evh1 }, 0 }, | |
3232 | { "mulQ", { Ev }, 0 }, /* Don't print the implicit register. */ | |
3233 | { "imulQ", { Ev }, 0 }, | |
3234 | { "divQ", { Ev }, 0 }, | |
3235 | { "idivQ", { Ev }, 0 }, | |
252b5132 | 3236 | }, |
1ceb70f8 | 3237 | /* REG_FE */ |
252b5132 | 3238 | { |
bf890a93 IT |
3239 | { "incA", { Ebh1 }, 0 }, |
3240 | { "decA", { Ebh1 }, 0 }, | |
252b5132 | 3241 | }, |
1ceb70f8 | 3242 | /* REG_FF */ |
252b5132 | 3243 | { |
bf890a93 IT |
3244 | { "incQ", { Evh1 }, 0 }, |
3245 | { "decQ", { Evh1 }, 0 }, | |
9fef80d6 | 3246 | { "call{&|}", { NOTRACK, indirEv, BND }, 0 }, |
4a357820 | 3247 | { MOD_TABLE (MOD_FF_REG_3) }, |
9fef80d6 | 3248 | { "jmp{&|}", { NOTRACK, indirEv, BND }, 0 }, |
4a357820 | 3249 | { MOD_TABLE (MOD_FF_REG_5) }, |
bf890a93 | 3250 | { "pushU", { stackEv }, 0 }, |
592d1631 | 3251 | { Bad_Opcode }, |
252b5132 | 3252 | }, |
1ceb70f8 | 3253 | /* REG_0F00 */ |
252b5132 | 3254 | { |
bf890a93 IT |
3255 | { "sldtD", { Sv }, 0 }, |
3256 | { "strD", { Sv }, 0 }, | |
3257 | { "lldt", { Ew }, 0 }, | |
3258 | { "ltr", { Ew }, 0 }, | |
3259 | { "verr", { Ew }, 0 }, | |
3260 | { "verw", { Ew }, 0 }, | |
592d1631 L |
3261 | { Bad_Opcode }, |
3262 | { Bad_Opcode }, | |
252b5132 | 3263 | }, |
1ceb70f8 | 3264 | /* REG_0F01 */ |
252b5132 | 3265 | { |
1ceb70f8 L |
3266 | { MOD_TABLE (MOD_0F01_REG_0) }, |
3267 | { MOD_TABLE (MOD_0F01_REG_1) }, | |
3268 | { MOD_TABLE (MOD_0F01_REG_2) }, | |
3269 | { MOD_TABLE (MOD_0F01_REG_3) }, | |
bf890a93 | 3270 | { "smswD", { Sv }, 0 }, |
8eab4136 | 3271 | { MOD_TABLE (MOD_0F01_REG_5) }, |
bf890a93 | 3272 | { "lmsw", { Ew }, 0 }, |
1ceb70f8 | 3273 | { MOD_TABLE (MOD_0F01_REG_7) }, |
252b5132 | 3274 | }, |
b5b1fc4f | 3275 | /* REG_0F0D */ |
252b5132 | 3276 | { |
bf890a93 IT |
3277 | { "prefetch", { Mb }, 0 }, |
3278 | { "prefetchw", { Mb }, 0 }, | |
3279 | { "prefetchwt1", { Mb }, 0 }, | |
3280 | { "prefetch", { Mb }, 0 }, | |
3281 | { "prefetch", { Mb }, 0 }, | |
3282 | { "prefetch", { Mb }, 0 }, | |
3283 | { "prefetch", { Mb }, 0 }, | |
3284 | { "prefetch", { Mb }, 0 }, | |
252b5132 | 3285 | }, |
1ceb70f8 | 3286 | /* REG_0F18 */ |
252b5132 | 3287 | { |
1ceb70f8 L |
3288 | { MOD_TABLE (MOD_0F18_REG_0) }, |
3289 | { MOD_TABLE (MOD_0F18_REG_1) }, | |
3290 | { MOD_TABLE (MOD_0F18_REG_2) }, | |
3291 | { MOD_TABLE (MOD_0F18_REG_3) }, | |
d7189fa5 RM |
3292 | { MOD_TABLE (MOD_0F18_REG_4) }, |
3293 | { MOD_TABLE (MOD_0F18_REG_5) }, | |
3294 | { MOD_TABLE (MOD_0F18_REG_6) }, | |
3295 | { MOD_TABLE (MOD_0F18_REG_7) }, | |
252b5132 | 3296 | }, |
f8687e93 | 3297 | /* REG_0F1C_P_0_MOD_0 */ |
c48935d7 IT |
3298 | { |
3299 | { "cldemote", { Mb }, 0 }, | |
3300 | { "nopQ", { Ev }, 0 }, | |
3301 | { "nopQ", { Ev }, 0 }, | |
3302 | { "nopQ", { Ev }, 0 }, | |
3303 | { "nopQ", { Ev }, 0 }, | |
3304 | { "nopQ", { Ev }, 0 }, | |
3305 | { "nopQ", { Ev }, 0 }, | |
3306 | { "nopQ", { Ev }, 0 }, | |
3307 | }, | |
f8687e93 | 3308 | /* REG_0F1E_P_1_MOD_3 */ |
603555e5 L |
3309 | { |
3310 | { "nopQ", { Ev }, 0 }, | |
3311 | { "rdsspK", { Rdq }, PREFIX_OPCODE }, | |
3312 | { "nopQ", { Ev }, 0 }, | |
3313 | { "nopQ", { Ev }, 0 }, | |
3314 | { "nopQ", { Ev }, 0 }, | |
3315 | { "nopQ", { Ev }, 0 }, | |
3316 | { "nopQ", { Ev }, 0 }, | |
f8687e93 | 3317 | { RM_TABLE (RM_0F1E_P_1_MOD_3_REG_7) }, |
603555e5 | 3318 | }, |
1ceb70f8 | 3319 | /* REG_0F71 */ |
a6bd098c | 3320 | { |
592d1631 L |
3321 | { Bad_Opcode }, |
3322 | { Bad_Opcode }, | |
1ceb70f8 | 3323 | { MOD_TABLE (MOD_0F71_REG_2) }, |
592d1631 | 3324 | { Bad_Opcode }, |
1ceb70f8 | 3325 | { MOD_TABLE (MOD_0F71_REG_4) }, |
592d1631 | 3326 | { Bad_Opcode }, |
1ceb70f8 | 3327 | { MOD_TABLE (MOD_0F71_REG_6) }, |
a6bd098c | 3328 | }, |
1ceb70f8 | 3329 | /* REG_0F72 */ |
a6bd098c | 3330 | { |
592d1631 L |
3331 | { Bad_Opcode }, |
3332 | { Bad_Opcode }, | |
1ceb70f8 | 3333 | { MOD_TABLE (MOD_0F72_REG_2) }, |
592d1631 | 3334 | { Bad_Opcode }, |
1ceb70f8 | 3335 | { MOD_TABLE (MOD_0F72_REG_4) }, |
592d1631 | 3336 | { Bad_Opcode }, |
1ceb70f8 | 3337 | { MOD_TABLE (MOD_0F72_REG_6) }, |
a6bd098c | 3338 | }, |
1ceb70f8 | 3339 | /* REG_0F73 */ |
252b5132 | 3340 | { |
592d1631 L |
3341 | { Bad_Opcode }, |
3342 | { Bad_Opcode }, | |
1ceb70f8 L |
3343 | { MOD_TABLE (MOD_0F73_REG_2) }, |
3344 | { MOD_TABLE (MOD_0F73_REG_3) }, | |
592d1631 L |
3345 | { Bad_Opcode }, |
3346 | { Bad_Opcode }, | |
1ceb70f8 L |
3347 | { MOD_TABLE (MOD_0F73_REG_6) }, |
3348 | { MOD_TABLE (MOD_0F73_REG_7) }, | |
252b5132 | 3349 | }, |
1ceb70f8 | 3350 | /* REG_0FA6 */ |
252b5132 | 3351 | { |
bf890a93 IT |
3352 | { "montmul", { { OP_0f07, 0 } }, 0 }, |
3353 | { "xsha1", { { OP_0f07, 0 } }, 0 }, | |
3354 | { "xsha256", { { OP_0f07, 0 } }, 0 }, | |
4e7d34a6 | 3355 | }, |
1ceb70f8 | 3356 | /* REG_0FA7 */ |
4e7d34a6 | 3357 | { |
bf890a93 IT |
3358 | { "xstore-rng", { { OP_0f07, 0 } }, 0 }, |
3359 | { "xcrypt-ecb", { { OP_0f07, 0 } }, 0 }, | |
3360 | { "xcrypt-cbc", { { OP_0f07, 0 } }, 0 }, | |
3361 | { "xcrypt-ctr", { { OP_0f07, 0 } }, 0 }, | |
3362 | { "xcrypt-cfb", { { OP_0f07, 0 } }, 0 }, | |
3363 | { "xcrypt-ofb", { { OP_0f07, 0 } }, 0 }, | |
4e7d34a6 | 3364 | }, |
1ceb70f8 | 3365 | /* REG_0FAE */ |
4e7d34a6 | 3366 | { |
1ceb70f8 L |
3367 | { MOD_TABLE (MOD_0FAE_REG_0) }, |
3368 | { MOD_TABLE (MOD_0FAE_REG_1) }, | |
3369 | { MOD_TABLE (MOD_0FAE_REG_2) }, | |
3370 | { MOD_TABLE (MOD_0FAE_REG_3) }, | |
475a2301 | 3371 | { MOD_TABLE (MOD_0FAE_REG_4) }, |
1ceb70f8 L |
3372 | { MOD_TABLE (MOD_0FAE_REG_5) }, |
3373 | { MOD_TABLE (MOD_0FAE_REG_6) }, | |
3374 | { MOD_TABLE (MOD_0FAE_REG_7) }, | |
252b5132 | 3375 | }, |
1ceb70f8 | 3376 | /* REG_0FBA */ |
252b5132 | 3377 | { |
592d1631 L |
3378 | { Bad_Opcode }, |
3379 | { Bad_Opcode }, | |
3380 | { Bad_Opcode }, | |
3381 | { Bad_Opcode }, | |
bf890a93 IT |
3382 | { "btQ", { Ev, Ib }, 0 }, |
3383 | { "btsQ", { Evh1, Ib }, 0 }, | |
3384 | { "btrQ", { Evh1, Ib }, 0 }, | |
3385 | { "btcQ", { Evh1, Ib }, 0 }, | |
c608c12e | 3386 | }, |
1ceb70f8 | 3387 | /* REG_0FC7 */ |
c608c12e | 3388 | { |
592d1631 | 3389 | { Bad_Opcode }, |
bf890a93 | 3390 | { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 }, |
592d1631 | 3391 | { Bad_Opcode }, |
963f3586 IT |
3392 | { MOD_TABLE (MOD_0FC7_REG_3) }, |
3393 | { MOD_TABLE (MOD_0FC7_REG_4) }, | |
3394 | { MOD_TABLE (MOD_0FC7_REG_5) }, | |
1ceb70f8 L |
3395 | { MOD_TABLE (MOD_0FC7_REG_6) }, |
3396 | { MOD_TABLE (MOD_0FC7_REG_7) }, | |
252b5132 | 3397 | }, |
592a252b | 3398 | /* REG_VEX_0F71 */ |
c0f3af97 | 3399 | { |
592d1631 L |
3400 | { Bad_Opcode }, |
3401 | { Bad_Opcode }, | |
592a252b | 3402 | { MOD_TABLE (MOD_VEX_0F71_REG_2) }, |
592d1631 | 3403 | { Bad_Opcode }, |
592a252b | 3404 | { MOD_TABLE (MOD_VEX_0F71_REG_4) }, |
592d1631 | 3405 | { Bad_Opcode }, |
592a252b | 3406 | { MOD_TABLE (MOD_VEX_0F71_REG_6) }, |
c0f3af97 | 3407 | }, |
592a252b | 3408 | /* REG_VEX_0F72 */ |
c0f3af97 | 3409 | { |
592d1631 L |
3410 | { Bad_Opcode }, |
3411 | { Bad_Opcode }, | |
592a252b | 3412 | { MOD_TABLE (MOD_VEX_0F72_REG_2) }, |
592d1631 | 3413 | { Bad_Opcode }, |
592a252b | 3414 | { MOD_TABLE (MOD_VEX_0F72_REG_4) }, |
592d1631 | 3415 | { Bad_Opcode }, |
592a252b | 3416 | { MOD_TABLE (MOD_VEX_0F72_REG_6) }, |
c0f3af97 | 3417 | }, |
592a252b | 3418 | /* REG_VEX_0F73 */ |
c0f3af97 | 3419 | { |
592d1631 L |
3420 | { Bad_Opcode }, |
3421 | { Bad_Opcode }, | |
592a252b L |
3422 | { MOD_TABLE (MOD_VEX_0F73_REG_2) }, |
3423 | { MOD_TABLE (MOD_VEX_0F73_REG_3) }, | |
592d1631 L |
3424 | { Bad_Opcode }, |
3425 | { Bad_Opcode }, | |
592a252b L |
3426 | { MOD_TABLE (MOD_VEX_0F73_REG_6) }, |
3427 | { MOD_TABLE (MOD_VEX_0F73_REG_7) }, | |
c0f3af97 | 3428 | }, |
592a252b | 3429 | /* REG_VEX_0FAE */ |
c0f3af97 | 3430 | { |
592d1631 L |
3431 | { Bad_Opcode }, |
3432 | { Bad_Opcode }, | |
592a252b L |
3433 | { MOD_TABLE (MOD_VEX_0FAE_REG_2) }, |
3434 | { MOD_TABLE (MOD_VEX_0FAE_REG_3) }, | |
c0f3af97 | 3435 | }, |
f12dc422 L |
3436 | /* REG_VEX_0F38F3 */ |
3437 | { | |
3438 | { Bad_Opcode }, | |
3439 | { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) }, | |
3440 | { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) }, | |
3441 | { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) }, | |
3442 | }, | |
f88c9eb0 SP |
3443 | /* REG_XOP_LWPCB */ |
3444 | { | |
bf890a93 IT |
3445 | { "llwpcb", { { OP_LWPCB_E, 0 } }, 0 }, |
3446 | { "slwpcb", { { OP_LWPCB_E, 0 } }, 0 }, | |
f88c9eb0 SP |
3447 | }, |
3448 | /* REG_XOP_LWP */ | |
3449 | { | |
c1dc7af5 JB |
3450 | { "lwpins", { { OP_LWP_E, 0 }, Ed, Id }, 0 }, |
3451 | { "lwpval", { { OP_LWP_E, 0 }, Ed, Id }, 0 }, | |
f88c9eb0 | 3452 | }, |
2a2a0f38 QN |
3453 | /* REG_XOP_TBM_01 */ |
3454 | { | |
3455 | { Bad_Opcode }, | |
c1dc7af5 JB |
3456 | { "blcfill", { { OP_LWP_E, 0 }, Edq }, 0 }, |
3457 | { "blsfill", { { OP_LWP_E, 0 }, Edq }, 0 }, | |
3458 | { "blcs", { { OP_LWP_E, 0 }, Edq }, 0 }, | |
3459 | { "tzmsk", { { OP_LWP_E, 0 }, Edq }, 0 }, | |
3460 | { "blcic", { { OP_LWP_E, 0 }, Edq }, 0 }, | |
3461 | { "blsic", { { OP_LWP_E, 0 }, Edq }, 0 }, | |
3462 | { "t1mskc", { { OP_LWP_E, 0 }, Edq }, 0 }, | |
2a2a0f38 QN |
3463 | }, |
3464 | /* REG_XOP_TBM_02 */ | |
3465 | { | |
3466 | { Bad_Opcode }, | |
c1dc7af5 | 3467 | { "blcmsk", { { OP_LWP_E, 0 }, Edq }, 0 }, |
2a2a0f38 QN |
3468 | { Bad_Opcode }, |
3469 | { Bad_Opcode }, | |
3470 | { Bad_Opcode }, | |
3471 | { Bad_Opcode }, | |
c1dc7af5 | 3472 | { "blci", { { OP_LWP_E, 0 }, Edq }, 0 }, |
2a2a0f38 | 3473 | }, |
ad692897 L |
3474 | |
3475 | #include "i386-dis-evex-reg.h" | |
4e7d34a6 L |
3476 | }; |
3477 | ||
1ceb70f8 L |
3478 | static const struct dis386 prefix_table[][4] = { |
3479 | /* PREFIX_90 */ | |
252b5132 | 3480 | { |
bf890a93 IT |
3481 | { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 }, |
3482 | { "pause", { XX }, 0 }, | |
3483 | { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 }, | |
507bd325 | 3484 | { NULL, { { NULL, 0 } }, PREFIX_IGNORED } |
0f10071e | 3485 | }, |
4e7d34a6 | 3486 | |
f9630fa6 | 3487 | /* PREFIX_0F01_REG_3_RM_1 */ |
a847e322 JB |
3488 | { |
3489 | { "vmmcall", { Skip_MODRM }, 0 }, | |
3490 | { "vmgexit", { Skip_MODRM }, 0 }, | |
d27c357a JB |
3491 | { Bad_Opcode }, |
3492 | { "vmgexit", { Skip_MODRM }, 0 }, | |
a847e322 JB |
3493 | }, |
3494 | ||
f8687e93 | 3495 | /* PREFIX_0F01_REG_5_MOD_0 */ |
603555e5 L |
3496 | { |
3497 | { Bad_Opcode }, | |
3498 | { "rstorssp", { Mq }, PREFIX_OPCODE }, | |
3499 | }, | |
3500 | ||
f8687e93 | 3501 | /* PREFIX_0F01_REG_5_MOD_3_RM_0 */ |
603555e5 | 3502 | { |
4b27d27c | 3503 | { "serialize", { Skip_MODRM }, PREFIX_OPCODE }, |
2234eee6 | 3504 | { "setssbsy", { Skip_MODRM }, PREFIX_OPCODE }, |
bb651e8b | 3505 | { Bad_Opcode }, |
efe30057 | 3506 | { "xsusldtrk", { Skip_MODRM }, PREFIX_OPCODE }, |
bb651e8b CL |
3507 | }, |
3508 | ||
3509 | /* PREFIX_0F01_REG_5_MOD_3_RM_1 */ | |
3510 | { | |
3511 | { Bad_Opcode }, | |
3512 | { Bad_Opcode }, | |
3513 | { Bad_Opcode }, | |
3514 | { "xresldtrk", { Skip_MODRM }, PREFIX_OPCODE }, | |
603555e5 L |
3515 | }, |
3516 | ||
f8687e93 | 3517 | /* PREFIX_0F01_REG_5_MOD_3_RM_2 */ |
603555e5 L |
3518 | { |
3519 | { Bad_Opcode }, | |
c2f76402 | 3520 | { "saveprevssp", { Skip_MODRM }, PREFIX_OPCODE }, |
603555e5 L |
3521 | }, |
3522 | ||
267b8516 JB |
3523 | /* PREFIX_0F01_REG_7_MOD_3_RM_2 */ |
3524 | { | |
3525 | { "monitorx", { { OP_Monitor, 0 } }, 0 }, | |
142861df | 3526 | { "mcommit", { Skip_MODRM }, 0 }, |
267b8516 JB |
3527 | }, |
3528 | ||
3529 | /* PREFIX_0F01_REG_7_MOD_3_RM_3 */ | |
3530 | { | |
7abb8d81 | 3531 | { "mwaitx", { { OP_Mwait, eBX_reg } }, 0 }, |
267b8516 JB |
3532 | }, |
3533 | ||
3233d7d0 IT |
3534 | /* PREFIX_0F09 */ |
3535 | { | |
3536 | { "wbinvd", { XX }, 0 }, | |
3537 | { "wbnoinvd", { XX }, 0 }, | |
3538 | }, | |
3539 | ||
1ceb70f8 | 3540 | /* PREFIX_0F10 */ |
cc0ec051 | 3541 | { |
507bd325 L |
3542 | { "movups", { XM, EXx }, PREFIX_OPCODE }, |
3543 | { "movss", { XM, EXd }, PREFIX_OPCODE }, | |
3544 | { "movupd", { XM, EXx }, PREFIX_OPCODE }, | |
3545 | { "movsd", { XM, EXq }, PREFIX_OPCODE }, | |
30d1c836 | 3546 | }, |
4e7d34a6 | 3547 | |
1ceb70f8 | 3548 | /* PREFIX_0F11 */ |
30d1c836 | 3549 | { |
507bd325 L |
3550 | { "movups", { EXxS, XM }, PREFIX_OPCODE }, |
3551 | { "movss", { EXdS, XM }, PREFIX_OPCODE }, | |
3552 | { "movupd", { EXxS, XM }, PREFIX_OPCODE }, | |
3553 | { "movsd", { EXqS, XM }, PREFIX_OPCODE }, | |
4e7d34a6 | 3554 | }, |
252b5132 | 3555 | |
1ceb70f8 | 3556 | /* PREFIX_0F12 */ |
c608c12e | 3557 | { |
1ceb70f8 | 3558 | { MOD_TABLE (MOD_0F12_PREFIX_0) }, |
507bd325 | 3559 | { "movsldup", { XM, EXx }, PREFIX_OPCODE }, |
18897deb | 3560 | { MOD_TABLE (MOD_0F12_PREFIX_2) }, |
507bd325 | 3561 | { "movddup", { XM, EXq }, PREFIX_OPCODE }, |
c608c12e | 3562 | }, |
4e7d34a6 | 3563 | |
1ceb70f8 | 3564 | /* PREFIX_0F16 */ |
c608c12e | 3565 | { |
1ceb70f8 | 3566 | { MOD_TABLE (MOD_0F16_PREFIX_0) }, |
507bd325 | 3567 | { "movshdup", { XM, EXx }, PREFIX_OPCODE }, |
18897deb | 3568 | { MOD_TABLE (MOD_0F16_PREFIX_2) }, |
c608c12e | 3569 | }, |
4e7d34a6 | 3570 | |
7e8b059b L |
3571 | /* PREFIX_0F1A */ |
3572 | { | |
3573 | { MOD_TABLE (MOD_0F1A_PREFIX_0) }, | |
bf890a93 IT |
3574 | { "bndcl", { Gbnd, Ev_bnd }, 0 }, |
3575 | { "bndmov", { Gbnd, Ebnd }, 0 }, | |
3576 | { "bndcu", { Gbnd, Ev_bnd }, 0 }, | |
7e8b059b L |
3577 | }, |
3578 | ||
3579 | /* PREFIX_0F1B */ | |
3580 | { | |
3581 | { MOD_TABLE (MOD_0F1B_PREFIX_0) }, | |
3582 | { MOD_TABLE (MOD_0F1B_PREFIX_1) }, | |
9f79e886 | 3583 | { "bndmov", { EbndS, Gbnd }, 0 }, |
bf890a93 | 3584 | { "bndcn", { Gbnd, Ev_bnd }, 0 }, |
7e8b059b L |
3585 | }, |
3586 | ||
c48935d7 IT |
3587 | /* PREFIX_0F1C */ |
3588 | { | |
3589 | { MOD_TABLE (MOD_0F1C_PREFIX_0) }, | |
3590 | { "nopQ", { Ev }, PREFIX_OPCODE }, | |
3591 | { "nopQ", { Ev }, PREFIX_OPCODE }, | |
3592 | { "nopQ", { Ev }, PREFIX_OPCODE }, | |
3593 | }, | |
3594 | ||
603555e5 L |
3595 | /* PREFIX_0F1E */ |
3596 | { | |
3597 | { "nopQ", { Ev }, PREFIX_OPCODE }, | |
3598 | { MOD_TABLE (MOD_0F1E_PREFIX_1) }, | |
3599 | { "nopQ", { Ev }, PREFIX_OPCODE }, | |
3600 | { "nopQ", { Ev }, PREFIX_OPCODE }, | |
3601 | }, | |
3602 | ||
1ceb70f8 | 3603 | /* PREFIX_0F2A */ |
c608c12e | 3604 | { |
507bd325 | 3605 | { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE }, |
e1a1babd | 3606 | { "cvtsi2ss%LQ", { XM, Edq }, PREFIX_OPCODE }, |
507bd325 | 3607 | { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE }, |
e1a1babd | 3608 | { "cvtsi2sd%LQ", { XM, Edq }, 0 }, |
c608c12e | 3609 | }, |
4e7d34a6 | 3610 | |
1ceb70f8 | 3611 | /* PREFIX_0F2B */ |
c608c12e | 3612 | { |
75c135a8 L |
3613 | { MOD_TABLE (MOD_0F2B_PREFIX_0) }, |
3614 | { MOD_TABLE (MOD_0F2B_PREFIX_1) }, | |
3615 | { MOD_TABLE (MOD_0F2B_PREFIX_2) }, | |
3616 | { MOD_TABLE (MOD_0F2B_PREFIX_3) }, | |
c608c12e | 3617 | }, |
4e7d34a6 | 3618 | |
1ceb70f8 | 3619 | /* PREFIX_0F2C */ |
c608c12e | 3620 | { |
507bd325 | 3621 | { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE }, |
e1a1babd | 3622 | { "cvttss2si", { Gdq, EXd }, PREFIX_OPCODE }, |
507bd325 | 3623 | { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE }, |
e1a1babd | 3624 | { "cvttsd2si", { Gdq, EXq }, PREFIX_OPCODE }, |
c608c12e | 3625 | }, |
4e7d34a6 | 3626 | |
1ceb70f8 | 3627 | /* PREFIX_0F2D */ |
c608c12e | 3628 | { |
507bd325 | 3629 | { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE }, |
e1a1babd | 3630 | { "cvtss2si", { Gdq, EXd }, PREFIX_OPCODE }, |
507bd325 | 3631 | { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE }, |
e1a1babd | 3632 | { "cvtsd2si", { Gdq, EXq }, PREFIX_OPCODE }, |
c608c12e | 3633 | }, |
4e7d34a6 | 3634 | |
1ceb70f8 | 3635 | /* PREFIX_0F2E */ |
c608c12e | 3636 | { |
bf890a93 | 3637 | { "ucomiss",{ XM, EXd }, 0 }, |
592d1631 | 3638 | { Bad_Opcode }, |
bf890a93 | 3639 | { "ucomisd",{ XM, EXq }, 0 }, |
c608c12e | 3640 | }, |
4e7d34a6 | 3641 | |
1ceb70f8 | 3642 | /* PREFIX_0F2F */ |
c608c12e | 3643 | { |
bf890a93 | 3644 | { "comiss", { XM, EXd }, 0 }, |
592d1631 | 3645 | { Bad_Opcode }, |
bf890a93 | 3646 | { "comisd", { XM, EXq }, 0 }, |
c608c12e | 3647 | }, |
4e7d34a6 | 3648 | |
1ceb70f8 | 3649 | /* PREFIX_0F51 */ |
c608c12e | 3650 | { |
507bd325 L |
3651 | { "sqrtps", { XM, EXx }, PREFIX_OPCODE }, |
3652 | { "sqrtss", { XM, EXd }, PREFIX_OPCODE }, | |
3653 | { "sqrtpd", { XM, EXx }, PREFIX_OPCODE }, | |
3654 | { "sqrtsd", { XM, EXq }, PREFIX_OPCODE }, | |
c608c12e | 3655 | }, |
4e7d34a6 | 3656 | |
1ceb70f8 | 3657 | /* PREFIX_0F52 */ |
c608c12e | 3658 | { |
507bd325 L |
3659 | { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE }, |
3660 | { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE }, | |
c608c12e | 3661 | }, |
4e7d34a6 | 3662 | |
1ceb70f8 | 3663 | /* PREFIX_0F53 */ |
c608c12e | 3664 | { |
507bd325 L |
3665 | { "rcpps", { XM, EXx }, PREFIX_OPCODE }, |
3666 | { "rcpss", { XM, EXd }, PREFIX_OPCODE }, | |
c608c12e | 3667 | }, |
4e7d34a6 | 3668 | |
1ceb70f8 | 3669 | /* PREFIX_0F58 */ |
c608c12e | 3670 | { |
507bd325 L |
3671 | { "addps", { XM, EXx }, PREFIX_OPCODE }, |
3672 | { "addss", { XM, EXd }, PREFIX_OPCODE }, | |
3673 | { "addpd", { XM, EXx }, PREFIX_OPCODE }, | |
3674 | { "addsd", { XM, EXq }, PREFIX_OPCODE }, | |
c608c12e | 3675 | }, |
4e7d34a6 | 3676 | |
1ceb70f8 | 3677 | /* PREFIX_0F59 */ |
c608c12e | 3678 | { |
507bd325 L |
3679 | { "mulps", { XM, EXx }, PREFIX_OPCODE }, |
3680 | { "mulss", { XM, EXd }, PREFIX_OPCODE }, | |
3681 | { "mulpd", { XM, EXx }, PREFIX_OPCODE }, | |
3682 | { "mulsd", { XM, EXq }, PREFIX_OPCODE }, | |
041bd2e0 | 3683 | }, |
4e7d34a6 | 3684 | |
1ceb70f8 | 3685 | /* PREFIX_0F5A */ |
041bd2e0 | 3686 | { |
507bd325 L |
3687 | { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE }, |
3688 | { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE }, | |
3689 | { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE }, | |
3690 | { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE }, | |
041bd2e0 | 3691 | }, |
4e7d34a6 | 3692 | |
1ceb70f8 | 3693 | /* PREFIX_0F5B */ |
041bd2e0 | 3694 | { |
507bd325 L |
3695 | { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE }, |
3696 | { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE }, | |
3697 | { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE }, | |
041bd2e0 | 3698 | }, |
4e7d34a6 | 3699 | |
1ceb70f8 | 3700 | /* PREFIX_0F5C */ |
041bd2e0 | 3701 | { |
507bd325 L |
3702 | { "subps", { XM, EXx }, PREFIX_OPCODE }, |
3703 | { "subss", { XM, EXd }, PREFIX_OPCODE }, | |
3704 | { "subpd", { XM, EXx }, PREFIX_OPCODE }, | |
3705 | { "subsd", { XM, EXq }, PREFIX_OPCODE }, | |
041bd2e0 | 3706 | }, |
4e7d34a6 | 3707 | |
1ceb70f8 | 3708 | /* PREFIX_0F5D */ |
041bd2e0 | 3709 | { |
507bd325 L |
3710 | { "minps", { XM, EXx }, PREFIX_OPCODE }, |
3711 | { "minss", { XM, EXd }, PREFIX_OPCODE }, | |
3712 | { "minpd", { XM, EXx }, PREFIX_OPCODE }, | |
3713 | { "minsd", { XM, EXq }, PREFIX_OPCODE }, | |
041bd2e0 | 3714 | }, |
4e7d34a6 | 3715 | |
1ceb70f8 | 3716 | /* PREFIX_0F5E */ |
041bd2e0 | 3717 | { |
507bd325 L |
3718 | { "divps", { XM, EXx }, PREFIX_OPCODE }, |
3719 | { "divss", { XM, EXd }, PREFIX_OPCODE }, | |
3720 | { "divpd", { XM, EXx }, PREFIX_OPCODE }, | |
3721 | { "divsd", { XM, EXq }, PREFIX_OPCODE }, | |
041bd2e0 | 3722 | }, |
4e7d34a6 | 3723 | |
1ceb70f8 | 3724 | /* PREFIX_0F5F */ |
041bd2e0 | 3725 | { |
507bd325 L |
3726 | { "maxps", { XM, EXx }, PREFIX_OPCODE }, |
3727 | { "maxss", { XM, EXd }, PREFIX_OPCODE }, | |
3728 | { "maxpd", { XM, EXx }, PREFIX_OPCODE }, | |
3729 | { "maxsd", { XM, EXq }, PREFIX_OPCODE }, | |
041bd2e0 | 3730 | }, |
4e7d34a6 | 3731 | |
1ceb70f8 | 3732 | /* PREFIX_0F60 */ |
041bd2e0 | 3733 | { |
507bd325 | 3734 | { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE }, |
592d1631 | 3735 | { Bad_Opcode }, |
507bd325 | 3736 | { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE }, |
041bd2e0 | 3737 | }, |
4e7d34a6 | 3738 | |
1ceb70f8 | 3739 | /* PREFIX_0F61 */ |
041bd2e0 | 3740 | { |
507bd325 | 3741 | { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE }, |
592d1631 | 3742 | { Bad_Opcode }, |
507bd325 | 3743 | { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE }, |
041bd2e0 | 3744 | }, |
4e7d34a6 | 3745 | |
1ceb70f8 | 3746 | /* PREFIX_0F62 */ |
041bd2e0 | 3747 | { |
507bd325 | 3748 | { "punpckldq",{ MX, EMd }, PREFIX_OPCODE }, |
592d1631 | 3749 | { Bad_Opcode }, |
507bd325 | 3750 | { "punpckldq",{ MX, EMx }, PREFIX_OPCODE }, |
041bd2e0 | 3751 | }, |
4e7d34a6 | 3752 | |
1ceb70f8 | 3753 | /* PREFIX_0F6C */ |
041bd2e0 | 3754 | { |
592d1631 L |
3755 | { Bad_Opcode }, |
3756 | { Bad_Opcode }, | |
507bd325 | 3757 | { "punpcklqdq", { XM, EXx }, PREFIX_OPCODE }, |
0f17484f | 3758 | }, |
4e7d34a6 | 3759 | |
1ceb70f8 | 3760 | /* PREFIX_0F6D */ |
0f17484f | 3761 | { |
592d1631 L |
3762 | { Bad_Opcode }, |
3763 | { Bad_Opcode }, | |
507bd325 | 3764 | { "punpckhqdq", { XM, EXx }, PREFIX_OPCODE }, |
041bd2e0 | 3765 | }, |
4e7d34a6 | 3766 | |
1ceb70f8 | 3767 | /* PREFIX_0F6F */ |
ca164297 | 3768 | { |
507bd325 L |
3769 | { "movq", { MX, EM }, PREFIX_OPCODE }, |
3770 | { "movdqu", { XM, EXx }, PREFIX_OPCODE }, | |
3771 | { "movdqa", { XM, EXx }, PREFIX_OPCODE }, | |
ca164297 | 3772 | }, |
4e7d34a6 | 3773 | |
1ceb70f8 | 3774 | /* PREFIX_0F70 */ |
4e7d34a6 | 3775 | { |
507bd325 L |
3776 | { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE }, |
3777 | { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE }, | |
3778 | { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE }, | |
3779 | { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE }, | |
4e7d34a6 L |
3780 | }, |
3781 | ||
92fddf8e L |
3782 | /* PREFIX_0F73_REG_3 */ |
3783 | { | |
592d1631 L |
3784 | { Bad_Opcode }, |
3785 | { Bad_Opcode }, | |
bf890a93 | 3786 | { "psrldq", { XS, Ib }, 0 }, |
92fddf8e L |
3787 | }, |
3788 | ||
3789 | /* PREFIX_0F73_REG_7 */ | |
3790 | { | |
592d1631 L |
3791 | { Bad_Opcode }, |
3792 | { Bad_Opcode }, | |
bf890a93 | 3793 | { "pslldq", { XS, Ib }, 0 }, |
92fddf8e L |
3794 | }, |
3795 | ||
1ceb70f8 | 3796 | /* PREFIX_0F78 */ |
4e7d34a6 | 3797 | { |
bf890a93 | 3798 | {"vmread", { Em, Gm }, 0 }, |
592d1631 | 3799 | { Bad_Opcode }, |
bf890a93 IT |
3800 | {"extrq", { XS, Ib, Ib }, 0 }, |
3801 | {"insertq", { XM, XS, Ib, Ib }, 0 }, | |
4e7d34a6 L |
3802 | }, |
3803 | ||
1ceb70f8 | 3804 | /* PREFIX_0F79 */ |
4e7d34a6 | 3805 | { |
bf890a93 | 3806 | {"vmwrite", { Gm, Em }, 0 }, |
592d1631 | 3807 | { Bad_Opcode }, |
bf890a93 IT |
3808 | {"extrq", { XM, XS }, 0 }, |
3809 | {"insertq", { XM, XS }, 0 }, | |
4e7d34a6 L |
3810 | }, |
3811 | ||
1ceb70f8 | 3812 | /* PREFIX_0F7C */ |
ca164297 | 3813 | { |
592d1631 L |
3814 | { Bad_Opcode }, |
3815 | { Bad_Opcode }, | |
507bd325 L |
3816 | { "haddpd", { XM, EXx }, PREFIX_OPCODE }, |
3817 | { "haddps", { XM, EXx }, PREFIX_OPCODE }, | |
ca164297 | 3818 | }, |
4e7d34a6 | 3819 | |
1ceb70f8 | 3820 | /* PREFIX_0F7D */ |
ca164297 | 3821 | { |
592d1631 L |
3822 | { Bad_Opcode }, |
3823 | { Bad_Opcode }, | |
507bd325 L |
3824 | { "hsubpd", { XM, EXx }, PREFIX_OPCODE }, |
3825 | { "hsubps", { XM, EXx }, PREFIX_OPCODE }, | |
ca164297 | 3826 | }, |
4e7d34a6 | 3827 | |
1ceb70f8 | 3828 | /* PREFIX_0F7E */ |
ca164297 | 3829 | { |
507bd325 L |
3830 | { "movK", { Edq, MX }, PREFIX_OPCODE }, |
3831 | { "movq", { XM, EXq }, PREFIX_OPCODE }, | |
3832 | { "movK", { Edq, XM }, PREFIX_OPCODE }, | |
ca164297 | 3833 | }, |
4e7d34a6 | 3834 | |
1ceb70f8 | 3835 | /* PREFIX_0F7F */ |
ca164297 | 3836 | { |
507bd325 L |
3837 | { "movq", { EMS, MX }, PREFIX_OPCODE }, |
3838 | { "movdqu", { EXxS, XM }, PREFIX_OPCODE }, | |
3839 | { "movdqa", { EXxS, XM }, PREFIX_OPCODE }, | |
ca164297 | 3840 | }, |
4e7d34a6 | 3841 | |
f8687e93 | 3842 | /* PREFIX_0FAE_REG_0_MOD_3 */ |
c7b8aa3a L |
3843 | { |
3844 | { Bad_Opcode }, | |
bf890a93 | 3845 | { "rdfsbase", { Ev }, 0 }, |
c7b8aa3a L |
3846 | }, |
3847 | ||
f8687e93 | 3848 | /* PREFIX_0FAE_REG_1_MOD_3 */ |
c7b8aa3a L |
3849 | { |
3850 | { Bad_Opcode }, | |
bf890a93 | 3851 | { "rdgsbase", { Ev }, 0 }, |
c7b8aa3a L |
3852 | }, |
3853 | ||
f8687e93 | 3854 | /* PREFIX_0FAE_REG_2_MOD_3 */ |
c7b8aa3a L |
3855 | { |
3856 | { Bad_Opcode }, | |
bf890a93 | 3857 | { "wrfsbase", { Ev }, 0 }, |
c7b8aa3a L |
3858 | }, |
3859 | ||
f8687e93 | 3860 | /* PREFIX_0FAE_REG_3_MOD_3 */ |
c7b8aa3a L |
3861 | { |
3862 | { Bad_Opcode }, | |
bf890a93 | 3863 | { "wrgsbase", { Ev }, 0 }, |
c7b8aa3a L |
3864 | }, |
3865 | ||
f8687e93 | 3866 | /* PREFIX_0FAE_REG_4_MOD_0 */ |
6b40c462 L |
3867 | { |
3868 | { "xsave", { FXSAVE }, 0 }, | |
3869 | { "ptwrite%LQ", { Edq }, 0 }, | |
3870 | }, | |
3871 | ||
f8687e93 | 3872 | /* PREFIX_0FAE_REG_4_MOD_3 */ |
6b40c462 L |
3873 | { |
3874 | { Bad_Opcode }, | |
3875 | { "ptwrite%LQ", { Edq }, 0 }, | |
3876 | }, | |
3877 | ||
f8687e93 | 3878 | /* PREFIX_0FAE_REG_5_MOD_0 */ |
603555e5 L |
3879 | { |
3880 | { "xrstor", { FXSAVE }, PREFIX_OPCODE }, | |
2234eee6 L |
3881 | }, |
3882 | ||
f8687e93 | 3883 | /* PREFIX_0FAE_REG_5_MOD_3 */ |
2234eee6 L |
3884 | { |
3885 | { "lfence", { Skip_MODRM }, 0 }, | |
3886 | { "incsspK", { Rdq }, PREFIX_OPCODE }, | |
603555e5 L |
3887 | }, |
3888 | ||
f8687e93 | 3889 | /* PREFIX_0FAE_REG_6_MOD_0 */ |
c5e7287a | 3890 | { |
603555e5 L |
3891 | { "xsaveopt", { FXSAVE }, PREFIX_OPCODE }, |
3892 | { "clrssbsy", { Mq }, PREFIX_OPCODE }, | |
3893 | { "clwb", { Mb }, PREFIX_OPCODE }, | |
c5e7287a IT |
3894 | }, |
3895 | ||
f8687e93 | 3896 | /* PREFIX_0FAE_REG_6_MOD_3 */ |
de89d0a3 | 3897 | { |
f8687e93 | 3898 | { RM_TABLE (RM_0FAE_REG_6_MOD_3_P_0) }, |
de89d0a3 | 3899 | { "umonitor", { Eva }, PREFIX_OPCODE }, |
ae1d3843 L |
3900 | { "tpause", { Edq }, PREFIX_OPCODE }, |
3901 | { "umwait", { Edq }, PREFIX_OPCODE }, | |
de89d0a3 IT |
3902 | }, |
3903 | ||
f8687e93 | 3904 | /* PREFIX_0FAE_REG_7_MOD_0 */ |
963f3586 | 3905 | { |
bf890a93 | 3906 | { "clflush", { Mb }, 0 }, |
963f3586 | 3907 | { Bad_Opcode }, |
bf890a93 | 3908 | { "clflushopt", { Mb }, 0 }, |
963f3586 IT |
3909 | }, |
3910 | ||
1ceb70f8 | 3911 | /* PREFIX_0FB8 */ |
ca164297 | 3912 | { |
592d1631 | 3913 | { Bad_Opcode }, |
bf890a93 | 3914 | { "popcntS", { Gv, Ev }, 0 }, |
ca164297 | 3915 | }, |
4e7d34a6 | 3916 | |
f12dc422 L |
3917 | /* PREFIX_0FBC */ |
3918 | { | |
bf890a93 IT |
3919 | { "bsfS", { Gv, Ev }, 0 }, |
3920 | { "tzcntS", { Gv, Ev }, 0 }, | |
3921 | { "bsfS", { Gv, Ev }, 0 }, | |
f12dc422 L |
3922 | }, |
3923 | ||
1ceb70f8 | 3924 | /* PREFIX_0FBD */ |
050dfa73 | 3925 | { |
bf890a93 IT |
3926 | { "bsrS", { Gv, Ev }, 0 }, |
3927 | { "lzcntS", { Gv, Ev }, 0 }, | |
3928 | { "bsrS", { Gv, Ev }, 0 }, | |
050dfa73 MM |
3929 | }, |
3930 | ||
1ceb70f8 | 3931 | /* PREFIX_0FC2 */ |
050dfa73 | 3932 | { |
507bd325 L |
3933 | { "cmpps", { XM, EXx, CMP }, PREFIX_OPCODE }, |
3934 | { "cmpss", { XM, EXd, CMP }, PREFIX_OPCODE }, | |
3935 | { "cmppd", { XM, EXx, CMP }, PREFIX_OPCODE }, | |
3936 | { "cmpsd", { XM, EXq, CMP }, PREFIX_OPCODE }, | |
050dfa73 | 3937 | }, |
246c51aa | 3938 | |
f8687e93 | 3939 | /* PREFIX_0FC3_MOD_0 */ |
4ee52178 | 3940 | { |
e1a1babd | 3941 | { "movntiS", { Edq, Gdq }, PREFIX_OPCODE }, |
4ee52178 L |
3942 | }, |
3943 | ||
f8687e93 | 3944 | /* PREFIX_0FC7_REG_6_MOD_0 */ |
92fddf8e | 3945 | { |
bf890a93 IT |
3946 | { "vmptrld",{ Mq }, 0 }, |
3947 | { "vmxon", { Mq }, 0 }, | |
3948 | { "vmclear",{ Mq }, 0 }, | |
92fddf8e L |
3949 | }, |
3950 | ||
f8687e93 | 3951 | /* PREFIX_0FC7_REG_6_MOD_3 */ |
f24bcbaa L |
3952 | { |
3953 | { "rdrand", { Ev }, 0 }, | |
3954 | { Bad_Opcode }, | |
3955 | { "rdrand", { Ev }, 0 } | |
3956 | }, | |
3957 | ||
f8687e93 | 3958 | /* PREFIX_0FC7_REG_7_MOD_3 */ |
f24bcbaa L |
3959 | { |
3960 | { "rdseed", { Ev }, 0 }, | |
8bc52696 | 3961 | { "rdpid", { Em }, 0 }, |
f24bcbaa L |
3962 | { "rdseed", { Ev }, 0 }, |
3963 | }, | |
3964 | ||
1ceb70f8 | 3965 | /* PREFIX_0FD0 */ |
050dfa73 | 3966 | { |
592d1631 L |
3967 | { Bad_Opcode }, |
3968 | { Bad_Opcode }, | |
bf890a93 IT |
3969 | { "addsubpd", { XM, EXx }, 0 }, |
3970 | { "addsubps", { XM, EXx }, 0 }, | |
246c51aa | 3971 | }, |
050dfa73 | 3972 | |
1ceb70f8 | 3973 | /* PREFIX_0FD6 */ |
050dfa73 | 3974 | { |
592d1631 | 3975 | { Bad_Opcode }, |
bf890a93 IT |
3976 | { "movq2dq",{ XM, MS }, 0 }, |
3977 | { "movq", { EXqS, XM }, 0 }, | |
3978 | { "movdq2q",{ MX, XS }, 0 }, | |
050dfa73 MM |
3979 | }, |
3980 | ||
1ceb70f8 | 3981 | /* PREFIX_0FE6 */ |
7918206c | 3982 | { |
592d1631 | 3983 | { Bad_Opcode }, |
507bd325 L |
3984 | { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE }, |
3985 | { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE }, | |
3986 | { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE }, | |
7918206c | 3987 | }, |
8b38ad71 | 3988 | |
1ceb70f8 | 3989 | /* PREFIX_0FE7 */ |
8b38ad71 | 3990 | { |
507bd325 | 3991 | { "movntq", { Mq, MX }, PREFIX_OPCODE }, |
592d1631 | 3992 | { Bad_Opcode }, |
75c135a8 | 3993 | { MOD_TABLE (MOD_0FE7_PREFIX_2) }, |
4e7d34a6 L |
3994 | }, |
3995 | ||
1ceb70f8 | 3996 | /* PREFIX_0FF0 */ |
4e7d34a6 | 3997 | { |
592d1631 L |
3998 | { Bad_Opcode }, |
3999 | { Bad_Opcode }, | |
4000 | { Bad_Opcode }, | |
1ceb70f8 | 4001 | { MOD_TABLE (MOD_0FF0_PREFIX_3) }, |
4e7d34a6 L |
4002 | }, |
4003 | ||
1ceb70f8 | 4004 | /* PREFIX_0FF7 */ |
4e7d34a6 | 4005 | { |
507bd325 | 4006 | { "maskmovq", { MX, MS }, PREFIX_OPCODE }, |
592d1631 | 4007 | { Bad_Opcode }, |
507bd325 | 4008 | { "maskmovdqu", { XM, XS }, PREFIX_OPCODE }, |
8b38ad71 | 4009 | }, |
42903f7f | 4010 | |
1ceb70f8 | 4011 | /* PREFIX_0F3810 */ |
42903f7f | 4012 | { |
592d1631 L |
4013 | { Bad_Opcode }, |
4014 | { Bad_Opcode }, | |
507bd325 | 4015 | { "pblendvb", { XM, EXx, XMM0 }, PREFIX_OPCODE }, |
42903f7f L |
4016 | }, |
4017 | ||
1ceb70f8 | 4018 | /* PREFIX_0F3814 */ |
42903f7f | 4019 | { |
592d1631 L |
4020 | { Bad_Opcode }, |
4021 | { Bad_Opcode }, | |
507bd325 | 4022 | { "blendvps", { XM, EXx, XMM0 }, PREFIX_OPCODE }, |
42903f7f L |
4023 | }, |
4024 | ||
1ceb70f8 | 4025 | /* PREFIX_0F3815 */ |
42903f7f | 4026 | { |
592d1631 L |
4027 | { Bad_Opcode }, |
4028 | { Bad_Opcode }, | |
507bd325 | 4029 | { "blendvpd", { XM, EXx, XMM0 }, PREFIX_OPCODE }, |
42903f7f L |
4030 | }, |
4031 | ||
1ceb70f8 | 4032 | /* PREFIX_0F3817 */ |
42903f7f | 4033 | { |
592d1631 L |
4034 | { Bad_Opcode }, |
4035 | { Bad_Opcode }, | |
507bd325 | 4036 | { "ptest", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4037 | }, |
4038 | ||
1ceb70f8 | 4039 | /* PREFIX_0F3820 */ |
42903f7f | 4040 | { |
592d1631 L |
4041 | { Bad_Opcode }, |
4042 | { Bad_Opcode }, | |
507bd325 | 4043 | { "pmovsxbw", { XM, EXq }, PREFIX_OPCODE }, |
42903f7f L |
4044 | }, |
4045 | ||
1ceb70f8 | 4046 | /* PREFIX_0F3821 */ |
42903f7f | 4047 | { |
592d1631 L |
4048 | { Bad_Opcode }, |
4049 | { Bad_Opcode }, | |
507bd325 | 4050 | { "pmovsxbd", { XM, EXd }, PREFIX_OPCODE }, |
42903f7f L |
4051 | }, |
4052 | ||
1ceb70f8 | 4053 | /* PREFIX_0F3822 */ |
42903f7f | 4054 | { |
592d1631 L |
4055 | { Bad_Opcode }, |
4056 | { Bad_Opcode }, | |
507bd325 | 4057 | { "pmovsxbq", { XM, EXw }, PREFIX_OPCODE }, |
42903f7f L |
4058 | }, |
4059 | ||
1ceb70f8 | 4060 | /* PREFIX_0F3823 */ |
42903f7f | 4061 | { |
592d1631 L |
4062 | { Bad_Opcode }, |
4063 | { Bad_Opcode }, | |
507bd325 | 4064 | { "pmovsxwd", { XM, EXq }, PREFIX_OPCODE }, |
42903f7f L |
4065 | }, |
4066 | ||
1ceb70f8 | 4067 | /* PREFIX_0F3824 */ |
42903f7f | 4068 | { |
592d1631 L |
4069 | { Bad_Opcode }, |
4070 | { Bad_Opcode }, | |
507bd325 | 4071 | { "pmovsxwq", { XM, EXd }, PREFIX_OPCODE }, |
42903f7f L |
4072 | }, |
4073 | ||
1ceb70f8 | 4074 | /* PREFIX_0F3825 */ |
42903f7f | 4075 | { |
592d1631 L |
4076 | { Bad_Opcode }, |
4077 | { Bad_Opcode }, | |
507bd325 | 4078 | { "pmovsxdq", { XM, EXq }, PREFIX_OPCODE }, |
42903f7f L |
4079 | }, |
4080 | ||
1ceb70f8 | 4081 | /* PREFIX_0F3828 */ |
42903f7f | 4082 | { |
592d1631 L |
4083 | { Bad_Opcode }, |
4084 | { Bad_Opcode }, | |
507bd325 | 4085 | { "pmuldq", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4086 | }, |
4087 | ||
1ceb70f8 | 4088 | /* PREFIX_0F3829 */ |
42903f7f | 4089 | { |
592d1631 L |
4090 | { Bad_Opcode }, |
4091 | { Bad_Opcode }, | |
507bd325 | 4092 | { "pcmpeqq", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4093 | }, |
4094 | ||
1ceb70f8 | 4095 | /* PREFIX_0F382A */ |
42903f7f | 4096 | { |
592d1631 L |
4097 | { Bad_Opcode }, |
4098 | { Bad_Opcode }, | |
75c135a8 | 4099 | { MOD_TABLE (MOD_0F382A_PREFIX_2) }, |
42903f7f L |
4100 | }, |
4101 | ||
1ceb70f8 | 4102 | /* PREFIX_0F382B */ |
42903f7f | 4103 | { |
592d1631 L |
4104 | { Bad_Opcode }, |
4105 | { Bad_Opcode }, | |
507bd325 | 4106 | { "packusdw", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4107 | }, |
4108 | ||
1ceb70f8 | 4109 | /* PREFIX_0F3830 */ |
42903f7f | 4110 | { |
592d1631 L |
4111 | { Bad_Opcode }, |
4112 | { Bad_Opcode }, | |
507bd325 | 4113 | { "pmovzxbw", { XM, EXq }, PREFIX_OPCODE }, |
42903f7f L |
4114 | }, |
4115 | ||
1ceb70f8 | 4116 | /* PREFIX_0F3831 */ |
42903f7f | 4117 | { |
592d1631 L |
4118 | { Bad_Opcode }, |
4119 | { Bad_Opcode }, | |
507bd325 | 4120 | { "pmovzxbd", { XM, EXd }, PREFIX_OPCODE }, |
42903f7f L |
4121 | }, |
4122 | ||
1ceb70f8 | 4123 | /* PREFIX_0F3832 */ |
42903f7f | 4124 | { |
592d1631 L |
4125 | { Bad_Opcode }, |
4126 | { Bad_Opcode }, | |
507bd325 | 4127 | { "pmovzxbq", { XM, EXw }, PREFIX_OPCODE }, |
42903f7f L |
4128 | }, |
4129 | ||
1ceb70f8 | 4130 | /* PREFIX_0F3833 */ |
42903f7f | 4131 | { |
592d1631 L |
4132 | { Bad_Opcode }, |
4133 | { Bad_Opcode }, | |
507bd325 | 4134 | { "pmovzxwd", { XM, EXq }, PREFIX_OPCODE }, |
42903f7f L |
4135 | }, |
4136 | ||
1ceb70f8 | 4137 | /* PREFIX_0F3834 */ |
42903f7f | 4138 | { |
592d1631 L |
4139 | { Bad_Opcode }, |
4140 | { Bad_Opcode }, | |
507bd325 | 4141 | { "pmovzxwq", { XM, EXd }, PREFIX_OPCODE }, |
42903f7f L |
4142 | }, |
4143 | ||
1ceb70f8 | 4144 | /* PREFIX_0F3835 */ |
42903f7f | 4145 | { |
592d1631 L |
4146 | { Bad_Opcode }, |
4147 | { Bad_Opcode }, | |
507bd325 | 4148 | { "pmovzxdq", { XM, EXq }, PREFIX_OPCODE }, |
42903f7f L |
4149 | }, |
4150 | ||
1ceb70f8 | 4151 | /* PREFIX_0F3837 */ |
4e7d34a6 | 4152 | { |
592d1631 L |
4153 | { Bad_Opcode }, |
4154 | { Bad_Opcode }, | |
507bd325 | 4155 | { "pcmpgtq", { XM, EXx }, PREFIX_OPCODE }, |
4e7d34a6 L |
4156 | }, |
4157 | ||
1ceb70f8 | 4158 | /* PREFIX_0F3838 */ |
42903f7f | 4159 | { |
592d1631 L |
4160 | { Bad_Opcode }, |
4161 | { Bad_Opcode }, | |
507bd325 | 4162 | { "pminsb", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4163 | }, |
4164 | ||
1ceb70f8 | 4165 | /* PREFIX_0F3839 */ |
42903f7f | 4166 | { |
592d1631 L |
4167 | { Bad_Opcode }, |
4168 | { Bad_Opcode }, | |
507bd325 | 4169 | { "pminsd", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4170 | }, |
4171 | ||
1ceb70f8 | 4172 | /* PREFIX_0F383A */ |
42903f7f | 4173 | { |
592d1631 L |
4174 | { Bad_Opcode }, |
4175 | { Bad_Opcode }, | |
507bd325 | 4176 | { "pminuw", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4177 | }, |
4178 | ||
1ceb70f8 | 4179 | /* PREFIX_0F383B */ |
42903f7f | 4180 | { |
592d1631 L |
4181 | { Bad_Opcode }, |
4182 | { Bad_Opcode }, | |
507bd325 | 4183 | { "pminud", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4184 | }, |
4185 | ||
1ceb70f8 | 4186 | /* PREFIX_0F383C */ |
42903f7f | 4187 | { |
592d1631 L |
4188 | { Bad_Opcode }, |
4189 | { Bad_Opcode }, | |
507bd325 | 4190 | { "pmaxsb", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4191 | }, |
4192 | ||
1ceb70f8 | 4193 | /* PREFIX_0F383D */ |
42903f7f | 4194 | { |
592d1631 L |
4195 | { Bad_Opcode }, |
4196 | { Bad_Opcode }, | |
507bd325 | 4197 | { "pmaxsd", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4198 | }, |
4199 | ||
1ceb70f8 | 4200 | /* PREFIX_0F383E */ |
42903f7f | 4201 | { |
592d1631 L |
4202 | { Bad_Opcode }, |
4203 | { Bad_Opcode }, | |
507bd325 | 4204 | { "pmaxuw", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4205 | }, |
4206 | ||
1ceb70f8 | 4207 | /* PREFIX_0F383F */ |
42903f7f | 4208 | { |
592d1631 L |
4209 | { Bad_Opcode }, |
4210 | { Bad_Opcode }, | |
507bd325 | 4211 | { "pmaxud", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4212 | }, |
4213 | ||
1ceb70f8 | 4214 | /* PREFIX_0F3840 */ |
42903f7f | 4215 | { |
592d1631 L |
4216 | { Bad_Opcode }, |
4217 | { Bad_Opcode }, | |
507bd325 | 4218 | { "pmulld", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4219 | }, |
4220 | ||
1ceb70f8 | 4221 | /* PREFIX_0F3841 */ |
42903f7f | 4222 | { |
592d1631 L |
4223 | { Bad_Opcode }, |
4224 | { Bad_Opcode }, | |
507bd325 | 4225 | { "phminposuw", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4226 | }, |
4227 | ||
f1f8f695 L |
4228 | /* PREFIX_0F3880 */ |
4229 | { | |
592d1631 L |
4230 | { Bad_Opcode }, |
4231 | { Bad_Opcode }, | |
507bd325 | 4232 | { "invept", { Gm, Mo }, PREFIX_OPCODE }, |
f1f8f695 L |
4233 | }, |
4234 | ||
4235 | /* PREFIX_0F3881 */ | |
4236 | { | |
592d1631 L |
4237 | { Bad_Opcode }, |
4238 | { Bad_Opcode }, | |
507bd325 | 4239 | { "invvpid", { Gm, Mo }, PREFIX_OPCODE }, |
f1f8f695 L |
4240 | }, |
4241 | ||
6c30d220 L |
4242 | /* PREFIX_0F3882 */ |
4243 | { | |
4244 | { Bad_Opcode }, | |
4245 | { Bad_Opcode }, | |
507bd325 | 4246 | { "invpcid", { Gm, M }, PREFIX_OPCODE }, |
6c30d220 L |
4247 | }, |
4248 | ||
a0046408 L |
4249 | /* PREFIX_0F38C8 */ |
4250 | { | |
507bd325 | 4251 | { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE }, |
a0046408 L |
4252 | }, |
4253 | ||
4254 | /* PREFIX_0F38C9 */ | |
4255 | { | |
507bd325 | 4256 | { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE }, |
a0046408 L |
4257 | }, |
4258 | ||
4259 | /* PREFIX_0F38CA */ | |
4260 | { | |
507bd325 | 4261 | { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE }, |
a0046408 L |
4262 | }, |
4263 | ||
4264 | /* PREFIX_0F38CB */ | |
4265 | { | |
507bd325 | 4266 | { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE }, |
a0046408 L |
4267 | }, |
4268 | ||
4269 | /* PREFIX_0F38CC */ | |
4270 | { | |
507bd325 | 4271 | { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE }, |
a0046408 L |
4272 | }, |
4273 | ||
4274 | /* PREFIX_0F38CD */ | |
4275 | { | |
507bd325 | 4276 | { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE }, |
a0046408 L |
4277 | }, |
4278 | ||
48521003 IT |
4279 | /* PREFIX_0F38CF */ |
4280 | { | |
4281 | { Bad_Opcode }, | |
4282 | { Bad_Opcode }, | |
4283 | { "gf2p8mulb", { XM, EXxmm }, PREFIX_OPCODE }, | |
4284 | }, | |
4285 | ||
c0f3af97 L |
4286 | /* PREFIX_0F38DB */ |
4287 | { | |
592d1631 L |
4288 | { Bad_Opcode }, |
4289 | { Bad_Opcode }, | |
507bd325 | 4290 | { "aesimc", { XM, EXx }, PREFIX_OPCODE }, |
c0f3af97 L |
4291 | }, |
4292 | ||
4293 | /* PREFIX_0F38DC */ | |
4294 | { | |
592d1631 L |
4295 | { Bad_Opcode }, |
4296 | { Bad_Opcode }, | |
507bd325 | 4297 | { "aesenc", { XM, EXx }, PREFIX_OPCODE }, |
c0f3af97 L |
4298 | }, |
4299 | ||
4300 | /* PREFIX_0F38DD */ | |
4301 | { | |
592d1631 L |
4302 | { Bad_Opcode }, |
4303 | { Bad_Opcode }, | |
507bd325 | 4304 | { "aesenclast", { XM, EXx }, PREFIX_OPCODE }, |
c0f3af97 L |
4305 | }, |
4306 | ||
4307 | /* PREFIX_0F38DE */ | |
4308 | { | |
592d1631 L |
4309 | { Bad_Opcode }, |
4310 | { Bad_Opcode }, | |
507bd325 | 4311 | { "aesdec", { XM, EXx }, PREFIX_OPCODE }, |
c0f3af97 L |
4312 | }, |
4313 | ||
4314 | /* PREFIX_0F38DF */ | |
4315 | { | |
592d1631 L |
4316 | { Bad_Opcode }, |
4317 | { Bad_Opcode }, | |
507bd325 | 4318 | { "aesdeclast", { XM, EXx }, PREFIX_OPCODE }, |
c0f3af97 L |
4319 | }, |
4320 | ||
1ceb70f8 | 4321 | /* PREFIX_0F38F0 */ |
4e7d34a6 | 4322 | { |
507bd325 | 4323 | { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE }, |
592d1631 | 4324 | { Bad_Opcode }, |
507bd325 L |
4325 | { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE }, |
4326 | { "crc32", { Gdq, { CRC32_Fixup, b_mode } }, PREFIX_OPCODE }, | |
4e7d34a6 L |
4327 | }, |
4328 | ||
1ceb70f8 | 4329 | /* PREFIX_0F38F1 */ |
4e7d34a6 | 4330 | { |
507bd325 | 4331 | { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE }, |
592d1631 | 4332 | { Bad_Opcode }, |
507bd325 L |
4333 | { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE }, |
4334 | { "crc32", { Gdq, { CRC32_Fixup, v_mode } }, PREFIX_OPCODE }, | |
4e7d34a6 L |
4335 | }, |
4336 | ||
603555e5 | 4337 | /* PREFIX_0F38F5 */ |
e2e1fcde L |
4338 | { |
4339 | { Bad_Opcode }, | |
603555e5 L |
4340 | { Bad_Opcode }, |
4341 | { MOD_TABLE (MOD_0F38F5_PREFIX_2) }, | |
4342 | }, | |
4343 | ||
4344 | /* PREFIX_0F38F6 */ | |
4345 | { | |
4346 | { MOD_TABLE (MOD_0F38F6_PREFIX_0) }, | |
507bd325 L |
4347 | { "adoxS", { Gdq, Edq}, PREFIX_OPCODE }, |
4348 | { "adcxS", { Gdq, Edq}, PREFIX_OPCODE }, | |
e2e1fcde L |
4349 | { Bad_Opcode }, |
4350 | }, | |
4351 | ||
c0a30a9f L |
4352 | /* PREFIX_0F38F8 */ |
4353 | { | |
4354 | { Bad_Opcode }, | |
5d79adc4 | 4355 | { MOD_TABLE (MOD_0F38F8_PREFIX_1) }, |
c0a30a9f | 4356 | { MOD_TABLE (MOD_0F38F8_PREFIX_2) }, |
5d79adc4 | 4357 | { MOD_TABLE (MOD_0F38F8_PREFIX_3) }, |
c0a30a9f L |
4358 | }, |
4359 | ||
4360 | /* PREFIX_0F38F9 */ | |
4361 | { | |
4362 | { MOD_TABLE (MOD_0F38F9_PREFIX_0) }, | |
4363 | }, | |
4364 | ||
1ceb70f8 | 4365 | /* PREFIX_0F3A08 */ |
42903f7f | 4366 | { |
592d1631 L |
4367 | { Bad_Opcode }, |
4368 | { Bad_Opcode }, | |
507bd325 | 4369 | { "roundps", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4370 | }, |
4371 | ||
1ceb70f8 | 4372 | /* PREFIX_0F3A09 */ |
42903f7f | 4373 | { |
592d1631 L |
4374 | { Bad_Opcode }, |
4375 | { Bad_Opcode }, | |
507bd325 | 4376 | { "roundpd", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4377 | }, |
4378 | ||
1ceb70f8 | 4379 | /* PREFIX_0F3A0A */ |
42903f7f | 4380 | { |
592d1631 L |
4381 | { Bad_Opcode }, |
4382 | { Bad_Opcode }, | |
507bd325 | 4383 | { "roundss", { XM, EXd, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4384 | }, |
4385 | ||
1ceb70f8 | 4386 | /* PREFIX_0F3A0B */ |
42903f7f | 4387 | { |
592d1631 L |
4388 | { Bad_Opcode }, |
4389 | { Bad_Opcode }, | |
507bd325 | 4390 | { "roundsd", { XM, EXq, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4391 | }, |
4392 | ||
1ceb70f8 | 4393 | /* PREFIX_0F3A0C */ |
42903f7f | 4394 | { |
592d1631 L |
4395 | { Bad_Opcode }, |
4396 | { Bad_Opcode }, | |
507bd325 | 4397 | { "blendps", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4398 | }, |
4399 | ||
1ceb70f8 | 4400 | /* PREFIX_0F3A0D */ |
42903f7f | 4401 | { |
592d1631 L |
4402 | { Bad_Opcode }, |
4403 | { Bad_Opcode }, | |
507bd325 | 4404 | { "blendpd", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4405 | }, |
4406 | ||
1ceb70f8 | 4407 | /* PREFIX_0F3A0E */ |
42903f7f | 4408 | { |
592d1631 L |
4409 | { Bad_Opcode }, |
4410 | { Bad_Opcode }, | |
507bd325 | 4411 | { "pblendw", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4412 | }, |
4413 | ||
1ceb70f8 | 4414 | /* PREFIX_0F3A14 */ |
42903f7f | 4415 | { |
592d1631 L |
4416 | { Bad_Opcode }, |
4417 | { Bad_Opcode }, | |
507bd325 | 4418 | { "pextrb", { Edqb, XM, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4419 | }, |
4420 | ||
1ceb70f8 | 4421 | /* PREFIX_0F3A15 */ |
42903f7f | 4422 | { |
592d1631 L |
4423 | { Bad_Opcode }, |
4424 | { Bad_Opcode }, | |
507bd325 | 4425 | { "pextrw", { Edqw, XM, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4426 | }, |
4427 | ||
1ceb70f8 | 4428 | /* PREFIX_0F3A16 */ |
42903f7f | 4429 | { |
592d1631 L |
4430 | { Bad_Opcode }, |
4431 | { Bad_Opcode }, | |
507bd325 | 4432 | { "pextrK", { Edq, XM, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4433 | }, |
4434 | ||
1ceb70f8 | 4435 | /* PREFIX_0F3A17 */ |
42903f7f | 4436 | { |
592d1631 L |
4437 | { Bad_Opcode }, |
4438 | { Bad_Opcode }, | |
507bd325 | 4439 | { "extractps", { Edqd, XM, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4440 | }, |
4441 | ||
1ceb70f8 | 4442 | /* PREFIX_0F3A20 */ |
42903f7f | 4443 | { |
592d1631 L |
4444 | { Bad_Opcode }, |
4445 | { Bad_Opcode }, | |
507bd325 | 4446 | { "pinsrb", { XM, Edqb, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4447 | }, |
4448 | ||
1ceb70f8 | 4449 | /* PREFIX_0F3A21 */ |
42903f7f | 4450 | { |
592d1631 L |
4451 | { Bad_Opcode }, |
4452 | { Bad_Opcode }, | |
507bd325 | 4453 | { "insertps", { XM, EXd, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4454 | }, |
4455 | ||
1ceb70f8 | 4456 | /* PREFIX_0F3A22 */ |
42903f7f | 4457 | { |
592d1631 L |
4458 | { Bad_Opcode }, |
4459 | { Bad_Opcode }, | |
507bd325 | 4460 | { "pinsrK", { XM, Edq, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4461 | }, |
4462 | ||
1ceb70f8 | 4463 | /* PREFIX_0F3A40 */ |
42903f7f | 4464 | { |
592d1631 L |
4465 | { Bad_Opcode }, |
4466 | { Bad_Opcode }, | |
507bd325 | 4467 | { "dpps", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4468 | }, |
4469 | ||
1ceb70f8 | 4470 | /* PREFIX_0F3A41 */ |
42903f7f | 4471 | { |
592d1631 L |
4472 | { Bad_Opcode }, |
4473 | { Bad_Opcode }, | |
507bd325 | 4474 | { "dppd", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4475 | }, |
4476 | ||
1ceb70f8 | 4477 | /* PREFIX_0F3A42 */ |
42903f7f | 4478 | { |
592d1631 L |
4479 | { Bad_Opcode }, |
4480 | { Bad_Opcode }, | |
507bd325 | 4481 | { "mpsadbw", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f | 4482 | }, |
381d071f | 4483 | |
c0f3af97 L |
4484 | /* PREFIX_0F3A44 */ |
4485 | { | |
592d1631 L |
4486 | { Bad_Opcode }, |
4487 | { Bad_Opcode }, | |
507bd325 | 4488 | { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_OPCODE }, |
c0f3af97 L |
4489 | }, |
4490 | ||
1ceb70f8 | 4491 | /* PREFIX_0F3A60 */ |
381d071f | 4492 | { |
592d1631 L |
4493 | { Bad_Opcode }, |
4494 | { Bad_Opcode }, | |
15c7c1d8 | 4495 | { "pcmpestrm", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE }, |
381d071f L |
4496 | }, |
4497 | ||
1ceb70f8 | 4498 | /* PREFIX_0F3A61 */ |
381d071f | 4499 | { |
592d1631 L |
4500 | { Bad_Opcode }, |
4501 | { Bad_Opcode }, | |
15c7c1d8 | 4502 | { "pcmpestri", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE }, |
381d071f L |
4503 | }, |
4504 | ||
1ceb70f8 | 4505 | /* PREFIX_0F3A62 */ |
381d071f | 4506 | { |
592d1631 L |
4507 | { Bad_Opcode }, |
4508 | { Bad_Opcode }, | |
507bd325 | 4509 | { "pcmpistrm", { XM, EXx, Ib }, PREFIX_OPCODE }, |
381d071f L |
4510 | }, |
4511 | ||
1ceb70f8 | 4512 | /* PREFIX_0F3A63 */ |
381d071f | 4513 | { |
592d1631 L |
4514 | { Bad_Opcode }, |
4515 | { Bad_Opcode }, | |
507bd325 | 4516 | { "pcmpistri", { XM, EXx, Ib }, PREFIX_OPCODE }, |
381d071f | 4517 | }, |
09a2c6cf | 4518 | |
a0046408 L |
4519 | /* PREFIX_0F3ACC */ |
4520 | { | |
507bd325 | 4521 | { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE }, |
a0046408 L |
4522 | }, |
4523 | ||
48521003 IT |
4524 | /* PREFIX_0F3ACE */ |
4525 | { | |
4526 | { Bad_Opcode }, | |
4527 | { Bad_Opcode }, | |
4528 | { "gf2p8affineqb", { XM, EXxmm, Ib }, PREFIX_OPCODE }, | |
4529 | }, | |
4530 | ||
4531 | /* PREFIX_0F3ACF */ | |
4532 | { | |
4533 | { Bad_Opcode }, | |
4534 | { Bad_Opcode }, | |
4535 | { "gf2p8affineinvqb", { XM, EXxmm, Ib }, PREFIX_OPCODE }, | |
4536 | }, | |
4537 | ||
c0f3af97 | 4538 | /* PREFIX_0F3ADF */ |
09a2c6cf | 4539 | { |
592d1631 L |
4540 | { Bad_Opcode }, |
4541 | { Bad_Opcode }, | |
507bd325 | 4542 | { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_OPCODE }, |
09a2c6cf L |
4543 | }, |
4544 | ||
592a252b | 4545 | /* PREFIX_VEX_0F10 */ |
09a2c6cf | 4546 | { |
ec6f095a | 4547 | { "vmovups", { XM, EXx }, 0 }, |
5b872f7d | 4548 | { "vmovss", { XMVexScalar, VexScalar, EXxmm_md }, 0 }, |
ec6f095a | 4549 | { "vmovupd", { XM, EXx }, 0 }, |
5b872f7d | 4550 | { "vmovsd", { XMVexScalar, VexScalar, EXxmm_mq }, 0 }, |
09a2c6cf L |
4551 | }, |
4552 | ||
592a252b | 4553 | /* PREFIX_VEX_0F11 */ |
09a2c6cf | 4554 | { |
ec6f095a L |
4555 | { "vmovups", { EXxS, XM }, 0 }, |
4556 | { "vmovss", { EXdVexScalarS, VexScalar, XMScalar }, 0 }, | |
4557 | { "vmovupd", { EXxS, XM }, 0 }, | |
4558 | { "vmovsd", { EXqVexScalarS, VexScalar, XMScalar }, 0 }, | |
09a2c6cf L |
4559 | }, |
4560 | ||
592a252b | 4561 | /* PREFIX_VEX_0F12 */ |
09a2c6cf | 4562 | { |
592a252b | 4563 | { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) }, |
ec6f095a | 4564 | { "vmovsldup", { XM, EXx }, 0 }, |
18897deb | 4565 | { MOD_TABLE (MOD_VEX_0F12_PREFIX_2) }, |
ec6f095a | 4566 | { "vmovddup", { XM, EXymmq }, 0 }, |
09a2c6cf L |
4567 | }, |
4568 | ||
592a252b | 4569 | /* PREFIX_VEX_0F16 */ |
09a2c6cf | 4570 | { |
592a252b | 4571 | { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) }, |
ec6f095a | 4572 | { "vmovshdup", { XM, EXx }, 0 }, |
18897deb | 4573 | { MOD_TABLE (MOD_VEX_0F16_PREFIX_2) }, |
5f754f58 | 4574 | }, |
7c52e0e8 | 4575 | |
592a252b | 4576 | /* PREFIX_VEX_0F2A */ |
5f754f58 | 4577 | { |
592d1631 | 4578 | { Bad_Opcode }, |
2b7bcc87 | 4579 | { "vcvtsi2ss%LQ", { XMScalar, VexScalar, Edq }, 0 }, |
592d1631 | 4580 | { Bad_Opcode }, |
2b7bcc87 | 4581 | { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Edq }, 0 }, |
5f754f58 | 4582 | }, |
7c52e0e8 | 4583 | |
592a252b | 4584 | /* PREFIX_VEX_0F2C */ |
5f754f58 | 4585 | { |
592d1631 | 4586 | { Bad_Opcode }, |
5b872f7d | 4587 | { "vcvttss2si", { Gdq, EXxmm_md }, 0 }, |
592d1631 | 4588 | { Bad_Opcode }, |
5b872f7d | 4589 | { "vcvttsd2si", { Gdq, EXxmm_mq }, 0 }, |
5f754f58 | 4590 | }, |
7c52e0e8 | 4591 | |
592a252b | 4592 | /* PREFIX_VEX_0F2D */ |
7c52e0e8 | 4593 | { |
592d1631 | 4594 | { Bad_Opcode }, |
5b872f7d | 4595 | { "vcvtss2si", { Gdq, EXxmm_md }, 0 }, |
592d1631 | 4596 | { Bad_Opcode }, |
5b872f7d | 4597 | { "vcvtsd2si", { Gdq, EXxmm_mq }, 0 }, |
7c52e0e8 L |
4598 | }, |
4599 | ||
592a252b | 4600 | /* PREFIX_VEX_0F2E */ |
7c52e0e8 | 4601 | { |
5b872f7d | 4602 | { "vucomiss", { XMScalar, EXxmm_md }, 0 }, |
592d1631 | 4603 | { Bad_Opcode }, |
5b872f7d | 4604 | { "vucomisd", { XMScalar, EXxmm_mq }, 0 }, |
7c52e0e8 L |
4605 | }, |
4606 | ||
592a252b | 4607 | /* PREFIX_VEX_0F2F */ |
7c52e0e8 | 4608 | { |
5b872f7d | 4609 | { "vcomiss", { XMScalar, EXxmm_md }, 0 }, |
592d1631 | 4610 | { Bad_Opcode }, |
5b872f7d | 4611 | { "vcomisd", { XMScalar, EXxmm_mq }, 0 }, |
7c52e0e8 L |
4612 | }, |
4613 | ||
43234a1e L |
4614 | /* PREFIX_VEX_0F41 */ |
4615 | { | |
4616 | { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) }, | |
1ba585e8 IT |
4617 | { Bad_Opcode }, |
4618 | { VEX_LEN_TABLE (VEX_LEN_0F41_P_2) }, | |
43234a1e L |
4619 | }, |
4620 | ||
4621 | /* PREFIX_VEX_0F42 */ | |
4622 | { | |
4623 | { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) }, | |
1ba585e8 IT |
4624 | { Bad_Opcode }, |
4625 | { VEX_LEN_TABLE (VEX_LEN_0F42_P_2) }, | |
43234a1e L |
4626 | }, |
4627 | ||
4628 | /* PREFIX_VEX_0F44 */ | |
4629 | { | |
4630 | { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) }, | |
1ba585e8 IT |
4631 | { Bad_Opcode }, |
4632 | { VEX_LEN_TABLE (VEX_LEN_0F44_P_2) }, | |
43234a1e L |
4633 | }, |
4634 | ||
4635 | /* PREFIX_VEX_0F45 */ | |
4636 | { | |
4637 | { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) }, | |
1ba585e8 IT |
4638 | { Bad_Opcode }, |
4639 | { VEX_LEN_TABLE (VEX_LEN_0F45_P_2) }, | |
43234a1e L |
4640 | }, |
4641 | ||
4642 | /* PREFIX_VEX_0F46 */ | |
4643 | { | |
4644 | { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) }, | |
1ba585e8 IT |
4645 | { Bad_Opcode }, |
4646 | { VEX_LEN_TABLE (VEX_LEN_0F46_P_2) }, | |
43234a1e L |
4647 | }, |
4648 | ||
4649 | /* PREFIX_VEX_0F47 */ | |
4650 | { | |
4651 | { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) }, | |
1ba585e8 IT |
4652 | { Bad_Opcode }, |
4653 | { VEX_LEN_TABLE (VEX_LEN_0F47_P_2) }, | |
43234a1e L |
4654 | }, |
4655 | ||
1ba585e8 | 4656 | /* PREFIX_VEX_0F4A */ |
43234a1e | 4657 | { |
1ba585e8 | 4658 | { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0) }, |
43234a1e | 4659 | { Bad_Opcode }, |
1ba585e8 IT |
4660 | { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2) }, |
4661 | }, | |
4662 | ||
4663 | /* PREFIX_VEX_0F4B */ | |
4664 | { | |
4665 | { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0) }, | |
43234a1e L |
4666 | { Bad_Opcode }, |
4667 | { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) }, | |
4668 | }, | |
4669 | ||
592a252b | 4670 | /* PREFIX_VEX_0F51 */ |
7c52e0e8 | 4671 | { |
ec6f095a | 4672 | { "vsqrtps", { XM, EXx }, 0 }, |
5b872f7d | 4673 | { "vsqrtss", { XMScalar, VexScalar, EXxmm_md }, 0 }, |
ec6f095a | 4674 | { "vsqrtpd", { XM, EXx }, 0 }, |
5b872f7d | 4675 | { "vsqrtsd", { XMScalar, VexScalar, EXxmm_mq }, 0 }, |
7c52e0e8 L |
4676 | }, |
4677 | ||
592a252b | 4678 | /* PREFIX_VEX_0F52 */ |
7c52e0e8 | 4679 | { |
ec6f095a | 4680 | { "vrsqrtps", { XM, EXx }, 0 }, |
5b872f7d | 4681 | { "vrsqrtss", { XMScalar, VexScalar, EXxmm_md }, 0 }, |
7c52e0e8 L |
4682 | }, |
4683 | ||
592a252b | 4684 | /* PREFIX_VEX_0F53 */ |
7c52e0e8 | 4685 | { |
ec6f095a | 4686 | { "vrcpps", { XM, EXx }, 0 }, |
5b872f7d | 4687 | { "vrcpss", { XMScalar, VexScalar, EXxmm_md }, 0 }, |
7c52e0e8 L |
4688 | }, |
4689 | ||
592a252b | 4690 | /* PREFIX_VEX_0F58 */ |
7c52e0e8 | 4691 | { |
ec6f095a | 4692 | { "vaddps", { XM, Vex, EXx }, 0 }, |
5b872f7d | 4693 | { "vaddss", { XMScalar, VexScalar, EXxmm_md }, 0 }, |
ec6f095a | 4694 | { "vaddpd", { XM, Vex, EXx }, 0 }, |
5b872f7d | 4695 | { "vaddsd", { XMScalar, VexScalar, EXxmm_mq }, 0 }, |
7c52e0e8 L |
4696 | }, |
4697 | ||
592a252b | 4698 | /* PREFIX_VEX_0F59 */ |
7c52e0e8 | 4699 | { |
ec6f095a | 4700 | { "vmulps", { XM, Vex, EXx }, 0 }, |
5b872f7d | 4701 | { "vmulss", { XMScalar, VexScalar, EXxmm_md }, 0 }, |
ec6f095a | 4702 | { "vmulpd", { XM, Vex, EXx }, 0 }, |
5b872f7d | 4703 | { "vmulsd", { XMScalar, VexScalar, EXxmm_mq }, 0 }, |
7c52e0e8 L |
4704 | }, |
4705 | ||
592a252b | 4706 | /* PREFIX_VEX_0F5A */ |
7c52e0e8 | 4707 | { |
ec6f095a | 4708 | { "vcvtps2pd", { XM, EXxmmq }, 0 }, |
5b872f7d | 4709 | { "vcvtss2sd", { XMScalar, VexScalar, EXxmm_md }, 0 }, |
ec6f095a | 4710 | { "vcvtpd2ps%XY",{ XMM, EXx }, 0 }, |
5b872f7d | 4711 | { "vcvtsd2ss", { XMScalar, VexScalar, EXxmm_mq }, 0 }, |
7c52e0e8 L |
4712 | }, |
4713 | ||
592a252b | 4714 | /* PREFIX_VEX_0F5B */ |
7c52e0e8 | 4715 | { |
ec6f095a L |
4716 | { "vcvtdq2ps", { XM, EXx }, 0 }, |
4717 | { "vcvttps2dq", { XM, EXx }, 0 }, | |
4718 | { "vcvtps2dq", { XM, EXx }, 0 }, | |
7c52e0e8 L |
4719 | }, |
4720 | ||
592a252b | 4721 | /* PREFIX_VEX_0F5C */ |
7c52e0e8 | 4722 | { |
ec6f095a | 4723 | { "vsubps", { XM, Vex, EXx }, 0 }, |
5b872f7d | 4724 | { "vsubss", { XMScalar, VexScalar, EXxmm_md }, 0 }, |
ec6f095a | 4725 | { "vsubpd", { XM, Vex, EXx }, 0 }, |
5b872f7d | 4726 | { "vsubsd", { XMScalar, VexScalar, EXxmm_mq }, 0 }, |
7c52e0e8 L |
4727 | }, |
4728 | ||
592a252b | 4729 | /* PREFIX_VEX_0F5D */ |
7c52e0e8 | 4730 | { |
ec6f095a | 4731 | { "vminps", { XM, Vex, EXx }, 0 }, |
5b872f7d | 4732 | { "vminss", { XMScalar, VexScalar, EXxmm_md }, 0 }, |
ec6f095a | 4733 | { "vminpd", { XM, Vex, EXx }, 0 }, |
5b872f7d | 4734 | { "vminsd", { XMScalar, VexScalar, EXxmm_mq }, 0 }, |
7c52e0e8 L |
4735 | }, |
4736 | ||
592a252b | 4737 | /* PREFIX_VEX_0F5E */ |
7c52e0e8 | 4738 | { |
ec6f095a | 4739 | { "vdivps", { XM, Vex, EXx }, 0 }, |
5b872f7d | 4740 | { "vdivss", { XMScalar, VexScalar, EXxmm_md }, 0 }, |
ec6f095a | 4741 | { "vdivpd", { XM, Vex, EXx }, 0 }, |
5b872f7d | 4742 | { "vdivsd", { XMScalar, VexScalar, EXxmm_mq }, 0 }, |
7c52e0e8 L |
4743 | }, |
4744 | ||
592a252b | 4745 | /* PREFIX_VEX_0F5F */ |
7c52e0e8 | 4746 | { |
ec6f095a | 4747 | { "vmaxps", { XM, Vex, EXx }, 0 }, |
5b872f7d | 4748 | { "vmaxss", { XMScalar, VexScalar, EXxmm_md }, 0 }, |
ec6f095a | 4749 | { "vmaxpd", { XM, Vex, EXx }, 0 }, |
5b872f7d | 4750 | { "vmaxsd", { XMScalar, VexScalar, EXxmm_mq }, 0 }, |
7c52e0e8 L |
4751 | }, |
4752 | ||
592a252b | 4753 | /* PREFIX_VEX_0F60 */ |
7c52e0e8 | 4754 | { |
592d1631 L |
4755 | { Bad_Opcode }, |
4756 | { Bad_Opcode }, | |
ec6f095a | 4757 | { "vpunpcklbw", { XM, Vex, EXx }, 0 }, |
7c52e0e8 L |
4758 | }, |
4759 | ||
592a252b | 4760 | /* PREFIX_VEX_0F61 */ |
7c52e0e8 | 4761 | { |
592d1631 L |
4762 | { Bad_Opcode }, |
4763 | { Bad_Opcode }, | |
ec6f095a | 4764 | { "vpunpcklwd", { XM, Vex, EXx }, 0 }, |
7c52e0e8 L |
4765 | }, |
4766 | ||
592a252b | 4767 | /* PREFIX_VEX_0F62 */ |
7c52e0e8 | 4768 | { |
592d1631 L |
4769 | { Bad_Opcode }, |
4770 | { Bad_Opcode }, | |
ec6f095a | 4771 | { "vpunpckldq", { XM, Vex, EXx }, 0 }, |
7c52e0e8 L |
4772 | }, |
4773 | ||
592a252b | 4774 | /* PREFIX_VEX_0F63 */ |
7c52e0e8 | 4775 | { |
592d1631 L |
4776 | { Bad_Opcode }, |
4777 | { Bad_Opcode }, | |
ec6f095a | 4778 | { "vpacksswb", { XM, Vex, EXx }, 0 }, |
7c52e0e8 L |
4779 | }, |
4780 | ||
592a252b | 4781 | /* PREFIX_VEX_0F64 */ |
7c52e0e8 | 4782 | { |
592d1631 L |
4783 | { Bad_Opcode }, |
4784 | { Bad_Opcode }, | |
ec6f095a | 4785 | { "vpcmpgtb", { XM, Vex, EXx }, 0 }, |
7c52e0e8 L |
4786 | }, |
4787 | ||
592a252b | 4788 | /* PREFIX_VEX_0F65 */ |
7c52e0e8 | 4789 | { |
592d1631 L |
4790 | { Bad_Opcode }, |
4791 | { Bad_Opcode }, | |
ec6f095a | 4792 | { "vpcmpgtw", { XM, Vex, EXx }, 0 }, |
7c52e0e8 L |
4793 | }, |
4794 | ||
592a252b | 4795 | /* PREFIX_VEX_0F66 */ |
7c52e0e8 | 4796 | { |
592d1631 L |
4797 | { Bad_Opcode }, |
4798 | { Bad_Opcode }, | |
ec6f095a | 4799 | { "vpcmpgtd", { XM, Vex, EXx }, 0 }, |
7c52e0e8 | 4800 | }, |
6439fc28 | 4801 | |
592a252b | 4802 | /* PREFIX_VEX_0F67 */ |
331d2d0d | 4803 | { |
592d1631 L |
4804 | { Bad_Opcode }, |
4805 | { Bad_Opcode }, | |
ec6f095a | 4806 | { "vpackuswb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
4807 | }, |
4808 | ||
592a252b | 4809 | /* PREFIX_VEX_0F68 */ |
c0f3af97 | 4810 | { |
592d1631 L |
4811 | { Bad_Opcode }, |
4812 | { Bad_Opcode }, | |
ec6f095a | 4813 | { "vpunpckhbw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
4814 | }, |
4815 | ||
592a252b | 4816 | /* PREFIX_VEX_0F69 */ |
c0f3af97 | 4817 | { |
592d1631 L |
4818 | { Bad_Opcode }, |
4819 | { Bad_Opcode }, | |
ec6f095a | 4820 | { "vpunpckhwd", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
4821 | }, |
4822 | ||
592a252b | 4823 | /* PREFIX_VEX_0F6A */ |
c0f3af97 | 4824 | { |
592d1631 L |
4825 | { Bad_Opcode }, |
4826 | { Bad_Opcode }, | |
ec6f095a | 4827 | { "vpunpckhdq", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
4828 | }, |
4829 | ||
592a252b | 4830 | /* PREFIX_VEX_0F6B */ |
c0f3af97 | 4831 | { |
592d1631 L |
4832 | { Bad_Opcode }, |
4833 | { Bad_Opcode }, | |
ec6f095a | 4834 | { "vpackssdw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
4835 | }, |
4836 | ||
592a252b | 4837 | /* PREFIX_VEX_0F6C */ |
c0f3af97 | 4838 | { |
592d1631 L |
4839 | { Bad_Opcode }, |
4840 | { Bad_Opcode }, | |
ec6f095a | 4841 | { "vpunpcklqdq", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
4842 | }, |
4843 | ||
592a252b | 4844 | /* PREFIX_VEX_0F6D */ |
c0f3af97 | 4845 | { |
592d1631 L |
4846 | { Bad_Opcode }, |
4847 | { Bad_Opcode }, | |
ec6f095a | 4848 | { "vpunpckhqdq", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
4849 | }, |
4850 | ||
592a252b | 4851 | /* PREFIX_VEX_0F6E */ |
c0f3af97 | 4852 | { |
592d1631 L |
4853 | { Bad_Opcode }, |
4854 | { Bad_Opcode }, | |
592a252b | 4855 | { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) }, |
c0f3af97 L |
4856 | }, |
4857 | ||
592a252b | 4858 | /* PREFIX_VEX_0F6F */ |
c0f3af97 | 4859 | { |
592d1631 | 4860 | { Bad_Opcode }, |
ec6f095a L |
4861 | { "vmovdqu", { XM, EXx }, 0 }, |
4862 | { "vmovdqa", { XM, EXx }, 0 }, | |
c0f3af97 L |
4863 | }, |
4864 | ||
592a252b | 4865 | /* PREFIX_VEX_0F70 */ |
c0f3af97 | 4866 | { |
592d1631 | 4867 | { Bad_Opcode }, |
ec6f095a L |
4868 | { "vpshufhw", { XM, EXx, Ib }, 0 }, |
4869 | { "vpshufd", { XM, EXx, Ib }, 0 }, | |
4870 | { "vpshuflw", { XM, EXx, Ib }, 0 }, | |
c0f3af97 L |
4871 | }, |
4872 | ||
592a252b | 4873 | /* PREFIX_VEX_0F71_REG_2 */ |
c0f3af97 | 4874 | { |
592d1631 L |
4875 | { Bad_Opcode }, |
4876 | { Bad_Opcode }, | |
ec6f095a | 4877 | { "vpsrlw", { Vex, XS, Ib }, 0 }, |
c0f3af97 L |
4878 | }, |
4879 | ||
592a252b | 4880 | /* PREFIX_VEX_0F71_REG_4 */ |
c0f3af97 | 4881 | { |
592d1631 L |
4882 | { Bad_Opcode }, |
4883 | { Bad_Opcode }, | |
ec6f095a | 4884 | { "vpsraw", { Vex, XS, Ib }, 0 }, |
c0f3af97 L |
4885 | }, |
4886 | ||
592a252b | 4887 | /* PREFIX_VEX_0F71_REG_6 */ |
c0f3af97 | 4888 | { |
592d1631 L |
4889 | { Bad_Opcode }, |
4890 | { Bad_Opcode }, | |
ec6f095a | 4891 | { "vpsllw", { Vex, XS, Ib }, 0 }, |
c0f3af97 L |
4892 | }, |
4893 | ||
592a252b | 4894 | /* PREFIX_VEX_0F72_REG_2 */ |
c0f3af97 | 4895 | { |
592d1631 L |
4896 | { Bad_Opcode }, |
4897 | { Bad_Opcode }, | |
ec6f095a | 4898 | { "vpsrld", { Vex, XS, Ib }, 0 }, |
c0f3af97 L |
4899 | }, |
4900 | ||
592a252b | 4901 | /* PREFIX_VEX_0F72_REG_4 */ |
c0f3af97 | 4902 | { |
592d1631 L |
4903 | { Bad_Opcode }, |
4904 | { Bad_Opcode }, | |
ec6f095a | 4905 | { "vpsrad", { Vex, XS, Ib }, 0 }, |
c0f3af97 L |
4906 | }, |
4907 | ||
592a252b | 4908 | /* PREFIX_VEX_0F72_REG_6 */ |
c0f3af97 | 4909 | { |
592d1631 L |
4910 | { Bad_Opcode }, |
4911 | { Bad_Opcode }, | |
ec6f095a | 4912 | { "vpslld", { Vex, XS, Ib }, 0 }, |
c0f3af97 L |
4913 | }, |
4914 | ||
592a252b | 4915 | /* PREFIX_VEX_0F73_REG_2 */ |
c0f3af97 | 4916 | { |
592d1631 L |
4917 | { Bad_Opcode }, |
4918 | { Bad_Opcode }, | |
ec6f095a | 4919 | { "vpsrlq", { Vex, XS, Ib }, 0 }, |
c0f3af97 L |
4920 | }, |
4921 | ||
592a252b | 4922 | /* PREFIX_VEX_0F73_REG_3 */ |
c0f3af97 | 4923 | { |
592d1631 L |
4924 | { Bad_Opcode }, |
4925 | { Bad_Opcode }, | |
ec6f095a | 4926 | { "vpsrldq", { Vex, XS, Ib }, 0 }, |
c0f3af97 L |
4927 | }, |
4928 | ||
592a252b | 4929 | /* PREFIX_VEX_0F73_REG_6 */ |
c0f3af97 | 4930 | { |
592d1631 L |
4931 | { Bad_Opcode }, |
4932 | { Bad_Opcode }, | |
ec6f095a | 4933 | { "vpsllq", { Vex, XS, Ib }, 0 }, |
c0f3af97 L |
4934 | }, |
4935 | ||
592a252b | 4936 | /* PREFIX_VEX_0F73_REG_7 */ |
c0f3af97 | 4937 | { |
592d1631 L |
4938 | { Bad_Opcode }, |
4939 | { Bad_Opcode }, | |
ec6f095a | 4940 | { "vpslldq", { Vex, XS, Ib }, 0 }, |
c0f3af97 L |
4941 | }, |
4942 | ||
592a252b | 4943 | /* PREFIX_VEX_0F74 */ |
c0f3af97 | 4944 | { |
592d1631 L |
4945 | { Bad_Opcode }, |
4946 | { Bad_Opcode }, | |
ec6f095a | 4947 | { "vpcmpeqb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
4948 | }, |
4949 | ||
592a252b | 4950 | /* PREFIX_VEX_0F75 */ |
c0f3af97 | 4951 | { |
592d1631 L |
4952 | { Bad_Opcode }, |
4953 | { Bad_Opcode }, | |
ec6f095a | 4954 | { "vpcmpeqw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
4955 | }, |
4956 | ||
592a252b | 4957 | /* PREFIX_VEX_0F76 */ |
c0f3af97 | 4958 | { |
592d1631 L |
4959 | { Bad_Opcode }, |
4960 | { Bad_Opcode }, | |
ec6f095a | 4961 | { "vpcmpeqd", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
4962 | }, |
4963 | ||
592a252b | 4964 | /* PREFIX_VEX_0F77 */ |
c0f3af97 | 4965 | { |
ec6f095a | 4966 | { VEX_LEN_TABLE (VEX_LEN_0F77_P_0) }, |
c0f3af97 L |
4967 | }, |
4968 | ||
592a252b | 4969 | /* PREFIX_VEX_0F7C */ |
c0f3af97 | 4970 | { |
592d1631 L |
4971 | { Bad_Opcode }, |
4972 | { Bad_Opcode }, | |
ec6f095a L |
4973 | { "vhaddpd", { XM, Vex, EXx }, 0 }, |
4974 | { "vhaddps", { XM, Vex, EXx }, 0 }, | |
c0f3af97 L |
4975 | }, |
4976 | ||
592a252b | 4977 | /* PREFIX_VEX_0F7D */ |
c0f3af97 | 4978 | { |
592d1631 L |
4979 | { Bad_Opcode }, |
4980 | { Bad_Opcode }, | |
ec6f095a L |
4981 | { "vhsubpd", { XM, Vex, EXx }, 0 }, |
4982 | { "vhsubps", { XM, Vex, EXx }, 0 }, | |
c0f3af97 L |
4983 | }, |
4984 | ||
592a252b | 4985 | /* PREFIX_VEX_0F7E */ |
c0f3af97 | 4986 | { |
592d1631 | 4987 | { Bad_Opcode }, |
592a252b L |
4988 | { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) }, |
4989 | { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) }, | |
c0f3af97 L |
4990 | }, |
4991 | ||
592a252b | 4992 | /* PREFIX_VEX_0F7F */ |
c0f3af97 | 4993 | { |
592d1631 | 4994 | { Bad_Opcode }, |
ec6f095a L |
4995 | { "vmovdqu", { EXxS, XM }, 0 }, |
4996 | { "vmovdqa", { EXxS, XM }, 0 }, | |
c0f3af97 L |
4997 | }, |
4998 | ||
43234a1e L |
4999 | /* PREFIX_VEX_0F90 */ |
5000 | { | |
5001 | { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) }, | |
1ba585e8 IT |
5002 | { Bad_Opcode }, |
5003 | { VEX_LEN_TABLE (VEX_LEN_0F90_P_2) }, | |
43234a1e L |
5004 | }, |
5005 | ||
5006 | /* PREFIX_VEX_0F91 */ | |
5007 | { | |
5008 | { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) }, | |
1ba585e8 IT |
5009 | { Bad_Opcode }, |
5010 | { VEX_LEN_TABLE (VEX_LEN_0F91_P_2) }, | |
43234a1e L |
5011 | }, |
5012 | ||
5013 | /* PREFIX_VEX_0F92 */ | |
5014 | { | |
5015 | { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) }, | |
1ba585e8 | 5016 | { Bad_Opcode }, |
90a915bf | 5017 | { VEX_LEN_TABLE (VEX_LEN_0F92_P_2) }, |
1ba585e8 | 5018 | { VEX_LEN_TABLE (VEX_LEN_0F92_P_3) }, |
43234a1e L |
5019 | }, |
5020 | ||
5021 | /* PREFIX_VEX_0F93 */ | |
5022 | { | |
5023 | { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) }, | |
1ba585e8 | 5024 | { Bad_Opcode }, |
90a915bf | 5025 | { VEX_LEN_TABLE (VEX_LEN_0F93_P_2) }, |
1ba585e8 | 5026 | { VEX_LEN_TABLE (VEX_LEN_0F93_P_3) }, |
43234a1e L |
5027 | }, |
5028 | ||
5029 | /* PREFIX_VEX_0F98 */ | |
5030 | { | |
5031 | { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) }, | |
1ba585e8 IT |
5032 | { Bad_Opcode }, |
5033 | { VEX_LEN_TABLE (VEX_LEN_0F98_P_2) }, | |
5034 | }, | |
5035 | ||
5036 | /* PREFIX_VEX_0F99 */ | |
5037 | { | |
5038 | { VEX_LEN_TABLE (VEX_LEN_0F99_P_0) }, | |
5039 | { Bad_Opcode }, | |
5040 | { VEX_LEN_TABLE (VEX_LEN_0F99_P_2) }, | |
43234a1e L |
5041 | }, |
5042 | ||
592a252b | 5043 | /* PREFIX_VEX_0FC2 */ |
c0f3af97 | 5044 | { |
ec6f095a | 5045 | { "vcmpps", { XM, Vex, EXx, VCMP }, 0 }, |
5b872f7d | 5046 | { "vcmpss", { XMScalar, VexScalar, EXxmm_md, VCMP }, 0 }, |
ec6f095a | 5047 | { "vcmppd", { XM, Vex, EXx, VCMP }, 0 }, |
5b872f7d | 5048 | { "vcmpsd", { XMScalar, VexScalar, EXxmm_mq, VCMP }, 0 }, |
c0f3af97 L |
5049 | }, |
5050 | ||
592a252b | 5051 | /* PREFIX_VEX_0FC4 */ |
c0f3af97 | 5052 | { |
592d1631 L |
5053 | { Bad_Opcode }, |
5054 | { Bad_Opcode }, | |
592a252b | 5055 | { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) }, |
c0f3af97 L |
5056 | }, |
5057 | ||
592a252b | 5058 | /* PREFIX_VEX_0FC5 */ |
c0f3af97 | 5059 | { |
592d1631 L |
5060 | { Bad_Opcode }, |
5061 | { Bad_Opcode }, | |
592a252b | 5062 | { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) }, |
c0f3af97 L |
5063 | }, |
5064 | ||
592a252b | 5065 | /* PREFIX_VEX_0FD0 */ |
c0f3af97 | 5066 | { |
592d1631 L |
5067 | { Bad_Opcode }, |
5068 | { Bad_Opcode }, | |
ec6f095a L |
5069 | { "vaddsubpd", { XM, Vex, EXx }, 0 }, |
5070 | { "vaddsubps", { XM, Vex, EXx }, 0 }, | |
c0f3af97 L |
5071 | }, |
5072 | ||
592a252b | 5073 | /* PREFIX_VEX_0FD1 */ |
c0f3af97 | 5074 | { |
592d1631 L |
5075 | { Bad_Opcode }, |
5076 | { Bad_Opcode }, | |
ec6f095a | 5077 | { "vpsrlw", { XM, Vex, EXxmm }, 0 }, |
c0f3af97 L |
5078 | }, |
5079 | ||
592a252b | 5080 | /* PREFIX_VEX_0FD2 */ |
c0f3af97 | 5081 | { |
592d1631 L |
5082 | { Bad_Opcode }, |
5083 | { Bad_Opcode }, | |
ec6f095a | 5084 | { "vpsrld", { XM, Vex, EXxmm }, 0 }, |
c0f3af97 L |
5085 | }, |
5086 | ||
592a252b | 5087 | /* PREFIX_VEX_0FD3 */ |
c0f3af97 | 5088 | { |
592d1631 L |
5089 | { Bad_Opcode }, |
5090 | { Bad_Opcode }, | |
ec6f095a | 5091 | { "vpsrlq", { XM, Vex, EXxmm }, 0 }, |
c0f3af97 L |
5092 | }, |
5093 | ||
592a252b | 5094 | /* PREFIX_VEX_0FD4 */ |
c0f3af97 | 5095 | { |
592d1631 L |
5096 | { Bad_Opcode }, |
5097 | { Bad_Opcode }, | |
ec6f095a | 5098 | { "vpaddq", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5099 | }, |
5100 | ||
592a252b | 5101 | /* PREFIX_VEX_0FD5 */ |
c0f3af97 | 5102 | { |
592d1631 L |
5103 | { Bad_Opcode }, |
5104 | { Bad_Opcode }, | |
ec6f095a | 5105 | { "vpmullw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5106 | }, |
5107 | ||
592a252b | 5108 | /* PREFIX_VEX_0FD6 */ |
c0f3af97 | 5109 | { |
592d1631 L |
5110 | { Bad_Opcode }, |
5111 | { Bad_Opcode }, | |
592a252b | 5112 | { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) }, |
c0f3af97 L |
5113 | }, |
5114 | ||
592a252b | 5115 | /* PREFIX_VEX_0FD7 */ |
c0f3af97 | 5116 | { |
592d1631 L |
5117 | { Bad_Opcode }, |
5118 | { Bad_Opcode }, | |
592a252b | 5119 | { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) }, |
c0f3af97 L |
5120 | }, |
5121 | ||
592a252b | 5122 | /* PREFIX_VEX_0FD8 */ |
c0f3af97 | 5123 | { |
592d1631 L |
5124 | { Bad_Opcode }, |
5125 | { Bad_Opcode }, | |
ec6f095a | 5126 | { "vpsubusb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5127 | }, |
5128 | ||
592a252b | 5129 | /* PREFIX_VEX_0FD9 */ |
c0f3af97 | 5130 | { |
592d1631 L |
5131 | { Bad_Opcode }, |
5132 | { Bad_Opcode }, | |
ec6f095a | 5133 | { "vpsubusw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5134 | }, |
5135 | ||
592a252b | 5136 | /* PREFIX_VEX_0FDA */ |
c0f3af97 | 5137 | { |
592d1631 L |
5138 | { Bad_Opcode }, |
5139 | { Bad_Opcode }, | |
ec6f095a | 5140 | { "vpminub", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5141 | }, |
5142 | ||
592a252b | 5143 | /* PREFIX_VEX_0FDB */ |
c0f3af97 | 5144 | { |
592d1631 L |
5145 | { Bad_Opcode }, |
5146 | { Bad_Opcode }, | |
ec6f095a | 5147 | { "vpand", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5148 | }, |
5149 | ||
592a252b | 5150 | /* PREFIX_VEX_0FDC */ |
c0f3af97 | 5151 | { |
592d1631 L |
5152 | { Bad_Opcode }, |
5153 | { Bad_Opcode }, | |
ec6f095a | 5154 | { "vpaddusb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5155 | }, |
5156 | ||
592a252b | 5157 | /* PREFIX_VEX_0FDD */ |
c0f3af97 | 5158 | { |
592d1631 L |
5159 | { Bad_Opcode }, |
5160 | { Bad_Opcode }, | |
ec6f095a | 5161 | { "vpaddusw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5162 | }, |
5163 | ||
592a252b | 5164 | /* PREFIX_VEX_0FDE */ |
c0f3af97 | 5165 | { |
592d1631 L |
5166 | { Bad_Opcode }, |
5167 | { Bad_Opcode }, | |
ec6f095a | 5168 | { "vpmaxub", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5169 | }, |
5170 | ||
592a252b | 5171 | /* PREFIX_VEX_0FDF */ |
c0f3af97 | 5172 | { |
592d1631 L |
5173 | { Bad_Opcode }, |
5174 | { Bad_Opcode }, | |
ec6f095a | 5175 | { "vpandn", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5176 | }, |
5177 | ||
592a252b | 5178 | /* PREFIX_VEX_0FE0 */ |
c0f3af97 | 5179 | { |
592d1631 L |
5180 | { Bad_Opcode }, |
5181 | { Bad_Opcode }, | |
ec6f095a | 5182 | { "vpavgb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5183 | }, |
5184 | ||
592a252b | 5185 | /* PREFIX_VEX_0FE1 */ |
c0f3af97 | 5186 | { |
592d1631 L |
5187 | { Bad_Opcode }, |
5188 | { Bad_Opcode }, | |
ec6f095a | 5189 | { "vpsraw", { XM, Vex, EXxmm }, 0 }, |
c0f3af97 L |
5190 | }, |
5191 | ||
592a252b | 5192 | /* PREFIX_VEX_0FE2 */ |
c0f3af97 | 5193 | { |
592d1631 L |
5194 | { Bad_Opcode }, |
5195 | { Bad_Opcode }, | |
ec6f095a | 5196 | { "vpsrad", { XM, Vex, EXxmm }, 0 }, |
c0f3af97 L |
5197 | }, |
5198 | ||
592a252b | 5199 | /* PREFIX_VEX_0FE3 */ |
c0f3af97 | 5200 | { |
592d1631 L |
5201 | { Bad_Opcode }, |
5202 | { Bad_Opcode }, | |
ec6f095a | 5203 | { "vpavgw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5204 | }, |
5205 | ||
592a252b | 5206 | /* PREFIX_VEX_0FE4 */ |
c0f3af97 | 5207 | { |
592d1631 L |
5208 | { Bad_Opcode }, |
5209 | { Bad_Opcode }, | |
ec6f095a | 5210 | { "vpmulhuw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5211 | }, |
5212 | ||
592a252b | 5213 | /* PREFIX_VEX_0FE5 */ |
c0f3af97 | 5214 | { |
592d1631 L |
5215 | { Bad_Opcode }, |
5216 | { Bad_Opcode }, | |
ec6f095a | 5217 | { "vpmulhw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5218 | }, |
5219 | ||
592a252b | 5220 | /* PREFIX_VEX_0FE6 */ |
c0f3af97 | 5221 | { |
592d1631 | 5222 | { Bad_Opcode }, |
ec6f095a L |
5223 | { "vcvtdq2pd", { XM, EXxmmq }, 0 }, |
5224 | { "vcvttpd2dq%XY", { XMM, EXx }, 0 }, | |
5225 | { "vcvtpd2dq%XY", { XMM, EXx }, 0 }, | |
c0f3af97 L |
5226 | }, |
5227 | ||
592a252b | 5228 | /* PREFIX_VEX_0FE7 */ |
c0f3af97 | 5229 | { |
592d1631 L |
5230 | { Bad_Opcode }, |
5231 | { Bad_Opcode }, | |
592a252b | 5232 | { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) }, |
c0f3af97 L |
5233 | }, |
5234 | ||
592a252b | 5235 | /* PREFIX_VEX_0FE8 */ |
c0f3af97 | 5236 | { |
592d1631 L |
5237 | { Bad_Opcode }, |
5238 | { Bad_Opcode }, | |
ec6f095a | 5239 | { "vpsubsb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5240 | }, |
5241 | ||
592a252b | 5242 | /* PREFIX_VEX_0FE9 */ |
c0f3af97 | 5243 | { |
592d1631 L |
5244 | { Bad_Opcode }, |
5245 | { Bad_Opcode }, | |
ec6f095a | 5246 | { "vpsubsw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5247 | }, |
5248 | ||
592a252b | 5249 | /* PREFIX_VEX_0FEA */ |
c0f3af97 | 5250 | { |
592d1631 L |
5251 | { Bad_Opcode }, |
5252 | { Bad_Opcode }, | |
ec6f095a | 5253 | { "vpminsw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5254 | }, |
5255 | ||
592a252b | 5256 | /* PREFIX_VEX_0FEB */ |
c0f3af97 | 5257 | { |
592d1631 L |
5258 | { Bad_Opcode }, |
5259 | { Bad_Opcode }, | |
ec6f095a | 5260 | { "vpor", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5261 | }, |
5262 | ||
592a252b | 5263 | /* PREFIX_VEX_0FEC */ |
c0f3af97 | 5264 | { |
592d1631 L |
5265 | { Bad_Opcode }, |
5266 | { Bad_Opcode }, | |
ec6f095a | 5267 | { "vpaddsb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5268 | }, |
5269 | ||
592a252b | 5270 | /* PREFIX_VEX_0FED */ |
c0f3af97 | 5271 | { |
592d1631 L |
5272 | { Bad_Opcode }, |
5273 | { Bad_Opcode }, | |
ec6f095a | 5274 | { "vpaddsw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5275 | }, |
5276 | ||
592a252b | 5277 | /* PREFIX_VEX_0FEE */ |
c0f3af97 | 5278 | { |
592d1631 L |
5279 | { Bad_Opcode }, |
5280 | { Bad_Opcode }, | |
ec6f095a | 5281 | { "vpmaxsw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5282 | }, |
5283 | ||
592a252b | 5284 | /* PREFIX_VEX_0FEF */ |
c0f3af97 | 5285 | { |
592d1631 L |
5286 | { Bad_Opcode }, |
5287 | { Bad_Opcode }, | |
ec6f095a | 5288 | { "vpxor", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5289 | }, |
5290 | ||
592a252b | 5291 | /* PREFIX_VEX_0FF0 */ |
c0f3af97 | 5292 | { |
592d1631 L |
5293 | { Bad_Opcode }, |
5294 | { Bad_Opcode }, | |
5295 | { Bad_Opcode }, | |
592a252b | 5296 | { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) }, |
c0f3af97 L |
5297 | }, |
5298 | ||
592a252b | 5299 | /* PREFIX_VEX_0FF1 */ |
c0f3af97 | 5300 | { |
592d1631 L |
5301 | { Bad_Opcode }, |
5302 | { Bad_Opcode }, | |
ec6f095a | 5303 | { "vpsllw", { XM, Vex, EXxmm }, 0 }, |
c0f3af97 L |
5304 | }, |
5305 | ||
592a252b | 5306 | /* PREFIX_VEX_0FF2 */ |
c0f3af97 | 5307 | { |
592d1631 L |
5308 | { Bad_Opcode }, |
5309 | { Bad_Opcode }, | |
ec6f095a | 5310 | { "vpslld", { XM, Vex, EXxmm }, 0 }, |
c0f3af97 L |
5311 | }, |
5312 | ||
592a252b | 5313 | /* PREFIX_VEX_0FF3 */ |
c0f3af97 | 5314 | { |
592d1631 L |
5315 | { Bad_Opcode }, |
5316 | { Bad_Opcode }, | |
ec6f095a | 5317 | { "vpsllq", { XM, Vex, EXxmm }, 0 }, |
c0f3af97 L |
5318 | }, |
5319 | ||
592a252b | 5320 | /* PREFIX_VEX_0FF4 */ |
c0f3af97 | 5321 | { |
592d1631 L |
5322 | { Bad_Opcode }, |
5323 | { Bad_Opcode }, | |
ec6f095a | 5324 | { "vpmuludq", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5325 | }, |
5326 | ||
592a252b | 5327 | /* PREFIX_VEX_0FF5 */ |
c0f3af97 | 5328 | { |
592d1631 L |
5329 | { Bad_Opcode }, |
5330 | { Bad_Opcode }, | |
ec6f095a | 5331 | { "vpmaddwd", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5332 | }, |
5333 | ||
592a252b | 5334 | /* PREFIX_VEX_0FF6 */ |
c0f3af97 | 5335 | { |
592d1631 L |
5336 | { Bad_Opcode }, |
5337 | { Bad_Opcode }, | |
ec6f095a | 5338 | { "vpsadbw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5339 | }, |
5340 | ||
592a252b | 5341 | /* PREFIX_VEX_0FF7 */ |
c0f3af97 | 5342 | { |
592d1631 L |
5343 | { Bad_Opcode }, |
5344 | { Bad_Opcode }, | |
592a252b | 5345 | { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) }, |
c0f3af97 L |
5346 | }, |
5347 | ||
592a252b | 5348 | /* PREFIX_VEX_0FF8 */ |
c0f3af97 | 5349 | { |
592d1631 L |
5350 | { Bad_Opcode }, |
5351 | { Bad_Opcode }, | |
ec6f095a | 5352 | { "vpsubb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5353 | }, |
5354 | ||
592a252b | 5355 | /* PREFIX_VEX_0FF9 */ |
c0f3af97 | 5356 | { |
592d1631 L |
5357 | { Bad_Opcode }, |
5358 | { Bad_Opcode }, | |
ec6f095a | 5359 | { "vpsubw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5360 | }, |
5361 | ||
592a252b | 5362 | /* PREFIX_VEX_0FFA */ |
c0f3af97 | 5363 | { |
592d1631 L |
5364 | { Bad_Opcode }, |
5365 | { Bad_Opcode }, | |
ec6f095a | 5366 | { "vpsubd", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5367 | }, |
5368 | ||
592a252b | 5369 | /* PREFIX_VEX_0FFB */ |
c0f3af97 | 5370 | { |
592d1631 L |
5371 | { Bad_Opcode }, |
5372 | { Bad_Opcode }, | |
ec6f095a | 5373 | { "vpsubq", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5374 | }, |
5375 | ||
592a252b | 5376 | /* PREFIX_VEX_0FFC */ |
c0f3af97 | 5377 | { |
592d1631 L |
5378 | { Bad_Opcode }, |
5379 | { Bad_Opcode }, | |
ec6f095a | 5380 | { "vpaddb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5381 | }, |
5382 | ||
592a252b | 5383 | /* PREFIX_VEX_0FFD */ |
c0f3af97 | 5384 | { |
592d1631 L |
5385 | { Bad_Opcode }, |
5386 | { Bad_Opcode }, | |
ec6f095a | 5387 | { "vpaddw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5388 | }, |
5389 | ||
592a252b | 5390 | /* PREFIX_VEX_0FFE */ |
c0f3af97 | 5391 | { |
592d1631 L |
5392 | { Bad_Opcode }, |
5393 | { Bad_Opcode }, | |
ec6f095a | 5394 | { "vpaddd", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5395 | }, |
5396 | ||
592a252b | 5397 | /* PREFIX_VEX_0F3800 */ |
c0f3af97 | 5398 | { |
592d1631 L |
5399 | { Bad_Opcode }, |
5400 | { Bad_Opcode }, | |
ec6f095a | 5401 | { "vpshufb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5402 | }, |
5403 | ||
592a252b | 5404 | /* PREFIX_VEX_0F3801 */ |
c0f3af97 | 5405 | { |
592d1631 L |
5406 | { Bad_Opcode }, |
5407 | { Bad_Opcode }, | |
ec6f095a | 5408 | { "vphaddw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5409 | }, |
5410 | ||
592a252b | 5411 | /* PREFIX_VEX_0F3802 */ |
c0f3af97 | 5412 | { |
592d1631 L |
5413 | { Bad_Opcode }, |
5414 | { Bad_Opcode }, | |
ec6f095a | 5415 | { "vphaddd", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5416 | }, |
5417 | ||
592a252b | 5418 | /* PREFIX_VEX_0F3803 */ |
c0f3af97 | 5419 | { |
592d1631 L |
5420 | { Bad_Opcode }, |
5421 | { Bad_Opcode }, | |
ec6f095a | 5422 | { "vphaddsw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5423 | }, |
5424 | ||
592a252b | 5425 | /* PREFIX_VEX_0F3804 */ |
c0f3af97 | 5426 | { |
592d1631 L |
5427 | { Bad_Opcode }, |
5428 | { Bad_Opcode }, | |
ec6f095a | 5429 | { "vpmaddubsw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5430 | }, |
5431 | ||
592a252b | 5432 | /* PREFIX_VEX_0F3805 */ |
c0f3af97 | 5433 | { |
592d1631 L |
5434 | { Bad_Opcode }, |
5435 | { Bad_Opcode }, | |
ec6f095a | 5436 | { "vphsubw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5437 | }, |
5438 | ||
592a252b | 5439 | /* PREFIX_VEX_0F3806 */ |
c0f3af97 | 5440 | { |
592d1631 L |
5441 | { Bad_Opcode }, |
5442 | { Bad_Opcode }, | |
ec6f095a | 5443 | { "vphsubd", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5444 | }, |
5445 | ||
592a252b | 5446 | /* PREFIX_VEX_0F3807 */ |
c0f3af97 | 5447 | { |
592d1631 L |
5448 | { Bad_Opcode }, |
5449 | { Bad_Opcode }, | |
ec6f095a | 5450 | { "vphsubsw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5451 | }, |
5452 | ||
592a252b | 5453 | /* PREFIX_VEX_0F3808 */ |
c0f3af97 | 5454 | { |
592d1631 L |
5455 | { Bad_Opcode }, |
5456 | { Bad_Opcode }, | |
ec6f095a | 5457 | { "vpsignb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5458 | }, |
5459 | ||
592a252b | 5460 | /* PREFIX_VEX_0F3809 */ |
c0f3af97 | 5461 | { |
592d1631 L |
5462 | { Bad_Opcode }, |
5463 | { Bad_Opcode }, | |
ec6f095a | 5464 | { "vpsignw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5465 | }, |
5466 | ||
592a252b | 5467 | /* PREFIX_VEX_0F380A */ |
c0f3af97 | 5468 | { |
592d1631 L |
5469 | { Bad_Opcode }, |
5470 | { Bad_Opcode }, | |
ec6f095a | 5471 | { "vpsignd", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5472 | }, |
5473 | ||
592a252b | 5474 | /* PREFIX_VEX_0F380B */ |
c0f3af97 | 5475 | { |
592d1631 L |
5476 | { Bad_Opcode }, |
5477 | { Bad_Opcode }, | |
ec6f095a | 5478 | { "vpmulhrsw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5479 | }, |
5480 | ||
592a252b | 5481 | /* PREFIX_VEX_0F380C */ |
c0f3af97 | 5482 | { |
592d1631 L |
5483 | { Bad_Opcode }, |
5484 | { Bad_Opcode }, | |
592a252b | 5485 | { VEX_W_TABLE (VEX_W_0F380C_P_2) }, |
c0f3af97 L |
5486 | }, |
5487 | ||
592a252b | 5488 | /* PREFIX_VEX_0F380D */ |
c0f3af97 | 5489 | { |
592d1631 L |
5490 | { Bad_Opcode }, |
5491 | { Bad_Opcode }, | |
592a252b | 5492 | { VEX_W_TABLE (VEX_W_0F380D_P_2) }, |
c0f3af97 L |
5493 | }, |
5494 | ||
592a252b | 5495 | /* PREFIX_VEX_0F380E */ |
c0f3af97 | 5496 | { |
592d1631 L |
5497 | { Bad_Opcode }, |
5498 | { Bad_Opcode }, | |
592a252b | 5499 | { VEX_W_TABLE (VEX_W_0F380E_P_2) }, |
c0f3af97 L |
5500 | }, |
5501 | ||
592a252b | 5502 | /* PREFIX_VEX_0F380F */ |
c0f3af97 | 5503 | { |
592d1631 L |
5504 | { Bad_Opcode }, |
5505 | { Bad_Opcode }, | |
592a252b | 5506 | { VEX_W_TABLE (VEX_W_0F380F_P_2) }, |
c0f3af97 L |
5507 | }, |
5508 | ||
592a252b | 5509 | /* PREFIX_VEX_0F3813 */ |
c7b8aa3a L |
5510 | { |
5511 | { Bad_Opcode }, | |
5512 | { Bad_Opcode }, | |
6431c801 | 5513 | { VEX_W_TABLE (VEX_W_0F3813_P_2) }, |
c7b8aa3a L |
5514 | }, |
5515 | ||
6c30d220 L |
5516 | /* PREFIX_VEX_0F3816 */ |
5517 | { | |
5518 | { Bad_Opcode }, | |
5519 | { Bad_Opcode }, | |
5520 | { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) }, | |
5521 | }, | |
5522 | ||
592a252b | 5523 | /* PREFIX_VEX_0F3817 */ |
c0f3af97 | 5524 | { |
592d1631 L |
5525 | { Bad_Opcode }, |
5526 | { Bad_Opcode }, | |
ec6f095a | 5527 | { "vptest", { XM, EXx }, 0 }, |
c0f3af97 L |
5528 | }, |
5529 | ||
592a252b | 5530 | /* PREFIX_VEX_0F3818 */ |
c0f3af97 | 5531 | { |
592d1631 L |
5532 | { Bad_Opcode }, |
5533 | { Bad_Opcode }, | |
6c30d220 | 5534 | { VEX_W_TABLE (VEX_W_0F3818_P_2) }, |
c0f3af97 L |
5535 | }, |
5536 | ||
592a252b | 5537 | /* PREFIX_VEX_0F3819 */ |
c0f3af97 | 5538 | { |
592d1631 L |
5539 | { Bad_Opcode }, |
5540 | { Bad_Opcode }, | |
6c30d220 | 5541 | { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) }, |
c0f3af97 L |
5542 | }, |
5543 | ||
592a252b | 5544 | /* PREFIX_VEX_0F381A */ |
c0f3af97 | 5545 | { |
592d1631 L |
5546 | { Bad_Opcode }, |
5547 | { Bad_Opcode }, | |
592a252b | 5548 | { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) }, |
c0f3af97 L |
5549 | }, |
5550 | ||
592a252b | 5551 | /* PREFIX_VEX_0F381C */ |
c0f3af97 | 5552 | { |
592d1631 L |
5553 | { Bad_Opcode }, |
5554 | { Bad_Opcode }, | |
ec6f095a | 5555 | { "vpabsb", { XM, EXx }, 0 }, |
c0f3af97 L |
5556 | }, |
5557 | ||
592a252b | 5558 | /* PREFIX_VEX_0F381D */ |
c0f3af97 | 5559 | { |
592d1631 L |
5560 | { Bad_Opcode }, |
5561 | { Bad_Opcode }, | |
ec6f095a | 5562 | { "vpabsw", { XM, EXx }, 0 }, |
c0f3af97 L |
5563 | }, |
5564 | ||
592a252b | 5565 | /* PREFIX_VEX_0F381E */ |
c0f3af97 | 5566 | { |
592d1631 L |
5567 | { Bad_Opcode }, |
5568 | { Bad_Opcode }, | |
ec6f095a | 5569 | { "vpabsd", { XM, EXx }, 0 }, |
c0f3af97 L |
5570 | }, |
5571 | ||
592a252b | 5572 | /* PREFIX_VEX_0F3820 */ |
c0f3af97 | 5573 | { |
592d1631 L |
5574 | { Bad_Opcode }, |
5575 | { Bad_Opcode }, | |
ec6f095a | 5576 | { "vpmovsxbw", { XM, EXxmmq }, 0 }, |
c0f3af97 L |
5577 | }, |
5578 | ||
592a252b | 5579 | /* PREFIX_VEX_0F3821 */ |
c0f3af97 | 5580 | { |
592d1631 L |
5581 | { Bad_Opcode }, |
5582 | { Bad_Opcode }, | |
ec6f095a | 5583 | { "vpmovsxbd", { XM, EXxmmqd }, 0 }, |
c0f3af97 L |
5584 | }, |
5585 | ||
592a252b | 5586 | /* PREFIX_VEX_0F3822 */ |
c0f3af97 | 5587 | { |
592d1631 L |
5588 | { Bad_Opcode }, |
5589 | { Bad_Opcode }, | |
ec6f095a | 5590 | { "vpmovsxbq", { XM, EXxmmdw }, 0 }, |
c0f3af97 L |
5591 | }, |
5592 | ||
592a252b | 5593 | /* PREFIX_VEX_0F3823 */ |
c0f3af97 | 5594 | { |
592d1631 L |
5595 | { Bad_Opcode }, |
5596 | { Bad_Opcode }, | |
ec6f095a | 5597 | { "vpmovsxwd", { XM, EXxmmq }, 0 }, |
c0f3af97 L |
5598 | }, |
5599 | ||
592a252b | 5600 | /* PREFIX_VEX_0F3824 */ |
c0f3af97 | 5601 | { |
592d1631 L |
5602 | { Bad_Opcode }, |
5603 | { Bad_Opcode }, | |
ec6f095a | 5604 | { "vpmovsxwq", { XM, EXxmmqd }, 0 }, |
c0f3af97 L |
5605 | }, |
5606 | ||
592a252b | 5607 | /* PREFIX_VEX_0F3825 */ |
c0f3af97 | 5608 | { |
592d1631 L |
5609 | { Bad_Opcode }, |
5610 | { Bad_Opcode }, | |
ec6f095a | 5611 | { "vpmovsxdq", { XM, EXxmmq }, 0 }, |
c0f3af97 L |
5612 | }, |
5613 | ||
592a252b | 5614 | /* PREFIX_VEX_0F3828 */ |
c0f3af97 | 5615 | { |
592d1631 L |
5616 | { Bad_Opcode }, |
5617 | { Bad_Opcode }, | |
ec6f095a | 5618 | { "vpmuldq", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5619 | }, |
5620 | ||
592a252b | 5621 | /* PREFIX_VEX_0F3829 */ |
c0f3af97 | 5622 | { |
592d1631 L |
5623 | { Bad_Opcode }, |
5624 | { Bad_Opcode }, | |
ec6f095a | 5625 | { "vpcmpeqq", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5626 | }, |
5627 | ||
592a252b | 5628 | /* PREFIX_VEX_0F382A */ |
c0f3af97 | 5629 | { |
592d1631 L |
5630 | { Bad_Opcode }, |
5631 | { Bad_Opcode }, | |
592a252b | 5632 | { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) }, |
c0f3af97 L |
5633 | }, |
5634 | ||
592a252b | 5635 | /* PREFIX_VEX_0F382B */ |
c0f3af97 | 5636 | { |
592d1631 L |
5637 | { Bad_Opcode }, |
5638 | { Bad_Opcode }, | |
ec6f095a | 5639 | { "vpackusdw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5640 | }, |
5641 | ||
592a252b | 5642 | /* PREFIX_VEX_0F382C */ |
c0f3af97 | 5643 | { |
592d1631 L |
5644 | { Bad_Opcode }, |
5645 | { Bad_Opcode }, | |
592a252b | 5646 | { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) }, |
c0f3af97 L |
5647 | }, |
5648 | ||
592a252b | 5649 | /* PREFIX_VEX_0F382D */ |
c0f3af97 | 5650 | { |
592d1631 L |
5651 | { Bad_Opcode }, |
5652 | { Bad_Opcode }, | |
592a252b | 5653 | { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) }, |
c0f3af97 L |
5654 | }, |
5655 | ||
592a252b | 5656 | /* PREFIX_VEX_0F382E */ |
c0f3af97 | 5657 | { |
592d1631 L |
5658 | { Bad_Opcode }, |
5659 | { Bad_Opcode }, | |
592a252b | 5660 | { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) }, |
c0f3af97 L |
5661 | }, |
5662 | ||
592a252b | 5663 | /* PREFIX_VEX_0F382F */ |
c0f3af97 | 5664 | { |
592d1631 L |
5665 | { Bad_Opcode }, |
5666 | { Bad_Opcode }, | |
592a252b | 5667 | { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) }, |
c0f3af97 L |
5668 | }, |
5669 | ||
592a252b | 5670 | /* PREFIX_VEX_0F3830 */ |
c0f3af97 | 5671 | { |
592d1631 L |
5672 | { Bad_Opcode }, |
5673 | { Bad_Opcode }, | |
ec6f095a | 5674 | { "vpmovzxbw", { XM, EXxmmq }, 0 }, |
c0f3af97 L |
5675 | }, |
5676 | ||
592a252b | 5677 | /* PREFIX_VEX_0F3831 */ |
c0f3af97 | 5678 | { |
592d1631 L |
5679 | { Bad_Opcode }, |
5680 | { Bad_Opcode }, | |
ec6f095a | 5681 | { "vpmovzxbd", { XM, EXxmmqd }, 0 }, |
c0f3af97 L |
5682 | }, |
5683 | ||
592a252b | 5684 | /* PREFIX_VEX_0F3832 */ |
c0f3af97 | 5685 | { |
592d1631 L |
5686 | { Bad_Opcode }, |
5687 | { Bad_Opcode }, | |
ec6f095a | 5688 | { "vpmovzxbq", { XM, EXxmmdw }, 0 }, |
c0f3af97 L |
5689 | }, |
5690 | ||
592a252b | 5691 | /* PREFIX_VEX_0F3833 */ |
c0f3af97 | 5692 | { |
592d1631 L |
5693 | { Bad_Opcode }, |
5694 | { Bad_Opcode }, | |
ec6f095a | 5695 | { "vpmovzxwd", { XM, EXxmmq }, 0 }, |
c0f3af97 L |
5696 | }, |
5697 | ||
592a252b | 5698 | /* PREFIX_VEX_0F3834 */ |
c0f3af97 | 5699 | { |
592d1631 L |
5700 | { Bad_Opcode }, |
5701 | { Bad_Opcode }, | |
ec6f095a | 5702 | { "vpmovzxwq", { XM, EXxmmqd }, 0 }, |
c0f3af97 L |
5703 | }, |
5704 | ||
592a252b | 5705 | /* PREFIX_VEX_0F3835 */ |
c0f3af97 | 5706 | { |
592d1631 L |
5707 | { Bad_Opcode }, |
5708 | { Bad_Opcode }, | |
ec6f095a | 5709 | { "vpmovzxdq", { XM, EXxmmq }, 0 }, |
6c30d220 L |
5710 | }, |
5711 | ||
5712 | /* PREFIX_VEX_0F3836 */ | |
5713 | { | |
5714 | { Bad_Opcode }, | |
5715 | { Bad_Opcode }, | |
5716 | { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) }, | |
c0f3af97 L |
5717 | }, |
5718 | ||
592a252b | 5719 | /* PREFIX_VEX_0F3837 */ |
c0f3af97 | 5720 | { |
592d1631 L |
5721 | { Bad_Opcode }, |
5722 | { Bad_Opcode }, | |
ec6f095a | 5723 | { "vpcmpgtq", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5724 | }, |
5725 | ||
592a252b | 5726 | /* PREFIX_VEX_0F3838 */ |
c0f3af97 | 5727 | { |
592d1631 L |
5728 | { Bad_Opcode }, |
5729 | { Bad_Opcode }, | |
ec6f095a | 5730 | { "vpminsb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5731 | }, |
5732 | ||
592a252b | 5733 | /* PREFIX_VEX_0F3839 */ |
c0f3af97 | 5734 | { |
592d1631 L |
5735 | { Bad_Opcode }, |
5736 | { Bad_Opcode }, | |
ec6f095a | 5737 | { "vpminsd", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5738 | }, |
5739 | ||
592a252b | 5740 | /* PREFIX_VEX_0F383A */ |
c0f3af97 | 5741 | { |
592d1631 L |
5742 | { Bad_Opcode }, |
5743 | { Bad_Opcode }, | |
ec6f095a | 5744 | { "vpminuw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5745 | }, |
5746 | ||
592a252b | 5747 | /* PREFIX_VEX_0F383B */ |
c0f3af97 | 5748 | { |
592d1631 L |
5749 | { Bad_Opcode }, |
5750 | { Bad_Opcode }, | |
ec6f095a | 5751 | { "vpminud", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5752 | }, |
5753 | ||
592a252b | 5754 | /* PREFIX_VEX_0F383C */ |
c0f3af97 | 5755 | { |
592d1631 L |
5756 | { Bad_Opcode }, |
5757 | { Bad_Opcode }, | |
ec6f095a | 5758 | { "vpmaxsb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5759 | }, |
5760 | ||
592a252b | 5761 | /* PREFIX_VEX_0F383D */ |
c0f3af97 | 5762 | { |
592d1631 L |
5763 | { Bad_Opcode }, |
5764 | { Bad_Opcode }, | |
ec6f095a | 5765 | { "vpmaxsd", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5766 | }, |
5767 | ||
592a252b | 5768 | /* PREFIX_VEX_0F383E */ |
c0f3af97 | 5769 | { |
592d1631 L |
5770 | { Bad_Opcode }, |
5771 | { Bad_Opcode }, | |
ec6f095a | 5772 | { "vpmaxuw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5773 | }, |
5774 | ||
592a252b | 5775 | /* PREFIX_VEX_0F383F */ |
c0f3af97 | 5776 | { |
592d1631 L |
5777 | { Bad_Opcode }, |
5778 | { Bad_Opcode }, | |
ec6f095a | 5779 | { "vpmaxud", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5780 | }, |
5781 | ||
592a252b | 5782 | /* PREFIX_VEX_0F3840 */ |
c0f3af97 | 5783 | { |
592d1631 L |
5784 | { Bad_Opcode }, |
5785 | { Bad_Opcode }, | |
ec6f095a | 5786 | { "vpmulld", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5787 | }, |
5788 | ||
592a252b | 5789 | /* PREFIX_VEX_0F3841 */ |
c0f3af97 | 5790 | { |
592d1631 L |
5791 | { Bad_Opcode }, |
5792 | { Bad_Opcode }, | |
592a252b | 5793 | { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) }, |
c0f3af97 L |
5794 | }, |
5795 | ||
6c30d220 L |
5796 | /* PREFIX_VEX_0F3845 */ |
5797 | { | |
5798 | { Bad_Opcode }, | |
5799 | { Bad_Opcode }, | |
bf890a93 | 5800 | { "vpsrlv%LW", { XM, Vex, EXx }, 0 }, |
6c30d220 L |
5801 | }, |
5802 | ||
5803 | /* PREFIX_VEX_0F3846 */ | |
5804 | { | |
5805 | { Bad_Opcode }, | |
5806 | { Bad_Opcode }, | |
5807 | { VEX_W_TABLE (VEX_W_0F3846_P_2) }, | |
5808 | }, | |
5809 | ||
5810 | /* PREFIX_VEX_0F3847 */ | |
5811 | { | |
5812 | { Bad_Opcode }, | |
5813 | { Bad_Opcode }, | |
bf890a93 | 5814 | { "vpsllv%LW", { XM, Vex, EXx }, 0 }, |
6c30d220 L |
5815 | }, |
5816 | ||
5817 | /* PREFIX_VEX_0F3858 */ | |
5818 | { | |
5819 | { Bad_Opcode }, | |
5820 | { Bad_Opcode }, | |
5821 | { VEX_W_TABLE (VEX_W_0F3858_P_2) }, | |
5822 | }, | |
5823 | ||
5824 | /* PREFIX_VEX_0F3859 */ | |
5825 | { | |
5826 | { Bad_Opcode }, | |
5827 | { Bad_Opcode }, | |
5828 | { VEX_W_TABLE (VEX_W_0F3859_P_2) }, | |
5829 | }, | |
5830 | ||
5831 | /* PREFIX_VEX_0F385A */ | |
5832 | { | |
5833 | { Bad_Opcode }, | |
5834 | { Bad_Opcode }, | |
5835 | { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) }, | |
5836 | }, | |
5837 | ||
5838 | /* PREFIX_VEX_0F3878 */ | |
5839 | { | |
5840 | { Bad_Opcode }, | |
5841 | { Bad_Opcode }, | |
5842 | { VEX_W_TABLE (VEX_W_0F3878_P_2) }, | |
5843 | }, | |
5844 | ||
5845 | /* PREFIX_VEX_0F3879 */ | |
5846 | { | |
5847 | { Bad_Opcode }, | |
5848 | { Bad_Opcode }, | |
5849 | { VEX_W_TABLE (VEX_W_0F3879_P_2) }, | |
5850 | }, | |
5851 | ||
5852 | /* PREFIX_VEX_0F388C */ | |
5853 | { | |
5854 | { Bad_Opcode }, | |
5855 | { Bad_Opcode }, | |
f7002f42 | 5856 | { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) }, |
6c30d220 L |
5857 | }, |
5858 | ||
5859 | /* PREFIX_VEX_0F388E */ | |
5860 | { | |
5861 | { Bad_Opcode }, | |
5862 | { Bad_Opcode }, | |
f7002f42 | 5863 | { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) }, |
6c30d220 L |
5864 | }, |
5865 | ||
5866 | /* PREFIX_VEX_0F3890 */ | |
5867 | { | |
5868 | { Bad_Opcode }, | |
5869 | { Bad_Opcode }, | |
bf890a93 | 5870 | { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex }, 0 }, |
6c30d220 L |
5871 | }, |
5872 | ||
5873 | /* PREFIX_VEX_0F3891 */ | |
5874 | { | |
5875 | { Bad_Opcode }, | |
5876 | { Bad_Opcode }, | |
bf890a93 | 5877 | { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 }, |
6c30d220 L |
5878 | }, |
5879 | ||
5880 | /* PREFIX_VEX_0F3892 */ | |
5881 | { | |
5882 | { Bad_Opcode }, | |
5883 | { Bad_Opcode }, | |
bf890a93 | 5884 | { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex }, 0 }, |
6c30d220 L |
5885 | }, |
5886 | ||
5887 | /* PREFIX_VEX_0F3893 */ | |
5888 | { | |
5889 | { Bad_Opcode }, | |
5890 | { Bad_Opcode }, | |
bf890a93 | 5891 | { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 }, |
6c30d220 L |
5892 | }, |
5893 | ||
592a252b | 5894 | /* PREFIX_VEX_0F3896 */ |
a5ff0eb2 | 5895 | { |
592d1631 L |
5896 | { Bad_Opcode }, |
5897 | { Bad_Opcode }, | |
6df22cf6 | 5898 | { "vfmaddsub132p%XW", { XM, Vex, EXx, EXxEVexR }, 0 }, |
a5ff0eb2 L |
5899 | }, |
5900 | ||
592a252b | 5901 | /* PREFIX_VEX_0F3897 */ |
a5ff0eb2 | 5902 | { |
592d1631 L |
5903 | { Bad_Opcode }, |
5904 | { Bad_Opcode }, | |
6df22cf6 | 5905 | { "vfmsubadd132p%XW", { XM, Vex, EXx, EXxEVexR }, 0 }, |
a5ff0eb2 L |
5906 | }, |
5907 | ||
592a252b | 5908 | /* PREFIX_VEX_0F3898 */ |
a5ff0eb2 | 5909 | { |
592d1631 L |
5910 | { Bad_Opcode }, |
5911 | { Bad_Opcode }, | |
6df22cf6 | 5912 | { "vfmadd132p%XW", { XM, Vex, EXx, EXxEVexR }, 0 }, |
a5ff0eb2 L |
5913 | }, |
5914 | ||
592a252b | 5915 | /* PREFIX_VEX_0F3899 */ |
a5ff0eb2 | 5916 | { |
592d1631 L |
5917 | { Bad_Opcode }, |
5918 | { Bad_Opcode }, | |
6df22cf6 | 5919 | { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 }, |
a5ff0eb2 L |
5920 | }, |
5921 | ||
592a252b | 5922 | /* PREFIX_VEX_0F389A */ |
a5ff0eb2 | 5923 | { |
592d1631 L |
5924 | { Bad_Opcode }, |
5925 | { Bad_Opcode }, | |
bf890a93 | 5926 | { "vfmsub132p%XW", { XM, Vex, EXx }, 0 }, |
a5ff0eb2 L |
5927 | }, |
5928 | ||
592a252b | 5929 | /* PREFIX_VEX_0F389B */ |
c0f3af97 | 5930 | { |
592d1631 L |
5931 | { Bad_Opcode }, |
5932 | { Bad_Opcode }, | |
bf890a93 | 5933 | { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
5934 | }, |
5935 | ||
592a252b | 5936 | /* PREFIX_VEX_0F389C */ |
c0f3af97 | 5937 | { |
592d1631 L |
5938 | { Bad_Opcode }, |
5939 | { Bad_Opcode }, | |
6df22cf6 | 5940 | { "vfnmadd132p%XW", { XM, Vex, EXx, EXxEVexR }, 0 }, |
c0f3af97 L |
5941 | }, |
5942 | ||
592a252b | 5943 | /* PREFIX_VEX_0F389D */ |
c0f3af97 | 5944 | { |
592d1631 L |
5945 | { Bad_Opcode }, |
5946 | { Bad_Opcode }, | |
6df22cf6 | 5947 | { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 }, |
c0f3af97 L |
5948 | }, |
5949 | ||
592a252b | 5950 | /* PREFIX_VEX_0F389E */ |
c0f3af97 | 5951 | { |
592d1631 L |
5952 | { Bad_Opcode }, |
5953 | { Bad_Opcode }, | |
6df22cf6 | 5954 | { "vfnmsub132p%XW", { XM, Vex, EXx, EXxEVexR }, 0 }, |
c0f3af97 L |
5955 | }, |
5956 | ||
592a252b | 5957 | /* PREFIX_VEX_0F389F */ |
c0f3af97 | 5958 | { |
592d1631 L |
5959 | { Bad_Opcode }, |
5960 | { Bad_Opcode }, | |
6df22cf6 | 5961 | { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 }, |
c0f3af97 L |
5962 | }, |
5963 | ||
592a252b | 5964 | /* PREFIX_VEX_0F38A6 */ |
c0f3af97 | 5965 | { |
592d1631 L |
5966 | { Bad_Opcode }, |
5967 | { Bad_Opcode }, | |
6df22cf6 | 5968 | { "vfmaddsub213p%XW", { XM, Vex, EXx, EXxEVexR }, 0 }, |
592d1631 | 5969 | { Bad_Opcode }, |
c0f3af97 L |
5970 | }, |
5971 | ||
592a252b | 5972 | /* PREFIX_VEX_0F38A7 */ |
c0f3af97 | 5973 | { |
592d1631 L |
5974 | { Bad_Opcode }, |
5975 | { Bad_Opcode }, | |
6df22cf6 | 5976 | { "vfmsubadd213p%XW", { XM, Vex, EXx, EXxEVexR }, 0 }, |
c0f3af97 L |
5977 | }, |
5978 | ||
592a252b | 5979 | /* PREFIX_VEX_0F38A8 */ |
c0f3af97 | 5980 | { |
592d1631 L |
5981 | { Bad_Opcode }, |
5982 | { Bad_Opcode }, | |
6df22cf6 | 5983 | { "vfmadd213p%XW", { XM, Vex, EXx, EXxEVexR }, 0 }, |
c0f3af97 L |
5984 | }, |
5985 | ||
592a252b | 5986 | /* PREFIX_VEX_0F38A9 */ |
c0f3af97 | 5987 | { |
592d1631 L |
5988 | { Bad_Opcode }, |
5989 | { Bad_Opcode }, | |
6df22cf6 | 5990 | { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 }, |
c0f3af97 L |
5991 | }, |
5992 | ||
592a252b | 5993 | /* PREFIX_VEX_0F38AA */ |
c0f3af97 | 5994 | { |
592d1631 L |
5995 | { Bad_Opcode }, |
5996 | { Bad_Opcode }, | |
bf890a93 | 5997 | { "vfmsub213p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5998 | }, |
5999 | ||
592a252b | 6000 | /* PREFIX_VEX_0F38AB */ |
c0f3af97 | 6001 | { |
592d1631 L |
6002 | { Bad_Opcode }, |
6003 | { Bad_Opcode }, | |
bf890a93 | 6004 | { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6005 | }, |
6006 | ||
592a252b | 6007 | /* PREFIX_VEX_0F38AC */ |
c0f3af97 | 6008 | { |
592d1631 L |
6009 | { Bad_Opcode }, |
6010 | { Bad_Opcode }, | |
6df22cf6 | 6011 | { "vfnmadd213p%XW", { XM, Vex, EXx, EXxEVexR }, 0 }, |
c0f3af97 L |
6012 | }, |
6013 | ||
592a252b | 6014 | /* PREFIX_VEX_0F38AD */ |
c0f3af97 | 6015 | { |
592d1631 L |
6016 | { Bad_Opcode }, |
6017 | { Bad_Opcode }, | |
6df22cf6 | 6018 | { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 }, |
c0f3af97 L |
6019 | }, |
6020 | ||
592a252b | 6021 | /* PREFIX_VEX_0F38AE */ |
c0f3af97 | 6022 | { |
592d1631 L |
6023 | { Bad_Opcode }, |
6024 | { Bad_Opcode }, | |
6df22cf6 | 6025 | { "vfnmsub213p%XW", { XM, Vex, EXx, EXxEVexR }, 0 }, |
c0f3af97 L |
6026 | }, |
6027 | ||
592a252b | 6028 | /* PREFIX_VEX_0F38AF */ |
c0f3af97 | 6029 | { |
592d1631 L |
6030 | { Bad_Opcode }, |
6031 | { Bad_Opcode }, | |
6df22cf6 | 6032 | { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 }, |
c0f3af97 L |
6033 | }, |
6034 | ||
592a252b | 6035 | /* PREFIX_VEX_0F38B6 */ |
c0f3af97 | 6036 | { |
592d1631 L |
6037 | { Bad_Opcode }, |
6038 | { Bad_Opcode }, | |
6df22cf6 | 6039 | { "vfmaddsub231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 }, |
c0f3af97 L |
6040 | }, |
6041 | ||
592a252b | 6042 | /* PREFIX_VEX_0F38B7 */ |
c0f3af97 | 6043 | { |
592d1631 L |
6044 | { Bad_Opcode }, |
6045 | { Bad_Opcode }, | |
6df22cf6 | 6046 | { "vfmsubadd231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 }, |
c0f3af97 L |
6047 | }, |
6048 | ||
592a252b | 6049 | /* PREFIX_VEX_0F38B8 */ |
c0f3af97 | 6050 | { |
592d1631 L |
6051 | { Bad_Opcode }, |
6052 | { Bad_Opcode }, | |
6df22cf6 | 6053 | { "vfmadd231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 }, |
c0f3af97 L |
6054 | }, |
6055 | ||
592a252b | 6056 | /* PREFIX_VEX_0F38B9 */ |
c0f3af97 | 6057 | { |
592d1631 L |
6058 | { Bad_Opcode }, |
6059 | { Bad_Opcode }, | |
6df22cf6 | 6060 | { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 }, |
c0f3af97 L |
6061 | }, |
6062 | ||
592a252b | 6063 | /* PREFIX_VEX_0F38BA */ |
c0f3af97 | 6064 | { |
592d1631 L |
6065 | { Bad_Opcode }, |
6066 | { Bad_Opcode }, | |
6df22cf6 | 6067 | { "vfmsub231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 }, |
c0f3af97 L |
6068 | }, |
6069 | ||
592a252b | 6070 | /* PREFIX_VEX_0F38BB */ |
c0f3af97 | 6071 | { |
592d1631 L |
6072 | { Bad_Opcode }, |
6073 | { Bad_Opcode }, | |
6df22cf6 | 6074 | { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 }, |
c0f3af97 L |
6075 | }, |
6076 | ||
592a252b | 6077 | /* PREFIX_VEX_0F38BC */ |
c0f3af97 | 6078 | { |
592d1631 L |
6079 | { Bad_Opcode }, |
6080 | { Bad_Opcode }, | |
6df22cf6 | 6081 | { "vfnmadd231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 }, |
c0f3af97 L |
6082 | }, |
6083 | ||
592a252b | 6084 | /* PREFIX_VEX_0F38BD */ |
c0f3af97 | 6085 | { |
592d1631 L |
6086 | { Bad_Opcode }, |
6087 | { Bad_Opcode }, | |
6df22cf6 | 6088 | { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 }, |
c0f3af97 L |
6089 | }, |
6090 | ||
592a252b | 6091 | /* PREFIX_VEX_0F38BE */ |
c0f3af97 | 6092 | { |
592d1631 L |
6093 | { Bad_Opcode }, |
6094 | { Bad_Opcode }, | |
6df22cf6 | 6095 | { "vfnmsub231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 }, |
c0f3af97 L |
6096 | }, |
6097 | ||
592a252b | 6098 | /* PREFIX_VEX_0F38BF */ |
c0f3af97 | 6099 | { |
592d1631 L |
6100 | { Bad_Opcode }, |
6101 | { Bad_Opcode }, | |
6df22cf6 | 6102 | { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 }, |
c0f3af97 L |
6103 | }, |
6104 | ||
48521003 IT |
6105 | /* PREFIX_VEX_0F38CF */ |
6106 | { | |
6107 | { Bad_Opcode }, | |
6108 | { Bad_Opcode }, | |
6109 | { VEX_W_TABLE (VEX_W_0F38CF_P_2) }, | |
6110 | }, | |
6111 | ||
592a252b | 6112 | /* PREFIX_VEX_0F38DB */ |
c0f3af97 | 6113 | { |
592d1631 L |
6114 | { Bad_Opcode }, |
6115 | { Bad_Opcode }, | |
592a252b | 6116 | { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) }, |
c0f3af97 L |
6117 | }, |
6118 | ||
592a252b | 6119 | /* PREFIX_VEX_0F38DC */ |
c0f3af97 | 6120 | { |
592d1631 L |
6121 | { Bad_Opcode }, |
6122 | { Bad_Opcode }, | |
8dcf1fad | 6123 | { "vaesenc", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6124 | }, |
6125 | ||
592a252b | 6126 | /* PREFIX_VEX_0F38DD */ |
c0f3af97 | 6127 | { |
592d1631 L |
6128 | { Bad_Opcode }, |
6129 | { Bad_Opcode }, | |
8dcf1fad | 6130 | { "vaesenclast", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6131 | }, |
6132 | ||
592a252b | 6133 | /* PREFIX_VEX_0F38DE */ |
c0f3af97 | 6134 | { |
592d1631 L |
6135 | { Bad_Opcode }, |
6136 | { Bad_Opcode }, | |
8dcf1fad | 6137 | { "vaesdec", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6138 | }, |
6139 | ||
592a252b | 6140 | /* PREFIX_VEX_0F38DF */ |
c0f3af97 | 6141 | { |
592d1631 L |
6142 | { Bad_Opcode }, |
6143 | { Bad_Opcode }, | |
8dcf1fad | 6144 | { "vaesdeclast", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6145 | }, |
6146 | ||
f12dc422 L |
6147 | /* PREFIX_VEX_0F38F2 */ |
6148 | { | |
6149 | { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) }, | |
6150 | }, | |
6151 | ||
6152 | /* PREFIX_VEX_0F38F3_REG_1 */ | |
6153 | { | |
6154 | { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) }, | |
6155 | }, | |
6156 | ||
6157 | /* PREFIX_VEX_0F38F3_REG_2 */ | |
6158 | { | |
6159 | { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) }, | |
6160 | }, | |
6161 | ||
6162 | /* PREFIX_VEX_0F38F3_REG_3 */ | |
6163 | { | |
6164 | { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) }, | |
6165 | }, | |
6166 | ||
6c30d220 L |
6167 | /* PREFIX_VEX_0F38F5 */ |
6168 | { | |
6169 | { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) }, | |
6170 | { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) }, | |
6171 | { Bad_Opcode }, | |
6172 | { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) }, | |
6173 | }, | |
6174 | ||
6175 | /* PREFIX_VEX_0F38F6 */ | |
6176 | { | |
6177 | { Bad_Opcode }, | |
6178 | { Bad_Opcode }, | |
6179 | { Bad_Opcode }, | |
6180 | { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) }, | |
6181 | }, | |
6182 | ||
f12dc422 L |
6183 | /* PREFIX_VEX_0F38F7 */ |
6184 | { | |
6185 | { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) }, | |
6c30d220 L |
6186 | { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) }, |
6187 | { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) }, | |
6188 | { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) }, | |
6189 | }, | |
6190 | ||
6191 | /* PREFIX_VEX_0F3A00 */ | |
6192 | { | |
6193 | { Bad_Opcode }, | |
6194 | { Bad_Opcode }, | |
6195 | { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) }, | |
6196 | }, | |
6197 | ||
6198 | /* PREFIX_VEX_0F3A01 */ | |
6199 | { | |
6200 | { Bad_Opcode }, | |
6201 | { Bad_Opcode }, | |
6202 | { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) }, | |
6203 | }, | |
6204 | ||
6205 | /* PREFIX_VEX_0F3A02 */ | |
6206 | { | |
6207 | { Bad_Opcode }, | |
6208 | { Bad_Opcode }, | |
6209 | { VEX_W_TABLE (VEX_W_0F3A02_P_2) }, | |
f12dc422 L |
6210 | }, |
6211 | ||
592a252b | 6212 | /* PREFIX_VEX_0F3A04 */ |
c0f3af97 | 6213 | { |
592d1631 L |
6214 | { Bad_Opcode }, |
6215 | { Bad_Opcode }, | |
592a252b | 6216 | { VEX_W_TABLE (VEX_W_0F3A04_P_2) }, |
c0f3af97 L |
6217 | }, |
6218 | ||
592a252b | 6219 | /* PREFIX_VEX_0F3A05 */ |
c0f3af97 | 6220 | { |
592d1631 L |
6221 | { Bad_Opcode }, |
6222 | { Bad_Opcode }, | |
592a252b | 6223 | { VEX_W_TABLE (VEX_W_0F3A05_P_2) }, |
c0f3af97 L |
6224 | }, |
6225 | ||
592a252b | 6226 | /* PREFIX_VEX_0F3A06 */ |
c0f3af97 | 6227 | { |
592d1631 L |
6228 | { Bad_Opcode }, |
6229 | { Bad_Opcode }, | |
592a252b | 6230 | { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) }, |
c0f3af97 L |
6231 | }, |
6232 | ||
592a252b | 6233 | /* PREFIX_VEX_0F3A08 */ |
c0f3af97 | 6234 | { |
592d1631 L |
6235 | { Bad_Opcode }, |
6236 | { Bad_Opcode }, | |
ec6f095a | 6237 | { "vroundps", { XM, EXx, Ib }, 0 }, |
c0f3af97 L |
6238 | }, |
6239 | ||
592a252b | 6240 | /* PREFIX_VEX_0F3A09 */ |
c0f3af97 | 6241 | { |
592d1631 L |
6242 | { Bad_Opcode }, |
6243 | { Bad_Opcode }, | |
ec6f095a | 6244 | { "vroundpd", { XM, EXx, Ib }, 0 }, |
c0f3af97 L |
6245 | }, |
6246 | ||
592a252b | 6247 | /* PREFIX_VEX_0F3A0A */ |
c0f3af97 | 6248 | { |
592d1631 L |
6249 | { Bad_Opcode }, |
6250 | { Bad_Opcode }, | |
5b872f7d | 6251 | { "vroundss", { XMScalar, VexScalar, EXxmm_md, Ib }, 0 }, |
0bfee649 L |
6252 | }, |
6253 | ||
592a252b | 6254 | /* PREFIX_VEX_0F3A0B */ |
0bfee649 | 6255 | { |
592d1631 L |
6256 | { Bad_Opcode }, |
6257 | { Bad_Opcode }, | |
5b872f7d | 6258 | { "vroundsd", { XMScalar, VexScalar, EXxmm_mq, Ib }, 0 }, |
0bfee649 L |
6259 | }, |
6260 | ||
592a252b | 6261 | /* PREFIX_VEX_0F3A0C */ |
0bfee649 | 6262 | { |
592d1631 L |
6263 | { Bad_Opcode }, |
6264 | { Bad_Opcode }, | |
ec6f095a | 6265 | { "vblendps", { XM, Vex, EXx, Ib }, 0 }, |
0bfee649 L |
6266 | }, |
6267 | ||
592a252b | 6268 | /* PREFIX_VEX_0F3A0D */ |
0bfee649 | 6269 | { |
592d1631 L |
6270 | { Bad_Opcode }, |
6271 | { Bad_Opcode }, | |
ec6f095a | 6272 | { "vblendpd", { XM, Vex, EXx, Ib }, 0 }, |
c0f3af97 L |
6273 | }, |
6274 | ||
592a252b | 6275 | /* PREFIX_VEX_0F3A0E */ |
0bfee649 | 6276 | { |
592d1631 L |
6277 | { Bad_Opcode }, |
6278 | { Bad_Opcode }, | |
ec6f095a | 6279 | { "vpblendw", { XM, Vex, EXx, Ib }, 0 }, |
0bfee649 L |
6280 | }, |
6281 | ||
592a252b | 6282 | /* PREFIX_VEX_0F3A0F */ |
0bfee649 | 6283 | { |
592d1631 L |
6284 | { Bad_Opcode }, |
6285 | { Bad_Opcode }, | |
ec6f095a | 6286 | { "vpalignr", { XM, Vex, EXx, Ib }, 0 }, |
0bfee649 L |
6287 | }, |
6288 | ||
592a252b | 6289 | /* PREFIX_VEX_0F3A14 */ |
0bfee649 | 6290 | { |
592d1631 L |
6291 | { Bad_Opcode }, |
6292 | { Bad_Opcode }, | |
592a252b | 6293 | { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) }, |
0bfee649 L |
6294 | }, |
6295 | ||
592a252b | 6296 | /* PREFIX_VEX_0F3A15 */ |
0bfee649 | 6297 | { |
592d1631 L |
6298 | { Bad_Opcode }, |
6299 | { Bad_Opcode }, | |
592a252b | 6300 | { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) }, |
0bfee649 L |
6301 | }, |
6302 | ||
592a252b | 6303 | /* PREFIX_VEX_0F3A16 */ |
c0f3af97 | 6304 | { |
592d1631 L |
6305 | { Bad_Opcode }, |
6306 | { Bad_Opcode }, | |
592a252b | 6307 | { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) }, |
c0f3af97 L |
6308 | }, |
6309 | ||
592a252b | 6310 | /* PREFIX_VEX_0F3A17 */ |
c0f3af97 | 6311 | { |
592d1631 L |
6312 | { Bad_Opcode }, |
6313 | { Bad_Opcode }, | |
592a252b | 6314 | { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) }, |
c0f3af97 L |
6315 | }, |
6316 | ||
592a252b | 6317 | /* PREFIX_VEX_0F3A18 */ |
c0f3af97 | 6318 | { |
592d1631 L |
6319 | { Bad_Opcode }, |
6320 | { Bad_Opcode }, | |
592a252b | 6321 | { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) }, |
c0f3af97 L |
6322 | }, |
6323 | ||
592a252b | 6324 | /* PREFIX_VEX_0F3A19 */ |
c0f3af97 | 6325 | { |
592d1631 L |
6326 | { Bad_Opcode }, |
6327 | { Bad_Opcode }, | |
592a252b | 6328 | { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) }, |
c0f3af97 L |
6329 | }, |
6330 | ||
592a252b | 6331 | /* PREFIX_VEX_0F3A1D */ |
c7b8aa3a L |
6332 | { |
6333 | { Bad_Opcode }, | |
6334 | { Bad_Opcode }, | |
6431c801 | 6335 | { VEX_W_TABLE (VEX_W_0F3A1D_P_2) }, |
c7b8aa3a L |
6336 | }, |
6337 | ||
592a252b | 6338 | /* PREFIX_VEX_0F3A20 */ |
c0f3af97 | 6339 | { |
592d1631 L |
6340 | { Bad_Opcode }, |
6341 | { Bad_Opcode }, | |
592a252b | 6342 | { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) }, |
c0f3af97 L |
6343 | }, |
6344 | ||
592a252b | 6345 | /* PREFIX_VEX_0F3A21 */ |
c0f3af97 | 6346 | { |
592d1631 L |
6347 | { Bad_Opcode }, |
6348 | { Bad_Opcode }, | |
592a252b | 6349 | { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) }, |
c0f3af97 L |
6350 | }, |
6351 | ||
592a252b | 6352 | /* PREFIX_VEX_0F3A22 */ |
0bfee649 | 6353 | { |
592d1631 L |
6354 | { Bad_Opcode }, |
6355 | { Bad_Opcode }, | |
592a252b | 6356 | { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) }, |
0bfee649 L |
6357 | }, |
6358 | ||
43234a1e L |
6359 | /* PREFIX_VEX_0F3A30 */ |
6360 | { | |
6361 | { Bad_Opcode }, | |
6362 | { Bad_Opcode }, | |
6363 | { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2) }, | |
6364 | }, | |
6365 | ||
1ba585e8 IT |
6366 | /* PREFIX_VEX_0F3A31 */ |
6367 | { | |
6368 | { Bad_Opcode }, | |
6369 | { Bad_Opcode }, | |
6370 | { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2) }, | |
6371 | }, | |
6372 | ||
43234a1e L |
6373 | /* PREFIX_VEX_0F3A32 */ |
6374 | { | |
6375 | { Bad_Opcode }, | |
6376 | { Bad_Opcode }, | |
6377 | { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2) }, | |
6378 | }, | |
6379 | ||
1ba585e8 IT |
6380 | /* PREFIX_VEX_0F3A33 */ |
6381 | { | |
6382 | { Bad_Opcode }, | |
6383 | { Bad_Opcode }, | |
6384 | { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2) }, | |
6385 | }, | |
6386 | ||
6c30d220 L |
6387 | /* PREFIX_VEX_0F3A38 */ |
6388 | { | |
6389 | { Bad_Opcode }, | |
6390 | { Bad_Opcode }, | |
6391 | { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) }, | |
6392 | }, | |
6393 | ||
6394 | /* PREFIX_VEX_0F3A39 */ | |
6395 | { | |
6396 | { Bad_Opcode }, | |
6397 | { Bad_Opcode }, | |
6398 | { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) }, | |
6399 | }, | |
6400 | ||
592a252b | 6401 | /* PREFIX_VEX_0F3A40 */ |
c0f3af97 | 6402 | { |
592d1631 L |
6403 | { Bad_Opcode }, |
6404 | { Bad_Opcode }, | |
ec6f095a | 6405 | { "vdpps", { XM, Vex, EXx, Ib }, 0 }, |
c0f3af97 L |
6406 | }, |
6407 | ||
592a252b | 6408 | /* PREFIX_VEX_0F3A41 */ |
c0f3af97 | 6409 | { |
592d1631 L |
6410 | { Bad_Opcode }, |
6411 | { Bad_Opcode }, | |
592a252b | 6412 | { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) }, |
c0f3af97 L |
6413 | }, |
6414 | ||
592a252b | 6415 | /* PREFIX_VEX_0F3A42 */ |
c0f3af97 | 6416 | { |
592d1631 L |
6417 | { Bad_Opcode }, |
6418 | { Bad_Opcode }, | |
ec6f095a | 6419 | { "vmpsadbw", { XM, Vex, EXx, Ib }, 0 }, |
c0f3af97 L |
6420 | }, |
6421 | ||
592a252b | 6422 | /* PREFIX_VEX_0F3A44 */ |
ce2f5b3c | 6423 | { |
592d1631 L |
6424 | { Bad_Opcode }, |
6425 | { Bad_Opcode }, | |
ff1982d5 | 6426 | { "vpclmulqdq", { XM, Vex, EXx, PCLMUL }, 0 }, |
ce2f5b3c L |
6427 | }, |
6428 | ||
6c30d220 L |
6429 | /* PREFIX_VEX_0F3A46 */ |
6430 | { | |
6431 | { Bad_Opcode }, | |
6432 | { Bad_Opcode }, | |
6433 | { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) }, | |
6434 | }, | |
6435 | ||
592a252b | 6436 | /* PREFIX_VEX_0F3A48 */ |
a683cc34 SP |
6437 | { |
6438 | { Bad_Opcode }, | |
6439 | { Bad_Opcode }, | |
592a252b | 6440 | { VEX_W_TABLE (VEX_W_0F3A48_P_2) }, |
a683cc34 SP |
6441 | }, |
6442 | ||
592a252b | 6443 | /* PREFIX_VEX_0F3A49 */ |
a683cc34 SP |
6444 | { |
6445 | { Bad_Opcode }, | |
6446 | { Bad_Opcode }, | |
592a252b | 6447 | { VEX_W_TABLE (VEX_W_0F3A49_P_2) }, |
a683cc34 SP |
6448 | }, |
6449 | ||
592a252b | 6450 | /* PREFIX_VEX_0F3A4A */ |
c0f3af97 | 6451 | { |
592d1631 L |
6452 | { Bad_Opcode }, |
6453 | { Bad_Opcode }, | |
592a252b | 6454 | { VEX_W_TABLE (VEX_W_0F3A4A_P_2) }, |
c0f3af97 L |
6455 | }, |
6456 | ||
592a252b | 6457 | /* PREFIX_VEX_0F3A4B */ |
c0f3af97 | 6458 | { |
592d1631 L |
6459 | { Bad_Opcode }, |
6460 | { Bad_Opcode }, | |
592a252b | 6461 | { VEX_W_TABLE (VEX_W_0F3A4B_P_2) }, |
c0f3af97 L |
6462 | }, |
6463 | ||
592a252b | 6464 | /* PREFIX_VEX_0F3A4C */ |
c0f3af97 | 6465 | { |
592d1631 L |
6466 | { Bad_Opcode }, |
6467 | { Bad_Opcode }, | |
6c30d220 | 6468 | { VEX_W_TABLE (VEX_W_0F3A4C_P_2) }, |
c0f3af97 L |
6469 | }, |
6470 | ||
592a252b | 6471 | /* PREFIX_VEX_0F3A5C */ |
922d8de8 | 6472 | { |
592d1631 L |
6473 | { Bad_Opcode }, |
6474 | { Bad_Opcode }, | |
3a2430e0 | 6475 | { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
922d8de8 DR |
6476 | }, |
6477 | ||
592a252b | 6478 | /* PREFIX_VEX_0F3A5D */ |
922d8de8 | 6479 | { |
592d1631 L |
6480 | { Bad_Opcode }, |
6481 | { Bad_Opcode }, | |
3a2430e0 | 6482 | { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
922d8de8 DR |
6483 | }, |
6484 | ||
592a252b | 6485 | /* PREFIX_VEX_0F3A5E */ |
922d8de8 | 6486 | { |
592d1631 L |
6487 | { Bad_Opcode }, |
6488 | { Bad_Opcode }, | |
3a2430e0 | 6489 | { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
922d8de8 DR |
6490 | }, |
6491 | ||
592a252b | 6492 | /* PREFIX_VEX_0F3A5F */ |
922d8de8 | 6493 | { |
592d1631 L |
6494 | { Bad_Opcode }, |
6495 | { Bad_Opcode }, | |
3a2430e0 | 6496 | { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
922d8de8 DR |
6497 | }, |
6498 | ||
592a252b | 6499 | /* PREFIX_VEX_0F3A60 */ |
c0f3af97 | 6500 | { |
592d1631 L |
6501 | { Bad_Opcode }, |
6502 | { Bad_Opcode }, | |
592a252b | 6503 | { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) }, |
592d1631 | 6504 | { Bad_Opcode }, |
c0f3af97 L |
6505 | }, |
6506 | ||
592a252b | 6507 | /* PREFIX_VEX_0F3A61 */ |
c0f3af97 | 6508 | { |
592d1631 L |
6509 | { Bad_Opcode }, |
6510 | { Bad_Opcode }, | |
592a252b | 6511 | { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) }, |
c0f3af97 L |
6512 | }, |
6513 | ||
592a252b | 6514 | /* PREFIX_VEX_0F3A62 */ |
c0f3af97 | 6515 | { |
592d1631 L |
6516 | { Bad_Opcode }, |
6517 | { Bad_Opcode }, | |
592a252b | 6518 | { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) }, |
c0f3af97 L |
6519 | }, |
6520 | ||
592a252b | 6521 | /* PREFIX_VEX_0F3A63 */ |
c0f3af97 | 6522 | { |
592d1631 L |
6523 | { Bad_Opcode }, |
6524 | { Bad_Opcode }, | |
592a252b | 6525 | { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) }, |
c0f3af97 | 6526 | }, |
a5ff0eb2 | 6527 | |
592a252b | 6528 | /* PREFIX_VEX_0F3A68 */ |
922d8de8 | 6529 | { |
592d1631 L |
6530 | { Bad_Opcode }, |
6531 | { Bad_Opcode }, | |
3a2430e0 | 6532 | { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
922d8de8 DR |
6533 | }, |
6534 | ||
592a252b | 6535 | /* PREFIX_VEX_0F3A69 */ |
922d8de8 | 6536 | { |
592d1631 L |
6537 | { Bad_Opcode }, |
6538 | { Bad_Opcode }, | |
3a2430e0 | 6539 | { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
922d8de8 DR |
6540 | }, |
6541 | ||
592a252b | 6542 | /* PREFIX_VEX_0F3A6A */ |
922d8de8 | 6543 | { |
592d1631 L |
6544 | { Bad_Opcode }, |
6545 | { Bad_Opcode }, | |
592a252b | 6546 | { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) }, |
922d8de8 DR |
6547 | }, |
6548 | ||
592a252b | 6549 | /* PREFIX_VEX_0F3A6B */ |
922d8de8 | 6550 | { |
592d1631 L |
6551 | { Bad_Opcode }, |
6552 | { Bad_Opcode }, | |
592a252b | 6553 | { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) }, |
922d8de8 DR |
6554 | }, |
6555 | ||
592a252b | 6556 | /* PREFIX_VEX_0F3A6C */ |
922d8de8 | 6557 | { |
592d1631 L |
6558 | { Bad_Opcode }, |
6559 | { Bad_Opcode }, | |
3a2430e0 | 6560 | { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
922d8de8 DR |
6561 | }, |
6562 | ||
592a252b | 6563 | /* PREFIX_VEX_0F3A6D */ |
922d8de8 | 6564 | { |
592d1631 L |
6565 | { Bad_Opcode }, |
6566 | { Bad_Opcode }, | |
3a2430e0 | 6567 | { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
922d8de8 DR |
6568 | }, |
6569 | ||
592a252b | 6570 | /* PREFIX_VEX_0F3A6E */ |
922d8de8 | 6571 | { |
592d1631 L |
6572 | { Bad_Opcode }, |
6573 | { Bad_Opcode }, | |
592a252b | 6574 | { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) }, |
922d8de8 DR |
6575 | }, |
6576 | ||
592a252b | 6577 | /* PREFIX_VEX_0F3A6F */ |
922d8de8 | 6578 | { |
592d1631 L |
6579 | { Bad_Opcode }, |
6580 | { Bad_Opcode }, | |
592a252b | 6581 | { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) }, |
922d8de8 DR |
6582 | }, |
6583 | ||
592a252b | 6584 | /* PREFIX_VEX_0F3A78 */ |
922d8de8 | 6585 | { |
592d1631 L |
6586 | { Bad_Opcode }, |
6587 | { Bad_Opcode }, | |
3a2430e0 | 6588 | { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
922d8de8 DR |
6589 | }, |
6590 | ||
592a252b | 6591 | /* PREFIX_VEX_0F3A79 */ |
922d8de8 | 6592 | { |
592d1631 L |
6593 | { Bad_Opcode }, |
6594 | { Bad_Opcode }, | |
3a2430e0 | 6595 | { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
922d8de8 DR |
6596 | }, |
6597 | ||
592a252b | 6598 | /* PREFIX_VEX_0F3A7A */ |
922d8de8 | 6599 | { |
592d1631 L |
6600 | { Bad_Opcode }, |
6601 | { Bad_Opcode }, | |
592a252b | 6602 | { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) }, |
922d8de8 DR |
6603 | }, |
6604 | ||
592a252b | 6605 | /* PREFIX_VEX_0F3A7B */ |
922d8de8 | 6606 | { |
592d1631 L |
6607 | { Bad_Opcode }, |
6608 | { Bad_Opcode }, | |
592a252b | 6609 | { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) }, |
922d8de8 DR |
6610 | }, |
6611 | ||
592a252b | 6612 | /* PREFIX_VEX_0F3A7C */ |
922d8de8 | 6613 | { |
592d1631 L |
6614 | { Bad_Opcode }, |
6615 | { Bad_Opcode }, | |
3a2430e0 | 6616 | { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
592d1631 | 6617 | { Bad_Opcode }, |
922d8de8 DR |
6618 | }, |
6619 | ||
592a252b | 6620 | /* PREFIX_VEX_0F3A7D */ |
922d8de8 | 6621 | { |
592d1631 L |
6622 | { Bad_Opcode }, |
6623 | { Bad_Opcode }, | |
3a2430e0 | 6624 | { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
922d8de8 DR |
6625 | }, |
6626 | ||
592a252b | 6627 | /* PREFIX_VEX_0F3A7E */ |
922d8de8 | 6628 | { |
592d1631 L |
6629 | { Bad_Opcode }, |
6630 | { Bad_Opcode }, | |
592a252b | 6631 | { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) }, |
922d8de8 DR |
6632 | }, |
6633 | ||
592a252b | 6634 | /* PREFIX_VEX_0F3A7F */ |
922d8de8 | 6635 | { |
592d1631 L |
6636 | { Bad_Opcode }, |
6637 | { Bad_Opcode }, | |
592a252b | 6638 | { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) }, |
922d8de8 DR |
6639 | }, |
6640 | ||
48521003 IT |
6641 | /* PREFIX_VEX_0F3ACE */ |
6642 | { | |
6643 | { Bad_Opcode }, | |
6644 | { Bad_Opcode }, | |
6645 | { VEX_W_TABLE (VEX_W_0F3ACE_P_2) }, | |
6646 | }, | |
6647 | ||
6648 | /* PREFIX_VEX_0F3ACF */ | |
6649 | { | |
6650 | { Bad_Opcode }, | |
6651 | { Bad_Opcode }, | |
6652 | { VEX_W_TABLE (VEX_W_0F3ACF_P_2) }, | |
6653 | }, | |
6654 | ||
592a252b | 6655 | /* PREFIX_VEX_0F3ADF */ |
a5ff0eb2 | 6656 | { |
592d1631 L |
6657 | { Bad_Opcode }, |
6658 | { Bad_Opcode }, | |
592a252b | 6659 | { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) }, |
a5ff0eb2 | 6660 | }, |
6c30d220 L |
6661 | |
6662 | /* PREFIX_VEX_0F3AF0 */ | |
6663 | { | |
6664 | { Bad_Opcode }, | |
6665 | { Bad_Opcode }, | |
6666 | { Bad_Opcode }, | |
6667 | { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) }, | |
6668 | }, | |
43234a1e | 6669 | |
ad692897 | 6670 | #include "i386-dis-evex-prefix.h" |
c0f3af97 L |
6671 | }; |
6672 | ||
6673 | static const struct dis386 x86_64_table[][2] = { | |
6674 | /* X86_64_06 */ | |
6675 | { | |
bf890a93 | 6676 | { "pushP", { es }, 0 }, |
c0f3af97 L |
6677 | }, |
6678 | ||
6679 | /* X86_64_07 */ | |
6680 | { | |
bf890a93 | 6681 | { "popP", { es }, 0 }, |
c0f3af97 L |
6682 | }, |
6683 | ||
1673df32 | 6684 | /* X86_64_0E */ |
c0f3af97 | 6685 | { |
bf890a93 | 6686 | { "pushP", { cs }, 0 }, |
c0f3af97 L |
6687 | }, |
6688 | ||
6689 | /* X86_64_16 */ | |
6690 | { | |
bf890a93 | 6691 | { "pushP", { ss }, 0 }, |
c0f3af97 L |
6692 | }, |
6693 | ||
6694 | /* X86_64_17 */ | |
6695 | { | |
bf890a93 | 6696 | { "popP", { ss }, 0 }, |
c0f3af97 L |
6697 | }, |
6698 | ||
6699 | /* X86_64_1E */ | |
6700 | { | |
bf890a93 | 6701 | { "pushP", { ds }, 0 }, |
c0f3af97 L |
6702 | }, |
6703 | ||
6704 | /* X86_64_1F */ | |
6705 | { | |
bf890a93 | 6706 | { "popP", { ds }, 0 }, |
c0f3af97 L |
6707 | }, |
6708 | ||
6709 | /* X86_64_27 */ | |
6710 | { | |
bf890a93 | 6711 | { "daa", { XX }, 0 }, |
c0f3af97 L |
6712 | }, |
6713 | ||
6714 | /* X86_64_2F */ | |
6715 | { | |
bf890a93 | 6716 | { "das", { XX }, 0 }, |
c0f3af97 L |
6717 | }, |
6718 | ||
6719 | /* X86_64_37 */ | |
6720 | { | |
bf890a93 | 6721 | { "aaa", { XX }, 0 }, |
c0f3af97 L |
6722 | }, |
6723 | ||
6724 | /* X86_64_3F */ | |
6725 | { | |
bf890a93 | 6726 | { "aas", { XX }, 0 }, |
c0f3af97 L |
6727 | }, |
6728 | ||
6729 | /* X86_64_60 */ | |
6730 | { | |
bf890a93 | 6731 | { "pushaP", { XX }, 0 }, |
c0f3af97 L |
6732 | }, |
6733 | ||
6734 | /* X86_64_61 */ | |
6735 | { | |
bf890a93 | 6736 | { "popaP", { XX }, 0 }, |
c0f3af97 L |
6737 | }, |
6738 | ||
6739 | /* X86_64_62 */ | |
6740 | { | |
6741 | { MOD_TABLE (MOD_62_32BIT) }, | |
43234a1e | 6742 | { EVEX_TABLE (EVEX_0F) }, |
c0f3af97 L |
6743 | }, |
6744 | ||
6745 | /* X86_64_63 */ | |
6746 | { | |
bf890a93 | 6747 | { "arpl", { Ew, Gw }, 0 }, |
bc31405e | 6748 | { "movs", { { OP_G, movsxd_mode }, { MOVSXD_Fixup, movsxd_mode } }, 0 }, |
c0f3af97 L |
6749 | }, |
6750 | ||
6751 | /* X86_64_6D */ | |
6752 | { | |
bf890a93 IT |
6753 | { "ins{R|}", { Yzr, indirDX }, 0 }, |
6754 | { "ins{G|}", { Yzr, indirDX }, 0 }, | |
c0f3af97 L |
6755 | }, |
6756 | ||
6757 | /* X86_64_6F */ | |
6758 | { | |
bf890a93 IT |
6759 | { "outs{R|}", { indirDXr, Xz }, 0 }, |
6760 | { "outs{G|}", { indirDXr, Xz }, 0 }, | |
c0f3af97 L |
6761 | }, |
6762 | ||
d039fef3 | 6763 | /* X86_64_82 */ |
8b89fe14 | 6764 | { |
de194d85 | 6765 | /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode. */ |
d039fef3 | 6766 | { REG_TABLE (REG_80) }, |
8b89fe14 L |
6767 | }, |
6768 | ||
c0f3af97 L |
6769 | /* X86_64_9A */ |
6770 | { | |
8f570d62 | 6771 | { "{l|}call{T|}", { Ap }, 0 }, |
c0f3af97 L |
6772 | }, |
6773 | ||
aeab2b26 JB |
6774 | /* X86_64_C2 */ |
6775 | { | |
6776 | { "retP", { Iw, BND }, 0 }, | |
6777 | { "ret@", { Iw, BND }, 0 }, | |
6778 | }, | |
6779 | ||
6780 | /* X86_64_C3 */ | |
6781 | { | |
6782 | { "retP", { BND }, 0 }, | |
6783 | { "ret@", { BND }, 0 }, | |
6784 | }, | |
6785 | ||
c0f3af97 L |
6786 | /* X86_64_C4 */ |
6787 | { | |
6788 | { MOD_TABLE (MOD_C4_32BIT) }, | |
6789 | { VEX_C4_TABLE (VEX_0F) }, | |
6790 | }, | |
6791 | ||
6792 | /* X86_64_C5 */ | |
6793 | { | |
6794 | { MOD_TABLE (MOD_C5_32BIT) }, | |
6795 | { VEX_C5_TABLE (VEX_0F) }, | |
6796 | }, | |
6797 | ||
6798 | /* X86_64_CE */ | |
6799 | { | |
bf890a93 | 6800 | { "into", { XX }, 0 }, |
c0f3af97 L |
6801 | }, |
6802 | ||
6803 | /* X86_64_D4 */ | |
6804 | { | |
bf890a93 | 6805 | { "aam", { Ib }, 0 }, |
c0f3af97 L |
6806 | }, |
6807 | ||
6808 | /* X86_64_D5 */ | |
6809 | { | |
bf890a93 | 6810 | { "aad", { Ib }, 0 }, |
c0f3af97 L |
6811 | }, |
6812 | ||
a72d2af2 L |
6813 | /* X86_64_E8 */ |
6814 | { | |
6815 | { "callP", { Jv, BND }, 0 }, | |
5db04b09 | 6816 | { "call@", { Jv, BND }, 0 } |
a72d2af2 L |
6817 | }, |
6818 | ||
6819 | /* X86_64_E9 */ | |
6820 | { | |
6821 | { "jmpP", { Jv, BND }, 0 }, | |
5db04b09 | 6822 | { "jmp@", { Jv, BND }, 0 } |
a72d2af2 L |
6823 | }, |
6824 | ||
c0f3af97 L |
6825 | /* X86_64_EA */ |
6826 | { | |
8f570d62 | 6827 | { "{l|}jmp{T|}", { Ap }, 0 }, |
c0f3af97 L |
6828 | }, |
6829 | ||
6830 | /* X86_64_0F01_REG_0 */ | |
6831 | { | |
d1c36125 | 6832 | { "sgdt{Q|Q}", { M }, 0 }, |
bf890a93 | 6833 | { "sgdt", { M }, 0 }, |
c0f3af97 L |
6834 | }, |
6835 | ||
6836 | /* X86_64_0F01_REG_1 */ | |
6837 | { | |
d1c36125 | 6838 | { "sidt{Q|Q}", { M }, 0 }, |
bf890a93 | 6839 | { "sidt", { M }, 0 }, |
c0f3af97 L |
6840 | }, |
6841 | ||
6842 | /* X86_64_0F01_REG_2 */ | |
6843 | { | |
bf890a93 IT |
6844 | { "lgdt{Q|Q}", { M }, 0 }, |
6845 | { "lgdt", { M }, 0 }, | |
c0f3af97 L |
6846 | }, |
6847 | ||
6848 | /* X86_64_0F01_REG_3 */ | |
6849 | { | |
bf890a93 IT |
6850 | { "lidt{Q|Q}", { M }, 0 }, |
6851 | { "lidt", { M }, 0 }, | |
c0f3af97 L |
6852 | }, |
6853 | }; | |
6854 | ||
6855 | static const struct dis386 three_byte_table[][256] = { | |
c1e679ec DR |
6856 | |
6857 | /* THREE_BYTE_0F38 */ | |
c0f3af97 L |
6858 | { |
6859 | /* 00 */ | |
507bd325 L |
6860 | { "pshufb", { MX, EM }, PREFIX_OPCODE }, |
6861 | { "phaddw", { MX, EM }, PREFIX_OPCODE }, | |
6862 | { "phaddd", { MX, EM }, PREFIX_OPCODE }, | |
6863 | { "phaddsw", { MX, EM }, PREFIX_OPCODE }, | |
6864 | { "pmaddubsw", { MX, EM }, PREFIX_OPCODE }, | |
6865 | { "phsubw", { MX, EM }, PREFIX_OPCODE }, | |
6866 | { "phsubd", { MX, EM }, PREFIX_OPCODE }, | |
6867 | { "phsubsw", { MX, EM }, PREFIX_OPCODE }, | |
c0f3af97 | 6868 | /* 08 */ |
507bd325 L |
6869 | { "psignb", { MX, EM }, PREFIX_OPCODE }, |
6870 | { "psignw", { MX, EM }, PREFIX_OPCODE }, | |
6871 | { "psignd", { MX, EM }, PREFIX_OPCODE }, | |
6872 | { "pmulhrsw", { MX, EM }, PREFIX_OPCODE }, | |
592d1631 L |
6873 | { Bad_Opcode }, |
6874 | { Bad_Opcode }, | |
6875 | { Bad_Opcode }, | |
6876 | { Bad_Opcode }, | |
f88c9eb0 SP |
6877 | /* 10 */ |
6878 | { PREFIX_TABLE (PREFIX_0F3810) }, | |
592d1631 L |
6879 | { Bad_Opcode }, |
6880 | { Bad_Opcode }, | |
6881 | { Bad_Opcode }, | |
f88c9eb0 SP |
6882 | { PREFIX_TABLE (PREFIX_0F3814) }, |
6883 | { PREFIX_TABLE (PREFIX_0F3815) }, | |
592d1631 | 6884 | { Bad_Opcode }, |
f88c9eb0 SP |
6885 | { PREFIX_TABLE (PREFIX_0F3817) }, |
6886 | /* 18 */ | |
592d1631 L |
6887 | { Bad_Opcode }, |
6888 | { Bad_Opcode }, | |
6889 | { Bad_Opcode }, | |
6890 | { Bad_Opcode }, | |
507bd325 L |
6891 | { "pabsb", { MX, EM }, PREFIX_OPCODE }, |
6892 | { "pabsw", { MX, EM }, PREFIX_OPCODE }, | |
6893 | { "pabsd", { MX, EM }, PREFIX_OPCODE }, | |
592d1631 | 6894 | { Bad_Opcode }, |
f88c9eb0 SP |
6895 | /* 20 */ |
6896 | { PREFIX_TABLE (PREFIX_0F3820) }, | |
6897 | { PREFIX_TABLE (PREFIX_0F3821) }, | |
6898 | { PREFIX_TABLE (PREFIX_0F3822) }, | |
6899 | { PREFIX_TABLE (PREFIX_0F3823) }, | |
6900 | { PREFIX_TABLE (PREFIX_0F3824) }, | |
6901 | { PREFIX_TABLE (PREFIX_0F3825) }, | |
592d1631 L |
6902 | { Bad_Opcode }, |
6903 | { Bad_Opcode }, | |
f88c9eb0 SP |
6904 | /* 28 */ |
6905 | { PREFIX_TABLE (PREFIX_0F3828) }, | |
6906 | { PREFIX_TABLE (PREFIX_0F3829) }, | |
6907 | { PREFIX_TABLE (PREFIX_0F382A) }, | |
6908 | { PREFIX_TABLE (PREFIX_0F382B) }, | |
592d1631 L |
6909 | { Bad_Opcode }, |
6910 | { Bad_Opcode }, | |
6911 | { Bad_Opcode }, | |
6912 | { Bad_Opcode }, | |
f88c9eb0 SP |
6913 | /* 30 */ |
6914 | { PREFIX_TABLE (PREFIX_0F3830) }, | |
6915 | { PREFIX_TABLE (PREFIX_0F3831) }, | |
6916 | { PREFIX_TABLE (PREFIX_0F3832) }, | |
6917 | { PREFIX_TABLE (PREFIX_0F3833) }, | |
6918 | { PREFIX_TABLE (PREFIX_0F3834) }, | |
6919 | { PREFIX_TABLE (PREFIX_0F3835) }, | |
592d1631 | 6920 | { Bad_Opcode }, |
f88c9eb0 SP |
6921 | { PREFIX_TABLE (PREFIX_0F3837) }, |
6922 | /* 38 */ | |
6923 | { PREFIX_TABLE (PREFIX_0F3838) }, | |
6924 | { PREFIX_TABLE (PREFIX_0F3839) }, | |
6925 | { PREFIX_TABLE (PREFIX_0F383A) }, | |
6926 | { PREFIX_TABLE (PREFIX_0F383B) }, | |
6927 | { PREFIX_TABLE (PREFIX_0F383C) }, | |
6928 | { PREFIX_TABLE (PREFIX_0F383D) }, | |
6929 | { PREFIX_TABLE (PREFIX_0F383E) }, | |
6930 | { PREFIX_TABLE (PREFIX_0F383F) }, | |
6931 | /* 40 */ | |
6932 | { PREFIX_TABLE (PREFIX_0F3840) }, | |
6933 | { PREFIX_TABLE (PREFIX_0F3841) }, | |
592d1631 L |
6934 | { Bad_Opcode }, |
6935 | { Bad_Opcode }, | |
6936 | { Bad_Opcode }, | |
6937 | { Bad_Opcode }, | |
6938 | { Bad_Opcode }, | |
6939 | { Bad_Opcode }, | |
f88c9eb0 | 6940 | /* 48 */ |
592d1631 L |
6941 | { Bad_Opcode }, |
6942 | { Bad_Opcode }, | |
6943 | { Bad_Opcode }, | |
6944 | { Bad_Opcode }, | |
6945 | { Bad_Opcode }, | |
6946 | { Bad_Opcode }, | |
6947 | { Bad_Opcode }, | |
6948 | { Bad_Opcode }, | |
f88c9eb0 | 6949 | /* 50 */ |
592d1631 L |
6950 | { Bad_Opcode }, |
6951 | { Bad_Opcode }, | |
6952 | { Bad_Opcode }, | |
6953 | { Bad_Opcode }, | |
6954 | { Bad_Opcode }, | |
6955 | { Bad_Opcode }, | |
6956 | { Bad_Opcode }, | |
6957 | { Bad_Opcode }, | |
f88c9eb0 | 6958 | /* 58 */ |
592d1631 L |
6959 | { Bad_Opcode }, |
6960 | { Bad_Opcode }, | |
6961 | { Bad_Opcode }, | |
6962 | { Bad_Opcode }, | |
6963 | { Bad_Opcode }, | |
6964 | { Bad_Opcode }, | |
6965 | { Bad_Opcode }, | |
6966 | { Bad_Opcode }, | |
f88c9eb0 | 6967 | /* 60 */ |
592d1631 L |
6968 | { Bad_Opcode }, |
6969 | { Bad_Opcode }, | |
6970 | { Bad_Opcode }, | |
6971 | { Bad_Opcode }, | |
6972 | { Bad_Opcode }, | |
6973 | { Bad_Opcode }, | |
6974 | { Bad_Opcode }, | |
6975 | { Bad_Opcode }, | |
f88c9eb0 | 6976 | /* 68 */ |
592d1631 L |
6977 | { Bad_Opcode }, |
6978 | { Bad_Opcode }, | |
6979 | { Bad_Opcode }, | |
6980 | { Bad_Opcode }, | |
6981 | { Bad_Opcode }, | |
6982 | { Bad_Opcode }, | |
6983 | { Bad_Opcode }, | |
6984 | { Bad_Opcode }, | |
f88c9eb0 | 6985 | /* 70 */ |
592d1631 L |
6986 | { Bad_Opcode }, |
6987 | { Bad_Opcode }, | |
6988 | { Bad_Opcode }, | |
6989 | { Bad_Opcode }, | |
6990 | { Bad_Opcode }, | |
6991 | { Bad_Opcode }, | |
6992 | { Bad_Opcode }, | |
6993 | { Bad_Opcode }, | |
f88c9eb0 | 6994 | /* 78 */ |
592d1631 L |
6995 | { Bad_Opcode }, |
6996 | { Bad_Opcode }, | |
6997 | { Bad_Opcode }, | |
6998 | { Bad_Opcode }, | |
6999 | { Bad_Opcode }, | |
7000 | { Bad_Opcode }, | |
7001 | { Bad_Opcode }, | |
7002 | { Bad_Opcode }, | |
f88c9eb0 SP |
7003 | /* 80 */ |
7004 | { PREFIX_TABLE (PREFIX_0F3880) }, | |
7005 | { PREFIX_TABLE (PREFIX_0F3881) }, | |
6c30d220 | 7006 | { PREFIX_TABLE (PREFIX_0F3882) }, |
592d1631 L |
7007 | { Bad_Opcode }, |
7008 | { Bad_Opcode }, | |
7009 | { Bad_Opcode }, | |
7010 | { Bad_Opcode }, | |
7011 | { Bad_Opcode }, | |
f88c9eb0 | 7012 | /* 88 */ |
592d1631 L |
7013 | { Bad_Opcode }, |
7014 | { Bad_Opcode }, | |
7015 | { Bad_Opcode }, | |
7016 | { Bad_Opcode }, | |
7017 | { Bad_Opcode }, | |
7018 | { Bad_Opcode }, | |
7019 | { Bad_Opcode }, | |
7020 | { Bad_Opcode }, | |
f88c9eb0 | 7021 | /* 90 */ |
592d1631 L |
7022 | { Bad_Opcode }, |
7023 | { Bad_Opcode }, | |
7024 | { Bad_Opcode }, | |
7025 | { Bad_Opcode }, | |
7026 | { Bad_Opcode }, | |
7027 | { Bad_Opcode }, | |
7028 | { Bad_Opcode }, | |
7029 | { Bad_Opcode }, | |
f88c9eb0 | 7030 | /* 98 */ |
592d1631 L |
7031 | { Bad_Opcode }, |
7032 | { Bad_Opcode }, | |
7033 | { Bad_Opcode }, | |
7034 | { Bad_Opcode }, | |
7035 | { Bad_Opcode }, | |
7036 | { Bad_Opcode }, | |
7037 | { Bad_Opcode }, | |
7038 | { Bad_Opcode }, | |
f88c9eb0 | 7039 | /* a0 */ |
592d1631 L |
7040 | { Bad_Opcode }, |
7041 | { Bad_Opcode }, | |
7042 | { Bad_Opcode }, | |
7043 | { Bad_Opcode }, | |
7044 | { Bad_Opcode }, | |
7045 | { Bad_Opcode }, | |
7046 | { Bad_Opcode }, | |
7047 | { Bad_Opcode }, | |
f88c9eb0 | 7048 | /* a8 */ |
592d1631 L |
7049 | { Bad_Opcode }, |
7050 | { Bad_Opcode }, | |
7051 | { Bad_Opcode }, | |
7052 | { Bad_Opcode }, | |
7053 | { Bad_Opcode }, | |
7054 | { Bad_Opcode }, | |
7055 | { Bad_Opcode }, | |
7056 | { Bad_Opcode }, | |
f88c9eb0 | 7057 | /* b0 */ |
592d1631 L |
7058 | { Bad_Opcode }, |
7059 | { Bad_Opcode }, | |
7060 | { Bad_Opcode }, | |
7061 | { Bad_Opcode }, | |
7062 | { Bad_Opcode }, | |
7063 | { Bad_Opcode }, | |
7064 | { Bad_Opcode }, | |
7065 | { Bad_Opcode }, | |
f88c9eb0 | 7066 | /* b8 */ |
592d1631 L |
7067 | { Bad_Opcode }, |
7068 | { Bad_Opcode }, | |
7069 | { Bad_Opcode }, | |
7070 | { Bad_Opcode }, | |
7071 | { Bad_Opcode }, | |
7072 | { Bad_Opcode }, | |
7073 | { Bad_Opcode }, | |
7074 | { Bad_Opcode }, | |
f88c9eb0 | 7075 | /* c0 */ |
592d1631 L |
7076 | { Bad_Opcode }, |
7077 | { Bad_Opcode }, | |
7078 | { Bad_Opcode }, | |
7079 | { Bad_Opcode }, | |
7080 | { Bad_Opcode }, | |
7081 | { Bad_Opcode }, | |
7082 | { Bad_Opcode }, | |
7083 | { Bad_Opcode }, | |
f88c9eb0 | 7084 | /* c8 */ |
a0046408 L |
7085 | { PREFIX_TABLE (PREFIX_0F38C8) }, |
7086 | { PREFIX_TABLE (PREFIX_0F38C9) }, | |
7087 | { PREFIX_TABLE (PREFIX_0F38CA) }, | |
7088 | { PREFIX_TABLE (PREFIX_0F38CB) }, | |
7089 | { PREFIX_TABLE (PREFIX_0F38CC) }, | |
7090 | { PREFIX_TABLE (PREFIX_0F38CD) }, | |
592d1631 | 7091 | { Bad_Opcode }, |
48521003 | 7092 | { PREFIX_TABLE (PREFIX_0F38CF) }, |
f88c9eb0 | 7093 | /* d0 */ |
592d1631 L |
7094 | { Bad_Opcode }, |
7095 | { Bad_Opcode }, | |
7096 | { Bad_Opcode }, | |
7097 | { Bad_Opcode }, | |
7098 | { Bad_Opcode }, | |
7099 | { Bad_Opcode }, | |
7100 | { Bad_Opcode }, | |
7101 | { Bad_Opcode }, | |
f88c9eb0 | 7102 | /* d8 */ |
592d1631 L |
7103 | { Bad_Opcode }, |
7104 | { Bad_Opcode }, | |
7105 | { Bad_Opcode }, | |
f88c9eb0 SP |
7106 | { PREFIX_TABLE (PREFIX_0F38DB) }, |
7107 | { PREFIX_TABLE (PREFIX_0F38DC) }, | |
7108 | { PREFIX_TABLE (PREFIX_0F38DD) }, | |
7109 | { PREFIX_TABLE (PREFIX_0F38DE) }, | |
7110 | { PREFIX_TABLE (PREFIX_0F38DF) }, | |
7111 | /* e0 */ | |
592d1631 L |
7112 | { Bad_Opcode }, |
7113 | { Bad_Opcode }, | |
7114 | { Bad_Opcode }, | |
7115 | { Bad_Opcode }, | |
7116 | { Bad_Opcode }, | |
7117 | { Bad_Opcode }, | |
7118 | { Bad_Opcode }, | |
7119 | { Bad_Opcode }, | |
f88c9eb0 | 7120 | /* e8 */ |
592d1631 L |
7121 | { Bad_Opcode }, |
7122 | { Bad_Opcode }, | |
7123 | { Bad_Opcode }, | |
7124 | { Bad_Opcode }, | |
7125 | { Bad_Opcode }, | |
7126 | { Bad_Opcode }, | |
7127 | { Bad_Opcode }, | |
7128 | { Bad_Opcode }, | |
f88c9eb0 SP |
7129 | /* f0 */ |
7130 | { PREFIX_TABLE (PREFIX_0F38F0) }, | |
7131 | { PREFIX_TABLE (PREFIX_0F38F1) }, | |
592d1631 L |
7132 | { Bad_Opcode }, |
7133 | { Bad_Opcode }, | |
7134 | { Bad_Opcode }, | |
603555e5 | 7135 | { PREFIX_TABLE (PREFIX_0F38F5) }, |
e2e1fcde | 7136 | { PREFIX_TABLE (PREFIX_0F38F6) }, |
592d1631 | 7137 | { Bad_Opcode }, |
f88c9eb0 | 7138 | /* f8 */ |
c0a30a9f L |
7139 | { PREFIX_TABLE (PREFIX_0F38F8) }, |
7140 | { PREFIX_TABLE (PREFIX_0F38F9) }, | |
592d1631 L |
7141 | { Bad_Opcode }, |
7142 | { Bad_Opcode }, | |
7143 | { Bad_Opcode }, | |
7144 | { Bad_Opcode }, | |
7145 | { Bad_Opcode }, | |
7146 | { Bad_Opcode }, | |
f88c9eb0 SP |
7147 | }, |
7148 | /* THREE_BYTE_0F3A */ | |
7149 | { | |
7150 | /* 00 */ | |
592d1631 L |
7151 | { Bad_Opcode }, |
7152 | { Bad_Opcode }, | |
7153 | { Bad_Opcode }, | |
7154 | { Bad_Opcode }, | |
7155 | { Bad_Opcode }, | |
7156 | { Bad_Opcode }, | |
7157 | { Bad_Opcode }, | |
7158 | { Bad_Opcode }, | |
f88c9eb0 SP |
7159 | /* 08 */ |
7160 | { PREFIX_TABLE (PREFIX_0F3A08) }, | |
7161 | { PREFIX_TABLE (PREFIX_0F3A09) }, | |
7162 | { PREFIX_TABLE (PREFIX_0F3A0A) }, | |
7163 | { PREFIX_TABLE (PREFIX_0F3A0B) }, | |
7164 | { PREFIX_TABLE (PREFIX_0F3A0C) }, | |
7165 | { PREFIX_TABLE (PREFIX_0F3A0D) }, | |
7166 | { PREFIX_TABLE (PREFIX_0F3A0E) }, | |
507bd325 | 7167 | { "palignr", { MX, EM, Ib }, PREFIX_OPCODE }, |
f88c9eb0 | 7168 | /* 10 */ |
592d1631 L |
7169 | { Bad_Opcode }, |
7170 | { Bad_Opcode }, | |
7171 | { Bad_Opcode }, | |
7172 | { Bad_Opcode }, | |
f88c9eb0 SP |
7173 | { PREFIX_TABLE (PREFIX_0F3A14) }, |
7174 | { PREFIX_TABLE (PREFIX_0F3A15) }, | |
7175 | { PREFIX_TABLE (PREFIX_0F3A16) }, | |
7176 | { PREFIX_TABLE (PREFIX_0F3A17) }, | |
7177 | /* 18 */ | |
592d1631 L |
7178 | { Bad_Opcode }, |
7179 | { Bad_Opcode }, | |
7180 | { Bad_Opcode }, | |
7181 | { Bad_Opcode }, | |
7182 | { Bad_Opcode }, | |
7183 | { Bad_Opcode }, | |
7184 | { Bad_Opcode }, | |
7185 | { Bad_Opcode }, | |
f88c9eb0 SP |
7186 | /* 20 */ |
7187 | { PREFIX_TABLE (PREFIX_0F3A20) }, | |
7188 | { PREFIX_TABLE (PREFIX_0F3A21) }, | |
7189 | { PREFIX_TABLE (PREFIX_0F3A22) }, | |
592d1631 L |
7190 | { Bad_Opcode }, |
7191 | { Bad_Opcode }, | |
7192 | { Bad_Opcode }, | |
7193 | { Bad_Opcode }, | |
7194 | { Bad_Opcode }, | |
f88c9eb0 | 7195 | /* 28 */ |
592d1631 L |
7196 | { Bad_Opcode }, |
7197 | { Bad_Opcode }, | |
7198 | { Bad_Opcode }, | |
7199 | { Bad_Opcode }, | |
7200 | { Bad_Opcode }, | |
7201 | { Bad_Opcode }, | |
7202 | { Bad_Opcode }, | |
7203 | { Bad_Opcode }, | |
f88c9eb0 | 7204 | /* 30 */ |
592d1631 L |
7205 | { Bad_Opcode }, |
7206 | { Bad_Opcode }, | |
7207 | { Bad_Opcode }, | |
7208 | { Bad_Opcode }, | |
7209 | { Bad_Opcode }, | |
7210 | { Bad_Opcode }, | |
7211 | { Bad_Opcode }, | |
7212 | { Bad_Opcode }, | |
f88c9eb0 | 7213 | /* 38 */ |
592d1631 L |
7214 | { Bad_Opcode }, |
7215 | { Bad_Opcode }, | |
7216 | { Bad_Opcode }, | |
7217 | { Bad_Opcode }, | |
7218 | { Bad_Opcode }, | |
7219 | { Bad_Opcode }, | |
7220 | { Bad_Opcode }, | |
7221 | { Bad_Opcode }, | |
f88c9eb0 SP |
7222 | /* 40 */ |
7223 | { PREFIX_TABLE (PREFIX_0F3A40) }, | |
7224 | { PREFIX_TABLE (PREFIX_0F3A41) }, | |
7225 | { PREFIX_TABLE (PREFIX_0F3A42) }, | |
592d1631 | 7226 | { Bad_Opcode }, |
f88c9eb0 | 7227 | { PREFIX_TABLE (PREFIX_0F3A44) }, |
592d1631 L |
7228 | { Bad_Opcode }, |
7229 | { Bad_Opcode }, | |
7230 | { Bad_Opcode }, | |
f88c9eb0 | 7231 | /* 48 */ |
592d1631 L |
7232 | { Bad_Opcode }, |
7233 | { Bad_Opcode }, | |
7234 | { Bad_Opcode }, | |
7235 | { Bad_Opcode }, | |
7236 | { Bad_Opcode }, | |
7237 | { Bad_Opcode }, | |
7238 | { Bad_Opcode }, | |
7239 | { Bad_Opcode }, | |
f88c9eb0 | 7240 | /* 50 */ |
592d1631 L |
7241 | { Bad_Opcode }, |
7242 | { Bad_Opcode }, | |
7243 | { Bad_Opcode }, | |
7244 | { Bad_Opcode }, | |
7245 | { Bad_Opcode }, | |
7246 | { Bad_Opcode }, | |
7247 | { Bad_Opcode }, | |
7248 | { Bad_Opcode }, | |
f88c9eb0 | 7249 | /* 58 */ |
592d1631 L |
7250 | { Bad_Opcode }, |
7251 | { Bad_Opcode }, | |
7252 | { Bad_Opcode }, | |
7253 | { Bad_Opcode }, | |
7254 | { Bad_Opcode }, | |
7255 | { Bad_Opcode }, | |
7256 | { Bad_Opcode }, | |
7257 | { Bad_Opcode }, | |
f88c9eb0 SP |
7258 | /* 60 */ |
7259 | { PREFIX_TABLE (PREFIX_0F3A60) }, | |
7260 | { PREFIX_TABLE (PREFIX_0F3A61) }, | |
7261 | { PREFIX_TABLE (PREFIX_0F3A62) }, | |
7262 | { PREFIX_TABLE (PREFIX_0F3A63) }, | |
592d1631 L |
7263 | { Bad_Opcode }, |
7264 | { Bad_Opcode }, | |
7265 | { Bad_Opcode }, | |
7266 | { Bad_Opcode }, | |
f88c9eb0 | 7267 | /* 68 */ |
592d1631 L |
7268 | { Bad_Opcode }, |
7269 | { Bad_Opcode }, | |
7270 | { Bad_Opcode }, | |
7271 | { Bad_Opcode }, | |
7272 | { Bad_Opcode }, | |
7273 | { Bad_Opcode }, | |
7274 | { Bad_Opcode }, | |
7275 | { Bad_Opcode }, | |
f88c9eb0 | 7276 | /* 70 */ |
592d1631 L |
7277 | { Bad_Opcode }, |
7278 | { Bad_Opcode }, | |
7279 | { Bad_Opcode }, | |
7280 | { Bad_Opcode }, | |
7281 | { Bad_Opcode }, | |
7282 | { Bad_Opcode }, | |
7283 | { Bad_Opcode }, | |
7284 | { Bad_Opcode }, | |
f88c9eb0 | 7285 | /* 78 */ |
592d1631 L |
7286 | { Bad_Opcode }, |
7287 | { Bad_Opcode }, | |
7288 | { Bad_Opcode }, | |
7289 | { Bad_Opcode }, | |
7290 | { Bad_Opcode }, | |
7291 | { Bad_Opcode }, | |
7292 | { Bad_Opcode }, | |
7293 | { Bad_Opcode }, | |
f88c9eb0 | 7294 | /* 80 */ |
592d1631 L |
7295 | { Bad_Opcode }, |
7296 | { Bad_Opcode }, | |
7297 | { Bad_Opcode }, | |
7298 | { Bad_Opcode }, | |
7299 | { Bad_Opcode }, | |
7300 | { Bad_Opcode }, | |
7301 | { Bad_Opcode }, | |
7302 | { Bad_Opcode }, | |
f88c9eb0 | 7303 | /* 88 */ |
592d1631 L |
7304 | { Bad_Opcode }, |
7305 | { Bad_Opcode }, | |
7306 | { Bad_Opcode }, | |
7307 | { Bad_Opcode }, | |
7308 | { Bad_Opcode }, | |
7309 | { Bad_Opcode }, | |
7310 | { Bad_Opcode }, | |
7311 | { Bad_Opcode }, | |
f88c9eb0 | 7312 | /* 90 */ |
592d1631 L |
7313 | { Bad_Opcode }, |
7314 | { Bad_Opcode }, | |
7315 | { Bad_Opcode }, | |
7316 | { Bad_Opcode }, | |
7317 | { Bad_Opcode }, | |
7318 | { Bad_Opcode }, | |
7319 | { Bad_Opcode }, | |
7320 | { Bad_Opcode }, | |
f88c9eb0 | 7321 | /* 98 */ |
592d1631 L |
7322 | { Bad_Opcode }, |
7323 | { Bad_Opcode }, | |
7324 | { Bad_Opcode }, | |
7325 | { Bad_Opcode }, | |
7326 | { Bad_Opcode }, | |
7327 | { Bad_Opcode }, | |
7328 | { Bad_Opcode }, | |
7329 | { Bad_Opcode }, | |
f88c9eb0 | 7330 | /* a0 */ |
592d1631 L |
7331 | { Bad_Opcode }, |
7332 | { Bad_Opcode }, | |
7333 | { Bad_Opcode }, | |
7334 | { Bad_Opcode }, | |
7335 | { Bad_Opcode }, | |
7336 | { Bad_Opcode }, | |
7337 | { Bad_Opcode }, | |
7338 | { Bad_Opcode }, | |
f88c9eb0 | 7339 | /* a8 */ |
592d1631 L |
7340 | { Bad_Opcode }, |
7341 | { Bad_Opcode }, | |
7342 | { Bad_Opcode }, | |
7343 | { Bad_Opcode }, | |
7344 | { Bad_Opcode }, | |
7345 | { Bad_Opcode }, | |
7346 | { Bad_Opcode }, | |
7347 | { Bad_Opcode }, | |
f88c9eb0 | 7348 | /* b0 */ |
592d1631 L |
7349 | { Bad_Opcode }, |
7350 | { Bad_Opcode }, | |
7351 | { Bad_Opcode }, | |
7352 | { Bad_Opcode }, | |
7353 | { Bad_Opcode }, | |
7354 | { Bad_Opcode }, | |
7355 | { Bad_Opcode }, | |
7356 | { Bad_Opcode }, | |
f88c9eb0 | 7357 | /* b8 */ |
592d1631 L |
7358 | { Bad_Opcode }, |
7359 | { Bad_Opcode }, | |
7360 | { Bad_Opcode }, | |
7361 | { Bad_Opcode }, | |
7362 | { Bad_Opcode }, | |
7363 | { Bad_Opcode }, | |
7364 | { Bad_Opcode }, | |
7365 | { Bad_Opcode }, | |
f88c9eb0 | 7366 | /* c0 */ |
592d1631 L |
7367 | { Bad_Opcode }, |
7368 | { Bad_Opcode }, | |
7369 | { Bad_Opcode }, | |
7370 | { Bad_Opcode }, | |
7371 | { Bad_Opcode }, | |
7372 | { Bad_Opcode }, | |
7373 | { Bad_Opcode }, | |
7374 | { Bad_Opcode }, | |
f88c9eb0 | 7375 | /* c8 */ |
592d1631 L |
7376 | { Bad_Opcode }, |
7377 | { Bad_Opcode }, | |
7378 | { Bad_Opcode }, | |
7379 | { Bad_Opcode }, | |
a0046408 | 7380 | { PREFIX_TABLE (PREFIX_0F3ACC) }, |
592d1631 | 7381 | { Bad_Opcode }, |
48521003 IT |
7382 | { PREFIX_TABLE (PREFIX_0F3ACE) }, |
7383 | { PREFIX_TABLE (PREFIX_0F3ACF) }, | |
f88c9eb0 | 7384 | /* d0 */ |
592d1631 L |
7385 | { Bad_Opcode }, |
7386 | { Bad_Opcode }, | |
7387 | { Bad_Opcode }, | |
7388 | { Bad_Opcode }, | |
7389 | { Bad_Opcode }, | |
7390 | { Bad_Opcode }, | |
7391 | { Bad_Opcode }, | |
7392 | { Bad_Opcode }, | |
f88c9eb0 | 7393 | /* d8 */ |
592d1631 L |
7394 | { Bad_Opcode }, |
7395 | { Bad_Opcode }, | |
7396 | { Bad_Opcode }, | |
7397 | { Bad_Opcode }, | |
7398 | { Bad_Opcode }, | |
7399 | { Bad_Opcode }, | |
7400 | { Bad_Opcode }, | |
f88c9eb0 SP |
7401 | { PREFIX_TABLE (PREFIX_0F3ADF) }, |
7402 | /* e0 */ | |
592d1631 L |
7403 | { Bad_Opcode }, |
7404 | { Bad_Opcode }, | |
7405 | { Bad_Opcode }, | |
7406 | { Bad_Opcode }, | |
7407 | { Bad_Opcode }, | |
592d1631 L |
7408 | { Bad_Opcode }, |
7409 | { Bad_Opcode }, | |
7410 | { Bad_Opcode }, | |
85f10a01 | 7411 | /* e8 */ |
592d1631 L |
7412 | { Bad_Opcode }, |
7413 | { Bad_Opcode }, | |
7414 | { Bad_Opcode }, | |
7415 | { Bad_Opcode }, | |
7416 | { Bad_Opcode }, | |
7417 | { Bad_Opcode }, | |
7418 | { Bad_Opcode }, | |
7419 | { Bad_Opcode }, | |
85f10a01 | 7420 | /* f0 */ |
592d1631 L |
7421 | { Bad_Opcode }, |
7422 | { Bad_Opcode }, | |
7423 | { Bad_Opcode }, | |
7424 | { Bad_Opcode }, | |
7425 | { Bad_Opcode }, | |
7426 | { Bad_Opcode }, | |
7427 | { Bad_Opcode }, | |
7428 | { Bad_Opcode }, | |
85f10a01 | 7429 | /* f8 */ |
592d1631 L |
7430 | { Bad_Opcode }, |
7431 | { Bad_Opcode }, | |
7432 | { Bad_Opcode }, | |
7433 | { Bad_Opcode }, | |
7434 | { Bad_Opcode }, | |
7435 | { Bad_Opcode }, | |
7436 | { Bad_Opcode }, | |
7437 | { Bad_Opcode }, | |
85f10a01 | 7438 | }, |
f88c9eb0 SP |
7439 | }; |
7440 | ||
7441 | static const struct dis386 xop_table[][256] = { | |
5dd85c99 | 7442 | /* XOP_08 */ |
85f10a01 MM |
7443 | { |
7444 | /* 00 */ | |
592d1631 L |
7445 | { Bad_Opcode }, |
7446 | { Bad_Opcode }, | |
7447 | { Bad_Opcode }, | |
7448 | { Bad_Opcode }, | |
7449 | { Bad_Opcode }, | |
7450 | { Bad_Opcode }, | |
7451 | { Bad_Opcode }, | |
7452 | { Bad_Opcode }, | |
85f10a01 | 7453 | /* 08 */ |
592d1631 L |
7454 | { Bad_Opcode }, |
7455 | { Bad_Opcode }, | |
7456 | { Bad_Opcode }, | |
7457 | { Bad_Opcode }, | |
7458 | { Bad_Opcode }, | |
7459 | { Bad_Opcode }, | |
7460 | { Bad_Opcode }, | |
7461 | { Bad_Opcode }, | |
85f10a01 | 7462 | /* 10 */ |
3929df09 | 7463 | { Bad_Opcode }, |
592d1631 L |
7464 | { Bad_Opcode }, |
7465 | { Bad_Opcode }, | |
7466 | { Bad_Opcode }, | |
7467 | { Bad_Opcode }, | |
7468 | { Bad_Opcode }, | |
7469 | { Bad_Opcode }, | |
7470 | { Bad_Opcode }, | |
85f10a01 | 7471 | /* 18 */ |
592d1631 L |
7472 | { Bad_Opcode }, |
7473 | { Bad_Opcode }, | |
7474 | { Bad_Opcode }, | |
7475 | { Bad_Opcode }, | |
7476 | { Bad_Opcode }, | |
7477 | { Bad_Opcode }, | |
7478 | { Bad_Opcode }, | |
7479 | { Bad_Opcode }, | |
85f10a01 | 7480 | /* 20 */ |
592d1631 L |
7481 | { Bad_Opcode }, |
7482 | { Bad_Opcode }, | |
7483 | { Bad_Opcode }, | |
7484 | { Bad_Opcode }, | |
7485 | { Bad_Opcode }, | |
7486 | { Bad_Opcode }, | |
7487 | { Bad_Opcode }, | |
7488 | { Bad_Opcode }, | |
85f10a01 | 7489 | /* 28 */ |
592d1631 L |
7490 | { Bad_Opcode }, |
7491 | { Bad_Opcode }, | |
7492 | { Bad_Opcode }, | |
7493 | { Bad_Opcode }, | |
7494 | { Bad_Opcode }, | |
7495 | { Bad_Opcode }, | |
7496 | { Bad_Opcode }, | |
7497 | { Bad_Opcode }, | |
c0f3af97 | 7498 | /* 30 */ |
592d1631 L |
7499 | { Bad_Opcode }, |
7500 | { Bad_Opcode }, | |
7501 | { Bad_Opcode }, | |
7502 | { Bad_Opcode }, | |
7503 | { Bad_Opcode }, | |
7504 | { Bad_Opcode }, | |
7505 | { Bad_Opcode }, | |
7506 | { Bad_Opcode }, | |
c0f3af97 | 7507 | /* 38 */ |
592d1631 L |
7508 | { Bad_Opcode }, |
7509 | { Bad_Opcode }, | |
7510 | { Bad_Opcode }, | |
7511 | { Bad_Opcode }, | |
7512 | { Bad_Opcode }, | |
7513 | { Bad_Opcode }, | |
7514 | { Bad_Opcode }, | |
7515 | { Bad_Opcode }, | |
c0f3af97 | 7516 | /* 40 */ |
592d1631 L |
7517 | { Bad_Opcode }, |
7518 | { Bad_Opcode }, | |
7519 | { Bad_Opcode }, | |
7520 | { Bad_Opcode }, | |
7521 | { Bad_Opcode }, | |
7522 | { Bad_Opcode }, | |
7523 | { Bad_Opcode }, | |
7524 | { Bad_Opcode }, | |
85f10a01 | 7525 | /* 48 */ |
592d1631 L |
7526 | { Bad_Opcode }, |
7527 | { Bad_Opcode }, | |
7528 | { Bad_Opcode }, | |
7529 | { Bad_Opcode }, | |
7530 | { Bad_Opcode }, | |
7531 | { Bad_Opcode }, | |
7532 | { Bad_Opcode }, | |
7533 | { Bad_Opcode }, | |
c0f3af97 | 7534 | /* 50 */ |
592d1631 L |
7535 | { Bad_Opcode }, |
7536 | { Bad_Opcode }, | |
7537 | { Bad_Opcode }, | |
7538 | { Bad_Opcode }, | |
7539 | { Bad_Opcode }, | |
7540 | { Bad_Opcode }, | |
7541 | { Bad_Opcode }, | |
7542 | { Bad_Opcode }, | |
85f10a01 | 7543 | /* 58 */ |
592d1631 L |
7544 | { Bad_Opcode }, |
7545 | { Bad_Opcode }, | |
7546 | { Bad_Opcode }, | |
7547 | { Bad_Opcode }, | |
7548 | { Bad_Opcode }, | |
7549 | { Bad_Opcode }, | |
7550 | { Bad_Opcode }, | |
7551 | { Bad_Opcode }, | |
c1e679ec | 7552 | /* 60 */ |
592d1631 L |
7553 | { Bad_Opcode }, |
7554 | { Bad_Opcode }, | |
7555 | { Bad_Opcode }, | |
7556 | { Bad_Opcode }, | |
7557 | { Bad_Opcode }, | |
7558 | { Bad_Opcode }, | |
7559 | { Bad_Opcode }, | |
7560 | { Bad_Opcode }, | |
c0f3af97 | 7561 | /* 68 */ |
592d1631 L |
7562 | { Bad_Opcode }, |
7563 | { Bad_Opcode }, | |
7564 | { Bad_Opcode }, | |
7565 | { Bad_Opcode }, | |
7566 | { Bad_Opcode }, | |
7567 | { Bad_Opcode }, | |
7568 | { Bad_Opcode }, | |
7569 | { Bad_Opcode }, | |
85f10a01 | 7570 | /* 70 */ |
592d1631 L |
7571 | { Bad_Opcode }, |
7572 | { Bad_Opcode }, | |
7573 | { Bad_Opcode }, | |
7574 | { Bad_Opcode }, | |
7575 | { Bad_Opcode }, | |
7576 | { Bad_Opcode }, | |
7577 | { Bad_Opcode }, | |
7578 | { Bad_Opcode }, | |
85f10a01 | 7579 | /* 78 */ |
592d1631 L |
7580 | { Bad_Opcode }, |
7581 | { Bad_Opcode }, | |
7582 | { Bad_Opcode }, | |
7583 | { Bad_Opcode }, | |
7584 | { Bad_Opcode }, | |
7585 | { Bad_Opcode }, | |
7586 | { Bad_Opcode }, | |
7587 | { Bad_Opcode }, | |
85f10a01 | 7588 | /* 80 */ |
592d1631 L |
7589 | { Bad_Opcode }, |
7590 | { Bad_Opcode }, | |
7591 | { Bad_Opcode }, | |
7592 | { Bad_Opcode }, | |
7593 | { Bad_Opcode }, | |
3a2430e0 JB |
7594 | { "vpmacssww", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
7595 | { "vpmacsswd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, | |
7596 | { "vpmacssdql", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, | |
5dd85c99 | 7597 | /* 88 */ |
592d1631 L |
7598 | { Bad_Opcode }, |
7599 | { Bad_Opcode }, | |
7600 | { Bad_Opcode }, | |
7601 | { Bad_Opcode }, | |
7602 | { Bad_Opcode }, | |
7603 | { Bad_Opcode }, | |
3a2430e0 JB |
7604 | { "vpmacssdd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
7605 | { "vpmacssdqh", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, | |
5dd85c99 | 7606 | /* 90 */ |
592d1631 L |
7607 | { Bad_Opcode }, |
7608 | { Bad_Opcode }, | |
7609 | { Bad_Opcode }, | |
7610 | { Bad_Opcode }, | |
7611 | { Bad_Opcode }, | |
3a2430e0 JB |
7612 | { "vpmacsww", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
7613 | { "vpmacswd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, | |
7614 | { "vpmacsdql", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, | |
5dd85c99 | 7615 | /* 98 */ |
592d1631 L |
7616 | { Bad_Opcode }, |
7617 | { Bad_Opcode }, | |
7618 | { Bad_Opcode }, | |
7619 | { Bad_Opcode }, | |
7620 | { Bad_Opcode }, | |
7621 | { Bad_Opcode }, | |
3a2430e0 JB |
7622 | { "vpmacsdd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
7623 | { "vpmacsdqh", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, | |
5dd85c99 | 7624 | /* a0 */ |
592d1631 L |
7625 | { Bad_Opcode }, |
7626 | { Bad_Opcode }, | |
3a2430e0 JB |
7627 | { "vpcmov", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
7628 | { "vpperm", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, | |
592d1631 L |
7629 | { Bad_Opcode }, |
7630 | { Bad_Opcode }, | |
3a2430e0 | 7631 | { "vpmadcsswd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
592d1631 | 7632 | { Bad_Opcode }, |
5dd85c99 | 7633 | /* a8 */ |
592d1631 L |
7634 | { Bad_Opcode }, |
7635 | { Bad_Opcode }, | |
7636 | { Bad_Opcode }, | |
7637 | { Bad_Opcode }, | |
7638 | { Bad_Opcode }, | |
7639 | { Bad_Opcode }, | |
7640 | { Bad_Opcode }, | |
7641 | { Bad_Opcode }, | |
5dd85c99 | 7642 | /* b0 */ |
592d1631 L |
7643 | { Bad_Opcode }, |
7644 | { Bad_Opcode }, | |
7645 | { Bad_Opcode }, | |
7646 | { Bad_Opcode }, | |
7647 | { Bad_Opcode }, | |
7648 | { Bad_Opcode }, | |
3a2430e0 | 7649 | { "vpmadcswd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
592d1631 | 7650 | { Bad_Opcode }, |
5dd85c99 | 7651 | /* b8 */ |
592d1631 L |
7652 | { Bad_Opcode }, |
7653 | { Bad_Opcode }, | |
7654 | { Bad_Opcode }, | |
7655 | { Bad_Opcode }, | |
7656 | { Bad_Opcode }, | |
7657 | { Bad_Opcode }, | |
7658 | { Bad_Opcode }, | |
7659 | { Bad_Opcode }, | |
5dd85c99 | 7660 | /* c0 */ |
bf890a93 IT |
7661 | { "vprotb", { XM, Vex_2src_1, Ib }, 0 }, |
7662 | { "vprotw", { XM, Vex_2src_1, Ib }, 0 }, | |
7663 | { "vprotd", { XM, Vex_2src_1, Ib }, 0 }, | |
7664 | { "vprotq", { XM, Vex_2src_1, Ib }, 0 }, | |
592d1631 L |
7665 | { Bad_Opcode }, |
7666 | { Bad_Opcode }, | |
7667 | { Bad_Opcode }, | |
7668 | { Bad_Opcode }, | |
5dd85c99 | 7669 | /* c8 */ |
592d1631 L |
7670 | { Bad_Opcode }, |
7671 | { Bad_Opcode }, | |
7672 | { Bad_Opcode }, | |
7673 | { Bad_Opcode }, | |
ff688e1f L |
7674 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) }, |
7675 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) }, | |
7676 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) }, | |
7677 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) }, | |
5dd85c99 | 7678 | /* d0 */ |
592d1631 L |
7679 | { Bad_Opcode }, |
7680 | { Bad_Opcode }, | |
7681 | { Bad_Opcode }, | |
7682 | { Bad_Opcode }, | |
7683 | { Bad_Opcode }, | |
7684 | { Bad_Opcode }, | |
7685 | { Bad_Opcode }, | |
7686 | { Bad_Opcode }, | |
5dd85c99 | 7687 | /* d8 */ |
592d1631 L |
7688 | { Bad_Opcode }, |
7689 | { Bad_Opcode }, | |
7690 | { Bad_Opcode }, | |
7691 | { Bad_Opcode }, | |
7692 | { Bad_Opcode }, | |
7693 | { Bad_Opcode }, | |
7694 | { Bad_Opcode }, | |
7695 | { Bad_Opcode }, | |
5dd85c99 | 7696 | /* e0 */ |
592d1631 L |
7697 | { Bad_Opcode }, |
7698 | { Bad_Opcode }, | |
7699 | { Bad_Opcode }, | |
7700 | { Bad_Opcode }, | |
7701 | { Bad_Opcode }, | |
7702 | { Bad_Opcode }, | |
7703 | { Bad_Opcode }, | |
7704 | { Bad_Opcode }, | |
5dd85c99 | 7705 | /* e8 */ |
592d1631 L |
7706 | { Bad_Opcode }, |
7707 | { Bad_Opcode }, | |
7708 | { Bad_Opcode }, | |
7709 | { Bad_Opcode }, | |
ff688e1f L |
7710 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) }, |
7711 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) }, | |
7712 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) }, | |
7713 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) }, | |
5dd85c99 | 7714 | /* f0 */ |
592d1631 L |
7715 | { Bad_Opcode }, |
7716 | { Bad_Opcode }, | |
7717 | { Bad_Opcode }, | |
7718 | { Bad_Opcode }, | |
7719 | { Bad_Opcode }, | |
7720 | { Bad_Opcode }, | |
7721 | { Bad_Opcode }, | |
7722 | { Bad_Opcode }, | |
5dd85c99 | 7723 | /* f8 */ |
592d1631 L |
7724 | { Bad_Opcode }, |
7725 | { Bad_Opcode }, | |
7726 | { Bad_Opcode }, | |
7727 | { Bad_Opcode }, | |
7728 | { Bad_Opcode }, | |
7729 | { Bad_Opcode }, | |
7730 | { Bad_Opcode }, | |
7731 | { Bad_Opcode }, | |
5dd85c99 SP |
7732 | }, |
7733 | /* XOP_09 */ | |
7734 | { | |
7735 | /* 00 */ | |
592d1631 | 7736 | { Bad_Opcode }, |
2a2a0f38 QN |
7737 | { REG_TABLE (REG_XOP_TBM_01) }, |
7738 | { REG_TABLE (REG_XOP_TBM_02) }, | |
592d1631 L |
7739 | { Bad_Opcode }, |
7740 | { Bad_Opcode }, | |
7741 | { Bad_Opcode }, | |
7742 | { Bad_Opcode }, | |
7743 | { Bad_Opcode }, | |
5dd85c99 | 7744 | /* 08 */ |
592d1631 L |
7745 | { Bad_Opcode }, |
7746 | { Bad_Opcode }, | |
7747 | { Bad_Opcode }, | |
7748 | { Bad_Opcode }, | |
7749 | { Bad_Opcode }, | |
7750 | { Bad_Opcode }, | |
7751 | { Bad_Opcode }, | |
7752 | { Bad_Opcode }, | |
5dd85c99 | 7753 | /* 10 */ |
592d1631 L |
7754 | { Bad_Opcode }, |
7755 | { Bad_Opcode }, | |
5dd85c99 | 7756 | { REG_TABLE (REG_XOP_LWPCB) }, |
592d1631 L |
7757 | { Bad_Opcode }, |
7758 | { Bad_Opcode }, | |
7759 | { Bad_Opcode }, | |
7760 | { Bad_Opcode }, | |
7761 | { Bad_Opcode }, | |
5dd85c99 | 7762 | /* 18 */ |
592d1631 L |
7763 | { Bad_Opcode }, |
7764 | { Bad_Opcode }, | |
7765 | { Bad_Opcode }, | |
7766 | { Bad_Opcode }, | |
7767 | { Bad_Opcode }, | |
7768 | { Bad_Opcode }, | |
7769 | { Bad_Opcode }, | |
7770 | { Bad_Opcode }, | |
5dd85c99 | 7771 | /* 20 */ |
592d1631 L |
7772 | { Bad_Opcode }, |
7773 | { Bad_Opcode }, | |
7774 | { Bad_Opcode }, | |
7775 | { Bad_Opcode }, | |
7776 | { Bad_Opcode }, | |
7777 | { Bad_Opcode }, | |
7778 | { Bad_Opcode }, | |
7779 | { Bad_Opcode }, | |
5dd85c99 | 7780 | /* 28 */ |
592d1631 L |
7781 | { Bad_Opcode }, |
7782 | { Bad_Opcode }, | |
7783 | { Bad_Opcode }, | |
7784 | { Bad_Opcode }, | |
7785 | { Bad_Opcode }, | |
7786 | { Bad_Opcode }, | |
7787 | { Bad_Opcode }, | |
7788 | { Bad_Opcode }, | |
5dd85c99 | 7789 | /* 30 */ |
592d1631 L |
7790 | { Bad_Opcode }, |
7791 | { Bad_Opcode }, | |
7792 | { Bad_Opcode }, | |
7793 | { Bad_Opcode }, | |
7794 | { Bad_Opcode }, | |
7795 | { Bad_Opcode }, | |
7796 | { Bad_Opcode }, | |
7797 | { Bad_Opcode }, | |
5dd85c99 | 7798 | /* 38 */ |
592d1631 L |
7799 | { Bad_Opcode }, |
7800 | { Bad_Opcode }, | |
7801 | { Bad_Opcode }, | |
7802 | { Bad_Opcode }, | |
7803 | { Bad_Opcode }, | |
7804 | { Bad_Opcode }, | |
7805 | { Bad_Opcode }, | |
7806 | { Bad_Opcode }, | |
5dd85c99 | 7807 | /* 40 */ |
592d1631 L |
7808 | { Bad_Opcode }, |
7809 | { Bad_Opcode }, | |
7810 | { Bad_Opcode }, | |
7811 | { Bad_Opcode }, | |
7812 | { Bad_Opcode }, | |
7813 | { Bad_Opcode }, | |
7814 | { Bad_Opcode }, | |
7815 | { Bad_Opcode }, | |
5dd85c99 | 7816 | /* 48 */ |
592d1631 L |
7817 | { Bad_Opcode }, |
7818 | { Bad_Opcode }, | |
7819 | { Bad_Opcode }, | |
7820 | { Bad_Opcode }, | |
7821 | { Bad_Opcode }, | |
7822 | { Bad_Opcode }, | |
7823 | { Bad_Opcode }, | |
7824 | { Bad_Opcode }, | |
5dd85c99 | 7825 | /* 50 */ |
592d1631 L |
7826 | { Bad_Opcode }, |
7827 | { Bad_Opcode }, | |
7828 | { Bad_Opcode }, | |
7829 | { Bad_Opcode }, | |
7830 | { Bad_Opcode }, | |
7831 | { Bad_Opcode }, | |
7832 | { Bad_Opcode }, | |
7833 | { Bad_Opcode }, | |
5dd85c99 | 7834 | /* 58 */ |
592d1631 L |
7835 | { Bad_Opcode }, |
7836 | { Bad_Opcode }, | |
7837 | { Bad_Opcode }, | |
7838 | { Bad_Opcode }, | |
7839 | { Bad_Opcode }, | |
7840 | { Bad_Opcode }, | |
7841 | { Bad_Opcode }, | |
7842 | { Bad_Opcode }, | |
5dd85c99 | 7843 | /* 60 */ |
592d1631 L |
7844 | { Bad_Opcode }, |
7845 | { Bad_Opcode }, | |
7846 | { Bad_Opcode }, | |
7847 | { Bad_Opcode }, | |
7848 | { Bad_Opcode }, | |
7849 | { Bad_Opcode }, | |
7850 | { Bad_Opcode }, | |
7851 | { Bad_Opcode }, | |
5dd85c99 | 7852 | /* 68 */ |
592d1631 L |
7853 | { Bad_Opcode }, |
7854 | { Bad_Opcode }, | |
7855 | { Bad_Opcode }, | |
7856 | { Bad_Opcode }, | |
7857 | { Bad_Opcode }, | |
7858 | { Bad_Opcode }, | |
7859 | { Bad_Opcode }, | |
7860 | { Bad_Opcode }, | |
5dd85c99 | 7861 | /* 70 */ |
592d1631 L |
7862 | { Bad_Opcode }, |
7863 | { Bad_Opcode }, | |
7864 | { Bad_Opcode }, | |
7865 | { Bad_Opcode }, | |
7866 | { Bad_Opcode }, | |
7867 | { Bad_Opcode }, | |
7868 | { Bad_Opcode }, | |
7869 | { Bad_Opcode }, | |
5dd85c99 | 7870 | /* 78 */ |
592d1631 L |
7871 | { Bad_Opcode }, |
7872 | { Bad_Opcode }, | |
7873 | { Bad_Opcode }, | |
7874 | { Bad_Opcode }, | |
7875 | { Bad_Opcode }, | |
7876 | { Bad_Opcode }, | |
7877 | { Bad_Opcode }, | |
7878 | { Bad_Opcode }, | |
5dd85c99 | 7879 | /* 80 */ |
592a252b L |
7880 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) }, |
7881 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) }, | |
bf890a93 IT |
7882 | { "vfrczss", { XM, EXd }, 0 }, |
7883 | { "vfrczsd", { XM, EXq }, 0 }, | |
592d1631 L |
7884 | { Bad_Opcode }, |
7885 | { Bad_Opcode }, | |
7886 | { Bad_Opcode }, | |
7887 | { Bad_Opcode }, | |
5dd85c99 | 7888 | /* 88 */ |
592d1631 L |
7889 | { Bad_Opcode }, |
7890 | { Bad_Opcode }, | |
7891 | { Bad_Opcode }, | |
7892 | { Bad_Opcode }, | |
7893 | { Bad_Opcode }, | |
7894 | { Bad_Opcode }, | |
7895 | { Bad_Opcode }, | |
7896 | { Bad_Opcode }, | |
5dd85c99 | 7897 | /* 90 */ |
bf890a93 IT |
7898 | { "vprotb", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, |
7899 | { "vprotw", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
7900 | { "vprotd", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
7901 | { "vprotq", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
7902 | { "vpshlb", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
7903 | { "vpshlw", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
7904 | { "vpshld", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
7905 | { "vpshlq", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
5dd85c99 | 7906 | /* 98 */ |
bf890a93 IT |
7907 | { "vpshab", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, |
7908 | { "vpshaw", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
7909 | { "vpshad", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
7910 | { "vpshaq", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
592d1631 L |
7911 | { Bad_Opcode }, |
7912 | { Bad_Opcode }, | |
7913 | { Bad_Opcode }, | |
7914 | { Bad_Opcode }, | |
5dd85c99 | 7915 | /* a0 */ |
592d1631 L |
7916 | { Bad_Opcode }, |
7917 | { Bad_Opcode }, | |
7918 | { Bad_Opcode }, | |
7919 | { Bad_Opcode }, | |
7920 | { Bad_Opcode }, | |
7921 | { Bad_Opcode }, | |
7922 | { Bad_Opcode }, | |
7923 | { Bad_Opcode }, | |
5dd85c99 | 7924 | /* a8 */ |
592d1631 L |
7925 | { Bad_Opcode }, |
7926 | { Bad_Opcode }, | |
7927 | { Bad_Opcode }, | |
7928 | { Bad_Opcode }, | |
7929 | { Bad_Opcode }, | |
7930 | { Bad_Opcode }, | |
7931 | { Bad_Opcode }, | |
7932 | { Bad_Opcode }, | |
5dd85c99 | 7933 | /* b0 */ |
592d1631 L |
7934 | { Bad_Opcode }, |
7935 | { Bad_Opcode }, | |
7936 | { Bad_Opcode }, | |
7937 | { Bad_Opcode }, | |
7938 | { Bad_Opcode }, | |
7939 | { Bad_Opcode }, | |
7940 | { Bad_Opcode }, | |
7941 | { Bad_Opcode }, | |
5dd85c99 | 7942 | /* b8 */ |
592d1631 L |
7943 | { Bad_Opcode }, |
7944 | { Bad_Opcode }, | |
7945 | { Bad_Opcode }, | |
7946 | { Bad_Opcode }, | |
7947 | { Bad_Opcode }, | |
7948 | { Bad_Opcode }, | |
7949 | { Bad_Opcode }, | |
7950 | { Bad_Opcode }, | |
5dd85c99 | 7951 | /* c0 */ |
592d1631 | 7952 | { Bad_Opcode }, |
bf890a93 IT |
7953 | { "vphaddbw", { XM, EXxmm }, 0 }, |
7954 | { "vphaddbd", { XM, EXxmm }, 0 }, | |
7955 | { "vphaddbq", { XM, EXxmm }, 0 }, | |
592d1631 L |
7956 | { Bad_Opcode }, |
7957 | { Bad_Opcode }, | |
bf890a93 IT |
7958 | { "vphaddwd", { XM, EXxmm }, 0 }, |
7959 | { "vphaddwq", { XM, EXxmm }, 0 }, | |
5dd85c99 | 7960 | /* c8 */ |
592d1631 L |
7961 | { Bad_Opcode }, |
7962 | { Bad_Opcode }, | |
7963 | { Bad_Opcode }, | |
bf890a93 | 7964 | { "vphadddq", { XM, EXxmm }, 0 }, |
592d1631 L |
7965 | { Bad_Opcode }, |
7966 | { Bad_Opcode }, | |
7967 | { Bad_Opcode }, | |
7968 | { Bad_Opcode }, | |
5dd85c99 | 7969 | /* d0 */ |
592d1631 | 7970 | { Bad_Opcode }, |
bf890a93 IT |
7971 | { "vphaddubw", { XM, EXxmm }, 0 }, |
7972 | { "vphaddubd", { XM, EXxmm }, 0 }, | |
7973 | { "vphaddubq", { XM, EXxmm }, 0 }, | |
592d1631 L |
7974 | { Bad_Opcode }, |
7975 | { Bad_Opcode }, | |
bf890a93 IT |
7976 | { "vphadduwd", { XM, EXxmm }, 0 }, |
7977 | { "vphadduwq", { XM, EXxmm }, 0 }, | |
5dd85c99 | 7978 | /* d8 */ |
592d1631 L |
7979 | { Bad_Opcode }, |
7980 | { Bad_Opcode }, | |
7981 | { Bad_Opcode }, | |
bf890a93 | 7982 | { "vphaddudq", { XM, EXxmm }, 0 }, |
592d1631 L |
7983 | { Bad_Opcode }, |
7984 | { Bad_Opcode }, | |
7985 | { Bad_Opcode }, | |
7986 | { Bad_Opcode }, | |
5dd85c99 | 7987 | /* e0 */ |
592d1631 | 7988 | { Bad_Opcode }, |
bf890a93 IT |
7989 | { "vphsubbw", { XM, EXxmm }, 0 }, |
7990 | { "vphsubwd", { XM, EXxmm }, 0 }, | |
7991 | { "vphsubdq", { XM, EXxmm }, 0 }, | |
592d1631 L |
7992 | { Bad_Opcode }, |
7993 | { Bad_Opcode }, | |
7994 | { Bad_Opcode }, | |
7995 | { Bad_Opcode }, | |
4e7d34a6 | 7996 | /* e8 */ |
592d1631 L |
7997 | { Bad_Opcode }, |
7998 | { Bad_Opcode }, | |
7999 | { Bad_Opcode }, | |
8000 | { Bad_Opcode }, | |
8001 | { Bad_Opcode }, | |
8002 | { Bad_Opcode }, | |
8003 | { Bad_Opcode }, | |
8004 | { Bad_Opcode }, | |
4e7d34a6 | 8005 | /* f0 */ |
592d1631 L |
8006 | { Bad_Opcode }, |
8007 | { Bad_Opcode }, | |
8008 | { Bad_Opcode }, | |
8009 | { Bad_Opcode }, | |
8010 | { Bad_Opcode }, | |
8011 | { Bad_Opcode }, | |
8012 | { Bad_Opcode }, | |
8013 | { Bad_Opcode }, | |
4e7d34a6 | 8014 | /* f8 */ |
592d1631 L |
8015 | { Bad_Opcode }, |
8016 | { Bad_Opcode }, | |
8017 | { Bad_Opcode }, | |
8018 | { Bad_Opcode }, | |
8019 | { Bad_Opcode }, | |
8020 | { Bad_Opcode }, | |
8021 | { Bad_Opcode }, | |
8022 | { Bad_Opcode }, | |
4e7d34a6 | 8023 | }, |
f88c9eb0 | 8024 | /* XOP_0A */ |
4e7d34a6 L |
8025 | { |
8026 | /* 00 */ | |
592d1631 L |
8027 | { Bad_Opcode }, |
8028 | { Bad_Opcode }, | |
8029 | { Bad_Opcode }, | |
8030 | { Bad_Opcode }, | |
8031 | { Bad_Opcode }, | |
8032 | { Bad_Opcode }, | |
8033 | { Bad_Opcode }, | |
8034 | { Bad_Opcode }, | |
4e7d34a6 | 8035 | /* 08 */ |
592d1631 L |
8036 | { Bad_Opcode }, |
8037 | { Bad_Opcode }, | |
8038 | { Bad_Opcode }, | |
8039 | { Bad_Opcode }, | |
8040 | { Bad_Opcode }, | |
8041 | { Bad_Opcode }, | |
8042 | { Bad_Opcode }, | |
8043 | { Bad_Opcode }, | |
4e7d34a6 | 8044 | /* 10 */ |
c1dc7af5 | 8045 | { "bextrS", { Gdq, Edq, Id }, 0 }, |
592d1631 | 8046 | { Bad_Opcode }, |
f88c9eb0 | 8047 | { REG_TABLE (REG_XOP_LWP) }, |
592d1631 L |
8048 | { Bad_Opcode }, |
8049 | { Bad_Opcode }, | |
8050 | { Bad_Opcode }, | |
8051 | { Bad_Opcode }, | |
8052 | { Bad_Opcode }, | |
4e7d34a6 | 8053 | /* 18 */ |
592d1631 L |
8054 | { Bad_Opcode }, |
8055 | { Bad_Opcode }, | |
8056 | { Bad_Opcode }, | |
8057 | { Bad_Opcode }, | |
8058 | { Bad_Opcode }, | |
8059 | { Bad_Opcode }, | |
8060 | { Bad_Opcode }, | |
8061 | { Bad_Opcode }, | |
4e7d34a6 | 8062 | /* 20 */ |
592d1631 L |
8063 | { Bad_Opcode }, |
8064 | { Bad_Opcode }, | |
8065 | { Bad_Opcode }, | |
8066 | { Bad_Opcode }, | |
8067 | { Bad_Opcode }, | |
8068 | { Bad_Opcode }, | |
8069 | { Bad_Opcode }, | |
8070 | { Bad_Opcode }, | |
4e7d34a6 | 8071 | /* 28 */ |
592d1631 L |
8072 | { Bad_Opcode }, |
8073 | { Bad_Opcode }, | |
8074 | { Bad_Opcode }, | |
8075 | { Bad_Opcode }, | |
8076 | { Bad_Opcode }, | |
8077 | { Bad_Opcode }, | |
8078 | { Bad_Opcode }, | |
8079 | { Bad_Opcode }, | |
4e7d34a6 | 8080 | /* 30 */ |
592d1631 L |
8081 | { Bad_Opcode }, |
8082 | { Bad_Opcode }, | |
8083 | { Bad_Opcode }, | |
8084 | { Bad_Opcode }, | |
8085 | { Bad_Opcode }, | |
8086 | { Bad_Opcode }, | |
8087 | { Bad_Opcode }, | |
8088 | { Bad_Opcode }, | |
c0f3af97 | 8089 | /* 38 */ |
592d1631 L |
8090 | { Bad_Opcode }, |
8091 | { Bad_Opcode }, | |
8092 | { Bad_Opcode }, | |
8093 | { Bad_Opcode }, | |
8094 | { Bad_Opcode }, | |
8095 | { Bad_Opcode }, | |
8096 | { Bad_Opcode }, | |
8097 | { Bad_Opcode }, | |
c0f3af97 | 8098 | /* 40 */ |
592d1631 L |
8099 | { Bad_Opcode }, |
8100 | { Bad_Opcode }, | |
8101 | { Bad_Opcode }, | |
8102 | { Bad_Opcode }, | |
8103 | { Bad_Opcode }, | |
8104 | { Bad_Opcode }, | |
8105 | { Bad_Opcode }, | |
8106 | { Bad_Opcode }, | |
c1e679ec | 8107 | /* 48 */ |
592d1631 L |
8108 | { Bad_Opcode }, |
8109 | { Bad_Opcode }, | |
8110 | { Bad_Opcode }, | |
8111 | { Bad_Opcode }, | |
8112 | { Bad_Opcode }, | |
8113 | { Bad_Opcode }, | |
8114 | { Bad_Opcode }, | |
8115 | { Bad_Opcode }, | |
c1e679ec | 8116 | /* 50 */ |
592d1631 L |
8117 | { Bad_Opcode }, |
8118 | { Bad_Opcode }, | |
8119 | { Bad_Opcode }, | |
8120 | { Bad_Opcode }, | |
8121 | { Bad_Opcode }, | |
8122 | { Bad_Opcode }, | |
8123 | { Bad_Opcode }, | |
8124 | { Bad_Opcode }, | |
4e7d34a6 | 8125 | /* 58 */ |
592d1631 L |
8126 | { Bad_Opcode }, |
8127 | { Bad_Opcode }, | |
8128 | { Bad_Opcode }, | |
8129 | { Bad_Opcode }, | |
8130 | { Bad_Opcode }, | |
8131 | { Bad_Opcode }, | |
8132 | { Bad_Opcode }, | |
8133 | { Bad_Opcode }, | |
4e7d34a6 | 8134 | /* 60 */ |
592d1631 L |
8135 | { Bad_Opcode }, |
8136 | { Bad_Opcode }, | |
8137 | { Bad_Opcode }, | |
8138 | { Bad_Opcode }, | |
8139 | { Bad_Opcode }, | |
8140 | { Bad_Opcode }, | |
8141 | { Bad_Opcode }, | |
8142 | { Bad_Opcode }, | |
4e7d34a6 | 8143 | /* 68 */ |
592d1631 L |
8144 | { Bad_Opcode }, |
8145 | { Bad_Opcode }, | |
8146 | { Bad_Opcode }, | |
8147 | { Bad_Opcode }, | |
8148 | { Bad_Opcode }, | |
8149 | { Bad_Opcode }, | |
8150 | { Bad_Opcode }, | |
8151 | { Bad_Opcode }, | |
4e7d34a6 | 8152 | /* 70 */ |
592d1631 L |
8153 | { Bad_Opcode }, |
8154 | { Bad_Opcode }, | |
8155 | { Bad_Opcode }, | |
8156 | { Bad_Opcode }, | |
8157 | { Bad_Opcode }, | |
8158 | { Bad_Opcode }, | |
8159 | { Bad_Opcode }, | |
8160 | { Bad_Opcode }, | |
4e7d34a6 | 8161 | /* 78 */ |
592d1631 L |
8162 | { Bad_Opcode }, |
8163 | { Bad_Opcode }, | |
8164 | { Bad_Opcode }, | |
8165 | { Bad_Opcode }, | |
8166 | { Bad_Opcode }, | |
8167 | { Bad_Opcode }, | |
8168 | { Bad_Opcode }, | |
8169 | { Bad_Opcode }, | |
4e7d34a6 | 8170 | /* 80 */ |
592d1631 L |
8171 | { Bad_Opcode }, |
8172 | { Bad_Opcode }, | |
8173 | { Bad_Opcode }, | |
8174 | { Bad_Opcode }, | |
8175 | { Bad_Opcode }, | |
8176 | { Bad_Opcode }, | |
8177 | { Bad_Opcode }, | |
8178 | { Bad_Opcode }, | |
4e7d34a6 | 8179 | /* 88 */ |
592d1631 L |
8180 | { Bad_Opcode }, |
8181 | { Bad_Opcode }, | |
8182 | { Bad_Opcode }, | |
8183 | { Bad_Opcode }, | |
8184 | { Bad_Opcode }, | |
8185 | { Bad_Opcode }, | |
8186 | { Bad_Opcode }, | |
8187 | { Bad_Opcode }, | |
4e7d34a6 | 8188 | /* 90 */ |
592d1631 L |
8189 | { Bad_Opcode }, |
8190 | { Bad_Opcode }, | |
8191 | { Bad_Opcode }, | |
8192 | { Bad_Opcode }, | |
8193 | { Bad_Opcode }, | |
8194 | { Bad_Opcode }, | |
8195 | { Bad_Opcode }, | |
8196 | { Bad_Opcode }, | |
4e7d34a6 | 8197 | /* 98 */ |
592d1631 L |
8198 | { Bad_Opcode }, |
8199 | { Bad_Opcode }, | |
8200 | { Bad_Opcode }, | |
8201 | { Bad_Opcode }, | |
8202 | { Bad_Opcode }, | |
8203 | { Bad_Opcode }, | |
8204 | { Bad_Opcode }, | |
8205 | { Bad_Opcode }, | |
4e7d34a6 | 8206 | /* a0 */ |
592d1631 L |
8207 | { Bad_Opcode }, |
8208 | { Bad_Opcode }, | |
8209 | { Bad_Opcode }, | |
8210 | { Bad_Opcode }, | |
8211 | { Bad_Opcode }, | |
8212 | { Bad_Opcode }, | |
8213 | { Bad_Opcode }, | |
8214 | { Bad_Opcode }, | |
4e7d34a6 | 8215 | /* a8 */ |
592d1631 L |
8216 | { Bad_Opcode }, |
8217 | { Bad_Opcode }, | |
8218 | { Bad_Opcode }, | |
8219 | { Bad_Opcode }, | |
8220 | { Bad_Opcode }, | |
8221 | { Bad_Opcode }, | |
8222 | { Bad_Opcode }, | |
8223 | { Bad_Opcode }, | |
d5d7db8e | 8224 | /* b0 */ |
592d1631 L |
8225 | { Bad_Opcode }, |
8226 | { Bad_Opcode }, | |
8227 | { Bad_Opcode }, | |
8228 | { Bad_Opcode }, | |
8229 | { Bad_Opcode }, | |
8230 | { Bad_Opcode }, | |
8231 | { Bad_Opcode }, | |
8232 | { Bad_Opcode }, | |
85f10a01 | 8233 | /* b8 */ |
592d1631 L |
8234 | { Bad_Opcode }, |
8235 | { Bad_Opcode }, | |
8236 | { Bad_Opcode }, | |
8237 | { Bad_Opcode }, | |
8238 | { Bad_Opcode }, | |
8239 | { Bad_Opcode }, | |
8240 | { Bad_Opcode }, | |
8241 | { Bad_Opcode }, | |
85f10a01 | 8242 | /* c0 */ |
592d1631 L |
8243 | { Bad_Opcode }, |
8244 | { Bad_Opcode }, | |
8245 | { Bad_Opcode }, | |
8246 | { Bad_Opcode }, | |
8247 | { Bad_Opcode }, | |
8248 | { Bad_Opcode }, | |
8249 | { Bad_Opcode }, | |
8250 | { Bad_Opcode }, | |
85f10a01 | 8251 | /* c8 */ |
592d1631 L |
8252 | { Bad_Opcode }, |
8253 | { Bad_Opcode }, | |
8254 | { Bad_Opcode }, | |
8255 | { Bad_Opcode }, | |
8256 | { Bad_Opcode }, | |
8257 | { Bad_Opcode }, | |
8258 | { Bad_Opcode }, | |
8259 | { Bad_Opcode }, | |
85f10a01 | 8260 | /* d0 */ |
592d1631 L |
8261 | { Bad_Opcode }, |
8262 | { Bad_Opcode }, | |
8263 | { Bad_Opcode }, | |
8264 | { Bad_Opcode }, | |
8265 | { Bad_Opcode }, | |
8266 | { Bad_Opcode }, | |
8267 | { Bad_Opcode }, | |
8268 | { Bad_Opcode }, | |
85f10a01 | 8269 | /* d8 */ |
592d1631 L |
8270 | { Bad_Opcode }, |
8271 | { Bad_Opcode }, | |
8272 | { Bad_Opcode }, | |
8273 | { Bad_Opcode }, | |
8274 | { Bad_Opcode }, | |
8275 | { Bad_Opcode }, | |
8276 | { Bad_Opcode }, | |
8277 | { Bad_Opcode }, | |
85f10a01 | 8278 | /* e0 */ |
592d1631 L |
8279 | { Bad_Opcode }, |
8280 | { Bad_Opcode }, | |
8281 | { Bad_Opcode }, | |
8282 | { Bad_Opcode }, | |
8283 | { Bad_Opcode }, | |
8284 | { Bad_Opcode }, | |
8285 | { Bad_Opcode }, | |
8286 | { Bad_Opcode }, | |
85f10a01 | 8287 | /* e8 */ |
592d1631 L |
8288 | { Bad_Opcode }, |
8289 | { Bad_Opcode }, | |
8290 | { Bad_Opcode }, | |
8291 | { Bad_Opcode }, | |
8292 | { Bad_Opcode }, | |
8293 | { Bad_Opcode }, | |
8294 | { Bad_Opcode }, | |
8295 | { Bad_Opcode }, | |
85f10a01 | 8296 | /* f0 */ |
592d1631 L |
8297 | { Bad_Opcode }, |
8298 | { Bad_Opcode }, | |
8299 | { Bad_Opcode }, | |
8300 | { Bad_Opcode }, | |
8301 | { Bad_Opcode }, | |
8302 | { Bad_Opcode }, | |
8303 | { Bad_Opcode }, | |
8304 | { Bad_Opcode }, | |
85f10a01 | 8305 | /* f8 */ |
592d1631 L |
8306 | { Bad_Opcode }, |
8307 | { Bad_Opcode }, | |
8308 | { Bad_Opcode }, | |
8309 | { Bad_Opcode }, | |
8310 | { Bad_Opcode }, | |
8311 | { Bad_Opcode }, | |
8312 | { Bad_Opcode }, | |
8313 | { Bad_Opcode }, | |
85f10a01 | 8314 | }, |
c0f3af97 L |
8315 | }; |
8316 | ||
8317 | static const struct dis386 vex_table[][256] = { | |
8318 | /* VEX_0F */ | |
85f10a01 MM |
8319 | { |
8320 | /* 00 */ | |
592d1631 L |
8321 | { Bad_Opcode }, |
8322 | { Bad_Opcode }, | |
8323 | { Bad_Opcode }, | |
8324 | { Bad_Opcode }, | |
8325 | { Bad_Opcode }, | |
8326 | { Bad_Opcode }, | |
8327 | { Bad_Opcode }, | |
8328 | { Bad_Opcode }, | |
85f10a01 | 8329 | /* 08 */ |
592d1631 L |
8330 | { Bad_Opcode }, |
8331 | { Bad_Opcode }, | |
8332 | { Bad_Opcode }, | |
8333 | { Bad_Opcode }, | |
8334 | { Bad_Opcode }, | |
8335 | { Bad_Opcode }, | |
8336 | { Bad_Opcode }, | |
8337 | { Bad_Opcode }, | |
c0f3af97 | 8338 | /* 10 */ |
592a252b L |
8339 | { PREFIX_TABLE (PREFIX_VEX_0F10) }, |
8340 | { PREFIX_TABLE (PREFIX_VEX_0F11) }, | |
8341 | { PREFIX_TABLE (PREFIX_VEX_0F12) }, | |
8342 | { MOD_TABLE (MOD_VEX_0F13) }, | |
bf926894 JB |
8343 | { "vunpcklpX", { XM, Vex, EXx }, PREFIX_OPCODE }, |
8344 | { "vunpckhpX", { XM, Vex, EXx }, PREFIX_OPCODE }, | |
592a252b L |
8345 | { PREFIX_TABLE (PREFIX_VEX_0F16) }, |
8346 | { MOD_TABLE (MOD_VEX_0F17) }, | |
c0f3af97 | 8347 | /* 18 */ |
592d1631 L |
8348 | { Bad_Opcode }, |
8349 | { Bad_Opcode }, | |
8350 | { Bad_Opcode }, | |
8351 | { Bad_Opcode }, | |
8352 | { Bad_Opcode }, | |
8353 | { Bad_Opcode }, | |
8354 | { Bad_Opcode }, | |
8355 | { Bad_Opcode }, | |
c0f3af97 | 8356 | /* 20 */ |
592d1631 L |
8357 | { Bad_Opcode }, |
8358 | { Bad_Opcode }, | |
8359 | { Bad_Opcode }, | |
8360 | { Bad_Opcode }, | |
8361 | { Bad_Opcode }, | |
8362 | { Bad_Opcode }, | |
8363 | { Bad_Opcode }, | |
8364 | { Bad_Opcode }, | |
c0f3af97 | 8365 | /* 28 */ |
bf926894 JB |
8366 | { "vmovapX", { XM, EXx }, PREFIX_OPCODE }, |
8367 | { "vmovapX", { EXxS, XM }, PREFIX_OPCODE }, | |
592a252b L |
8368 | { PREFIX_TABLE (PREFIX_VEX_0F2A) }, |
8369 | { MOD_TABLE (MOD_VEX_0F2B) }, | |
8370 | { PREFIX_TABLE (PREFIX_VEX_0F2C) }, | |
8371 | { PREFIX_TABLE (PREFIX_VEX_0F2D) }, | |
8372 | { PREFIX_TABLE (PREFIX_VEX_0F2E) }, | |
8373 | { PREFIX_TABLE (PREFIX_VEX_0F2F) }, | |
85f10a01 | 8374 | /* 30 */ |
592d1631 L |
8375 | { Bad_Opcode }, |
8376 | { Bad_Opcode }, | |
8377 | { Bad_Opcode }, | |
8378 | { Bad_Opcode }, | |
8379 | { Bad_Opcode }, | |
8380 | { Bad_Opcode }, | |
8381 | { Bad_Opcode }, | |
8382 | { Bad_Opcode }, | |
4e7d34a6 | 8383 | /* 38 */ |
592d1631 L |
8384 | { Bad_Opcode }, |
8385 | { Bad_Opcode }, | |
8386 | { Bad_Opcode }, | |
8387 | { Bad_Opcode }, | |
8388 | { Bad_Opcode }, | |
8389 | { Bad_Opcode }, | |
8390 | { Bad_Opcode }, | |
8391 | { Bad_Opcode }, | |
d5d7db8e | 8392 | /* 40 */ |
592d1631 | 8393 | { Bad_Opcode }, |
43234a1e L |
8394 | { PREFIX_TABLE (PREFIX_VEX_0F41) }, |
8395 | { PREFIX_TABLE (PREFIX_VEX_0F42) }, | |
592d1631 | 8396 | { Bad_Opcode }, |
43234a1e L |
8397 | { PREFIX_TABLE (PREFIX_VEX_0F44) }, |
8398 | { PREFIX_TABLE (PREFIX_VEX_0F45) }, | |
8399 | { PREFIX_TABLE (PREFIX_VEX_0F46) }, | |
8400 | { PREFIX_TABLE (PREFIX_VEX_0F47) }, | |
85f10a01 | 8401 | /* 48 */ |
592d1631 L |
8402 | { Bad_Opcode }, |
8403 | { Bad_Opcode }, | |
1ba585e8 | 8404 | { PREFIX_TABLE (PREFIX_VEX_0F4A) }, |
43234a1e | 8405 | { PREFIX_TABLE (PREFIX_VEX_0F4B) }, |
592d1631 L |
8406 | { Bad_Opcode }, |
8407 | { Bad_Opcode }, | |
8408 | { Bad_Opcode }, | |
8409 | { Bad_Opcode }, | |
d5d7db8e | 8410 | /* 50 */ |
592a252b L |
8411 | { MOD_TABLE (MOD_VEX_0F50) }, |
8412 | { PREFIX_TABLE (PREFIX_VEX_0F51) }, | |
8413 | { PREFIX_TABLE (PREFIX_VEX_0F52) }, | |
8414 | { PREFIX_TABLE (PREFIX_VEX_0F53) }, | |
bf926894 JB |
8415 | { "vandpX", { XM, Vex, EXx }, PREFIX_OPCODE }, |
8416 | { "vandnpX", { XM, Vex, EXx }, PREFIX_OPCODE }, | |
8417 | { "vorpX", { XM, Vex, EXx }, PREFIX_OPCODE }, | |
8418 | { "vxorpX", { XM, Vex, EXx }, PREFIX_OPCODE }, | |
c0f3af97 | 8419 | /* 58 */ |
592a252b L |
8420 | { PREFIX_TABLE (PREFIX_VEX_0F58) }, |
8421 | { PREFIX_TABLE (PREFIX_VEX_0F59) }, | |
8422 | { PREFIX_TABLE (PREFIX_VEX_0F5A) }, | |
8423 | { PREFIX_TABLE (PREFIX_VEX_0F5B) }, | |
8424 | { PREFIX_TABLE (PREFIX_VEX_0F5C) }, | |
8425 | { PREFIX_TABLE (PREFIX_VEX_0F5D) }, | |
8426 | { PREFIX_TABLE (PREFIX_VEX_0F5E) }, | |
8427 | { PREFIX_TABLE (PREFIX_VEX_0F5F) }, | |
c0f3af97 | 8428 | /* 60 */ |
592a252b L |
8429 | { PREFIX_TABLE (PREFIX_VEX_0F60) }, |
8430 | { PREFIX_TABLE (PREFIX_VEX_0F61) }, | |
8431 | { PREFIX_TABLE (PREFIX_VEX_0F62) }, | |
8432 | { PREFIX_TABLE (PREFIX_VEX_0F63) }, | |
8433 | { PREFIX_TABLE (PREFIX_VEX_0F64) }, | |
8434 | { PREFIX_TABLE (PREFIX_VEX_0F65) }, | |
8435 | { PREFIX_TABLE (PREFIX_VEX_0F66) }, | |
8436 | { PREFIX_TABLE (PREFIX_VEX_0F67) }, | |
c0f3af97 | 8437 | /* 68 */ |
592a252b L |
8438 | { PREFIX_TABLE (PREFIX_VEX_0F68) }, |
8439 | { PREFIX_TABLE (PREFIX_VEX_0F69) }, | |
8440 | { PREFIX_TABLE (PREFIX_VEX_0F6A) }, | |
8441 | { PREFIX_TABLE (PREFIX_VEX_0F6B) }, | |
8442 | { PREFIX_TABLE (PREFIX_VEX_0F6C) }, | |
8443 | { PREFIX_TABLE (PREFIX_VEX_0F6D) }, | |
8444 | { PREFIX_TABLE (PREFIX_VEX_0F6E) }, | |
8445 | { PREFIX_TABLE (PREFIX_VEX_0F6F) }, | |
c0f3af97 | 8446 | /* 70 */ |
592a252b L |
8447 | { PREFIX_TABLE (PREFIX_VEX_0F70) }, |
8448 | { REG_TABLE (REG_VEX_0F71) }, | |
8449 | { REG_TABLE (REG_VEX_0F72) }, | |
8450 | { REG_TABLE (REG_VEX_0F73) }, | |
8451 | { PREFIX_TABLE (PREFIX_VEX_0F74) }, | |
8452 | { PREFIX_TABLE (PREFIX_VEX_0F75) }, | |
8453 | { PREFIX_TABLE (PREFIX_VEX_0F76) }, | |
8454 | { PREFIX_TABLE (PREFIX_VEX_0F77) }, | |
c0f3af97 | 8455 | /* 78 */ |
592d1631 L |
8456 | { Bad_Opcode }, |
8457 | { Bad_Opcode }, | |
8458 | { Bad_Opcode }, | |
8459 | { Bad_Opcode }, | |
592a252b L |
8460 | { PREFIX_TABLE (PREFIX_VEX_0F7C) }, |
8461 | { PREFIX_TABLE (PREFIX_VEX_0F7D) }, | |
8462 | { PREFIX_TABLE (PREFIX_VEX_0F7E) }, | |
8463 | { PREFIX_TABLE (PREFIX_VEX_0F7F) }, | |
c0f3af97 | 8464 | /* 80 */ |
592d1631 L |
8465 | { Bad_Opcode }, |
8466 | { Bad_Opcode }, | |
8467 | { Bad_Opcode }, | |
8468 | { Bad_Opcode }, | |
8469 | { Bad_Opcode }, | |
8470 | { Bad_Opcode }, | |
8471 | { Bad_Opcode }, | |
8472 | { Bad_Opcode }, | |
c0f3af97 | 8473 | /* 88 */ |
592d1631 L |
8474 | { Bad_Opcode }, |
8475 | { Bad_Opcode }, | |
8476 | { Bad_Opcode }, | |
8477 | { Bad_Opcode }, | |
8478 | { Bad_Opcode }, | |
8479 | { Bad_Opcode }, | |
8480 | { Bad_Opcode }, | |
8481 | { Bad_Opcode }, | |
c0f3af97 | 8482 | /* 90 */ |
43234a1e L |
8483 | { PREFIX_TABLE (PREFIX_VEX_0F90) }, |
8484 | { PREFIX_TABLE (PREFIX_VEX_0F91) }, | |
8485 | { PREFIX_TABLE (PREFIX_VEX_0F92) }, | |
8486 | { PREFIX_TABLE (PREFIX_VEX_0F93) }, | |
592d1631 L |
8487 | { Bad_Opcode }, |
8488 | { Bad_Opcode }, | |
8489 | { Bad_Opcode }, | |
8490 | { Bad_Opcode }, | |
c0f3af97 | 8491 | /* 98 */ |
43234a1e | 8492 | { PREFIX_TABLE (PREFIX_VEX_0F98) }, |
1ba585e8 | 8493 | { PREFIX_TABLE (PREFIX_VEX_0F99) }, |
592d1631 L |
8494 | { Bad_Opcode }, |
8495 | { Bad_Opcode }, | |
8496 | { Bad_Opcode }, | |
8497 | { Bad_Opcode }, | |
8498 | { Bad_Opcode }, | |
8499 | { Bad_Opcode }, | |
c0f3af97 | 8500 | /* a0 */ |
592d1631 L |
8501 | { Bad_Opcode }, |
8502 | { Bad_Opcode }, | |
8503 | { Bad_Opcode }, | |
8504 | { Bad_Opcode }, | |
8505 | { Bad_Opcode }, | |
8506 | { Bad_Opcode }, | |
8507 | { Bad_Opcode }, | |
8508 | { Bad_Opcode }, | |
c0f3af97 | 8509 | /* a8 */ |
592d1631 L |
8510 | { Bad_Opcode }, |
8511 | { Bad_Opcode }, | |
8512 | { Bad_Opcode }, | |
8513 | { Bad_Opcode }, | |
8514 | { Bad_Opcode }, | |
8515 | { Bad_Opcode }, | |
592a252b | 8516 | { REG_TABLE (REG_VEX_0FAE) }, |
592d1631 | 8517 | { Bad_Opcode }, |
c0f3af97 | 8518 | /* b0 */ |
592d1631 L |
8519 | { Bad_Opcode }, |
8520 | { Bad_Opcode }, | |
8521 | { Bad_Opcode }, | |
8522 | { Bad_Opcode }, | |
8523 | { Bad_Opcode }, | |
8524 | { Bad_Opcode }, | |
8525 | { Bad_Opcode }, | |
8526 | { Bad_Opcode }, | |
c0f3af97 | 8527 | /* b8 */ |
592d1631 L |
8528 | { Bad_Opcode }, |
8529 | { Bad_Opcode }, | |
8530 | { Bad_Opcode }, | |
8531 | { Bad_Opcode }, | |
8532 | { Bad_Opcode }, | |
8533 | { Bad_Opcode }, | |
8534 | { Bad_Opcode }, | |
8535 | { Bad_Opcode }, | |
c0f3af97 | 8536 | /* c0 */ |
592d1631 L |
8537 | { Bad_Opcode }, |
8538 | { Bad_Opcode }, | |
592a252b | 8539 | { PREFIX_TABLE (PREFIX_VEX_0FC2) }, |
592d1631 | 8540 | { Bad_Opcode }, |
592a252b L |
8541 | { PREFIX_TABLE (PREFIX_VEX_0FC4) }, |
8542 | { PREFIX_TABLE (PREFIX_VEX_0FC5) }, | |
bf926894 | 8543 | { "vshufpX", { XM, Vex, EXx, Ib }, PREFIX_OPCODE }, |
592d1631 | 8544 | { Bad_Opcode }, |
c0f3af97 | 8545 | /* c8 */ |
592d1631 L |
8546 | { Bad_Opcode }, |
8547 | { Bad_Opcode }, | |
8548 | { Bad_Opcode }, | |
8549 | { Bad_Opcode }, | |
8550 | { Bad_Opcode }, | |
8551 | { Bad_Opcode }, | |
8552 | { Bad_Opcode }, | |
8553 | { Bad_Opcode }, | |
c0f3af97 | 8554 | /* d0 */ |
592a252b L |
8555 | { PREFIX_TABLE (PREFIX_VEX_0FD0) }, |
8556 | { PREFIX_TABLE (PREFIX_VEX_0FD1) }, | |
8557 | { PREFIX_TABLE (PREFIX_VEX_0FD2) }, | |
8558 | { PREFIX_TABLE (PREFIX_VEX_0FD3) }, | |
8559 | { PREFIX_TABLE (PREFIX_VEX_0FD4) }, | |
8560 | { PREFIX_TABLE (PREFIX_VEX_0FD5) }, | |
8561 | { PREFIX_TABLE (PREFIX_VEX_0FD6) }, | |
8562 | { PREFIX_TABLE (PREFIX_VEX_0FD7) }, | |
c0f3af97 | 8563 | /* d8 */ |
592a252b L |
8564 | { PREFIX_TABLE (PREFIX_VEX_0FD8) }, |
8565 | { PREFIX_TABLE (PREFIX_VEX_0FD9) }, | |
8566 | { PREFIX_TABLE (PREFIX_VEX_0FDA) }, | |
8567 | { PREFIX_TABLE (PREFIX_VEX_0FDB) }, | |
8568 | { PREFIX_TABLE (PREFIX_VEX_0FDC) }, | |
8569 | { PREFIX_TABLE (PREFIX_VEX_0FDD) }, | |
8570 | { PREFIX_TABLE (PREFIX_VEX_0FDE) }, | |
8571 | { PREFIX_TABLE (PREFIX_VEX_0FDF) }, | |
c0f3af97 | 8572 | /* e0 */ |
592a252b L |
8573 | { PREFIX_TABLE (PREFIX_VEX_0FE0) }, |
8574 | { PREFIX_TABLE (PREFIX_VEX_0FE1) }, | |
8575 | { PREFIX_TABLE (PREFIX_VEX_0FE2) }, | |
8576 | { PREFIX_TABLE (PREFIX_VEX_0FE3) }, | |
8577 | { PREFIX_TABLE (PREFIX_VEX_0FE4) }, | |
8578 | { PREFIX_TABLE (PREFIX_VEX_0FE5) }, | |
8579 | { PREFIX_TABLE (PREFIX_VEX_0FE6) }, | |
8580 | { PREFIX_TABLE (PREFIX_VEX_0FE7) }, | |
c0f3af97 | 8581 | /* e8 */ |
592a252b L |
8582 | { PREFIX_TABLE (PREFIX_VEX_0FE8) }, |
8583 | { PREFIX_TABLE (PREFIX_VEX_0FE9) }, | |
8584 | { PREFIX_TABLE (PREFIX_VEX_0FEA) }, | |
8585 | { PREFIX_TABLE (PREFIX_VEX_0FEB) }, | |
8586 | { PREFIX_TABLE (PREFIX_VEX_0FEC) }, | |
8587 | { PREFIX_TABLE (PREFIX_VEX_0FED) }, | |
8588 | { PREFIX_TABLE (PREFIX_VEX_0FEE) }, | |
8589 | { PREFIX_TABLE (PREFIX_VEX_0FEF) }, | |
c0f3af97 | 8590 | /* f0 */ |
592a252b L |
8591 | { PREFIX_TABLE (PREFIX_VEX_0FF0) }, |
8592 | { PREFIX_TABLE (PREFIX_VEX_0FF1) }, | |
8593 | { PREFIX_TABLE (PREFIX_VEX_0FF2) }, | |
8594 | { PREFIX_TABLE (PREFIX_VEX_0FF3) }, | |
8595 | { PREFIX_TABLE (PREFIX_VEX_0FF4) }, | |
8596 | { PREFIX_TABLE (PREFIX_VEX_0FF5) }, | |
8597 | { PREFIX_TABLE (PREFIX_VEX_0FF6) }, | |
8598 | { PREFIX_TABLE (PREFIX_VEX_0FF7) }, | |
c0f3af97 | 8599 | /* f8 */ |
592a252b L |
8600 | { PREFIX_TABLE (PREFIX_VEX_0FF8) }, |
8601 | { PREFIX_TABLE (PREFIX_VEX_0FF9) }, | |
8602 | { PREFIX_TABLE (PREFIX_VEX_0FFA) }, | |
8603 | { PREFIX_TABLE (PREFIX_VEX_0FFB) }, | |
8604 | { PREFIX_TABLE (PREFIX_VEX_0FFC) }, | |
8605 | { PREFIX_TABLE (PREFIX_VEX_0FFD) }, | |
8606 | { PREFIX_TABLE (PREFIX_VEX_0FFE) }, | |
592d1631 | 8607 | { Bad_Opcode }, |
c0f3af97 L |
8608 | }, |
8609 | /* VEX_0F38 */ | |
8610 | { | |
8611 | /* 00 */ | |
592a252b L |
8612 | { PREFIX_TABLE (PREFIX_VEX_0F3800) }, |
8613 | { PREFIX_TABLE (PREFIX_VEX_0F3801) }, | |
8614 | { PREFIX_TABLE (PREFIX_VEX_0F3802) }, | |
8615 | { PREFIX_TABLE (PREFIX_VEX_0F3803) }, | |
8616 | { PREFIX_TABLE (PREFIX_VEX_0F3804) }, | |
8617 | { PREFIX_TABLE (PREFIX_VEX_0F3805) }, | |
8618 | { PREFIX_TABLE (PREFIX_VEX_0F3806) }, | |
8619 | { PREFIX_TABLE (PREFIX_VEX_0F3807) }, | |
c0f3af97 | 8620 | /* 08 */ |
592a252b L |
8621 | { PREFIX_TABLE (PREFIX_VEX_0F3808) }, |
8622 | { PREFIX_TABLE (PREFIX_VEX_0F3809) }, | |
8623 | { PREFIX_TABLE (PREFIX_VEX_0F380A) }, | |
8624 | { PREFIX_TABLE (PREFIX_VEX_0F380B) }, | |
8625 | { PREFIX_TABLE (PREFIX_VEX_0F380C) }, | |
8626 | { PREFIX_TABLE (PREFIX_VEX_0F380D) }, | |
8627 | { PREFIX_TABLE (PREFIX_VEX_0F380E) }, | |
8628 | { PREFIX_TABLE (PREFIX_VEX_0F380F) }, | |
c0f3af97 | 8629 | /* 10 */ |
592d1631 L |
8630 | { Bad_Opcode }, |
8631 | { Bad_Opcode }, | |
8632 | { Bad_Opcode }, | |
592a252b | 8633 | { PREFIX_TABLE (PREFIX_VEX_0F3813) }, |
592d1631 L |
8634 | { Bad_Opcode }, |
8635 | { Bad_Opcode }, | |
6c30d220 | 8636 | { PREFIX_TABLE (PREFIX_VEX_0F3816) }, |
592a252b | 8637 | { PREFIX_TABLE (PREFIX_VEX_0F3817) }, |
c0f3af97 | 8638 | /* 18 */ |
592a252b L |
8639 | { PREFIX_TABLE (PREFIX_VEX_0F3818) }, |
8640 | { PREFIX_TABLE (PREFIX_VEX_0F3819) }, | |
8641 | { PREFIX_TABLE (PREFIX_VEX_0F381A) }, | |
592d1631 | 8642 | { Bad_Opcode }, |
592a252b L |
8643 | { PREFIX_TABLE (PREFIX_VEX_0F381C) }, |
8644 | { PREFIX_TABLE (PREFIX_VEX_0F381D) }, | |
8645 | { PREFIX_TABLE (PREFIX_VEX_0F381E) }, | |
592d1631 | 8646 | { Bad_Opcode }, |
c0f3af97 | 8647 | /* 20 */ |
592a252b L |
8648 | { PREFIX_TABLE (PREFIX_VEX_0F3820) }, |
8649 | { PREFIX_TABLE (PREFIX_VEX_0F3821) }, | |
8650 | { PREFIX_TABLE (PREFIX_VEX_0F3822) }, | |
8651 | { PREFIX_TABLE (PREFIX_VEX_0F3823) }, | |
8652 | { PREFIX_TABLE (PREFIX_VEX_0F3824) }, | |
8653 | { PREFIX_TABLE (PREFIX_VEX_0F3825) }, | |
592d1631 L |
8654 | { Bad_Opcode }, |
8655 | { Bad_Opcode }, | |
c0f3af97 | 8656 | /* 28 */ |
592a252b L |
8657 | { PREFIX_TABLE (PREFIX_VEX_0F3828) }, |
8658 | { PREFIX_TABLE (PREFIX_VEX_0F3829) }, | |
8659 | { PREFIX_TABLE (PREFIX_VEX_0F382A) }, | |
8660 | { PREFIX_TABLE (PREFIX_VEX_0F382B) }, | |
8661 | { PREFIX_TABLE (PREFIX_VEX_0F382C) }, | |
8662 | { PREFIX_TABLE (PREFIX_VEX_0F382D) }, | |
8663 | { PREFIX_TABLE (PREFIX_VEX_0F382E) }, | |
8664 | { PREFIX_TABLE (PREFIX_VEX_0F382F) }, | |
c0f3af97 | 8665 | /* 30 */ |
592a252b L |
8666 | { PREFIX_TABLE (PREFIX_VEX_0F3830) }, |
8667 | { PREFIX_TABLE (PREFIX_VEX_0F3831) }, | |
8668 | { PREFIX_TABLE (PREFIX_VEX_0F3832) }, | |
8669 | { PREFIX_TABLE (PREFIX_VEX_0F3833) }, | |
8670 | { PREFIX_TABLE (PREFIX_VEX_0F3834) }, | |
8671 | { PREFIX_TABLE (PREFIX_VEX_0F3835) }, | |
6c30d220 | 8672 | { PREFIX_TABLE (PREFIX_VEX_0F3836) }, |
592a252b | 8673 | { PREFIX_TABLE (PREFIX_VEX_0F3837) }, |
c0f3af97 | 8674 | /* 38 */ |
592a252b L |
8675 | { PREFIX_TABLE (PREFIX_VEX_0F3838) }, |
8676 | { PREFIX_TABLE (PREFIX_VEX_0F3839) }, | |
8677 | { PREFIX_TABLE (PREFIX_VEX_0F383A) }, | |
8678 | { PREFIX_TABLE (PREFIX_VEX_0F383B) }, | |
8679 | { PREFIX_TABLE (PREFIX_VEX_0F383C) }, | |
8680 | { PREFIX_TABLE (PREFIX_VEX_0F383D) }, | |
8681 | { PREFIX_TABLE (PREFIX_VEX_0F383E) }, | |
8682 | { PREFIX_TABLE (PREFIX_VEX_0F383F) }, | |
c0f3af97 | 8683 | /* 40 */ |
592a252b L |
8684 | { PREFIX_TABLE (PREFIX_VEX_0F3840) }, |
8685 | { PREFIX_TABLE (PREFIX_VEX_0F3841) }, | |
592d1631 L |
8686 | { Bad_Opcode }, |
8687 | { Bad_Opcode }, | |
8688 | { Bad_Opcode }, | |
6c30d220 L |
8689 | { PREFIX_TABLE (PREFIX_VEX_0F3845) }, |
8690 | { PREFIX_TABLE (PREFIX_VEX_0F3846) }, | |
8691 | { PREFIX_TABLE (PREFIX_VEX_0F3847) }, | |
c0f3af97 | 8692 | /* 48 */ |
592d1631 L |
8693 | { Bad_Opcode }, |
8694 | { Bad_Opcode }, | |
8695 | { Bad_Opcode }, | |
8696 | { Bad_Opcode }, | |
8697 | { Bad_Opcode }, | |
8698 | { Bad_Opcode }, | |
8699 | { Bad_Opcode }, | |
8700 | { Bad_Opcode }, | |
c0f3af97 | 8701 | /* 50 */ |
592d1631 L |
8702 | { Bad_Opcode }, |
8703 | { Bad_Opcode }, | |
8704 | { Bad_Opcode }, | |
8705 | { Bad_Opcode }, | |
8706 | { Bad_Opcode }, | |
8707 | { Bad_Opcode }, | |
8708 | { Bad_Opcode }, | |
8709 | { Bad_Opcode }, | |
c0f3af97 | 8710 | /* 58 */ |
6c30d220 L |
8711 | { PREFIX_TABLE (PREFIX_VEX_0F3858) }, |
8712 | { PREFIX_TABLE (PREFIX_VEX_0F3859) }, | |
8713 | { PREFIX_TABLE (PREFIX_VEX_0F385A) }, | |
592d1631 L |
8714 | { Bad_Opcode }, |
8715 | { Bad_Opcode }, | |
8716 | { Bad_Opcode }, | |
8717 | { Bad_Opcode }, | |
8718 | { Bad_Opcode }, | |
c0f3af97 | 8719 | /* 60 */ |
592d1631 L |
8720 | { Bad_Opcode }, |
8721 | { Bad_Opcode }, | |
8722 | { Bad_Opcode }, | |
8723 | { Bad_Opcode }, | |
8724 | { Bad_Opcode }, | |
8725 | { Bad_Opcode }, | |
8726 | { Bad_Opcode }, | |
8727 | { Bad_Opcode }, | |
c0f3af97 | 8728 | /* 68 */ |
592d1631 L |
8729 | { Bad_Opcode }, |
8730 | { Bad_Opcode }, | |
8731 | { Bad_Opcode }, | |
8732 | { Bad_Opcode }, | |
8733 | { Bad_Opcode }, | |
8734 | { Bad_Opcode }, | |
8735 | { Bad_Opcode }, | |
8736 | { Bad_Opcode }, | |
c0f3af97 | 8737 | /* 70 */ |
592d1631 L |
8738 | { Bad_Opcode }, |
8739 | { Bad_Opcode }, | |
8740 | { Bad_Opcode }, | |
8741 | { Bad_Opcode }, | |
8742 | { Bad_Opcode }, | |
8743 | { Bad_Opcode }, | |
8744 | { Bad_Opcode }, | |
8745 | { Bad_Opcode }, | |
c0f3af97 | 8746 | /* 78 */ |
6c30d220 L |
8747 | { PREFIX_TABLE (PREFIX_VEX_0F3878) }, |
8748 | { PREFIX_TABLE (PREFIX_VEX_0F3879) }, | |
592d1631 L |
8749 | { Bad_Opcode }, |
8750 | { Bad_Opcode }, | |
8751 | { Bad_Opcode }, | |
8752 | { Bad_Opcode }, | |
8753 | { Bad_Opcode }, | |
8754 | { Bad_Opcode }, | |
c0f3af97 | 8755 | /* 80 */ |
592d1631 L |
8756 | { Bad_Opcode }, |
8757 | { Bad_Opcode }, | |
8758 | { Bad_Opcode }, | |
8759 | { Bad_Opcode }, | |
8760 | { Bad_Opcode }, | |
8761 | { Bad_Opcode }, | |
8762 | { Bad_Opcode }, | |
8763 | { Bad_Opcode }, | |
c0f3af97 | 8764 | /* 88 */ |
592d1631 L |
8765 | { Bad_Opcode }, |
8766 | { Bad_Opcode }, | |
8767 | { Bad_Opcode }, | |
8768 | { Bad_Opcode }, | |
6c30d220 | 8769 | { PREFIX_TABLE (PREFIX_VEX_0F388C) }, |
592d1631 | 8770 | { Bad_Opcode }, |
6c30d220 | 8771 | { PREFIX_TABLE (PREFIX_VEX_0F388E) }, |
592d1631 | 8772 | { Bad_Opcode }, |
c0f3af97 | 8773 | /* 90 */ |
6c30d220 L |
8774 | { PREFIX_TABLE (PREFIX_VEX_0F3890) }, |
8775 | { PREFIX_TABLE (PREFIX_VEX_0F3891) }, | |
8776 | { PREFIX_TABLE (PREFIX_VEX_0F3892) }, | |
8777 | { PREFIX_TABLE (PREFIX_VEX_0F3893) }, | |
592d1631 L |
8778 | { Bad_Opcode }, |
8779 | { Bad_Opcode }, | |
592a252b L |
8780 | { PREFIX_TABLE (PREFIX_VEX_0F3896) }, |
8781 | { PREFIX_TABLE (PREFIX_VEX_0F3897) }, | |
c0f3af97 | 8782 | /* 98 */ |
592a252b L |
8783 | { PREFIX_TABLE (PREFIX_VEX_0F3898) }, |
8784 | { PREFIX_TABLE (PREFIX_VEX_0F3899) }, | |
8785 | { PREFIX_TABLE (PREFIX_VEX_0F389A) }, | |
8786 | { PREFIX_TABLE (PREFIX_VEX_0F389B) }, | |
8787 | { PREFIX_TABLE (PREFIX_VEX_0F389C) }, | |
8788 | { PREFIX_TABLE (PREFIX_VEX_0F389D) }, | |
8789 | { PREFIX_TABLE (PREFIX_VEX_0F389E) }, | |
8790 | { PREFIX_TABLE (PREFIX_VEX_0F389F) }, | |
c0f3af97 | 8791 | /* a0 */ |
592d1631 L |
8792 | { Bad_Opcode }, |
8793 | { Bad_Opcode }, | |
8794 | { Bad_Opcode }, | |
8795 | { Bad_Opcode }, | |
8796 | { Bad_Opcode }, | |
8797 | { Bad_Opcode }, | |
592a252b L |
8798 | { PREFIX_TABLE (PREFIX_VEX_0F38A6) }, |
8799 | { PREFIX_TABLE (PREFIX_VEX_0F38A7) }, | |
c0f3af97 | 8800 | /* a8 */ |
592a252b L |
8801 | { PREFIX_TABLE (PREFIX_VEX_0F38A8) }, |
8802 | { PREFIX_TABLE (PREFIX_VEX_0F38A9) }, | |
8803 | { PREFIX_TABLE (PREFIX_VEX_0F38AA) }, | |
8804 | { PREFIX_TABLE (PREFIX_VEX_0F38AB) }, | |
8805 | { PREFIX_TABLE (PREFIX_VEX_0F38AC) }, | |
8806 | { PREFIX_TABLE (PREFIX_VEX_0F38AD) }, | |
8807 | { PREFIX_TABLE (PREFIX_VEX_0F38AE) }, | |
8808 | { PREFIX_TABLE (PREFIX_VEX_0F38AF) }, | |
c0f3af97 | 8809 | /* b0 */ |
592d1631 L |
8810 | { Bad_Opcode }, |
8811 | { Bad_Opcode }, | |
8812 | { Bad_Opcode }, | |
8813 | { Bad_Opcode }, | |
8814 | { Bad_Opcode }, | |
8815 | { Bad_Opcode }, | |
592a252b L |
8816 | { PREFIX_TABLE (PREFIX_VEX_0F38B6) }, |
8817 | { PREFIX_TABLE (PREFIX_VEX_0F38B7) }, | |
c0f3af97 | 8818 | /* b8 */ |
592a252b L |
8819 | { PREFIX_TABLE (PREFIX_VEX_0F38B8) }, |
8820 | { PREFIX_TABLE (PREFIX_VEX_0F38B9) }, | |
8821 | { PREFIX_TABLE (PREFIX_VEX_0F38BA) }, | |
8822 | { PREFIX_TABLE (PREFIX_VEX_0F38BB) }, | |
8823 | { PREFIX_TABLE (PREFIX_VEX_0F38BC) }, | |
8824 | { PREFIX_TABLE (PREFIX_VEX_0F38BD) }, | |
8825 | { PREFIX_TABLE (PREFIX_VEX_0F38BE) }, | |
8826 | { PREFIX_TABLE (PREFIX_VEX_0F38BF) }, | |
c0f3af97 | 8827 | /* c0 */ |
592d1631 L |
8828 | { Bad_Opcode }, |
8829 | { Bad_Opcode }, | |
8830 | { Bad_Opcode }, | |
8831 | { Bad_Opcode }, | |
8832 | { Bad_Opcode }, | |
8833 | { Bad_Opcode }, | |
8834 | { Bad_Opcode }, | |
8835 | { Bad_Opcode }, | |
c0f3af97 | 8836 | /* c8 */ |
592d1631 L |
8837 | { Bad_Opcode }, |
8838 | { Bad_Opcode }, | |
8839 | { Bad_Opcode }, | |
8840 | { Bad_Opcode }, | |
8841 | { Bad_Opcode }, | |
8842 | { Bad_Opcode }, | |
8843 | { Bad_Opcode }, | |
48521003 | 8844 | { PREFIX_TABLE (PREFIX_VEX_0F38CF) }, |
c0f3af97 | 8845 | /* d0 */ |
592d1631 L |
8846 | { Bad_Opcode }, |
8847 | { Bad_Opcode }, | |
8848 | { Bad_Opcode }, | |
8849 | { Bad_Opcode }, | |
8850 | { Bad_Opcode }, | |
8851 | { Bad_Opcode }, | |
8852 | { Bad_Opcode }, | |
8853 | { Bad_Opcode }, | |
c0f3af97 | 8854 | /* d8 */ |
592d1631 L |
8855 | { Bad_Opcode }, |
8856 | { Bad_Opcode }, | |
8857 | { Bad_Opcode }, | |
592a252b L |
8858 | { PREFIX_TABLE (PREFIX_VEX_0F38DB) }, |
8859 | { PREFIX_TABLE (PREFIX_VEX_0F38DC) }, | |
8860 | { PREFIX_TABLE (PREFIX_VEX_0F38DD) }, | |
8861 | { PREFIX_TABLE (PREFIX_VEX_0F38DE) }, | |
8862 | { PREFIX_TABLE (PREFIX_VEX_0F38DF) }, | |
c0f3af97 | 8863 | /* e0 */ |
592d1631 L |
8864 | { Bad_Opcode }, |
8865 | { Bad_Opcode }, | |
8866 | { Bad_Opcode }, | |
8867 | { Bad_Opcode }, | |
8868 | { Bad_Opcode }, | |
8869 | { Bad_Opcode }, | |
8870 | { Bad_Opcode }, | |
8871 | { Bad_Opcode }, | |
c0f3af97 | 8872 | /* e8 */ |
592d1631 L |
8873 | { Bad_Opcode }, |
8874 | { Bad_Opcode }, | |
8875 | { Bad_Opcode }, | |
8876 | { Bad_Opcode }, | |
8877 | { Bad_Opcode }, | |
8878 | { Bad_Opcode }, | |
8879 | { Bad_Opcode }, | |
8880 | { Bad_Opcode }, | |
c0f3af97 | 8881 | /* f0 */ |
592d1631 L |
8882 | { Bad_Opcode }, |
8883 | { Bad_Opcode }, | |
f12dc422 L |
8884 | { PREFIX_TABLE (PREFIX_VEX_0F38F2) }, |
8885 | { REG_TABLE (REG_VEX_0F38F3) }, | |
592d1631 | 8886 | { Bad_Opcode }, |
6c30d220 L |
8887 | { PREFIX_TABLE (PREFIX_VEX_0F38F5) }, |
8888 | { PREFIX_TABLE (PREFIX_VEX_0F38F6) }, | |
f12dc422 | 8889 | { PREFIX_TABLE (PREFIX_VEX_0F38F7) }, |
c0f3af97 | 8890 | /* f8 */ |
592d1631 L |
8891 | { Bad_Opcode }, |
8892 | { Bad_Opcode }, | |
8893 | { Bad_Opcode }, | |
8894 | { Bad_Opcode }, | |
8895 | { Bad_Opcode }, | |
8896 | { Bad_Opcode }, | |
8897 | { Bad_Opcode }, | |
8898 | { Bad_Opcode }, | |
c0f3af97 L |
8899 | }, |
8900 | /* VEX_0F3A */ | |
8901 | { | |
8902 | /* 00 */ | |
6c30d220 L |
8903 | { PREFIX_TABLE (PREFIX_VEX_0F3A00) }, |
8904 | { PREFIX_TABLE (PREFIX_VEX_0F3A01) }, | |
8905 | { PREFIX_TABLE (PREFIX_VEX_0F3A02) }, | |
592d1631 | 8906 | { Bad_Opcode }, |
592a252b L |
8907 | { PREFIX_TABLE (PREFIX_VEX_0F3A04) }, |
8908 | { PREFIX_TABLE (PREFIX_VEX_0F3A05) }, | |
8909 | { PREFIX_TABLE (PREFIX_VEX_0F3A06) }, | |
592d1631 | 8910 | { Bad_Opcode }, |
c0f3af97 | 8911 | /* 08 */ |
592a252b L |
8912 | { PREFIX_TABLE (PREFIX_VEX_0F3A08) }, |
8913 | { PREFIX_TABLE (PREFIX_VEX_0F3A09) }, | |
8914 | { PREFIX_TABLE (PREFIX_VEX_0F3A0A) }, | |
8915 | { PREFIX_TABLE (PREFIX_VEX_0F3A0B) }, | |
8916 | { PREFIX_TABLE (PREFIX_VEX_0F3A0C) }, | |
8917 | { PREFIX_TABLE (PREFIX_VEX_0F3A0D) }, | |
8918 | { PREFIX_TABLE (PREFIX_VEX_0F3A0E) }, | |
8919 | { PREFIX_TABLE (PREFIX_VEX_0F3A0F) }, | |
c0f3af97 | 8920 | /* 10 */ |
592d1631 L |
8921 | { Bad_Opcode }, |
8922 | { Bad_Opcode }, | |
8923 | { Bad_Opcode }, | |
8924 | { Bad_Opcode }, | |
592a252b L |
8925 | { PREFIX_TABLE (PREFIX_VEX_0F3A14) }, |
8926 | { PREFIX_TABLE (PREFIX_VEX_0F3A15) }, | |
8927 | { PREFIX_TABLE (PREFIX_VEX_0F3A16) }, | |
8928 | { PREFIX_TABLE (PREFIX_VEX_0F3A17) }, | |
c0f3af97 | 8929 | /* 18 */ |
592a252b L |
8930 | { PREFIX_TABLE (PREFIX_VEX_0F3A18) }, |
8931 | { PREFIX_TABLE (PREFIX_VEX_0F3A19) }, | |
592d1631 L |
8932 | { Bad_Opcode }, |
8933 | { Bad_Opcode }, | |
8934 | { Bad_Opcode }, | |
592a252b | 8935 | { PREFIX_TABLE (PREFIX_VEX_0F3A1D) }, |
592d1631 L |
8936 | { Bad_Opcode }, |
8937 | { Bad_Opcode }, | |
c0f3af97 | 8938 | /* 20 */ |
592a252b L |
8939 | { PREFIX_TABLE (PREFIX_VEX_0F3A20) }, |
8940 | { PREFIX_TABLE (PREFIX_VEX_0F3A21) }, | |
8941 | { PREFIX_TABLE (PREFIX_VEX_0F3A22) }, | |
592d1631 L |
8942 | { Bad_Opcode }, |
8943 | { Bad_Opcode }, | |
8944 | { Bad_Opcode }, | |
8945 | { Bad_Opcode }, | |
8946 | { Bad_Opcode }, | |
c0f3af97 | 8947 | /* 28 */ |
592d1631 L |
8948 | { Bad_Opcode }, |
8949 | { Bad_Opcode }, | |
8950 | { Bad_Opcode }, | |
8951 | { Bad_Opcode }, | |
8952 | { Bad_Opcode }, | |
8953 | { Bad_Opcode }, | |
8954 | { Bad_Opcode }, | |
8955 | { Bad_Opcode }, | |
c0f3af97 | 8956 | /* 30 */ |
43234a1e | 8957 | { PREFIX_TABLE (PREFIX_VEX_0F3A30) }, |
1ba585e8 | 8958 | { PREFIX_TABLE (PREFIX_VEX_0F3A31) }, |
43234a1e | 8959 | { PREFIX_TABLE (PREFIX_VEX_0F3A32) }, |
1ba585e8 | 8960 | { PREFIX_TABLE (PREFIX_VEX_0F3A33) }, |
592d1631 L |
8961 | { Bad_Opcode }, |
8962 | { Bad_Opcode }, | |
8963 | { Bad_Opcode }, | |
8964 | { Bad_Opcode }, | |
c0f3af97 | 8965 | /* 38 */ |
6c30d220 L |
8966 | { PREFIX_TABLE (PREFIX_VEX_0F3A38) }, |
8967 | { PREFIX_TABLE (PREFIX_VEX_0F3A39) }, | |
592d1631 L |
8968 | { Bad_Opcode }, |
8969 | { Bad_Opcode }, | |
8970 | { Bad_Opcode }, | |
8971 | { Bad_Opcode }, | |
8972 | { Bad_Opcode }, | |
8973 | { Bad_Opcode }, | |
c0f3af97 | 8974 | /* 40 */ |
592a252b L |
8975 | { PREFIX_TABLE (PREFIX_VEX_0F3A40) }, |
8976 | { PREFIX_TABLE (PREFIX_VEX_0F3A41) }, | |
8977 | { PREFIX_TABLE (PREFIX_VEX_0F3A42) }, | |
592d1631 | 8978 | { Bad_Opcode }, |
592a252b | 8979 | { PREFIX_TABLE (PREFIX_VEX_0F3A44) }, |
592d1631 | 8980 | { Bad_Opcode }, |
6c30d220 | 8981 | { PREFIX_TABLE (PREFIX_VEX_0F3A46) }, |
592d1631 | 8982 | { Bad_Opcode }, |
c0f3af97 | 8983 | /* 48 */ |
592a252b L |
8984 | { PREFIX_TABLE (PREFIX_VEX_0F3A48) }, |
8985 | { PREFIX_TABLE (PREFIX_VEX_0F3A49) }, | |
8986 | { PREFIX_TABLE (PREFIX_VEX_0F3A4A) }, | |
8987 | { PREFIX_TABLE (PREFIX_VEX_0F3A4B) }, | |
8988 | { PREFIX_TABLE (PREFIX_VEX_0F3A4C) }, | |
592d1631 L |
8989 | { Bad_Opcode }, |
8990 | { Bad_Opcode }, | |
8991 | { Bad_Opcode }, | |
c0f3af97 | 8992 | /* 50 */ |
592d1631 L |
8993 | { Bad_Opcode }, |
8994 | { Bad_Opcode }, | |
8995 | { Bad_Opcode }, | |
8996 | { Bad_Opcode }, | |
8997 | { Bad_Opcode }, | |
8998 | { Bad_Opcode }, | |
8999 | { Bad_Opcode }, | |
9000 | { Bad_Opcode }, | |
c0f3af97 | 9001 | /* 58 */ |
592d1631 L |
9002 | { Bad_Opcode }, |
9003 | { Bad_Opcode }, | |
9004 | { Bad_Opcode }, | |
9005 | { Bad_Opcode }, | |
592a252b L |
9006 | { PREFIX_TABLE (PREFIX_VEX_0F3A5C) }, |
9007 | { PREFIX_TABLE (PREFIX_VEX_0F3A5D) }, | |
9008 | { PREFIX_TABLE (PREFIX_VEX_0F3A5E) }, | |
9009 | { PREFIX_TABLE (PREFIX_VEX_0F3A5F) }, | |
c0f3af97 | 9010 | /* 60 */ |
592a252b L |
9011 | { PREFIX_TABLE (PREFIX_VEX_0F3A60) }, |
9012 | { PREFIX_TABLE (PREFIX_VEX_0F3A61) }, | |
9013 | { PREFIX_TABLE (PREFIX_VEX_0F3A62) }, | |
9014 | { PREFIX_TABLE (PREFIX_VEX_0F3A63) }, | |
592d1631 L |
9015 | { Bad_Opcode }, |
9016 | { Bad_Opcode }, | |
9017 | { Bad_Opcode }, | |
9018 | { Bad_Opcode }, | |
c0f3af97 | 9019 | /* 68 */ |
592a252b L |
9020 | { PREFIX_TABLE (PREFIX_VEX_0F3A68) }, |
9021 | { PREFIX_TABLE (PREFIX_VEX_0F3A69) }, | |
9022 | { PREFIX_TABLE (PREFIX_VEX_0F3A6A) }, | |
9023 | { PREFIX_TABLE (PREFIX_VEX_0F3A6B) }, | |
9024 | { PREFIX_TABLE (PREFIX_VEX_0F3A6C) }, | |
9025 | { PREFIX_TABLE (PREFIX_VEX_0F3A6D) }, | |
9026 | { PREFIX_TABLE (PREFIX_VEX_0F3A6E) }, | |
9027 | { PREFIX_TABLE (PREFIX_VEX_0F3A6F) }, | |
c0f3af97 | 9028 | /* 70 */ |
592d1631 L |
9029 | { Bad_Opcode }, |
9030 | { Bad_Opcode }, | |
9031 | { Bad_Opcode }, | |
9032 | { Bad_Opcode }, | |
9033 | { Bad_Opcode }, | |
9034 | { Bad_Opcode }, | |
9035 | { Bad_Opcode }, | |
9036 | { Bad_Opcode }, | |
c0f3af97 | 9037 | /* 78 */ |
592a252b L |
9038 | { PREFIX_TABLE (PREFIX_VEX_0F3A78) }, |
9039 | { PREFIX_TABLE (PREFIX_VEX_0F3A79) }, | |
9040 | { PREFIX_TABLE (PREFIX_VEX_0F3A7A) }, | |
9041 | { PREFIX_TABLE (PREFIX_VEX_0F3A7B) }, | |
9042 | { PREFIX_TABLE (PREFIX_VEX_0F3A7C) }, | |
9043 | { PREFIX_TABLE (PREFIX_VEX_0F3A7D) }, | |
9044 | { PREFIX_TABLE (PREFIX_VEX_0F3A7E) }, | |
9045 | { PREFIX_TABLE (PREFIX_VEX_0F3A7F) }, | |
c0f3af97 | 9046 | /* 80 */ |
592d1631 L |
9047 | { Bad_Opcode }, |
9048 | { Bad_Opcode }, | |
9049 | { Bad_Opcode }, | |
9050 | { Bad_Opcode }, | |
9051 | { Bad_Opcode }, | |
9052 | { Bad_Opcode }, | |
9053 | { Bad_Opcode }, | |
9054 | { Bad_Opcode }, | |
c0f3af97 | 9055 | /* 88 */ |
592d1631 L |
9056 | { Bad_Opcode }, |
9057 | { Bad_Opcode }, | |
9058 | { Bad_Opcode }, | |
9059 | { Bad_Opcode }, | |
9060 | { Bad_Opcode }, | |
9061 | { Bad_Opcode }, | |
9062 | { Bad_Opcode }, | |
9063 | { Bad_Opcode }, | |
c0f3af97 | 9064 | /* 90 */ |
592d1631 L |
9065 | { Bad_Opcode }, |
9066 | { Bad_Opcode }, | |
9067 | { Bad_Opcode }, | |
9068 | { Bad_Opcode }, | |
9069 | { Bad_Opcode }, | |
9070 | { Bad_Opcode }, | |
9071 | { Bad_Opcode }, | |
9072 | { Bad_Opcode }, | |
c0f3af97 | 9073 | /* 98 */ |
592d1631 L |
9074 | { Bad_Opcode }, |
9075 | { Bad_Opcode }, | |
9076 | { Bad_Opcode }, | |
9077 | { Bad_Opcode }, | |
9078 | { Bad_Opcode }, | |
9079 | { Bad_Opcode }, | |
9080 | { Bad_Opcode }, | |
9081 | { Bad_Opcode }, | |
c0f3af97 | 9082 | /* a0 */ |
592d1631 L |
9083 | { Bad_Opcode }, |
9084 | { Bad_Opcode }, | |
9085 | { Bad_Opcode }, | |
9086 | { Bad_Opcode }, | |
9087 | { Bad_Opcode }, | |
9088 | { Bad_Opcode }, | |
9089 | { Bad_Opcode }, | |
9090 | { Bad_Opcode }, | |
c0f3af97 | 9091 | /* a8 */ |
592d1631 L |
9092 | { Bad_Opcode }, |
9093 | { Bad_Opcode }, | |
9094 | { Bad_Opcode }, | |
9095 | { Bad_Opcode }, | |
9096 | { Bad_Opcode }, | |
9097 | { Bad_Opcode }, | |
9098 | { Bad_Opcode }, | |
9099 | { Bad_Opcode }, | |
c0f3af97 | 9100 | /* b0 */ |
592d1631 L |
9101 | { Bad_Opcode }, |
9102 | { Bad_Opcode }, | |
9103 | { Bad_Opcode }, | |
9104 | { Bad_Opcode }, | |
9105 | { Bad_Opcode }, | |
9106 | { Bad_Opcode }, | |
9107 | { Bad_Opcode }, | |
9108 | { Bad_Opcode }, | |
c0f3af97 | 9109 | /* b8 */ |
592d1631 L |
9110 | { Bad_Opcode }, |
9111 | { Bad_Opcode }, | |
9112 | { Bad_Opcode }, | |
9113 | { Bad_Opcode }, | |
9114 | { Bad_Opcode }, | |
9115 | { Bad_Opcode }, | |
9116 | { Bad_Opcode }, | |
9117 | { Bad_Opcode }, | |
c0f3af97 | 9118 | /* c0 */ |
592d1631 L |
9119 | { Bad_Opcode }, |
9120 | { Bad_Opcode }, | |
9121 | { Bad_Opcode }, | |
9122 | { Bad_Opcode }, | |
9123 | { Bad_Opcode }, | |
9124 | { Bad_Opcode }, | |
9125 | { Bad_Opcode }, | |
9126 | { Bad_Opcode }, | |
c0f3af97 | 9127 | /* c8 */ |
592d1631 L |
9128 | { Bad_Opcode }, |
9129 | { Bad_Opcode }, | |
9130 | { Bad_Opcode }, | |
9131 | { Bad_Opcode }, | |
9132 | { Bad_Opcode }, | |
9133 | { Bad_Opcode }, | |
48521003 IT |
9134 | { PREFIX_TABLE(PREFIX_VEX_0F3ACE) }, |
9135 | { PREFIX_TABLE(PREFIX_VEX_0F3ACF) }, | |
c0f3af97 | 9136 | /* d0 */ |
592d1631 L |
9137 | { Bad_Opcode }, |
9138 | { Bad_Opcode }, | |
9139 | { Bad_Opcode }, | |
9140 | { Bad_Opcode }, | |
9141 | { Bad_Opcode }, | |
9142 | { Bad_Opcode }, | |
9143 | { Bad_Opcode }, | |
9144 | { Bad_Opcode }, | |
c0f3af97 | 9145 | /* d8 */ |
592d1631 L |
9146 | { Bad_Opcode }, |
9147 | { Bad_Opcode }, | |
9148 | { Bad_Opcode }, | |
9149 | { Bad_Opcode }, | |
9150 | { Bad_Opcode }, | |
9151 | { Bad_Opcode }, | |
9152 | { Bad_Opcode }, | |
592a252b | 9153 | { PREFIX_TABLE (PREFIX_VEX_0F3ADF) }, |
c0f3af97 | 9154 | /* e0 */ |
592d1631 L |
9155 | { Bad_Opcode }, |
9156 | { Bad_Opcode }, | |
9157 | { Bad_Opcode }, | |
9158 | { Bad_Opcode }, | |
9159 | { Bad_Opcode }, | |
9160 | { Bad_Opcode }, | |
9161 | { Bad_Opcode }, | |
9162 | { Bad_Opcode }, | |
c0f3af97 | 9163 | /* e8 */ |
592d1631 L |
9164 | { Bad_Opcode }, |
9165 | { Bad_Opcode }, | |
9166 | { Bad_Opcode }, | |
9167 | { Bad_Opcode }, | |
9168 | { Bad_Opcode }, | |
9169 | { Bad_Opcode }, | |
9170 | { Bad_Opcode }, | |
9171 | { Bad_Opcode }, | |
c0f3af97 | 9172 | /* f0 */ |
6c30d220 | 9173 | { PREFIX_TABLE (PREFIX_VEX_0F3AF0) }, |
592d1631 L |
9174 | { Bad_Opcode }, |
9175 | { Bad_Opcode }, | |
9176 | { Bad_Opcode }, | |
9177 | { Bad_Opcode }, | |
9178 | { Bad_Opcode }, | |
9179 | { Bad_Opcode }, | |
9180 | { Bad_Opcode }, | |
c0f3af97 | 9181 | /* f8 */ |
592d1631 L |
9182 | { Bad_Opcode }, |
9183 | { Bad_Opcode }, | |
9184 | { Bad_Opcode }, | |
9185 | { Bad_Opcode }, | |
9186 | { Bad_Opcode }, | |
9187 | { Bad_Opcode }, | |
9188 | { Bad_Opcode }, | |
9189 | { Bad_Opcode }, | |
c0f3af97 L |
9190 | }, |
9191 | }; | |
9192 | ||
43234a1e | 9193 | #include "i386-dis-evex.h" |
ad692897 | 9194 | |
c0f3af97 | 9195 | static const struct dis386 vex_len_table[][2] = { |
18897deb | 9196 | /* VEX_LEN_0F12_P_0_M_0 / VEX_LEN_0F12_P_2_M_0 */ |
c0f3af97 | 9197 | { |
18897deb | 9198 | { "vmovlpX", { XM, Vex128, EXq }, 0 }, |
c0f3af97 L |
9199 | }, |
9200 | ||
592a252b | 9201 | /* VEX_LEN_0F12_P_0_M_1 */ |
c0f3af97 | 9202 | { |
ec6f095a | 9203 | { "vmovhlps", { XM, Vex128, EXq }, 0 }, |
c0f3af97 L |
9204 | }, |
9205 | ||
592a252b | 9206 | /* VEX_LEN_0F13_M_0 */ |
c0f3af97 | 9207 | { |
bf926894 | 9208 | { "vmovlpX", { EXq, XM }, PREFIX_OPCODE }, |
c0f3af97 L |
9209 | }, |
9210 | ||
18897deb | 9211 | /* VEX_LEN_0F16_P_0_M_0 / VEX_LEN_0F16_P_2_M_0 */ |
c0f3af97 | 9212 | { |
18897deb | 9213 | { "vmovhpX", { XM, Vex128, EXq }, 0 }, |
c0f3af97 L |
9214 | }, |
9215 | ||
592a252b | 9216 | /* VEX_LEN_0F16_P_0_M_1 */ |
c0f3af97 | 9217 | { |
ec6f095a | 9218 | { "vmovlhps", { XM, Vex128, EXq }, 0 }, |
c0f3af97 L |
9219 | }, |
9220 | ||
592a252b | 9221 | /* VEX_LEN_0F17_M_0 */ |
c0f3af97 | 9222 | { |
bf926894 | 9223 | { "vmovhpX", { EXq, XM }, PREFIX_OPCODE }, |
c0f3af97 L |
9224 | }, |
9225 | ||
43234a1e L |
9226 | /* VEX_LEN_0F41_P_0 */ |
9227 | { | |
9228 | { Bad_Opcode }, | |
9229 | { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) }, | |
9230 | }, | |
1ba585e8 IT |
9231 | /* VEX_LEN_0F41_P_2 */ |
9232 | { | |
9233 | { Bad_Opcode }, | |
9234 | { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) }, | |
9235 | }, | |
43234a1e L |
9236 | /* VEX_LEN_0F42_P_0 */ |
9237 | { | |
9238 | { Bad_Opcode }, | |
9239 | { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) }, | |
9240 | }, | |
1ba585e8 IT |
9241 | /* VEX_LEN_0F42_P_2 */ |
9242 | { | |
9243 | { Bad_Opcode }, | |
9244 | { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) }, | |
9245 | }, | |
43234a1e L |
9246 | /* VEX_LEN_0F44_P_0 */ |
9247 | { | |
9248 | { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) }, | |
9249 | }, | |
1ba585e8 IT |
9250 | /* VEX_LEN_0F44_P_2 */ |
9251 | { | |
9252 | { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) }, | |
9253 | }, | |
43234a1e L |
9254 | /* VEX_LEN_0F45_P_0 */ |
9255 | { | |
9256 | { Bad_Opcode }, | |
9257 | { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) }, | |
9258 | }, | |
1ba585e8 IT |
9259 | /* VEX_LEN_0F45_P_2 */ |
9260 | { | |
9261 | { Bad_Opcode }, | |
9262 | { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) }, | |
9263 | }, | |
43234a1e L |
9264 | /* VEX_LEN_0F46_P_0 */ |
9265 | { | |
9266 | { Bad_Opcode }, | |
9267 | { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) }, | |
9268 | }, | |
1ba585e8 IT |
9269 | /* VEX_LEN_0F46_P_2 */ |
9270 | { | |
9271 | { Bad_Opcode }, | |
9272 | { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) }, | |
9273 | }, | |
43234a1e L |
9274 | /* VEX_LEN_0F47_P_0 */ |
9275 | { | |
9276 | { Bad_Opcode }, | |
9277 | { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) }, | |
9278 | }, | |
1ba585e8 IT |
9279 | /* VEX_LEN_0F47_P_2 */ |
9280 | { | |
9281 | { Bad_Opcode }, | |
9282 | { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) }, | |
9283 | }, | |
9284 | /* VEX_LEN_0F4A_P_0 */ | |
9285 | { | |
9286 | { Bad_Opcode }, | |
9287 | { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) }, | |
9288 | }, | |
9289 | /* VEX_LEN_0F4A_P_2 */ | |
9290 | { | |
9291 | { Bad_Opcode }, | |
9292 | { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) }, | |
9293 | }, | |
9294 | /* VEX_LEN_0F4B_P_0 */ | |
9295 | { | |
9296 | { Bad_Opcode }, | |
9297 | { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) }, | |
9298 | }, | |
43234a1e L |
9299 | /* VEX_LEN_0F4B_P_2 */ |
9300 | { | |
9301 | { Bad_Opcode }, | |
9302 | { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) }, | |
9303 | }, | |
9304 | ||
ec6f095a | 9305 | /* VEX_LEN_0F6E_P_2 */ |
c0f3af97 | 9306 | { |
ec6f095a | 9307 | { "vmovK", { XMScalar, Edq }, 0 }, |
c0f3af97 L |
9308 | }, |
9309 | ||
ec6f095a | 9310 | /* VEX_LEN_0F77_P_1 */ |
c0f3af97 | 9311 | { |
ec6f095a L |
9312 | { "vzeroupper", { XX }, 0 }, |
9313 | { "vzeroall", { XX }, 0 }, | |
c0f3af97 L |
9314 | }, |
9315 | ||
ec6f095a | 9316 | /* VEX_LEN_0F7E_P_1 */ |
c0f3af97 | 9317 | { |
5b872f7d | 9318 | { "vmovq", { XMScalar, EXxmm_mq }, 0 }, |
c0f3af97 L |
9319 | }, |
9320 | ||
ec6f095a | 9321 | /* VEX_LEN_0F7E_P_2 */ |
c0f3af97 | 9322 | { |
ec6f095a | 9323 | { "vmovK", { Edq, XMScalar }, 0 }, |
c0f3af97 L |
9324 | }, |
9325 | ||
ec6f095a | 9326 | /* VEX_LEN_0F90_P_0 */ |
c0f3af97 | 9327 | { |
ec6f095a | 9328 | { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) }, |
c0f3af97 L |
9329 | }, |
9330 | ||
ec6f095a | 9331 | /* VEX_LEN_0F90_P_2 */ |
c0f3af97 | 9332 | { |
ec6f095a | 9333 | { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) }, |
c0f3af97 L |
9334 | }, |
9335 | ||
ec6f095a | 9336 | /* VEX_LEN_0F91_P_0 */ |
c0f3af97 | 9337 | { |
ec6f095a | 9338 | { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) }, |
c0f3af97 L |
9339 | }, |
9340 | ||
ec6f095a | 9341 | /* VEX_LEN_0F91_P_2 */ |
c0f3af97 | 9342 | { |
ec6f095a | 9343 | { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) }, |
c0f3af97 L |
9344 | }, |
9345 | ||
ec6f095a | 9346 | /* VEX_LEN_0F92_P_0 */ |
c0f3af97 | 9347 | { |
ec6f095a | 9348 | { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) }, |
c0f3af97 L |
9349 | }, |
9350 | ||
ec6f095a | 9351 | /* VEX_LEN_0F92_P_2 */ |
c0f3af97 | 9352 | { |
ec6f095a | 9353 | { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) }, |
c0f3af97 L |
9354 | }, |
9355 | ||
ec6f095a | 9356 | /* VEX_LEN_0F92_P_3 */ |
c0f3af97 | 9357 | { |
58a211d2 | 9358 | { MOD_TABLE (MOD_VEX_0F92_P_3_LEN_0) }, |
c0f3af97 L |
9359 | }, |
9360 | ||
ec6f095a | 9361 | /* VEX_LEN_0F93_P_0 */ |
c0f3af97 | 9362 | { |
ec6f095a | 9363 | { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) }, |
c0f3af97 L |
9364 | }, |
9365 | ||
ec6f095a | 9366 | /* VEX_LEN_0F93_P_2 */ |
c0f3af97 | 9367 | { |
ec6f095a | 9368 | { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) }, |
c0f3af97 L |
9369 | }, |
9370 | ||
ec6f095a | 9371 | /* VEX_LEN_0F93_P_3 */ |
c0f3af97 | 9372 | { |
58a211d2 | 9373 | { MOD_TABLE (MOD_VEX_0F93_P_3_LEN_0) }, |
c0f3af97 L |
9374 | }, |
9375 | ||
ec6f095a | 9376 | /* VEX_LEN_0F98_P_0 */ |
43234a1e L |
9377 | { |
9378 | { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) }, | |
9379 | }, | |
9380 | ||
1ba585e8 IT |
9381 | /* VEX_LEN_0F98_P_2 */ |
9382 | { | |
9383 | { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) }, | |
9384 | }, | |
9385 | ||
9386 | /* VEX_LEN_0F99_P_0 */ | |
9387 | { | |
9388 | { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) }, | |
9389 | }, | |
9390 | ||
9391 | /* VEX_LEN_0F99_P_2 */ | |
9392 | { | |
9393 | { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0) }, | |
9394 | }, | |
9395 | ||
6c30d220 | 9396 | /* VEX_LEN_0FAE_R_2_M_0 */ |
c0f3af97 | 9397 | { |
ec6f095a | 9398 | { "vldmxcsr", { Md }, 0 }, |
c0f3af97 L |
9399 | }, |
9400 | ||
6c30d220 | 9401 | /* VEX_LEN_0FAE_R_3_M_0 */ |
c0f3af97 | 9402 | { |
ec6f095a | 9403 | { "vstmxcsr", { Md }, 0 }, |
c0f3af97 L |
9404 | }, |
9405 | ||
6c30d220 | 9406 | /* VEX_LEN_0FC4_P_2 */ |
c0f3af97 | 9407 | { |
b50c9f31 | 9408 | { "vpinsrw", { XM, Vex128, Edqw, Ib }, 0 }, |
c0f3af97 L |
9409 | }, |
9410 | ||
6c30d220 | 9411 | /* VEX_LEN_0FC5_P_2 */ |
c0f3af97 | 9412 | { |
b50c9f31 | 9413 | { "vpextrw", { Gdq, XS, Ib }, 0 }, |
c0f3af97 L |
9414 | }, |
9415 | ||
6c30d220 | 9416 | /* VEX_LEN_0FD6_P_2 */ |
c0f3af97 | 9417 | { |
39e0f456 | 9418 | { "vmovq", { EXqVexScalarS, XMScalar }, 0 }, |
c0f3af97 L |
9419 | }, |
9420 | ||
6c30d220 | 9421 | /* VEX_LEN_0FF7_P_2 */ |
c0f3af97 | 9422 | { |
ec6f095a | 9423 | { "vmaskmovdqu", { XM, XS }, 0 }, |
c0f3af97 L |
9424 | }, |
9425 | ||
6c30d220 | 9426 | /* VEX_LEN_0F3816_P_2 */ |
c0f3af97 | 9427 | { |
6c30d220 L |
9428 | { Bad_Opcode }, |
9429 | { VEX_W_TABLE (VEX_W_0F3816_P_2) }, | |
c0f3af97 L |
9430 | }, |
9431 | ||
6c30d220 | 9432 | /* VEX_LEN_0F3819_P_2 */ |
c0f3af97 | 9433 | { |
6c30d220 L |
9434 | { Bad_Opcode }, |
9435 | { VEX_W_TABLE (VEX_W_0F3819_P_2) }, | |
c0f3af97 L |
9436 | }, |
9437 | ||
6c30d220 | 9438 | /* VEX_LEN_0F381A_P_2_M_0 */ |
c0f3af97 | 9439 | { |
6c30d220 L |
9440 | { Bad_Opcode }, |
9441 | { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) }, | |
c0f3af97 L |
9442 | }, |
9443 | ||
6c30d220 | 9444 | /* VEX_LEN_0F3836_P_2 */ |
c0f3af97 | 9445 | { |
6c30d220 L |
9446 | { Bad_Opcode }, |
9447 | { VEX_W_TABLE (VEX_W_0F3836_P_2) }, | |
c0f3af97 L |
9448 | }, |
9449 | ||
592a252b | 9450 | /* VEX_LEN_0F3841_P_2 */ |
c0f3af97 | 9451 | { |
ec6f095a | 9452 | { "vphminposuw", { XM, EXx }, 0 }, |
c0f3af97 L |
9453 | }, |
9454 | ||
6c30d220 L |
9455 | /* VEX_LEN_0F385A_P_2_M_0 */ |
9456 | { | |
9457 | { Bad_Opcode }, | |
9458 | { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) }, | |
9459 | }, | |
9460 | ||
592a252b | 9461 | /* VEX_LEN_0F38DB_P_2 */ |
a5ff0eb2 | 9462 | { |
ec6f095a | 9463 | { "vaesimc", { XM, EXx }, 0 }, |
a5ff0eb2 L |
9464 | }, |
9465 | ||
f12dc422 L |
9466 | /* VEX_LEN_0F38F2_P_0 */ |
9467 | { | |
bf890a93 | 9468 | { "andnS", { Gdq, VexGdq, Edq }, 0 }, |
f12dc422 L |
9469 | }, |
9470 | ||
9471 | /* VEX_LEN_0F38F3_R_1_P_0 */ | |
9472 | { | |
bf890a93 | 9473 | { "blsrS", { VexGdq, Edq }, 0 }, |
f12dc422 L |
9474 | }, |
9475 | ||
9476 | /* VEX_LEN_0F38F3_R_2_P_0 */ | |
9477 | { | |
bf890a93 | 9478 | { "blsmskS", { VexGdq, Edq }, 0 }, |
f12dc422 L |
9479 | }, |
9480 | ||
9481 | /* VEX_LEN_0F38F3_R_3_P_0 */ | |
9482 | { | |
bf890a93 | 9483 | { "blsiS", { VexGdq, Edq }, 0 }, |
f12dc422 L |
9484 | }, |
9485 | ||
6c30d220 L |
9486 | /* VEX_LEN_0F38F5_P_0 */ |
9487 | { | |
bf890a93 | 9488 | { "bzhiS", { Gdq, Edq, VexGdq }, 0 }, |
6c30d220 L |
9489 | }, |
9490 | ||
9491 | /* VEX_LEN_0F38F5_P_1 */ | |
9492 | { | |
bf890a93 | 9493 | { "pextS", { Gdq, VexGdq, Edq }, 0 }, |
6c30d220 L |
9494 | }, |
9495 | ||
9496 | /* VEX_LEN_0F38F5_P_3 */ | |
9497 | { | |
bf890a93 | 9498 | { "pdepS", { Gdq, VexGdq, Edq }, 0 }, |
6c30d220 L |
9499 | }, |
9500 | ||
9501 | /* VEX_LEN_0F38F6_P_3 */ | |
9502 | { | |
bf890a93 | 9503 | { "mulxS", { Gdq, VexGdq, Edq }, 0 }, |
6c30d220 L |
9504 | }, |
9505 | ||
f12dc422 L |
9506 | /* VEX_LEN_0F38F7_P_0 */ |
9507 | { | |
bf890a93 | 9508 | { "bextrS", { Gdq, Edq, VexGdq }, 0 }, |
f12dc422 L |
9509 | }, |
9510 | ||
6c30d220 L |
9511 | /* VEX_LEN_0F38F7_P_1 */ |
9512 | { | |
bf890a93 | 9513 | { "sarxS", { Gdq, Edq, VexGdq }, 0 }, |
6c30d220 L |
9514 | }, |
9515 | ||
9516 | /* VEX_LEN_0F38F7_P_2 */ | |
9517 | { | |
bf890a93 | 9518 | { "shlxS", { Gdq, Edq, VexGdq }, 0 }, |
6c30d220 L |
9519 | }, |
9520 | ||
9521 | /* VEX_LEN_0F38F7_P_3 */ | |
9522 | { | |
bf890a93 | 9523 | { "shrxS", { Gdq, Edq, VexGdq }, 0 }, |
6c30d220 L |
9524 | }, |
9525 | ||
9526 | /* VEX_LEN_0F3A00_P_2 */ | |
9527 | { | |
9528 | { Bad_Opcode }, | |
9529 | { VEX_W_TABLE (VEX_W_0F3A00_P_2) }, | |
9530 | }, | |
9531 | ||
9532 | /* VEX_LEN_0F3A01_P_2 */ | |
9533 | { | |
9534 | { Bad_Opcode }, | |
9535 | { VEX_W_TABLE (VEX_W_0F3A01_P_2) }, | |
9536 | }, | |
9537 | ||
592a252b | 9538 | /* VEX_LEN_0F3A06_P_2 */ |
c0f3af97 | 9539 | { |
592d1631 | 9540 | { Bad_Opcode }, |
592a252b | 9541 | { VEX_W_TABLE (VEX_W_0F3A06_P_2) }, |
c0f3af97 L |
9542 | }, |
9543 | ||
592a252b | 9544 | /* VEX_LEN_0F3A14_P_2 */ |
c0f3af97 | 9545 | { |
b50c9f31 | 9546 | { "vpextrb", { Edqb, XM, Ib }, 0 }, |
c0f3af97 L |
9547 | }, |
9548 | ||
592a252b | 9549 | /* VEX_LEN_0F3A15_P_2 */ |
c0f3af97 | 9550 | { |
b50c9f31 | 9551 | { "vpextrw", { Edqw, XM, Ib }, 0 }, |
c0f3af97 L |
9552 | }, |
9553 | ||
592a252b | 9554 | /* VEX_LEN_0F3A16_P_2 */ |
c0f3af97 | 9555 | { |
bf890a93 | 9556 | { "vpextrK", { Edq, XM, Ib }, 0 }, |
c0f3af97 L |
9557 | }, |
9558 | ||
592a252b | 9559 | /* VEX_LEN_0F3A17_P_2 */ |
c0f3af97 | 9560 | { |
bf890a93 | 9561 | { "vextractps", { Edqd, XM, Ib }, 0 }, |
c0f3af97 L |
9562 | }, |
9563 | ||
592a252b | 9564 | /* VEX_LEN_0F3A18_P_2 */ |
c0f3af97 | 9565 | { |
592d1631 | 9566 | { Bad_Opcode }, |
592a252b | 9567 | { VEX_W_TABLE (VEX_W_0F3A18_P_2) }, |
c0f3af97 L |
9568 | }, |
9569 | ||
592a252b | 9570 | /* VEX_LEN_0F3A19_P_2 */ |
c0f3af97 | 9571 | { |
592d1631 | 9572 | { Bad_Opcode }, |
592a252b | 9573 | { VEX_W_TABLE (VEX_W_0F3A19_P_2) }, |
c0f3af97 L |
9574 | }, |
9575 | ||
592a252b | 9576 | /* VEX_LEN_0F3A20_P_2 */ |
c0f3af97 | 9577 | { |
b50c9f31 | 9578 | { "vpinsrb", { XM, Vex128, Edqb, Ib }, 0 }, |
c0f3af97 L |
9579 | }, |
9580 | ||
592a252b | 9581 | /* VEX_LEN_0F3A21_P_2 */ |
c0f3af97 | 9582 | { |
ec6f095a | 9583 | { "vinsertps", { XM, Vex128, EXd, Ib }, 0 }, |
c0f3af97 L |
9584 | }, |
9585 | ||
592a252b | 9586 | /* VEX_LEN_0F3A22_P_2 */ |
c0f3af97 | 9587 | { |
bf890a93 | 9588 | { "vpinsrK", { XM, Vex128, Edq, Ib }, 0 }, |
c0f3af97 L |
9589 | }, |
9590 | ||
43234a1e L |
9591 | /* VEX_LEN_0F3A30_P_2 */ |
9592 | { | |
9593 | { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) }, | |
9594 | }, | |
9595 | ||
1ba585e8 IT |
9596 | /* VEX_LEN_0F3A31_P_2 */ |
9597 | { | |
9598 | { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0) }, | |
9599 | }, | |
9600 | ||
43234a1e L |
9601 | /* VEX_LEN_0F3A32_P_2 */ |
9602 | { | |
9603 | { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) }, | |
9604 | }, | |
9605 | ||
1ba585e8 IT |
9606 | /* VEX_LEN_0F3A33_P_2 */ |
9607 | { | |
9608 | { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0) }, | |
9609 | }, | |
9610 | ||
6c30d220 | 9611 | /* VEX_LEN_0F3A38_P_2 */ |
c0f3af97 | 9612 | { |
6c30d220 L |
9613 | { Bad_Opcode }, |
9614 | { VEX_W_TABLE (VEX_W_0F3A38_P_2) }, | |
c0f3af97 L |
9615 | }, |
9616 | ||
6c30d220 | 9617 | /* VEX_LEN_0F3A39_P_2 */ |
c0f3af97 | 9618 | { |
6c30d220 L |
9619 | { Bad_Opcode }, |
9620 | { VEX_W_TABLE (VEX_W_0F3A39_P_2) }, | |
9621 | }, | |
9622 | ||
9623 | /* VEX_LEN_0F3A41_P_2 */ | |
9624 | { | |
ec6f095a | 9625 | { "vdppd", { XM, Vex128, EXx, Ib }, 0 }, |
c0f3af97 L |
9626 | }, |
9627 | ||
6c30d220 | 9628 | /* VEX_LEN_0F3A46_P_2 */ |
c0f3af97 | 9629 | { |
6c30d220 L |
9630 | { Bad_Opcode }, |
9631 | { VEX_W_TABLE (VEX_W_0F3A46_P_2) }, | |
c0f3af97 L |
9632 | }, |
9633 | ||
592a252b | 9634 | /* VEX_LEN_0F3A60_P_2 */ |
c0f3af97 | 9635 | { |
15c7c1d8 | 9636 | { "vpcmpestrm", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 }, |
c0f3af97 L |
9637 | }, |
9638 | ||
592a252b | 9639 | /* VEX_LEN_0F3A61_P_2 */ |
c0f3af97 | 9640 | { |
15c7c1d8 | 9641 | { "vpcmpestri", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 }, |
c0f3af97 L |
9642 | }, |
9643 | ||
592a252b | 9644 | /* VEX_LEN_0F3A62_P_2 */ |
c0f3af97 | 9645 | { |
ec6f095a | 9646 | { "vpcmpistrm", { XM, EXx, Ib }, 0 }, |
c0f3af97 L |
9647 | }, |
9648 | ||
592a252b | 9649 | /* VEX_LEN_0F3A63_P_2 */ |
c0f3af97 | 9650 | { |
ec6f095a | 9651 | { "vpcmpistri", { XM, EXx, Ib }, 0 }, |
c0f3af97 L |
9652 | }, |
9653 | ||
592a252b | 9654 | /* VEX_LEN_0F3A6A_P_2 */ |
922d8de8 | 9655 | { |
3a2430e0 | 9656 | { "vfmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 }, |
922d8de8 DR |
9657 | }, |
9658 | ||
592a252b | 9659 | /* VEX_LEN_0F3A6B_P_2 */ |
922d8de8 | 9660 | { |
3a2430e0 | 9661 | { "vfmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 }, |
922d8de8 DR |
9662 | }, |
9663 | ||
592a252b | 9664 | /* VEX_LEN_0F3A6E_P_2 */ |
922d8de8 | 9665 | { |
3a2430e0 | 9666 | { "vfmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 }, |
922d8de8 DR |
9667 | }, |
9668 | ||
592a252b | 9669 | /* VEX_LEN_0F3A6F_P_2 */ |
922d8de8 | 9670 | { |
3a2430e0 | 9671 | { "vfmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 }, |
922d8de8 DR |
9672 | }, |
9673 | ||
592a252b | 9674 | /* VEX_LEN_0F3A7A_P_2 */ |
922d8de8 | 9675 | { |
3a2430e0 | 9676 | { "vfnmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 }, |
922d8de8 DR |
9677 | }, |
9678 | ||
592a252b | 9679 | /* VEX_LEN_0F3A7B_P_2 */ |
922d8de8 | 9680 | { |
3a2430e0 | 9681 | { "vfnmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 }, |
922d8de8 DR |
9682 | }, |
9683 | ||
592a252b | 9684 | /* VEX_LEN_0F3A7E_P_2 */ |
922d8de8 | 9685 | { |
3a2430e0 | 9686 | { "vfnmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 }, |
922d8de8 DR |
9687 | }, |
9688 | ||
592a252b | 9689 | /* VEX_LEN_0F3A7F_P_2 */ |
922d8de8 | 9690 | { |
3a2430e0 | 9691 | { "vfnmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 }, |
922d8de8 DR |
9692 | }, |
9693 | ||
592a252b | 9694 | /* VEX_LEN_0F3ADF_P_2 */ |
a5ff0eb2 | 9695 | { |
ec6f095a | 9696 | { "vaeskeygenassist", { XM, EXx, Ib }, 0 }, |
a5ff0eb2 | 9697 | }, |
4c807e72 | 9698 | |
6c30d220 L |
9699 | /* VEX_LEN_0F3AF0_P_3 */ |
9700 | { | |
bf890a93 | 9701 | { "rorxS", { Gdq, Edq, Ib }, 0 }, |
6c30d220 L |
9702 | }, |
9703 | ||
ff688e1f L |
9704 | /* VEX_LEN_0FXOP_08_CC */ |
9705 | { | |
be92cb14 | 9706 | { "vpcomb", { XM, Vex128, EXx, VPCOM }, 0 }, |
ff688e1f L |
9707 | }, |
9708 | ||
9709 | /* VEX_LEN_0FXOP_08_CD */ | |
9710 | { | |
be92cb14 | 9711 | { "vpcomw", { XM, Vex128, EXx, VPCOM }, 0 }, |
ff688e1f L |
9712 | }, |
9713 | ||
9714 | /* VEX_LEN_0FXOP_08_CE */ | |
9715 | { | |
be92cb14 | 9716 | { "vpcomd", { XM, Vex128, EXx, VPCOM }, 0 }, |
ff688e1f L |
9717 | }, |
9718 | ||
9719 | /* VEX_LEN_0FXOP_08_CF */ | |
9720 | { | |
be92cb14 | 9721 | { "vpcomq", { XM, Vex128, EXx, VPCOM }, 0 }, |
ff688e1f L |
9722 | }, |
9723 | ||
9724 | /* VEX_LEN_0FXOP_08_EC */ | |
9725 | { | |
be92cb14 | 9726 | { "vpcomub", { XM, Vex128, EXx, VPCOM }, 0 }, |
ff688e1f L |
9727 | }, |
9728 | ||
9729 | /* VEX_LEN_0FXOP_08_ED */ | |
9730 | { | |
be92cb14 | 9731 | { "vpcomuw", { XM, Vex128, EXx, VPCOM }, 0 }, |
ff688e1f L |
9732 | }, |
9733 | ||
9734 | /* VEX_LEN_0FXOP_08_EE */ | |
9735 | { | |
be92cb14 | 9736 | { "vpcomud", { XM, Vex128, EXx, VPCOM }, 0 }, |
ff688e1f L |
9737 | }, |
9738 | ||
9739 | /* VEX_LEN_0FXOP_08_EF */ | |
9740 | { | |
be92cb14 | 9741 | { "vpcomuq", { XM, Vex128, EXx, VPCOM }, 0 }, |
ff688e1f L |
9742 | }, |
9743 | ||
592a252b | 9744 | /* VEX_LEN_0FXOP_09_80 */ |
5dd85c99 | 9745 | { |
bf890a93 IT |
9746 | { "vfrczps", { XM, EXxmm }, 0 }, |
9747 | { "vfrczps", { XM, EXymmq }, 0 }, | |
5dd85c99 | 9748 | }, |
4c807e72 | 9749 | |
592a252b | 9750 | /* VEX_LEN_0FXOP_09_81 */ |
5dd85c99 | 9751 | { |
bf890a93 IT |
9752 | { "vfrczpd", { XM, EXxmm }, 0 }, |
9753 | { "vfrczpd", { XM, EXymmq }, 0 }, | |
5dd85c99 | 9754 | }, |
331d2d0d L |
9755 | }; |
9756 | ||
ad692897 | 9757 | #include "i386-dis-evex-len.h" |
04e2a182 | 9758 | |
9e30b8e0 | 9759 | static const struct dis386 vex_w_table[][2] = { |
43234a1e L |
9760 | { |
9761 | /* VEX_W_0F41_P_0_LEN_1 */ | |
ab4e4ed5 AF |
9762 | { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1) }, |
9763 | { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1) }, | |
1ba585e8 IT |
9764 | }, |
9765 | { | |
9766 | /* VEX_W_0F41_P_2_LEN_1 */ | |
ab4e4ed5 AF |
9767 | { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1) }, |
9768 | { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1) } | |
43234a1e L |
9769 | }, |
9770 | { | |
9771 | /* VEX_W_0F42_P_0_LEN_1 */ | |
ab4e4ed5 AF |
9772 | { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1) }, |
9773 | { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1) }, | |
1ba585e8 IT |
9774 | }, |
9775 | { | |
9776 | /* VEX_W_0F42_P_2_LEN_1 */ | |
ab4e4ed5 AF |
9777 | { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1) }, |
9778 | { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1) }, | |
43234a1e L |
9779 | }, |
9780 | { | |
9781 | /* VEX_W_0F44_P_0_LEN_0 */ | |
ab4e4ed5 AF |
9782 | { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1) }, |
9783 | { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1) }, | |
1ba585e8 IT |
9784 | }, |
9785 | { | |
9786 | /* VEX_W_0F44_P_2_LEN_0 */ | |
ab4e4ed5 AF |
9787 | { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1) }, |
9788 | { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1) }, | |
43234a1e L |
9789 | }, |
9790 | { | |
ec6f095a L |
9791 | /* VEX_W_0F45_P_0_LEN_1 */ |
9792 | { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1) }, | |
9793 | { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1) }, | |
9e30b8e0 L |
9794 | }, |
9795 | { | |
ec6f095a L |
9796 | /* VEX_W_0F45_P_2_LEN_1 */ |
9797 | { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1) }, | |
9798 | { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1) }, | |
9e30b8e0 L |
9799 | }, |
9800 | { | |
ec6f095a L |
9801 | /* VEX_W_0F46_P_0_LEN_1 */ |
9802 | { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1) }, | |
9803 | { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1) }, | |
9e30b8e0 L |
9804 | }, |
9805 | { | |
ec6f095a L |
9806 | /* VEX_W_0F46_P_2_LEN_1 */ |
9807 | { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1) }, | |
9808 | { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1) }, | |
9e30b8e0 L |
9809 | }, |
9810 | { | |
ec6f095a L |
9811 | /* VEX_W_0F47_P_0_LEN_1 */ |
9812 | { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1) }, | |
9813 | { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1) }, | |
9e30b8e0 L |
9814 | }, |
9815 | { | |
ec6f095a L |
9816 | /* VEX_W_0F47_P_2_LEN_1 */ |
9817 | { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1) }, | |
9818 | { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1) }, | |
9e30b8e0 L |
9819 | }, |
9820 | { | |
ec6f095a L |
9821 | /* VEX_W_0F4A_P_0_LEN_1 */ |
9822 | { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1) }, | |
9823 | { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1) }, | |
9e30b8e0 L |
9824 | }, |
9825 | { | |
ec6f095a L |
9826 | /* VEX_W_0F4A_P_2_LEN_1 */ |
9827 | { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1) }, | |
9828 | { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1) }, | |
9e30b8e0 L |
9829 | }, |
9830 | { | |
ec6f095a L |
9831 | /* VEX_W_0F4B_P_0_LEN_1 */ |
9832 | { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1) }, | |
9833 | { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1) }, | |
9e30b8e0 L |
9834 | }, |
9835 | { | |
ec6f095a L |
9836 | /* VEX_W_0F4B_P_2_LEN_1 */ |
9837 | { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1) }, | |
9e30b8e0 L |
9838 | }, |
9839 | { | |
ec6f095a L |
9840 | /* VEX_W_0F90_P_0_LEN_0 */ |
9841 | { "kmovw", { MaskG, MaskE }, 0 }, | |
9842 | { "kmovq", { MaskG, MaskE }, 0 }, | |
9e30b8e0 L |
9843 | }, |
9844 | { | |
ec6f095a L |
9845 | /* VEX_W_0F90_P_2_LEN_0 */ |
9846 | { "kmovb", { MaskG, MaskBDE }, 0 }, | |
9847 | { "kmovd", { MaskG, MaskBDE }, 0 }, | |
9e30b8e0 L |
9848 | }, |
9849 | { | |
ec6f095a L |
9850 | /* VEX_W_0F91_P_0_LEN_0 */ |
9851 | { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0) }, | |
9852 | { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0) }, | |
9e30b8e0 L |
9853 | }, |
9854 | { | |
ec6f095a L |
9855 | /* VEX_W_0F91_P_2_LEN_0 */ |
9856 | { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0) }, | |
9857 | { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0) }, | |
9e30b8e0 L |
9858 | }, |
9859 | { | |
ec6f095a L |
9860 | /* VEX_W_0F92_P_0_LEN_0 */ |
9861 | { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0) }, | |
9e30b8e0 L |
9862 | }, |
9863 | { | |
ec6f095a L |
9864 | /* VEX_W_0F92_P_2_LEN_0 */ |
9865 | { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0) }, | |
9e30b8e0 | 9866 | }, |
9e30b8e0 | 9867 | { |
ec6f095a L |
9868 | /* VEX_W_0F93_P_0_LEN_0 */ |
9869 | { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0) }, | |
9e30b8e0 L |
9870 | }, |
9871 | { | |
ec6f095a L |
9872 | /* VEX_W_0F93_P_2_LEN_0 */ |
9873 | { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0) }, | |
9e30b8e0 | 9874 | }, |
9e30b8e0 | 9875 | { |
ec6f095a L |
9876 | /* VEX_W_0F98_P_0_LEN_0 */ |
9877 | { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0) }, | |
9878 | { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0) }, | |
9e30b8e0 L |
9879 | }, |
9880 | { | |
ec6f095a L |
9881 | /* VEX_W_0F98_P_2_LEN_0 */ |
9882 | { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0) }, | |
9883 | { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0) }, | |
9e30b8e0 L |
9884 | }, |
9885 | { | |
ec6f095a L |
9886 | /* VEX_W_0F99_P_0_LEN_0 */ |
9887 | { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0) }, | |
9888 | { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0) }, | |
9e30b8e0 L |
9889 | }, |
9890 | { | |
ec6f095a L |
9891 | /* VEX_W_0F99_P_2_LEN_0 */ |
9892 | { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0) }, | |
9893 | { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0) }, | |
9e30b8e0 | 9894 | }, |
9e30b8e0 | 9895 | { |
592a252b | 9896 | /* VEX_W_0F380C_P_2 */ |
bf890a93 | 9897 | { "vpermilps", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
9898 | }, |
9899 | { | |
592a252b | 9900 | /* VEX_W_0F380D_P_2 */ |
bf890a93 | 9901 | { "vpermilpd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
9902 | }, |
9903 | { | |
592a252b | 9904 | /* VEX_W_0F380E_P_2 */ |
bf890a93 | 9905 | { "vtestps", { XM, EXx }, 0 }, |
9e30b8e0 L |
9906 | }, |
9907 | { | |
592a252b | 9908 | /* VEX_W_0F380F_P_2 */ |
bf890a93 | 9909 | { "vtestpd", { XM, EXx }, 0 }, |
9e30b8e0 | 9910 | }, |
6431c801 JB |
9911 | { |
9912 | /* VEX_W_0F3813_P_2 */ | |
9913 | { "vcvtph2ps", { XM, EXxmmq }, 0 }, | |
9914 | }, | |
6c30d220 L |
9915 | { |
9916 | /* VEX_W_0F3816_P_2 */ | |
bf890a93 | 9917 | { "vpermps", { XM, Vex, EXx }, 0 }, |
6c30d220 | 9918 | }, |
bcf2684f | 9919 | { |
6c30d220 | 9920 | /* VEX_W_0F3818_P_2 */ |
bf890a93 | 9921 | { "vbroadcastss", { XM, EXxmm_md }, 0 }, |
bcf2684f | 9922 | }, |
9e30b8e0 | 9923 | { |
6c30d220 | 9924 | /* VEX_W_0F3819_P_2 */ |
bf890a93 | 9925 | { "vbroadcastsd", { XM, EXxmm_mq }, 0 }, |
9e30b8e0 L |
9926 | }, |
9927 | { | |
592a252b | 9928 | /* VEX_W_0F381A_P_2_M_0 */ |
bf890a93 | 9929 | { "vbroadcastf128", { XM, Mxmm }, 0 }, |
9e30b8e0 | 9930 | }, |
53aa04a0 | 9931 | { |
592a252b | 9932 | /* VEX_W_0F382C_P_2_M_0 */ |
bf890a93 | 9933 | { "vmaskmovps", { XM, Vex, Mx }, 0 }, |
53aa04a0 L |
9934 | }, |
9935 | { | |
592a252b | 9936 | /* VEX_W_0F382D_P_2_M_0 */ |
bf890a93 | 9937 | { "vmaskmovpd", { XM, Vex, Mx }, 0 }, |
53aa04a0 L |
9938 | }, |
9939 | { | |
592a252b | 9940 | /* VEX_W_0F382E_P_2_M_0 */ |
bf890a93 | 9941 | { "vmaskmovps", { Mx, Vex, XM }, 0 }, |
53aa04a0 L |
9942 | }, |
9943 | { | |
592a252b | 9944 | /* VEX_W_0F382F_P_2_M_0 */ |
bf890a93 | 9945 | { "vmaskmovpd", { Mx, Vex, XM }, 0 }, |
53aa04a0 | 9946 | }, |
6c30d220 L |
9947 | { |
9948 | /* VEX_W_0F3836_P_2 */ | |
bf890a93 | 9949 | { "vpermd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 | 9950 | }, |
6c30d220 L |
9951 | { |
9952 | /* VEX_W_0F3846_P_2 */ | |
bf890a93 | 9953 | { "vpsravd", { XM, Vex, EXx }, 0 }, |
6c30d220 L |
9954 | }, |
9955 | { | |
9956 | /* VEX_W_0F3858_P_2 */ | |
bf890a93 | 9957 | { "vpbroadcastd", { XM, EXxmm_md }, 0 }, |
6c30d220 L |
9958 | }, |
9959 | { | |
9960 | /* VEX_W_0F3859_P_2 */ | |
bf890a93 | 9961 | { "vpbroadcastq", { XM, EXxmm_mq }, 0 }, |
6c30d220 L |
9962 | }, |
9963 | { | |
9964 | /* VEX_W_0F385A_P_2_M_0 */ | |
bf890a93 | 9965 | { "vbroadcasti128", { XM, Mxmm }, 0 }, |
6c30d220 L |
9966 | }, |
9967 | { | |
9968 | /* VEX_W_0F3878_P_2 */ | |
bf890a93 | 9969 | { "vpbroadcastb", { XM, EXxmm_mb }, 0 }, |
6c30d220 L |
9970 | }, |
9971 | { | |
9972 | /* VEX_W_0F3879_P_2 */ | |
bf890a93 | 9973 | { "vpbroadcastw", { XM, EXxmm_mw }, 0 }, |
6c30d220 | 9974 | }, |
48521003 IT |
9975 | { |
9976 | /* VEX_W_0F38CF_P_2 */ | |
9977 | { "vgf2p8mulb", { XM, Vex, EXx }, 0 }, | |
9978 | }, | |
6c30d220 L |
9979 | { |
9980 | /* VEX_W_0F3A00_P_2 */ | |
9981 | { Bad_Opcode }, | |
bf890a93 | 9982 | { "vpermq", { XM, EXx, Ib }, 0 }, |
6c30d220 L |
9983 | }, |
9984 | { | |
9985 | /* VEX_W_0F3A01_P_2 */ | |
9986 | { Bad_Opcode }, | |
bf890a93 | 9987 | { "vpermpd", { XM, EXx, Ib }, 0 }, |
6c30d220 L |
9988 | }, |
9989 | { | |
9990 | /* VEX_W_0F3A02_P_2 */ | |
bf890a93 | 9991 | { "vpblendd", { XM, Vex, EXx, Ib }, 0 }, |
6c30d220 | 9992 | }, |
9e30b8e0 | 9993 | { |
592a252b | 9994 | /* VEX_W_0F3A04_P_2 */ |
bf890a93 | 9995 | { "vpermilps", { XM, EXx, Ib }, 0 }, |
9e30b8e0 L |
9996 | }, |
9997 | { | |
592a252b | 9998 | /* VEX_W_0F3A05_P_2 */ |
bf890a93 | 9999 | { "vpermilpd", { XM, EXx, Ib }, 0 }, |
9e30b8e0 L |
10000 | }, |
10001 | { | |
592a252b | 10002 | /* VEX_W_0F3A06_P_2 */ |
bf890a93 | 10003 | { "vperm2f128", { XM, Vex256, EXx, Ib }, 0 }, |
9e30b8e0 | 10004 | }, |
9e30b8e0 | 10005 | { |
592a252b | 10006 | /* VEX_W_0F3A18_P_2 */ |
bf890a93 | 10007 | { "vinsertf128", { XM, Vex256, EXxmm, Ib }, 0 }, |
9e30b8e0 L |
10008 | }, |
10009 | { | |
592a252b | 10010 | /* VEX_W_0F3A19_P_2 */ |
bf890a93 | 10011 | { "vextractf128", { EXxmm, XM, Ib }, 0 }, |
9e30b8e0 | 10012 | }, |
6431c801 JB |
10013 | { |
10014 | /* VEX_W_0F3A1D_P_2 */ | |
10015 | { "vcvtps2ph", { EXxmmq, XM, EXxEVexS, Ib }, 0 }, | |
10016 | }, | |
43234a1e | 10017 | { |
1ba585e8 | 10018 | /* VEX_W_0F3A30_P_2_LEN_0 */ |
ab4e4ed5 AF |
10019 | { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0) }, |
10020 | { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0) }, | |
43234a1e L |
10021 | }, |
10022 | { | |
1ba585e8 | 10023 | /* VEX_W_0F3A31_P_2_LEN_0 */ |
ab4e4ed5 AF |
10024 | { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0) }, |
10025 | { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0) }, | |
1ba585e8 IT |
10026 | }, |
10027 | { | |
10028 | /* VEX_W_0F3A32_P_2_LEN_0 */ | |
ab4e4ed5 AF |
10029 | { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0) }, |
10030 | { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0) }, | |
43234a1e | 10031 | }, |
1ba585e8 IT |
10032 | { |
10033 | /* VEX_W_0F3A33_P_2_LEN_0 */ | |
ab4e4ed5 AF |
10034 | { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0) }, |
10035 | { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0) }, | |
1ba585e8 | 10036 | }, |
6c30d220 L |
10037 | { |
10038 | /* VEX_W_0F3A38_P_2 */ | |
bf890a93 | 10039 | { "vinserti128", { XM, Vex256, EXxmm, Ib }, 0 }, |
6c30d220 L |
10040 | }, |
10041 | { | |
10042 | /* VEX_W_0F3A39_P_2 */ | |
bf890a93 | 10043 | { "vextracti128", { EXxmm, XM, Ib }, 0 }, |
6c30d220 | 10044 | }, |
6c30d220 L |
10045 | { |
10046 | /* VEX_W_0F3A46_P_2 */ | |
bf890a93 | 10047 | { "vperm2i128", { XM, Vex256, EXx, Ib }, 0 }, |
6c30d220 | 10048 | }, |
a683cc34 | 10049 | { |
592a252b | 10050 | /* VEX_W_0F3A48_P_2 */ |
bf890a93 IT |
10051 | { "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 }, |
10052 | { "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 }, | |
a683cc34 SP |
10053 | }, |
10054 | { | |
592a252b | 10055 | /* VEX_W_0F3A49_P_2 */ |
bf890a93 IT |
10056 | { "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 }, |
10057 | { "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 }, | |
a683cc34 | 10058 | }, |
9e30b8e0 | 10059 | { |
592a252b | 10060 | /* VEX_W_0F3A4A_P_2 */ |
bf890a93 | 10061 | { "vblendvps", { XM, Vex, EXx, XMVexI4 }, 0 }, |
9e30b8e0 L |
10062 | }, |
10063 | { | |
592a252b | 10064 | /* VEX_W_0F3A4B_P_2 */ |
bf890a93 | 10065 | { "vblendvpd", { XM, Vex, EXx, XMVexI4 }, 0 }, |
9e30b8e0 L |
10066 | }, |
10067 | { | |
592a252b | 10068 | /* VEX_W_0F3A4C_P_2 */ |
bf890a93 | 10069 | { "vpblendvb", { XM, Vex, EXx, XMVexI4 }, 0 }, |
9e30b8e0 | 10070 | }, |
48521003 IT |
10071 | { |
10072 | /* VEX_W_0F3ACE_P_2 */ | |
10073 | { Bad_Opcode }, | |
10074 | { "vgf2p8affineqb", { XM, Vex, EXx, Ib }, 0 }, | |
10075 | }, | |
10076 | { | |
10077 | /* VEX_W_0F3ACF_P_2 */ | |
10078 | { Bad_Opcode }, | |
10079 | { "vgf2p8affineinvqb", { XM, Vex, EXx, Ib }, 0 }, | |
10080 | }, | |
ad692897 L |
10081 | |
10082 | #include "i386-dis-evex-w.h" | |
9e30b8e0 L |
10083 | }; |
10084 | ||
10085 | static const struct dis386 mod_table[][2] = { | |
10086 | { | |
10087 | /* MOD_8D */ | |
bf890a93 | 10088 | { "leaS", { Gv, M }, 0 }, |
9e30b8e0 | 10089 | }, |
42164a71 L |
10090 | { |
10091 | /* MOD_C6_REG_7 */ | |
10092 | { Bad_Opcode }, | |
10093 | { RM_TABLE (RM_C6_REG_7) }, | |
10094 | }, | |
10095 | { | |
10096 | /* MOD_C7_REG_7 */ | |
10097 | { Bad_Opcode }, | |
10098 | { RM_TABLE (RM_C7_REG_7) }, | |
10099 | }, | |
4a357820 MZ |
10100 | { |
10101 | /* MOD_FF_REG_3 */ | |
8f570d62 | 10102 | { "{l|}call^", { indirEp }, 0 }, |
4a357820 MZ |
10103 | }, |
10104 | { | |
10105 | /* MOD_FF_REG_5 */ | |
8f570d62 | 10106 | { "{l|}jmp^", { indirEp }, 0 }, |
4a357820 | 10107 | }, |
9e30b8e0 L |
10108 | { |
10109 | /* MOD_0F01_REG_0 */ | |
10110 | { X86_64_TABLE (X86_64_0F01_REG_0) }, | |
10111 | { RM_TABLE (RM_0F01_REG_0) }, | |
10112 | }, | |
10113 | { | |
10114 | /* MOD_0F01_REG_1 */ | |
10115 | { X86_64_TABLE (X86_64_0F01_REG_1) }, | |
10116 | { RM_TABLE (RM_0F01_REG_1) }, | |
10117 | }, | |
10118 | { | |
10119 | /* MOD_0F01_REG_2 */ | |
10120 | { X86_64_TABLE (X86_64_0F01_REG_2) }, | |
10121 | { RM_TABLE (RM_0F01_REG_2) }, | |
10122 | }, | |
10123 | { | |
10124 | /* MOD_0F01_REG_3 */ | |
10125 | { X86_64_TABLE (X86_64_0F01_REG_3) }, | |
10126 | { RM_TABLE (RM_0F01_REG_3) }, | |
10127 | }, | |
8eab4136 L |
10128 | { |
10129 | /* MOD_0F01_REG_5 */ | |
f8687e93 JB |
10130 | { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_0) }, |
10131 | { RM_TABLE (RM_0F01_REG_5_MOD_3) }, | |
8eab4136 | 10132 | }, |
9e30b8e0 L |
10133 | { |
10134 | /* MOD_0F01_REG_7 */ | |
bf890a93 | 10135 | { "invlpg", { Mb }, 0 }, |
f8687e93 | 10136 | { RM_TABLE (RM_0F01_REG_7_MOD_3) }, |
9e30b8e0 L |
10137 | }, |
10138 | { | |
10139 | /* MOD_0F12_PREFIX_0 */ | |
18897deb JB |
10140 | { "movlpX", { XM, EXq }, 0 }, |
10141 | { "movhlps", { XM, EXq }, 0 }, | |
10142 | }, | |
10143 | { | |
10144 | /* MOD_0F12_PREFIX_2 */ | |
10145 | { "movlpX", { XM, EXq }, 0 }, | |
9e30b8e0 L |
10146 | }, |
10147 | { | |
10148 | /* MOD_0F13 */ | |
507bd325 | 10149 | { "movlpX", { EXq, XM }, PREFIX_OPCODE }, |
9e30b8e0 L |
10150 | }, |
10151 | { | |
10152 | /* MOD_0F16_PREFIX_0 */ | |
18897deb | 10153 | { "movhpX", { XM, EXq }, 0 }, |
bf890a93 | 10154 | { "movlhps", { XM, EXq }, 0 }, |
9e30b8e0 | 10155 | }, |
18897deb JB |
10156 | { |
10157 | /* MOD_0F16_PREFIX_2 */ | |
10158 | { "movhpX", { XM, EXq }, 0 }, | |
10159 | }, | |
9e30b8e0 L |
10160 | { |
10161 | /* MOD_0F17 */ | |
507bd325 | 10162 | { "movhpX", { EXq, XM }, PREFIX_OPCODE }, |
9e30b8e0 L |
10163 | }, |
10164 | { | |
10165 | /* MOD_0F18_REG_0 */ | |
bf890a93 | 10166 | { "prefetchnta", { Mb }, 0 }, |
9e30b8e0 L |
10167 | }, |
10168 | { | |
10169 | /* MOD_0F18_REG_1 */ | |
bf890a93 | 10170 | { "prefetcht0", { Mb }, 0 }, |
9e30b8e0 L |
10171 | }, |
10172 | { | |
10173 | /* MOD_0F18_REG_2 */ | |
bf890a93 | 10174 | { "prefetcht1", { Mb }, 0 }, |
9e30b8e0 L |
10175 | }, |
10176 | { | |
10177 | /* MOD_0F18_REG_3 */ | |
bf890a93 | 10178 | { "prefetcht2", { Mb }, 0 }, |
9e30b8e0 | 10179 | }, |
d7189fa5 RM |
10180 | { |
10181 | /* MOD_0F18_REG_4 */ | |
bf890a93 | 10182 | { "nop/reserved", { Mb }, 0 }, |
d7189fa5 RM |
10183 | }, |
10184 | { | |
10185 | /* MOD_0F18_REG_5 */ | |
bf890a93 | 10186 | { "nop/reserved", { Mb }, 0 }, |
d7189fa5 RM |
10187 | }, |
10188 | { | |
10189 | /* MOD_0F18_REG_6 */ | |
bf890a93 | 10190 | { "nop/reserved", { Mb }, 0 }, |
d7189fa5 RM |
10191 | }, |
10192 | { | |
10193 | /* MOD_0F18_REG_7 */ | |
bf890a93 | 10194 | { "nop/reserved", { Mb }, 0 }, |
d7189fa5 | 10195 | }, |
7e8b059b L |
10196 | { |
10197 | /* MOD_0F1A_PREFIX_0 */ | |
d276ec69 | 10198 | { "bndldx", { Gbnd, Mv_bnd }, 0 }, |
bf890a93 | 10199 | { "nopQ", { Ev }, 0 }, |
7e8b059b L |
10200 | }, |
10201 | { | |
10202 | /* MOD_0F1B_PREFIX_0 */ | |
d276ec69 | 10203 | { "bndstx", { Mv_bnd, Gbnd }, 0 }, |
bf890a93 | 10204 | { "nopQ", { Ev }, 0 }, |
7e8b059b L |
10205 | }, |
10206 | { | |
10207 | /* MOD_0F1B_PREFIX_1 */ | |
d276ec69 | 10208 | { "bndmk", { Gbnd, Mv_bnd }, 0 }, |
bf890a93 | 10209 | { "nopQ", { Ev }, 0 }, |
7e8b059b | 10210 | }, |
c48935d7 IT |
10211 | { |
10212 | /* MOD_0F1C_PREFIX_0 */ | |
f8687e93 | 10213 | { REG_TABLE (REG_0F1C_P_0_MOD_0) }, |
c48935d7 IT |
10214 | { "nopQ", { Ev }, 0 }, |
10215 | }, | |
603555e5 L |
10216 | { |
10217 | /* MOD_0F1E_PREFIX_1 */ | |
10218 | { "nopQ", { Ev }, 0 }, | |
f8687e93 | 10219 | { REG_TABLE (REG_0F1E_P_1_MOD_3) }, |
603555e5 | 10220 | }, |
b844680a | 10221 | { |
92fddf8e | 10222 | /* MOD_0F24 */ |
7bb15c6f | 10223 | { Bad_Opcode }, |
bf890a93 | 10224 | { "movL", { Rd, Td }, 0 }, |
b844680a L |
10225 | }, |
10226 | { | |
92fddf8e | 10227 | /* MOD_0F26 */ |
592d1631 | 10228 | { Bad_Opcode }, |
bf890a93 | 10229 | { "movL", { Td, Rd }, 0 }, |
b844680a | 10230 | }, |
75c135a8 L |
10231 | { |
10232 | /* MOD_0F2B_PREFIX_0 */ | |
507bd325 | 10233 | {"movntps", { Mx, XM }, PREFIX_OPCODE }, |
75c135a8 L |
10234 | }, |
10235 | { | |
10236 | /* MOD_0F2B_PREFIX_1 */ | |
507bd325 | 10237 | {"movntss", { Md, XM }, PREFIX_OPCODE }, |
75c135a8 L |
10238 | }, |
10239 | { | |
10240 | /* MOD_0F2B_PREFIX_2 */ | |
507bd325 | 10241 | {"movntpd", { Mx, XM }, PREFIX_OPCODE }, |
75c135a8 L |
10242 | }, |
10243 | { | |
10244 | /* MOD_0F2B_PREFIX_3 */ | |
507bd325 | 10245 | {"movntsd", { Mq, XM }, PREFIX_OPCODE }, |
75c135a8 L |
10246 | }, |
10247 | { | |
a5aaedb9 | 10248 | /* MOD_0F50 */ |
592d1631 | 10249 | { Bad_Opcode }, |
507bd325 | 10250 | { "movmskpX", { Gdq, XS }, PREFIX_OPCODE }, |
75c135a8 | 10251 | }, |
b844680a | 10252 | { |
1ceb70f8 | 10253 | /* MOD_0F71_REG_2 */ |
592d1631 | 10254 | { Bad_Opcode }, |
bf890a93 | 10255 | { "psrlw", { MS, Ib }, 0 }, |
b844680a L |
10256 | }, |
10257 | { | |
1ceb70f8 | 10258 | /* MOD_0F71_REG_4 */ |
592d1631 | 10259 | { Bad_Opcode }, |
bf890a93 | 10260 | { "psraw", { MS, Ib }, 0 }, |
b844680a L |
10261 | }, |
10262 | { | |
1ceb70f8 | 10263 | /* MOD_0F71_REG_6 */ |
592d1631 | 10264 | { Bad_Opcode }, |
bf890a93 | 10265 | { "psllw", { MS, Ib }, 0 }, |
b844680a L |
10266 | }, |
10267 | { | |
1ceb70f8 | 10268 | /* MOD_0F72_REG_2 */ |
592d1631 | 10269 | { Bad_Opcode }, |
bf890a93 | 10270 | { "psrld", { MS, Ib }, 0 }, |
b844680a L |
10271 | }, |
10272 | { | |
1ceb70f8 | 10273 | /* MOD_0F72_REG_4 */ |
592d1631 | 10274 | { Bad_Opcode }, |
bf890a93 | 10275 | { "psrad", { MS, Ib }, 0 }, |
b844680a L |
10276 | }, |
10277 | { | |
1ceb70f8 | 10278 | /* MOD_0F72_REG_6 */ |
592d1631 | 10279 | { Bad_Opcode }, |
bf890a93 | 10280 | { "pslld", { MS, Ib }, 0 }, |
b844680a L |
10281 | }, |
10282 | { | |
1ceb70f8 | 10283 | /* MOD_0F73_REG_2 */ |
592d1631 | 10284 | { Bad_Opcode }, |
bf890a93 | 10285 | { "psrlq", { MS, Ib }, 0 }, |
b844680a L |
10286 | }, |
10287 | { | |
1ceb70f8 | 10288 | /* MOD_0F73_REG_3 */ |
592d1631 | 10289 | { Bad_Opcode }, |
c0f3af97 L |
10290 | { PREFIX_TABLE (PREFIX_0F73_REG_3) }, |
10291 | }, | |
10292 | { | |
10293 | /* MOD_0F73_REG_6 */ | |
592d1631 | 10294 | { Bad_Opcode }, |
bf890a93 | 10295 | { "psllq", { MS, Ib }, 0 }, |
c0f3af97 L |
10296 | }, |
10297 | { | |
10298 | /* MOD_0F73_REG_7 */ | |
592d1631 | 10299 | { Bad_Opcode }, |
c0f3af97 L |
10300 | { PREFIX_TABLE (PREFIX_0F73_REG_7) }, |
10301 | }, | |
10302 | { | |
10303 | /* MOD_0FAE_REG_0 */ | |
bf890a93 | 10304 | { "fxsave", { FXSAVE }, 0 }, |
f8687e93 | 10305 | { PREFIX_TABLE (PREFIX_0FAE_REG_0_MOD_3) }, |
c0f3af97 L |
10306 | }, |
10307 | { | |
10308 | /* MOD_0FAE_REG_1 */ | |
bf890a93 | 10309 | { "fxrstor", { FXSAVE }, 0 }, |
f8687e93 | 10310 | { PREFIX_TABLE (PREFIX_0FAE_REG_1_MOD_3) }, |
c0f3af97 L |
10311 | }, |
10312 | { | |
10313 | /* MOD_0FAE_REG_2 */ | |
bf890a93 | 10314 | { "ldmxcsr", { Md }, 0 }, |
f8687e93 | 10315 | { PREFIX_TABLE (PREFIX_0FAE_REG_2_MOD_3) }, |
c0f3af97 L |
10316 | }, |
10317 | { | |
10318 | /* MOD_0FAE_REG_3 */ | |
bf890a93 | 10319 | { "stmxcsr", { Md }, 0 }, |
f8687e93 | 10320 | { PREFIX_TABLE (PREFIX_0FAE_REG_3_MOD_3) }, |
c0f3af97 L |
10321 | }, |
10322 | { | |
10323 | /* MOD_0FAE_REG_4 */ | |
f8687e93 JB |
10324 | { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_0) }, |
10325 | { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_3) }, | |
c0f3af97 L |
10326 | }, |
10327 | { | |
10328 | /* MOD_0FAE_REG_5 */ | |
f8687e93 JB |
10329 | { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_0) }, |
10330 | { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_3) }, | |
c0f3af97 L |
10331 | }, |
10332 | { | |
10333 | /* MOD_0FAE_REG_6 */ | |
f8687e93 JB |
10334 | { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_0) }, |
10335 | { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_3) }, | |
c0f3af97 L |
10336 | }, |
10337 | { | |
10338 | /* MOD_0FAE_REG_7 */ | |
f8687e93 JB |
10339 | { PREFIX_TABLE (PREFIX_0FAE_REG_7_MOD_0) }, |
10340 | { RM_TABLE (RM_0FAE_REG_7_MOD_3) }, | |
c0f3af97 L |
10341 | }, |
10342 | { | |
10343 | /* MOD_0FB2 */ | |
bf890a93 | 10344 | { "lssS", { Gv, Mp }, 0 }, |
c0f3af97 L |
10345 | }, |
10346 | { | |
10347 | /* MOD_0FB4 */ | |
bf890a93 | 10348 | { "lfsS", { Gv, Mp }, 0 }, |
c0f3af97 L |
10349 | }, |
10350 | { | |
10351 | /* MOD_0FB5 */ | |
bf890a93 | 10352 | { "lgsS", { Gv, Mp }, 0 }, |
c0f3af97 | 10353 | }, |
a8484f96 L |
10354 | { |
10355 | /* MOD_0FC3 */ | |
f8687e93 | 10356 | { PREFIX_TABLE (PREFIX_0FC3_MOD_0) }, |
a8484f96 | 10357 | }, |
963f3586 IT |
10358 | { |
10359 | /* MOD_0FC7_REG_3 */ | |
a8484f96 | 10360 | { "xrstors", { FXSAVE }, 0 }, |
963f3586 IT |
10361 | }, |
10362 | { | |
10363 | /* MOD_0FC7_REG_4 */ | |
bf890a93 | 10364 | { "xsavec", { FXSAVE }, 0 }, |
963f3586 IT |
10365 | }, |
10366 | { | |
10367 | /* MOD_0FC7_REG_5 */ | |
bf890a93 | 10368 | { "xsaves", { FXSAVE }, 0 }, |
963f3586 | 10369 | }, |
c0f3af97 L |
10370 | { |
10371 | /* MOD_0FC7_REG_6 */ | |
f8687e93 JB |
10372 | { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_0) }, |
10373 | { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_3) } | |
c0f3af97 L |
10374 | }, |
10375 | { | |
10376 | /* MOD_0FC7_REG_7 */ | |
bf890a93 | 10377 | { "vmptrst", { Mq }, 0 }, |
f8687e93 | 10378 | { PREFIX_TABLE (PREFIX_0FC7_REG_7_MOD_3) } |
c0f3af97 L |
10379 | }, |
10380 | { | |
10381 | /* MOD_0FD7 */ | |
592d1631 | 10382 | { Bad_Opcode }, |
bf890a93 | 10383 | { "pmovmskb", { Gdq, MS }, 0 }, |
c0f3af97 L |
10384 | }, |
10385 | { | |
10386 | /* MOD_0FE7_PREFIX_2 */ | |
bf890a93 | 10387 | { "movntdq", { Mx, XM }, 0 }, |
c0f3af97 L |
10388 | }, |
10389 | { | |
10390 | /* MOD_0FF0_PREFIX_3 */ | |
bf890a93 | 10391 | { "lddqu", { XM, M }, 0 }, |
c0f3af97 L |
10392 | }, |
10393 | { | |
10394 | /* MOD_0F382A_PREFIX_2 */ | |
bf890a93 | 10395 | { "movntdqa", { XM, Mx }, 0 }, |
c0f3af97 | 10396 | }, |
603555e5 L |
10397 | { |
10398 | /* MOD_0F38F5_PREFIX_2 */ | |
10399 | { "wrussK", { M, Gdq }, PREFIX_OPCODE }, | |
10400 | }, | |
10401 | { | |
10402 | /* MOD_0F38F6_PREFIX_0 */ | |
10403 | { "wrssK", { M, Gdq }, PREFIX_OPCODE }, | |
10404 | }, | |
5d79adc4 L |
10405 | { |
10406 | /* MOD_0F38F8_PREFIX_1 */ | |
10407 | { "enqcmds", { Gva, M }, PREFIX_OPCODE }, | |
10408 | }, | |
c0a30a9f L |
10409 | { |
10410 | /* MOD_0F38F8_PREFIX_2 */ | |
10411 | { "movdir64b", { Gva, M }, PREFIX_OPCODE }, | |
10412 | }, | |
5d79adc4 L |
10413 | { |
10414 | /* MOD_0F38F8_PREFIX_3 */ | |
10415 | { "enqcmd", { Gva, M }, PREFIX_OPCODE }, | |
10416 | }, | |
c0a30a9f L |
10417 | { |
10418 | /* MOD_0F38F9_PREFIX_0 */ | |
77ad8092 | 10419 | { "movdiri", { Ev, Gv }, PREFIX_OPCODE }, |
c0a30a9f | 10420 | }, |
c0f3af97 L |
10421 | { |
10422 | /* MOD_62_32BIT */ | |
bf890a93 | 10423 | { "bound{S|}", { Gv, Ma }, 0 }, |
43234a1e | 10424 | { EVEX_TABLE (EVEX_0F) }, |
c0f3af97 L |
10425 | }, |
10426 | { | |
10427 | /* MOD_C4_32BIT */ | |
bf890a93 | 10428 | { "lesS", { Gv, Mp }, 0 }, |
c0f3af97 L |
10429 | { VEX_C4_TABLE (VEX_0F) }, |
10430 | }, | |
10431 | { | |
10432 | /* MOD_C5_32BIT */ | |
bf890a93 | 10433 | { "ldsS", { Gv, Mp }, 0 }, |
c0f3af97 L |
10434 | { VEX_C5_TABLE (VEX_0F) }, |
10435 | }, | |
10436 | { | |
592a252b L |
10437 | /* MOD_VEX_0F12_PREFIX_0 */ |
10438 | { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) }, | |
10439 | { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) }, | |
c0f3af97 | 10440 | }, |
18897deb JB |
10441 | { |
10442 | /* MOD_VEX_0F12_PREFIX_2 */ | |
10443 | { VEX_LEN_TABLE (VEX_LEN_0F12_P_2_M_0) }, | |
10444 | }, | |
c0f3af97 | 10445 | { |
592a252b L |
10446 | /* MOD_VEX_0F13 */ |
10447 | { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) }, | |
c0f3af97 L |
10448 | }, |
10449 | { | |
592a252b L |
10450 | /* MOD_VEX_0F16_PREFIX_0 */ |
10451 | { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) }, | |
10452 | { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) }, | |
c0f3af97 | 10453 | }, |
18897deb JB |
10454 | { |
10455 | /* MOD_VEX_0F16_PREFIX_2 */ | |
10456 | { VEX_LEN_TABLE (VEX_LEN_0F16_P_2_M_0) }, | |
10457 | }, | |
c0f3af97 | 10458 | { |
592a252b L |
10459 | /* MOD_VEX_0F17 */ |
10460 | { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) }, | |
c0f3af97 L |
10461 | }, |
10462 | { | |
592a252b | 10463 | /* MOD_VEX_0F2B */ |
bf926894 | 10464 | { "vmovntpX", { Mx, XM }, PREFIX_OPCODE }, |
c0f3af97 | 10465 | }, |
ab4e4ed5 AF |
10466 | { |
10467 | /* MOD_VEX_W_0_0F41_P_0_LEN_1 */ | |
10468 | { Bad_Opcode }, | |
10469 | { "kandw", { MaskG, MaskVex, MaskR }, 0 }, | |
10470 | }, | |
10471 | { | |
10472 | /* MOD_VEX_W_1_0F41_P_0_LEN_1 */ | |
10473 | { Bad_Opcode }, | |
10474 | { "kandq", { MaskG, MaskVex, MaskR }, 0 }, | |
10475 | }, | |
10476 | { | |
10477 | /* MOD_VEX_W_0_0F41_P_2_LEN_1 */ | |
10478 | { Bad_Opcode }, | |
10479 | { "kandb", { MaskG, MaskVex, MaskR }, 0 }, | |
10480 | }, | |
10481 | { | |
10482 | /* MOD_VEX_W_1_0F41_P_2_LEN_1 */ | |
10483 | { Bad_Opcode }, | |
10484 | { "kandd", { MaskG, MaskVex, MaskR }, 0 }, | |
10485 | }, | |
10486 | { | |
10487 | /* MOD_VEX_W_0_0F42_P_0_LEN_1 */ | |
10488 | { Bad_Opcode }, | |
10489 | { "kandnw", { MaskG, MaskVex, MaskR }, 0 }, | |
10490 | }, | |
10491 | { | |
10492 | /* MOD_VEX_W_1_0F42_P_0_LEN_1 */ | |
10493 | { Bad_Opcode }, | |
10494 | { "kandnq", { MaskG, MaskVex, MaskR }, 0 }, | |
10495 | }, | |
10496 | { | |
10497 | /* MOD_VEX_W_0_0F42_P_2_LEN_1 */ | |
10498 | { Bad_Opcode }, | |
10499 | { "kandnb", { MaskG, MaskVex, MaskR }, 0 }, | |
10500 | }, | |
10501 | { | |
10502 | /* MOD_VEX_W_1_0F42_P_2_LEN_1 */ | |
10503 | { Bad_Opcode }, | |
10504 | { "kandnd", { MaskG, MaskVex, MaskR }, 0 }, | |
10505 | }, | |
10506 | { | |
10507 | /* MOD_VEX_W_0_0F44_P_0_LEN_0 */ | |
10508 | { Bad_Opcode }, | |
10509 | { "knotw", { MaskG, MaskR }, 0 }, | |
10510 | }, | |
10511 | { | |
10512 | /* MOD_VEX_W_1_0F44_P_0_LEN_0 */ | |
10513 | { Bad_Opcode }, | |
10514 | { "knotq", { MaskG, MaskR }, 0 }, | |
10515 | }, | |
10516 | { | |
10517 | /* MOD_VEX_W_0_0F44_P_2_LEN_0 */ | |
10518 | { Bad_Opcode }, | |
10519 | { "knotb", { MaskG, MaskR }, 0 }, | |
10520 | }, | |
10521 | { | |
10522 | /* MOD_VEX_W_1_0F44_P_2_LEN_0 */ | |
10523 | { Bad_Opcode }, | |
10524 | { "knotd", { MaskG, MaskR }, 0 }, | |
10525 | }, | |
10526 | { | |
10527 | /* MOD_VEX_W_0_0F45_P_0_LEN_1 */ | |
10528 | { Bad_Opcode }, | |
10529 | { "korw", { MaskG, MaskVex, MaskR }, 0 }, | |
10530 | }, | |
10531 | { | |
10532 | /* MOD_VEX_W_1_0F45_P_0_LEN_1 */ | |
10533 | { Bad_Opcode }, | |
10534 | { "korq", { MaskG, MaskVex, MaskR }, 0 }, | |
10535 | }, | |
10536 | { | |
10537 | /* MOD_VEX_W_0_0F45_P_2_LEN_1 */ | |
10538 | { Bad_Opcode }, | |
10539 | { "korb", { MaskG, MaskVex, MaskR }, 0 }, | |
10540 | }, | |
10541 | { | |
10542 | /* MOD_VEX_W_1_0F45_P_2_LEN_1 */ | |
10543 | { Bad_Opcode }, | |
10544 | { "kord", { MaskG, MaskVex, MaskR }, 0 }, | |
10545 | }, | |
10546 | { | |
10547 | /* MOD_VEX_W_0_0F46_P_0_LEN_1 */ | |
10548 | { Bad_Opcode }, | |
10549 | { "kxnorw", { MaskG, MaskVex, MaskR }, 0 }, | |
10550 | }, | |
10551 | { | |
10552 | /* MOD_VEX_W_1_0F46_P_0_LEN_1 */ | |
10553 | { Bad_Opcode }, | |
10554 | { "kxnorq", { MaskG, MaskVex, MaskR }, 0 }, | |
10555 | }, | |
10556 | { | |
10557 | /* MOD_VEX_W_0_0F46_P_2_LEN_1 */ | |
10558 | { Bad_Opcode }, | |
10559 | { "kxnorb", { MaskG, MaskVex, MaskR }, 0 }, | |
10560 | }, | |
10561 | { | |
10562 | /* MOD_VEX_W_1_0F46_P_2_LEN_1 */ | |
10563 | { Bad_Opcode }, | |
10564 | { "kxnord", { MaskG, MaskVex, MaskR }, 0 }, | |
10565 | }, | |
10566 | { | |
10567 | /* MOD_VEX_W_0_0F47_P_0_LEN_1 */ | |
10568 | { Bad_Opcode }, | |
10569 | { "kxorw", { MaskG, MaskVex, MaskR }, 0 }, | |
10570 | }, | |
10571 | { | |
10572 | /* MOD_VEX_W_1_0F47_P_0_LEN_1 */ | |
10573 | { Bad_Opcode }, | |
10574 | { "kxorq", { MaskG, MaskVex, MaskR }, 0 }, | |
10575 | }, | |
10576 | { | |
10577 | /* MOD_VEX_W_0_0F47_P_2_LEN_1 */ | |
10578 | { Bad_Opcode }, | |
10579 | { "kxorb", { MaskG, MaskVex, MaskR }, 0 }, | |
10580 | }, | |
10581 | { | |
10582 | /* MOD_VEX_W_1_0F47_P_2_LEN_1 */ | |
10583 | { Bad_Opcode }, | |
10584 | { "kxord", { MaskG, MaskVex, MaskR }, 0 }, | |
10585 | }, | |
10586 | { | |
10587 | /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */ | |
10588 | { Bad_Opcode }, | |
10589 | { "kaddw", { MaskG, MaskVex, MaskR }, 0 }, | |
10590 | }, | |
10591 | { | |
10592 | /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */ | |
10593 | { Bad_Opcode }, | |
10594 | { "kaddq", { MaskG, MaskVex, MaskR }, 0 }, | |
10595 | }, | |
10596 | { | |
10597 | /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */ | |
10598 | { Bad_Opcode }, | |
10599 | { "kaddb", { MaskG, MaskVex, MaskR }, 0 }, | |
10600 | }, | |
10601 | { | |
10602 | /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */ | |
10603 | { Bad_Opcode }, | |
10604 | { "kaddd", { MaskG, MaskVex, MaskR }, 0 }, | |
10605 | }, | |
10606 | { | |
10607 | /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */ | |
10608 | { Bad_Opcode }, | |
10609 | { "kunpckwd", { MaskG, MaskVex, MaskR }, 0 }, | |
10610 | }, | |
10611 | { | |
10612 | /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */ | |
10613 | { Bad_Opcode }, | |
10614 | { "kunpckdq", { MaskG, MaskVex, MaskR }, 0 }, | |
10615 | }, | |
10616 | { | |
10617 | /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */ | |
10618 | { Bad_Opcode }, | |
10619 | { "kunpckbw", { MaskG, MaskVex, MaskR }, 0 }, | |
10620 | }, | |
c0f3af97 | 10621 | { |
592a252b | 10622 | /* MOD_VEX_0F50 */ |
592d1631 | 10623 | { Bad_Opcode }, |
bf926894 | 10624 | { "vmovmskpX", { Gdq, XS }, PREFIX_OPCODE }, |
c0f3af97 L |
10625 | }, |
10626 | { | |
592a252b | 10627 | /* MOD_VEX_0F71_REG_2 */ |
592d1631 | 10628 | { Bad_Opcode }, |
592a252b | 10629 | { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) }, |
b844680a L |
10630 | }, |
10631 | { | |
592a252b | 10632 | /* MOD_VEX_0F71_REG_4 */ |
592d1631 | 10633 | { Bad_Opcode }, |
592a252b | 10634 | { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) }, |
b844680a L |
10635 | }, |
10636 | { | |
592a252b | 10637 | /* MOD_VEX_0F71_REG_6 */ |
592d1631 | 10638 | { Bad_Opcode }, |
592a252b | 10639 | { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) }, |
b844680a L |
10640 | }, |
10641 | { | |
592a252b | 10642 | /* MOD_VEX_0F72_REG_2 */ |
592d1631 | 10643 | { Bad_Opcode }, |
592a252b | 10644 | { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) }, |
b844680a | 10645 | }, |
d8faab4e | 10646 | { |
592a252b | 10647 | /* MOD_VEX_0F72_REG_4 */ |
592d1631 | 10648 | { Bad_Opcode }, |
592a252b | 10649 | { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) }, |
d8faab4e L |
10650 | }, |
10651 | { | |
592a252b | 10652 | /* MOD_VEX_0F72_REG_6 */ |
592d1631 | 10653 | { Bad_Opcode }, |
592a252b | 10654 | { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) }, |
d8faab4e | 10655 | }, |
876d4bfa | 10656 | { |
592a252b | 10657 | /* MOD_VEX_0F73_REG_2 */ |
592d1631 | 10658 | { Bad_Opcode }, |
592a252b | 10659 | { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) }, |
876d4bfa L |
10660 | }, |
10661 | { | |
592a252b | 10662 | /* MOD_VEX_0F73_REG_3 */ |
592d1631 | 10663 | { Bad_Opcode }, |
592a252b | 10664 | { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) }, |
475a2301 L |
10665 | }, |
10666 | { | |
592a252b | 10667 | /* MOD_VEX_0F73_REG_6 */ |
592d1631 | 10668 | { Bad_Opcode }, |
592a252b | 10669 | { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) }, |
876d4bfa L |
10670 | }, |
10671 | { | |
592a252b | 10672 | /* MOD_VEX_0F73_REG_7 */ |
592d1631 | 10673 | { Bad_Opcode }, |
592a252b | 10674 | { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) }, |
876d4bfa | 10675 | }, |
ab4e4ed5 AF |
10676 | { |
10677 | /* MOD_VEX_W_0_0F91_P_0_LEN_0 */ | |
10678 | { "kmovw", { Ew, MaskG }, 0 }, | |
10679 | { Bad_Opcode }, | |
10680 | }, | |
10681 | { | |
10682 | /* MOD_VEX_W_0_0F91_P_0_LEN_0 */ | |
10683 | { "kmovq", { Eq, MaskG }, 0 }, | |
10684 | { Bad_Opcode }, | |
10685 | }, | |
10686 | { | |
10687 | /* MOD_VEX_W_0_0F91_P_2_LEN_0 */ | |
10688 | { "kmovb", { Eb, MaskG }, 0 }, | |
10689 | { Bad_Opcode }, | |
10690 | }, | |
10691 | { | |
10692 | /* MOD_VEX_W_0_0F91_P_2_LEN_0 */ | |
10693 | { "kmovd", { Ed, MaskG }, 0 }, | |
10694 | { Bad_Opcode }, | |
10695 | }, | |
10696 | { | |
10697 | /* MOD_VEX_W_0_0F92_P_0_LEN_0 */ | |
10698 | { Bad_Opcode }, | |
10699 | { "kmovw", { MaskG, Rdq }, 0 }, | |
10700 | }, | |
10701 | { | |
10702 | /* MOD_VEX_W_0_0F92_P_2_LEN_0 */ | |
10703 | { Bad_Opcode }, | |
10704 | { "kmovb", { MaskG, Rdq }, 0 }, | |
10705 | }, | |
10706 | { | |
58a211d2 | 10707 | /* MOD_VEX_0F92_P_3_LEN_0 */ |
ab4e4ed5 | 10708 | { Bad_Opcode }, |
58a211d2 | 10709 | { "kmovK", { MaskG, Rdq }, 0 }, |
ab4e4ed5 AF |
10710 | }, |
10711 | { | |
10712 | /* MOD_VEX_W_0_0F93_P_0_LEN_0 */ | |
10713 | { Bad_Opcode }, | |
10714 | { "kmovw", { Gdq, MaskR }, 0 }, | |
10715 | }, | |
10716 | { | |
10717 | /* MOD_VEX_W_0_0F93_P_2_LEN_0 */ | |
10718 | { Bad_Opcode }, | |
10719 | { "kmovb", { Gdq, MaskR }, 0 }, | |
10720 | }, | |
10721 | { | |
58a211d2 | 10722 | /* MOD_VEX_0F93_P_3_LEN_0 */ |
ab4e4ed5 | 10723 | { Bad_Opcode }, |
58a211d2 | 10724 | { "kmovK", { Gdq, MaskR }, 0 }, |
ab4e4ed5 AF |
10725 | }, |
10726 | { | |
10727 | /* MOD_VEX_W_0_0F98_P_0_LEN_0 */ | |
10728 | { Bad_Opcode }, | |
10729 | { "kortestw", { MaskG, MaskR }, 0 }, | |
10730 | }, | |
10731 | { | |
10732 | /* MOD_VEX_W_1_0F98_P_0_LEN_0 */ | |
10733 | { Bad_Opcode }, | |
10734 | { "kortestq", { MaskG, MaskR }, 0 }, | |
10735 | }, | |
10736 | { | |
10737 | /* MOD_VEX_W_0_0F98_P_2_LEN_0 */ | |
10738 | { Bad_Opcode }, | |
10739 | { "kortestb", { MaskG, MaskR }, 0 }, | |
10740 | }, | |
10741 | { | |
10742 | /* MOD_VEX_W_1_0F98_P_2_LEN_0 */ | |
10743 | { Bad_Opcode }, | |
10744 | { "kortestd", { MaskG, MaskR }, 0 }, | |
10745 | }, | |
10746 | { | |
10747 | /* MOD_VEX_W_0_0F99_P_0_LEN_0 */ | |
10748 | { Bad_Opcode }, | |
10749 | { "ktestw", { MaskG, MaskR }, 0 }, | |
10750 | }, | |
10751 | { | |
10752 | /* MOD_VEX_W_1_0F99_P_0_LEN_0 */ | |
10753 | { Bad_Opcode }, | |
10754 | { "ktestq", { MaskG, MaskR }, 0 }, | |
10755 | }, | |
10756 | { | |
10757 | /* MOD_VEX_W_0_0F99_P_2_LEN_0 */ | |
10758 | { Bad_Opcode }, | |
10759 | { "ktestb", { MaskG, MaskR }, 0 }, | |
10760 | }, | |
10761 | { | |
10762 | /* MOD_VEX_W_1_0F99_P_2_LEN_0 */ | |
10763 | { Bad_Opcode }, | |
10764 | { "ktestd", { MaskG, MaskR }, 0 }, | |
10765 | }, | |
876d4bfa | 10766 | { |
592a252b L |
10767 | /* MOD_VEX_0FAE_REG_2 */ |
10768 | { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) }, | |
876d4bfa | 10769 | }, |
bbedc832 | 10770 | { |
592a252b L |
10771 | /* MOD_VEX_0FAE_REG_3 */ |
10772 | { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) }, | |
bbedc832 | 10773 | }, |
144c41d9 | 10774 | { |
592a252b | 10775 | /* MOD_VEX_0FD7_PREFIX_2 */ |
592d1631 | 10776 | { Bad_Opcode }, |
ec6f095a | 10777 | { "vpmovmskb", { Gdq, XS }, 0 }, |
144c41d9 | 10778 | }, |
1afd85e3 | 10779 | { |
592a252b | 10780 | /* MOD_VEX_0FE7_PREFIX_2 */ |
ec6f095a | 10781 | { "vmovntdq", { Mx, XM }, 0 }, |
1afd85e3 L |
10782 | }, |
10783 | { | |
592a252b | 10784 | /* MOD_VEX_0FF0_PREFIX_3 */ |
ec6f095a | 10785 | { "vlddqu", { XM, M }, 0 }, |
92fddf8e | 10786 | }, |
75c135a8 | 10787 | { |
592a252b L |
10788 | /* MOD_VEX_0F381A_PREFIX_2 */ |
10789 | { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) }, | |
75c135a8 | 10790 | }, |
1afd85e3 | 10791 | { |
592a252b | 10792 | /* MOD_VEX_0F382A_PREFIX_2 */ |
ec6f095a | 10793 | { "vmovntdqa", { XM, Mx }, 0 }, |
1afd85e3 | 10794 | }, |
75c135a8 | 10795 | { |
592a252b L |
10796 | /* MOD_VEX_0F382C_PREFIX_2 */ |
10797 | { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) }, | |
75c135a8 | 10798 | }, |
1afd85e3 | 10799 | { |
592a252b L |
10800 | /* MOD_VEX_0F382D_PREFIX_2 */ |
10801 | { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) }, | |
1afd85e3 L |
10802 | }, |
10803 | { | |
592a252b L |
10804 | /* MOD_VEX_0F382E_PREFIX_2 */ |
10805 | { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) }, | |
1afd85e3 L |
10806 | }, |
10807 | { | |
592a252b L |
10808 | /* MOD_VEX_0F382F_PREFIX_2 */ |
10809 | { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) }, | |
1afd85e3 | 10810 | }, |
6c30d220 L |
10811 | { |
10812 | /* MOD_VEX_0F385A_PREFIX_2 */ | |
10813 | { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) }, | |
10814 | }, | |
10815 | { | |
10816 | /* MOD_VEX_0F388C_PREFIX_2 */ | |
bf890a93 | 10817 | { "vpmaskmov%LW", { XM, Vex, Mx }, 0 }, |
6c30d220 L |
10818 | }, |
10819 | { | |
10820 | /* MOD_VEX_0F388E_PREFIX_2 */ | |
bf890a93 | 10821 | { "vpmaskmov%LW", { Mx, Vex, XM }, 0 }, |
6c30d220 | 10822 | }, |
ab4e4ed5 AF |
10823 | { |
10824 | /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */ | |
10825 | { Bad_Opcode }, | |
10826 | { "kshiftrb", { MaskG, MaskR, Ib }, 0 }, | |
10827 | }, | |
10828 | { | |
10829 | /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */ | |
10830 | { Bad_Opcode }, | |
10831 | { "kshiftrw", { MaskG, MaskR, Ib }, 0 }, | |
10832 | }, | |
10833 | { | |
10834 | /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */ | |
10835 | { Bad_Opcode }, | |
10836 | { "kshiftrd", { MaskG, MaskR, Ib }, 0 }, | |
10837 | }, | |
10838 | { | |
10839 | /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */ | |
10840 | { Bad_Opcode }, | |
10841 | { "kshiftrq", { MaskG, MaskR, Ib }, 0 }, | |
10842 | }, | |
10843 | { | |
10844 | /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */ | |
10845 | { Bad_Opcode }, | |
10846 | { "kshiftlb", { MaskG, MaskR, Ib }, 0 }, | |
10847 | }, | |
10848 | { | |
10849 | /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */ | |
10850 | { Bad_Opcode }, | |
10851 | { "kshiftlw", { MaskG, MaskR, Ib }, 0 }, | |
10852 | }, | |
10853 | { | |
10854 | /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */ | |
10855 | { Bad_Opcode }, | |
10856 | { "kshiftld", { MaskG, MaskR, Ib }, 0 }, | |
10857 | }, | |
10858 | { | |
10859 | /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */ | |
10860 | { Bad_Opcode }, | |
10861 | { "kshiftlq", { MaskG, MaskR, Ib }, 0 }, | |
10862 | }, | |
ad692897 L |
10863 | |
10864 | #include "i386-dis-evex-mod.h" | |
b844680a L |
10865 | }; |
10866 | ||
1ceb70f8 | 10867 | static const struct dis386 rm_table[][8] = { |
42164a71 L |
10868 | { |
10869 | /* RM_C6_REG_7 */ | |
bf890a93 | 10870 | { "xabort", { Skip_MODRM, Ib }, 0 }, |
42164a71 L |
10871 | }, |
10872 | { | |
10873 | /* RM_C7_REG_7 */ | |
376cd056 | 10874 | { "xbeginT", { Skip_MODRM, Jdqw }, 0 }, |
42164a71 | 10875 | }, |
b844680a | 10876 | { |
1ceb70f8 | 10877 | /* RM_0F01_REG_0 */ |
a4e78aa5 | 10878 | { "enclv", { Skip_MODRM }, 0 }, |
bf890a93 IT |
10879 | { "vmcall", { Skip_MODRM }, 0 }, |
10880 | { "vmlaunch", { Skip_MODRM }, 0 }, | |
10881 | { "vmresume", { Skip_MODRM }, 0 }, | |
10882 | { "vmxoff", { Skip_MODRM }, 0 }, | |
be3a8dca | 10883 | { "pconfig", { Skip_MODRM }, 0 }, |
b844680a L |
10884 | }, |
10885 | { | |
1ceb70f8 | 10886 | /* RM_0F01_REG_1 */ |
bf890a93 IT |
10887 | { "monitor", { { OP_Monitor, 0 } }, 0 }, |
10888 | { "mwait", { { OP_Mwait, 0 } }, 0 }, | |
10889 | { "clac", { Skip_MODRM }, 0 }, | |
10890 | { "stac", { Skip_MODRM }, 0 }, | |
2cf200a4 IT |
10891 | { Bad_Opcode }, |
10892 | { Bad_Opcode }, | |
10893 | { Bad_Opcode }, | |
bf890a93 | 10894 | { "encls", { Skip_MODRM }, 0 }, |
b844680a | 10895 | }, |
475a2301 L |
10896 | { |
10897 | /* RM_0F01_REG_2 */ | |
bf890a93 IT |
10898 | { "xgetbv", { Skip_MODRM }, 0 }, |
10899 | { "xsetbv", { Skip_MODRM }, 0 }, | |
8729a6f6 L |
10900 | { Bad_Opcode }, |
10901 | { Bad_Opcode }, | |
bf890a93 IT |
10902 | { "vmfunc", { Skip_MODRM }, 0 }, |
10903 | { "xend", { Skip_MODRM }, 0 }, | |
10904 | { "xtest", { Skip_MODRM }, 0 }, | |
10905 | { "enclu", { Skip_MODRM }, 0 }, | |
475a2301 | 10906 | }, |
b844680a | 10907 | { |
1ceb70f8 | 10908 | /* RM_0F01_REG_3 */ |
bf890a93 | 10909 | { "vmrun", { Skip_MODRM }, 0 }, |
a847e322 | 10910 | { PREFIX_TABLE (PREFIX_0F01_REG_3_RM_1) }, |
bf890a93 IT |
10911 | { "vmload", { Skip_MODRM }, 0 }, |
10912 | { "vmsave", { Skip_MODRM }, 0 }, | |
10913 | { "stgi", { Skip_MODRM }, 0 }, | |
10914 | { "clgi", { Skip_MODRM }, 0 }, | |
10915 | { "skinit", { Skip_MODRM }, 0 }, | |
10916 | { "invlpga", { Skip_MODRM }, 0 }, | |
4e7d34a6 | 10917 | }, |
8eab4136 | 10918 | { |
f8687e93 JB |
10919 | /* RM_0F01_REG_5_MOD_3 */ |
10920 | { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_0) }, | |
bb651e8b | 10921 | { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_1) }, |
f8687e93 | 10922 | { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_2) }, |
8eab4136 L |
10923 | { Bad_Opcode }, |
10924 | { Bad_Opcode }, | |
10925 | { Bad_Opcode }, | |
10926 | { "rdpkru", { Skip_MODRM }, 0 }, | |
10927 | { "wrpkru", { Skip_MODRM }, 0 }, | |
10928 | }, | |
4e7d34a6 | 10929 | { |
f8687e93 | 10930 | /* RM_0F01_REG_7_MOD_3 */ |
bf890a93 IT |
10931 | { "swapgs", { Skip_MODRM }, 0 }, |
10932 | { "rdtscp", { Skip_MODRM }, 0 }, | |
267b8516 JB |
10933 | { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_2) }, |
10934 | { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_3) }, | |
bf890a93 | 10935 | { "clzero", { Skip_MODRM }, 0 }, |
142861df | 10936 | { "rdpru", { Skip_MODRM }, 0 }, |
b844680a | 10937 | }, |
603555e5 | 10938 | { |
f8687e93 | 10939 | /* RM_0F1E_P_1_MOD_3_REG_7 */ |
603555e5 L |
10940 | { "nopQ", { Ev }, 0 }, |
10941 | { "nopQ", { Ev }, 0 }, | |
10942 | { "endbr64", { Skip_MODRM }, PREFIX_OPCODE }, | |
10943 | { "endbr32", { Skip_MODRM }, PREFIX_OPCODE }, | |
10944 | { "nopQ", { Ev }, 0 }, | |
10945 | { "nopQ", { Ev }, 0 }, | |
10946 | { "nopQ", { Ev }, 0 }, | |
10947 | { "nopQ", { Ev }, 0 }, | |
10948 | }, | |
b844680a | 10949 | { |
f8687e93 | 10950 | /* RM_0FAE_REG_6_MOD_3 */ |
bf890a93 | 10951 | { "mfence", { Skip_MODRM }, 0 }, |
b844680a | 10952 | }, |
bbedc832 | 10953 | { |
f8687e93 | 10954 | /* RM_0FAE_REG_7_MOD_3 */ |
b5cefcca L |
10955 | { "sfence", { Skip_MODRM }, 0 }, |
10956 | ||
144c41d9 | 10957 | }, |
b844680a L |
10958 | }; |
10959 | ||
c608c12e AM |
10960 | #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>") |
10961 | ||
f16cd0d5 L |
10962 | /* We use the high bit to indicate different name for the same |
10963 | prefix. */ | |
f16cd0d5 | 10964 | #define REP_PREFIX (0xf3 | 0x100) |
42164a71 L |
10965 | #define XACQUIRE_PREFIX (0xf2 | 0x200) |
10966 | #define XRELEASE_PREFIX (0xf3 | 0x400) | |
7e8b059b | 10967 | #define BND_PREFIX (0xf2 | 0x400) |
04ef582a | 10968 | #define NOTRACK_PREFIX (0x3e | 0x100) |
f16cd0d5 | 10969 | |
1d67fe3b TT |
10970 | /* Remember if the current op is a jump instruction. */ |
10971 | static bfd_boolean op_is_jump = FALSE; | |
10972 | ||
f16cd0d5 | 10973 | static int |
26ca5450 | 10974 | ckprefix (void) |
252b5132 | 10975 | { |
f16cd0d5 | 10976 | int newrex, i, length; |
52b15da3 | 10977 | rex = 0; |
252b5132 | 10978 | prefixes = 0; |
7d421014 | 10979 | used_prefixes = 0; |
52b15da3 | 10980 | rex_used = 0; |
f16cd0d5 L |
10981 | last_lock_prefix = -1; |
10982 | last_repz_prefix = -1; | |
10983 | last_repnz_prefix = -1; | |
10984 | last_data_prefix = -1; | |
10985 | last_addr_prefix = -1; | |
10986 | last_rex_prefix = -1; | |
10987 | last_seg_prefix = -1; | |
d9949a36 | 10988 | fwait_prefix = -1; |
285ca992 | 10989 | active_seg_prefix = 0; |
f310f33d L |
10990 | for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++) |
10991 | all_prefixes[i] = 0; | |
10992 | i = 0; | |
f16cd0d5 L |
10993 | length = 0; |
10994 | /* The maximum instruction length is 15bytes. */ | |
10995 | while (length < MAX_CODE_LENGTH - 1) | |
252b5132 RH |
10996 | { |
10997 | FETCH_DATA (the_info, codep + 1); | |
52b15da3 | 10998 | newrex = 0; |
252b5132 RH |
10999 | switch (*codep) |
11000 | { | |
52b15da3 JH |
11001 | /* REX prefixes family. */ |
11002 | case 0x40: | |
11003 | case 0x41: | |
11004 | case 0x42: | |
11005 | case 0x43: | |
11006 | case 0x44: | |
11007 | case 0x45: | |
11008 | case 0x46: | |
11009 | case 0x47: | |
11010 | case 0x48: | |
11011 | case 0x49: | |
11012 | case 0x4a: | |
11013 | case 0x4b: | |
11014 | case 0x4c: | |
11015 | case 0x4d: | |
11016 | case 0x4e: | |
11017 | case 0x4f: | |
f16cd0d5 L |
11018 | if (address_mode == mode_64bit) |
11019 | newrex = *codep; | |
11020 | else | |
11021 | return 1; | |
11022 | last_rex_prefix = i; | |
52b15da3 | 11023 | break; |
252b5132 RH |
11024 | case 0xf3: |
11025 | prefixes |= PREFIX_REPZ; | |
f16cd0d5 | 11026 | last_repz_prefix = i; |
252b5132 RH |
11027 | break; |
11028 | case 0xf2: | |
11029 | prefixes |= PREFIX_REPNZ; | |
f16cd0d5 | 11030 | last_repnz_prefix = i; |
252b5132 RH |
11031 | break; |
11032 | case 0xf0: | |
11033 | prefixes |= PREFIX_LOCK; | |
f16cd0d5 | 11034 | last_lock_prefix = i; |
252b5132 RH |
11035 | break; |
11036 | case 0x2e: | |
11037 | prefixes |= PREFIX_CS; | |
f16cd0d5 | 11038 | last_seg_prefix = i; |
285ca992 | 11039 | active_seg_prefix = PREFIX_CS; |
252b5132 RH |
11040 | break; |
11041 | case 0x36: | |
11042 | prefixes |= PREFIX_SS; | |
f16cd0d5 | 11043 | last_seg_prefix = i; |
285ca992 | 11044 | active_seg_prefix = PREFIX_SS; |
252b5132 RH |
11045 | break; |
11046 | case 0x3e: | |
11047 | prefixes |= PREFIX_DS; | |
f16cd0d5 | 11048 | last_seg_prefix = i; |
285ca992 | 11049 | active_seg_prefix = PREFIX_DS; |
252b5132 RH |
11050 | break; |
11051 | case 0x26: | |
11052 | prefixes |= PREFIX_ES; | |
f16cd0d5 | 11053 | last_seg_prefix = i; |
285ca992 | 11054 | active_seg_prefix = PREFIX_ES; |
252b5132 RH |
11055 | break; |
11056 | case 0x64: | |
11057 | prefixes |= PREFIX_FS; | |
f16cd0d5 | 11058 | last_seg_prefix = i; |
285ca992 | 11059 | active_seg_prefix = PREFIX_FS; |
252b5132 RH |
11060 | break; |
11061 | case 0x65: | |
11062 | prefixes |= PREFIX_GS; | |
f16cd0d5 | 11063 | last_seg_prefix = i; |
285ca992 | 11064 | active_seg_prefix = PREFIX_GS; |
252b5132 RH |
11065 | break; |
11066 | case 0x66: | |
11067 | prefixes |= PREFIX_DATA; | |
f16cd0d5 | 11068 | last_data_prefix = i; |
252b5132 RH |
11069 | break; |
11070 | case 0x67: | |
11071 | prefixes |= PREFIX_ADDR; | |
f16cd0d5 | 11072 | last_addr_prefix = i; |
252b5132 | 11073 | break; |
5076851f | 11074 | case FWAIT_OPCODE: |
252b5132 RH |
11075 | /* fwait is really an instruction. If there are prefixes |
11076 | before the fwait, they belong to the fwait, *not* to the | |
11077 | following instruction. */ | |
d9949a36 | 11078 | fwait_prefix = i; |
3e7d61b2 | 11079 | if (prefixes || rex) |
252b5132 RH |
11080 | { |
11081 | prefixes |= PREFIX_FWAIT; | |
11082 | codep++; | |
6c067bbb RM |
11083 | /* This ensures that the previous REX prefixes are noticed |
11084 | as unused prefixes, as in the return case below. */ | |
11085 | rex_used = rex; | |
f16cd0d5 | 11086 | return 1; |
252b5132 RH |
11087 | } |
11088 | prefixes = PREFIX_FWAIT; | |
11089 | break; | |
11090 | default: | |
f16cd0d5 | 11091 | return 1; |
252b5132 | 11092 | } |
52b15da3 JH |
11093 | /* Rex is ignored when followed by another prefix. */ |
11094 | if (rex) | |
11095 | { | |
3e7d61b2 | 11096 | rex_used = rex; |
f16cd0d5 | 11097 | return 1; |
52b15da3 | 11098 | } |
f16cd0d5 | 11099 | if (*codep != FWAIT_OPCODE) |
4e9ac44a | 11100 | all_prefixes[i++] = *codep; |
52b15da3 | 11101 | rex = newrex; |
252b5132 | 11102 | codep++; |
f16cd0d5 L |
11103 | length++; |
11104 | } | |
11105 | return 0; | |
11106 | } | |
11107 | ||
7d421014 ILT |
11108 | /* Return the name of the prefix byte PREF, or NULL if PREF is not a |
11109 | prefix byte. */ | |
11110 | ||
11111 | static const char * | |
26ca5450 | 11112 | prefix_name (int pref, int sizeflag) |
7d421014 | 11113 | { |
0003779b L |
11114 | static const char *rexes [16] = |
11115 | { | |
11116 | "rex", /* 0x40 */ | |
11117 | "rex.B", /* 0x41 */ | |
11118 | "rex.X", /* 0x42 */ | |
11119 | "rex.XB", /* 0x43 */ | |
11120 | "rex.R", /* 0x44 */ | |
11121 | "rex.RB", /* 0x45 */ | |
11122 | "rex.RX", /* 0x46 */ | |
11123 | "rex.RXB", /* 0x47 */ | |
11124 | "rex.W", /* 0x48 */ | |
11125 | "rex.WB", /* 0x49 */ | |
11126 | "rex.WX", /* 0x4a */ | |
11127 | "rex.WXB", /* 0x4b */ | |
11128 | "rex.WR", /* 0x4c */ | |
11129 | "rex.WRB", /* 0x4d */ | |
11130 | "rex.WRX", /* 0x4e */ | |
11131 | "rex.WRXB", /* 0x4f */ | |
11132 | }; | |
11133 | ||
7d421014 ILT |
11134 | switch (pref) |
11135 | { | |
52b15da3 JH |
11136 | /* REX prefixes family. */ |
11137 | case 0x40: | |
52b15da3 | 11138 | case 0x41: |
52b15da3 | 11139 | case 0x42: |
52b15da3 | 11140 | case 0x43: |
52b15da3 | 11141 | case 0x44: |
52b15da3 | 11142 | case 0x45: |
52b15da3 | 11143 | case 0x46: |
52b15da3 | 11144 | case 0x47: |
52b15da3 | 11145 | case 0x48: |
52b15da3 | 11146 | case 0x49: |
52b15da3 | 11147 | case 0x4a: |
52b15da3 | 11148 | case 0x4b: |
52b15da3 | 11149 | case 0x4c: |
52b15da3 | 11150 | case 0x4d: |
52b15da3 | 11151 | case 0x4e: |
52b15da3 | 11152 | case 0x4f: |
0003779b | 11153 | return rexes [pref - 0x40]; |
7d421014 ILT |
11154 | case 0xf3: |
11155 | return "repz"; | |
11156 | case 0xf2: | |
11157 | return "repnz"; | |
11158 | case 0xf0: | |
11159 | return "lock"; | |
11160 | case 0x2e: | |
11161 | return "cs"; | |
11162 | case 0x36: | |
11163 | return "ss"; | |
11164 | case 0x3e: | |
11165 | return "ds"; | |
11166 | case 0x26: | |
11167 | return "es"; | |
11168 | case 0x64: | |
11169 | return "fs"; | |
11170 | case 0x65: | |
11171 | return "gs"; | |
11172 | case 0x66: | |
11173 | return (sizeflag & DFLAG) ? "data16" : "data32"; | |
11174 | case 0x67: | |
cb712a9e | 11175 | if (address_mode == mode_64bit) |
db6eb5be | 11176 | return (sizeflag & AFLAG) ? "addr32" : "addr64"; |
c1a64871 | 11177 | else |
2888cb7a | 11178 | return (sizeflag & AFLAG) ? "addr16" : "addr32"; |
7d421014 ILT |
11179 | case FWAIT_OPCODE: |
11180 | return "fwait"; | |
f16cd0d5 L |
11181 | case REP_PREFIX: |
11182 | return "rep"; | |
42164a71 L |
11183 | case XACQUIRE_PREFIX: |
11184 | return "xacquire"; | |
11185 | case XRELEASE_PREFIX: | |
11186 | return "xrelease"; | |
7e8b059b L |
11187 | case BND_PREFIX: |
11188 | return "bnd"; | |
04ef582a L |
11189 | case NOTRACK_PREFIX: |
11190 | return "notrack"; | |
7d421014 ILT |
11191 | default: |
11192 | return NULL; | |
11193 | } | |
11194 | } | |
11195 | ||
ce518a5f L |
11196 | static char op_out[MAX_OPERANDS][100]; |
11197 | static int op_ad, op_index[MAX_OPERANDS]; | |
1d9f512f | 11198 | static int two_source_ops; |
ce518a5f L |
11199 | static bfd_vma op_address[MAX_OPERANDS]; |
11200 | static bfd_vma op_riprel[MAX_OPERANDS]; | |
52b15da3 | 11201 | static bfd_vma start_pc; |
ce518a5f | 11202 | |
252b5132 RH |
11203 | /* |
11204 | * On the 386's of 1988, the maximum length of an instruction is 15 bytes. | |
11205 | * (see topic "Redundant prefixes" in the "Differences from 8086" | |
11206 | * section of the "Virtual 8086 Mode" chapter.) | |
11207 | * 'pc' should be the address of this instruction, it will | |
11208 | * be used to print the target address if this is a relative jump or call | |
11209 | * The function returns the length of this instruction in bytes. | |
11210 | */ | |
11211 | ||
252b5132 | 11212 | static char intel_syntax; |
9d141669 | 11213 | static char intel_mnemonic = !SYSV386_COMPAT; |
252b5132 RH |
11214 | static char open_char; |
11215 | static char close_char; | |
11216 | static char separator_char; | |
11217 | static char scale_char; | |
11218 | ||
5db04b09 L |
11219 | enum x86_64_isa |
11220 | { | |
d835a58b | 11221 | amd64 = 1, |
5db04b09 L |
11222 | intel64 |
11223 | }; | |
11224 | ||
11225 | static enum x86_64_isa isa64; | |
11226 | ||
e396998b AM |
11227 | /* Here for backwards compatibility. When gdb stops using |
11228 | print_insn_i386_att and print_insn_i386_intel these functions can | |
11229 | disappear, and print_insn_i386 be merged into print_insn. */ | |
252b5132 | 11230 | int |
26ca5450 | 11231 | print_insn_i386_att (bfd_vma pc, disassemble_info *info) |
252b5132 RH |
11232 | { |
11233 | intel_syntax = 0; | |
e396998b AM |
11234 | |
11235 | return print_insn (pc, info); | |
252b5132 RH |
11236 | } |
11237 | ||
11238 | int | |
26ca5450 | 11239 | print_insn_i386_intel (bfd_vma pc, disassemble_info *info) |
252b5132 RH |
11240 | { |
11241 | intel_syntax = 1; | |
e396998b AM |
11242 | |
11243 | return print_insn (pc, info); | |
252b5132 RH |
11244 | } |
11245 | ||
e396998b | 11246 | int |
26ca5450 | 11247 | print_insn_i386 (bfd_vma pc, disassemble_info *info) |
e396998b AM |
11248 | { |
11249 | intel_syntax = -1; | |
11250 | ||
11251 | return print_insn (pc, info); | |
11252 | } | |
11253 | ||
f59a29b9 L |
11254 | void |
11255 | print_i386_disassembler_options (FILE *stream) | |
11256 | { | |
11257 | fprintf (stream, _("\n\ | |
11258 | The following i386/x86-64 specific disassembler options are supported for use\n\ | |
11259 | with the -M switch (multiple options should be separated by commas):\n")); | |
11260 | ||
11261 | fprintf (stream, _(" x86-64 Disassemble in 64bit mode\n")); | |
11262 | fprintf (stream, _(" i386 Disassemble in 32bit mode\n")); | |
11263 | fprintf (stream, _(" i8086 Disassemble in 16bit mode\n")); | |
11264 | fprintf (stream, _(" att Display instruction in AT&T syntax\n")); | |
11265 | fprintf (stream, _(" intel Display instruction in Intel syntax\n")); | |
9d141669 L |
11266 | fprintf (stream, _(" att-mnemonic\n" |
11267 | " Display instruction in AT&T mnemonic\n")); | |
11268 | fprintf (stream, _(" intel-mnemonic\n" | |
11269 | " Display instruction in Intel mnemonic\n")); | |
f59a29b9 L |
11270 | fprintf (stream, _(" addr64 Assume 64bit address size\n")); |
11271 | fprintf (stream, _(" addr32 Assume 32bit address size\n")); | |
11272 | fprintf (stream, _(" addr16 Assume 16bit address size\n")); | |
11273 | fprintf (stream, _(" data32 Assume 32bit data size\n")); | |
11274 | fprintf (stream, _(" data16 Assume 16bit data size\n")); | |
11275 | fprintf (stream, _(" suffix Always display instruction suffix in AT&T syntax\n")); | |
5db04b09 L |
11276 | fprintf (stream, _(" amd64 Display instruction in AMD64 ISA\n")); |
11277 | fprintf (stream, _(" intel64 Display instruction in Intel64 ISA\n")); | |
f59a29b9 L |
11278 | } |
11279 | ||
592d1631 | 11280 | /* Bad opcode. */ |
bf890a93 | 11281 | static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 }; |
592d1631 | 11282 | |
b844680a L |
11283 | /* Get a pointer to struct dis386 with a valid name. */ |
11284 | ||
11285 | static const struct dis386 * | |
8bb15339 | 11286 | get_valid_dis386 (const struct dis386 *dp, disassemble_info *info) |
b844680a | 11287 | { |
91d6fa6a | 11288 | int vindex, vex_table_index; |
b844680a L |
11289 | |
11290 | if (dp->name != NULL) | |
11291 | return dp; | |
11292 | ||
11293 | switch (dp->op[0].bytemode) | |
11294 | { | |
1ceb70f8 L |
11295 | case USE_REG_TABLE: |
11296 | dp = ®_table[dp->op[1].bytemode][modrm.reg]; | |
11297 | break; | |
11298 | ||
11299 | case USE_MOD_TABLE: | |
91d6fa6a NC |
11300 | vindex = modrm.mod == 0x3 ? 1 : 0; |
11301 | dp = &mod_table[dp->op[1].bytemode][vindex]; | |
1ceb70f8 L |
11302 | break; |
11303 | ||
11304 | case USE_RM_TABLE: | |
11305 | dp = &rm_table[dp->op[1].bytemode][modrm.rm]; | |
b844680a L |
11306 | break; |
11307 | ||
4e7d34a6 | 11308 | case USE_PREFIX_TABLE: |
c0f3af97 | 11309 | if (need_vex) |
b844680a | 11310 | { |
c0f3af97 L |
11311 | /* The prefix in VEX is implicit. */ |
11312 | switch (vex.prefix) | |
11313 | { | |
11314 | case 0: | |
91d6fa6a | 11315 | vindex = 0; |
c0f3af97 L |
11316 | break; |
11317 | case REPE_PREFIX_OPCODE: | |
91d6fa6a | 11318 | vindex = 1; |
c0f3af97 L |
11319 | break; |
11320 | case DATA_PREFIX_OPCODE: | |
91d6fa6a | 11321 | vindex = 2; |
c0f3af97 L |
11322 | break; |
11323 | case REPNE_PREFIX_OPCODE: | |
91d6fa6a | 11324 | vindex = 3; |
c0f3af97 L |
11325 | break; |
11326 | default: | |
11327 | abort (); | |
11328 | break; | |
11329 | } | |
b844680a | 11330 | } |
7bb15c6f | 11331 | else |
b844680a | 11332 | { |
285ca992 L |
11333 | int last_prefix = -1; |
11334 | int prefix = 0; | |
91d6fa6a | 11335 | vindex = 0; |
285ca992 L |
11336 | /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA. |
11337 | When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the | |
11338 | last one wins. */ | |
11339 | if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0) | |
b844680a | 11340 | { |
285ca992 | 11341 | if (last_repz_prefix > last_repnz_prefix) |
c0f3af97 | 11342 | { |
285ca992 L |
11343 | vindex = 1; |
11344 | prefix = PREFIX_REPZ; | |
11345 | last_prefix = last_repz_prefix; | |
c0f3af97 L |
11346 | } |
11347 | else | |
b844680a | 11348 | { |
285ca992 L |
11349 | vindex = 3; |
11350 | prefix = PREFIX_REPNZ; | |
11351 | last_prefix = last_repnz_prefix; | |
b844680a | 11352 | } |
285ca992 | 11353 | |
507bd325 L |
11354 | /* Check if prefix should be ignored. */ |
11355 | if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement | |
11356 | & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT) | |
11357 | & prefix) != 0) | |
285ca992 L |
11358 | vindex = 0; |
11359 | } | |
11360 | ||
11361 | if (vindex == 0 && (prefixes & PREFIX_DATA) != 0) | |
11362 | { | |
11363 | vindex = 2; | |
11364 | prefix = PREFIX_DATA; | |
11365 | last_prefix = last_data_prefix; | |
11366 | } | |
11367 | ||
11368 | if (vindex != 0) | |
11369 | { | |
11370 | used_prefixes |= prefix; | |
11371 | all_prefixes[last_prefix] = 0; | |
b844680a L |
11372 | } |
11373 | } | |
91d6fa6a | 11374 | dp = &prefix_table[dp->op[1].bytemode][vindex]; |
b844680a L |
11375 | break; |
11376 | ||
4e7d34a6 | 11377 | case USE_X86_64_TABLE: |
91d6fa6a NC |
11378 | vindex = address_mode == mode_64bit ? 1 : 0; |
11379 | dp = &x86_64_table[dp->op[1].bytemode][vindex]; | |
b844680a L |
11380 | break; |
11381 | ||
4e7d34a6 | 11382 | case USE_3BYTE_TABLE: |
8bb15339 | 11383 | FETCH_DATA (info, codep + 2); |
91d6fa6a NC |
11384 | vindex = *codep++; |
11385 | dp = &three_byte_table[dp->op[1].bytemode][vindex]; | |
285ca992 | 11386 | end_codep = codep; |
8bb15339 L |
11387 | modrm.mod = (*codep >> 6) & 3; |
11388 | modrm.reg = (*codep >> 3) & 7; | |
11389 | modrm.rm = *codep & 7; | |
11390 | break; | |
11391 | ||
c0f3af97 L |
11392 | case USE_VEX_LEN_TABLE: |
11393 | if (!need_vex) | |
11394 | abort (); | |
11395 | ||
11396 | switch (vex.length) | |
11397 | { | |
11398 | case 128: | |
91d6fa6a | 11399 | vindex = 0; |
c0f3af97 L |
11400 | break; |
11401 | case 256: | |
91d6fa6a | 11402 | vindex = 1; |
c0f3af97 L |
11403 | break; |
11404 | default: | |
11405 | abort (); | |
11406 | break; | |
11407 | } | |
11408 | ||
91d6fa6a | 11409 | dp = &vex_len_table[dp->op[1].bytemode][vindex]; |
c0f3af97 L |
11410 | break; |
11411 | ||
04e2a182 L |
11412 | case USE_EVEX_LEN_TABLE: |
11413 | if (!vex.evex) | |
11414 | abort (); | |
11415 | ||
11416 | switch (vex.length) | |
11417 | { | |
11418 | case 128: | |
11419 | vindex = 0; | |
11420 | break; | |
11421 | case 256: | |
11422 | vindex = 1; | |
11423 | break; | |
11424 | case 512: | |
11425 | vindex = 2; | |
11426 | break; | |
11427 | default: | |
11428 | abort (); | |
11429 | break; | |
11430 | } | |
11431 | ||
11432 | dp = &evex_len_table[dp->op[1].bytemode][vindex]; | |
11433 | break; | |
11434 | ||
f88c9eb0 SP |
11435 | case USE_XOP_8F_TABLE: |
11436 | FETCH_DATA (info, codep + 3); | |
f88c9eb0 SP |
11437 | rex = ~(*codep >> 5) & 0x7; |
11438 | ||
11439 | /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */ | |
11440 | switch ((*codep & 0x1f)) | |
11441 | { | |
11442 | default: | |
f07af43e L |
11443 | dp = &bad_opcode; |
11444 | return dp; | |
5dd85c99 SP |
11445 | case 0x8: |
11446 | vex_table_index = XOP_08; | |
11447 | break; | |
f88c9eb0 SP |
11448 | case 0x9: |
11449 | vex_table_index = XOP_09; | |
11450 | break; | |
11451 | case 0xa: | |
11452 | vex_table_index = XOP_0A; | |
11453 | break; | |
11454 | } | |
11455 | codep++; | |
11456 | vex.w = *codep & 0x80; | |
11457 | if (vex.w && address_mode == mode_64bit) | |
11458 | rex |= REX_W; | |
11459 | ||
11460 | vex.register_specifier = (~(*codep >> 3)) & 0xf; | |
abfcb414 | 11461 | if (address_mode != mode_64bit) |
f07af43e | 11462 | { |
abfcb414 AP |
11463 | /* In 16/32-bit mode REX_B is silently ignored. */ |
11464 | rex &= ~REX_B; | |
f07af43e | 11465 | } |
f88c9eb0 SP |
11466 | |
11467 | vex.length = (*codep & 0x4) ? 256 : 128; | |
11468 | switch ((*codep & 0x3)) | |
11469 | { | |
11470 | case 0: | |
f88c9eb0 SP |
11471 | break; |
11472 | case 1: | |
11473 | vex.prefix = DATA_PREFIX_OPCODE; | |
11474 | break; | |
11475 | case 2: | |
11476 | vex.prefix = REPE_PREFIX_OPCODE; | |
11477 | break; | |
11478 | case 3: | |
11479 | vex.prefix = REPNE_PREFIX_OPCODE; | |
11480 | break; | |
11481 | } | |
11482 | need_vex = 1; | |
11483 | need_vex_reg = 1; | |
11484 | codep++; | |
91d6fa6a NC |
11485 | vindex = *codep++; |
11486 | dp = &xop_table[vex_table_index][vindex]; | |
c48244a5 | 11487 | |
285ca992 | 11488 | end_codep = codep; |
c48244a5 SP |
11489 | FETCH_DATA (info, codep + 1); |
11490 | modrm.mod = (*codep >> 6) & 3; | |
11491 | modrm.reg = (*codep >> 3) & 7; | |
11492 | modrm.rm = *codep & 7; | |
f88c9eb0 SP |
11493 | break; |
11494 | ||
c0f3af97 | 11495 | case USE_VEX_C4_TABLE: |
43234a1e | 11496 | /* VEX prefix. */ |
c0f3af97 | 11497 | FETCH_DATA (info, codep + 3); |
c0f3af97 L |
11498 | rex = ~(*codep >> 5) & 0x7; |
11499 | switch ((*codep & 0x1f)) | |
11500 | { | |
11501 | default: | |
f07af43e L |
11502 | dp = &bad_opcode; |
11503 | return dp; | |
c0f3af97 | 11504 | case 0x1: |
f88c9eb0 | 11505 | vex_table_index = VEX_0F; |
c0f3af97 L |
11506 | break; |
11507 | case 0x2: | |
f88c9eb0 | 11508 | vex_table_index = VEX_0F38; |
c0f3af97 L |
11509 | break; |
11510 | case 0x3: | |
f88c9eb0 | 11511 | vex_table_index = VEX_0F3A; |
c0f3af97 L |
11512 | break; |
11513 | } | |
11514 | codep++; | |
11515 | vex.w = *codep & 0x80; | |
9889cbb1 | 11516 | if (address_mode == mode_64bit) |
f07af43e | 11517 | { |
9889cbb1 L |
11518 | if (vex.w) |
11519 | rex |= REX_W; | |
9889cbb1 L |
11520 | } |
11521 | else | |
11522 | { | |
11523 | /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit | |
11524 | is ignored, other REX bits are 0 and the highest bit in | |
5f847646 | 11525 | VEX.vvvv is also ignored (but we mustn't clear it here). */ |
9889cbb1 | 11526 | rex = 0; |
f07af43e | 11527 | } |
5f847646 | 11528 | vex.register_specifier = (~(*codep >> 3)) & 0xf; |
c0f3af97 L |
11529 | vex.length = (*codep & 0x4) ? 256 : 128; |
11530 | switch ((*codep & 0x3)) | |
11531 | { | |
11532 | case 0: | |
c0f3af97 L |
11533 | break; |
11534 | case 1: | |
11535 | vex.prefix = DATA_PREFIX_OPCODE; | |
11536 | break; | |
11537 | case 2: | |
11538 | vex.prefix = REPE_PREFIX_OPCODE; | |
11539 | break; | |
11540 | case 3: | |
11541 | vex.prefix = REPNE_PREFIX_OPCODE; | |
11542 | break; | |
11543 | } | |
11544 | need_vex = 1; | |
11545 | need_vex_reg = 1; | |
11546 | codep++; | |
91d6fa6a NC |
11547 | vindex = *codep++; |
11548 | dp = &vex_table[vex_table_index][vindex]; | |
285ca992 | 11549 | end_codep = codep; |
53c4d625 JB |
11550 | /* There is no MODRM byte for VEX0F 77. */ |
11551 | if (vex_table_index != VEX_0F || vindex != 0x77) | |
c0f3af97 L |
11552 | { |
11553 | FETCH_DATA (info, codep + 1); | |
11554 | modrm.mod = (*codep >> 6) & 3; | |
11555 | modrm.reg = (*codep >> 3) & 7; | |
11556 | modrm.rm = *codep & 7; | |
11557 | } | |
11558 | break; | |
11559 | ||
11560 | case USE_VEX_C5_TABLE: | |
43234a1e | 11561 | /* VEX prefix. */ |
c0f3af97 | 11562 | FETCH_DATA (info, codep + 2); |
c0f3af97 L |
11563 | rex = (*codep & 0x80) ? 0 : REX_R; |
11564 | ||
9889cbb1 L |
11565 | /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in |
11566 | VEX.vvvv is 1. */ | |
c0f3af97 | 11567 | vex.register_specifier = (~(*codep >> 3)) & 0xf; |
c0f3af97 L |
11568 | vex.length = (*codep & 0x4) ? 256 : 128; |
11569 | switch ((*codep & 0x3)) | |
11570 | { | |
11571 | case 0: | |
c0f3af97 L |
11572 | break; |
11573 | case 1: | |
11574 | vex.prefix = DATA_PREFIX_OPCODE; | |
11575 | break; | |
11576 | case 2: | |
11577 | vex.prefix = REPE_PREFIX_OPCODE; | |
11578 | break; | |
11579 | case 3: | |
11580 | vex.prefix = REPNE_PREFIX_OPCODE; | |
11581 | break; | |
11582 | } | |
11583 | need_vex = 1; | |
11584 | need_vex_reg = 1; | |
11585 | codep++; | |
91d6fa6a NC |
11586 | vindex = *codep++; |
11587 | dp = &vex_table[dp->op[1].bytemode][vindex]; | |
285ca992 | 11588 | end_codep = codep; |
53c4d625 JB |
11589 | /* There is no MODRM byte for VEX 77. */ |
11590 | if (vindex != 0x77) | |
c0f3af97 L |
11591 | { |
11592 | FETCH_DATA (info, codep + 1); | |
11593 | modrm.mod = (*codep >> 6) & 3; | |
11594 | modrm.reg = (*codep >> 3) & 7; | |
11595 | modrm.rm = *codep & 7; | |
11596 | } | |
11597 | break; | |
11598 | ||
9e30b8e0 L |
11599 | case USE_VEX_W_TABLE: |
11600 | if (!need_vex) | |
11601 | abort (); | |
11602 | ||
11603 | dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0]; | |
11604 | break; | |
11605 | ||
43234a1e L |
11606 | case USE_EVEX_TABLE: |
11607 | two_source_ops = 0; | |
11608 | /* EVEX prefix. */ | |
11609 | vex.evex = 1; | |
11610 | FETCH_DATA (info, codep + 4); | |
43234a1e L |
11611 | /* The first byte after 0x62. */ |
11612 | rex = ~(*codep >> 5) & 0x7; | |
11613 | vex.r = *codep & 0x10; | |
11614 | switch ((*codep & 0xf)) | |
11615 | { | |
11616 | default: | |
11617 | return &bad_opcode; | |
11618 | case 0x1: | |
11619 | vex_table_index = EVEX_0F; | |
11620 | break; | |
11621 | case 0x2: | |
11622 | vex_table_index = EVEX_0F38; | |
11623 | break; | |
11624 | case 0x3: | |
11625 | vex_table_index = EVEX_0F3A; | |
11626 | break; | |
11627 | } | |
11628 | ||
11629 | /* The second byte after 0x62. */ | |
11630 | codep++; | |
11631 | vex.w = *codep & 0x80; | |
11632 | if (vex.w && address_mode == mode_64bit) | |
11633 | rex |= REX_W; | |
11634 | ||
11635 | vex.register_specifier = (~(*codep >> 3)) & 0xf; | |
43234a1e L |
11636 | |
11637 | /* The U bit. */ | |
11638 | if (!(*codep & 0x4)) | |
11639 | return &bad_opcode; | |
11640 | ||
11641 | switch ((*codep & 0x3)) | |
11642 | { | |
11643 | case 0: | |
43234a1e L |
11644 | break; |
11645 | case 1: | |
11646 | vex.prefix = DATA_PREFIX_OPCODE; | |
11647 | break; | |
11648 | case 2: | |
11649 | vex.prefix = REPE_PREFIX_OPCODE; | |
11650 | break; | |
11651 | case 3: | |
11652 | vex.prefix = REPNE_PREFIX_OPCODE; | |
11653 | break; | |
11654 | } | |
11655 | ||
11656 | /* The third byte after 0x62. */ | |
11657 | codep++; | |
11658 | ||
11659 | /* Remember the static rounding bits. */ | |
11660 | vex.ll = (*codep >> 5) & 3; | |
11661 | vex.b = (*codep & 0x10) != 0; | |
11662 | ||
11663 | vex.v = *codep & 0x8; | |
11664 | vex.mask_register_specifier = *codep & 0x7; | |
11665 | vex.zeroing = *codep & 0x80; | |
11666 | ||
5f847646 JB |
11667 | if (address_mode != mode_64bit) |
11668 | { | |
11669 | /* In 16/32-bit mode silently ignore following bits. */ | |
11670 | rex &= ~REX_B; | |
11671 | vex.r = 1; | |
11672 | vex.v = 1; | |
11673 | } | |
11674 | ||
43234a1e L |
11675 | need_vex = 1; |
11676 | need_vex_reg = 1; | |
11677 | codep++; | |
11678 | vindex = *codep++; | |
11679 | dp = &evex_table[vex_table_index][vindex]; | |
285ca992 | 11680 | end_codep = codep; |
43234a1e L |
11681 | FETCH_DATA (info, codep + 1); |
11682 | modrm.mod = (*codep >> 6) & 3; | |
11683 | modrm.reg = (*codep >> 3) & 7; | |
11684 | modrm.rm = *codep & 7; | |
11685 | ||
11686 | /* Set vector length. */ | |
11687 | if (modrm.mod == 3 && vex.b) | |
11688 | vex.length = 512; | |
11689 | else | |
11690 | { | |
11691 | switch (vex.ll) | |
11692 | { | |
11693 | case 0x0: | |
11694 | vex.length = 128; | |
11695 | break; | |
11696 | case 0x1: | |
11697 | vex.length = 256; | |
11698 | break; | |
11699 | case 0x2: | |
11700 | vex.length = 512; | |
11701 | break; | |
11702 | default: | |
11703 | return &bad_opcode; | |
11704 | } | |
11705 | } | |
11706 | break; | |
11707 | ||
592d1631 L |
11708 | case 0: |
11709 | dp = &bad_opcode; | |
11710 | break; | |
11711 | ||
b844680a | 11712 | default: |
d34b5006 | 11713 | abort (); |
b844680a L |
11714 | } |
11715 | ||
11716 | if (dp->name != NULL) | |
11717 | return dp; | |
11718 | else | |
8bb15339 | 11719 | return get_valid_dis386 (dp, info); |
b844680a L |
11720 | } |
11721 | ||
dfc8cf43 | 11722 | static void |
55cf16e1 | 11723 | get_sib (disassemble_info *info, int sizeflag) |
dfc8cf43 L |
11724 | { |
11725 | /* If modrm.mod == 3, operand must be register. */ | |
11726 | if (need_modrm | |
55cf16e1 | 11727 | && ((sizeflag & AFLAG) || address_mode == mode_64bit) |
dfc8cf43 L |
11728 | && modrm.mod != 3 |
11729 | && modrm.rm == 4) | |
11730 | { | |
11731 | FETCH_DATA (info, codep + 2); | |
11732 | sib.index = (codep [1] >> 3) & 7; | |
11733 | sib.scale = (codep [1] >> 6) & 3; | |
11734 | sib.base = codep [1] & 7; | |
11735 | } | |
11736 | } | |
11737 | ||
e396998b | 11738 | static int |
26ca5450 | 11739 | print_insn (bfd_vma pc, disassemble_info *info) |
252b5132 | 11740 | { |
2da11e11 | 11741 | const struct dis386 *dp; |
252b5132 | 11742 | int i; |
ce518a5f | 11743 | char *op_txt[MAX_OPERANDS]; |
252b5132 | 11744 | int needcomma; |
df18fdba | 11745 | int sizeflag, orig_sizeflag; |
e396998b | 11746 | const char *p; |
252b5132 | 11747 | struct dis_private priv; |
f16cd0d5 | 11748 | int prefix_length; |
252b5132 | 11749 | |
d7921315 L |
11750 | priv.orig_sizeflag = AFLAG | DFLAG; |
11751 | if ((info->mach & bfd_mach_i386_i386) != 0) | |
cb712a9e | 11752 | address_mode = mode_32bit; |
2da11e11 | 11753 | else if (info->mach == bfd_mach_i386_i8086) |
d7921315 L |
11754 | { |
11755 | address_mode = mode_16bit; | |
11756 | priv.orig_sizeflag = 0; | |
11757 | } | |
2da11e11 | 11758 | else |
d7921315 L |
11759 | address_mode = mode_64bit; |
11760 | ||
11761 | if (intel_syntax == (char) -1) | |
11762 | intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0; | |
e396998b AM |
11763 | |
11764 | for (p = info->disassembler_options; p != NULL; ) | |
11765 | { | |
5db04b09 L |
11766 | if (CONST_STRNEQ (p, "amd64")) |
11767 | isa64 = amd64; | |
11768 | else if (CONST_STRNEQ (p, "intel64")) | |
11769 | isa64 = intel64; | |
11770 | else if (CONST_STRNEQ (p, "x86-64")) | |
e396998b | 11771 | { |
cb712a9e | 11772 | address_mode = mode_64bit; |
2a1bb84c | 11773 | priv.orig_sizeflag |= AFLAG | DFLAG; |
e396998b | 11774 | } |
0112cd26 | 11775 | else if (CONST_STRNEQ (p, "i386")) |
e396998b | 11776 | { |
cb712a9e | 11777 | address_mode = mode_32bit; |
2a1bb84c | 11778 | priv.orig_sizeflag |= AFLAG | DFLAG; |
e396998b | 11779 | } |
0112cd26 | 11780 | else if (CONST_STRNEQ (p, "i8086")) |
e396998b | 11781 | { |
cb712a9e | 11782 | address_mode = mode_16bit; |
2a1bb84c | 11783 | priv.orig_sizeflag &= ~(AFLAG | DFLAG); |
e396998b | 11784 | } |
0112cd26 | 11785 | else if (CONST_STRNEQ (p, "intel")) |
e396998b AM |
11786 | { |
11787 | intel_syntax = 1; | |
9d141669 L |
11788 | if (CONST_STRNEQ (p + 5, "-mnemonic")) |
11789 | intel_mnemonic = 1; | |
e396998b | 11790 | } |
0112cd26 | 11791 | else if (CONST_STRNEQ (p, "att")) |
e396998b AM |
11792 | { |
11793 | intel_syntax = 0; | |
9d141669 L |
11794 | if (CONST_STRNEQ (p + 3, "-mnemonic")) |
11795 | intel_mnemonic = 0; | |
e396998b | 11796 | } |
0112cd26 | 11797 | else if (CONST_STRNEQ (p, "addr")) |
e396998b | 11798 | { |
f59a29b9 L |
11799 | if (address_mode == mode_64bit) |
11800 | { | |
11801 | if (p[4] == '3' && p[5] == '2') | |
11802 | priv.orig_sizeflag &= ~AFLAG; | |
11803 | else if (p[4] == '6' && p[5] == '4') | |
11804 | priv.orig_sizeflag |= AFLAG; | |
11805 | } | |
11806 | else | |
11807 | { | |
11808 | if (p[4] == '1' && p[5] == '6') | |
11809 | priv.orig_sizeflag &= ~AFLAG; | |
11810 | else if (p[4] == '3' && p[5] == '2') | |
11811 | priv.orig_sizeflag |= AFLAG; | |
11812 | } | |
e396998b | 11813 | } |
0112cd26 | 11814 | else if (CONST_STRNEQ (p, "data")) |
e396998b AM |
11815 | { |
11816 | if (p[4] == '1' && p[5] == '6') | |
11817 | priv.orig_sizeflag &= ~DFLAG; | |
11818 | else if (p[4] == '3' && p[5] == '2') | |
11819 | priv.orig_sizeflag |= DFLAG; | |
11820 | } | |
0112cd26 | 11821 | else if (CONST_STRNEQ (p, "suffix")) |
e396998b AM |
11822 | priv.orig_sizeflag |= SUFFIX_ALWAYS; |
11823 | ||
11824 | p = strchr (p, ','); | |
11825 | if (p != NULL) | |
11826 | p++; | |
11827 | } | |
11828 | ||
c0f92bf9 L |
11829 | if (address_mode == mode_64bit && sizeof (bfd_vma) < 8) |
11830 | { | |
11831 | (*info->fprintf_func) (info->stream, | |
11832 | _("64-bit address is disabled")); | |
11833 | return -1; | |
11834 | } | |
11835 | ||
e396998b AM |
11836 | if (intel_syntax) |
11837 | { | |
11838 | names64 = intel_names64; | |
11839 | names32 = intel_names32; | |
11840 | names16 = intel_names16; | |
11841 | names8 = intel_names8; | |
11842 | names8rex = intel_names8rex; | |
11843 | names_seg = intel_names_seg; | |
b9733481 | 11844 | names_mm = intel_names_mm; |
7e8b059b | 11845 | names_bnd = intel_names_bnd; |
b9733481 L |
11846 | names_xmm = intel_names_xmm; |
11847 | names_ymm = intel_names_ymm; | |
43234a1e | 11848 | names_zmm = intel_names_zmm; |
db51cc60 L |
11849 | index64 = intel_index64; |
11850 | index32 = intel_index32; | |
43234a1e | 11851 | names_mask = intel_names_mask; |
e396998b AM |
11852 | index16 = intel_index16; |
11853 | open_char = '['; | |
11854 | close_char = ']'; | |
11855 | separator_char = '+'; | |
11856 | scale_char = '*'; | |
11857 | } | |
11858 | else | |
11859 | { | |
11860 | names64 = att_names64; | |
11861 | names32 = att_names32; | |
11862 | names16 = att_names16; | |
11863 | names8 = att_names8; | |
11864 | names8rex = att_names8rex; | |
11865 | names_seg = att_names_seg; | |
b9733481 | 11866 | names_mm = att_names_mm; |
7e8b059b | 11867 | names_bnd = att_names_bnd; |
b9733481 L |
11868 | names_xmm = att_names_xmm; |
11869 | names_ymm = att_names_ymm; | |
43234a1e | 11870 | names_zmm = att_names_zmm; |
db51cc60 L |
11871 | index64 = att_index64; |
11872 | index32 = att_index32; | |
43234a1e | 11873 | names_mask = att_names_mask; |
e396998b AM |
11874 | index16 = att_index16; |
11875 | open_char = '('; | |
11876 | close_char = ')'; | |
11877 | separator_char = ','; | |
11878 | scale_char = ','; | |
11879 | } | |
2da11e11 | 11880 | |
4fe53c98 | 11881 | /* The output looks better if we put 7 bytes on a line, since that |
8a9036a4 L |
11882 | puts most long word instructions on a single line. Use 8 bytes |
11883 | for Intel L1OM. */ | |
d7921315 | 11884 | if ((info->mach & bfd_mach_l1om) != 0) |
8a9036a4 L |
11885 | info->bytes_per_line = 8; |
11886 | else | |
11887 | info->bytes_per_line = 7; | |
252b5132 | 11888 | |
26ca5450 | 11889 | info->private_data = &priv; |
252b5132 RH |
11890 | priv.max_fetched = priv.the_buffer; |
11891 | priv.insn_start = pc; | |
252b5132 RH |
11892 | |
11893 | obuf[0] = 0; | |
ce518a5f L |
11894 | for (i = 0; i < MAX_OPERANDS; ++i) |
11895 | { | |
11896 | op_out[i][0] = 0; | |
11897 | op_index[i] = -1; | |
11898 | } | |
252b5132 RH |
11899 | |
11900 | the_info = info; | |
11901 | start_pc = pc; | |
e396998b AM |
11902 | start_codep = priv.the_buffer; |
11903 | codep = priv.the_buffer; | |
252b5132 | 11904 | |
8df14d78 | 11905 | if (OPCODES_SIGSETJMP (priv.bailout) != 0) |
5076851f | 11906 | { |
7d421014 ILT |
11907 | const char *name; |
11908 | ||
5076851f | 11909 | /* Getting here means we tried for data but didn't get it. That |
e396998b AM |
11910 | means we have an incomplete instruction of some sort. Just |
11911 | print the first byte as a prefix or a .byte pseudo-op. */ | |
11912 | if (codep > priv.the_buffer) | |
5076851f | 11913 | { |
e396998b | 11914 | name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag); |
7d421014 ILT |
11915 | if (name != NULL) |
11916 | (*info->fprintf_func) (info->stream, "%s", name); | |
11917 | else | |
5076851f | 11918 | { |
7d421014 ILT |
11919 | /* Just print the first byte as a .byte instruction. */ |
11920 | (*info->fprintf_func) (info->stream, ".byte 0x%x", | |
e396998b | 11921 | (unsigned int) priv.the_buffer[0]); |
5076851f | 11922 | } |
5076851f | 11923 | |
7d421014 | 11924 | return 1; |
5076851f ILT |
11925 | } |
11926 | ||
11927 | return -1; | |
11928 | } | |
11929 | ||
52b15da3 | 11930 | obufp = obuf; |
f16cd0d5 L |
11931 | sizeflag = priv.orig_sizeflag; |
11932 | ||
11933 | if (!ckprefix () || rex_used) | |
11934 | { | |
11935 | /* Too many prefixes or unused REX prefixes. */ | |
11936 | for (i = 0; | |
f6dd4781 | 11937 | i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i]; |
f16cd0d5 | 11938 | i++) |
de882298 | 11939 | (*info->fprintf_func) (info->stream, "%s%s", |
6c067bbb | 11940 | i == 0 ? "" : " ", |
f16cd0d5 | 11941 | prefix_name (all_prefixes[i], sizeflag)); |
de882298 | 11942 | return i; |
f16cd0d5 | 11943 | } |
252b5132 RH |
11944 | |
11945 | insn_codep = codep; | |
11946 | ||
11947 | FETCH_DATA (info, codep + 1); | |
11948 | two_source_ops = (*codep == 0x62) || (*codep == 0xc8); | |
11949 | ||
3e7d61b2 | 11950 | if (((prefixes & PREFIX_FWAIT) |
f16cd0d5 | 11951 | && ((*codep < 0xd8) || (*codep > 0xdf)))) |
252b5132 | 11952 | { |
86a80a50 | 11953 | /* Handle prefixes before fwait. */ |
d9949a36 | 11954 | for (i = 0; i < fwait_prefix && all_prefixes[i]; |
86a80a50 L |
11955 | i++) |
11956 | (*info->fprintf_func) (info->stream, "%s ", | |
11957 | prefix_name (all_prefixes[i], sizeflag)); | |
f16cd0d5 | 11958 | (*info->fprintf_func) (info->stream, "fwait"); |
86a80a50 | 11959 | return i + 1; |
252b5132 RH |
11960 | } |
11961 | ||
252b5132 RH |
11962 | if (*codep == 0x0f) |
11963 | { | |
eec0f4ca | 11964 | unsigned char threebyte; |
5f40e14d JS |
11965 | |
11966 | codep++; | |
11967 | FETCH_DATA (info, codep + 1); | |
11968 | threebyte = *codep; | |
eec0f4ca | 11969 | dp = &dis386_twobyte[threebyte]; |
252b5132 | 11970 | need_modrm = twobyte_has_modrm[*codep]; |
eec0f4ca | 11971 | codep++; |
252b5132 RH |
11972 | } |
11973 | else | |
11974 | { | |
6439fc28 | 11975 | dp = &dis386[*codep]; |
252b5132 | 11976 | need_modrm = onebyte_has_modrm[*codep]; |
eec0f4ca | 11977 | codep++; |
252b5132 | 11978 | } |
246c51aa | 11979 | |
df18fdba L |
11980 | /* Save sizeflag for printing the extra prefixes later before updating |
11981 | it for mnemonic and operand processing. The prefix names depend | |
11982 | only on the address mode. */ | |
11983 | orig_sizeflag = sizeflag; | |
c608c12e | 11984 | if (prefixes & PREFIX_ADDR) |
df18fdba | 11985 | sizeflag ^= AFLAG; |
b844680a | 11986 | if ((prefixes & PREFIX_DATA)) |
df18fdba | 11987 | sizeflag ^= DFLAG; |
3ffd33cf | 11988 | |
285ca992 | 11989 | end_codep = codep; |
8bb15339 | 11990 | if (need_modrm) |
252b5132 RH |
11991 | { |
11992 | FETCH_DATA (info, codep + 1); | |
7967e09e L |
11993 | modrm.mod = (*codep >> 6) & 3; |
11994 | modrm.reg = (*codep >> 3) & 7; | |
11995 | modrm.rm = *codep & 7; | |
252b5132 RH |
11996 | } |
11997 | ||
42d5f9c6 MS |
11998 | need_vex = 0; |
11999 | need_vex_reg = 0; | |
12000 | vex_w_done = 0; | |
caf0678c | 12001 | memset (&vex, 0, sizeof (vex)); |
55b126d4 | 12002 | |
ce518a5f | 12003 | if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE) |
252b5132 | 12004 | { |
55cf16e1 | 12005 | get_sib (info, sizeflag); |
252b5132 RH |
12006 | dofloat (sizeflag); |
12007 | } | |
12008 | else | |
12009 | { | |
8bb15339 | 12010 | dp = get_valid_dis386 (dp, info); |
b844680a | 12011 | if (dp != NULL && putop (dp->name, sizeflag) == 0) |
6c067bbb | 12012 | { |
55cf16e1 | 12013 | get_sib (info, sizeflag); |
ce518a5f L |
12014 | for (i = 0; i < MAX_OPERANDS; ++i) |
12015 | { | |
246c51aa | 12016 | obufp = op_out[i]; |
ce518a5f L |
12017 | op_ad = MAX_OPERANDS - 1 - i; |
12018 | if (dp->op[i].rtn) | |
12019 | (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag); | |
43234a1e L |
12020 | /* For EVEX instruction after the last operand masking |
12021 | should be printed. */ | |
12022 | if (i == 0 && vex.evex) | |
12023 | { | |
12024 | /* Don't print {%k0}. */ | |
12025 | if (vex.mask_register_specifier) | |
12026 | { | |
12027 | oappend ("{"); | |
12028 | oappend (names_mask[vex.mask_register_specifier]); | |
12029 | oappend ("}"); | |
12030 | } | |
12031 | if (vex.zeroing) | |
12032 | oappend ("{z}"); | |
12033 | } | |
ce518a5f | 12034 | } |
6439fc28 | 12035 | } |
252b5132 RH |
12036 | } |
12037 | ||
1d67fe3b TT |
12038 | /* Clear instruction information. */ |
12039 | if (the_info) | |
12040 | { | |
12041 | the_info->insn_info_valid = 0; | |
12042 | the_info->branch_delay_insns = 0; | |
12043 | the_info->data_size = 0; | |
12044 | the_info->insn_type = dis_noninsn; | |
12045 | the_info->target = 0; | |
12046 | the_info->target2 = 0; | |
12047 | } | |
12048 | ||
12049 | /* Reset jump operation indicator. */ | |
12050 | op_is_jump = FALSE; | |
12051 | ||
12052 | { | |
12053 | int jump_detection = 0; | |
12054 | ||
12055 | /* Extract flags. */ | |
12056 | for (i = 0; i < MAX_OPERANDS; ++i) | |
12057 | { | |
12058 | if ((dp->op[i].rtn == OP_J) | |
12059 | || (dp->op[i].rtn == OP_indirE)) | |
12060 | jump_detection |= 1; | |
12061 | else if ((dp->op[i].rtn == BND_Fixup) | |
12062 | || (!dp->op[i].rtn && !dp->op[i].bytemode)) | |
12063 | jump_detection |= 2; | |
12064 | else if ((dp->op[i].bytemode == cond_jump_mode) | |
12065 | || (dp->op[i].bytemode == loop_jcxz_mode)) | |
12066 | jump_detection |= 4; | |
12067 | } | |
12068 | ||
12069 | /* Determine if this is a jump or branch. */ | |
12070 | if ((jump_detection & 0x3) == 0x3) | |
12071 | { | |
12072 | op_is_jump = TRUE; | |
12073 | if (jump_detection & 0x4) | |
12074 | the_info->insn_type = dis_condbranch; | |
12075 | else | |
12076 | the_info->insn_type = | |
12077 | (dp->name && !strncmp(dp->name, "call", 4)) | |
12078 | ? dis_jsr : dis_branch; | |
12079 | } | |
12080 | } | |
12081 | ||
63c6fc6c L |
12082 | /* If VEX.vvvv and EVEX.vvvv are unused, they must be all 1s, which |
12083 | are all 0s in inverted form. */ | |
12084 | if (need_vex && vex.register_specifier != 0) | |
12085 | { | |
12086 | (*info->fprintf_func) (info->stream, "(bad)"); | |
12087 | return end_codep - priv.the_buffer; | |
12088 | } | |
12089 | ||
d869730d | 12090 | /* Check if the REX prefix is used. */ |
73239888 | 12091 | if ((rex ^ rex_used) == 0 && !need_vex && last_rex_prefix >= 0) |
f16cd0d5 L |
12092 | all_prefixes[last_rex_prefix] = 0; |
12093 | ||
5e6718e4 | 12094 | /* Check if the SEG prefix is used. */ |
f16cd0d5 L |
12095 | if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES |
12096 | | PREFIX_FS | PREFIX_GS)) != 0 | |
285ca992 | 12097 | && (used_prefixes & active_seg_prefix) != 0) |
f16cd0d5 L |
12098 | all_prefixes[last_seg_prefix] = 0; |
12099 | ||
5e6718e4 | 12100 | /* Check if the ADDR prefix is used. */ |
f16cd0d5 L |
12101 | if ((prefixes & PREFIX_ADDR) != 0 |
12102 | && (used_prefixes & PREFIX_ADDR) != 0) | |
12103 | all_prefixes[last_addr_prefix] = 0; | |
12104 | ||
df18fdba L |
12105 | /* Check if the DATA prefix is used. */ |
12106 | if ((prefixes & PREFIX_DATA) != 0 | |
73239888 JB |
12107 | && (used_prefixes & PREFIX_DATA) != 0 |
12108 | && !need_vex) | |
df18fdba | 12109 | all_prefixes[last_data_prefix] = 0; |
f16cd0d5 | 12110 | |
df18fdba | 12111 | /* Print the extra prefixes. */ |
f16cd0d5 | 12112 | prefix_length = 0; |
f310f33d | 12113 | for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++) |
f16cd0d5 L |
12114 | if (all_prefixes[i]) |
12115 | { | |
12116 | const char *name; | |
df18fdba | 12117 | name = prefix_name (all_prefixes[i], orig_sizeflag); |
f16cd0d5 L |
12118 | if (name == NULL) |
12119 | abort (); | |
12120 | prefix_length += strlen (name) + 1; | |
12121 | (*info->fprintf_func) (info->stream, "%s ", name); | |
12122 | } | |
b844680a | 12123 | |
285ca992 L |
12124 | /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is |
12125 | unused, opcode is invalid. Since the PREFIX_DATA prefix may be | |
12126 | used by putop and MMX/SSE operand and may be overriden by the | |
12127 | PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix | |
12128 | separately. */ | |
3888916d | 12129 | if (dp->prefix_requirement == PREFIX_OPCODE |
bf926894 JB |
12130 | && (((need_vex |
12131 | ? vex.prefix == REPE_PREFIX_OPCODE | |
12132 | || vex.prefix == REPNE_PREFIX_OPCODE | |
12133 | : (prefixes | |
12134 | & (PREFIX_REPZ | PREFIX_REPNZ)) != 0) | |
285ca992 L |
12135 | && (used_prefixes |
12136 | & (PREFIX_REPZ | PREFIX_REPNZ)) == 0) | |
bf926894 JB |
12137 | || (((need_vex |
12138 | ? vex.prefix == DATA_PREFIX_OPCODE | |
12139 | : ((prefixes | |
12140 | & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA)) | |
12141 | == PREFIX_DATA)) | |
97e6786a JB |
12142 | && (used_prefixes & PREFIX_DATA) == 0)) |
12143 | || (vex.evex && !vex.w != !(used_prefixes & PREFIX_DATA)))) | |
285ca992 L |
12144 | { |
12145 | (*info->fprintf_func) (info->stream, "(bad)"); | |
12146 | return end_codep - priv.the_buffer; | |
12147 | } | |
12148 | ||
f16cd0d5 L |
12149 | /* Check maximum code length. */ |
12150 | if ((codep - start_codep) > MAX_CODE_LENGTH) | |
12151 | { | |
12152 | (*info->fprintf_func) (info->stream, "(bad)"); | |
12153 | return MAX_CODE_LENGTH; | |
12154 | } | |
b844680a | 12155 | |
ea397f5b | 12156 | obufp = mnemonicendp; |
f16cd0d5 | 12157 | for (i = strlen (obuf) + prefix_length; i < 6; i++) |
252b5132 RH |
12158 | oappend (" "); |
12159 | oappend (" "); | |
12160 | (*info->fprintf_func) (info->stream, "%s", obuf); | |
12161 | ||
12162 | /* The enter and bound instructions are printed with operands in the same | |
12163 | order as the intel book; everything else is printed in reverse order. */ | |
2da11e11 | 12164 | if (intel_syntax || two_source_ops) |
252b5132 | 12165 | { |
185b1163 L |
12166 | bfd_vma riprel; |
12167 | ||
ce518a5f | 12168 | for (i = 0; i < MAX_OPERANDS; ++i) |
6c067bbb | 12169 | op_txt[i] = op_out[i]; |
246c51aa | 12170 | |
3a8547d2 JB |
12171 | if (intel_syntax && dp && dp->op[2].rtn == OP_Rounding |
12172 | && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL) | |
12173 | { | |
12174 | op_txt[2] = op_out[3]; | |
12175 | op_txt[3] = op_out[2]; | |
12176 | } | |
12177 | ||
ce518a5f L |
12178 | for (i = 0; i < (MAX_OPERANDS >> 1); ++i) |
12179 | { | |
6c067bbb RM |
12180 | op_ad = op_index[i]; |
12181 | op_index[i] = op_index[MAX_OPERANDS - 1 - i]; | |
12182 | op_index[MAX_OPERANDS - 1 - i] = op_ad; | |
185b1163 L |
12183 | riprel = op_riprel[i]; |
12184 | op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i]; | |
12185 | op_riprel[MAX_OPERANDS - 1 - i] = riprel; | |
ce518a5f | 12186 | } |
252b5132 RH |
12187 | } |
12188 | else | |
12189 | { | |
ce518a5f | 12190 | for (i = 0; i < MAX_OPERANDS; ++i) |
6c067bbb | 12191 | op_txt[MAX_OPERANDS - 1 - i] = op_out[i]; |
050dfa73 MM |
12192 | } |
12193 | ||
ce518a5f L |
12194 | needcomma = 0; |
12195 | for (i = 0; i < MAX_OPERANDS; ++i) | |
12196 | if (*op_txt[i]) | |
12197 | { | |
12198 | if (needcomma) | |
12199 | (*info->fprintf_func) (info->stream, ","); | |
12200 | if (op_index[i] != -1 && !op_riprel[i]) | |
1d67fe3b TT |
12201 | { |
12202 | bfd_vma target = (bfd_vma) op_address[op_index[i]]; | |
12203 | ||
12204 | if (the_info && op_is_jump) | |
12205 | { | |
12206 | the_info->insn_info_valid = 1; | |
12207 | the_info->branch_delay_insns = 0; | |
12208 | the_info->data_size = 0; | |
12209 | the_info->target = target; | |
12210 | the_info->target2 = 0; | |
12211 | } | |
12212 | (*info->print_address_func) (target, info); | |
12213 | } | |
ce518a5f L |
12214 | else |
12215 | (*info->fprintf_func) (info->stream, "%s", op_txt[i]); | |
12216 | needcomma = 1; | |
12217 | } | |
050dfa73 | 12218 | |
ce518a5f | 12219 | for (i = 0; i < MAX_OPERANDS; i++) |
52b15da3 JH |
12220 | if (op_index[i] != -1 && op_riprel[i]) |
12221 | { | |
12222 | (*info->fprintf_func) (info->stream, " # "); | |
4fd7268a | 12223 | (*info->print_address_func) ((bfd_vma) (start_pc + (codep - start_codep) |
52b15da3 | 12224 | + op_address[op_index[i]]), info); |
185b1163 | 12225 | break; |
52b15da3 | 12226 | } |
e396998b | 12227 | return codep - priv.the_buffer; |
252b5132 RH |
12228 | } |
12229 | ||
6439fc28 | 12230 | static const char *float_mem[] = { |
252b5132 | 12231 | /* d8 */ |
7c52e0e8 L |
12232 | "fadd{s|}", |
12233 | "fmul{s|}", | |
12234 | "fcom{s|}", | |
12235 | "fcomp{s|}", | |
12236 | "fsub{s|}", | |
12237 | "fsubr{s|}", | |
12238 | "fdiv{s|}", | |
12239 | "fdivr{s|}", | |
db6eb5be | 12240 | /* d9 */ |
7c52e0e8 | 12241 | "fld{s|}", |
252b5132 | 12242 | "(bad)", |
7c52e0e8 L |
12243 | "fst{s|}", |
12244 | "fstp{s|}", | |
d1c36125 | 12245 | "fldenv{C|C}", |
252b5132 | 12246 | "fldcw", |
d1c36125 | 12247 | "fNstenv{C|C}", |
252b5132 RH |
12248 | "fNstcw", |
12249 | /* da */ | |
7c52e0e8 L |
12250 | "fiadd{l|}", |
12251 | "fimul{l|}", | |
12252 | "ficom{l|}", | |
12253 | "ficomp{l|}", | |
12254 | "fisub{l|}", | |
12255 | "fisubr{l|}", | |
12256 | "fidiv{l|}", | |
12257 | "fidivr{l|}", | |
252b5132 | 12258 | /* db */ |
7c52e0e8 L |
12259 | "fild{l|}", |
12260 | "fisttp{l|}", | |
12261 | "fist{l|}", | |
12262 | "fistp{l|}", | |
252b5132 | 12263 | "(bad)", |
464dc4af | 12264 | "fld{t|}", |
252b5132 | 12265 | "(bad)", |
464dc4af | 12266 | "fstp{t|}", |
252b5132 | 12267 | /* dc */ |
7c52e0e8 L |
12268 | "fadd{l|}", |
12269 | "fmul{l|}", | |
12270 | "fcom{l|}", | |
12271 | "fcomp{l|}", | |
12272 | "fsub{l|}", | |
12273 | "fsubr{l|}", | |
12274 | "fdiv{l|}", | |
12275 | "fdivr{l|}", | |
252b5132 | 12276 | /* dd */ |
7c52e0e8 L |
12277 | "fld{l|}", |
12278 | "fisttp{ll|}", | |
12279 | "fst{l||}", | |
12280 | "fstp{l|}", | |
d1c36125 | 12281 | "frstor{C|C}", |
252b5132 | 12282 | "(bad)", |
d1c36125 | 12283 | "fNsave{C|C}", |
252b5132 RH |
12284 | "fNstsw", |
12285 | /* de */ | |
ac465521 JB |
12286 | "fiadd{s|}", |
12287 | "fimul{s|}", | |
12288 | "ficom{s|}", | |
12289 | "ficomp{s|}", | |
12290 | "fisub{s|}", | |
12291 | "fisubr{s|}", | |
12292 | "fidiv{s|}", | |
12293 | "fidivr{s|}", | |
252b5132 | 12294 | /* df */ |
ac465521 JB |
12295 | "fild{s|}", |
12296 | "fisttp{s|}", | |
12297 | "fist{s|}", | |
12298 | "fistp{s|}", | |
252b5132 | 12299 | "fbld", |
7c52e0e8 | 12300 | "fild{ll|}", |
252b5132 | 12301 | "fbstp", |
7c52e0e8 | 12302 | "fistp{ll|}", |
1d9f512f AM |
12303 | }; |
12304 | ||
12305 | static const unsigned char float_mem_mode[] = { | |
12306 | /* d8 */ | |
12307 | d_mode, | |
12308 | d_mode, | |
12309 | d_mode, | |
12310 | d_mode, | |
12311 | d_mode, | |
12312 | d_mode, | |
12313 | d_mode, | |
12314 | d_mode, | |
12315 | /* d9 */ | |
12316 | d_mode, | |
12317 | 0, | |
12318 | d_mode, | |
12319 | d_mode, | |
12320 | 0, | |
12321 | w_mode, | |
12322 | 0, | |
12323 | w_mode, | |
12324 | /* da */ | |
12325 | d_mode, | |
12326 | d_mode, | |
12327 | d_mode, | |
12328 | d_mode, | |
12329 | d_mode, | |
12330 | d_mode, | |
12331 | d_mode, | |
12332 | d_mode, | |
12333 | /* db */ | |
12334 | d_mode, | |
12335 | d_mode, | |
12336 | d_mode, | |
12337 | d_mode, | |
12338 | 0, | |
9306ca4a | 12339 | t_mode, |
1d9f512f | 12340 | 0, |
9306ca4a | 12341 | t_mode, |
1d9f512f AM |
12342 | /* dc */ |
12343 | q_mode, | |
12344 | q_mode, | |
12345 | q_mode, | |
12346 | q_mode, | |
12347 | q_mode, | |
12348 | q_mode, | |
12349 | q_mode, | |
12350 | q_mode, | |
12351 | /* dd */ | |
12352 | q_mode, | |
12353 | q_mode, | |
12354 | q_mode, | |
12355 | q_mode, | |
12356 | 0, | |
12357 | 0, | |
12358 | 0, | |
12359 | w_mode, | |
12360 | /* de */ | |
12361 | w_mode, | |
12362 | w_mode, | |
12363 | w_mode, | |
12364 | w_mode, | |
12365 | w_mode, | |
12366 | w_mode, | |
12367 | w_mode, | |
12368 | w_mode, | |
12369 | /* df */ | |
12370 | w_mode, | |
12371 | w_mode, | |
12372 | w_mode, | |
12373 | w_mode, | |
9306ca4a | 12374 | t_mode, |
1d9f512f | 12375 | q_mode, |
9306ca4a | 12376 | t_mode, |
1d9f512f | 12377 | q_mode |
252b5132 RH |
12378 | }; |
12379 | ||
ce518a5f L |
12380 | #define ST { OP_ST, 0 } |
12381 | #define STi { OP_STi, 0 } | |
252b5132 | 12382 | |
48c97fa1 L |
12383 | #define FGRPd9_2 NULL, { { NULL, 1 } }, 0 |
12384 | #define FGRPd9_4 NULL, { { NULL, 2 } }, 0 | |
12385 | #define FGRPd9_5 NULL, { { NULL, 3 } }, 0 | |
12386 | #define FGRPd9_6 NULL, { { NULL, 4 } }, 0 | |
12387 | #define FGRPd9_7 NULL, { { NULL, 5 } }, 0 | |
12388 | #define FGRPda_5 NULL, { { NULL, 6 } }, 0 | |
12389 | #define FGRPdb_4 NULL, { { NULL, 7 } }, 0 | |
12390 | #define FGRPde_3 NULL, { { NULL, 8 } }, 0 | |
12391 | #define FGRPdf_4 NULL, { { NULL, 9 } }, 0 | |
252b5132 | 12392 | |
2da11e11 | 12393 | static const struct dis386 float_reg[][8] = { |
252b5132 RH |
12394 | /* d8 */ |
12395 | { | |
bf890a93 IT |
12396 | { "fadd", { ST, STi }, 0 }, |
12397 | { "fmul", { ST, STi }, 0 }, | |
12398 | { "fcom", { STi }, 0 }, | |
12399 | { "fcomp", { STi }, 0 }, | |
12400 | { "fsub", { ST, STi }, 0 }, | |
12401 | { "fsubr", { ST, STi }, 0 }, | |
12402 | { "fdiv", { ST, STi }, 0 }, | |
12403 | { "fdivr", { ST, STi }, 0 }, | |
252b5132 RH |
12404 | }, |
12405 | /* d9 */ | |
12406 | { | |
bf890a93 IT |
12407 | { "fld", { STi }, 0 }, |
12408 | { "fxch", { STi }, 0 }, | |
252b5132 | 12409 | { FGRPd9_2 }, |
592d1631 | 12410 | { Bad_Opcode }, |
252b5132 RH |
12411 | { FGRPd9_4 }, |
12412 | { FGRPd9_5 }, | |
12413 | { FGRPd9_6 }, | |
12414 | { FGRPd9_7 }, | |
12415 | }, | |
12416 | /* da */ | |
12417 | { | |
bf890a93 IT |
12418 | { "fcmovb", { ST, STi }, 0 }, |
12419 | { "fcmove", { ST, STi }, 0 }, | |
12420 | { "fcmovbe",{ ST, STi }, 0 }, | |
12421 | { "fcmovu", { ST, STi }, 0 }, | |
592d1631 | 12422 | { Bad_Opcode }, |
252b5132 | 12423 | { FGRPda_5 }, |
592d1631 L |
12424 | { Bad_Opcode }, |
12425 | { Bad_Opcode }, | |
252b5132 RH |
12426 | }, |
12427 | /* db */ | |
12428 | { | |
bf890a93 IT |
12429 | { "fcmovnb",{ ST, STi }, 0 }, |
12430 | { "fcmovne",{ ST, STi }, 0 }, | |
12431 | { "fcmovnbe",{ ST, STi }, 0 }, | |
12432 | { "fcmovnu",{ ST, STi }, 0 }, | |
252b5132 | 12433 | { FGRPdb_4 }, |
bf890a93 IT |
12434 | { "fucomi", { ST, STi }, 0 }, |
12435 | { "fcomi", { ST, STi }, 0 }, | |
592d1631 | 12436 | { Bad_Opcode }, |
252b5132 RH |
12437 | }, |
12438 | /* dc */ | |
12439 | { | |
bf890a93 IT |
12440 | { "fadd", { STi, ST }, 0 }, |
12441 | { "fmul", { STi, ST }, 0 }, | |
592d1631 L |
12442 | { Bad_Opcode }, |
12443 | { Bad_Opcode }, | |
d53e6b98 JB |
12444 | { "fsub{!M|r}", { STi, ST }, 0 }, |
12445 | { "fsub{M|}", { STi, ST }, 0 }, | |
12446 | { "fdiv{!M|r}", { STi, ST }, 0 }, | |
12447 | { "fdiv{M|}", { STi, ST }, 0 }, | |
252b5132 RH |
12448 | }, |
12449 | /* dd */ | |
12450 | { | |
bf890a93 | 12451 | { "ffree", { STi }, 0 }, |
592d1631 | 12452 | { Bad_Opcode }, |
bf890a93 IT |
12453 | { "fst", { STi }, 0 }, |
12454 | { "fstp", { STi }, 0 }, | |
12455 | { "fucom", { STi }, 0 }, | |
12456 | { "fucomp", { STi }, 0 }, | |
592d1631 L |
12457 | { Bad_Opcode }, |
12458 | { Bad_Opcode }, | |
252b5132 RH |
12459 | }, |
12460 | /* de */ | |
12461 | { | |
bf890a93 IT |
12462 | { "faddp", { STi, ST }, 0 }, |
12463 | { "fmulp", { STi, ST }, 0 }, | |
592d1631 | 12464 | { Bad_Opcode }, |
252b5132 | 12465 | { FGRPde_3 }, |
d53e6b98 JB |
12466 | { "fsub{!M|r}p", { STi, ST }, 0 }, |
12467 | { "fsub{M|}p", { STi, ST }, 0 }, | |
12468 | { "fdiv{!M|r}p", { STi, ST }, 0 }, | |
12469 | { "fdiv{M|}p", { STi, ST }, 0 }, | |
252b5132 RH |
12470 | }, |
12471 | /* df */ | |
12472 | { | |
bf890a93 | 12473 | { "ffreep", { STi }, 0 }, |
592d1631 L |
12474 | { Bad_Opcode }, |
12475 | { Bad_Opcode }, | |
12476 | { Bad_Opcode }, | |
252b5132 | 12477 | { FGRPdf_4 }, |
bf890a93 IT |
12478 | { "fucomip", { ST, STi }, 0 }, |
12479 | { "fcomip", { ST, STi }, 0 }, | |
592d1631 | 12480 | { Bad_Opcode }, |
252b5132 RH |
12481 | }, |
12482 | }; | |
12483 | ||
252b5132 | 12484 | static char *fgrps[][8] = { |
48c97fa1 L |
12485 | /* Bad opcode 0 */ |
12486 | { | |
12487 | "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
12488 | }, | |
12489 | ||
12490 | /* d9_2 1 */ | |
252b5132 RH |
12491 | { |
12492 | "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
12493 | }, | |
12494 | ||
48c97fa1 | 12495 | /* d9_4 2 */ |
252b5132 RH |
12496 | { |
12497 | "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)", | |
12498 | }, | |
12499 | ||
48c97fa1 | 12500 | /* d9_5 3 */ |
252b5132 RH |
12501 | { |
12502 | "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)", | |
12503 | }, | |
12504 | ||
48c97fa1 | 12505 | /* d9_6 4 */ |
252b5132 RH |
12506 | { |
12507 | "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp", | |
12508 | }, | |
12509 | ||
48c97fa1 | 12510 | /* d9_7 5 */ |
252b5132 RH |
12511 | { |
12512 | "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos", | |
12513 | }, | |
12514 | ||
48c97fa1 | 12515 | /* da_5 6 */ |
252b5132 RH |
12516 | { |
12517 | "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
12518 | }, | |
12519 | ||
48c97fa1 | 12520 | /* db_4 7 */ |
252b5132 | 12521 | { |
309d3373 JB |
12522 | "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit", |
12523 | "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)", | |
252b5132 RH |
12524 | }, |
12525 | ||
48c97fa1 | 12526 | /* de_3 8 */ |
252b5132 RH |
12527 | { |
12528 | "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
12529 | }, | |
12530 | ||
48c97fa1 | 12531 | /* df_4 9 */ |
252b5132 RH |
12532 | { |
12533 | "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
12534 | }, | |
12535 | }; | |
12536 | ||
b6169b20 L |
12537 | static void |
12538 | swap_operand (void) | |
12539 | { | |
12540 | mnemonicendp[0] = '.'; | |
12541 | mnemonicendp[1] = 's'; | |
12542 | mnemonicendp += 2; | |
12543 | } | |
12544 | ||
b844680a L |
12545 | static void |
12546 | OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED, | |
12547 | int sizeflag ATTRIBUTE_UNUSED) | |
12548 | { | |
12549 | /* Skip mod/rm byte. */ | |
12550 | MODRM_CHECK; | |
12551 | codep++; | |
12552 | } | |
12553 | ||
252b5132 | 12554 | static void |
26ca5450 | 12555 | dofloat (int sizeflag) |
252b5132 | 12556 | { |
2da11e11 | 12557 | const struct dis386 *dp; |
252b5132 RH |
12558 | unsigned char floatop; |
12559 | ||
12560 | floatop = codep[-1]; | |
12561 | ||
7967e09e | 12562 | if (modrm.mod != 3) |
252b5132 | 12563 | { |
7967e09e | 12564 | int fp_indx = (floatop - 0xd8) * 8 + modrm.reg; |
1d9f512f AM |
12565 | |
12566 | putop (float_mem[fp_indx], sizeflag); | |
ce518a5f | 12567 | obufp = op_out[0]; |
6e50d963 | 12568 | op_ad = 2; |
1d9f512f | 12569 | OP_E (float_mem_mode[fp_indx], sizeflag); |
252b5132 RH |
12570 | return; |
12571 | } | |
6608db57 | 12572 | /* Skip mod/rm byte. */ |
4bba6815 | 12573 | MODRM_CHECK; |
252b5132 RH |
12574 | codep++; |
12575 | ||
7967e09e | 12576 | dp = &float_reg[floatop - 0xd8][modrm.reg]; |
252b5132 RH |
12577 | if (dp->name == NULL) |
12578 | { | |
7967e09e | 12579 | putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag); |
252b5132 | 12580 | |
6608db57 | 12581 | /* Instruction fnstsw is only one with strange arg. */ |
252b5132 | 12582 | if (floatop == 0xdf && codep[-1] == 0xe0) |
ce518a5f | 12583 | strcpy (op_out[0], names16[0]); |
252b5132 RH |
12584 | } |
12585 | else | |
12586 | { | |
12587 | putop (dp->name, sizeflag); | |
12588 | ||
ce518a5f | 12589 | obufp = op_out[0]; |
6e50d963 | 12590 | op_ad = 2; |
ce518a5f L |
12591 | if (dp->op[0].rtn) |
12592 | (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag); | |
6e50d963 | 12593 | |
ce518a5f | 12594 | obufp = op_out[1]; |
6e50d963 | 12595 | op_ad = 1; |
ce518a5f L |
12596 | if (dp->op[1].rtn) |
12597 | (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag); | |
252b5132 RH |
12598 | } |
12599 | } | |
12600 | ||
9ce09ba2 RM |
12601 | /* Like oappend (below), but S is a string starting with '%'. |
12602 | In Intel syntax, the '%' is elided. */ | |
12603 | static void | |
12604 | oappend_maybe_intel (const char *s) | |
12605 | { | |
12606 | oappend (s + intel_syntax); | |
12607 | } | |
12608 | ||
252b5132 | 12609 | static void |
26ca5450 | 12610 | OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 12611 | { |
9ce09ba2 | 12612 | oappend_maybe_intel ("%st"); |
252b5132 RH |
12613 | } |
12614 | ||
252b5132 | 12615 | static void |
26ca5450 | 12616 | OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 12617 | { |
7967e09e | 12618 | sprintf (scratchbuf, "%%st(%d)", modrm.rm); |
9ce09ba2 | 12619 | oappend_maybe_intel (scratchbuf); |
252b5132 RH |
12620 | } |
12621 | ||
6608db57 | 12622 | /* Capital letters in template are macros. */ |
6439fc28 | 12623 | static int |
d3ce72d0 | 12624 | putop (const char *in_template, int sizeflag) |
252b5132 | 12625 | { |
2da11e11 | 12626 | const char *p; |
9306ca4a | 12627 | int alt = 0; |
9d141669 | 12628 | int cond = 1; |
98b528ac L |
12629 | unsigned int l = 0, len = 1; |
12630 | char last[4]; | |
12631 | ||
12632 | #define SAVE_LAST(c) \ | |
12633 | if (l < len && l < sizeof (last)) \ | |
12634 | last[l++] = c; \ | |
12635 | else \ | |
12636 | abort (); | |
252b5132 | 12637 | |
d3ce72d0 | 12638 | for (p = in_template; *p; p++) |
252b5132 RH |
12639 | { |
12640 | switch (*p) | |
12641 | { | |
12642 | default: | |
12643 | *obufp++ = *p; | |
12644 | break; | |
98b528ac L |
12645 | case '%': |
12646 | len++; | |
12647 | break; | |
9d141669 L |
12648 | case '!': |
12649 | cond = 0; | |
12650 | break; | |
6439fc28 | 12651 | case '{': |
6439fc28 | 12652 | if (intel_syntax) |
6439fc28 AM |
12653 | { |
12654 | while (*++p != '|') | |
7c52e0e8 L |
12655 | if (*p == '}' || *p == '\0') |
12656 | abort (); | |
d1c36125 | 12657 | alt = 1; |
6439fc28 | 12658 | } |
d1c36125 | 12659 | break; |
6439fc28 AM |
12660 | case '|': |
12661 | while (*++p != '}') | |
12662 | { | |
12663 | if (*p == '\0') | |
12664 | abort (); | |
12665 | } | |
12666 | break; | |
12667 | case '}': | |
d1c36125 | 12668 | alt = 0; |
6439fc28 | 12669 | break; |
252b5132 | 12670 | case 'A': |
db6eb5be AM |
12671 | if (intel_syntax) |
12672 | break; | |
7967e09e | 12673 | if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS)) |
252b5132 RH |
12674 | *obufp++ = 'b'; |
12675 | break; | |
12676 | case 'B': | |
4b06377f L |
12677 | if (l == 0 && len == 1) |
12678 | { | |
dc1e8a47 | 12679 | case_B: |
4b06377f L |
12680 | if (intel_syntax) |
12681 | break; | |
12682 | if (sizeflag & SUFFIX_ALWAYS) | |
12683 | *obufp++ = 'b'; | |
12684 | } | |
12685 | else | |
12686 | { | |
12687 | if (l != 1 | |
12688 | || len != 2 | |
12689 | || last[0] != 'L') | |
12690 | { | |
12691 | SAVE_LAST (*p); | |
12692 | break; | |
12693 | } | |
12694 | ||
12695 | if (address_mode == mode_64bit | |
12696 | && !(prefixes & PREFIX_ADDR)) | |
12697 | { | |
12698 | *obufp++ = 'a'; | |
12699 | *obufp++ = 'b'; | |
12700 | *obufp++ = 's'; | |
12701 | } | |
12702 | ||
12703 | goto case_B; | |
12704 | } | |
252b5132 | 12705 | break; |
9306ca4a JB |
12706 | case 'C': |
12707 | if (intel_syntax && !alt) | |
12708 | break; | |
12709 | if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS)) | |
12710 | { | |
12711 | if (sizeflag & DFLAG) | |
12712 | *obufp++ = intel_syntax ? 'd' : 'l'; | |
12713 | else | |
12714 | *obufp++ = intel_syntax ? 'w' : 's'; | |
12715 | used_prefixes |= (prefixes & PREFIX_DATA); | |
12716 | } | |
12717 | break; | |
ed7841b3 JB |
12718 | case 'D': |
12719 | if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS)) | |
12720 | break; | |
161a04f6 | 12721 | USED_REX (REX_W); |
7967e09e | 12722 | if (modrm.mod == 3) |
ed7841b3 | 12723 | { |
161a04f6 | 12724 | if (rex & REX_W) |
ed7841b3 | 12725 | *obufp++ = 'q'; |
ed7841b3 | 12726 | else |
f16cd0d5 L |
12727 | { |
12728 | if (sizeflag & DFLAG) | |
12729 | *obufp++ = intel_syntax ? 'd' : 'l'; | |
12730 | else | |
12731 | *obufp++ = 'w'; | |
12732 | used_prefixes |= (prefixes & PREFIX_DATA); | |
12733 | } | |
ed7841b3 JB |
12734 | } |
12735 | else | |
12736 | *obufp++ = 'w'; | |
12737 | break; | |
252b5132 | 12738 | case 'E': /* For jcxz/jecxz */ |
cb712a9e | 12739 | if (address_mode == mode_64bit) |
c1a64871 JH |
12740 | { |
12741 | if (sizeflag & AFLAG) | |
12742 | *obufp++ = 'r'; | |
12743 | else | |
12744 | *obufp++ = 'e'; | |
12745 | } | |
12746 | else | |
12747 | if (sizeflag & AFLAG) | |
12748 | *obufp++ = 'e'; | |
3ffd33cf AM |
12749 | used_prefixes |= (prefixes & PREFIX_ADDR); |
12750 | break; | |
12751 | case 'F': | |
db6eb5be AM |
12752 | if (intel_syntax) |
12753 | break; | |
e396998b | 12754 | if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS)) |
3ffd33cf AM |
12755 | { |
12756 | if (sizeflag & AFLAG) | |
cb712a9e | 12757 | *obufp++ = address_mode == mode_64bit ? 'q' : 'l'; |
3ffd33cf | 12758 | else |
cb712a9e | 12759 | *obufp++ = address_mode == mode_64bit ? 'l' : 'w'; |
3ffd33cf AM |
12760 | used_prefixes |= (prefixes & PREFIX_ADDR); |
12761 | } | |
252b5132 | 12762 | break; |
52fd6d94 JB |
12763 | case 'G': |
12764 | if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS))) | |
12765 | break; | |
161a04f6 | 12766 | if ((rex & REX_W) || (sizeflag & DFLAG)) |
52fd6d94 JB |
12767 | *obufp++ = 'l'; |
12768 | else | |
12769 | *obufp++ = 'w'; | |
161a04f6 | 12770 | if (!(rex & REX_W)) |
52fd6d94 JB |
12771 | used_prefixes |= (prefixes & PREFIX_DATA); |
12772 | break; | |
5dd0794d | 12773 | case 'H': |
db6eb5be AM |
12774 | if (intel_syntax) |
12775 | break; | |
5dd0794d AM |
12776 | if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS |
12777 | || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS) | |
12778 | { | |
12779 | used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS); | |
12780 | *obufp++ = ','; | |
12781 | *obufp++ = 'p'; | |
12782 | if (prefixes & PREFIX_DS) | |
12783 | *obufp++ = 't'; | |
12784 | else | |
12785 | *obufp++ = 'n'; | |
12786 | } | |
12787 | break; | |
42903f7f L |
12788 | case 'K': |
12789 | USED_REX (REX_W); | |
12790 | if (rex & REX_W) | |
12791 | *obufp++ = 'q'; | |
12792 | else | |
12793 | *obufp++ = 'd'; | |
12794 | break; | |
6dd5059a | 12795 | case 'Z': |
04d824a4 JB |
12796 | if (l != 0 || len != 1) |
12797 | { | |
12798 | if (l != 1 || len != 2 || last[0] != 'X') | |
12799 | { | |
12800 | SAVE_LAST (*p); | |
12801 | break; | |
12802 | } | |
12803 | if (!need_vex || !vex.evex) | |
12804 | abort (); | |
12805 | if (intel_syntax | |
12806 | || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS))) | |
12807 | break; | |
12808 | switch (vex.length) | |
12809 | { | |
12810 | case 128: | |
12811 | *obufp++ = 'x'; | |
12812 | break; | |
12813 | case 256: | |
12814 | *obufp++ = 'y'; | |
12815 | break; | |
12816 | case 512: | |
12817 | *obufp++ = 'z'; | |
12818 | break; | |
12819 | default: | |
12820 | abort (); | |
12821 | } | |
12822 | break; | |
12823 | } | |
6dd5059a L |
12824 | if (intel_syntax) |
12825 | break; | |
12826 | if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS)) | |
12827 | { | |
12828 | *obufp++ = 'q'; | |
12829 | break; | |
12830 | } | |
12831 | /* Fall through. */ | |
98b528ac | 12832 | goto case_L; |
252b5132 | 12833 | case 'L': |
98b528ac L |
12834 | if (l != 0 || len != 1) |
12835 | { | |
12836 | SAVE_LAST (*p); | |
12837 | break; | |
12838 | } | |
dc1e8a47 | 12839 | case_L: |
db6eb5be AM |
12840 | if (intel_syntax) |
12841 | break; | |
252b5132 RH |
12842 | if (sizeflag & SUFFIX_ALWAYS) |
12843 | *obufp++ = 'l'; | |
252b5132 | 12844 | break; |
9d141669 L |
12845 | case 'M': |
12846 | if (intel_mnemonic != cond) | |
12847 | *obufp++ = 'r'; | |
12848 | break; | |
252b5132 RH |
12849 | case 'N': |
12850 | if ((prefixes & PREFIX_FWAIT) == 0) | |
12851 | *obufp++ = 'n'; | |
7d421014 ILT |
12852 | else |
12853 | used_prefixes |= PREFIX_FWAIT; | |
252b5132 | 12854 | break; |
52b15da3 | 12855 | case 'O': |
161a04f6 L |
12856 | USED_REX (REX_W); |
12857 | if (rex & REX_W) | |
6439fc28 | 12858 | *obufp++ = 'o'; |
a35ca55a JB |
12859 | else if (intel_syntax && (sizeflag & DFLAG)) |
12860 | *obufp++ = 'q'; | |
52b15da3 JH |
12861 | else |
12862 | *obufp++ = 'd'; | |
161a04f6 | 12863 | if (!(rex & REX_W)) |
a35ca55a | 12864 | used_prefixes |= (prefixes & PREFIX_DATA); |
52b15da3 | 12865 | break; |
07f5af7d L |
12866 | case '&': |
12867 | if (!intel_syntax | |
12868 | && address_mode == mode_64bit | |
12869 | && isa64 == intel64) | |
12870 | { | |
12871 | *obufp++ = 'q'; | |
12872 | break; | |
12873 | } | |
12874 | /* Fall through. */ | |
6439fc28 | 12875 | case 'T': |
d9e3625e L |
12876 | if (!intel_syntax |
12877 | && address_mode == mode_64bit | |
7bb15c6f | 12878 | && ((sizeflag & DFLAG) || (rex & REX_W))) |
6439fc28 AM |
12879 | { |
12880 | *obufp++ = 'q'; | |
12881 | break; | |
12882 | } | |
6608db57 | 12883 | /* Fall through. */ |
4b4c407a | 12884 | goto case_P; |
252b5132 | 12885 | case 'P': |
4b4c407a | 12886 | if (l == 0 && len == 1) |
d9e3625e | 12887 | { |
dc1e8a47 | 12888 | case_P: |
4b4c407a | 12889 | if (intel_syntax) |
d9e3625e | 12890 | { |
4b4c407a L |
12891 | if ((rex & REX_W) == 0 |
12892 | && (prefixes & PREFIX_DATA)) | |
12893 | { | |
12894 | if ((sizeflag & DFLAG) == 0) | |
12895 | *obufp++ = 'w'; | |
12896 | used_prefixes |= (prefixes & PREFIX_DATA); | |
12897 | } | |
12898 | break; | |
12899 | } | |
12900 | if ((prefixes & PREFIX_DATA) | |
12901 | || (rex & REX_W) | |
12902 | || (sizeflag & SUFFIX_ALWAYS)) | |
12903 | { | |
12904 | USED_REX (REX_W); | |
12905 | if (rex & REX_W) | |
12906 | *obufp++ = 'q'; | |
12907 | else | |
12908 | { | |
12909 | if (sizeflag & DFLAG) | |
12910 | *obufp++ = 'l'; | |
12911 | else | |
12912 | *obufp++ = 'w'; | |
12913 | used_prefixes |= (prefixes & PREFIX_DATA); | |
12914 | } | |
d9e3625e | 12915 | } |
d9e3625e | 12916 | } |
4b4c407a | 12917 | else |
252b5132 | 12918 | { |
4b4c407a L |
12919 | if (l != 1 || len != 2 || last[0] != 'L') |
12920 | { | |
12921 | SAVE_LAST (*p); | |
12922 | break; | |
12923 | } | |
12924 | ||
12925 | if ((prefixes & PREFIX_DATA) | |
12926 | || (rex & REX_W) | |
12927 | || (sizeflag & SUFFIX_ALWAYS)) | |
52b15da3 | 12928 | { |
4b4c407a L |
12929 | USED_REX (REX_W); |
12930 | if (rex & REX_W) | |
12931 | *obufp++ = 'q'; | |
12932 | else | |
12933 | { | |
12934 | if (sizeflag & DFLAG) | |
12935 | *obufp++ = intel_syntax ? 'd' : 'l'; | |
12936 | else | |
12937 | *obufp++ = 'w'; | |
12938 | used_prefixes |= (prefixes & PREFIX_DATA); | |
12939 | } | |
52b15da3 | 12940 | } |
252b5132 RH |
12941 | } |
12942 | break; | |
6439fc28 | 12943 | case 'U': |
db6eb5be AM |
12944 | if (intel_syntax) |
12945 | break; | |
7bb15c6f | 12946 | if (address_mode == mode_64bit |
6c067bbb | 12947 | && ((sizeflag & DFLAG) || (rex & REX_W))) |
6439fc28 | 12948 | { |
7967e09e | 12949 | if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS)) |
1a114b12 | 12950 | *obufp++ = 'q'; |
6439fc28 AM |
12951 | break; |
12952 | } | |
6608db57 | 12953 | /* Fall through. */ |
98b528ac | 12954 | goto case_Q; |
252b5132 | 12955 | case 'Q': |
98b528ac | 12956 | if (l == 0 && len == 1) |
252b5132 | 12957 | { |
dc1e8a47 | 12958 | case_Q: |
98b528ac L |
12959 | if (intel_syntax && !alt) |
12960 | break; | |
12961 | USED_REX (REX_W); | |
12962 | if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS)) | |
52b15da3 | 12963 | { |
98b528ac L |
12964 | if (rex & REX_W) |
12965 | *obufp++ = 'q'; | |
52b15da3 | 12966 | else |
98b528ac L |
12967 | { |
12968 | if (sizeflag & DFLAG) | |
12969 | *obufp++ = intel_syntax ? 'd' : 'l'; | |
12970 | else | |
12971 | *obufp++ = 'w'; | |
f16cd0d5 | 12972 | used_prefixes |= (prefixes & PREFIX_DATA); |
98b528ac | 12973 | } |
52b15da3 | 12974 | } |
98b528ac L |
12975 | } |
12976 | else | |
12977 | { | |
12978 | if (l != 1 || len != 2 || last[0] != 'L') | |
12979 | { | |
12980 | SAVE_LAST (*p); | |
12981 | break; | |
12982 | } | |
589958d6 | 12983 | if ((intel_syntax && need_modrm) |
98b528ac L |
12984 | || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS))) |
12985 | break; | |
12986 | if ((rex & REX_W)) | |
12987 | { | |
12988 | USED_REX (REX_W); | |
12989 | *obufp++ = 'q'; | |
12990 | } | |
589958d6 JB |
12991 | else if((address_mode == mode_64bit && need_modrm) |
12992 | || (sizeflag & SUFFIX_ALWAYS)) | |
12993 | *obufp++ = intel_syntax? 'd' : 'l'; | |
252b5132 RH |
12994 | } |
12995 | break; | |
12996 | case 'R': | |
161a04f6 L |
12997 | USED_REX (REX_W); |
12998 | if (rex & REX_W) | |
a35ca55a JB |
12999 | *obufp++ = 'q'; |
13000 | else if (sizeflag & DFLAG) | |
c608c12e | 13001 | { |
a35ca55a | 13002 | if (intel_syntax) |
c608c12e | 13003 | *obufp++ = 'd'; |
c608c12e | 13004 | else |
a35ca55a | 13005 | *obufp++ = 'l'; |
c608c12e | 13006 | } |
252b5132 | 13007 | else |
a35ca55a JB |
13008 | *obufp++ = 'w'; |
13009 | if (intel_syntax && !p[1] | |
161a04f6 | 13010 | && ((rex & REX_W) || (sizeflag & DFLAG))) |
a35ca55a | 13011 | *obufp++ = 'e'; |
161a04f6 | 13012 | if (!(rex & REX_W)) |
52b15da3 | 13013 | used_prefixes |= (prefixes & PREFIX_DATA); |
252b5132 | 13014 | break; |
1a114b12 | 13015 | case 'V': |
4b06377f | 13016 | if (l == 0 && len == 1) |
1a114b12 | 13017 | { |
4b06377f L |
13018 | if (intel_syntax) |
13019 | break; | |
7bb15c6f | 13020 | if (address_mode == mode_64bit |
6c067bbb | 13021 | && ((sizeflag & DFLAG) || (rex & REX_W))) |
4b06377f L |
13022 | { |
13023 | if (sizeflag & SUFFIX_ALWAYS) | |
13024 | *obufp++ = 'q'; | |
13025 | break; | |
13026 | } | |
13027 | } | |
13028 | else | |
13029 | { | |
13030 | if (l != 1 | |
13031 | || len != 2 | |
13032 | || last[0] != 'L') | |
13033 | { | |
13034 | SAVE_LAST (*p); | |
13035 | break; | |
13036 | } | |
13037 | ||
13038 | if (rex & REX_W) | |
13039 | { | |
13040 | *obufp++ = 'a'; | |
13041 | *obufp++ = 'b'; | |
13042 | *obufp++ = 's'; | |
13043 | } | |
1a114b12 JB |
13044 | } |
13045 | /* Fall through. */ | |
4b06377f | 13046 | goto case_S; |
252b5132 | 13047 | case 'S': |
4b06377f | 13048 | if (l == 0 && len == 1) |
252b5132 | 13049 | { |
dc1e8a47 | 13050 | case_S: |
4b06377f L |
13051 | if (intel_syntax) |
13052 | break; | |
13053 | if (sizeflag & SUFFIX_ALWAYS) | |
52b15da3 | 13054 | { |
4b06377f L |
13055 | if (rex & REX_W) |
13056 | *obufp++ = 'q'; | |
52b15da3 | 13057 | else |
4b06377f L |
13058 | { |
13059 | if (sizeflag & DFLAG) | |
13060 | *obufp++ = 'l'; | |
13061 | else | |
13062 | *obufp++ = 'w'; | |
13063 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13064 | } | |
13065 | } | |
13066 | } | |
13067 | else | |
13068 | { | |
13069 | if (l != 1 | |
13070 | || len != 2 | |
13071 | || last[0] != 'L') | |
13072 | { | |
13073 | SAVE_LAST (*p); | |
13074 | break; | |
52b15da3 | 13075 | } |
4b06377f L |
13076 | |
13077 | if (address_mode == mode_64bit | |
13078 | && !(prefixes & PREFIX_ADDR)) | |
13079 | { | |
13080 | *obufp++ = 'a'; | |
13081 | *obufp++ = 'b'; | |
13082 | *obufp++ = 's'; | |
13083 | } | |
13084 | ||
13085 | goto case_S; | |
252b5132 | 13086 | } |
252b5132 | 13087 | break; |
041bd2e0 | 13088 | case 'X': |
c0f3af97 L |
13089 | if (l != 0 || len != 1) |
13090 | { | |
13091 | SAVE_LAST (*p); | |
13092 | break; | |
13093 | } | |
bf926894 JB |
13094 | if (need_vex |
13095 | ? vex.prefix == DATA_PREFIX_OPCODE | |
13096 | : prefixes & PREFIX_DATA) | |
c0f3af97 | 13097 | { |
bf926894 JB |
13098 | *obufp++ = 'd'; |
13099 | used_prefixes |= PREFIX_DATA; | |
c0f3af97 | 13100 | } |
041bd2e0 | 13101 | else |
bf926894 | 13102 | *obufp++ = 's'; |
041bd2e0 | 13103 | break; |
76f227a5 | 13104 | case 'Y': |
c0f3af97 | 13105 | if (l == 0 && len == 1) |
9646c87b | 13106 | abort (); |
c0f3af97 L |
13107 | else |
13108 | { | |
13109 | if (l != 1 || len != 2 || last[0] != 'X') | |
13110 | { | |
13111 | SAVE_LAST (*p); | |
13112 | break; | |
13113 | } | |
13114 | if (!need_vex) | |
13115 | abort (); | |
13116 | if (intel_syntax | |
04d824a4 | 13117 | || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS))) |
c0f3af97 L |
13118 | break; |
13119 | switch (vex.length) | |
13120 | { | |
13121 | case 128: | |
13122 | *obufp++ = 'x'; | |
13123 | break; | |
13124 | case 256: | |
13125 | *obufp++ = 'y'; | |
13126 | break; | |
04d824a4 JB |
13127 | case 512: |
13128 | if (!vex.evex) | |
c0f3af97 | 13129 | default: |
04d824a4 | 13130 | abort (); |
c0f3af97 | 13131 | } |
76f227a5 JH |
13132 | } |
13133 | break; | |
252b5132 | 13134 | case 'W': |
0bfee649 | 13135 | if (l == 0 && len == 1) |
a35ca55a | 13136 | { |
0bfee649 L |
13137 | /* operand size flag for cwtl, cbtw */ |
13138 | USED_REX (REX_W); | |
13139 | if (rex & REX_W) | |
13140 | { | |
13141 | if (intel_syntax) | |
13142 | *obufp++ = 'd'; | |
13143 | else | |
13144 | *obufp++ = 'l'; | |
13145 | } | |
13146 | else if (sizeflag & DFLAG) | |
13147 | *obufp++ = 'w'; | |
a35ca55a | 13148 | else |
0bfee649 L |
13149 | *obufp++ = 'b'; |
13150 | if (!(rex & REX_W)) | |
13151 | used_prefixes |= (prefixes & PREFIX_DATA); | |
a35ca55a | 13152 | } |
252b5132 | 13153 | else |
0bfee649 | 13154 | { |
6c30d220 L |
13155 | if (l != 1 |
13156 | || len != 2 | |
13157 | || (last[0] != 'X' | |
13158 | && last[0] != 'L')) | |
0bfee649 L |
13159 | { |
13160 | SAVE_LAST (*p); | |
13161 | break; | |
13162 | } | |
13163 | if (!need_vex) | |
13164 | abort (); | |
6c30d220 L |
13165 | if (last[0] == 'X') |
13166 | *obufp++ = vex.w ? 'd': 's'; | |
13167 | else | |
13168 | *obufp++ = vex.w ? 'q': 'd'; | |
0bfee649 | 13169 | } |
252b5132 | 13170 | break; |
a72d2af2 L |
13171 | case '^': |
13172 | if (intel_syntax) | |
13173 | break; | |
5990e377 JB |
13174 | if (isa64 == intel64 && (rex & REX_W)) |
13175 | { | |
13176 | USED_REX (REX_W); | |
13177 | *obufp++ = 'q'; | |
13178 | break; | |
13179 | } | |
a72d2af2 L |
13180 | if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS)) |
13181 | { | |
13182 | if (sizeflag & DFLAG) | |
13183 | *obufp++ = 'l'; | |
13184 | else | |
13185 | *obufp++ = 'w'; | |
13186 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13187 | } | |
13188 | break; | |
5db04b09 L |
13189 | case '@': |
13190 | if (intel_syntax) | |
13191 | break; | |
13192 | if (address_mode == mode_64bit | |
13193 | && (isa64 == intel64 | |
13194 | || ((sizeflag & DFLAG) || (rex & REX_W)))) | |
13195 | *obufp++ = 'q'; | |
13196 | else if ((prefixes & PREFIX_DATA)) | |
13197 | { | |
13198 | if (!(sizeflag & DFLAG)) | |
13199 | *obufp++ = 'w'; | |
13200 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13201 | } | |
13202 | break; | |
252b5132 RH |
13203 | } |
13204 | } | |
13205 | *obufp = 0; | |
ea397f5b | 13206 | mnemonicendp = obufp; |
6439fc28 | 13207 | return 0; |
252b5132 RH |
13208 | } |
13209 | ||
13210 | static void | |
26ca5450 | 13211 | oappend (const char *s) |
252b5132 | 13212 | { |
ea397f5b | 13213 | obufp = stpcpy (obufp, s); |
252b5132 RH |
13214 | } |
13215 | ||
13216 | static void | |
26ca5450 | 13217 | append_seg (void) |
252b5132 | 13218 | { |
285ca992 L |
13219 | /* Only print the active segment register. */ |
13220 | if (!active_seg_prefix) | |
13221 | return; | |
13222 | ||
13223 | used_prefixes |= active_seg_prefix; | |
13224 | switch (active_seg_prefix) | |
7d421014 | 13225 | { |
285ca992 | 13226 | case PREFIX_CS: |
9ce09ba2 | 13227 | oappend_maybe_intel ("%cs:"); |
285ca992 L |
13228 | break; |
13229 | case PREFIX_DS: | |
9ce09ba2 | 13230 | oappend_maybe_intel ("%ds:"); |
285ca992 L |
13231 | break; |
13232 | case PREFIX_SS: | |
9ce09ba2 | 13233 | oappend_maybe_intel ("%ss:"); |
285ca992 L |
13234 | break; |
13235 | case PREFIX_ES: | |
9ce09ba2 | 13236 | oappend_maybe_intel ("%es:"); |
285ca992 L |
13237 | break; |
13238 | case PREFIX_FS: | |
9ce09ba2 | 13239 | oappend_maybe_intel ("%fs:"); |
285ca992 L |
13240 | break; |
13241 | case PREFIX_GS: | |
9ce09ba2 | 13242 | oappend_maybe_intel ("%gs:"); |
285ca992 L |
13243 | break; |
13244 | default: | |
13245 | break; | |
7d421014 | 13246 | } |
252b5132 RH |
13247 | } |
13248 | ||
13249 | static void | |
26ca5450 | 13250 | OP_indirE (int bytemode, int sizeflag) |
252b5132 RH |
13251 | { |
13252 | if (!intel_syntax) | |
13253 | oappend ("*"); | |
13254 | OP_E (bytemode, sizeflag); | |
13255 | } | |
13256 | ||
52b15da3 | 13257 | static void |
26ca5450 | 13258 | print_operand_value (char *buf, int hex, bfd_vma disp) |
52b15da3 | 13259 | { |
cb712a9e | 13260 | if (address_mode == mode_64bit) |
52b15da3 JH |
13261 | { |
13262 | if (hex) | |
13263 | { | |
13264 | char tmp[30]; | |
13265 | int i; | |
13266 | buf[0] = '0'; | |
13267 | buf[1] = 'x'; | |
13268 | sprintf_vma (tmp, disp); | |
6608db57 | 13269 | for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++); |
52b15da3 JH |
13270 | strcpy (buf + 2, tmp + i); |
13271 | } | |
13272 | else | |
13273 | { | |
13274 | bfd_signed_vma v = disp; | |
13275 | char tmp[30]; | |
13276 | int i; | |
13277 | if (v < 0) | |
13278 | { | |
13279 | *(buf++) = '-'; | |
13280 | v = -disp; | |
6608db57 | 13281 | /* Check for possible overflow on 0x8000000000000000. */ |
52b15da3 JH |
13282 | if (v < 0) |
13283 | { | |
13284 | strcpy (buf, "9223372036854775808"); | |
13285 | return; | |
13286 | } | |
13287 | } | |
13288 | if (!v) | |
13289 | { | |
13290 | strcpy (buf, "0"); | |
13291 | return; | |
13292 | } | |
13293 | ||
13294 | i = 0; | |
13295 | tmp[29] = 0; | |
13296 | while (v) | |
13297 | { | |
6608db57 | 13298 | tmp[28 - i] = (v % 10) + '0'; |
52b15da3 JH |
13299 | v /= 10; |
13300 | i++; | |
13301 | } | |
13302 | strcpy (buf, tmp + 29 - i); | |
13303 | } | |
13304 | } | |
13305 | else | |
13306 | { | |
13307 | if (hex) | |
13308 | sprintf (buf, "0x%x", (unsigned int) disp); | |
13309 | else | |
13310 | sprintf (buf, "%d", (int) disp); | |
13311 | } | |
13312 | } | |
13313 | ||
5d669648 L |
13314 | /* Put DISP in BUF as signed hex number. */ |
13315 | ||
13316 | static void | |
13317 | print_displacement (char *buf, bfd_vma disp) | |
13318 | { | |
13319 | bfd_signed_vma val = disp; | |
13320 | char tmp[30]; | |
13321 | int i, j = 0; | |
13322 | ||
13323 | if (val < 0) | |
13324 | { | |
13325 | buf[j++] = '-'; | |
13326 | val = -disp; | |
13327 | ||
13328 | /* Check for possible overflow. */ | |
13329 | if (val < 0) | |
13330 | { | |
13331 | switch (address_mode) | |
13332 | { | |
13333 | case mode_64bit: | |
13334 | strcpy (buf + j, "0x8000000000000000"); | |
13335 | break; | |
13336 | case mode_32bit: | |
13337 | strcpy (buf + j, "0x80000000"); | |
13338 | break; | |
13339 | case mode_16bit: | |
13340 | strcpy (buf + j, "0x8000"); | |
13341 | break; | |
13342 | } | |
13343 | return; | |
13344 | } | |
13345 | } | |
13346 | ||
13347 | buf[j++] = '0'; | |
13348 | buf[j++] = 'x'; | |
13349 | ||
0af1713e | 13350 | sprintf_vma (tmp, (bfd_vma) val); |
5d669648 L |
13351 | for (i = 0; tmp[i] == '0'; i++) |
13352 | continue; | |
13353 | if (tmp[i] == '\0') | |
13354 | i--; | |
13355 | strcpy (buf + j, tmp + i); | |
13356 | } | |
13357 | ||
3f31e633 JB |
13358 | static void |
13359 | intel_operand_size (int bytemode, int sizeflag) | |
13360 | { | |
43234a1e L |
13361 | if (vex.evex |
13362 | && vex.b | |
13363 | && (bytemode == x_mode | |
13364 | || bytemode == evex_half_bcst_xmmq_mode)) | |
13365 | { | |
13366 | if (vex.w) | |
13367 | oappend ("QWORD PTR "); | |
13368 | else | |
13369 | oappend ("DWORD PTR "); | |
13370 | return; | |
13371 | } | |
3f31e633 JB |
13372 | switch (bytemode) |
13373 | { | |
13374 | case b_mode: | |
b6169b20 | 13375 | case b_swap_mode: |
42903f7f | 13376 | case dqb_mode: |
1ba585e8 | 13377 | case db_mode: |
3f31e633 JB |
13378 | oappend ("BYTE PTR "); |
13379 | break; | |
13380 | case w_mode: | |
1ba585e8 | 13381 | case dw_mode: |
3f31e633 JB |
13382 | case dqw_mode: |
13383 | oappend ("WORD PTR "); | |
13384 | break; | |
07f5af7d L |
13385 | case indir_v_mode: |
13386 | if (address_mode == mode_64bit && isa64 == intel64) | |
13387 | { | |
13388 | oappend ("QWORD PTR "); | |
13389 | break; | |
13390 | } | |
1a0670f3 | 13391 | /* Fall through. */ |
1a114b12 | 13392 | case stack_v_mode: |
7bb15c6f | 13393 | if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W))) |
3f31e633 JB |
13394 | { |
13395 | oappend ("QWORD PTR "); | |
3f31e633 JB |
13396 | break; |
13397 | } | |
1a0670f3 | 13398 | /* Fall through. */ |
3f31e633 | 13399 | case v_mode: |
b6169b20 | 13400 | case v_swap_mode: |
3f31e633 | 13401 | case dq_mode: |
161a04f6 L |
13402 | USED_REX (REX_W); |
13403 | if (rex & REX_W) | |
3f31e633 | 13404 | oappend ("QWORD PTR "); |
3f31e633 | 13405 | else |
f16cd0d5 L |
13406 | { |
13407 | if ((sizeflag & DFLAG) || bytemode == dq_mode) | |
13408 | oappend ("DWORD PTR "); | |
13409 | else | |
13410 | oappend ("WORD PTR "); | |
13411 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13412 | } | |
3f31e633 | 13413 | break; |
52fd6d94 | 13414 | case z_mode: |
161a04f6 | 13415 | if ((rex & REX_W) || (sizeflag & DFLAG)) |
52fd6d94 JB |
13416 | *obufp++ = 'D'; |
13417 | oappend ("WORD PTR "); | |
161a04f6 | 13418 | if (!(rex & REX_W)) |
52fd6d94 JB |
13419 | used_prefixes |= (prefixes & PREFIX_DATA); |
13420 | break; | |
34b772a6 JB |
13421 | case a_mode: |
13422 | if (sizeflag & DFLAG) | |
13423 | oappend ("QWORD PTR "); | |
13424 | else | |
13425 | oappend ("DWORD PTR "); | |
13426 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13427 | break; | |
bc31405e L |
13428 | case movsxd_mode: |
13429 | if (!(sizeflag & DFLAG) && isa64 == intel64) | |
13430 | oappend ("WORD PTR "); | |
13431 | else | |
13432 | oappend ("DWORD PTR "); | |
13433 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13434 | break; | |
3f31e633 | 13435 | case d_mode: |
539f890d | 13436 | case d_scalar_swap_mode: |
fa99fab2 | 13437 | case d_swap_mode: |
42903f7f | 13438 | case dqd_mode: |
3f31e633 JB |
13439 | oappend ("DWORD PTR "); |
13440 | break; | |
13441 | case q_mode: | |
539f890d | 13442 | case q_scalar_swap_mode: |
b6169b20 | 13443 | case q_swap_mode: |
3f31e633 JB |
13444 | oappend ("QWORD PTR "); |
13445 | break; | |
13446 | case m_mode: | |
cb712a9e | 13447 | if (address_mode == mode_64bit) |
3f31e633 JB |
13448 | oappend ("QWORD PTR "); |
13449 | else | |
13450 | oappend ("DWORD PTR "); | |
13451 | break; | |
13452 | case f_mode: | |
13453 | if (sizeflag & DFLAG) | |
13454 | oappend ("FWORD PTR "); | |
13455 | else | |
13456 | oappend ("DWORD PTR "); | |
13457 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13458 | break; | |
13459 | case t_mode: | |
13460 | oappend ("TBYTE PTR "); | |
13461 | break; | |
13462 | case x_mode: | |
b6169b20 | 13463 | case x_swap_mode: |
43234a1e L |
13464 | case evex_x_gscat_mode: |
13465 | case evex_x_nobcst_mode: | |
53467f57 IT |
13466 | case b_scalar_mode: |
13467 | case w_scalar_mode: | |
c0f3af97 L |
13468 | if (need_vex) |
13469 | { | |
13470 | switch (vex.length) | |
13471 | { | |
13472 | case 128: | |
13473 | oappend ("XMMWORD PTR "); | |
13474 | break; | |
13475 | case 256: | |
13476 | oappend ("YMMWORD PTR "); | |
13477 | break; | |
43234a1e L |
13478 | case 512: |
13479 | oappend ("ZMMWORD PTR "); | |
13480 | break; | |
c0f3af97 L |
13481 | default: |
13482 | abort (); | |
13483 | } | |
13484 | } | |
13485 | else | |
13486 | oappend ("XMMWORD PTR "); | |
13487 | break; | |
13488 | case xmm_mode: | |
3f31e633 JB |
13489 | oappend ("XMMWORD PTR "); |
13490 | break; | |
43234a1e L |
13491 | case ymm_mode: |
13492 | oappend ("YMMWORD PTR "); | |
13493 | break; | |
c0f3af97 | 13494 | case xmmq_mode: |
43234a1e | 13495 | case evex_half_bcst_xmmq_mode: |
c0f3af97 L |
13496 | if (!need_vex) |
13497 | abort (); | |
13498 | ||
13499 | switch (vex.length) | |
13500 | { | |
13501 | case 128: | |
13502 | oappend ("QWORD PTR "); | |
13503 | break; | |
13504 | case 256: | |
13505 | oappend ("XMMWORD PTR "); | |
13506 | break; | |
43234a1e L |
13507 | case 512: |
13508 | oappend ("YMMWORD PTR "); | |
13509 | break; | |
c0f3af97 L |
13510 | default: |
13511 | abort (); | |
13512 | } | |
13513 | break; | |
6c30d220 L |
13514 | case xmm_mb_mode: |
13515 | if (!need_vex) | |
13516 | abort (); | |
13517 | ||
13518 | switch (vex.length) | |
13519 | { | |
13520 | case 128: | |
13521 | case 256: | |
43234a1e | 13522 | case 512: |
6c30d220 L |
13523 | oappend ("BYTE PTR "); |
13524 | break; | |
13525 | default: | |
13526 | abort (); | |
13527 | } | |
13528 | break; | |
13529 | case xmm_mw_mode: | |
13530 | if (!need_vex) | |
13531 | abort (); | |
13532 | ||
13533 | switch (vex.length) | |
13534 | { | |
13535 | case 128: | |
13536 | case 256: | |
43234a1e | 13537 | case 512: |
6c30d220 L |
13538 | oappend ("WORD PTR "); |
13539 | break; | |
13540 | default: | |
13541 | abort (); | |
13542 | } | |
13543 | break; | |
13544 | case xmm_md_mode: | |
13545 | if (!need_vex) | |
13546 | abort (); | |
13547 | ||
13548 | switch (vex.length) | |
13549 | { | |
13550 | case 128: | |
13551 | case 256: | |
43234a1e | 13552 | case 512: |
6c30d220 L |
13553 | oappend ("DWORD PTR "); |
13554 | break; | |
13555 | default: | |
13556 | abort (); | |
13557 | } | |
13558 | break; | |
13559 | case xmm_mq_mode: | |
13560 | if (!need_vex) | |
13561 | abort (); | |
13562 | ||
13563 | switch (vex.length) | |
13564 | { | |
13565 | case 128: | |
13566 | case 256: | |
43234a1e | 13567 | case 512: |
6c30d220 L |
13568 | oappend ("QWORD PTR "); |
13569 | break; | |
13570 | default: | |
13571 | abort (); | |
13572 | } | |
13573 | break; | |
13574 | case xmmdw_mode: | |
13575 | if (!need_vex) | |
13576 | abort (); | |
13577 | ||
13578 | switch (vex.length) | |
13579 | { | |
13580 | case 128: | |
13581 | oappend ("WORD PTR "); | |
13582 | break; | |
13583 | case 256: | |
13584 | oappend ("DWORD PTR "); | |
13585 | break; | |
43234a1e L |
13586 | case 512: |
13587 | oappend ("QWORD PTR "); | |
13588 | break; | |
6c30d220 L |
13589 | default: |
13590 | abort (); | |
13591 | } | |
13592 | break; | |
13593 | case xmmqd_mode: | |
13594 | if (!need_vex) | |
13595 | abort (); | |
13596 | ||
13597 | switch (vex.length) | |
13598 | { | |
13599 | case 128: | |
13600 | oappend ("DWORD PTR "); | |
13601 | break; | |
13602 | case 256: | |
13603 | oappend ("QWORD PTR "); | |
13604 | break; | |
43234a1e L |
13605 | case 512: |
13606 | oappend ("XMMWORD PTR "); | |
13607 | break; | |
6c30d220 L |
13608 | default: |
13609 | abort (); | |
13610 | } | |
13611 | break; | |
c0f3af97 L |
13612 | case ymmq_mode: |
13613 | if (!need_vex) | |
13614 | abort (); | |
13615 | ||
13616 | switch (vex.length) | |
13617 | { | |
13618 | case 128: | |
13619 | oappend ("QWORD PTR "); | |
13620 | break; | |
13621 | case 256: | |
13622 | oappend ("YMMWORD PTR "); | |
13623 | break; | |
43234a1e L |
13624 | case 512: |
13625 | oappend ("ZMMWORD PTR "); | |
13626 | break; | |
c0f3af97 L |
13627 | default: |
13628 | abort (); | |
13629 | } | |
13630 | break; | |
6c30d220 L |
13631 | case ymmxmm_mode: |
13632 | if (!need_vex) | |
13633 | abort (); | |
13634 | ||
13635 | switch (vex.length) | |
13636 | { | |
13637 | case 128: | |
13638 | case 256: | |
13639 | oappend ("XMMWORD PTR "); | |
13640 | break; | |
13641 | default: | |
13642 | abort (); | |
13643 | } | |
13644 | break; | |
fb9c77c7 L |
13645 | case o_mode: |
13646 | oappend ("OWORD PTR "); | |
13647 | break; | |
1c480963 | 13648 | case vex_scalar_w_dq_mode: |
0bfee649 L |
13649 | if (!need_vex) |
13650 | abort (); | |
13651 | ||
13652 | if (vex.w) | |
13653 | oappend ("QWORD PTR "); | |
13654 | else | |
13655 | oappend ("DWORD PTR "); | |
13656 | break; | |
43234a1e L |
13657 | case vex_vsib_d_w_dq_mode: |
13658 | case vex_vsib_q_w_dq_mode: | |
13659 | if (!need_vex) | |
13660 | abort (); | |
13661 | ||
13662 | if (!vex.evex) | |
13663 | { | |
13664 | if (vex.w) | |
13665 | oappend ("QWORD PTR "); | |
13666 | else | |
13667 | oappend ("DWORD PTR "); | |
13668 | } | |
13669 | else | |
13670 | { | |
b28d1bda IT |
13671 | switch (vex.length) |
13672 | { | |
13673 | case 128: | |
13674 | oappend ("XMMWORD PTR "); | |
13675 | break; | |
13676 | case 256: | |
13677 | oappend ("YMMWORD PTR "); | |
13678 | break; | |
13679 | case 512: | |
13680 | oappend ("ZMMWORD PTR "); | |
13681 | break; | |
13682 | default: | |
13683 | abort (); | |
13684 | } | |
43234a1e L |
13685 | } |
13686 | break; | |
5fc35d96 IT |
13687 | case vex_vsib_q_w_d_mode: |
13688 | case vex_vsib_d_w_d_mode: | |
b28d1bda | 13689 | if (!need_vex || !vex.evex) |
5fc35d96 IT |
13690 | abort (); |
13691 | ||
b28d1bda IT |
13692 | switch (vex.length) |
13693 | { | |
13694 | case 128: | |
13695 | oappend ("QWORD PTR "); | |
13696 | break; | |
13697 | case 256: | |
13698 | oappend ("XMMWORD PTR "); | |
13699 | break; | |
13700 | case 512: | |
13701 | oappend ("YMMWORD PTR "); | |
13702 | break; | |
13703 | default: | |
13704 | abort (); | |
13705 | } | |
5fc35d96 IT |
13706 | |
13707 | break; | |
1ba585e8 IT |
13708 | case mask_bd_mode: |
13709 | if (!need_vex || vex.length != 128) | |
13710 | abort (); | |
13711 | if (vex.w) | |
13712 | oappend ("DWORD PTR "); | |
13713 | else | |
13714 | oappend ("BYTE PTR "); | |
13715 | break; | |
43234a1e L |
13716 | case mask_mode: |
13717 | if (!need_vex) | |
13718 | abort (); | |
1ba585e8 IT |
13719 | if (vex.w) |
13720 | oappend ("QWORD PTR "); | |
13721 | else | |
13722 | oappend ("WORD PTR "); | |
43234a1e | 13723 | break; |
6c75cc62 | 13724 | case v_bnd_mode: |
d276ec69 | 13725 | case v_bndmk_mode: |
3f31e633 JB |
13726 | default: |
13727 | break; | |
13728 | } | |
13729 | } | |
13730 | ||
252b5132 | 13731 | static void |
c0f3af97 | 13732 | OP_E_register (int bytemode, int sizeflag) |
252b5132 | 13733 | { |
c0f3af97 L |
13734 | int reg = modrm.rm; |
13735 | const char **names; | |
252b5132 | 13736 | |
c0f3af97 L |
13737 | USED_REX (REX_B); |
13738 | if ((rex & REX_B)) | |
13739 | reg += 8; | |
252b5132 | 13740 | |
b6169b20 | 13741 | if ((sizeflag & SUFFIX_ALWAYS) |
1ba585e8 | 13742 | && (bytemode == b_swap_mode |
9f79e886 | 13743 | || bytemode == bnd_swap_mode |
60227d64 | 13744 | || bytemode == v_swap_mode)) |
b6169b20 L |
13745 | swap_operand (); |
13746 | ||
c0f3af97 | 13747 | switch (bytemode) |
252b5132 | 13748 | { |
c0f3af97 | 13749 | case b_mode: |
b6169b20 | 13750 | case b_swap_mode: |
c0f3af97 L |
13751 | USED_REX (0); |
13752 | if (rex) | |
13753 | names = names8rex; | |
13754 | else | |
13755 | names = names8; | |
13756 | break; | |
13757 | case w_mode: | |
13758 | names = names16; | |
13759 | break; | |
13760 | case d_mode: | |
1ba585e8 IT |
13761 | case dw_mode: |
13762 | case db_mode: | |
c0f3af97 L |
13763 | names = names32; |
13764 | break; | |
13765 | case q_mode: | |
13766 | names = names64; | |
13767 | break; | |
13768 | case m_mode: | |
6c75cc62 | 13769 | case v_bnd_mode: |
c0f3af97 L |
13770 | names = address_mode == mode_64bit ? names64 : names32; |
13771 | break; | |
7e8b059b | 13772 | case bnd_mode: |
9f79e886 | 13773 | case bnd_swap_mode: |
0d96e4df L |
13774 | if (reg > 0x3) |
13775 | { | |
13776 | oappend ("(bad)"); | |
13777 | return; | |
13778 | } | |
7e8b059b L |
13779 | names = names_bnd; |
13780 | break; | |
07f5af7d L |
13781 | case indir_v_mode: |
13782 | if (address_mode == mode_64bit && isa64 == intel64) | |
13783 | { | |
13784 | names = names64; | |
13785 | break; | |
13786 | } | |
1a0670f3 | 13787 | /* Fall through. */ |
c0f3af97 | 13788 | case stack_v_mode: |
7bb15c6f | 13789 | if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W))) |
252b5132 | 13790 | { |
c0f3af97 | 13791 | names = names64; |
252b5132 | 13792 | break; |
252b5132 | 13793 | } |
c0f3af97 | 13794 | bytemode = v_mode; |
1a0670f3 | 13795 | /* Fall through. */ |
c0f3af97 | 13796 | case v_mode: |
b6169b20 | 13797 | case v_swap_mode: |
c0f3af97 L |
13798 | case dq_mode: |
13799 | case dqb_mode: | |
13800 | case dqd_mode: | |
13801 | case dqw_mode: | |
13802 | USED_REX (REX_W); | |
13803 | if (rex & REX_W) | |
13804 | names = names64; | |
c0f3af97 | 13805 | else |
f16cd0d5 | 13806 | { |
7bb15c6f | 13807 | if ((sizeflag & DFLAG) |
f16cd0d5 L |
13808 | || (bytemode != v_mode |
13809 | && bytemode != v_swap_mode)) | |
13810 | names = names32; | |
13811 | else | |
13812 | names = names16; | |
13813 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13814 | } | |
c0f3af97 | 13815 | break; |
bc31405e L |
13816 | case movsxd_mode: |
13817 | if (!(sizeflag & DFLAG) && isa64 == intel64) | |
13818 | names = names16; | |
13819 | else | |
13820 | names = names32; | |
13821 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13822 | break; | |
de89d0a3 IT |
13823 | case va_mode: |
13824 | names = (address_mode == mode_64bit | |
13825 | ? names64 : names32); | |
13826 | if (!(prefixes & PREFIX_ADDR)) | |
aa178437 IT |
13827 | names = (address_mode == mode_16bit |
13828 | ? names16 : names); | |
de89d0a3 IT |
13829 | else |
13830 | { | |
13831 | /* Remove "addr16/addr32". */ | |
13832 | all_prefixes[last_addr_prefix] = 0; | |
13833 | names = (address_mode != mode_32bit | |
13834 | ? names32 : names16); | |
13835 | used_prefixes |= PREFIX_ADDR; | |
13836 | } | |
13837 | break; | |
1ba585e8 | 13838 | case mask_bd_mode: |
43234a1e | 13839 | case mask_mode: |
9889cbb1 L |
13840 | if (reg > 0x7) |
13841 | { | |
13842 | oappend ("(bad)"); | |
13843 | return; | |
13844 | } | |
43234a1e L |
13845 | names = names_mask; |
13846 | break; | |
c0f3af97 L |
13847 | case 0: |
13848 | return; | |
13849 | default: | |
13850 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
252b5132 RH |
13851 | return; |
13852 | } | |
c0f3af97 L |
13853 | oappend (names[reg]); |
13854 | } | |
13855 | ||
13856 | static void | |
c1e679ec | 13857 | OP_E_memory (int bytemode, int sizeflag) |
c0f3af97 L |
13858 | { |
13859 | bfd_vma disp = 0; | |
13860 | int add = (rex & REX_B) ? 8 : 0; | |
13861 | int riprel = 0; | |
43234a1e L |
13862 | int shift; |
13863 | ||
13864 | if (vex.evex) | |
13865 | { | |
13866 | /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0. */ | |
13867 | if (vex.b | |
13868 | && bytemode != x_mode | |
90a915bf | 13869 | && bytemode != xmmq_mode |
43234a1e L |
13870 | && bytemode != evex_half_bcst_xmmq_mode) |
13871 | { | |
13872 | BadOp (); | |
13873 | return; | |
13874 | } | |
13875 | switch (bytemode) | |
13876 | { | |
1ba585e8 IT |
13877 | case dqw_mode: |
13878 | case dw_mode: | |
1ba585e8 IT |
13879 | shift = 1; |
13880 | break; | |
13881 | case dqb_mode: | |
13882 | case db_mode: | |
13883 | shift = 0; | |
13884 | break; | |
b50c9f31 JB |
13885 | case dq_mode: |
13886 | if (address_mode != mode_64bit) | |
13887 | { | |
13888 | shift = 2; | |
13889 | break; | |
13890 | } | |
13891 | /* fall through */ | |
4102be5c | 13892 | case vex_scalar_w_dq_mode: |
43234a1e | 13893 | case vex_vsib_d_w_dq_mode: |
5fc35d96 | 13894 | case vex_vsib_d_w_d_mode: |
eaa9d1ad | 13895 | case vex_vsib_q_w_dq_mode: |
5fc35d96 | 13896 | case vex_vsib_q_w_d_mode: |
43234a1e | 13897 | case evex_x_gscat_mode: |
43234a1e L |
13898 | shift = vex.w ? 3 : 2; |
13899 | break; | |
43234a1e L |
13900 | case x_mode: |
13901 | case evex_half_bcst_xmmq_mode: | |
90a915bf | 13902 | case xmmq_mode: |
43234a1e L |
13903 | if (vex.b) |
13904 | { | |
13905 | shift = vex.w ? 3 : 2; | |
13906 | break; | |
13907 | } | |
1a0670f3 | 13908 | /* Fall through. */ |
43234a1e L |
13909 | case xmmqd_mode: |
13910 | case xmmdw_mode: | |
43234a1e L |
13911 | case ymmq_mode: |
13912 | case evex_x_nobcst_mode: | |
13913 | case x_swap_mode: | |
13914 | switch (vex.length) | |
13915 | { | |
13916 | case 128: | |
13917 | shift = 4; | |
13918 | break; | |
13919 | case 256: | |
13920 | shift = 5; | |
13921 | break; | |
13922 | case 512: | |
13923 | shift = 6; | |
13924 | break; | |
13925 | default: | |
13926 | abort (); | |
13927 | } | |
13928 | break; | |
13929 | case ymm_mode: | |
13930 | shift = 5; | |
13931 | break; | |
13932 | case xmm_mode: | |
13933 | shift = 4; | |
13934 | break; | |
13935 | case xmm_mq_mode: | |
13936 | case q_mode: | |
43234a1e L |
13937 | case q_swap_mode: |
13938 | case q_scalar_swap_mode: | |
13939 | shift = 3; | |
13940 | break; | |
13941 | case dqd_mode: | |
13942 | case xmm_md_mode: | |
13943 | case d_mode: | |
43234a1e L |
13944 | case d_swap_mode: |
13945 | case d_scalar_swap_mode: | |
13946 | shift = 2; | |
13947 | break; | |
5074ad8a | 13948 | case w_scalar_mode: |
43234a1e L |
13949 | case xmm_mw_mode: |
13950 | shift = 1; | |
13951 | break; | |
5074ad8a | 13952 | case b_scalar_mode: |
43234a1e L |
13953 | case xmm_mb_mode: |
13954 | shift = 0; | |
13955 | break; | |
13956 | default: | |
13957 | abort (); | |
13958 | } | |
13959 | /* Make necessary corrections to shift for modes that need it. | |
13960 | For these modes we currently have shift 4, 5 or 6 depending on | |
13961 | vex.length (it corresponds to xmmword, ymmword or zmmword | |
13962 | operand). We might want to make it 3, 4 or 5 (e.g. for | |
13963 | xmmq_mode). In case of broadcast enabled the corrections | |
13964 | aren't needed, as element size is always 32 or 64 bits. */ | |
90a915bf IT |
13965 | if (!vex.b |
13966 | && (bytemode == xmmq_mode | |
13967 | || bytemode == evex_half_bcst_xmmq_mode)) | |
43234a1e L |
13968 | shift -= 1; |
13969 | else if (bytemode == xmmqd_mode) | |
13970 | shift -= 2; | |
13971 | else if (bytemode == xmmdw_mode) | |
13972 | shift -= 3; | |
b28d1bda IT |
13973 | else if (bytemode == ymmq_mode && vex.length == 128) |
13974 | shift -= 1; | |
43234a1e L |
13975 | } |
13976 | else | |
13977 | shift = 0; | |
252b5132 | 13978 | |
c0f3af97 | 13979 | USED_REX (REX_B); |
3f31e633 JB |
13980 | if (intel_syntax) |
13981 | intel_operand_size (bytemode, sizeflag); | |
252b5132 RH |
13982 | append_seg (); |
13983 | ||
5d669648 | 13984 | if ((sizeflag & AFLAG) || address_mode == mode_64bit) |
252b5132 | 13985 | { |
5d669648 L |
13986 | /* 32/64 bit address mode */ |
13987 | int havedisp; | |
252b5132 RH |
13988 | int havesib; |
13989 | int havebase; | |
0f7da397 | 13990 | int haveindex; |
20afcfb7 | 13991 | int needindex; |
1bc60e56 | 13992 | int needaddr32; |
82c18208 | 13993 | int base, rbase; |
91d6fa6a | 13994 | int vindex = 0; |
252b5132 | 13995 | int scale = 0; |
7e8b059b L |
13996 | int addr32flag = !((sizeflag & AFLAG) |
13997 | || bytemode == v_bnd_mode | |
d276ec69 | 13998 | || bytemode == v_bndmk_mode |
9f79e886 JB |
13999 | || bytemode == bnd_mode |
14000 | || bytemode == bnd_swap_mode); | |
6c30d220 L |
14001 | const char **indexes64 = names64; |
14002 | const char **indexes32 = names32; | |
252b5132 RH |
14003 | |
14004 | havesib = 0; | |
14005 | havebase = 1; | |
0f7da397 | 14006 | haveindex = 0; |
7967e09e | 14007 | base = modrm.rm; |
252b5132 RH |
14008 | |
14009 | if (base == 4) | |
14010 | { | |
14011 | havesib = 1; | |
dfc8cf43 | 14012 | vindex = sib.index; |
161a04f6 L |
14013 | USED_REX (REX_X); |
14014 | if (rex & REX_X) | |
91d6fa6a | 14015 | vindex += 8; |
6c30d220 L |
14016 | switch (bytemode) |
14017 | { | |
14018 | case vex_vsib_d_w_dq_mode: | |
5fc35d96 | 14019 | case vex_vsib_d_w_d_mode: |
6c30d220 | 14020 | case vex_vsib_q_w_dq_mode: |
5fc35d96 | 14021 | case vex_vsib_q_w_d_mode: |
6c30d220 L |
14022 | if (!need_vex) |
14023 | abort (); | |
43234a1e L |
14024 | if (vex.evex) |
14025 | { | |
14026 | if (!vex.v) | |
14027 | vindex += 16; | |
14028 | } | |
6c30d220 L |
14029 | |
14030 | haveindex = 1; | |
14031 | switch (vex.length) | |
14032 | { | |
14033 | case 128: | |
7bb15c6f | 14034 | indexes64 = indexes32 = names_xmm; |
6c30d220 L |
14035 | break; |
14036 | case 256: | |
5fc35d96 IT |
14037 | if (!vex.w |
14038 | || bytemode == vex_vsib_q_w_dq_mode | |
14039 | || bytemode == vex_vsib_q_w_d_mode) | |
7bb15c6f | 14040 | indexes64 = indexes32 = names_ymm; |
6c30d220 | 14041 | else |
7bb15c6f | 14042 | indexes64 = indexes32 = names_xmm; |
6c30d220 | 14043 | break; |
43234a1e | 14044 | case 512: |
5fc35d96 IT |
14045 | if (!vex.w |
14046 | || bytemode == vex_vsib_q_w_dq_mode | |
14047 | || bytemode == vex_vsib_q_w_d_mode) | |
43234a1e L |
14048 | indexes64 = indexes32 = names_zmm; |
14049 | else | |
14050 | indexes64 = indexes32 = names_ymm; | |
14051 | break; | |
6c30d220 L |
14052 | default: |
14053 | abort (); | |
14054 | } | |
14055 | break; | |
14056 | default: | |
14057 | haveindex = vindex != 4; | |
14058 | break; | |
14059 | } | |
14060 | scale = sib.scale; | |
14061 | base = sib.base; | |
252b5132 RH |
14062 | codep++; |
14063 | } | |
82c18208 | 14064 | rbase = base + add; |
252b5132 | 14065 | |
7967e09e | 14066 | switch (modrm.mod) |
252b5132 RH |
14067 | { |
14068 | case 0: | |
82c18208 | 14069 | if (base == 5) |
252b5132 RH |
14070 | { |
14071 | havebase = 0; | |
cb712a9e | 14072 | if (address_mode == mode_64bit && !havesib) |
52b15da3 JH |
14073 | riprel = 1; |
14074 | disp = get32s (); | |
d276ec69 JB |
14075 | if (riprel && bytemode == v_bndmk_mode) |
14076 | { | |
14077 | oappend ("(bad)"); | |
14078 | return; | |
14079 | } | |
252b5132 RH |
14080 | } |
14081 | break; | |
14082 | case 1: | |
14083 | FETCH_DATA (the_info, codep + 1); | |
14084 | disp = *codep++; | |
14085 | if ((disp & 0x80) != 0) | |
14086 | disp -= 0x100; | |
43234a1e L |
14087 | if (vex.evex && shift > 0) |
14088 | disp <<= shift; | |
252b5132 RH |
14089 | break; |
14090 | case 2: | |
52b15da3 | 14091 | disp = get32s (); |
252b5132 RH |
14092 | break; |
14093 | } | |
14094 | ||
1bc60e56 L |
14095 | needindex = 0; |
14096 | needaddr32 = 0; | |
14097 | if (havesib | |
14098 | && !havebase | |
14099 | && !haveindex | |
14100 | && address_mode != mode_16bit) | |
14101 | { | |
14102 | if (address_mode == mode_64bit) | |
14103 | { | |
14104 | /* Display eiz instead of addr32. */ | |
14105 | needindex = addr32flag; | |
14106 | needaddr32 = 1; | |
14107 | } | |
14108 | else | |
14109 | { | |
14110 | /* In 32-bit mode, we need index register to tell [offset] | |
14111 | from [eiz*1 + offset]. */ | |
14112 | needindex = 1; | |
14113 | } | |
14114 | } | |
14115 | ||
20afcfb7 L |
14116 | havedisp = (havebase |
14117 | || needindex | |
14118 | || (havesib && (haveindex || scale != 0))); | |
5d669648 | 14119 | |
252b5132 | 14120 | if (!intel_syntax) |
82c18208 | 14121 | if (modrm.mod != 0 || base == 5) |
db6eb5be | 14122 | { |
5d669648 L |
14123 | if (havedisp || riprel) |
14124 | print_displacement (scratchbuf, disp); | |
14125 | else | |
14126 | print_operand_value (scratchbuf, 1, disp); | |
db6eb5be | 14127 | oappend (scratchbuf); |
52b15da3 JH |
14128 | if (riprel) |
14129 | { | |
14130 | set_op (disp, 1); | |
28596323 | 14131 | oappend (!addr32flag ? "(%rip)" : "(%eip)"); |
52b15da3 | 14132 | } |
db6eb5be | 14133 | } |
2da11e11 | 14134 | |
c1dc7af5 | 14135 | if ((havebase || haveindex || needindex || needaddr32 || riprel) |
a23b33b3 JB |
14136 | && (address_mode != mode_64bit |
14137 | || ((bytemode != v_bnd_mode) | |
14138 | && (bytemode != v_bndmk_mode) | |
14139 | && (bytemode != bnd_mode) | |
14140 | && (bytemode != bnd_swap_mode)))) | |
87767711 JB |
14141 | used_prefixes |= PREFIX_ADDR; |
14142 | ||
5d669648 | 14143 | if (havedisp || (intel_syntax && riprel)) |
252b5132 | 14144 | { |
252b5132 | 14145 | *obufp++ = open_char; |
52b15da3 | 14146 | if (intel_syntax && riprel) |
185b1163 L |
14147 | { |
14148 | set_op (disp, 1); | |
28596323 | 14149 | oappend (!addr32flag ? "rip" : "eip"); |
185b1163 | 14150 | } |
db6eb5be | 14151 | *obufp = '\0'; |
252b5132 | 14152 | if (havebase) |
7e8b059b | 14153 | oappend (address_mode == mode_64bit && !addr32flag |
82c18208 | 14154 | ? names64[rbase] : names32[rbase]); |
252b5132 RH |
14155 | if (havesib) |
14156 | { | |
db51cc60 L |
14157 | /* ESP/RSP won't allow index. If base isn't ESP/RSP, |
14158 | print index to tell base + index from base. */ | |
14159 | if (scale != 0 | |
20afcfb7 | 14160 | || needindex |
db51cc60 L |
14161 | || haveindex |
14162 | || (havebase && base != ESP_REG_NUM)) | |
252b5132 | 14163 | { |
9306ca4a | 14164 | if (!intel_syntax || havebase) |
db6eb5be | 14165 | { |
9306ca4a JB |
14166 | *obufp++ = separator_char; |
14167 | *obufp = '\0'; | |
db6eb5be | 14168 | } |
db51cc60 | 14169 | if (haveindex) |
7e8b059b | 14170 | oappend (address_mode == mode_64bit && !addr32flag |
6c30d220 | 14171 | ? indexes64[vindex] : indexes32[vindex]); |
db51cc60 | 14172 | else |
7e8b059b | 14173 | oappend (address_mode == mode_64bit && !addr32flag |
db51cc60 L |
14174 | ? index64 : index32); |
14175 | ||
db6eb5be AM |
14176 | *obufp++ = scale_char; |
14177 | *obufp = '\0'; | |
14178 | sprintf (scratchbuf, "%d", 1 << scale); | |
14179 | oappend (scratchbuf); | |
14180 | } | |
252b5132 | 14181 | } |
185b1163 | 14182 | if (intel_syntax |
82c18208 | 14183 | && (disp || modrm.mod != 0 || base == 5)) |
3d456fa1 | 14184 | { |
db51cc60 | 14185 | if (!havedisp || (bfd_signed_vma) disp >= 0) |
3d456fa1 JB |
14186 | { |
14187 | *obufp++ = '+'; | |
14188 | *obufp = '\0'; | |
14189 | } | |
05203043 | 14190 | else if (modrm.mod != 1 && disp != -disp) |
3d456fa1 JB |
14191 | { |
14192 | *obufp++ = '-'; | |
14193 | *obufp = '\0'; | |
14194 | disp = - (bfd_signed_vma) disp; | |
14195 | } | |
14196 | ||
db51cc60 L |
14197 | if (havedisp) |
14198 | print_displacement (scratchbuf, disp); | |
14199 | else | |
14200 | print_operand_value (scratchbuf, 1, disp); | |
3d456fa1 JB |
14201 | oappend (scratchbuf); |
14202 | } | |
252b5132 RH |
14203 | |
14204 | *obufp++ = close_char; | |
db6eb5be | 14205 | *obufp = '\0'; |
252b5132 RH |
14206 | } |
14207 | else if (intel_syntax) | |
db6eb5be | 14208 | { |
82c18208 | 14209 | if (modrm.mod != 0 || base == 5) |
db6eb5be | 14210 | { |
285ca992 | 14211 | if (!active_seg_prefix) |
252b5132 | 14212 | { |
d708bcba | 14213 | oappend (names_seg[ds_reg - es_reg]); |
252b5132 RH |
14214 | oappend (":"); |
14215 | } | |
52b15da3 | 14216 | print_operand_value (scratchbuf, 1, disp); |
db6eb5be AM |
14217 | oappend (scratchbuf); |
14218 | } | |
14219 | } | |
252b5132 | 14220 | } |
a23b33b3 JB |
14221 | else if (bytemode == v_bnd_mode |
14222 | || bytemode == v_bndmk_mode | |
14223 | || bytemode == bnd_mode | |
14224 | || bytemode == bnd_swap_mode) | |
14225 | { | |
14226 | oappend ("(bad)"); | |
14227 | return; | |
14228 | } | |
252b5132 | 14229 | else |
f16cd0d5 L |
14230 | { |
14231 | /* 16 bit address mode */ | |
14232 | used_prefixes |= prefixes & PREFIX_ADDR; | |
7967e09e | 14233 | switch (modrm.mod) |
252b5132 RH |
14234 | { |
14235 | case 0: | |
7967e09e | 14236 | if (modrm.rm == 6) |
252b5132 RH |
14237 | { |
14238 | disp = get16 (); | |
14239 | if ((disp & 0x8000) != 0) | |
14240 | disp -= 0x10000; | |
14241 | } | |
14242 | break; | |
14243 | case 1: | |
14244 | FETCH_DATA (the_info, codep + 1); | |
14245 | disp = *codep++; | |
14246 | if ((disp & 0x80) != 0) | |
14247 | disp -= 0x100; | |
65f3ed04 JB |
14248 | if (vex.evex && shift > 0) |
14249 | disp <<= shift; | |
252b5132 RH |
14250 | break; |
14251 | case 2: | |
14252 | disp = get16 (); | |
14253 | if ((disp & 0x8000) != 0) | |
14254 | disp -= 0x10000; | |
14255 | break; | |
14256 | } | |
14257 | ||
14258 | if (!intel_syntax) | |
7967e09e | 14259 | if (modrm.mod != 0 || modrm.rm == 6) |
db6eb5be | 14260 | { |
5d669648 | 14261 | print_displacement (scratchbuf, disp); |
db6eb5be AM |
14262 | oappend (scratchbuf); |
14263 | } | |
252b5132 | 14264 | |
7967e09e | 14265 | if (modrm.mod != 0 || modrm.rm != 6) |
252b5132 RH |
14266 | { |
14267 | *obufp++ = open_char; | |
db6eb5be | 14268 | *obufp = '\0'; |
7967e09e | 14269 | oappend (index16[modrm.rm]); |
5d669648 L |
14270 | if (intel_syntax |
14271 | && (disp || modrm.mod != 0 || modrm.rm == 6)) | |
3d456fa1 | 14272 | { |
5d669648 | 14273 | if ((bfd_signed_vma) disp >= 0) |
3d456fa1 JB |
14274 | { |
14275 | *obufp++ = '+'; | |
14276 | *obufp = '\0'; | |
14277 | } | |
7967e09e | 14278 | else if (modrm.mod != 1) |
3d456fa1 JB |
14279 | { |
14280 | *obufp++ = '-'; | |
14281 | *obufp = '\0'; | |
14282 | disp = - (bfd_signed_vma) disp; | |
14283 | } | |
14284 | ||
5d669648 | 14285 | print_displacement (scratchbuf, disp); |
3d456fa1 JB |
14286 | oappend (scratchbuf); |
14287 | } | |
14288 | ||
db6eb5be AM |
14289 | *obufp++ = close_char; |
14290 | *obufp = '\0'; | |
252b5132 | 14291 | } |
3d456fa1 JB |
14292 | else if (intel_syntax) |
14293 | { | |
285ca992 | 14294 | if (!active_seg_prefix) |
3d456fa1 JB |
14295 | { |
14296 | oappend (names_seg[ds_reg - es_reg]); | |
14297 | oappend (":"); | |
14298 | } | |
14299 | print_operand_value (scratchbuf, 1, disp & 0xffff); | |
14300 | oappend (scratchbuf); | |
14301 | } | |
252b5132 | 14302 | } |
43234a1e L |
14303 | if (vex.evex && vex.b |
14304 | && (bytemode == x_mode | |
90a915bf | 14305 | || bytemode == xmmq_mode |
43234a1e L |
14306 | || bytemode == evex_half_bcst_xmmq_mode)) |
14307 | { | |
90a915bf IT |
14308 | if (vex.w |
14309 | || bytemode == xmmq_mode | |
14310 | || bytemode == evex_half_bcst_xmmq_mode) | |
b28d1bda IT |
14311 | { |
14312 | switch (vex.length) | |
14313 | { | |
14314 | case 128: | |
14315 | oappend ("{1to2}"); | |
14316 | break; | |
14317 | case 256: | |
14318 | oappend ("{1to4}"); | |
14319 | break; | |
14320 | case 512: | |
14321 | oappend ("{1to8}"); | |
14322 | break; | |
14323 | default: | |
14324 | abort (); | |
14325 | } | |
14326 | } | |
43234a1e | 14327 | else |
b28d1bda IT |
14328 | { |
14329 | switch (vex.length) | |
14330 | { | |
14331 | case 128: | |
14332 | oappend ("{1to4}"); | |
14333 | break; | |
14334 | case 256: | |
14335 | oappend ("{1to8}"); | |
14336 | break; | |
14337 | case 512: | |
14338 | oappend ("{1to16}"); | |
14339 | break; | |
14340 | default: | |
14341 | abort (); | |
14342 | } | |
14343 | } | |
43234a1e | 14344 | } |
252b5132 RH |
14345 | } |
14346 | ||
c0f3af97 | 14347 | static void |
8b3f93e7 | 14348 | OP_E (int bytemode, int sizeflag) |
c0f3af97 L |
14349 | { |
14350 | /* Skip mod/rm byte. */ | |
14351 | MODRM_CHECK; | |
14352 | codep++; | |
14353 | ||
14354 | if (modrm.mod == 3) | |
14355 | OP_E_register (bytemode, sizeflag); | |
14356 | else | |
c1e679ec | 14357 | OP_E_memory (bytemode, sizeflag); |
c0f3af97 L |
14358 | } |
14359 | ||
252b5132 | 14360 | static void |
26ca5450 | 14361 | OP_G (int bytemode, int sizeflag) |
252b5132 | 14362 | { |
52b15da3 | 14363 | int add = 0; |
c0a30a9f | 14364 | const char **names; |
161a04f6 L |
14365 | USED_REX (REX_R); |
14366 | if (rex & REX_R) | |
52b15da3 | 14367 | add += 8; |
252b5132 RH |
14368 | switch (bytemode) |
14369 | { | |
14370 | case b_mode: | |
52b15da3 JH |
14371 | USED_REX (0); |
14372 | if (rex) | |
7967e09e | 14373 | oappend (names8rex[modrm.reg + add]); |
52b15da3 | 14374 | else |
7967e09e | 14375 | oappend (names8[modrm.reg + add]); |
252b5132 RH |
14376 | break; |
14377 | case w_mode: | |
7967e09e | 14378 | oappend (names16[modrm.reg + add]); |
252b5132 RH |
14379 | break; |
14380 | case d_mode: | |
1ba585e8 IT |
14381 | case db_mode: |
14382 | case dw_mode: | |
7967e09e | 14383 | oappend (names32[modrm.reg + add]); |
52b15da3 JH |
14384 | break; |
14385 | case q_mode: | |
7967e09e | 14386 | oappend (names64[modrm.reg + add]); |
252b5132 | 14387 | break; |
7e8b059b | 14388 | case bnd_mode: |
0d96e4df L |
14389 | if (modrm.reg > 0x3) |
14390 | { | |
14391 | oappend ("(bad)"); | |
14392 | return; | |
14393 | } | |
7e8b059b L |
14394 | oappend (names_bnd[modrm.reg]); |
14395 | break; | |
252b5132 | 14396 | case v_mode: |
9306ca4a | 14397 | case dq_mode: |
42903f7f L |
14398 | case dqb_mode: |
14399 | case dqd_mode: | |
9306ca4a | 14400 | case dqw_mode: |
bc31405e | 14401 | case movsxd_mode: |
161a04f6 L |
14402 | USED_REX (REX_W); |
14403 | if (rex & REX_W) | |
7967e09e | 14404 | oappend (names64[modrm.reg + add]); |
252b5132 | 14405 | else |
f16cd0d5 | 14406 | { |
bc31405e L |
14407 | if ((sizeflag & DFLAG) |
14408 | || (bytemode != v_mode && bytemode != movsxd_mode)) | |
f16cd0d5 L |
14409 | oappend (names32[modrm.reg + add]); |
14410 | else | |
14411 | oappend (names16[modrm.reg + add]); | |
14412 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14413 | } | |
252b5132 | 14414 | break; |
c0a30a9f L |
14415 | case va_mode: |
14416 | names = (address_mode == mode_64bit | |
14417 | ? names64 : names32); | |
14418 | if (!(prefixes & PREFIX_ADDR)) | |
14419 | { | |
14420 | if (address_mode == mode_16bit) | |
14421 | names = names16; | |
14422 | } | |
14423 | else | |
14424 | { | |
14425 | /* Remove "addr16/addr32". */ | |
14426 | all_prefixes[last_addr_prefix] = 0; | |
14427 | names = (address_mode != mode_32bit | |
14428 | ? names32 : names16); | |
14429 | used_prefixes |= PREFIX_ADDR; | |
14430 | } | |
14431 | oappend (names[modrm.reg + add]); | |
14432 | break; | |
90700ea2 | 14433 | case m_mode: |
cb712a9e | 14434 | if (address_mode == mode_64bit) |
7967e09e | 14435 | oappend (names64[modrm.reg + add]); |
90700ea2 | 14436 | else |
7967e09e | 14437 | oappend (names32[modrm.reg + add]); |
90700ea2 | 14438 | break; |
1ba585e8 | 14439 | case mask_bd_mode: |
43234a1e | 14440 | case mask_mode: |
9889cbb1 L |
14441 | if ((modrm.reg + add) > 0x7) |
14442 | { | |
14443 | oappend ("(bad)"); | |
14444 | return; | |
14445 | } | |
43234a1e L |
14446 | oappend (names_mask[modrm.reg + add]); |
14447 | break; | |
252b5132 RH |
14448 | default: |
14449 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
14450 | break; | |
14451 | } | |
14452 | } | |
14453 | ||
52b15da3 | 14454 | static bfd_vma |
26ca5450 | 14455 | get64 (void) |
52b15da3 | 14456 | { |
5dd0794d | 14457 | bfd_vma x; |
52b15da3 | 14458 | #ifdef BFD64 |
5dd0794d AM |
14459 | unsigned int a; |
14460 | unsigned int b; | |
14461 | ||
52b15da3 JH |
14462 | FETCH_DATA (the_info, codep + 8); |
14463 | a = *codep++ & 0xff; | |
14464 | a |= (*codep++ & 0xff) << 8; | |
14465 | a |= (*codep++ & 0xff) << 16; | |
070fe95d | 14466 | a |= (*codep++ & 0xffu) << 24; |
5dd0794d | 14467 | b = *codep++ & 0xff; |
52b15da3 JH |
14468 | b |= (*codep++ & 0xff) << 8; |
14469 | b |= (*codep++ & 0xff) << 16; | |
070fe95d | 14470 | b |= (*codep++ & 0xffu) << 24; |
52b15da3 JH |
14471 | x = a + ((bfd_vma) b << 32); |
14472 | #else | |
6608db57 | 14473 | abort (); |
5dd0794d | 14474 | x = 0; |
52b15da3 JH |
14475 | #endif |
14476 | return x; | |
14477 | } | |
14478 | ||
14479 | static bfd_signed_vma | |
26ca5450 | 14480 | get32 (void) |
252b5132 | 14481 | { |
52b15da3 | 14482 | bfd_signed_vma x = 0; |
252b5132 RH |
14483 | |
14484 | FETCH_DATA (the_info, codep + 4); | |
52b15da3 JH |
14485 | x = *codep++ & (bfd_signed_vma) 0xff; |
14486 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 8; | |
14487 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 16; | |
14488 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 24; | |
14489 | return x; | |
14490 | } | |
14491 | ||
14492 | static bfd_signed_vma | |
26ca5450 | 14493 | get32s (void) |
52b15da3 JH |
14494 | { |
14495 | bfd_signed_vma x = 0; | |
14496 | ||
14497 | FETCH_DATA (the_info, codep + 4); | |
14498 | x = *codep++ & (bfd_signed_vma) 0xff; | |
14499 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 8; | |
14500 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 16; | |
14501 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 24; | |
14502 | ||
14503 | x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31); | |
14504 | ||
252b5132 RH |
14505 | return x; |
14506 | } | |
14507 | ||
14508 | static int | |
26ca5450 | 14509 | get16 (void) |
252b5132 RH |
14510 | { |
14511 | int x = 0; | |
14512 | ||
14513 | FETCH_DATA (the_info, codep + 2); | |
14514 | x = *codep++ & 0xff; | |
14515 | x |= (*codep++ & 0xff) << 8; | |
14516 | return x; | |
14517 | } | |
14518 | ||
14519 | static void | |
26ca5450 | 14520 | set_op (bfd_vma op, int riprel) |
252b5132 RH |
14521 | { |
14522 | op_index[op_ad] = op_ad; | |
cb712a9e | 14523 | if (address_mode == mode_64bit) |
7081ff04 AJ |
14524 | { |
14525 | op_address[op_ad] = op; | |
14526 | op_riprel[op_ad] = riprel; | |
14527 | } | |
14528 | else | |
14529 | { | |
14530 | /* Mask to get a 32-bit address. */ | |
14531 | op_address[op_ad] = op & 0xffffffff; | |
14532 | op_riprel[op_ad] = riprel & 0xffffffff; | |
14533 | } | |
252b5132 RH |
14534 | } |
14535 | ||
14536 | static void | |
26ca5450 | 14537 | OP_REG (int code, int sizeflag) |
252b5132 | 14538 | { |
2da11e11 | 14539 | const char *s; |
9b60702d | 14540 | int add; |
de882298 RM |
14541 | |
14542 | switch (code) | |
14543 | { | |
14544 | case es_reg: case ss_reg: case cs_reg: | |
14545 | case ds_reg: case fs_reg: case gs_reg: | |
14546 | oappend (names_seg[code - es_reg]); | |
14547 | return; | |
14548 | } | |
14549 | ||
161a04f6 L |
14550 | USED_REX (REX_B); |
14551 | if (rex & REX_B) | |
52b15da3 | 14552 | add = 8; |
9b60702d L |
14553 | else |
14554 | add = 0; | |
52b15da3 JH |
14555 | |
14556 | switch (code) | |
14557 | { | |
52b15da3 JH |
14558 | case ax_reg: case cx_reg: case dx_reg: case bx_reg: |
14559 | case sp_reg: case bp_reg: case si_reg: case di_reg: | |
14560 | s = names16[code - ax_reg + add]; | |
14561 | break; | |
52b15da3 JH |
14562 | case al_reg: case ah_reg: case cl_reg: case ch_reg: |
14563 | case dl_reg: case dh_reg: case bl_reg: case bh_reg: | |
14564 | USED_REX (0); | |
14565 | if (rex) | |
14566 | s = names8rex[code - al_reg + add]; | |
14567 | else | |
14568 | s = names8[code - al_reg]; | |
14569 | break; | |
6439fc28 AM |
14570 | case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg: |
14571 | case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg: | |
7bb15c6f | 14572 | if (address_mode == mode_64bit |
6c067bbb | 14573 | && ((sizeflag & DFLAG) || (rex & REX_W))) |
6439fc28 AM |
14574 | { |
14575 | s = names64[code - rAX_reg + add]; | |
14576 | break; | |
14577 | } | |
14578 | code += eAX_reg - rAX_reg; | |
6608db57 | 14579 | /* Fall through. */ |
52b15da3 JH |
14580 | case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg: |
14581 | case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg: | |
161a04f6 L |
14582 | USED_REX (REX_W); |
14583 | if (rex & REX_W) | |
52b15da3 | 14584 | s = names64[code - eAX_reg + add]; |
52b15da3 | 14585 | else |
f16cd0d5 L |
14586 | { |
14587 | if (sizeflag & DFLAG) | |
14588 | s = names32[code - eAX_reg + add]; | |
14589 | else | |
14590 | s = names16[code - eAX_reg + add]; | |
14591 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14592 | } | |
52b15da3 | 14593 | break; |
52b15da3 JH |
14594 | default: |
14595 | s = INTERNAL_DISASSEMBLER_ERROR; | |
14596 | break; | |
14597 | } | |
14598 | oappend (s); | |
14599 | } | |
14600 | ||
14601 | static void | |
26ca5450 | 14602 | OP_IMREG (int code, int sizeflag) |
52b15da3 JH |
14603 | { |
14604 | const char *s; | |
252b5132 RH |
14605 | |
14606 | switch (code) | |
14607 | { | |
14608 | case indir_dx_reg: | |
d708bcba | 14609 | if (intel_syntax) |
52fd6d94 | 14610 | s = "dx"; |
d708bcba | 14611 | else |
db6eb5be | 14612 | s = "(%dx)"; |
252b5132 RH |
14613 | break; |
14614 | case ax_reg: case cx_reg: case dx_reg: case bx_reg: | |
14615 | case sp_reg: case bp_reg: case si_reg: case di_reg: | |
14616 | s = names16[code - ax_reg]; | |
14617 | break; | |
14618 | case es_reg: case ss_reg: case cs_reg: | |
14619 | case ds_reg: case fs_reg: case gs_reg: | |
14620 | s = names_seg[code - es_reg]; | |
14621 | break; | |
14622 | case al_reg: case ah_reg: case cl_reg: case ch_reg: | |
14623 | case dl_reg: case dh_reg: case bl_reg: case bh_reg: | |
52b15da3 JH |
14624 | USED_REX (0); |
14625 | if (rex) | |
14626 | s = names8rex[code - al_reg]; | |
14627 | else | |
14628 | s = names8[code - al_reg]; | |
252b5132 RH |
14629 | break; |
14630 | case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg: | |
14631 | case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg: | |
161a04f6 L |
14632 | USED_REX (REX_W); |
14633 | if (rex & REX_W) | |
52b15da3 | 14634 | s = names64[code - eAX_reg]; |
252b5132 | 14635 | else |
f16cd0d5 L |
14636 | { |
14637 | if (sizeflag & DFLAG) | |
14638 | s = names32[code - eAX_reg]; | |
14639 | else | |
14640 | s = names16[code - eAX_reg]; | |
14641 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14642 | } | |
252b5132 | 14643 | break; |
52fd6d94 | 14644 | case z_mode_ax_reg: |
161a04f6 | 14645 | if ((rex & REX_W) || (sizeflag & DFLAG)) |
52fd6d94 JB |
14646 | s = *names32; |
14647 | else | |
14648 | s = *names16; | |
161a04f6 | 14649 | if (!(rex & REX_W)) |
52fd6d94 JB |
14650 | used_prefixes |= (prefixes & PREFIX_DATA); |
14651 | break; | |
252b5132 RH |
14652 | default: |
14653 | s = INTERNAL_DISASSEMBLER_ERROR; | |
14654 | break; | |
14655 | } | |
14656 | oappend (s); | |
14657 | } | |
14658 | ||
14659 | static void | |
26ca5450 | 14660 | OP_I (int bytemode, int sizeflag) |
252b5132 | 14661 | { |
52b15da3 JH |
14662 | bfd_signed_vma op; |
14663 | bfd_signed_vma mask = -1; | |
252b5132 RH |
14664 | |
14665 | switch (bytemode) | |
14666 | { | |
14667 | case b_mode: | |
14668 | FETCH_DATA (the_info, codep + 1); | |
52b15da3 JH |
14669 | op = *codep++; |
14670 | mask = 0xff; | |
14671 | break; | |
252b5132 | 14672 | case v_mode: |
161a04f6 L |
14673 | USED_REX (REX_W); |
14674 | if (rex & REX_W) | |
52b15da3 | 14675 | op = get32s (); |
252b5132 | 14676 | else |
52b15da3 | 14677 | { |
f16cd0d5 L |
14678 | if (sizeflag & DFLAG) |
14679 | { | |
14680 | op = get32 (); | |
14681 | mask = 0xffffffff; | |
14682 | } | |
14683 | else | |
14684 | { | |
14685 | op = get16 (); | |
14686 | mask = 0xfffff; | |
14687 | } | |
14688 | used_prefixes |= (prefixes & PREFIX_DATA); | |
52b15da3 | 14689 | } |
252b5132 | 14690 | break; |
c1dc7af5 JB |
14691 | case d_mode: |
14692 | mask = 0xffffffff; | |
14693 | op = get32 (); | |
14694 | break; | |
252b5132 | 14695 | case w_mode: |
52b15da3 | 14696 | mask = 0xfffff; |
252b5132 RH |
14697 | op = get16 (); |
14698 | break; | |
9306ca4a JB |
14699 | case const_1_mode: |
14700 | if (intel_syntax) | |
6c067bbb | 14701 | oappend ("1"); |
9306ca4a | 14702 | return; |
252b5132 RH |
14703 | default: |
14704 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
14705 | return; | |
14706 | } | |
14707 | ||
52b15da3 JH |
14708 | op &= mask; |
14709 | scratchbuf[0] = '$'; | |
d708bcba | 14710 | print_operand_value (scratchbuf + 1, 1, op); |
9ce09ba2 | 14711 | oappend_maybe_intel (scratchbuf); |
52b15da3 JH |
14712 | scratchbuf[0] = '\0'; |
14713 | } | |
14714 | ||
14715 | static void | |
26ca5450 | 14716 | OP_I64 (int bytemode, int sizeflag) |
52b15da3 | 14717 | { |
a280ab8e | 14718 | if (bytemode != v_mode || address_mode != mode_64bit || !(rex & REX_W)) |
6439fc28 AM |
14719 | { |
14720 | OP_I (bytemode, sizeflag); | |
14721 | return; | |
14722 | } | |
14723 | ||
a280ab8e | 14724 | USED_REX (REX_W); |
52b15da3 | 14725 | |
52b15da3 | 14726 | scratchbuf[0] = '$'; |
a280ab8e | 14727 | print_operand_value (scratchbuf + 1, 1, get64 ()); |
9ce09ba2 | 14728 | oappend_maybe_intel (scratchbuf); |
252b5132 RH |
14729 | scratchbuf[0] = '\0'; |
14730 | } | |
14731 | ||
14732 | static void | |
26ca5450 | 14733 | OP_sI (int bytemode, int sizeflag) |
252b5132 | 14734 | { |
52b15da3 | 14735 | bfd_signed_vma op; |
252b5132 RH |
14736 | |
14737 | switch (bytemode) | |
14738 | { | |
14739 | case b_mode: | |
e3949f17 | 14740 | case b_T_mode: |
252b5132 RH |
14741 | FETCH_DATA (the_info, codep + 1); |
14742 | op = *codep++; | |
14743 | if ((op & 0x80) != 0) | |
14744 | op -= 0x100; | |
e3949f17 L |
14745 | if (bytemode == b_T_mode) |
14746 | { | |
14747 | if (address_mode != mode_64bit | |
7bb15c6f | 14748 | || !((sizeflag & DFLAG) || (rex & REX_W))) |
e3949f17 | 14749 | { |
6c067bbb RM |
14750 | /* The operand-size prefix is overridden by a REX prefix. */ |
14751 | if ((sizeflag & DFLAG) || (rex & REX_W)) | |
e3949f17 L |
14752 | op &= 0xffffffff; |
14753 | else | |
14754 | op &= 0xffff; | |
14755 | } | |
14756 | } | |
14757 | else | |
14758 | { | |
14759 | if (!(rex & REX_W)) | |
14760 | { | |
14761 | if (sizeflag & DFLAG) | |
14762 | op &= 0xffffffff; | |
14763 | else | |
14764 | op &= 0xffff; | |
14765 | } | |
14766 | } | |
252b5132 RH |
14767 | break; |
14768 | case v_mode: | |
7bb15c6f RM |
14769 | /* The operand-size prefix is overridden by a REX prefix. */ |
14770 | if ((sizeflag & DFLAG) || (rex & REX_W)) | |
52b15da3 | 14771 | op = get32s (); |
252b5132 | 14772 | else |
d9e3625e | 14773 | op = get16 (); |
252b5132 RH |
14774 | break; |
14775 | default: | |
14776 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
14777 | return; | |
14778 | } | |
52b15da3 JH |
14779 | |
14780 | scratchbuf[0] = '$'; | |
14781 | print_operand_value (scratchbuf + 1, 1, op); | |
9ce09ba2 | 14782 | oappend_maybe_intel (scratchbuf); |
252b5132 RH |
14783 | } |
14784 | ||
14785 | static void | |
26ca5450 | 14786 | OP_J (int bytemode, int sizeflag) |
252b5132 | 14787 | { |
52b15da3 | 14788 | bfd_vma disp; |
7081ff04 | 14789 | bfd_vma mask = -1; |
65ca155d | 14790 | bfd_vma segment = 0; |
252b5132 RH |
14791 | |
14792 | switch (bytemode) | |
14793 | { | |
14794 | case b_mode: | |
14795 | FETCH_DATA (the_info, codep + 1); | |
14796 | disp = *codep++; | |
14797 | if ((disp & 0x80) != 0) | |
14798 | disp -= 0x100; | |
14799 | break; | |
14800 | case v_mode: | |
d835a58b | 14801 | if (isa64 != intel64) |
376cd056 | 14802 | case dqw_mode: |
5db04b09 L |
14803 | USED_REX (REX_W); |
14804 | if ((sizeflag & DFLAG) | |
14805 | || (address_mode == mode_64bit | |
d835a58b | 14806 | && ((isa64 == intel64 && bytemode != dqw_mode) |
376cd056 | 14807 | || (rex & REX_W)))) |
52b15da3 | 14808 | disp = get32s (); |
252b5132 RH |
14809 | else |
14810 | { | |
14811 | disp = get16 (); | |
206717e8 L |
14812 | if ((disp & 0x8000) != 0) |
14813 | disp -= 0x10000; | |
65ca155d L |
14814 | /* In 16bit mode, address is wrapped around at 64k within |
14815 | the same segment. Otherwise, a data16 prefix on a jump | |
14816 | instruction means that the pc is masked to 16 bits after | |
14817 | the displacement is added! */ | |
14818 | mask = 0xffff; | |
14819 | if ((prefixes & PREFIX_DATA) == 0) | |
4fd7268a | 14820 | segment = ((start_pc + (codep - start_codep)) |
65ca155d | 14821 | & ~((bfd_vma) 0xffff)); |
252b5132 | 14822 | } |
5db04b09 | 14823 | if (address_mode != mode_64bit |
d835a58b | 14824 | || (isa64 != intel64 && !(rex & REX_W))) |
f16cd0d5 | 14825 | used_prefixes |= (prefixes & PREFIX_DATA); |
252b5132 RH |
14826 | break; |
14827 | default: | |
14828 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
14829 | return; | |
14830 | } | |
42d5f9c6 | 14831 | disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment; |
52b15da3 JH |
14832 | set_op (disp, 0); |
14833 | print_operand_value (scratchbuf, 1, disp); | |
252b5132 RH |
14834 | oappend (scratchbuf); |
14835 | } | |
14836 | ||
252b5132 | 14837 | static void |
ed7841b3 | 14838 | OP_SEG (int bytemode, int sizeflag) |
252b5132 | 14839 | { |
ed7841b3 | 14840 | if (bytemode == w_mode) |
7967e09e | 14841 | oappend (names_seg[modrm.reg]); |
ed7841b3 | 14842 | else |
7967e09e | 14843 | OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag); |
252b5132 RH |
14844 | } |
14845 | ||
14846 | static void | |
26ca5450 | 14847 | OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag) |
252b5132 RH |
14848 | { |
14849 | int seg, offset; | |
14850 | ||
c608c12e | 14851 | if (sizeflag & DFLAG) |
252b5132 | 14852 | { |
c608c12e AM |
14853 | offset = get32 (); |
14854 | seg = get16 (); | |
252b5132 | 14855 | } |
c608c12e AM |
14856 | else |
14857 | { | |
14858 | offset = get16 (); | |
14859 | seg = get16 (); | |
14860 | } | |
7d421014 | 14861 | used_prefixes |= (prefixes & PREFIX_DATA); |
d708bcba | 14862 | if (intel_syntax) |
3f31e633 | 14863 | sprintf (scratchbuf, "0x%x:0x%x", seg, offset); |
d708bcba AM |
14864 | else |
14865 | sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset); | |
c608c12e | 14866 | oappend (scratchbuf); |
252b5132 RH |
14867 | } |
14868 | ||
252b5132 | 14869 | static void |
3f31e633 | 14870 | OP_OFF (int bytemode, int sizeflag) |
252b5132 | 14871 | { |
52b15da3 | 14872 | bfd_vma off; |
252b5132 | 14873 | |
3f31e633 JB |
14874 | if (intel_syntax && (sizeflag & SUFFIX_ALWAYS)) |
14875 | intel_operand_size (bytemode, sizeflag); | |
252b5132 RH |
14876 | append_seg (); |
14877 | ||
cb712a9e | 14878 | if ((sizeflag & AFLAG) || address_mode == mode_64bit) |
252b5132 RH |
14879 | off = get32 (); |
14880 | else | |
14881 | off = get16 (); | |
14882 | ||
14883 | if (intel_syntax) | |
14884 | { | |
285ca992 | 14885 | if (!active_seg_prefix) |
252b5132 | 14886 | { |
d708bcba | 14887 | oappend (names_seg[ds_reg - es_reg]); |
252b5132 RH |
14888 | oappend (":"); |
14889 | } | |
14890 | } | |
52b15da3 JH |
14891 | print_operand_value (scratchbuf, 1, off); |
14892 | oappend (scratchbuf); | |
14893 | } | |
6439fc28 | 14894 | |
52b15da3 | 14895 | static void |
3f31e633 | 14896 | OP_OFF64 (int bytemode, int sizeflag) |
52b15da3 JH |
14897 | { |
14898 | bfd_vma off; | |
14899 | ||
539e75ad L |
14900 | if (address_mode != mode_64bit |
14901 | || (prefixes & PREFIX_ADDR)) | |
6439fc28 AM |
14902 | { |
14903 | OP_OFF (bytemode, sizeflag); | |
14904 | return; | |
14905 | } | |
14906 | ||
3f31e633 JB |
14907 | if (intel_syntax && (sizeflag & SUFFIX_ALWAYS)) |
14908 | intel_operand_size (bytemode, sizeflag); | |
52b15da3 JH |
14909 | append_seg (); |
14910 | ||
6608db57 | 14911 | off = get64 (); |
52b15da3 JH |
14912 | |
14913 | if (intel_syntax) | |
14914 | { | |
285ca992 | 14915 | if (!active_seg_prefix) |
52b15da3 | 14916 | { |
d708bcba | 14917 | oappend (names_seg[ds_reg - es_reg]); |
52b15da3 JH |
14918 | oappend (":"); |
14919 | } | |
14920 | } | |
14921 | print_operand_value (scratchbuf, 1, off); | |
252b5132 RH |
14922 | oappend (scratchbuf); |
14923 | } | |
14924 | ||
14925 | static void | |
26ca5450 | 14926 | ptr_reg (int code, int sizeflag) |
252b5132 | 14927 | { |
2da11e11 | 14928 | const char *s; |
d708bcba | 14929 | |
1d9f512f | 14930 | *obufp++ = open_char; |
20f0a1fc | 14931 | used_prefixes |= (prefixes & PREFIX_ADDR); |
cb712a9e | 14932 | if (address_mode == mode_64bit) |
c1a64871 JH |
14933 | { |
14934 | if (!(sizeflag & AFLAG)) | |
db6eb5be | 14935 | s = names32[code - eAX_reg]; |
c1a64871 | 14936 | else |
db6eb5be | 14937 | s = names64[code - eAX_reg]; |
c1a64871 | 14938 | } |
52b15da3 | 14939 | else if (sizeflag & AFLAG) |
252b5132 RH |
14940 | s = names32[code - eAX_reg]; |
14941 | else | |
14942 | s = names16[code - eAX_reg]; | |
14943 | oappend (s); | |
1d9f512f AM |
14944 | *obufp++ = close_char; |
14945 | *obufp = 0; | |
252b5132 RH |
14946 | } |
14947 | ||
14948 | static void | |
26ca5450 | 14949 | OP_ESreg (int code, int sizeflag) |
252b5132 | 14950 | { |
9306ca4a | 14951 | if (intel_syntax) |
52fd6d94 JB |
14952 | { |
14953 | switch (codep[-1]) | |
14954 | { | |
14955 | case 0x6d: /* insw/insl */ | |
14956 | intel_operand_size (z_mode, sizeflag); | |
14957 | break; | |
14958 | case 0xa5: /* movsw/movsl/movsq */ | |
14959 | case 0xa7: /* cmpsw/cmpsl/cmpsq */ | |
14960 | case 0xab: /* stosw/stosl */ | |
14961 | case 0xaf: /* scasw/scasl */ | |
14962 | intel_operand_size (v_mode, sizeflag); | |
14963 | break; | |
14964 | default: | |
14965 | intel_operand_size (b_mode, sizeflag); | |
14966 | } | |
14967 | } | |
9ce09ba2 | 14968 | oappend_maybe_intel ("%es:"); |
252b5132 RH |
14969 | ptr_reg (code, sizeflag); |
14970 | } | |
14971 | ||
14972 | static void | |
26ca5450 | 14973 | OP_DSreg (int code, int sizeflag) |
252b5132 | 14974 | { |
9306ca4a | 14975 | if (intel_syntax) |
52fd6d94 JB |
14976 | { |
14977 | switch (codep[-1]) | |
14978 | { | |
14979 | case 0x6f: /* outsw/outsl */ | |
14980 | intel_operand_size (z_mode, sizeflag); | |
14981 | break; | |
14982 | case 0xa5: /* movsw/movsl/movsq */ | |
14983 | case 0xa7: /* cmpsw/cmpsl/cmpsq */ | |
14984 | case 0xad: /* lodsw/lodsl/lodsq */ | |
14985 | intel_operand_size (v_mode, sizeflag); | |
14986 | break; | |
14987 | default: | |
14988 | intel_operand_size (b_mode, sizeflag); | |
14989 | } | |
14990 | } | |
285ca992 L |
14991 | /* Set active_seg_prefix to PREFIX_DS if it is unset so that the |
14992 | default segment register DS is printed. */ | |
14993 | if (!active_seg_prefix) | |
14994 | active_seg_prefix = PREFIX_DS; | |
6608db57 | 14995 | append_seg (); |
252b5132 RH |
14996 | ptr_reg (code, sizeflag); |
14997 | } | |
14998 | ||
252b5132 | 14999 | static void |
26ca5450 | 15000 | OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 15001 | { |
9b60702d | 15002 | int add; |
161a04f6 | 15003 | if (rex & REX_R) |
c4a530c5 | 15004 | { |
161a04f6 | 15005 | USED_REX (REX_R); |
c4a530c5 JB |
15006 | add = 8; |
15007 | } | |
cb712a9e | 15008 | else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK)) |
c4a530c5 | 15009 | { |
f16cd0d5 | 15010 | all_prefixes[last_lock_prefix] = 0; |
c4a530c5 JB |
15011 | used_prefixes |= PREFIX_LOCK; |
15012 | add = 8; | |
15013 | } | |
9b60702d L |
15014 | else |
15015 | add = 0; | |
7967e09e | 15016 | sprintf (scratchbuf, "%%cr%d", modrm.reg + add); |
9ce09ba2 | 15017 | oappend_maybe_intel (scratchbuf); |
252b5132 RH |
15018 | } |
15019 | ||
252b5132 | 15020 | static void |
26ca5450 | 15021 | OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 15022 | { |
9b60702d | 15023 | int add; |
161a04f6 L |
15024 | USED_REX (REX_R); |
15025 | if (rex & REX_R) | |
52b15da3 | 15026 | add = 8; |
9b60702d L |
15027 | else |
15028 | add = 0; | |
d708bcba | 15029 | if (intel_syntax) |
7967e09e | 15030 | sprintf (scratchbuf, "db%d", modrm.reg + add); |
d708bcba | 15031 | else |
7967e09e | 15032 | sprintf (scratchbuf, "%%db%d", modrm.reg + add); |
252b5132 RH |
15033 | oappend (scratchbuf); |
15034 | } | |
15035 | ||
252b5132 | 15036 | static void |
26ca5450 | 15037 | OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 15038 | { |
7967e09e | 15039 | sprintf (scratchbuf, "%%tr%d", modrm.reg); |
9ce09ba2 | 15040 | oappend_maybe_intel (scratchbuf); |
252b5132 RH |
15041 | } |
15042 | ||
15043 | static void | |
6f74c397 | 15044 | OP_R (int bytemode, int sizeflag) |
252b5132 | 15045 | { |
68f34464 L |
15046 | /* Skip mod/rm byte. */ |
15047 | MODRM_CHECK; | |
15048 | codep++; | |
15049 | OP_E_register (bytemode, sizeflag); | |
252b5132 RH |
15050 | } |
15051 | ||
15052 | static void | |
26ca5450 | 15053 | OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 15054 | { |
b9733481 L |
15055 | int reg = modrm.reg; |
15056 | const char **names; | |
15057 | ||
041bd2e0 JH |
15058 | used_prefixes |= (prefixes & PREFIX_DATA); |
15059 | if (prefixes & PREFIX_DATA) | |
20f0a1fc | 15060 | { |
b9733481 | 15061 | names = names_xmm; |
161a04f6 L |
15062 | USED_REX (REX_R); |
15063 | if (rex & REX_R) | |
b9733481 | 15064 | reg += 8; |
20f0a1fc | 15065 | } |
041bd2e0 | 15066 | else |
b9733481 L |
15067 | names = names_mm; |
15068 | oappend (names[reg]); | |
252b5132 RH |
15069 | } |
15070 | ||
c608c12e | 15071 | static void |
c0f3af97 | 15072 | OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED) |
c608c12e | 15073 | { |
b9733481 L |
15074 | int reg = modrm.reg; |
15075 | const char **names; | |
15076 | ||
161a04f6 L |
15077 | USED_REX (REX_R); |
15078 | if (rex & REX_R) | |
b9733481 | 15079 | reg += 8; |
43234a1e L |
15080 | if (vex.evex) |
15081 | { | |
15082 | if (!vex.r) | |
15083 | reg += 16; | |
15084 | } | |
15085 | ||
539f890d L |
15086 | if (need_vex |
15087 | && bytemode != xmm_mode | |
43234a1e L |
15088 | && bytemode != xmmq_mode |
15089 | && bytemode != evex_half_bcst_xmmq_mode | |
15090 | && bytemode != ymm_mode | |
539f890d | 15091 | && bytemode != scalar_mode) |
c0f3af97 L |
15092 | { |
15093 | switch (vex.length) | |
15094 | { | |
15095 | case 128: | |
b9733481 | 15096 | names = names_xmm; |
c0f3af97 L |
15097 | break; |
15098 | case 256: | |
5fc35d96 IT |
15099 | if (vex.w |
15100 | || (bytemode != vex_vsib_q_w_dq_mode | |
15101 | && bytemode != vex_vsib_q_w_d_mode)) | |
6c30d220 L |
15102 | names = names_ymm; |
15103 | else | |
15104 | names = names_xmm; | |
c0f3af97 | 15105 | break; |
43234a1e L |
15106 | case 512: |
15107 | names = names_zmm; | |
15108 | break; | |
c0f3af97 L |
15109 | default: |
15110 | abort (); | |
15111 | } | |
15112 | } | |
43234a1e L |
15113 | else if (bytemode == xmmq_mode |
15114 | || bytemode == evex_half_bcst_xmmq_mode) | |
15115 | { | |
15116 | switch (vex.length) | |
15117 | { | |
15118 | case 128: | |
15119 | case 256: | |
15120 | names = names_xmm; | |
15121 | break; | |
15122 | case 512: | |
15123 | names = names_ymm; | |
15124 | break; | |
15125 | default: | |
15126 | abort (); | |
15127 | } | |
15128 | } | |
15129 | else if (bytemode == ymm_mode) | |
15130 | names = names_ymm; | |
c0f3af97 | 15131 | else |
b9733481 L |
15132 | names = names_xmm; |
15133 | oappend (names[reg]); | |
c608c12e AM |
15134 | } |
15135 | ||
252b5132 | 15136 | static void |
26ca5450 | 15137 | OP_EM (int bytemode, int sizeflag) |
252b5132 | 15138 | { |
b9733481 L |
15139 | int reg; |
15140 | const char **names; | |
15141 | ||
7967e09e | 15142 | if (modrm.mod != 3) |
252b5132 | 15143 | { |
b6169b20 L |
15144 | if (intel_syntax |
15145 | && (bytemode == v_mode || bytemode == v_swap_mode)) | |
9306ca4a JB |
15146 | { |
15147 | bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode; | |
15148 | used_prefixes |= (prefixes & PREFIX_DATA); | |
6c067bbb | 15149 | } |
252b5132 RH |
15150 | OP_E (bytemode, sizeflag); |
15151 | return; | |
15152 | } | |
15153 | ||
b6169b20 L |
15154 | if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode) |
15155 | swap_operand (); | |
15156 | ||
6608db57 | 15157 | /* Skip mod/rm byte. */ |
4bba6815 | 15158 | MODRM_CHECK; |
252b5132 | 15159 | codep++; |
041bd2e0 | 15160 | used_prefixes |= (prefixes & PREFIX_DATA); |
b9733481 | 15161 | reg = modrm.rm; |
041bd2e0 | 15162 | if (prefixes & PREFIX_DATA) |
20f0a1fc | 15163 | { |
b9733481 | 15164 | names = names_xmm; |
161a04f6 L |
15165 | USED_REX (REX_B); |
15166 | if (rex & REX_B) | |
b9733481 | 15167 | reg += 8; |
20f0a1fc | 15168 | } |
041bd2e0 | 15169 | else |
b9733481 L |
15170 | names = names_mm; |
15171 | oappend (names[reg]); | |
252b5132 RH |
15172 | } |
15173 | ||
246c51aa L |
15174 | /* cvt* are the only instructions in sse2 which have |
15175 | both SSE and MMX operands and also have 0x66 prefix | |
15176 | in their opcode. 0x66 was originally used to differentiate | |
15177 | between SSE and MMX instruction(operands). So we have to handle the | |
4d9567e0 MM |
15178 | cvt* separately using OP_EMC and OP_MXC */ |
15179 | static void | |
15180 | OP_EMC (int bytemode, int sizeflag) | |
15181 | { | |
7967e09e | 15182 | if (modrm.mod != 3) |
4d9567e0 MM |
15183 | { |
15184 | if (intel_syntax && bytemode == v_mode) | |
15185 | { | |
15186 | bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode; | |
15187 | used_prefixes |= (prefixes & PREFIX_DATA); | |
6c067bbb | 15188 | } |
4d9567e0 MM |
15189 | OP_E (bytemode, sizeflag); |
15190 | return; | |
15191 | } | |
246c51aa | 15192 | |
4d9567e0 MM |
15193 | /* Skip mod/rm byte. */ |
15194 | MODRM_CHECK; | |
15195 | codep++; | |
15196 | used_prefixes |= (prefixes & PREFIX_DATA); | |
b9733481 | 15197 | oappend (names_mm[modrm.rm]); |
4d9567e0 MM |
15198 | } |
15199 | ||
15200 | static void | |
15201 | OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
15202 | { | |
15203 | used_prefixes |= (prefixes & PREFIX_DATA); | |
b9733481 | 15204 | oappend (names_mm[modrm.reg]); |
4d9567e0 MM |
15205 | } |
15206 | ||
c608c12e | 15207 | static void |
26ca5450 | 15208 | OP_EX (int bytemode, int sizeflag) |
c608c12e | 15209 | { |
b9733481 L |
15210 | int reg; |
15211 | const char **names; | |
d6f574e0 L |
15212 | |
15213 | /* Skip mod/rm byte. */ | |
15214 | MODRM_CHECK; | |
15215 | codep++; | |
15216 | ||
7967e09e | 15217 | if (modrm.mod != 3) |
c608c12e | 15218 | { |
c1e679ec | 15219 | OP_E_memory (bytemode, sizeflag); |
c608c12e AM |
15220 | return; |
15221 | } | |
d6f574e0 | 15222 | |
b9733481 | 15223 | reg = modrm.rm; |
161a04f6 L |
15224 | USED_REX (REX_B); |
15225 | if (rex & REX_B) | |
b9733481 | 15226 | reg += 8; |
43234a1e L |
15227 | if (vex.evex) |
15228 | { | |
15229 | USED_REX (REX_X); | |
15230 | if ((rex & REX_X)) | |
15231 | reg += 16; | |
15232 | } | |
c608c12e | 15233 | |
b6169b20 | 15234 | if ((sizeflag & SUFFIX_ALWAYS) |
fa99fab2 L |
15235 | && (bytemode == x_swap_mode |
15236 | || bytemode == d_swap_mode | |
7bb15c6f | 15237 | || bytemode == d_scalar_swap_mode |
539f890d L |
15238 | || bytemode == q_swap_mode |
15239 | || bytemode == q_scalar_swap_mode)) | |
b6169b20 L |
15240 | swap_operand (); |
15241 | ||
c0f3af97 L |
15242 | if (need_vex |
15243 | && bytemode != xmm_mode | |
6c30d220 L |
15244 | && bytemode != xmmdw_mode |
15245 | && bytemode != xmmqd_mode | |
15246 | && bytemode != xmm_mb_mode | |
15247 | && bytemode != xmm_mw_mode | |
15248 | && bytemode != xmm_md_mode | |
15249 | && bytemode != xmm_mq_mode | |
539f890d | 15250 | && bytemode != xmmq_mode |
43234a1e L |
15251 | && bytemode != evex_half_bcst_xmmq_mode |
15252 | && bytemode != ymm_mode | |
7bb15c6f | 15253 | && bytemode != d_scalar_swap_mode |
1c480963 L |
15254 | && bytemode != q_scalar_swap_mode |
15255 | && bytemode != vex_scalar_w_dq_mode) | |
c0f3af97 L |
15256 | { |
15257 | switch (vex.length) | |
15258 | { | |
15259 | case 128: | |
b9733481 | 15260 | names = names_xmm; |
c0f3af97 L |
15261 | break; |
15262 | case 256: | |
b9733481 | 15263 | names = names_ymm; |
c0f3af97 | 15264 | break; |
43234a1e L |
15265 | case 512: |
15266 | names = names_zmm; | |
15267 | break; | |
c0f3af97 L |
15268 | default: |
15269 | abort (); | |
15270 | } | |
15271 | } | |
43234a1e L |
15272 | else if (bytemode == xmmq_mode |
15273 | || bytemode == evex_half_bcst_xmmq_mode) | |
15274 | { | |
15275 | switch (vex.length) | |
15276 | { | |
15277 | case 128: | |
15278 | case 256: | |
15279 | names = names_xmm; | |
15280 | break; | |
15281 | case 512: | |
15282 | names = names_ymm; | |
15283 | break; | |
15284 | default: | |
15285 | abort (); | |
15286 | } | |
15287 | } | |
15288 | else if (bytemode == ymm_mode) | |
15289 | names = names_ymm; | |
c0f3af97 | 15290 | else |
b9733481 L |
15291 | names = names_xmm; |
15292 | oappend (names[reg]); | |
c608c12e AM |
15293 | } |
15294 | ||
252b5132 | 15295 | static void |
26ca5450 | 15296 | OP_MS (int bytemode, int sizeflag) |
252b5132 | 15297 | { |
7967e09e | 15298 | if (modrm.mod == 3) |
2da11e11 AM |
15299 | OP_EM (bytemode, sizeflag); |
15300 | else | |
6608db57 | 15301 | BadOp (); |
252b5132 RH |
15302 | } |
15303 | ||
992aaec9 | 15304 | static void |
26ca5450 | 15305 | OP_XS (int bytemode, int sizeflag) |
992aaec9 | 15306 | { |
7967e09e | 15307 | if (modrm.mod == 3) |
992aaec9 AM |
15308 | OP_EX (bytemode, sizeflag); |
15309 | else | |
6608db57 | 15310 | BadOp (); |
992aaec9 AM |
15311 | } |
15312 | ||
cc0ec051 AM |
15313 | static void |
15314 | OP_M (int bytemode, int sizeflag) | |
15315 | { | |
7967e09e | 15316 | if (modrm.mod == 3) |
75413a22 L |
15317 | /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */ |
15318 | BadOp (); | |
cc0ec051 AM |
15319 | else |
15320 | OP_E (bytemode, sizeflag); | |
15321 | } | |
15322 | ||
15323 | static void | |
15324 | OP_0f07 (int bytemode, int sizeflag) | |
15325 | { | |
7967e09e | 15326 | if (modrm.mod != 3 || modrm.rm != 0) |
cc0ec051 AM |
15327 | BadOp (); |
15328 | else | |
15329 | OP_E (bytemode, sizeflag); | |
15330 | } | |
15331 | ||
46e883c5 | 15332 | /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in |
246c51aa | 15333 | 32bit mode and "xchg %rax,%rax" in 64bit mode. */ |
46e883c5 | 15334 | |
cc0ec051 | 15335 | static void |
46e883c5 | 15336 | NOP_Fixup1 (int bytemode, int sizeflag) |
cc0ec051 | 15337 | { |
8b38ad71 L |
15338 | if ((prefixes & PREFIX_DATA) != 0 |
15339 | || (rex != 0 | |
15340 | && rex != 0x48 | |
15341 | && address_mode == mode_64bit)) | |
46e883c5 L |
15342 | OP_REG (bytemode, sizeflag); |
15343 | else | |
15344 | strcpy (obuf, "nop"); | |
15345 | } | |
15346 | ||
15347 | static void | |
15348 | NOP_Fixup2 (int bytemode, int sizeflag) | |
15349 | { | |
8b38ad71 L |
15350 | if ((prefixes & PREFIX_DATA) != 0 |
15351 | || (rex != 0 | |
15352 | && rex != 0x48 | |
15353 | && address_mode == mode_64bit)) | |
46e883c5 | 15354 | OP_IMREG (bytemode, sizeflag); |
cc0ec051 AM |
15355 | } |
15356 | ||
84037f8c | 15357 | static const char *const Suffix3DNow[] = { |
252b5132 RH |
15358 | /* 00 */ NULL, NULL, NULL, NULL, |
15359 | /* 04 */ NULL, NULL, NULL, NULL, | |
15360 | /* 08 */ NULL, NULL, NULL, NULL, | |
9e525108 | 15361 | /* 0C */ "pi2fw", "pi2fd", NULL, NULL, |
252b5132 RH |
15362 | /* 10 */ NULL, NULL, NULL, NULL, |
15363 | /* 14 */ NULL, NULL, NULL, NULL, | |
15364 | /* 18 */ NULL, NULL, NULL, NULL, | |
9e525108 | 15365 | /* 1C */ "pf2iw", "pf2id", NULL, NULL, |
252b5132 RH |
15366 | /* 20 */ NULL, NULL, NULL, NULL, |
15367 | /* 24 */ NULL, NULL, NULL, NULL, | |
15368 | /* 28 */ NULL, NULL, NULL, NULL, | |
15369 | /* 2C */ NULL, NULL, NULL, NULL, | |
15370 | /* 30 */ NULL, NULL, NULL, NULL, | |
15371 | /* 34 */ NULL, NULL, NULL, NULL, | |
15372 | /* 38 */ NULL, NULL, NULL, NULL, | |
15373 | /* 3C */ NULL, NULL, NULL, NULL, | |
15374 | /* 40 */ NULL, NULL, NULL, NULL, | |
15375 | /* 44 */ NULL, NULL, NULL, NULL, | |
15376 | /* 48 */ NULL, NULL, NULL, NULL, | |
15377 | /* 4C */ NULL, NULL, NULL, NULL, | |
15378 | /* 50 */ NULL, NULL, NULL, NULL, | |
15379 | /* 54 */ NULL, NULL, NULL, NULL, | |
15380 | /* 58 */ NULL, NULL, NULL, NULL, | |
15381 | /* 5C */ NULL, NULL, NULL, NULL, | |
15382 | /* 60 */ NULL, NULL, NULL, NULL, | |
15383 | /* 64 */ NULL, NULL, NULL, NULL, | |
15384 | /* 68 */ NULL, NULL, NULL, NULL, | |
15385 | /* 6C */ NULL, NULL, NULL, NULL, | |
15386 | /* 70 */ NULL, NULL, NULL, NULL, | |
15387 | /* 74 */ NULL, NULL, NULL, NULL, | |
15388 | /* 78 */ NULL, NULL, NULL, NULL, | |
15389 | /* 7C */ NULL, NULL, NULL, NULL, | |
15390 | /* 80 */ NULL, NULL, NULL, NULL, | |
15391 | /* 84 */ NULL, NULL, NULL, NULL, | |
9e525108 AM |
15392 | /* 88 */ NULL, NULL, "pfnacc", NULL, |
15393 | /* 8C */ NULL, NULL, "pfpnacc", NULL, | |
252b5132 RH |
15394 | /* 90 */ "pfcmpge", NULL, NULL, NULL, |
15395 | /* 94 */ "pfmin", NULL, "pfrcp", "pfrsqrt", | |
15396 | /* 98 */ NULL, NULL, "pfsub", NULL, | |
15397 | /* 9C */ NULL, NULL, "pfadd", NULL, | |
15398 | /* A0 */ "pfcmpgt", NULL, NULL, NULL, | |
15399 | /* A4 */ "pfmax", NULL, "pfrcpit1", "pfrsqit1", | |
15400 | /* A8 */ NULL, NULL, "pfsubr", NULL, | |
15401 | /* AC */ NULL, NULL, "pfacc", NULL, | |
15402 | /* B0 */ "pfcmpeq", NULL, NULL, NULL, | |
9beff690 | 15403 | /* B4 */ "pfmul", NULL, "pfrcpit2", "pmulhrw", |
9e525108 | 15404 | /* B8 */ NULL, NULL, NULL, "pswapd", |
252b5132 RH |
15405 | /* BC */ NULL, NULL, NULL, "pavgusb", |
15406 | /* C0 */ NULL, NULL, NULL, NULL, | |
15407 | /* C4 */ NULL, NULL, NULL, NULL, | |
15408 | /* C8 */ NULL, NULL, NULL, NULL, | |
15409 | /* CC */ NULL, NULL, NULL, NULL, | |
15410 | /* D0 */ NULL, NULL, NULL, NULL, | |
15411 | /* D4 */ NULL, NULL, NULL, NULL, | |
15412 | /* D8 */ NULL, NULL, NULL, NULL, | |
15413 | /* DC */ NULL, NULL, NULL, NULL, | |
15414 | /* E0 */ NULL, NULL, NULL, NULL, | |
15415 | /* E4 */ NULL, NULL, NULL, NULL, | |
15416 | /* E8 */ NULL, NULL, NULL, NULL, | |
15417 | /* EC */ NULL, NULL, NULL, NULL, | |
15418 | /* F0 */ NULL, NULL, NULL, NULL, | |
15419 | /* F4 */ NULL, NULL, NULL, NULL, | |
15420 | /* F8 */ NULL, NULL, NULL, NULL, | |
15421 | /* FC */ NULL, NULL, NULL, NULL, | |
15422 | }; | |
15423 | ||
15424 | static void | |
26ca5450 | 15425 | OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 RH |
15426 | { |
15427 | const char *mnemonic; | |
15428 | ||
15429 | FETCH_DATA (the_info, codep + 1); | |
15430 | /* AMD 3DNow! instructions are specified by an opcode suffix in the | |
15431 | place where an 8-bit immediate would normally go. ie. the last | |
15432 | byte of the instruction. */ | |
ea397f5b | 15433 | obufp = mnemonicendp; |
c608c12e | 15434 | mnemonic = Suffix3DNow[*codep++ & 0xff]; |
252b5132 | 15435 | if (mnemonic) |
2da11e11 | 15436 | oappend (mnemonic); |
252b5132 RH |
15437 | else |
15438 | { | |
15439 | /* Since a variable sized modrm/sib chunk is between the start | |
15440 | of the opcode (0x0f0f) and the opcode suffix, we need to do | |
15441 | all the modrm processing first, and don't know until now that | |
15442 | we have a bad opcode. This necessitates some cleaning up. */ | |
ce518a5f L |
15443 | op_out[0][0] = '\0'; |
15444 | op_out[1][0] = '\0'; | |
6608db57 | 15445 | BadOp (); |
252b5132 | 15446 | } |
ea397f5b | 15447 | mnemonicendp = obufp; |
252b5132 | 15448 | } |
c608c12e | 15449 | |
ea397f5b L |
15450 | static struct op simd_cmp_op[] = |
15451 | { | |
15452 | { STRING_COMMA_LEN ("eq") }, | |
15453 | { STRING_COMMA_LEN ("lt") }, | |
15454 | { STRING_COMMA_LEN ("le") }, | |
15455 | { STRING_COMMA_LEN ("unord") }, | |
15456 | { STRING_COMMA_LEN ("neq") }, | |
15457 | { STRING_COMMA_LEN ("nlt") }, | |
15458 | { STRING_COMMA_LEN ("nle") }, | |
15459 | { STRING_COMMA_LEN ("ord") } | |
c608c12e AM |
15460 | }; |
15461 | ||
15462 | static void | |
ad19981d | 15463 | CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
c608c12e AM |
15464 | { |
15465 | unsigned int cmp_type; | |
15466 | ||
15467 | FETCH_DATA (the_info, codep + 1); | |
15468 | cmp_type = *codep++ & 0xff; | |
c0f3af97 | 15469 | if (cmp_type < ARRAY_SIZE (simd_cmp_op)) |
c608c12e | 15470 | { |
ad19981d | 15471 | char suffix [3]; |
ea397f5b | 15472 | char *p = mnemonicendp - 2; |
ad19981d L |
15473 | suffix[0] = p[0]; |
15474 | suffix[1] = p[1]; | |
15475 | suffix[2] = '\0'; | |
ea397f5b L |
15476 | sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix); |
15477 | mnemonicendp += simd_cmp_op[cmp_type].len; | |
c608c12e AM |
15478 | } |
15479 | else | |
15480 | { | |
ad19981d L |
15481 | /* We have a reserved extension byte. Output it directly. */ |
15482 | scratchbuf[0] = '$'; | |
15483 | print_operand_value (scratchbuf + 1, 1, cmp_type); | |
9ce09ba2 | 15484 | oappend_maybe_intel (scratchbuf); |
ad19981d | 15485 | scratchbuf[0] = '\0'; |
c608c12e AM |
15486 | } |
15487 | } | |
15488 | ||
9916071f | 15489 | static void |
7abb8d81 | 15490 | OP_Mwait (int bytemode, int sizeflag ATTRIBUTE_UNUSED) |
9916071f | 15491 | { |
7abb8d81 | 15492 | /* mwait %eax,%ecx / mwaitx %eax,%ecx,%ebx */ |
b844680a L |
15493 | if (!intel_syntax) |
15494 | { | |
081e283f JB |
15495 | strcpy (op_out[0], names32[0]); |
15496 | strcpy (op_out[1], names32[1]); | |
7abb8d81 | 15497 | if (bytemode == eBX_reg) |
081e283f | 15498 | strcpy (op_out[2], names32[3]); |
b844680a L |
15499 | two_source_ops = 1; |
15500 | } | |
15501 | /* Skip mod/rm byte. */ | |
15502 | MODRM_CHECK; | |
15503 | codep++; | |
15504 | } | |
15505 | ||
15506 | static void | |
15507 | OP_Monitor (int bytemode ATTRIBUTE_UNUSED, | |
15508 | int sizeflag ATTRIBUTE_UNUSED) | |
ca164297 | 15509 | { |
081e283f | 15510 | /* monitor %{e,r,}ax,%ecx,%edx" */ |
b844680a | 15511 | if (!intel_syntax) |
ca164297 | 15512 | { |
cb712a9e L |
15513 | const char **names = (address_mode == mode_64bit |
15514 | ? names64 : names32); | |
1d9f512f | 15515 | |
081e283f | 15516 | if (prefixes & PREFIX_ADDR) |
ca164297 | 15517 | { |
b844680a | 15518 | /* Remove "addr16/addr32". */ |
f16cd0d5 | 15519 | all_prefixes[last_addr_prefix] = 0; |
081e283f JB |
15520 | names = (address_mode != mode_32bit |
15521 | ? names32 : names16); | |
b844680a | 15522 | used_prefixes |= PREFIX_ADDR; |
ca164297 | 15523 | } |
081e283f JB |
15524 | else if (address_mode == mode_16bit) |
15525 | names = names16; | |
15526 | strcpy (op_out[0], names[0]); | |
15527 | strcpy (op_out[1], names32[1]); | |
15528 | strcpy (op_out[2], names32[2]); | |
b844680a | 15529 | two_source_ops = 1; |
ca164297 | 15530 | } |
b844680a L |
15531 | /* Skip mod/rm byte. */ |
15532 | MODRM_CHECK; | |
15533 | codep++; | |
30123838 JB |
15534 | } |
15535 | ||
6608db57 KH |
15536 | static void |
15537 | BadOp (void) | |
2da11e11 | 15538 | { |
6608db57 KH |
15539 | /* Throw away prefixes and 1st. opcode byte. */ |
15540 | codep = insn_codep + 1; | |
2da11e11 AM |
15541 | oappend ("(bad)"); |
15542 | } | |
4cc91dba | 15543 | |
35c52694 L |
15544 | static void |
15545 | REP_Fixup (int bytemode, int sizeflag) | |
15546 | { | |
15547 | /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs, | |
15548 | lods and stos. */ | |
35c52694 | 15549 | if (prefixes & PREFIX_REPZ) |
f16cd0d5 | 15550 | all_prefixes[last_repz_prefix] = REP_PREFIX; |
35c52694 L |
15551 | |
15552 | switch (bytemode) | |
15553 | { | |
15554 | case al_reg: | |
15555 | case eAX_reg: | |
15556 | case indir_dx_reg: | |
15557 | OP_IMREG (bytemode, sizeflag); | |
15558 | break; | |
15559 | case eDI_reg: | |
15560 | OP_ESreg (bytemode, sizeflag); | |
15561 | break; | |
15562 | case eSI_reg: | |
15563 | OP_DSreg (bytemode, sizeflag); | |
15564 | break; | |
15565 | default: | |
15566 | abort (); | |
15567 | break; | |
15568 | } | |
15569 | } | |
f5804c90 | 15570 | |
d835a58b JB |
15571 | static void |
15572 | SEP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
15573 | { | |
15574 | if ( isa64 != amd64 ) | |
15575 | return; | |
15576 | ||
15577 | obufp = obuf; | |
15578 | BadOp (); | |
15579 | mnemonicendp = obufp; | |
15580 | ++codep; | |
15581 | } | |
15582 | ||
7e8b059b L |
15583 | /* For BND-prefixed instructions 0xF2 prefix should be displayed as |
15584 | "bnd". */ | |
15585 | ||
15586 | static void | |
15587 | BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
15588 | { | |
15589 | if (prefixes & PREFIX_REPNZ) | |
15590 | all_prefixes[last_repnz_prefix] = BND_PREFIX; | |
15591 | } | |
15592 | ||
04ef582a L |
15593 | /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as |
15594 | "notrack". */ | |
15595 | ||
15596 | static void | |
15597 | NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED, | |
15598 | int sizeflag ATTRIBUTE_UNUSED) | |
15599 | { | |
9fef80d6 | 15600 | if (active_seg_prefix == PREFIX_DS |
04ef582a L |
15601 | && (address_mode != mode_64bit || last_data_prefix < 0)) |
15602 | { | |
4e9ac44a | 15603 | /* NOTRACK prefix is only valid on indirect branch instructions. |
9fef80d6 | 15604 | NB: DATA prefix is unsupported for Intel64. */ |
04ef582a L |
15605 | active_seg_prefix = 0; |
15606 | all_prefixes[last_seg_prefix] = NOTRACK_PREFIX; | |
15607 | } | |
15608 | } | |
15609 | ||
42164a71 L |
15610 | /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as |
15611 | "xacquire"/"xrelease" for memory operand if there is a LOCK prefix. | |
15612 | */ | |
15613 | ||
15614 | static void | |
15615 | HLE_Fixup1 (int bytemode, int sizeflag) | |
15616 | { | |
15617 | if (modrm.mod != 3 | |
15618 | && (prefixes & PREFIX_LOCK) != 0) | |
15619 | { | |
15620 | if (prefixes & PREFIX_REPZ) | |
15621 | all_prefixes[last_repz_prefix] = XRELEASE_PREFIX; | |
15622 | if (prefixes & PREFIX_REPNZ) | |
15623 | all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX; | |
15624 | } | |
15625 | ||
15626 | OP_E (bytemode, sizeflag); | |
15627 | } | |
15628 | ||
15629 | /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as | |
15630 | "xacquire"/"xrelease" for memory operand. No check for LOCK prefix. | |
15631 | */ | |
15632 | ||
15633 | static void | |
15634 | HLE_Fixup2 (int bytemode, int sizeflag) | |
15635 | { | |
15636 | if (modrm.mod != 3) | |
15637 | { | |
15638 | if (prefixes & PREFIX_REPZ) | |
15639 | all_prefixes[last_repz_prefix] = XRELEASE_PREFIX; | |
15640 | if (prefixes & PREFIX_REPNZ) | |
15641 | all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX; | |
15642 | } | |
15643 | ||
15644 | OP_E (bytemode, sizeflag); | |
15645 | } | |
15646 | ||
15647 | /* Similar to OP_E. But the 0xf3 prefixes should be displayed as | |
15648 | "xrelease" for memory operand. No check for LOCK prefix. */ | |
15649 | ||
15650 | static void | |
15651 | HLE_Fixup3 (int bytemode, int sizeflag) | |
15652 | { | |
15653 | if (modrm.mod != 3 | |
15654 | && last_repz_prefix > last_repnz_prefix | |
15655 | && (prefixes & PREFIX_REPZ) != 0) | |
15656 | all_prefixes[last_repz_prefix] = XRELEASE_PREFIX; | |
15657 | ||
15658 | OP_E (bytemode, sizeflag); | |
15659 | } | |
15660 | ||
f5804c90 L |
15661 | static void |
15662 | CMPXCHG8B_Fixup (int bytemode, int sizeflag) | |
15663 | { | |
161a04f6 L |
15664 | USED_REX (REX_W); |
15665 | if (rex & REX_W) | |
f5804c90 L |
15666 | { |
15667 | /* Change cmpxchg8b to cmpxchg16b. */ | |
ea397f5b L |
15668 | char *p = mnemonicendp - 2; |
15669 | mnemonicendp = stpcpy (p, "16b"); | |
fb9c77c7 | 15670 | bytemode = o_mode; |
f5804c90 | 15671 | } |
42164a71 L |
15672 | else if ((prefixes & PREFIX_LOCK) != 0) |
15673 | { | |
15674 | if (prefixes & PREFIX_REPZ) | |
15675 | all_prefixes[last_repz_prefix] = XRELEASE_PREFIX; | |
15676 | if (prefixes & PREFIX_REPNZ) | |
15677 | all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX; | |
15678 | } | |
15679 | ||
f5804c90 L |
15680 | OP_M (bytemode, sizeflag); |
15681 | } | |
42903f7f L |
15682 | |
15683 | static void | |
15684 | XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED) | |
15685 | { | |
b9733481 L |
15686 | const char **names; |
15687 | ||
c0f3af97 L |
15688 | if (need_vex) |
15689 | { | |
15690 | switch (vex.length) | |
15691 | { | |
15692 | case 128: | |
b9733481 | 15693 | names = names_xmm; |
c0f3af97 L |
15694 | break; |
15695 | case 256: | |
b9733481 | 15696 | names = names_ymm; |
c0f3af97 L |
15697 | break; |
15698 | default: | |
15699 | abort (); | |
15700 | } | |
15701 | } | |
15702 | else | |
b9733481 L |
15703 | names = names_xmm; |
15704 | oappend (names[reg]); | |
42903f7f | 15705 | } |
381d071f L |
15706 | |
15707 | static void | |
15708 | CRC32_Fixup (int bytemode, int sizeflag) | |
15709 | { | |
15710 | /* Add proper suffix to "crc32". */ | |
ea397f5b | 15711 | char *p = mnemonicendp; |
381d071f L |
15712 | |
15713 | switch (bytemode) | |
15714 | { | |
15715 | case b_mode: | |
20592a94 | 15716 | if (intel_syntax) |
ea397f5b | 15717 | goto skip; |
20592a94 | 15718 | |
381d071f L |
15719 | *p++ = 'b'; |
15720 | break; | |
15721 | case v_mode: | |
20592a94 | 15722 | if (intel_syntax) |
ea397f5b | 15723 | goto skip; |
20592a94 | 15724 | |
381d071f L |
15725 | USED_REX (REX_W); |
15726 | if (rex & REX_W) | |
15727 | *p++ = 'q'; | |
7bb15c6f | 15728 | else |
f16cd0d5 L |
15729 | { |
15730 | if (sizeflag & DFLAG) | |
15731 | *p++ = 'l'; | |
15732 | else | |
15733 | *p++ = 'w'; | |
15734 | used_prefixes |= (prefixes & PREFIX_DATA); | |
15735 | } | |
381d071f L |
15736 | break; |
15737 | default: | |
15738 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
15739 | break; | |
15740 | } | |
ea397f5b | 15741 | mnemonicendp = p; |
381d071f L |
15742 | *p = '\0'; |
15743 | ||
dc1e8a47 | 15744 | skip: |
381d071f L |
15745 | if (modrm.mod == 3) |
15746 | { | |
15747 | int add; | |
15748 | ||
15749 | /* Skip mod/rm byte. */ | |
15750 | MODRM_CHECK; | |
15751 | codep++; | |
15752 | ||
15753 | USED_REX (REX_B); | |
15754 | add = (rex & REX_B) ? 8 : 0; | |
15755 | if (bytemode == b_mode) | |
15756 | { | |
15757 | USED_REX (0); | |
15758 | if (rex) | |
15759 | oappend (names8rex[modrm.rm + add]); | |
15760 | else | |
15761 | oappend (names8[modrm.rm + add]); | |
15762 | } | |
15763 | else | |
15764 | { | |
15765 | USED_REX (REX_W); | |
15766 | if (rex & REX_W) | |
15767 | oappend (names64[modrm.rm + add]); | |
15768 | else if ((prefixes & PREFIX_DATA)) | |
15769 | oappend (names16[modrm.rm + add]); | |
15770 | else | |
15771 | oappend (names32[modrm.rm + add]); | |
15772 | } | |
15773 | } | |
15774 | else | |
9344ff29 | 15775 | OP_E (bytemode, sizeflag); |
381d071f | 15776 | } |
85f10a01 | 15777 | |
eacc9c89 L |
15778 | static void |
15779 | FXSAVE_Fixup (int bytemode, int sizeflag) | |
15780 | { | |
15781 | /* Add proper suffix to "fxsave" and "fxrstor". */ | |
15782 | USED_REX (REX_W); | |
15783 | if (rex & REX_W) | |
15784 | { | |
15785 | char *p = mnemonicendp; | |
15786 | *p++ = '6'; | |
15787 | *p++ = '4'; | |
15788 | *p = '\0'; | |
15789 | mnemonicendp = p; | |
15790 | } | |
15791 | OP_M (bytemode, sizeflag); | |
15792 | } | |
15793 | ||
15c7c1d8 JB |
15794 | static void |
15795 | PCMPESTR_Fixup (int bytemode, int sizeflag) | |
15796 | { | |
15797 | /* Add proper suffix to "{,v}pcmpestr{i,m}". */ | |
15798 | if (!intel_syntax) | |
15799 | { | |
15800 | char *p = mnemonicendp; | |
15801 | ||
15802 | USED_REX (REX_W); | |
15803 | if (rex & REX_W) | |
15804 | *p++ = 'q'; | |
15805 | else if (sizeflag & SUFFIX_ALWAYS) | |
15806 | *p++ = 'l'; | |
15807 | ||
15808 | *p = '\0'; | |
15809 | mnemonicendp = p; | |
15810 | } | |
15811 | ||
15812 | OP_EX (bytemode, sizeflag); | |
15813 | } | |
15814 | ||
c0f3af97 L |
15815 | /* Display the destination register operand for instructions with |
15816 | VEX. */ | |
15817 | ||
15818 | static void | |
15819 | OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED) | |
15820 | { | |
539f890d | 15821 | int reg; |
b9733481 L |
15822 | const char **names; |
15823 | ||
c0f3af97 L |
15824 | if (!need_vex) |
15825 | abort (); | |
15826 | ||
15827 | if (!need_vex_reg) | |
15828 | return; | |
15829 | ||
539f890d | 15830 | reg = vex.register_specifier; |
63c6fc6c | 15831 | vex.register_specifier = 0; |
5f847646 JB |
15832 | if (address_mode != mode_64bit) |
15833 | reg &= 7; | |
15834 | else if (vex.evex && !vex.v) | |
15835 | reg += 16; | |
43234a1e | 15836 | |
539f890d L |
15837 | if (bytemode == vex_scalar_mode) |
15838 | { | |
15839 | oappend (names_xmm[reg]); | |
15840 | return; | |
15841 | } | |
15842 | ||
c0f3af97 L |
15843 | switch (vex.length) |
15844 | { | |
15845 | case 128: | |
15846 | switch (bytemode) | |
15847 | { | |
15848 | case vex_mode: | |
15849 | case vex128_mode: | |
6c30d220 | 15850 | case vex_vsib_q_w_dq_mode: |
5fc35d96 | 15851 | case vex_vsib_q_w_d_mode: |
cb21baef L |
15852 | names = names_xmm; |
15853 | break; | |
15854 | case dq_mode: | |
390a6789 | 15855 | if (rex & REX_W) |
cb21baef L |
15856 | names = names64; |
15857 | else | |
15858 | names = names32; | |
c0f3af97 | 15859 | break; |
1ba585e8 | 15860 | case mask_bd_mode: |
43234a1e | 15861 | case mask_mode: |
9889cbb1 L |
15862 | if (reg > 0x7) |
15863 | { | |
15864 | oappend ("(bad)"); | |
15865 | return; | |
15866 | } | |
43234a1e L |
15867 | names = names_mask; |
15868 | break; | |
c0f3af97 L |
15869 | default: |
15870 | abort (); | |
15871 | return; | |
15872 | } | |
c0f3af97 L |
15873 | break; |
15874 | case 256: | |
15875 | switch (bytemode) | |
15876 | { | |
15877 | case vex_mode: | |
15878 | case vex256_mode: | |
6c30d220 L |
15879 | names = names_ymm; |
15880 | break; | |
15881 | case vex_vsib_q_w_dq_mode: | |
5fc35d96 | 15882 | case vex_vsib_q_w_d_mode: |
6c30d220 | 15883 | names = vex.w ? names_ymm : names_xmm; |
c0f3af97 | 15884 | break; |
1ba585e8 | 15885 | case mask_bd_mode: |
43234a1e | 15886 | case mask_mode: |
9889cbb1 L |
15887 | if (reg > 0x7) |
15888 | { | |
15889 | oappend ("(bad)"); | |
15890 | return; | |
15891 | } | |
43234a1e L |
15892 | names = names_mask; |
15893 | break; | |
c0f3af97 | 15894 | default: |
a37a2806 NC |
15895 | /* See PR binutils/20893 for a reproducer. */ |
15896 | oappend ("(bad)"); | |
c0f3af97 L |
15897 | return; |
15898 | } | |
c0f3af97 | 15899 | break; |
43234a1e L |
15900 | case 512: |
15901 | names = names_zmm; | |
15902 | break; | |
c0f3af97 L |
15903 | default: |
15904 | abort (); | |
15905 | break; | |
15906 | } | |
539f890d | 15907 | oappend (names[reg]); |
c0f3af97 L |
15908 | } |
15909 | ||
922d8de8 DR |
15910 | /* Get the VEX immediate byte without moving codep. */ |
15911 | ||
15912 | static unsigned char | |
ccc5981b | 15913 | get_vex_imm8 (int sizeflag, int opnum) |
922d8de8 DR |
15914 | { |
15915 | int bytes_before_imm = 0; | |
15916 | ||
922d8de8 DR |
15917 | if (modrm.mod != 3) |
15918 | { | |
15919 | /* There are SIB/displacement bytes. */ | |
15920 | if ((sizeflag & AFLAG) || address_mode == mode_64bit) | |
6c067bbb | 15921 | { |
922d8de8 | 15922 | /* 32/64 bit address mode */ |
6c067bbb | 15923 | int base = modrm.rm; |
922d8de8 DR |
15924 | |
15925 | /* Check SIB byte. */ | |
6c067bbb RM |
15926 | if (base == 4) |
15927 | { | |
15928 | FETCH_DATA (the_info, codep + 1); | |
15929 | base = *codep & 7; | |
15930 | /* When decoding the third source, don't increase | |
15931 | bytes_before_imm as this has already been incremented | |
15932 | by one in OP_E_memory while decoding the second | |
15933 | source operand. */ | |
15934 | if (opnum == 0) | |
15935 | bytes_before_imm++; | |
15936 | } | |
15937 | ||
15938 | /* Don't increase bytes_before_imm when decoding the third source, | |
15939 | it has already been incremented by OP_E_memory while decoding | |
15940 | the second source operand. */ | |
15941 | if (opnum == 0) | |
15942 | { | |
15943 | switch (modrm.mod) | |
15944 | { | |
15945 | case 0: | |
15946 | /* When modrm.rm == 5 or modrm.rm == 4 and base in | |
15947 | SIB == 5, there is a 4 byte displacement. */ | |
15948 | if (base != 5) | |
15949 | /* No displacement. */ | |
15950 | break; | |
1a0670f3 | 15951 | /* Fall through. */ |
6c067bbb RM |
15952 | case 2: |
15953 | /* 4 byte displacement. */ | |
15954 | bytes_before_imm += 4; | |
15955 | break; | |
15956 | case 1: | |
15957 | /* 1 byte displacement. */ | |
15958 | bytes_before_imm++; | |
15959 | break; | |
15960 | } | |
15961 | } | |
15962 | } | |
922d8de8 | 15963 | else |
02e647f9 SP |
15964 | { |
15965 | /* 16 bit address mode */ | |
6c067bbb RM |
15966 | /* Don't increase bytes_before_imm when decoding the third source, |
15967 | it has already been incremented by OP_E_memory while decoding | |
15968 | the second source operand. */ | |
15969 | if (opnum == 0) | |
15970 | { | |
02e647f9 SP |
15971 | switch (modrm.mod) |
15972 | { | |
15973 | case 0: | |
15974 | /* When modrm.rm == 6, there is a 2 byte displacement. */ | |
15975 | if (modrm.rm != 6) | |
15976 | /* No displacement. */ | |
15977 | break; | |
1a0670f3 | 15978 | /* Fall through. */ |
02e647f9 SP |
15979 | case 2: |
15980 | /* 2 byte displacement. */ | |
15981 | bytes_before_imm += 2; | |
15982 | break; | |
15983 | case 1: | |
15984 | /* 1 byte displacement: when decoding the third source, | |
15985 | don't increase bytes_before_imm as this has already | |
15986 | been incremented by one in OP_E_memory while decoding | |
15987 | the second source operand. */ | |
15988 | if (opnum == 0) | |
15989 | bytes_before_imm++; | |
ccc5981b | 15990 | |
02e647f9 SP |
15991 | break; |
15992 | } | |
922d8de8 DR |
15993 | } |
15994 | } | |
15995 | } | |
15996 | ||
15997 | FETCH_DATA (the_info, codep + bytes_before_imm + 1); | |
15998 | return codep [bytes_before_imm]; | |
15999 | } | |
16000 | ||
16001 | static void | |
16002 | OP_EX_VexReg (int bytemode, int sizeflag, int reg) | |
16003 | { | |
b9733481 L |
16004 | const char **names; |
16005 | ||
922d8de8 DR |
16006 | if (reg == -1 && modrm.mod != 3) |
16007 | { | |
16008 | OP_E_memory (bytemode, sizeflag); | |
16009 | return; | |
16010 | } | |
16011 | else | |
16012 | { | |
16013 | if (reg == -1) | |
16014 | { | |
16015 | reg = modrm.rm; | |
16016 | USED_REX (REX_B); | |
16017 | if (rex & REX_B) | |
16018 | reg += 8; | |
16019 | } | |
5f847646 JB |
16020 | if (address_mode != mode_64bit) |
16021 | reg &= 7; | |
922d8de8 DR |
16022 | } |
16023 | ||
16024 | switch (vex.length) | |
16025 | { | |
16026 | case 128: | |
b9733481 | 16027 | names = names_xmm; |
922d8de8 DR |
16028 | break; |
16029 | case 256: | |
b9733481 | 16030 | names = names_ymm; |
922d8de8 DR |
16031 | break; |
16032 | default: | |
16033 | abort (); | |
16034 | } | |
b9733481 | 16035 | oappend (names[reg]); |
922d8de8 DR |
16036 | } |
16037 | ||
a683cc34 SP |
16038 | static void |
16039 | OP_EX_VexImmW (int bytemode, int sizeflag) | |
16040 | { | |
16041 | int reg = -1; | |
16042 | static unsigned char vex_imm8; | |
16043 | ||
16044 | if (vex_w_done == 0) | |
16045 | { | |
16046 | vex_w_done = 1; | |
16047 | ||
16048 | /* Skip mod/rm byte. */ | |
16049 | MODRM_CHECK; | |
16050 | codep++; | |
16051 | ||
16052 | vex_imm8 = get_vex_imm8 (sizeflag, 0); | |
16053 | ||
16054 | if (vex.w) | |
16055 | reg = vex_imm8 >> 4; | |
16056 | ||
16057 | OP_EX_VexReg (bytemode, sizeflag, reg); | |
16058 | } | |
16059 | else if (vex_w_done == 1) | |
16060 | { | |
16061 | vex_w_done = 2; | |
16062 | ||
16063 | if (!vex.w) | |
16064 | reg = vex_imm8 >> 4; | |
16065 | ||
16066 | OP_EX_VexReg (bytemode, sizeflag, reg); | |
16067 | } | |
16068 | else | |
16069 | { | |
16070 | /* Output the imm8 directly. */ | |
16071 | scratchbuf[0] = '$'; | |
16072 | print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf); | |
9ce09ba2 | 16073 | oappend_maybe_intel (scratchbuf); |
a683cc34 SP |
16074 | scratchbuf[0] = '\0'; |
16075 | codep++; | |
16076 | } | |
16077 | } | |
16078 | ||
5dd85c99 SP |
16079 | static void |
16080 | OP_Vex_2src (int bytemode, int sizeflag) | |
16081 | { | |
16082 | if (modrm.mod == 3) | |
16083 | { | |
b9733481 | 16084 | int reg = modrm.rm; |
5dd85c99 | 16085 | USED_REX (REX_B); |
b9733481 L |
16086 | if (rex & REX_B) |
16087 | reg += 8; | |
16088 | oappend (names_xmm[reg]); | |
5dd85c99 SP |
16089 | } |
16090 | else | |
16091 | { | |
16092 | if (intel_syntax | |
16093 | && (bytemode == v_mode || bytemode == v_swap_mode)) | |
16094 | { | |
16095 | bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode; | |
16096 | used_prefixes |= (prefixes & PREFIX_DATA); | |
16097 | } | |
16098 | OP_E (bytemode, sizeflag); | |
16099 | } | |
16100 | } | |
16101 | ||
16102 | static void | |
16103 | OP_Vex_2src_1 (int bytemode, int sizeflag) | |
16104 | { | |
16105 | if (modrm.mod == 3) | |
16106 | { | |
16107 | /* Skip mod/rm byte. */ | |
16108 | MODRM_CHECK; | |
16109 | codep++; | |
16110 | } | |
16111 | ||
16112 | if (vex.w) | |
5f847646 JB |
16113 | { |
16114 | unsigned int reg = vex.register_specifier; | |
63c6fc6c | 16115 | vex.register_specifier = 0; |
5f847646 JB |
16116 | |
16117 | if (address_mode != mode_64bit) | |
16118 | reg &= 7; | |
16119 | oappend (names_xmm[reg]); | |
16120 | } | |
5dd85c99 SP |
16121 | else |
16122 | OP_Vex_2src (bytemode, sizeflag); | |
16123 | } | |
16124 | ||
16125 | static void | |
16126 | OP_Vex_2src_2 (int bytemode, int sizeflag) | |
16127 | { | |
16128 | if (vex.w) | |
16129 | OP_Vex_2src (bytemode, sizeflag); | |
16130 | else | |
5f847646 JB |
16131 | { |
16132 | unsigned int reg = vex.register_specifier; | |
63c6fc6c | 16133 | vex.register_specifier = 0; |
5f847646 JB |
16134 | |
16135 | if (address_mode != mode_64bit) | |
16136 | reg &= 7; | |
16137 | oappend (names_xmm[reg]); | |
16138 | } | |
5dd85c99 SP |
16139 | } |
16140 | ||
922d8de8 DR |
16141 | static void |
16142 | OP_EX_VexW (int bytemode, int sizeflag) | |
16143 | { | |
16144 | int reg = -1; | |
16145 | ||
16146 | if (!vex_w_done) | |
16147 | { | |
41effecb SP |
16148 | /* Skip mod/rm byte. */ |
16149 | MODRM_CHECK; | |
16150 | codep++; | |
16151 | ||
922d8de8 | 16152 | if (vex.w) |
ccc5981b | 16153 | reg = get_vex_imm8 (sizeflag, 0) >> 4; |
922d8de8 DR |
16154 | } |
16155 | else | |
16156 | { | |
16157 | if (!vex.w) | |
ccc5981b | 16158 | reg = get_vex_imm8 (sizeflag, 1) >> 4; |
922d8de8 DR |
16159 | } |
16160 | ||
16161 | OP_EX_VexReg (bytemode, sizeflag, reg); | |
922d8de8 | 16162 | |
3a2430e0 JB |
16163 | if (vex_w_done) |
16164 | codep++; | |
16165 | vex_w_done = 1; | |
922d8de8 DR |
16166 | } |
16167 | ||
c0f3af97 L |
16168 | static void |
16169 | OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED) | |
16170 | { | |
16171 | int reg; | |
b9733481 L |
16172 | const char **names; |
16173 | ||
c0f3af97 L |
16174 | FETCH_DATA (the_info, codep + 1); |
16175 | reg = *codep++; | |
16176 | ||
16177 | if (bytemode != x_mode) | |
16178 | abort (); | |
16179 | ||
c0f3af97 | 16180 | reg >>= 4; |
5f847646 JB |
16181 | if (address_mode != mode_64bit) |
16182 | reg &= 7; | |
dae39acc | 16183 | |
c0f3af97 L |
16184 | switch (vex.length) |
16185 | { | |
16186 | case 128: | |
b9733481 | 16187 | names = names_xmm; |
c0f3af97 L |
16188 | break; |
16189 | case 256: | |
b9733481 | 16190 | names = names_ymm; |
c0f3af97 L |
16191 | break; |
16192 | default: | |
16193 | abort (); | |
16194 | } | |
b9733481 | 16195 | oappend (names[reg]); |
c0f3af97 L |
16196 | } |
16197 | ||
922d8de8 DR |
16198 | static void |
16199 | OP_XMM_VexW (int bytemode, int sizeflag) | |
16200 | { | |
16201 | /* Turn off the REX.W bit since it is used for swapping operands | |
16202 | now. */ | |
16203 | rex &= ~REX_W; | |
16204 | OP_XMM (bytemode, sizeflag); | |
16205 | } | |
16206 | ||
c0f3af97 L |
16207 | static void |
16208 | OP_EX_Vex (int bytemode, int sizeflag) | |
16209 | { | |
16210 | if (modrm.mod != 3) | |
63c6fc6c | 16211 | need_vex_reg = 0; |
c0f3af97 L |
16212 | OP_EX (bytemode, sizeflag); |
16213 | } | |
16214 | ||
16215 | static void | |
16216 | OP_XMM_Vex (int bytemode, int sizeflag) | |
16217 | { | |
16218 | if (modrm.mod != 3) | |
63c6fc6c | 16219 | need_vex_reg = 0; |
c0f3af97 L |
16220 | OP_XMM (bytemode, sizeflag); |
16221 | } | |
16222 | ||
ea397f5b L |
16223 | static struct op vex_cmp_op[] = |
16224 | { | |
16225 | { STRING_COMMA_LEN ("eq") }, | |
16226 | { STRING_COMMA_LEN ("lt") }, | |
16227 | { STRING_COMMA_LEN ("le") }, | |
16228 | { STRING_COMMA_LEN ("unord") }, | |
16229 | { STRING_COMMA_LEN ("neq") }, | |
16230 | { STRING_COMMA_LEN ("nlt") }, | |
16231 | { STRING_COMMA_LEN ("nle") }, | |
16232 | { STRING_COMMA_LEN ("ord") }, | |
16233 | { STRING_COMMA_LEN ("eq_uq") }, | |
16234 | { STRING_COMMA_LEN ("nge") }, | |
16235 | { STRING_COMMA_LEN ("ngt") }, | |
16236 | { STRING_COMMA_LEN ("false") }, | |
16237 | { STRING_COMMA_LEN ("neq_oq") }, | |
16238 | { STRING_COMMA_LEN ("ge") }, | |
16239 | { STRING_COMMA_LEN ("gt") }, | |
16240 | { STRING_COMMA_LEN ("true") }, | |
16241 | { STRING_COMMA_LEN ("eq_os") }, | |
16242 | { STRING_COMMA_LEN ("lt_oq") }, | |
16243 | { STRING_COMMA_LEN ("le_oq") }, | |
16244 | { STRING_COMMA_LEN ("unord_s") }, | |
16245 | { STRING_COMMA_LEN ("neq_us") }, | |
16246 | { STRING_COMMA_LEN ("nlt_uq") }, | |
16247 | { STRING_COMMA_LEN ("nle_uq") }, | |
16248 | { STRING_COMMA_LEN ("ord_s") }, | |
16249 | { STRING_COMMA_LEN ("eq_us") }, | |
16250 | { STRING_COMMA_LEN ("nge_uq") }, | |
16251 | { STRING_COMMA_LEN ("ngt_uq") }, | |
16252 | { STRING_COMMA_LEN ("false_os") }, | |
16253 | { STRING_COMMA_LEN ("neq_os") }, | |
16254 | { STRING_COMMA_LEN ("ge_oq") }, | |
16255 | { STRING_COMMA_LEN ("gt_oq") }, | |
16256 | { STRING_COMMA_LEN ("true_us") }, | |
c0f3af97 L |
16257 | }; |
16258 | ||
16259 | static void | |
16260 | VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
16261 | { | |
16262 | unsigned int cmp_type; | |
16263 | ||
16264 | FETCH_DATA (the_info, codep + 1); | |
16265 | cmp_type = *codep++ & 0xff; | |
16266 | if (cmp_type < ARRAY_SIZE (vex_cmp_op)) | |
16267 | { | |
16268 | char suffix [3]; | |
ea397f5b | 16269 | char *p = mnemonicendp - 2; |
c0f3af97 L |
16270 | suffix[0] = p[0]; |
16271 | suffix[1] = p[1]; | |
16272 | suffix[2] = '\0'; | |
ea397f5b L |
16273 | sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix); |
16274 | mnemonicendp += vex_cmp_op[cmp_type].len; | |
c0f3af97 L |
16275 | } |
16276 | else | |
16277 | { | |
16278 | /* We have a reserved extension byte. Output it directly. */ | |
16279 | scratchbuf[0] = '$'; | |
16280 | print_operand_value (scratchbuf + 1, 1, cmp_type); | |
9ce09ba2 | 16281 | oappend_maybe_intel (scratchbuf); |
c0f3af97 L |
16282 | scratchbuf[0] = '\0'; |
16283 | } | |
16284 | } | |
16285 | ||
43234a1e L |
16286 | static void |
16287 | VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, | |
16288 | int sizeflag ATTRIBUTE_UNUSED) | |
16289 | { | |
16290 | unsigned int cmp_type; | |
16291 | ||
16292 | if (!vex.evex) | |
16293 | abort (); | |
16294 | ||
16295 | FETCH_DATA (the_info, codep + 1); | |
16296 | cmp_type = *codep++ & 0xff; | |
16297 | /* There are aliases for immediates 0, 1, 2, 4, 5, 6. | |
16298 | If it's the case, print suffix, otherwise - print the immediate. */ | |
16299 | if (cmp_type < ARRAY_SIZE (simd_cmp_op) | |
16300 | && cmp_type != 3 | |
16301 | && cmp_type != 7) | |
16302 | { | |
16303 | char suffix [3]; | |
16304 | char *p = mnemonicendp - 2; | |
16305 | ||
16306 | /* vpcmp* can have both one- and two-lettered suffix. */ | |
16307 | if (p[0] == 'p') | |
16308 | { | |
16309 | p++; | |
16310 | suffix[0] = p[0]; | |
16311 | suffix[1] = '\0'; | |
16312 | } | |
16313 | else | |
16314 | { | |
16315 | suffix[0] = p[0]; | |
16316 | suffix[1] = p[1]; | |
16317 | suffix[2] = '\0'; | |
16318 | } | |
16319 | ||
16320 | sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix); | |
16321 | mnemonicendp += simd_cmp_op[cmp_type].len; | |
16322 | } | |
be92cb14 JB |
16323 | else |
16324 | { | |
16325 | /* We have a reserved extension byte. Output it directly. */ | |
16326 | scratchbuf[0] = '$'; | |
16327 | print_operand_value (scratchbuf + 1, 1, cmp_type); | |
16328 | oappend_maybe_intel (scratchbuf); | |
16329 | scratchbuf[0] = '\0'; | |
16330 | } | |
16331 | } | |
16332 | ||
16333 | static const struct op xop_cmp_op[] = | |
16334 | { | |
16335 | { STRING_COMMA_LEN ("lt") }, | |
16336 | { STRING_COMMA_LEN ("le") }, | |
16337 | { STRING_COMMA_LEN ("gt") }, | |
16338 | { STRING_COMMA_LEN ("ge") }, | |
16339 | { STRING_COMMA_LEN ("eq") }, | |
16340 | { STRING_COMMA_LEN ("neq") }, | |
16341 | { STRING_COMMA_LEN ("false") }, | |
16342 | { STRING_COMMA_LEN ("true") } | |
16343 | }; | |
16344 | ||
16345 | static void | |
16346 | VPCOM_Fixup (int bytemode ATTRIBUTE_UNUSED, | |
16347 | int sizeflag ATTRIBUTE_UNUSED) | |
16348 | { | |
16349 | unsigned int cmp_type; | |
16350 | ||
16351 | FETCH_DATA (the_info, codep + 1); | |
16352 | cmp_type = *codep++ & 0xff; | |
16353 | if (cmp_type < ARRAY_SIZE (xop_cmp_op)) | |
16354 | { | |
16355 | char suffix[3]; | |
16356 | char *p = mnemonicendp - 2; | |
16357 | ||
16358 | /* vpcom* can have both one- and two-lettered suffix. */ | |
16359 | if (p[0] == 'm') | |
16360 | { | |
16361 | p++; | |
16362 | suffix[0] = p[0]; | |
16363 | suffix[1] = '\0'; | |
16364 | } | |
16365 | else | |
16366 | { | |
16367 | suffix[0] = p[0]; | |
16368 | suffix[1] = p[1]; | |
16369 | suffix[2] = '\0'; | |
16370 | } | |
16371 | ||
16372 | sprintf (p, "%s%s", xop_cmp_op[cmp_type].name, suffix); | |
16373 | mnemonicendp += xop_cmp_op[cmp_type].len; | |
16374 | } | |
43234a1e L |
16375 | else |
16376 | { | |
16377 | /* We have a reserved extension byte. Output it directly. */ | |
16378 | scratchbuf[0] = '$'; | |
16379 | print_operand_value (scratchbuf + 1, 1, cmp_type); | |
9ce09ba2 | 16380 | oappend_maybe_intel (scratchbuf); |
43234a1e L |
16381 | scratchbuf[0] = '\0'; |
16382 | } | |
16383 | } | |
16384 | ||
ea397f5b L |
16385 | static const struct op pclmul_op[] = |
16386 | { | |
16387 | { STRING_COMMA_LEN ("lql") }, | |
16388 | { STRING_COMMA_LEN ("hql") }, | |
16389 | { STRING_COMMA_LEN ("lqh") }, | |
16390 | { STRING_COMMA_LEN ("hqh") } | |
c0f3af97 L |
16391 | }; |
16392 | ||
16393 | static void | |
16394 | PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED, | |
16395 | int sizeflag ATTRIBUTE_UNUSED) | |
16396 | { | |
16397 | unsigned int pclmul_type; | |
16398 | ||
16399 | FETCH_DATA (the_info, codep + 1); | |
16400 | pclmul_type = *codep++ & 0xff; | |
16401 | switch (pclmul_type) | |
16402 | { | |
16403 | case 0x10: | |
16404 | pclmul_type = 2; | |
16405 | break; | |
16406 | case 0x11: | |
16407 | pclmul_type = 3; | |
16408 | break; | |
16409 | default: | |
16410 | break; | |
7bb15c6f | 16411 | } |
c0f3af97 L |
16412 | if (pclmul_type < ARRAY_SIZE (pclmul_op)) |
16413 | { | |
16414 | char suffix [4]; | |
ea397f5b | 16415 | char *p = mnemonicendp - 3; |
c0f3af97 L |
16416 | suffix[0] = p[0]; |
16417 | suffix[1] = p[1]; | |
16418 | suffix[2] = p[2]; | |
16419 | suffix[3] = '\0'; | |
ea397f5b L |
16420 | sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix); |
16421 | mnemonicendp += pclmul_op[pclmul_type].len; | |
c0f3af97 L |
16422 | } |
16423 | else | |
16424 | { | |
16425 | /* We have a reserved extension byte. Output it directly. */ | |
16426 | scratchbuf[0] = '$'; | |
16427 | print_operand_value (scratchbuf + 1, 1, pclmul_type); | |
9ce09ba2 | 16428 | oappend_maybe_intel (scratchbuf); |
c0f3af97 L |
16429 | scratchbuf[0] = '\0'; |
16430 | } | |
16431 | } | |
16432 | ||
f1f8f695 L |
16433 | static void |
16434 | MOVBE_Fixup (int bytemode, int sizeflag) | |
16435 | { | |
16436 | /* Add proper suffix to "movbe". */ | |
ea397f5b | 16437 | char *p = mnemonicendp; |
f1f8f695 L |
16438 | |
16439 | switch (bytemode) | |
16440 | { | |
16441 | case v_mode: | |
16442 | if (intel_syntax) | |
ea397f5b | 16443 | goto skip; |
f1f8f695 L |
16444 | |
16445 | USED_REX (REX_W); | |
16446 | if (sizeflag & SUFFIX_ALWAYS) | |
16447 | { | |
16448 | if (rex & REX_W) | |
16449 | *p++ = 'q'; | |
f1f8f695 | 16450 | else |
f16cd0d5 L |
16451 | { |
16452 | if (sizeflag & DFLAG) | |
16453 | *p++ = 'l'; | |
16454 | else | |
16455 | *p++ = 'w'; | |
16456 | used_prefixes |= (prefixes & PREFIX_DATA); | |
16457 | } | |
f1f8f695 | 16458 | } |
f1f8f695 L |
16459 | break; |
16460 | default: | |
16461 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
16462 | break; | |
16463 | } | |
ea397f5b | 16464 | mnemonicendp = p; |
f1f8f695 L |
16465 | *p = '\0'; |
16466 | ||
dc1e8a47 | 16467 | skip: |
f1f8f695 L |
16468 | OP_M (bytemode, sizeflag); |
16469 | } | |
f88c9eb0 | 16470 | |
bc31405e L |
16471 | static void |
16472 | MOVSXD_Fixup (int bytemode, int sizeflag) | |
16473 | { | |
16474 | /* Add proper suffix to "movsxd". */ | |
16475 | char *p = mnemonicendp; | |
16476 | ||
16477 | switch (bytemode) | |
16478 | { | |
16479 | case movsxd_mode: | |
16480 | if (intel_syntax) | |
16481 | { | |
16482 | *p++ = 'x'; | |
16483 | *p++ = 'd'; | |
16484 | goto skip; | |
16485 | } | |
16486 | ||
16487 | USED_REX (REX_W); | |
16488 | if (rex & REX_W) | |
16489 | { | |
16490 | *p++ = 'l'; | |
16491 | *p++ = 'q'; | |
16492 | } | |
16493 | else | |
16494 | { | |
16495 | *p++ = 'x'; | |
16496 | *p++ = 'd'; | |
16497 | } | |
16498 | break; | |
16499 | default: | |
16500 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
16501 | break; | |
16502 | } | |
16503 | ||
dc1e8a47 | 16504 | skip: |
bc31405e L |
16505 | mnemonicendp = p; |
16506 | *p = '\0'; | |
16507 | OP_E (bytemode, sizeflag); | |
16508 | } | |
16509 | ||
f88c9eb0 SP |
16510 | static void |
16511 | OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
16512 | { | |
16513 | int reg; | |
16514 | const char **names; | |
16515 | ||
16516 | /* Skip mod/rm byte. */ | |
16517 | MODRM_CHECK; | |
16518 | codep++; | |
16519 | ||
390a6789 | 16520 | if (rex & REX_W) |
f88c9eb0 | 16521 | names = names64; |
f88c9eb0 | 16522 | else |
ce7d077e | 16523 | names = names32; |
f88c9eb0 SP |
16524 | |
16525 | reg = modrm.rm; | |
16526 | USED_REX (REX_B); | |
16527 | if (rex & REX_B) | |
16528 | reg += 8; | |
16529 | ||
16530 | oappend (names[reg]); | |
16531 | } | |
16532 | ||
16533 | static void | |
16534 | OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
16535 | { | |
16536 | const char **names; | |
5f847646 | 16537 | unsigned int reg = vex.register_specifier; |
63c6fc6c | 16538 | vex.register_specifier = 0; |
f88c9eb0 | 16539 | |
390a6789 | 16540 | if (rex & REX_W) |
f88c9eb0 | 16541 | names = names64; |
f88c9eb0 | 16542 | else |
ce7d077e | 16543 | names = names32; |
f88c9eb0 | 16544 | |
5f847646 JB |
16545 | if (address_mode != mode_64bit) |
16546 | reg &= 7; | |
16547 | oappend (names[reg]); | |
f88c9eb0 | 16548 | } |
43234a1e L |
16549 | |
16550 | static void | |
16551 | OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED) | |
16552 | { | |
16553 | if (!vex.evex | |
1ba585e8 | 16554 | || (bytemode != mask_mode && bytemode != mask_bd_mode)) |
43234a1e L |
16555 | abort (); |
16556 | ||
16557 | USED_REX (REX_R); | |
16558 | if ((rex & REX_R) != 0 || !vex.r) | |
16559 | { | |
16560 | BadOp (); | |
16561 | return; | |
16562 | } | |
16563 | ||
16564 | oappend (names_mask [modrm.reg]); | |
16565 | } | |
16566 | ||
16567 | static void | |
16568 | OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED) | |
16569 | { | |
43234a1e L |
16570 | if (modrm.mod == 3 && vex.b) |
16571 | switch (bytemode) | |
16572 | { | |
70df6fc9 L |
16573 | case evex_rounding_64_mode: |
16574 | if (address_mode != mode_64bit) | |
16575 | { | |
16576 | oappend ("(bad)"); | |
16577 | break; | |
16578 | } | |
16579 | /* Fall through. */ | |
43234a1e L |
16580 | case evex_rounding_mode: |
16581 | oappend (names_rounding[vex.ll]); | |
16582 | break; | |
16583 | case evex_sae_mode: | |
16584 | oappend ("{sae}"); | |
16585 | break; | |
16586 | default: | |
6df22cf6 | 16587 | abort (); |
43234a1e L |
16588 | break; |
16589 | } | |
16590 | } |