Commit | Line | Data |
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252b5132 | 1 | /* Print i386 instructions for GDB, the GNU debugger. |
b3adc24a | 2 | Copyright (C) 1988-2020 Free Software Foundation, Inc. |
252b5132 | 3 | |
9b201bb5 | 4 | This file is part of the GNU opcodes library. |
20f0a1fc | 5 | |
9b201bb5 | 6 | This library is free software; you can redistribute it and/or modify |
20f0a1fc | 7 | it under the terms of the GNU General Public License as published by |
9b201bb5 NC |
8 | the Free Software Foundation; either version 3, or (at your option) |
9 | any later version. | |
20f0a1fc | 10 | |
9b201bb5 NC |
11 | It is distributed in the hope that it will be useful, but WITHOUT |
12 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
13 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
14 | License for more details. | |
20f0a1fc NC |
15 | |
16 | You should have received a copy of the GNU General Public License | |
17 | along with this program; if not, write to the Free Software | |
9b201bb5 NC |
18 | Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, |
19 | MA 02110-1301, USA. */ | |
20 | ||
20f0a1fc NC |
21 | |
22 | /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu) | |
23 | July 1988 | |
24 | modified by John Hassey (hassey@dg-rtp.dg.com) | |
25 | x86-64 support added by Jan Hubicka (jh@suse.cz) | |
26 | VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */ | |
27 | ||
28 | /* The main tables describing the instructions is essentially a copy | |
29 | of the "Opcode Map" chapter (Appendix A) of the Intel 80386 | |
30 | Programmers Manual. Usually, there is a capital letter, followed | |
31 | by a small letter. The capital letter tell the addressing mode, | |
32 | and the small letter tells about the operand size. Refer to | |
33 | the Intel manual for details. */ | |
252b5132 | 34 | |
252b5132 | 35 | #include "sysdep.h" |
88c1242d | 36 | #include "disassemble.h" |
252b5132 | 37 | #include "opintl.h" |
0b1cf022 | 38 | #include "opcode/i386.h" |
85f10a01 | 39 | #include "libiberty.h" |
5b872f7d | 40 | #include "safe-ctype.h" |
252b5132 RH |
41 | |
42 | #include <setjmp.h> | |
43 | ||
26ca5450 AJ |
44 | static int print_insn (bfd_vma, disassemble_info *); |
45 | static void dofloat (int); | |
46 | static void OP_ST (int, int); | |
47 | static void OP_STi (int, int); | |
48 | static int putop (const char *, int); | |
49 | static void oappend (const char *); | |
50 | static void append_seg (void); | |
51 | static void OP_indirE (int, int); | |
52 | static void print_operand_value (char *, int, bfd_vma); | |
c0f3af97 | 53 | static void OP_E_register (int, int); |
c1e679ec | 54 | static void OP_E_memory (int, int); |
5d669648 | 55 | static void print_displacement (char *, bfd_vma); |
26ca5450 AJ |
56 | static void OP_E (int, int); |
57 | static void OP_G (int, int); | |
58 | static bfd_vma get64 (void); | |
59 | static bfd_signed_vma get32 (void); | |
60 | static bfd_signed_vma get32s (void); | |
61 | static int get16 (void); | |
62 | static void set_op (bfd_vma, int); | |
b844680a | 63 | static void OP_Skip_MODRM (int, int); |
26ca5450 AJ |
64 | static void OP_REG (int, int); |
65 | static void OP_IMREG (int, int); | |
66 | static void OP_I (int, int); | |
67 | static void OP_I64 (int, int); | |
68 | static void OP_sI (int, int); | |
69 | static void OP_J (int, int); | |
70 | static void OP_SEG (int, int); | |
71 | static void OP_DIR (int, int); | |
72 | static void OP_OFF (int, int); | |
73 | static void OP_OFF64 (int, int); | |
74 | static void ptr_reg (int, int); | |
75 | static void OP_ESreg (int, int); | |
76 | static void OP_DSreg (int, int); | |
77 | static void OP_C (int, int); | |
78 | static void OP_D (int, int); | |
79 | static void OP_T (int, int); | |
6f74c397 | 80 | static void OP_R (int, int); |
26ca5450 AJ |
81 | static void OP_MMX (int, int); |
82 | static void OP_XMM (int, int); | |
83 | static void OP_EM (int, int); | |
84 | static void OP_EX (int, int); | |
4d9567e0 MM |
85 | static void OP_EMC (int,int); |
86 | static void OP_MXC (int,int); | |
26ca5450 AJ |
87 | static void OP_MS (int, int); |
88 | static void OP_XS (int, int); | |
cc0ec051 | 89 | static void OP_M (int, int); |
c0f3af97 L |
90 | static void OP_VEX (int, int); |
91 | static void OP_EX_Vex (int, int); | |
922d8de8 | 92 | static void OP_EX_VexW (int, int); |
a683cc34 | 93 | static void OP_EX_VexImmW (int, int); |
c0f3af97 | 94 | static void OP_XMM_Vex (int, int); |
922d8de8 | 95 | static void OP_XMM_VexW (int, int); |
43234a1e | 96 | static void OP_Rounding (int, int); |
c0f3af97 L |
97 | static void OP_REG_VexI4 (int, int); |
98 | static void PCLMUL_Fixup (int, int); | |
c0f3af97 | 99 | static void VCMP_Fixup (int, int); |
43234a1e | 100 | static void VPCMP_Fixup (int, int); |
be92cb14 | 101 | static void VPCOM_Fixup (int, int); |
cc0ec051 | 102 | static void OP_0f07 (int, int); |
b844680a L |
103 | static void OP_Monitor (int, int); |
104 | static void OP_Mwait (int, int); | |
46e883c5 L |
105 | static void NOP_Fixup1 (int, int); |
106 | static void NOP_Fixup2 (int, int); | |
26ca5450 | 107 | static void OP_3DNowSuffix (int, int); |
ad19981d | 108 | static void CMP_Fixup (int, int); |
26ca5450 | 109 | static void BadOp (void); |
35c52694 | 110 | static void REP_Fixup (int, int); |
d835a58b | 111 | static void SEP_Fixup (int, int); |
7e8b059b | 112 | static void BND_Fixup (int, int); |
04ef582a | 113 | static void NOTRACK_Fixup (int, int); |
42164a71 L |
114 | static void HLE_Fixup1 (int, int); |
115 | static void HLE_Fixup2 (int, int); | |
116 | static void HLE_Fixup3 (int, int); | |
f5804c90 | 117 | static void CMPXCHG8B_Fixup (int, int); |
42903f7f | 118 | static void XMM_Fixup (int, int); |
381d071f | 119 | static void CRC32_Fixup (int, int); |
eacc9c89 | 120 | static void FXSAVE_Fixup (int, int); |
15c7c1d8 | 121 | static void PCMPESTR_Fixup (int, int); |
f88c9eb0 SP |
122 | static void OP_LWPCB_E (int, int); |
123 | static void OP_LWP_E (int, int); | |
5dd85c99 SP |
124 | static void OP_Vex_2src_1 (int, int); |
125 | static void OP_Vex_2src_2 (int, int); | |
c1e679ec | 126 | |
f1f8f695 | 127 | static void MOVBE_Fixup (int, int); |
bc31405e | 128 | static void MOVSXD_Fixup (int, int); |
252b5132 | 129 | |
43234a1e L |
130 | static void OP_Mask (int, int); |
131 | ||
6608db57 | 132 | struct dis_private { |
252b5132 RH |
133 | /* Points to first byte not fetched. */ |
134 | bfd_byte *max_fetched; | |
0b1cf022 | 135 | bfd_byte the_buffer[MAX_MNEM_SIZE]; |
252b5132 | 136 | bfd_vma insn_start; |
e396998b | 137 | int orig_sizeflag; |
8df14d78 | 138 | OPCODES_SIGJMP_BUF bailout; |
252b5132 RH |
139 | }; |
140 | ||
cb712a9e L |
141 | enum address_mode |
142 | { | |
143 | mode_16bit, | |
144 | mode_32bit, | |
145 | mode_64bit | |
146 | }; | |
147 | ||
148 | enum address_mode address_mode; | |
52b15da3 | 149 | |
5076851f ILT |
150 | /* Flags for the prefixes for the current instruction. See below. */ |
151 | static int prefixes; | |
152 | ||
52b15da3 JH |
153 | /* REX prefix the current instruction. See below. */ |
154 | static int rex; | |
155 | /* Bits of REX we've already used. */ | |
156 | static int rex_used; | |
52b15da3 JH |
157 | /* Mark parts used in the REX prefix. When we are testing for |
158 | empty prefix (for 8bit register REX extension), just mask it | |
159 | out. Otherwise test for REX bit is excuse for existence of REX | |
160 | only in case value is nonzero. */ | |
161 | #define USED_REX(value) \ | |
162 | { \ | |
163 | if (value) \ | |
161a04f6 L |
164 | { \ |
165 | if ((rex & value)) \ | |
166 | rex_used |= (value) | REX_OPCODE; \ | |
167 | } \ | |
52b15da3 | 168 | else \ |
161a04f6 | 169 | rex_used |= REX_OPCODE; \ |
52b15da3 JH |
170 | } |
171 | ||
7d421014 ILT |
172 | /* Flags for prefixes which we somehow handled when printing the |
173 | current instruction. */ | |
174 | static int used_prefixes; | |
175 | ||
5076851f ILT |
176 | /* Flags stored in PREFIXES. */ |
177 | #define PREFIX_REPZ 1 | |
178 | #define PREFIX_REPNZ 2 | |
179 | #define PREFIX_LOCK 4 | |
180 | #define PREFIX_CS 8 | |
181 | #define PREFIX_SS 0x10 | |
182 | #define PREFIX_DS 0x20 | |
183 | #define PREFIX_ES 0x40 | |
184 | #define PREFIX_FS 0x80 | |
185 | #define PREFIX_GS 0x100 | |
186 | #define PREFIX_DATA 0x200 | |
187 | #define PREFIX_ADDR 0x400 | |
188 | #define PREFIX_FWAIT 0x800 | |
189 | ||
252b5132 RH |
190 | /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive) |
191 | to ADDR (exclusive) are valid. Returns 1 for success, longjmps | |
192 | on error. */ | |
193 | #define FETCH_DATA(info, addr) \ | |
6608db57 | 194 | ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \ |
252b5132 RH |
195 | ? 1 : fetch_data ((info), (addr))) |
196 | ||
197 | static int | |
26ca5450 | 198 | fetch_data (struct disassemble_info *info, bfd_byte *addr) |
252b5132 RH |
199 | { |
200 | int status; | |
6608db57 | 201 | struct dis_private *priv = (struct dis_private *) info->private_data; |
252b5132 RH |
202 | bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer); |
203 | ||
0b1cf022 | 204 | if (addr <= priv->the_buffer + MAX_MNEM_SIZE) |
272c9217 JB |
205 | status = (*info->read_memory_func) (start, |
206 | priv->max_fetched, | |
207 | addr - priv->max_fetched, | |
208 | info); | |
209 | else | |
210 | status = -1; | |
252b5132 RH |
211 | if (status != 0) |
212 | { | |
7d421014 | 213 | /* If we did manage to read at least one byte, then |
db6eb5be AM |
214 | print_insn_i386 will do something sensible. Otherwise, print |
215 | an error. We do that here because this is where we know | |
216 | STATUS. */ | |
7d421014 | 217 | if (priv->max_fetched == priv->the_buffer) |
5076851f | 218 | (*info->memory_error_func) (status, start, info); |
8df14d78 | 219 | OPCODES_SIGLONGJMP (priv->bailout, 1); |
252b5132 RH |
220 | } |
221 | else | |
222 | priv->max_fetched = addr; | |
223 | return 1; | |
224 | } | |
225 | ||
bf890a93 | 226 | /* Possible values for prefix requirement. */ |
507bd325 L |
227 | #define PREFIX_IGNORED_SHIFT 16 |
228 | #define PREFIX_IGNORED_REPZ (PREFIX_REPZ << PREFIX_IGNORED_SHIFT) | |
229 | #define PREFIX_IGNORED_REPNZ (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT) | |
230 | #define PREFIX_IGNORED_DATA (PREFIX_DATA << PREFIX_IGNORED_SHIFT) | |
231 | #define PREFIX_IGNORED_ADDR (PREFIX_ADDR << PREFIX_IGNORED_SHIFT) | |
232 | #define PREFIX_IGNORED_LOCK (PREFIX_LOCK << PREFIX_IGNORED_SHIFT) | |
233 | ||
234 | /* Opcode prefixes. */ | |
235 | #define PREFIX_OPCODE (PREFIX_REPZ \ | |
236 | | PREFIX_REPNZ \ | |
237 | | PREFIX_DATA) | |
238 | ||
239 | /* Prefixes ignored. */ | |
240 | #define PREFIX_IGNORED (PREFIX_IGNORED_REPZ \ | |
241 | | PREFIX_IGNORED_REPNZ \ | |
242 | | PREFIX_IGNORED_DATA) | |
bf890a93 | 243 | |
ce518a5f | 244 | #define XX { NULL, 0 } |
507bd325 | 245 | #define Bad_Opcode NULL, { { NULL, 0 } }, 0 |
ce518a5f L |
246 | |
247 | #define Eb { OP_E, b_mode } | |
7e8b059b | 248 | #define Ebnd { OP_E, bnd_mode } |
b6169b20 | 249 | #define EbS { OP_E, b_swap_mode } |
9f79e886 | 250 | #define EbndS { OP_E, bnd_swap_mode } |
ce518a5f | 251 | #define Ev { OP_E, v_mode } |
de89d0a3 | 252 | #define Eva { OP_E, va_mode } |
7e8b059b | 253 | #define Ev_bnd { OP_E, v_bnd_mode } |
b6169b20 | 254 | #define EvS { OP_E, v_swap_mode } |
ce518a5f L |
255 | #define Ed { OP_E, d_mode } |
256 | #define Edq { OP_E, dq_mode } | |
257 | #define Edqw { OP_E, dqw_mode } | |
42903f7f | 258 | #define Edqb { OP_E, dqb_mode } |
1ba585e8 IT |
259 | #define Edb { OP_E, db_mode } |
260 | #define Edw { OP_E, dw_mode } | |
42903f7f | 261 | #define Edqd { OP_E, dqd_mode } |
09335d05 | 262 | #define Eq { OP_E, q_mode } |
07f5af7d | 263 | #define indirEv { OP_indirE, indir_v_mode } |
ce518a5f L |
264 | #define indirEp { OP_indirE, f_mode } |
265 | #define stackEv { OP_E, stack_v_mode } | |
266 | #define Em { OP_E, m_mode } | |
267 | #define Ew { OP_E, w_mode } | |
268 | #define M { OP_M, 0 } /* lea, lgdt, etc. */ | |
34b772a6 | 269 | #define Ma { OP_M, a_mode } |
b844680a | 270 | #define Mb { OP_M, b_mode } |
d9a5e5e5 | 271 | #define Md { OP_M, d_mode } |
f1f8f695 | 272 | #define Mo { OP_M, o_mode } |
ce518a5f L |
273 | #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */ |
274 | #define Mq { OP_M, q_mode } | |
d276ec69 | 275 | #define Mv_bnd { OP_M, v_bndmk_mode } |
4ee52178 | 276 | #define Mx { OP_M, x_mode } |
c0f3af97 | 277 | #define Mxmm { OP_M, xmm_mode } |
ce518a5f | 278 | #define Gb { OP_G, b_mode } |
7e8b059b | 279 | #define Gbnd { OP_G, bnd_mode } |
ce518a5f L |
280 | #define Gv { OP_G, v_mode } |
281 | #define Gd { OP_G, d_mode } | |
282 | #define Gdq { OP_G, dq_mode } | |
283 | #define Gm { OP_G, m_mode } | |
c0a30a9f | 284 | #define Gva { OP_G, va_mode } |
ce518a5f | 285 | #define Gw { OP_G, w_mode } |
6f74c397 | 286 | #define Rd { OP_R, d_mode } |
43234a1e | 287 | #define Rdq { OP_R, dq_mode } |
6f74c397 | 288 | #define Rm { OP_R, m_mode } |
ce518a5f L |
289 | #define Ib { OP_I, b_mode } |
290 | #define sIb { OP_sI, b_mode } /* sign extened byte */ | |
e3949f17 | 291 | #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */ |
ce518a5f | 292 | #define Iv { OP_I, v_mode } |
7bb15c6f | 293 | #define sIv { OP_sI, v_mode } |
ce518a5f | 294 | #define Iv64 { OP_I64, v_mode } |
c1dc7af5 | 295 | #define Id { OP_I, d_mode } |
ce518a5f L |
296 | #define Iw { OP_I, w_mode } |
297 | #define I1 { OP_I, const_1_mode } | |
298 | #define Jb { OP_J, b_mode } | |
299 | #define Jv { OP_J, v_mode } | |
376cd056 | 300 | #define Jdqw { OP_J, dqw_mode } |
ce518a5f L |
301 | #define Cm { OP_C, m_mode } |
302 | #define Dm { OP_D, m_mode } | |
303 | #define Td { OP_T, d_mode } | |
b844680a | 304 | #define Skip_MODRM { OP_Skip_MODRM, 0 } |
ce518a5f L |
305 | |
306 | #define RMeAX { OP_REG, eAX_reg } | |
307 | #define RMeBX { OP_REG, eBX_reg } | |
308 | #define RMeCX { OP_REG, eCX_reg } | |
309 | #define RMeDX { OP_REG, eDX_reg } | |
310 | #define RMeSP { OP_REG, eSP_reg } | |
311 | #define RMeBP { OP_REG, eBP_reg } | |
312 | #define RMeSI { OP_REG, eSI_reg } | |
313 | #define RMeDI { OP_REG, eDI_reg } | |
314 | #define RMrAX { OP_REG, rAX_reg } | |
315 | #define RMrBX { OP_REG, rBX_reg } | |
316 | #define RMrCX { OP_REG, rCX_reg } | |
317 | #define RMrDX { OP_REG, rDX_reg } | |
318 | #define RMrSP { OP_REG, rSP_reg } | |
319 | #define RMrBP { OP_REG, rBP_reg } | |
320 | #define RMrSI { OP_REG, rSI_reg } | |
321 | #define RMrDI { OP_REG, rDI_reg } | |
322 | #define RMAL { OP_REG, al_reg } | |
ce518a5f L |
323 | #define RMCL { OP_REG, cl_reg } |
324 | #define RMDL { OP_REG, dl_reg } | |
325 | #define RMBL { OP_REG, bl_reg } | |
326 | #define RMAH { OP_REG, ah_reg } | |
327 | #define RMCH { OP_REG, ch_reg } | |
328 | #define RMDH { OP_REG, dh_reg } | |
329 | #define RMBH { OP_REG, bh_reg } | |
330 | #define RMAX { OP_REG, ax_reg } | |
331 | #define RMDX { OP_REG, dx_reg } | |
332 | ||
333 | #define eAX { OP_IMREG, eAX_reg } | |
334 | #define eBX { OP_IMREG, eBX_reg } | |
335 | #define eCX { OP_IMREG, eCX_reg } | |
336 | #define eDX { OP_IMREG, eDX_reg } | |
337 | #define eSP { OP_IMREG, eSP_reg } | |
338 | #define eBP { OP_IMREG, eBP_reg } | |
339 | #define eSI { OP_IMREG, eSI_reg } | |
340 | #define eDI { OP_IMREG, eDI_reg } | |
341 | #define AL { OP_IMREG, al_reg } | |
342 | #define CL { OP_IMREG, cl_reg } | |
343 | #define DL { OP_IMREG, dl_reg } | |
344 | #define BL { OP_IMREG, bl_reg } | |
345 | #define AH { OP_IMREG, ah_reg } | |
346 | #define CH { OP_IMREG, ch_reg } | |
347 | #define DH { OP_IMREG, dh_reg } | |
348 | #define BH { OP_IMREG, bh_reg } | |
349 | #define AX { OP_IMREG, ax_reg } | |
350 | #define DX { OP_IMREG, dx_reg } | |
351 | #define zAX { OP_IMREG, z_mode_ax_reg } | |
352 | #define indirDX { OP_IMREG, indir_dx_reg } | |
353 | ||
354 | #define Sw { OP_SEG, w_mode } | |
355 | #define Sv { OP_SEG, v_mode } | |
356 | #define Ap { OP_DIR, 0 } | |
357 | #define Ob { OP_OFF64, b_mode } | |
358 | #define Ov { OP_OFF64, v_mode } | |
359 | #define Xb { OP_DSreg, eSI_reg } | |
360 | #define Xv { OP_DSreg, eSI_reg } | |
361 | #define Xz { OP_DSreg, eSI_reg } | |
362 | #define Yb { OP_ESreg, eDI_reg } | |
363 | #define Yv { OP_ESreg, eDI_reg } | |
364 | #define DSBX { OP_DSreg, eBX_reg } | |
365 | ||
366 | #define es { OP_REG, es_reg } | |
367 | #define ss { OP_REG, ss_reg } | |
368 | #define cs { OP_REG, cs_reg } | |
369 | #define ds { OP_REG, ds_reg } | |
370 | #define fs { OP_REG, fs_reg } | |
371 | #define gs { OP_REG, gs_reg } | |
372 | ||
373 | #define MX { OP_MMX, 0 } | |
374 | #define XM { OP_XMM, 0 } | |
539f890d | 375 | #define XMScalar { OP_XMM, scalar_mode } |
6c30d220 | 376 | #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode } |
c0f3af97 | 377 | #define XMM { OP_XMM, xmm_mode } |
43234a1e | 378 | #define XMxmmq { OP_XMM, xmmq_mode } |
ce518a5f | 379 | #define EM { OP_EM, v_mode } |
b6169b20 | 380 | #define EMS { OP_EM, v_swap_mode } |
09a2c6cf | 381 | #define EMd { OP_EM, d_mode } |
14051056 | 382 | #define EMx { OP_EM, x_mode } |
53467f57 | 383 | #define EXbScalar { OP_EX, b_scalar_mode } |
8976381e | 384 | #define EXw { OP_EX, w_mode } |
53467f57 | 385 | #define EXwScalar { OP_EX, w_scalar_mode } |
09a2c6cf | 386 | #define EXd { OP_EX, d_mode } |
fa99fab2 | 387 | #define EXdS { OP_EX, d_swap_mode } |
09a2c6cf | 388 | #define EXq { OP_EX, q_mode } |
b6169b20 | 389 | #define EXqS { OP_EX, q_swap_mode } |
09a2c6cf | 390 | #define EXx { OP_EX, x_mode } |
b6169b20 | 391 | #define EXxS { OP_EX, x_swap_mode } |
c0f3af97 | 392 | #define EXxmm { OP_EX, xmm_mode } |
43234a1e | 393 | #define EXymm { OP_EX, ymm_mode } |
c0f3af97 | 394 | #define EXxmmq { OP_EX, xmmq_mode } |
43234a1e | 395 | #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode } |
6c30d220 L |
396 | #define EXxmm_mb { OP_EX, xmm_mb_mode } |
397 | #define EXxmm_mw { OP_EX, xmm_mw_mode } | |
398 | #define EXxmm_md { OP_EX, xmm_md_mode } | |
399 | #define EXxmm_mq { OP_EX, xmm_mq_mode } | |
400 | #define EXxmmdw { OP_EX, xmmdw_mode } | |
401 | #define EXxmmqd { OP_EX, xmmqd_mode } | |
c0f3af97 | 402 | #define EXymmq { OP_EX, ymmq_mode } |
1c480963 | 403 | #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode } |
43234a1e L |
404 | #define EXEvexXGscat { OP_EX, evex_x_gscat_mode } |
405 | #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode } | |
ce518a5f L |
406 | #define MS { OP_MS, v_mode } |
407 | #define XS { OP_XS, v_mode } | |
09335d05 | 408 | #define EMCq { OP_EMC, q_mode } |
ce518a5f | 409 | #define MXC { OP_MXC, 0 } |
ce518a5f | 410 | #define OPSUF { OP_3DNowSuffix, 0 } |
d835a58b | 411 | #define SEP { SEP_Fixup, 0 } |
ad19981d | 412 | #define CMP { CMP_Fixup, 0 } |
42903f7f | 413 | #define XMM0 { XMM_Fixup, 0 } |
eacc9c89 | 414 | #define FXSAVE { FXSAVE_Fixup, 0 } |
5dd85c99 SP |
415 | #define Vex_2src_1 { OP_Vex_2src_1, 0 } |
416 | #define Vex_2src_2 { OP_Vex_2src_2, 0 } | |
252b5132 | 417 | |
c0f3af97 | 418 | #define Vex { OP_VEX, vex_mode } |
539f890d | 419 | #define VexScalar { OP_VEX, vex_scalar_mode } |
6c30d220 | 420 | #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode } |
c0f3af97 L |
421 | #define Vex128 { OP_VEX, vex128_mode } |
422 | #define Vex256 { OP_VEX, vex256_mode } | |
cb21baef | 423 | #define VexGdq { OP_VEX, dq_mode } |
539f890d | 424 | #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode } |
539f890d | 425 | #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode } |
922d8de8 DR |
426 | #define EXVexW { OP_EX_VexW, x_mode } |
427 | #define EXdVexW { OP_EX_VexW, d_mode } | |
428 | #define EXqVexW { OP_EX_VexW, q_mode } | |
a683cc34 | 429 | #define EXVexImmW { OP_EX_VexImmW, x_mode } |
539f890d | 430 | #define XMVexScalar { OP_XMM_Vex, scalar_mode } |
922d8de8 | 431 | #define XMVexW { OP_XMM_VexW, 0 } |
c0f3af97 L |
432 | #define XMVexI4 { OP_REG_VexI4, x_mode } |
433 | #define PCLMUL { PCLMUL_Fixup, 0 } | |
c0f3af97 | 434 | #define VCMP { VCMP_Fixup, 0 } |
43234a1e | 435 | #define VPCMP { VPCMP_Fixup, 0 } |
be92cb14 | 436 | #define VPCOM { VPCOM_Fixup, 0 } |
43234a1e L |
437 | |
438 | #define EXxEVexR { OP_Rounding, evex_rounding_mode } | |
70df6fc9 | 439 | #define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode } |
43234a1e L |
440 | #define EXxEVexS { OP_Rounding, evex_sae_mode } |
441 | ||
442 | #define XMask { OP_Mask, mask_mode } | |
443 | #define MaskG { OP_G, mask_mode } | |
444 | #define MaskE { OP_E, mask_mode } | |
1ba585e8 | 445 | #define MaskBDE { OP_E, mask_bd_mode } |
43234a1e L |
446 | #define MaskR { OP_R, mask_mode } |
447 | #define MaskVex { OP_VEX, mask_mode } | |
c0f3af97 | 448 | |
6c30d220 | 449 | #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode } |
5fc35d96 | 450 | #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode } |
6c30d220 | 451 | #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode } |
5fc35d96 | 452 | #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode } |
6c30d220 | 453 | |
35c52694 | 454 | /* Used handle "rep" prefix for string instructions. */ |
ce518a5f L |
455 | #define Xbr { REP_Fixup, eSI_reg } |
456 | #define Xvr { REP_Fixup, eSI_reg } | |
457 | #define Ybr { REP_Fixup, eDI_reg } | |
458 | #define Yvr { REP_Fixup, eDI_reg } | |
459 | #define Yzr { REP_Fixup, eDI_reg } | |
460 | #define indirDXr { REP_Fixup, indir_dx_reg } | |
461 | #define ALr { REP_Fixup, al_reg } | |
462 | #define eAXr { REP_Fixup, eAX_reg } | |
463 | ||
42164a71 L |
464 | /* Used handle HLE prefix for lockable instructions. */ |
465 | #define Ebh1 { HLE_Fixup1, b_mode } | |
466 | #define Evh1 { HLE_Fixup1, v_mode } | |
467 | #define Ebh2 { HLE_Fixup2, b_mode } | |
468 | #define Evh2 { HLE_Fixup2, v_mode } | |
469 | #define Ebh3 { HLE_Fixup3, b_mode } | |
470 | #define Evh3 { HLE_Fixup3, v_mode } | |
471 | ||
7e8b059b | 472 | #define BND { BND_Fixup, 0 } |
04ef582a | 473 | #define NOTRACK { NOTRACK_Fixup, 0 } |
7e8b059b | 474 | |
ce518a5f L |
475 | #define cond_jump_flag { NULL, cond_jump_mode } |
476 | #define loop_jcxz_flag { NULL, loop_jcxz_mode } | |
3ffd33cf | 477 | |
252b5132 | 478 | /* bits in sizeflag */ |
252b5132 | 479 | #define SUFFIX_ALWAYS 4 |
252b5132 RH |
480 | #define AFLAG 2 |
481 | #define DFLAG 1 | |
482 | ||
51e7da1b L |
483 | enum |
484 | { | |
485 | /* byte operand */ | |
486 | b_mode = 1, | |
487 | /* byte operand with operand swapped */ | |
3873ba12 | 488 | b_swap_mode, |
e3949f17 L |
489 | /* byte operand, sign extend like 'T' suffix */ |
490 | b_T_mode, | |
51e7da1b | 491 | /* operand size depends on prefixes */ |
3873ba12 | 492 | v_mode, |
51e7da1b | 493 | /* operand size depends on prefixes with operand swapped */ |
3873ba12 | 494 | v_swap_mode, |
de89d0a3 IT |
495 | /* operand size depends on address prefix */ |
496 | va_mode, | |
51e7da1b | 497 | /* word operand */ |
3873ba12 | 498 | w_mode, |
51e7da1b | 499 | /* double word operand */ |
3873ba12 | 500 | d_mode, |
51e7da1b | 501 | /* double word operand with operand swapped */ |
3873ba12 | 502 | d_swap_mode, |
51e7da1b | 503 | /* quad word operand */ |
3873ba12 | 504 | q_mode, |
51e7da1b | 505 | /* quad word operand with operand swapped */ |
3873ba12 | 506 | q_swap_mode, |
51e7da1b | 507 | /* ten-byte operand */ |
3873ba12 | 508 | t_mode, |
43234a1e L |
509 | /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand. In EVEX with |
510 | broadcast enabled. */ | |
3873ba12 | 511 | x_mode, |
43234a1e L |
512 | /* Similar to x_mode, but with different EVEX mem shifts. */ |
513 | evex_x_gscat_mode, | |
514 | /* Similar to x_mode, but with disabled broadcast. */ | |
515 | evex_x_nobcst_mode, | |
516 | /* Similar to x_mode, but with operands swapped and disabled broadcast | |
517 | in EVEX. */ | |
3873ba12 | 518 | x_swap_mode, |
51e7da1b | 519 | /* 16-byte XMM operand */ |
3873ba12 | 520 | xmm_mode, |
43234a1e L |
521 | /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword |
522 | memory operand (depending on vector length). Broadcast isn't | |
523 | allowed. */ | |
3873ba12 | 524 | xmmq_mode, |
43234a1e L |
525 | /* Same as xmmq_mode, but broadcast is allowed. */ |
526 | evex_half_bcst_xmmq_mode, | |
6c30d220 L |
527 | /* XMM register or byte memory operand */ |
528 | xmm_mb_mode, | |
529 | /* XMM register or word memory operand */ | |
530 | xmm_mw_mode, | |
531 | /* XMM register or double word memory operand */ | |
532 | xmm_md_mode, | |
533 | /* XMM register or quad word memory operand */ | |
534 | xmm_mq_mode, | |
43234a1e | 535 | /* 16-byte XMM, word, double word or quad word operand. */ |
6c30d220 | 536 | xmmdw_mode, |
43234a1e | 537 | /* 16-byte XMM, double word, quad word operand or xmm word operand. */ |
6c30d220 | 538 | xmmqd_mode, |
43234a1e L |
539 | /* 32-byte YMM operand */ |
540 | ymm_mode, | |
541 | /* quad word, ymmword or zmmword memory operand. */ | |
3873ba12 | 542 | ymmq_mode, |
6c30d220 L |
543 | /* 32-byte YMM or 16-byte word operand */ |
544 | ymmxmm_mode, | |
51e7da1b | 545 | /* d_mode in 32bit, q_mode in 64bit mode. */ |
3873ba12 | 546 | m_mode, |
51e7da1b | 547 | /* pair of v_mode operands */ |
3873ba12 L |
548 | a_mode, |
549 | cond_jump_mode, | |
550 | loop_jcxz_mode, | |
bc31405e | 551 | movsxd_mode, |
7e8b059b | 552 | v_bnd_mode, |
d276ec69 JB |
553 | /* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode. */ |
554 | v_bndmk_mode, | |
51e7da1b | 555 | /* operand size depends on REX prefixes. */ |
3873ba12 | 556 | dq_mode, |
376cd056 JB |
557 | /* registers like dq_mode, memory like w_mode, displacements like |
558 | v_mode without considering Intel64 ISA. */ | |
3873ba12 | 559 | dqw_mode, |
9f79e886 | 560 | /* bounds operand */ |
7e8b059b | 561 | bnd_mode, |
9f79e886 JB |
562 | /* bounds operand with operand swapped */ |
563 | bnd_swap_mode, | |
51e7da1b | 564 | /* 4- or 6-byte pointer operand */ |
3873ba12 L |
565 | f_mode, |
566 | const_1_mode, | |
07f5af7d L |
567 | /* v_mode for indirect branch opcodes. */ |
568 | indir_v_mode, | |
51e7da1b | 569 | /* v_mode for stack-related opcodes. */ |
3873ba12 | 570 | stack_v_mode, |
51e7da1b | 571 | /* non-quad operand size depends on prefixes */ |
3873ba12 | 572 | z_mode, |
51e7da1b | 573 | /* 16-byte operand */ |
3873ba12 | 574 | o_mode, |
51e7da1b | 575 | /* registers like dq_mode, memory like b_mode. */ |
3873ba12 | 576 | dqb_mode, |
1ba585e8 IT |
577 | /* registers like d_mode, memory like b_mode. */ |
578 | db_mode, | |
579 | /* registers like d_mode, memory like w_mode. */ | |
580 | dw_mode, | |
51e7da1b | 581 | /* registers like dq_mode, memory like d_mode. */ |
3873ba12 | 582 | dqd_mode, |
51e7da1b | 583 | /* normal vex mode */ |
3873ba12 | 584 | vex_mode, |
51e7da1b | 585 | /* 128bit vex mode */ |
3873ba12 | 586 | vex128_mode, |
51e7da1b | 587 | /* 256bit vex mode */ |
3873ba12 | 588 | vex256_mode, |
d55ee72f | 589 | |
825bd36c | 590 | /* Operand size depends on the VEX.W bit, with VSIB dword indices. */ |
6c30d220 | 591 | vex_vsib_d_w_dq_mode, |
5fc35d96 IT |
592 | /* Similar to vex_vsib_d_w_dq_mode, with smaller memory. */ |
593 | vex_vsib_d_w_d_mode, | |
825bd36c | 594 | /* Operand size depends on the VEX.W bit, with VSIB qword indices. */ |
6c30d220 | 595 | vex_vsib_q_w_dq_mode, |
5fc35d96 IT |
596 | /* Similar to vex_vsib_q_w_dq_mode, with smaller memory. */ |
597 | vex_vsib_q_w_d_mode, | |
6c30d220 | 598 | |
539f890d L |
599 | /* scalar, ignore vector length. */ |
600 | scalar_mode, | |
53467f57 IT |
601 | /* like b_mode, ignore vector length. */ |
602 | b_scalar_mode, | |
603 | /* like w_mode, ignore vector length. */ | |
604 | w_scalar_mode, | |
539f890d L |
605 | /* like d_swap_mode, ignore vector length. */ |
606 | d_scalar_swap_mode, | |
539f890d L |
607 | /* like q_swap_mode, ignore vector length. */ |
608 | q_scalar_swap_mode, | |
609 | /* like vex_mode, ignore vector length. */ | |
610 | vex_scalar_mode, | |
825bd36c | 611 | /* Operand size depends on the VEX.W bit, ignore vector length. */ |
1c480963 | 612 | vex_scalar_w_dq_mode, |
539f890d | 613 | |
43234a1e L |
614 | /* Static rounding. */ |
615 | evex_rounding_mode, | |
70df6fc9 L |
616 | /* Static rounding, 64-bit mode only. */ |
617 | evex_rounding_64_mode, | |
43234a1e L |
618 | /* Supress all exceptions. */ |
619 | evex_sae_mode, | |
620 | ||
621 | /* Mask register operand. */ | |
622 | mask_mode, | |
1ba585e8 IT |
623 | /* Mask register operand. */ |
624 | mask_bd_mode, | |
43234a1e | 625 | |
3873ba12 L |
626 | es_reg, |
627 | cs_reg, | |
628 | ss_reg, | |
629 | ds_reg, | |
630 | fs_reg, | |
631 | gs_reg, | |
d55ee72f | 632 | |
3873ba12 L |
633 | eAX_reg, |
634 | eCX_reg, | |
635 | eDX_reg, | |
636 | eBX_reg, | |
637 | eSP_reg, | |
638 | eBP_reg, | |
639 | eSI_reg, | |
640 | eDI_reg, | |
d55ee72f | 641 | |
3873ba12 L |
642 | al_reg, |
643 | cl_reg, | |
644 | dl_reg, | |
645 | bl_reg, | |
646 | ah_reg, | |
647 | ch_reg, | |
648 | dh_reg, | |
649 | bh_reg, | |
d55ee72f | 650 | |
3873ba12 L |
651 | ax_reg, |
652 | cx_reg, | |
653 | dx_reg, | |
654 | bx_reg, | |
655 | sp_reg, | |
656 | bp_reg, | |
657 | si_reg, | |
658 | di_reg, | |
d55ee72f | 659 | |
3873ba12 L |
660 | rAX_reg, |
661 | rCX_reg, | |
662 | rDX_reg, | |
663 | rBX_reg, | |
664 | rSP_reg, | |
665 | rBP_reg, | |
666 | rSI_reg, | |
667 | rDI_reg, | |
d55ee72f | 668 | |
3873ba12 L |
669 | z_mode_ax_reg, |
670 | indir_dx_reg | |
51e7da1b | 671 | }; |
252b5132 | 672 | |
51e7da1b L |
673 | enum |
674 | { | |
675 | FLOATCODE = 1, | |
3873ba12 L |
676 | USE_REG_TABLE, |
677 | USE_MOD_TABLE, | |
678 | USE_RM_TABLE, | |
679 | USE_PREFIX_TABLE, | |
680 | USE_X86_64_TABLE, | |
681 | USE_3BYTE_TABLE, | |
f88c9eb0 | 682 | USE_XOP_8F_TABLE, |
3873ba12 L |
683 | USE_VEX_C4_TABLE, |
684 | USE_VEX_C5_TABLE, | |
9e30b8e0 | 685 | USE_VEX_LEN_TABLE, |
43234a1e | 686 | USE_VEX_W_TABLE, |
04e2a182 L |
687 | USE_EVEX_TABLE, |
688 | USE_EVEX_LEN_TABLE | |
51e7da1b | 689 | }; |
6439fc28 | 690 | |
bf890a93 | 691 | #define FLOAT NULL, { { NULL, FLOATCODE } }, 0 |
4efba78c | 692 | |
bf890a93 IT |
693 | #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }, 0 |
694 | #define DIS386_PREFIX(T, I, P) NULL, { { NULL, (T)}, { NULL, (I) } }, P | |
1ceb70f8 L |
695 | #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I)) |
696 | #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I)) | |
697 | #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I)) | |
698 | #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I)) | |
4e7d34a6 L |
699 | #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I)) |
700 | #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I)) | |
bf890a93 | 701 | #define THREE_BYTE_TABLE_PREFIX(I, P) DIS386_PREFIX (USE_3BYTE_TABLE, (I), P) |
f88c9eb0 | 702 | #define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I)) |
c0f3af97 L |
703 | #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I)) |
704 | #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I)) | |
705 | #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I)) | |
9e30b8e0 | 706 | #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I)) |
43234a1e | 707 | #define EVEX_TABLE(I) DIS386 (USE_EVEX_TABLE, (I)) |
04e2a182 | 708 | #define EVEX_LEN_TABLE(I) DIS386 (USE_EVEX_LEN_TABLE, (I)) |
1ceb70f8 | 709 | |
51e7da1b L |
710 | enum |
711 | { | |
712 | REG_80 = 0, | |
3873ba12 | 713 | REG_81, |
7148c369 | 714 | REG_83, |
3873ba12 L |
715 | REG_8F, |
716 | REG_C0, | |
717 | REG_C1, | |
718 | REG_C6, | |
719 | REG_C7, | |
720 | REG_D0, | |
721 | REG_D1, | |
722 | REG_D2, | |
723 | REG_D3, | |
724 | REG_F6, | |
725 | REG_F7, | |
726 | REG_FE, | |
727 | REG_FF, | |
728 | REG_0F00, | |
729 | REG_0F01, | |
730 | REG_0F0D, | |
731 | REG_0F18, | |
f8687e93 JB |
732 | REG_0F1C_P_0_MOD_0, |
733 | REG_0F1E_P_1_MOD_3, | |
3873ba12 L |
734 | REG_0F71, |
735 | REG_0F72, | |
736 | REG_0F73, | |
737 | REG_0FA6, | |
738 | REG_0FA7, | |
739 | REG_0FAE, | |
740 | REG_0FBA, | |
741 | REG_0FC7, | |
592a252b L |
742 | REG_VEX_0F71, |
743 | REG_VEX_0F72, | |
744 | REG_VEX_0F73, | |
745 | REG_VEX_0FAE, | |
f12dc422 | 746 | REG_VEX_0F38F3, |
f88c9eb0 | 747 | REG_XOP_LWPCB, |
2a2a0f38 QN |
748 | REG_XOP_LWP, |
749 | REG_XOP_TBM_01, | |
43234a1e L |
750 | REG_XOP_TBM_02, |
751 | ||
1ba585e8 | 752 | REG_EVEX_0F71, |
43234a1e L |
753 | REG_EVEX_0F72, |
754 | REG_EVEX_0F73, | |
755 | REG_EVEX_0F38C6, | |
756 | REG_EVEX_0F38C7 | |
51e7da1b | 757 | }; |
1ceb70f8 | 758 | |
51e7da1b L |
759 | enum |
760 | { | |
761 | MOD_8D = 0, | |
42164a71 L |
762 | MOD_C6_REG_7, |
763 | MOD_C7_REG_7, | |
4a357820 MZ |
764 | MOD_FF_REG_3, |
765 | MOD_FF_REG_5, | |
3873ba12 L |
766 | MOD_0F01_REG_0, |
767 | MOD_0F01_REG_1, | |
768 | MOD_0F01_REG_2, | |
769 | MOD_0F01_REG_3, | |
8eab4136 | 770 | MOD_0F01_REG_5, |
3873ba12 L |
771 | MOD_0F01_REG_7, |
772 | MOD_0F12_PREFIX_0, | |
18897deb | 773 | MOD_0F12_PREFIX_2, |
3873ba12 L |
774 | MOD_0F13, |
775 | MOD_0F16_PREFIX_0, | |
18897deb | 776 | MOD_0F16_PREFIX_2, |
3873ba12 L |
777 | MOD_0F17, |
778 | MOD_0F18_REG_0, | |
779 | MOD_0F18_REG_1, | |
780 | MOD_0F18_REG_2, | |
781 | MOD_0F18_REG_3, | |
d7189fa5 RM |
782 | MOD_0F18_REG_4, |
783 | MOD_0F18_REG_5, | |
784 | MOD_0F18_REG_6, | |
785 | MOD_0F18_REG_7, | |
7e8b059b L |
786 | MOD_0F1A_PREFIX_0, |
787 | MOD_0F1B_PREFIX_0, | |
788 | MOD_0F1B_PREFIX_1, | |
c48935d7 | 789 | MOD_0F1C_PREFIX_0, |
603555e5 | 790 | MOD_0F1E_PREFIX_1, |
3873ba12 L |
791 | MOD_0F24, |
792 | MOD_0F26, | |
793 | MOD_0F2B_PREFIX_0, | |
794 | MOD_0F2B_PREFIX_1, | |
795 | MOD_0F2B_PREFIX_2, | |
796 | MOD_0F2B_PREFIX_3, | |
a5aaedb9 | 797 | MOD_0F50, |
3873ba12 L |
798 | MOD_0F71_REG_2, |
799 | MOD_0F71_REG_4, | |
800 | MOD_0F71_REG_6, | |
801 | MOD_0F72_REG_2, | |
802 | MOD_0F72_REG_4, | |
803 | MOD_0F72_REG_6, | |
804 | MOD_0F73_REG_2, | |
805 | MOD_0F73_REG_3, | |
806 | MOD_0F73_REG_6, | |
807 | MOD_0F73_REG_7, | |
808 | MOD_0FAE_REG_0, | |
809 | MOD_0FAE_REG_1, | |
810 | MOD_0FAE_REG_2, | |
811 | MOD_0FAE_REG_3, | |
812 | MOD_0FAE_REG_4, | |
813 | MOD_0FAE_REG_5, | |
814 | MOD_0FAE_REG_6, | |
815 | MOD_0FAE_REG_7, | |
816 | MOD_0FB2, | |
817 | MOD_0FB4, | |
818 | MOD_0FB5, | |
a8484f96 | 819 | MOD_0FC3, |
963f3586 IT |
820 | MOD_0FC7_REG_3, |
821 | MOD_0FC7_REG_4, | |
822 | MOD_0FC7_REG_5, | |
3873ba12 L |
823 | MOD_0FC7_REG_6, |
824 | MOD_0FC7_REG_7, | |
825 | MOD_0FD7, | |
826 | MOD_0FE7_PREFIX_2, | |
827 | MOD_0FF0_PREFIX_3, | |
828 | MOD_0F382A_PREFIX_2, | |
603555e5 L |
829 | MOD_0F38F5_PREFIX_2, |
830 | MOD_0F38F6_PREFIX_0, | |
5d79adc4 | 831 | MOD_0F38F8_PREFIX_1, |
c0a30a9f | 832 | MOD_0F38F8_PREFIX_2, |
5d79adc4 | 833 | MOD_0F38F8_PREFIX_3, |
c0a30a9f | 834 | MOD_0F38F9_PREFIX_0, |
3873ba12 L |
835 | MOD_62_32BIT, |
836 | MOD_C4_32BIT, | |
837 | MOD_C5_32BIT, | |
592a252b | 838 | MOD_VEX_0F12_PREFIX_0, |
18897deb | 839 | MOD_VEX_0F12_PREFIX_2, |
592a252b L |
840 | MOD_VEX_0F13, |
841 | MOD_VEX_0F16_PREFIX_0, | |
18897deb | 842 | MOD_VEX_0F16_PREFIX_2, |
592a252b L |
843 | MOD_VEX_0F17, |
844 | MOD_VEX_0F2B, | |
ab4e4ed5 AF |
845 | MOD_VEX_W_0_0F41_P_0_LEN_1, |
846 | MOD_VEX_W_1_0F41_P_0_LEN_1, | |
847 | MOD_VEX_W_0_0F41_P_2_LEN_1, | |
848 | MOD_VEX_W_1_0F41_P_2_LEN_1, | |
849 | MOD_VEX_W_0_0F42_P_0_LEN_1, | |
850 | MOD_VEX_W_1_0F42_P_0_LEN_1, | |
851 | MOD_VEX_W_0_0F42_P_2_LEN_1, | |
852 | MOD_VEX_W_1_0F42_P_2_LEN_1, | |
853 | MOD_VEX_W_0_0F44_P_0_LEN_1, | |
854 | MOD_VEX_W_1_0F44_P_0_LEN_1, | |
855 | MOD_VEX_W_0_0F44_P_2_LEN_1, | |
856 | MOD_VEX_W_1_0F44_P_2_LEN_1, | |
857 | MOD_VEX_W_0_0F45_P_0_LEN_1, | |
858 | MOD_VEX_W_1_0F45_P_0_LEN_1, | |
859 | MOD_VEX_W_0_0F45_P_2_LEN_1, | |
860 | MOD_VEX_W_1_0F45_P_2_LEN_1, | |
861 | MOD_VEX_W_0_0F46_P_0_LEN_1, | |
862 | MOD_VEX_W_1_0F46_P_0_LEN_1, | |
863 | MOD_VEX_W_0_0F46_P_2_LEN_1, | |
864 | MOD_VEX_W_1_0F46_P_2_LEN_1, | |
865 | MOD_VEX_W_0_0F47_P_0_LEN_1, | |
866 | MOD_VEX_W_1_0F47_P_0_LEN_1, | |
867 | MOD_VEX_W_0_0F47_P_2_LEN_1, | |
868 | MOD_VEX_W_1_0F47_P_2_LEN_1, | |
869 | MOD_VEX_W_0_0F4A_P_0_LEN_1, | |
870 | MOD_VEX_W_1_0F4A_P_0_LEN_1, | |
871 | MOD_VEX_W_0_0F4A_P_2_LEN_1, | |
872 | MOD_VEX_W_1_0F4A_P_2_LEN_1, | |
873 | MOD_VEX_W_0_0F4B_P_0_LEN_1, | |
874 | MOD_VEX_W_1_0F4B_P_0_LEN_1, | |
875 | MOD_VEX_W_0_0F4B_P_2_LEN_1, | |
592a252b L |
876 | MOD_VEX_0F50, |
877 | MOD_VEX_0F71_REG_2, | |
878 | MOD_VEX_0F71_REG_4, | |
879 | MOD_VEX_0F71_REG_6, | |
880 | MOD_VEX_0F72_REG_2, | |
881 | MOD_VEX_0F72_REG_4, | |
882 | MOD_VEX_0F72_REG_6, | |
883 | MOD_VEX_0F73_REG_2, | |
884 | MOD_VEX_0F73_REG_3, | |
885 | MOD_VEX_0F73_REG_6, | |
886 | MOD_VEX_0F73_REG_7, | |
ab4e4ed5 AF |
887 | MOD_VEX_W_0_0F91_P_0_LEN_0, |
888 | MOD_VEX_W_1_0F91_P_0_LEN_0, | |
889 | MOD_VEX_W_0_0F91_P_2_LEN_0, | |
890 | MOD_VEX_W_1_0F91_P_2_LEN_0, | |
891 | MOD_VEX_W_0_0F92_P_0_LEN_0, | |
892 | MOD_VEX_W_0_0F92_P_2_LEN_0, | |
58a211d2 | 893 | MOD_VEX_0F92_P_3_LEN_0, |
ab4e4ed5 AF |
894 | MOD_VEX_W_0_0F93_P_0_LEN_0, |
895 | MOD_VEX_W_0_0F93_P_2_LEN_0, | |
58a211d2 | 896 | MOD_VEX_0F93_P_3_LEN_0, |
ab4e4ed5 AF |
897 | MOD_VEX_W_0_0F98_P_0_LEN_0, |
898 | MOD_VEX_W_1_0F98_P_0_LEN_0, | |
899 | MOD_VEX_W_0_0F98_P_2_LEN_0, | |
900 | MOD_VEX_W_1_0F98_P_2_LEN_0, | |
901 | MOD_VEX_W_0_0F99_P_0_LEN_0, | |
902 | MOD_VEX_W_1_0F99_P_0_LEN_0, | |
903 | MOD_VEX_W_0_0F99_P_2_LEN_0, | |
904 | MOD_VEX_W_1_0F99_P_2_LEN_0, | |
592a252b L |
905 | MOD_VEX_0FAE_REG_2, |
906 | MOD_VEX_0FAE_REG_3, | |
907 | MOD_VEX_0FD7_PREFIX_2, | |
908 | MOD_VEX_0FE7_PREFIX_2, | |
909 | MOD_VEX_0FF0_PREFIX_3, | |
592a252b L |
910 | MOD_VEX_0F381A_PREFIX_2, |
911 | MOD_VEX_0F382A_PREFIX_2, | |
912 | MOD_VEX_0F382C_PREFIX_2, | |
913 | MOD_VEX_0F382D_PREFIX_2, | |
914 | MOD_VEX_0F382E_PREFIX_2, | |
6c30d220 L |
915 | MOD_VEX_0F382F_PREFIX_2, |
916 | MOD_VEX_0F385A_PREFIX_2, | |
917 | MOD_VEX_0F388C_PREFIX_2, | |
918 | MOD_VEX_0F388E_PREFIX_2, | |
ab4e4ed5 AF |
919 | MOD_VEX_W_0_0F3A30_P_2_LEN_0, |
920 | MOD_VEX_W_1_0F3A30_P_2_LEN_0, | |
921 | MOD_VEX_W_0_0F3A31_P_2_LEN_0, | |
922 | MOD_VEX_W_1_0F3A31_P_2_LEN_0, | |
923 | MOD_VEX_W_0_0F3A32_P_2_LEN_0, | |
924 | MOD_VEX_W_1_0F3A32_P_2_LEN_0, | |
925 | MOD_VEX_W_0_0F3A33_P_2_LEN_0, | |
926 | MOD_VEX_W_1_0F3A33_P_2_LEN_0, | |
43234a1e | 927 | |
43234a1e | 928 | MOD_EVEX_0F12_PREFIX_0, |
97e6786a JB |
929 | MOD_EVEX_0F12_PREFIX_2, |
930 | MOD_EVEX_0F13, | |
43234a1e | 931 | MOD_EVEX_0F16_PREFIX_0, |
97e6786a JB |
932 | MOD_EVEX_0F16_PREFIX_2, |
933 | MOD_EVEX_0F17, | |
934 | MOD_EVEX_0F2B, | |
43234a1e L |
935 | MOD_EVEX_0F38C6_REG_1, |
936 | MOD_EVEX_0F38C6_REG_2, | |
937 | MOD_EVEX_0F38C6_REG_5, | |
938 | MOD_EVEX_0F38C6_REG_6, | |
939 | MOD_EVEX_0F38C7_REG_1, | |
940 | MOD_EVEX_0F38C7_REG_2, | |
941 | MOD_EVEX_0F38C7_REG_5, | |
942 | MOD_EVEX_0F38C7_REG_6 | |
51e7da1b | 943 | }; |
1ceb70f8 | 944 | |
51e7da1b L |
945 | enum |
946 | { | |
42164a71 L |
947 | RM_C6_REG_7 = 0, |
948 | RM_C7_REG_7, | |
949 | RM_0F01_REG_0, | |
3873ba12 L |
950 | RM_0F01_REG_1, |
951 | RM_0F01_REG_2, | |
952 | RM_0F01_REG_3, | |
f8687e93 JB |
953 | RM_0F01_REG_5_MOD_3, |
954 | RM_0F01_REG_7_MOD_3, | |
955 | RM_0F1E_P_1_MOD_3_REG_7, | |
956 | RM_0FAE_REG_6_MOD_3_P_0, | |
957 | RM_0FAE_REG_7_MOD_3, | |
51e7da1b | 958 | }; |
1ceb70f8 | 959 | |
51e7da1b L |
960 | enum |
961 | { | |
962 | PREFIX_90 = 0, | |
a847e322 | 963 | PREFIX_0F01_REG_3_RM_1, |
f8687e93 JB |
964 | PREFIX_0F01_REG_5_MOD_0, |
965 | PREFIX_0F01_REG_5_MOD_3_RM_0, | |
bb651e8b | 966 | PREFIX_0F01_REG_5_MOD_3_RM_1, |
f8687e93 | 967 | PREFIX_0F01_REG_5_MOD_3_RM_2, |
267b8516 JB |
968 | PREFIX_0F01_REG_7_MOD_3_RM_2, |
969 | PREFIX_0F01_REG_7_MOD_3_RM_3, | |
3233d7d0 | 970 | PREFIX_0F09, |
3873ba12 L |
971 | PREFIX_0F10, |
972 | PREFIX_0F11, | |
973 | PREFIX_0F12, | |
974 | PREFIX_0F16, | |
7e8b059b L |
975 | PREFIX_0F1A, |
976 | PREFIX_0F1B, | |
c48935d7 | 977 | PREFIX_0F1C, |
603555e5 | 978 | PREFIX_0F1E, |
3873ba12 L |
979 | PREFIX_0F2A, |
980 | PREFIX_0F2B, | |
981 | PREFIX_0F2C, | |
982 | PREFIX_0F2D, | |
983 | PREFIX_0F2E, | |
984 | PREFIX_0F2F, | |
985 | PREFIX_0F51, | |
986 | PREFIX_0F52, | |
987 | PREFIX_0F53, | |
988 | PREFIX_0F58, | |
989 | PREFIX_0F59, | |
990 | PREFIX_0F5A, | |
991 | PREFIX_0F5B, | |
992 | PREFIX_0F5C, | |
993 | PREFIX_0F5D, | |
994 | PREFIX_0F5E, | |
995 | PREFIX_0F5F, | |
996 | PREFIX_0F60, | |
997 | PREFIX_0F61, | |
998 | PREFIX_0F62, | |
999 | PREFIX_0F6C, | |
1000 | PREFIX_0F6D, | |
1001 | PREFIX_0F6F, | |
1002 | PREFIX_0F70, | |
1003 | PREFIX_0F73_REG_3, | |
1004 | PREFIX_0F73_REG_7, | |
1005 | PREFIX_0F78, | |
1006 | PREFIX_0F79, | |
1007 | PREFIX_0F7C, | |
1008 | PREFIX_0F7D, | |
1009 | PREFIX_0F7E, | |
1010 | PREFIX_0F7F, | |
f8687e93 JB |
1011 | PREFIX_0FAE_REG_0_MOD_3, |
1012 | PREFIX_0FAE_REG_1_MOD_3, | |
1013 | PREFIX_0FAE_REG_2_MOD_3, | |
1014 | PREFIX_0FAE_REG_3_MOD_3, | |
1015 | PREFIX_0FAE_REG_4_MOD_0, | |
1016 | PREFIX_0FAE_REG_4_MOD_3, | |
1017 | PREFIX_0FAE_REG_5_MOD_0, | |
1018 | PREFIX_0FAE_REG_5_MOD_3, | |
1019 | PREFIX_0FAE_REG_6_MOD_0, | |
1020 | PREFIX_0FAE_REG_6_MOD_3, | |
1021 | PREFIX_0FAE_REG_7_MOD_0, | |
3873ba12 | 1022 | PREFIX_0FB8, |
f12dc422 | 1023 | PREFIX_0FBC, |
3873ba12 L |
1024 | PREFIX_0FBD, |
1025 | PREFIX_0FC2, | |
f8687e93 JB |
1026 | PREFIX_0FC3_MOD_0, |
1027 | PREFIX_0FC7_REG_6_MOD_0, | |
1028 | PREFIX_0FC7_REG_6_MOD_3, | |
1029 | PREFIX_0FC7_REG_7_MOD_3, | |
3873ba12 L |
1030 | PREFIX_0FD0, |
1031 | PREFIX_0FD6, | |
1032 | PREFIX_0FE6, | |
1033 | PREFIX_0FE7, | |
1034 | PREFIX_0FF0, | |
1035 | PREFIX_0FF7, | |
1036 | PREFIX_0F3810, | |
1037 | PREFIX_0F3814, | |
1038 | PREFIX_0F3815, | |
1039 | PREFIX_0F3817, | |
1040 | PREFIX_0F3820, | |
1041 | PREFIX_0F3821, | |
1042 | PREFIX_0F3822, | |
1043 | PREFIX_0F3823, | |
1044 | PREFIX_0F3824, | |
1045 | PREFIX_0F3825, | |
1046 | PREFIX_0F3828, | |
1047 | PREFIX_0F3829, | |
1048 | PREFIX_0F382A, | |
1049 | PREFIX_0F382B, | |
1050 | PREFIX_0F3830, | |
1051 | PREFIX_0F3831, | |
1052 | PREFIX_0F3832, | |
1053 | PREFIX_0F3833, | |
1054 | PREFIX_0F3834, | |
1055 | PREFIX_0F3835, | |
1056 | PREFIX_0F3837, | |
1057 | PREFIX_0F3838, | |
1058 | PREFIX_0F3839, | |
1059 | PREFIX_0F383A, | |
1060 | PREFIX_0F383B, | |
1061 | PREFIX_0F383C, | |
1062 | PREFIX_0F383D, | |
1063 | PREFIX_0F383E, | |
1064 | PREFIX_0F383F, | |
1065 | PREFIX_0F3840, | |
1066 | PREFIX_0F3841, | |
1067 | PREFIX_0F3880, | |
1068 | PREFIX_0F3881, | |
6c30d220 | 1069 | PREFIX_0F3882, |
a0046408 L |
1070 | PREFIX_0F38C8, |
1071 | PREFIX_0F38C9, | |
1072 | PREFIX_0F38CA, | |
1073 | PREFIX_0F38CB, | |
1074 | PREFIX_0F38CC, | |
1075 | PREFIX_0F38CD, | |
48521003 | 1076 | PREFIX_0F38CF, |
3873ba12 L |
1077 | PREFIX_0F38DB, |
1078 | PREFIX_0F38DC, | |
1079 | PREFIX_0F38DD, | |
1080 | PREFIX_0F38DE, | |
1081 | PREFIX_0F38DF, | |
1082 | PREFIX_0F38F0, | |
1083 | PREFIX_0F38F1, | |
603555e5 | 1084 | PREFIX_0F38F5, |
e2e1fcde | 1085 | PREFIX_0F38F6, |
c0a30a9f L |
1086 | PREFIX_0F38F8, |
1087 | PREFIX_0F38F9, | |
3873ba12 L |
1088 | PREFIX_0F3A08, |
1089 | PREFIX_0F3A09, | |
1090 | PREFIX_0F3A0A, | |
1091 | PREFIX_0F3A0B, | |
1092 | PREFIX_0F3A0C, | |
1093 | PREFIX_0F3A0D, | |
1094 | PREFIX_0F3A0E, | |
1095 | PREFIX_0F3A14, | |
1096 | PREFIX_0F3A15, | |
1097 | PREFIX_0F3A16, | |
1098 | PREFIX_0F3A17, | |
1099 | PREFIX_0F3A20, | |
1100 | PREFIX_0F3A21, | |
1101 | PREFIX_0F3A22, | |
1102 | PREFIX_0F3A40, | |
1103 | PREFIX_0F3A41, | |
1104 | PREFIX_0F3A42, | |
1105 | PREFIX_0F3A44, | |
1106 | PREFIX_0F3A60, | |
1107 | PREFIX_0F3A61, | |
1108 | PREFIX_0F3A62, | |
1109 | PREFIX_0F3A63, | |
a0046408 | 1110 | PREFIX_0F3ACC, |
48521003 IT |
1111 | PREFIX_0F3ACE, |
1112 | PREFIX_0F3ACF, | |
3873ba12 | 1113 | PREFIX_0F3ADF, |
592a252b L |
1114 | PREFIX_VEX_0F10, |
1115 | PREFIX_VEX_0F11, | |
1116 | PREFIX_VEX_0F12, | |
1117 | PREFIX_VEX_0F16, | |
1118 | PREFIX_VEX_0F2A, | |
1119 | PREFIX_VEX_0F2C, | |
1120 | PREFIX_VEX_0F2D, | |
1121 | PREFIX_VEX_0F2E, | |
1122 | PREFIX_VEX_0F2F, | |
43234a1e L |
1123 | PREFIX_VEX_0F41, |
1124 | PREFIX_VEX_0F42, | |
1125 | PREFIX_VEX_0F44, | |
1126 | PREFIX_VEX_0F45, | |
1127 | PREFIX_VEX_0F46, | |
1128 | PREFIX_VEX_0F47, | |
1ba585e8 | 1129 | PREFIX_VEX_0F4A, |
43234a1e | 1130 | PREFIX_VEX_0F4B, |
592a252b L |
1131 | PREFIX_VEX_0F51, |
1132 | PREFIX_VEX_0F52, | |
1133 | PREFIX_VEX_0F53, | |
1134 | PREFIX_VEX_0F58, | |
1135 | PREFIX_VEX_0F59, | |
1136 | PREFIX_VEX_0F5A, | |
1137 | PREFIX_VEX_0F5B, | |
1138 | PREFIX_VEX_0F5C, | |
1139 | PREFIX_VEX_0F5D, | |
1140 | PREFIX_VEX_0F5E, | |
1141 | PREFIX_VEX_0F5F, | |
1142 | PREFIX_VEX_0F60, | |
1143 | PREFIX_VEX_0F61, | |
1144 | PREFIX_VEX_0F62, | |
1145 | PREFIX_VEX_0F63, | |
1146 | PREFIX_VEX_0F64, | |
1147 | PREFIX_VEX_0F65, | |
1148 | PREFIX_VEX_0F66, | |
1149 | PREFIX_VEX_0F67, | |
1150 | PREFIX_VEX_0F68, | |
1151 | PREFIX_VEX_0F69, | |
1152 | PREFIX_VEX_0F6A, | |
1153 | PREFIX_VEX_0F6B, | |
1154 | PREFIX_VEX_0F6C, | |
1155 | PREFIX_VEX_0F6D, | |
1156 | PREFIX_VEX_0F6E, | |
1157 | PREFIX_VEX_0F6F, | |
1158 | PREFIX_VEX_0F70, | |
1159 | PREFIX_VEX_0F71_REG_2, | |
1160 | PREFIX_VEX_0F71_REG_4, | |
1161 | PREFIX_VEX_0F71_REG_6, | |
1162 | PREFIX_VEX_0F72_REG_2, | |
1163 | PREFIX_VEX_0F72_REG_4, | |
1164 | PREFIX_VEX_0F72_REG_6, | |
1165 | PREFIX_VEX_0F73_REG_2, | |
1166 | PREFIX_VEX_0F73_REG_3, | |
1167 | PREFIX_VEX_0F73_REG_6, | |
1168 | PREFIX_VEX_0F73_REG_7, | |
1169 | PREFIX_VEX_0F74, | |
1170 | PREFIX_VEX_0F75, | |
1171 | PREFIX_VEX_0F76, | |
1172 | PREFIX_VEX_0F77, | |
1173 | PREFIX_VEX_0F7C, | |
1174 | PREFIX_VEX_0F7D, | |
1175 | PREFIX_VEX_0F7E, | |
1176 | PREFIX_VEX_0F7F, | |
43234a1e L |
1177 | PREFIX_VEX_0F90, |
1178 | PREFIX_VEX_0F91, | |
1179 | PREFIX_VEX_0F92, | |
1180 | PREFIX_VEX_0F93, | |
1181 | PREFIX_VEX_0F98, | |
1ba585e8 | 1182 | PREFIX_VEX_0F99, |
592a252b L |
1183 | PREFIX_VEX_0FC2, |
1184 | PREFIX_VEX_0FC4, | |
1185 | PREFIX_VEX_0FC5, | |
1186 | PREFIX_VEX_0FD0, | |
1187 | PREFIX_VEX_0FD1, | |
1188 | PREFIX_VEX_0FD2, | |
1189 | PREFIX_VEX_0FD3, | |
1190 | PREFIX_VEX_0FD4, | |
1191 | PREFIX_VEX_0FD5, | |
1192 | PREFIX_VEX_0FD6, | |
1193 | PREFIX_VEX_0FD7, | |
1194 | PREFIX_VEX_0FD8, | |
1195 | PREFIX_VEX_0FD9, | |
1196 | PREFIX_VEX_0FDA, | |
1197 | PREFIX_VEX_0FDB, | |
1198 | PREFIX_VEX_0FDC, | |
1199 | PREFIX_VEX_0FDD, | |
1200 | PREFIX_VEX_0FDE, | |
1201 | PREFIX_VEX_0FDF, | |
1202 | PREFIX_VEX_0FE0, | |
1203 | PREFIX_VEX_0FE1, | |
1204 | PREFIX_VEX_0FE2, | |
1205 | PREFIX_VEX_0FE3, | |
1206 | PREFIX_VEX_0FE4, | |
1207 | PREFIX_VEX_0FE5, | |
1208 | PREFIX_VEX_0FE6, | |
1209 | PREFIX_VEX_0FE7, | |
1210 | PREFIX_VEX_0FE8, | |
1211 | PREFIX_VEX_0FE9, | |
1212 | PREFIX_VEX_0FEA, | |
1213 | PREFIX_VEX_0FEB, | |
1214 | PREFIX_VEX_0FEC, | |
1215 | PREFIX_VEX_0FED, | |
1216 | PREFIX_VEX_0FEE, | |
1217 | PREFIX_VEX_0FEF, | |
1218 | PREFIX_VEX_0FF0, | |
1219 | PREFIX_VEX_0FF1, | |
1220 | PREFIX_VEX_0FF2, | |
1221 | PREFIX_VEX_0FF3, | |
1222 | PREFIX_VEX_0FF4, | |
1223 | PREFIX_VEX_0FF5, | |
1224 | PREFIX_VEX_0FF6, | |
1225 | PREFIX_VEX_0FF7, | |
1226 | PREFIX_VEX_0FF8, | |
1227 | PREFIX_VEX_0FF9, | |
1228 | PREFIX_VEX_0FFA, | |
1229 | PREFIX_VEX_0FFB, | |
1230 | PREFIX_VEX_0FFC, | |
1231 | PREFIX_VEX_0FFD, | |
1232 | PREFIX_VEX_0FFE, | |
1233 | PREFIX_VEX_0F3800, | |
1234 | PREFIX_VEX_0F3801, | |
1235 | PREFIX_VEX_0F3802, | |
1236 | PREFIX_VEX_0F3803, | |
1237 | PREFIX_VEX_0F3804, | |
1238 | PREFIX_VEX_0F3805, | |
1239 | PREFIX_VEX_0F3806, | |
1240 | PREFIX_VEX_0F3807, | |
1241 | PREFIX_VEX_0F3808, | |
1242 | PREFIX_VEX_0F3809, | |
1243 | PREFIX_VEX_0F380A, | |
1244 | PREFIX_VEX_0F380B, | |
1245 | PREFIX_VEX_0F380C, | |
1246 | PREFIX_VEX_0F380D, | |
1247 | PREFIX_VEX_0F380E, | |
1248 | PREFIX_VEX_0F380F, | |
1249 | PREFIX_VEX_0F3813, | |
6c30d220 | 1250 | PREFIX_VEX_0F3816, |
592a252b L |
1251 | PREFIX_VEX_0F3817, |
1252 | PREFIX_VEX_0F3818, | |
1253 | PREFIX_VEX_0F3819, | |
1254 | PREFIX_VEX_0F381A, | |
1255 | PREFIX_VEX_0F381C, | |
1256 | PREFIX_VEX_0F381D, | |
1257 | PREFIX_VEX_0F381E, | |
1258 | PREFIX_VEX_0F3820, | |
1259 | PREFIX_VEX_0F3821, | |
1260 | PREFIX_VEX_0F3822, | |
1261 | PREFIX_VEX_0F3823, | |
1262 | PREFIX_VEX_0F3824, | |
1263 | PREFIX_VEX_0F3825, | |
1264 | PREFIX_VEX_0F3828, | |
1265 | PREFIX_VEX_0F3829, | |
1266 | PREFIX_VEX_0F382A, | |
1267 | PREFIX_VEX_0F382B, | |
1268 | PREFIX_VEX_0F382C, | |
1269 | PREFIX_VEX_0F382D, | |
1270 | PREFIX_VEX_0F382E, | |
1271 | PREFIX_VEX_0F382F, | |
1272 | PREFIX_VEX_0F3830, | |
1273 | PREFIX_VEX_0F3831, | |
1274 | PREFIX_VEX_0F3832, | |
1275 | PREFIX_VEX_0F3833, | |
1276 | PREFIX_VEX_0F3834, | |
1277 | PREFIX_VEX_0F3835, | |
6c30d220 | 1278 | PREFIX_VEX_0F3836, |
592a252b L |
1279 | PREFIX_VEX_0F3837, |
1280 | PREFIX_VEX_0F3838, | |
1281 | PREFIX_VEX_0F3839, | |
1282 | PREFIX_VEX_0F383A, | |
1283 | PREFIX_VEX_0F383B, | |
1284 | PREFIX_VEX_0F383C, | |
1285 | PREFIX_VEX_0F383D, | |
1286 | PREFIX_VEX_0F383E, | |
1287 | PREFIX_VEX_0F383F, | |
1288 | PREFIX_VEX_0F3840, | |
1289 | PREFIX_VEX_0F3841, | |
6c30d220 L |
1290 | PREFIX_VEX_0F3845, |
1291 | PREFIX_VEX_0F3846, | |
1292 | PREFIX_VEX_0F3847, | |
1293 | PREFIX_VEX_0F3858, | |
1294 | PREFIX_VEX_0F3859, | |
1295 | PREFIX_VEX_0F385A, | |
1296 | PREFIX_VEX_0F3878, | |
1297 | PREFIX_VEX_0F3879, | |
1298 | PREFIX_VEX_0F388C, | |
1299 | PREFIX_VEX_0F388E, | |
1300 | PREFIX_VEX_0F3890, | |
1301 | PREFIX_VEX_0F3891, | |
1302 | PREFIX_VEX_0F3892, | |
1303 | PREFIX_VEX_0F3893, | |
592a252b L |
1304 | PREFIX_VEX_0F3896, |
1305 | PREFIX_VEX_0F3897, | |
1306 | PREFIX_VEX_0F3898, | |
1307 | PREFIX_VEX_0F3899, | |
1308 | PREFIX_VEX_0F389A, | |
1309 | PREFIX_VEX_0F389B, | |
1310 | PREFIX_VEX_0F389C, | |
1311 | PREFIX_VEX_0F389D, | |
1312 | PREFIX_VEX_0F389E, | |
1313 | PREFIX_VEX_0F389F, | |
1314 | PREFIX_VEX_0F38A6, | |
1315 | PREFIX_VEX_0F38A7, | |
1316 | PREFIX_VEX_0F38A8, | |
1317 | PREFIX_VEX_0F38A9, | |
1318 | PREFIX_VEX_0F38AA, | |
1319 | PREFIX_VEX_0F38AB, | |
1320 | PREFIX_VEX_0F38AC, | |
1321 | PREFIX_VEX_0F38AD, | |
1322 | PREFIX_VEX_0F38AE, | |
1323 | PREFIX_VEX_0F38AF, | |
1324 | PREFIX_VEX_0F38B6, | |
1325 | PREFIX_VEX_0F38B7, | |
1326 | PREFIX_VEX_0F38B8, | |
1327 | PREFIX_VEX_0F38B9, | |
1328 | PREFIX_VEX_0F38BA, | |
1329 | PREFIX_VEX_0F38BB, | |
1330 | PREFIX_VEX_0F38BC, | |
1331 | PREFIX_VEX_0F38BD, | |
1332 | PREFIX_VEX_0F38BE, | |
1333 | PREFIX_VEX_0F38BF, | |
48521003 | 1334 | PREFIX_VEX_0F38CF, |
592a252b L |
1335 | PREFIX_VEX_0F38DB, |
1336 | PREFIX_VEX_0F38DC, | |
1337 | PREFIX_VEX_0F38DD, | |
1338 | PREFIX_VEX_0F38DE, | |
1339 | PREFIX_VEX_0F38DF, | |
f12dc422 L |
1340 | PREFIX_VEX_0F38F2, |
1341 | PREFIX_VEX_0F38F3_REG_1, | |
1342 | PREFIX_VEX_0F38F3_REG_2, | |
1343 | PREFIX_VEX_0F38F3_REG_3, | |
6c30d220 L |
1344 | PREFIX_VEX_0F38F5, |
1345 | PREFIX_VEX_0F38F6, | |
f12dc422 | 1346 | PREFIX_VEX_0F38F7, |
6c30d220 L |
1347 | PREFIX_VEX_0F3A00, |
1348 | PREFIX_VEX_0F3A01, | |
1349 | PREFIX_VEX_0F3A02, | |
592a252b L |
1350 | PREFIX_VEX_0F3A04, |
1351 | PREFIX_VEX_0F3A05, | |
1352 | PREFIX_VEX_0F3A06, | |
1353 | PREFIX_VEX_0F3A08, | |
1354 | PREFIX_VEX_0F3A09, | |
1355 | PREFIX_VEX_0F3A0A, | |
1356 | PREFIX_VEX_0F3A0B, | |
1357 | PREFIX_VEX_0F3A0C, | |
1358 | PREFIX_VEX_0F3A0D, | |
1359 | PREFIX_VEX_0F3A0E, | |
1360 | PREFIX_VEX_0F3A0F, | |
1361 | PREFIX_VEX_0F3A14, | |
1362 | PREFIX_VEX_0F3A15, | |
1363 | PREFIX_VEX_0F3A16, | |
1364 | PREFIX_VEX_0F3A17, | |
1365 | PREFIX_VEX_0F3A18, | |
1366 | PREFIX_VEX_0F3A19, | |
1367 | PREFIX_VEX_0F3A1D, | |
1368 | PREFIX_VEX_0F3A20, | |
1369 | PREFIX_VEX_0F3A21, | |
1370 | PREFIX_VEX_0F3A22, | |
43234a1e | 1371 | PREFIX_VEX_0F3A30, |
1ba585e8 | 1372 | PREFIX_VEX_0F3A31, |
43234a1e | 1373 | PREFIX_VEX_0F3A32, |
1ba585e8 | 1374 | PREFIX_VEX_0F3A33, |
6c30d220 L |
1375 | PREFIX_VEX_0F3A38, |
1376 | PREFIX_VEX_0F3A39, | |
592a252b L |
1377 | PREFIX_VEX_0F3A40, |
1378 | PREFIX_VEX_0F3A41, | |
1379 | PREFIX_VEX_0F3A42, | |
1380 | PREFIX_VEX_0F3A44, | |
6c30d220 | 1381 | PREFIX_VEX_0F3A46, |
592a252b L |
1382 | PREFIX_VEX_0F3A48, |
1383 | PREFIX_VEX_0F3A49, | |
1384 | PREFIX_VEX_0F3A4A, | |
1385 | PREFIX_VEX_0F3A4B, | |
1386 | PREFIX_VEX_0F3A4C, | |
1387 | PREFIX_VEX_0F3A5C, | |
1388 | PREFIX_VEX_0F3A5D, | |
1389 | PREFIX_VEX_0F3A5E, | |
1390 | PREFIX_VEX_0F3A5F, | |
1391 | PREFIX_VEX_0F3A60, | |
1392 | PREFIX_VEX_0F3A61, | |
1393 | PREFIX_VEX_0F3A62, | |
1394 | PREFIX_VEX_0F3A63, | |
1395 | PREFIX_VEX_0F3A68, | |
1396 | PREFIX_VEX_0F3A69, | |
1397 | PREFIX_VEX_0F3A6A, | |
1398 | PREFIX_VEX_0F3A6B, | |
1399 | PREFIX_VEX_0F3A6C, | |
1400 | PREFIX_VEX_0F3A6D, | |
1401 | PREFIX_VEX_0F3A6E, | |
1402 | PREFIX_VEX_0F3A6F, | |
1403 | PREFIX_VEX_0F3A78, | |
1404 | PREFIX_VEX_0F3A79, | |
1405 | PREFIX_VEX_0F3A7A, | |
1406 | PREFIX_VEX_0F3A7B, | |
1407 | PREFIX_VEX_0F3A7C, | |
1408 | PREFIX_VEX_0F3A7D, | |
1409 | PREFIX_VEX_0F3A7E, | |
1410 | PREFIX_VEX_0F3A7F, | |
48521003 IT |
1411 | PREFIX_VEX_0F3ACE, |
1412 | PREFIX_VEX_0F3ACF, | |
6c30d220 | 1413 | PREFIX_VEX_0F3ADF, |
43234a1e L |
1414 | PREFIX_VEX_0F3AF0, |
1415 | ||
1416 | PREFIX_EVEX_0F10, | |
1417 | PREFIX_EVEX_0F11, | |
1418 | PREFIX_EVEX_0F12, | |
43234a1e | 1419 | PREFIX_EVEX_0F16, |
43234a1e | 1420 | PREFIX_EVEX_0F2A, |
43234a1e L |
1421 | PREFIX_EVEX_0F2C, |
1422 | PREFIX_EVEX_0F2D, | |
1423 | PREFIX_EVEX_0F2E, | |
1424 | PREFIX_EVEX_0F2F, | |
1425 | PREFIX_EVEX_0F51, | |
1426 | PREFIX_EVEX_0F58, | |
1427 | PREFIX_EVEX_0F59, | |
1428 | PREFIX_EVEX_0F5A, | |
1429 | PREFIX_EVEX_0F5B, | |
1430 | PREFIX_EVEX_0F5C, | |
1431 | PREFIX_EVEX_0F5D, | |
1432 | PREFIX_EVEX_0F5E, | |
1433 | PREFIX_EVEX_0F5F, | |
1434 | PREFIX_EVEX_0F62, | |
1ba585e8 IT |
1435 | PREFIX_EVEX_0F64, |
1436 | PREFIX_EVEX_0F65, | |
43234a1e L |
1437 | PREFIX_EVEX_0F66, |
1438 | PREFIX_EVEX_0F6A, | |
1ba585e8 | 1439 | PREFIX_EVEX_0F6B, |
43234a1e L |
1440 | PREFIX_EVEX_0F6C, |
1441 | PREFIX_EVEX_0F6D, | |
1442 | PREFIX_EVEX_0F6E, | |
1443 | PREFIX_EVEX_0F6F, | |
1444 | PREFIX_EVEX_0F70, | |
1ba585e8 IT |
1445 | PREFIX_EVEX_0F71_REG_2, |
1446 | PREFIX_EVEX_0F71_REG_4, | |
1447 | PREFIX_EVEX_0F71_REG_6, | |
43234a1e L |
1448 | PREFIX_EVEX_0F72_REG_0, |
1449 | PREFIX_EVEX_0F72_REG_1, | |
1450 | PREFIX_EVEX_0F72_REG_2, | |
1451 | PREFIX_EVEX_0F72_REG_4, | |
1452 | PREFIX_EVEX_0F72_REG_6, | |
1453 | PREFIX_EVEX_0F73_REG_2, | |
1ba585e8 | 1454 | PREFIX_EVEX_0F73_REG_3, |
43234a1e | 1455 | PREFIX_EVEX_0F73_REG_6, |
1ba585e8 IT |
1456 | PREFIX_EVEX_0F73_REG_7, |
1457 | PREFIX_EVEX_0F74, | |
1458 | PREFIX_EVEX_0F75, | |
43234a1e L |
1459 | PREFIX_EVEX_0F76, |
1460 | PREFIX_EVEX_0F78, | |
1461 | PREFIX_EVEX_0F79, | |
1462 | PREFIX_EVEX_0F7A, | |
1463 | PREFIX_EVEX_0F7B, | |
1464 | PREFIX_EVEX_0F7E, | |
1465 | PREFIX_EVEX_0F7F, | |
1466 | PREFIX_EVEX_0FC2, | |
1ba585e8 IT |
1467 | PREFIX_EVEX_0FC4, |
1468 | PREFIX_EVEX_0FC5, | |
43234a1e L |
1469 | PREFIX_EVEX_0FD2, |
1470 | PREFIX_EVEX_0FD3, | |
1471 | PREFIX_EVEX_0FD4, | |
1472 | PREFIX_EVEX_0FD6, | |
1473 | PREFIX_EVEX_0FDB, | |
1474 | PREFIX_EVEX_0FDF, | |
1475 | PREFIX_EVEX_0FE2, | |
1476 | PREFIX_EVEX_0FE6, | |
1477 | PREFIX_EVEX_0FE7, | |
1478 | PREFIX_EVEX_0FEB, | |
1479 | PREFIX_EVEX_0FEF, | |
1480 | PREFIX_EVEX_0FF2, | |
1481 | PREFIX_EVEX_0FF3, | |
1482 | PREFIX_EVEX_0FF4, | |
1483 | PREFIX_EVEX_0FFA, | |
1484 | PREFIX_EVEX_0FFB, | |
1485 | PREFIX_EVEX_0FFE, | |
43234a1e | 1486 | PREFIX_EVEX_0F380D, |
1ba585e8 | 1487 | PREFIX_EVEX_0F3810, |
43234a1e L |
1488 | PREFIX_EVEX_0F3811, |
1489 | PREFIX_EVEX_0F3812, | |
1490 | PREFIX_EVEX_0F3813, | |
1491 | PREFIX_EVEX_0F3814, | |
1492 | PREFIX_EVEX_0F3815, | |
1493 | PREFIX_EVEX_0F3816, | |
43234a1e L |
1494 | PREFIX_EVEX_0F3819, |
1495 | PREFIX_EVEX_0F381A, | |
1496 | PREFIX_EVEX_0F381B, | |
1497 | PREFIX_EVEX_0F381E, | |
1498 | PREFIX_EVEX_0F381F, | |
1ba585e8 | 1499 | PREFIX_EVEX_0F3820, |
43234a1e L |
1500 | PREFIX_EVEX_0F3821, |
1501 | PREFIX_EVEX_0F3822, | |
1502 | PREFIX_EVEX_0F3823, | |
1503 | PREFIX_EVEX_0F3824, | |
1504 | PREFIX_EVEX_0F3825, | |
1ba585e8 | 1505 | PREFIX_EVEX_0F3826, |
43234a1e L |
1506 | PREFIX_EVEX_0F3827, |
1507 | PREFIX_EVEX_0F3828, | |
1508 | PREFIX_EVEX_0F3829, | |
1509 | PREFIX_EVEX_0F382A, | |
1ba585e8 | 1510 | PREFIX_EVEX_0F382B, |
43234a1e L |
1511 | PREFIX_EVEX_0F382C, |
1512 | PREFIX_EVEX_0F382D, | |
1ba585e8 | 1513 | PREFIX_EVEX_0F3830, |
43234a1e L |
1514 | PREFIX_EVEX_0F3831, |
1515 | PREFIX_EVEX_0F3832, | |
1516 | PREFIX_EVEX_0F3833, | |
1517 | PREFIX_EVEX_0F3834, | |
1518 | PREFIX_EVEX_0F3835, | |
1519 | PREFIX_EVEX_0F3836, | |
1520 | PREFIX_EVEX_0F3837, | |
1ba585e8 | 1521 | PREFIX_EVEX_0F3838, |
43234a1e L |
1522 | PREFIX_EVEX_0F3839, |
1523 | PREFIX_EVEX_0F383A, | |
1524 | PREFIX_EVEX_0F383B, | |
1525 | PREFIX_EVEX_0F383D, | |
1526 | PREFIX_EVEX_0F383F, | |
1527 | PREFIX_EVEX_0F3840, | |
1528 | PREFIX_EVEX_0F3842, | |
1529 | PREFIX_EVEX_0F3843, | |
1530 | PREFIX_EVEX_0F3844, | |
1531 | PREFIX_EVEX_0F3845, | |
1532 | PREFIX_EVEX_0F3846, | |
1533 | PREFIX_EVEX_0F3847, | |
1534 | PREFIX_EVEX_0F384C, | |
1535 | PREFIX_EVEX_0F384D, | |
1536 | PREFIX_EVEX_0F384E, | |
1537 | PREFIX_EVEX_0F384F, | |
8cfcb765 IT |
1538 | PREFIX_EVEX_0F3850, |
1539 | PREFIX_EVEX_0F3851, | |
47acf0bd IT |
1540 | PREFIX_EVEX_0F3852, |
1541 | PREFIX_EVEX_0F3853, | |
ee6872be | 1542 | PREFIX_EVEX_0F3854, |
620214f7 | 1543 | PREFIX_EVEX_0F3855, |
43234a1e L |
1544 | PREFIX_EVEX_0F3859, |
1545 | PREFIX_EVEX_0F385A, | |
1546 | PREFIX_EVEX_0F385B, | |
53467f57 IT |
1547 | PREFIX_EVEX_0F3862, |
1548 | PREFIX_EVEX_0F3863, | |
43234a1e L |
1549 | PREFIX_EVEX_0F3864, |
1550 | PREFIX_EVEX_0F3865, | |
1ba585e8 | 1551 | PREFIX_EVEX_0F3866, |
9186c494 | 1552 | PREFIX_EVEX_0F3868, |
53467f57 IT |
1553 | PREFIX_EVEX_0F3870, |
1554 | PREFIX_EVEX_0F3871, | |
1555 | PREFIX_EVEX_0F3872, | |
1556 | PREFIX_EVEX_0F3873, | |
1ba585e8 | 1557 | PREFIX_EVEX_0F3875, |
43234a1e L |
1558 | PREFIX_EVEX_0F3876, |
1559 | PREFIX_EVEX_0F3877, | |
1ba585e8 IT |
1560 | PREFIX_EVEX_0F387A, |
1561 | PREFIX_EVEX_0F387B, | |
43234a1e | 1562 | PREFIX_EVEX_0F387C, |
1ba585e8 | 1563 | PREFIX_EVEX_0F387D, |
43234a1e L |
1564 | PREFIX_EVEX_0F387E, |
1565 | PREFIX_EVEX_0F387F, | |
14f195c9 | 1566 | PREFIX_EVEX_0F3883, |
43234a1e L |
1567 | PREFIX_EVEX_0F3888, |
1568 | PREFIX_EVEX_0F3889, | |
1569 | PREFIX_EVEX_0F388A, | |
1570 | PREFIX_EVEX_0F388B, | |
1ba585e8 | 1571 | PREFIX_EVEX_0F388D, |
ee6872be | 1572 | PREFIX_EVEX_0F388F, |
43234a1e L |
1573 | PREFIX_EVEX_0F3890, |
1574 | PREFIX_EVEX_0F3891, | |
1575 | PREFIX_EVEX_0F3892, | |
1576 | PREFIX_EVEX_0F3893, | |
43234a1e L |
1577 | PREFIX_EVEX_0F389A, |
1578 | PREFIX_EVEX_0F389B, | |
43234a1e L |
1579 | PREFIX_EVEX_0F38A0, |
1580 | PREFIX_EVEX_0F38A1, | |
1581 | PREFIX_EVEX_0F38A2, | |
1582 | PREFIX_EVEX_0F38A3, | |
43234a1e L |
1583 | PREFIX_EVEX_0F38AA, |
1584 | PREFIX_EVEX_0F38AB, | |
2cc1b5aa IT |
1585 | PREFIX_EVEX_0F38B4, |
1586 | PREFIX_EVEX_0F38B5, | |
43234a1e L |
1587 | PREFIX_EVEX_0F38C4, |
1588 | PREFIX_EVEX_0F38C6_REG_1, | |
1589 | PREFIX_EVEX_0F38C6_REG_2, | |
1590 | PREFIX_EVEX_0F38C6_REG_5, | |
1591 | PREFIX_EVEX_0F38C6_REG_6, | |
1592 | PREFIX_EVEX_0F38C7_REG_1, | |
1593 | PREFIX_EVEX_0F38C7_REG_2, | |
1594 | PREFIX_EVEX_0F38C7_REG_5, | |
1595 | PREFIX_EVEX_0F38C7_REG_6, | |
1596 | PREFIX_EVEX_0F38C8, | |
1597 | PREFIX_EVEX_0F38CA, | |
1598 | PREFIX_EVEX_0F38CB, | |
1599 | PREFIX_EVEX_0F38CC, | |
1600 | PREFIX_EVEX_0F38CD, | |
1601 | ||
1602 | PREFIX_EVEX_0F3A00, | |
1603 | PREFIX_EVEX_0F3A01, | |
1604 | PREFIX_EVEX_0F3A03, | |
43234a1e L |
1605 | PREFIX_EVEX_0F3A05, |
1606 | PREFIX_EVEX_0F3A08, | |
1607 | PREFIX_EVEX_0F3A09, | |
1608 | PREFIX_EVEX_0F3A0A, | |
1609 | PREFIX_EVEX_0F3A0B, | |
1ba585e8 IT |
1610 | PREFIX_EVEX_0F3A14, |
1611 | PREFIX_EVEX_0F3A15, | |
90a915bf | 1612 | PREFIX_EVEX_0F3A16, |
43234a1e L |
1613 | PREFIX_EVEX_0F3A17, |
1614 | PREFIX_EVEX_0F3A18, | |
1615 | PREFIX_EVEX_0F3A19, | |
1616 | PREFIX_EVEX_0F3A1A, | |
1617 | PREFIX_EVEX_0F3A1B, | |
43234a1e L |
1618 | PREFIX_EVEX_0F3A1E, |
1619 | PREFIX_EVEX_0F3A1F, | |
1ba585e8 | 1620 | PREFIX_EVEX_0F3A20, |
43234a1e | 1621 | PREFIX_EVEX_0F3A21, |
90a915bf | 1622 | PREFIX_EVEX_0F3A22, |
43234a1e L |
1623 | PREFIX_EVEX_0F3A23, |
1624 | PREFIX_EVEX_0F3A25, | |
1625 | PREFIX_EVEX_0F3A26, | |
1626 | PREFIX_EVEX_0F3A27, | |
1627 | PREFIX_EVEX_0F3A38, | |
1628 | PREFIX_EVEX_0F3A39, | |
1629 | PREFIX_EVEX_0F3A3A, | |
1630 | PREFIX_EVEX_0F3A3B, | |
1ba585e8 IT |
1631 | PREFIX_EVEX_0F3A3E, |
1632 | PREFIX_EVEX_0F3A3F, | |
1633 | PREFIX_EVEX_0F3A42, | |
43234a1e | 1634 | PREFIX_EVEX_0F3A43, |
90a915bf IT |
1635 | PREFIX_EVEX_0F3A50, |
1636 | PREFIX_EVEX_0F3A51, | |
43234a1e | 1637 | PREFIX_EVEX_0F3A54, |
90a915bf IT |
1638 | PREFIX_EVEX_0F3A55, |
1639 | PREFIX_EVEX_0F3A56, | |
1640 | PREFIX_EVEX_0F3A57, | |
1641 | PREFIX_EVEX_0F3A66, | |
53467f57 IT |
1642 | PREFIX_EVEX_0F3A67, |
1643 | PREFIX_EVEX_0F3A70, | |
1644 | PREFIX_EVEX_0F3A71, | |
1645 | PREFIX_EVEX_0F3A72, | |
48521003 | 1646 | PREFIX_EVEX_0F3A73, |
51e7da1b | 1647 | }; |
4e7d34a6 | 1648 | |
51e7da1b L |
1649 | enum |
1650 | { | |
1651 | X86_64_06 = 0, | |
3873ba12 | 1652 | X86_64_07, |
1673df32 | 1653 | X86_64_0E, |
3873ba12 L |
1654 | X86_64_16, |
1655 | X86_64_17, | |
1656 | X86_64_1E, | |
1657 | X86_64_1F, | |
1658 | X86_64_27, | |
1659 | X86_64_2F, | |
1660 | X86_64_37, | |
1661 | X86_64_3F, | |
1662 | X86_64_60, | |
1663 | X86_64_61, | |
1664 | X86_64_62, | |
1665 | X86_64_63, | |
1666 | X86_64_6D, | |
1667 | X86_64_6F, | |
d039fef3 | 1668 | X86_64_82, |
3873ba12 | 1669 | X86_64_9A, |
aeab2b26 JB |
1670 | X86_64_C2, |
1671 | X86_64_C3, | |
3873ba12 L |
1672 | X86_64_C4, |
1673 | X86_64_C5, | |
1674 | X86_64_CE, | |
1675 | X86_64_D4, | |
1676 | X86_64_D5, | |
a72d2af2 L |
1677 | X86_64_E8, |
1678 | X86_64_E9, | |
3873ba12 L |
1679 | X86_64_EA, |
1680 | X86_64_0F01_REG_0, | |
1681 | X86_64_0F01_REG_1, | |
1682 | X86_64_0F01_REG_2, | |
1683 | X86_64_0F01_REG_3 | |
51e7da1b | 1684 | }; |
4e7d34a6 | 1685 | |
51e7da1b L |
1686 | enum |
1687 | { | |
1688 | THREE_BYTE_0F38 = 0, | |
1f334aeb | 1689 | THREE_BYTE_0F3A |
51e7da1b | 1690 | }; |
4e7d34a6 | 1691 | |
f88c9eb0 SP |
1692 | enum |
1693 | { | |
5dd85c99 SP |
1694 | XOP_08 = 0, |
1695 | XOP_09, | |
f88c9eb0 SP |
1696 | XOP_0A |
1697 | }; | |
1698 | ||
51e7da1b L |
1699 | enum |
1700 | { | |
1701 | VEX_0F = 0, | |
3873ba12 L |
1702 | VEX_0F38, |
1703 | VEX_0F3A | |
51e7da1b | 1704 | }; |
c0f3af97 | 1705 | |
43234a1e L |
1706 | enum |
1707 | { | |
1708 | EVEX_0F = 0, | |
1709 | EVEX_0F38, | |
1710 | EVEX_0F3A | |
1711 | }; | |
1712 | ||
51e7da1b L |
1713 | enum |
1714 | { | |
ec6f095a | 1715 | VEX_LEN_0F12_P_0_M_0 = 0, |
592a252b | 1716 | VEX_LEN_0F12_P_0_M_1, |
18897deb | 1717 | #define VEX_LEN_0F12_P_2_M_0 VEX_LEN_0F12_P_0_M_0 |
592a252b L |
1718 | VEX_LEN_0F13_M_0, |
1719 | VEX_LEN_0F16_P_0_M_0, | |
1720 | VEX_LEN_0F16_P_0_M_1, | |
18897deb | 1721 | #define VEX_LEN_0F16_P_2_M_0 VEX_LEN_0F16_P_0_M_0 |
592a252b | 1722 | VEX_LEN_0F17_M_0, |
43234a1e | 1723 | VEX_LEN_0F41_P_0, |
1ba585e8 | 1724 | VEX_LEN_0F41_P_2, |
43234a1e | 1725 | VEX_LEN_0F42_P_0, |
1ba585e8 | 1726 | VEX_LEN_0F42_P_2, |
43234a1e | 1727 | VEX_LEN_0F44_P_0, |
1ba585e8 | 1728 | VEX_LEN_0F44_P_2, |
43234a1e | 1729 | VEX_LEN_0F45_P_0, |
1ba585e8 | 1730 | VEX_LEN_0F45_P_2, |
43234a1e | 1731 | VEX_LEN_0F46_P_0, |
1ba585e8 | 1732 | VEX_LEN_0F46_P_2, |
43234a1e | 1733 | VEX_LEN_0F47_P_0, |
1ba585e8 IT |
1734 | VEX_LEN_0F47_P_2, |
1735 | VEX_LEN_0F4A_P_0, | |
1736 | VEX_LEN_0F4A_P_2, | |
1737 | VEX_LEN_0F4B_P_0, | |
43234a1e | 1738 | VEX_LEN_0F4B_P_2, |
592a252b | 1739 | VEX_LEN_0F6E_P_2, |
ec6f095a | 1740 | VEX_LEN_0F77_P_0, |
592a252b L |
1741 | VEX_LEN_0F7E_P_1, |
1742 | VEX_LEN_0F7E_P_2, | |
43234a1e | 1743 | VEX_LEN_0F90_P_0, |
1ba585e8 | 1744 | VEX_LEN_0F90_P_2, |
43234a1e | 1745 | VEX_LEN_0F91_P_0, |
1ba585e8 | 1746 | VEX_LEN_0F91_P_2, |
43234a1e | 1747 | VEX_LEN_0F92_P_0, |
90a915bf | 1748 | VEX_LEN_0F92_P_2, |
1ba585e8 | 1749 | VEX_LEN_0F92_P_3, |
43234a1e | 1750 | VEX_LEN_0F93_P_0, |
90a915bf | 1751 | VEX_LEN_0F93_P_2, |
1ba585e8 | 1752 | VEX_LEN_0F93_P_3, |
43234a1e | 1753 | VEX_LEN_0F98_P_0, |
1ba585e8 IT |
1754 | VEX_LEN_0F98_P_2, |
1755 | VEX_LEN_0F99_P_0, | |
1756 | VEX_LEN_0F99_P_2, | |
592a252b L |
1757 | VEX_LEN_0FAE_R_2_M_0, |
1758 | VEX_LEN_0FAE_R_3_M_0, | |
592a252b L |
1759 | VEX_LEN_0FC4_P_2, |
1760 | VEX_LEN_0FC5_P_2, | |
592a252b | 1761 | VEX_LEN_0FD6_P_2, |
592a252b | 1762 | VEX_LEN_0FF7_P_2, |
6c30d220 L |
1763 | VEX_LEN_0F3816_P_2, |
1764 | VEX_LEN_0F3819_P_2, | |
592a252b | 1765 | VEX_LEN_0F381A_P_2_M_0, |
6c30d220 | 1766 | VEX_LEN_0F3836_P_2, |
592a252b | 1767 | VEX_LEN_0F3841_P_2, |
6c30d220 | 1768 | VEX_LEN_0F385A_P_2_M_0, |
592a252b | 1769 | VEX_LEN_0F38DB_P_2, |
f12dc422 L |
1770 | VEX_LEN_0F38F2_P_0, |
1771 | VEX_LEN_0F38F3_R_1_P_0, | |
1772 | VEX_LEN_0F38F3_R_2_P_0, | |
1773 | VEX_LEN_0F38F3_R_3_P_0, | |
6c30d220 L |
1774 | VEX_LEN_0F38F5_P_0, |
1775 | VEX_LEN_0F38F5_P_1, | |
1776 | VEX_LEN_0F38F5_P_3, | |
1777 | VEX_LEN_0F38F6_P_3, | |
f12dc422 | 1778 | VEX_LEN_0F38F7_P_0, |
6c30d220 L |
1779 | VEX_LEN_0F38F7_P_1, |
1780 | VEX_LEN_0F38F7_P_2, | |
1781 | VEX_LEN_0F38F7_P_3, | |
1782 | VEX_LEN_0F3A00_P_2, | |
1783 | VEX_LEN_0F3A01_P_2, | |
592a252b | 1784 | VEX_LEN_0F3A06_P_2, |
592a252b L |
1785 | VEX_LEN_0F3A14_P_2, |
1786 | VEX_LEN_0F3A15_P_2, | |
1787 | VEX_LEN_0F3A16_P_2, | |
1788 | VEX_LEN_0F3A17_P_2, | |
1789 | VEX_LEN_0F3A18_P_2, | |
1790 | VEX_LEN_0F3A19_P_2, | |
1791 | VEX_LEN_0F3A20_P_2, | |
1792 | VEX_LEN_0F3A21_P_2, | |
1793 | VEX_LEN_0F3A22_P_2, | |
43234a1e | 1794 | VEX_LEN_0F3A30_P_2, |
1ba585e8 | 1795 | VEX_LEN_0F3A31_P_2, |
43234a1e | 1796 | VEX_LEN_0F3A32_P_2, |
1ba585e8 | 1797 | VEX_LEN_0F3A33_P_2, |
6c30d220 L |
1798 | VEX_LEN_0F3A38_P_2, |
1799 | VEX_LEN_0F3A39_P_2, | |
592a252b | 1800 | VEX_LEN_0F3A41_P_2, |
6c30d220 | 1801 | VEX_LEN_0F3A46_P_2, |
592a252b L |
1802 | VEX_LEN_0F3A60_P_2, |
1803 | VEX_LEN_0F3A61_P_2, | |
1804 | VEX_LEN_0F3A62_P_2, | |
1805 | VEX_LEN_0F3A63_P_2, | |
1806 | VEX_LEN_0F3A6A_P_2, | |
1807 | VEX_LEN_0F3A6B_P_2, | |
1808 | VEX_LEN_0F3A6E_P_2, | |
1809 | VEX_LEN_0F3A6F_P_2, | |
1810 | VEX_LEN_0F3A7A_P_2, | |
1811 | VEX_LEN_0F3A7B_P_2, | |
1812 | VEX_LEN_0F3A7E_P_2, | |
1813 | VEX_LEN_0F3A7F_P_2, | |
1814 | VEX_LEN_0F3ADF_P_2, | |
6c30d220 | 1815 | VEX_LEN_0F3AF0_P_3, |
ff688e1f L |
1816 | VEX_LEN_0FXOP_08_CC, |
1817 | VEX_LEN_0FXOP_08_CD, | |
1818 | VEX_LEN_0FXOP_08_CE, | |
1819 | VEX_LEN_0FXOP_08_CF, | |
1820 | VEX_LEN_0FXOP_08_EC, | |
1821 | VEX_LEN_0FXOP_08_ED, | |
1822 | VEX_LEN_0FXOP_08_EE, | |
1823 | VEX_LEN_0FXOP_08_EF, | |
592a252b L |
1824 | VEX_LEN_0FXOP_09_80, |
1825 | VEX_LEN_0FXOP_09_81 | |
51e7da1b | 1826 | }; |
c0f3af97 | 1827 | |
04e2a182 L |
1828 | enum |
1829 | { | |
1830 | EVEX_LEN_0F6E_P_2 = 0, | |
1831 | EVEX_LEN_0F7E_P_1, | |
1832 | EVEX_LEN_0F7E_P_2, | |
e74d9fa9 JB |
1833 | EVEX_LEN_0FC4_P_2, |
1834 | EVEX_LEN_0FC5_P_2, | |
12efd68d | 1835 | EVEX_LEN_0FD6_P_2, |
f0a6222e L |
1836 | EVEX_LEN_0F3819_P_2_W_0, |
1837 | EVEX_LEN_0F3819_P_2_W_1, | |
1838 | EVEX_LEN_0F381A_P_2_W_0, | |
1839 | EVEX_LEN_0F381A_P_2_W_1, | |
1840 | EVEX_LEN_0F381B_P_2_W_0, | |
1841 | EVEX_LEN_0F381B_P_2_W_1, | |
1842 | EVEX_LEN_0F385A_P_2_W_0, | |
1843 | EVEX_LEN_0F385A_P_2_W_1, | |
1844 | EVEX_LEN_0F385B_P_2_W_0, | |
1845 | EVEX_LEN_0F385B_P_2_W_1, | |
e395f487 L |
1846 | EVEX_LEN_0F38C6_REG_1_PREFIX_2, |
1847 | EVEX_LEN_0F38C6_REG_2_PREFIX_2, | |
1848 | EVEX_LEN_0F38C6_REG_5_PREFIX_2, | |
1849 | EVEX_LEN_0F38C6_REG_6_PREFIX_2, | |
1850 | EVEX_LEN_0F38C7_R_1_P_2_W_0, | |
1851 | EVEX_LEN_0F38C7_R_1_P_2_W_1, | |
1852 | EVEX_LEN_0F38C7_R_2_P_2_W_0, | |
1853 | EVEX_LEN_0F38C7_R_2_P_2_W_1, | |
1854 | EVEX_LEN_0F38C7_R_5_P_2_W_0, | |
1855 | EVEX_LEN_0F38C7_R_5_P_2_W_1, | |
1856 | EVEX_LEN_0F38C7_R_6_P_2_W_0, | |
1857 | EVEX_LEN_0F38C7_R_6_P_2_W_1, | |
e74d9fa9 JB |
1858 | EVEX_LEN_0F3A14_P_2, |
1859 | EVEX_LEN_0F3A15_P_2, | |
1860 | EVEX_LEN_0F3A16_P_2, | |
1861 | EVEX_LEN_0F3A17_P_2, | |
12efd68d L |
1862 | EVEX_LEN_0F3A18_P_2_W_0, |
1863 | EVEX_LEN_0F3A18_P_2_W_1, | |
1864 | EVEX_LEN_0F3A19_P_2_W_0, | |
1865 | EVEX_LEN_0F3A19_P_2_W_1, | |
1866 | EVEX_LEN_0F3A1A_P_2_W_0, | |
1867 | EVEX_LEN_0F3A1A_P_2_W_1, | |
1868 | EVEX_LEN_0F3A1B_P_2_W_0, | |
6e1c90b7 | 1869 | EVEX_LEN_0F3A1B_P_2_W_1, |
e74d9fa9 JB |
1870 | EVEX_LEN_0F3A20_P_2, |
1871 | EVEX_LEN_0F3A21_P_2_W_0, | |
1872 | EVEX_LEN_0F3A22_P_2, | |
6e1c90b7 L |
1873 | EVEX_LEN_0F3A23_P_2_W_0, |
1874 | EVEX_LEN_0F3A23_P_2_W_1, | |
1875 | EVEX_LEN_0F3A38_P_2_W_0, | |
1876 | EVEX_LEN_0F3A38_P_2_W_1, | |
1877 | EVEX_LEN_0F3A39_P_2_W_0, | |
1878 | EVEX_LEN_0F3A39_P_2_W_1, | |
1879 | EVEX_LEN_0F3A3A_P_2_W_0, | |
1880 | EVEX_LEN_0F3A3A_P_2_W_1, | |
1881 | EVEX_LEN_0F3A3B_P_2_W_0, | |
1882 | EVEX_LEN_0F3A3B_P_2_W_1, | |
1883 | EVEX_LEN_0F3A43_P_2_W_0, | |
1884 | EVEX_LEN_0F3A43_P_2_W_1 | |
04e2a182 L |
1885 | }; |
1886 | ||
9e30b8e0 L |
1887 | enum |
1888 | { | |
ec6f095a | 1889 | VEX_W_0F41_P_0_LEN_1 = 0, |
1ba585e8 | 1890 | VEX_W_0F41_P_2_LEN_1, |
43234a1e | 1891 | VEX_W_0F42_P_0_LEN_1, |
1ba585e8 | 1892 | VEX_W_0F42_P_2_LEN_1, |
43234a1e | 1893 | VEX_W_0F44_P_0_LEN_0, |
1ba585e8 | 1894 | VEX_W_0F44_P_2_LEN_0, |
43234a1e | 1895 | VEX_W_0F45_P_0_LEN_1, |
1ba585e8 | 1896 | VEX_W_0F45_P_2_LEN_1, |
43234a1e | 1897 | VEX_W_0F46_P_0_LEN_1, |
1ba585e8 | 1898 | VEX_W_0F46_P_2_LEN_1, |
43234a1e | 1899 | VEX_W_0F47_P_0_LEN_1, |
1ba585e8 IT |
1900 | VEX_W_0F47_P_2_LEN_1, |
1901 | VEX_W_0F4A_P_0_LEN_1, | |
1902 | VEX_W_0F4A_P_2_LEN_1, | |
1903 | VEX_W_0F4B_P_0_LEN_1, | |
43234a1e | 1904 | VEX_W_0F4B_P_2_LEN_1, |
43234a1e | 1905 | VEX_W_0F90_P_0_LEN_0, |
1ba585e8 | 1906 | VEX_W_0F90_P_2_LEN_0, |
43234a1e | 1907 | VEX_W_0F91_P_0_LEN_0, |
1ba585e8 | 1908 | VEX_W_0F91_P_2_LEN_0, |
43234a1e | 1909 | VEX_W_0F92_P_0_LEN_0, |
90a915bf | 1910 | VEX_W_0F92_P_2_LEN_0, |
43234a1e | 1911 | VEX_W_0F93_P_0_LEN_0, |
90a915bf | 1912 | VEX_W_0F93_P_2_LEN_0, |
43234a1e | 1913 | VEX_W_0F98_P_0_LEN_0, |
1ba585e8 IT |
1914 | VEX_W_0F98_P_2_LEN_0, |
1915 | VEX_W_0F99_P_0_LEN_0, | |
1916 | VEX_W_0F99_P_2_LEN_0, | |
592a252b L |
1917 | VEX_W_0F380C_P_2, |
1918 | VEX_W_0F380D_P_2, | |
1919 | VEX_W_0F380E_P_2, | |
1920 | VEX_W_0F380F_P_2, | |
6431c801 | 1921 | VEX_W_0F3813_P_2, |
6c30d220 | 1922 | VEX_W_0F3816_P_2, |
6c30d220 L |
1923 | VEX_W_0F3818_P_2, |
1924 | VEX_W_0F3819_P_2, | |
592a252b | 1925 | VEX_W_0F381A_P_2_M_0, |
592a252b L |
1926 | VEX_W_0F382C_P_2_M_0, |
1927 | VEX_W_0F382D_P_2_M_0, | |
1928 | VEX_W_0F382E_P_2_M_0, | |
1929 | VEX_W_0F382F_P_2_M_0, | |
6c30d220 | 1930 | VEX_W_0F3836_P_2, |
6c30d220 L |
1931 | VEX_W_0F3846_P_2, |
1932 | VEX_W_0F3858_P_2, | |
1933 | VEX_W_0F3859_P_2, | |
1934 | VEX_W_0F385A_P_2_M_0, | |
1935 | VEX_W_0F3878_P_2, | |
1936 | VEX_W_0F3879_P_2, | |
48521003 | 1937 | VEX_W_0F38CF_P_2, |
6c30d220 L |
1938 | VEX_W_0F3A00_P_2, |
1939 | VEX_W_0F3A01_P_2, | |
1940 | VEX_W_0F3A02_P_2, | |
592a252b L |
1941 | VEX_W_0F3A04_P_2, |
1942 | VEX_W_0F3A05_P_2, | |
1943 | VEX_W_0F3A06_P_2, | |
592a252b L |
1944 | VEX_W_0F3A18_P_2, |
1945 | VEX_W_0F3A19_P_2, | |
6431c801 | 1946 | VEX_W_0F3A1D_P_2, |
43234a1e | 1947 | VEX_W_0F3A30_P_2_LEN_0, |
1ba585e8 | 1948 | VEX_W_0F3A31_P_2_LEN_0, |
43234a1e | 1949 | VEX_W_0F3A32_P_2_LEN_0, |
1ba585e8 | 1950 | VEX_W_0F3A33_P_2_LEN_0, |
6c30d220 L |
1951 | VEX_W_0F3A38_P_2, |
1952 | VEX_W_0F3A39_P_2, | |
6c30d220 | 1953 | VEX_W_0F3A46_P_2, |
592a252b L |
1954 | VEX_W_0F3A48_P_2, |
1955 | VEX_W_0F3A49_P_2, | |
1956 | VEX_W_0F3A4A_P_2, | |
1957 | VEX_W_0F3A4B_P_2, | |
1958 | VEX_W_0F3A4C_P_2, | |
48521003 IT |
1959 | VEX_W_0F3ACE_P_2, |
1960 | VEX_W_0F3ACF_P_2, | |
43234a1e | 1961 | |
36cc073e | 1962 | EVEX_W_0F10_P_1, |
36cc073e | 1963 | EVEX_W_0F10_P_3, |
36cc073e | 1964 | EVEX_W_0F11_P_1, |
36cc073e | 1965 | EVEX_W_0F11_P_3, |
43234a1e L |
1966 | EVEX_W_0F12_P_0_M_1, |
1967 | EVEX_W_0F12_P_1, | |
43234a1e | 1968 | EVEX_W_0F12_P_3, |
43234a1e L |
1969 | EVEX_W_0F16_P_0_M_1, |
1970 | EVEX_W_0F16_P_1, | |
43234a1e | 1971 | EVEX_W_0F2A_P_3, |
43234a1e | 1972 | EVEX_W_0F51_P_1, |
43234a1e | 1973 | EVEX_W_0F51_P_3, |
43234a1e | 1974 | EVEX_W_0F58_P_1, |
43234a1e | 1975 | EVEX_W_0F58_P_3, |
43234a1e | 1976 | EVEX_W_0F59_P_1, |
43234a1e L |
1977 | EVEX_W_0F59_P_3, |
1978 | EVEX_W_0F5A_P_0, | |
1979 | EVEX_W_0F5A_P_1, | |
1980 | EVEX_W_0F5A_P_2, | |
1981 | EVEX_W_0F5A_P_3, | |
1982 | EVEX_W_0F5B_P_0, | |
1983 | EVEX_W_0F5B_P_1, | |
1984 | EVEX_W_0F5B_P_2, | |
43234a1e | 1985 | EVEX_W_0F5C_P_1, |
43234a1e | 1986 | EVEX_W_0F5C_P_3, |
43234a1e | 1987 | EVEX_W_0F5D_P_1, |
43234a1e | 1988 | EVEX_W_0F5D_P_3, |
43234a1e | 1989 | EVEX_W_0F5E_P_1, |
43234a1e | 1990 | EVEX_W_0F5E_P_3, |
43234a1e | 1991 | EVEX_W_0F5F_P_1, |
43234a1e L |
1992 | EVEX_W_0F5F_P_3, |
1993 | EVEX_W_0F62_P_2, | |
1994 | EVEX_W_0F66_P_2, | |
1995 | EVEX_W_0F6A_P_2, | |
1ba585e8 | 1996 | EVEX_W_0F6B_P_2, |
43234a1e L |
1997 | EVEX_W_0F6C_P_2, |
1998 | EVEX_W_0F6D_P_2, | |
43234a1e L |
1999 | EVEX_W_0F6F_P_1, |
2000 | EVEX_W_0F6F_P_2, | |
1ba585e8 | 2001 | EVEX_W_0F6F_P_3, |
43234a1e L |
2002 | EVEX_W_0F70_P_2, |
2003 | EVEX_W_0F72_R_2_P_2, | |
2004 | EVEX_W_0F72_R_6_P_2, | |
2005 | EVEX_W_0F73_R_2_P_2, | |
2006 | EVEX_W_0F73_R_6_P_2, | |
2007 | EVEX_W_0F76_P_2, | |
2008 | EVEX_W_0F78_P_0, | |
90a915bf | 2009 | EVEX_W_0F78_P_2, |
43234a1e | 2010 | EVEX_W_0F79_P_0, |
90a915bf | 2011 | EVEX_W_0F79_P_2, |
43234a1e | 2012 | EVEX_W_0F7A_P_1, |
90a915bf | 2013 | EVEX_W_0F7A_P_2, |
43234a1e | 2014 | EVEX_W_0F7A_P_3, |
90a915bf | 2015 | EVEX_W_0F7B_P_2, |
43234a1e L |
2016 | EVEX_W_0F7B_P_3, |
2017 | EVEX_W_0F7E_P_1, | |
43234a1e L |
2018 | EVEX_W_0F7F_P_1, |
2019 | EVEX_W_0F7F_P_2, | |
1ba585e8 | 2020 | EVEX_W_0F7F_P_3, |
43234a1e | 2021 | EVEX_W_0FC2_P_1, |
43234a1e | 2022 | EVEX_W_0FC2_P_3, |
43234a1e L |
2023 | EVEX_W_0FD2_P_2, |
2024 | EVEX_W_0FD3_P_2, | |
2025 | EVEX_W_0FD4_P_2, | |
2026 | EVEX_W_0FD6_P_2, | |
2027 | EVEX_W_0FE6_P_1, | |
2028 | EVEX_W_0FE6_P_2, | |
2029 | EVEX_W_0FE6_P_3, | |
2030 | EVEX_W_0FE7_P_2, | |
2031 | EVEX_W_0FF2_P_2, | |
2032 | EVEX_W_0FF3_P_2, | |
2033 | EVEX_W_0FF4_P_2, | |
2034 | EVEX_W_0FFA_P_2, | |
2035 | EVEX_W_0FFB_P_2, | |
2036 | EVEX_W_0FFE_P_2, | |
43234a1e | 2037 | EVEX_W_0F380D_P_2, |
1ba585e8 IT |
2038 | EVEX_W_0F3810_P_1, |
2039 | EVEX_W_0F3810_P_2, | |
43234a1e | 2040 | EVEX_W_0F3811_P_1, |
1ba585e8 | 2041 | EVEX_W_0F3811_P_2, |
43234a1e | 2042 | EVEX_W_0F3812_P_1, |
1ba585e8 | 2043 | EVEX_W_0F3812_P_2, |
43234a1e L |
2044 | EVEX_W_0F3813_P_1, |
2045 | EVEX_W_0F3813_P_2, | |
2046 | EVEX_W_0F3814_P_1, | |
2047 | EVEX_W_0F3815_P_1, | |
43234a1e L |
2048 | EVEX_W_0F3819_P_2, |
2049 | EVEX_W_0F381A_P_2, | |
2050 | EVEX_W_0F381B_P_2, | |
2051 | EVEX_W_0F381E_P_2, | |
2052 | EVEX_W_0F381F_P_2, | |
1ba585e8 | 2053 | EVEX_W_0F3820_P_1, |
43234a1e L |
2054 | EVEX_W_0F3821_P_1, |
2055 | EVEX_W_0F3822_P_1, | |
2056 | EVEX_W_0F3823_P_1, | |
2057 | EVEX_W_0F3824_P_1, | |
2058 | EVEX_W_0F3825_P_1, | |
2059 | EVEX_W_0F3825_P_2, | |
1ba585e8 IT |
2060 | EVEX_W_0F3826_P_1, |
2061 | EVEX_W_0F3826_P_2, | |
2062 | EVEX_W_0F3828_P_1, | |
43234a1e | 2063 | EVEX_W_0F3828_P_2, |
1ba585e8 | 2064 | EVEX_W_0F3829_P_1, |
43234a1e L |
2065 | EVEX_W_0F3829_P_2, |
2066 | EVEX_W_0F382A_P_1, | |
2067 | EVEX_W_0F382A_P_2, | |
1ba585e8 IT |
2068 | EVEX_W_0F382B_P_2, |
2069 | EVEX_W_0F3830_P_1, | |
43234a1e L |
2070 | EVEX_W_0F3831_P_1, |
2071 | EVEX_W_0F3832_P_1, | |
2072 | EVEX_W_0F3833_P_1, | |
2073 | EVEX_W_0F3834_P_1, | |
2074 | EVEX_W_0F3835_P_1, | |
2075 | EVEX_W_0F3835_P_2, | |
2076 | EVEX_W_0F3837_P_2, | |
90a915bf IT |
2077 | EVEX_W_0F3838_P_1, |
2078 | EVEX_W_0F3839_P_1, | |
43234a1e L |
2079 | EVEX_W_0F383A_P_1, |
2080 | EVEX_W_0F3840_P_2, | |
d6aab7a1 | 2081 | EVEX_W_0F3852_P_1, |
ee6872be | 2082 | EVEX_W_0F3854_P_2, |
620214f7 | 2083 | EVEX_W_0F3855_P_2, |
43234a1e L |
2084 | EVEX_W_0F3859_P_2, |
2085 | EVEX_W_0F385A_P_2, | |
2086 | EVEX_W_0F385B_P_2, | |
53467f57 IT |
2087 | EVEX_W_0F3862_P_2, |
2088 | EVEX_W_0F3863_P_2, | |
1ba585e8 | 2089 | EVEX_W_0F3866_P_2, |
9186c494 | 2090 | EVEX_W_0F3868_P_3, |
53467f57 IT |
2091 | EVEX_W_0F3870_P_2, |
2092 | EVEX_W_0F3871_P_2, | |
d6aab7a1 | 2093 | EVEX_W_0F3872_P_1, |
53467f57 | 2094 | EVEX_W_0F3872_P_2, |
d6aab7a1 | 2095 | EVEX_W_0F3872_P_3, |
53467f57 | 2096 | EVEX_W_0F3873_P_2, |
1ba585e8 | 2097 | EVEX_W_0F3875_P_2, |
1ba585e8 IT |
2098 | EVEX_W_0F387A_P_2, |
2099 | EVEX_W_0F387B_P_2, | |
2100 | EVEX_W_0F387D_P_2, | |
14f195c9 | 2101 | EVEX_W_0F3883_P_2, |
1ba585e8 | 2102 | EVEX_W_0F388D_P_2, |
43234a1e L |
2103 | EVEX_W_0F3891_P_2, |
2104 | EVEX_W_0F3893_P_2, | |
2105 | EVEX_W_0F38A1_P_2, | |
2106 | EVEX_W_0F38A3_P_2, | |
2107 | EVEX_W_0F38C7_R_1_P_2, | |
2108 | EVEX_W_0F38C7_R_2_P_2, | |
2109 | EVEX_W_0F38C7_R_5_P_2, | |
2110 | EVEX_W_0F38C7_R_6_P_2, | |
2111 | ||
2112 | EVEX_W_0F3A00_P_2, | |
2113 | EVEX_W_0F3A01_P_2, | |
43234a1e L |
2114 | EVEX_W_0F3A05_P_2, |
2115 | EVEX_W_0F3A08_P_2, | |
2116 | EVEX_W_0F3A09_P_2, | |
2117 | EVEX_W_0F3A0A_P_2, | |
2118 | EVEX_W_0F3A0B_P_2, | |
2119 | EVEX_W_0F3A18_P_2, | |
2120 | EVEX_W_0F3A19_P_2, | |
2121 | EVEX_W_0F3A1A_P_2, | |
2122 | EVEX_W_0F3A1B_P_2, | |
43234a1e L |
2123 | EVEX_W_0F3A21_P_2, |
2124 | EVEX_W_0F3A23_P_2, | |
2125 | EVEX_W_0F3A38_P_2, | |
2126 | EVEX_W_0F3A39_P_2, | |
2127 | EVEX_W_0F3A3A_P_2, | |
2128 | EVEX_W_0F3A3B_P_2, | |
1ba585e8 IT |
2129 | EVEX_W_0F3A3E_P_2, |
2130 | EVEX_W_0F3A3F_P_2, | |
2131 | EVEX_W_0F3A42_P_2, | |
90a915bf IT |
2132 | EVEX_W_0F3A43_P_2, |
2133 | EVEX_W_0F3A50_P_2, | |
2134 | EVEX_W_0F3A51_P_2, | |
2135 | EVEX_W_0F3A56_P_2, | |
2136 | EVEX_W_0F3A57_P_2, | |
2137 | EVEX_W_0F3A66_P_2, | |
53467f57 IT |
2138 | EVEX_W_0F3A67_P_2, |
2139 | EVEX_W_0F3A70_P_2, | |
2140 | EVEX_W_0F3A71_P_2, | |
2141 | EVEX_W_0F3A72_P_2, | |
48521003 | 2142 | EVEX_W_0F3A73_P_2, |
9e30b8e0 L |
2143 | }; |
2144 | ||
26ca5450 | 2145 | typedef void (*op_rtn) (int bytemode, int sizeflag); |
252b5132 RH |
2146 | |
2147 | struct dis386 { | |
2da11e11 | 2148 | const char *name; |
ce518a5f L |
2149 | struct |
2150 | { | |
2151 | op_rtn rtn; | |
2152 | int bytemode; | |
2153 | } op[MAX_OPERANDS]; | |
bf890a93 | 2154 | unsigned int prefix_requirement; |
252b5132 RH |
2155 | }; |
2156 | ||
2157 | /* Upper case letters in the instruction names here are macros. | |
2158 | 'A' => print 'b' if no register operands or suffix_always is true | |
2159 | 'B' => print 'b' if suffix_always is true | |
9306ca4a | 2160 | 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand |
98b528ac | 2161 | size prefix |
ed7841b3 | 2162 | 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if |
98b528ac | 2163 | suffix_always is true |
252b5132 | 2164 | 'E' => print 'e' if 32-bit form of jcxz |
3ffd33cf | 2165 | 'F' => print 'w' or 'l' depending on address size prefix (loop insns) |
52fd6d94 | 2166 | 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns) |
5dd0794d | 2167 | 'H' => print ",pt" or ",pn" branch hint |
d1c36125 | 2168 | 'I' unused. |
8f570d62 | 2169 | 'J' unused. |
42903f7f | 2170 | 'K' => print 'd' or 'q' if rex prefix is present. |
252b5132 | 2171 | 'L' => print 'l' if suffix_always is true |
9d141669 | 2172 | 'M' => print 'r' if intel_mnemonic is false. |
252b5132 | 2173 | 'N' => print 'n' if instruction has no wait "prefix" |
a35ca55a | 2174 | 'O' => print 'd' or 'o' (or 'q' in Intel mode) |
52b15da3 | 2175 | 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix, |
98b528ac L |
2176 | or suffix_always is true. print 'q' if rex prefix is present. |
2177 | 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always | |
2178 | is true | |
a35ca55a | 2179 | 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode) |
52b15da3 | 2180 | 'S' => print 'w', 'l' or 'q' if suffix_always is true |
a72d2af2 L |
2181 | 'T' => print 'q' in 64bit mode if instruction has no operand size |
2182 | prefix and behave as 'P' otherwise | |
2183 | 'U' => print 'q' in 64bit mode if instruction has no operand size | |
2184 | prefix and behave as 'Q' otherwise | |
2185 | 'V' => print 'q' in 64bit mode if instruction has no operand size | |
2186 | prefix and behave as 'S' otherwise | |
a35ca55a | 2187 | 'W' => print 'b', 'w' or 'l' ('d' in Intel mode) |
9306ca4a | 2188 | 'X' => print 's', 'd' depending on data16 prefix (for XMM) |
9646c87b | 2189 | 'Y' unused. |
6dd5059a | 2190 | 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise |
9d141669 | 2191 | '!' => change condition from true to false or from false to true. |
98b528ac | 2192 | '%' => add 1 upper case letter to the macro. |
5990e377 JB |
2193 | '^' => print 'w', 'l', or 'q' (Intel64 ISA only) depending on operand size |
2194 | prefix or suffix_always is true (lcall/ljmp). | |
5db04b09 L |
2195 | '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending |
2196 | on operand size prefix. | |
07f5af7d L |
2197 | '&' => print 'q' in 64bit mode for Intel64 ISA or if instruction |
2198 | has no operand size prefix for AMD64 ISA, behave as 'P' | |
2199 | otherwise | |
98b528ac L |
2200 | |
2201 | 2 upper case letter macros: | |
04d824a4 JB |
2202 | "XY" => print 'x' or 'y' if suffix_always is true or no register |
2203 | operands and no broadcast. | |
2204 | "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no | |
2205 | register operands and no broadcast. | |
4b06377f | 2206 | "XW" => print 's', 'd' depending on the VEX.W bit (for FMA) |
589958d6 JB |
2207 | "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory |
2208 | operand or no operand at all in 64bit mode, or if suffix_always | |
2209 | is true. | |
4b06377f L |
2210 | "LB" => print "abs" in 64bit mode and behave as 'B' otherwise |
2211 | "LS" => print "abs" in 64bit mode and behave as 'S' otherwise | |
2212 | "LV" => print "abs" for 64bit operand and behave as 'S' otherwise | |
6c30d220 | 2213 | "LW" => print 'd', 'q' depending on the VEX.W bit |
4b4c407a L |
2214 | "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has |
2215 | an operand size prefix, or suffix_always is true. print | |
2216 | 'q' if rex prefix is present. | |
52b15da3 | 2217 | |
6439fc28 AM |
2218 | Many of the above letters print nothing in Intel mode. See "putop" |
2219 | for the details. | |
52b15da3 | 2220 | |
6439fc28 | 2221 | Braces '{' and '}', and vertical bars '|', indicate alternative |
7c52e0e8 | 2222 | mnemonic strings for AT&T and Intel. */ |
252b5132 | 2223 | |
6439fc28 | 2224 | static const struct dis386 dis386[] = { |
252b5132 | 2225 | /* 00 */ |
bf890a93 IT |
2226 | { "addB", { Ebh1, Gb }, 0 }, |
2227 | { "addS", { Evh1, Gv }, 0 }, | |
2228 | { "addB", { Gb, EbS }, 0 }, | |
2229 | { "addS", { Gv, EvS }, 0 }, | |
2230 | { "addB", { AL, Ib }, 0 }, | |
2231 | { "addS", { eAX, Iv }, 0 }, | |
4e7d34a6 L |
2232 | { X86_64_TABLE (X86_64_06) }, |
2233 | { X86_64_TABLE (X86_64_07) }, | |
252b5132 | 2234 | /* 08 */ |
bf890a93 IT |
2235 | { "orB", { Ebh1, Gb }, 0 }, |
2236 | { "orS", { Evh1, Gv }, 0 }, | |
2237 | { "orB", { Gb, EbS }, 0 }, | |
2238 | { "orS", { Gv, EvS }, 0 }, | |
2239 | { "orB", { AL, Ib }, 0 }, | |
2240 | { "orS", { eAX, Iv }, 0 }, | |
1673df32 | 2241 | { X86_64_TABLE (X86_64_0E) }, |
592d1631 | 2242 | { Bad_Opcode }, /* 0x0f extended opcode escape */ |
252b5132 | 2243 | /* 10 */ |
bf890a93 IT |
2244 | { "adcB", { Ebh1, Gb }, 0 }, |
2245 | { "adcS", { Evh1, Gv }, 0 }, | |
2246 | { "adcB", { Gb, EbS }, 0 }, | |
2247 | { "adcS", { Gv, EvS }, 0 }, | |
2248 | { "adcB", { AL, Ib }, 0 }, | |
2249 | { "adcS", { eAX, Iv }, 0 }, | |
4e7d34a6 L |
2250 | { X86_64_TABLE (X86_64_16) }, |
2251 | { X86_64_TABLE (X86_64_17) }, | |
252b5132 | 2252 | /* 18 */ |
bf890a93 IT |
2253 | { "sbbB", { Ebh1, Gb }, 0 }, |
2254 | { "sbbS", { Evh1, Gv }, 0 }, | |
2255 | { "sbbB", { Gb, EbS }, 0 }, | |
2256 | { "sbbS", { Gv, EvS }, 0 }, | |
2257 | { "sbbB", { AL, Ib }, 0 }, | |
2258 | { "sbbS", { eAX, Iv }, 0 }, | |
4e7d34a6 L |
2259 | { X86_64_TABLE (X86_64_1E) }, |
2260 | { X86_64_TABLE (X86_64_1F) }, | |
252b5132 | 2261 | /* 20 */ |
bf890a93 IT |
2262 | { "andB", { Ebh1, Gb }, 0 }, |
2263 | { "andS", { Evh1, Gv }, 0 }, | |
2264 | { "andB", { Gb, EbS }, 0 }, | |
2265 | { "andS", { Gv, EvS }, 0 }, | |
2266 | { "andB", { AL, Ib }, 0 }, | |
2267 | { "andS", { eAX, Iv }, 0 }, | |
592d1631 | 2268 | { Bad_Opcode }, /* SEG ES prefix */ |
4e7d34a6 | 2269 | { X86_64_TABLE (X86_64_27) }, |
252b5132 | 2270 | /* 28 */ |
bf890a93 IT |
2271 | { "subB", { Ebh1, Gb }, 0 }, |
2272 | { "subS", { Evh1, Gv }, 0 }, | |
2273 | { "subB", { Gb, EbS }, 0 }, | |
2274 | { "subS", { Gv, EvS }, 0 }, | |
2275 | { "subB", { AL, Ib }, 0 }, | |
2276 | { "subS", { eAX, Iv }, 0 }, | |
592d1631 | 2277 | { Bad_Opcode }, /* SEG CS prefix */ |
4e7d34a6 | 2278 | { X86_64_TABLE (X86_64_2F) }, |
252b5132 | 2279 | /* 30 */ |
bf890a93 IT |
2280 | { "xorB", { Ebh1, Gb }, 0 }, |
2281 | { "xorS", { Evh1, Gv }, 0 }, | |
2282 | { "xorB", { Gb, EbS }, 0 }, | |
2283 | { "xorS", { Gv, EvS }, 0 }, | |
2284 | { "xorB", { AL, Ib }, 0 }, | |
2285 | { "xorS", { eAX, Iv }, 0 }, | |
592d1631 | 2286 | { Bad_Opcode }, /* SEG SS prefix */ |
4e7d34a6 | 2287 | { X86_64_TABLE (X86_64_37) }, |
252b5132 | 2288 | /* 38 */ |
bf890a93 IT |
2289 | { "cmpB", { Eb, Gb }, 0 }, |
2290 | { "cmpS", { Ev, Gv }, 0 }, | |
2291 | { "cmpB", { Gb, EbS }, 0 }, | |
2292 | { "cmpS", { Gv, EvS }, 0 }, | |
2293 | { "cmpB", { AL, Ib }, 0 }, | |
2294 | { "cmpS", { eAX, Iv }, 0 }, | |
592d1631 | 2295 | { Bad_Opcode }, /* SEG DS prefix */ |
4e7d34a6 | 2296 | { X86_64_TABLE (X86_64_3F) }, |
252b5132 | 2297 | /* 40 */ |
bf890a93 IT |
2298 | { "inc{S|}", { RMeAX }, 0 }, |
2299 | { "inc{S|}", { RMeCX }, 0 }, | |
2300 | { "inc{S|}", { RMeDX }, 0 }, | |
2301 | { "inc{S|}", { RMeBX }, 0 }, | |
2302 | { "inc{S|}", { RMeSP }, 0 }, | |
2303 | { "inc{S|}", { RMeBP }, 0 }, | |
2304 | { "inc{S|}", { RMeSI }, 0 }, | |
2305 | { "inc{S|}", { RMeDI }, 0 }, | |
252b5132 | 2306 | /* 48 */ |
bf890a93 IT |
2307 | { "dec{S|}", { RMeAX }, 0 }, |
2308 | { "dec{S|}", { RMeCX }, 0 }, | |
2309 | { "dec{S|}", { RMeDX }, 0 }, | |
2310 | { "dec{S|}", { RMeBX }, 0 }, | |
2311 | { "dec{S|}", { RMeSP }, 0 }, | |
2312 | { "dec{S|}", { RMeBP }, 0 }, | |
2313 | { "dec{S|}", { RMeSI }, 0 }, | |
2314 | { "dec{S|}", { RMeDI }, 0 }, | |
252b5132 | 2315 | /* 50 */ |
bf890a93 IT |
2316 | { "pushV", { RMrAX }, 0 }, |
2317 | { "pushV", { RMrCX }, 0 }, | |
2318 | { "pushV", { RMrDX }, 0 }, | |
2319 | { "pushV", { RMrBX }, 0 }, | |
2320 | { "pushV", { RMrSP }, 0 }, | |
2321 | { "pushV", { RMrBP }, 0 }, | |
2322 | { "pushV", { RMrSI }, 0 }, | |
2323 | { "pushV", { RMrDI }, 0 }, | |
252b5132 | 2324 | /* 58 */ |
bf890a93 IT |
2325 | { "popV", { RMrAX }, 0 }, |
2326 | { "popV", { RMrCX }, 0 }, | |
2327 | { "popV", { RMrDX }, 0 }, | |
2328 | { "popV", { RMrBX }, 0 }, | |
2329 | { "popV", { RMrSP }, 0 }, | |
2330 | { "popV", { RMrBP }, 0 }, | |
2331 | { "popV", { RMrSI }, 0 }, | |
2332 | { "popV", { RMrDI }, 0 }, | |
252b5132 | 2333 | /* 60 */ |
4e7d34a6 L |
2334 | { X86_64_TABLE (X86_64_60) }, |
2335 | { X86_64_TABLE (X86_64_61) }, | |
2336 | { X86_64_TABLE (X86_64_62) }, | |
2337 | { X86_64_TABLE (X86_64_63) }, | |
592d1631 L |
2338 | { Bad_Opcode }, /* seg fs */ |
2339 | { Bad_Opcode }, /* seg gs */ | |
2340 | { Bad_Opcode }, /* op size prefix */ | |
2341 | { Bad_Opcode }, /* adr size prefix */ | |
252b5132 | 2342 | /* 68 */ |
bf890a93 IT |
2343 | { "pushT", { sIv }, 0 }, |
2344 | { "imulS", { Gv, Ev, Iv }, 0 }, | |
2345 | { "pushT", { sIbT }, 0 }, | |
2346 | { "imulS", { Gv, Ev, sIb }, 0 }, | |
2347 | { "ins{b|}", { Ybr, indirDX }, 0 }, | |
4e7d34a6 | 2348 | { X86_64_TABLE (X86_64_6D) }, |
bf890a93 | 2349 | { "outs{b|}", { indirDXr, Xb }, 0 }, |
4e7d34a6 | 2350 | { X86_64_TABLE (X86_64_6F) }, |
252b5132 | 2351 | /* 70 */ |
bf890a93 IT |
2352 | { "joH", { Jb, BND, cond_jump_flag }, 0 }, |
2353 | { "jnoH", { Jb, BND, cond_jump_flag }, 0 }, | |
2354 | { "jbH", { Jb, BND, cond_jump_flag }, 0 }, | |
2355 | { "jaeH", { Jb, BND, cond_jump_flag }, 0 }, | |
2356 | { "jeH", { Jb, BND, cond_jump_flag }, 0 }, | |
2357 | { "jneH", { Jb, BND, cond_jump_flag }, 0 }, | |
2358 | { "jbeH", { Jb, BND, cond_jump_flag }, 0 }, | |
2359 | { "jaH", { Jb, BND, cond_jump_flag }, 0 }, | |
252b5132 | 2360 | /* 78 */ |
bf890a93 IT |
2361 | { "jsH", { Jb, BND, cond_jump_flag }, 0 }, |
2362 | { "jnsH", { Jb, BND, cond_jump_flag }, 0 }, | |
2363 | { "jpH", { Jb, BND, cond_jump_flag }, 0 }, | |
2364 | { "jnpH", { Jb, BND, cond_jump_flag }, 0 }, | |
2365 | { "jlH", { Jb, BND, cond_jump_flag }, 0 }, | |
2366 | { "jgeH", { Jb, BND, cond_jump_flag }, 0 }, | |
2367 | { "jleH", { Jb, BND, cond_jump_flag }, 0 }, | |
2368 | { "jgH", { Jb, BND, cond_jump_flag }, 0 }, | |
252b5132 | 2369 | /* 80 */ |
1ceb70f8 L |
2370 | { REG_TABLE (REG_80) }, |
2371 | { REG_TABLE (REG_81) }, | |
d039fef3 | 2372 | { X86_64_TABLE (X86_64_82) }, |
7148c369 | 2373 | { REG_TABLE (REG_83) }, |
bf890a93 IT |
2374 | { "testB", { Eb, Gb }, 0 }, |
2375 | { "testS", { Ev, Gv }, 0 }, | |
2376 | { "xchgB", { Ebh2, Gb }, 0 }, | |
2377 | { "xchgS", { Evh2, Gv }, 0 }, | |
252b5132 | 2378 | /* 88 */ |
bf890a93 IT |
2379 | { "movB", { Ebh3, Gb }, 0 }, |
2380 | { "movS", { Evh3, Gv }, 0 }, | |
2381 | { "movB", { Gb, EbS }, 0 }, | |
2382 | { "movS", { Gv, EvS }, 0 }, | |
2383 | { "movD", { Sv, Sw }, 0 }, | |
1ceb70f8 | 2384 | { MOD_TABLE (MOD_8D) }, |
bf890a93 | 2385 | { "movD", { Sw, Sv }, 0 }, |
1ceb70f8 | 2386 | { REG_TABLE (REG_8F) }, |
252b5132 | 2387 | /* 90 */ |
1ceb70f8 | 2388 | { PREFIX_TABLE (PREFIX_90) }, |
bf890a93 IT |
2389 | { "xchgS", { RMeCX, eAX }, 0 }, |
2390 | { "xchgS", { RMeDX, eAX }, 0 }, | |
2391 | { "xchgS", { RMeBX, eAX }, 0 }, | |
2392 | { "xchgS", { RMeSP, eAX }, 0 }, | |
2393 | { "xchgS", { RMeBP, eAX }, 0 }, | |
2394 | { "xchgS", { RMeSI, eAX }, 0 }, | |
2395 | { "xchgS", { RMeDI, eAX }, 0 }, | |
252b5132 | 2396 | /* 98 */ |
bf890a93 IT |
2397 | { "cW{t|}R", { XX }, 0 }, |
2398 | { "cR{t|}O", { XX }, 0 }, | |
4e7d34a6 | 2399 | { X86_64_TABLE (X86_64_9A) }, |
592d1631 | 2400 | { Bad_Opcode }, /* fwait */ |
bf890a93 IT |
2401 | { "pushfT", { XX }, 0 }, |
2402 | { "popfT", { XX }, 0 }, | |
2403 | { "sahf", { XX }, 0 }, | |
2404 | { "lahf", { XX }, 0 }, | |
252b5132 | 2405 | /* a0 */ |
bf890a93 IT |
2406 | { "mov%LB", { AL, Ob }, 0 }, |
2407 | { "mov%LS", { eAX, Ov }, 0 }, | |
2408 | { "mov%LB", { Ob, AL }, 0 }, | |
2409 | { "mov%LS", { Ov, eAX }, 0 }, | |
2410 | { "movs{b|}", { Ybr, Xb }, 0 }, | |
2411 | { "movs{R|}", { Yvr, Xv }, 0 }, | |
2412 | { "cmps{b|}", { Xb, Yb }, 0 }, | |
2413 | { "cmps{R|}", { Xv, Yv }, 0 }, | |
252b5132 | 2414 | /* a8 */ |
bf890a93 IT |
2415 | { "testB", { AL, Ib }, 0 }, |
2416 | { "testS", { eAX, Iv }, 0 }, | |
2417 | { "stosB", { Ybr, AL }, 0 }, | |
2418 | { "stosS", { Yvr, eAX }, 0 }, | |
2419 | { "lodsB", { ALr, Xb }, 0 }, | |
2420 | { "lodsS", { eAXr, Xv }, 0 }, | |
2421 | { "scasB", { AL, Yb }, 0 }, | |
2422 | { "scasS", { eAX, Yv }, 0 }, | |
252b5132 | 2423 | /* b0 */ |
bf890a93 IT |
2424 | { "movB", { RMAL, Ib }, 0 }, |
2425 | { "movB", { RMCL, Ib }, 0 }, | |
2426 | { "movB", { RMDL, Ib }, 0 }, | |
2427 | { "movB", { RMBL, Ib }, 0 }, | |
2428 | { "movB", { RMAH, Ib }, 0 }, | |
2429 | { "movB", { RMCH, Ib }, 0 }, | |
2430 | { "movB", { RMDH, Ib }, 0 }, | |
2431 | { "movB", { RMBH, Ib }, 0 }, | |
252b5132 | 2432 | /* b8 */ |
bf890a93 IT |
2433 | { "mov%LV", { RMeAX, Iv64 }, 0 }, |
2434 | { "mov%LV", { RMeCX, Iv64 }, 0 }, | |
2435 | { "mov%LV", { RMeDX, Iv64 }, 0 }, | |
2436 | { "mov%LV", { RMeBX, Iv64 }, 0 }, | |
2437 | { "mov%LV", { RMeSP, Iv64 }, 0 }, | |
2438 | { "mov%LV", { RMeBP, Iv64 }, 0 }, | |
2439 | { "mov%LV", { RMeSI, Iv64 }, 0 }, | |
2440 | { "mov%LV", { RMeDI, Iv64 }, 0 }, | |
252b5132 | 2441 | /* c0 */ |
1ceb70f8 L |
2442 | { REG_TABLE (REG_C0) }, |
2443 | { REG_TABLE (REG_C1) }, | |
aeab2b26 JB |
2444 | { X86_64_TABLE (X86_64_C2) }, |
2445 | { X86_64_TABLE (X86_64_C3) }, | |
4e7d34a6 L |
2446 | { X86_64_TABLE (X86_64_C4) }, |
2447 | { X86_64_TABLE (X86_64_C5) }, | |
1ceb70f8 L |
2448 | { REG_TABLE (REG_C6) }, |
2449 | { REG_TABLE (REG_C7) }, | |
252b5132 | 2450 | /* c8 */ |
bf890a93 IT |
2451 | { "enterT", { Iw, Ib }, 0 }, |
2452 | { "leaveT", { XX }, 0 }, | |
8f570d62 JB |
2453 | { "{l|}ret{|f}P", { Iw }, 0 }, |
2454 | { "{l|}ret{|f}P", { XX }, 0 }, | |
bf890a93 IT |
2455 | { "int3", { XX }, 0 }, |
2456 | { "int", { Ib }, 0 }, | |
4e7d34a6 | 2457 | { X86_64_TABLE (X86_64_CE) }, |
bf890a93 | 2458 | { "iret%LP", { XX }, 0 }, |
252b5132 | 2459 | /* d0 */ |
1ceb70f8 L |
2460 | { REG_TABLE (REG_D0) }, |
2461 | { REG_TABLE (REG_D1) }, | |
2462 | { REG_TABLE (REG_D2) }, | |
2463 | { REG_TABLE (REG_D3) }, | |
4e7d34a6 L |
2464 | { X86_64_TABLE (X86_64_D4) }, |
2465 | { X86_64_TABLE (X86_64_D5) }, | |
592d1631 | 2466 | { Bad_Opcode }, |
bf890a93 | 2467 | { "xlat", { DSBX }, 0 }, |
252b5132 RH |
2468 | /* d8 */ |
2469 | { FLOAT }, | |
2470 | { FLOAT }, | |
2471 | { FLOAT }, | |
2472 | { FLOAT }, | |
2473 | { FLOAT }, | |
2474 | { FLOAT }, | |
2475 | { FLOAT }, | |
2476 | { FLOAT }, | |
2477 | /* e0 */ | |
bf890a93 IT |
2478 | { "loopneFH", { Jb, XX, loop_jcxz_flag }, 0 }, |
2479 | { "loopeFH", { Jb, XX, loop_jcxz_flag }, 0 }, | |
2480 | { "loopFH", { Jb, XX, loop_jcxz_flag }, 0 }, | |
2481 | { "jEcxzH", { Jb, XX, loop_jcxz_flag }, 0 }, | |
2482 | { "inB", { AL, Ib }, 0 }, | |
2483 | { "inG", { zAX, Ib }, 0 }, | |
2484 | { "outB", { Ib, AL }, 0 }, | |
2485 | { "outG", { Ib, zAX }, 0 }, | |
252b5132 | 2486 | /* e8 */ |
a72d2af2 L |
2487 | { X86_64_TABLE (X86_64_E8) }, |
2488 | { X86_64_TABLE (X86_64_E9) }, | |
4e7d34a6 | 2489 | { X86_64_TABLE (X86_64_EA) }, |
bf890a93 IT |
2490 | { "jmp", { Jb, BND }, 0 }, |
2491 | { "inB", { AL, indirDX }, 0 }, | |
2492 | { "inG", { zAX, indirDX }, 0 }, | |
2493 | { "outB", { indirDX, AL }, 0 }, | |
2494 | { "outG", { indirDX, zAX }, 0 }, | |
252b5132 | 2495 | /* f0 */ |
592d1631 | 2496 | { Bad_Opcode }, /* lock prefix */ |
bf890a93 | 2497 | { "icebp", { XX }, 0 }, |
592d1631 L |
2498 | { Bad_Opcode }, /* repne */ |
2499 | { Bad_Opcode }, /* repz */ | |
bf890a93 IT |
2500 | { "hlt", { XX }, 0 }, |
2501 | { "cmc", { XX }, 0 }, | |
1ceb70f8 L |
2502 | { REG_TABLE (REG_F6) }, |
2503 | { REG_TABLE (REG_F7) }, | |
252b5132 | 2504 | /* f8 */ |
bf890a93 IT |
2505 | { "clc", { XX }, 0 }, |
2506 | { "stc", { XX }, 0 }, | |
2507 | { "cli", { XX }, 0 }, | |
2508 | { "sti", { XX }, 0 }, | |
2509 | { "cld", { XX }, 0 }, | |
2510 | { "std", { XX }, 0 }, | |
1ceb70f8 L |
2511 | { REG_TABLE (REG_FE) }, |
2512 | { REG_TABLE (REG_FF) }, | |
252b5132 RH |
2513 | }; |
2514 | ||
6439fc28 | 2515 | static const struct dis386 dis386_twobyte[] = { |
252b5132 | 2516 | /* 00 */ |
1ceb70f8 L |
2517 | { REG_TABLE (REG_0F00 ) }, |
2518 | { REG_TABLE (REG_0F01 ) }, | |
bf890a93 IT |
2519 | { "larS", { Gv, Ew }, 0 }, |
2520 | { "lslS", { Gv, Ew }, 0 }, | |
592d1631 | 2521 | { Bad_Opcode }, |
bf890a93 IT |
2522 | { "syscall", { XX }, 0 }, |
2523 | { "clts", { XX }, 0 }, | |
589958d6 | 2524 | { "sysret%LQ", { XX }, 0 }, |
252b5132 | 2525 | /* 08 */ |
bf890a93 | 2526 | { "invd", { XX }, 0 }, |
3233d7d0 | 2527 | { PREFIX_TABLE (PREFIX_0F09) }, |
592d1631 | 2528 | { Bad_Opcode }, |
bf890a93 | 2529 | { "ud2", { XX }, 0 }, |
592d1631 | 2530 | { Bad_Opcode }, |
b5b1fc4f | 2531 | { REG_TABLE (REG_0F0D) }, |
bf890a93 IT |
2532 | { "femms", { XX }, 0 }, |
2533 | { "", { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix. */ | |
252b5132 | 2534 | /* 10 */ |
1ceb70f8 L |
2535 | { PREFIX_TABLE (PREFIX_0F10) }, |
2536 | { PREFIX_TABLE (PREFIX_0F11) }, | |
2537 | { PREFIX_TABLE (PREFIX_0F12) }, | |
2538 | { MOD_TABLE (MOD_0F13) }, | |
507bd325 L |
2539 | { "unpcklpX", { XM, EXx }, PREFIX_OPCODE }, |
2540 | { "unpckhpX", { XM, EXx }, PREFIX_OPCODE }, | |
1ceb70f8 L |
2541 | { PREFIX_TABLE (PREFIX_0F16) }, |
2542 | { MOD_TABLE (MOD_0F17) }, | |
252b5132 | 2543 | /* 18 */ |
1ceb70f8 | 2544 | { REG_TABLE (REG_0F18) }, |
bf890a93 | 2545 | { "nopQ", { Ev }, 0 }, |
7e8b059b L |
2546 | { PREFIX_TABLE (PREFIX_0F1A) }, |
2547 | { PREFIX_TABLE (PREFIX_0F1B) }, | |
c48935d7 | 2548 | { PREFIX_TABLE (PREFIX_0F1C) }, |
bf890a93 | 2549 | { "nopQ", { Ev }, 0 }, |
603555e5 | 2550 | { PREFIX_TABLE (PREFIX_0F1E) }, |
bf890a93 | 2551 | { "nopQ", { Ev }, 0 }, |
252b5132 | 2552 | /* 20 */ |
bf890a93 IT |
2553 | { "movZ", { Rm, Cm }, 0 }, |
2554 | { "movZ", { Rm, Dm }, 0 }, | |
2555 | { "movZ", { Cm, Rm }, 0 }, | |
2556 | { "movZ", { Dm, Rm }, 0 }, | |
1ceb70f8 | 2557 | { MOD_TABLE (MOD_0F24) }, |
592d1631 | 2558 | { Bad_Opcode }, |
1ceb70f8 | 2559 | { MOD_TABLE (MOD_0F26) }, |
592d1631 | 2560 | { Bad_Opcode }, |
252b5132 | 2561 | /* 28 */ |
507bd325 L |
2562 | { "movapX", { XM, EXx }, PREFIX_OPCODE }, |
2563 | { "movapX", { EXxS, XM }, PREFIX_OPCODE }, | |
1ceb70f8 L |
2564 | { PREFIX_TABLE (PREFIX_0F2A) }, |
2565 | { PREFIX_TABLE (PREFIX_0F2B) }, | |
2566 | { PREFIX_TABLE (PREFIX_0F2C) }, | |
2567 | { PREFIX_TABLE (PREFIX_0F2D) }, | |
2568 | { PREFIX_TABLE (PREFIX_0F2E) }, | |
2569 | { PREFIX_TABLE (PREFIX_0F2F) }, | |
252b5132 | 2570 | /* 30 */ |
bf890a93 IT |
2571 | { "wrmsr", { XX }, 0 }, |
2572 | { "rdtsc", { XX }, 0 }, | |
2573 | { "rdmsr", { XX }, 0 }, | |
2574 | { "rdpmc", { XX }, 0 }, | |
d835a58b JB |
2575 | { "sysenter", { SEP }, 0 }, |
2576 | { "sysexit", { SEP }, 0 }, | |
592d1631 | 2577 | { Bad_Opcode }, |
bf890a93 | 2578 | { "getsec", { XX }, 0 }, |
252b5132 | 2579 | /* 38 */ |
507bd325 | 2580 | { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) }, |
592d1631 | 2581 | { Bad_Opcode }, |
507bd325 | 2582 | { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) }, |
592d1631 L |
2583 | { Bad_Opcode }, |
2584 | { Bad_Opcode }, | |
2585 | { Bad_Opcode }, | |
2586 | { Bad_Opcode }, | |
2587 | { Bad_Opcode }, | |
252b5132 | 2588 | /* 40 */ |
bf890a93 IT |
2589 | { "cmovoS", { Gv, Ev }, 0 }, |
2590 | { "cmovnoS", { Gv, Ev }, 0 }, | |
2591 | { "cmovbS", { Gv, Ev }, 0 }, | |
2592 | { "cmovaeS", { Gv, Ev }, 0 }, | |
2593 | { "cmoveS", { Gv, Ev }, 0 }, | |
2594 | { "cmovneS", { Gv, Ev }, 0 }, | |
2595 | { "cmovbeS", { Gv, Ev }, 0 }, | |
2596 | { "cmovaS", { Gv, Ev }, 0 }, | |
252b5132 | 2597 | /* 48 */ |
bf890a93 IT |
2598 | { "cmovsS", { Gv, Ev }, 0 }, |
2599 | { "cmovnsS", { Gv, Ev }, 0 }, | |
2600 | { "cmovpS", { Gv, Ev }, 0 }, | |
2601 | { "cmovnpS", { Gv, Ev }, 0 }, | |
2602 | { "cmovlS", { Gv, Ev }, 0 }, | |
2603 | { "cmovgeS", { Gv, Ev }, 0 }, | |
2604 | { "cmovleS", { Gv, Ev }, 0 }, | |
2605 | { "cmovgS", { Gv, Ev }, 0 }, | |
252b5132 | 2606 | /* 50 */ |
a5aaedb9 | 2607 | { MOD_TABLE (MOD_0F50) }, |
1ceb70f8 L |
2608 | { PREFIX_TABLE (PREFIX_0F51) }, |
2609 | { PREFIX_TABLE (PREFIX_0F52) }, | |
2610 | { PREFIX_TABLE (PREFIX_0F53) }, | |
507bd325 L |
2611 | { "andpX", { XM, EXx }, PREFIX_OPCODE }, |
2612 | { "andnpX", { XM, EXx }, PREFIX_OPCODE }, | |
2613 | { "orpX", { XM, EXx }, PREFIX_OPCODE }, | |
2614 | { "xorpX", { XM, EXx }, PREFIX_OPCODE }, | |
252b5132 | 2615 | /* 58 */ |
1ceb70f8 L |
2616 | { PREFIX_TABLE (PREFIX_0F58) }, |
2617 | { PREFIX_TABLE (PREFIX_0F59) }, | |
2618 | { PREFIX_TABLE (PREFIX_0F5A) }, | |
2619 | { PREFIX_TABLE (PREFIX_0F5B) }, | |
2620 | { PREFIX_TABLE (PREFIX_0F5C) }, | |
2621 | { PREFIX_TABLE (PREFIX_0F5D) }, | |
2622 | { PREFIX_TABLE (PREFIX_0F5E) }, | |
2623 | { PREFIX_TABLE (PREFIX_0F5F) }, | |
252b5132 | 2624 | /* 60 */ |
1ceb70f8 L |
2625 | { PREFIX_TABLE (PREFIX_0F60) }, |
2626 | { PREFIX_TABLE (PREFIX_0F61) }, | |
2627 | { PREFIX_TABLE (PREFIX_0F62) }, | |
507bd325 L |
2628 | { "packsswb", { MX, EM }, PREFIX_OPCODE }, |
2629 | { "pcmpgtb", { MX, EM }, PREFIX_OPCODE }, | |
2630 | { "pcmpgtw", { MX, EM }, PREFIX_OPCODE }, | |
2631 | { "pcmpgtd", { MX, EM }, PREFIX_OPCODE }, | |
2632 | { "packuswb", { MX, EM }, PREFIX_OPCODE }, | |
252b5132 | 2633 | /* 68 */ |
507bd325 L |
2634 | { "punpckhbw", { MX, EM }, PREFIX_OPCODE }, |
2635 | { "punpckhwd", { MX, EM }, PREFIX_OPCODE }, | |
2636 | { "punpckhdq", { MX, EM }, PREFIX_OPCODE }, | |
2637 | { "packssdw", { MX, EM }, PREFIX_OPCODE }, | |
1ceb70f8 L |
2638 | { PREFIX_TABLE (PREFIX_0F6C) }, |
2639 | { PREFIX_TABLE (PREFIX_0F6D) }, | |
507bd325 | 2640 | { "movK", { MX, Edq }, PREFIX_OPCODE }, |
1ceb70f8 | 2641 | { PREFIX_TABLE (PREFIX_0F6F) }, |
252b5132 | 2642 | /* 70 */ |
1ceb70f8 L |
2643 | { PREFIX_TABLE (PREFIX_0F70) }, |
2644 | { REG_TABLE (REG_0F71) }, | |
2645 | { REG_TABLE (REG_0F72) }, | |
2646 | { REG_TABLE (REG_0F73) }, | |
507bd325 L |
2647 | { "pcmpeqb", { MX, EM }, PREFIX_OPCODE }, |
2648 | { "pcmpeqw", { MX, EM }, PREFIX_OPCODE }, | |
2649 | { "pcmpeqd", { MX, EM }, PREFIX_OPCODE }, | |
2650 | { "emms", { XX }, PREFIX_OPCODE }, | |
252b5132 | 2651 | /* 78 */ |
1ceb70f8 L |
2652 | { PREFIX_TABLE (PREFIX_0F78) }, |
2653 | { PREFIX_TABLE (PREFIX_0F79) }, | |
1f334aeb | 2654 | { Bad_Opcode }, |
592d1631 | 2655 | { Bad_Opcode }, |
1ceb70f8 L |
2656 | { PREFIX_TABLE (PREFIX_0F7C) }, |
2657 | { PREFIX_TABLE (PREFIX_0F7D) }, | |
2658 | { PREFIX_TABLE (PREFIX_0F7E) }, | |
2659 | { PREFIX_TABLE (PREFIX_0F7F) }, | |
252b5132 | 2660 | /* 80 */ |
bf890a93 IT |
2661 | { "joH", { Jv, BND, cond_jump_flag }, 0 }, |
2662 | { "jnoH", { Jv, BND, cond_jump_flag }, 0 }, | |
2663 | { "jbH", { Jv, BND, cond_jump_flag }, 0 }, | |
2664 | { "jaeH", { Jv, BND, cond_jump_flag }, 0 }, | |
2665 | { "jeH", { Jv, BND, cond_jump_flag }, 0 }, | |
2666 | { "jneH", { Jv, BND, cond_jump_flag }, 0 }, | |
2667 | { "jbeH", { Jv, BND, cond_jump_flag }, 0 }, | |
2668 | { "jaH", { Jv, BND, cond_jump_flag }, 0 }, | |
252b5132 | 2669 | /* 88 */ |
bf890a93 IT |
2670 | { "jsH", { Jv, BND, cond_jump_flag }, 0 }, |
2671 | { "jnsH", { Jv, BND, cond_jump_flag }, 0 }, | |
2672 | { "jpH", { Jv, BND, cond_jump_flag }, 0 }, | |
2673 | { "jnpH", { Jv, BND, cond_jump_flag }, 0 }, | |
2674 | { "jlH", { Jv, BND, cond_jump_flag }, 0 }, | |
2675 | { "jgeH", { Jv, BND, cond_jump_flag }, 0 }, | |
2676 | { "jleH", { Jv, BND, cond_jump_flag }, 0 }, | |
2677 | { "jgH", { Jv, BND, cond_jump_flag }, 0 }, | |
252b5132 | 2678 | /* 90 */ |
bf890a93 IT |
2679 | { "seto", { Eb }, 0 }, |
2680 | { "setno", { Eb }, 0 }, | |
2681 | { "setb", { Eb }, 0 }, | |
2682 | { "setae", { Eb }, 0 }, | |
2683 | { "sete", { Eb }, 0 }, | |
2684 | { "setne", { Eb }, 0 }, | |
2685 | { "setbe", { Eb }, 0 }, | |
2686 | { "seta", { Eb }, 0 }, | |
252b5132 | 2687 | /* 98 */ |
bf890a93 IT |
2688 | { "sets", { Eb }, 0 }, |
2689 | { "setns", { Eb }, 0 }, | |
2690 | { "setp", { Eb }, 0 }, | |
2691 | { "setnp", { Eb }, 0 }, | |
2692 | { "setl", { Eb }, 0 }, | |
2693 | { "setge", { Eb }, 0 }, | |
2694 | { "setle", { Eb }, 0 }, | |
2695 | { "setg", { Eb }, 0 }, | |
252b5132 | 2696 | /* a0 */ |
bf890a93 IT |
2697 | { "pushT", { fs }, 0 }, |
2698 | { "popT", { fs }, 0 }, | |
2699 | { "cpuid", { XX }, 0 }, | |
2700 | { "btS", { Ev, Gv }, 0 }, | |
2701 | { "shldS", { Ev, Gv, Ib }, 0 }, | |
2702 | { "shldS", { Ev, Gv, CL }, 0 }, | |
1ceb70f8 L |
2703 | { REG_TABLE (REG_0FA6) }, |
2704 | { REG_TABLE (REG_0FA7) }, | |
252b5132 | 2705 | /* a8 */ |
bf890a93 IT |
2706 | { "pushT", { gs }, 0 }, |
2707 | { "popT", { gs }, 0 }, | |
2708 | { "rsm", { XX }, 0 }, | |
2709 | { "btsS", { Evh1, Gv }, 0 }, | |
2710 | { "shrdS", { Ev, Gv, Ib }, 0 }, | |
2711 | { "shrdS", { Ev, Gv, CL }, 0 }, | |
1ceb70f8 | 2712 | { REG_TABLE (REG_0FAE) }, |
bf890a93 | 2713 | { "imulS", { Gv, Ev }, 0 }, |
252b5132 | 2714 | /* b0 */ |
bf890a93 IT |
2715 | { "cmpxchgB", { Ebh1, Gb }, 0 }, |
2716 | { "cmpxchgS", { Evh1, Gv }, 0 }, | |
1ceb70f8 | 2717 | { MOD_TABLE (MOD_0FB2) }, |
bf890a93 | 2718 | { "btrS", { Evh1, Gv }, 0 }, |
1ceb70f8 L |
2719 | { MOD_TABLE (MOD_0FB4) }, |
2720 | { MOD_TABLE (MOD_0FB5) }, | |
bf890a93 IT |
2721 | { "movz{bR|x}", { Gv, Eb }, 0 }, |
2722 | { "movz{wR|x}", { Gv, Ew }, 0 }, /* yes, there really is movzww ! */ | |
252b5132 | 2723 | /* b8 */ |
1ceb70f8 | 2724 | { PREFIX_TABLE (PREFIX_0FB8) }, |
66f1eba0 | 2725 | { "ud1S", { Gv, Ev }, 0 }, |
1ceb70f8 | 2726 | { REG_TABLE (REG_0FBA) }, |
bf890a93 | 2727 | { "btcS", { Evh1, Gv }, 0 }, |
f12dc422 | 2728 | { PREFIX_TABLE (PREFIX_0FBC) }, |
1ceb70f8 | 2729 | { PREFIX_TABLE (PREFIX_0FBD) }, |
bf890a93 IT |
2730 | { "movs{bR|x}", { Gv, Eb }, 0 }, |
2731 | { "movs{wR|x}", { Gv, Ew }, 0 }, /* yes, there really is movsww ! */ | |
252b5132 | 2732 | /* c0 */ |
bf890a93 IT |
2733 | { "xaddB", { Ebh1, Gb }, 0 }, |
2734 | { "xaddS", { Evh1, Gv }, 0 }, | |
1ceb70f8 | 2735 | { PREFIX_TABLE (PREFIX_0FC2) }, |
a8484f96 | 2736 | { MOD_TABLE (MOD_0FC3) }, |
507bd325 L |
2737 | { "pinsrw", { MX, Edqw, Ib }, PREFIX_OPCODE }, |
2738 | { "pextrw", { Gdq, MS, Ib }, PREFIX_OPCODE }, | |
2739 | { "shufpX", { XM, EXx, Ib }, PREFIX_OPCODE }, | |
1ceb70f8 | 2740 | { REG_TABLE (REG_0FC7) }, |
252b5132 | 2741 | /* c8 */ |
bf890a93 IT |
2742 | { "bswap", { RMeAX }, 0 }, |
2743 | { "bswap", { RMeCX }, 0 }, | |
2744 | { "bswap", { RMeDX }, 0 }, | |
2745 | { "bswap", { RMeBX }, 0 }, | |
2746 | { "bswap", { RMeSP }, 0 }, | |
2747 | { "bswap", { RMeBP }, 0 }, | |
2748 | { "bswap", { RMeSI }, 0 }, | |
2749 | { "bswap", { RMeDI }, 0 }, | |
252b5132 | 2750 | /* d0 */ |
1ceb70f8 | 2751 | { PREFIX_TABLE (PREFIX_0FD0) }, |
507bd325 L |
2752 | { "psrlw", { MX, EM }, PREFIX_OPCODE }, |
2753 | { "psrld", { MX, EM }, PREFIX_OPCODE }, | |
2754 | { "psrlq", { MX, EM }, PREFIX_OPCODE }, | |
2755 | { "paddq", { MX, EM }, PREFIX_OPCODE }, | |
2756 | { "pmullw", { MX, EM }, PREFIX_OPCODE }, | |
1ceb70f8 | 2757 | { PREFIX_TABLE (PREFIX_0FD6) }, |
75c135a8 | 2758 | { MOD_TABLE (MOD_0FD7) }, |
252b5132 | 2759 | /* d8 */ |
507bd325 L |
2760 | { "psubusb", { MX, EM }, PREFIX_OPCODE }, |
2761 | { "psubusw", { MX, EM }, PREFIX_OPCODE }, | |
2762 | { "pminub", { MX, EM }, PREFIX_OPCODE }, | |
2763 | { "pand", { MX, EM }, PREFIX_OPCODE }, | |
2764 | { "paddusb", { MX, EM }, PREFIX_OPCODE }, | |
2765 | { "paddusw", { MX, EM }, PREFIX_OPCODE }, | |
2766 | { "pmaxub", { MX, EM }, PREFIX_OPCODE }, | |
2767 | { "pandn", { MX, EM }, PREFIX_OPCODE }, | |
252b5132 | 2768 | /* e0 */ |
507bd325 L |
2769 | { "pavgb", { MX, EM }, PREFIX_OPCODE }, |
2770 | { "psraw", { MX, EM }, PREFIX_OPCODE }, | |
2771 | { "psrad", { MX, EM }, PREFIX_OPCODE }, | |
2772 | { "pavgw", { MX, EM }, PREFIX_OPCODE }, | |
2773 | { "pmulhuw", { MX, EM }, PREFIX_OPCODE }, | |
2774 | { "pmulhw", { MX, EM }, PREFIX_OPCODE }, | |
1ceb70f8 L |
2775 | { PREFIX_TABLE (PREFIX_0FE6) }, |
2776 | { PREFIX_TABLE (PREFIX_0FE7) }, | |
252b5132 | 2777 | /* e8 */ |
507bd325 L |
2778 | { "psubsb", { MX, EM }, PREFIX_OPCODE }, |
2779 | { "psubsw", { MX, EM }, PREFIX_OPCODE }, | |
2780 | { "pminsw", { MX, EM }, PREFIX_OPCODE }, | |
2781 | { "por", { MX, EM }, PREFIX_OPCODE }, | |
2782 | { "paddsb", { MX, EM }, PREFIX_OPCODE }, | |
2783 | { "paddsw", { MX, EM }, PREFIX_OPCODE }, | |
2784 | { "pmaxsw", { MX, EM }, PREFIX_OPCODE }, | |
2785 | { "pxor", { MX, EM }, PREFIX_OPCODE }, | |
252b5132 | 2786 | /* f0 */ |
1ceb70f8 | 2787 | { PREFIX_TABLE (PREFIX_0FF0) }, |
507bd325 L |
2788 | { "psllw", { MX, EM }, PREFIX_OPCODE }, |
2789 | { "pslld", { MX, EM }, PREFIX_OPCODE }, | |
2790 | { "psllq", { MX, EM }, PREFIX_OPCODE }, | |
2791 | { "pmuludq", { MX, EM }, PREFIX_OPCODE }, | |
2792 | { "pmaddwd", { MX, EM }, PREFIX_OPCODE }, | |
2793 | { "psadbw", { MX, EM }, PREFIX_OPCODE }, | |
1ceb70f8 | 2794 | { PREFIX_TABLE (PREFIX_0FF7) }, |
252b5132 | 2795 | /* f8 */ |
507bd325 L |
2796 | { "psubb", { MX, EM }, PREFIX_OPCODE }, |
2797 | { "psubw", { MX, EM }, PREFIX_OPCODE }, | |
2798 | { "psubd", { MX, EM }, PREFIX_OPCODE }, | |
2799 | { "psubq", { MX, EM }, PREFIX_OPCODE }, | |
2800 | { "paddb", { MX, EM }, PREFIX_OPCODE }, | |
2801 | { "paddw", { MX, EM }, PREFIX_OPCODE }, | |
2802 | { "paddd", { MX, EM }, PREFIX_OPCODE }, | |
66f1eba0 | 2803 | { "ud0S", { Gv, Ev }, 0 }, |
252b5132 RH |
2804 | }; |
2805 | ||
2806 | static const unsigned char onebyte_has_modrm[256] = { | |
c608c12e AM |
2807 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ |
2808 | /* ------------------------------- */ | |
2809 | /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */ | |
2810 | /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */ | |
2811 | /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */ | |
2812 | /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */ | |
2813 | /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */ | |
2814 | /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */ | |
2815 | /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */ | |
2816 | /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */ | |
2817 | /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */ | |
2818 | /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */ | |
2819 | /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */ | |
2820 | /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */ | |
2821 | /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */ | |
2822 | /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */ | |
2823 | /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */ | |
2824 | /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */ | |
2825 | /* ------------------------------- */ | |
2826 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ | |
252b5132 RH |
2827 | }; |
2828 | ||
2829 | static const unsigned char twobyte_has_modrm[256] = { | |
c608c12e AM |
2830 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ |
2831 | /* ------------------------------- */ | |
252b5132 | 2832 | /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */ |
b5b1fc4f | 2833 | /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */ |
85f10a01 | 2834 | /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */ |
331d2d0d | 2835 | /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */ |
252b5132 | 2836 | /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */ |
4bba6815 AM |
2837 | /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */ |
2838 | /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */ | |
85f10a01 | 2839 | /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */ |
252b5132 RH |
2840 | /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */ |
2841 | /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */ | |
30d1c836 | 2842 | /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */ |
66f1eba0 | 2843 | /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */ |
252b5132 | 2844 | /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */ |
ca164297 | 2845 | /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */ |
4bba6815 | 2846 | /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */ |
66f1eba0 | 2847 | /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1 /* ff */ |
c608c12e AM |
2848 | /* ------------------------------- */ |
2849 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ | |
2850 | }; | |
2851 | ||
252b5132 RH |
2852 | static char obuf[100]; |
2853 | static char *obufp; | |
ea397f5b | 2854 | static char *mnemonicendp; |
252b5132 RH |
2855 | static char scratchbuf[100]; |
2856 | static unsigned char *start_codep; | |
2857 | static unsigned char *insn_codep; | |
2858 | static unsigned char *codep; | |
285ca992 | 2859 | static unsigned char *end_codep; |
f16cd0d5 L |
2860 | static int last_lock_prefix; |
2861 | static int last_repz_prefix; | |
2862 | static int last_repnz_prefix; | |
2863 | static int last_data_prefix; | |
2864 | static int last_addr_prefix; | |
2865 | static int last_rex_prefix; | |
2866 | static int last_seg_prefix; | |
d9949a36 | 2867 | static int fwait_prefix; |
285ca992 L |
2868 | /* The active segment register prefix. */ |
2869 | static int active_seg_prefix; | |
f16cd0d5 L |
2870 | #define MAX_CODE_LENGTH 15 |
2871 | /* We can up to 14 prefixes since the maximum instruction length is | |
2872 | 15bytes. */ | |
2873 | static int all_prefixes[MAX_CODE_LENGTH - 1]; | |
252b5132 | 2874 | static disassemble_info *the_info; |
7967e09e L |
2875 | static struct |
2876 | { | |
2877 | int mod; | |
7967e09e | 2878 | int reg; |
484c222e | 2879 | int rm; |
7967e09e L |
2880 | } |
2881 | modrm; | |
4bba6815 | 2882 | static unsigned char need_modrm; |
dfc8cf43 L |
2883 | static struct |
2884 | { | |
2885 | int scale; | |
2886 | int index; | |
2887 | int base; | |
2888 | } | |
2889 | sib; | |
c0f3af97 L |
2890 | static struct |
2891 | { | |
2892 | int register_specifier; | |
2893 | int length; | |
2894 | int prefix; | |
2895 | int w; | |
43234a1e L |
2896 | int evex; |
2897 | int r; | |
2898 | int v; | |
2899 | int mask_register_specifier; | |
2900 | int zeroing; | |
2901 | int ll; | |
2902 | int b; | |
c0f3af97 L |
2903 | } |
2904 | vex; | |
2905 | static unsigned char need_vex; | |
2906 | static unsigned char need_vex_reg; | |
dae39acc | 2907 | static unsigned char vex_w_done; |
252b5132 | 2908 | |
ea397f5b L |
2909 | struct op |
2910 | { | |
2911 | const char *name; | |
2912 | unsigned int len; | |
2913 | }; | |
2914 | ||
4bba6815 AM |
2915 | /* If we are accessing mod/rm/reg without need_modrm set, then the |
2916 | values are stale. Hitting this abort likely indicates that you | |
2917 | need to update onebyte_has_modrm or twobyte_has_modrm. */ | |
2918 | #define MODRM_CHECK if (!need_modrm) abort () | |
2919 | ||
d708bcba AM |
2920 | static const char **names64; |
2921 | static const char **names32; | |
2922 | static const char **names16; | |
2923 | static const char **names8; | |
2924 | static const char **names8rex; | |
2925 | static const char **names_seg; | |
db51cc60 L |
2926 | static const char *index64; |
2927 | static const char *index32; | |
d708bcba | 2928 | static const char **index16; |
7e8b059b | 2929 | static const char **names_bnd; |
d708bcba AM |
2930 | |
2931 | static const char *intel_names64[] = { | |
2932 | "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi", | |
2933 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15" | |
2934 | }; | |
2935 | static const char *intel_names32[] = { | |
2936 | "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi", | |
2937 | "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d" | |
2938 | }; | |
2939 | static const char *intel_names16[] = { | |
2940 | "ax", "cx", "dx", "bx", "sp", "bp", "si", "di", | |
2941 | "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w" | |
2942 | }; | |
2943 | static const char *intel_names8[] = { | |
2944 | "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh", | |
2945 | }; | |
2946 | static const char *intel_names8rex[] = { | |
2947 | "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil", | |
2948 | "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b" | |
2949 | }; | |
2950 | static const char *intel_names_seg[] = { | |
2951 | "es", "cs", "ss", "ds", "fs", "gs", "?", "?", | |
2952 | }; | |
db51cc60 L |
2953 | static const char *intel_index64 = "riz"; |
2954 | static const char *intel_index32 = "eiz"; | |
d708bcba AM |
2955 | static const char *intel_index16[] = { |
2956 | "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx" | |
2957 | }; | |
2958 | ||
2959 | static const char *att_names64[] = { | |
2960 | "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi", | |
52b15da3 JH |
2961 | "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15" |
2962 | }; | |
d708bcba AM |
2963 | static const char *att_names32[] = { |
2964 | "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi", | |
52b15da3 | 2965 | "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d" |
252b5132 | 2966 | }; |
d708bcba AM |
2967 | static const char *att_names16[] = { |
2968 | "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di", | |
52b15da3 | 2969 | "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w" |
252b5132 | 2970 | }; |
d708bcba AM |
2971 | static const char *att_names8[] = { |
2972 | "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh", | |
252b5132 | 2973 | }; |
d708bcba AM |
2974 | static const char *att_names8rex[] = { |
2975 | "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil", | |
52b15da3 JH |
2976 | "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b" |
2977 | }; | |
d708bcba AM |
2978 | static const char *att_names_seg[] = { |
2979 | "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?", | |
252b5132 | 2980 | }; |
db51cc60 L |
2981 | static const char *att_index64 = "%riz"; |
2982 | static const char *att_index32 = "%eiz"; | |
d708bcba AM |
2983 | static const char *att_index16[] = { |
2984 | "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx" | |
252b5132 RH |
2985 | }; |
2986 | ||
b9733481 L |
2987 | static const char **names_mm; |
2988 | static const char *intel_names_mm[] = { | |
2989 | "mm0", "mm1", "mm2", "mm3", | |
2990 | "mm4", "mm5", "mm6", "mm7" | |
2991 | }; | |
2992 | static const char *att_names_mm[] = { | |
2993 | "%mm0", "%mm1", "%mm2", "%mm3", | |
2994 | "%mm4", "%mm5", "%mm6", "%mm7" | |
2995 | }; | |
2996 | ||
7e8b059b L |
2997 | static const char *intel_names_bnd[] = { |
2998 | "bnd0", "bnd1", "bnd2", "bnd3" | |
2999 | }; | |
3000 | ||
3001 | static const char *att_names_bnd[] = { | |
3002 | "%bnd0", "%bnd1", "%bnd2", "%bnd3" | |
3003 | }; | |
3004 | ||
b9733481 L |
3005 | static const char **names_xmm; |
3006 | static const char *intel_names_xmm[] = { | |
3007 | "xmm0", "xmm1", "xmm2", "xmm3", | |
3008 | "xmm4", "xmm5", "xmm6", "xmm7", | |
3009 | "xmm8", "xmm9", "xmm10", "xmm11", | |
43234a1e L |
3010 | "xmm12", "xmm13", "xmm14", "xmm15", |
3011 | "xmm16", "xmm17", "xmm18", "xmm19", | |
3012 | "xmm20", "xmm21", "xmm22", "xmm23", | |
3013 | "xmm24", "xmm25", "xmm26", "xmm27", | |
3014 | "xmm28", "xmm29", "xmm30", "xmm31" | |
b9733481 L |
3015 | }; |
3016 | static const char *att_names_xmm[] = { | |
3017 | "%xmm0", "%xmm1", "%xmm2", "%xmm3", | |
3018 | "%xmm4", "%xmm5", "%xmm6", "%xmm7", | |
3019 | "%xmm8", "%xmm9", "%xmm10", "%xmm11", | |
43234a1e L |
3020 | "%xmm12", "%xmm13", "%xmm14", "%xmm15", |
3021 | "%xmm16", "%xmm17", "%xmm18", "%xmm19", | |
3022 | "%xmm20", "%xmm21", "%xmm22", "%xmm23", | |
3023 | "%xmm24", "%xmm25", "%xmm26", "%xmm27", | |
3024 | "%xmm28", "%xmm29", "%xmm30", "%xmm31" | |
b9733481 L |
3025 | }; |
3026 | ||
3027 | static const char **names_ymm; | |
3028 | static const char *intel_names_ymm[] = { | |
3029 | "ymm0", "ymm1", "ymm2", "ymm3", | |
3030 | "ymm4", "ymm5", "ymm6", "ymm7", | |
3031 | "ymm8", "ymm9", "ymm10", "ymm11", | |
43234a1e L |
3032 | "ymm12", "ymm13", "ymm14", "ymm15", |
3033 | "ymm16", "ymm17", "ymm18", "ymm19", | |
3034 | "ymm20", "ymm21", "ymm22", "ymm23", | |
3035 | "ymm24", "ymm25", "ymm26", "ymm27", | |
3036 | "ymm28", "ymm29", "ymm30", "ymm31" | |
b9733481 L |
3037 | }; |
3038 | static const char *att_names_ymm[] = { | |
3039 | "%ymm0", "%ymm1", "%ymm2", "%ymm3", | |
3040 | "%ymm4", "%ymm5", "%ymm6", "%ymm7", | |
3041 | "%ymm8", "%ymm9", "%ymm10", "%ymm11", | |
43234a1e L |
3042 | "%ymm12", "%ymm13", "%ymm14", "%ymm15", |
3043 | "%ymm16", "%ymm17", "%ymm18", "%ymm19", | |
3044 | "%ymm20", "%ymm21", "%ymm22", "%ymm23", | |
3045 | "%ymm24", "%ymm25", "%ymm26", "%ymm27", | |
3046 | "%ymm28", "%ymm29", "%ymm30", "%ymm31" | |
3047 | }; | |
3048 | ||
3049 | static const char **names_zmm; | |
3050 | static const char *intel_names_zmm[] = { | |
3051 | "zmm0", "zmm1", "zmm2", "zmm3", | |
3052 | "zmm4", "zmm5", "zmm6", "zmm7", | |
3053 | "zmm8", "zmm9", "zmm10", "zmm11", | |
3054 | "zmm12", "zmm13", "zmm14", "zmm15", | |
3055 | "zmm16", "zmm17", "zmm18", "zmm19", | |
3056 | "zmm20", "zmm21", "zmm22", "zmm23", | |
3057 | "zmm24", "zmm25", "zmm26", "zmm27", | |
3058 | "zmm28", "zmm29", "zmm30", "zmm31" | |
3059 | }; | |
3060 | static const char *att_names_zmm[] = { | |
3061 | "%zmm0", "%zmm1", "%zmm2", "%zmm3", | |
3062 | "%zmm4", "%zmm5", "%zmm6", "%zmm7", | |
3063 | "%zmm8", "%zmm9", "%zmm10", "%zmm11", | |
3064 | "%zmm12", "%zmm13", "%zmm14", "%zmm15", | |
3065 | "%zmm16", "%zmm17", "%zmm18", "%zmm19", | |
3066 | "%zmm20", "%zmm21", "%zmm22", "%zmm23", | |
3067 | "%zmm24", "%zmm25", "%zmm26", "%zmm27", | |
3068 | "%zmm28", "%zmm29", "%zmm30", "%zmm31" | |
3069 | }; | |
3070 | ||
3071 | static const char **names_mask; | |
3072 | static const char *intel_names_mask[] = { | |
3073 | "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7" | |
3074 | }; | |
3075 | static const char *att_names_mask[] = { | |
3076 | "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7" | |
3077 | }; | |
3078 | ||
3079 | static const char *names_rounding[] = | |
3080 | { | |
3081 | "{rn-sae}", | |
3082 | "{rd-sae}", | |
3083 | "{ru-sae}", | |
3084 | "{rz-sae}" | |
b9733481 L |
3085 | }; |
3086 | ||
1ceb70f8 L |
3087 | static const struct dis386 reg_table[][8] = { |
3088 | /* REG_80 */ | |
252b5132 | 3089 | { |
bf890a93 IT |
3090 | { "addA", { Ebh1, Ib }, 0 }, |
3091 | { "orA", { Ebh1, Ib }, 0 }, | |
3092 | { "adcA", { Ebh1, Ib }, 0 }, | |
3093 | { "sbbA", { Ebh1, Ib }, 0 }, | |
3094 | { "andA", { Ebh1, Ib }, 0 }, | |
3095 | { "subA", { Ebh1, Ib }, 0 }, | |
3096 | { "xorA", { Ebh1, Ib }, 0 }, | |
3097 | { "cmpA", { Eb, Ib }, 0 }, | |
252b5132 | 3098 | }, |
1ceb70f8 | 3099 | /* REG_81 */ |
252b5132 | 3100 | { |
bf890a93 IT |
3101 | { "addQ", { Evh1, Iv }, 0 }, |
3102 | { "orQ", { Evh1, Iv }, 0 }, | |
3103 | { "adcQ", { Evh1, Iv }, 0 }, | |
3104 | { "sbbQ", { Evh1, Iv }, 0 }, | |
3105 | { "andQ", { Evh1, Iv }, 0 }, | |
3106 | { "subQ", { Evh1, Iv }, 0 }, | |
3107 | { "xorQ", { Evh1, Iv }, 0 }, | |
3108 | { "cmpQ", { Ev, Iv }, 0 }, | |
252b5132 | 3109 | }, |
7148c369 | 3110 | /* REG_83 */ |
252b5132 | 3111 | { |
bf890a93 IT |
3112 | { "addQ", { Evh1, sIb }, 0 }, |
3113 | { "orQ", { Evh1, sIb }, 0 }, | |
3114 | { "adcQ", { Evh1, sIb }, 0 }, | |
3115 | { "sbbQ", { Evh1, sIb }, 0 }, | |
3116 | { "andQ", { Evh1, sIb }, 0 }, | |
3117 | { "subQ", { Evh1, sIb }, 0 }, | |
3118 | { "xorQ", { Evh1, sIb }, 0 }, | |
3119 | { "cmpQ", { Ev, sIb }, 0 }, | |
252b5132 | 3120 | }, |
1ceb70f8 | 3121 | /* REG_8F */ |
4e7d34a6 | 3122 | { |
bf890a93 | 3123 | { "popU", { stackEv }, 0 }, |
c48244a5 | 3124 | { XOP_8F_TABLE (XOP_09) }, |
592d1631 L |
3125 | { Bad_Opcode }, |
3126 | { Bad_Opcode }, | |
3127 | { Bad_Opcode }, | |
f88c9eb0 | 3128 | { XOP_8F_TABLE (XOP_09) }, |
4e7d34a6 | 3129 | }, |
1ceb70f8 | 3130 | /* REG_C0 */ |
252b5132 | 3131 | { |
bf890a93 IT |
3132 | { "rolA", { Eb, Ib }, 0 }, |
3133 | { "rorA", { Eb, Ib }, 0 }, | |
3134 | { "rclA", { Eb, Ib }, 0 }, | |
3135 | { "rcrA", { Eb, Ib }, 0 }, | |
3136 | { "shlA", { Eb, Ib }, 0 }, | |
3137 | { "shrA", { Eb, Ib }, 0 }, | |
e4bdd679 | 3138 | { "shlA", { Eb, Ib }, 0 }, |
bf890a93 | 3139 | { "sarA", { Eb, Ib }, 0 }, |
252b5132 | 3140 | }, |
1ceb70f8 | 3141 | /* REG_C1 */ |
252b5132 | 3142 | { |
bf890a93 IT |
3143 | { "rolQ", { Ev, Ib }, 0 }, |
3144 | { "rorQ", { Ev, Ib }, 0 }, | |
3145 | { "rclQ", { Ev, Ib }, 0 }, | |
3146 | { "rcrQ", { Ev, Ib }, 0 }, | |
3147 | { "shlQ", { Ev, Ib }, 0 }, | |
3148 | { "shrQ", { Ev, Ib }, 0 }, | |
e4bdd679 | 3149 | { "shlQ", { Ev, Ib }, 0 }, |
bf890a93 | 3150 | { "sarQ", { Ev, Ib }, 0 }, |
252b5132 | 3151 | }, |
1ceb70f8 | 3152 | /* REG_C6 */ |
4e7d34a6 | 3153 | { |
bf890a93 | 3154 | { "movA", { Ebh3, Ib }, 0 }, |
42164a71 L |
3155 | { Bad_Opcode }, |
3156 | { Bad_Opcode }, | |
3157 | { Bad_Opcode }, | |
3158 | { Bad_Opcode }, | |
3159 | { Bad_Opcode }, | |
3160 | { Bad_Opcode }, | |
3161 | { MOD_TABLE (MOD_C6_REG_7) }, | |
4e7d34a6 | 3162 | }, |
1ceb70f8 | 3163 | /* REG_C7 */ |
4e7d34a6 | 3164 | { |
bf890a93 | 3165 | { "movQ", { Evh3, Iv }, 0 }, |
42164a71 L |
3166 | { Bad_Opcode }, |
3167 | { Bad_Opcode }, | |
3168 | { Bad_Opcode }, | |
3169 | { Bad_Opcode }, | |
3170 | { Bad_Opcode }, | |
3171 | { Bad_Opcode }, | |
3172 | { MOD_TABLE (MOD_C7_REG_7) }, | |
4e7d34a6 | 3173 | }, |
1ceb70f8 | 3174 | /* REG_D0 */ |
252b5132 | 3175 | { |
bf890a93 IT |
3176 | { "rolA", { Eb, I1 }, 0 }, |
3177 | { "rorA", { Eb, I1 }, 0 }, | |
3178 | { "rclA", { Eb, I1 }, 0 }, | |
3179 | { "rcrA", { Eb, I1 }, 0 }, | |
3180 | { "shlA", { Eb, I1 }, 0 }, | |
3181 | { "shrA", { Eb, I1 }, 0 }, | |
e4bdd679 | 3182 | { "shlA", { Eb, I1 }, 0 }, |
bf890a93 | 3183 | { "sarA", { Eb, I1 }, 0 }, |
252b5132 | 3184 | }, |
1ceb70f8 | 3185 | /* REG_D1 */ |
252b5132 | 3186 | { |
bf890a93 IT |
3187 | { "rolQ", { Ev, I1 }, 0 }, |
3188 | { "rorQ", { Ev, I1 }, 0 }, | |
3189 | { "rclQ", { Ev, I1 }, 0 }, | |
3190 | { "rcrQ", { Ev, I1 }, 0 }, | |
3191 | { "shlQ", { Ev, I1 }, 0 }, | |
3192 | { "shrQ", { Ev, I1 }, 0 }, | |
e4bdd679 | 3193 | { "shlQ", { Ev, I1 }, 0 }, |
bf890a93 | 3194 | { "sarQ", { Ev, I1 }, 0 }, |
252b5132 | 3195 | }, |
1ceb70f8 | 3196 | /* REG_D2 */ |
252b5132 | 3197 | { |
bf890a93 IT |
3198 | { "rolA", { Eb, CL }, 0 }, |
3199 | { "rorA", { Eb, CL }, 0 }, | |
3200 | { "rclA", { Eb, CL }, 0 }, | |
3201 | { "rcrA", { Eb, CL }, 0 }, | |
3202 | { "shlA", { Eb, CL }, 0 }, | |
3203 | { "shrA", { Eb, CL }, 0 }, | |
e4bdd679 | 3204 | { "shlA", { Eb, CL }, 0 }, |
bf890a93 | 3205 | { "sarA", { Eb, CL }, 0 }, |
252b5132 | 3206 | }, |
1ceb70f8 | 3207 | /* REG_D3 */ |
252b5132 | 3208 | { |
bf890a93 IT |
3209 | { "rolQ", { Ev, CL }, 0 }, |
3210 | { "rorQ", { Ev, CL }, 0 }, | |
3211 | { "rclQ", { Ev, CL }, 0 }, | |
3212 | { "rcrQ", { Ev, CL }, 0 }, | |
3213 | { "shlQ", { Ev, CL }, 0 }, | |
3214 | { "shrQ", { Ev, CL }, 0 }, | |
e4bdd679 | 3215 | { "shlQ", { Ev, CL }, 0 }, |
bf890a93 | 3216 | { "sarQ", { Ev, CL }, 0 }, |
252b5132 | 3217 | }, |
1ceb70f8 | 3218 | /* REG_F6 */ |
252b5132 | 3219 | { |
bf890a93 | 3220 | { "testA", { Eb, Ib }, 0 }, |
7db2c588 | 3221 | { "testA", { Eb, Ib }, 0 }, |
bf890a93 IT |
3222 | { "notA", { Ebh1 }, 0 }, |
3223 | { "negA", { Ebh1 }, 0 }, | |
3224 | { "mulA", { Eb }, 0 }, /* Don't print the implicit %al register, */ | |
3225 | { "imulA", { Eb }, 0 }, /* to distinguish these opcodes from other */ | |
3226 | { "divA", { Eb }, 0 }, /* mul/imul opcodes. Do the same for div */ | |
3227 | { "idivA", { Eb }, 0 }, /* and idiv for consistency. */ | |
252b5132 | 3228 | }, |
1ceb70f8 | 3229 | /* REG_F7 */ |
252b5132 | 3230 | { |
bf890a93 | 3231 | { "testQ", { Ev, Iv }, 0 }, |
7db2c588 | 3232 | { "testQ", { Ev, Iv }, 0 }, |
bf890a93 IT |
3233 | { "notQ", { Evh1 }, 0 }, |
3234 | { "negQ", { Evh1 }, 0 }, | |
3235 | { "mulQ", { Ev }, 0 }, /* Don't print the implicit register. */ | |
3236 | { "imulQ", { Ev }, 0 }, | |
3237 | { "divQ", { Ev }, 0 }, | |
3238 | { "idivQ", { Ev }, 0 }, | |
252b5132 | 3239 | }, |
1ceb70f8 | 3240 | /* REG_FE */ |
252b5132 | 3241 | { |
bf890a93 IT |
3242 | { "incA", { Ebh1 }, 0 }, |
3243 | { "decA", { Ebh1 }, 0 }, | |
252b5132 | 3244 | }, |
1ceb70f8 | 3245 | /* REG_FF */ |
252b5132 | 3246 | { |
bf890a93 IT |
3247 | { "incQ", { Evh1 }, 0 }, |
3248 | { "decQ", { Evh1 }, 0 }, | |
9fef80d6 | 3249 | { "call{&|}", { NOTRACK, indirEv, BND }, 0 }, |
4a357820 | 3250 | { MOD_TABLE (MOD_FF_REG_3) }, |
9fef80d6 | 3251 | { "jmp{&|}", { NOTRACK, indirEv, BND }, 0 }, |
4a357820 | 3252 | { MOD_TABLE (MOD_FF_REG_5) }, |
bf890a93 | 3253 | { "pushU", { stackEv }, 0 }, |
592d1631 | 3254 | { Bad_Opcode }, |
252b5132 | 3255 | }, |
1ceb70f8 | 3256 | /* REG_0F00 */ |
252b5132 | 3257 | { |
bf890a93 IT |
3258 | { "sldtD", { Sv }, 0 }, |
3259 | { "strD", { Sv }, 0 }, | |
3260 | { "lldt", { Ew }, 0 }, | |
3261 | { "ltr", { Ew }, 0 }, | |
3262 | { "verr", { Ew }, 0 }, | |
3263 | { "verw", { Ew }, 0 }, | |
592d1631 L |
3264 | { Bad_Opcode }, |
3265 | { Bad_Opcode }, | |
252b5132 | 3266 | }, |
1ceb70f8 | 3267 | /* REG_0F01 */ |
252b5132 | 3268 | { |
1ceb70f8 L |
3269 | { MOD_TABLE (MOD_0F01_REG_0) }, |
3270 | { MOD_TABLE (MOD_0F01_REG_1) }, | |
3271 | { MOD_TABLE (MOD_0F01_REG_2) }, | |
3272 | { MOD_TABLE (MOD_0F01_REG_3) }, | |
bf890a93 | 3273 | { "smswD", { Sv }, 0 }, |
8eab4136 | 3274 | { MOD_TABLE (MOD_0F01_REG_5) }, |
bf890a93 | 3275 | { "lmsw", { Ew }, 0 }, |
1ceb70f8 | 3276 | { MOD_TABLE (MOD_0F01_REG_7) }, |
252b5132 | 3277 | }, |
b5b1fc4f | 3278 | /* REG_0F0D */ |
252b5132 | 3279 | { |
bf890a93 IT |
3280 | { "prefetch", { Mb }, 0 }, |
3281 | { "prefetchw", { Mb }, 0 }, | |
3282 | { "prefetchwt1", { Mb }, 0 }, | |
3283 | { "prefetch", { Mb }, 0 }, | |
3284 | { "prefetch", { Mb }, 0 }, | |
3285 | { "prefetch", { Mb }, 0 }, | |
3286 | { "prefetch", { Mb }, 0 }, | |
3287 | { "prefetch", { Mb }, 0 }, | |
252b5132 | 3288 | }, |
1ceb70f8 | 3289 | /* REG_0F18 */ |
252b5132 | 3290 | { |
1ceb70f8 L |
3291 | { MOD_TABLE (MOD_0F18_REG_0) }, |
3292 | { MOD_TABLE (MOD_0F18_REG_1) }, | |
3293 | { MOD_TABLE (MOD_0F18_REG_2) }, | |
3294 | { MOD_TABLE (MOD_0F18_REG_3) }, | |
d7189fa5 RM |
3295 | { MOD_TABLE (MOD_0F18_REG_4) }, |
3296 | { MOD_TABLE (MOD_0F18_REG_5) }, | |
3297 | { MOD_TABLE (MOD_0F18_REG_6) }, | |
3298 | { MOD_TABLE (MOD_0F18_REG_7) }, | |
252b5132 | 3299 | }, |
f8687e93 | 3300 | /* REG_0F1C_P_0_MOD_0 */ |
c48935d7 IT |
3301 | { |
3302 | { "cldemote", { Mb }, 0 }, | |
3303 | { "nopQ", { Ev }, 0 }, | |
3304 | { "nopQ", { Ev }, 0 }, | |
3305 | { "nopQ", { Ev }, 0 }, | |
3306 | { "nopQ", { Ev }, 0 }, | |
3307 | { "nopQ", { Ev }, 0 }, | |
3308 | { "nopQ", { Ev }, 0 }, | |
3309 | { "nopQ", { Ev }, 0 }, | |
3310 | }, | |
f8687e93 | 3311 | /* REG_0F1E_P_1_MOD_3 */ |
603555e5 L |
3312 | { |
3313 | { "nopQ", { Ev }, 0 }, | |
3314 | { "rdsspK", { Rdq }, PREFIX_OPCODE }, | |
3315 | { "nopQ", { Ev }, 0 }, | |
3316 | { "nopQ", { Ev }, 0 }, | |
3317 | { "nopQ", { Ev }, 0 }, | |
3318 | { "nopQ", { Ev }, 0 }, | |
3319 | { "nopQ", { Ev }, 0 }, | |
f8687e93 | 3320 | { RM_TABLE (RM_0F1E_P_1_MOD_3_REG_7) }, |
603555e5 | 3321 | }, |
1ceb70f8 | 3322 | /* REG_0F71 */ |
a6bd098c | 3323 | { |
592d1631 L |
3324 | { Bad_Opcode }, |
3325 | { Bad_Opcode }, | |
1ceb70f8 | 3326 | { MOD_TABLE (MOD_0F71_REG_2) }, |
592d1631 | 3327 | { Bad_Opcode }, |
1ceb70f8 | 3328 | { MOD_TABLE (MOD_0F71_REG_4) }, |
592d1631 | 3329 | { Bad_Opcode }, |
1ceb70f8 | 3330 | { MOD_TABLE (MOD_0F71_REG_6) }, |
a6bd098c | 3331 | }, |
1ceb70f8 | 3332 | /* REG_0F72 */ |
a6bd098c | 3333 | { |
592d1631 L |
3334 | { Bad_Opcode }, |
3335 | { Bad_Opcode }, | |
1ceb70f8 | 3336 | { MOD_TABLE (MOD_0F72_REG_2) }, |
592d1631 | 3337 | { Bad_Opcode }, |
1ceb70f8 | 3338 | { MOD_TABLE (MOD_0F72_REG_4) }, |
592d1631 | 3339 | { Bad_Opcode }, |
1ceb70f8 | 3340 | { MOD_TABLE (MOD_0F72_REG_6) }, |
a6bd098c | 3341 | }, |
1ceb70f8 | 3342 | /* REG_0F73 */ |
252b5132 | 3343 | { |
592d1631 L |
3344 | { Bad_Opcode }, |
3345 | { Bad_Opcode }, | |
1ceb70f8 L |
3346 | { MOD_TABLE (MOD_0F73_REG_2) }, |
3347 | { MOD_TABLE (MOD_0F73_REG_3) }, | |
592d1631 L |
3348 | { Bad_Opcode }, |
3349 | { Bad_Opcode }, | |
1ceb70f8 L |
3350 | { MOD_TABLE (MOD_0F73_REG_6) }, |
3351 | { MOD_TABLE (MOD_0F73_REG_7) }, | |
252b5132 | 3352 | }, |
1ceb70f8 | 3353 | /* REG_0FA6 */ |
252b5132 | 3354 | { |
bf890a93 IT |
3355 | { "montmul", { { OP_0f07, 0 } }, 0 }, |
3356 | { "xsha1", { { OP_0f07, 0 } }, 0 }, | |
3357 | { "xsha256", { { OP_0f07, 0 } }, 0 }, | |
4e7d34a6 | 3358 | }, |
1ceb70f8 | 3359 | /* REG_0FA7 */ |
4e7d34a6 | 3360 | { |
bf890a93 IT |
3361 | { "xstore-rng", { { OP_0f07, 0 } }, 0 }, |
3362 | { "xcrypt-ecb", { { OP_0f07, 0 } }, 0 }, | |
3363 | { "xcrypt-cbc", { { OP_0f07, 0 } }, 0 }, | |
3364 | { "xcrypt-ctr", { { OP_0f07, 0 } }, 0 }, | |
3365 | { "xcrypt-cfb", { { OP_0f07, 0 } }, 0 }, | |
3366 | { "xcrypt-ofb", { { OP_0f07, 0 } }, 0 }, | |
4e7d34a6 | 3367 | }, |
1ceb70f8 | 3368 | /* REG_0FAE */ |
4e7d34a6 | 3369 | { |
1ceb70f8 L |
3370 | { MOD_TABLE (MOD_0FAE_REG_0) }, |
3371 | { MOD_TABLE (MOD_0FAE_REG_1) }, | |
3372 | { MOD_TABLE (MOD_0FAE_REG_2) }, | |
3373 | { MOD_TABLE (MOD_0FAE_REG_3) }, | |
475a2301 | 3374 | { MOD_TABLE (MOD_0FAE_REG_4) }, |
1ceb70f8 L |
3375 | { MOD_TABLE (MOD_0FAE_REG_5) }, |
3376 | { MOD_TABLE (MOD_0FAE_REG_6) }, | |
3377 | { MOD_TABLE (MOD_0FAE_REG_7) }, | |
252b5132 | 3378 | }, |
1ceb70f8 | 3379 | /* REG_0FBA */ |
252b5132 | 3380 | { |
592d1631 L |
3381 | { Bad_Opcode }, |
3382 | { Bad_Opcode }, | |
3383 | { Bad_Opcode }, | |
3384 | { Bad_Opcode }, | |
bf890a93 IT |
3385 | { "btQ", { Ev, Ib }, 0 }, |
3386 | { "btsQ", { Evh1, Ib }, 0 }, | |
3387 | { "btrQ", { Evh1, Ib }, 0 }, | |
3388 | { "btcQ", { Evh1, Ib }, 0 }, | |
c608c12e | 3389 | }, |
1ceb70f8 | 3390 | /* REG_0FC7 */ |
c608c12e | 3391 | { |
592d1631 | 3392 | { Bad_Opcode }, |
bf890a93 | 3393 | { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 }, |
592d1631 | 3394 | { Bad_Opcode }, |
963f3586 IT |
3395 | { MOD_TABLE (MOD_0FC7_REG_3) }, |
3396 | { MOD_TABLE (MOD_0FC7_REG_4) }, | |
3397 | { MOD_TABLE (MOD_0FC7_REG_5) }, | |
1ceb70f8 L |
3398 | { MOD_TABLE (MOD_0FC7_REG_6) }, |
3399 | { MOD_TABLE (MOD_0FC7_REG_7) }, | |
252b5132 | 3400 | }, |
592a252b | 3401 | /* REG_VEX_0F71 */ |
c0f3af97 | 3402 | { |
592d1631 L |
3403 | { Bad_Opcode }, |
3404 | { Bad_Opcode }, | |
592a252b | 3405 | { MOD_TABLE (MOD_VEX_0F71_REG_2) }, |
592d1631 | 3406 | { Bad_Opcode }, |
592a252b | 3407 | { MOD_TABLE (MOD_VEX_0F71_REG_4) }, |
592d1631 | 3408 | { Bad_Opcode }, |
592a252b | 3409 | { MOD_TABLE (MOD_VEX_0F71_REG_6) }, |
c0f3af97 | 3410 | }, |
592a252b | 3411 | /* REG_VEX_0F72 */ |
c0f3af97 | 3412 | { |
592d1631 L |
3413 | { Bad_Opcode }, |
3414 | { Bad_Opcode }, | |
592a252b | 3415 | { MOD_TABLE (MOD_VEX_0F72_REG_2) }, |
592d1631 | 3416 | { Bad_Opcode }, |
592a252b | 3417 | { MOD_TABLE (MOD_VEX_0F72_REG_4) }, |
592d1631 | 3418 | { Bad_Opcode }, |
592a252b | 3419 | { MOD_TABLE (MOD_VEX_0F72_REG_6) }, |
c0f3af97 | 3420 | }, |
592a252b | 3421 | /* REG_VEX_0F73 */ |
c0f3af97 | 3422 | { |
592d1631 L |
3423 | { Bad_Opcode }, |
3424 | { Bad_Opcode }, | |
592a252b L |
3425 | { MOD_TABLE (MOD_VEX_0F73_REG_2) }, |
3426 | { MOD_TABLE (MOD_VEX_0F73_REG_3) }, | |
592d1631 L |
3427 | { Bad_Opcode }, |
3428 | { Bad_Opcode }, | |
592a252b L |
3429 | { MOD_TABLE (MOD_VEX_0F73_REG_6) }, |
3430 | { MOD_TABLE (MOD_VEX_0F73_REG_7) }, | |
c0f3af97 | 3431 | }, |
592a252b | 3432 | /* REG_VEX_0FAE */ |
c0f3af97 | 3433 | { |
592d1631 L |
3434 | { Bad_Opcode }, |
3435 | { Bad_Opcode }, | |
592a252b L |
3436 | { MOD_TABLE (MOD_VEX_0FAE_REG_2) }, |
3437 | { MOD_TABLE (MOD_VEX_0FAE_REG_3) }, | |
c0f3af97 | 3438 | }, |
f12dc422 L |
3439 | /* REG_VEX_0F38F3 */ |
3440 | { | |
3441 | { Bad_Opcode }, | |
3442 | { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) }, | |
3443 | { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) }, | |
3444 | { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) }, | |
3445 | }, | |
f88c9eb0 SP |
3446 | /* REG_XOP_LWPCB */ |
3447 | { | |
bf890a93 IT |
3448 | { "llwpcb", { { OP_LWPCB_E, 0 } }, 0 }, |
3449 | { "slwpcb", { { OP_LWPCB_E, 0 } }, 0 }, | |
f88c9eb0 SP |
3450 | }, |
3451 | /* REG_XOP_LWP */ | |
3452 | { | |
c1dc7af5 JB |
3453 | { "lwpins", { { OP_LWP_E, 0 }, Ed, Id }, 0 }, |
3454 | { "lwpval", { { OP_LWP_E, 0 }, Ed, Id }, 0 }, | |
f88c9eb0 | 3455 | }, |
2a2a0f38 QN |
3456 | /* REG_XOP_TBM_01 */ |
3457 | { | |
3458 | { Bad_Opcode }, | |
c1dc7af5 JB |
3459 | { "blcfill", { { OP_LWP_E, 0 }, Edq }, 0 }, |
3460 | { "blsfill", { { OP_LWP_E, 0 }, Edq }, 0 }, | |
3461 | { "blcs", { { OP_LWP_E, 0 }, Edq }, 0 }, | |
3462 | { "tzmsk", { { OP_LWP_E, 0 }, Edq }, 0 }, | |
3463 | { "blcic", { { OP_LWP_E, 0 }, Edq }, 0 }, | |
3464 | { "blsic", { { OP_LWP_E, 0 }, Edq }, 0 }, | |
3465 | { "t1mskc", { { OP_LWP_E, 0 }, Edq }, 0 }, | |
2a2a0f38 QN |
3466 | }, |
3467 | /* REG_XOP_TBM_02 */ | |
3468 | { | |
3469 | { Bad_Opcode }, | |
c1dc7af5 | 3470 | { "blcmsk", { { OP_LWP_E, 0 }, Edq }, 0 }, |
2a2a0f38 QN |
3471 | { Bad_Opcode }, |
3472 | { Bad_Opcode }, | |
3473 | { Bad_Opcode }, | |
3474 | { Bad_Opcode }, | |
c1dc7af5 | 3475 | { "blci", { { OP_LWP_E, 0 }, Edq }, 0 }, |
2a2a0f38 | 3476 | }, |
ad692897 L |
3477 | |
3478 | #include "i386-dis-evex-reg.h" | |
4e7d34a6 L |
3479 | }; |
3480 | ||
1ceb70f8 L |
3481 | static const struct dis386 prefix_table[][4] = { |
3482 | /* PREFIX_90 */ | |
252b5132 | 3483 | { |
bf890a93 IT |
3484 | { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 }, |
3485 | { "pause", { XX }, 0 }, | |
3486 | { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 }, | |
507bd325 | 3487 | { NULL, { { NULL, 0 } }, PREFIX_IGNORED } |
0f10071e | 3488 | }, |
4e7d34a6 | 3489 | |
f9630fa6 | 3490 | /* PREFIX_0F01_REG_3_RM_1 */ |
a847e322 JB |
3491 | { |
3492 | { "vmmcall", { Skip_MODRM }, 0 }, | |
3493 | { "vmgexit", { Skip_MODRM }, 0 }, | |
d27c357a JB |
3494 | { Bad_Opcode }, |
3495 | { "vmgexit", { Skip_MODRM }, 0 }, | |
a847e322 JB |
3496 | }, |
3497 | ||
f8687e93 | 3498 | /* PREFIX_0F01_REG_5_MOD_0 */ |
603555e5 L |
3499 | { |
3500 | { Bad_Opcode }, | |
3501 | { "rstorssp", { Mq }, PREFIX_OPCODE }, | |
3502 | }, | |
3503 | ||
f8687e93 | 3504 | /* PREFIX_0F01_REG_5_MOD_3_RM_0 */ |
603555e5 | 3505 | { |
4b27d27c | 3506 | { "serialize", { Skip_MODRM }, PREFIX_OPCODE }, |
2234eee6 | 3507 | { "setssbsy", { Skip_MODRM }, PREFIX_OPCODE }, |
bb651e8b | 3508 | { Bad_Opcode }, |
efe30057 | 3509 | { "xsusldtrk", { Skip_MODRM }, PREFIX_OPCODE }, |
bb651e8b CL |
3510 | }, |
3511 | ||
3512 | /* PREFIX_0F01_REG_5_MOD_3_RM_1 */ | |
3513 | { | |
3514 | { Bad_Opcode }, | |
3515 | { Bad_Opcode }, | |
3516 | { Bad_Opcode }, | |
3517 | { "xresldtrk", { Skip_MODRM }, PREFIX_OPCODE }, | |
603555e5 L |
3518 | }, |
3519 | ||
f8687e93 | 3520 | /* PREFIX_0F01_REG_5_MOD_3_RM_2 */ |
603555e5 L |
3521 | { |
3522 | { Bad_Opcode }, | |
c2f76402 | 3523 | { "saveprevssp", { Skip_MODRM }, PREFIX_OPCODE }, |
603555e5 L |
3524 | }, |
3525 | ||
267b8516 JB |
3526 | /* PREFIX_0F01_REG_7_MOD_3_RM_2 */ |
3527 | { | |
3528 | { "monitorx", { { OP_Monitor, 0 } }, 0 }, | |
142861df | 3529 | { "mcommit", { Skip_MODRM }, 0 }, |
267b8516 JB |
3530 | }, |
3531 | ||
3532 | /* PREFIX_0F01_REG_7_MOD_3_RM_3 */ | |
3533 | { | |
7abb8d81 | 3534 | { "mwaitx", { { OP_Mwait, eBX_reg } }, 0 }, |
267b8516 JB |
3535 | }, |
3536 | ||
3233d7d0 IT |
3537 | /* PREFIX_0F09 */ |
3538 | { | |
3539 | { "wbinvd", { XX }, 0 }, | |
3540 | { "wbnoinvd", { XX }, 0 }, | |
3541 | }, | |
3542 | ||
1ceb70f8 | 3543 | /* PREFIX_0F10 */ |
cc0ec051 | 3544 | { |
507bd325 L |
3545 | { "movups", { XM, EXx }, PREFIX_OPCODE }, |
3546 | { "movss", { XM, EXd }, PREFIX_OPCODE }, | |
3547 | { "movupd", { XM, EXx }, PREFIX_OPCODE }, | |
3548 | { "movsd", { XM, EXq }, PREFIX_OPCODE }, | |
30d1c836 | 3549 | }, |
4e7d34a6 | 3550 | |
1ceb70f8 | 3551 | /* PREFIX_0F11 */ |
30d1c836 | 3552 | { |
507bd325 L |
3553 | { "movups", { EXxS, XM }, PREFIX_OPCODE }, |
3554 | { "movss", { EXdS, XM }, PREFIX_OPCODE }, | |
3555 | { "movupd", { EXxS, XM }, PREFIX_OPCODE }, | |
3556 | { "movsd", { EXqS, XM }, PREFIX_OPCODE }, | |
4e7d34a6 | 3557 | }, |
252b5132 | 3558 | |
1ceb70f8 | 3559 | /* PREFIX_0F12 */ |
c608c12e | 3560 | { |
1ceb70f8 | 3561 | { MOD_TABLE (MOD_0F12_PREFIX_0) }, |
507bd325 | 3562 | { "movsldup", { XM, EXx }, PREFIX_OPCODE }, |
18897deb | 3563 | { MOD_TABLE (MOD_0F12_PREFIX_2) }, |
507bd325 | 3564 | { "movddup", { XM, EXq }, PREFIX_OPCODE }, |
c608c12e | 3565 | }, |
4e7d34a6 | 3566 | |
1ceb70f8 | 3567 | /* PREFIX_0F16 */ |
c608c12e | 3568 | { |
1ceb70f8 | 3569 | { MOD_TABLE (MOD_0F16_PREFIX_0) }, |
507bd325 | 3570 | { "movshdup", { XM, EXx }, PREFIX_OPCODE }, |
18897deb | 3571 | { MOD_TABLE (MOD_0F16_PREFIX_2) }, |
c608c12e | 3572 | }, |
4e7d34a6 | 3573 | |
7e8b059b L |
3574 | /* PREFIX_0F1A */ |
3575 | { | |
3576 | { MOD_TABLE (MOD_0F1A_PREFIX_0) }, | |
bf890a93 IT |
3577 | { "bndcl", { Gbnd, Ev_bnd }, 0 }, |
3578 | { "bndmov", { Gbnd, Ebnd }, 0 }, | |
3579 | { "bndcu", { Gbnd, Ev_bnd }, 0 }, | |
7e8b059b L |
3580 | }, |
3581 | ||
3582 | /* PREFIX_0F1B */ | |
3583 | { | |
3584 | { MOD_TABLE (MOD_0F1B_PREFIX_0) }, | |
3585 | { MOD_TABLE (MOD_0F1B_PREFIX_1) }, | |
9f79e886 | 3586 | { "bndmov", { EbndS, Gbnd }, 0 }, |
bf890a93 | 3587 | { "bndcn", { Gbnd, Ev_bnd }, 0 }, |
7e8b059b L |
3588 | }, |
3589 | ||
c48935d7 IT |
3590 | /* PREFIX_0F1C */ |
3591 | { | |
3592 | { MOD_TABLE (MOD_0F1C_PREFIX_0) }, | |
3593 | { "nopQ", { Ev }, PREFIX_OPCODE }, | |
3594 | { "nopQ", { Ev }, PREFIX_OPCODE }, | |
3595 | { "nopQ", { Ev }, PREFIX_OPCODE }, | |
3596 | }, | |
3597 | ||
603555e5 L |
3598 | /* PREFIX_0F1E */ |
3599 | { | |
3600 | { "nopQ", { Ev }, PREFIX_OPCODE }, | |
3601 | { MOD_TABLE (MOD_0F1E_PREFIX_1) }, | |
3602 | { "nopQ", { Ev }, PREFIX_OPCODE }, | |
3603 | { "nopQ", { Ev }, PREFIX_OPCODE }, | |
3604 | }, | |
3605 | ||
1ceb70f8 | 3606 | /* PREFIX_0F2A */ |
c608c12e | 3607 | { |
507bd325 | 3608 | { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE }, |
e1a1babd | 3609 | { "cvtsi2ss%LQ", { XM, Edq }, PREFIX_OPCODE }, |
507bd325 | 3610 | { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE }, |
e1a1babd | 3611 | { "cvtsi2sd%LQ", { XM, Edq }, 0 }, |
c608c12e | 3612 | }, |
4e7d34a6 | 3613 | |
1ceb70f8 | 3614 | /* PREFIX_0F2B */ |
c608c12e | 3615 | { |
75c135a8 L |
3616 | { MOD_TABLE (MOD_0F2B_PREFIX_0) }, |
3617 | { MOD_TABLE (MOD_0F2B_PREFIX_1) }, | |
3618 | { MOD_TABLE (MOD_0F2B_PREFIX_2) }, | |
3619 | { MOD_TABLE (MOD_0F2B_PREFIX_3) }, | |
c608c12e | 3620 | }, |
4e7d34a6 | 3621 | |
1ceb70f8 | 3622 | /* PREFIX_0F2C */ |
c608c12e | 3623 | { |
507bd325 | 3624 | { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE }, |
e1a1babd | 3625 | { "cvttss2si", { Gdq, EXd }, PREFIX_OPCODE }, |
507bd325 | 3626 | { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE }, |
e1a1babd | 3627 | { "cvttsd2si", { Gdq, EXq }, PREFIX_OPCODE }, |
c608c12e | 3628 | }, |
4e7d34a6 | 3629 | |
1ceb70f8 | 3630 | /* PREFIX_0F2D */ |
c608c12e | 3631 | { |
507bd325 | 3632 | { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE }, |
e1a1babd | 3633 | { "cvtss2si", { Gdq, EXd }, PREFIX_OPCODE }, |
507bd325 | 3634 | { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE }, |
e1a1babd | 3635 | { "cvtsd2si", { Gdq, EXq }, PREFIX_OPCODE }, |
c608c12e | 3636 | }, |
4e7d34a6 | 3637 | |
1ceb70f8 | 3638 | /* PREFIX_0F2E */ |
c608c12e | 3639 | { |
bf890a93 | 3640 | { "ucomiss",{ XM, EXd }, 0 }, |
592d1631 | 3641 | { Bad_Opcode }, |
bf890a93 | 3642 | { "ucomisd",{ XM, EXq }, 0 }, |
c608c12e | 3643 | }, |
4e7d34a6 | 3644 | |
1ceb70f8 | 3645 | /* PREFIX_0F2F */ |
c608c12e | 3646 | { |
bf890a93 | 3647 | { "comiss", { XM, EXd }, 0 }, |
592d1631 | 3648 | { Bad_Opcode }, |
bf890a93 | 3649 | { "comisd", { XM, EXq }, 0 }, |
c608c12e | 3650 | }, |
4e7d34a6 | 3651 | |
1ceb70f8 | 3652 | /* PREFIX_0F51 */ |
c608c12e | 3653 | { |
507bd325 L |
3654 | { "sqrtps", { XM, EXx }, PREFIX_OPCODE }, |
3655 | { "sqrtss", { XM, EXd }, PREFIX_OPCODE }, | |
3656 | { "sqrtpd", { XM, EXx }, PREFIX_OPCODE }, | |
3657 | { "sqrtsd", { XM, EXq }, PREFIX_OPCODE }, | |
c608c12e | 3658 | }, |
4e7d34a6 | 3659 | |
1ceb70f8 | 3660 | /* PREFIX_0F52 */ |
c608c12e | 3661 | { |
507bd325 L |
3662 | { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE }, |
3663 | { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE }, | |
c608c12e | 3664 | }, |
4e7d34a6 | 3665 | |
1ceb70f8 | 3666 | /* PREFIX_0F53 */ |
c608c12e | 3667 | { |
507bd325 L |
3668 | { "rcpps", { XM, EXx }, PREFIX_OPCODE }, |
3669 | { "rcpss", { XM, EXd }, PREFIX_OPCODE }, | |
c608c12e | 3670 | }, |
4e7d34a6 | 3671 | |
1ceb70f8 | 3672 | /* PREFIX_0F58 */ |
c608c12e | 3673 | { |
507bd325 L |
3674 | { "addps", { XM, EXx }, PREFIX_OPCODE }, |
3675 | { "addss", { XM, EXd }, PREFIX_OPCODE }, | |
3676 | { "addpd", { XM, EXx }, PREFIX_OPCODE }, | |
3677 | { "addsd", { XM, EXq }, PREFIX_OPCODE }, | |
c608c12e | 3678 | }, |
4e7d34a6 | 3679 | |
1ceb70f8 | 3680 | /* PREFIX_0F59 */ |
c608c12e | 3681 | { |
507bd325 L |
3682 | { "mulps", { XM, EXx }, PREFIX_OPCODE }, |
3683 | { "mulss", { XM, EXd }, PREFIX_OPCODE }, | |
3684 | { "mulpd", { XM, EXx }, PREFIX_OPCODE }, | |
3685 | { "mulsd", { XM, EXq }, PREFIX_OPCODE }, | |
041bd2e0 | 3686 | }, |
4e7d34a6 | 3687 | |
1ceb70f8 | 3688 | /* PREFIX_0F5A */ |
041bd2e0 | 3689 | { |
507bd325 L |
3690 | { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE }, |
3691 | { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE }, | |
3692 | { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE }, | |
3693 | { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE }, | |
041bd2e0 | 3694 | }, |
4e7d34a6 | 3695 | |
1ceb70f8 | 3696 | /* PREFIX_0F5B */ |
041bd2e0 | 3697 | { |
507bd325 L |
3698 | { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE }, |
3699 | { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE }, | |
3700 | { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE }, | |
041bd2e0 | 3701 | }, |
4e7d34a6 | 3702 | |
1ceb70f8 | 3703 | /* PREFIX_0F5C */ |
041bd2e0 | 3704 | { |
507bd325 L |
3705 | { "subps", { XM, EXx }, PREFIX_OPCODE }, |
3706 | { "subss", { XM, EXd }, PREFIX_OPCODE }, | |
3707 | { "subpd", { XM, EXx }, PREFIX_OPCODE }, | |
3708 | { "subsd", { XM, EXq }, PREFIX_OPCODE }, | |
041bd2e0 | 3709 | }, |
4e7d34a6 | 3710 | |
1ceb70f8 | 3711 | /* PREFIX_0F5D */ |
041bd2e0 | 3712 | { |
507bd325 L |
3713 | { "minps", { XM, EXx }, PREFIX_OPCODE }, |
3714 | { "minss", { XM, EXd }, PREFIX_OPCODE }, | |
3715 | { "minpd", { XM, EXx }, PREFIX_OPCODE }, | |
3716 | { "minsd", { XM, EXq }, PREFIX_OPCODE }, | |
041bd2e0 | 3717 | }, |
4e7d34a6 | 3718 | |
1ceb70f8 | 3719 | /* PREFIX_0F5E */ |
041bd2e0 | 3720 | { |
507bd325 L |
3721 | { "divps", { XM, EXx }, PREFIX_OPCODE }, |
3722 | { "divss", { XM, EXd }, PREFIX_OPCODE }, | |
3723 | { "divpd", { XM, EXx }, PREFIX_OPCODE }, | |
3724 | { "divsd", { XM, EXq }, PREFIX_OPCODE }, | |
041bd2e0 | 3725 | }, |
4e7d34a6 | 3726 | |
1ceb70f8 | 3727 | /* PREFIX_0F5F */ |
041bd2e0 | 3728 | { |
507bd325 L |
3729 | { "maxps", { XM, EXx }, PREFIX_OPCODE }, |
3730 | { "maxss", { XM, EXd }, PREFIX_OPCODE }, | |
3731 | { "maxpd", { XM, EXx }, PREFIX_OPCODE }, | |
3732 | { "maxsd", { XM, EXq }, PREFIX_OPCODE }, | |
041bd2e0 | 3733 | }, |
4e7d34a6 | 3734 | |
1ceb70f8 | 3735 | /* PREFIX_0F60 */ |
041bd2e0 | 3736 | { |
507bd325 | 3737 | { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE }, |
592d1631 | 3738 | { Bad_Opcode }, |
507bd325 | 3739 | { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE }, |
041bd2e0 | 3740 | }, |
4e7d34a6 | 3741 | |
1ceb70f8 | 3742 | /* PREFIX_0F61 */ |
041bd2e0 | 3743 | { |
507bd325 | 3744 | { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE }, |
592d1631 | 3745 | { Bad_Opcode }, |
507bd325 | 3746 | { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE }, |
041bd2e0 | 3747 | }, |
4e7d34a6 | 3748 | |
1ceb70f8 | 3749 | /* PREFIX_0F62 */ |
041bd2e0 | 3750 | { |
507bd325 | 3751 | { "punpckldq",{ MX, EMd }, PREFIX_OPCODE }, |
592d1631 | 3752 | { Bad_Opcode }, |
507bd325 | 3753 | { "punpckldq",{ MX, EMx }, PREFIX_OPCODE }, |
041bd2e0 | 3754 | }, |
4e7d34a6 | 3755 | |
1ceb70f8 | 3756 | /* PREFIX_0F6C */ |
041bd2e0 | 3757 | { |
592d1631 L |
3758 | { Bad_Opcode }, |
3759 | { Bad_Opcode }, | |
507bd325 | 3760 | { "punpcklqdq", { XM, EXx }, PREFIX_OPCODE }, |
0f17484f | 3761 | }, |
4e7d34a6 | 3762 | |
1ceb70f8 | 3763 | /* PREFIX_0F6D */ |
0f17484f | 3764 | { |
592d1631 L |
3765 | { Bad_Opcode }, |
3766 | { Bad_Opcode }, | |
507bd325 | 3767 | { "punpckhqdq", { XM, EXx }, PREFIX_OPCODE }, |
041bd2e0 | 3768 | }, |
4e7d34a6 | 3769 | |
1ceb70f8 | 3770 | /* PREFIX_0F6F */ |
ca164297 | 3771 | { |
507bd325 L |
3772 | { "movq", { MX, EM }, PREFIX_OPCODE }, |
3773 | { "movdqu", { XM, EXx }, PREFIX_OPCODE }, | |
3774 | { "movdqa", { XM, EXx }, PREFIX_OPCODE }, | |
ca164297 | 3775 | }, |
4e7d34a6 | 3776 | |
1ceb70f8 | 3777 | /* PREFIX_0F70 */ |
4e7d34a6 | 3778 | { |
507bd325 L |
3779 | { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE }, |
3780 | { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE }, | |
3781 | { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE }, | |
3782 | { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE }, | |
4e7d34a6 L |
3783 | }, |
3784 | ||
92fddf8e L |
3785 | /* PREFIX_0F73_REG_3 */ |
3786 | { | |
592d1631 L |
3787 | { Bad_Opcode }, |
3788 | { Bad_Opcode }, | |
bf890a93 | 3789 | { "psrldq", { XS, Ib }, 0 }, |
92fddf8e L |
3790 | }, |
3791 | ||
3792 | /* PREFIX_0F73_REG_7 */ | |
3793 | { | |
592d1631 L |
3794 | { Bad_Opcode }, |
3795 | { Bad_Opcode }, | |
bf890a93 | 3796 | { "pslldq", { XS, Ib }, 0 }, |
92fddf8e L |
3797 | }, |
3798 | ||
1ceb70f8 | 3799 | /* PREFIX_0F78 */ |
4e7d34a6 | 3800 | { |
bf890a93 | 3801 | {"vmread", { Em, Gm }, 0 }, |
592d1631 | 3802 | { Bad_Opcode }, |
bf890a93 IT |
3803 | {"extrq", { XS, Ib, Ib }, 0 }, |
3804 | {"insertq", { XM, XS, Ib, Ib }, 0 }, | |
4e7d34a6 L |
3805 | }, |
3806 | ||
1ceb70f8 | 3807 | /* PREFIX_0F79 */ |
4e7d34a6 | 3808 | { |
bf890a93 | 3809 | {"vmwrite", { Gm, Em }, 0 }, |
592d1631 | 3810 | { Bad_Opcode }, |
bf890a93 IT |
3811 | {"extrq", { XM, XS }, 0 }, |
3812 | {"insertq", { XM, XS }, 0 }, | |
4e7d34a6 L |
3813 | }, |
3814 | ||
1ceb70f8 | 3815 | /* PREFIX_0F7C */ |
ca164297 | 3816 | { |
592d1631 L |
3817 | { Bad_Opcode }, |
3818 | { Bad_Opcode }, | |
507bd325 L |
3819 | { "haddpd", { XM, EXx }, PREFIX_OPCODE }, |
3820 | { "haddps", { XM, EXx }, PREFIX_OPCODE }, | |
ca164297 | 3821 | }, |
4e7d34a6 | 3822 | |
1ceb70f8 | 3823 | /* PREFIX_0F7D */ |
ca164297 | 3824 | { |
592d1631 L |
3825 | { Bad_Opcode }, |
3826 | { Bad_Opcode }, | |
507bd325 L |
3827 | { "hsubpd", { XM, EXx }, PREFIX_OPCODE }, |
3828 | { "hsubps", { XM, EXx }, PREFIX_OPCODE }, | |
ca164297 | 3829 | }, |
4e7d34a6 | 3830 | |
1ceb70f8 | 3831 | /* PREFIX_0F7E */ |
ca164297 | 3832 | { |
507bd325 L |
3833 | { "movK", { Edq, MX }, PREFIX_OPCODE }, |
3834 | { "movq", { XM, EXq }, PREFIX_OPCODE }, | |
3835 | { "movK", { Edq, XM }, PREFIX_OPCODE }, | |
ca164297 | 3836 | }, |
4e7d34a6 | 3837 | |
1ceb70f8 | 3838 | /* PREFIX_0F7F */ |
ca164297 | 3839 | { |
507bd325 L |
3840 | { "movq", { EMS, MX }, PREFIX_OPCODE }, |
3841 | { "movdqu", { EXxS, XM }, PREFIX_OPCODE }, | |
3842 | { "movdqa", { EXxS, XM }, PREFIX_OPCODE }, | |
ca164297 | 3843 | }, |
4e7d34a6 | 3844 | |
f8687e93 | 3845 | /* PREFIX_0FAE_REG_0_MOD_3 */ |
c7b8aa3a L |
3846 | { |
3847 | { Bad_Opcode }, | |
bf890a93 | 3848 | { "rdfsbase", { Ev }, 0 }, |
c7b8aa3a L |
3849 | }, |
3850 | ||
f8687e93 | 3851 | /* PREFIX_0FAE_REG_1_MOD_3 */ |
c7b8aa3a L |
3852 | { |
3853 | { Bad_Opcode }, | |
bf890a93 | 3854 | { "rdgsbase", { Ev }, 0 }, |
c7b8aa3a L |
3855 | }, |
3856 | ||
f8687e93 | 3857 | /* PREFIX_0FAE_REG_2_MOD_3 */ |
c7b8aa3a L |
3858 | { |
3859 | { Bad_Opcode }, | |
bf890a93 | 3860 | { "wrfsbase", { Ev }, 0 }, |
c7b8aa3a L |
3861 | }, |
3862 | ||
f8687e93 | 3863 | /* PREFIX_0FAE_REG_3_MOD_3 */ |
c7b8aa3a L |
3864 | { |
3865 | { Bad_Opcode }, | |
bf890a93 | 3866 | { "wrgsbase", { Ev }, 0 }, |
c7b8aa3a L |
3867 | }, |
3868 | ||
f8687e93 | 3869 | /* PREFIX_0FAE_REG_4_MOD_0 */ |
6b40c462 L |
3870 | { |
3871 | { "xsave", { FXSAVE }, 0 }, | |
3872 | { "ptwrite%LQ", { Edq }, 0 }, | |
3873 | }, | |
3874 | ||
f8687e93 | 3875 | /* PREFIX_0FAE_REG_4_MOD_3 */ |
6b40c462 L |
3876 | { |
3877 | { Bad_Opcode }, | |
3878 | { "ptwrite%LQ", { Edq }, 0 }, | |
3879 | }, | |
3880 | ||
f8687e93 | 3881 | /* PREFIX_0FAE_REG_5_MOD_0 */ |
603555e5 L |
3882 | { |
3883 | { "xrstor", { FXSAVE }, PREFIX_OPCODE }, | |
2234eee6 L |
3884 | }, |
3885 | ||
f8687e93 | 3886 | /* PREFIX_0FAE_REG_5_MOD_3 */ |
2234eee6 L |
3887 | { |
3888 | { "lfence", { Skip_MODRM }, 0 }, | |
3889 | { "incsspK", { Rdq }, PREFIX_OPCODE }, | |
603555e5 L |
3890 | }, |
3891 | ||
f8687e93 | 3892 | /* PREFIX_0FAE_REG_6_MOD_0 */ |
c5e7287a | 3893 | { |
603555e5 L |
3894 | { "xsaveopt", { FXSAVE }, PREFIX_OPCODE }, |
3895 | { "clrssbsy", { Mq }, PREFIX_OPCODE }, | |
3896 | { "clwb", { Mb }, PREFIX_OPCODE }, | |
c5e7287a IT |
3897 | }, |
3898 | ||
f8687e93 | 3899 | /* PREFIX_0FAE_REG_6_MOD_3 */ |
de89d0a3 | 3900 | { |
f8687e93 | 3901 | { RM_TABLE (RM_0FAE_REG_6_MOD_3_P_0) }, |
de89d0a3 | 3902 | { "umonitor", { Eva }, PREFIX_OPCODE }, |
ae1d3843 L |
3903 | { "tpause", { Edq }, PREFIX_OPCODE }, |
3904 | { "umwait", { Edq }, PREFIX_OPCODE }, | |
de89d0a3 IT |
3905 | }, |
3906 | ||
f8687e93 | 3907 | /* PREFIX_0FAE_REG_7_MOD_0 */ |
963f3586 | 3908 | { |
bf890a93 | 3909 | { "clflush", { Mb }, 0 }, |
963f3586 | 3910 | { Bad_Opcode }, |
bf890a93 | 3911 | { "clflushopt", { Mb }, 0 }, |
963f3586 IT |
3912 | }, |
3913 | ||
1ceb70f8 | 3914 | /* PREFIX_0FB8 */ |
ca164297 | 3915 | { |
592d1631 | 3916 | { Bad_Opcode }, |
bf890a93 | 3917 | { "popcntS", { Gv, Ev }, 0 }, |
ca164297 | 3918 | }, |
4e7d34a6 | 3919 | |
f12dc422 L |
3920 | /* PREFIX_0FBC */ |
3921 | { | |
bf890a93 IT |
3922 | { "bsfS", { Gv, Ev }, 0 }, |
3923 | { "tzcntS", { Gv, Ev }, 0 }, | |
3924 | { "bsfS", { Gv, Ev }, 0 }, | |
f12dc422 L |
3925 | }, |
3926 | ||
1ceb70f8 | 3927 | /* PREFIX_0FBD */ |
050dfa73 | 3928 | { |
bf890a93 IT |
3929 | { "bsrS", { Gv, Ev }, 0 }, |
3930 | { "lzcntS", { Gv, Ev }, 0 }, | |
3931 | { "bsrS", { Gv, Ev }, 0 }, | |
050dfa73 MM |
3932 | }, |
3933 | ||
1ceb70f8 | 3934 | /* PREFIX_0FC2 */ |
050dfa73 | 3935 | { |
507bd325 L |
3936 | { "cmpps", { XM, EXx, CMP }, PREFIX_OPCODE }, |
3937 | { "cmpss", { XM, EXd, CMP }, PREFIX_OPCODE }, | |
3938 | { "cmppd", { XM, EXx, CMP }, PREFIX_OPCODE }, | |
3939 | { "cmpsd", { XM, EXq, CMP }, PREFIX_OPCODE }, | |
050dfa73 | 3940 | }, |
246c51aa | 3941 | |
f8687e93 | 3942 | /* PREFIX_0FC3_MOD_0 */ |
4ee52178 | 3943 | { |
e1a1babd | 3944 | { "movntiS", { Edq, Gdq }, PREFIX_OPCODE }, |
4ee52178 L |
3945 | }, |
3946 | ||
f8687e93 | 3947 | /* PREFIX_0FC7_REG_6_MOD_0 */ |
92fddf8e | 3948 | { |
bf890a93 IT |
3949 | { "vmptrld",{ Mq }, 0 }, |
3950 | { "vmxon", { Mq }, 0 }, | |
3951 | { "vmclear",{ Mq }, 0 }, | |
92fddf8e L |
3952 | }, |
3953 | ||
f8687e93 | 3954 | /* PREFIX_0FC7_REG_6_MOD_3 */ |
f24bcbaa L |
3955 | { |
3956 | { "rdrand", { Ev }, 0 }, | |
3957 | { Bad_Opcode }, | |
3958 | { "rdrand", { Ev }, 0 } | |
3959 | }, | |
3960 | ||
f8687e93 | 3961 | /* PREFIX_0FC7_REG_7_MOD_3 */ |
f24bcbaa L |
3962 | { |
3963 | { "rdseed", { Ev }, 0 }, | |
8bc52696 | 3964 | { "rdpid", { Em }, 0 }, |
f24bcbaa L |
3965 | { "rdseed", { Ev }, 0 }, |
3966 | }, | |
3967 | ||
1ceb70f8 | 3968 | /* PREFIX_0FD0 */ |
050dfa73 | 3969 | { |
592d1631 L |
3970 | { Bad_Opcode }, |
3971 | { Bad_Opcode }, | |
bf890a93 IT |
3972 | { "addsubpd", { XM, EXx }, 0 }, |
3973 | { "addsubps", { XM, EXx }, 0 }, | |
246c51aa | 3974 | }, |
050dfa73 | 3975 | |
1ceb70f8 | 3976 | /* PREFIX_0FD6 */ |
050dfa73 | 3977 | { |
592d1631 | 3978 | { Bad_Opcode }, |
bf890a93 IT |
3979 | { "movq2dq",{ XM, MS }, 0 }, |
3980 | { "movq", { EXqS, XM }, 0 }, | |
3981 | { "movdq2q",{ MX, XS }, 0 }, | |
050dfa73 MM |
3982 | }, |
3983 | ||
1ceb70f8 | 3984 | /* PREFIX_0FE6 */ |
7918206c | 3985 | { |
592d1631 | 3986 | { Bad_Opcode }, |
507bd325 L |
3987 | { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE }, |
3988 | { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE }, | |
3989 | { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE }, | |
7918206c | 3990 | }, |
8b38ad71 | 3991 | |
1ceb70f8 | 3992 | /* PREFIX_0FE7 */ |
8b38ad71 | 3993 | { |
507bd325 | 3994 | { "movntq", { Mq, MX }, PREFIX_OPCODE }, |
592d1631 | 3995 | { Bad_Opcode }, |
75c135a8 | 3996 | { MOD_TABLE (MOD_0FE7_PREFIX_2) }, |
4e7d34a6 L |
3997 | }, |
3998 | ||
1ceb70f8 | 3999 | /* PREFIX_0FF0 */ |
4e7d34a6 | 4000 | { |
592d1631 L |
4001 | { Bad_Opcode }, |
4002 | { Bad_Opcode }, | |
4003 | { Bad_Opcode }, | |
1ceb70f8 | 4004 | { MOD_TABLE (MOD_0FF0_PREFIX_3) }, |
4e7d34a6 L |
4005 | }, |
4006 | ||
1ceb70f8 | 4007 | /* PREFIX_0FF7 */ |
4e7d34a6 | 4008 | { |
507bd325 | 4009 | { "maskmovq", { MX, MS }, PREFIX_OPCODE }, |
592d1631 | 4010 | { Bad_Opcode }, |
507bd325 | 4011 | { "maskmovdqu", { XM, XS }, PREFIX_OPCODE }, |
8b38ad71 | 4012 | }, |
42903f7f | 4013 | |
1ceb70f8 | 4014 | /* PREFIX_0F3810 */ |
42903f7f | 4015 | { |
592d1631 L |
4016 | { Bad_Opcode }, |
4017 | { Bad_Opcode }, | |
507bd325 | 4018 | { "pblendvb", { XM, EXx, XMM0 }, PREFIX_OPCODE }, |
42903f7f L |
4019 | }, |
4020 | ||
1ceb70f8 | 4021 | /* PREFIX_0F3814 */ |
42903f7f | 4022 | { |
592d1631 L |
4023 | { Bad_Opcode }, |
4024 | { Bad_Opcode }, | |
507bd325 | 4025 | { "blendvps", { XM, EXx, XMM0 }, PREFIX_OPCODE }, |
42903f7f L |
4026 | }, |
4027 | ||
1ceb70f8 | 4028 | /* PREFIX_0F3815 */ |
42903f7f | 4029 | { |
592d1631 L |
4030 | { Bad_Opcode }, |
4031 | { Bad_Opcode }, | |
507bd325 | 4032 | { "blendvpd", { XM, EXx, XMM0 }, PREFIX_OPCODE }, |
42903f7f L |
4033 | }, |
4034 | ||
1ceb70f8 | 4035 | /* PREFIX_0F3817 */ |
42903f7f | 4036 | { |
592d1631 L |
4037 | { Bad_Opcode }, |
4038 | { Bad_Opcode }, | |
507bd325 | 4039 | { "ptest", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4040 | }, |
4041 | ||
1ceb70f8 | 4042 | /* PREFIX_0F3820 */ |
42903f7f | 4043 | { |
592d1631 L |
4044 | { Bad_Opcode }, |
4045 | { Bad_Opcode }, | |
507bd325 | 4046 | { "pmovsxbw", { XM, EXq }, PREFIX_OPCODE }, |
42903f7f L |
4047 | }, |
4048 | ||
1ceb70f8 | 4049 | /* PREFIX_0F3821 */ |
42903f7f | 4050 | { |
592d1631 L |
4051 | { Bad_Opcode }, |
4052 | { Bad_Opcode }, | |
507bd325 | 4053 | { "pmovsxbd", { XM, EXd }, PREFIX_OPCODE }, |
42903f7f L |
4054 | }, |
4055 | ||
1ceb70f8 | 4056 | /* PREFIX_0F3822 */ |
42903f7f | 4057 | { |
592d1631 L |
4058 | { Bad_Opcode }, |
4059 | { Bad_Opcode }, | |
507bd325 | 4060 | { "pmovsxbq", { XM, EXw }, PREFIX_OPCODE }, |
42903f7f L |
4061 | }, |
4062 | ||
1ceb70f8 | 4063 | /* PREFIX_0F3823 */ |
42903f7f | 4064 | { |
592d1631 L |
4065 | { Bad_Opcode }, |
4066 | { Bad_Opcode }, | |
507bd325 | 4067 | { "pmovsxwd", { XM, EXq }, PREFIX_OPCODE }, |
42903f7f L |
4068 | }, |
4069 | ||
1ceb70f8 | 4070 | /* PREFIX_0F3824 */ |
42903f7f | 4071 | { |
592d1631 L |
4072 | { Bad_Opcode }, |
4073 | { Bad_Opcode }, | |
507bd325 | 4074 | { "pmovsxwq", { XM, EXd }, PREFIX_OPCODE }, |
42903f7f L |
4075 | }, |
4076 | ||
1ceb70f8 | 4077 | /* PREFIX_0F3825 */ |
42903f7f | 4078 | { |
592d1631 L |
4079 | { Bad_Opcode }, |
4080 | { Bad_Opcode }, | |
507bd325 | 4081 | { "pmovsxdq", { XM, EXq }, PREFIX_OPCODE }, |
42903f7f L |
4082 | }, |
4083 | ||
1ceb70f8 | 4084 | /* PREFIX_0F3828 */ |
42903f7f | 4085 | { |
592d1631 L |
4086 | { Bad_Opcode }, |
4087 | { Bad_Opcode }, | |
507bd325 | 4088 | { "pmuldq", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4089 | }, |
4090 | ||
1ceb70f8 | 4091 | /* PREFIX_0F3829 */ |
42903f7f | 4092 | { |
592d1631 L |
4093 | { Bad_Opcode }, |
4094 | { Bad_Opcode }, | |
507bd325 | 4095 | { "pcmpeqq", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4096 | }, |
4097 | ||
1ceb70f8 | 4098 | /* PREFIX_0F382A */ |
42903f7f | 4099 | { |
592d1631 L |
4100 | { Bad_Opcode }, |
4101 | { Bad_Opcode }, | |
75c135a8 | 4102 | { MOD_TABLE (MOD_0F382A_PREFIX_2) }, |
42903f7f L |
4103 | }, |
4104 | ||
1ceb70f8 | 4105 | /* PREFIX_0F382B */ |
42903f7f | 4106 | { |
592d1631 L |
4107 | { Bad_Opcode }, |
4108 | { Bad_Opcode }, | |
507bd325 | 4109 | { "packusdw", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4110 | }, |
4111 | ||
1ceb70f8 | 4112 | /* PREFIX_0F3830 */ |
42903f7f | 4113 | { |
592d1631 L |
4114 | { Bad_Opcode }, |
4115 | { Bad_Opcode }, | |
507bd325 | 4116 | { "pmovzxbw", { XM, EXq }, PREFIX_OPCODE }, |
42903f7f L |
4117 | }, |
4118 | ||
1ceb70f8 | 4119 | /* PREFIX_0F3831 */ |
42903f7f | 4120 | { |
592d1631 L |
4121 | { Bad_Opcode }, |
4122 | { Bad_Opcode }, | |
507bd325 | 4123 | { "pmovzxbd", { XM, EXd }, PREFIX_OPCODE }, |
42903f7f L |
4124 | }, |
4125 | ||
1ceb70f8 | 4126 | /* PREFIX_0F3832 */ |
42903f7f | 4127 | { |
592d1631 L |
4128 | { Bad_Opcode }, |
4129 | { Bad_Opcode }, | |
507bd325 | 4130 | { "pmovzxbq", { XM, EXw }, PREFIX_OPCODE }, |
42903f7f L |
4131 | }, |
4132 | ||
1ceb70f8 | 4133 | /* PREFIX_0F3833 */ |
42903f7f | 4134 | { |
592d1631 L |
4135 | { Bad_Opcode }, |
4136 | { Bad_Opcode }, | |
507bd325 | 4137 | { "pmovzxwd", { XM, EXq }, PREFIX_OPCODE }, |
42903f7f L |
4138 | }, |
4139 | ||
1ceb70f8 | 4140 | /* PREFIX_0F3834 */ |
42903f7f | 4141 | { |
592d1631 L |
4142 | { Bad_Opcode }, |
4143 | { Bad_Opcode }, | |
507bd325 | 4144 | { "pmovzxwq", { XM, EXd }, PREFIX_OPCODE }, |
42903f7f L |
4145 | }, |
4146 | ||
1ceb70f8 | 4147 | /* PREFIX_0F3835 */ |
42903f7f | 4148 | { |
592d1631 L |
4149 | { Bad_Opcode }, |
4150 | { Bad_Opcode }, | |
507bd325 | 4151 | { "pmovzxdq", { XM, EXq }, PREFIX_OPCODE }, |
42903f7f L |
4152 | }, |
4153 | ||
1ceb70f8 | 4154 | /* PREFIX_0F3837 */ |
4e7d34a6 | 4155 | { |
592d1631 L |
4156 | { Bad_Opcode }, |
4157 | { Bad_Opcode }, | |
507bd325 | 4158 | { "pcmpgtq", { XM, EXx }, PREFIX_OPCODE }, |
4e7d34a6 L |
4159 | }, |
4160 | ||
1ceb70f8 | 4161 | /* PREFIX_0F3838 */ |
42903f7f | 4162 | { |
592d1631 L |
4163 | { Bad_Opcode }, |
4164 | { Bad_Opcode }, | |
507bd325 | 4165 | { "pminsb", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4166 | }, |
4167 | ||
1ceb70f8 | 4168 | /* PREFIX_0F3839 */ |
42903f7f | 4169 | { |
592d1631 L |
4170 | { Bad_Opcode }, |
4171 | { Bad_Opcode }, | |
507bd325 | 4172 | { "pminsd", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4173 | }, |
4174 | ||
1ceb70f8 | 4175 | /* PREFIX_0F383A */ |
42903f7f | 4176 | { |
592d1631 L |
4177 | { Bad_Opcode }, |
4178 | { Bad_Opcode }, | |
507bd325 | 4179 | { "pminuw", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4180 | }, |
4181 | ||
1ceb70f8 | 4182 | /* PREFIX_0F383B */ |
42903f7f | 4183 | { |
592d1631 L |
4184 | { Bad_Opcode }, |
4185 | { Bad_Opcode }, | |
507bd325 | 4186 | { "pminud", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4187 | }, |
4188 | ||
1ceb70f8 | 4189 | /* PREFIX_0F383C */ |
42903f7f | 4190 | { |
592d1631 L |
4191 | { Bad_Opcode }, |
4192 | { Bad_Opcode }, | |
507bd325 | 4193 | { "pmaxsb", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4194 | }, |
4195 | ||
1ceb70f8 | 4196 | /* PREFIX_0F383D */ |
42903f7f | 4197 | { |
592d1631 L |
4198 | { Bad_Opcode }, |
4199 | { Bad_Opcode }, | |
507bd325 | 4200 | { "pmaxsd", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4201 | }, |
4202 | ||
1ceb70f8 | 4203 | /* PREFIX_0F383E */ |
42903f7f | 4204 | { |
592d1631 L |
4205 | { Bad_Opcode }, |
4206 | { Bad_Opcode }, | |
507bd325 | 4207 | { "pmaxuw", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4208 | }, |
4209 | ||
1ceb70f8 | 4210 | /* PREFIX_0F383F */ |
42903f7f | 4211 | { |
592d1631 L |
4212 | { Bad_Opcode }, |
4213 | { Bad_Opcode }, | |
507bd325 | 4214 | { "pmaxud", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4215 | }, |
4216 | ||
1ceb70f8 | 4217 | /* PREFIX_0F3840 */ |
42903f7f | 4218 | { |
592d1631 L |
4219 | { Bad_Opcode }, |
4220 | { Bad_Opcode }, | |
507bd325 | 4221 | { "pmulld", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4222 | }, |
4223 | ||
1ceb70f8 | 4224 | /* PREFIX_0F3841 */ |
42903f7f | 4225 | { |
592d1631 L |
4226 | { Bad_Opcode }, |
4227 | { Bad_Opcode }, | |
507bd325 | 4228 | { "phminposuw", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4229 | }, |
4230 | ||
f1f8f695 L |
4231 | /* PREFIX_0F3880 */ |
4232 | { | |
592d1631 L |
4233 | { Bad_Opcode }, |
4234 | { Bad_Opcode }, | |
507bd325 | 4235 | { "invept", { Gm, Mo }, PREFIX_OPCODE }, |
f1f8f695 L |
4236 | }, |
4237 | ||
4238 | /* PREFIX_0F3881 */ | |
4239 | { | |
592d1631 L |
4240 | { Bad_Opcode }, |
4241 | { Bad_Opcode }, | |
507bd325 | 4242 | { "invvpid", { Gm, Mo }, PREFIX_OPCODE }, |
f1f8f695 L |
4243 | }, |
4244 | ||
6c30d220 L |
4245 | /* PREFIX_0F3882 */ |
4246 | { | |
4247 | { Bad_Opcode }, | |
4248 | { Bad_Opcode }, | |
507bd325 | 4249 | { "invpcid", { Gm, M }, PREFIX_OPCODE }, |
6c30d220 L |
4250 | }, |
4251 | ||
a0046408 L |
4252 | /* PREFIX_0F38C8 */ |
4253 | { | |
507bd325 | 4254 | { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE }, |
a0046408 L |
4255 | }, |
4256 | ||
4257 | /* PREFIX_0F38C9 */ | |
4258 | { | |
507bd325 | 4259 | { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE }, |
a0046408 L |
4260 | }, |
4261 | ||
4262 | /* PREFIX_0F38CA */ | |
4263 | { | |
507bd325 | 4264 | { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE }, |
a0046408 L |
4265 | }, |
4266 | ||
4267 | /* PREFIX_0F38CB */ | |
4268 | { | |
507bd325 | 4269 | { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE }, |
a0046408 L |
4270 | }, |
4271 | ||
4272 | /* PREFIX_0F38CC */ | |
4273 | { | |
507bd325 | 4274 | { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE }, |
a0046408 L |
4275 | }, |
4276 | ||
4277 | /* PREFIX_0F38CD */ | |
4278 | { | |
507bd325 | 4279 | { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE }, |
a0046408 L |
4280 | }, |
4281 | ||
48521003 IT |
4282 | /* PREFIX_0F38CF */ |
4283 | { | |
4284 | { Bad_Opcode }, | |
4285 | { Bad_Opcode }, | |
4286 | { "gf2p8mulb", { XM, EXxmm }, PREFIX_OPCODE }, | |
4287 | }, | |
4288 | ||
c0f3af97 L |
4289 | /* PREFIX_0F38DB */ |
4290 | { | |
592d1631 L |
4291 | { Bad_Opcode }, |
4292 | { Bad_Opcode }, | |
507bd325 | 4293 | { "aesimc", { XM, EXx }, PREFIX_OPCODE }, |
c0f3af97 L |
4294 | }, |
4295 | ||
4296 | /* PREFIX_0F38DC */ | |
4297 | { | |
592d1631 L |
4298 | { Bad_Opcode }, |
4299 | { Bad_Opcode }, | |
507bd325 | 4300 | { "aesenc", { XM, EXx }, PREFIX_OPCODE }, |
c0f3af97 L |
4301 | }, |
4302 | ||
4303 | /* PREFIX_0F38DD */ | |
4304 | { | |
592d1631 L |
4305 | { Bad_Opcode }, |
4306 | { Bad_Opcode }, | |
507bd325 | 4307 | { "aesenclast", { XM, EXx }, PREFIX_OPCODE }, |
c0f3af97 L |
4308 | }, |
4309 | ||
4310 | /* PREFIX_0F38DE */ | |
4311 | { | |
592d1631 L |
4312 | { Bad_Opcode }, |
4313 | { Bad_Opcode }, | |
507bd325 | 4314 | { "aesdec", { XM, EXx }, PREFIX_OPCODE }, |
c0f3af97 L |
4315 | }, |
4316 | ||
4317 | /* PREFIX_0F38DF */ | |
4318 | { | |
592d1631 L |
4319 | { Bad_Opcode }, |
4320 | { Bad_Opcode }, | |
507bd325 | 4321 | { "aesdeclast", { XM, EXx }, PREFIX_OPCODE }, |
c0f3af97 L |
4322 | }, |
4323 | ||
1ceb70f8 | 4324 | /* PREFIX_0F38F0 */ |
4e7d34a6 | 4325 | { |
507bd325 | 4326 | { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE }, |
592d1631 | 4327 | { Bad_Opcode }, |
507bd325 L |
4328 | { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE }, |
4329 | { "crc32", { Gdq, { CRC32_Fixup, b_mode } }, PREFIX_OPCODE }, | |
4e7d34a6 L |
4330 | }, |
4331 | ||
1ceb70f8 | 4332 | /* PREFIX_0F38F1 */ |
4e7d34a6 | 4333 | { |
507bd325 | 4334 | { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE }, |
592d1631 | 4335 | { Bad_Opcode }, |
507bd325 L |
4336 | { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE }, |
4337 | { "crc32", { Gdq, { CRC32_Fixup, v_mode } }, PREFIX_OPCODE }, | |
4e7d34a6 L |
4338 | }, |
4339 | ||
603555e5 | 4340 | /* PREFIX_0F38F5 */ |
e2e1fcde L |
4341 | { |
4342 | { Bad_Opcode }, | |
603555e5 L |
4343 | { Bad_Opcode }, |
4344 | { MOD_TABLE (MOD_0F38F5_PREFIX_2) }, | |
4345 | }, | |
4346 | ||
4347 | /* PREFIX_0F38F6 */ | |
4348 | { | |
4349 | { MOD_TABLE (MOD_0F38F6_PREFIX_0) }, | |
507bd325 L |
4350 | { "adoxS", { Gdq, Edq}, PREFIX_OPCODE }, |
4351 | { "adcxS", { Gdq, Edq}, PREFIX_OPCODE }, | |
e2e1fcde L |
4352 | { Bad_Opcode }, |
4353 | }, | |
4354 | ||
c0a30a9f L |
4355 | /* PREFIX_0F38F8 */ |
4356 | { | |
4357 | { Bad_Opcode }, | |
5d79adc4 | 4358 | { MOD_TABLE (MOD_0F38F8_PREFIX_1) }, |
c0a30a9f | 4359 | { MOD_TABLE (MOD_0F38F8_PREFIX_2) }, |
5d79adc4 | 4360 | { MOD_TABLE (MOD_0F38F8_PREFIX_3) }, |
c0a30a9f L |
4361 | }, |
4362 | ||
4363 | /* PREFIX_0F38F9 */ | |
4364 | { | |
4365 | { MOD_TABLE (MOD_0F38F9_PREFIX_0) }, | |
4366 | }, | |
4367 | ||
1ceb70f8 | 4368 | /* PREFIX_0F3A08 */ |
42903f7f | 4369 | { |
592d1631 L |
4370 | { Bad_Opcode }, |
4371 | { Bad_Opcode }, | |
507bd325 | 4372 | { "roundps", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4373 | }, |
4374 | ||
1ceb70f8 | 4375 | /* PREFIX_0F3A09 */ |
42903f7f | 4376 | { |
592d1631 L |
4377 | { Bad_Opcode }, |
4378 | { Bad_Opcode }, | |
507bd325 | 4379 | { "roundpd", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4380 | }, |
4381 | ||
1ceb70f8 | 4382 | /* PREFIX_0F3A0A */ |
42903f7f | 4383 | { |
592d1631 L |
4384 | { Bad_Opcode }, |
4385 | { Bad_Opcode }, | |
507bd325 | 4386 | { "roundss", { XM, EXd, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4387 | }, |
4388 | ||
1ceb70f8 | 4389 | /* PREFIX_0F3A0B */ |
42903f7f | 4390 | { |
592d1631 L |
4391 | { Bad_Opcode }, |
4392 | { Bad_Opcode }, | |
507bd325 | 4393 | { "roundsd", { XM, EXq, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4394 | }, |
4395 | ||
1ceb70f8 | 4396 | /* PREFIX_0F3A0C */ |
42903f7f | 4397 | { |
592d1631 L |
4398 | { Bad_Opcode }, |
4399 | { Bad_Opcode }, | |
507bd325 | 4400 | { "blendps", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4401 | }, |
4402 | ||
1ceb70f8 | 4403 | /* PREFIX_0F3A0D */ |
42903f7f | 4404 | { |
592d1631 L |
4405 | { Bad_Opcode }, |
4406 | { Bad_Opcode }, | |
507bd325 | 4407 | { "blendpd", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4408 | }, |
4409 | ||
1ceb70f8 | 4410 | /* PREFIX_0F3A0E */ |
42903f7f | 4411 | { |
592d1631 L |
4412 | { Bad_Opcode }, |
4413 | { Bad_Opcode }, | |
507bd325 | 4414 | { "pblendw", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4415 | }, |
4416 | ||
1ceb70f8 | 4417 | /* PREFIX_0F3A14 */ |
42903f7f | 4418 | { |
592d1631 L |
4419 | { Bad_Opcode }, |
4420 | { Bad_Opcode }, | |
507bd325 | 4421 | { "pextrb", { Edqb, XM, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4422 | }, |
4423 | ||
1ceb70f8 | 4424 | /* PREFIX_0F3A15 */ |
42903f7f | 4425 | { |
592d1631 L |
4426 | { Bad_Opcode }, |
4427 | { Bad_Opcode }, | |
507bd325 | 4428 | { "pextrw", { Edqw, XM, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4429 | }, |
4430 | ||
1ceb70f8 | 4431 | /* PREFIX_0F3A16 */ |
42903f7f | 4432 | { |
592d1631 L |
4433 | { Bad_Opcode }, |
4434 | { Bad_Opcode }, | |
507bd325 | 4435 | { "pextrK", { Edq, XM, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4436 | }, |
4437 | ||
1ceb70f8 | 4438 | /* PREFIX_0F3A17 */ |
42903f7f | 4439 | { |
592d1631 L |
4440 | { Bad_Opcode }, |
4441 | { Bad_Opcode }, | |
507bd325 | 4442 | { "extractps", { Edqd, XM, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4443 | }, |
4444 | ||
1ceb70f8 | 4445 | /* PREFIX_0F3A20 */ |
42903f7f | 4446 | { |
592d1631 L |
4447 | { Bad_Opcode }, |
4448 | { Bad_Opcode }, | |
507bd325 | 4449 | { "pinsrb", { XM, Edqb, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4450 | }, |
4451 | ||
1ceb70f8 | 4452 | /* PREFIX_0F3A21 */ |
42903f7f | 4453 | { |
592d1631 L |
4454 | { Bad_Opcode }, |
4455 | { Bad_Opcode }, | |
507bd325 | 4456 | { "insertps", { XM, EXd, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4457 | }, |
4458 | ||
1ceb70f8 | 4459 | /* PREFIX_0F3A22 */ |
42903f7f | 4460 | { |
592d1631 L |
4461 | { Bad_Opcode }, |
4462 | { Bad_Opcode }, | |
507bd325 | 4463 | { "pinsrK", { XM, Edq, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4464 | }, |
4465 | ||
1ceb70f8 | 4466 | /* PREFIX_0F3A40 */ |
42903f7f | 4467 | { |
592d1631 L |
4468 | { Bad_Opcode }, |
4469 | { Bad_Opcode }, | |
507bd325 | 4470 | { "dpps", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4471 | }, |
4472 | ||
1ceb70f8 | 4473 | /* PREFIX_0F3A41 */ |
42903f7f | 4474 | { |
592d1631 L |
4475 | { Bad_Opcode }, |
4476 | { Bad_Opcode }, | |
507bd325 | 4477 | { "dppd", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4478 | }, |
4479 | ||
1ceb70f8 | 4480 | /* PREFIX_0F3A42 */ |
42903f7f | 4481 | { |
592d1631 L |
4482 | { Bad_Opcode }, |
4483 | { Bad_Opcode }, | |
507bd325 | 4484 | { "mpsadbw", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f | 4485 | }, |
381d071f | 4486 | |
c0f3af97 L |
4487 | /* PREFIX_0F3A44 */ |
4488 | { | |
592d1631 L |
4489 | { Bad_Opcode }, |
4490 | { Bad_Opcode }, | |
507bd325 | 4491 | { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_OPCODE }, |
c0f3af97 L |
4492 | }, |
4493 | ||
1ceb70f8 | 4494 | /* PREFIX_0F3A60 */ |
381d071f | 4495 | { |
592d1631 L |
4496 | { Bad_Opcode }, |
4497 | { Bad_Opcode }, | |
15c7c1d8 | 4498 | { "pcmpestrm", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE }, |
381d071f L |
4499 | }, |
4500 | ||
1ceb70f8 | 4501 | /* PREFIX_0F3A61 */ |
381d071f | 4502 | { |
592d1631 L |
4503 | { Bad_Opcode }, |
4504 | { Bad_Opcode }, | |
15c7c1d8 | 4505 | { "pcmpestri", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE }, |
381d071f L |
4506 | }, |
4507 | ||
1ceb70f8 | 4508 | /* PREFIX_0F3A62 */ |
381d071f | 4509 | { |
592d1631 L |
4510 | { Bad_Opcode }, |
4511 | { Bad_Opcode }, | |
507bd325 | 4512 | { "pcmpistrm", { XM, EXx, Ib }, PREFIX_OPCODE }, |
381d071f L |
4513 | }, |
4514 | ||
1ceb70f8 | 4515 | /* PREFIX_0F3A63 */ |
381d071f | 4516 | { |
592d1631 L |
4517 | { Bad_Opcode }, |
4518 | { Bad_Opcode }, | |
507bd325 | 4519 | { "pcmpistri", { XM, EXx, Ib }, PREFIX_OPCODE }, |
381d071f | 4520 | }, |
09a2c6cf | 4521 | |
a0046408 L |
4522 | /* PREFIX_0F3ACC */ |
4523 | { | |
507bd325 | 4524 | { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE }, |
a0046408 L |
4525 | }, |
4526 | ||
48521003 IT |
4527 | /* PREFIX_0F3ACE */ |
4528 | { | |
4529 | { Bad_Opcode }, | |
4530 | { Bad_Opcode }, | |
4531 | { "gf2p8affineqb", { XM, EXxmm, Ib }, PREFIX_OPCODE }, | |
4532 | }, | |
4533 | ||
4534 | /* PREFIX_0F3ACF */ | |
4535 | { | |
4536 | { Bad_Opcode }, | |
4537 | { Bad_Opcode }, | |
4538 | { "gf2p8affineinvqb", { XM, EXxmm, Ib }, PREFIX_OPCODE }, | |
4539 | }, | |
4540 | ||
c0f3af97 | 4541 | /* PREFIX_0F3ADF */ |
09a2c6cf | 4542 | { |
592d1631 L |
4543 | { Bad_Opcode }, |
4544 | { Bad_Opcode }, | |
507bd325 | 4545 | { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_OPCODE }, |
09a2c6cf L |
4546 | }, |
4547 | ||
592a252b | 4548 | /* PREFIX_VEX_0F10 */ |
09a2c6cf | 4549 | { |
ec6f095a | 4550 | { "vmovups", { XM, EXx }, 0 }, |
5b872f7d | 4551 | { "vmovss", { XMVexScalar, VexScalar, EXxmm_md }, 0 }, |
ec6f095a | 4552 | { "vmovupd", { XM, EXx }, 0 }, |
5b872f7d | 4553 | { "vmovsd", { XMVexScalar, VexScalar, EXxmm_mq }, 0 }, |
09a2c6cf L |
4554 | }, |
4555 | ||
592a252b | 4556 | /* PREFIX_VEX_0F11 */ |
09a2c6cf | 4557 | { |
ec6f095a L |
4558 | { "vmovups", { EXxS, XM }, 0 }, |
4559 | { "vmovss", { EXdVexScalarS, VexScalar, XMScalar }, 0 }, | |
4560 | { "vmovupd", { EXxS, XM }, 0 }, | |
4561 | { "vmovsd", { EXqVexScalarS, VexScalar, XMScalar }, 0 }, | |
09a2c6cf L |
4562 | }, |
4563 | ||
592a252b | 4564 | /* PREFIX_VEX_0F12 */ |
09a2c6cf | 4565 | { |
592a252b | 4566 | { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) }, |
ec6f095a | 4567 | { "vmovsldup", { XM, EXx }, 0 }, |
18897deb | 4568 | { MOD_TABLE (MOD_VEX_0F12_PREFIX_2) }, |
ec6f095a | 4569 | { "vmovddup", { XM, EXymmq }, 0 }, |
09a2c6cf L |
4570 | }, |
4571 | ||
592a252b | 4572 | /* PREFIX_VEX_0F16 */ |
09a2c6cf | 4573 | { |
592a252b | 4574 | { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) }, |
ec6f095a | 4575 | { "vmovshdup", { XM, EXx }, 0 }, |
18897deb | 4576 | { MOD_TABLE (MOD_VEX_0F16_PREFIX_2) }, |
5f754f58 | 4577 | }, |
7c52e0e8 | 4578 | |
592a252b | 4579 | /* PREFIX_VEX_0F2A */ |
5f754f58 | 4580 | { |
592d1631 | 4581 | { Bad_Opcode }, |
2b7bcc87 | 4582 | { "vcvtsi2ss%LQ", { XMScalar, VexScalar, Edq }, 0 }, |
592d1631 | 4583 | { Bad_Opcode }, |
2b7bcc87 | 4584 | { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Edq }, 0 }, |
5f754f58 | 4585 | }, |
7c52e0e8 | 4586 | |
592a252b | 4587 | /* PREFIX_VEX_0F2C */ |
5f754f58 | 4588 | { |
592d1631 | 4589 | { Bad_Opcode }, |
5b872f7d | 4590 | { "vcvttss2si", { Gdq, EXxmm_md }, 0 }, |
592d1631 | 4591 | { Bad_Opcode }, |
5b872f7d | 4592 | { "vcvttsd2si", { Gdq, EXxmm_mq }, 0 }, |
5f754f58 | 4593 | }, |
7c52e0e8 | 4594 | |
592a252b | 4595 | /* PREFIX_VEX_0F2D */ |
7c52e0e8 | 4596 | { |
592d1631 | 4597 | { Bad_Opcode }, |
5b872f7d | 4598 | { "vcvtss2si", { Gdq, EXxmm_md }, 0 }, |
592d1631 | 4599 | { Bad_Opcode }, |
5b872f7d | 4600 | { "vcvtsd2si", { Gdq, EXxmm_mq }, 0 }, |
7c52e0e8 L |
4601 | }, |
4602 | ||
592a252b | 4603 | /* PREFIX_VEX_0F2E */ |
7c52e0e8 | 4604 | { |
5b872f7d | 4605 | { "vucomiss", { XMScalar, EXxmm_md }, 0 }, |
592d1631 | 4606 | { Bad_Opcode }, |
5b872f7d | 4607 | { "vucomisd", { XMScalar, EXxmm_mq }, 0 }, |
7c52e0e8 L |
4608 | }, |
4609 | ||
592a252b | 4610 | /* PREFIX_VEX_0F2F */ |
7c52e0e8 | 4611 | { |
5b872f7d | 4612 | { "vcomiss", { XMScalar, EXxmm_md }, 0 }, |
592d1631 | 4613 | { Bad_Opcode }, |
5b872f7d | 4614 | { "vcomisd", { XMScalar, EXxmm_mq }, 0 }, |
7c52e0e8 L |
4615 | }, |
4616 | ||
43234a1e L |
4617 | /* PREFIX_VEX_0F41 */ |
4618 | { | |
4619 | { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) }, | |
1ba585e8 IT |
4620 | { Bad_Opcode }, |
4621 | { VEX_LEN_TABLE (VEX_LEN_0F41_P_2) }, | |
43234a1e L |
4622 | }, |
4623 | ||
4624 | /* PREFIX_VEX_0F42 */ | |
4625 | { | |
4626 | { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) }, | |
1ba585e8 IT |
4627 | { Bad_Opcode }, |
4628 | { VEX_LEN_TABLE (VEX_LEN_0F42_P_2) }, | |
43234a1e L |
4629 | }, |
4630 | ||
4631 | /* PREFIX_VEX_0F44 */ | |
4632 | { | |
4633 | { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) }, | |
1ba585e8 IT |
4634 | { Bad_Opcode }, |
4635 | { VEX_LEN_TABLE (VEX_LEN_0F44_P_2) }, | |
43234a1e L |
4636 | }, |
4637 | ||
4638 | /* PREFIX_VEX_0F45 */ | |
4639 | { | |
4640 | { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) }, | |
1ba585e8 IT |
4641 | { Bad_Opcode }, |
4642 | { VEX_LEN_TABLE (VEX_LEN_0F45_P_2) }, | |
43234a1e L |
4643 | }, |
4644 | ||
4645 | /* PREFIX_VEX_0F46 */ | |
4646 | { | |
4647 | { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) }, | |
1ba585e8 IT |
4648 | { Bad_Opcode }, |
4649 | { VEX_LEN_TABLE (VEX_LEN_0F46_P_2) }, | |
43234a1e L |
4650 | }, |
4651 | ||
4652 | /* PREFIX_VEX_0F47 */ | |
4653 | { | |
4654 | { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) }, | |
1ba585e8 IT |
4655 | { Bad_Opcode }, |
4656 | { VEX_LEN_TABLE (VEX_LEN_0F47_P_2) }, | |
43234a1e L |
4657 | }, |
4658 | ||
1ba585e8 | 4659 | /* PREFIX_VEX_0F4A */ |
43234a1e | 4660 | { |
1ba585e8 | 4661 | { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0) }, |
43234a1e | 4662 | { Bad_Opcode }, |
1ba585e8 IT |
4663 | { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2) }, |
4664 | }, | |
4665 | ||
4666 | /* PREFIX_VEX_0F4B */ | |
4667 | { | |
4668 | { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0) }, | |
43234a1e L |
4669 | { Bad_Opcode }, |
4670 | { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) }, | |
4671 | }, | |
4672 | ||
592a252b | 4673 | /* PREFIX_VEX_0F51 */ |
7c52e0e8 | 4674 | { |
ec6f095a | 4675 | { "vsqrtps", { XM, EXx }, 0 }, |
5b872f7d | 4676 | { "vsqrtss", { XMScalar, VexScalar, EXxmm_md }, 0 }, |
ec6f095a | 4677 | { "vsqrtpd", { XM, EXx }, 0 }, |
5b872f7d | 4678 | { "vsqrtsd", { XMScalar, VexScalar, EXxmm_mq }, 0 }, |
7c52e0e8 L |
4679 | }, |
4680 | ||
592a252b | 4681 | /* PREFIX_VEX_0F52 */ |
7c52e0e8 | 4682 | { |
ec6f095a | 4683 | { "vrsqrtps", { XM, EXx }, 0 }, |
5b872f7d | 4684 | { "vrsqrtss", { XMScalar, VexScalar, EXxmm_md }, 0 }, |
7c52e0e8 L |
4685 | }, |
4686 | ||
592a252b | 4687 | /* PREFIX_VEX_0F53 */ |
7c52e0e8 | 4688 | { |
ec6f095a | 4689 | { "vrcpps", { XM, EXx }, 0 }, |
5b872f7d | 4690 | { "vrcpss", { XMScalar, VexScalar, EXxmm_md }, 0 }, |
7c52e0e8 L |
4691 | }, |
4692 | ||
592a252b | 4693 | /* PREFIX_VEX_0F58 */ |
7c52e0e8 | 4694 | { |
ec6f095a | 4695 | { "vaddps", { XM, Vex, EXx }, 0 }, |
5b872f7d | 4696 | { "vaddss", { XMScalar, VexScalar, EXxmm_md }, 0 }, |
ec6f095a | 4697 | { "vaddpd", { XM, Vex, EXx }, 0 }, |
5b872f7d | 4698 | { "vaddsd", { XMScalar, VexScalar, EXxmm_mq }, 0 }, |
7c52e0e8 L |
4699 | }, |
4700 | ||
592a252b | 4701 | /* PREFIX_VEX_0F59 */ |
7c52e0e8 | 4702 | { |
ec6f095a | 4703 | { "vmulps", { XM, Vex, EXx }, 0 }, |
5b872f7d | 4704 | { "vmulss", { XMScalar, VexScalar, EXxmm_md }, 0 }, |
ec6f095a | 4705 | { "vmulpd", { XM, Vex, EXx }, 0 }, |
5b872f7d | 4706 | { "vmulsd", { XMScalar, VexScalar, EXxmm_mq }, 0 }, |
7c52e0e8 L |
4707 | }, |
4708 | ||
592a252b | 4709 | /* PREFIX_VEX_0F5A */ |
7c52e0e8 | 4710 | { |
ec6f095a | 4711 | { "vcvtps2pd", { XM, EXxmmq }, 0 }, |
5b872f7d | 4712 | { "vcvtss2sd", { XMScalar, VexScalar, EXxmm_md }, 0 }, |
ec6f095a | 4713 | { "vcvtpd2ps%XY",{ XMM, EXx }, 0 }, |
5b872f7d | 4714 | { "vcvtsd2ss", { XMScalar, VexScalar, EXxmm_mq }, 0 }, |
7c52e0e8 L |
4715 | }, |
4716 | ||
592a252b | 4717 | /* PREFIX_VEX_0F5B */ |
7c52e0e8 | 4718 | { |
ec6f095a L |
4719 | { "vcvtdq2ps", { XM, EXx }, 0 }, |
4720 | { "vcvttps2dq", { XM, EXx }, 0 }, | |
4721 | { "vcvtps2dq", { XM, EXx }, 0 }, | |
7c52e0e8 L |
4722 | }, |
4723 | ||
592a252b | 4724 | /* PREFIX_VEX_0F5C */ |
7c52e0e8 | 4725 | { |
ec6f095a | 4726 | { "vsubps", { XM, Vex, EXx }, 0 }, |
5b872f7d | 4727 | { "vsubss", { XMScalar, VexScalar, EXxmm_md }, 0 }, |
ec6f095a | 4728 | { "vsubpd", { XM, Vex, EXx }, 0 }, |
5b872f7d | 4729 | { "vsubsd", { XMScalar, VexScalar, EXxmm_mq }, 0 }, |
7c52e0e8 L |
4730 | }, |
4731 | ||
592a252b | 4732 | /* PREFIX_VEX_0F5D */ |
7c52e0e8 | 4733 | { |
ec6f095a | 4734 | { "vminps", { XM, Vex, EXx }, 0 }, |
5b872f7d | 4735 | { "vminss", { XMScalar, VexScalar, EXxmm_md }, 0 }, |
ec6f095a | 4736 | { "vminpd", { XM, Vex, EXx }, 0 }, |
5b872f7d | 4737 | { "vminsd", { XMScalar, VexScalar, EXxmm_mq }, 0 }, |
7c52e0e8 L |
4738 | }, |
4739 | ||
592a252b | 4740 | /* PREFIX_VEX_0F5E */ |
7c52e0e8 | 4741 | { |
ec6f095a | 4742 | { "vdivps", { XM, Vex, EXx }, 0 }, |
5b872f7d | 4743 | { "vdivss", { XMScalar, VexScalar, EXxmm_md }, 0 }, |
ec6f095a | 4744 | { "vdivpd", { XM, Vex, EXx }, 0 }, |
5b872f7d | 4745 | { "vdivsd", { XMScalar, VexScalar, EXxmm_mq }, 0 }, |
7c52e0e8 L |
4746 | }, |
4747 | ||
592a252b | 4748 | /* PREFIX_VEX_0F5F */ |
7c52e0e8 | 4749 | { |
ec6f095a | 4750 | { "vmaxps", { XM, Vex, EXx }, 0 }, |
5b872f7d | 4751 | { "vmaxss", { XMScalar, VexScalar, EXxmm_md }, 0 }, |
ec6f095a | 4752 | { "vmaxpd", { XM, Vex, EXx }, 0 }, |
5b872f7d | 4753 | { "vmaxsd", { XMScalar, VexScalar, EXxmm_mq }, 0 }, |
7c52e0e8 L |
4754 | }, |
4755 | ||
592a252b | 4756 | /* PREFIX_VEX_0F60 */ |
7c52e0e8 | 4757 | { |
592d1631 L |
4758 | { Bad_Opcode }, |
4759 | { Bad_Opcode }, | |
ec6f095a | 4760 | { "vpunpcklbw", { XM, Vex, EXx }, 0 }, |
7c52e0e8 L |
4761 | }, |
4762 | ||
592a252b | 4763 | /* PREFIX_VEX_0F61 */ |
7c52e0e8 | 4764 | { |
592d1631 L |
4765 | { Bad_Opcode }, |
4766 | { Bad_Opcode }, | |
ec6f095a | 4767 | { "vpunpcklwd", { XM, Vex, EXx }, 0 }, |
7c52e0e8 L |
4768 | }, |
4769 | ||
592a252b | 4770 | /* PREFIX_VEX_0F62 */ |
7c52e0e8 | 4771 | { |
592d1631 L |
4772 | { Bad_Opcode }, |
4773 | { Bad_Opcode }, | |
ec6f095a | 4774 | { "vpunpckldq", { XM, Vex, EXx }, 0 }, |
7c52e0e8 L |
4775 | }, |
4776 | ||
592a252b | 4777 | /* PREFIX_VEX_0F63 */ |
7c52e0e8 | 4778 | { |
592d1631 L |
4779 | { Bad_Opcode }, |
4780 | { Bad_Opcode }, | |
ec6f095a | 4781 | { "vpacksswb", { XM, Vex, EXx }, 0 }, |
7c52e0e8 L |
4782 | }, |
4783 | ||
592a252b | 4784 | /* PREFIX_VEX_0F64 */ |
7c52e0e8 | 4785 | { |
592d1631 L |
4786 | { Bad_Opcode }, |
4787 | { Bad_Opcode }, | |
ec6f095a | 4788 | { "vpcmpgtb", { XM, Vex, EXx }, 0 }, |
7c52e0e8 L |
4789 | }, |
4790 | ||
592a252b | 4791 | /* PREFIX_VEX_0F65 */ |
7c52e0e8 | 4792 | { |
592d1631 L |
4793 | { Bad_Opcode }, |
4794 | { Bad_Opcode }, | |
ec6f095a | 4795 | { "vpcmpgtw", { XM, Vex, EXx }, 0 }, |
7c52e0e8 L |
4796 | }, |
4797 | ||
592a252b | 4798 | /* PREFIX_VEX_0F66 */ |
7c52e0e8 | 4799 | { |
592d1631 L |
4800 | { Bad_Opcode }, |
4801 | { Bad_Opcode }, | |
ec6f095a | 4802 | { "vpcmpgtd", { XM, Vex, EXx }, 0 }, |
7c52e0e8 | 4803 | }, |
6439fc28 | 4804 | |
592a252b | 4805 | /* PREFIX_VEX_0F67 */ |
331d2d0d | 4806 | { |
592d1631 L |
4807 | { Bad_Opcode }, |
4808 | { Bad_Opcode }, | |
ec6f095a | 4809 | { "vpackuswb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
4810 | }, |
4811 | ||
592a252b | 4812 | /* PREFIX_VEX_0F68 */ |
c0f3af97 | 4813 | { |
592d1631 L |
4814 | { Bad_Opcode }, |
4815 | { Bad_Opcode }, | |
ec6f095a | 4816 | { "vpunpckhbw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
4817 | }, |
4818 | ||
592a252b | 4819 | /* PREFIX_VEX_0F69 */ |
c0f3af97 | 4820 | { |
592d1631 L |
4821 | { Bad_Opcode }, |
4822 | { Bad_Opcode }, | |
ec6f095a | 4823 | { "vpunpckhwd", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
4824 | }, |
4825 | ||
592a252b | 4826 | /* PREFIX_VEX_0F6A */ |
c0f3af97 | 4827 | { |
592d1631 L |
4828 | { Bad_Opcode }, |
4829 | { Bad_Opcode }, | |
ec6f095a | 4830 | { "vpunpckhdq", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
4831 | }, |
4832 | ||
592a252b | 4833 | /* PREFIX_VEX_0F6B */ |
c0f3af97 | 4834 | { |
592d1631 L |
4835 | { Bad_Opcode }, |
4836 | { Bad_Opcode }, | |
ec6f095a | 4837 | { "vpackssdw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
4838 | }, |
4839 | ||
592a252b | 4840 | /* PREFIX_VEX_0F6C */ |
c0f3af97 | 4841 | { |
592d1631 L |
4842 | { Bad_Opcode }, |
4843 | { Bad_Opcode }, | |
ec6f095a | 4844 | { "vpunpcklqdq", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
4845 | }, |
4846 | ||
592a252b | 4847 | /* PREFIX_VEX_0F6D */ |
c0f3af97 | 4848 | { |
592d1631 L |
4849 | { Bad_Opcode }, |
4850 | { Bad_Opcode }, | |
ec6f095a | 4851 | { "vpunpckhqdq", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
4852 | }, |
4853 | ||
592a252b | 4854 | /* PREFIX_VEX_0F6E */ |
c0f3af97 | 4855 | { |
592d1631 L |
4856 | { Bad_Opcode }, |
4857 | { Bad_Opcode }, | |
592a252b | 4858 | { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) }, |
c0f3af97 L |
4859 | }, |
4860 | ||
592a252b | 4861 | /* PREFIX_VEX_0F6F */ |
c0f3af97 | 4862 | { |
592d1631 | 4863 | { Bad_Opcode }, |
ec6f095a L |
4864 | { "vmovdqu", { XM, EXx }, 0 }, |
4865 | { "vmovdqa", { XM, EXx }, 0 }, | |
c0f3af97 L |
4866 | }, |
4867 | ||
592a252b | 4868 | /* PREFIX_VEX_0F70 */ |
c0f3af97 | 4869 | { |
592d1631 | 4870 | { Bad_Opcode }, |
ec6f095a L |
4871 | { "vpshufhw", { XM, EXx, Ib }, 0 }, |
4872 | { "vpshufd", { XM, EXx, Ib }, 0 }, | |
4873 | { "vpshuflw", { XM, EXx, Ib }, 0 }, | |
c0f3af97 L |
4874 | }, |
4875 | ||
592a252b | 4876 | /* PREFIX_VEX_0F71_REG_2 */ |
c0f3af97 | 4877 | { |
592d1631 L |
4878 | { Bad_Opcode }, |
4879 | { Bad_Opcode }, | |
ec6f095a | 4880 | { "vpsrlw", { Vex, XS, Ib }, 0 }, |
c0f3af97 L |
4881 | }, |
4882 | ||
592a252b | 4883 | /* PREFIX_VEX_0F71_REG_4 */ |
c0f3af97 | 4884 | { |
592d1631 L |
4885 | { Bad_Opcode }, |
4886 | { Bad_Opcode }, | |
ec6f095a | 4887 | { "vpsraw", { Vex, XS, Ib }, 0 }, |
c0f3af97 L |
4888 | }, |
4889 | ||
592a252b | 4890 | /* PREFIX_VEX_0F71_REG_6 */ |
c0f3af97 | 4891 | { |
592d1631 L |
4892 | { Bad_Opcode }, |
4893 | { Bad_Opcode }, | |
ec6f095a | 4894 | { "vpsllw", { Vex, XS, Ib }, 0 }, |
c0f3af97 L |
4895 | }, |
4896 | ||
592a252b | 4897 | /* PREFIX_VEX_0F72_REG_2 */ |
c0f3af97 | 4898 | { |
592d1631 L |
4899 | { Bad_Opcode }, |
4900 | { Bad_Opcode }, | |
ec6f095a | 4901 | { "vpsrld", { Vex, XS, Ib }, 0 }, |
c0f3af97 L |
4902 | }, |
4903 | ||
592a252b | 4904 | /* PREFIX_VEX_0F72_REG_4 */ |
c0f3af97 | 4905 | { |
592d1631 L |
4906 | { Bad_Opcode }, |
4907 | { Bad_Opcode }, | |
ec6f095a | 4908 | { "vpsrad", { Vex, XS, Ib }, 0 }, |
c0f3af97 L |
4909 | }, |
4910 | ||
592a252b | 4911 | /* PREFIX_VEX_0F72_REG_6 */ |
c0f3af97 | 4912 | { |
592d1631 L |
4913 | { Bad_Opcode }, |
4914 | { Bad_Opcode }, | |
ec6f095a | 4915 | { "vpslld", { Vex, XS, Ib }, 0 }, |
c0f3af97 L |
4916 | }, |
4917 | ||
592a252b | 4918 | /* PREFIX_VEX_0F73_REG_2 */ |
c0f3af97 | 4919 | { |
592d1631 L |
4920 | { Bad_Opcode }, |
4921 | { Bad_Opcode }, | |
ec6f095a | 4922 | { "vpsrlq", { Vex, XS, Ib }, 0 }, |
c0f3af97 L |
4923 | }, |
4924 | ||
592a252b | 4925 | /* PREFIX_VEX_0F73_REG_3 */ |
c0f3af97 | 4926 | { |
592d1631 L |
4927 | { Bad_Opcode }, |
4928 | { Bad_Opcode }, | |
ec6f095a | 4929 | { "vpsrldq", { Vex, XS, Ib }, 0 }, |
c0f3af97 L |
4930 | }, |
4931 | ||
592a252b | 4932 | /* PREFIX_VEX_0F73_REG_6 */ |
c0f3af97 | 4933 | { |
592d1631 L |
4934 | { Bad_Opcode }, |
4935 | { Bad_Opcode }, | |
ec6f095a | 4936 | { "vpsllq", { Vex, XS, Ib }, 0 }, |
c0f3af97 L |
4937 | }, |
4938 | ||
592a252b | 4939 | /* PREFIX_VEX_0F73_REG_7 */ |
c0f3af97 | 4940 | { |
592d1631 L |
4941 | { Bad_Opcode }, |
4942 | { Bad_Opcode }, | |
ec6f095a | 4943 | { "vpslldq", { Vex, XS, Ib }, 0 }, |
c0f3af97 L |
4944 | }, |
4945 | ||
592a252b | 4946 | /* PREFIX_VEX_0F74 */ |
c0f3af97 | 4947 | { |
592d1631 L |
4948 | { Bad_Opcode }, |
4949 | { Bad_Opcode }, | |
ec6f095a | 4950 | { "vpcmpeqb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
4951 | }, |
4952 | ||
592a252b | 4953 | /* PREFIX_VEX_0F75 */ |
c0f3af97 | 4954 | { |
592d1631 L |
4955 | { Bad_Opcode }, |
4956 | { Bad_Opcode }, | |
ec6f095a | 4957 | { "vpcmpeqw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
4958 | }, |
4959 | ||
592a252b | 4960 | /* PREFIX_VEX_0F76 */ |
c0f3af97 | 4961 | { |
592d1631 L |
4962 | { Bad_Opcode }, |
4963 | { Bad_Opcode }, | |
ec6f095a | 4964 | { "vpcmpeqd", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
4965 | }, |
4966 | ||
592a252b | 4967 | /* PREFIX_VEX_0F77 */ |
c0f3af97 | 4968 | { |
ec6f095a | 4969 | { VEX_LEN_TABLE (VEX_LEN_0F77_P_0) }, |
c0f3af97 L |
4970 | }, |
4971 | ||
592a252b | 4972 | /* PREFIX_VEX_0F7C */ |
c0f3af97 | 4973 | { |
592d1631 L |
4974 | { Bad_Opcode }, |
4975 | { Bad_Opcode }, | |
ec6f095a L |
4976 | { "vhaddpd", { XM, Vex, EXx }, 0 }, |
4977 | { "vhaddps", { XM, Vex, EXx }, 0 }, | |
c0f3af97 L |
4978 | }, |
4979 | ||
592a252b | 4980 | /* PREFIX_VEX_0F7D */ |
c0f3af97 | 4981 | { |
592d1631 L |
4982 | { Bad_Opcode }, |
4983 | { Bad_Opcode }, | |
ec6f095a L |
4984 | { "vhsubpd", { XM, Vex, EXx }, 0 }, |
4985 | { "vhsubps", { XM, Vex, EXx }, 0 }, | |
c0f3af97 L |
4986 | }, |
4987 | ||
592a252b | 4988 | /* PREFIX_VEX_0F7E */ |
c0f3af97 | 4989 | { |
592d1631 | 4990 | { Bad_Opcode }, |
592a252b L |
4991 | { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) }, |
4992 | { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) }, | |
c0f3af97 L |
4993 | }, |
4994 | ||
592a252b | 4995 | /* PREFIX_VEX_0F7F */ |
c0f3af97 | 4996 | { |
592d1631 | 4997 | { Bad_Opcode }, |
ec6f095a L |
4998 | { "vmovdqu", { EXxS, XM }, 0 }, |
4999 | { "vmovdqa", { EXxS, XM }, 0 }, | |
c0f3af97 L |
5000 | }, |
5001 | ||
43234a1e L |
5002 | /* PREFIX_VEX_0F90 */ |
5003 | { | |
5004 | { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) }, | |
1ba585e8 IT |
5005 | { Bad_Opcode }, |
5006 | { VEX_LEN_TABLE (VEX_LEN_0F90_P_2) }, | |
43234a1e L |
5007 | }, |
5008 | ||
5009 | /* PREFIX_VEX_0F91 */ | |
5010 | { | |
5011 | { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) }, | |
1ba585e8 IT |
5012 | { Bad_Opcode }, |
5013 | { VEX_LEN_TABLE (VEX_LEN_0F91_P_2) }, | |
43234a1e L |
5014 | }, |
5015 | ||
5016 | /* PREFIX_VEX_0F92 */ | |
5017 | { | |
5018 | { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) }, | |
1ba585e8 | 5019 | { Bad_Opcode }, |
90a915bf | 5020 | { VEX_LEN_TABLE (VEX_LEN_0F92_P_2) }, |
1ba585e8 | 5021 | { VEX_LEN_TABLE (VEX_LEN_0F92_P_3) }, |
43234a1e L |
5022 | }, |
5023 | ||
5024 | /* PREFIX_VEX_0F93 */ | |
5025 | { | |
5026 | { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) }, | |
1ba585e8 | 5027 | { Bad_Opcode }, |
90a915bf | 5028 | { VEX_LEN_TABLE (VEX_LEN_0F93_P_2) }, |
1ba585e8 | 5029 | { VEX_LEN_TABLE (VEX_LEN_0F93_P_3) }, |
43234a1e L |
5030 | }, |
5031 | ||
5032 | /* PREFIX_VEX_0F98 */ | |
5033 | { | |
5034 | { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) }, | |
1ba585e8 IT |
5035 | { Bad_Opcode }, |
5036 | { VEX_LEN_TABLE (VEX_LEN_0F98_P_2) }, | |
5037 | }, | |
5038 | ||
5039 | /* PREFIX_VEX_0F99 */ | |
5040 | { | |
5041 | { VEX_LEN_TABLE (VEX_LEN_0F99_P_0) }, | |
5042 | { Bad_Opcode }, | |
5043 | { VEX_LEN_TABLE (VEX_LEN_0F99_P_2) }, | |
43234a1e L |
5044 | }, |
5045 | ||
592a252b | 5046 | /* PREFIX_VEX_0FC2 */ |
c0f3af97 | 5047 | { |
ec6f095a | 5048 | { "vcmpps", { XM, Vex, EXx, VCMP }, 0 }, |
5b872f7d | 5049 | { "vcmpss", { XMScalar, VexScalar, EXxmm_md, VCMP }, 0 }, |
ec6f095a | 5050 | { "vcmppd", { XM, Vex, EXx, VCMP }, 0 }, |
5b872f7d | 5051 | { "vcmpsd", { XMScalar, VexScalar, EXxmm_mq, VCMP }, 0 }, |
c0f3af97 L |
5052 | }, |
5053 | ||
592a252b | 5054 | /* PREFIX_VEX_0FC4 */ |
c0f3af97 | 5055 | { |
592d1631 L |
5056 | { Bad_Opcode }, |
5057 | { Bad_Opcode }, | |
592a252b | 5058 | { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) }, |
c0f3af97 L |
5059 | }, |
5060 | ||
592a252b | 5061 | /* PREFIX_VEX_0FC5 */ |
c0f3af97 | 5062 | { |
592d1631 L |
5063 | { Bad_Opcode }, |
5064 | { Bad_Opcode }, | |
592a252b | 5065 | { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) }, |
c0f3af97 L |
5066 | }, |
5067 | ||
592a252b | 5068 | /* PREFIX_VEX_0FD0 */ |
c0f3af97 | 5069 | { |
592d1631 L |
5070 | { Bad_Opcode }, |
5071 | { Bad_Opcode }, | |
ec6f095a L |
5072 | { "vaddsubpd", { XM, Vex, EXx }, 0 }, |
5073 | { "vaddsubps", { XM, Vex, EXx }, 0 }, | |
c0f3af97 L |
5074 | }, |
5075 | ||
592a252b | 5076 | /* PREFIX_VEX_0FD1 */ |
c0f3af97 | 5077 | { |
592d1631 L |
5078 | { Bad_Opcode }, |
5079 | { Bad_Opcode }, | |
ec6f095a | 5080 | { "vpsrlw", { XM, Vex, EXxmm }, 0 }, |
c0f3af97 L |
5081 | }, |
5082 | ||
592a252b | 5083 | /* PREFIX_VEX_0FD2 */ |
c0f3af97 | 5084 | { |
592d1631 L |
5085 | { Bad_Opcode }, |
5086 | { Bad_Opcode }, | |
ec6f095a | 5087 | { "vpsrld", { XM, Vex, EXxmm }, 0 }, |
c0f3af97 L |
5088 | }, |
5089 | ||
592a252b | 5090 | /* PREFIX_VEX_0FD3 */ |
c0f3af97 | 5091 | { |
592d1631 L |
5092 | { Bad_Opcode }, |
5093 | { Bad_Opcode }, | |
ec6f095a | 5094 | { "vpsrlq", { XM, Vex, EXxmm }, 0 }, |
c0f3af97 L |
5095 | }, |
5096 | ||
592a252b | 5097 | /* PREFIX_VEX_0FD4 */ |
c0f3af97 | 5098 | { |
592d1631 L |
5099 | { Bad_Opcode }, |
5100 | { Bad_Opcode }, | |
ec6f095a | 5101 | { "vpaddq", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5102 | }, |
5103 | ||
592a252b | 5104 | /* PREFIX_VEX_0FD5 */ |
c0f3af97 | 5105 | { |
592d1631 L |
5106 | { Bad_Opcode }, |
5107 | { Bad_Opcode }, | |
ec6f095a | 5108 | { "vpmullw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5109 | }, |
5110 | ||
592a252b | 5111 | /* PREFIX_VEX_0FD6 */ |
c0f3af97 | 5112 | { |
592d1631 L |
5113 | { Bad_Opcode }, |
5114 | { Bad_Opcode }, | |
592a252b | 5115 | { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) }, |
c0f3af97 L |
5116 | }, |
5117 | ||
592a252b | 5118 | /* PREFIX_VEX_0FD7 */ |
c0f3af97 | 5119 | { |
592d1631 L |
5120 | { Bad_Opcode }, |
5121 | { Bad_Opcode }, | |
592a252b | 5122 | { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) }, |
c0f3af97 L |
5123 | }, |
5124 | ||
592a252b | 5125 | /* PREFIX_VEX_0FD8 */ |
c0f3af97 | 5126 | { |
592d1631 L |
5127 | { Bad_Opcode }, |
5128 | { Bad_Opcode }, | |
ec6f095a | 5129 | { "vpsubusb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5130 | }, |
5131 | ||
592a252b | 5132 | /* PREFIX_VEX_0FD9 */ |
c0f3af97 | 5133 | { |
592d1631 L |
5134 | { Bad_Opcode }, |
5135 | { Bad_Opcode }, | |
ec6f095a | 5136 | { "vpsubusw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5137 | }, |
5138 | ||
592a252b | 5139 | /* PREFIX_VEX_0FDA */ |
c0f3af97 | 5140 | { |
592d1631 L |
5141 | { Bad_Opcode }, |
5142 | { Bad_Opcode }, | |
ec6f095a | 5143 | { "vpminub", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5144 | }, |
5145 | ||
592a252b | 5146 | /* PREFIX_VEX_0FDB */ |
c0f3af97 | 5147 | { |
592d1631 L |
5148 | { Bad_Opcode }, |
5149 | { Bad_Opcode }, | |
ec6f095a | 5150 | { "vpand", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5151 | }, |
5152 | ||
592a252b | 5153 | /* PREFIX_VEX_0FDC */ |
c0f3af97 | 5154 | { |
592d1631 L |
5155 | { Bad_Opcode }, |
5156 | { Bad_Opcode }, | |
ec6f095a | 5157 | { "vpaddusb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5158 | }, |
5159 | ||
592a252b | 5160 | /* PREFIX_VEX_0FDD */ |
c0f3af97 | 5161 | { |
592d1631 L |
5162 | { Bad_Opcode }, |
5163 | { Bad_Opcode }, | |
ec6f095a | 5164 | { "vpaddusw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5165 | }, |
5166 | ||
592a252b | 5167 | /* PREFIX_VEX_0FDE */ |
c0f3af97 | 5168 | { |
592d1631 L |
5169 | { Bad_Opcode }, |
5170 | { Bad_Opcode }, | |
ec6f095a | 5171 | { "vpmaxub", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5172 | }, |
5173 | ||
592a252b | 5174 | /* PREFIX_VEX_0FDF */ |
c0f3af97 | 5175 | { |
592d1631 L |
5176 | { Bad_Opcode }, |
5177 | { Bad_Opcode }, | |
ec6f095a | 5178 | { "vpandn", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5179 | }, |
5180 | ||
592a252b | 5181 | /* PREFIX_VEX_0FE0 */ |
c0f3af97 | 5182 | { |
592d1631 L |
5183 | { Bad_Opcode }, |
5184 | { Bad_Opcode }, | |
ec6f095a | 5185 | { "vpavgb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5186 | }, |
5187 | ||
592a252b | 5188 | /* PREFIX_VEX_0FE1 */ |
c0f3af97 | 5189 | { |
592d1631 L |
5190 | { Bad_Opcode }, |
5191 | { Bad_Opcode }, | |
ec6f095a | 5192 | { "vpsraw", { XM, Vex, EXxmm }, 0 }, |
c0f3af97 L |
5193 | }, |
5194 | ||
592a252b | 5195 | /* PREFIX_VEX_0FE2 */ |
c0f3af97 | 5196 | { |
592d1631 L |
5197 | { Bad_Opcode }, |
5198 | { Bad_Opcode }, | |
ec6f095a | 5199 | { "vpsrad", { XM, Vex, EXxmm }, 0 }, |
c0f3af97 L |
5200 | }, |
5201 | ||
592a252b | 5202 | /* PREFIX_VEX_0FE3 */ |
c0f3af97 | 5203 | { |
592d1631 L |
5204 | { Bad_Opcode }, |
5205 | { Bad_Opcode }, | |
ec6f095a | 5206 | { "vpavgw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5207 | }, |
5208 | ||
592a252b | 5209 | /* PREFIX_VEX_0FE4 */ |
c0f3af97 | 5210 | { |
592d1631 L |
5211 | { Bad_Opcode }, |
5212 | { Bad_Opcode }, | |
ec6f095a | 5213 | { "vpmulhuw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5214 | }, |
5215 | ||
592a252b | 5216 | /* PREFIX_VEX_0FE5 */ |
c0f3af97 | 5217 | { |
592d1631 L |
5218 | { Bad_Opcode }, |
5219 | { Bad_Opcode }, | |
ec6f095a | 5220 | { "vpmulhw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5221 | }, |
5222 | ||
592a252b | 5223 | /* PREFIX_VEX_0FE6 */ |
c0f3af97 | 5224 | { |
592d1631 | 5225 | { Bad_Opcode }, |
ec6f095a L |
5226 | { "vcvtdq2pd", { XM, EXxmmq }, 0 }, |
5227 | { "vcvttpd2dq%XY", { XMM, EXx }, 0 }, | |
5228 | { "vcvtpd2dq%XY", { XMM, EXx }, 0 }, | |
c0f3af97 L |
5229 | }, |
5230 | ||
592a252b | 5231 | /* PREFIX_VEX_0FE7 */ |
c0f3af97 | 5232 | { |
592d1631 L |
5233 | { Bad_Opcode }, |
5234 | { Bad_Opcode }, | |
592a252b | 5235 | { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) }, |
c0f3af97 L |
5236 | }, |
5237 | ||
592a252b | 5238 | /* PREFIX_VEX_0FE8 */ |
c0f3af97 | 5239 | { |
592d1631 L |
5240 | { Bad_Opcode }, |
5241 | { Bad_Opcode }, | |
ec6f095a | 5242 | { "vpsubsb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5243 | }, |
5244 | ||
592a252b | 5245 | /* PREFIX_VEX_0FE9 */ |
c0f3af97 | 5246 | { |
592d1631 L |
5247 | { Bad_Opcode }, |
5248 | { Bad_Opcode }, | |
ec6f095a | 5249 | { "vpsubsw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5250 | }, |
5251 | ||
592a252b | 5252 | /* PREFIX_VEX_0FEA */ |
c0f3af97 | 5253 | { |
592d1631 L |
5254 | { Bad_Opcode }, |
5255 | { Bad_Opcode }, | |
ec6f095a | 5256 | { "vpminsw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5257 | }, |
5258 | ||
592a252b | 5259 | /* PREFIX_VEX_0FEB */ |
c0f3af97 | 5260 | { |
592d1631 L |
5261 | { Bad_Opcode }, |
5262 | { Bad_Opcode }, | |
ec6f095a | 5263 | { "vpor", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5264 | }, |
5265 | ||
592a252b | 5266 | /* PREFIX_VEX_0FEC */ |
c0f3af97 | 5267 | { |
592d1631 L |
5268 | { Bad_Opcode }, |
5269 | { Bad_Opcode }, | |
ec6f095a | 5270 | { "vpaddsb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5271 | }, |
5272 | ||
592a252b | 5273 | /* PREFIX_VEX_0FED */ |
c0f3af97 | 5274 | { |
592d1631 L |
5275 | { Bad_Opcode }, |
5276 | { Bad_Opcode }, | |
ec6f095a | 5277 | { "vpaddsw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5278 | }, |
5279 | ||
592a252b | 5280 | /* PREFIX_VEX_0FEE */ |
c0f3af97 | 5281 | { |
592d1631 L |
5282 | { Bad_Opcode }, |
5283 | { Bad_Opcode }, | |
ec6f095a | 5284 | { "vpmaxsw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5285 | }, |
5286 | ||
592a252b | 5287 | /* PREFIX_VEX_0FEF */ |
c0f3af97 | 5288 | { |
592d1631 L |
5289 | { Bad_Opcode }, |
5290 | { Bad_Opcode }, | |
ec6f095a | 5291 | { "vpxor", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5292 | }, |
5293 | ||
592a252b | 5294 | /* PREFIX_VEX_0FF0 */ |
c0f3af97 | 5295 | { |
592d1631 L |
5296 | { Bad_Opcode }, |
5297 | { Bad_Opcode }, | |
5298 | { Bad_Opcode }, | |
592a252b | 5299 | { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) }, |
c0f3af97 L |
5300 | }, |
5301 | ||
592a252b | 5302 | /* PREFIX_VEX_0FF1 */ |
c0f3af97 | 5303 | { |
592d1631 L |
5304 | { Bad_Opcode }, |
5305 | { Bad_Opcode }, | |
ec6f095a | 5306 | { "vpsllw", { XM, Vex, EXxmm }, 0 }, |
c0f3af97 L |
5307 | }, |
5308 | ||
592a252b | 5309 | /* PREFIX_VEX_0FF2 */ |
c0f3af97 | 5310 | { |
592d1631 L |
5311 | { Bad_Opcode }, |
5312 | { Bad_Opcode }, | |
ec6f095a | 5313 | { "vpslld", { XM, Vex, EXxmm }, 0 }, |
c0f3af97 L |
5314 | }, |
5315 | ||
592a252b | 5316 | /* PREFIX_VEX_0FF3 */ |
c0f3af97 | 5317 | { |
592d1631 L |
5318 | { Bad_Opcode }, |
5319 | { Bad_Opcode }, | |
ec6f095a | 5320 | { "vpsllq", { XM, Vex, EXxmm }, 0 }, |
c0f3af97 L |
5321 | }, |
5322 | ||
592a252b | 5323 | /* PREFIX_VEX_0FF4 */ |
c0f3af97 | 5324 | { |
592d1631 L |
5325 | { Bad_Opcode }, |
5326 | { Bad_Opcode }, | |
ec6f095a | 5327 | { "vpmuludq", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5328 | }, |
5329 | ||
592a252b | 5330 | /* PREFIX_VEX_0FF5 */ |
c0f3af97 | 5331 | { |
592d1631 L |
5332 | { Bad_Opcode }, |
5333 | { Bad_Opcode }, | |
ec6f095a | 5334 | { "vpmaddwd", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5335 | }, |
5336 | ||
592a252b | 5337 | /* PREFIX_VEX_0FF6 */ |
c0f3af97 | 5338 | { |
592d1631 L |
5339 | { Bad_Opcode }, |
5340 | { Bad_Opcode }, | |
ec6f095a | 5341 | { "vpsadbw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5342 | }, |
5343 | ||
592a252b | 5344 | /* PREFIX_VEX_0FF7 */ |
c0f3af97 | 5345 | { |
592d1631 L |
5346 | { Bad_Opcode }, |
5347 | { Bad_Opcode }, | |
592a252b | 5348 | { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) }, |
c0f3af97 L |
5349 | }, |
5350 | ||
592a252b | 5351 | /* PREFIX_VEX_0FF8 */ |
c0f3af97 | 5352 | { |
592d1631 L |
5353 | { Bad_Opcode }, |
5354 | { Bad_Opcode }, | |
ec6f095a | 5355 | { "vpsubb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5356 | }, |
5357 | ||
592a252b | 5358 | /* PREFIX_VEX_0FF9 */ |
c0f3af97 | 5359 | { |
592d1631 L |
5360 | { Bad_Opcode }, |
5361 | { Bad_Opcode }, | |
ec6f095a | 5362 | { "vpsubw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5363 | }, |
5364 | ||
592a252b | 5365 | /* PREFIX_VEX_0FFA */ |
c0f3af97 | 5366 | { |
592d1631 L |
5367 | { Bad_Opcode }, |
5368 | { Bad_Opcode }, | |
ec6f095a | 5369 | { "vpsubd", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5370 | }, |
5371 | ||
592a252b | 5372 | /* PREFIX_VEX_0FFB */ |
c0f3af97 | 5373 | { |
592d1631 L |
5374 | { Bad_Opcode }, |
5375 | { Bad_Opcode }, | |
ec6f095a | 5376 | { "vpsubq", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5377 | }, |
5378 | ||
592a252b | 5379 | /* PREFIX_VEX_0FFC */ |
c0f3af97 | 5380 | { |
592d1631 L |
5381 | { Bad_Opcode }, |
5382 | { Bad_Opcode }, | |
ec6f095a | 5383 | { "vpaddb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5384 | }, |
5385 | ||
592a252b | 5386 | /* PREFIX_VEX_0FFD */ |
c0f3af97 | 5387 | { |
592d1631 L |
5388 | { Bad_Opcode }, |
5389 | { Bad_Opcode }, | |
ec6f095a | 5390 | { "vpaddw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5391 | }, |
5392 | ||
592a252b | 5393 | /* PREFIX_VEX_0FFE */ |
c0f3af97 | 5394 | { |
592d1631 L |
5395 | { Bad_Opcode }, |
5396 | { Bad_Opcode }, | |
ec6f095a | 5397 | { "vpaddd", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5398 | }, |
5399 | ||
592a252b | 5400 | /* PREFIX_VEX_0F3800 */ |
c0f3af97 | 5401 | { |
592d1631 L |
5402 | { Bad_Opcode }, |
5403 | { Bad_Opcode }, | |
ec6f095a | 5404 | { "vpshufb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5405 | }, |
5406 | ||
592a252b | 5407 | /* PREFIX_VEX_0F3801 */ |
c0f3af97 | 5408 | { |
592d1631 L |
5409 | { Bad_Opcode }, |
5410 | { Bad_Opcode }, | |
ec6f095a | 5411 | { "vphaddw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5412 | }, |
5413 | ||
592a252b | 5414 | /* PREFIX_VEX_0F3802 */ |
c0f3af97 | 5415 | { |
592d1631 L |
5416 | { Bad_Opcode }, |
5417 | { Bad_Opcode }, | |
ec6f095a | 5418 | { "vphaddd", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5419 | }, |
5420 | ||
592a252b | 5421 | /* PREFIX_VEX_0F3803 */ |
c0f3af97 | 5422 | { |
592d1631 L |
5423 | { Bad_Opcode }, |
5424 | { Bad_Opcode }, | |
ec6f095a | 5425 | { "vphaddsw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5426 | }, |
5427 | ||
592a252b | 5428 | /* PREFIX_VEX_0F3804 */ |
c0f3af97 | 5429 | { |
592d1631 L |
5430 | { Bad_Opcode }, |
5431 | { Bad_Opcode }, | |
ec6f095a | 5432 | { "vpmaddubsw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5433 | }, |
5434 | ||
592a252b | 5435 | /* PREFIX_VEX_0F3805 */ |
c0f3af97 | 5436 | { |
592d1631 L |
5437 | { Bad_Opcode }, |
5438 | { Bad_Opcode }, | |
ec6f095a | 5439 | { "vphsubw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5440 | }, |
5441 | ||
592a252b | 5442 | /* PREFIX_VEX_0F3806 */ |
c0f3af97 | 5443 | { |
592d1631 L |
5444 | { Bad_Opcode }, |
5445 | { Bad_Opcode }, | |
ec6f095a | 5446 | { "vphsubd", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5447 | }, |
5448 | ||
592a252b | 5449 | /* PREFIX_VEX_0F3807 */ |
c0f3af97 | 5450 | { |
592d1631 L |
5451 | { Bad_Opcode }, |
5452 | { Bad_Opcode }, | |
ec6f095a | 5453 | { "vphsubsw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5454 | }, |
5455 | ||
592a252b | 5456 | /* PREFIX_VEX_0F3808 */ |
c0f3af97 | 5457 | { |
592d1631 L |
5458 | { Bad_Opcode }, |
5459 | { Bad_Opcode }, | |
ec6f095a | 5460 | { "vpsignb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5461 | }, |
5462 | ||
592a252b | 5463 | /* PREFIX_VEX_0F3809 */ |
c0f3af97 | 5464 | { |
592d1631 L |
5465 | { Bad_Opcode }, |
5466 | { Bad_Opcode }, | |
ec6f095a | 5467 | { "vpsignw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5468 | }, |
5469 | ||
592a252b | 5470 | /* PREFIX_VEX_0F380A */ |
c0f3af97 | 5471 | { |
592d1631 L |
5472 | { Bad_Opcode }, |
5473 | { Bad_Opcode }, | |
ec6f095a | 5474 | { "vpsignd", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5475 | }, |
5476 | ||
592a252b | 5477 | /* PREFIX_VEX_0F380B */ |
c0f3af97 | 5478 | { |
592d1631 L |
5479 | { Bad_Opcode }, |
5480 | { Bad_Opcode }, | |
ec6f095a | 5481 | { "vpmulhrsw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5482 | }, |
5483 | ||
592a252b | 5484 | /* PREFIX_VEX_0F380C */ |
c0f3af97 | 5485 | { |
592d1631 L |
5486 | { Bad_Opcode }, |
5487 | { Bad_Opcode }, | |
592a252b | 5488 | { VEX_W_TABLE (VEX_W_0F380C_P_2) }, |
c0f3af97 L |
5489 | }, |
5490 | ||
592a252b | 5491 | /* PREFIX_VEX_0F380D */ |
c0f3af97 | 5492 | { |
592d1631 L |
5493 | { Bad_Opcode }, |
5494 | { Bad_Opcode }, | |
592a252b | 5495 | { VEX_W_TABLE (VEX_W_0F380D_P_2) }, |
c0f3af97 L |
5496 | }, |
5497 | ||
592a252b | 5498 | /* PREFIX_VEX_0F380E */ |
c0f3af97 | 5499 | { |
592d1631 L |
5500 | { Bad_Opcode }, |
5501 | { Bad_Opcode }, | |
592a252b | 5502 | { VEX_W_TABLE (VEX_W_0F380E_P_2) }, |
c0f3af97 L |
5503 | }, |
5504 | ||
592a252b | 5505 | /* PREFIX_VEX_0F380F */ |
c0f3af97 | 5506 | { |
592d1631 L |
5507 | { Bad_Opcode }, |
5508 | { Bad_Opcode }, | |
592a252b | 5509 | { VEX_W_TABLE (VEX_W_0F380F_P_2) }, |
c0f3af97 L |
5510 | }, |
5511 | ||
592a252b | 5512 | /* PREFIX_VEX_0F3813 */ |
c7b8aa3a L |
5513 | { |
5514 | { Bad_Opcode }, | |
5515 | { Bad_Opcode }, | |
6431c801 | 5516 | { VEX_W_TABLE (VEX_W_0F3813_P_2) }, |
c7b8aa3a L |
5517 | }, |
5518 | ||
6c30d220 L |
5519 | /* PREFIX_VEX_0F3816 */ |
5520 | { | |
5521 | { Bad_Opcode }, | |
5522 | { Bad_Opcode }, | |
5523 | { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) }, | |
5524 | }, | |
5525 | ||
592a252b | 5526 | /* PREFIX_VEX_0F3817 */ |
c0f3af97 | 5527 | { |
592d1631 L |
5528 | { Bad_Opcode }, |
5529 | { Bad_Opcode }, | |
ec6f095a | 5530 | { "vptest", { XM, EXx }, 0 }, |
c0f3af97 L |
5531 | }, |
5532 | ||
592a252b | 5533 | /* PREFIX_VEX_0F3818 */ |
c0f3af97 | 5534 | { |
592d1631 L |
5535 | { Bad_Opcode }, |
5536 | { Bad_Opcode }, | |
6c30d220 | 5537 | { VEX_W_TABLE (VEX_W_0F3818_P_2) }, |
c0f3af97 L |
5538 | }, |
5539 | ||
592a252b | 5540 | /* PREFIX_VEX_0F3819 */ |
c0f3af97 | 5541 | { |
592d1631 L |
5542 | { Bad_Opcode }, |
5543 | { Bad_Opcode }, | |
6c30d220 | 5544 | { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) }, |
c0f3af97 L |
5545 | }, |
5546 | ||
592a252b | 5547 | /* PREFIX_VEX_0F381A */ |
c0f3af97 | 5548 | { |
592d1631 L |
5549 | { Bad_Opcode }, |
5550 | { Bad_Opcode }, | |
592a252b | 5551 | { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) }, |
c0f3af97 L |
5552 | }, |
5553 | ||
592a252b | 5554 | /* PREFIX_VEX_0F381C */ |
c0f3af97 | 5555 | { |
592d1631 L |
5556 | { Bad_Opcode }, |
5557 | { Bad_Opcode }, | |
ec6f095a | 5558 | { "vpabsb", { XM, EXx }, 0 }, |
c0f3af97 L |
5559 | }, |
5560 | ||
592a252b | 5561 | /* PREFIX_VEX_0F381D */ |
c0f3af97 | 5562 | { |
592d1631 L |
5563 | { Bad_Opcode }, |
5564 | { Bad_Opcode }, | |
ec6f095a | 5565 | { "vpabsw", { XM, EXx }, 0 }, |
c0f3af97 L |
5566 | }, |
5567 | ||
592a252b | 5568 | /* PREFIX_VEX_0F381E */ |
c0f3af97 | 5569 | { |
592d1631 L |
5570 | { Bad_Opcode }, |
5571 | { Bad_Opcode }, | |
ec6f095a | 5572 | { "vpabsd", { XM, EXx }, 0 }, |
c0f3af97 L |
5573 | }, |
5574 | ||
592a252b | 5575 | /* PREFIX_VEX_0F3820 */ |
c0f3af97 | 5576 | { |
592d1631 L |
5577 | { Bad_Opcode }, |
5578 | { Bad_Opcode }, | |
ec6f095a | 5579 | { "vpmovsxbw", { XM, EXxmmq }, 0 }, |
c0f3af97 L |
5580 | }, |
5581 | ||
592a252b | 5582 | /* PREFIX_VEX_0F3821 */ |
c0f3af97 | 5583 | { |
592d1631 L |
5584 | { Bad_Opcode }, |
5585 | { Bad_Opcode }, | |
ec6f095a | 5586 | { "vpmovsxbd", { XM, EXxmmqd }, 0 }, |
c0f3af97 L |
5587 | }, |
5588 | ||
592a252b | 5589 | /* PREFIX_VEX_0F3822 */ |
c0f3af97 | 5590 | { |
592d1631 L |
5591 | { Bad_Opcode }, |
5592 | { Bad_Opcode }, | |
ec6f095a | 5593 | { "vpmovsxbq", { XM, EXxmmdw }, 0 }, |
c0f3af97 L |
5594 | }, |
5595 | ||
592a252b | 5596 | /* PREFIX_VEX_0F3823 */ |
c0f3af97 | 5597 | { |
592d1631 L |
5598 | { Bad_Opcode }, |
5599 | { Bad_Opcode }, | |
ec6f095a | 5600 | { "vpmovsxwd", { XM, EXxmmq }, 0 }, |
c0f3af97 L |
5601 | }, |
5602 | ||
592a252b | 5603 | /* PREFIX_VEX_0F3824 */ |
c0f3af97 | 5604 | { |
592d1631 L |
5605 | { Bad_Opcode }, |
5606 | { Bad_Opcode }, | |
ec6f095a | 5607 | { "vpmovsxwq", { XM, EXxmmqd }, 0 }, |
c0f3af97 L |
5608 | }, |
5609 | ||
592a252b | 5610 | /* PREFIX_VEX_0F3825 */ |
c0f3af97 | 5611 | { |
592d1631 L |
5612 | { Bad_Opcode }, |
5613 | { Bad_Opcode }, | |
ec6f095a | 5614 | { "vpmovsxdq", { XM, EXxmmq }, 0 }, |
c0f3af97 L |
5615 | }, |
5616 | ||
592a252b | 5617 | /* PREFIX_VEX_0F3828 */ |
c0f3af97 | 5618 | { |
592d1631 L |
5619 | { Bad_Opcode }, |
5620 | { Bad_Opcode }, | |
ec6f095a | 5621 | { "vpmuldq", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5622 | }, |
5623 | ||
592a252b | 5624 | /* PREFIX_VEX_0F3829 */ |
c0f3af97 | 5625 | { |
592d1631 L |
5626 | { Bad_Opcode }, |
5627 | { Bad_Opcode }, | |
ec6f095a | 5628 | { "vpcmpeqq", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5629 | }, |
5630 | ||
592a252b | 5631 | /* PREFIX_VEX_0F382A */ |
c0f3af97 | 5632 | { |
592d1631 L |
5633 | { Bad_Opcode }, |
5634 | { Bad_Opcode }, | |
592a252b | 5635 | { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) }, |
c0f3af97 L |
5636 | }, |
5637 | ||
592a252b | 5638 | /* PREFIX_VEX_0F382B */ |
c0f3af97 | 5639 | { |
592d1631 L |
5640 | { Bad_Opcode }, |
5641 | { Bad_Opcode }, | |
ec6f095a | 5642 | { "vpackusdw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5643 | }, |
5644 | ||
592a252b | 5645 | /* PREFIX_VEX_0F382C */ |
c0f3af97 | 5646 | { |
592d1631 L |
5647 | { Bad_Opcode }, |
5648 | { Bad_Opcode }, | |
592a252b | 5649 | { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) }, |
c0f3af97 L |
5650 | }, |
5651 | ||
592a252b | 5652 | /* PREFIX_VEX_0F382D */ |
c0f3af97 | 5653 | { |
592d1631 L |
5654 | { Bad_Opcode }, |
5655 | { Bad_Opcode }, | |
592a252b | 5656 | { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) }, |
c0f3af97 L |
5657 | }, |
5658 | ||
592a252b | 5659 | /* PREFIX_VEX_0F382E */ |
c0f3af97 | 5660 | { |
592d1631 L |
5661 | { Bad_Opcode }, |
5662 | { Bad_Opcode }, | |
592a252b | 5663 | { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) }, |
c0f3af97 L |
5664 | }, |
5665 | ||
592a252b | 5666 | /* PREFIX_VEX_0F382F */ |
c0f3af97 | 5667 | { |
592d1631 L |
5668 | { Bad_Opcode }, |
5669 | { Bad_Opcode }, | |
592a252b | 5670 | { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) }, |
c0f3af97 L |
5671 | }, |
5672 | ||
592a252b | 5673 | /* PREFIX_VEX_0F3830 */ |
c0f3af97 | 5674 | { |
592d1631 L |
5675 | { Bad_Opcode }, |
5676 | { Bad_Opcode }, | |
ec6f095a | 5677 | { "vpmovzxbw", { XM, EXxmmq }, 0 }, |
c0f3af97 L |
5678 | }, |
5679 | ||
592a252b | 5680 | /* PREFIX_VEX_0F3831 */ |
c0f3af97 | 5681 | { |
592d1631 L |
5682 | { Bad_Opcode }, |
5683 | { Bad_Opcode }, | |
ec6f095a | 5684 | { "vpmovzxbd", { XM, EXxmmqd }, 0 }, |
c0f3af97 L |
5685 | }, |
5686 | ||
592a252b | 5687 | /* PREFIX_VEX_0F3832 */ |
c0f3af97 | 5688 | { |
592d1631 L |
5689 | { Bad_Opcode }, |
5690 | { Bad_Opcode }, | |
ec6f095a | 5691 | { "vpmovzxbq", { XM, EXxmmdw }, 0 }, |
c0f3af97 L |
5692 | }, |
5693 | ||
592a252b | 5694 | /* PREFIX_VEX_0F3833 */ |
c0f3af97 | 5695 | { |
592d1631 L |
5696 | { Bad_Opcode }, |
5697 | { Bad_Opcode }, | |
ec6f095a | 5698 | { "vpmovzxwd", { XM, EXxmmq }, 0 }, |
c0f3af97 L |
5699 | }, |
5700 | ||
592a252b | 5701 | /* PREFIX_VEX_0F3834 */ |
c0f3af97 | 5702 | { |
592d1631 L |
5703 | { Bad_Opcode }, |
5704 | { Bad_Opcode }, | |
ec6f095a | 5705 | { "vpmovzxwq", { XM, EXxmmqd }, 0 }, |
c0f3af97 L |
5706 | }, |
5707 | ||
592a252b | 5708 | /* PREFIX_VEX_0F3835 */ |
c0f3af97 | 5709 | { |
592d1631 L |
5710 | { Bad_Opcode }, |
5711 | { Bad_Opcode }, | |
ec6f095a | 5712 | { "vpmovzxdq", { XM, EXxmmq }, 0 }, |
6c30d220 L |
5713 | }, |
5714 | ||
5715 | /* PREFIX_VEX_0F3836 */ | |
5716 | { | |
5717 | { Bad_Opcode }, | |
5718 | { Bad_Opcode }, | |
5719 | { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) }, | |
c0f3af97 L |
5720 | }, |
5721 | ||
592a252b | 5722 | /* PREFIX_VEX_0F3837 */ |
c0f3af97 | 5723 | { |
592d1631 L |
5724 | { Bad_Opcode }, |
5725 | { Bad_Opcode }, | |
ec6f095a | 5726 | { "vpcmpgtq", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5727 | }, |
5728 | ||
592a252b | 5729 | /* PREFIX_VEX_0F3838 */ |
c0f3af97 | 5730 | { |
592d1631 L |
5731 | { Bad_Opcode }, |
5732 | { Bad_Opcode }, | |
ec6f095a | 5733 | { "vpminsb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5734 | }, |
5735 | ||
592a252b | 5736 | /* PREFIX_VEX_0F3839 */ |
c0f3af97 | 5737 | { |
592d1631 L |
5738 | { Bad_Opcode }, |
5739 | { Bad_Opcode }, | |
ec6f095a | 5740 | { "vpminsd", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5741 | }, |
5742 | ||
592a252b | 5743 | /* PREFIX_VEX_0F383A */ |
c0f3af97 | 5744 | { |
592d1631 L |
5745 | { Bad_Opcode }, |
5746 | { Bad_Opcode }, | |
ec6f095a | 5747 | { "vpminuw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5748 | }, |
5749 | ||
592a252b | 5750 | /* PREFIX_VEX_0F383B */ |
c0f3af97 | 5751 | { |
592d1631 L |
5752 | { Bad_Opcode }, |
5753 | { Bad_Opcode }, | |
ec6f095a | 5754 | { "vpminud", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5755 | }, |
5756 | ||
592a252b | 5757 | /* PREFIX_VEX_0F383C */ |
c0f3af97 | 5758 | { |
592d1631 L |
5759 | { Bad_Opcode }, |
5760 | { Bad_Opcode }, | |
ec6f095a | 5761 | { "vpmaxsb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5762 | }, |
5763 | ||
592a252b | 5764 | /* PREFIX_VEX_0F383D */ |
c0f3af97 | 5765 | { |
592d1631 L |
5766 | { Bad_Opcode }, |
5767 | { Bad_Opcode }, | |
ec6f095a | 5768 | { "vpmaxsd", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5769 | }, |
5770 | ||
592a252b | 5771 | /* PREFIX_VEX_0F383E */ |
c0f3af97 | 5772 | { |
592d1631 L |
5773 | { Bad_Opcode }, |
5774 | { Bad_Opcode }, | |
ec6f095a | 5775 | { "vpmaxuw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5776 | }, |
5777 | ||
592a252b | 5778 | /* PREFIX_VEX_0F383F */ |
c0f3af97 | 5779 | { |
592d1631 L |
5780 | { Bad_Opcode }, |
5781 | { Bad_Opcode }, | |
ec6f095a | 5782 | { "vpmaxud", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5783 | }, |
5784 | ||
592a252b | 5785 | /* PREFIX_VEX_0F3840 */ |
c0f3af97 | 5786 | { |
592d1631 L |
5787 | { Bad_Opcode }, |
5788 | { Bad_Opcode }, | |
ec6f095a | 5789 | { "vpmulld", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5790 | }, |
5791 | ||
592a252b | 5792 | /* PREFIX_VEX_0F3841 */ |
c0f3af97 | 5793 | { |
592d1631 L |
5794 | { Bad_Opcode }, |
5795 | { Bad_Opcode }, | |
592a252b | 5796 | { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) }, |
c0f3af97 L |
5797 | }, |
5798 | ||
6c30d220 L |
5799 | /* PREFIX_VEX_0F3845 */ |
5800 | { | |
5801 | { Bad_Opcode }, | |
5802 | { Bad_Opcode }, | |
bf890a93 | 5803 | { "vpsrlv%LW", { XM, Vex, EXx }, 0 }, |
6c30d220 L |
5804 | }, |
5805 | ||
5806 | /* PREFIX_VEX_0F3846 */ | |
5807 | { | |
5808 | { Bad_Opcode }, | |
5809 | { Bad_Opcode }, | |
5810 | { VEX_W_TABLE (VEX_W_0F3846_P_2) }, | |
5811 | }, | |
5812 | ||
5813 | /* PREFIX_VEX_0F3847 */ | |
5814 | { | |
5815 | { Bad_Opcode }, | |
5816 | { Bad_Opcode }, | |
bf890a93 | 5817 | { "vpsllv%LW", { XM, Vex, EXx }, 0 }, |
6c30d220 L |
5818 | }, |
5819 | ||
5820 | /* PREFIX_VEX_0F3858 */ | |
5821 | { | |
5822 | { Bad_Opcode }, | |
5823 | { Bad_Opcode }, | |
5824 | { VEX_W_TABLE (VEX_W_0F3858_P_2) }, | |
5825 | }, | |
5826 | ||
5827 | /* PREFIX_VEX_0F3859 */ | |
5828 | { | |
5829 | { Bad_Opcode }, | |
5830 | { Bad_Opcode }, | |
5831 | { VEX_W_TABLE (VEX_W_0F3859_P_2) }, | |
5832 | }, | |
5833 | ||
5834 | /* PREFIX_VEX_0F385A */ | |
5835 | { | |
5836 | { Bad_Opcode }, | |
5837 | { Bad_Opcode }, | |
5838 | { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) }, | |
5839 | }, | |
5840 | ||
5841 | /* PREFIX_VEX_0F3878 */ | |
5842 | { | |
5843 | { Bad_Opcode }, | |
5844 | { Bad_Opcode }, | |
5845 | { VEX_W_TABLE (VEX_W_0F3878_P_2) }, | |
5846 | }, | |
5847 | ||
5848 | /* PREFIX_VEX_0F3879 */ | |
5849 | { | |
5850 | { Bad_Opcode }, | |
5851 | { Bad_Opcode }, | |
5852 | { VEX_W_TABLE (VEX_W_0F3879_P_2) }, | |
5853 | }, | |
5854 | ||
5855 | /* PREFIX_VEX_0F388C */ | |
5856 | { | |
5857 | { Bad_Opcode }, | |
5858 | { Bad_Opcode }, | |
f7002f42 | 5859 | { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) }, |
6c30d220 L |
5860 | }, |
5861 | ||
5862 | /* PREFIX_VEX_0F388E */ | |
5863 | { | |
5864 | { Bad_Opcode }, | |
5865 | { Bad_Opcode }, | |
f7002f42 | 5866 | { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) }, |
6c30d220 L |
5867 | }, |
5868 | ||
5869 | /* PREFIX_VEX_0F3890 */ | |
5870 | { | |
5871 | { Bad_Opcode }, | |
5872 | { Bad_Opcode }, | |
bf890a93 | 5873 | { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex }, 0 }, |
6c30d220 L |
5874 | }, |
5875 | ||
5876 | /* PREFIX_VEX_0F3891 */ | |
5877 | { | |
5878 | { Bad_Opcode }, | |
5879 | { Bad_Opcode }, | |
bf890a93 | 5880 | { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 }, |
6c30d220 L |
5881 | }, |
5882 | ||
5883 | /* PREFIX_VEX_0F3892 */ | |
5884 | { | |
5885 | { Bad_Opcode }, | |
5886 | { Bad_Opcode }, | |
bf890a93 | 5887 | { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex }, 0 }, |
6c30d220 L |
5888 | }, |
5889 | ||
5890 | /* PREFIX_VEX_0F3893 */ | |
5891 | { | |
5892 | { Bad_Opcode }, | |
5893 | { Bad_Opcode }, | |
bf890a93 | 5894 | { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 }, |
6c30d220 L |
5895 | }, |
5896 | ||
592a252b | 5897 | /* PREFIX_VEX_0F3896 */ |
a5ff0eb2 | 5898 | { |
592d1631 L |
5899 | { Bad_Opcode }, |
5900 | { Bad_Opcode }, | |
6df22cf6 | 5901 | { "vfmaddsub132p%XW", { XM, Vex, EXx, EXxEVexR }, 0 }, |
a5ff0eb2 L |
5902 | }, |
5903 | ||
592a252b | 5904 | /* PREFIX_VEX_0F3897 */ |
a5ff0eb2 | 5905 | { |
592d1631 L |
5906 | { Bad_Opcode }, |
5907 | { Bad_Opcode }, | |
6df22cf6 | 5908 | { "vfmsubadd132p%XW", { XM, Vex, EXx, EXxEVexR }, 0 }, |
a5ff0eb2 L |
5909 | }, |
5910 | ||
592a252b | 5911 | /* PREFIX_VEX_0F3898 */ |
a5ff0eb2 | 5912 | { |
592d1631 L |
5913 | { Bad_Opcode }, |
5914 | { Bad_Opcode }, | |
6df22cf6 | 5915 | { "vfmadd132p%XW", { XM, Vex, EXx, EXxEVexR }, 0 }, |
a5ff0eb2 L |
5916 | }, |
5917 | ||
592a252b | 5918 | /* PREFIX_VEX_0F3899 */ |
a5ff0eb2 | 5919 | { |
592d1631 L |
5920 | { Bad_Opcode }, |
5921 | { Bad_Opcode }, | |
6df22cf6 | 5922 | { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 }, |
a5ff0eb2 L |
5923 | }, |
5924 | ||
592a252b | 5925 | /* PREFIX_VEX_0F389A */ |
a5ff0eb2 | 5926 | { |
592d1631 L |
5927 | { Bad_Opcode }, |
5928 | { Bad_Opcode }, | |
bf890a93 | 5929 | { "vfmsub132p%XW", { XM, Vex, EXx }, 0 }, |
a5ff0eb2 L |
5930 | }, |
5931 | ||
592a252b | 5932 | /* PREFIX_VEX_0F389B */ |
c0f3af97 | 5933 | { |
592d1631 L |
5934 | { Bad_Opcode }, |
5935 | { Bad_Opcode }, | |
bf890a93 | 5936 | { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
5937 | }, |
5938 | ||
592a252b | 5939 | /* PREFIX_VEX_0F389C */ |
c0f3af97 | 5940 | { |
592d1631 L |
5941 | { Bad_Opcode }, |
5942 | { Bad_Opcode }, | |
6df22cf6 | 5943 | { "vfnmadd132p%XW", { XM, Vex, EXx, EXxEVexR }, 0 }, |
c0f3af97 L |
5944 | }, |
5945 | ||
592a252b | 5946 | /* PREFIX_VEX_0F389D */ |
c0f3af97 | 5947 | { |
592d1631 L |
5948 | { Bad_Opcode }, |
5949 | { Bad_Opcode }, | |
6df22cf6 | 5950 | { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 }, |
c0f3af97 L |
5951 | }, |
5952 | ||
592a252b | 5953 | /* PREFIX_VEX_0F389E */ |
c0f3af97 | 5954 | { |
592d1631 L |
5955 | { Bad_Opcode }, |
5956 | { Bad_Opcode }, | |
6df22cf6 | 5957 | { "vfnmsub132p%XW", { XM, Vex, EXx, EXxEVexR }, 0 }, |
c0f3af97 L |
5958 | }, |
5959 | ||
592a252b | 5960 | /* PREFIX_VEX_0F389F */ |
c0f3af97 | 5961 | { |
592d1631 L |
5962 | { Bad_Opcode }, |
5963 | { Bad_Opcode }, | |
6df22cf6 | 5964 | { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 }, |
c0f3af97 L |
5965 | }, |
5966 | ||
592a252b | 5967 | /* PREFIX_VEX_0F38A6 */ |
c0f3af97 | 5968 | { |
592d1631 L |
5969 | { Bad_Opcode }, |
5970 | { Bad_Opcode }, | |
6df22cf6 | 5971 | { "vfmaddsub213p%XW", { XM, Vex, EXx, EXxEVexR }, 0 }, |
592d1631 | 5972 | { Bad_Opcode }, |
c0f3af97 L |
5973 | }, |
5974 | ||
592a252b | 5975 | /* PREFIX_VEX_0F38A7 */ |
c0f3af97 | 5976 | { |
592d1631 L |
5977 | { Bad_Opcode }, |
5978 | { Bad_Opcode }, | |
6df22cf6 | 5979 | { "vfmsubadd213p%XW", { XM, Vex, EXx, EXxEVexR }, 0 }, |
c0f3af97 L |
5980 | }, |
5981 | ||
592a252b | 5982 | /* PREFIX_VEX_0F38A8 */ |
c0f3af97 | 5983 | { |
592d1631 L |
5984 | { Bad_Opcode }, |
5985 | { Bad_Opcode }, | |
6df22cf6 | 5986 | { "vfmadd213p%XW", { XM, Vex, EXx, EXxEVexR }, 0 }, |
c0f3af97 L |
5987 | }, |
5988 | ||
592a252b | 5989 | /* PREFIX_VEX_0F38A9 */ |
c0f3af97 | 5990 | { |
592d1631 L |
5991 | { Bad_Opcode }, |
5992 | { Bad_Opcode }, | |
6df22cf6 | 5993 | { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 }, |
c0f3af97 L |
5994 | }, |
5995 | ||
592a252b | 5996 | /* PREFIX_VEX_0F38AA */ |
c0f3af97 | 5997 | { |
592d1631 L |
5998 | { Bad_Opcode }, |
5999 | { Bad_Opcode }, | |
bf890a93 | 6000 | { "vfmsub213p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6001 | }, |
6002 | ||
592a252b | 6003 | /* PREFIX_VEX_0F38AB */ |
c0f3af97 | 6004 | { |
592d1631 L |
6005 | { Bad_Opcode }, |
6006 | { Bad_Opcode }, | |
bf890a93 | 6007 | { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6008 | }, |
6009 | ||
592a252b | 6010 | /* PREFIX_VEX_0F38AC */ |
c0f3af97 | 6011 | { |
592d1631 L |
6012 | { Bad_Opcode }, |
6013 | { Bad_Opcode }, | |
6df22cf6 | 6014 | { "vfnmadd213p%XW", { XM, Vex, EXx, EXxEVexR }, 0 }, |
c0f3af97 L |
6015 | }, |
6016 | ||
592a252b | 6017 | /* PREFIX_VEX_0F38AD */ |
c0f3af97 | 6018 | { |
592d1631 L |
6019 | { Bad_Opcode }, |
6020 | { Bad_Opcode }, | |
6df22cf6 | 6021 | { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 }, |
c0f3af97 L |
6022 | }, |
6023 | ||
592a252b | 6024 | /* PREFIX_VEX_0F38AE */ |
c0f3af97 | 6025 | { |
592d1631 L |
6026 | { Bad_Opcode }, |
6027 | { Bad_Opcode }, | |
6df22cf6 | 6028 | { "vfnmsub213p%XW", { XM, Vex, EXx, EXxEVexR }, 0 }, |
c0f3af97 L |
6029 | }, |
6030 | ||
592a252b | 6031 | /* PREFIX_VEX_0F38AF */ |
c0f3af97 | 6032 | { |
592d1631 L |
6033 | { Bad_Opcode }, |
6034 | { Bad_Opcode }, | |
6df22cf6 | 6035 | { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 }, |
c0f3af97 L |
6036 | }, |
6037 | ||
592a252b | 6038 | /* PREFIX_VEX_0F38B6 */ |
c0f3af97 | 6039 | { |
592d1631 L |
6040 | { Bad_Opcode }, |
6041 | { Bad_Opcode }, | |
6df22cf6 | 6042 | { "vfmaddsub231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 }, |
c0f3af97 L |
6043 | }, |
6044 | ||
592a252b | 6045 | /* PREFIX_VEX_0F38B7 */ |
c0f3af97 | 6046 | { |
592d1631 L |
6047 | { Bad_Opcode }, |
6048 | { Bad_Opcode }, | |
6df22cf6 | 6049 | { "vfmsubadd231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 }, |
c0f3af97 L |
6050 | }, |
6051 | ||
592a252b | 6052 | /* PREFIX_VEX_0F38B8 */ |
c0f3af97 | 6053 | { |
592d1631 L |
6054 | { Bad_Opcode }, |
6055 | { Bad_Opcode }, | |
6df22cf6 | 6056 | { "vfmadd231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 }, |
c0f3af97 L |
6057 | }, |
6058 | ||
592a252b | 6059 | /* PREFIX_VEX_0F38B9 */ |
c0f3af97 | 6060 | { |
592d1631 L |
6061 | { Bad_Opcode }, |
6062 | { Bad_Opcode }, | |
6df22cf6 | 6063 | { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 }, |
c0f3af97 L |
6064 | }, |
6065 | ||
592a252b | 6066 | /* PREFIX_VEX_0F38BA */ |
c0f3af97 | 6067 | { |
592d1631 L |
6068 | { Bad_Opcode }, |
6069 | { Bad_Opcode }, | |
6df22cf6 | 6070 | { "vfmsub231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 }, |
c0f3af97 L |
6071 | }, |
6072 | ||
592a252b | 6073 | /* PREFIX_VEX_0F38BB */ |
c0f3af97 | 6074 | { |
592d1631 L |
6075 | { Bad_Opcode }, |
6076 | { Bad_Opcode }, | |
6df22cf6 | 6077 | { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 }, |
c0f3af97 L |
6078 | }, |
6079 | ||
592a252b | 6080 | /* PREFIX_VEX_0F38BC */ |
c0f3af97 | 6081 | { |
592d1631 L |
6082 | { Bad_Opcode }, |
6083 | { Bad_Opcode }, | |
6df22cf6 | 6084 | { "vfnmadd231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 }, |
c0f3af97 L |
6085 | }, |
6086 | ||
592a252b | 6087 | /* PREFIX_VEX_0F38BD */ |
c0f3af97 | 6088 | { |
592d1631 L |
6089 | { Bad_Opcode }, |
6090 | { Bad_Opcode }, | |
6df22cf6 | 6091 | { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 }, |
c0f3af97 L |
6092 | }, |
6093 | ||
592a252b | 6094 | /* PREFIX_VEX_0F38BE */ |
c0f3af97 | 6095 | { |
592d1631 L |
6096 | { Bad_Opcode }, |
6097 | { Bad_Opcode }, | |
6df22cf6 | 6098 | { "vfnmsub231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 }, |
c0f3af97 L |
6099 | }, |
6100 | ||
592a252b | 6101 | /* PREFIX_VEX_0F38BF */ |
c0f3af97 | 6102 | { |
592d1631 L |
6103 | { Bad_Opcode }, |
6104 | { Bad_Opcode }, | |
6df22cf6 | 6105 | { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 }, |
c0f3af97 L |
6106 | }, |
6107 | ||
48521003 IT |
6108 | /* PREFIX_VEX_0F38CF */ |
6109 | { | |
6110 | { Bad_Opcode }, | |
6111 | { Bad_Opcode }, | |
6112 | { VEX_W_TABLE (VEX_W_0F38CF_P_2) }, | |
6113 | }, | |
6114 | ||
592a252b | 6115 | /* PREFIX_VEX_0F38DB */ |
c0f3af97 | 6116 | { |
592d1631 L |
6117 | { Bad_Opcode }, |
6118 | { Bad_Opcode }, | |
592a252b | 6119 | { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) }, |
c0f3af97 L |
6120 | }, |
6121 | ||
592a252b | 6122 | /* PREFIX_VEX_0F38DC */ |
c0f3af97 | 6123 | { |
592d1631 L |
6124 | { Bad_Opcode }, |
6125 | { Bad_Opcode }, | |
8dcf1fad | 6126 | { "vaesenc", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6127 | }, |
6128 | ||
592a252b | 6129 | /* PREFIX_VEX_0F38DD */ |
c0f3af97 | 6130 | { |
592d1631 L |
6131 | { Bad_Opcode }, |
6132 | { Bad_Opcode }, | |
8dcf1fad | 6133 | { "vaesenclast", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6134 | }, |
6135 | ||
592a252b | 6136 | /* PREFIX_VEX_0F38DE */ |
c0f3af97 | 6137 | { |
592d1631 L |
6138 | { Bad_Opcode }, |
6139 | { Bad_Opcode }, | |
8dcf1fad | 6140 | { "vaesdec", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6141 | }, |
6142 | ||
592a252b | 6143 | /* PREFIX_VEX_0F38DF */ |
c0f3af97 | 6144 | { |
592d1631 L |
6145 | { Bad_Opcode }, |
6146 | { Bad_Opcode }, | |
8dcf1fad | 6147 | { "vaesdeclast", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6148 | }, |
6149 | ||
f12dc422 L |
6150 | /* PREFIX_VEX_0F38F2 */ |
6151 | { | |
6152 | { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) }, | |
6153 | }, | |
6154 | ||
6155 | /* PREFIX_VEX_0F38F3_REG_1 */ | |
6156 | { | |
6157 | { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) }, | |
6158 | }, | |
6159 | ||
6160 | /* PREFIX_VEX_0F38F3_REG_2 */ | |
6161 | { | |
6162 | { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) }, | |
6163 | }, | |
6164 | ||
6165 | /* PREFIX_VEX_0F38F3_REG_3 */ | |
6166 | { | |
6167 | { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) }, | |
6168 | }, | |
6169 | ||
6c30d220 L |
6170 | /* PREFIX_VEX_0F38F5 */ |
6171 | { | |
6172 | { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) }, | |
6173 | { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) }, | |
6174 | { Bad_Opcode }, | |
6175 | { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) }, | |
6176 | }, | |
6177 | ||
6178 | /* PREFIX_VEX_0F38F6 */ | |
6179 | { | |
6180 | { Bad_Opcode }, | |
6181 | { Bad_Opcode }, | |
6182 | { Bad_Opcode }, | |
6183 | { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) }, | |
6184 | }, | |
6185 | ||
f12dc422 L |
6186 | /* PREFIX_VEX_0F38F7 */ |
6187 | { | |
6188 | { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) }, | |
6c30d220 L |
6189 | { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) }, |
6190 | { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) }, | |
6191 | { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) }, | |
6192 | }, | |
6193 | ||
6194 | /* PREFIX_VEX_0F3A00 */ | |
6195 | { | |
6196 | { Bad_Opcode }, | |
6197 | { Bad_Opcode }, | |
6198 | { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) }, | |
6199 | }, | |
6200 | ||
6201 | /* PREFIX_VEX_0F3A01 */ | |
6202 | { | |
6203 | { Bad_Opcode }, | |
6204 | { Bad_Opcode }, | |
6205 | { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) }, | |
6206 | }, | |
6207 | ||
6208 | /* PREFIX_VEX_0F3A02 */ | |
6209 | { | |
6210 | { Bad_Opcode }, | |
6211 | { Bad_Opcode }, | |
6212 | { VEX_W_TABLE (VEX_W_0F3A02_P_2) }, | |
f12dc422 L |
6213 | }, |
6214 | ||
592a252b | 6215 | /* PREFIX_VEX_0F3A04 */ |
c0f3af97 | 6216 | { |
592d1631 L |
6217 | { Bad_Opcode }, |
6218 | { Bad_Opcode }, | |
592a252b | 6219 | { VEX_W_TABLE (VEX_W_0F3A04_P_2) }, |
c0f3af97 L |
6220 | }, |
6221 | ||
592a252b | 6222 | /* PREFIX_VEX_0F3A05 */ |
c0f3af97 | 6223 | { |
592d1631 L |
6224 | { Bad_Opcode }, |
6225 | { Bad_Opcode }, | |
592a252b | 6226 | { VEX_W_TABLE (VEX_W_0F3A05_P_2) }, |
c0f3af97 L |
6227 | }, |
6228 | ||
592a252b | 6229 | /* PREFIX_VEX_0F3A06 */ |
c0f3af97 | 6230 | { |
592d1631 L |
6231 | { Bad_Opcode }, |
6232 | { Bad_Opcode }, | |
592a252b | 6233 | { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) }, |
c0f3af97 L |
6234 | }, |
6235 | ||
592a252b | 6236 | /* PREFIX_VEX_0F3A08 */ |
c0f3af97 | 6237 | { |
592d1631 L |
6238 | { Bad_Opcode }, |
6239 | { Bad_Opcode }, | |
ec6f095a | 6240 | { "vroundps", { XM, EXx, Ib }, 0 }, |
c0f3af97 L |
6241 | }, |
6242 | ||
592a252b | 6243 | /* PREFIX_VEX_0F3A09 */ |
c0f3af97 | 6244 | { |
592d1631 L |
6245 | { Bad_Opcode }, |
6246 | { Bad_Opcode }, | |
ec6f095a | 6247 | { "vroundpd", { XM, EXx, Ib }, 0 }, |
c0f3af97 L |
6248 | }, |
6249 | ||
592a252b | 6250 | /* PREFIX_VEX_0F3A0A */ |
c0f3af97 | 6251 | { |
592d1631 L |
6252 | { Bad_Opcode }, |
6253 | { Bad_Opcode }, | |
5b872f7d | 6254 | { "vroundss", { XMScalar, VexScalar, EXxmm_md, Ib }, 0 }, |
0bfee649 L |
6255 | }, |
6256 | ||
592a252b | 6257 | /* PREFIX_VEX_0F3A0B */ |
0bfee649 | 6258 | { |
592d1631 L |
6259 | { Bad_Opcode }, |
6260 | { Bad_Opcode }, | |
5b872f7d | 6261 | { "vroundsd", { XMScalar, VexScalar, EXxmm_mq, Ib }, 0 }, |
0bfee649 L |
6262 | }, |
6263 | ||
592a252b | 6264 | /* PREFIX_VEX_0F3A0C */ |
0bfee649 | 6265 | { |
592d1631 L |
6266 | { Bad_Opcode }, |
6267 | { Bad_Opcode }, | |
ec6f095a | 6268 | { "vblendps", { XM, Vex, EXx, Ib }, 0 }, |
0bfee649 L |
6269 | }, |
6270 | ||
592a252b | 6271 | /* PREFIX_VEX_0F3A0D */ |
0bfee649 | 6272 | { |
592d1631 L |
6273 | { Bad_Opcode }, |
6274 | { Bad_Opcode }, | |
ec6f095a | 6275 | { "vblendpd", { XM, Vex, EXx, Ib }, 0 }, |
c0f3af97 L |
6276 | }, |
6277 | ||
592a252b | 6278 | /* PREFIX_VEX_0F3A0E */ |
0bfee649 | 6279 | { |
592d1631 L |
6280 | { Bad_Opcode }, |
6281 | { Bad_Opcode }, | |
ec6f095a | 6282 | { "vpblendw", { XM, Vex, EXx, Ib }, 0 }, |
0bfee649 L |
6283 | }, |
6284 | ||
592a252b | 6285 | /* PREFIX_VEX_0F3A0F */ |
0bfee649 | 6286 | { |
592d1631 L |
6287 | { Bad_Opcode }, |
6288 | { Bad_Opcode }, | |
ec6f095a | 6289 | { "vpalignr", { XM, Vex, EXx, Ib }, 0 }, |
0bfee649 L |
6290 | }, |
6291 | ||
592a252b | 6292 | /* PREFIX_VEX_0F3A14 */ |
0bfee649 | 6293 | { |
592d1631 L |
6294 | { Bad_Opcode }, |
6295 | { Bad_Opcode }, | |
592a252b | 6296 | { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) }, |
0bfee649 L |
6297 | }, |
6298 | ||
592a252b | 6299 | /* PREFIX_VEX_0F3A15 */ |
0bfee649 | 6300 | { |
592d1631 L |
6301 | { Bad_Opcode }, |
6302 | { Bad_Opcode }, | |
592a252b | 6303 | { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) }, |
0bfee649 L |
6304 | }, |
6305 | ||
592a252b | 6306 | /* PREFIX_VEX_0F3A16 */ |
c0f3af97 | 6307 | { |
592d1631 L |
6308 | { Bad_Opcode }, |
6309 | { Bad_Opcode }, | |
592a252b | 6310 | { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) }, |
c0f3af97 L |
6311 | }, |
6312 | ||
592a252b | 6313 | /* PREFIX_VEX_0F3A17 */ |
c0f3af97 | 6314 | { |
592d1631 L |
6315 | { Bad_Opcode }, |
6316 | { Bad_Opcode }, | |
592a252b | 6317 | { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) }, |
c0f3af97 L |
6318 | }, |
6319 | ||
592a252b | 6320 | /* PREFIX_VEX_0F3A18 */ |
c0f3af97 | 6321 | { |
592d1631 L |
6322 | { Bad_Opcode }, |
6323 | { Bad_Opcode }, | |
592a252b | 6324 | { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) }, |
c0f3af97 L |
6325 | }, |
6326 | ||
592a252b | 6327 | /* PREFIX_VEX_0F3A19 */ |
c0f3af97 | 6328 | { |
592d1631 L |
6329 | { Bad_Opcode }, |
6330 | { Bad_Opcode }, | |
592a252b | 6331 | { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) }, |
c0f3af97 L |
6332 | }, |
6333 | ||
592a252b | 6334 | /* PREFIX_VEX_0F3A1D */ |
c7b8aa3a L |
6335 | { |
6336 | { Bad_Opcode }, | |
6337 | { Bad_Opcode }, | |
6431c801 | 6338 | { VEX_W_TABLE (VEX_W_0F3A1D_P_2) }, |
c7b8aa3a L |
6339 | }, |
6340 | ||
592a252b | 6341 | /* PREFIX_VEX_0F3A20 */ |
c0f3af97 | 6342 | { |
592d1631 L |
6343 | { Bad_Opcode }, |
6344 | { Bad_Opcode }, | |
592a252b | 6345 | { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) }, |
c0f3af97 L |
6346 | }, |
6347 | ||
592a252b | 6348 | /* PREFIX_VEX_0F3A21 */ |
c0f3af97 | 6349 | { |
592d1631 L |
6350 | { Bad_Opcode }, |
6351 | { Bad_Opcode }, | |
592a252b | 6352 | { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) }, |
c0f3af97 L |
6353 | }, |
6354 | ||
592a252b | 6355 | /* PREFIX_VEX_0F3A22 */ |
0bfee649 | 6356 | { |
592d1631 L |
6357 | { Bad_Opcode }, |
6358 | { Bad_Opcode }, | |
592a252b | 6359 | { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) }, |
0bfee649 L |
6360 | }, |
6361 | ||
43234a1e L |
6362 | /* PREFIX_VEX_0F3A30 */ |
6363 | { | |
6364 | { Bad_Opcode }, | |
6365 | { Bad_Opcode }, | |
6366 | { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2) }, | |
6367 | }, | |
6368 | ||
1ba585e8 IT |
6369 | /* PREFIX_VEX_0F3A31 */ |
6370 | { | |
6371 | { Bad_Opcode }, | |
6372 | { Bad_Opcode }, | |
6373 | { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2) }, | |
6374 | }, | |
6375 | ||
43234a1e L |
6376 | /* PREFIX_VEX_0F3A32 */ |
6377 | { | |
6378 | { Bad_Opcode }, | |
6379 | { Bad_Opcode }, | |
6380 | { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2) }, | |
6381 | }, | |
6382 | ||
1ba585e8 IT |
6383 | /* PREFIX_VEX_0F3A33 */ |
6384 | { | |
6385 | { Bad_Opcode }, | |
6386 | { Bad_Opcode }, | |
6387 | { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2) }, | |
6388 | }, | |
6389 | ||
6c30d220 L |
6390 | /* PREFIX_VEX_0F3A38 */ |
6391 | { | |
6392 | { Bad_Opcode }, | |
6393 | { Bad_Opcode }, | |
6394 | { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) }, | |
6395 | }, | |
6396 | ||
6397 | /* PREFIX_VEX_0F3A39 */ | |
6398 | { | |
6399 | { Bad_Opcode }, | |
6400 | { Bad_Opcode }, | |
6401 | { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) }, | |
6402 | }, | |
6403 | ||
592a252b | 6404 | /* PREFIX_VEX_0F3A40 */ |
c0f3af97 | 6405 | { |
592d1631 L |
6406 | { Bad_Opcode }, |
6407 | { Bad_Opcode }, | |
ec6f095a | 6408 | { "vdpps", { XM, Vex, EXx, Ib }, 0 }, |
c0f3af97 L |
6409 | }, |
6410 | ||
592a252b | 6411 | /* PREFIX_VEX_0F3A41 */ |
c0f3af97 | 6412 | { |
592d1631 L |
6413 | { Bad_Opcode }, |
6414 | { Bad_Opcode }, | |
592a252b | 6415 | { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) }, |
c0f3af97 L |
6416 | }, |
6417 | ||
592a252b | 6418 | /* PREFIX_VEX_0F3A42 */ |
c0f3af97 | 6419 | { |
592d1631 L |
6420 | { Bad_Opcode }, |
6421 | { Bad_Opcode }, | |
ec6f095a | 6422 | { "vmpsadbw", { XM, Vex, EXx, Ib }, 0 }, |
c0f3af97 L |
6423 | }, |
6424 | ||
592a252b | 6425 | /* PREFIX_VEX_0F3A44 */ |
ce2f5b3c | 6426 | { |
592d1631 L |
6427 | { Bad_Opcode }, |
6428 | { Bad_Opcode }, | |
ff1982d5 | 6429 | { "vpclmulqdq", { XM, Vex, EXx, PCLMUL }, 0 }, |
ce2f5b3c L |
6430 | }, |
6431 | ||
6c30d220 L |
6432 | /* PREFIX_VEX_0F3A46 */ |
6433 | { | |
6434 | { Bad_Opcode }, | |
6435 | { Bad_Opcode }, | |
6436 | { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) }, | |
6437 | }, | |
6438 | ||
592a252b | 6439 | /* PREFIX_VEX_0F3A48 */ |
a683cc34 SP |
6440 | { |
6441 | { Bad_Opcode }, | |
6442 | { Bad_Opcode }, | |
592a252b | 6443 | { VEX_W_TABLE (VEX_W_0F3A48_P_2) }, |
a683cc34 SP |
6444 | }, |
6445 | ||
592a252b | 6446 | /* PREFIX_VEX_0F3A49 */ |
a683cc34 SP |
6447 | { |
6448 | { Bad_Opcode }, | |
6449 | { Bad_Opcode }, | |
592a252b | 6450 | { VEX_W_TABLE (VEX_W_0F3A49_P_2) }, |
a683cc34 SP |
6451 | }, |
6452 | ||
592a252b | 6453 | /* PREFIX_VEX_0F3A4A */ |
c0f3af97 | 6454 | { |
592d1631 L |
6455 | { Bad_Opcode }, |
6456 | { Bad_Opcode }, | |
592a252b | 6457 | { VEX_W_TABLE (VEX_W_0F3A4A_P_2) }, |
c0f3af97 L |
6458 | }, |
6459 | ||
592a252b | 6460 | /* PREFIX_VEX_0F3A4B */ |
c0f3af97 | 6461 | { |
592d1631 L |
6462 | { Bad_Opcode }, |
6463 | { Bad_Opcode }, | |
592a252b | 6464 | { VEX_W_TABLE (VEX_W_0F3A4B_P_2) }, |
c0f3af97 L |
6465 | }, |
6466 | ||
592a252b | 6467 | /* PREFIX_VEX_0F3A4C */ |
c0f3af97 | 6468 | { |
592d1631 L |
6469 | { Bad_Opcode }, |
6470 | { Bad_Opcode }, | |
6c30d220 | 6471 | { VEX_W_TABLE (VEX_W_0F3A4C_P_2) }, |
c0f3af97 L |
6472 | }, |
6473 | ||
592a252b | 6474 | /* PREFIX_VEX_0F3A5C */ |
922d8de8 | 6475 | { |
592d1631 L |
6476 | { Bad_Opcode }, |
6477 | { Bad_Opcode }, | |
3a2430e0 | 6478 | { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
922d8de8 DR |
6479 | }, |
6480 | ||
592a252b | 6481 | /* PREFIX_VEX_0F3A5D */ |
922d8de8 | 6482 | { |
592d1631 L |
6483 | { Bad_Opcode }, |
6484 | { Bad_Opcode }, | |
3a2430e0 | 6485 | { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
922d8de8 DR |
6486 | }, |
6487 | ||
592a252b | 6488 | /* PREFIX_VEX_0F3A5E */ |
922d8de8 | 6489 | { |
592d1631 L |
6490 | { Bad_Opcode }, |
6491 | { Bad_Opcode }, | |
3a2430e0 | 6492 | { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
922d8de8 DR |
6493 | }, |
6494 | ||
592a252b | 6495 | /* PREFIX_VEX_0F3A5F */ |
922d8de8 | 6496 | { |
592d1631 L |
6497 | { Bad_Opcode }, |
6498 | { Bad_Opcode }, | |
3a2430e0 | 6499 | { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
922d8de8 DR |
6500 | }, |
6501 | ||
592a252b | 6502 | /* PREFIX_VEX_0F3A60 */ |
c0f3af97 | 6503 | { |
592d1631 L |
6504 | { Bad_Opcode }, |
6505 | { Bad_Opcode }, | |
592a252b | 6506 | { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) }, |
592d1631 | 6507 | { Bad_Opcode }, |
c0f3af97 L |
6508 | }, |
6509 | ||
592a252b | 6510 | /* PREFIX_VEX_0F3A61 */ |
c0f3af97 | 6511 | { |
592d1631 L |
6512 | { Bad_Opcode }, |
6513 | { Bad_Opcode }, | |
592a252b | 6514 | { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) }, |
c0f3af97 L |
6515 | }, |
6516 | ||
592a252b | 6517 | /* PREFIX_VEX_0F3A62 */ |
c0f3af97 | 6518 | { |
592d1631 L |
6519 | { Bad_Opcode }, |
6520 | { Bad_Opcode }, | |
592a252b | 6521 | { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) }, |
c0f3af97 L |
6522 | }, |
6523 | ||
592a252b | 6524 | /* PREFIX_VEX_0F3A63 */ |
c0f3af97 | 6525 | { |
592d1631 L |
6526 | { Bad_Opcode }, |
6527 | { Bad_Opcode }, | |
592a252b | 6528 | { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) }, |
c0f3af97 | 6529 | }, |
a5ff0eb2 | 6530 | |
592a252b | 6531 | /* PREFIX_VEX_0F3A68 */ |
922d8de8 | 6532 | { |
592d1631 L |
6533 | { Bad_Opcode }, |
6534 | { Bad_Opcode }, | |
3a2430e0 | 6535 | { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
922d8de8 DR |
6536 | }, |
6537 | ||
592a252b | 6538 | /* PREFIX_VEX_0F3A69 */ |
922d8de8 | 6539 | { |
592d1631 L |
6540 | { Bad_Opcode }, |
6541 | { Bad_Opcode }, | |
3a2430e0 | 6542 | { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
922d8de8 DR |
6543 | }, |
6544 | ||
592a252b | 6545 | /* PREFIX_VEX_0F3A6A */ |
922d8de8 | 6546 | { |
592d1631 L |
6547 | { Bad_Opcode }, |
6548 | { Bad_Opcode }, | |
592a252b | 6549 | { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) }, |
922d8de8 DR |
6550 | }, |
6551 | ||
592a252b | 6552 | /* PREFIX_VEX_0F3A6B */ |
922d8de8 | 6553 | { |
592d1631 L |
6554 | { Bad_Opcode }, |
6555 | { Bad_Opcode }, | |
592a252b | 6556 | { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) }, |
922d8de8 DR |
6557 | }, |
6558 | ||
592a252b | 6559 | /* PREFIX_VEX_0F3A6C */ |
922d8de8 | 6560 | { |
592d1631 L |
6561 | { Bad_Opcode }, |
6562 | { Bad_Opcode }, | |
3a2430e0 | 6563 | { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
922d8de8 DR |
6564 | }, |
6565 | ||
592a252b | 6566 | /* PREFIX_VEX_0F3A6D */ |
922d8de8 | 6567 | { |
592d1631 L |
6568 | { Bad_Opcode }, |
6569 | { Bad_Opcode }, | |
3a2430e0 | 6570 | { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
922d8de8 DR |
6571 | }, |
6572 | ||
592a252b | 6573 | /* PREFIX_VEX_0F3A6E */ |
922d8de8 | 6574 | { |
592d1631 L |
6575 | { Bad_Opcode }, |
6576 | { Bad_Opcode }, | |
592a252b | 6577 | { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) }, |
922d8de8 DR |
6578 | }, |
6579 | ||
592a252b | 6580 | /* PREFIX_VEX_0F3A6F */ |
922d8de8 | 6581 | { |
592d1631 L |
6582 | { Bad_Opcode }, |
6583 | { Bad_Opcode }, | |
592a252b | 6584 | { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) }, |
922d8de8 DR |
6585 | }, |
6586 | ||
592a252b | 6587 | /* PREFIX_VEX_0F3A78 */ |
922d8de8 | 6588 | { |
592d1631 L |
6589 | { Bad_Opcode }, |
6590 | { Bad_Opcode }, | |
3a2430e0 | 6591 | { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
922d8de8 DR |
6592 | }, |
6593 | ||
592a252b | 6594 | /* PREFIX_VEX_0F3A79 */ |
922d8de8 | 6595 | { |
592d1631 L |
6596 | { Bad_Opcode }, |
6597 | { Bad_Opcode }, | |
3a2430e0 | 6598 | { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
922d8de8 DR |
6599 | }, |
6600 | ||
592a252b | 6601 | /* PREFIX_VEX_0F3A7A */ |
922d8de8 | 6602 | { |
592d1631 L |
6603 | { Bad_Opcode }, |
6604 | { Bad_Opcode }, | |
592a252b | 6605 | { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) }, |
922d8de8 DR |
6606 | }, |
6607 | ||
592a252b | 6608 | /* PREFIX_VEX_0F3A7B */ |
922d8de8 | 6609 | { |
592d1631 L |
6610 | { Bad_Opcode }, |
6611 | { Bad_Opcode }, | |
592a252b | 6612 | { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) }, |
922d8de8 DR |
6613 | }, |
6614 | ||
592a252b | 6615 | /* PREFIX_VEX_0F3A7C */ |
922d8de8 | 6616 | { |
592d1631 L |
6617 | { Bad_Opcode }, |
6618 | { Bad_Opcode }, | |
3a2430e0 | 6619 | { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
592d1631 | 6620 | { Bad_Opcode }, |
922d8de8 DR |
6621 | }, |
6622 | ||
592a252b | 6623 | /* PREFIX_VEX_0F3A7D */ |
922d8de8 | 6624 | { |
592d1631 L |
6625 | { Bad_Opcode }, |
6626 | { Bad_Opcode }, | |
3a2430e0 | 6627 | { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
922d8de8 DR |
6628 | }, |
6629 | ||
592a252b | 6630 | /* PREFIX_VEX_0F3A7E */ |
922d8de8 | 6631 | { |
592d1631 L |
6632 | { Bad_Opcode }, |
6633 | { Bad_Opcode }, | |
592a252b | 6634 | { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) }, |
922d8de8 DR |
6635 | }, |
6636 | ||
592a252b | 6637 | /* PREFIX_VEX_0F3A7F */ |
922d8de8 | 6638 | { |
592d1631 L |
6639 | { Bad_Opcode }, |
6640 | { Bad_Opcode }, | |
592a252b | 6641 | { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) }, |
922d8de8 DR |
6642 | }, |
6643 | ||
48521003 IT |
6644 | /* PREFIX_VEX_0F3ACE */ |
6645 | { | |
6646 | { Bad_Opcode }, | |
6647 | { Bad_Opcode }, | |
6648 | { VEX_W_TABLE (VEX_W_0F3ACE_P_2) }, | |
6649 | }, | |
6650 | ||
6651 | /* PREFIX_VEX_0F3ACF */ | |
6652 | { | |
6653 | { Bad_Opcode }, | |
6654 | { Bad_Opcode }, | |
6655 | { VEX_W_TABLE (VEX_W_0F3ACF_P_2) }, | |
6656 | }, | |
6657 | ||
592a252b | 6658 | /* PREFIX_VEX_0F3ADF */ |
a5ff0eb2 | 6659 | { |
592d1631 L |
6660 | { Bad_Opcode }, |
6661 | { Bad_Opcode }, | |
592a252b | 6662 | { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) }, |
a5ff0eb2 | 6663 | }, |
6c30d220 L |
6664 | |
6665 | /* PREFIX_VEX_0F3AF0 */ | |
6666 | { | |
6667 | { Bad_Opcode }, | |
6668 | { Bad_Opcode }, | |
6669 | { Bad_Opcode }, | |
6670 | { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) }, | |
6671 | }, | |
43234a1e | 6672 | |
ad692897 | 6673 | #include "i386-dis-evex-prefix.h" |
c0f3af97 L |
6674 | }; |
6675 | ||
6676 | static const struct dis386 x86_64_table[][2] = { | |
6677 | /* X86_64_06 */ | |
6678 | { | |
bf890a93 | 6679 | { "pushP", { es }, 0 }, |
c0f3af97 L |
6680 | }, |
6681 | ||
6682 | /* X86_64_07 */ | |
6683 | { | |
bf890a93 | 6684 | { "popP", { es }, 0 }, |
c0f3af97 L |
6685 | }, |
6686 | ||
1673df32 | 6687 | /* X86_64_0E */ |
c0f3af97 | 6688 | { |
bf890a93 | 6689 | { "pushP", { cs }, 0 }, |
c0f3af97 L |
6690 | }, |
6691 | ||
6692 | /* X86_64_16 */ | |
6693 | { | |
bf890a93 | 6694 | { "pushP", { ss }, 0 }, |
c0f3af97 L |
6695 | }, |
6696 | ||
6697 | /* X86_64_17 */ | |
6698 | { | |
bf890a93 | 6699 | { "popP", { ss }, 0 }, |
c0f3af97 L |
6700 | }, |
6701 | ||
6702 | /* X86_64_1E */ | |
6703 | { | |
bf890a93 | 6704 | { "pushP", { ds }, 0 }, |
c0f3af97 L |
6705 | }, |
6706 | ||
6707 | /* X86_64_1F */ | |
6708 | { | |
bf890a93 | 6709 | { "popP", { ds }, 0 }, |
c0f3af97 L |
6710 | }, |
6711 | ||
6712 | /* X86_64_27 */ | |
6713 | { | |
bf890a93 | 6714 | { "daa", { XX }, 0 }, |
c0f3af97 L |
6715 | }, |
6716 | ||
6717 | /* X86_64_2F */ | |
6718 | { | |
bf890a93 | 6719 | { "das", { XX }, 0 }, |
c0f3af97 L |
6720 | }, |
6721 | ||
6722 | /* X86_64_37 */ | |
6723 | { | |
bf890a93 | 6724 | { "aaa", { XX }, 0 }, |
c0f3af97 L |
6725 | }, |
6726 | ||
6727 | /* X86_64_3F */ | |
6728 | { | |
bf890a93 | 6729 | { "aas", { XX }, 0 }, |
c0f3af97 L |
6730 | }, |
6731 | ||
6732 | /* X86_64_60 */ | |
6733 | { | |
bf890a93 | 6734 | { "pushaP", { XX }, 0 }, |
c0f3af97 L |
6735 | }, |
6736 | ||
6737 | /* X86_64_61 */ | |
6738 | { | |
bf890a93 | 6739 | { "popaP", { XX }, 0 }, |
c0f3af97 L |
6740 | }, |
6741 | ||
6742 | /* X86_64_62 */ | |
6743 | { | |
6744 | { MOD_TABLE (MOD_62_32BIT) }, | |
43234a1e | 6745 | { EVEX_TABLE (EVEX_0F) }, |
c0f3af97 L |
6746 | }, |
6747 | ||
6748 | /* X86_64_63 */ | |
6749 | { | |
bf890a93 | 6750 | { "arpl", { Ew, Gw }, 0 }, |
bc31405e | 6751 | { "movs", { { OP_G, movsxd_mode }, { MOVSXD_Fixup, movsxd_mode } }, 0 }, |
c0f3af97 L |
6752 | }, |
6753 | ||
6754 | /* X86_64_6D */ | |
6755 | { | |
bf890a93 IT |
6756 | { "ins{R|}", { Yzr, indirDX }, 0 }, |
6757 | { "ins{G|}", { Yzr, indirDX }, 0 }, | |
c0f3af97 L |
6758 | }, |
6759 | ||
6760 | /* X86_64_6F */ | |
6761 | { | |
bf890a93 IT |
6762 | { "outs{R|}", { indirDXr, Xz }, 0 }, |
6763 | { "outs{G|}", { indirDXr, Xz }, 0 }, | |
c0f3af97 L |
6764 | }, |
6765 | ||
d039fef3 | 6766 | /* X86_64_82 */ |
8b89fe14 | 6767 | { |
de194d85 | 6768 | /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode. */ |
d039fef3 | 6769 | { REG_TABLE (REG_80) }, |
8b89fe14 L |
6770 | }, |
6771 | ||
c0f3af97 L |
6772 | /* X86_64_9A */ |
6773 | { | |
8f570d62 | 6774 | { "{l|}call{T|}", { Ap }, 0 }, |
c0f3af97 L |
6775 | }, |
6776 | ||
aeab2b26 JB |
6777 | /* X86_64_C2 */ |
6778 | { | |
6779 | { "retP", { Iw, BND }, 0 }, | |
6780 | { "ret@", { Iw, BND }, 0 }, | |
6781 | }, | |
6782 | ||
6783 | /* X86_64_C3 */ | |
6784 | { | |
6785 | { "retP", { BND }, 0 }, | |
6786 | { "ret@", { BND }, 0 }, | |
6787 | }, | |
6788 | ||
c0f3af97 L |
6789 | /* X86_64_C4 */ |
6790 | { | |
6791 | { MOD_TABLE (MOD_C4_32BIT) }, | |
6792 | { VEX_C4_TABLE (VEX_0F) }, | |
6793 | }, | |
6794 | ||
6795 | /* X86_64_C5 */ | |
6796 | { | |
6797 | { MOD_TABLE (MOD_C5_32BIT) }, | |
6798 | { VEX_C5_TABLE (VEX_0F) }, | |
6799 | }, | |
6800 | ||
6801 | /* X86_64_CE */ | |
6802 | { | |
bf890a93 | 6803 | { "into", { XX }, 0 }, |
c0f3af97 L |
6804 | }, |
6805 | ||
6806 | /* X86_64_D4 */ | |
6807 | { | |
bf890a93 | 6808 | { "aam", { Ib }, 0 }, |
c0f3af97 L |
6809 | }, |
6810 | ||
6811 | /* X86_64_D5 */ | |
6812 | { | |
bf890a93 | 6813 | { "aad", { Ib }, 0 }, |
c0f3af97 L |
6814 | }, |
6815 | ||
a72d2af2 L |
6816 | /* X86_64_E8 */ |
6817 | { | |
6818 | { "callP", { Jv, BND }, 0 }, | |
5db04b09 | 6819 | { "call@", { Jv, BND }, 0 } |
a72d2af2 L |
6820 | }, |
6821 | ||
6822 | /* X86_64_E9 */ | |
6823 | { | |
6824 | { "jmpP", { Jv, BND }, 0 }, | |
5db04b09 | 6825 | { "jmp@", { Jv, BND }, 0 } |
a72d2af2 L |
6826 | }, |
6827 | ||
c0f3af97 L |
6828 | /* X86_64_EA */ |
6829 | { | |
8f570d62 | 6830 | { "{l|}jmp{T|}", { Ap }, 0 }, |
c0f3af97 L |
6831 | }, |
6832 | ||
6833 | /* X86_64_0F01_REG_0 */ | |
6834 | { | |
d1c36125 | 6835 | { "sgdt{Q|Q}", { M }, 0 }, |
bf890a93 | 6836 | { "sgdt", { M }, 0 }, |
c0f3af97 L |
6837 | }, |
6838 | ||
6839 | /* X86_64_0F01_REG_1 */ | |
6840 | { | |
d1c36125 | 6841 | { "sidt{Q|Q}", { M }, 0 }, |
bf890a93 | 6842 | { "sidt", { M }, 0 }, |
c0f3af97 L |
6843 | }, |
6844 | ||
6845 | /* X86_64_0F01_REG_2 */ | |
6846 | { | |
bf890a93 IT |
6847 | { "lgdt{Q|Q}", { M }, 0 }, |
6848 | { "lgdt", { M }, 0 }, | |
c0f3af97 L |
6849 | }, |
6850 | ||
6851 | /* X86_64_0F01_REG_3 */ | |
6852 | { | |
bf890a93 IT |
6853 | { "lidt{Q|Q}", { M }, 0 }, |
6854 | { "lidt", { M }, 0 }, | |
c0f3af97 L |
6855 | }, |
6856 | }; | |
6857 | ||
6858 | static const struct dis386 three_byte_table[][256] = { | |
c1e679ec DR |
6859 | |
6860 | /* THREE_BYTE_0F38 */ | |
c0f3af97 L |
6861 | { |
6862 | /* 00 */ | |
507bd325 L |
6863 | { "pshufb", { MX, EM }, PREFIX_OPCODE }, |
6864 | { "phaddw", { MX, EM }, PREFIX_OPCODE }, | |
6865 | { "phaddd", { MX, EM }, PREFIX_OPCODE }, | |
6866 | { "phaddsw", { MX, EM }, PREFIX_OPCODE }, | |
6867 | { "pmaddubsw", { MX, EM }, PREFIX_OPCODE }, | |
6868 | { "phsubw", { MX, EM }, PREFIX_OPCODE }, | |
6869 | { "phsubd", { MX, EM }, PREFIX_OPCODE }, | |
6870 | { "phsubsw", { MX, EM }, PREFIX_OPCODE }, | |
c0f3af97 | 6871 | /* 08 */ |
507bd325 L |
6872 | { "psignb", { MX, EM }, PREFIX_OPCODE }, |
6873 | { "psignw", { MX, EM }, PREFIX_OPCODE }, | |
6874 | { "psignd", { MX, EM }, PREFIX_OPCODE }, | |
6875 | { "pmulhrsw", { MX, EM }, PREFIX_OPCODE }, | |
592d1631 L |
6876 | { Bad_Opcode }, |
6877 | { Bad_Opcode }, | |
6878 | { Bad_Opcode }, | |
6879 | { Bad_Opcode }, | |
f88c9eb0 SP |
6880 | /* 10 */ |
6881 | { PREFIX_TABLE (PREFIX_0F3810) }, | |
592d1631 L |
6882 | { Bad_Opcode }, |
6883 | { Bad_Opcode }, | |
6884 | { Bad_Opcode }, | |
f88c9eb0 SP |
6885 | { PREFIX_TABLE (PREFIX_0F3814) }, |
6886 | { PREFIX_TABLE (PREFIX_0F3815) }, | |
592d1631 | 6887 | { Bad_Opcode }, |
f88c9eb0 SP |
6888 | { PREFIX_TABLE (PREFIX_0F3817) }, |
6889 | /* 18 */ | |
592d1631 L |
6890 | { Bad_Opcode }, |
6891 | { Bad_Opcode }, | |
6892 | { Bad_Opcode }, | |
6893 | { Bad_Opcode }, | |
507bd325 L |
6894 | { "pabsb", { MX, EM }, PREFIX_OPCODE }, |
6895 | { "pabsw", { MX, EM }, PREFIX_OPCODE }, | |
6896 | { "pabsd", { MX, EM }, PREFIX_OPCODE }, | |
592d1631 | 6897 | { Bad_Opcode }, |
f88c9eb0 SP |
6898 | /* 20 */ |
6899 | { PREFIX_TABLE (PREFIX_0F3820) }, | |
6900 | { PREFIX_TABLE (PREFIX_0F3821) }, | |
6901 | { PREFIX_TABLE (PREFIX_0F3822) }, | |
6902 | { PREFIX_TABLE (PREFIX_0F3823) }, | |
6903 | { PREFIX_TABLE (PREFIX_0F3824) }, | |
6904 | { PREFIX_TABLE (PREFIX_0F3825) }, | |
592d1631 L |
6905 | { Bad_Opcode }, |
6906 | { Bad_Opcode }, | |
f88c9eb0 SP |
6907 | /* 28 */ |
6908 | { PREFIX_TABLE (PREFIX_0F3828) }, | |
6909 | { PREFIX_TABLE (PREFIX_0F3829) }, | |
6910 | { PREFIX_TABLE (PREFIX_0F382A) }, | |
6911 | { PREFIX_TABLE (PREFIX_0F382B) }, | |
592d1631 L |
6912 | { Bad_Opcode }, |
6913 | { Bad_Opcode }, | |
6914 | { Bad_Opcode }, | |
6915 | { Bad_Opcode }, | |
f88c9eb0 SP |
6916 | /* 30 */ |
6917 | { PREFIX_TABLE (PREFIX_0F3830) }, | |
6918 | { PREFIX_TABLE (PREFIX_0F3831) }, | |
6919 | { PREFIX_TABLE (PREFIX_0F3832) }, | |
6920 | { PREFIX_TABLE (PREFIX_0F3833) }, | |
6921 | { PREFIX_TABLE (PREFIX_0F3834) }, | |
6922 | { PREFIX_TABLE (PREFIX_0F3835) }, | |
592d1631 | 6923 | { Bad_Opcode }, |
f88c9eb0 SP |
6924 | { PREFIX_TABLE (PREFIX_0F3837) }, |
6925 | /* 38 */ | |
6926 | { PREFIX_TABLE (PREFIX_0F3838) }, | |
6927 | { PREFIX_TABLE (PREFIX_0F3839) }, | |
6928 | { PREFIX_TABLE (PREFIX_0F383A) }, | |
6929 | { PREFIX_TABLE (PREFIX_0F383B) }, | |
6930 | { PREFIX_TABLE (PREFIX_0F383C) }, | |
6931 | { PREFIX_TABLE (PREFIX_0F383D) }, | |
6932 | { PREFIX_TABLE (PREFIX_0F383E) }, | |
6933 | { PREFIX_TABLE (PREFIX_0F383F) }, | |
6934 | /* 40 */ | |
6935 | { PREFIX_TABLE (PREFIX_0F3840) }, | |
6936 | { PREFIX_TABLE (PREFIX_0F3841) }, | |
592d1631 L |
6937 | { Bad_Opcode }, |
6938 | { Bad_Opcode }, | |
6939 | { Bad_Opcode }, | |
6940 | { Bad_Opcode }, | |
6941 | { Bad_Opcode }, | |
6942 | { Bad_Opcode }, | |
f88c9eb0 | 6943 | /* 48 */ |
592d1631 L |
6944 | { Bad_Opcode }, |
6945 | { Bad_Opcode }, | |
6946 | { Bad_Opcode }, | |
6947 | { Bad_Opcode }, | |
6948 | { Bad_Opcode }, | |
6949 | { Bad_Opcode }, | |
6950 | { Bad_Opcode }, | |
6951 | { Bad_Opcode }, | |
f88c9eb0 | 6952 | /* 50 */ |
592d1631 L |
6953 | { Bad_Opcode }, |
6954 | { Bad_Opcode }, | |
6955 | { Bad_Opcode }, | |
6956 | { Bad_Opcode }, | |
6957 | { Bad_Opcode }, | |
6958 | { Bad_Opcode }, | |
6959 | { Bad_Opcode }, | |
6960 | { Bad_Opcode }, | |
f88c9eb0 | 6961 | /* 58 */ |
592d1631 L |
6962 | { Bad_Opcode }, |
6963 | { Bad_Opcode }, | |
6964 | { Bad_Opcode }, | |
6965 | { Bad_Opcode }, | |
6966 | { Bad_Opcode }, | |
6967 | { Bad_Opcode }, | |
6968 | { Bad_Opcode }, | |
6969 | { Bad_Opcode }, | |
f88c9eb0 | 6970 | /* 60 */ |
592d1631 L |
6971 | { Bad_Opcode }, |
6972 | { Bad_Opcode }, | |
6973 | { Bad_Opcode }, | |
6974 | { Bad_Opcode }, | |
6975 | { Bad_Opcode }, | |
6976 | { Bad_Opcode }, | |
6977 | { Bad_Opcode }, | |
6978 | { Bad_Opcode }, | |
f88c9eb0 | 6979 | /* 68 */ |
592d1631 L |
6980 | { Bad_Opcode }, |
6981 | { Bad_Opcode }, | |
6982 | { Bad_Opcode }, | |
6983 | { Bad_Opcode }, | |
6984 | { Bad_Opcode }, | |
6985 | { Bad_Opcode }, | |
6986 | { Bad_Opcode }, | |
6987 | { Bad_Opcode }, | |
f88c9eb0 | 6988 | /* 70 */ |
592d1631 L |
6989 | { Bad_Opcode }, |
6990 | { Bad_Opcode }, | |
6991 | { Bad_Opcode }, | |
6992 | { Bad_Opcode }, | |
6993 | { Bad_Opcode }, | |
6994 | { Bad_Opcode }, | |
6995 | { Bad_Opcode }, | |
6996 | { Bad_Opcode }, | |
f88c9eb0 | 6997 | /* 78 */ |
592d1631 L |
6998 | { Bad_Opcode }, |
6999 | { Bad_Opcode }, | |
7000 | { Bad_Opcode }, | |
7001 | { Bad_Opcode }, | |
7002 | { Bad_Opcode }, | |
7003 | { Bad_Opcode }, | |
7004 | { Bad_Opcode }, | |
7005 | { Bad_Opcode }, | |
f88c9eb0 SP |
7006 | /* 80 */ |
7007 | { PREFIX_TABLE (PREFIX_0F3880) }, | |
7008 | { PREFIX_TABLE (PREFIX_0F3881) }, | |
6c30d220 | 7009 | { PREFIX_TABLE (PREFIX_0F3882) }, |
592d1631 L |
7010 | { Bad_Opcode }, |
7011 | { Bad_Opcode }, | |
7012 | { Bad_Opcode }, | |
7013 | { Bad_Opcode }, | |
7014 | { Bad_Opcode }, | |
f88c9eb0 | 7015 | /* 88 */ |
592d1631 L |
7016 | { Bad_Opcode }, |
7017 | { Bad_Opcode }, | |
7018 | { Bad_Opcode }, | |
7019 | { Bad_Opcode }, | |
7020 | { Bad_Opcode }, | |
7021 | { Bad_Opcode }, | |
7022 | { Bad_Opcode }, | |
7023 | { Bad_Opcode }, | |
f88c9eb0 | 7024 | /* 90 */ |
592d1631 L |
7025 | { Bad_Opcode }, |
7026 | { Bad_Opcode }, | |
7027 | { Bad_Opcode }, | |
7028 | { Bad_Opcode }, | |
7029 | { Bad_Opcode }, | |
7030 | { Bad_Opcode }, | |
7031 | { Bad_Opcode }, | |
7032 | { Bad_Opcode }, | |
f88c9eb0 | 7033 | /* 98 */ |
592d1631 L |
7034 | { Bad_Opcode }, |
7035 | { Bad_Opcode }, | |
7036 | { Bad_Opcode }, | |
7037 | { Bad_Opcode }, | |
7038 | { Bad_Opcode }, | |
7039 | { Bad_Opcode }, | |
7040 | { Bad_Opcode }, | |
7041 | { Bad_Opcode }, | |
f88c9eb0 | 7042 | /* a0 */ |
592d1631 L |
7043 | { Bad_Opcode }, |
7044 | { Bad_Opcode }, | |
7045 | { Bad_Opcode }, | |
7046 | { Bad_Opcode }, | |
7047 | { Bad_Opcode }, | |
7048 | { Bad_Opcode }, | |
7049 | { Bad_Opcode }, | |
7050 | { Bad_Opcode }, | |
f88c9eb0 | 7051 | /* a8 */ |
592d1631 L |
7052 | { Bad_Opcode }, |
7053 | { Bad_Opcode }, | |
7054 | { Bad_Opcode }, | |
7055 | { Bad_Opcode }, | |
7056 | { Bad_Opcode }, | |
7057 | { Bad_Opcode }, | |
7058 | { Bad_Opcode }, | |
7059 | { Bad_Opcode }, | |
f88c9eb0 | 7060 | /* b0 */ |
592d1631 L |
7061 | { Bad_Opcode }, |
7062 | { Bad_Opcode }, | |
7063 | { Bad_Opcode }, | |
7064 | { Bad_Opcode }, | |
7065 | { Bad_Opcode }, | |
7066 | { Bad_Opcode }, | |
7067 | { Bad_Opcode }, | |
7068 | { Bad_Opcode }, | |
f88c9eb0 | 7069 | /* b8 */ |
592d1631 L |
7070 | { Bad_Opcode }, |
7071 | { Bad_Opcode }, | |
7072 | { Bad_Opcode }, | |
7073 | { Bad_Opcode }, | |
7074 | { Bad_Opcode }, | |
7075 | { Bad_Opcode }, | |
7076 | { Bad_Opcode }, | |
7077 | { Bad_Opcode }, | |
f88c9eb0 | 7078 | /* c0 */ |
592d1631 L |
7079 | { Bad_Opcode }, |
7080 | { Bad_Opcode }, | |
7081 | { Bad_Opcode }, | |
7082 | { Bad_Opcode }, | |
7083 | { Bad_Opcode }, | |
7084 | { Bad_Opcode }, | |
7085 | { Bad_Opcode }, | |
7086 | { Bad_Opcode }, | |
f88c9eb0 | 7087 | /* c8 */ |
a0046408 L |
7088 | { PREFIX_TABLE (PREFIX_0F38C8) }, |
7089 | { PREFIX_TABLE (PREFIX_0F38C9) }, | |
7090 | { PREFIX_TABLE (PREFIX_0F38CA) }, | |
7091 | { PREFIX_TABLE (PREFIX_0F38CB) }, | |
7092 | { PREFIX_TABLE (PREFIX_0F38CC) }, | |
7093 | { PREFIX_TABLE (PREFIX_0F38CD) }, | |
592d1631 | 7094 | { Bad_Opcode }, |
48521003 | 7095 | { PREFIX_TABLE (PREFIX_0F38CF) }, |
f88c9eb0 | 7096 | /* d0 */ |
592d1631 L |
7097 | { Bad_Opcode }, |
7098 | { Bad_Opcode }, | |
7099 | { Bad_Opcode }, | |
7100 | { Bad_Opcode }, | |
7101 | { Bad_Opcode }, | |
7102 | { Bad_Opcode }, | |
7103 | { Bad_Opcode }, | |
7104 | { Bad_Opcode }, | |
f88c9eb0 | 7105 | /* d8 */ |
592d1631 L |
7106 | { Bad_Opcode }, |
7107 | { Bad_Opcode }, | |
7108 | { Bad_Opcode }, | |
f88c9eb0 SP |
7109 | { PREFIX_TABLE (PREFIX_0F38DB) }, |
7110 | { PREFIX_TABLE (PREFIX_0F38DC) }, | |
7111 | { PREFIX_TABLE (PREFIX_0F38DD) }, | |
7112 | { PREFIX_TABLE (PREFIX_0F38DE) }, | |
7113 | { PREFIX_TABLE (PREFIX_0F38DF) }, | |
7114 | /* e0 */ | |
592d1631 L |
7115 | { Bad_Opcode }, |
7116 | { Bad_Opcode }, | |
7117 | { Bad_Opcode }, | |
7118 | { Bad_Opcode }, | |
7119 | { Bad_Opcode }, | |
7120 | { Bad_Opcode }, | |
7121 | { Bad_Opcode }, | |
7122 | { Bad_Opcode }, | |
f88c9eb0 | 7123 | /* e8 */ |
592d1631 L |
7124 | { Bad_Opcode }, |
7125 | { Bad_Opcode }, | |
7126 | { Bad_Opcode }, | |
7127 | { Bad_Opcode }, | |
7128 | { Bad_Opcode }, | |
7129 | { Bad_Opcode }, | |
7130 | { Bad_Opcode }, | |
7131 | { Bad_Opcode }, | |
f88c9eb0 SP |
7132 | /* f0 */ |
7133 | { PREFIX_TABLE (PREFIX_0F38F0) }, | |
7134 | { PREFIX_TABLE (PREFIX_0F38F1) }, | |
592d1631 L |
7135 | { Bad_Opcode }, |
7136 | { Bad_Opcode }, | |
7137 | { Bad_Opcode }, | |
603555e5 | 7138 | { PREFIX_TABLE (PREFIX_0F38F5) }, |
e2e1fcde | 7139 | { PREFIX_TABLE (PREFIX_0F38F6) }, |
592d1631 | 7140 | { Bad_Opcode }, |
f88c9eb0 | 7141 | /* f8 */ |
c0a30a9f L |
7142 | { PREFIX_TABLE (PREFIX_0F38F8) }, |
7143 | { PREFIX_TABLE (PREFIX_0F38F9) }, | |
592d1631 L |
7144 | { Bad_Opcode }, |
7145 | { Bad_Opcode }, | |
7146 | { Bad_Opcode }, | |
7147 | { Bad_Opcode }, | |
7148 | { Bad_Opcode }, | |
7149 | { Bad_Opcode }, | |
f88c9eb0 SP |
7150 | }, |
7151 | /* THREE_BYTE_0F3A */ | |
7152 | { | |
7153 | /* 00 */ | |
592d1631 L |
7154 | { Bad_Opcode }, |
7155 | { Bad_Opcode }, | |
7156 | { Bad_Opcode }, | |
7157 | { Bad_Opcode }, | |
7158 | { Bad_Opcode }, | |
7159 | { Bad_Opcode }, | |
7160 | { Bad_Opcode }, | |
7161 | { Bad_Opcode }, | |
f88c9eb0 SP |
7162 | /* 08 */ |
7163 | { PREFIX_TABLE (PREFIX_0F3A08) }, | |
7164 | { PREFIX_TABLE (PREFIX_0F3A09) }, | |
7165 | { PREFIX_TABLE (PREFIX_0F3A0A) }, | |
7166 | { PREFIX_TABLE (PREFIX_0F3A0B) }, | |
7167 | { PREFIX_TABLE (PREFIX_0F3A0C) }, | |
7168 | { PREFIX_TABLE (PREFIX_0F3A0D) }, | |
7169 | { PREFIX_TABLE (PREFIX_0F3A0E) }, | |
507bd325 | 7170 | { "palignr", { MX, EM, Ib }, PREFIX_OPCODE }, |
f88c9eb0 | 7171 | /* 10 */ |
592d1631 L |
7172 | { Bad_Opcode }, |
7173 | { Bad_Opcode }, | |
7174 | { Bad_Opcode }, | |
7175 | { Bad_Opcode }, | |
f88c9eb0 SP |
7176 | { PREFIX_TABLE (PREFIX_0F3A14) }, |
7177 | { PREFIX_TABLE (PREFIX_0F3A15) }, | |
7178 | { PREFIX_TABLE (PREFIX_0F3A16) }, | |
7179 | { PREFIX_TABLE (PREFIX_0F3A17) }, | |
7180 | /* 18 */ | |
592d1631 L |
7181 | { Bad_Opcode }, |
7182 | { Bad_Opcode }, | |
7183 | { Bad_Opcode }, | |
7184 | { Bad_Opcode }, | |
7185 | { Bad_Opcode }, | |
7186 | { Bad_Opcode }, | |
7187 | { Bad_Opcode }, | |
7188 | { Bad_Opcode }, | |
f88c9eb0 SP |
7189 | /* 20 */ |
7190 | { PREFIX_TABLE (PREFIX_0F3A20) }, | |
7191 | { PREFIX_TABLE (PREFIX_0F3A21) }, | |
7192 | { PREFIX_TABLE (PREFIX_0F3A22) }, | |
592d1631 L |
7193 | { Bad_Opcode }, |
7194 | { Bad_Opcode }, | |
7195 | { Bad_Opcode }, | |
7196 | { Bad_Opcode }, | |
7197 | { Bad_Opcode }, | |
f88c9eb0 | 7198 | /* 28 */ |
592d1631 L |
7199 | { Bad_Opcode }, |
7200 | { Bad_Opcode }, | |
7201 | { Bad_Opcode }, | |
7202 | { Bad_Opcode }, | |
7203 | { Bad_Opcode }, | |
7204 | { Bad_Opcode }, | |
7205 | { Bad_Opcode }, | |
7206 | { Bad_Opcode }, | |
f88c9eb0 | 7207 | /* 30 */ |
592d1631 L |
7208 | { Bad_Opcode }, |
7209 | { Bad_Opcode }, | |
7210 | { Bad_Opcode }, | |
7211 | { Bad_Opcode }, | |
7212 | { Bad_Opcode }, | |
7213 | { Bad_Opcode }, | |
7214 | { Bad_Opcode }, | |
7215 | { Bad_Opcode }, | |
f88c9eb0 | 7216 | /* 38 */ |
592d1631 L |
7217 | { Bad_Opcode }, |
7218 | { Bad_Opcode }, | |
7219 | { Bad_Opcode }, | |
7220 | { Bad_Opcode }, | |
7221 | { Bad_Opcode }, | |
7222 | { Bad_Opcode }, | |
7223 | { Bad_Opcode }, | |
7224 | { Bad_Opcode }, | |
f88c9eb0 SP |
7225 | /* 40 */ |
7226 | { PREFIX_TABLE (PREFIX_0F3A40) }, | |
7227 | { PREFIX_TABLE (PREFIX_0F3A41) }, | |
7228 | { PREFIX_TABLE (PREFIX_0F3A42) }, | |
592d1631 | 7229 | { Bad_Opcode }, |
f88c9eb0 | 7230 | { PREFIX_TABLE (PREFIX_0F3A44) }, |
592d1631 L |
7231 | { Bad_Opcode }, |
7232 | { Bad_Opcode }, | |
7233 | { Bad_Opcode }, | |
f88c9eb0 | 7234 | /* 48 */ |
592d1631 L |
7235 | { Bad_Opcode }, |
7236 | { Bad_Opcode }, | |
7237 | { Bad_Opcode }, | |
7238 | { Bad_Opcode }, | |
7239 | { Bad_Opcode }, | |
7240 | { Bad_Opcode }, | |
7241 | { Bad_Opcode }, | |
7242 | { Bad_Opcode }, | |
f88c9eb0 | 7243 | /* 50 */ |
592d1631 L |
7244 | { Bad_Opcode }, |
7245 | { Bad_Opcode }, | |
7246 | { Bad_Opcode }, | |
7247 | { Bad_Opcode }, | |
7248 | { Bad_Opcode }, | |
7249 | { Bad_Opcode }, | |
7250 | { Bad_Opcode }, | |
7251 | { Bad_Opcode }, | |
f88c9eb0 | 7252 | /* 58 */ |
592d1631 L |
7253 | { Bad_Opcode }, |
7254 | { Bad_Opcode }, | |
7255 | { Bad_Opcode }, | |
7256 | { Bad_Opcode }, | |
7257 | { Bad_Opcode }, | |
7258 | { Bad_Opcode }, | |
7259 | { Bad_Opcode }, | |
7260 | { Bad_Opcode }, | |
f88c9eb0 SP |
7261 | /* 60 */ |
7262 | { PREFIX_TABLE (PREFIX_0F3A60) }, | |
7263 | { PREFIX_TABLE (PREFIX_0F3A61) }, | |
7264 | { PREFIX_TABLE (PREFIX_0F3A62) }, | |
7265 | { PREFIX_TABLE (PREFIX_0F3A63) }, | |
592d1631 L |
7266 | { Bad_Opcode }, |
7267 | { Bad_Opcode }, | |
7268 | { Bad_Opcode }, | |
7269 | { Bad_Opcode }, | |
f88c9eb0 | 7270 | /* 68 */ |
592d1631 L |
7271 | { Bad_Opcode }, |
7272 | { Bad_Opcode }, | |
7273 | { Bad_Opcode }, | |
7274 | { Bad_Opcode }, | |
7275 | { Bad_Opcode }, | |
7276 | { Bad_Opcode }, | |
7277 | { Bad_Opcode }, | |
7278 | { Bad_Opcode }, | |
f88c9eb0 | 7279 | /* 70 */ |
592d1631 L |
7280 | { Bad_Opcode }, |
7281 | { Bad_Opcode }, | |
7282 | { Bad_Opcode }, | |
7283 | { Bad_Opcode }, | |
7284 | { Bad_Opcode }, | |
7285 | { Bad_Opcode }, | |
7286 | { Bad_Opcode }, | |
7287 | { Bad_Opcode }, | |
f88c9eb0 | 7288 | /* 78 */ |
592d1631 L |
7289 | { Bad_Opcode }, |
7290 | { Bad_Opcode }, | |
7291 | { Bad_Opcode }, | |
7292 | { Bad_Opcode }, | |
7293 | { Bad_Opcode }, | |
7294 | { Bad_Opcode }, | |
7295 | { Bad_Opcode }, | |
7296 | { Bad_Opcode }, | |
f88c9eb0 | 7297 | /* 80 */ |
592d1631 L |
7298 | { Bad_Opcode }, |
7299 | { Bad_Opcode }, | |
7300 | { Bad_Opcode }, | |
7301 | { Bad_Opcode }, | |
7302 | { Bad_Opcode }, | |
7303 | { Bad_Opcode }, | |
7304 | { Bad_Opcode }, | |
7305 | { Bad_Opcode }, | |
f88c9eb0 | 7306 | /* 88 */ |
592d1631 L |
7307 | { Bad_Opcode }, |
7308 | { Bad_Opcode }, | |
7309 | { Bad_Opcode }, | |
7310 | { Bad_Opcode }, | |
7311 | { Bad_Opcode }, | |
7312 | { Bad_Opcode }, | |
7313 | { Bad_Opcode }, | |
7314 | { Bad_Opcode }, | |
f88c9eb0 | 7315 | /* 90 */ |
592d1631 L |
7316 | { Bad_Opcode }, |
7317 | { Bad_Opcode }, | |
7318 | { Bad_Opcode }, | |
7319 | { Bad_Opcode }, | |
7320 | { Bad_Opcode }, | |
7321 | { Bad_Opcode }, | |
7322 | { Bad_Opcode }, | |
7323 | { Bad_Opcode }, | |
f88c9eb0 | 7324 | /* 98 */ |
592d1631 L |
7325 | { Bad_Opcode }, |
7326 | { Bad_Opcode }, | |
7327 | { Bad_Opcode }, | |
7328 | { Bad_Opcode }, | |
7329 | { Bad_Opcode }, | |
7330 | { Bad_Opcode }, | |
7331 | { Bad_Opcode }, | |
7332 | { Bad_Opcode }, | |
f88c9eb0 | 7333 | /* a0 */ |
592d1631 L |
7334 | { Bad_Opcode }, |
7335 | { Bad_Opcode }, | |
7336 | { Bad_Opcode }, | |
7337 | { Bad_Opcode }, | |
7338 | { Bad_Opcode }, | |
7339 | { Bad_Opcode }, | |
7340 | { Bad_Opcode }, | |
7341 | { Bad_Opcode }, | |
f88c9eb0 | 7342 | /* a8 */ |
592d1631 L |
7343 | { Bad_Opcode }, |
7344 | { Bad_Opcode }, | |
7345 | { Bad_Opcode }, | |
7346 | { Bad_Opcode }, | |
7347 | { Bad_Opcode }, | |
7348 | { Bad_Opcode }, | |
7349 | { Bad_Opcode }, | |
7350 | { Bad_Opcode }, | |
f88c9eb0 | 7351 | /* b0 */ |
592d1631 L |
7352 | { Bad_Opcode }, |
7353 | { Bad_Opcode }, | |
7354 | { Bad_Opcode }, | |
7355 | { Bad_Opcode }, | |
7356 | { Bad_Opcode }, | |
7357 | { Bad_Opcode }, | |
7358 | { Bad_Opcode }, | |
7359 | { Bad_Opcode }, | |
f88c9eb0 | 7360 | /* b8 */ |
592d1631 L |
7361 | { Bad_Opcode }, |
7362 | { Bad_Opcode }, | |
7363 | { Bad_Opcode }, | |
7364 | { Bad_Opcode }, | |
7365 | { Bad_Opcode }, | |
7366 | { Bad_Opcode }, | |
7367 | { Bad_Opcode }, | |
7368 | { Bad_Opcode }, | |
f88c9eb0 | 7369 | /* c0 */ |
592d1631 L |
7370 | { Bad_Opcode }, |
7371 | { Bad_Opcode }, | |
7372 | { Bad_Opcode }, | |
7373 | { Bad_Opcode }, | |
7374 | { Bad_Opcode }, | |
7375 | { Bad_Opcode }, | |
7376 | { Bad_Opcode }, | |
7377 | { Bad_Opcode }, | |
f88c9eb0 | 7378 | /* c8 */ |
592d1631 L |
7379 | { Bad_Opcode }, |
7380 | { Bad_Opcode }, | |
7381 | { Bad_Opcode }, | |
7382 | { Bad_Opcode }, | |
a0046408 | 7383 | { PREFIX_TABLE (PREFIX_0F3ACC) }, |
592d1631 | 7384 | { Bad_Opcode }, |
48521003 IT |
7385 | { PREFIX_TABLE (PREFIX_0F3ACE) }, |
7386 | { PREFIX_TABLE (PREFIX_0F3ACF) }, | |
f88c9eb0 | 7387 | /* d0 */ |
592d1631 L |
7388 | { Bad_Opcode }, |
7389 | { Bad_Opcode }, | |
7390 | { Bad_Opcode }, | |
7391 | { Bad_Opcode }, | |
7392 | { Bad_Opcode }, | |
7393 | { Bad_Opcode }, | |
7394 | { Bad_Opcode }, | |
7395 | { Bad_Opcode }, | |
f88c9eb0 | 7396 | /* d8 */ |
592d1631 L |
7397 | { Bad_Opcode }, |
7398 | { Bad_Opcode }, | |
7399 | { Bad_Opcode }, | |
7400 | { Bad_Opcode }, | |
7401 | { Bad_Opcode }, | |
7402 | { Bad_Opcode }, | |
7403 | { Bad_Opcode }, | |
f88c9eb0 SP |
7404 | { PREFIX_TABLE (PREFIX_0F3ADF) }, |
7405 | /* e0 */ | |
592d1631 L |
7406 | { Bad_Opcode }, |
7407 | { Bad_Opcode }, | |
7408 | { Bad_Opcode }, | |
7409 | { Bad_Opcode }, | |
7410 | { Bad_Opcode }, | |
592d1631 L |
7411 | { Bad_Opcode }, |
7412 | { Bad_Opcode }, | |
7413 | { Bad_Opcode }, | |
85f10a01 | 7414 | /* e8 */ |
592d1631 L |
7415 | { Bad_Opcode }, |
7416 | { Bad_Opcode }, | |
7417 | { Bad_Opcode }, | |
7418 | { Bad_Opcode }, | |
7419 | { Bad_Opcode }, | |
7420 | { Bad_Opcode }, | |
7421 | { Bad_Opcode }, | |
7422 | { Bad_Opcode }, | |
85f10a01 | 7423 | /* f0 */ |
592d1631 L |
7424 | { Bad_Opcode }, |
7425 | { Bad_Opcode }, | |
7426 | { Bad_Opcode }, | |
7427 | { Bad_Opcode }, | |
7428 | { Bad_Opcode }, | |
7429 | { Bad_Opcode }, | |
7430 | { Bad_Opcode }, | |
7431 | { Bad_Opcode }, | |
85f10a01 | 7432 | /* f8 */ |
592d1631 L |
7433 | { Bad_Opcode }, |
7434 | { Bad_Opcode }, | |
7435 | { Bad_Opcode }, | |
7436 | { Bad_Opcode }, | |
7437 | { Bad_Opcode }, | |
7438 | { Bad_Opcode }, | |
7439 | { Bad_Opcode }, | |
7440 | { Bad_Opcode }, | |
85f10a01 | 7441 | }, |
f88c9eb0 SP |
7442 | }; |
7443 | ||
7444 | static const struct dis386 xop_table[][256] = { | |
5dd85c99 | 7445 | /* XOP_08 */ |
85f10a01 MM |
7446 | { |
7447 | /* 00 */ | |
592d1631 L |
7448 | { Bad_Opcode }, |
7449 | { Bad_Opcode }, | |
7450 | { Bad_Opcode }, | |
7451 | { Bad_Opcode }, | |
7452 | { Bad_Opcode }, | |
7453 | { Bad_Opcode }, | |
7454 | { Bad_Opcode }, | |
7455 | { Bad_Opcode }, | |
85f10a01 | 7456 | /* 08 */ |
592d1631 L |
7457 | { Bad_Opcode }, |
7458 | { Bad_Opcode }, | |
7459 | { Bad_Opcode }, | |
7460 | { Bad_Opcode }, | |
7461 | { Bad_Opcode }, | |
7462 | { Bad_Opcode }, | |
7463 | { Bad_Opcode }, | |
7464 | { Bad_Opcode }, | |
85f10a01 | 7465 | /* 10 */ |
3929df09 | 7466 | { Bad_Opcode }, |
592d1631 L |
7467 | { Bad_Opcode }, |
7468 | { Bad_Opcode }, | |
7469 | { Bad_Opcode }, | |
7470 | { Bad_Opcode }, | |
7471 | { Bad_Opcode }, | |
7472 | { Bad_Opcode }, | |
7473 | { Bad_Opcode }, | |
85f10a01 | 7474 | /* 18 */ |
592d1631 L |
7475 | { Bad_Opcode }, |
7476 | { Bad_Opcode }, | |
7477 | { Bad_Opcode }, | |
7478 | { Bad_Opcode }, | |
7479 | { Bad_Opcode }, | |
7480 | { Bad_Opcode }, | |
7481 | { Bad_Opcode }, | |
7482 | { Bad_Opcode }, | |
85f10a01 | 7483 | /* 20 */ |
592d1631 L |
7484 | { Bad_Opcode }, |
7485 | { Bad_Opcode }, | |
7486 | { Bad_Opcode }, | |
7487 | { Bad_Opcode }, | |
7488 | { Bad_Opcode }, | |
7489 | { Bad_Opcode }, | |
7490 | { Bad_Opcode }, | |
7491 | { Bad_Opcode }, | |
85f10a01 | 7492 | /* 28 */ |
592d1631 L |
7493 | { Bad_Opcode }, |
7494 | { Bad_Opcode }, | |
7495 | { Bad_Opcode }, | |
7496 | { Bad_Opcode }, | |
7497 | { Bad_Opcode }, | |
7498 | { Bad_Opcode }, | |
7499 | { Bad_Opcode }, | |
7500 | { Bad_Opcode }, | |
c0f3af97 | 7501 | /* 30 */ |
592d1631 L |
7502 | { Bad_Opcode }, |
7503 | { Bad_Opcode }, | |
7504 | { Bad_Opcode }, | |
7505 | { Bad_Opcode }, | |
7506 | { Bad_Opcode }, | |
7507 | { Bad_Opcode }, | |
7508 | { Bad_Opcode }, | |
7509 | { Bad_Opcode }, | |
c0f3af97 | 7510 | /* 38 */ |
592d1631 L |
7511 | { Bad_Opcode }, |
7512 | { Bad_Opcode }, | |
7513 | { Bad_Opcode }, | |
7514 | { Bad_Opcode }, | |
7515 | { Bad_Opcode }, | |
7516 | { Bad_Opcode }, | |
7517 | { Bad_Opcode }, | |
7518 | { Bad_Opcode }, | |
c0f3af97 | 7519 | /* 40 */ |
592d1631 L |
7520 | { Bad_Opcode }, |
7521 | { Bad_Opcode }, | |
7522 | { Bad_Opcode }, | |
7523 | { Bad_Opcode }, | |
7524 | { Bad_Opcode }, | |
7525 | { Bad_Opcode }, | |
7526 | { Bad_Opcode }, | |
7527 | { Bad_Opcode }, | |
85f10a01 | 7528 | /* 48 */ |
592d1631 L |
7529 | { Bad_Opcode }, |
7530 | { Bad_Opcode }, | |
7531 | { Bad_Opcode }, | |
7532 | { Bad_Opcode }, | |
7533 | { Bad_Opcode }, | |
7534 | { Bad_Opcode }, | |
7535 | { Bad_Opcode }, | |
7536 | { Bad_Opcode }, | |
c0f3af97 | 7537 | /* 50 */ |
592d1631 L |
7538 | { Bad_Opcode }, |
7539 | { Bad_Opcode }, | |
7540 | { Bad_Opcode }, | |
7541 | { Bad_Opcode }, | |
7542 | { Bad_Opcode }, | |
7543 | { Bad_Opcode }, | |
7544 | { Bad_Opcode }, | |
7545 | { Bad_Opcode }, | |
85f10a01 | 7546 | /* 58 */ |
592d1631 L |
7547 | { Bad_Opcode }, |
7548 | { Bad_Opcode }, | |
7549 | { Bad_Opcode }, | |
7550 | { Bad_Opcode }, | |
7551 | { Bad_Opcode }, | |
7552 | { Bad_Opcode }, | |
7553 | { Bad_Opcode }, | |
7554 | { Bad_Opcode }, | |
c1e679ec | 7555 | /* 60 */ |
592d1631 L |
7556 | { Bad_Opcode }, |
7557 | { Bad_Opcode }, | |
7558 | { Bad_Opcode }, | |
7559 | { Bad_Opcode }, | |
7560 | { Bad_Opcode }, | |
7561 | { Bad_Opcode }, | |
7562 | { Bad_Opcode }, | |
7563 | { Bad_Opcode }, | |
c0f3af97 | 7564 | /* 68 */ |
592d1631 L |
7565 | { Bad_Opcode }, |
7566 | { Bad_Opcode }, | |
7567 | { Bad_Opcode }, | |
7568 | { Bad_Opcode }, | |
7569 | { Bad_Opcode }, | |
7570 | { Bad_Opcode }, | |
7571 | { Bad_Opcode }, | |
7572 | { Bad_Opcode }, | |
85f10a01 | 7573 | /* 70 */ |
592d1631 L |
7574 | { Bad_Opcode }, |
7575 | { Bad_Opcode }, | |
7576 | { Bad_Opcode }, | |
7577 | { Bad_Opcode }, | |
7578 | { Bad_Opcode }, | |
7579 | { Bad_Opcode }, | |
7580 | { Bad_Opcode }, | |
7581 | { Bad_Opcode }, | |
85f10a01 | 7582 | /* 78 */ |
592d1631 L |
7583 | { Bad_Opcode }, |
7584 | { Bad_Opcode }, | |
7585 | { Bad_Opcode }, | |
7586 | { Bad_Opcode }, | |
7587 | { Bad_Opcode }, | |
7588 | { Bad_Opcode }, | |
7589 | { Bad_Opcode }, | |
7590 | { Bad_Opcode }, | |
85f10a01 | 7591 | /* 80 */ |
592d1631 L |
7592 | { Bad_Opcode }, |
7593 | { Bad_Opcode }, | |
7594 | { Bad_Opcode }, | |
7595 | { Bad_Opcode }, | |
7596 | { Bad_Opcode }, | |
3a2430e0 JB |
7597 | { "vpmacssww", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
7598 | { "vpmacsswd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, | |
7599 | { "vpmacssdql", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, | |
5dd85c99 | 7600 | /* 88 */ |
592d1631 L |
7601 | { Bad_Opcode }, |
7602 | { Bad_Opcode }, | |
7603 | { Bad_Opcode }, | |
7604 | { Bad_Opcode }, | |
7605 | { Bad_Opcode }, | |
7606 | { Bad_Opcode }, | |
3a2430e0 JB |
7607 | { "vpmacssdd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
7608 | { "vpmacssdqh", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, | |
5dd85c99 | 7609 | /* 90 */ |
592d1631 L |
7610 | { Bad_Opcode }, |
7611 | { Bad_Opcode }, | |
7612 | { Bad_Opcode }, | |
7613 | { Bad_Opcode }, | |
7614 | { Bad_Opcode }, | |
3a2430e0 JB |
7615 | { "vpmacsww", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
7616 | { "vpmacswd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, | |
7617 | { "vpmacsdql", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, | |
5dd85c99 | 7618 | /* 98 */ |
592d1631 L |
7619 | { Bad_Opcode }, |
7620 | { Bad_Opcode }, | |
7621 | { Bad_Opcode }, | |
7622 | { Bad_Opcode }, | |
7623 | { Bad_Opcode }, | |
7624 | { Bad_Opcode }, | |
3a2430e0 JB |
7625 | { "vpmacsdd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
7626 | { "vpmacsdqh", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, | |
5dd85c99 | 7627 | /* a0 */ |
592d1631 L |
7628 | { Bad_Opcode }, |
7629 | { Bad_Opcode }, | |
3a2430e0 JB |
7630 | { "vpcmov", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
7631 | { "vpperm", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, | |
592d1631 L |
7632 | { Bad_Opcode }, |
7633 | { Bad_Opcode }, | |
3a2430e0 | 7634 | { "vpmadcsswd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
592d1631 | 7635 | { Bad_Opcode }, |
5dd85c99 | 7636 | /* a8 */ |
592d1631 L |
7637 | { Bad_Opcode }, |
7638 | { Bad_Opcode }, | |
7639 | { Bad_Opcode }, | |
7640 | { Bad_Opcode }, | |
7641 | { Bad_Opcode }, | |
7642 | { Bad_Opcode }, | |
7643 | { Bad_Opcode }, | |
7644 | { Bad_Opcode }, | |
5dd85c99 | 7645 | /* b0 */ |
592d1631 L |
7646 | { Bad_Opcode }, |
7647 | { Bad_Opcode }, | |
7648 | { Bad_Opcode }, | |
7649 | { Bad_Opcode }, | |
7650 | { Bad_Opcode }, | |
7651 | { Bad_Opcode }, | |
3a2430e0 | 7652 | { "vpmadcswd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
592d1631 | 7653 | { Bad_Opcode }, |
5dd85c99 | 7654 | /* b8 */ |
592d1631 L |
7655 | { Bad_Opcode }, |
7656 | { Bad_Opcode }, | |
7657 | { Bad_Opcode }, | |
7658 | { Bad_Opcode }, | |
7659 | { Bad_Opcode }, | |
7660 | { Bad_Opcode }, | |
7661 | { Bad_Opcode }, | |
7662 | { Bad_Opcode }, | |
5dd85c99 | 7663 | /* c0 */ |
bf890a93 IT |
7664 | { "vprotb", { XM, Vex_2src_1, Ib }, 0 }, |
7665 | { "vprotw", { XM, Vex_2src_1, Ib }, 0 }, | |
7666 | { "vprotd", { XM, Vex_2src_1, Ib }, 0 }, | |
7667 | { "vprotq", { XM, Vex_2src_1, Ib }, 0 }, | |
592d1631 L |
7668 | { Bad_Opcode }, |
7669 | { Bad_Opcode }, | |
7670 | { Bad_Opcode }, | |
7671 | { Bad_Opcode }, | |
5dd85c99 | 7672 | /* c8 */ |
592d1631 L |
7673 | { Bad_Opcode }, |
7674 | { Bad_Opcode }, | |
7675 | { Bad_Opcode }, | |
7676 | { Bad_Opcode }, | |
ff688e1f L |
7677 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) }, |
7678 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) }, | |
7679 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) }, | |
7680 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) }, | |
5dd85c99 | 7681 | /* d0 */ |
592d1631 L |
7682 | { Bad_Opcode }, |
7683 | { Bad_Opcode }, | |
7684 | { Bad_Opcode }, | |
7685 | { Bad_Opcode }, | |
7686 | { Bad_Opcode }, | |
7687 | { Bad_Opcode }, | |
7688 | { Bad_Opcode }, | |
7689 | { Bad_Opcode }, | |
5dd85c99 | 7690 | /* d8 */ |
592d1631 L |
7691 | { Bad_Opcode }, |
7692 | { Bad_Opcode }, | |
7693 | { Bad_Opcode }, | |
7694 | { Bad_Opcode }, | |
7695 | { Bad_Opcode }, | |
7696 | { Bad_Opcode }, | |
7697 | { Bad_Opcode }, | |
7698 | { Bad_Opcode }, | |
5dd85c99 | 7699 | /* e0 */ |
592d1631 L |
7700 | { Bad_Opcode }, |
7701 | { Bad_Opcode }, | |
7702 | { Bad_Opcode }, | |
7703 | { Bad_Opcode }, | |
7704 | { Bad_Opcode }, | |
7705 | { Bad_Opcode }, | |
7706 | { Bad_Opcode }, | |
7707 | { Bad_Opcode }, | |
5dd85c99 | 7708 | /* e8 */ |
592d1631 L |
7709 | { Bad_Opcode }, |
7710 | { Bad_Opcode }, | |
7711 | { Bad_Opcode }, | |
7712 | { Bad_Opcode }, | |
ff688e1f L |
7713 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) }, |
7714 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) }, | |
7715 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) }, | |
7716 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) }, | |
5dd85c99 | 7717 | /* f0 */ |
592d1631 L |
7718 | { Bad_Opcode }, |
7719 | { Bad_Opcode }, | |
7720 | { Bad_Opcode }, | |
7721 | { Bad_Opcode }, | |
7722 | { Bad_Opcode }, | |
7723 | { Bad_Opcode }, | |
7724 | { Bad_Opcode }, | |
7725 | { Bad_Opcode }, | |
5dd85c99 | 7726 | /* f8 */ |
592d1631 L |
7727 | { Bad_Opcode }, |
7728 | { Bad_Opcode }, | |
7729 | { Bad_Opcode }, | |
7730 | { Bad_Opcode }, | |
7731 | { Bad_Opcode }, | |
7732 | { Bad_Opcode }, | |
7733 | { Bad_Opcode }, | |
7734 | { Bad_Opcode }, | |
5dd85c99 SP |
7735 | }, |
7736 | /* XOP_09 */ | |
7737 | { | |
7738 | /* 00 */ | |
592d1631 | 7739 | { Bad_Opcode }, |
2a2a0f38 QN |
7740 | { REG_TABLE (REG_XOP_TBM_01) }, |
7741 | { REG_TABLE (REG_XOP_TBM_02) }, | |
592d1631 L |
7742 | { Bad_Opcode }, |
7743 | { Bad_Opcode }, | |
7744 | { Bad_Opcode }, | |
7745 | { Bad_Opcode }, | |
7746 | { Bad_Opcode }, | |
5dd85c99 | 7747 | /* 08 */ |
592d1631 L |
7748 | { Bad_Opcode }, |
7749 | { Bad_Opcode }, | |
7750 | { Bad_Opcode }, | |
7751 | { Bad_Opcode }, | |
7752 | { Bad_Opcode }, | |
7753 | { Bad_Opcode }, | |
7754 | { Bad_Opcode }, | |
7755 | { Bad_Opcode }, | |
5dd85c99 | 7756 | /* 10 */ |
592d1631 L |
7757 | { Bad_Opcode }, |
7758 | { Bad_Opcode }, | |
5dd85c99 | 7759 | { REG_TABLE (REG_XOP_LWPCB) }, |
592d1631 L |
7760 | { Bad_Opcode }, |
7761 | { Bad_Opcode }, | |
7762 | { Bad_Opcode }, | |
7763 | { Bad_Opcode }, | |
7764 | { Bad_Opcode }, | |
5dd85c99 | 7765 | /* 18 */ |
592d1631 L |
7766 | { Bad_Opcode }, |
7767 | { Bad_Opcode }, | |
7768 | { Bad_Opcode }, | |
7769 | { Bad_Opcode }, | |
7770 | { Bad_Opcode }, | |
7771 | { Bad_Opcode }, | |
7772 | { Bad_Opcode }, | |
7773 | { Bad_Opcode }, | |
5dd85c99 | 7774 | /* 20 */ |
592d1631 L |
7775 | { Bad_Opcode }, |
7776 | { Bad_Opcode }, | |
7777 | { Bad_Opcode }, | |
7778 | { Bad_Opcode }, | |
7779 | { Bad_Opcode }, | |
7780 | { Bad_Opcode }, | |
7781 | { Bad_Opcode }, | |
7782 | { Bad_Opcode }, | |
5dd85c99 | 7783 | /* 28 */ |
592d1631 L |
7784 | { Bad_Opcode }, |
7785 | { Bad_Opcode }, | |
7786 | { Bad_Opcode }, | |
7787 | { Bad_Opcode }, | |
7788 | { Bad_Opcode }, | |
7789 | { Bad_Opcode }, | |
7790 | { Bad_Opcode }, | |
7791 | { Bad_Opcode }, | |
5dd85c99 | 7792 | /* 30 */ |
592d1631 L |
7793 | { Bad_Opcode }, |
7794 | { Bad_Opcode }, | |
7795 | { Bad_Opcode }, | |
7796 | { Bad_Opcode }, | |
7797 | { Bad_Opcode }, | |
7798 | { Bad_Opcode }, | |
7799 | { Bad_Opcode }, | |
7800 | { Bad_Opcode }, | |
5dd85c99 | 7801 | /* 38 */ |
592d1631 L |
7802 | { Bad_Opcode }, |
7803 | { Bad_Opcode }, | |
7804 | { Bad_Opcode }, | |
7805 | { Bad_Opcode }, | |
7806 | { Bad_Opcode }, | |
7807 | { Bad_Opcode }, | |
7808 | { Bad_Opcode }, | |
7809 | { Bad_Opcode }, | |
5dd85c99 | 7810 | /* 40 */ |
592d1631 L |
7811 | { Bad_Opcode }, |
7812 | { Bad_Opcode }, | |
7813 | { Bad_Opcode }, | |
7814 | { Bad_Opcode }, | |
7815 | { Bad_Opcode }, | |
7816 | { Bad_Opcode }, | |
7817 | { Bad_Opcode }, | |
7818 | { Bad_Opcode }, | |
5dd85c99 | 7819 | /* 48 */ |
592d1631 L |
7820 | { Bad_Opcode }, |
7821 | { Bad_Opcode }, | |
7822 | { Bad_Opcode }, | |
7823 | { Bad_Opcode }, | |
7824 | { Bad_Opcode }, | |
7825 | { Bad_Opcode }, | |
7826 | { Bad_Opcode }, | |
7827 | { Bad_Opcode }, | |
5dd85c99 | 7828 | /* 50 */ |
592d1631 L |
7829 | { Bad_Opcode }, |
7830 | { Bad_Opcode }, | |
7831 | { Bad_Opcode }, | |
7832 | { Bad_Opcode }, | |
7833 | { Bad_Opcode }, | |
7834 | { Bad_Opcode }, | |
7835 | { Bad_Opcode }, | |
7836 | { Bad_Opcode }, | |
5dd85c99 | 7837 | /* 58 */ |
592d1631 L |
7838 | { Bad_Opcode }, |
7839 | { Bad_Opcode }, | |
7840 | { Bad_Opcode }, | |
7841 | { Bad_Opcode }, | |
7842 | { Bad_Opcode }, | |
7843 | { Bad_Opcode }, | |
7844 | { Bad_Opcode }, | |
7845 | { Bad_Opcode }, | |
5dd85c99 | 7846 | /* 60 */ |
592d1631 L |
7847 | { Bad_Opcode }, |
7848 | { Bad_Opcode }, | |
7849 | { Bad_Opcode }, | |
7850 | { Bad_Opcode }, | |
7851 | { Bad_Opcode }, | |
7852 | { Bad_Opcode }, | |
7853 | { Bad_Opcode }, | |
7854 | { Bad_Opcode }, | |
5dd85c99 | 7855 | /* 68 */ |
592d1631 L |
7856 | { Bad_Opcode }, |
7857 | { Bad_Opcode }, | |
7858 | { Bad_Opcode }, | |
7859 | { Bad_Opcode }, | |
7860 | { Bad_Opcode }, | |
7861 | { Bad_Opcode }, | |
7862 | { Bad_Opcode }, | |
7863 | { Bad_Opcode }, | |
5dd85c99 | 7864 | /* 70 */ |
592d1631 L |
7865 | { Bad_Opcode }, |
7866 | { Bad_Opcode }, | |
7867 | { Bad_Opcode }, | |
7868 | { Bad_Opcode }, | |
7869 | { Bad_Opcode }, | |
7870 | { Bad_Opcode }, | |
7871 | { Bad_Opcode }, | |
7872 | { Bad_Opcode }, | |
5dd85c99 | 7873 | /* 78 */ |
592d1631 L |
7874 | { Bad_Opcode }, |
7875 | { Bad_Opcode }, | |
7876 | { Bad_Opcode }, | |
7877 | { Bad_Opcode }, | |
7878 | { Bad_Opcode }, | |
7879 | { Bad_Opcode }, | |
7880 | { Bad_Opcode }, | |
7881 | { Bad_Opcode }, | |
5dd85c99 | 7882 | /* 80 */ |
592a252b L |
7883 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) }, |
7884 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) }, | |
bf890a93 IT |
7885 | { "vfrczss", { XM, EXd }, 0 }, |
7886 | { "vfrczsd", { XM, EXq }, 0 }, | |
592d1631 L |
7887 | { Bad_Opcode }, |
7888 | { Bad_Opcode }, | |
7889 | { Bad_Opcode }, | |
7890 | { Bad_Opcode }, | |
5dd85c99 | 7891 | /* 88 */ |
592d1631 L |
7892 | { Bad_Opcode }, |
7893 | { Bad_Opcode }, | |
7894 | { Bad_Opcode }, | |
7895 | { Bad_Opcode }, | |
7896 | { Bad_Opcode }, | |
7897 | { Bad_Opcode }, | |
7898 | { Bad_Opcode }, | |
7899 | { Bad_Opcode }, | |
5dd85c99 | 7900 | /* 90 */ |
bf890a93 IT |
7901 | { "vprotb", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, |
7902 | { "vprotw", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
7903 | { "vprotd", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
7904 | { "vprotq", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
7905 | { "vpshlb", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
7906 | { "vpshlw", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
7907 | { "vpshld", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
7908 | { "vpshlq", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
5dd85c99 | 7909 | /* 98 */ |
bf890a93 IT |
7910 | { "vpshab", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, |
7911 | { "vpshaw", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
7912 | { "vpshad", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
7913 | { "vpshaq", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
592d1631 L |
7914 | { Bad_Opcode }, |
7915 | { Bad_Opcode }, | |
7916 | { Bad_Opcode }, | |
7917 | { Bad_Opcode }, | |
5dd85c99 | 7918 | /* a0 */ |
592d1631 L |
7919 | { Bad_Opcode }, |
7920 | { Bad_Opcode }, | |
7921 | { Bad_Opcode }, | |
7922 | { Bad_Opcode }, | |
7923 | { Bad_Opcode }, | |
7924 | { Bad_Opcode }, | |
7925 | { Bad_Opcode }, | |
7926 | { Bad_Opcode }, | |
5dd85c99 | 7927 | /* a8 */ |
592d1631 L |
7928 | { Bad_Opcode }, |
7929 | { Bad_Opcode }, | |
7930 | { Bad_Opcode }, | |
7931 | { Bad_Opcode }, | |
7932 | { Bad_Opcode }, | |
7933 | { Bad_Opcode }, | |
7934 | { Bad_Opcode }, | |
7935 | { Bad_Opcode }, | |
5dd85c99 | 7936 | /* b0 */ |
592d1631 L |
7937 | { Bad_Opcode }, |
7938 | { Bad_Opcode }, | |
7939 | { Bad_Opcode }, | |
7940 | { Bad_Opcode }, | |
7941 | { Bad_Opcode }, | |
7942 | { Bad_Opcode }, | |
7943 | { Bad_Opcode }, | |
7944 | { Bad_Opcode }, | |
5dd85c99 | 7945 | /* b8 */ |
592d1631 L |
7946 | { Bad_Opcode }, |
7947 | { Bad_Opcode }, | |
7948 | { Bad_Opcode }, | |
7949 | { Bad_Opcode }, | |
7950 | { Bad_Opcode }, | |
7951 | { Bad_Opcode }, | |
7952 | { Bad_Opcode }, | |
7953 | { Bad_Opcode }, | |
5dd85c99 | 7954 | /* c0 */ |
592d1631 | 7955 | { Bad_Opcode }, |
bf890a93 IT |
7956 | { "vphaddbw", { XM, EXxmm }, 0 }, |
7957 | { "vphaddbd", { XM, EXxmm }, 0 }, | |
7958 | { "vphaddbq", { XM, EXxmm }, 0 }, | |
592d1631 L |
7959 | { Bad_Opcode }, |
7960 | { Bad_Opcode }, | |
bf890a93 IT |
7961 | { "vphaddwd", { XM, EXxmm }, 0 }, |
7962 | { "vphaddwq", { XM, EXxmm }, 0 }, | |
5dd85c99 | 7963 | /* c8 */ |
592d1631 L |
7964 | { Bad_Opcode }, |
7965 | { Bad_Opcode }, | |
7966 | { Bad_Opcode }, | |
bf890a93 | 7967 | { "vphadddq", { XM, EXxmm }, 0 }, |
592d1631 L |
7968 | { Bad_Opcode }, |
7969 | { Bad_Opcode }, | |
7970 | { Bad_Opcode }, | |
7971 | { Bad_Opcode }, | |
5dd85c99 | 7972 | /* d0 */ |
592d1631 | 7973 | { Bad_Opcode }, |
bf890a93 IT |
7974 | { "vphaddubw", { XM, EXxmm }, 0 }, |
7975 | { "vphaddubd", { XM, EXxmm }, 0 }, | |
7976 | { "vphaddubq", { XM, EXxmm }, 0 }, | |
592d1631 L |
7977 | { Bad_Opcode }, |
7978 | { Bad_Opcode }, | |
bf890a93 IT |
7979 | { "vphadduwd", { XM, EXxmm }, 0 }, |
7980 | { "vphadduwq", { XM, EXxmm }, 0 }, | |
5dd85c99 | 7981 | /* d8 */ |
592d1631 L |
7982 | { Bad_Opcode }, |
7983 | { Bad_Opcode }, | |
7984 | { Bad_Opcode }, | |
bf890a93 | 7985 | { "vphaddudq", { XM, EXxmm }, 0 }, |
592d1631 L |
7986 | { Bad_Opcode }, |
7987 | { Bad_Opcode }, | |
7988 | { Bad_Opcode }, | |
7989 | { Bad_Opcode }, | |
5dd85c99 | 7990 | /* e0 */ |
592d1631 | 7991 | { Bad_Opcode }, |
bf890a93 IT |
7992 | { "vphsubbw", { XM, EXxmm }, 0 }, |
7993 | { "vphsubwd", { XM, EXxmm }, 0 }, | |
7994 | { "vphsubdq", { XM, EXxmm }, 0 }, | |
592d1631 L |
7995 | { Bad_Opcode }, |
7996 | { Bad_Opcode }, | |
7997 | { Bad_Opcode }, | |
7998 | { Bad_Opcode }, | |
4e7d34a6 | 7999 | /* e8 */ |
592d1631 L |
8000 | { Bad_Opcode }, |
8001 | { Bad_Opcode }, | |
8002 | { Bad_Opcode }, | |
8003 | { Bad_Opcode }, | |
8004 | { Bad_Opcode }, | |
8005 | { Bad_Opcode }, | |
8006 | { Bad_Opcode }, | |
8007 | { Bad_Opcode }, | |
4e7d34a6 | 8008 | /* f0 */ |
592d1631 L |
8009 | { Bad_Opcode }, |
8010 | { Bad_Opcode }, | |
8011 | { Bad_Opcode }, | |
8012 | { Bad_Opcode }, | |
8013 | { Bad_Opcode }, | |
8014 | { Bad_Opcode }, | |
8015 | { Bad_Opcode }, | |
8016 | { Bad_Opcode }, | |
4e7d34a6 | 8017 | /* f8 */ |
592d1631 L |
8018 | { Bad_Opcode }, |
8019 | { Bad_Opcode }, | |
8020 | { Bad_Opcode }, | |
8021 | { Bad_Opcode }, | |
8022 | { Bad_Opcode }, | |
8023 | { Bad_Opcode }, | |
8024 | { Bad_Opcode }, | |
8025 | { Bad_Opcode }, | |
4e7d34a6 | 8026 | }, |
f88c9eb0 | 8027 | /* XOP_0A */ |
4e7d34a6 L |
8028 | { |
8029 | /* 00 */ | |
592d1631 L |
8030 | { Bad_Opcode }, |
8031 | { Bad_Opcode }, | |
8032 | { Bad_Opcode }, | |
8033 | { Bad_Opcode }, | |
8034 | { Bad_Opcode }, | |
8035 | { Bad_Opcode }, | |
8036 | { Bad_Opcode }, | |
8037 | { Bad_Opcode }, | |
4e7d34a6 | 8038 | /* 08 */ |
592d1631 L |
8039 | { Bad_Opcode }, |
8040 | { Bad_Opcode }, | |
8041 | { Bad_Opcode }, | |
8042 | { Bad_Opcode }, | |
8043 | { Bad_Opcode }, | |
8044 | { Bad_Opcode }, | |
8045 | { Bad_Opcode }, | |
8046 | { Bad_Opcode }, | |
4e7d34a6 | 8047 | /* 10 */ |
c1dc7af5 | 8048 | { "bextrS", { Gdq, Edq, Id }, 0 }, |
592d1631 | 8049 | { Bad_Opcode }, |
f88c9eb0 | 8050 | { REG_TABLE (REG_XOP_LWP) }, |
592d1631 L |
8051 | { Bad_Opcode }, |
8052 | { Bad_Opcode }, | |
8053 | { Bad_Opcode }, | |
8054 | { Bad_Opcode }, | |
8055 | { Bad_Opcode }, | |
4e7d34a6 | 8056 | /* 18 */ |
592d1631 L |
8057 | { Bad_Opcode }, |
8058 | { Bad_Opcode }, | |
8059 | { Bad_Opcode }, | |
8060 | { Bad_Opcode }, | |
8061 | { Bad_Opcode }, | |
8062 | { Bad_Opcode }, | |
8063 | { Bad_Opcode }, | |
8064 | { Bad_Opcode }, | |
4e7d34a6 | 8065 | /* 20 */ |
592d1631 L |
8066 | { Bad_Opcode }, |
8067 | { Bad_Opcode }, | |
8068 | { Bad_Opcode }, | |
8069 | { Bad_Opcode }, | |
8070 | { Bad_Opcode }, | |
8071 | { Bad_Opcode }, | |
8072 | { Bad_Opcode }, | |
8073 | { Bad_Opcode }, | |
4e7d34a6 | 8074 | /* 28 */ |
592d1631 L |
8075 | { Bad_Opcode }, |
8076 | { Bad_Opcode }, | |
8077 | { Bad_Opcode }, | |
8078 | { Bad_Opcode }, | |
8079 | { Bad_Opcode }, | |
8080 | { Bad_Opcode }, | |
8081 | { Bad_Opcode }, | |
8082 | { Bad_Opcode }, | |
4e7d34a6 | 8083 | /* 30 */ |
592d1631 L |
8084 | { Bad_Opcode }, |
8085 | { Bad_Opcode }, | |
8086 | { Bad_Opcode }, | |
8087 | { Bad_Opcode }, | |
8088 | { Bad_Opcode }, | |
8089 | { Bad_Opcode }, | |
8090 | { Bad_Opcode }, | |
8091 | { Bad_Opcode }, | |
c0f3af97 | 8092 | /* 38 */ |
592d1631 L |
8093 | { Bad_Opcode }, |
8094 | { Bad_Opcode }, | |
8095 | { Bad_Opcode }, | |
8096 | { Bad_Opcode }, | |
8097 | { Bad_Opcode }, | |
8098 | { Bad_Opcode }, | |
8099 | { Bad_Opcode }, | |
8100 | { Bad_Opcode }, | |
c0f3af97 | 8101 | /* 40 */ |
592d1631 L |
8102 | { Bad_Opcode }, |
8103 | { Bad_Opcode }, | |
8104 | { Bad_Opcode }, | |
8105 | { Bad_Opcode }, | |
8106 | { Bad_Opcode }, | |
8107 | { Bad_Opcode }, | |
8108 | { Bad_Opcode }, | |
8109 | { Bad_Opcode }, | |
c1e679ec | 8110 | /* 48 */ |
592d1631 L |
8111 | { Bad_Opcode }, |
8112 | { Bad_Opcode }, | |
8113 | { Bad_Opcode }, | |
8114 | { Bad_Opcode }, | |
8115 | { Bad_Opcode }, | |
8116 | { Bad_Opcode }, | |
8117 | { Bad_Opcode }, | |
8118 | { Bad_Opcode }, | |
c1e679ec | 8119 | /* 50 */ |
592d1631 L |
8120 | { Bad_Opcode }, |
8121 | { Bad_Opcode }, | |
8122 | { Bad_Opcode }, | |
8123 | { Bad_Opcode }, | |
8124 | { Bad_Opcode }, | |
8125 | { Bad_Opcode }, | |
8126 | { Bad_Opcode }, | |
8127 | { Bad_Opcode }, | |
4e7d34a6 | 8128 | /* 58 */ |
592d1631 L |
8129 | { Bad_Opcode }, |
8130 | { Bad_Opcode }, | |
8131 | { Bad_Opcode }, | |
8132 | { Bad_Opcode }, | |
8133 | { Bad_Opcode }, | |
8134 | { Bad_Opcode }, | |
8135 | { Bad_Opcode }, | |
8136 | { Bad_Opcode }, | |
4e7d34a6 | 8137 | /* 60 */ |
592d1631 L |
8138 | { Bad_Opcode }, |
8139 | { Bad_Opcode }, | |
8140 | { Bad_Opcode }, | |
8141 | { Bad_Opcode }, | |
8142 | { Bad_Opcode }, | |
8143 | { Bad_Opcode }, | |
8144 | { Bad_Opcode }, | |
8145 | { Bad_Opcode }, | |
4e7d34a6 | 8146 | /* 68 */ |
592d1631 L |
8147 | { Bad_Opcode }, |
8148 | { Bad_Opcode }, | |
8149 | { Bad_Opcode }, | |
8150 | { Bad_Opcode }, | |
8151 | { Bad_Opcode }, | |
8152 | { Bad_Opcode }, | |
8153 | { Bad_Opcode }, | |
8154 | { Bad_Opcode }, | |
4e7d34a6 | 8155 | /* 70 */ |
592d1631 L |
8156 | { Bad_Opcode }, |
8157 | { Bad_Opcode }, | |
8158 | { Bad_Opcode }, | |
8159 | { Bad_Opcode }, | |
8160 | { Bad_Opcode }, | |
8161 | { Bad_Opcode }, | |
8162 | { Bad_Opcode }, | |
8163 | { Bad_Opcode }, | |
4e7d34a6 | 8164 | /* 78 */ |
592d1631 L |
8165 | { Bad_Opcode }, |
8166 | { Bad_Opcode }, | |
8167 | { Bad_Opcode }, | |
8168 | { Bad_Opcode }, | |
8169 | { Bad_Opcode }, | |
8170 | { Bad_Opcode }, | |
8171 | { Bad_Opcode }, | |
8172 | { Bad_Opcode }, | |
4e7d34a6 | 8173 | /* 80 */ |
592d1631 L |
8174 | { Bad_Opcode }, |
8175 | { Bad_Opcode }, | |
8176 | { Bad_Opcode }, | |
8177 | { Bad_Opcode }, | |
8178 | { Bad_Opcode }, | |
8179 | { Bad_Opcode }, | |
8180 | { Bad_Opcode }, | |
8181 | { Bad_Opcode }, | |
4e7d34a6 | 8182 | /* 88 */ |
592d1631 L |
8183 | { Bad_Opcode }, |
8184 | { Bad_Opcode }, | |
8185 | { Bad_Opcode }, | |
8186 | { Bad_Opcode }, | |
8187 | { Bad_Opcode }, | |
8188 | { Bad_Opcode }, | |
8189 | { Bad_Opcode }, | |
8190 | { Bad_Opcode }, | |
4e7d34a6 | 8191 | /* 90 */ |
592d1631 L |
8192 | { Bad_Opcode }, |
8193 | { Bad_Opcode }, | |
8194 | { Bad_Opcode }, | |
8195 | { Bad_Opcode }, | |
8196 | { Bad_Opcode }, | |
8197 | { Bad_Opcode }, | |
8198 | { Bad_Opcode }, | |
8199 | { Bad_Opcode }, | |
4e7d34a6 | 8200 | /* 98 */ |
592d1631 L |
8201 | { Bad_Opcode }, |
8202 | { Bad_Opcode }, | |
8203 | { Bad_Opcode }, | |
8204 | { Bad_Opcode }, | |
8205 | { Bad_Opcode }, | |
8206 | { Bad_Opcode }, | |
8207 | { Bad_Opcode }, | |
8208 | { Bad_Opcode }, | |
4e7d34a6 | 8209 | /* a0 */ |
592d1631 L |
8210 | { Bad_Opcode }, |
8211 | { Bad_Opcode }, | |
8212 | { Bad_Opcode }, | |
8213 | { Bad_Opcode }, | |
8214 | { Bad_Opcode }, | |
8215 | { Bad_Opcode }, | |
8216 | { Bad_Opcode }, | |
8217 | { Bad_Opcode }, | |
4e7d34a6 | 8218 | /* a8 */ |
592d1631 L |
8219 | { Bad_Opcode }, |
8220 | { Bad_Opcode }, | |
8221 | { Bad_Opcode }, | |
8222 | { Bad_Opcode }, | |
8223 | { Bad_Opcode }, | |
8224 | { Bad_Opcode }, | |
8225 | { Bad_Opcode }, | |
8226 | { Bad_Opcode }, | |
d5d7db8e | 8227 | /* b0 */ |
592d1631 L |
8228 | { Bad_Opcode }, |
8229 | { Bad_Opcode }, | |
8230 | { Bad_Opcode }, | |
8231 | { Bad_Opcode }, | |
8232 | { Bad_Opcode }, | |
8233 | { Bad_Opcode }, | |
8234 | { Bad_Opcode }, | |
8235 | { Bad_Opcode }, | |
85f10a01 | 8236 | /* b8 */ |
592d1631 L |
8237 | { Bad_Opcode }, |
8238 | { Bad_Opcode }, | |
8239 | { Bad_Opcode }, | |
8240 | { Bad_Opcode }, | |
8241 | { Bad_Opcode }, | |
8242 | { Bad_Opcode }, | |
8243 | { Bad_Opcode }, | |
8244 | { Bad_Opcode }, | |
85f10a01 | 8245 | /* c0 */ |
592d1631 L |
8246 | { Bad_Opcode }, |
8247 | { Bad_Opcode }, | |
8248 | { Bad_Opcode }, | |
8249 | { Bad_Opcode }, | |
8250 | { Bad_Opcode }, | |
8251 | { Bad_Opcode }, | |
8252 | { Bad_Opcode }, | |
8253 | { Bad_Opcode }, | |
85f10a01 | 8254 | /* c8 */ |
592d1631 L |
8255 | { Bad_Opcode }, |
8256 | { Bad_Opcode }, | |
8257 | { Bad_Opcode }, | |
8258 | { Bad_Opcode }, | |
8259 | { Bad_Opcode }, | |
8260 | { Bad_Opcode }, | |
8261 | { Bad_Opcode }, | |
8262 | { Bad_Opcode }, | |
85f10a01 | 8263 | /* d0 */ |
592d1631 L |
8264 | { Bad_Opcode }, |
8265 | { Bad_Opcode }, | |
8266 | { Bad_Opcode }, | |
8267 | { Bad_Opcode }, | |
8268 | { Bad_Opcode }, | |
8269 | { Bad_Opcode }, | |
8270 | { Bad_Opcode }, | |
8271 | { Bad_Opcode }, | |
85f10a01 | 8272 | /* d8 */ |
592d1631 L |
8273 | { Bad_Opcode }, |
8274 | { Bad_Opcode }, | |
8275 | { Bad_Opcode }, | |
8276 | { Bad_Opcode }, | |
8277 | { Bad_Opcode }, | |
8278 | { Bad_Opcode }, | |
8279 | { Bad_Opcode }, | |
8280 | { Bad_Opcode }, | |
85f10a01 | 8281 | /* e0 */ |
592d1631 L |
8282 | { Bad_Opcode }, |
8283 | { Bad_Opcode }, | |
8284 | { Bad_Opcode }, | |
8285 | { Bad_Opcode }, | |
8286 | { Bad_Opcode }, | |
8287 | { Bad_Opcode }, | |
8288 | { Bad_Opcode }, | |
8289 | { Bad_Opcode }, | |
85f10a01 | 8290 | /* e8 */ |
592d1631 L |
8291 | { Bad_Opcode }, |
8292 | { Bad_Opcode }, | |
8293 | { Bad_Opcode }, | |
8294 | { Bad_Opcode }, | |
8295 | { Bad_Opcode }, | |
8296 | { Bad_Opcode }, | |
8297 | { Bad_Opcode }, | |
8298 | { Bad_Opcode }, | |
85f10a01 | 8299 | /* f0 */ |
592d1631 L |
8300 | { Bad_Opcode }, |
8301 | { Bad_Opcode }, | |
8302 | { Bad_Opcode }, | |
8303 | { Bad_Opcode }, | |
8304 | { Bad_Opcode }, | |
8305 | { Bad_Opcode }, | |
8306 | { Bad_Opcode }, | |
8307 | { Bad_Opcode }, | |
85f10a01 | 8308 | /* f8 */ |
592d1631 L |
8309 | { Bad_Opcode }, |
8310 | { Bad_Opcode }, | |
8311 | { Bad_Opcode }, | |
8312 | { Bad_Opcode }, | |
8313 | { Bad_Opcode }, | |
8314 | { Bad_Opcode }, | |
8315 | { Bad_Opcode }, | |
8316 | { Bad_Opcode }, | |
85f10a01 | 8317 | }, |
c0f3af97 L |
8318 | }; |
8319 | ||
8320 | static const struct dis386 vex_table[][256] = { | |
8321 | /* VEX_0F */ | |
85f10a01 MM |
8322 | { |
8323 | /* 00 */ | |
592d1631 L |
8324 | { Bad_Opcode }, |
8325 | { Bad_Opcode }, | |
8326 | { Bad_Opcode }, | |
8327 | { Bad_Opcode }, | |
8328 | { Bad_Opcode }, | |
8329 | { Bad_Opcode }, | |
8330 | { Bad_Opcode }, | |
8331 | { Bad_Opcode }, | |
85f10a01 | 8332 | /* 08 */ |
592d1631 L |
8333 | { Bad_Opcode }, |
8334 | { Bad_Opcode }, | |
8335 | { Bad_Opcode }, | |
8336 | { Bad_Opcode }, | |
8337 | { Bad_Opcode }, | |
8338 | { Bad_Opcode }, | |
8339 | { Bad_Opcode }, | |
8340 | { Bad_Opcode }, | |
c0f3af97 | 8341 | /* 10 */ |
592a252b L |
8342 | { PREFIX_TABLE (PREFIX_VEX_0F10) }, |
8343 | { PREFIX_TABLE (PREFIX_VEX_0F11) }, | |
8344 | { PREFIX_TABLE (PREFIX_VEX_0F12) }, | |
8345 | { MOD_TABLE (MOD_VEX_0F13) }, | |
bf926894 JB |
8346 | { "vunpcklpX", { XM, Vex, EXx }, PREFIX_OPCODE }, |
8347 | { "vunpckhpX", { XM, Vex, EXx }, PREFIX_OPCODE }, | |
592a252b L |
8348 | { PREFIX_TABLE (PREFIX_VEX_0F16) }, |
8349 | { MOD_TABLE (MOD_VEX_0F17) }, | |
c0f3af97 | 8350 | /* 18 */ |
592d1631 L |
8351 | { Bad_Opcode }, |
8352 | { Bad_Opcode }, | |
8353 | { Bad_Opcode }, | |
8354 | { Bad_Opcode }, | |
8355 | { Bad_Opcode }, | |
8356 | { Bad_Opcode }, | |
8357 | { Bad_Opcode }, | |
8358 | { Bad_Opcode }, | |
c0f3af97 | 8359 | /* 20 */ |
592d1631 L |
8360 | { Bad_Opcode }, |
8361 | { Bad_Opcode }, | |
8362 | { Bad_Opcode }, | |
8363 | { Bad_Opcode }, | |
8364 | { Bad_Opcode }, | |
8365 | { Bad_Opcode }, | |
8366 | { Bad_Opcode }, | |
8367 | { Bad_Opcode }, | |
c0f3af97 | 8368 | /* 28 */ |
bf926894 JB |
8369 | { "vmovapX", { XM, EXx }, PREFIX_OPCODE }, |
8370 | { "vmovapX", { EXxS, XM }, PREFIX_OPCODE }, | |
592a252b L |
8371 | { PREFIX_TABLE (PREFIX_VEX_0F2A) }, |
8372 | { MOD_TABLE (MOD_VEX_0F2B) }, | |
8373 | { PREFIX_TABLE (PREFIX_VEX_0F2C) }, | |
8374 | { PREFIX_TABLE (PREFIX_VEX_0F2D) }, | |
8375 | { PREFIX_TABLE (PREFIX_VEX_0F2E) }, | |
8376 | { PREFIX_TABLE (PREFIX_VEX_0F2F) }, | |
85f10a01 | 8377 | /* 30 */ |
592d1631 L |
8378 | { Bad_Opcode }, |
8379 | { Bad_Opcode }, | |
8380 | { Bad_Opcode }, | |
8381 | { Bad_Opcode }, | |
8382 | { Bad_Opcode }, | |
8383 | { Bad_Opcode }, | |
8384 | { Bad_Opcode }, | |
8385 | { Bad_Opcode }, | |
4e7d34a6 | 8386 | /* 38 */ |
592d1631 L |
8387 | { Bad_Opcode }, |
8388 | { Bad_Opcode }, | |
8389 | { Bad_Opcode }, | |
8390 | { Bad_Opcode }, | |
8391 | { Bad_Opcode }, | |
8392 | { Bad_Opcode }, | |
8393 | { Bad_Opcode }, | |
8394 | { Bad_Opcode }, | |
d5d7db8e | 8395 | /* 40 */ |
592d1631 | 8396 | { Bad_Opcode }, |
43234a1e L |
8397 | { PREFIX_TABLE (PREFIX_VEX_0F41) }, |
8398 | { PREFIX_TABLE (PREFIX_VEX_0F42) }, | |
592d1631 | 8399 | { Bad_Opcode }, |
43234a1e L |
8400 | { PREFIX_TABLE (PREFIX_VEX_0F44) }, |
8401 | { PREFIX_TABLE (PREFIX_VEX_0F45) }, | |
8402 | { PREFIX_TABLE (PREFIX_VEX_0F46) }, | |
8403 | { PREFIX_TABLE (PREFIX_VEX_0F47) }, | |
85f10a01 | 8404 | /* 48 */ |
592d1631 L |
8405 | { Bad_Opcode }, |
8406 | { Bad_Opcode }, | |
1ba585e8 | 8407 | { PREFIX_TABLE (PREFIX_VEX_0F4A) }, |
43234a1e | 8408 | { PREFIX_TABLE (PREFIX_VEX_0F4B) }, |
592d1631 L |
8409 | { Bad_Opcode }, |
8410 | { Bad_Opcode }, | |
8411 | { Bad_Opcode }, | |
8412 | { Bad_Opcode }, | |
d5d7db8e | 8413 | /* 50 */ |
592a252b L |
8414 | { MOD_TABLE (MOD_VEX_0F50) }, |
8415 | { PREFIX_TABLE (PREFIX_VEX_0F51) }, | |
8416 | { PREFIX_TABLE (PREFIX_VEX_0F52) }, | |
8417 | { PREFIX_TABLE (PREFIX_VEX_0F53) }, | |
bf926894 JB |
8418 | { "vandpX", { XM, Vex, EXx }, PREFIX_OPCODE }, |
8419 | { "vandnpX", { XM, Vex, EXx }, PREFIX_OPCODE }, | |
8420 | { "vorpX", { XM, Vex, EXx }, PREFIX_OPCODE }, | |
8421 | { "vxorpX", { XM, Vex, EXx }, PREFIX_OPCODE }, | |
c0f3af97 | 8422 | /* 58 */ |
592a252b L |
8423 | { PREFIX_TABLE (PREFIX_VEX_0F58) }, |
8424 | { PREFIX_TABLE (PREFIX_VEX_0F59) }, | |
8425 | { PREFIX_TABLE (PREFIX_VEX_0F5A) }, | |
8426 | { PREFIX_TABLE (PREFIX_VEX_0F5B) }, | |
8427 | { PREFIX_TABLE (PREFIX_VEX_0F5C) }, | |
8428 | { PREFIX_TABLE (PREFIX_VEX_0F5D) }, | |
8429 | { PREFIX_TABLE (PREFIX_VEX_0F5E) }, | |
8430 | { PREFIX_TABLE (PREFIX_VEX_0F5F) }, | |
c0f3af97 | 8431 | /* 60 */ |
592a252b L |
8432 | { PREFIX_TABLE (PREFIX_VEX_0F60) }, |
8433 | { PREFIX_TABLE (PREFIX_VEX_0F61) }, | |
8434 | { PREFIX_TABLE (PREFIX_VEX_0F62) }, | |
8435 | { PREFIX_TABLE (PREFIX_VEX_0F63) }, | |
8436 | { PREFIX_TABLE (PREFIX_VEX_0F64) }, | |
8437 | { PREFIX_TABLE (PREFIX_VEX_0F65) }, | |
8438 | { PREFIX_TABLE (PREFIX_VEX_0F66) }, | |
8439 | { PREFIX_TABLE (PREFIX_VEX_0F67) }, | |
c0f3af97 | 8440 | /* 68 */ |
592a252b L |
8441 | { PREFIX_TABLE (PREFIX_VEX_0F68) }, |
8442 | { PREFIX_TABLE (PREFIX_VEX_0F69) }, | |
8443 | { PREFIX_TABLE (PREFIX_VEX_0F6A) }, | |
8444 | { PREFIX_TABLE (PREFIX_VEX_0F6B) }, | |
8445 | { PREFIX_TABLE (PREFIX_VEX_0F6C) }, | |
8446 | { PREFIX_TABLE (PREFIX_VEX_0F6D) }, | |
8447 | { PREFIX_TABLE (PREFIX_VEX_0F6E) }, | |
8448 | { PREFIX_TABLE (PREFIX_VEX_0F6F) }, | |
c0f3af97 | 8449 | /* 70 */ |
592a252b L |
8450 | { PREFIX_TABLE (PREFIX_VEX_0F70) }, |
8451 | { REG_TABLE (REG_VEX_0F71) }, | |
8452 | { REG_TABLE (REG_VEX_0F72) }, | |
8453 | { REG_TABLE (REG_VEX_0F73) }, | |
8454 | { PREFIX_TABLE (PREFIX_VEX_0F74) }, | |
8455 | { PREFIX_TABLE (PREFIX_VEX_0F75) }, | |
8456 | { PREFIX_TABLE (PREFIX_VEX_0F76) }, | |
8457 | { PREFIX_TABLE (PREFIX_VEX_0F77) }, | |
c0f3af97 | 8458 | /* 78 */ |
592d1631 L |
8459 | { Bad_Opcode }, |
8460 | { Bad_Opcode }, | |
8461 | { Bad_Opcode }, | |
8462 | { Bad_Opcode }, | |
592a252b L |
8463 | { PREFIX_TABLE (PREFIX_VEX_0F7C) }, |
8464 | { PREFIX_TABLE (PREFIX_VEX_0F7D) }, | |
8465 | { PREFIX_TABLE (PREFIX_VEX_0F7E) }, | |
8466 | { PREFIX_TABLE (PREFIX_VEX_0F7F) }, | |
c0f3af97 | 8467 | /* 80 */ |
592d1631 L |
8468 | { Bad_Opcode }, |
8469 | { Bad_Opcode }, | |
8470 | { Bad_Opcode }, | |
8471 | { Bad_Opcode }, | |
8472 | { Bad_Opcode }, | |
8473 | { Bad_Opcode }, | |
8474 | { Bad_Opcode }, | |
8475 | { Bad_Opcode }, | |
c0f3af97 | 8476 | /* 88 */ |
592d1631 L |
8477 | { Bad_Opcode }, |
8478 | { Bad_Opcode }, | |
8479 | { Bad_Opcode }, | |
8480 | { Bad_Opcode }, | |
8481 | { Bad_Opcode }, | |
8482 | { Bad_Opcode }, | |
8483 | { Bad_Opcode }, | |
8484 | { Bad_Opcode }, | |
c0f3af97 | 8485 | /* 90 */ |
43234a1e L |
8486 | { PREFIX_TABLE (PREFIX_VEX_0F90) }, |
8487 | { PREFIX_TABLE (PREFIX_VEX_0F91) }, | |
8488 | { PREFIX_TABLE (PREFIX_VEX_0F92) }, | |
8489 | { PREFIX_TABLE (PREFIX_VEX_0F93) }, | |
592d1631 L |
8490 | { Bad_Opcode }, |
8491 | { Bad_Opcode }, | |
8492 | { Bad_Opcode }, | |
8493 | { Bad_Opcode }, | |
c0f3af97 | 8494 | /* 98 */ |
43234a1e | 8495 | { PREFIX_TABLE (PREFIX_VEX_0F98) }, |
1ba585e8 | 8496 | { PREFIX_TABLE (PREFIX_VEX_0F99) }, |
592d1631 L |
8497 | { Bad_Opcode }, |
8498 | { Bad_Opcode }, | |
8499 | { Bad_Opcode }, | |
8500 | { Bad_Opcode }, | |
8501 | { Bad_Opcode }, | |
8502 | { Bad_Opcode }, | |
c0f3af97 | 8503 | /* a0 */ |
592d1631 L |
8504 | { Bad_Opcode }, |
8505 | { Bad_Opcode }, | |
8506 | { Bad_Opcode }, | |
8507 | { Bad_Opcode }, | |
8508 | { Bad_Opcode }, | |
8509 | { Bad_Opcode }, | |
8510 | { Bad_Opcode }, | |
8511 | { Bad_Opcode }, | |
c0f3af97 | 8512 | /* a8 */ |
592d1631 L |
8513 | { Bad_Opcode }, |
8514 | { Bad_Opcode }, | |
8515 | { Bad_Opcode }, | |
8516 | { Bad_Opcode }, | |
8517 | { Bad_Opcode }, | |
8518 | { Bad_Opcode }, | |
592a252b | 8519 | { REG_TABLE (REG_VEX_0FAE) }, |
592d1631 | 8520 | { Bad_Opcode }, |
c0f3af97 | 8521 | /* b0 */ |
592d1631 L |
8522 | { Bad_Opcode }, |
8523 | { Bad_Opcode }, | |
8524 | { Bad_Opcode }, | |
8525 | { Bad_Opcode }, | |
8526 | { Bad_Opcode }, | |
8527 | { Bad_Opcode }, | |
8528 | { Bad_Opcode }, | |
8529 | { Bad_Opcode }, | |
c0f3af97 | 8530 | /* b8 */ |
592d1631 L |
8531 | { Bad_Opcode }, |
8532 | { Bad_Opcode }, | |
8533 | { Bad_Opcode }, | |
8534 | { Bad_Opcode }, | |
8535 | { Bad_Opcode }, | |
8536 | { Bad_Opcode }, | |
8537 | { Bad_Opcode }, | |
8538 | { Bad_Opcode }, | |
c0f3af97 | 8539 | /* c0 */ |
592d1631 L |
8540 | { Bad_Opcode }, |
8541 | { Bad_Opcode }, | |
592a252b | 8542 | { PREFIX_TABLE (PREFIX_VEX_0FC2) }, |
592d1631 | 8543 | { Bad_Opcode }, |
592a252b L |
8544 | { PREFIX_TABLE (PREFIX_VEX_0FC4) }, |
8545 | { PREFIX_TABLE (PREFIX_VEX_0FC5) }, | |
bf926894 | 8546 | { "vshufpX", { XM, Vex, EXx, Ib }, PREFIX_OPCODE }, |
592d1631 | 8547 | { Bad_Opcode }, |
c0f3af97 | 8548 | /* c8 */ |
592d1631 L |
8549 | { Bad_Opcode }, |
8550 | { Bad_Opcode }, | |
8551 | { Bad_Opcode }, | |
8552 | { Bad_Opcode }, | |
8553 | { Bad_Opcode }, | |
8554 | { Bad_Opcode }, | |
8555 | { Bad_Opcode }, | |
8556 | { Bad_Opcode }, | |
c0f3af97 | 8557 | /* d0 */ |
592a252b L |
8558 | { PREFIX_TABLE (PREFIX_VEX_0FD0) }, |
8559 | { PREFIX_TABLE (PREFIX_VEX_0FD1) }, | |
8560 | { PREFIX_TABLE (PREFIX_VEX_0FD2) }, | |
8561 | { PREFIX_TABLE (PREFIX_VEX_0FD3) }, | |
8562 | { PREFIX_TABLE (PREFIX_VEX_0FD4) }, | |
8563 | { PREFIX_TABLE (PREFIX_VEX_0FD5) }, | |
8564 | { PREFIX_TABLE (PREFIX_VEX_0FD6) }, | |
8565 | { PREFIX_TABLE (PREFIX_VEX_0FD7) }, | |
c0f3af97 | 8566 | /* d8 */ |
592a252b L |
8567 | { PREFIX_TABLE (PREFIX_VEX_0FD8) }, |
8568 | { PREFIX_TABLE (PREFIX_VEX_0FD9) }, | |
8569 | { PREFIX_TABLE (PREFIX_VEX_0FDA) }, | |
8570 | { PREFIX_TABLE (PREFIX_VEX_0FDB) }, | |
8571 | { PREFIX_TABLE (PREFIX_VEX_0FDC) }, | |
8572 | { PREFIX_TABLE (PREFIX_VEX_0FDD) }, | |
8573 | { PREFIX_TABLE (PREFIX_VEX_0FDE) }, | |
8574 | { PREFIX_TABLE (PREFIX_VEX_0FDF) }, | |
c0f3af97 | 8575 | /* e0 */ |
592a252b L |
8576 | { PREFIX_TABLE (PREFIX_VEX_0FE0) }, |
8577 | { PREFIX_TABLE (PREFIX_VEX_0FE1) }, | |
8578 | { PREFIX_TABLE (PREFIX_VEX_0FE2) }, | |
8579 | { PREFIX_TABLE (PREFIX_VEX_0FE3) }, | |
8580 | { PREFIX_TABLE (PREFIX_VEX_0FE4) }, | |
8581 | { PREFIX_TABLE (PREFIX_VEX_0FE5) }, | |
8582 | { PREFIX_TABLE (PREFIX_VEX_0FE6) }, | |
8583 | { PREFIX_TABLE (PREFIX_VEX_0FE7) }, | |
c0f3af97 | 8584 | /* e8 */ |
592a252b L |
8585 | { PREFIX_TABLE (PREFIX_VEX_0FE8) }, |
8586 | { PREFIX_TABLE (PREFIX_VEX_0FE9) }, | |
8587 | { PREFIX_TABLE (PREFIX_VEX_0FEA) }, | |
8588 | { PREFIX_TABLE (PREFIX_VEX_0FEB) }, | |
8589 | { PREFIX_TABLE (PREFIX_VEX_0FEC) }, | |
8590 | { PREFIX_TABLE (PREFIX_VEX_0FED) }, | |
8591 | { PREFIX_TABLE (PREFIX_VEX_0FEE) }, | |
8592 | { PREFIX_TABLE (PREFIX_VEX_0FEF) }, | |
c0f3af97 | 8593 | /* f0 */ |
592a252b L |
8594 | { PREFIX_TABLE (PREFIX_VEX_0FF0) }, |
8595 | { PREFIX_TABLE (PREFIX_VEX_0FF1) }, | |
8596 | { PREFIX_TABLE (PREFIX_VEX_0FF2) }, | |
8597 | { PREFIX_TABLE (PREFIX_VEX_0FF3) }, | |
8598 | { PREFIX_TABLE (PREFIX_VEX_0FF4) }, | |
8599 | { PREFIX_TABLE (PREFIX_VEX_0FF5) }, | |
8600 | { PREFIX_TABLE (PREFIX_VEX_0FF6) }, | |
8601 | { PREFIX_TABLE (PREFIX_VEX_0FF7) }, | |
c0f3af97 | 8602 | /* f8 */ |
592a252b L |
8603 | { PREFIX_TABLE (PREFIX_VEX_0FF8) }, |
8604 | { PREFIX_TABLE (PREFIX_VEX_0FF9) }, | |
8605 | { PREFIX_TABLE (PREFIX_VEX_0FFA) }, | |
8606 | { PREFIX_TABLE (PREFIX_VEX_0FFB) }, | |
8607 | { PREFIX_TABLE (PREFIX_VEX_0FFC) }, | |
8608 | { PREFIX_TABLE (PREFIX_VEX_0FFD) }, | |
8609 | { PREFIX_TABLE (PREFIX_VEX_0FFE) }, | |
592d1631 | 8610 | { Bad_Opcode }, |
c0f3af97 L |
8611 | }, |
8612 | /* VEX_0F38 */ | |
8613 | { | |
8614 | /* 00 */ | |
592a252b L |
8615 | { PREFIX_TABLE (PREFIX_VEX_0F3800) }, |
8616 | { PREFIX_TABLE (PREFIX_VEX_0F3801) }, | |
8617 | { PREFIX_TABLE (PREFIX_VEX_0F3802) }, | |
8618 | { PREFIX_TABLE (PREFIX_VEX_0F3803) }, | |
8619 | { PREFIX_TABLE (PREFIX_VEX_0F3804) }, | |
8620 | { PREFIX_TABLE (PREFIX_VEX_0F3805) }, | |
8621 | { PREFIX_TABLE (PREFIX_VEX_0F3806) }, | |
8622 | { PREFIX_TABLE (PREFIX_VEX_0F3807) }, | |
c0f3af97 | 8623 | /* 08 */ |
592a252b L |
8624 | { PREFIX_TABLE (PREFIX_VEX_0F3808) }, |
8625 | { PREFIX_TABLE (PREFIX_VEX_0F3809) }, | |
8626 | { PREFIX_TABLE (PREFIX_VEX_0F380A) }, | |
8627 | { PREFIX_TABLE (PREFIX_VEX_0F380B) }, | |
8628 | { PREFIX_TABLE (PREFIX_VEX_0F380C) }, | |
8629 | { PREFIX_TABLE (PREFIX_VEX_0F380D) }, | |
8630 | { PREFIX_TABLE (PREFIX_VEX_0F380E) }, | |
8631 | { PREFIX_TABLE (PREFIX_VEX_0F380F) }, | |
c0f3af97 | 8632 | /* 10 */ |
592d1631 L |
8633 | { Bad_Opcode }, |
8634 | { Bad_Opcode }, | |
8635 | { Bad_Opcode }, | |
592a252b | 8636 | { PREFIX_TABLE (PREFIX_VEX_0F3813) }, |
592d1631 L |
8637 | { Bad_Opcode }, |
8638 | { Bad_Opcode }, | |
6c30d220 | 8639 | { PREFIX_TABLE (PREFIX_VEX_0F3816) }, |
592a252b | 8640 | { PREFIX_TABLE (PREFIX_VEX_0F3817) }, |
c0f3af97 | 8641 | /* 18 */ |
592a252b L |
8642 | { PREFIX_TABLE (PREFIX_VEX_0F3818) }, |
8643 | { PREFIX_TABLE (PREFIX_VEX_0F3819) }, | |
8644 | { PREFIX_TABLE (PREFIX_VEX_0F381A) }, | |
592d1631 | 8645 | { Bad_Opcode }, |
592a252b L |
8646 | { PREFIX_TABLE (PREFIX_VEX_0F381C) }, |
8647 | { PREFIX_TABLE (PREFIX_VEX_0F381D) }, | |
8648 | { PREFIX_TABLE (PREFIX_VEX_0F381E) }, | |
592d1631 | 8649 | { Bad_Opcode }, |
c0f3af97 | 8650 | /* 20 */ |
592a252b L |
8651 | { PREFIX_TABLE (PREFIX_VEX_0F3820) }, |
8652 | { PREFIX_TABLE (PREFIX_VEX_0F3821) }, | |
8653 | { PREFIX_TABLE (PREFIX_VEX_0F3822) }, | |
8654 | { PREFIX_TABLE (PREFIX_VEX_0F3823) }, | |
8655 | { PREFIX_TABLE (PREFIX_VEX_0F3824) }, | |
8656 | { PREFIX_TABLE (PREFIX_VEX_0F3825) }, | |
592d1631 L |
8657 | { Bad_Opcode }, |
8658 | { Bad_Opcode }, | |
c0f3af97 | 8659 | /* 28 */ |
592a252b L |
8660 | { PREFIX_TABLE (PREFIX_VEX_0F3828) }, |
8661 | { PREFIX_TABLE (PREFIX_VEX_0F3829) }, | |
8662 | { PREFIX_TABLE (PREFIX_VEX_0F382A) }, | |
8663 | { PREFIX_TABLE (PREFIX_VEX_0F382B) }, | |
8664 | { PREFIX_TABLE (PREFIX_VEX_0F382C) }, | |
8665 | { PREFIX_TABLE (PREFIX_VEX_0F382D) }, | |
8666 | { PREFIX_TABLE (PREFIX_VEX_0F382E) }, | |
8667 | { PREFIX_TABLE (PREFIX_VEX_0F382F) }, | |
c0f3af97 | 8668 | /* 30 */ |
592a252b L |
8669 | { PREFIX_TABLE (PREFIX_VEX_0F3830) }, |
8670 | { PREFIX_TABLE (PREFIX_VEX_0F3831) }, | |
8671 | { PREFIX_TABLE (PREFIX_VEX_0F3832) }, | |
8672 | { PREFIX_TABLE (PREFIX_VEX_0F3833) }, | |
8673 | { PREFIX_TABLE (PREFIX_VEX_0F3834) }, | |
8674 | { PREFIX_TABLE (PREFIX_VEX_0F3835) }, | |
6c30d220 | 8675 | { PREFIX_TABLE (PREFIX_VEX_0F3836) }, |
592a252b | 8676 | { PREFIX_TABLE (PREFIX_VEX_0F3837) }, |
c0f3af97 | 8677 | /* 38 */ |
592a252b L |
8678 | { PREFIX_TABLE (PREFIX_VEX_0F3838) }, |
8679 | { PREFIX_TABLE (PREFIX_VEX_0F3839) }, | |
8680 | { PREFIX_TABLE (PREFIX_VEX_0F383A) }, | |
8681 | { PREFIX_TABLE (PREFIX_VEX_0F383B) }, | |
8682 | { PREFIX_TABLE (PREFIX_VEX_0F383C) }, | |
8683 | { PREFIX_TABLE (PREFIX_VEX_0F383D) }, | |
8684 | { PREFIX_TABLE (PREFIX_VEX_0F383E) }, | |
8685 | { PREFIX_TABLE (PREFIX_VEX_0F383F) }, | |
c0f3af97 | 8686 | /* 40 */ |
592a252b L |
8687 | { PREFIX_TABLE (PREFIX_VEX_0F3840) }, |
8688 | { PREFIX_TABLE (PREFIX_VEX_0F3841) }, | |
592d1631 L |
8689 | { Bad_Opcode }, |
8690 | { Bad_Opcode }, | |
8691 | { Bad_Opcode }, | |
6c30d220 L |
8692 | { PREFIX_TABLE (PREFIX_VEX_0F3845) }, |
8693 | { PREFIX_TABLE (PREFIX_VEX_0F3846) }, | |
8694 | { PREFIX_TABLE (PREFIX_VEX_0F3847) }, | |
c0f3af97 | 8695 | /* 48 */ |
592d1631 L |
8696 | { Bad_Opcode }, |
8697 | { Bad_Opcode }, | |
8698 | { Bad_Opcode }, | |
8699 | { Bad_Opcode }, | |
8700 | { Bad_Opcode }, | |
8701 | { Bad_Opcode }, | |
8702 | { Bad_Opcode }, | |
8703 | { Bad_Opcode }, | |
c0f3af97 | 8704 | /* 50 */ |
592d1631 L |
8705 | { Bad_Opcode }, |
8706 | { Bad_Opcode }, | |
8707 | { Bad_Opcode }, | |
8708 | { Bad_Opcode }, | |
8709 | { Bad_Opcode }, | |
8710 | { Bad_Opcode }, | |
8711 | { Bad_Opcode }, | |
8712 | { Bad_Opcode }, | |
c0f3af97 | 8713 | /* 58 */ |
6c30d220 L |
8714 | { PREFIX_TABLE (PREFIX_VEX_0F3858) }, |
8715 | { PREFIX_TABLE (PREFIX_VEX_0F3859) }, | |
8716 | { PREFIX_TABLE (PREFIX_VEX_0F385A) }, | |
592d1631 L |
8717 | { Bad_Opcode }, |
8718 | { Bad_Opcode }, | |
8719 | { Bad_Opcode }, | |
8720 | { Bad_Opcode }, | |
8721 | { Bad_Opcode }, | |
c0f3af97 | 8722 | /* 60 */ |
592d1631 L |
8723 | { Bad_Opcode }, |
8724 | { Bad_Opcode }, | |
8725 | { Bad_Opcode }, | |
8726 | { Bad_Opcode }, | |
8727 | { Bad_Opcode }, | |
8728 | { Bad_Opcode }, | |
8729 | { Bad_Opcode }, | |
8730 | { Bad_Opcode }, | |
c0f3af97 | 8731 | /* 68 */ |
592d1631 L |
8732 | { Bad_Opcode }, |
8733 | { Bad_Opcode }, | |
8734 | { Bad_Opcode }, | |
8735 | { Bad_Opcode }, | |
8736 | { Bad_Opcode }, | |
8737 | { Bad_Opcode }, | |
8738 | { Bad_Opcode }, | |
8739 | { Bad_Opcode }, | |
c0f3af97 | 8740 | /* 70 */ |
592d1631 L |
8741 | { Bad_Opcode }, |
8742 | { Bad_Opcode }, | |
8743 | { Bad_Opcode }, | |
8744 | { Bad_Opcode }, | |
8745 | { Bad_Opcode }, | |
8746 | { Bad_Opcode }, | |
8747 | { Bad_Opcode }, | |
8748 | { Bad_Opcode }, | |
c0f3af97 | 8749 | /* 78 */ |
6c30d220 L |
8750 | { PREFIX_TABLE (PREFIX_VEX_0F3878) }, |
8751 | { PREFIX_TABLE (PREFIX_VEX_0F3879) }, | |
592d1631 L |
8752 | { Bad_Opcode }, |
8753 | { Bad_Opcode }, | |
8754 | { Bad_Opcode }, | |
8755 | { Bad_Opcode }, | |
8756 | { Bad_Opcode }, | |
8757 | { Bad_Opcode }, | |
c0f3af97 | 8758 | /* 80 */ |
592d1631 L |
8759 | { Bad_Opcode }, |
8760 | { Bad_Opcode }, | |
8761 | { Bad_Opcode }, | |
8762 | { Bad_Opcode }, | |
8763 | { Bad_Opcode }, | |
8764 | { Bad_Opcode }, | |
8765 | { Bad_Opcode }, | |
8766 | { Bad_Opcode }, | |
c0f3af97 | 8767 | /* 88 */ |
592d1631 L |
8768 | { Bad_Opcode }, |
8769 | { Bad_Opcode }, | |
8770 | { Bad_Opcode }, | |
8771 | { Bad_Opcode }, | |
6c30d220 | 8772 | { PREFIX_TABLE (PREFIX_VEX_0F388C) }, |
592d1631 | 8773 | { Bad_Opcode }, |
6c30d220 | 8774 | { PREFIX_TABLE (PREFIX_VEX_0F388E) }, |
592d1631 | 8775 | { Bad_Opcode }, |
c0f3af97 | 8776 | /* 90 */ |
6c30d220 L |
8777 | { PREFIX_TABLE (PREFIX_VEX_0F3890) }, |
8778 | { PREFIX_TABLE (PREFIX_VEX_0F3891) }, | |
8779 | { PREFIX_TABLE (PREFIX_VEX_0F3892) }, | |
8780 | { PREFIX_TABLE (PREFIX_VEX_0F3893) }, | |
592d1631 L |
8781 | { Bad_Opcode }, |
8782 | { Bad_Opcode }, | |
592a252b L |
8783 | { PREFIX_TABLE (PREFIX_VEX_0F3896) }, |
8784 | { PREFIX_TABLE (PREFIX_VEX_0F3897) }, | |
c0f3af97 | 8785 | /* 98 */ |
592a252b L |
8786 | { PREFIX_TABLE (PREFIX_VEX_0F3898) }, |
8787 | { PREFIX_TABLE (PREFIX_VEX_0F3899) }, | |
8788 | { PREFIX_TABLE (PREFIX_VEX_0F389A) }, | |
8789 | { PREFIX_TABLE (PREFIX_VEX_0F389B) }, | |
8790 | { PREFIX_TABLE (PREFIX_VEX_0F389C) }, | |
8791 | { PREFIX_TABLE (PREFIX_VEX_0F389D) }, | |
8792 | { PREFIX_TABLE (PREFIX_VEX_0F389E) }, | |
8793 | { PREFIX_TABLE (PREFIX_VEX_0F389F) }, | |
c0f3af97 | 8794 | /* a0 */ |
592d1631 L |
8795 | { Bad_Opcode }, |
8796 | { Bad_Opcode }, | |
8797 | { Bad_Opcode }, | |
8798 | { Bad_Opcode }, | |
8799 | { Bad_Opcode }, | |
8800 | { Bad_Opcode }, | |
592a252b L |
8801 | { PREFIX_TABLE (PREFIX_VEX_0F38A6) }, |
8802 | { PREFIX_TABLE (PREFIX_VEX_0F38A7) }, | |
c0f3af97 | 8803 | /* a8 */ |
592a252b L |
8804 | { PREFIX_TABLE (PREFIX_VEX_0F38A8) }, |
8805 | { PREFIX_TABLE (PREFIX_VEX_0F38A9) }, | |
8806 | { PREFIX_TABLE (PREFIX_VEX_0F38AA) }, | |
8807 | { PREFIX_TABLE (PREFIX_VEX_0F38AB) }, | |
8808 | { PREFIX_TABLE (PREFIX_VEX_0F38AC) }, | |
8809 | { PREFIX_TABLE (PREFIX_VEX_0F38AD) }, | |
8810 | { PREFIX_TABLE (PREFIX_VEX_0F38AE) }, | |
8811 | { PREFIX_TABLE (PREFIX_VEX_0F38AF) }, | |
c0f3af97 | 8812 | /* b0 */ |
592d1631 L |
8813 | { Bad_Opcode }, |
8814 | { Bad_Opcode }, | |
8815 | { Bad_Opcode }, | |
8816 | { Bad_Opcode }, | |
8817 | { Bad_Opcode }, | |
8818 | { Bad_Opcode }, | |
592a252b L |
8819 | { PREFIX_TABLE (PREFIX_VEX_0F38B6) }, |
8820 | { PREFIX_TABLE (PREFIX_VEX_0F38B7) }, | |
c0f3af97 | 8821 | /* b8 */ |
592a252b L |
8822 | { PREFIX_TABLE (PREFIX_VEX_0F38B8) }, |
8823 | { PREFIX_TABLE (PREFIX_VEX_0F38B9) }, | |
8824 | { PREFIX_TABLE (PREFIX_VEX_0F38BA) }, | |
8825 | { PREFIX_TABLE (PREFIX_VEX_0F38BB) }, | |
8826 | { PREFIX_TABLE (PREFIX_VEX_0F38BC) }, | |
8827 | { PREFIX_TABLE (PREFIX_VEX_0F38BD) }, | |
8828 | { PREFIX_TABLE (PREFIX_VEX_0F38BE) }, | |
8829 | { PREFIX_TABLE (PREFIX_VEX_0F38BF) }, | |
c0f3af97 | 8830 | /* c0 */ |
592d1631 L |
8831 | { Bad_Opcode }, |
8832 | { Bad_Opcode }, | |
8833 | { Bad_Opcode }, | |
8834 | { Bad_Opcode }, | |
8835 | { Bad_Opcode }, | |
8836 | { Bad_Opcode }, | |
8837 | { Bad_Opcode }, | |
8838 | { Bad_Opcode }, | |
c0f3af97 | 8839 | /* c8 */ |
592d1631 L |
8840 | { Bad_Opcode }, |
8841 | { Bad_Opcode }, | |
8842 | { Bad_Opcode }, | |
8843 | { Bad_Opcode }, | |
8844 | { Bad_Opcode }, | |
8845 | { Bad_Opcode }, | |
8846 | { Bad_Opcode }, | |
48521003 | 8847 | { PREFIX_TABLE (PREFIX_VEX_0F38CF) }, |
c0f3af97 | 8848 | /* d0 */ |
592d1631 L |
8849 | { Bad_Opcode }, |
8850 | { Bad_Opcode }, | |
8851 | { Bad_Opcode }, | |
8852 | { Bad_Opcode }, | |
8853 | { Bad_Opcode }, | |
8854 | { Bad_Opcode }, | |
8855 | { Bad_Opcode }, | |
8856 | { Bad_Opcode }, | |
c0f3af97 | 8857 | /* d8 */ |
592d1631 L |
8858 | { Bad_Opcode }, |
8859 | { Bad_Opcode }, | |
8860 | { Bad_Opcode }, | |
592a252b L |
8861 | { PREFIX_TABLE (PREFIX_VEX_0F38DB) }, |
8862 | { PREFIX_TABLE (PREFIX_VEX_0F38DC) }, | |
8863 | { PREFIX_TABLE (PREFIX_VEX_0F38DD) }, | |
8864 | { PREFIX_TABLE (PREFIX_VEX_0F38DE) }, | |
8865 | { PREFIX_TABLE (PREFIX_VEX_0F38DF) }, | |
c0f3af97 | 8866 | /* e0 */ |
592d1631 L |
8867 | { Bad_Opcode }, |
8868 | { Bad_Opcode }, | |
8869 | { Bad_Opcode }, | |
8870 | { Bad_Opcode }, | |
8871 | { Bad_Opcode }, | |
8872 | { Bad_Opcode }, | |
8873 | { Bad_Opcode }, | |
8874 | { Bad_Opcode }, | |
c0f3af97 | 8875 | /* e8 */ |
592d1631 L |
8876 | { Bad_Opcode }, |
8877 | { Bad_Opcode }, | |
8878 | { Bad_Opcode }, | |
8879 | { Bad_Opcode }, | |
8880 | { Bad_Opcode }, | |
8881 | { Bad_Opcode }, | |
8882 | { Bad_Opcode }, | |
8883 | { Bad_Opcode }, | |
c0f3af97 | 8884 | /* f0 */ |
592d1631 L |
8885 | { Bad_Opcode }, |
8886 | { Bad_Opcode }, | |
f12dc422 L |
8887 | { PREFIX_TABLE (PREFIX_VEX_0F38F2) }, |
8888 | { REG_TABLE (REG_VEX_0F38F3) }, | |
592d1631 | 8889 | { Bad_Opcode }, |
6c30d220 L |
8890 | { PREFIX_TABLE (PREFIX_VEX_0F38F5) }, |
8891 | { PREFIX_TABLE (PREFIX_VEX_0F38F6) }, | |
f12dc422 | 8892 | { PREFIX_TABLE (PREFIX_VEX_0F38F7) }, |
c0f3af97 | 8893 | /* f8 */ |
592d1631 L |
8894 | { Bad_Opcode }, |
8895 | { Bad_Opcode }, | |
8896 | { Bad_Opcode }, | |
8897 | { Bad_Opcode }, | |
8898 | { Bad_Opcode }, | |
8899 | { Bad_Opcode }, | |
8900 | { Bad_Opcode }, | |
8901 | { Bad_Opcode }, | |
c0f3af97 L |
8902 | }, |
8903 | /* VEX_0F3A */ | |
8904 | { | |
8905 | /* 00 */ | |
6c30d220 L |
8906 | { PREFIX_TABLE (PREFIX_VEX_0F3A00) }, |
8907 | { PREFIX_TABLE (PREFIX_VEX_0F3A01) }, | |
8908 | { PREFIX_TABLE (PREFIX_VEX_0F3A02) }, | |
592d1631 | 8909 | { Bad_Opcode }, |
592a252b L |
8910 | { PREFIX_TABLE (PREFIX_VEX_0F3A04) }, |
8911 | { PREFIX_TABLE (PREFIX_VEX_0F3A05) }, | |
8912 | { PREFIX_TABLE (PREFIX_VEX_0F3A06) }, | |
592d1631 | 8913 | { Bad_Opcode }, |
c0f3af97 | 8914 | /* 08 */ |
592a252b L |
8915 | { PREFIX_TABLE (PREFIX_VEX_0F3A08) }, |
8916 | { PREFIX_TABLE (PREFIX_VEX_0F3A09) }, | |
8917 | { PREFIX_TABLE (PREFIX_VEX_0F3A0A) }, | |
8918 | { PREFIX_TABLE (PREFIX_VEX_0F3A0B) }, | |
8919 | { PREFIX_TABLE (PREFIX_VEX_0F3A0C) }, | |
8920 | { PREFIX_TABLE (PREFIX_VEX_0F3A0D) }, | |
8921 | { PREFIX_TABLE (PREFIX_VEX_0F3A0E) }, | |
8922 | { PREFIX_TABLE (PREFIX_VEX_0F3A0F) }, | |
c0f3af97 | 8923 | /* 10 */ |
592d1631 L |
8924 | { Bad_Opcode }, |
8925 | { Bad_Opcode }, | |
8926 | { Bad_Opcode }, | |
8927 | { Bad_Opcode }, | |
592a252b L |
8928 | { PREFIX_TABLE (PREFIX_VEX_0F3A14) }, |
8929 | { PREFIX_TABLE (PREFIX_VEX_0F3A15) }, | |
8930 | { PREFIX_TABLE (PREFIX_VEX_0F3A16) }, | |
8931 | { PREFIX_TABLE (PREFIX_VEX_0F3A17) }, | |
c0f3af97 | 8932 | /* 18 */ |
592a252b L |
8933 | { PREFIX_TABLE (PREFIX_VEX_0F3A18) }, |
8934 | { PREFIX_TABLE (PREFIX_VEX_0F3A19) }, | |
592d1631 L |
8935 | { Bad_Opcode }, |
8936 | { Bad_Opcode }, | |
8937 | { Bad_Opcode }, | |
592a252b | 8938 | { PREFIX_TABLE (PREFIX_VEX_0F3A1D) }, |
592d1631 L |
8939 | { Bad_Opcode }, |
8940 | { Bad_Opcode }, | |
c0f3af97 | 8941 | /* 20 */ |
592a252b L |
8942 | { PREFIX_TABLE (PREFIX_VEX_0F3A20) }, |
8943 | { PREFIX_TABLE (PREFIX_VEX_0F3A21) }, | |
8944 | { PREFIX_TABLE (PREFIX_VEX_0F3A22) }, | |
592d1631 L |
8945 | { Bad_Opcode }, |
8946 | { Bad_Opcode }, | |
8947 | { Bad_Opcode }, | |
8948 | { Bad_Opcode }, | |
8949 | { Bad_Opcode }, | |
c0f3af97 | 8950 | /* 28 */ |
592d1631 L |
8951 | { Bad_Opcode }, |
8952 | { Bad_Opcode }, | |
8953 | { Bad_Opcode }, | |
8954 | { Bad_Opcode }, | |
8955 | { Bad_Opcode }, | |
8956 | { Bad_Opcode }, | |
8957 | { Bad_Opcode }, | |
8958 | { Bad_Opcode }, | |
c0f3af97 | 8959 | /* 30 */ |
43234a1e | 8960 | { PREFIX_TABLE (PREFIX_VEX_0F3A30) }, |
1ba585e8 | 8961 | { PREFIX_TABLE (PREFIX_VEX_0F3A31) }, |
43234a1e | 8962 | { PREFIX_TABLE (PREFIX_VEX_0F3A32) }, |
1ba585e8 | 8963 | { PREFIX_TABLE (PREFIX_VEX_0F3A33) }, |
592d1631 L |
8964 | { Bad_Opcode }, |
8965 | { Bad_Opcode }, | |
8966 | { Bad_Opcode }, | |
8967 | { Bad_Opcode }, | |
c0f3af97 | 8968 | /* 38 */ |
6c30d220 L |
8969 | { PREFIX_TABLE (PREFIX_VEX_0F3A38) }, |
8970 | { PREFIX_TABLE (PREFIX_VEX_0F3A39) }, | |
592d1631 L |
8971 | { Bad_Opcode }, |
8972 | { Bad_Opcode }, | |
8973 | { Bad_Opcode }, | |
8974 | { Bad_Opcode }, | |
8975 | { Bad_Opcode }, | |
8976 | { Bad_Opcode }, | |
c0f3af97 | 8977 | /* 40 */ |
592a252b L |
8978 | { PREFIX_TABLE (PREFIX_VEX_0F3A40) }, |
8979 | { PREFIX_TABLE (PREFIX_VEX_0F3A41) }, | |
8980 | { PREFIX_TABLE (PREFIX_VEX_0F3A42) }, | |
592d1631 | 8981 | { Bad_Opcode }, |
592a252b | 8982 | { PREFIX_TABLE (PREFIX_VEX_0F3A44) }, |
592d1631 | 8983 | { Bad_Opcode }, |
6c30d220 | 8984 | { PREFIX_TABLE (PREFIX_VEX_0F3A46) }, |
592d1631 | 8985 | { Bad_Opcode }, |
c0f3af97 | 8986 | /* 48 */ |
592a252b L |
8987 | { PREFIX_TABLE (PREFIX_VEX_0F3A48) }, |
8988 | { PREFIX_TABLE (PREFIX_VEX_0F3A49) }, | |
8989 | { PREFIX_TABLE (PREFIX_VEX_0F3A4A) }, | |
8990 | { PREFIX_TABLE (PREFIX_VEX_0F3A4B) }, | |
8991 | { PREFIX_TABLE (PREFIX_VEX_0F3A4C) }, | |
592d1631 L |
8992 | { Bad_Opcode }, |
8993 | { Bad_Opcode }, | |
8994 | { Bad_Opcode }, | |
c0f3af97 | 8995 | /* 50 */ |
592d1631 L |
8996 | { Bad_Opcode }, |
8997 | { Bad_Opcode }, | |
8998 | { Bad_Opcode }, | |
8999 | { Bad_Opcode }, | |
9000 | { Bad_Opcode }, | |
9001 | { Bad_Opcode }, | |
9002 | { Bad_Opcode }, | |
9003 | { Bad_Opcode }, | |
c0f3af97 | 9004 | /* 58 */ |
592d1631 L |
9005 | { Bad_Opcode }, |
9006 | { Bad_Opcode }, | |
9007 | { Bad_Opcode }, | |
9008 | { Bad_Opcode }, | |
592a252b L |
9009 | { PREFIX_TABLE (PREFIX_VEX_0F3A5C) }, |
9010 | { PREFIX_TABLE (PREFIX_VEX_0F3A5D) }, | |
9011 | { PREFIX_TABLE (PREFIX_VEX_0F3A5E) }, | |
9012 | { PREFIX_TABLE (PREFIX_VEX_0F3A5F) }, | |
c0f3af97 | 9013 | /* 60 */ |
592a252b L |
9014 | { PREFIX_TABLE (PREFIX_VEX_0F3A60) }, |
9015 | { PREFIX_TABLE (PREFIX_VEX_0F3A61) }, | |
9016 | { PREFIX_TABLE (PREFIX_VEX_0F3A62) }, | |
9017 | { PREFIX_TABLE (PREFIX_VEX_0F3A63) }, | |
592d1631 L |
9018 | { Bad_Opcode }, |
9019 | { Bad_Opcode }, | |
9020 | { Bad_Opcode }, | |
9021 | { Bad_Opcode }, | |
c0f3af97 | 9022 | /* 68 */ |
592a252b L |
9023 | { PREFIX_TABLE (PREFIX_VEX_0F3A68) }, |
9024 | { PREFIX_TABLE (PREFIX_VEX_0F3A69) }, | |
9025 | { PREFIX_TABLE (PREFIX_VEX_0F3A6A) }, | |
9026 | { PREFIX_TABLE (PREFIX_VEX_0F3A6B) }, | |
9027 | { PREFIX_TABLE (PREFIX_VEX_0F3A6C) }, | |
9028 | { PREFIX_TABLE (PREFIX_VEX_0F3A6D) }, | |
9029 | { PREFIX_TABLE (PREFIX_VEX_0F3A6E) }, | |
9030 | { PREFIX_TABLE (PREFIX_VEX_0F3A6F) }, | |
c0f3af97 | 9031 | /* 70 */ |
592d1631 L |
9032 | { Bad_Opcode }, |
9033 | { Bad_Opcode }, | |
9034 | { Bad_Opcode }, | |
9035 | { Bad_Opcode }, | |
9036 | { Bad_Opcode }, | |
9037 | { Bad_Opcode }, | |
9038 | { Bad_Opcode }, | |
9039 | { Bad_Opcode }, | |
c0f3af97 | 9040 | /* 78 */ |
592a252b L |
9041 | { PREFIX_TABLE (PREFIX_VEX_0F3A78) }, |
9042 | { PREFIX_TABLE (PREFIX_VEX_0F3A79) }, | |
9043 | { PREFIX_TABLE (PREFIX_VEX_0F3A7A) }, | |
9044 | { PREFIX_TABLE (PREFIX_VEX_0F3A7B) }, | |
9045 | { PREFIX_TABLE (PREFIX_VEX_0F3A7C) }, | |
9046 | { PREFIX_TABLE (PREFIX_VEX_0F3A7D) }, | |
9047 | { PREFIX_TABLE (PREFIX_VEX_0F3A7E) }, | |
9048 | { PREFIX_TABLE (PREFIX_VEX_0F3A7F) }, | |
c0f3af97 | 9049 | /* 80 */ |
592d1631 L |
9050 | { Bad_Opcode }, |
9051 | { Bad_Opcode }, | |
9052 | { Bad_Opcode }, | |
9053 | { Bad_Opcode }, | |
9054 | { Bad_Opcode }, | |
9055 | { Bad_Opcode }, | |
9056 | { Bad_Opcode }, | |
9057 | { Bad_Opcode }, | |
c0f3af97 | 9058 | /* 88 */ |
592d1631 L |
9059 | { Bad_Opcode }, |
9060 | { Bad_Opcode }, | |
9061 | { Bad_Opcode }, | |
9062 | { Bad_Opcode }, | |
9063 | { Bad_Opcode }, | |
9064 | { Bad_Opcode }, | |
9065 | { Bad_Opcode }, | |
9066 | { Bad_Opcode }, | |
c0f3af97 | 9067 | /* 90 */ |
592d1631 L |
9068 | { Bad_Opcode }, |
9069 | { Bad_Opcode }, | |
9070 | { Bad_Opcode }, | |
9071 | { Bad_Opcode }, | |
9072 | { Bad_Opcode }, | |
9073 | { Bad_Opcode }, | |
9074 | { Bad_Opcode }, | |
9075 | { Bad_Opcode }, | |
c0f3af97 | 9076 | /* 98 */ |
592d1631 L |
9077 | { Bad_Opcode }, |
9078 | { Bad_Opcode }, | |
9079 | { Bad_Opcode }, | |
9080 | { Bad_Opcode }, | |
9081 | { Bad_Opcode }, | |
9082 | { Bad_Opcode }, | |
9083 | { Bad_Opcode }, | |
9084 | { Bad_Opcode }, | |
c0f3af97 | 9085 | /* a0 */ |
592d1631 L |
9086 | { Bad_Opcode }, |
9087 | { Bad_Opcode }, | |
9088 | { Bad_Opcode }, | |
9089 | { Bad_Opcode }, | |
9090 | { Bad_Opcode }, | |
9091 | { Bad_Opcode }, | |
9092 | { Bad_Opcode }, | |
9093 | { Bad_Opcode }, | |
c0f3af97 | 9094 | /* a8 */ |
592d1631 L |
9095 | { Bad_Opcode }, |
9096 | { Bad_Opcode }, | |
9097 | { Bad_Opcode }, | |
9098 | { Bad_Opcode }, | |
9099 | { Bad_Opcode }, | |
9100 | { Bad_Opcode }, | |
9101 | { Bad_Opcode }, | |
9102 | { Bad_Opcode }, | |
c0f3af97 | 9103 | /* b0 */ |
592d1631 L |
9104 | { Bad_Opcode }, |
9105 | { Bad_Opcode }, | |
9106 | { Bad_Opcode }, | |
9107 | { Bad_Opcode }, | |
9108 | { Bad_Opcode }, | |
9109 | { Bad_Opcode }, | |
9110 | { Bad_Opcode }, | |
9111 | { Bad_Opcode }, | |
c0f3af97 | 9112 | /* b8 */ |
592d1631 L |
9113 | { Bad_Opcode }, |
9114 | { Bad_Opcode }, | |
9115 | { Bad_Opcode }, | |
9116 | { Bad_Opcode }, | |
9117 | { Bad_Opcode }, | |
9118 | { Bad_Opcode }, | |
9119 | { Bad_Opcode }, | |
9120 | { Bad_Opcode }, | |
c0f3af97 | 9121 | /* c0 */ |
592d1631 L |
9122 | { Bad_Opcode }, |
9123 | { Bad_Opcode }, | |
9124 | { Bad_Opcode }, | |
9125 | { Bad_Opcode }, | |
9126 | { Bad_Opcode }, | |
9127 | { Bad_Opcode }, | |
9128 | { Bad_Opcode }, | |
9129 | { Bad_Opcode }, | |
c0f3af97 | 9130 | /* c8 */ |
592d1631 L |
9131 | { Bad_Opcode }, |
9132 | { Bad_Opcode }, | |
9133 | { Bad_Opcode }, | |
9134 | { Bad_Opcode }, | |
9135 | { Bad_Opcode }, | |
9136 | { Bad_Opcode }, | |
48521003 IT |
9137 | { PREFIX_TABLE(PREFIX_VEX_0F3ACE) }, |
9138 | { PREFIX_TABLE(PREFIX_VEX_0F3ACF) }, | |
c0f3af97 | 9139 | /* d0 */ |
592d1631 L |
9140 | { Bad_Opcode }, |
9141 | { Bad_Opcode }, | |
9142 | { Bad_Opcode }, | |
9143 | { Bad_Opcode }, | |
9144 | { Bad_Opcode }, | |
9145 | { Bad_Opcode }, | |
9146 | { Bad_Opcode }, | |
9147 | { Bad_Opcode }, | |
c0f3af97 | 9148 | /* d8 */ |
592d1631 L |
9149 | { Bad_Opcode }, |
9150 | { Bad_Opcode }, | |
9151 | { Bad_Opcode }, | |
9152 | { Bad_Opcode }, | |
9153 | { Bad_Opcode }, | |
9154 | { Bad_Opcode }, | |
9155 | { Bad_Opcode }, | |
592a252b | 9156 | { PREFIX_TABLE (PREFIX_VEX_0F3ADF) }, |
c0f3af97 | 9157 | /* e0 */ |
592d1631 L |
9158 | { Bad_Opcode }, |
9159 | { Bad_Opcode }, | |
9160 | { Bad_Opcode }, | |
9161 | { Bad_Opcode }, | |
9162 | { Bad_Opcode }, | |
9163 | { Bad_Opcode }, | |
9164 | { Bad_Opcode }, | |
9165 | { Bad_Opcode }, | |
c0f3af97 | 9166 | /* e8 */ |
592d1631 L |
9167 | { Bad_Opcode }, |
9168 | { Bad_Opcode }, | |
9169 | { Bad_Opcode }, | |
9170 | { Bad_Opcode }, | |
9171 | { Bad_Opcode }, | |
9172 | { Bad_Opcode }, | |
9173 | { Bad_Opcode }, | |
9174 | { Bad_Opcode }, | |
c0f3af97 | 9175 | /* f0 */ |
6c30d220 | 9176 | { PREFIX_TABLE (PREFIX_VEX_0F3AF0) }, |
592d1631 L |
9177 | { Bad_Opcode }, |
9178 | { Bad_Opcode }, | |
9179 | { Bad_Opcode }, | |
9180 | { Bad_Opcode }, | |
9181 | { Bad_Opcode }, | |
9182 | { Bad_Opcode }, | |
9183 | { Bad_Opcode }, | |
c0f3af97 | 9184 | /* f8 */ |
592d1631 L |
9185 | { Bad_Opcode }, |
9186 | { Bad_Opcode }, | |
9187 | { Bad_Opcode }, | |
9188 | { Bad_Opcode }, | |
9189 | { Bad_Opcode }, | |
9190 | { Bad_Opcode }, | |
9191 | { Bad_Opcode }, | |
9192 | { Bad_Opcode }, | |
c0f3af97 L |
9193 | }, |
9194 | }; | |
9195 | ||
43234a1e | 9196 | #include "i386-dis-evex.h" |
ad692897 | 9197 | |
c0f3af97 | 9198 | static const struct dis386 vex_len_table[][2] = { |
18897deb | 9199 | /* VEX_LEN_0F12_P_0_M_0 / VEX_LEN_0F12_P_2_M_0 */ |
c0f3af97 | 9200 | { |
18897deb | 9201 | { "vmovlpX", { XM, Vex128, EXq }, 0 }, |
c0f3af97 L |
9202 | }, |
9203 | ||
592a252b | 9204 | /* VEX_LEN_0F12_P_0_M_1 */ |
c0f3af97 | 9205 | { |
ec6f095a | 9206 | { "vmovhlps", { XM, Vex128, EXq }, 0 }, |
c0f3af97 L |
9207 | }, |
9208 | ||
592a252b | 9209 | /* VEX_LEN_0F13_M_0 */ |
c0f3af97 | 9210 | { |
bf926894 | 9211 | { "vmovlpX", { EXq, XM }, PREFIX_OPCODE }, |
c0f3af97 L |
9212 | }, |
9213 | ||
18897deb | 9214 | /* VEX_LEN_0F16_P_0_M_0 / VEX_LEN_0F16_P_2_M_0 */ |
c0f3af97 | 9215 | { |
18897deb | 9216 | { "vmovhpX", { XM, Vex128, EXq }, 0 }, |
c0f3af97 L |
9217 | }, |
9218 | ||
592a252b | 9219 | /* VEX_LEN_0F16_P_0_M_1 */ |
c0f3af97 | 9220 | { |
ec6f095a | 9221 | { "vmovlhps", { XM, Vex128, EXq }, 0 }, |
c0f3af97 L |
9222 | }, |
9223 | ||
592a252b | 9224 | /* VEX_LEN_0F17_M_0 */ |
c0f3af97 | 9225 | { |
bf926894 | 9226 | { "vmovhpX", { EXq, XM }, PREFIX_OPCODE }, |
c0f3af97 L |
9227 | }, |
9228 | ||
43234a1e L |
9229 | /* VEX_LEN_0F41_P_0 */ |
9230 | { | |
9231 | { Bad_Opcode }, | |
9232 | { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) }, | |
9233 | }, | |
1ba585e8 IT |
9234 | /* VEX_LEN_0F41_P_2 */ |
9235 | { | |
9236 | { Bad_Opcode }, | |
9237 | { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) }, | |
9238 | }, | |
43234a1e L |
9239 | /* VEX_LEN_0F42_P_0 */ |
9240 | { | |
9241 | { Bad_Opcode }, | |
9242 | { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) }, | |
9243 | }, | |
1ba585e8 IT |
9244 | /* VEX_LEN_0F42_P_2 */ |
9245 | { | |
9246 | { Bad_Opcode }, | |
9247 | { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) }, | |
9248 | }, | |
43234a1e L |
9249 | /* VEX_LEN_0F44_P_0 */ |
9250 | { | |
9251 | { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) }, | |
9252 | }, | |
1ba585e8 IT |
9253 | /* VEX_LEN_0F44_P_2 */ |
9254 | { | |
9255 | { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) }, | |
9256 | }, | |
43234a1e L |
9257 | /* VEX_LEN_0F45_P_0 */ |
9258 | { | |
9259 | { Bad_Opcode }, | |
9260 | { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) }, | |
9261 | }, | |
1ba585e8 IT |
9262 | /* VEX_LEN_0F45_P_2 */ |
9263 | { | |
9264 | { Bad_Opcode }, | |
9265 | { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) }, | |
9266 | }, | |
43234a1e L |
9267 | /* VEX_LEN_0F46_P_0 */ |
9268 | { | |
9269 | { Bad_Opcode }, | |
9270 | { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) }, | |
9271 | }, | |
1ba585e8 IT |
9272 | /* VEX_LEN_0F46_P_2 */ |
9273 | { | |
9274 | { Bad_Opcode }, | |
9275 | { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) }, | |
9276 | }, | |
43234a1e L |
9277 | /* VEX_LEN_0F47_P_0 */ |
9278 | { | |
9279 | { Bad_Opcode }, | |
9280 | { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) }, | |
9281 | }, | |
1ba585e8 IT |
9282 | /* VEX_LEN_0F47_P_2 */ |
9283 | { | |
9284 | { Bad_Opcode }, | |
9285 | { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) }, | |
9286 | }, | |
9287 | /* VEX_LEN_0F4A_P_0 */ | |
9288 | { | |
9289 | { Bad_Opcode }, | |
9290 | { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) }, | |
9291 | }, | |
9292 | /* VEX_LEN_0F4A_P_2 */ | |
9293 | { | |
9294 | { Bad_Opcode }, | |
9295 | { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) }, | |
9296 | }, | |
9297 | /* VEX_LEN_0F4B_P_0 */ | |
9298 | { | |
9299 | { Bad_Opcode }, | |
9300 | { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) }, | |
9301 | }, | |
43234a1e L |
9302 | /* VEX_LEN_0F4B_P_2 */ |
9303 | { | |
9304 | { Bad_Opcode }, | |
9305 | { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) }, | |
9306 | }, | |
9307 | ||
ec6f095a | 9308 | /* VEX_LEN_0F6E_P_2 */ |
c0f3af97 | 9309 | { |
ec6f095a | 9310 | { "vmovK", { XMScalar, Edq }, 0 }, |
c0f3af97 L |
9311 | }, |
9312 | ||
ec6f095a | 9313 | /* VEX_LEN_0F77_P_1 */ |
c0f3af97 | 9314 | { |
ec6f095a L |
9315 | { "vzeroupper", { XX }, 0 }, |
9316 | { "vzeroall", { XX }, 0 }, | |
c0f3af97 L |
9317 | }, |
9318 | ||
ec6f095a | 9319 | /* VEX_LEN_0F7E_P_1 */ |
c0f3af97 | 9320 | { |
5b872f7d | 9321 | { "vmovq", { XMScalar, EXxmm_mq }, 0 }, |
c0f3af97 L |
9322 | }, |
9323 | ||
ec6f095a | 9324 | /* VEX_LEN_0F7E_P_2 */ |
c0f3af97 | 9325 | { |
ec6f095a | 9326 | { "vmovK", { Edq, XMScalar }, 0 }, |
c0f3af97 L |
9327 | }, |
9328 | ||
ec6f095a | 9329 | /* VEX_LEN_0F90_P_0 */ |
c0f3af97 | 9330 | { |
ec6f095a | 9331 | { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) }, |
c0f3af97 L |
9332 | }, |
9333 | ||
ec6f095a | 9334 | /* VEX_LEN_0F90_P_2 */ |
c0f3af97 | 9335 | { |
ec6f095a | 9336 | { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) }, |
c0f3af97 L |
9337 | }, |
9338 | ||
ec6f095a | 9339 | /* VEX_LEN_0F91_P_0 */ |
c0f3af97 | 9340 | { |
ec6f095a | 9341 | { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) }, |
c0f3af97 L |
9342 | }, |
9343 | ||
ec6f095a | 9344 | /* VEX_LEN_0F91_P_2 */ |
c0f3af97 | 9345 | { |
ec6f095a | 9346 | { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) }, |
c0f3af97 L |
9347 | }, |
9348 | ||
ec6f095a | 9349 | /* VEX_LEN_0F92_P_0 */ |
c0f3af97 | 9350 | { |
ec6f095a | 9351 | { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) }, |
c0f3af97 L |
9352 | }, |
9353 | ||
ec6f095a | 9354 | /* VEX_LEN_0F92_P_2 */ |
c0f3af97 | 9355 | { |
ec6f095a | 9356 | { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) }, |
c0f3af97 L |
9357 | }, |
9358 | ||
ec6f095a | 9359 | /* VEX_LEN_0F92_P_3 */ |
c0f3af97 | 9360 | { |
58a211d2 | 9361 | { MOD_TABLE (MOD_VEX_0F92_P_3_LEN_0) }, |
c0f3af97 L |
9362 | }, |
9363 | ||
ec6f095a | 9364 | /* VEX_LEN_0F93_P_0 */ |
c0f3af97 | 9365 | { |
ec6f095a | 9366 | { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) }, |
c0f3af97 L |
9367 | }, |
9368 | ||
ec6f095a | 9369 | /* VEX_LEN_0F93_P_2 */ |
c0f3af97 | 9370 | { |
ec6f095a | 9371 | { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) }, |
c0f3af97 L |
9372 | }, |
9373 | ||
ec6f095a | 9374 | /* VEX_LEN_0F93_P_3 */ |
c0f3af97 | 9375 | { |
58a211d2 | 9376 | { MOD_TABLE (MOD_VEX_0F93_P_3_LEN_0) }, |
c0f3af97 L |
9377 | }, |
9378 | ||
ec6f095a | 9379 | /* VEX_LEN_0F98_P_0 */ |
43234a1e L |
9380 | { |
9381 | { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) }, | |
9382 | }, | |
9383 | ||
1ba585e8 IT |
9384 | /* VEX_LEN_0F98_P_2 */ |
9385 | { | |
9386 | { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) }, | |
9387 | }, | |
9388 | ||
9389 | /* VEX_LEN_0F99_P_0 */ | |
9390 | { | |
9391 | { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) }, | |
9392 | }, | |
9393 | ||
9394 | /* VEX_LEN_0F99_P_2 */ | |
9395 | { | |
9396 | { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0) }, | |
9397 | }, | |
9398 | ||
6c30d220 | 9399 | /* VEX_LEN_0FAE_R_2_M_0 */ |
c0f3af97 | 9400 | { |
ec6f095a | 9401 | { "vldmxcsr", { Md }, 0 }, |
c0f3af97 L |
9402 | }, |
9403 | ||
6c30d220 | 9404 | /* VEX_LEN_0FAE_R_3_M_0 */ |
c0f3af97 | 9405 | { |
ec6f095a | 9406 | { "vstmxcsr", { Md }, 0 }, |
c0f3af97 L |
9407 | }, |
9408 | ||
6c30d220 | 9409 | /* VEX_LEN_0FC4_P_2 */ |
c0f3af97 | 9410 | { |
b50c9f31 | 9411 | { "vpinsrw", { XM, Vex128, Edqw, Ib }, 0 }, |
c0f3af97 L |
9412 | }, |
9413 | ||
6c30d220 | 9414 | /* VEX_LEN_0FC5_P_2 */ |
c0f3af97 | 9415 | { |
b50c9f31 | 9416 | { "vpextrw", { Gdq, XS, Ib }, 0 }, |
c0f3af97 L |
9417 | }, |
9418 | ||
6c30d220 | 9419 | /* VEX_LEN_0FD6_P_2 */ |
c0f3af97 | 9420 | { |
39e0f456 | 9421 | { "vmovq", { EXqVexScalarS, XMScalar }, 0 }, |
c0f3af97 L |
9422 | }, |
9423 | ||
6c30d220 | 9424 | /* VEX_LEN_0FF7_P_2 */ |
c0f3af97 | 9425 | { |
ec6f095a | 9426 | { "vmaskmovdqu", { XM, XS }, 0 }, |
c0f3af97 L |
9427 | }, |
9428 | ||
6c30d220 | 9429 | /* VEX_LEN_0F3816_P_2 */ |
c0f3af97 | 9430 | { |
6c30d220 L |
9431 | { Bad_Opcode }, |
9432 | { VEX_W_TABLE (VEX_W_0F3816_P_2) }, | |
c0f3af97 L |
9433 | }, |
9434 | ||
6c30d220 | 9435 | /* VEX_LEN_0F3819_P_2 */ |
c0f3af97 | 9436 | { |
6c30d220 L |
9437 | { Bad_Opcode }, |
9438 | { VEX_W_TABLE (VEX_W_0F3819_P_2) }, | |
c0f3af97 L |
9439 | }, |
9440 | ||
6c30d220 | 9441 | /* VEX_LEN_0F381A_P_2_M_0 */ |
c0f3af97 | 9442 | { |
6c30d220 L |
9443 | { Bad_Opcode }, |
9444 | { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) }, | |
c0f3af97 L |
9445 | }, |
9446 | ||
6c30d220 | 9447 | /* VEX_LEN_0F3836_P_2 */ |
c0f3af97 | 9448 | { |
6c30d220 L |
9449 | { Bad_Opcode }, |
9450 | { VEX_W_TABLE (VEX_W_0F3836_P_2) }, | |
c0f3af97 L |
9451 | }, |
9452 | ||
592a252b | 9453 | /* VEX_LEN_0F3841_P_2 */ |
c0f3af97 | 9454 | { |
ec6f095a | 9455 | { "vphminposuw", { XM, EXx }, 0 }, |
c0f3af97 L |
9456 | }, |
9457 | ||
6c30d220 L |
9458 | /* VEX_LEN_0F385A_P_2_M_0 */ |
9459 | { | |
9460 | { Bad_Opcode }, | |
9461 | { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) }, | |
9462 | }, | |
9463 | ||
592a252b | 9464 | /* VEX_LEN_0F38DB_P_2 */ |
a5ff0eb2 | 9465 | { |
ec6f095a | 9466 | { "vaesimc", { XM, EXx }, 0 }, |
a5ff0eb2 L |
9467 | }, |
9468 | ||
f12dc422 L |
9469 | /* VEX_LEN_0F38F2_P_0 */ |
9470 | { | |
bf890a93 | 9471 | { "andnS", { Gdq, VexGdq, Edq }, 0 }, |
f12dc422 L |
9472 | }, |
9473 | ||
9474 | /* VEX_LEN_0F38F3_R_1_P_0 */ | |
9475 | { | |
bf890a93 | 9476 | { "blsrS", { VexGdq, Edq }, 0 }, |
f12dc422 L |
9477 | }, |
9478 | ||
9479 | /* VEX_LEN_0F38F3_R_2_P_0 */ | |
9480 | { | |
bf890a93 | 9481 | { "blsmskS", { VexGdq, Edq }, 0 }, |
f12dc422 L |
9482 | }, |
9483 | ||
9484 | /* VEX_LEN_0F38F3_R_3_P_0 */ | |
9485 | { | |
bf890a93 | 9486 | { "blsiS", { VexGdq, Edq }, 0 }, |
f12dc422 L |
9487 | }, |
9488 | ||
6c30d220 L |
9489 | /* VEX_LEN_0F38F5_P_0 */ |
9490 | { | |
bf890a93 | 9491 | { "bzhiS", { Gdq, Edq, VexGdq }, 0 }, |
6c30d220 L |
9492 | }, |
9493 | ||
9494 | /* VEX_LEN_0F38F5_P_1 */ | |
9495 | { | |
bf890a93 | 9496 | { "pextS", { Gdq, VexGdq, Edq }, 0 }, |
6c30d220 L |
9497 | }, |
9498 | ||
9499 | /* VEX_LEN_0F38F5_P_3 */ | |
9500 | { | |
bf890a93 | 9501 | { "pdepS", { Gdq, VexGdq, Edq }, 0 }, |
6c30d220 L |
9502 | }, |
9503 | ||
9504 | /* VEX_LEN_0F38F6_P_3 */ | |
9505 | { | |
bf890a93 | 9506 | { "mulxS", { Gdq, VexGdq, Edq }, 0 }, |
6c30d220 L |
9507 | }, |
9508 | ||
f12dc422 L |
9509 | /* VEX_LEN_0F38F7_P_0 */ |
9510 | { | |
bf890a93 | 9511 | { "bextrS", { Gdq, Edq, VexGdq }, 0 }, |
f12dc422 L |
9512 | }, |
9513 | ||
6c30d220 L |
9514 | /* VEX_LEN_0F38F7_P_1 */ |
9515 | { | |
bf890a93 | 9516 | { "sarxS", { Gdq, Edq, VexGdq }, 0 }, |
6c30d220 L |
9517 | }, |
9518 | ||
9519 | /* VEX_LEN_0F38F7_P_2 */ | |
9520 | { | |
bf890a93 | 9521 | { "shlxS", { Gdq, Edq, VexGdq }, 0 }, |
6c30d220 L |
9522 | }, |
9523 | ||
9524 | /* VEX_LEN_0F38F7_P_3 */ | |
9525 | { | |
bf890a93 | 9526 | { "shrxS", { Gdq, Edq, VexGdq }, 0 }, |
6c30d220 L |
9527 | }, |
9528 | ||
9529 | /* VEX_LEN_0F3A00_P_2 */ | |
9530 | { | |
9531 | { Bad_Opcode }, | |
9532 | { VEX_W_TABLE (VEX_W_0F3A00_P_2) }, | |
9533 | }, | |
9534 | ||
9535 | /* VEX_LEN_0F3A01_P_2 */ | |
9536 | { | |
9537 | { Bad_Opcode }, | |
9538 | { VEX_W_TABLE (VEX_W_0F3A01_P_2) }, | |
9539 | }, | |
9540 | ||
592a252b | 9541 | /* VEX_LEN_0F3A06_P_2 */ |
c0f3af97 | 9542 | { |
592d1631 | 9543 | { Bad_Opcode }, |
592a252b | 9544 | { VEX_W_TABLE (VEX_W_0F3A06_P_2) }, |
c0f3af97 L |
9545 | }, |
9546 | ||
592a252b | 9547 | /* VEX_LEN_0F3A14_P_2 */ |
c0f3af97 | 9548 | { |
b50c9f31 | 9549 | { "vpextrb", { Edqb, XM, Ib }, 0 }, |
c0f3af97 L |
9550 | }, |
9551 | ||
592a252b | 9552 | /* VEX_LEN_0F3A15_P_2 */ |
c0f3af97 | 9553 | { |
b50c9f31 | 9554 | { "vpextrw", { Edqw, XM, Ib }, 0 }, |
c0f3af97 L |
9555 | }, |
9556 | ||
592a252b | 9557 | /* VEX_LEN_0F3A16_P_2 */ |
c0f3af97 | 9558 | { |
bf890a93 | 9559 | { "vpextrK", { Edq, XM, Ib }, 0 }, |
c0f3af97 L |
9560 | }, |
9561 | ||
592a252b | 9562 | /* VEX_LEN_0F3A17_P_2 */ |
c0f3af97 | 9563 | { |
bf890a93 | 9564 | { "vextractps", { Edqd, XM, Ib }, 0 }, |
c0f3af97 L |
9565 | }, |
9566 | ||
592a252b | 9567 | /* VEX_LEN_0F3A18_P_2 */ |
c0f3af97 | 9568 | { |
592d1631 | 9569 | { Bad_Opcode }, |
592a252b | 9570 | { VEX_W_TABLE (VEX_W_0F3A18_P_2) }, |
c0f3af97 L |
9571 | }, |
9572 | ||
592a252b | 9573 | /* VEX_LEN_0F3A19_P_2 */ |
c0f3af97 | 9574 | { |
592d1631 | 9575 | { Bad_Opcode }, |
592a252b | 9576 | { VEX_W_TABLE (VEX_W_0F3A19_P_2) }, |
c0f3af97 L |
9577 | }, |
9578 | ||
592a252b | 9579 | /* VEX_LEN_0F3A20_P_2 */ |
c0f3af97 | 9580 | { |
b50c9f31 | 9581 | { "vpinsrb", { XM, Vex128, Edqb, Ib }, 0 }, |
c0f3af97 L |
9582 | }, |
9583 | ||
592a252b | 9584 | /* VEX_LEN_0F3A21_P_2 */ |
c0f3af97 | 9585 | { |
ec6f095a | 9586 | { "vinsertps", { XM, Vex128, EXd, Ib }, 0 }, |
c0f3af97 L |
9587 | }, |
9588 | ||
592a252b | 9589 | /* VEX_LEN_0F3A22_P_2 */ |
c0f3af97 | 9590 | { |
bf890a93 | 9591 | { "vpinsrK", { XM, Vex128, Edq, Ib }, 0 }, |
c0f3af97 L |
9592 | }, |
9593 | ||
43234a1e L |
9594 | /* VEX_LEN_0F3A30_P_2 */ |
9595 | { | |
9596 | { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) }, | |
9597 | }, | |
9598 | ||
1ba585e8 IT |
9599 | /* VEX_LEN_0F3A31_P_2 */ |
9600 | { | |
9601 | { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0) }, | |
9602 | }, | |
9603 | ||
43234a1e L |
9604 | /* VEX_LEN_0F3A32_P_2 */ |
9605 | { | |
9606 | { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) }, | |
9607 | }, | |
9608 | ||
1ba585e8 IT |
9609 | /* VEX_LEN_0F3A33_P_2 */ |
9610 | { | |
9611 | { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0) }, | |
9612 | }, | |
9613 | ||
6c30d220 | 9614 | /* VEX_LEN_0F3A38_P_2 */ |
c0f3af97 | 9615 | { |
6c30d220 L |
9616 | { Bad_Opcode }, |
9617 | { VEX_W_TABLE (VEX_W_0F3A38_P_2) }, | |
c0f3af97 L |
9618 | }, |
9619 | ||
6c30d220 | 9620 | /* VEX_LEN_0F3A39_P_2 */ |
c0f3af97 | 9621 | { |
6c30d220 L |
9622 | { Bad_Opcode }, |
9623 | { VEX_W_TABLE (VEX_W_0F3A39_P_2) }, | |
9624 | }, | |
9625 | ||
9626 | /* VEX_LEN_0F3A41_P_2 */ | |
9627 | { | |
ec6f095a | 9628 | { "vdppd", { XM, Vex128, EXx, Ib }, 0 }, |
c0f3af97 L |
9629 | }, |
9630 | ||
6c30d220 | 9631 | /* VEX_LEN_0F3A46_P_2 */ |
c0f3af97 | 9632 | { |
6c30d220 L |
9633 | { Bad_Opcode }, |
9634 | { VEX_W_TABLE (VEX_W_0F3A46_P_2) }, | |
c0f3af97 L |
9635 | }, |
9636 | ||
592a252b | 9637 | /* VEX_LEN_0F3A60_P_2 */ |
c0f3af97 | 9638 | { |
15c7c1d8 | 9639 | { "vpcmpestrm", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 }, |
c0f3af97 L |
9640 | }, |
9641 | ||
592a252b | 9642 | /* VEX_LEN_0F3A61_P_2 */ |
c0f3af97 | 9643 | { |
15c7c1d8 | 9644 | { "vpcmpestri", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 }, |
c0f3af97 L |
9645 | }, |
9646 | ||
592a252b | 9647 | /* VEX_LEN_0F3A62_P_2 */ |
c0f3af97 | 9648 | { |
ec6f095a | 9649 | { "vpcmpistrm", { XM, EXx, Ib }, 0 }, |
c0f3af97 L |
9650 | }, |
9651 | ||
592a252b | 9652 | /* VEX_LEN_0F3A63_P_2 */ |
c0f3af97 | 9653 | { |
ec6f095a | 9654 | { "vpcmpistri", { XM, EXx, Ib }, 0 }, |
c0f3af97 L |
9655 | }, |
9656 | ||
592a252b | 9657 | /* VEX_LEN_0F3A6A_P_2 */ |
922d8de8 | 9658 | { |
3a2430e0 | 9659 | { "vfmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 }, |
922d8de8 DR |
9660 | }, |
9661 | ||
592a252b | 9662 | /* VEX_LEN_0F3A6B_P_2 */ |
922d8de8 | 9663 | { |
3a2430e0 | 9664 | { "vfmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 }, |
922d8de8 DR |
9665 | }, |
9666 | ||
592a252b | 9667 | /* VEX_LEN_0F3A6E_P_2 */ |
922d8de8 | 9668 | { |
3a2430e0 | 9669 | { "vfmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 }, |
922d8de8 DR |
9670 | }, |
9671 | ||
592a252b | 9672 | /* VEX_LEN_0F3A6F_P_2 */ |
922d8de8 | 9673 | { |
3a2430e0 | 9674 | { "vfmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 }, |
922d8de8 DR |
9675 | }, |
9676 | ||
592a252b | 9677 | /* VEX_LEN_0F3A7A_P_2 */ |
922d8de8 | 9678 | { |
3a2430e0 | 9679 | { "vfnmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 }, |
922d8de8 DR |
9680 | }, |
9681 | ||
592a252b | 9682 | /* VEX_LEN_0F3A7B_P_2 */ |
922d8de8 | 9683 | { |
3a2430e0 | 9684 | { "vfnmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 }, |
922d8de8 DR |
9685 | }, |
9686 | ||
592a252b | 9687 | /* VEX_LEN_0F3A7E_P_2 */ |
922d8de8 | 9688 | { |
3a2430e0 | 9689 | { "vfnmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 }, |
922d8de8 DR |
9690 | }, |
9691 | ||
592a252b | 9692 | /* VEX_LEN_0F3A7F_P_2 */ |
922d8de8 | 9693 | { |
3a2430e0 | 9694 | { "vfnmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 }, |
922d8de8 DR |
9695 | }, |
9696 | ||
592a252b | 9697 | /* VEX_LEN_0F3ADF_P_2 */ |
a5ff0eb2 | 9698 | { |
ec6f095a | 9699 | { "vaeskeygenassist", { XM, EXx, Ib }, 0 }, |
a5ff0eb2 | 9700 | }, |
4c807e72 | 9701 | |
6c30d220 L |
9702 | /* VEX_LEN_0F3AF0_P_3 */ |
9703 | { | |
bf890a93 | 9704 | { "rorxS", { Gdq, Edq, Ib }, 0 }, |
6c30d220 L |
9705 | }, |
9706 | ||
ff688e1f L |
9707 | /* VEX_LEN_0FXOP_08_CC */ |
9708 | { | |
be92cb14 | 9709 | { "vpcomb", { XM, Vex128, EXx, VPCOM }, 0 }, |
ff688e1f L |
9710 | }, |
9711 | ||
9712 | /* VEX_LEN_0FXOP_08_CD */ | |
9713 | { | |
be92cb14 | 9714 | { "vpcomw", { XM, Vex128, EXx, VPCOM }, 0 }, |
ff688e1f L |
9715 | }, |
9716 | ||
9717 | /* VEX_LEN_0FXOP_08_CE */ | |
9718 | { | |
be92cb14 | 9719 | { "vpcomd", { XM, Vex128, EXx, VPCOM }, 0 }, |
ff688e1f L |
9720 | }, |
9721 | ||
9722 | /* VEX_LEN_0FXOP_08_CF */ | |
9723 | { | |
be92cb14 | 9724 | { "vpcomq", { XM, Vex128, EXx, VPCOM }, 0 }, |
ff688e1f L |
9725 | }, |
9726 | ||
9727 | /* VEX_LEN_0FXOP_08_EC */ | |
9728 | { | |
be92cb14 | 9729 | { "vpcomub", { XM, Vex128, EXx, VPCOM }, 0 }, |
ff688e1f L |
9730 | }, |
9731 | ||
9732 | /* VEX_LEN_0FXOP_08_ED */ | |
9733 | { | |
be92cb14 | 9734 | { "vpcomuw", { XM, Vex128, EXx, VPCOM }, 0 }, |
ff688e1f L |
9735 | }, |
9736 | ||
9737 | /* VEX_LEN_0FXOP_08_EE */ | |
9738 | { | |
be92cb14 | 9739 | { "vpcomud", { XM, Vex128, EXx, VPCOM }, 0 }, |
ff688e1f L |
9740 | }, |
9741 | ||
9742 | /* VEX_LEN_0FXOP_08_EF */ | |
9743 | { | |
be92cb14 | 9744 | { "vpcomuq", { XM, Vex128, EXx, VPCOM }, 0 }, |
ff688e1f L |
9745 | }, |
9746 | ||
592a252b | 9747 | /* VEX_LEN_0FXOP_09_80 */ |
5dd85c99 | 9748 | { |
bf890a93 IT |
9749 | { "vfrczps", { XM, EXxmm }, 0 }, |
9750 | { "vfrczps", { XM, EXymmq }, 0 }, | |
5dd85c99 | 9751 | }, |
4c807e72 | 9752 | |
592a252b | 9753 | /* VEX_LEN_0FXOP_09_81 */ |
5dd85c99 | 9754 | { |
bf890a93 IT |
9755 | { "vfrczpd", { XM, EXxmm }, 0 }, |
9756 | { "vfrczpd", { XM, EXymmq }, 0 }, | |
5dd85c99 | 9757 | }, |
331d2d0d L |
9758 | }; |
9759 | ||
ad692897 | 9760 | #include "i386-dis-evex-len.h" |
04e2a182 | 9761 | |
9e30b8e0 | 9762 | static const struct dis386 vex_w_table[][2] = { |
43234a1e L |
9763 | { |
9764 | /* VEX_W_0F41_P_0_LEN_1 */ | |
ab4e4ed5 AF |
9765 | { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1) }, |
9766 | { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1) }, | |
1ba585e8 IT |
9767 | }, |
9768 | { | |
9769 | /* VEX_W_0F41_P_2_LEN_1 */ | |
ab4e4ed5 AF |
9770 | { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1) }, |
9771 | { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1) } | |
43234a1e L |
9772 | }, |
9773 | { | |
9774 | /* VEX_W_0F42_P_0_LEN_1 */ | |
ab4e4ed5 AF |
9775 | { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1) }, |
9776 | { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1) }, | |
1ba585e8 IT |
9777 | }, |
9778 | { | |
9779 | /* VEX_W_0F42_P_2_LEN_1 */ | |
ab4e4ed5 AF |
9780 | { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1) }, |
9781 | { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1) }, | |
43234a1e L |
9782 | }, |
9783 | { | |
9784 | /* VEX_W_0F44_P_0_LEN_0 */ | |
ab4e4ed5 AF |
9785 | { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1) }, |
9786 | { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1) }, | |
1ba585e8 IT |
9787 | }, |
9788 | { | |
9789 | /* VEX_W_0F44_P_2_LEN_0 */ | |
ab4e4ed5 AF |
9790 | { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1) }, |
9791 | { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1) }, | |
43234a1e L |
9792 | }, |
9793 | { | |
ec6f095a L |
9794 | /* VEX_W_0F45_P_0_LEN_1 */ |
9795 | { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1) }, | |
9796 | { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1) }, | |
9e30b8e0 L |
9797 | }, |
9798 | { | |
ec6f095a L |
9799 | /* VEX_W_0F45_P_2_LEN_1 */ |
9800 | { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1) }, | |
9801 | { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1) }, | |
9e30b8e0 L |
9802 | }, |
9803 | { | |
ec6f095a L |
9804 | /* VEX_W_0F46_P_0_LEN_1 */ |
9805 | { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1) }, | |
9806 | { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1) }, | |
9e30b8e0 L |
9807 | }, |
9808 | { | |
ec6f095a L |
9809 | /* VEX_W_0F46_P_2_LEN_1 */ |
9810 | { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1) }, | |
9811 | { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1) }, | |
9e30b8e0 L |
9812 | }, |
9813 | { | |
ec6f095a L |
9814 | /* VEX_W_0F47_P_0_LEN_1 */ |
9815 | { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1) }, | |
9816 | { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1) }, | |
9e30b8e0 L |
9817 | }, |
9818 | { | |
ec6f095a L |
9819 | /* VEX_W_0F47_P_2_LEN_1 */ |
9820 | { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1) }, | |
9821 | { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1) }, | |
9e30b8e0 L |
9822 | }, |
9823 | { | |
ec6f095a L |
9824 | /* VEX_W_0F4A_P_0_LEN_1 */ |
9825 | { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1) }, | |
9826 | { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1) }, | |
9e30b8e0 L |
9827 | }, |
9828 | { | |
ec6f095a L |
9829 | /* VEX_W_0F4A_P_2_LEN_1 */ |
9830 | { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1) }, | |
9831 | { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1) }, | |
9e30b8e0 L |
9832 | }, |
9833 | { | |
ec6f095a L |
9834 | /* VEX_W_0F4B_P_0_LEN_1 */ |
9835 | { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1) }, | |
9836 | { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1) }, | |
9e30b8e0 L |
9837 | }, |
9838 | { | |
ec6f095a L |
9839 | /* VEX_W_0F4B_P_2_LEN_1 */ |
9840 | { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1) }, | |
9e30b8e0 L |
9841 | }, |
9842 | { | |
ec6f095a L |
9843 | /* VEX_W_0F90_P_0_LEN_0 */ |
9844 | { "kmovw", { MaskG, MaskE }, 0 }, | |
9845 | { "kmovq", { MaskG, MaskE }, 0 }, | |
9e30b8e0 L |
9846 | }, |
9847 | { | |
ec6f095a L |
9848 | /* VEX_W_0F90_P_2_LEN_0 */ |
9849 | { "kmovb", { MaskG, MaskBDE }, 0 }, | |
9850 | { "kmovd", { MaskG, MaskBDE }, 0 }, | |
9e30b8e0 L |
9851 | }, |
9852 | { | |
ec6f095a L |
9853 | /* VEX_W_0F91_P_0_LEN_0 */ |
9854 | { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0) }, | |
9855 | { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0) }, | |
9e30b8e0 L |
9856 | }, |
9857 | { | |
ec6f095a L |
9858 | /* VEX_W_0F91_P_2_LEN_0 */ |
9859 | { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0) }, | |
9860 | { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0) }, | |
9e30b8e0 L |
9861 | }, |
9862 | { | |
ec6f095a L |
9863 | /* VEX_W_0F92_P_0_LEN_0 */ |
9864 | { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0) }, | |
9e30b8e0 L |
9865 | }, |
9866 | { | |
ec6f095a L |
9867 | /* VEX_W_0F92_P_2_LEN_0 */ |
9868 | { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0) }, | |
9e30b8e0 | 9869 | }, |
9e30b8e0 | 9870 | { |
ec6f095a L |
9871 | /* VEX_W_0F93_P_0_LEN_0 */ |
9872 | { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0) }, | |
9e30b8e0 L |
9873 | }, |
9874 | { | |
ec6f095a L |
9875 | /* VEX_W_0F93_P_2_LEN_0 */ |
9876 | { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0) }, | |
9e30b8e0 | 9877 | }, |
9e30b8e0 | 9878 | { |
ec6f095a L |
9879 | /* VEX_W_0F98_P_0_LEN_0 */ |
9880 | { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0) }, | |
9881 | { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0) }, | |
9e30b8e0 L |
9882 | }, |
9883 | { | |
ec6f095a L |
9884 | /* VEX_W_0F98_P_2_LEN_0 */ |
9885 | { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0) }, | |
9886 | { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0) }, | |
9e30b8e0 L |
9887 | }, |
9888 | { | |
ec6f095a L |
9889 | /* VEX_W_0F99_P_0_LEN_0 */ |
9890 | { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0) }, | |
9891 | { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0) }, | |
9e30b8e0 L |
9892 | }, |
9893 | { | |
ec6f095a L |
9894 | /* VEX_W_0F99_P_2_LEN_0 */ |
9895 | { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0) }, | |
9896 | { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0) }, | |
9e30b8e0 | 9897 | }, |
9e30b8e0 | 9898 | { |
592a252b | 9899 | /* VEX_W_0F380C_P_2 */ |
bf890a93 | 9900 | { "vpermilps", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
9901 | }, |
9902 | { | |
592a252b | 9903 | /* VEX_W_0F380D_P_2 */ |
bf890a93 | 9904 | { "vpermilpd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
9905 | }, |
9906 | { | |
592a252b | 9907 | /* VEX_W_0F380E_P_2 */ |
bf890a93 | 9908 | { "vtestps", { XM, EXx }, 0 }, |
9e30b8e0 L |
9909 | }, |
9910 | { | |
592a252b | 9911 | /* VEX_W_0F380F_P_2 */ |
bf890a93 | 9912 | { "vtestpd", { XM, EXx }, 0 }, |
9e30b8e0 | 9913 | }, |
6431c801 JB |
9914 | { |
9915 | /* VEX_W_0F3813_P_2 */ | |
9916 | { "vcvtph2ps", { XM, EXxmmq }, 0 }, | |
9917 | }, | |
6c30d220 L |
9918 | { |
9919 | /* VEX_W_0F3816_P_2 */ | |
bf890a93 | 9920 | { "vpermps", { XM, Vex, EXx }, 0 }, |
6c30d220 | 9921 | }, |
bcf2684f | 9922 | { |
6c30d220 | 9923 | /* VEX_W_0F3818_P_2 */ |
bf890a93 | 9924 | { "vbroadcastss", { XM, EXxmm_md }, 0 }, |
bcf2684f | 9925 | }, |
9e30b8e0 | 9926 | { |
6c30d220 | 9927 | /* VEX_W_0F3819_P_2 */ |
bf890a93 | 9928 | { "vbroadcastsd", { XM, EXxmm_mq }, 0 }, |
9e30b8e0 L |
9929 | }, |
9930 | { | |
592a252b | 9931 | /* VEX_W_0F381A_P_2_M_0 */ |
bf890a93 | 9932 | { "vbroadcastf128", { XM, Mxmm }, 0 }, |
9e30b8e0 | 9933 | }, |
53aa04a0 | 9934 | { |
592a252b | 9935 | /* VEX_W_0F382C_P_2_M_0 */ |
bf890a93 | 9936 | { "vmaskmovps", { XM, Vex, Mx }, 0 }, |
53aa04a0 L |
9937 | }, |
9938 | { | |
592a252b | 9939 | /* VEX_W_0F382D_P_2_M_0 */ |
bf890a93 | 9940 | { "vmaskmovpd", { XM, Vex, Mx }, 0 }, |
53aa04a0 L |
9941 | }, |
9942 | { | |
592a252b | 9943 | /* VEX_W_0F382E_P_2_M_0 */ |
bf890a93 | 9944 | { "vmaskmovps", { Mx, Vex, XM }, 0 }, |
53aa04a0 L |
9945 | }, |
9946 | { | |
592a252b | 9947 | /* VEX_W_0F382F_P_2_M_0 */ |
bf890a93 | 9948 | { "vmaskmovpd", { Mx, Vex, XM }, 0 }, |
53aa04a0 | 9949 | }, |
6c30d220 L |
9950 | { |
9951 | /* VEX_W_0F3836_P_2 */ | |
bf890a93 | 9952 | { "vpermd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 | 9953 | }, |
6c30d220 L |
9954 | { |
9955 | /* VEX_W_0F3846_P_2 */ | |
bf890a93 | 9956 | { "vpsravd", { XM, Vex, EXx }, 0 }, |
6c30d220 L |
9957 | }, |
9958 | { | |
9959 | /* VEX_W_0F3858_P_2 */ | |
bf890a93 | 9960 | { "vpbroadcastd", { XM, EXxmm_md }, 0 }, |
6c30d220 L |
9961 | }, |
9962 | { | |
9963 | /* VEX_W_0F3859_P_2 */ | |
bf890a93 | 9964 | { "vpbroadcastq", { XM, EXxmm_mq }, 0 }, |
6c30d220 L |
9965 | }, |
9966 | { | |
9967 | /* VEX_W_0F385A_P_2_M_0 */ | |
bf890a93 | 9968 | { "vbroadcasti128", { XM, Mxmm }, 0 }, |
6c30d220 L |
9969 | }, |
9970 | { | |
9971 | /* VEX_W_0F3878_P_2 */ | |
bf890a93 | 9972 | { "vpbroadcastb", { XM, EXxmm_mb }, 0 }, |
6c30d220 L |
9973 | }, |
9974 | { | |
9975 | /* VEX_W_0F3879_P_2 */ | |
bf890a93 | 9976 | { "vpbroadcastw", { XM, EXxmm_mw }, 0 }, |
6c30d220 | 9977 | }, |
48521003 IT |
9978 | { |
9979 | /* VEX_W_0F38CF_P_2 */ | |
9980 | { "vgf2p8mulb", { XM, Vex, EXx }, 0 }, | |
9981 | }, | |
6c30d220 L |
9982 | { |
9983 | /* VEX_W_0F3A00_P_2 */ | |
9984 | { Bad_Opcode }, | |
bf890a93 | 9985 | { "vpermq", { XM, EXx, Ib }, 0 }, |
6c30d220 L |
9986 | }, |
9987 | { | |
9988 | /* VEX_W_0F3A01_P_2 */ | |
9989 | { Bad_Opcode }, | |
bf890a93 | 9990 | { "vpermpd", { XM, EXx, Ib }, 0 }, |
6c30d220 L |
9991 | }, |
9992 | { | |
9993 | /* VEX_W_0F3A02_P_2 */ | |
bf890a93 | 9994 | { "vpblendd", { XM, Vex, EXx, Ib }, 0 }, |
6c30d220 | 9995 | }, |
9e30b8e0 | 9996 | { |
592a252b | 9997 | /* VEX_W_0F3A04_P_2 */ |
bf890a93 | 9998 | { "vpermilps", { XM, EXx, Ib }, 0 }, |
9e30b8e0 L |
9999 | }, |
10000 | { | |
592a252b | 10001 | /* VEX_W_0F3A05_P_2 */ |
bf890a93 | 10002 | { "vpermilpd", { XM, EXx, Ib }, 0 }, |
9e30b8e0 L |
10003 | }, |
10004 | { | |
592a252b | 10005 | /* VEX_W_0F3A06_P_2 */ |
bf890a93 | 10006 | { "vperm2f128", { XM, Vex256, EXx, Ib }, 0 }, |
9e30b8e0 | 10007 | }, |
9e30b8e0 | 10008 | { |
592a252b | 10009 | /* VEX_W_0F3A18_P_2 */ |
bf890a93 | 10010 | { "vinsertf128", { XM, Vex256, EXxmm, Ib }, 0 }, |
9e30b8e0 L |
10011 | }, |
10012 | { | |
592a252b | 10013 | /* VEX_W_0F3A19_P_2 */ |
bf890a93 | 10014 | { "vextractf128", { EXxmm, XM, Ib }, 0 }, |
9e30b8e0 | 10015 | }, |
6431c801 JB |
10016 | { |
10017 | /* VEX_W_0F3A1D_P_2 */ | |
10018 | { "vcvtps2ph", { EXxmmq, XM, EXxEVexS, Ib }, 0 }, | |
10019 | }, | |
43234a1e | 10020 | { |
1ba585e8 | 10021 | /* VEX_W_0F3A30_P_2_LEN_0 */ |
ab4e4ed5 AF |
10022 | { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0) }, |
10023 | { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0) }, | |
43234a1e L |
10024 | }, |
10025 | { | |
1ba585e8 | 10026 | /* VEX_W_0F3A31_P_2_LEN_0 */ |
ab4e4ed5 AF |
10027 | { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0) }, |
10028 | { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0) }, | |
1ba585e8 IT |
10029 | }, |
10030 | { | |
10031 | /* VEX_W_0F3A32_P_2_LEN_0 */ | |
ab4e4ed5 AF |
10032 | { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0) }, |
10033 | { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0) }, | |
43234a1e | 10034 | }, |
1ba585e8 IT |
10035 | { |
10036 | /* VEX_W_0F3A33_P_2_LEN_0 */ | |
ab4e4ed5 AF |
10037 | { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0) }, |
10038 | { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0) }, | |
1ba585e8 | 10039 | }, |
6c30d220 L |
10040 | { |
10041 | /* VEX_W_0F3A38_P_2 */ | |
bf890a93 | 10042 | { "vinserti128", { XM, Vex256, EXxmm, Ib }, 0 }, |
6c30d220 L |
10043 | }, |
10044 | { | |
10045 | /* VEX_W_0F3A39_P_2 */ | |
bf890a93 | 10046 | { "vextracti128", { EXxmm, XM, Ib }, 0 }, |
6c30d220 | 10047 | }, |
6c30d220 L |
10048 | { |
10049 | /* VEX_W_0F3A46_P_2 */ | |
bf890a93 | 10050 | { "vperm2i128", { XM, Vex256, EXx, Ib }, 0 }, |
6c30d220 | 10051 | }, |
a683cc34 | 10052 | { |
592a252b | 10053 | /* VEX_W_0F3A48_P_2 */ |
bf890a93 IT |
10054 | { "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 }, |
10055 | { "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 }, | |
a683cc34 SP |
10056 | }, |
10057 | { | |
592a252b | 10058 | /* VEX_W_0F3A49_P_2 */ |
bf890a93 IT |
10059 | { "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 }, |
10060 | { "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 }, | |
a683cc34 | 10061 | }, |
9e30b8e0 | 10062 | { |
592a252b | 10063 | /* VEX_W_0F3A4A_P_2 */ |
bf890a93 | 10064 | { "vblendvps", { XM, Vex, EXx, XMVexI4 }, 0 }, |
9e30b8e0 L |
10065 | }, |
10066 | { | |
592a252b | 10067 | /* VEX_W_0F3A4B_P_2 */ |
bf890a93 | 10068 | { "vblendvpd", { XM, Vex, EXx, XMVexI4 }, 0 }, |
9e30b8e0 L |
10069 | }, |
10070 | { | |
592a252b | 10071 | /* VEX_W_0F3A4C_P_2 */ |
bf890a93 | 10072 | { "vpblendvb", { XM, Vex, EXx, XMVexI4 }, 0 }, |
9e30b8e0 | 10073 | }, |
48521003 IT |
10074 | { |
10075 | /* VEX_W_0F3ACE_P_2 */ | |
10076 | { Bad_Opcode }, | |
10077 | { "vgf2p8affineqb", { XM, Vex, EXx, Ib }, 0 }, | |
10078 | }, | |
10079 | { | |
10080 | /* VEX_W_0F3ACF_P_2 */ | |
10081 | { Bad_Opcode }, | |
10082 | { "vgf2p8affineinvqb", { XM, Vex, EXx, Ib }, 0 }, | |
10083 | }, | |
ad692897 L |
10084 | |
10085 | #include "i386-dis-evex-w.h" | |
9e30b8e0 L |
10086 | }; |
10087 | ||
10088 | static const struct dis386 mod_table[][2] = { | |
10089 | { | |
10090 | /* MOD_8D */ | |
bf890a93 | 10091 | { "leaS", { Gv, M }, 0 }, |
9e30b8e0 | 10092 | }, |
42164a71 L |
10093 | { |
10094 | /* MOD_C6_REG_7 */ | |
10095 | { Bad_Opcode }, | |
10096 | { RM_TABLE (RM_C6_REG_7) }, | |
10097 | }, | |
10098 | { | |
10099 | /* MOD_C7_REG_7 */ | |
10100 | { Bad_Opcode }, | |
10101 | { RM_TABLE (RM_C7_REG_7) }, | |
10102 | }, | |
4a357820 MZ |
10103 | { |
10104 | /* MOD_FF_REG_3 */ | |
8f570d62 | 10105 | { "{l|}call^", { indirEp }, 0 }, |
4a357820 MZ |
10106 | }, |
10107 | { | |
10108 | /* MOD_FF_REG_5 */ | |
8f570d62 | 10109 | { "{l|}jmp^", { indirEp }, 0 }, |
4a357820 | 10110 | }, |
9e30b8e0 L |
10111 | { |
10112 | /* MOD_0F01_REG_0 */ | |
10113 | { X86_64_TABLE (X86_64_0F01_REG_0) }, | |
10114 | { RM_TABLE (RM_0F01_REG_0) }, | |
10115 | }, | |
10116 | { | |
10117 | /* MOD_0F01_REG_1 */ | |
10118 | { X86_64_TABLE (X86_64_0F01_REG_1) }, | |
10119 | { RM_TABLE (RM_0F01_REG_1) }, | |
10120 | }, | |
10121 | { | |
10122 | /* MOD_0F01_REG_2 */ | |
10123 | { X86_64_TABLE (X86_64_0F01_REG_2) }, | |
10124 | { RM_TABLE (RM_0F01_REG_2) }, | |
10125 | }, | |
10126 | { | |
10127 | /* MOD_0F01_REG_3 */ | |
10128 | { X86_64_TABLE (X86_64_0F01_REG_3) }, | |
10129 | { RM_TABLE (RM_0F01_REG_3) }, | |
10130 | }, | |
8eab4136 L |
10131 | { |
10132 | /* MOD_0F01_REG_5 */ | |
f8687e93 JB |
10133 | { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_0) }, |
10134 | { RM_TABLE (RM_0F01_REG_5_MOD_3) }, | |
8eab4136 | 10135 | }, |
9e30b8e0 L |
10136 | { |
10137 | /* MOD_0F01_REG_7 */ | |
bf890a93 | 10138 | { "invlpg", { Mb }, 0 }, |
f8687e93 | 10139 | { RM_TABLE (RM_0F01_REG_7_MOD_3) }, |
9e30b8e0 L |
10140 | }, |
10141 | { | |
10142 | /* MOD_0F12_PREFIX_0 */ | |
18897deb JB |
10143 | { "movlpX", { XM, EXq }, 0 }, |
10144 | { "movhlps", { XM, EXq }, 0 }, | |
10145 | }, | |
10146 | { | |
10147 | /* MOD_0F12_PREFIX_2 */ | |
10148 | { "movlpX", { XM, EXq }, 0 }, | |
9e30b8e0 L |
10149 | }, |
10150 | { | |
10151 | /* MOD_0F13 */ | |
507bd325 | 10152 | { "movlpX", { EXq, XM }, PREFIX_OPCODE }, |
9e30b8e0 L |
10153 | }, |
10154 | { | |
10155 | /* MOD_0F16_PREFIX_0 */ | |
18897deb | 10156 | { "movhpX", { XM, EXq }, 0 }, |
bf890a93 | 10157 | { "movlhps", { XM, EXq }, 0 }, |
9e30b8e0 | 10158 | }, |
18897deb JB |
10159 | { |
10160 | /* MOD_0F16_PREFIX_2 */ | |
10161 | { "movhpX", { XM, EXq }, 0 }, | |
10162 | }, | |
9e30b8e0 L |
10163 | { |
10164 | /* MOD_0F17 */ | |
507bd325 | 10165 | { "movhpX", { EXq, XM }, PREFIX_OPCODE }, |
9e30b8e0 L |
10166 | }, |
10167 | { | |
10168 | /* MOD_0F18_REG_0 */ | |
bf890a93 | 10169 | { "prefetchnta", { Mb }, 0 }, |
9e30b8e0 L |
10170 | }, |
10171 | { | |
10172 | /* MOD_0F18_REG_1 */ | |
bf890a93 | 10173 | { "prefetcht0", { Mb }, 0 }, |
9e30b8e0 L |
10174 | }, |
10175 | { | |
10176 | /* MOD_0F18_REG_2 */ | |
bf890a93 | 10177 | { "prefetcht1", { Mb }, 0 }, |
9e30b8e0 L |
10178 | }, |
10179 | { | |
10180 | /* MOD_0F18_REG_3 */ | |
bf890a93 | 10181 | { "prefetcht2", { Mb }, 0 }, |
9e30b8e0 | 10182 | }, |
d7189fa5 RM |
10183 | { |
10184 | /* MOD_0F18_REG_4 */ | |
bf890a93 | 10185 | { "nop/reserved", { Mb }, 0 }, |
d7189fa5 RM |
10186 | }, |
10187 | { | |
10188 | /* MOD_0F18_REG_5 */ | |
bf890a93 | 10189 | { "nop/reserved", { Mb }, 0 }, |
d7189fa5 RM |
10190 | }, |
10191 | { | |
10192 | /* MOD_0F18_REG_6 */ | |
bf890a93 | 10193 | { "nop/reserved", { Mb }, 0 }, |
d7189fa5 RM |
10194 | }, |
10195 | { | |
10196 | /* MOD_0F18_REG_7 */ | |
bf890a93 | 10197 | { "nop/reserved", { Mb }, 0 }, |
d7189fa5 | 10198 | }, |
7e8b059b L |
10199 | { |
10200 | /* MOD_0F1A_PREFIX_0 */ | |
d276ec69 | 10201 | { "bndldx", { Gbnd, Mv_bnd }, 0 }, |
bf890a93 | 10202 | { "nopQ", { Ev }, 0 }, |
7e8b059b L |
10203 | }, |
10204 | { | |
10205 | /* MOD_0F1B_PREFIX_0 */ | |
d276ec69 | 10206 | { "bndstx", { Mv_bnd, Gbnd }, 0 }, |
bf890a93 | 10207 | { "nopQ", { Ev }, 0 }, |
7e8b059b L |
10208 | }, |
10209 | { | |
10210 | /* MOD_0F1B_PREFIX_1 */ | |
d276ec69 | 10211 | { "bndmk", { Gbnd, Mv_bnd }, 0 }, |
bf890a93 | 10212 | { "nopQ", { Ev }, 0 }, |
7e8b059b | 10213 | }, |
c48935d7 IT |
10214 | { |
10215 | /* MOD_0F1C_PREFIX_0 */ | |
f8687e93 | 10216 | { REG_TABLE (REG_0F1C_P_0_MOD_0) }, |
c48935d7 IT |
10217 | { "nopQ", { Ev }, 0 }, |
10218 | }, | |
603555e5 L |
10219 | { |
10220 | /* MOD_0F1E_PREFIX_1 */ | |
10221 | { "nopQ", { Ev }, 0 }, | |
f8687e93 | 10222 | { REG_TABLE (REG_0F1E_P_1_MOD_3) }, |
603555e5 | 10223 | }, |
b844680a | 10224 | { |
92fddf8e | 10225 | /* MOD_0F24 */ |
7bb15c6f | 10226 | { Bad_Opcode }, |
bf890a93 | 10227 | { "movL", { Rd, Td }, 0 }, |
b844680a L |
10228 | }, |
10229 | { | |
92fddf8e | 10230 | /* MOD_0F26 */ |
592d1631 | 10231 | { Bad_Opcode }, |
bf890a93 | 10232 | { "movL", { Td, Rd }, 0 }, |
b844680a | 10233 | }, |
75c135a8 L |
10234 | { |
10235 | /* MOD_0F2B_PREFIX_0 */ | |
507bd325 | 10236 | {"movntps", { Mx, XM }, PREFIX_OPCODE }, |
75c135a8 L |
10237 | }, |
10238 | { | |
10239 | /* MOD_0F2B_PREFIX_1 */ | |
507bd325 | 10240 | {"movntss", { Md, XM }, PREFIX_OPCODE }, |
75c135a8 L |
10241 | }, |
10242 | { | |
10243 | /* MOD_0F2B_PREFIX_2 */ | |
507bd325 | 10244 | {"movntpd", { Mx, XM }, PREFIX_OPCODE }, |
75c135a8 L |
10245 | }, |
10246 | { | |
10247 | /* MOD_0F2B_PREFIX_3 */ | |
507bd325 | 10248 | {"movntsd", { Mq, XM }, PREFIX_OPCODE }, |
75c135a8 L |
10249 | }, |
10250 | { | |
a5aaedb9 | 10251 | /* MOD_0F50 */ |
592d1631 | 10252 | { Bad_Opcode }, |
507bd325 | 10253 | { "movmskpX", { Gdq, XS }, PREFIX_OPCODE }, |
75c135a8 | 10254 | }, |
b844680a | 10255 | { |
1ceb70f8 | 10256 | /* MOD_0F71_REG_2 */ |
592d1631 | 10257 | { Bad_Opcode }, |
bf890a93 | 10258 | { "psrlw", { MS, Ib }, 0 }, |
b844680a L |
10259 | }, |
10260 | { | |
1ceb70f8 | 10261 | /* MOD_0F71_REG_4 */ |
592d1631 | 10262 | { Bad_Opcode }, |
bf890a93 | 10263 | { "psraw", { MS, Ib }, 0 }, |
b844680a L |
10264 | }, |
10265 | { | |
1ceb70f8 | 10266 | /* MOD_0F71_REG_6 */ |
592d1631 | 10267 | { Bad_Opcode }, |
bf890a93 | 10268 | { "psllw", { MS, Ib }, 0 }, |
b844680a L |
10269 | }, |
10270 | { | |
1ceb70f8 | 10271 | /* MOD_0F72_REG_2 */ |
592d1631 | 10272 | { Bad_Opcode }, |
bf890a93 | 10273 | { "psrld", { MS, Ib }, 0 }, |
b844680a L |
10274 | }, |
10275 | { | |
1ceb70f8 | 10276 | /* MOD_0F72_REG_4 */ |
592d1631 | 10277 | { Bad_Opcode }, |
bf890a93 | 10278 | { "psrad", { MS, Ib }, 0 }, |
b844680a L |
10279 | }, |
10280 | { | |
1ceb70f8 | 10281 | /* MOD_0F72_REG_6 */ |
592d1631 | 10282 | { Bad_Opcode }, |
bf890a93 | 10283 | { "pslld", { MS, Ib }, 0 }, |
b844680a L |
10284 | }, |
10285 | { | |
1ceb70f8 | 10286 | /* MOD_0F73_REG_2 */ |
592d1631 | 10287 | { Bad_Opcode }, |
bf890a93 | 10288 | { "psrlq", { MS, Ib }, 0 }, |
b844680a L |
10289 | }, |
10290 | { | |
1ceb70f8 | 10291 | /* MOD_0F73_REG_3 */ |
592d1631 | 10292 | { Bad_Opcode }, |
c0f3af97 L |
10293 | { PREFIX_TABLE (PREFIX_0F73_REG_3) }, |
10294 | }, | |
10295 | { | |
10296 | /* MOD_0F73_REG_6 */ | |
592d1631 | 10297 | { Bad_Opcode }, |
bf890a93 | 10298 | { "psllq", { MS, Ib }, 0 }, |
c0f3af97 L |
10299 | }, |
10300 | { | |
10301 | /* MOD_0F73_REG_7 */ | |
592d1631 | 10302 | { Bad_Opcode }, |
c0f3af97 L |
10303 | { PREFIX_TABLE (PREFIX_0F73_REG_7) }, |
10304 | }, | |
10305 | { | |
10306 | /* MOD_0FAE_REG_0 */ | |
bf890a93 | 10307 | { "fxsave", { FXSAVE }, 0 }, |
f8687e93 | 10308 | { PREFIX_TABLE (PREFIX_0FAE_REG_0_MOD_3) }, |
c0f3af97 L |
10309 | }, |
10310 | { | |
10311 | /* MOD_0FAE_REG_1 */ | |
bf890a93 | 10312 | { "fxrstor", { FXSAVE }, 0 }, |
f8687e93 | 10313 | { PREFIX_TABLE (PREFIX_0FAE_REG_1_MOD_3) }, |
c0f3af97 L |
10314 | }, |
10315 | { | |
10316 | /* MOD_0FAE_REG_2 */ | |
bf890a93 | 10317 | { "ldmxcsr", { Md }, 0 }, |
f8687e93 | 10318 | { PREFIX_TABLE (PREFIX_0FAE_REG_2_MOD_3) }, |
c0f3af97 L |
10319 | }, |
10320 | { | |
10321 | /* MOD_0FAE_REG_3 */ | |
bf890a93 | 10322 | { "stmxcsr", { Md }, 0 }, |
f8687e93 | 10323 | { PREFIX_TABLE (PREFIX_0FAE_REG_3_MOD_3) }, |
c0f3af97 L |
10324 | }, |
10325 | { | |
10326 | /* MOD_0FAE_REG_4 */ | |
f8687e93 JB |
10327 | { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_0) }, |
10328 | { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_3) }, | |
c0f3af97 L |
10329 | }, |
10330 | { | |
10331 | /* MOD_0FAE_REG_5 */ | |
f8687e93 JB |
10332 | { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_0) }, |
10333 | { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_3) }, | |
c0f3af97 L |
10334 | }, |
10335 | { | |
10336 | /* MOD_0FAE_REG_6 */ | |
f8687e93 JB |
10337 | { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_0) }, |
10338 | { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_3) }, | |
c0f3af97 L |
10339 | }, |
10340 | { | |
10341 | /* MOD_0FAE_REG_7 */ | |
f8687e93 JB |
10342 | { PREFIX_TABLE (PREFIX_0FAE_REG_7_MOD_0) }, |
10343 | { RM_TABLE (RM_0FAE_REG_7_MOD_3) }, | |
c0f3af97 L |
10344 | }, |
10345 | { | |
10346 | /* MOD_0FB2 */ | |
bf890a93 | 10347 | { "lssS", { Gv, Mp }, 0 }, |
c0f3af97 L |
10348 | }, |
10349 | { | |
10350 | /* MOD_0FB4 */ | |
bf890a93 | 10351 | { "lfsS", { Gv, Mp }, 0 }, |
c0f3af97 L |
10352 | }, |
10353 | { | |
10354 | /* MOD_0FB5 */ | |
bf890a93 | 10355 | { "lgsS", { Gv, Mp }, 0 }, |
c0f3af97 | 10356 | }, |
a8484f96 L |
10357 | { |
10358 | /* MOD_0FC3 */ | |
f8687e93 | 10359 | { PREFIX_TABLE (PREFIX_0FC3_MOD_0) }, |
a8484f96 | 10360 | }, |
963f3586 IT |
10361 | { |
10362 | /* MOD_0FC7_REG_3 */ | |
a8484f96 | 10363 | { "xrstors", { FXSAVE }, 0 }, |
963f3586 IT |
10364 | }, |
10365 | { | |
10366 | /* MOD_0FC7_REG_4 */ | |
bf890a93 | 10367 | { "xsavec", { FXSAVE }, 0 }, |
963f3586 IT |
10368 | }, |
10369 | { | |
10370 | /* MOD_0FC7_REG_5 */ | |
bf890a93 | 10371 | { "xsaves", { FXSAVE }, 0 }, |
963f3586 | 10372 | }, |
c0f3af97 L |
10373 | { |
10374 | /* MOD_0FC7_REG_6 */ | |
f8687e93 JB |
10375 | { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_0) }, |
10376 | { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_3) } | |
c0f3af97 L |
10377 | }, |
10378 | { | |
10379 | /* MOD_0FC7_REG_7 */ | |
bf890a93 | 10380 | { "vmptrst", { Mq }, 0 }, |
f8687e93 | 10381 | { PREFIX_TABLE (PREFIX_0FC7_REG_7_MOD_3) } |
c0f3af97 L |
10382 | }, |
10383 | { | |
10384 | /* MOD_0FD7 */ | |
592d1631 | 10385 | { Bad_Opcode }, |
bf890a93 | 10386 | { "pmovmskb", { Gdq, MS }, 0 }, |
c0f3af97 L |
10387 | }, |
10388 | { | |
10389 | /* MOD_0FE7_PREFIX_2 */ | |
bf890a93 | 10390 | { "movntdq", { Mx, XM }, 0 }, |
c0f3af97 L |
10391 | }, |
10392 | { | |
10393 | /* MOD_0FF0_PREFIX_3 */ | |
bf890a93 | 10394 | { "lddqu", { XM, M }, 0 }, |
c0f3af97 L |
10395 | }, |
10396 | { | |
10397 | /* MOD_0F382A_PREFIX_2 */ | |
bf890a93 | 10398 | { "movntdqa", { XM, Mx }, 0 }, |
c0f3af97 | 10399 | }, |
603555e5 L |
10400 | { |
10401 | /* MOD_0F38F5_PREFIX_2 */ | |
10402 | { "wrussK", { M, Gdq }, PREFIX_OPCODE }, | |
10403 | }, | |
10404 | { | |
10405 | /* MOD_0F38F6_PREFIX_0 */ | |
10406 | { "wrssK", { M, Gdq }, PREFIX_OPCODE }, | |
10407 | }, | |
5d79adc4 L |
10408 | { |
10409 | /* MOD_0F38F8_PREFIX_1 */ | |
10410 | { "enqcmds", { Gva, M }, PREFIX_OPCODE }, | |
10411 | }, | |
c0a30a9f L |
10412 | { |
10413 | /* MOD_0F38F8_PREFIX_2 */ | |
10414 | { "movdir64b", { Gva, M }, PREFIX_OPCODE }, | |
10415 | }, | |
5d79adc4 L |
10416 | { |
10417 | /* MOD_0F38F8_PREFIX_3 */ | |
10418 | { "enqcmd", { Gva, M }, PREFIX_OPCODE }, | |
10419 | }, | |
c0a30a9f L |
10420 | { |
10421 | /* MOD_0F38F9_PREFIX_0 */ | |
77ad8092 | 10422 | { "movdiri", { Ev, Gv }, PREFIX_OPCODE }, |
c0a30a9f | 10423 | }, |
c0f3af97 L |
10424 | { |
10425 | /* MOD_62_32BIT */ | |
bf890a93 | 10426 | { "bound{S|}", { Gv, Ma }, 0 }, |
43234a1e | 10427 | { EVEX_TABLE (EVEX_0F) }, |
c0f3af97 L |
10428 | }, |
10429 | { | |
10430 | /* MOD_C4_32BIT */ | |
bf890a93 | 10431 | { "lesS", { Gv, Mp }, 0 }, |
c0f3af97 L |
10432 | { VEX_C4_TABLE (VEX_0F) }, |
10433 | }, | |
10434 | { | |
10435 | /* MOD_C5_32BIT */ | |
bf890a93 | 10436 | { "ldsS", { Gv, Mp }, 0 }, |
c0f3af97 L |
10437 | { VEX_C5_TABLE (VEX_0F) }, |
10438 | }, | |
10439 | { | |
592a252b L |
10440 | /* MOD_VEX_0F12_PREFIX_0 */ |
10441 | { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) }, | |
10442 | { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) }, | |
c0f3af97 | 10443 | }, |
18897deb JB |
10444 | { |
10445 | /* MOD_VEX_0F12_PREFIX_2 */ | |
10446 | { VEX_LEN_TABLE (VEX_LEN_0F12_P_2_M_0) }, | |
10447 | }, | |
c0f3af97 | 10448 | { |
592a252b L |
10449 | /* MOD_VEX_0F13 */ |
10450 | { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) }, | |
c0f3af97 L |
10451 | }, |
10452 | { | |
592a252b L |
10453 | /* MOD_VEX_0F16_PREFIX_0 */ |
10454 | { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) }, | |
10455 | { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) }, | |
c0f3af97 | 10456 | }, |
18897deb JB |
10457 | { |
10458 | /* MOD_VEX_0F16_PREFIX_2 */ | |
10459 | { VEX_LEN_TABLE (VEX_LEN_0F16_P_2_M_0) }, | |
10460 | }, | |
c0f3af97 | 10461 | { |
592a252b L |
10462 | /* MOD_VEX_0F17 */ |
10463 | { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) }, | |
c0f3af97 L |
10464 | }, |
10465 | { | |
592a252b | 10466 | /* MOD_VEX_0F2B */ |
bf926894 | 10467 | { "vmovntpX", { Mx, XM }, PREFIX_OPCODE }, |
c0f3af97 | 10468 | }, |
ab4e4ed5 AF |
10469 | { |
10470 | /* MOD_VEX_W_0_0F41_P_0_LEN_1 */ | |
10471 | { Bad_Opcode }, | |
10472 | { "kandw", { MaskG, MaskVex, MaskR }, 0 }, | |
10473 | }, | |
10474 | { | |
10475 | /* MOD_VEX_W_1_0F41_P_0_LEN_1 */ | |
10476 | { Bad_Opcode }, | |
10477 | { "kandq", { MaskG, MaskVex, MaskR }, 0 }, | |
10478 | }, | |
10479 | { | |
10480 | /* MOD_VEX_W_0_0F41_P_2_LEN_1 */ | |
10481 | { Bad_Opcode }, | |
10482 | { "kandb", { MaskG, MaskVex, MaskR }, 0 }, | |
10483 | }, | |
10484 | { | |
10485 | /* MOD_VEX_W_1_0F41_P_2_LEN_1 */ | |
10486 | { Bad_Opcode }, | |
10487 | { "kandd", { MaskG, MaskVex, MaskR }, 0 }, | |
10488 | }, | |
10489 | { | |
10490 | /* MOD_VEX_W_0_0F42_P_0_LEN_1 */ | |
10491 | { Bad_Opcode }, | |
10492 | { "kandnw", { MaskG, MaskVex, MaskR }, 0 }, | |
10493 | }, | |
10494 | { | |
10495 | /* MOD_VEX_W_1_0F42_P_0_LEN_1 */ | |
10496 | { Bad_Opcode }, | |
10497 | { "kandnq", { MaskG, MaskVex, MaskR }, 0 }, | |
10498 | }, | |
10499 | { | |
10500 | /* MOD_VEX_W_0_0F42_P_2_LEN_1 */ | |
10501 | { Bad_Opcode }, | |
10502 | { "kandnb", { MaskG, MaskVex, MaskR }, 0 }, | |
10503 | }, | |
10504 | { | |
10505 | /* MOD_VEX_W_1_0F42_P_2_LEN_1 */ | |
10506 | { Bad_Opcode }, | |
10507 | { "kandnd", { MaskG, MaskVex, MaskR }, 0 }, | |
10508 | }, | |
10509 | { | |
10510 | /* MOD_VEX_W_0_0F44_P_0_LEN_0 */ | |
10511 | { Bad_Opcode }, | |
10512 | { "knotw", { MaskG, MaskR }, 0 }, | |
10513 | }, | |
10514 | { | |
10515 | /* MOD_VEX_W_1_0F44_P_0_LEN_0 */ | |
10516 | { Bad_Opcode }, | |
10517 | { "knotq", { MaskG, MaskR }, 0 }, | |
10518 | }, | |
10519 | { | |
10520 | /* MOD_VEX_W_0_0F44_P_2_LEN_0 */ | |
10521 | { Bad_Opcode }, | |
10522 | { "knotb", { MaskG, MaskR }, 0 }, | |
10523 | }, | |
10524 | { | |
10525 | /* MOD_VEX_W_1_0F44_P_2_LEN_0 */ | |
10526 | { Bad_Opcode }, | |
10527 | { "knotd", { MaskG, MaskR }, 0 }, | |
10528 | }, | |
10529 | { | |
10530 | /* MOD_VEX_W_0_0F45_P_0_LEN_1 */ | |
10531 | { Bad_Opcode }, | |
10532 | { "korw", { MaskG, MaskVex, MaskR }, 0 }, | |
10533 | }, | |
10534 | { | |
10535 | /* MOD_VEX_W_1_0F45_P_0_LEN_1 */ | |
10536 | { Bad_Opcode }, | |
10537 | { "korq", { MaskG, MaskVex, MaskR }, 0 }, | |
10538 | }, | |
10539 | { | |
10540 | /* MOD_VEX_W_0_0F45_P_2_LEN_1 */ | |
10541 | { Bad_Opcode }, | |
10542 | { "korb", { MaskG, MaskVex, MaskR }, 0 }, | |
10543 | }, | |
10544 | { | |
10545 | /* MOD_VEX_W_1_0F45_P_2_LEN_1 */ | |
10546 | { Bad_Opcode }, | |
10547 | { "kord", { MaskG, MaskVex, MaskR }, 0 }, | |
10548 | }, | |
10549 | { | |
10550 | /* MOD_VEX_W_0_0F46_P_0_LEN_1 */ | |
10551 | { Bad_Opcode }, | |
10552 | { "kxnorw", { MaskG, MaskVex, MaskR }, 0 }, | |
10553 | }, | |
10554 | { | |
10555 | /* MOD_VEX_W_1_0F46_P_0_LEN_1 */ | |
10556 | { Bad_Opcode }, | |
10557 | { "kxnorq", { MaskG, MaskVex, MaskR }, 0 }, | |
10558 | }, | |
10559 | { | |
10560 | /* MOD_VEX_W_0_0F46_P_2_LEN_1 */ | |
10561 | { Bad_Opcode }, | |
10562 | { "kxnorb", { MaskG, MaskVex, MaskR }, 0 }, | |
10563 | }, | |
10564 | { | |
10565 | /* MOD_VEX_W_1_0F46_P_2_LEN_1 */ | |
10566 | { Bad_Opcode }, | |
10567 | { "kxnord", { MaskG, MaskVex, MaskR }, 0 }, | |
10568 | }, | |
10569 | { | |
10570 | /* MOD_VEX_W_0_0F47_P_0_LEN_1 */ | |
10571 | { Bad_Opcode }, | |
10572 | { "kxorw", { MaskG, MaskVex, MaskR }, 0 }, | |
10573 | }, | |
10574 | { | |
10575 | /* MOD_VEX_W_1_0F47_P_0_LEN_1 */ | |
10576 | { Bad_Opcode }, | |
10577 | { "kxorq", { MaskG, MaskVex, MaskR }, 0 }, | |
10578 | }, | |
10579 | { | |
10580 | /* MOD_VEX_W_0_0F47_P_2_LEN_1 */ | |
10581 | { Bad_Opcode }, | |
10582 | { "kxorb", { MaskG, MaskVex, MaskR }, 0 }, | |
10583 | }, | |
10584 | { | |
10585 | /* MOD_VEX_W_1_0F47_P_2_LEN_1 */ | |
10586 | { Bad_Opcode }, | |
10587 | { "kxord", { MaskG, MaskVex, MaskR }, 0 }, | |
10588 | }, | |
10589 | { | |
10590 | /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */ | |
10591 | { Bad_Opcode }, | |
10592 | { "kaddw", { MaskG, MaskVex, MaskR }, 0 }, | |
10593 | }, | |
10594 | { | |
10595 | /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */ | |
10596 | { Bad_Opcode }, | |
10597 | { "kaddq", { MaskG, MaskVex, MaskR }, 0 }, | |
10598 | }, | |
10599 | { | |
10600 | /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */ | |
10601 | { Bad_Opcode }, | |
10602 | { "kaddb", { MaskG, MaskVex, MaskR }, 0 }, | |
10603 | }, | |
10604 | { | |
10605 | /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */ | |
10606 | { Bad_Opcode }, | |
10607 | { "kaddd", { MaskG, MaskVex, MaskR }, 0 }, | |
10608 | }, | |
10609 | { | |
10610 | /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */ | |
10611 | { Bad_Opcode }, | |
10612 | { "kunpckwd", { MaskG, MaskVex, MaskR }, 0 }, | |
10613 | }, | |
10614 | { | |
10615 | /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */ | |
10616 | { Bad_Opcode }, | |
10617 | { "kunpckdq", { MaskG, MaskVex, MaskR }, 0 }, | |
10618 | }, | |
10619 | { | |
10620 | /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */ | |
10621 | { Bad_Opcode }, | |
10622 | { "kunpckbw", { MaskG, MaskVex, MaskR }, 0 }, | |
10623 | }, | |
c0f3af97 | 10624 | { |
592a252b | 10625 | /* MOD_VEX_0F50 */ |
592d1631 | 10626 | { Bad_Opcode }, |
bf926894 | 10627 | { "vmovmskpX", { Gdq, XS }, PREFIX_OPCODE }, |
c0f3af97 L |
10628 | }, |
10629 | { | |
592a252b | 10630 | /* MOD_VEX_0F71_REG_2 */ |
592d1631 | 10631 | { Bad_Opcode }, |
592a252b | 10632 | { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) }, |
b844680a L |
10633 | }, |
10634 | { | |
592a252b | 10635 | /* MOD_VEX_0F71_REG_4 */ |
592d1631 | 10636 | { Bad_Opcode }, |
592a252b | 10637 | { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) }, |
b844680a L |
10638 | }, |
10639 | { | |
592a252b | 10640 | /* MOD_VEX_0F71_REG_6 */ |
592d1631 | 10641 | { Bad_Opcode }, |
592a252b | 10642 | { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) }, |
b844680a L |
10643 | }, |
10644 | { | |
592a252b | 10645 | /* MOD_VEX_0F72_REG_2 */ |
592d1631 | 10646 | { Bad_Opcode }, |
592a252b | 10647 | { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) }, |
b844680a | 10648 | }, |
d8faab4e | 10649 | { |
592a252b | 10650 | /* MOD_VEX_0F72_REG_4 */ |
592d1631 | 10651 | { Bad_Opcode }, |
592a252b | 10652 | { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) }, |
d8faab4e L |
10653 | }, |
10654 | { | |
592a252b | 10655 | /* MOD_VEX_0F72_REG_6 */ |
592d1631 | 10656 | { Bad_Opcode }, |
592a252b | 10657 | { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) }, |
d8faab4e | 10658 | }, |
876d4bfa | 10659 | { |
592a252b | 10660 | /* MOD_VEX_0F73_REG_2 */ |
592d1631 | 10661 | { Bad_Opcode }, |
592a252b | 10662 | { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) }, |
876d4bfa L |
10663 | }, |
10664 | { | |
592a252b | 10665 | /* MOD_VEX_0F73_REG_3 */ |
592d1631 | 10666 | { Bad_Opcode }, |
592a252b | 10667 | { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) }, |
475a2301 L |
10668 | }, |
10669 | { | |
592a252b | 10670 | /* MOD_VEX_0F73_REG_6 */ |
592d1631 | 10671 | { Bad_Opcode }, |
592a252b | 10672 | { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) }, |
876d4bfa L |
10673 | }, |
10674 | { | |
592a252b | 10675 | /* MOD_VEX_0F73_REG_7 */ |
592d1631 | 10676 | { Bad_Opcode }, |
592a252b | 10677 | { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) }, |
876d4bfa | 10678 | }, |
ab4e4ed5 AF |
10679 | { |
10680 | /* MOD_VEX_W_0_0F91_P_0_LEN_0 */ | |
10681 | { "kmovw", { Ew, MaskG }, 0 }, | |
10682 | { Bad_Opcode }, | |
10683 | }, | |
10684 | { | |
10685 | /* MOD_VEX_W_0_0F91_P_0_LEN_0 */ | |
10686 | { "kmovq", { Eq, MaskG }, 0 }, | |
10687 | { Bad_Opcode }, | |
10688 | }, | |
10689 | { | |
10690 | /* MOD_VEX_W_0_0F91_P_2_LEN_0 */ | |
10691 | { "kmovb", { Eb, MaskG }, 0 }, | |
10692 | { Bad_Opcode }, | |
10693 | }, | |
10694 | { | |
10695 | /* MOD_VEX_W_0_0F91_P_2_LEN_0 */ | |
10696 | { "kmovd", { Ed, MaskG }, 0 }, | |
10697 | { Bad_Opcode }, | |
10698 | }, | |
10699 | { | |
10700 | /* MOD_VEX_W_0_0F92_P_0_LEN_0 */ | |
10701 | { Bad_Opcode }, | |
10702 | { "kmovw", { MaskG, Rdq }, 0 }, | |
10703 | }, | |
10704 | { | |
10705 | /* MOD_VEX_W_0_0F92_P_2_LEN_0 */ | |
10706 | { Bad_Opcode }, | |
10707 | { "kmovb", { MaskG, Rdq }, 0 }, | |
10708 | }, | |
10709 | { | |
58a211d2 | 10710 | /* MOD_VEX_0F92_P_3_LEN_0 */ |
ab4e4ed5 | 10711 | { Bad_Opcode }, |
58a211d2 | 10712 | { "kmovK", { MaskG, Rdq }, 0 }, |
ab4e4ed5 AF |
10713 | }, |
10714 | { | |
10715 | /* MOD_VEX_W_0_0F93_P_0_LEN_0 */ | |
10716 | { Bad_Opcode }, | |
10717 | { "kmovw", { Gdq, MaskR }, 0 }, | |
10718 | }, | |
10719 | { | |
10720 | /* MOD_VEX_W_0_0F93_P_2_LEN_0 */ | |
10721 | { Bad_Opcode }, | |
10722 | { "kmovb", { Gdq, MaskR }, 0 }, | |
10723 | }, | |
10724 | { | |
58a211d2 | 10725 | /* MOD_VEX_0F93_P_3_LEN_0 */ |
ab4e4ed5 | 10726 | { Bad_Opcode }, |
58a211d2 | 10727 | { "kmovK", { Gdq, MaskR }, 0 }, |
ab4e4ed5 AF |
10728 | }, |
10729 | { | |
10730 | /* MOD_VEX_W_0_0F98_P_0_LEN_0 */ | |
10731 | { Bad_Opcode }, | |
10732 | { "kortestw", { MaskG, MaskR }, 0 }, | |
10733 | }, | |
10734 | { | |
10735 | /* MOD_VEX_W_1_0F98_P_0_LEN_0 */ | |
10736 | { Bad_Opcode }, | |
10737 | { "kortestq", { MaskG, MaskR }, 0 }, | |
10738 | }, | |
10739 | { | |
10740 | /* MOD_VEX_W_0_0F98_P_2_LEN_0 */ | |
10741 | { Bad_Opcode }, | |
10742 | { "kortestb", { MaskG, MaskR }, 0 }, | |
10743 | }, | |
10744 | { | |
10745 | /* MOD_VEX_W_1_0F98_P_2_LEN_0 */ | |
10746 | { Bad_Opcode }, | |
10747 | { "kortestd", { MaskG, MaskR }, 0 }, | |
10748 | }, | |
10749 | { | |
10750 | /* MOD_VEX_W_0_0F99_P_0_LEN_0 */ | |
10751 | { Bad_Opcode }, | |
10752 | { "ktestw", { MaskG, MaskR }, 0 }, | |
10753 | }, | |
10754 | { | |
10755 | /* MOD_VEX_W_1_0F99_P_0_LEN_0 */ | |
10756 | { Bad_Opcode }, | |
10757 | { "ktestq", { MaskG, MaskR }, 0 }, | |
10758 | }, | |
10759 | { | |
10760 | /* MOD_VEX_W_0_0F99_P_2_LEN_0 */ | |
10761 | { Bad_Opcode }, | |
10762 | { "ktestb", { MaskG, MaskR }, 0 }, | |
10763 | }, | |
10764 | { | |
10765 | /* MOD_VEX_W_1_0F99_P_2_LEN_0 */ | |
10766 | { Bad_Opcode }, | |
10767 | { "ktestd", { MaskG, MaskR }, 0 }, | |
10768 | }, | |
876d4bfa | 10769 | { |
592a252b L |
10770 | /* MOD_VEX_0FAE_REG_2 */ |
10771 | { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) }, | |
876d4bfa | 10772 | }, |
bbedc832 | 10773 | { |
592a252b L |
10774 | /* MOD_VEX_0FAE_REG_3 */ |
10775 | { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) }, | |
bbedc832 | 10776 | }, |
144c41d9 | 10777 | { |
592a252b | 10778 | /* MOD_VEX_0FD7_PREFIX_2 */ |
592d1631 | 10779 | { Bad_Opcode }, |
ec6f095a | 10780 | { "vpmovmskb", { Gdq, XS }, 0 }, |
144c41d9 | 10781 | }, |
1afd85e3 | 10782 | { |
592a252b | 10783 | /* MOD_VEX_0FE7_PREFIX_2 */ |
ec6f095a | 10784 | { "vmovntdq", { Mx, XM }, 0 }, |
1afd85e3 L |
10785 | }, |
10786 | { | |
592a252b | 10787 | /* MOD_VEX_0FF0_PREFIX_3 */ |
ec6f095a | 10788 | { "vlddqu", { XM, M }, 0 }, |
92fddf8e | 10789 | }, |
75c135a8 | 10790 | { |
592a252b L |
10791 | /* MOD_VEX_0F381A_PREFIX_2 */ |
10792 | { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) }, | |
75c135a8 | 10793 | }, |
1afd85e3 | 10794 | { |
592a252b | 10795 | /* MOD_VEX_0F382A_PREFIX_2 */ |
ec6f095a | 10796 | { "vmovntdqa", { XM, Mx }, 0 }, |
1afd85e3 | 10797 | }, |
75c135a8 | 10798 | { |
592a252b L |
10799 | /* MOD_VEX_0F382C_PREFIX_2 */ |
10800 | { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) }, | |
75c135a8 | 10801 | }, |
1afd85e3 | 10802 | { |
592a252b L |
10803 | /* MOD_VEX_0F382D_PREFIX_2 */ |
10804 | { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) }, | |
1afd85e3 L |
10805 | }, |
10806 | { | |
592a252b L |
10807 | /* MOD_VEX_0F382E_PREFIX_2 */ |
10808 | { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) }, | |
1afd85e3 L |
10809 | }, |
10810 | { | |
592a252b L |
10811 | /* MOD_VEX_0F382F_PREFIX_2 */ |
10812 | { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) }, | |
1afd85e3 | 10813 | }, |
6c30d220 L |
10814 | { |
10815 | /* MOD_VEX_0F385A_PREFIX_2 */ | |
10816 | { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) }, | |
10817 | }, | |
10818 | { | |
10819 | /* MOD_VEX_0F388C_PREFIX_2 */ | |
bf890a93 | 10820 | { "vpmaskmov%LW", { XM, Vex, Mx }, 0 }, |
6c30d220 L |
10821 | }, |
10822 | { | |
10823 | /* MOD_VEX_0F388E_PREFIX_2 */ | |
bf890a93 | 10824 | { "vpmaskmov%LW", { Mx, Vex, XM }, 0 }, |
6c30d220 | 10825 | }, |
ab4e4ed5 AF |
10826 | { |
10827 | /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */ | |
10828 | { Bad_Opcode }, | |
10829 | { "kshiftrb", { MaskG, MaskR, Ib }, 0 }, | |
10830 | }, | |
10831 | { | |
10832 | /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */ | |
10833 | { Bad_Opcode }, | |
10834 | { "kshiftrw", { MaskG, MaskR, Ib }, 0 }, | |
10835 | }, | |
10836 | { | |
10837 | /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */ | |
10838 | { Bad_Opcode }, | |
10839 | { "kshiftrd", { MaskG, MaskR, Ib }, 0 }, | |
10840 | }, | |
10841 | { | |
10842 | /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */ | |
10843 | { Bad_Opcode }, | |
10844 | { "kshiftrq", { MaskG, MaskR, Ib }, 0 }, | |
10845 | }, | |
10846 | { | |
10847 | /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */ | |
10848 | { Bad_Opcode }, | |
10849 | { "kshiftlb", { MaskG, MaskR, Ib }, 0 }, | |
10850 | }, | |
10851 | { | |
10852 | /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */ | |
10853 | { Bad_Opcode }, | |
10854 | { "kshiftlw", { MaskG, MaskR, Ib }, 0 }, | |
10855 | }, | |
10856 | { | |
10857 | /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */ | |
10858 | { Bad_Opcode }, | |
10859 | { "kshiftld", { MaskG, MaskR, Ib }, 0 }, | |
10860 | }, | |
10861 | { | |
10862 | /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */ | |
10863 | { Bad_Opcode }, | |
10864 | { "kshiftlq", { MaskG, MaskR, Ib }, 0 }, | |
10865 | }, | |
ad692897 L |
10866 | |
10867 | #include "i386-dis-evex-mod.h" | |
b844680a L |
10868 | }; |
10869 | ||
1ceb70f8 | 10870 | static const struct dis386 rm_table[][8] = { |
42164a71 L |
10871 | { |
10872 | /* RM_C6_REG_7 */ | |
bf890a93 | 10873 | { "xabort", { Skip_MODRM, Ib }, 0 }, |
42164a71 L |
10874 | }, |
10875 | { | |
10876 | /* RM_C7_REG_7 */ | |
376cd056 | 10877 | { "xbeginT", { Skip_MODRM, Jdqw }, 0 }, |
42164a71 | 10878 | }, |
b844680a | 10879 | { |
1ceb70f8 | 10880 | /* RM_0F01_REG_0 */ |
a4e78aa5 | 10881 | { "enclv", { Skip_MODRM }, 0 }, |
bf890a93 IT |
10882 | { "vmcall", { Skip_MODRM }, 0 }, |
10883 | { "vmlaunch", { Skip_MODRM }, 0 }, | |
10884 | { "vmresume", { Skip_MODRM }, 0 }, | |
10885 | { "vmxoff", { Skip_MODRM }, 0 }, | |
be3a8dca | 10886 | { "pconfig", { Skip_MODRM }, 0 }, |
b844680a L |
10887 | }, |
10888 | { | |
1ceb70f8 | 10889 | /* RM_0F01_REG_1 */ |
bf890a93 IT |
10890 | { "monitor", { { OP_Monitor, 0 } }, 0 }, |
10891 | { "mwait", { { OP_Mwait, 0 } }, 0 }, | |
10892 | { "clac", { Skip_MODRM }, 0 }, | |
10893 | { "stac", { Skip_MODRM }, 0 }, | |
2cf200a4 IT |
10894 | { Bad_Opcode }, |
10895 | { Bad_Opcode }, | |
10896 | { Bad_Opcode }, | |
bf890a93 | 10897 | { "encls", { Skip_MODRM }, 0 }, |
b844680a | 10898 | }, |
475a2301 L |
10899 | { |
10900 | /* RM_0F01_REG_2 */ | |
bf890a93 IT |
10901 | { "xgetbv", { Skip_MODRM }, 0 }, |
10902 | { "xsetbv", { Skip_MODRM }, 0 }, | |
8729a6f6 L |
10903 | { Bad_Opcode }, |
10904 | { Bad_Opcode }, | |
bf890a93 IT |
10905 | { "vmfunc", { Skip_MODRM }, 0 }, |
10906 | { "xend", { Skip_MODRM }, 0 }, | |
10907 | { "xtest", { Skip_MODRM }, 0 }, | |
10908 | { "enclu", { Skip_MODRM }, 0 }, | |
475a2301 | 10909 | }, |
b844680a | 10910 | { |
1ceb70f8 | 10911 | /* RM_0F01_REG_3 */ |
bf890a93 | 10912 | { "vmrun", { Skip_MODRM }, 0 }, |
a847e322 | 10913 | { PREFIX_TABLE (PREFIX_0F01_REG_3_RM_1) }, |
bf890a93 IT |
10914 | { "vmload", { Skip_MODRM }, 0 }, |
10915 | { "vmsave", { Skip_MODRM }, 0 }, | |
10916 | { "stgi", { Skip_MODRM }, 0 }, | |
10917 | { "clgi", { Skip_MODRM }, 0 }, | |
10918 | { "skinit", { Skip_MODRM }, 0 }, | |
10919 | { "invlpga", { Skip_MODRM }, 0 }, | |
4e7d34a6 | 10920 | }, |
8eab4136 | 10921 | { |
f8687e93 JB |
10922 | /* RM_0F01_REG_5_MOD_3 */ |
10923 | { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_0) }, | |
bb651e8b | 10924 | { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_1) }, |
f8687e93 | 10925 | { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_2) }, |
8eab4136 L |
10926 | { Bad_Opcode }, |
10927 | { Bad_Opcode }, | |
10928 | { Bad_Opcode }, | |
10929 | { "rdpkru", { Skip_MODRM }, 0 }, | |
10930 | { "wrpkru", { Skip_MODRM }, 0 }, | |
10931 | }, | |
4e7d34a6 | 10932 | { |
f8687e93 | 10933 | /* RM_0F01_REG_7_MOD_3 */ |
bf890a93 IT |
10934 | { "swapgs", { Skip_MODRM }, 0 }, |
10935 | { "rdtscp", { Skip_MODRM }, 0 }, | |
267b8516 JB |
10936 | { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_2) }, |
10937 | { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_3) }, | |
bf890a93 | 10938 | { "clzero", { Skip_MODRM }, 0 }, |
142861df | 10939 | { "rdpru", { Skip_MODRM }, 0 }, |
b844680a | 10940 | }, |
603555e5 | 10941 | { |
f8687e93 | 10942 | /* RM_0F1E_P_1_MOD_3_REG_7 */ |
603555e5 L |
10943 | { "nopQ", { Ev }, 0 }, |
10944 | { "nopQ", { Ev }, 0 }, | |
10945 | { "endbr64", { Skip_MODRM }, PREFIX_OPCODE }, | |
10946 | { "endbr32", { Skip_MODRM }, PREFIX_OPCODE }, | |
10947 | { "nopQ", { Ev }, 0 }, | |
10948 | { "nopQ", { Ev }, 0 }, | |
10949 | { "nopQ", { Ev }, 0 }, | |
10950 | { "nopQ", { Ev }, 0 }, | |
10951 | }, | |
b844680a | 10952 | { |
f8687e93 | 10953 | /* RM_0FAE_REG_6_MOD_3 */ |
bf890a93 | 10954 | { "mfence", { Skip_MODRM }, 0 }, |
b844680a | 10955 | }, |
bbedc832 | 10956 | { |
f8687e93 | 10957 | /* RM_0FAE_REG_7_MOD_3 */ |
b5cefcca L |
10958 | { "sfence", { Skip_MODRM }, 0 }, |
10959 | ||
144c41d9 | 10960 | }, |
b844680a L |
10961 | }; |
10962 | ||
c608c12e AM |
10963 | #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>") |
10964 | ||
f16cd0d5 L |
10965 | /* We use the high bit to indicate different name for the same |
10966 | prefix. */ | |
f16cd0d5 | 10967 | #define REP_PREFIX (0xf3 | 0x100) |
42164a71 L |
10968 | #define XACQUIRE_PREFIX (0xf2 | 0x200) |
10969 | #define XRELEASE_PREFIX (0xf3 | 0x400) | |
7e8b059b | 10970 | #define BND_PREFIX (0xf2 | 0x400) |
04ef582a | 10971 | #define NOTRACK_PREFIX (0x3e | 0x100) |
f16cd0d5 | 10972 | |
1d67fe3b TT |
10973 | /* Remember if the current op is a jump instruction. */ |
10974 | static bfd_boolean op_is_jump = FALSE; | |
10975 | ||
f16cd0d5 | 10976 | static int |
26ca5450 | 10977 | ckprefix (void) |
252b5132 | 10978 | { |
f16cd0d5 | 10979 | int newrex, i, length; |
52b15da3 | 10980 | rex = 0; |
252b5132 | 10981 | prefixes = 0; |
7d421014 | 10982 | used_prefixes = 0; |
52b15da3 | 10983 | rex_used = 0; |
f16cd0d5 L |
10984 | last_lock_prefix = -1; |
10985 | last_repz_prefix = -1; | |
10986 | last_repnz_prefix = -1; | |
10987 | last_data_prefix = -1; | |
10988 | last_addr_prefix = -1; | |
10989 | last_rex_prefix = -1; | |
10990 | last_seg_prefix = -1; | |
d9949a36 | 10991 | fwait_prefix = -1; |
285ca992 | 10992 | active_seg_prefix = 0; |
f310f33d L |
10993 | for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++) |
10994 | all_prefixes[i] = 0; | |
10995 | i = 0; | |
f16cd0d5 L |
10996 | length = 0; |
10997 | /* The maximum instruction length is 15bytes. */ | |
10998 | while (length < MAX_CODE_LENGTH - 1) | |
252b5132 RH |
10999 | { |
11000 | FETCH_DATA (the_info, codep + 1); | |
52b15da3 | 11001 | newrex = 0; |
252b5132 RH |
11002 | switch (*codep) |
11003 | { | |
52b15da3 JH |
11004 | /* REX prefixes family. */ |
11005 | case 0x40: | |
11006 | case 0x41: | |
11007 | case 0x42: | |
11008 | case 0x43: | |
11009 | case 0x44: | |
11010 | case 0x45: | |
11011 | case 0x46: | |
11012 | case 0x47: | |
11013 | case 0x48: | |
11014 | case 0x49: | |
11015 | case 0x4a: | |
11016 | case 0x4b: | |
11017 | case 0x4c: | |
11018 | case 0x4d: | |
11019 | case 0x4e: | |
11020 | case 0x4f: | |
f16cd0d5 L |
11021 | if (address_mode == mode_64bit) |
11022 | newrex = *codep; | |
11023 | else | |
11024 | return 1; | |
11025 | last_rex_prefix = i; | |
52b15da3 | 11026 | break; |
252b5132 RH |
11027 | case 0xf3: |
11028 | prefixes |= PREFIX_REPZ; | |
f16cd0d5 | 11029 | last_repz_prefix = i; |
252b5132 RH |
11030 | break; |
11031 | case 0xf2: | |
11032 | prefixes |= PREFIX_REPNZ; | |
f16cd0d5 | 11033 | last_repnz_prefix = i; |
252b5132 RH |
11034 | break; |
11035 | case 0xf0: | |
11036 | prefixes |= PREFIX_LOCK; | |
f16cd0d5 | 11037 | last_lock_prefix = i; |
252b5132 RH |
11038 | break; |
11039 | case 0x2e: | |
11040 | prefixes |= PREFIX_CS; | |
f16cd0d5 | 11041 | last_seg_prefix = i; |
285ca992 | 11042 | active_seg_prefix = PREFIX_CS; |
252b5132 RH |
11043 | break; |
11044 | case 0x36: | |
11045 | prefixes |= PREFIX_SS; | |
f16cd0d5 | 11046 | last_seg_prefix = i; |
285ca992 | 11047 | active_seg_prefix = PREFIX_SS; |
252b5132 RH |
11048 | break; |
11049 | case 0x3e: | |
11050 | prefixes |= PREFIX_DS; | |
f16cd0d5 | 11051 | last_seg_prefix = i; |
285ca992 | 11052 | active_seg_prefix = PREFIX_DS; |
252b5132 RH |
11053 | break; |
11054 | case 0x26: | |
11055 | prefixes |= PREFIX_ES; | |
f16cd0d5 | 11056 | last_seg_prefix = i; |
285ca992 | 11057 | active_seg_prefix = PREFIX_ES; |
252b5132 RH |
11058 | break; |
11059 | case 0x64: | |
11060 | prefixes |= PREFIX_FS; | |
f16cd0d5 | 11061 | last_seg_prefix = i; |
285ca992 | 11062 | active_seg_prefix = PREFIX_FS; |
252b5132 RH |
11063 | break; |
11064 | case 0x65: | |
11065 | prefixes |= PREFIX_GS; | |
f16cd0d5 | 11066 | last_seg_prefix = i; |
285ca992 | 11067 | active_seg_prefix = PREFIX_GS; |
252b5132 RH |
11068 | break; |
11069 | case 0x66: | |
11070 | prefixes |= PREFIX_DATA; | |
f16cd0d5 | 11071 | last_data_prefix = i; |
252b5132 RH |
11072 | break; |
11073 | case 0x67: | |
11074 | prefixes |= PREFIX_ADDR; | |
f16cd0d5 | 11075 | last_addr_prefix = i; |
252b5132 | 11076 | break; |
5076851f | 11077 | case FWAIT_OPCODE: |
252b5132 RH |
11078 | /* fwait is really an instruction. If there are prefixes |
11079 | before the fwait, they belong to the fwait, *not* to the | |
11080 | following instruction. */ | |
d9949a36 | 11081 | fwait_prefix = i; |
3e7d61b2 | 11082 | if (prefixes || rex) |
252b5132 RH |
11083 | { |
11084 | prefixes |= PREFIX_FWAIT; | |
11085 | codep++; | |
6c067bbb RM |
11086 | /* This ensures that the previous REX prefixes are noticed |
11087 | as unused prefixes, as in the return case below. */ | |
11088 | rex_used = rex; | |
f16cd0d5 | 11089 | return 1; |
252b5132 RH |
11090 | } |
11091 | prefixes = PREFIX_FWAIT; | |
11092 | break; | |
11093 | default: | |
f16cd0d5 | 11094 | return 1; |
252b5132 | 11095 | } |
52b15da3 JH |
11096 | /* Rex is ignored when followed by another prefix. */ |
11097 | if (rex) | |
11098 | { | |
3e7d61b2 | 11099 | rex_used = rex; |
f16cd0d5 | 11100 | return 1; |
52b15da3 | 11101 | } |
f16cd0d5 | 11102 | if (*codep != FWAIT_OPCODE) |
4e9ac44a | 11103 | all_prefixes[i++] = *codep; |
52b15da3 | 11104 | rex = newrex; |
252b5132 | 11105 | codep++; |
f16cd0d5 L |
11106 | length++; |
11107 | } | |
11108 | return 0; | |
11109 | } | |
11110 | ||
7d421014 ILT |
11111 | /* Return the name of the prefix byte PREF, or NULL if PREF is not a |
11112 | prefix byte. */ | |
11113 | ||
11114 | static const char * | |
26ca5450 | 11115 | prefix_name (int pref, int sizeflag) |
7d421014 | 11116 | { |
0003779b L |
11117 | static const char *rexes [16] = |
11118 | { | |
11119 | "rex", /* 0x40 */ | |
11120 | "rex.B", /* 0x41 */ | |
11121 | "rex.X", /* 0x42 */ | |
11122 | "rex.XB", /* 0x43 */ | |
11123 | "rex.R", /* 0x44 */ | |
11124 | "rex.RB", /* 0x45 */ | |
11125 | "rex.RX", /* 0x46 */ | |
11126 | "rex.RXB", /* 0x47 */ | |
11127 | "rex.W", /* 0x48 */ | |
11128 | "rex.WB", /* 0x49 */ | |
11129 | "rex.WX", /* 0x4a */ | |
11130 | "rex.WXB", /* 0x4b */ | |
11131 | "rex.WR", /* 0x4c */ | |
11132 | "rex.WRB", /* 0x4d */ | |
11133 | "rex.WRX", /* 0x4e */ | |
11134 | "rex.WRXB", /* 0x4f */ | |
11135 | }; | |
11136 | ||
7d421014 ILT |
11137 | switch (pref) |
11138 | { | |
52b15da3 JH |
11139 | /* REX prefixes family. */ |
11140 | case 0x40: | |
52b15da3 | 11141 | case 0x41: |
52b15da3 | 11142 | case 0x42: |
52b15da3 | 11143 | case 0x43: |
52b15da3 | 11144 | case 0x44: |
52b15da3 | 11145 | case 0x45: |
52b15da3 | 11146 | case 0x46: |
52b15da3 | 11147 | case 0x47: |
52b15da3 | 11148 | case 0x48: |
52b15da3 | 11149 | case 0x49: |
52b15da3 | 11150 | case 0x4a: |
52b15da3 | 11151 | case 0x4b: |
52b15da3 | 11152 | case 0x4c: |
52b15da3 | 11153 | case 0x4d: |
52b15da3 | 11154 | case 0x4e: |
52b15da3 | 11155 | case 0x4f: |
0003779b | 11156 | return rexes [pref - 0x40]; |
7d421014 ILT |
11157 | case 0xf3: |
11158 | return "repz"; | |
11159 | case 0xf2: | |
11160 | return "repnz"; | |
11161 | case 0xf0: | |
11162 | return "lock"; | |
11163 | case 0x2e: | |
11164 | return "cs"; | |
11165 | case 0x36: | |
11166 | return "ss"; | |
11167 | case 0x3e: | |
11168 | return "ds"; | |
11169 | case 0x26: | |
11170 | return "es"; | |
11171 | case 0x64: | |
11172 | return "fs"; | |
11173 | case 0x65: | |
11174 | return "gs"; | |
11175 | case 0x66: | |
11176 | return (sizeflag & DFLAG) ? "data16" : "data32"; | |
11177 | case 0x67: | |
cb712a9e | 11178 | if (address_mode == mode_64bit) |
db6eb5be | 11179 | return (sizeflag & AFLAG) ? "addr32" : "addr64"; |
c1a64871 | 11180 | else |
2888cb7a | 11181 | return (sizeflag & AFLAG) ? "addr16" : "addr32"; |
7d421014 ILT |
11182 | case FWAIT_OPCODE: |
11183 | return "fwait"; | |
f16cd0d5 L |
11184 | case REP_PREFIX: |
11185 | return "rep"; | |
42164a71 L |
11186 | case XACQUIRE_PREFIX: |
11187 | return "xacquire"; | |
11188 | case XRELEASE_PREFIX: | |
11189 | return "xrelease"; | |
7e8b059b L |
11190 | case BND_PREFIX: |
11191 | return "bnd"; | |
04ef582a L |
11192 | case NOTRACK_PREFIX: |
11193 | return "notrack"; | |
7d421014 ILT |
11194 | default: |
11195 | return NULL; | |
11196 | } | |
11197 | } | |
11198 | ||
ce518a5f L |
11199 | static char op_out[MAX_OPERANDS][100]; |
11200 | static int op_ad, op_index[MAX_OPERANDS]; | |
1d9f512f | 11201 | static int two_source_ops; |
ce518a5f L |
11202 | static bfd_vma op_address[MAX_OPERANDS]; |
11203 | static bfd_vma op_riprel[MAX_OPERANDS]; | |
52b15da3 | 11204 | static bfd_vma start_pc; |
ce518a5f | 11205 | |
252b5132 RH |
11206 | /* |
11207 | * On the 386's of 1988, the maximum length of an instruction is 15 bytes. | |
11208 | * (see topic "Redundant prefixes" in the "Differences from 8086" | |
11209 | * section of the "Virtual 8086 Mode" chapter.) | |
11210 | * 'pc' should be the address of this instruction, it will | |
11211 | * be used to print the target address if this is a relative jump or call | |
11212 | * The function returns the length of this instruction in bytes. | |
11213 | */ | |
11214 | ||
252b5132 | 11215 | static char intel_syntax; |
9d141669 | 11216 | static char intel_mnemonic = !SYSV386_COMPAT; |
252b5132 RH |
11217 | static char open_char; |
11218 | static char close_char; | |
11219 | static char separator_char; | |
11220 | static char scale_char; | |
11221 | ||
5db04b09 L |
11222 | enum x86_64_isa |
11223 | { | |
d835a58b | 11224 | amd64 = 1, |
5db04b09 L |
11225 | intel64 |
11226 | }; | |
11227 | ||
11228 | static enum x86_64_isa isa64; | |
11229 | ||
e396998b AM |
11230 | /* Here for backwards compatibility. When gdb stops using |
11231 | print_insn_i386_att and print_insn_i386_intel these functions can | |
11232 | disappear, and print_insn_i386 be merged into print_insn. */ | |
252b5132 | 11233 | int |
26ca5450 | 11234 | print_insn_i386_att (bfd_vma pc, disassemble_info *info) |
252b5132 RH |
11235 | { |
11236 | intel_syntax = 0; | |
e396998b AM |
11237 | |
11238 | return print_insn (pc, info); | |
252b5132 RH |
11239 | } |
11240 | ||
11241 | int | |
26ca5450 | 11242 | print_insn_i386_intel (bfd_vma pc, disassemble_info *info) |
252b5132 RH |
11243 | { |
11244 | intel_syntax = 1; | |
e396998b AM |
11245 | |
11246 | return print_insn (pc, info); | |
252b5132 RH |
11247 | } |
11248 | ||
e396998b | 11249 | int |
26ca5450 | 11250 | print_insn_i386 (bfd_vma pc, disassemble_info *info) |
e396998b AM |
11251 | { |
11252 | intel_syntax = -1; | |
11253 | ||
11254 | return print_insn (pc, info); | |
11255 | } | |
11256 | ||
f59a29b9 L |
11257 | void |
11258 | print_i386_disassembler_options (FILE *stream) | |
11259 | { | |
11260 | fprintf (stream, _("\n\ | |
11261 | The following i386/x86-64 specific disassembler options are supported for use\n\ | |
11262 | with the -M switch (multiple options should be separated by commas):\n")); | |
11263 | ||
11264 | fprintf (stream, _(" x86-64 Disassemble in 64bit mode\n")); | |
11265 | fprintf (stream, _(" i386 Disassemble in 32bit mode\n")); | |
11266 | fprintf (stream, _(" i8086 Disassemble in 16bit mode\n")); | |
11267 | fprintf (stream, _(" att Display instruction in AT&T syntax\n")); | |
11268 | fprintf (stream, _(" intel Display instruction in Intel syntax\n")); | |
9d141669 L |
11269 | fprintf (stream, _(" att-mnemonic\n" |
11270 | " Display instruction in AT&T mnemonic\n")); | |
11271 | fprintf (stream, _(" intel-mnemonic\n" | |
11272 | " Display instruction in Intel mnemonic\n")); | |
f59a29b9 L |
11273 | fprintf (stream, _(" addr64 Assume 64bit address size\n")); |
11274 | fprintf (stream, _(" addr32 Assume 32bit address size\n")); | |
11275 | fprintf (stream, _(" addr16 Assume 16bit address size\n")); | |
11276 | fprintf (stream, _(" data32 Assume 32bit data size\n")); | |
11277 | fprintf (stream, _(" data16 Assume 16bit data size\n")); | |
11278 | fprintf (stream, _(" suffix Always display instruction suffix in AT&T syntax\n")); | |
5db04b09 L |
11279 | fprintf (stream, _(" amd64 Display instruction in AMD64 ISA\n")); |
11280 | fprintf (stream, _(" intel64 Display instruction in Intel64 ISA\n")); | |
f59a29b9 L |
11281 | } |
11282 | ||
592d1631 | 11283 | /* Bad opcode. */ |
bf890a93 | 11284 | static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 }; |
592d1631 | 11285 | |
b844680a L |
11286 | /* Get a pointer to struct dis386 with a valid name. */ |
11287 | ||
11288 | static const struct dis386 * | |
8bb15339 | 11289 | get_valid_dis386 (const struct dis386 *dp, disassemble_info *info) |
b844680a | 11290 | { |
91d6fa6a | 11291 | int vindex, vex_table_index; |
b844680a L |
11292 | |
11293 | if (dp->name != NULL) | |
11294 | return dp; | |
11295 | ||
11296 | switch (dp->op[0].bytemode) | |
11297 | { | |
1ceb70f8 L |
11298 | case USE_REG_TABLE: |
11299 | dp = ®_table[dp->op[1].bytemode][modrm.reg]; | |
11300 | break; | |
11301 | ||
11302 | case USE_MOD_TABLE: | |
91d6fa6a NC |
11303 | vindex = modrm.mod == 0x3 ? 1 : 0; |
11304 | dp = &mod_table[dp->op[1].bytemode][vindex]; | |
1ceb70f8 L |
11305 | break; |
11306 | ||
11307 | case USE_RM_TABLE: | |
11308 | dp = &rm_table[dp->op[1].bytemode][modrm.rm]; | |
b844680a L |
11309 | break; |
11310 | ||
4e7d34a6 | 11311 | case USE_PREFIX_TABLE: |
c0f3af97 | 11312 | if (need_vex) |
b844680a | 11313 | { |
c0f3af97 L |
11314 | /* The prefix in VEX is implicit. */ |
11315 | switch (vex.prefix) | |
11316 | { | |
11317 | case 0: | |
91d6fa6a | 11318 | vindex = 0; |
c0f3af97 L |
11319 | break; |
11320 | case REPE_PREFIX_OPCODE: | |
91d6fa6a | 11321 | vindex = 1; |
c0f3af97 L |
11322 | break; |
11323 | case DATA_PREFIX_OPCODE: | |
91d6fa6a | 11324 | vindex = 2; |
c0f3af97 L |
11325 | break; |
11326 | case REPNE_PREFIX_OPCODE: | |
91d6fa6a | 11327 | vindex = 3; |
c0f3af97 L |
11328 | break; |
11329 | default: | |
11330 | abort (); | |
11331 | break; | |
11332 | } | |
b844680a | 11333 | } |
7bb15c6f | 11334 | else |
b844680a | 11335 | { |
285ca992 L |
11336 | int last_prefix = -1; |
11337 | int prefix = 0; | |
91d6fa6a | 11338 | vindex = 0; |
285ca992 L |
11339 | /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA. |
11340 | When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the | |
11341 | last one wins. */ | |
11342 | if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0) | |
b844680a | 11343 | { |
285ca992 | 11344 | if (last_repz_prefix > last_repnz_prefix) |
c0f3af97 | 11345 | { |
285ca992 L |
11346 | vindex = 1; |
11347 | prefix = PREFIX_REPZ; | |
11348 | last_prefix = last_repz_prefix; | |
c0f3af97 L |
11349 | } |
11350 | else | |
b844680a | 11351 | { |
285ca992 L |
11352 | vindex = 3; |
11353 | prefix = PREFIX_REPNZ; | |
11354 | last_prefix = last_repnz_prefix; | |
b844680a | 11355 | } |
285ca992 | 11356 | |
507bd325 L |
11357 | /* Check if prefix should be ignored. */ |
11358 | if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement | |
11359 | & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT) | |
11360 | & prefix) != 0) | |
285ca992 L |
11361 | vindex = 0; |
11362 | } | |
11363 | ||
11364 | if (vindex == 0 && (prefixes & PREFIX_DATA) != 0) | |
11365 | { | |
11366 | vindex = 2; | |
11367 | prefix = PREFIX_DATA; | |
11368 | last_prefix = last_data_prefix; | |
11369 | } | |
11370 | ||
11371 | if (vindex != 0) | |
11372 | { | |
11373 | used_prefixes |= prefix; | |
11374 | all_prefixes[last_prefix] = 0; | |
b844680a L |
11375 | } |
11376 | } | |
91d6fa6a | 11377 | dp = &prefix_table[dp->op[1].bytemode][vindex]; |
b844680a L |
11378 | break; |
11379 | ||
4e7d34a6 | 11380 | case USE_X86_64_TABLE: |
91d6fa6a NC |
11381 | vindex = address_mode == mode_64bit ? 1 : 0; |
11382 | dp = &x86_64_table[dp->op[1].bytemode][vindex]; | |
b844680a L |
11383 | break; |
11384 | ||
4e7d34a6 | 11385 | case USE_3BYTE_TABLE: |
8bb15339 | 11386 | FETCH_DATA (info, codep + 2); |
91d6fa6a NC |
11387 | vindex = *codep++; |
11388 | dp = &three_byte_table[dp->op[1].bytemode][vindex]; | |
285ca992 | 11389 | end_codep = codep; |
8bb15339 L |
11390 | modrm.mod = (*codep >> 6) & 3; |
11391 | modrm.reg = (*codep >> 3) & 7; | |
11392 | modrm.rm = *codep & 7; | |
11393 | break; | |
11394 | ||
c0f3af97 L |
11395 | case USE_VEX_LEN_TABLE: |
11396 | if (!need_vex) | |
11397 | abort (); | |
11398 | ||
11399 | switch (vex.length) | |
11400 | { | |
11401 | case 128: | |
91d6fa6a | 11402 | vindex = 0; |
c0f3af97 L |
11403 | break; |
11404 | case 256: | |
91d6fa6a | 11405 | vindex = 1; |
c0f3af97 L |
11406 | break; |
11407 | default: | |
11408 | abort (); | |
11409 | break; | |
11410 | } | |
11411 | ||
91d6fa6a | 11412 | dp = &vex_len_table[dp->op[1].bytemode][vindex]; |
c0f3af97 L |
11413 | break; |
11414 | ||
04e2a182 L |
11415 | case USE_EVEX_LEN_TABLE: |
11416 | if (!vex.evex) | |
11417 | abort (); | |
11418 | ||
11419 | switch (vex.length) | |
11420 | { | |
11421 | case 128: | |
11422 | vindex = 0; | |
11423 | break; | |
11424 | case 256: | |
11425 | vindex = 1; | |
11426 | break; | |
11427 | case 512: | |
11428 | vindex = 2; | |
11429 | break; | |
11430 | default: | |
11431 | abort (); | |
11432 | break; | |
11433 | } | |
11434 | ||
11435 | dp = &evex_len_table[dp->op[1].bytemode][vindex]; | |
11436 | break; | |
11437 | ||
f88c9eb0 SP |
11438 | case USE_XOP_8F_TABLE: |
11439 | FETCH_DATA (info, codep + 3); | |
f88c9eb0 SP |
11440 | rex = ~(*codep >> 5) & 0x7; |
11441 | ||
11442 | /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */ | |
11443 | switch ((*codep & 0x1f)) | |
11444 | { | |
11445 | default: | |
f07af43e L |
11446 | dp = &bad_opcode; |
11447 | return dp; | |
5dd85c99 SP |
11448 | case 0x8: |
11449 | vex_table_index = XOP_08; | |
11450 | break; | |
f88c9eb0 SP |
11451 | case 0x9: |
11452 | vex_table_index = XOP_09; | |
11453 | break; | |
11454 | case 0xa: | |
11455 | vex_table_index = XOP_0A; | |
11456 | break; | |
11457 | } | |
11458 | codep++; | |
11459 | vex.w = *codep & 0x80; | |
11460 | if (vex.w && address_mode == mode_64bit) | |
11461 | rex |= REX_W; | |
11462 | ||
11463 | vex.register_specifier = (~(*codep >> 3)) & 0xf; | |
abfcb414 | 11464 | if (address_mode != mode_64bit) |
f07af43e | 11465 | { |
abfcb414 AP |
11466 | /* In 16/32-bit mode REX_B is silently ignored. */ |
11467 | rex &= ~REX_B; | |
f07af43e | 11468 | } |
f88c9eb0 SP |
11469 | |
11470 | vex.length = (*codep & 0x4) ? 256 : 128; | |
11471 | switch ((*codep & 0x3)) | |
11472 | { | |
11473 | case 0: | |
f88c9eb0 SP |
11474 | break; |
11475 | case 1: | |
11476 | vex.prefix = DATA_PREFIX_OPCODE; | |
11477 | break; | |
11478 | case 2: | |
11479 | vex.prefix = REPE_PREFIX_OPCODE; | |
11480 | break; | |
11481 | case 3: | |
11482 | vex.prefix = REPNE_PREFIX_OPCODE; | |
11483 | break; | |
11484 | } | |
11485 | need_vex = 1; | |
11486 | need_vex_reg = 1; | |
11487 | codep++; | |
91d6fa6a NC |
11488 | vindex = *codep++; |
11489 | dp = &xop_table[vex_table_index][vindex]; | |
c48244a5 | 11490 | |
285ca992 | 11491 | end_codep = codep; |
c48244a5 SP |
11492 | FETCH_DATA (info, codep + 1); |
11493 | modrm.mod = (*codep >> 6) & 3; | |
11494 | modrm.reg = (*codep >> 3) & 7; | |
11495 | modrm.rm = *codep & 7; | |
f88c9eb0 SP |
11496 | break; |
11497 | ||
c0f3af97 | 11498 | case USE_VEX_C4_TABLE: |
43234a1e | 11499 | /* VEX prefix. */ |
c0f3af97 | 11500 | FETCH_DATA (info, codep + 3); |
c0f3af97 L |
11501 | rex = ~(*codep >> 5) & 0x7; |
11502 | switch ((*codep & 0x1f)) | |
11503 | { | |
11504 | default: | |
f07af43e L |
11505 | dp = &bad_opcode; |
11506 | return dp; | |
c0f3af97 | 11507 | case 0x1: |
f88c9eb0 | 11508 | vex_table_index = VEX_0F; |
c0f3af97 L |
11509 | break; |
11510 | case 0x2: | |
f88c9eb0 | 11511 | vex_table_index = VEX_0F38; |
c0f3af97 L |
11512 | break; |
11513 | case 0x3: | |
f88c9eb0 | 11514 | vex_table_index = VEX_0F3A; |
c0f3af97 L |
11515 | break; |
11516 | } | |
11517 | codep++; | |
11518 | vex.w = *codep & 0x80; | |
9889cbb1 | 11519 | if (address_mode == mode_64bit) |
f07af43e | 11520 | { |
9889cbb1 L |
11521 | if (vex.w) |
11522 | rex |= REX_W; | |
9889cbb1 L |
11523 | } |
11524 | else | |
11525 | { | |
11526 | /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit | |
11527 | is ignored, other REX bits are 0 and the highest bit in | |
5f847646 | 11528 | VEX.vvvv is also ignored (but we mustn't clear it here). */ |
9889cbb1 | 11529 | rex = 0; |
f07af43e | 11530 | } |
5f847646 | 11531 | vex.register_specifier = (~(*codep >> 3)) & 0xf; |
c0f3af97 L |
11532 | vex.length = (*codep & 0x4) ? 256 : 128; |
11533 | switch ((*codep & 0x3)) | |
11534 | { | |
11535 | case 0: | |
c0f3af97 L |
11536 | break; |
11537 | case 1: | |
11538 | vex.prefix = DATA_PREFIX_OPCODE; | |
11539 | break; | |
11540 | case 2: | |
11541 | vex.prefix = REPE_PREFIX_OPCODE; | |
11542 | break; | |
11543 | case 3: | |
11544 | vex.prefix = REPNE_PREFIX_OPCODE; | |
11545 | break; | |
11546 | } | |
11547 | need_vex = 1; | |
11548 | need_vex_reg = 1; | |
11549 | codep++; | |
91d6fa6a NC |
11550 | vindex = *codep++; |
11551 | dp = &vex_table[vex_table_index][vindex]; | |
285ca992 | 11552 | end_codep = codep; |
53c4d625 JB |
11553 | /* There is no MODRM byte for VEX0F 77. */ |
11554 | if (vex_table_index != VEX_0F || vindex != 0x77) | |
c0f3af97 L |
11555 | { |
11556 | FETCH_DATA (info, codep + 1); | |
11557 | modrm.mod = (*codep >> 6) & 3; | |
11558 | modrm.reg = (*codep >> 3) & 7; | |
11559 | modrm.rm = *codep & 7; | |
11560 | } | |
11561 | break; | |
11562 | ||
11563 | case USE_VEX_C5_TABLE: | |
43234a1e | 11564 | /* VEX prefix. */ |
c0f3af97 | 11565 | FETCH_DATA (info, codep + 2); |
c0f3af97 L |
11566 | rex = (*codep & 0x80) ? 0 : REX_R; |
11567 | ||
9889cbb1 L |
11568 | /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in |
11569 | VEX.vvvv is 1. */ | |
c0f3af97 | 11570 | vex.register_specifier = (~(*codep >> 3)) & 0xf; |
c0f3af97 L |
11571 | vex.length = (*codep & 0x4) ? 256 : 128; |
11572 | switch ((*codep & 0x3)) | |
11573 | { | |
11574 | case 0: | |
c0f3af97 L |
11575 | break; |
11576 | case 1: | |
11577 | vex.prefix = DATA_PREFIX_OPCODE; | |
11578 | break; | |
11579 | case 2: | |
11580 | vex.prefix = REPE_PREFIX_OPCODE; | |
11581 | break; | |
11582 | case 3: | |
11583 | vex.prefix = REPNE_PREFIX_OPCODE; | |
11584 | break; | |
11585 | } | |
11586 | need_vex = 1; | |
11587 | need_vex_reg = 1; | |
11588 | codep++; | |
91d6fa6a NC |
11589 | vindex = *codep++; |
11590 | dp = &vex_table[dp->op[1].bytemode][vindex]; | |
285ca992 | 11591 | end_codep = codep; |
53c4d625 JB |
11592 | /* There is no MODRM byte for VEX 77. */ |
11593 | if (vindex != 0x77) | |
c0f3af97 L |
11594 | { |
11595 | FETCH_DATA (info, codep + 1); | |
11596 | modrm.mod = (*codep >> 6) & 3; | |
11597 | modrm.reg = (*codep >> 3) & 7; | |
11598 | modrm.rm = *codep & 7; | |
11599 | } | |
11600 | break; | |
11601 | ||
9e30b8e0 L |
11602 | case USE_VEX_W_TABLE: |
11603 | if (!need_vex) | |
11604 | abort (); | |
11605 | ||
11606 | dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0]; | |
11607 | break; | |
11608 | ||
43234a1e L |
11609 | case USE_EVEX_TABLE: |
11610 | two_source_ops = 0; | |
11611 | /* EVEX prefix. */ | |
11612 | vex.evex = 1; | |
11613 | FETCH_DATA (info, codep + 4); | |
43234a1e L |
11614 | /* The first byte after 0x62. */ |
11615 | rex = ~(*codep >> 5) & 0x7; | |
11616 | vex.r = *codep & 0x10; | |
11617 | switch ((*codep & 0xf)) | |
11618 | { | |
11619 | default: | |
11620 | return &bad_opcode; | |
11621 | case 0x1: | |
11622 | vex_table_index = EVEX_0F; | |
11623 | break; | |
11624 | case 0x2: | |
11625 | vex_table_index = EVEX_0F38; | |
11626 | break; | |
11627 | case 0x3: | |
11628 | vex_table_index = EVEX_0F3A; | |
11629 | break; | |
11630 | } | |
11631 | ||
11632 | /* The second byte after 0x62. */ | |
11633 | codep++; | |
11634 | vex.w = *codep & 0x80; | |
11635 | if (vex.w && address_mode == mode_64bit) | |
11636 | rex |= REX_W; | |
11637 | ||
11638 | vex.register_specifier = (~(*codep >> 3)) & 0xf; | |
43234a1e L |
11639 | |
11640 | /* The U bit. */ | |
11641 | if (!(*codep & 0x4)) | |
11642 | return &bad_opcode; | |
11643 | ||
11644 | switch ((*codep & 0x3)) | |
11645 | { | |
11646 | case 0: | |
43234a1e L |
11647 | break; |
11648 | case 1: | |
11649 | vex.prefix = DATA_PREFIX_OPCODE; | |
11650 | break; | |
11651 | case 2: | |
11652 | vex.prefix = REPE_PREFIX_OPCODE; | |
11653 | break; | |
11654 | case 3: | |
11655 | vex.prefix = REPNE_PREFIX_OPCODE; | |
11656 | break; | |
11657 | } | |
11658 | ||
11659 | /* The third byte after 0x62. */ | |
11660 | codep++; | |
11661 | ||
11662 | /* Remember the static rounding bits. */ | |
11663 | vex.ll = (*codep >> 5) & 3; | |
11664 | vex.b = (*codep & 0x10) != 0; | |
11665 | ||
11666 | vex.v = *codep & 0x8; | |
11667 | vex.mask_register_specifier = *codep & 0x7; | |
11668 | vex.zeroing = *codep & 0x80; | |
11669 | ||
5f847646 JB |
11670 | if (address_mode != mode_64bit) |
11671 | { | |
11672 | /* In 16/32-bit mode silently ignore following bits. */ | |
11673 | rex &= ~REX_B; | |
11674 | vex.r = 1; | |
11675 | vex.v = 1; | |
11676 | } | |
11677 | ||
43234a1e L |
11678 | need_vex = 1; |
11679 | need_vex_reg = 1; | |
11680 | codep++; | |
11681 | vindex = *codep++; | |
11682 | dp = &evex_table[vex_table_index][vindex]; | |
285ca992 | 11683 | end_codep = codep; |
43234a1e L |
11684 | FETCH_DATA (info, codep + 1); |
11685 | modrm.mod = (*codep >> 6) & 3; | |
11686 | modrm.reg = (*codep >> 3) & 7; | |
11687 | modrm.rm = *codep & 7; | |
11688 | ||
11689 | /* Set vector length. */ | |
11690 | if (modrm.mod == 3 && vex.b) | |
11691 | vex.length = 512; | |
11692 | else | |
11693 | { | |
11694 | switch (vex.ll) | |
11695 | { | |
11696 | case 0x0: | |
11697 | vex.length = 128; | |
11698 | break; | |
11699 | case 0x1: | |
11700 | vex.length = 256; | |
11701 | break; | |
11702 | case 0x2: | |
11703 | vex.length = 512; | |
11704 | break; | |
11705 | default: | |
11706 | return &bad_opcode; | |
11707 | } | |
11708 | } | |
11709 | break; | |
11710 | ||
592d1631 L |
11711 | case 0: |
11712 | dp = &bad_opcode; | |
11713 | break; | |
11714 | ||
b844680a | 11715 | default: |
d34b5006 | 11716 | abort (); |
b844680a L |
11717 | } |
11718 | ||
11719 | if (dp->name != NULL) | |
11720 | return dp; | |
11721 | else | |
8bb15339 | 11722 | return get_valid_dis386 (dp, info); |
b844680a L |
11723 | } |
11724 | ||
dfc8cf43 | 11725 | static void |
55cf16e1 | 11726 | get_sib (disassemble_info *info, int sizeflag) |
dfc8cf43 L |
11727 | { |
11728 | /* If modrm.mod == 3, operand must be register. */ | |
11729 | if (need_modrm | |
55cf16e1 | 11730 | && ((sizeflag & AFLAG) || address_mode == mode_64bit) |
dfc8cf43 L |
11731 | && modrm.mod != 3 |
11732 | && modrm.rm == 4) | |
11733 | { | |
11734 | FETCH_DATA (info, codep + 2); | |
11735 | sib.index = (codep [1] >> 3) & 7; | |
11736 | sib.scale = (codep [1] >> 6) & 3; | |
11737 | sib.base = codep [1] & 7; | |
11738 | } | |
11739 | } | |
11740 | ||
e396998b | 11741 | static int |
26ca5450 | 11742 | print_insn (bfd_vma pc, disassemble_info *info) |
252b5132 | 11743 | { |
2da11e11 | 11744 | const struct dis386 *dp; |
252b5132 | 11745 | int i; |
ce518a5f | 11746 | char *op_txt[MAX_OPERANDS]; |
252b5132 | 11747 | int needcomma; |
df18fdba | 11748 | int sizeflag, orig_sizeflag; |
e396998b | 11749 | const char *p; |
252b5132 | 11750 | struct dis_private priv; |
f16cd0d5 | 11751 | int prefix_length; |
252b5132 | 11752 | |
d7921315 L |
11753 | priv.orig_sizeflag = AFLAG | DFLAG; |
11754 | if ((info->mach & bfd_mach_i386_i386) != 0) | |
cb712a9e | 11755 | address_mode = mode_32bit; |
2da11e11 | 11756 | else if (info->mach == bfd_mach_i386_i8086) |
d7921315 L |
11757 | { |
11758 | address_mode = mode_16bit; | |
11759 | priv.orig_sizeflag = 0; | |
11760 | } | |
2da11e11 | 11761 | else |
d7921315 L |
11762 | address_mode = mode_64bit; |
11763 | ||
11764 | if (intel_syntax == (char) -1) | |
11765 | intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0; | |
e396998b AM |
11766 | |
11767 | for (p = info->disassembler_options; p != NULL; ) | |
11768 | { | |
5db04b09 L |
11769 | if (CONST_STRNEQ (p, "amd64")) |
11770 | isa64 = amd64; | |
11771 | else if (CONST_STRNEQ (p, "intel64")) | |
11772 | isa64 = intel64; | |
11773 | else if (CONST_STRNEQ (p, "x86-64")) | |
e396998b | 11774 | { |
cb712a9e | 11775 | address_mode = mode_64bit; |
2a1bb84c | 11776 | priv.orig_sizeflag |= AFLAG | DFLAG; |
e396998b | 11777 | } |
0112cd26 | 11778 | else if (CONST_STRNEQ (p, "i386")) |
e396998b | 11779 | { |
cb712a9e | 11780 | address_mode = mode_32bit; |
2a1bb84c | 11781 | priv.orig_sizeflag |= AFLAG | DFLAG; |
e396998b | 11782 | } |
0112cd26 | 11783 | else if (CONST_STRNEQ (p, "i8086")) |
e396998b | 11784 | { |
cb712a9e | 11785 | address_mode = mode_16bit; |
2a1bb84c | 11786 | priv.orig_sizeflag &= ~(AFLAG | DFLAG); |
e396998b | 11787 | } |
0112cd26 | 11788 | else if (CONST_STRNEQ (p, "intel")) |
e396998b AM |
11789 | { |
11790 | intel_syntax = 1; | |
9d141669 L |
11791 | if (CONST_STRNEQ (p + 5, "-mnemonic")) |
11792 | intel_mnemonic = 1; | |
e396998b | 11793 | } |
0112cd26 | 11794 | else if (CONST_STRNEQ (p, "att")) |
e396998b AM |
11795 | { |
11796 | intel_syntax = 0; | |
9d141669 L |
11797 | if (CONST_STRNEQ (p + 3, "-mnemonic")) |
11798 | intel_mnemonic = 0; | |
e396998b | 11799 | } |
0112cd26 | 11800 | else if (CONST_STRNEQ (p, "addr")) |
e396998b | 11801 | { |
f59a29b9 L |
11802 | if (address_mode == mode_64bit) |
11803 | { | |
11804 | if (p[4] == '3' && p[5] == '2') | |
11805 | priv.orig_sizeflag &= ~AFLAG; | |
11806 | else if (p[4] == '6' && p[5] == '4') | |
11807 | priv.orig_sizeflag |= AFLAG; | |
11808 | } | |
11809 | else | |
11810 | { | |
11811 | if (p[4] == '1' && p[5] == '6') | |
11812 | priv.orig_sizeflag &= ~AFLAG; | |
11813 | else if (p[4] == '3' && p[5] == '2') | |
11814 | priv.orig_sizeflag |= AFLAG; | |
11815 | } | |
e396998b | 11816 | } |
0112cd26 | 11817 | else if (CONST_STRNEQ (p, "data")) |
e396998b AM |
11818 | { |
11819 | if (p[4] == '1' && p[5] == '6') | |
11820 | priv.orig_sizeflag &= ~DFLAG; | |
11821 | else if (p[4] == '3' && p[5] == '2') | |
11822 | priv.orig_sizeflag |= DFLAG; | |
11823 | } | |
0112cd26 | 11824 | else if (CONST_STRNEQ (p, "suffix")) |
e396998b AM |
11825 | priv.orig_sizeflag |= SUFFIX_ALWAYS; |
11826 | ||
11827 | p = strchr (p, ','); | |
11828 | if (p != NULL) | |
11829 | p++; | |
11830 | } | |
11831 | ||
c0f92bf9 L |
11832 | if (address_mode == mode_64bit && sizeof (bfd_vma) < 8) |
11833 | { | |
11834 | (*info->fprintf_func) (info->stream, | |
11835 | _("64-bit address is disabled")); | |
11836 | return -1; | |
11837 | } | |
11838 | ||
e396998b AM |
11839 | if (intel_syntax) |
11840 | { | |
11841 | names64 = intel_names64; | |
11842 | names32 = intel_names32; | |
11843 | names16 = intel_names16; | |
11844 | names8 = intel_names8; | |
11845 | names8rex = intel_names8rex; | |
11846 | names_seg = intel_names_seg; | |
b9733481 | 11847 | names_mm = intel_names_mm; |
7e8b059b | 11848 | names_bnd = intel_names_bnd; |
b9733481 L |
11849 | names_xmm = intel_names_xmm; |
11850 | names_ymm = intel_names_ymm; | |
43234a1e | 11851 | names_zmm = intel_names_zmm; |
db51cc60 L |
11852 | index64 = intel_index64; |
11853 | index32 = intel_index32; | |
43234a1e | 11854 | names_mask = intel_names_mask; |
e396998b AM |
11855 | index16 = intel_index16; |
11856 | open_char = '['; | |
11857 | close_char = ']'; | |
11858 | separator_char = '+'; | |
11859 | scale_char = '*'; | |
11860 | } | |
11861 | else | |
11862 | { | |
11863 | names64 = att_names64; | |
11864 | names32 = att_names32; | |
11865 | names16 = att_names16; | |
11866 | names8 = att_names8; | |
11867 | names8rex = att_names8rex; | |
11868 | names_seg = att_names_seg; | |
b9733481 | 11869 | names_mm = att_names_mm; |
7e8b059b | 11870 | names_bnd = att_names_bnd; |
b9733481 L |
11871 | names_xmm = att_names_xmm; |
11872 | names_ymm = att_names_ymm; | |
43234a1e | 11873 | names_zmm = att_names_zmm; |
db51cc60 L |
11874 | index64 = att_index64; |
11875 | index32 = att_index32; | |
43234a1e | 11876 | names_mask = att_names_mask; |
e396998b AM |
11877 | index16 = att_index16; |
11878 | open_char = '('; | |
11879 | close_char = ')'; | |
11880 | separator_char = ','; | |
11881 | scale_char = ','; | |
11882 | } | |
2da11e11 | 11883 | |
4fe53c98 | 11884 | /* The output looks better if we put 7 bytes on a line, since that |
8a9036a4 L |
11885 | puts most long word instructions on a single line. Use 8 bytes |
11886 | for Intel L1OM. */ | |
d7921315 | 11887 | if ((info->mach & bfd_mach_l1om) != 0) |
8a9036a4 L |
11888 | info->bytes_per_line = 8; |
11889 | else | |
11890 | info->bytes_per_line = 7; | |
252b5132 | 11891 | |
26ca5450 | 11892 | info->private_data = &priv; |
252b5132 RH |
11893 | priv.max_fetched = priv.the_buffer; |
11894 | priv.insn_start = pc; | |
252b5132 RH |
11895 | |
11896 | obuf[0] = 0; | |
ce518a5f L |
11897 | for (i = 0; i < MAX_OPERANDS; ++i) |
11898 | { | |
11899 | op_out[i][0] = 0; | |
11900 | op_index[i] = -1; | |
11901 | } | |
252b5132 RH |
11902 | |
11903 | the_info = info; | |
11904 | start_pc = pc; | |
e396998b AM |
11905 | start_codep = priv.the_buffer; |
11906 | codep = priv.the_buffer; | |
252b5132 | 11907 | |
8df14d78 | 11908 | if (OPCODES_SIGSETJMP (priv.bailout) != 0) |
5076851f | 11909 | { |
7d421014 ILT |
11910 | const char *name; |
11911 | ||
5076851f | 11912 | /* Getting here means we tried for data but didn't get it. That |
e396998b AM |
11913 | means we have an incomplete instruction of some sort. Just |
11914 | print the first byte as a prefix or a .byte pseudo-op. */ | |
11915 | if (codep > priv.the_buffer) | |
5076851f | 11916 | { |
e396998b | 11917 | name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag); |
7d421014 ILT |
11918 | if (name != NULL) |
11919 | (*info->fprintf_func) (info->stream, "%s", name); | |
11920 | else | |
5076851f | 11921 | { |
7d421014 ILT |
11922 | /* Just print the first byte as a .byte instruction. */ |
11923 | (*info->fprintf_func) (info->stream, ".byte 0x%x", | |
e396998b | 11924 | (unsigned int) priv.the_buffer[0]); |
5076851f | 11925 | } |
5076851f | 11926 | |
7d421014 | 11927 | return 1; |
5076851f ILT |
11928 | } |
11929 | ||
11930 | return -1; | |
11931 | } | |
11932 | ||
52b15da3 | 11933 | obufp = obuf; |
f16cd0d5 L |
11934 | sizeflag = priv.orig_sizeflag; |
11935 | ||
11936 | if (!ckprefix () || rex_used) | |
11937 | { | |
11938 | /* Too many prefixes or unused REX prefixes. */ | |
11939 | for (i = 0; | |
f6dd4781 | 11940 | i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i]; |
f16cd0d5 | 11941 | i++) |
de882298 | 11942 | (*info->fprintf_func) (info->stream, "%s%s", |
6c067bbb | 11943 | i == 0 ? "" : " ", |
f16cd0d5 | 11944 | prefix_name (all_prefixes[i], sizeflag)); |
de882298 | 11945 | return i; |
f16cd0d5 | 11946 | } |
252b5132 RH |
11947 | |
11948 | insn_codep = codep; | |
11949 | ||
11950 | FETCH_DATA (info, codep + 1); | |
11951 | two_source_ops = (*codep == 0x62) || (*codep == 0xc8); | |
11952 | ||
3e7d61b2 | 11953 | if (((prefixes & PREFIX_FWAIT) |
f16cd0d5 | 11954 | && ((*codep < 0xd8) || (*codep > 0xdf)))) |
252b5132 | 11955 | { |
86a80a50 | 11956 | /* Handle prefixes before fwait. */ |
d9949a36 | 11957 | for (i = 0; i < fwait_prefix && all_prefixes[i]; |
86a80a50 L |
11958 | i++) |
11959 | (*info->fprintf_func) (info->stream, "%s ", | |
11960 | prefix_name (all_prefixes[i], sizeflag)); | |
f16cd0d5 | 11961 | (*info->fprintf_func) (info->stream, "fwait"); |
86a80a50 | 11962 | return i + 1; |
252b5132 RH |
11963 | } |
11964 | ||
252b5132 RH |
11965 | if (*codep == 0x0f) |
11966 | { | |
eec0f4ca | 11967 | unsigned char threebyte; |
5f40e14d JS |
11968 | |
11969 | codep++; | |
11970 | FETCH_DATA (info, codep + 1); | |
11971 | threebyte = *codep; | |
eec0f4ca | 11972 | dp = &dis386_twobyte[threebyte]; |
252b5132 | 11973 | need_modrm = twobyte_has_modrm[*codep]; |
eec0f4ca | 11974 | codep++; |
252b5132 RH |
11975 | } |
11976 | else | |
11977 | { | |
6439fc28 | 11978 | dp = &dis386[*codep]; |
252b5132 | 11979 | need_modrm = onebyte_has_modrm[*codep]; |
eec0f4ca | 11980 | codep++; |
252b5132 | 11981 | } |
246c51aa | 11982 | |
df18fdba L |
11983 | /* Save sizeflag for printing the extra prefixes later before updating |
11984 | it for mnemonic and operand processing. The prefix names depend | |
11985 | only on the address mode. */ | |
11986 | orig_sizeflag = sizeflag; | |
c608c12e | 11987 | if (prefixes & PREFIX_ADDR) |
df18fdba | 11988 | sizeflag ^= AFLAG; |
b844680a | 11989 | if ((prefixes & PREFIX_DATA)) |
df18fdba | 11990 | sizeflag ^= DFLAG; |
3ffd33cf | 11991 | |
285ca992 | 11992 | end_codep = codep; |
8bb15339 | 11993 | if (need_modrm) |
252b5132 RH |
11994 | { |
11995 | FETCH_DATA (info, codep + 1); | |
7967e09e L |
11996 | modrm.mod = (*codep >> 6) & 3; |
11997 | modrm.reg = (*codep >> 3) & 7; | |
11998 | modrm.rm = *codep & 7; | |
252b5132 RH |
11999 | } |
12000 | ||
42d5f9c6 MS |
12001 | need_vex = 0; |
12002 | need_vex_reg = 0; | |
12003 | vex_w_done = 0; | |
caf0678c | 12004 | memset (&vex, 0, sizeof (vex)); |
55b126d4 | 12005 | |
ce518a5f | 12006 | if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE) |
252b5132 | 12007 | { |
55cf16e1 | 12008 | get_sib (info, sizeflag); |
252b5132 RH |
12009 | dofloat (sizeflag); |
12010 | } | |
12011 | else | |
12012 | { | |
8bb15339 | 12013 | dp = get_valid_dis386 (dp, info); |
b844680a | 12014 | if (dp != NULL && putop (dp->name, sizeflag) == 0) |
6c067bbb | 12015 | { |
55cf16e1 | 12016 | get_sib (info, sizeflag); |
ce518a5f L |
12017 | for (i = 0; i < MAX_OPERANDS; ++i) |
12018 | { | |
246c51aa | 12019 | obufp = op_out[i]; |
ce518a5f L |
12020 | op_ad = MAX_OPERANDS - 1 - i; |
12021 | if (dp->op[i].rtn) | |
12022 | (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag); | |
43234a1e L |
12023 | /* For EVEX instruction after the last operand masking |
12024 | should be printed. */ | |
12025 | if (i == 0 && vex.evex) | |
12026 | { | |
12027 | /* Don't print {%k0}. */ | |
12028 | if (vex.mask_register_specifier) | |
12029 | { | |
12030 | oappend ("{"); | |
12031 | oappend (names_mask[vex.mask_register_specifier]); | |
12032 | oappend ("}"); | |
12033 | } | |
12034 | if (vex.zeroing) | |
12035 | oappend ("{z}"); | |
12036 | } | |
ce518a5f | 12037 | } |
6439fc28 | 12038 | } |
252b5132 RH |
12039 | } |
12040 | ||
1d67fe3b TT |
12041 | /* Clear instruction information. */ |
12042 | if (the_info) | |
12043 | { | |
12044 | the_info->insn_info_valid = 0; | |
12045 | the_info->branch_delay_insns = 0; | |
12046 | the_info->data_size = 0; | |
12047 | the_info->insn_type = dis_noninsn; | |
12048 | the_info->target = 0; | |
12049 | the_info->target2 = 0; | |
12050 | } | |
12051 | ||
12052 | /* Reset jump operation indicator. */ | |
12053 | op_is_jump = FALSE; | |
12054 | ||
12055 | { | |
12056 | int jump_detection = 0; | |
12057 | ||
12058 | /* Extract flags. */ | |
12059 | for (i = 0; i < MAX_OPERANDS; ++i) | |
12060 | { | |
12061 | if ((dp->op[i].rtn == OP_J) | |
12062 | || (dp->op[i].rtn == OP_indirE)) | |
12063 | jump_detection |= 1; | |
12064 | else if ((dp->op[i].rtn == BND_Fixup) | |
12065 | || (!dp->op[i].rtn && !dp->op[i].bytemode)) | |
12066 | jump_detection |= 2; | |
12067 | else if ((dp->op[i].bytemode == cond_jump_mode) | |
12068 | || (dp->op[i].bytemode == loop_jcxz_mode)) | |
12069 | jump_detection |= 4; | |
12070 | } | |
12071 | ||
12072 | /* Determine if this is a jump or branch. */ | |
12073 | if ((jump_detection & 0x3) == 0x3) | |
12074 | { | |
12075 | op_is_jump = TRUE; | |
12076 | if (jump_detection & 0x4) | |
12077 | the_info->insn_type = dis_condbranch; | |
12078 | else | |
12079 | the_info->insn_type = | |
12080 | (dp->name && !strncmp(dp->name, "call", 4)) | |
12081 | ? dis_jsr : dis_branch; | |
12082 | } | |
12083 | } | |
12084 | ||
63c6fc6c L |
12085 | /* If VEX.vvvv and EVEX.vvvv are unused, they must be all 1s, which |
12086 | are all 0s in inverted form. */ | |
12087 | if (need_vex && vex.register_specifier != 0) | |
12088 | { | |
12089 | (*info->fprintf_func) (info->stream, "(bad)"); | |
12090 | return end_codep - priv.the_buffer; | |
12091 | } | |
12092 | ||
d869730d | 12093 | /* Check if the REX prefix is used. */ |
73239888 | 12094 | if ((rex ^ rex_used) == 0 && !need_vex && last_rex_prefix >= 0) |
f16cd0d5 L |
12095 | all_prefixes[last_rex_prefix] = 0; |
12096 | ||
5e6718e4 | 12097 | /* Check if the SEG prefix is used. */ |
f16cd0d5 L |
12098 | if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES |
12099 | | PREFIX_FS | PREFIX_GS)) != 0 | |
285ca992 | 12100 | && (used_prefixes & active_seg_prefix) != 0) |
f16cd0d5 L |
12101 | all_prefixes[last_seg_prefix] = 0; |
12102 | ||
5e6718e4 | 12103 | /* Check if the ADDR prefix is used. */ |
f16cd0d5 L |
12104 | if ((prefixes & PREFIX_ADDR) != 0 |
12105 | && (used_prefixes & PREFIX_ADDR) != 0) | |
12106 | all_prefixes[last_addr_prefix] = 0; | |
12107 | ||
df18fdba L |
12108 | /* Check if the DATA prefix is used. */ |
12109 | if ((prefixes & PREFIX_DATA) != 0 | |
73239888 JB |
12110 | && (used_prefixes & PREFIX_DATA) != 0 |
12111 | && !need_vex) | |
df18fdba | 12112 | all_prefixes[last_data_prefix] = 0; |
f16cd0d5 | 12113 | |
df18fdba | 12114 | /* Print the extra prefixes. */ |
f16cd0d5 | 12115 | prefix_length = 0; |
f310f33d | 12116 | for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++) |
f16cd0d5 L |
12117 | if (all_prefixes[i]) |
12118 | { | |
12119 | const char *name; | |
df18fdba | 12120 | name = prefix_name (all_prefixes[i], orig_sizeflag); |
f16cd0d5 L |
12121 | if (name == NULL) |
12122 | abort (); | |
12123 | prefix_length += strlen (name) + 1; | |
12124 | (*info->fprintf_func) (info->stream, "%s ", name); | |
12125 | } | |
b844680a | 12126 | |
285ca992 L |
12127 | /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is |
12128 | unused, opcode is invalid. Since the PREFIX_DATA prefix may be | |
12129 | used by putop and MMX/SSE operand and may be overriden by the | |
12130 | PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix | |
12131 | separately. */ | |
3888916d | 12132 | if (dp->prefix_requirement == PREFIX_OPCODE |
bf926894 JB |
12133 | && (((need_vex |
12134 | ? vex.prefix == REPE_PREFIX_OPCODE | |
12135 | || vex.prefix == REPNE_PREFIX_OPCODE | |
12136 | : (prefixes | |
12137 | & (PREFIX_REPZ | PREFIX_REPNZ)) != 0) | |
285ca992 L |
12138 | && (used_prefixes |
12139 | & (PREFIX_REPZ | PREFIX_REPNZ)) == 0) | |
bf926894 JB |
12140 | || (((need_vex |
12141 | ? vex.prefix == DATA_PREFIX_OPCODE | |
12142 | : ((prefixes | |
12143 | & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA)) | |
12144 | == PREFIX_DATA)) | |
97e6786a JB |
12145 | && (used_prefixes & PREFIX_DATA) == 0)) |
12146 | || (vex.evex && !vex.w != !(used_prefixes & PREFIX_DATA)))) | |
285ca992 L |
12147 | { |
12148 | (*info->fprintf_func) (info->stream, "(bad)"); | |
12149 | return end_codep - priv.the_buffer; | |
12150 | } | |
12151 | ||
f16cd0d5 L |
12152 | /* Check maximum code length. */ |
12153 | if ((codep - start_codep) > MAX_CODE_LENGTH) | |
12154 | { | |
12155 | (*info->fprintf_func) (info->stream, "(bad)"); | |
12156 | return MAX_CODE_LENGTH; | |
12157 | } | |
b844680a | 12158 | |
ea397f5b | 12159 | obufp = mnemonicendp; |
f16cd0d5 | 12160 | for (i = strlen (obuf) + prefix_length; i < 6; i++) |
252b5132 RH |
12161 | oappend (" "); |
12162 | oappend (" "); | |
12163 | (*info->fprintf_func) (info->stream, "%s", obuf); | |
12164 | ||
12165 | /* The enter and bound instructions are printed with operands in the same | |
12166 | order as the intel book; everything else is printed in reverse order. */ | |
2da11e11 | 12167 | if (intel_syntax || two_source_ops) |
252b5132 | 12168 | { |
185b1163 L |
12169 | bfd_vma riprel; |
12170 | ||
ce518a5f | 12171 | for (i = 0; i < MAX_OPERANDS; ++i) |
6c067bbb | 12172 | op_txt[i] = op_out[i]; |
246c51aa | 12173 | |
3a8547d2 JB |
12174 | if (intel_syntax && dp && dp->op[2].rtn == OP_Rounding |
12175 | && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL) | |
12176 | { | |
12177 | op_txt[2] = op_out[3]; | |
12178 | op_txt[3] = op_out[2]; | |
12179 | } | |
12180 | ||
ce518a5f L |
12181 | for (i = 0; i < (MAX_OPERANDS >> 1); ++i) |
12182 | { | |
6c067bbb RM |
12183 | op_ad = op_index[i]; |
12184 | op_index[i] = op_index[MAX_OPERANDS - 1 - i]; | |
12185 | op_index[MAX_OPERANDS - 1 - i] = op_ad; | |
185b1163 L |
12186 | riprel = op_riprel[i]; |
12187 | op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i]; | |
12188 | op_riprel[MAX_OPERANDS - 1 - i] = riprel; | |
ce518a5f | 12189 | } |
252b5132 RH |
12190 | } |
12191 | else | |
12192 | { | |
ce518a5f | 12193 | for (i = 0; i < MAX_OPERANDS; ++i) |
6c067bbb | 12194 | op_txt[MAX_OPERANDS - 1 - i] = op_out[i]; |
050dfa73 MM |
12195 | } |
12196 | ||
ce518a5f L |
12197 | needcomma = 0; |
12198 | for (i = 0; i < MAX_OPERANDS; ++i) | |
12199 | if (*op_txt[i]) | |
12200 | { | |
12201 | if (needcomma) | |
12202 | (*info->fprintf_func) (info->stream, ","); | |
12203 | if (op_index[i] != -1 && !op_riprel[i]) | |
1d67fe3b TT |
12204 | { |
12205 | bfd_vma target = (bfd_vma) op_address[op_index[i]]; | |
12206 | ||
12207 | if (the_info && op_is_jump) | |
12208 | { | |
12209 | the_info->insn_info_valid = 1; | |
12210 | the_info->branch_delay_insns = 0; | |
12211 | the_info->data_size = 0; | |
12212 | the_info->target = target; | |
12213 | the_info->target2 = 0; | |
12214 | } | |
12215 | (*info->print_address_func) (target, info); | |
12216 | } | |
ce518a5f L |
12217 | else |
12218 | (*info->fprintf_func) (info->stream, "%s", op_txt[i]); | |
12219 | needcomma = 1; | |
12220 | } | |
050dfa73 | 12221 | |
ce518a5f | 12222 | for (i = 0; i < MAX_OPERANDS; i++) |
52b15da3 JH |
12223 | if (op_index[i] != -1 && op_riprel[i]) |
12224 | { | |
12225 | (*info->fprintf_func) (info->stream, " # "); | |
4fd7268a | 12226 | (*info->print_address_func) ((bfd_vma) (start_pc + (codep - start_codep) |
52b15da3 | 12227 | + op_address[op_index[i]]), info); |
185b1163 | 12228 | break; |
52b15da3 | 12229 | } |
e396998b | 12230 | return codep - priv.the_buffer; |
252b5132 RH |
12231 | } |
12232 | ||
6439fc28 | 12233 | static const char *float_mem[] = { |
252b5132 | 12234 | /* d8 */ |
7c52e0e8 L |
12235 | "fadd{s|}", |
12236 | "fmul{s|}", | |
12237 | "fcom{s|}", | |
12238 | "fcomp{s|}", | |
12239 | "fsub{s|}", | |
12240 | "fsubr{s|}", | |
12241 | "fdiv{s|}", | |
12242 | "fdivr{s|}", | |
db6eb5be | 12243 | /* d9 */ |
7c52e0e8 | 12244 | "fld{s|}", |
252b5132 | 12245 | "(bad)", |
7c52e0e8 L |
12246 | "fst{s|}", |
12247 | "fstp{s|}", | |
d1c36125 | 12248 | "fldenv{C|C}", |
252b5132 | 12249 | "fldcw", |
d1c36125 | 12250 | "fNstenv{C|C}", |
252b5132 RH |
12251 | "fNstcw", |
12252 | /* da */ | |
7c52e0e8 L |
12253 | "fiadd{l|}", |
12254 | "fimul{l|}", | |
12255 | "ficom{l|}", | |
12256 | "ficomp{l|}", | |
12257 | "fisub{l|}", | |
12258 | "fisubr{l|}", | |
12259 | "fidiv{l|}", | |
12260 | "fidivr{l|}", | |
252b5132 | 12261 | /* db */ |
7c52e0e8 L |
12262 | "fild{l|}", |
12263 | "fisttp{l|}", | |
12264 | "fist{l|}", | |
12265 | "fistp{l|}", | |
252b5132 | 12266 | "(bad)", |
464dc4af | 12267 | "fld{t|}", |
252b5132 | 12268 | "(bad)", |
464dc4af | 12269 | "fstp{t|}", |
252b5132 | 12270 | /* dc */ |
7c52e0e8 L |
12271 | "fadd{l|}", |
12272 | "fmul{l|}", | |
12273 | "fcom{l|}", | |
12274 | "fcomp{l|}", | |
12275 | "fsub{l|}", | |
12276 | "fsubr{l|}", | |
12277 | "fdiv{l|}", | |
12278 | "fdivr{l|}", | |
252b5132 | 12279 | /* dd */ |
7c52e0e8 L |
12280 | "fld{l|}", |
12281 | "fisttp{ll|}", | |
12282 | "fst{l||}", | |
12283 | "fstp{l|}", | |
d1c36125 | 12284 | "frstor{C|C}", |
252b5132 | 12285 | "(bad)", |
d1c36125 | 12286 | "fNsave{C|C}", |
252b5132 RH |
12287 | "fNstsw", |
12288 | /* de */ | |
ac465521 JB |
12289 | "fiadd{s|}", |
12290 | "fimul{s|}", | |
12291 | "ficom{s|}", | |
12292 | "ficomp{s|}", | |
12293 | "fisub{s|}", | |
12294 | "fisubr{s|}", | |
12295 | "fidiv{s|}", | |
12296 | "fidivr{s|}", | |
252b5132 | 12297 | /* df */ |
ac465521 JB |
12298 | "fild{s|}", |
12299 | "fisttp{s|}", | |
12300 | "fist{s|}", | |
12301 | "fistp{s|}", | |
252b5132 | 12302 | "fbld", |
7c52e0e8 | 12303 | "fild{ll|}", |
252b5132 | 12304 | "fbstp", |
7c52e0e8 | 12305 | "fistp{ll|}", |
1d9f512f AM |
12306 | }; |
12307 | ||
12308 | static const unsigned char float_mem_mode[] = { | |
12309 | /* d8 */ | |
12310 | d_mode, | |
12311 | d_mode, | |
12312 | d_mode, | |
12313 | d_mode, | |
12314 | d_mode, | |
12315 | d_mode, | |
12316 | d_mode, | |
12317 | d_mode, | |
12318 | /* d9 */ | |
12319 | d_mode, | |
12320 | 0, | |
12321 | d_mode, | |
12322 | d_mode, | |
12323 | 0, | |
12324 | w_mode, | |
12325 | 0, | |
12326 | w_mode, | |
12327 | /* da */ | |
12328 | d_mode, | |
12329 | d_mode, | |
12330 | d_mode, | |
12331 | d_mode, | |
12332 | d_mode, | |
12333 | d_mode, | |
12334 | d_mode, | |
12335 | d_mode, | |
12336 | /* db */ | |
12337 | d_mode, | |
12338 | d_mode, | |
12339 | d_mode, | |
12340 | d_mode, | |
12341 | 0, | |
9306ca4a | 12342 | t_mode, |
1d9f512f | 12343 | 0, |
9306ca4a | 12344 | t_mode, |
1d9f512f AM |
12345 | /* dc */ |
12346 | q_mode, | |
12347 | q_mode, | |
12348 | q_mode, | |
12349 | q_mode, | |
12350 | q_mode, | |
12351 | q_mode, | |
12352 | q_mode, | |
12353 | q_mode, | |
12354 | /* dd */ | |
12355 | q_mode, | |
12356 | q_mode, | |
12357 | q_mode, | |
12358 | q_mode, | |
12359 | 0, | |
12360 | 0, | |
12361 | 0, | |
12362 | w_mode, | |
12363 | /* de */ | |
12364 | w_mode, | |
12365 | w_mode, | |
12366 | w_mode, | |
12367 | w_mode, | |
12368 | w_mode, | |
12369 | w_mode, | |
12370 | w_mode, | |
12371 | w_mode, | |
12372 | /* df */ | |
12373 | w_mode, | |
12374 | w_mode, | |
12375 | w_mode, | |
12376 | w_mode, | |
9306ca4a | 12377 | t_mode, |
1d9f512f | 12378 | q_mode, |
9306ca4a | 12379 | t_mode, |
1d9f512f | 12380 | q_mode |
252b5132 RH |
12381 | }; |
12382 | ||
ce518a5f L |
12383 | #define ST { OP_ST, 0 } |
12384 | #define STi { OP_STi, 0 } | |
252b5132 | 12385 | |
48c97fa1 L |
12386 | #define FGRPd9_2 NULL, { { NULL, 1 } }, 0 |
12387 | #define FGRPd9_4 NULL, { { NULL, 2 } }, 0 | |
12388 | #define FGRPd9_5 NULL, { { NULL, 3 } }, 0 | |
12389 | #define FGRPd9_6 NULL, { { NULL, 4 } }, 0 | |
12390 | #define FGRPd9_7 NULL, { { NULL, 5 } }, 0 | |
12391 | #define FGRPda_5 NULL, { { NULL, 6 } }, 0 | |
12392 | #define FGRPdb_4 NULL, { { NULL, 7 } }, 0 | |
12393 | #define FGRPde_3 NULL, { { NULL, 8 } }, 0 | |
12394 | #define FGRPdf_4 NULL, { { NULL, 9 } }, 0 | |
252b5132 | 12395 | |
2da11e11 | 12396 | static const struct dis386 float_reg[][8] = { |
252b5132 RH |
12397 | /* d8 */ |
12398 | { | |
bf890a93 IT |
12399 | { "fadd", { ST, STi }, 0 }, |
12400 | { "fmul", { ST, STi }, 0 }, | |
12401 | { "fcom", { STi }, 0 }, | |
12402 | { "fcomp", { STi }, 0 }, | |
12403 | { "fsub", { ST, STi }, 0 }, | |
12404 | { "fsubr", { ST, STi }, 0 }, | |
12405 | { "fdiv", { ST, STi }, 0 }, | |
12406 | { "fdivr", { ST, STi }, 0 }, | |
252b5132 RH |
12407 | }, |
12408 | /* d9 */ | |
12409 | { | |
bf890a93 IT |
12410 | { "fld", { STi }, 0 }, |
12411 | { "fxch", { STi }, 0 }, | |
252b5132 | 12412 | { FGRPd9_2 }, |
592d1631 | 12413 | { Bad_Opcode }, |
252b5132 RH |
12414 | { FGRPd9_4 }, |
12415 | { FGRPd9_5 }, | |
12416 | { FGRPd9_6 }, | |
12417 | { FGRPd9_7 }, | |
12418 | }, | |
12419 | /* da */ | |
12420 | { | |
bf890a93 IT |
12421 | { "fcmovb", { ST, STi }, 0 }, |
12422 | { "fcmove", { ST, STi }, 0 }, | |
12423 | { "fcmovbe",{ ST, STi }, 0 }, | |
12424 | { "fcmovu", { ST, STi }, 0 }, | |
592d1631 | 12425 | { Bad_Opcode }, |
252b5132 | 12426 | { FGRPda_5 }, |
592d1631 L |
12427 | { Bad_Opcode }, |
12428 | { Bad_Opcode }, | |
252b5132 RH |
12429 | }, |
12430 | /* db */ | |
12431 | { | |
bf890a93 IT |
12432 | { "fcmovnb",{ ST, STi }, 0 }, |
12433 | { "fcmovne",{ ST, STi }, 0 }, | |
12434 | { "fcmovnbe",{ ST, STi }, 0 }, | |
12435 | { "fcmovnu",{ ST, STi }, 0 }, | |
252b5132 | 12436 | { FGRPdb_4 }, |
bf890a93 IT |
12437 | { "fucomi", { ST, STi }, 0 }, |
12438 | { "fcomi", { ST, STi }, 0 }, | |
592d1631 | 12439 | { Bad_Opcode }, |
252b5132 RH |
12440 | }, |
12441 | /* dc */ | |
12442 | { | |
bf890a93 IT |
12443 | { "fadd", { STi, ST }, 0 }, |
12444 | { "fmul", { STi, ST }, 0 }, | |
592d1631 L |
12445 | { Bad_Opcode }, |
12446 | { Bad_Opcode }, | |
d53e6b98 JB |
12447 | { "fsub{!M|r}", { STi, ST }, 0 }, |
12448 | { "fsub{M|}", { STi, ST }, 0 }, | |
12449 | { "fdiv{!M|r}", { STi, ST }, 0 }, | |
12450 | { "fdiv{M|}", { STi, ST }, 0 }, | |
252b5132 RH |
12451 | }, |
12452 | /* dd */ | |
12453 | { | |
bf890a93 | 12454 | { "ffree", { STi }, 0 }, |
592d1631 | 12455 | { Bad_Opcode }, |
bf890a93 IT |
12456 | { "fst", { STi }, 0 }, |
12457 | { "fstp", { STi }, 0 }, | |
12458 | { "fucom", { STi }, 0 }, | |
12459 | { "fucomp", { STi }, 0 }, | |
592d1631 L |
12460 | { Bad_Opcode }, |
12461 | { Bad_Opcode }, | |
252b5132 RH |
12462 | }, |
12463 | /* de */ | |
12464 | { | |
bf890a93 IT |
12465 | { "faddp", { STi, ST }, 0 }, |
12466 | { "fmulp", { STi, ST }, 0 }, | |
592d1631 | 12467 | { Bad_Opcode }, |
252b5132 | 12468 | { FGRPde_3 }, |
d53e6b98 JB |
12469 | { "fsub{!M|r}p", { STi, ST }, 0 }, |
12470 | { "fsub{M|}p", { STi, ST }, 0 }, | |
12471 | { "fdiv{!M|r}p", { STi, ST }, 0 }, | |
12472 | { "fdiv{M|}p", { STi, ST }, 0 }, | |
252b5132 RH |
12473 | }, |
12474 | /* df */ | |
12475 | { | |
bf890a93 | 12476 | { "ffreep", { STi }, 0 }, |
592d1631 L |
12477 | { Bad_Opcode }, |
12478 | { Bad_Opcode }, | |
12479 | { Bad_Opcode }, | |
252b5132 | 12480 | { FGRPdf_4 }, |
bf890a93 IT |
12481 | { "fucomip", { ST, STi }, 0 }, |
12482 | { "fcomip", { ST, STi }, 0 }, | |
592d1631 | 12483 | { Bad_Opcode }, |
252b5132 RH |
12484 | }, |
12485 | }; | |
12486 | ||
252b5132 | 12487 | static char *fgrps[][8] = { |
48c97fa1 L |
12488 | /* Bad opcode 0 */ |
12489 | { | |
12490 | "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
12491 | }, | |
12492 | ||
12493 | /* d9_2 1 */ | |
252b5132 RH |
12494 | { |
12495 | "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
12496 | }, | |
12497 | ||
48c97fa1 | 12498 | /* d9_4 2 */ |
252b5132 RH |
12499 | { |
12500 | "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)", | |
12501 | }, | |
12502 | ||
48c97fa1 | 12503 | /* d9_5 3 */ |
252b5132 RH |
12504 | { |
12505 | "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)", | |
12506 | }, | |
12507 | ||
48c97fa1 | 12508 | /* d9_6 4 */ |
252b5132 RH |
12509 | { |
12510 | "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp", | |
12511 | }, | |
12512 | ||
48c97fa1 | 12513 | /* d9_7 5 */ |
252b5132 RH |
12514 | { |
12515 | "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos", | |
12516 | }, | |
12517 | ||
48c97fa1 | 12518 | /* da_5 6 */ |
252b5132 RH |
12519 | { |
12520 | "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
12521 | }, | |
12522 | ||
48c97fa1 | 12523 | /* db_4 7 */ |
252b5132 | 12524 | { |
309d3373 JB |
12525 | "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit", |
12526 | "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)", | |
252b5132 RH |
12527 | }, |
12528 | ||
48c97fa1 | 12529 | /* de_3 8 */ |
252b5132 RH |
12530 | { |
12531 | "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
12532 | }, | |
12533 | ||
48c97fa1 | 12534 | /* df_4 9 */ |
252b5132 RH |
12535 | { |
12536 | "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
12537 | }, | |
12538 | }; | |
12539 | ||
b6169b20 L |
12540 | static void |
12541 | swap_operand (void) | |
12542 | { | |
12543 | mnemonicendp[0] = '.'; | |
12544 | mnemonicendp[1] = 's'; | |
12545 | mnemonicendp += 2; | |
12546 | } | |
12547 | ||
b844680a L |
12548 | static void |
12549 | OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED, | |
12550 | int sizeflag ATTRIBUTE_UNUSED) | |
12551 | { | |
12552 | /* Skip mod/rm byte. */ | |
12553 | MODRM_CHECK; | |
12554 | codep++; | |
12555 | } | |
12556 | ||
252b5132 | 12557 | static void |
26ca5450 | 12558 | dofloat (int sizeflag) |
252b5132 | 12559 | { |
2da11e11 | 12560 | const struct dis386 *dp; |
252b5132 RH |
12561 | unsigned char floatop; |
12562 | ||
12563 | floatop = codep[-1]; | |
12564 | ||
7967e09e | 12565 | if (modrm.mod != 3) |
252b5132 | 12566 | { |
7967e09e | 12567 | int fp_indx = (floatop - 0xd8) * 8 + modrm.reg; |
1d9f512f AM |
12568 | |
12569 | putop (float_mem[fp_indx], sizeflag); | |
ce518a5f | 12570 | obufp = op_out[0]; |
6e50d963 | 12571 | op_ad = 2; |
1d9f512f | 12572 | OP_E (float_mem_mode[fp_indx], sizeflag); |
252b5132 RH |
12573 | return; |
12574 | } | |
6608db57 | 12575 | /* Skip mod/rm byte. */ |
4bba6815 | 12576 | MODRM_CHECK; |
252b5132 RH |
12577 | codep++; |
12578 | ||
7967e09e | 12579 | dp = &float_reg[floatop - 0xd8][modrm.reg]; |
252b5132 RH |
12580 | if (dp->name == NULL) |
12581 | { | |
7967e09e | 12582 | putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag); |
252b5132 | 12583 | |
6608db57 | 12584 | /* Instruction fnstsw is only one with strange arg. */ |
252b5132 | 12585 | if (floatop == 0xdf && codep[-1] == 0xe0) |
ce518a5f | 12586 | strcpy (op_out[0], names16[0]); |
252b5132 RH |
12587 | } |
12588 | else | |
12589 | { | |
12590 | putop (dp->name, sizeflag); | |
12591 | ||
ce518a5f | 12592 | obufp = op_out[0]; |
6e50d963 | 12593 | op_ad = 2; |
ce518a5f L |
12594 | if (dp->op[0].rtn) |
12595 | (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag); | |
6e50d963 | 12596 | |
ce518a5f | 12597 | obufp = op_out[1]; |
6e50d963 | 12598 | op_ad = 1; |
ce518a5f L |
12599 | if (dp->op[1].rtn) |
12600 | (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag); | |
252b5132 RH |
12601 | } |
12602 | } | |
12603 | ||
9ce09ba2 RM |
12604 | /* Like oappend (below), but S is a string starting with '%'. |
12605 | In Intel syntax, the '%' is elided. */ | |
12606 | static void | |
12607 | oappend_maybe_intel (const char *s) | |
12608 | { | |
12609 | oappend (s + intel_syntax); | |
12610 | } | |
12611 | ||
252b5132 | 12612 | static void |
26ca5450 | 12613 | OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 12614 | { |
9ce09ba2 | 12615 | oappend_maybe_intel ("%st"); |
252b5132 RH |
12616 | } |
12617 | ||
252b5132 | 12618 | static void |
26ca5450 | 12619 | OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 12620 | { |
7967e09e | 12621 | sprintf (scratchbuf, "%%st(%d)", modrm.rm); |
9ce09ba2 | 12622 | oappend_maybe_intel (scratchbuf); |
252b5132 RH |
12623 | } |
12624 | ||
6608db57 | 12625 | /* Capital letters in template are macros. */ |
6439fc28 | 12626 | static int |
d3ce72d0 | 12627 | putop (const char *in_template, int sizeflag) |
252b5132 | 12628 | { |
2da11e11 | 12629 | const char *p; |
9306ca4a | 12630 | int alt = 0; |
9d141669 | 12631 | int cond = 1; |
98b528ac L |
12632 | unsigned int l = 0, len = 1; |
12633 | char last[4]; | |
12634 | ||
12635 | #define SAVE_LAST(c) \ | |
12636 | if (l < len && l < sizeof (last)) \ | |
12637 | last[l++] = c; \ | |
12638 | else \ | |
12639 | abort (); | |
252b5132 | 12640 | |
d3ce72d0 | 12641 | for (p = in_template; *p; p++) |
252b5132 RH |
12642 | { |
12643 | switch (*p) | |
12644 | { | |
12645 | default: | |
12646 | *obufp++ = *p; | |
12647 | break; | |
98b528ac L |
12648 | case '%': |
12649 | len++; | |
12650 | break; | |
9d141669 L |
12651 | case '!': |
12652 | cond = 0; | |
12653 | break; | |
6439fc28 | 12654 | case '{': |
6439fc28 | 12655 | if (intel_syntax) |
6439fc28 AM |
12656 | { |
12657 | while (*++p != '|') | |
7c52e0e8 L |
12658 | if (*p == '}' || *p == '\0') |
12659 | abort (); | |
d1c36125 | 12660 | alt = 1; |
6439fc28 | 12661 | } |
d1c36125 | 12662 | break; |
6439fc28 AM |
12663 | case '|': |
12664 | while (*++p != '}') | |
12665 | { | |
12666 | if (*p == '\0') | |
12667 | abort (); | |
12668 | } | |
12669 | break; | |
12670 | case '}': | |
d1c36125 | 12671 | alt = 0; |
6439fc28 | 12672 | break; |
252b5132 | 12673 | case 'A': |
db6eb5be AM |
12674 | if (intel_syntax) |
12675 | break; | |
7967e09e | 12676 | if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS)) |
252b5132 RH |
12677 | *obufp++ = 'b'; |
12678 | break; | |
12679 | case 'B': | |
4b06377f L |
12680 | if (l == 0 && len == 1) |
12681 | { | |
dc1e8a47 | 12682 | case_B: |
4b06377f L |
12683 | if (intel_syntax) |
12684 | break; | |
12685 | if (sizeflag & SUFFIX_ALWAYS) | |
12686 | *obufp++ = 'b'; | |
12687 | } | |
12688 | else | |
12689 | { | |
12690 | if (l != 1 | |
12691 | || len != 2 | |
12692 | || last[0] != 'L') | |
12693 | { | |
12694 | SAVE_LAST (*p); | |
12695 | break; | |
12696 | } | |
12697 | ||
12698 | if (address_mode == mode_64bit | |
12699 | && !(prefixes & PREFIX_ADDR)) | |
12700 | { | |
12701 | *obufp++ = 'a'; | |
12702 | *obufp++ = 'b'; | |
12703 | *obufp++ = 's'; | |
12704 | } | |
12705 | ||
12706 | goto case_B; | |
12707 | } | |
252b5132 | 12708 | break; |
9306ca4a JB |
12709 | case 'C': |
12710 | if (intel_syntax && !alt) | |
12711 | break; | |
12712 | if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS)) | |
12713 | { | |
12714 | if (sizeflag & DFLAG) | |
12715 | *obufp++ = intel_syntax ? 'd' : 'l'; | |
12716 | else | |
12717 | *obufp++ = intel_syntax ? 'w' : 's'; | |
12718 | used_prefixes |= (prefixes & PREFIX_DATA); | |
12719 | } | |
12720 | break; | |
ed7841b3 JB |
12721 | case 'D': |
12722 | if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS)) | |
12723 | break; | |
161a04f6 | 12724 | USED_REX (REX_W); |
7967e09e | 12725 | if (modrm.mod == 3) |
ed7841b3 | 12726 | { |
161a04f6 | 12727 | if (rex & REX_W) |
ed7841b3 | 12728 | *obufp++ = 'q'; |
ed7841b3 | 12729 | else |
f16cd0d5 L |
12730 | { |
12731 | if (sizeflag & DFLAG) | |
12732 | *obufp++ = intel_syntax ? 'd' : 'l'; | |
12733 | else | |
12734 | *obufp++ = 'w'; | |
12735 | used_prefixes |= (prefixes & PREFIX_DATA); | |
12736 | } | |
ed7841b3 JB |
12737 | } |
12738 | else | |
12739 | *obufp++ = 'w'; | |
12740 | break; | |
252b5132 | 12741 | case 'E': /* For jcxz/jecxz */ |
cb712a9e | 12742 | if (address_mode == mode_64bit) |
c1a64871 JH |
12743 | { |
12744 | if (sizeflag & AFLAG) | |
12745 | *obufp++ = 'r'; | |
12746 | else | |
12747 | *obufp++ = 'e'; | |
12748 | } | |
12749 | else | |
12750 | if (sizeflag & AFLAG) | |
12751 | *obufp++ = 'e'; | |
3ffd33cf AM |
12752 | used_prefixes |= (prefixes & PREFIX_ADDR); |
12753 | break; | |
12754 | case 'F': | |
db6eb5be AM |
12755 | if (intel_syntax) |
12756 | break; | |
e396998b | 12757 | if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS)) |
3ffd33cf AM |
12758 | { |
12759 | if (sizeflag & AFLAG) | |
cb712a9e | 12760 | *obufp++ = address_mode == mode_64bit ? 'q' : 'l'; |
3ffd33cf | 12761 | else |
cb712a9e | 12762 | *obufp++ = address_mode == mode_64bit ? 'l' : 'w'; |
3ffd33cf AM |
12763 | used_prefixes |= (prefixes & PREFIX_ADDR); |
12764 | } | |
252b5132 | 12765 | break; |
52fd6d94 JB |
12766 | case 'G': |
12767 | if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS))) | |
12768 | break; | |
161a04f6 | 12769 | if ((rex & REX_W) || (sizeflag & DFLAG)) |
52fd6d94 JB |
12770 | *obufp++ = 'l'; |
12771 | else | |
12772 | *obufp++ = 'w'; | |
161a04f6 | 12773 | if (!(rex & REX_W)) |
52fd6d94 JB |
12774 | used_prefixes |= (prefixes & PREFIX_DATA); |
12775 | break; | |
5dd0794d | 12776 | case 'H': |
db6eb5be AM |
12777 | if (intel_syntax) |
12778 | break; | |
5dd0794d AM |
12779 | if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS |
12780 | || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS) | |
12781 | { | |
12782 | used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS); | |
12783 | *obufp++ = ','; | |
12784 | *obufp++ = 'p'; | |
12785 | if (prefixes & PREFIX_DS) | |
12786 | *obufp++ = 't'; | |
12787 | else | |
12788 | *obufp++ = 'n'; | |
12789 | } | |
12790 | break; | |
42903f7f L |
12791 | case 'K': |
12792 | USED_REX (REX_W); | |
12793 | if (rex & REX_W) | |
12794 | *obufp++ = 'q'; | |
12795 | else | |
12796 | *obufp++ = 'd'; | |
12797 | break; | |
6dd5059a | 12798 | case 'Z': |
04d824a4 JB |
12799 | if (l != 0 || len != 1) |
12800 | { | |
12801 | if (l != 1 || len != 2 || last[0] != 'X') | |
12802 | { | |
12803 | SAVE_LAST (*p); | |
12804 | break; | |
12805 | } | |
12806 | if (!need_vex || !vex.evex) | |
12807 | abort (); | |
12808 | if (intel_syntax | |
12809 | || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS))) | |
12810 | break; | |
12811 | switch (vex.length) | |
12812 | { | |
12813 | case 128: | |
12814 | *obufp++ = 'x'; | |
12815 | break; | |
12816 | case 256: | |
12817 | *obufp++ = 'y'; | |
12818 | break; | |
12819 | case 512: | |
12820 | *obufp++ = 'z'; | |
12821 | break; | |
12822 | default: | |
12823 | abort (); | |
12824 | } | |
12825 | break; | |
12826 | } | |
6dd5059a L |
12827 | if (intel_syntax) |
12828 | break; | |
12829 | if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS)) | |
12830 | { | |
12831 | *obufp++ = 'q'; | |
12832 | break; | |
12833 | } | |
12834 | /* Fall through. */ | |
98b528ac | 12835 | goto case_L; |
252b5132 | 12836 | case 'L': |
98b528ac L |
12837 | if (l != 0 || len != 1) |
12838 | { | |
12839 | SAVE_LAST (*p); | |
12840 | break; | |
12841 | } | |
dc1e8a47 | 12842 | case_L: |
db6eb5be AM |
12843 | if (intel_syntax) |
12844 | break; | |
252b5132 RH |
12845 | if (sizeflag & SUFFIX_ALWAYS) |
12846 | *obufp++ = 'l'; | |
252b5132 | 12847 | break; |
9d141669 L |
12848 | case 'M': |
12849 | if (intel_mnemonic != cond) | |
12850 | *obufp++ = 'r'; | |
12851 | break; | |
252b5132 RH |
12852 | case 'N': |
12853 | if ((prefixes & PREFIX_FWAIT) == 0) | |
12854 | *obufp++ = 'n'; | |
7d421014 ILT |
12855 | else |
12856 | used_prefixes |= PREFIX_FWAIT; | |
252b5132 | 12857 | break; |
52b15da3 | 12858 | case 'O': |
161a04f6 L |
12859 | USED_REX (REX_W); |
12860 | if (rex & REX_W) | |
6439fc28 | 12861 | *obufp++ = 'o'; |
a35ca55a JB |
12862 | else if (intel_syntax && (sizeflag & DFLAG)) |
12863 | *obufp++ = 'q'; | |
52b15da3 JH |
12864 | else |
12865 | *obufp++ = 'd'; | |
161a04f6 | 12866 | if (!(rex & REX_W)) |
a35ca55a | 12867 | used_prefixes |= (prefixes & PREFIX_DATA); |
52b15da3 | 12868 | break; |
07f5af7d L |
12869 | case '&': |
12870 | if (!intel_syntax | |
12871 | && address_mode == mode_64bit | |
12872 | && isa64 == intel64) | |
12873 | { | |
12874 | *obufp++ = 'q'; | |
12875 | break; | |
12876 | } | |
12877 | /* Fall through. */ | |
6439fc28 | 12878 | case 'T': |
d9e3625e L |
12879 | if (!intel_syntax |
12880 | && address_mode == mode_64bit | |
7bb15c6f | 12881 | && ((sizeflag & DFLAG) || (rex & REX_W))) |
6439fc28 AM |
12882 | { |
12883 | *obufp++ = 'q'; | |
12884 | break; | |
12885 | } | |
6608db57 | 12886 | /* Fall through. */ |
4b4c407a | 12887 | goto case_P; |
252b5132 | 12888 | case 'P': |
4b4c407a | 12889 | if (l == 0 && len == 1) |
d9e3625e | 12890 | { |
dc1e8a47 | 12891 | case_P: |
4b4c407a | 12892 | if (intel_syntax) |
d9e3625e | 12893 | { |
4b4c407a L |
12894 | if ((rex & REX_W) == 0 |
12895 | && (prefixes & PREFIX_DATA)) | |
12896 | { | |
12897 | if ((sizeflag & DFLAG) == 0) | |
12898 | *obufp++ = 'w'; | |
12899 | used_prefixes |= (prefixes & PREFIX_DATA); | |
12900 | } | |
12901 | break; | |
12902 | } | |
12903 | if ((prefixes & PREFIX_DATA) | |
12904 | || (rex & REX_W) | |
12905 | || (sizeflag & SUFFIX_ALWAYS)) | |
12906 | { | |
12907 | USED_REX (REX_W); | |
12908 | if (rex & REX_W) | |
12909 | *obufp++ = 'q'; | |
12910 | else | |
12911 | { | |
12912 | if (sizeflag & DFLAG) | |
12913 | *obufp++ = 'l'; | |
12914 | else | |
12915 | *obufp++ = 'w'; | |
12916 | used_prefixes |= (prefixes & PREFIX_DATA); | |
12917 | } | |
d9e3625e | 12918 | } |
d9e3625e | 12919 | } |
4b4c407a | 12920 | else |
252b5132 | 12921 | { |
4b4c407a L |
12922 | if (l != 1 || len != 2 || last[0] != 'L') |
12923 | { | |
12924 | SAVE_LAST (*p); | |
12925 | break; | |
12926 | } | |
12927 | ||
12928 | if ((prefixes & PREFIX_DATA) | |
12929 | || (rex & REX_W) | |
12930 | || (sizeflag & SUFFIX_ALWAYS)) | |
52b15da3 | 12931 | { |
4b4c407a L |
12932 | USED_REX (REX_W); |
12933 | if (rex & REX_W) | |
12934 | *obufp++ = 'q'; | |
12935 | else | |
12936 | { | |
12937 | if (sizeflag & DFLAG) | |
12938 | *obufp++ = intel_syntax ? 'd' : 'l'; | |
12939 | else | |
12940 | *obufp++ = 'w'; | |
12941 | used_prefixes |= (prefixes & PREFIX_DATA); | |
12942 | } | |
52b15da3 | 12943 | } |
252b5132 RH |
12944 | } |
12945 | break; | |
6439fc28 | 12946 | case 'U': |
db6eb5be AM |
12947 | if (intel_syntax) |
12948 | break; | |
7bb15c6f | 12949 | if (address_mode == mode_64bit |
6c067bbb | 12950 | && ((sizeflag & DFLAG) || (rex & REX_W))) |
6439fc28 | 12951 | { |
7967e09e | 12952 | if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS)) |
1a114b12 | 12953 | *obufp++ = 'q'; |
6439fc28 AM |
12954 | break; |
12955 | } | |
6608db57 | 12956 | /* Fall through. */ |
98b528ac | 12957 | goto case_Q; |
252b5132 | 12958 | case 'Q': |
98b528ac | 12959 | if (l == 0 && len == 1) |
252b5132 | 12960 | { |
dc1e8a47 | 12961 | case_Q: |
98b528ac L |
12962 | if (intel_syntax && !alt) |
12963 | break; | |
12964 | USED_REX (REX_W); | |
12965 | if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS)) | |
52b15da3 | 12966 | { |
98b528ac L |
12967 | if (rex & REX_W) |
12968 | *obufp++ = 'q'; | |
52b15da3 | 12969 | else |
98b528ac L |
12970 | { |
12971 | if (sizeflag & DFLAG) | |
12972 | *obufp++ = intel_syntax ? 'd' : 'l'; | |
12973 | else | |
12974 | *obufp++ = 'w'; | |
f16cd0d5 | 12975 | used_prefixes |= (prefixes & PREFIX_DATA); |
98b528ac | 12976 | } |
52b15da3 | 12977 | } |
98b528ac L |
12978 | } |
12979 | else | |
12980 | { | |
12981 | if (l != 1 || len != 2 || last[0] != 'L') | |
12982 | { | |
12983 | SAVE_LAST (*p); | |
12984 | break; | |
12985 | } | |
589958d6 | 12986 | if ((intel_syntax && need_modrm) |
98b528ac L |
12987 | || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS))) |
12988 | break; | |
12989 | if ((rex & REX_W)) | |
12990 | { | |
12991 | USED_REX (REX_W); | |
12992 | *obufp++ = 'q'; | |
12993 | } | |
589958d6 JB |
12994 | else if((address_mode == mode_64bit && need_modrm) |
12995 | || (sizeflag & SUFFIX_ALWAYS)) | |
12996 | *obufp++ = intel_syntax? 'd' : 'l'; | |
252b5132 RH |
12997 | } |
12998 | break; | |
12999 | case 'R': | |
161a04f6 L |
13000 | USED_REX (REX_W); |
13001 | if (rex & REX_W) | |
a35ca55a JB |
13002 | *obufp++ = 'q'; |
13003 | else if (sizeflag & DFLAG) | |
c608c12e | 13004 | { |
a35ca55a | 13005 | if (intel_syntax) |
c608c12e | 13006 | *obufp++ = 'd'; |
c608c12e | 13007 | else |
a35ca55a | 13008 | *obufp++ = 'l'; |
c608c12e | 13009 | } |
252b5132 | 13010 | else |
a35ca55a JB |
13011 | *obufp++ = 'w'; |
13012 | if (intel_syntax && !p[1] | |
161a04f6 | 13013 | && ((rex & REX_W) || (sizeflag & DFLAG))) |
a35ca55a | 13014 | *obufp++ = 'e'; |
161a04f6 | 13015 | if (!(rex & REX_W)) |
52b15da3 | 13016 | used_prefixes |= (prefixes & PREFIX_DATA); |
252b5132 | 13017 | break; |
1a114b12 | 13018 | case 'V': |
4b06377f | 13019 | if (l == 0 && len == 1) |
1a114b12 | 13020 | { |
4b06377f L |
13021 | if (intel_syntax) |
13022 | break; | |
7bb15c6f | 13023 | if (address_mode == mode_64bit |
6c067bbb | 13024 | && ((sizeflag & DFLAG) || (rex & REX_W))) |
4b06377f L |
13025 | { |
13026 | if (sizeflag & SUFFIX_ALWAYS) | |
13027 | *obufp++ = 'q'; | |
13028 | break; | |
13029 | } | |
13030 | } | |
13031 | else | |
13032 | { | |
13033 | if (l != 1 | |
13034 | || len != 2 | |
13035 | || last[0] != 'L') | |
13036 | { | |
13037 | SAVE_LAST (*p); | |
13038 | break; | |
13039 | } | |
13040 | ||
13041 | if (rex & REX_W) | |
13042 | { | |
13043 | *obufp++ = 'a'; | |
13044 | *obufp++ = 'b'; | |
13045 | *obufp++ = 's'; | |
13046 | } | |
1a114b12 JB |
13047 | } |
13048 | /* Fall through. */ | |
4b06377f | 13049 | goto case_S; |
252b5132 | 13050 | case 'S': |
4b06377f | 13051 | if (l == 0 && len == 1) |
252b5132 | 13052 | { |
dc1e8a47 | 13053 | case_S: |
4b06377f L |
13054 | if (intel_syntax) |
13055 | break; | |
13056 | if (sizeflag & SUFFIX_ALWAYS) | |
52b15da3 | 13057 | { |
4b06377f L |
13058 | if (rex & REX_W) |
13059 | *obufp++ = 'q'; | |
52b15da3 | 13060 | else |
4b06377f L |
13061 | { |
13062 | if (sizeflag & DFLAG) | |
13063 | *obufp++ = 'l'; | |
13064 | else | |
13065 | *obufp++ = 'w'; | |
13066 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13067 | } | |
13068 | } | |
13069 | } | |
13070 | else | |
13071 | { | |
13072 | if (l != 1 | |
13073 | || len != 2 | |
13074 | || last[0] != 'L') | |
13075 | { | |
13076 | SAVE_LAST (*p); | |
13077 | break; | |
52b15da3 | 13078 | } |
4b06377f L |
13079 | |
13080 | if (address_mode == mode_64bit | |
13081 | && !(prefixes & PREFIX_ADDR)) | |
13082 | { | |
13083 | *obufp++ = 'a'; | |
13084 | *obufp++ = 'b'; | |
13085 | *obufp++ = 's'; | |
13086 | } | |
13087 | ||
13088 | goto case_S; | |
252b5132 | 13089 | } |
252b5132 | 13090 | break; |
041bd2e0 | 13091 | case 'X': |
c0f3af97 L |
13092 | if (l != 0 || len != 1) |
13093 | { | |
13094 | SAVE_LAST (*p); | |
13095 | break; | |
13096 | } | |
bf926894 JB |
13097 | if (need_vex |
13098 | ? vex.prefix == DATA_PREFIX_OPCODE | |
13099 | : prefixes & PREFIX_DATA) | |
c0f3af97 | 13100 | { |
bf926894 JB |
13101 | *obufp++ = 'd'; |
13102 | used_prefixes |= PREFIX_DATA; | |
c0f3af97 | 13103 | } |
041bd2e0 | 13104 | else |
bf926894 | 13105 | *obufp++ = 's'; |
041bd2e0 | 13106 | break; |
76f227a5 | 13107 | case 'Y': |
c0f3af97 | 13108 | if (l == 0 && len == 1) |
9646c87b | 13109 | abort (); |
c0f3af97 L |
13110 | else |
13111 | { | |
13112 | if (l != 1 || len != 2 || last[0] != 'X') | |
13113 | { | |
13114 | SAVE_LAST (*p); | |
13115 | break; | |
13116 | } | |
13117 | if (!need_vex) | |
13118 | abort (); | |
13119 | if (intel_syntax | |
04d824a4 | 13120 | || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS))) |
c0f3af97 L |
13121 | break; |
13122 | switch (vex.length) | |
13123 | { | |
13124 | case 128: | |
13125 | *obufp++ = 'x'; | |
13126 | break; | |
13127 | case 256: | |
13128 | *obufp++ = 'y'; | |
13129 | break; | |
04d824a4 JB |
13130 | case 512: |
13131 | if (!vex.evex) | |
c0f3af97 | 13132 | default: |
04d824a4 | 13133 | abort (); |
c0f3af97 | 13134 | } |
76f227a5 JH |
13135 | } |
13136 | break; | |
252b5132 | 13137 | case 'W': |
0bfee649 | 13138 | if (l == 0 && len == 1) |
a35ca55a | 13139 | { |
0bfee649 L |
13140 | /* operand size flag for cwtl, cbtw */ |
13141 | USED_REX (REX_W); | |
13142 | if (rex & REX_W) | |
13143 | { | |
13144 | if (intel_syntax) | |
13145 | *obufp++ = 'd'; | |
13146 | else | |
13147 | *obufp++ = 'l'; | |
13148 | } | |
13149 | else if (sizeflag & DFLAG) | |
13150 | *obufp++ = 'w'; | |
a35ca55a | 13151 | else |
0bfee649 L |
13152 | *obufp++ = 'b'; |
13153 | if (!(rex & REX_W)) | |
13154 | used_prefixes |= (prefixes & PREFIX_DATA); | |
a35ca55a | 13155 | } |
252b5132 | 13156 | else |
0bfee649 | 13157 | { |
6c30d220 L |
13158 | if (l != 1 |
13159 | || len != 2 | |
13160 | || (last[0] != 'X' | |
13161 | && last[0] != 'L')) | |
0bfee649 L |
13162 | { |
13163 | SAVE_LAST (*p); | |
13164 | break; | |
13165 | } | |
13166 | if (!need_vex) | |
13167 | abort (); | |
6c30d220 L |
13168 | if (last[0] == 'X') |
13169 | *obufp++ = vex.w ? 'd': 's'; | |
13170 | else | |
13171 | *obufp++ = vex.w ? 'q': 'd'; | |
0bfee649 | 13172 | } |
252b5132 | 13173 | break; |
a72d2af2 L |
13174 | case '^': |
13175 | if (intel_syntax) | |
13176 | break; | |
5990e377 JB |
13177 | if (isa64 == intel64 && (rex & REX_W)) |
13178 | { | |
13179 | USED_REX (REX_W); | |
13180 | *obufp++ = 'q'; | |
13181 | break; | |
13182 | } | |
a72d2af2 L |
13183 | if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS)) |
13184 | { | |
13185 | if (sizeflag & DFLAG) | |
13186 | *obufp++ = 'l'; | |
13187 | else | |
13188 | *obufp++ = 'w'; | |
13189 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13190 | } | |
13191 | break; | |
5db04b09 L |
13192 | case '@': |
13193 | if (intel_syntax) | |
13194 | break; | |
13195 | if (address_mode == mode_64bit | |
13196 | && (isa64 == intel64 | |
13197 | || ((sizeflag & DFLAG) || (rex & REX_W)))) | |
13198 | *obufp++ = 'q'; | |
13199 | else if ((prefixes & PREFIX_DATA)) | |
13200 | { | |
13201 | if (!(sizeflag & DFLAG)) | |
13202 | *obufp++ = 'w'; | |
13203 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13204 | } | |
13205 | break; | |
252b5132 RH |
13206 | } |
13207 | } | |
13208 | *obufp = 0; | |
ea397f5b | 13209 | mnemonicendp = obufp; |
6439fc28 | 13210 | return 0; |
252b5132 RH |
13211 | } |
13212 | ||
13213 | static void | |
26ca5450 | 13214 | oappend (const char *s) |
252b5132 | 13215 | { |
ea397f5b | 13216 | obufp = stpcpy (obufp, s); |
252b5132 RH |
13217 | } |
13218 | ||
13219 | static void | |
26ca5450 | 13220 | append_seg (void) |
252b5132 | 13221 | { |
285ca992 L |
13222 | /* Only print the active segment register. */ |
13223 | if (!active_seg_prefix) | |
13224 | return; | |
13225 | ||
13226 | used_prefixes |= active_seg_prefix; | |
13227 | switch (active_seg_prefix) | |
7d421014 | 13228 | { |
285ca992 | 13229 | case PREFIX_CS: |
9ce09ba2 | 13230 | oappend_maybe_intel ("%cs:"); |
285ca992 L |
13231 | break; |
13232 | case PREFIX_DS: | |
9ce09ba2 | 13233 | oappend_maybe_intel ("%ds:"); |
285ca992 L |
13234 | break; |
13235 | case PREFIX_SS: | |
9ce09ba2 | 13236 | oappend_maybe_intel ("%ss:"); |
285ca992 L |
13237 | break; |
13238 | case PREFIX_ES: | |
9ce09ba2 | 13239 | oappend_maybe_intel ("%es:"); |
285ca992 L |
13240 | break; |
13241 | case PREFIX_FS: | |
9ce09ba2 | 13242 | oappend_maybe_intel ("%fs:"); |
285ca992 L |
13243 | break; |
13244 | case PREFIX_GS: | |
9ce09ba2 | 13245 | oappend_maybe_intel ("%gs:"); |
285ca992 L |
13246 | break; |
13247 | default: | |
13248 | break; | |
7d421014 | 13249 | } |
252b5132 RH |
13250 | } |
13251 | ||
13252 | static void | |
26ca5450 | 13253 | OP_indirE (int bytemode, int sizeflag) |
252b5132 RH |
13254 | { |
13255 | if (!intel_syntax) | |
13256 | oappend ("*"); | |
13257 | OP_E (bytemode, sizeflag); | |
13258 | } | |
13259 | ||
52b15da3 | 13260 | static void |
26ca5450 | 13261 | print_operand_value (char *buf, int hex, bfd_vma disp) |
52b15da3 | 13262 | { |
cb712a9e | 13263 | if (address_mode == mode_64bit) |
52b15da3 JH |
13264 | { |
13265 | if (hex) | |
13266 | { | |
13267 | char tmp[30]; | |
13268 | int i; | |
13269 | buf[0] = '0'; | |
13270 | buf[1] = 'x'; | |
13271 | sprintf_vma (tmp, disp); | |
6608db57 | 13272 | for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++); |
52b15da3 JH |
13273 | strcpy (buf + 2, tmp + i); |
13274 | } | |
13275 | else | |
13276 | { | |
13277 | bfd_signed_vma v = disp; | |
13278 | char tmp[30]; | |
13279 | int i; | |
13280 | if (v < 0) | |
13281 | { | |
13282 | *(buf++) = '-'; | |
13283 | v = -disp; | |
6608db57 | 13284 | /* Check for possible overflow on 0x8000000000000000. */ |
52b15da3 JH |
13285 | if (v < 0) |
13286 | { | |
13287 | strcpy (buf, "9223372036854775808"); | |
13288 | return; | |
13289 | } | |
13290 | } | |
13291 | if (!v) | |
13292 | { | |
13293 | strcpy (buf, "0"); | |
13294 | return; | |
13295 | } | |
13296 | ||
13297 | i = 0; | |
13298 | tmp[29] = 0; | |
13299 | while (v) | |
13300 | { | |
6608db57 | 13301 | tmp[28 - i] = (v % 10) + '0'; |
52b15da3 JH |
13302 | v /= 10; |
13303 | i++; | |
13304 | } | |
13305 | strcpy (buf, tmp + 29 - i); | |
13306 | } | |
13307 | } | |
13308 | else | |
13309 | { | |
13310 | if (hex) | |
13311 | sprintf (buf, "0x%x", (unsigned int) disp); | |
13312 | else | |
13313 | sprintf (buf, "%d", (int) disp); | |
13314 | } | |
13315 | } | |
13316 | ||
5d669648 L |
13317 | /* Put DISP in BUF as signed hex number. */ |
13318 | ||
13319 | static void | |
13320 | print_displacement (char *buf, bfd_vma disp) | |
13321 | { | |
13322 | bfd_signed_vma val = disp; | |
13323 | char tmp[30]; | |
13324 | int i, j = 0; | |
13325 | ||
13326 | if (val < 0) | |
13327 | { | |
13328 | buf[j++] = '-'; | |
13329 | val = -disp; | |
13330 | ||
13331 | /* Check for possible overflow. */ | |
13332 | if (val < 0) | |
13333 | { | |
13334 | switch (address_mode) | |
13335 | { | |
13336 | case mode_64bit: | |
13337 | strcpy (buf + j, "0x8000000000000000"); | |
13338 | break; | |
13339 | case mode_32bit: | |
13340 | strcpy (buf + j, "0x80000000"); | |
13341 | break; | |
13342 | case mode_16bit: | |
13343 | strcpy (buf + j, "0x8000"); | |
13344 | break; | |
13345 | } | |
13346 | return; | |
13347 | } | |
13348 | } | |
13349 | ||
13350 | buf[j++] = '0'; | |
13351 | buf[j++] = 'x'; | |
13352 | ||
0af1713e | 13353 | sprintf_vma (tmp, (bfd_vma) val); |
5d669648 L |
13354 | for (i = 0; tmp[i] == '0'; i++) |
13355 | continue; | |
13356 | if (tmp[i] == '\0') | |
13357 | i--; | |
13358 | strcpy (buf + j, tmp + i); | |
13359 | } | |
13360 | ||
3f31e633 JB |
13361 | static void |
13362 | intel_operand_size (int bytemode, int sizeflag) | |
13363 | { | |
43234a1e L |
13364 | if (vex.evex |
13365 | && vex.b | |
13366 | && (bytemode == x_mode | |
13367 | || bytemode == evex_half_bcst_xmmq_mode)) | |
13368 | { | |
13369 | if (vex.w) | |
13370 | oappend ("QWORD PTR "); | |
13371 | else | |
13372 | oappend ("DWORD PTR "); | |
13373 | return; | |
13374 | } | |
3f31e633 JB |
13375 | switch (bytemode) |
13376 | { | |
13377 | case b_mode: | |
b6169b20 | 13378 | case b_swap_mode: |
42903f7f | 13379 | case dqb_mode: |
1ba585e8 | 13380 | case db_mode: |
3f31e633 JB |
13381 | oappend ("BYTE PTR "); |
13382 | break; | |
13383 | case w_mode: | |
1ba585e8 | 13384 | case dw_mode: |
3f31e633 JB |
13385 | case dqw_mode: |
13386 | oappend ("WORD PTR "); | |
13387 | break; | |
07f5af7d L |
13388 | case indir_v_mode: |
13389 | if (address_mode == mode_64bit && isa64 == intel64) | |
13390 | { | |
13391 | oappend ("QWORD PTR "); | |
13392 | break; | |
13393 | } | |
1a0670f3 | 13394 | /* Fall through. */ |
1a114b12 | 13395 | case stack_v_mode: |
7bb15c6f | 13396 | if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W))) |
3f31e633 JB |
13397 | { |
13398 | oappend ("QWORD PTR "); | |
3f31e633 JB |
13399 | break; |
13400 | } | |
1a0670f3 | 13401 | /* Fall through. */ |
3f31e633 | 13402 | case v_mode: |
b6169b20 | 13403 | case v_swap_mode: |
3f31e633 | 13404 | case dq_mode: |
161a04f6 L |
13405 | USED_REX (REX_W); |
13406 | if (rex & REX_W) | |
3f31e633 | 13407 | oappend ("QWORD PTR "); |
3f31e633 | 13408 | else |
f16cd0d5 L |
13409 | { |
13410 | if ((sizeflag & DFLAG) || bytemode == dq_mode) | |
13411 | oappend ("DWORD PTR "); | |
13412 | else | |
13413 | oappend ("WORD PTR "); | |
13414 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13415 | } | |
3f31e633 | 13416 | break; |
52fd6d94 | 13417 | case z_mode: |
161a04f6 | 13418 | if ((rex & REX_W) || (sizeflag & DFLAG)) |
52fd6d94 JB |
13419 | *obufp++ = 'D'; |
13420 | oappend ("WORD PTR "); | |
161a04f6 | 13421 | if (!(rex & REX_W)) |
52fd6d94 JB |
13422 | used_prefixes |= (prefixes & PREFIX_DATA); |
13423 | break; | |
34b772a6 JB |
13424 | case a_mode: |
13425 | if (sizeflag & DFLAG) | |
13426 | oappend ("QWORD PTR "); | |
13427 | else | |
13428 | oappend ("DWORD PTR "); | |
13429 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13430 | break; | |
bc31405e L |
13431 | case movsxd_mode: |
13432 | if (!(sizeflag & DFLAG) && isa64 == intel64) | |
13433 | oappend ("WORD PTR "); | |
13434 | else | |
13435 | oappend ("DWORD PTR "); | |
13436 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13437 | break; | |
3f31e633 | 13438 | case d_mode: |
539f890d | 13439 | case d_scalar_swap_mode: |
fa99fab2 | 13440 | case d_swap_mode: |
42903f7f | 13441 | case dqd_mode: |
3f31e633 JB |
13442 | oappend ("DWORD PTR "); |
13443 | break; | |
13444 | case q_mode: | |
539f890d | 13445 | case q_scalar_swap_mode: |
b6169b20 | 13446 | case q_swap_mode: |
3f31e633 JB |
13447 | oappend ("QWORD PTR "); |
13448 | break; | |
13449 | case m_mode: | |
cb712a9e | 13450 | if (address_mode == mode_64bit) |
3f31e633 JB |
13451 | oappend ("QWORD PTR "); |
13452 | else | |
13453 | oappend ("DWORD PTR "); | |
13454 | break; | |
13455 | case f_mode: | |
13456 | if (sizeflag & DFLAG) | |
13457 | oappend ("FWORD PTR "); | |
13458 | else | |
13459 | oappend ("DWORD PTR "); | |
13460 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13461 | break; | |
13462 | case t_mode: | |
13463 | oappend ("TBYTE PTR "); | |
13464 | break; | |
13465 | case x_mode: | |
b6169b20 | 13466 | case x_swap_mode: |
43234a1e L |
13467 | case evex_x_gscat_mode: |
13468 | case evex_x_nobcst_mode: | |
53467f57 IT |
13469 | case b_scalar_mode: |
13470 | case w_scalar_mode: | |
c0f3af97 L |
13471 | if (need_vex) |
13472 | { | |
13473 | switch (vex.length) | |
13474 | { | |
13475 | case 128: | |
13476 | oappend ("XMMWORD PTR "); | |
13477 | break; | |
13478 | case 256: | |
13479 | oappend ("YMMWORD PTR "); | |
13480 | break; | |
43234a1e L |
13481 | case 512: |
13482 | oappend ("ZMMWORD PTR "); | |
13483 | break; | |
c0f3af97 L |
13484 | default: |
13485 | abort (); | |
13486 | } | |
13487 | } | |
13488 | else | |
13489 | oappend ("XMMWORD PTR "); | |
13490 | break; | |
13491 | case xmm_mode: | |
3f31e633 JB |
13492 | oappend ("XMMWORD PTR "); |
13493 | break; | |
43234a1e L |
13494 | case ymm_mode: |
13495 | oappend ("YMMWORD PTR "); | |
13496 | break; | |
c0f3af97 | 13497 | case xmmq_mode: |
43234a1e | 13498 | case evex_half_bcst_xmmq_mode: |
c0f3af97 L |
13499 | if (!need_vex) |
13500 | abort (); | |
13501 | ||
13502 | switch (vex.length) | |
13503 | { | |
13504 | case 128: | |
13505 | oappend ("QWORD PTR "); | |
13506 | break; | |
13507 | case 256: | |
13508 | oappend ("XMMWORD PTR "); | |
13509 | break; | |
43234a1e L |
13510 | case 512: |
13511 | oappend ("YMMWORD PTR "); | |
13512 | break; | |
c0f3af97 L |
13513 | default: |
13514 | abort (); | |
13515 | } | |
13516 | break; | |
6c30d220 L |
13517 | case xmm_mb_mode: |
13518 | if (!need_vex) | |
13519 | abort (); | |
13520 | ||
13521 | switch (vex.length) | |
13522 | { | |
13523 | case 128: | |
13524 | case 256: | |
43234a1e | 13525 | case 512: |
6c30d220 L |
13526 | oappend ("BYTE PTR "); |
13527 | break; | |
13528 | default: | |
13529 | abort (); | |
13530 | } | |
13531 | break; | |
13532 | case xmm_mw_mode: | |
13533 | if (!need_vex) | |
13534 | abort (); | |
13535 | ||
13536 | switch (vex.length) | |
13537 | { | |
13538 | case 128: | |
13539 | case 256: | |
43234a1e | 13540 | case 512: |
6c30d220 L |
13541 | oappend ("WORD PTR "); |
13542 | break; | |
13543 | default: | |
13544 | abort (); | |
13545 | } | |
13546 | break; | |
13547 | case xmm_md_mode: | |
13548 | if (!need_vex) | |
13549 | abort (); | |
13550 | ||
13551 | switch (vex.length) | |
13552 | { | |
13553 | case 128: | |
13554 | case 256: | |
43234a1e | 13555 | case 512: |
6c30d220 L |
13556 | oappend ("DWORD PTR "); |
13557 | break; | |
13558 | default: | |
13559 | abort (); | |
13560 | } | |
13561 | break; | |
13562 | case xmm_mq_mode: | |
13563 | if (!need_vex) | |
13564 | abort (); | |
13565 | ||
13566 | switch (vex.length) | |
13567 | { | |
13568 | case 128: | |
13569 | case 256: | |
43234a1e | 13570 | case 512: |
6c30d220 L |
13571 | oappend ("QWORD PTR "); |
13572 | break; | |
13573 | default: | |
13574 | abort (); | |
13575 | } | |
13576 | break; | |
13577 | case xmmdw_mode: | |
13578 | if (!need_vex) | |
13579 | abort (); | |
13580 | ||
13581 | switch (vex.length) | |
13582 | { | |
13583 | case 128: | |
13584 | oappend ("WORD PTR "); | |
13585 | break; | |
13586 | case 256: | |
13587 | oappend ("DWORD PTR "); | |
13588 | break; | |
43234a1e L |
13589 | case 512: |
13590 | oappend ("QWORD PTR "); | |
13591 | break; | |
6c30d220 L |
13592 | default: |
13593 | abort (); | |
13594 | } | |
13595 | break; | |
13596 | case xmmqd_mode: | |
13597 | if (!need_vex) | |
13598 | abort (); | |
13599 | ||
13600 | switch (vex.length) | |
13601 | { | |
13602 | case 128: | |
13603 | oappend ("DWORD PTR "); | |
13604 | break; | |
13605 | case 256: | |
13606 | oappend ("QWORD PTR "); | |
13607 | break; | |
43234a1e L |
13608 | case 512: |
13609 | oappend ("XMMWORD PTR "); | |
13610 | break; | |
6c30d220 L |
13611 | default: |
13612 | abort (); | |
13613 | } | |
13614 | break; | |
c0f3af97 L |
13615 | case ymmq_mode: |
13616 | if (!need_vex) | |
13617 | abort (); | |
13618 | ||
13619 | switch (vex.length) | |
13620 | { | |
13621 | case 128: | |
13622 | oappend ("QWORD PTR "); | |
13623 | break; | |
13624 | case 256: | |
13625 | oappend ("YMMWORD PTR "); | |
13626 | break; | |
43234a1e L |
13627 | case 512: |
13628 | oappend ("ZMMWORD PTR "); | |
13629 | break; | |
c0f3af97 L |
13630 | default: |
13631 | abort (); | |
13632 | } | |
13633 | break; | |
6c30d220 L |
13634 | case ymmxmm_mode: |
13635 | if (!need_vex) | |
13636 | abort (); | |
13637 | ||
13638 | switch (vex.length) | |
13639 | { | |
13640 | case 128: | |
13641 | case 256: | |
13642 | oappend ("XMMWORD PTR "); | |
13643 | break; | |
13644 | default: | |
13645 | abort (); | |
13646 | } | |
13647 | break; | |
fb9c77c7 L |
13648 | case o_mode: |
13649 | oappend ("OWORD PTR "); | |
13650 | break; | |
1c480963 | 13651 | case vex_scalar_w_dq_mode: |
0bfee649 L |
13652 | if (!need_vex) |
13653 | abort (); | |
13654 | ||
13655 | if (vex.w) | |
13656 | oappend ("QWORD PTR "); | |
13657 | else | |
13658 | oappend ("DWORD PTR "); | |
13659 | break; | |
43234a1e L |
13660 | case vex_vsib_d_w_dq_mode: |
13661 | case vex_vsib_q_w_dq_mode: | |
13662 | if (!need_vex) | |
13663 | abort (); | |
13664 | ||
13665 | if (!vex.evex) | |
13666 | { | |
13667 | if (vex.w) | |
13668 | oappend ("QWORD PTR "); | |
13669 | else | |
13670 | oappend ("DWORD PTR "); | |
13671 | } | |
13672 | else | |
13673 | { | |
b28d1bda IT |
13674 | switch (vex.length) |
13675 | { | |
13676 | case 128: | |
13677 | oappend ("XMMWORD PTR "); | |
13678 | break; | |
13679 | case 256: | |
13680 | oappend ("YMMWORD PTR "); | |
13681 | break; | |
13682 | case 512: | |
13683 | oappend ("ZMMWORD PTR "); | |
13684 | break; | |
13685 | default: | |
13686 | abort (); | |
13687 | } | |
43234a1e L |
13688 | } |
13689 | break; | |
5fc35d96 IT |
13690 | case vex_vsib_q_w_d_mode: |
13691 | case vex_vsib_d_w_d_mode: | |
b28d1bda | 13692 | if (!need_vex || !vex.evex) |
5fc35d96 IT |
13693 | abort (); |
13694 | ||
b28d1bda IT |
13695 | switch (vex.length) |
13696 | { | |
13697 | case 128: | |
13698 | oappend ("QWORD PTR "); | |
13699 | break; | |
13700 | case 256: | |
13701 | oappend ("XMMWORD PTR "); | |
13702 | break; | |
13703 | case 512: | |
13704 | oappend ("YMMWORD PTR "); | |
13705 | break; | |
13706 | default: | |
13707 | abort (); | |
13708 | } | |
5fc35d96 IT |
13709 | |
13710 | break; | |
1ba585e8 IT |
13711 | case mask_bd_mode: |
13712 | if (!need_vex || vex.length != 128) | |
13713 | abort (); | |
13714 | if (vex.w) | |
13715 | oappend ("DWORD PTR "); | |
13716 | else | |
13717 | oappend ("BYTE PTR "); | |
13718 | break; | |
43234a1e L |
13719 | case mask_mode: |
13720 | if (!need_vex) | |
13721 | abort (); | |
1ba585e8 IT |
13722 | if (vex.w) |
13723 | oappend ("QWORD PTR "); | |
13724 | else | |
13725 | oappend ("WORD PTR "); | |
43234a1e | 13726 | break; |
6c75cc62 | 13727 | case v_bnd_mode: |
d276ec69 | 13728 | case v_bndmk_mode: |
3f31e633 JB |
13729 | default: |
13730 | break; | |
13731 | } | |
13732 | } | |
13733 | ||
252b5132 | 13734 | static void |
c0f3af97 | 13735 | OP_E_register (int bytemode, int sizeflag) |
252b5132 | 13736 | { |
c0f3af97 L |
13737 | int reg = modrm.rm; |
13738 | const char **names; | |
252b5132 | 13739 | |
c0f3af97 L |
13740 | USED_REX (REX_B); |
13741 | if ((rex & REX_B)) | |
13742 | reg += 8; | |
252b5132 | 13743 | |
b6169b20 | 13744 | if ((sizeflag & SUFFIX_ALWAYS) |
1ba585e8 | 13745 | && (bytemode == b_swap_mode |
9f79e886 | 13746 | || bytemode == bnd_swap_mode |
60227d64 | 13747 | || bytemode == v_swap_mode)) |
b6169b20 L |
13748 | swap_operand (); |
13749 | ||
c0f3af97 | 13750 | switch (bytemode) |
252b5132 | 13751 | { |
c0f3af97 | 13752 | case b_mode: |
b6169b20 | 13753 | case b_swap_mode: |
c0f3af97 L |
13754 | USED_REX (0); |
13755 | if (rex) | |
13756 | names = names8rex; | |
13757 | else | |
13758 | names = names8; | |
13759 | break; | |
13760 | case w_mode: | |
13761 | names = names16; | |
13762 | break; | |
13763 | case d_mode: | |
1ba585e8 IT |
13764 | case dw_mode: |
13765 | case db_mode: | |
c0f3af97 L |
13766 | names = names32; |
13767 | break; | |
13768 | case q_mode: | |
13769 | names = names64; | |
13770 | break; | |
13771 | case m_mode: | |
6c75cc62 | 13772 | case v_bnd_mode: |
c0f3af97 L |
13773 | names = address_mode == mode_64bit ? names64 : names32; |
13774 | break; | |
7e8b059b | 13775 | case bnd_mode: |
9f79e886 | 13776 | case bnd_swap_mode: |
0d96e4df L |
13777 | if (reg > 0x3) |
13778 | { | |
13779 | oappend ("(bad)"); | |
13780 | return; | |
13781 | } | |
7e8b059b L |
13782 | names = names_bnd; |
13783 | break; | |
07f5af7d L |
13784 | case indir_v_mode: |
13785 | if (address_mode == mode_64bit && isa64 == intel64) | |
13786 | { | |
13787 | names = names64; | |
13788 | break; | |
13789 | } | |
1a0670f3 | 13790 | /* Fall through. */ |
c0f3af97 | 13791 | case stack_v_mode: |
7bb15c6f | 13792 | if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W))) |
252b5132 | 13793 | { |
c0f3af97 | 13794 | names = names64; |
252b5132 | 13795 | break; |
252b5132 | 13796 | } |
c0f3af97 | 13797 | bytemode = v_mode; |
1a0670f3 | 13798 | /* Fall through. */ |
c0f3af97 | 13799 | case v_mode: |
b6169b20 | 13800 | case v_swap_mode: |
c0f3af97 L |
13801 | case dq_mode: |
13802 | case dqb_mode: | |
13803 | case dqd_mode: | |
13804 | case dqw_mode: | |
13805 | USED_REX (REX_W); | |
13806 | if (rex & REX_W) | |
13807 | names = names64; | |
c0f3af97 | 13808 | else |
f16cd0d5 | 13809 | { |
7bb15c6f | 13810 | if ((sizeflag & DFLAG) |
f16cd0d5 L |
13811 | || (bytemode != v_mode |
13812 | && bytemode != v_swap_mode)) | |
13813 | names = names32; | |
13814 | else | |
13815 | names = names16; | |
13816 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13817 | } | |
c0f3af97 | 13818 | break; |
bc31405e L |
13819 | case movsxd_mode: |
13820 | if (!(sizeflag & DFLAG) && isa64 == intel64) | |
13821 | names = names16; | |
13822 | else | |
13823 | names = names32; | |
13824 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13825 | break; | |
de89d0a3 IT |
13826 | case va_mode: |
13827 | names = (address_mode == mode_64bit | |
13828 | ? names64 : names32); | |
13829 | if (!(prefixes & PREFIX_ADDR)) | |
aa178437 IT |
13830 | names = (address_mode == mode_16bit |
13831 | ? names16 : names); | |
de89d0a3 IT |
13832 | else |
13833 | { | |
13834 | /* Remove "addr16/addr32". */ | |
13835 | all_prefixes[last_addr_prefix] = 0; | |
13836 | names = (address_mode != mode_32bit | |
13837 | ? names32 : names16); | |
13838 | used_prefixes |= PREFIX_ADDR; | |
13839 | } | |
13840 | break; | |
1ba585e8 | 13841 | case mask_bd_mode: |
43234a1e | 13842 | case mask_mode: |
9889cbb1 L |
13843 | if (reg > 0x7) |
13844 | { | |
13845 | oappend ("(bad)"); | |
13846 | return; | |
13847 | } | |
43234a1e L |
13848 | names = names_mask; |
13849 | break; | |
c0f3af97 L |
13850 | case 0: |
13851 | return; | |
13852 | default: | |
13853 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
252b5132 RH |
13854 | return; |
13855 | } | |
c0f3af97 L |
13856 | oappend (names[reg]); |
13857 | } | |
13858 | ||
13859 | static void | |
c1e679ec | 13860 | OP_E_memory (int bytemode, int sizeflag) |
c0f3af97 L |
13861 | { |
13862 | bfd_vma disp = 0; | |
13863 | int add = (rex & REX_B) ? 8 : 0; | |
13864 | int riprel = 0; | |
43234a1e L |
13865 | int shift; |
13866 | ||
13867 | if (vex.evex) | |
13868 | { | |
13869 | /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0. */ | |
13870 | if (vex.b | |
13871 | && bytemode != x_mode | |
90a915bf | 13872 | && bytemode != xmmq_mode |
43234a1e L |
13873 | && bytemode != evex_half_bcst_xmmq_mode) |
13874 | { | |
13875 | BadOp (); | |
13876 | return; | |
13877 | } | |
13878 | switch (bytemode) | |
13879 | { | |
1ba585e8 IT |
13880 | case dqw_mode: |
13881 | case dw_mode: | |
1ba585e8 IT |
13882 | shift = 1; |
13883 | break; | |
13884 | case dqb_mode: | |
13885 | case db_mode: | |
13886 | shift = 0; | |
13887 | break; | |
b50c9f31 JB |
13888 | case dq_mode: |
13889 | if (address_mode != mode_64bit) | |
13890 | { | |
13891 | shift = 2; | |
13892 | break; | |
13893 | } | |
13894 | /* fall through */ | |
4102be5c | 13895 | case vex_scalar_w_dq_mode: |
43234a1e | 13896 | case vex_vsib_d_w_dq_mode: |
5fc35d96 | 13897 | case vex_vsib_d_w_d_mode: |
eaa9d1ad | 13898 | case vex_vsib_q_w_dq_mode: |
5fc35d96 | 13899 | case vex_vsib_q_w_d_mode: |
43234a1e | 13900 | case evex_x_gscat_mode: |
43234a1e L |
13901 | shift = vex.w ? 3 : 2; |
13902 | break; | |
43234a1e L |
13903 | case x_mode: |
13904 | case evex_half_bcst_xmmq_mode: | |
90a915bf | 13905 | case xmmq_mode: |
43234a1e L |
13906 | if (vex.b) |
13907 | { | |
13908 | shift = vex.w ? 3 : 2; | |
13909 | break; | |
13910 | } | |
1a0670f3 | 13911 | /* Fall through. */ |
43234a1e L |
13912 | case xmmqd_mode: |
13913 | case xmmdw_mode: | |
43234a1e L |
13914 | case ymmq_mode: |
13915 | case evex_x_nobcst_mode: | |
13916 | case x_swap_mode: | |
13917 | switch (vex.length) | |
13918 | { | |
13919 | case 128: | |
13920 | shift = 4; | |
13921 | break; | |
13922 | case 256: | |
13923 | shift = 5; | |
13924 | break; | |
13925 | case 512: | |
13926 | shift = 6; | |
13927 | break; | |
13928 | default: | |
13929 | abort (); | |
13930 | } | |
13931 | break; | |
13932 | case ymm_mode: | |
13933 | shift = 5; | |
13934 | break; | |
13935 | case xmm_mode: | |
13936 | shift = 4; | |
13937 | break; | |
13938 | case xmm_mq_mode: | |
13939 | case q_mode: | |
43234a1e L |
13940 | case q_swap_mode: |
13941 | case q_scalar_swap_mode: | |
13942 | shift = 3; | |
13943 | break; | |
13944 | case dqd_mode: | |
13945 | case xmm_md_mode: | |
13946 | case d_mode: | |
43234a1e L |
13947 | case d_swap_mode: |
13948 | case d_scalar_swap_mode: | |
13949 | shift = 2; | |
13950 | break; | |
5074ad8a | 13951 | case w_scalar_mode: |
43234a1e L |
13952 | case xmm_mw_mode: |
13953 | shift = 1; | |
13954 | break; | |
5074ad8a | 13955 | case b_scalar_mode: |
43234a1e L |
13956 | case xmm_mb_mode: |
13957 | shift = 0; | |
13958 | break; | |
13959 | default: | |
13960 | abort (); | |
13961 | } | |
13962 | /* Make necessary corrections to shift for modes that need it. | |
13963 | For these modes we currently have shift 4, 5 or 6 depending on | |
13964 | vex.length (it corresponds to xmmword, ymmword or zmmword | |
13965 | operand). We might want to make it 3, 4 or 5 (e.g. for | |
13966 | xmmq_mode). In case of broadcast enabled the corrections | |
13967 | aren't needed, as element size is always 32 or 64 bits. */ | |
90a915bf IT |
13968 | if (!vex.b |
13969 | && (bytemode == xmmq_mode | |
13970 | || bytemode == evex_half_bcst_xmmq_mode)) | |
43234a1e L |
13971 | shift -= 1; |
13972 | else if (bytemode == xmmqd_mode) | |
13973 | shift -= 2; | |
13974 | else if (bytemode == xmmdw_mode) | |
13975 | shift -= 3; | |
b28d1bda IT |
13976 | else if (bytemode == ymmq_mode && vex.length == 128) |
13977 | shift -= 1; | |
43234a1e L |
13978 | } |
13979 | else | |
13980 | shift = 0; | |
252b5132 | 13981 | |
c0f3af97 | 13982 | USED_REX (REX_B); |
3f31e633 JB |
13983 | if (intel_syntax) |
13984 | intel_operand_size (bytemode, sizeflag); | |
252b5132 RH |
13985 | append_seg (); |
13986 | ||
5d669648 | 13987 | if ((sizeflag & AFLAG) || address_mode == mode_64bit) |
252b5132 | 13988 | { |
5d669648 L |
13989 | /* 32/64 bit address mode */ |
13990 | int havedisp; | |
252b5132 RH |
13991 | int havesib; |
13992 | int havebase; | |
0f7da397 | 13993 | int haveindex; |
20afcfb7 | 13994 | int needindex; |
1bc60e56 | 13995 | int needaddr32; |
82c18208 | 13996 | int base, rbase; |
91d6fa6a | 13997 | int vindex = 0; |
252b5132 | 13998 | int scale = 0; |
7e8b059b L |
13999 | int addr32flag = !((sizeflag & AFLAG) |
14000 | || bytemode == v_bnd_mode | |
d276ec69 | 14001 | || bytemode == v_bndmk_mode |
9f79e886 JB |
14002 | || bytemode == bnd_mode |
14003 | || bytemode == bnd_swap_mode); | |
6c30d220 L |
14004 | const char **indexes64 = names64; |
14005 | const char **indexes32 = names32; | |
252b5132 RH |
14006 | |
14007 | havesib = 0; | |
14008 | havebase = 1; | |
0f7da397 | 14009 | haveindex = 0; |
7967e09e | 14010 | base = modrm.rm; |
252b5132 RH |
14011 | |
14012 | if (base == 4) | |
14013 | { | |
14014 | havesib = 1; | |
dfc8cf43 | 14015 | vindex = sib.index; |
161a04f6 L |
14016 | USED_REX (REX_X); |
14017 | if (rex & REX_X) | |
91d6fa6a | 14018 | vindex += 8; |
6c30d220 L |
14019 | switch (bytemode) |
14020 | { | |
14021 | case vex_vsib_d_w_dq_mode: | |
5fc35d96 | 14022 | case vex_vsib_d_w_d_mode: |
6c30d220 | 14023 | case vex_vsib_q_w_dq_mode: |
5fc35d96 | 14024 | case vex_vsib_q_w_d_mode: |
6c30d220 L |
14025 | if (!need_vex) |
14026 | abort (); | |
43234a1e L |
14027 | if (vex.evex) |
14028 | { | |
14029 | if (!vex.v) | |
14030 | vindex += 16; | |
14031 | } | |
6c30d220 L |
14032 | |
14033 | haveindex = 1; | |
14034 | switch (vex.length) | |
14035 | { | |
14036 | case 128: | |
7bb15c6f | 14037 | indexes64 = indexes32 = names_xmm; |
6c30d220 L |
14038 | break; |
14039 | case 256: | |
5fc35d96 IT |
14040 | if (!vex.w |
14041 | || bytemode == vex_vsib_q_w_dq_mode | |
14042 | || bytemode == vex_vsib_q_w_d_mode) | |
7bb15c6f | 14043 | indexes64 = indexes32 = names_ymm; |
6c30d220 | 14044 | else |
7bb15c6f | 14045 | indexes64 = indexes32 = names_xmm; |
6c30d220 | 14046 | break; |
43234a1e | 14047 | case 512: |
5fc35d96 IT |
14048 | if (!vex.w |
14049 | || bytemode == vex_vsib_q_w_dq_mode | |
14050 | || bytemode == vex_vsib_q_w_d_mode) | |
43234a1e L |
14051 | indexes64 = indexes32 = names_zmm; |
14052 | else | |
14053 | indexes64 = indexes32 = names_ymm; | |
14054 | break; | |
6c30d220 L |
14055 | default: |
14056 | abort (); | |
14057 | } | |
14058 | break; | |
14059 | default: | |
14060 | haveindex = vindex != 4; | |
14061 | break; | |
14062 | } | |
14063 | scale = sib.scale; | |
14064 | base = sib.base; | |
252b5132 RH |
14065 | codep++; |
14066 | } | |
82c18208 | 14067 | rbase = base + add; |
252b5132 | 14068 | |
7967e09e | 14069 | switch (modrm.mod) |
252b5132 RH |
14070 | { |
14071 | case 0: | |
82c18208 | 14072 | if (base == 5) |
252b5132 RH |
14073 | { |
14074 | havebase = 0; | |
cb712a9e | 14075 | if (address_mode == mode_64bit && !havesib) |
52b15da3 JH |
14076 | riprel = 1; |
14077 | disp = get32s (); | |
d276ec69 JB |
14078 | if (riprel && bytemode == v_bndmk_mode) |
14079 | { | |
14080 | oappend ("(bad)"); | |
14081 | return; | |
14082 | } | |
252b5132 RH |
14083 | } |
14084 | break; | |
14085 | case 1: | |
14086 | FETCH_DATA (the_info, codep + 1); | |
14087 | disp = *codep++; | |
14088 | if ((disp & 0x80) != 0) | |
14089 | disp -= 0x100; | |
43234a1e L |
14090 | if (vex.evex && shift > 0) |
14091 | disp <<= shift; | |
252b5132 RH |
14092 | break; |
14093 | case 2: | |
52b15da3 | 14094 | disp = get32s (); |
252b5132 RH |
14095 | break; |
14096 | } | |
14097 | ||
1bc60e56 L |
14098 | needindex = 0; |
14099 | needaddr32 = 0; | |
14100 | if (havesib | |
14101 | && !havebase | |
14102 | && !haveindex | |
14103 | && address_mode != mode_16bit) | |
14104 | { | |
14105 | if (address_mode == mode_64bit) | |
14106 | { | |
14107 | /* Display eiz instead of addr32. */ | |
14108 | needindex = addr32flag; | |
14109 | needaddr32 = 1; | |
14110 | } | |
14111 | else | |
14112 | { | |
14113 | /* In 32-bit mode, we need index register to tell [offset] | |
14114 | from [eiz*1 + offset]. */ | |
14115 | needindex = 1; | |
14116 | } | |
14117 | } | |
14118 | ||
20afcfb7 L |
14119 | havedisp = (havebase |
14120 | || needindex | |
14121 | || (havesib && (haveindex || scale != 0))); | |
5d669648 | 14122 | |
252b5132 | 14123 | if (!intel_syntax) |
82c18208 | 14124 | if (modrm.mod != 0 || base == 5) |
db6eb5be | 14125 | { |
5d669648 L |
14126 | if (havedisp || riprel) |
14127 | print_displacement (scratchbuf, disp); | |
14128 | else | |
14129 | print_operand_value (scratchbuf, 1, disp); | |
db6eb5be | 14130 | oappend (scratchbuf); |
52b15da3 JH |
14131 | if (riprel) |
14132 | { | |
14133 | set_op (disp, 1); | |
28596323 | 14134 | oappend (!addr32flag ? "(%rip)" : "(%eip)"); |
52b15da3 | 14135 | } |
db6eb5be | 14136 | } |
2da11e11 | 14137 | |
c1dc7af5 | 14138 | if ((havebase || haveindex || needindex || needaddr32 || riprel) |
a23b33b3 JB |
14139 | && (address_mode != mode_64bit |
14140 | || ((bytemode != v_bnd_mode) | |
14141 | && (bytemode != v_bndmk_mode) | |
14142 | && (bytemode != bnd_mode) | |
14143 | && (bytemode != bnd_swap_mode)))) | |
87767711 JB |
14144 | used_prefixes |= PREFIX_ADDR; |
14145 | ||
5d669648 | 14146 | if (havedisp || (intel_syntax && riprel)) |
252b5132 | 14147 | { |
252b5132 | 14148 | *obufp++ = open_char; |
52b15da3 | 14149 | if (intel_syntax && riprel) |
185b1163 L |
14150 | { |
14151 | set_op (disp, 1); | |
28596323 | 14152 | oappend (!addr32flag ? "rip" : "eip"); |
185b1163 | 14153 | } |
db6eb5be | 14154 | *obufp = '\0'; |
252b5132 | 14155 | if (havebase) |
7e8b059b | 14156 | oappend (address_mode == mode_64bit && !addr32flag |
82c18208 | 14157 | ? names64[rbase] : names32[rbase]); |
252b5132 RH |
14158 | if (havesib) |
14159 | { | |
db51cc60 L |
14160 | /* ESP/RSP won't allow index. If base isn't ESP/RSP, |
14161 | print index to tell base + index from base. */ | |
14162 | if (scale != 0 | |
20afcfb7 | 14163 | || needindex |
db51cc60 L |
14164 | || haveindex |
14165 | || (havebase && base != ESP_REG_NUM)) | |
252b5132 | 14166 | { |
9306ca4a | 14167 | if (!intel_syntax || havebase) |
db6eb5be | 14168 | { |
9306ca4a JB |
14169 | *obufp++ = separator_char; |
14170 | *obufp = '\0'; | |
db6eb5be | 14171 | } |
db51cc60 | 14172 | if (haveindex) |
7e8b059b | 14173 | oappend (address_mode == mode_64bit && !addr32flag |
6c30d220 | 14174 | ? indexes64[vindex] : indexes32[vindex]); |
db51cc60 | 14175 | else |
7e8b059b | 14176 | oappend (address_mode == mode_64bit && !addr32flag |
db51cc60 L |
14177 | ? index64 : index32); |
14178 | ||
db6eb5be AM |
14179 | *obufp++ = scale_char; |
14180 | *obufp = '\0'; | |
14181 | sprintf (scratchbuf, "%d", 1 << scale); | |
14182 | oappend (scratchbuf); | |
14183 | } | |
252b5132 | 14184 | } |
185b1163 | 14185 | if (intel_syntax |
82c18208 | 14186 | && (disp || modrm.mod != 0 || base == 5)) |
3d456fa1 | 14187 | { |
db51cc60 | 14188 | if (!havedisp || (bfd_signed_vma) disp >= 0) |
3d456fa1 JB |
14189 | { |
14190 | *obufp++ = '+'; | |
14191 | *obufp = '\0'; | |
14192 | } | |
05203043 | 14193 | else if (modrm.mod != 1 && disp != -disp) |
3d456fa1 JB |
14194 | { |
14195 | *obufp++ = '-'; | |
14196 | *obufp = '\0'; | |
14197 | disp = - (bfd_signed_vma) disp; | |
14198 | } | |
14199 | ||
db51cc60 L |
14200 | if (havedisp) |
14201 | print_displacement (scratchbuf, disp); | |
14202 | else | |
14203 | print_operand_value (scratchbuf, 1, disp); | |
3d456fa1 JB |
14204 | oappend (scratchbuf); |
14205 | } | |
252b5132 RH |
14206 | |
14207 | *obufp++ = close_char; | |
db6eb5be | 14208 | *obufp = '\0'; |
252b5132 RH |
14209 | } |
14210 | else if (intel_syntax) | |
db6eb5be | 14211 | { |
82c18208 | 14212 | if (modrm.mod != 0 || base == 5) |
db6eb5be | 14213 | { |
285ca992 | 14214 | if (!active_seg_prefix) |
252b5132 | 14215 | { |
d708bcba | 14216 | oappend (names_seg[ds_reg - es_reg]); |
252b5132 RH |
14217 | oappend (":"); |
14218 | } | |
52b15da3 | 14219 | print_operand_value (scratchbuf, 1, disp); |
db6eb5be AM |
14220 | oappend (scratchbuf); |
14221 | } | |
14222 | } | |
252b5132 | 14223 | } |
a23b33b3 JB |
14224 | else if (bytemode == v_bnd_mode |
14225 | || bytemode == v_bndmk_mode | |
14226 | || bytemode == bnd_mode | |
14227 | || bytemode == bnd_swap_mode) | |
14228 | { | |
14229 | oappend ("(bad)"); | |
14230 | return; | |
14231 | } | |
252b5132 | 14232 | else |
f16cd0d5 L |
14233 | { |
14234 | /* 16 bit address mode */ | |
14235 | used_prefixes |= prefixes & PREFIX_ADDR; | |
7967e09e | 14236 | switch (modrm.mod) |
252b5132 RH |
14237 | { |
14238 | case 0: | |
7967e09e | 14239 | if (modrm.rm == 6) |
252b5132 RH |
14240 | { |
14241 | disp = get16 (); | |
14242 | if ((disp & 0x8000) != 0) | |
14243 | disp -= 0x10000; | |
14244 | } | |
14245 | break; | |
14246 | case 1: | |
14247 | FETCH_DATA (the_info, codep + 1); | |
14248 | disp = *codep++; | |
14249 | if ((disp & 0x80) != 0) | |
14250 | disp -= 0x100; | |
65f3ed04 JB |
14251 | if (vex.evex && shift > 0) |
14252 | disp <<= shift; | |
252b5132 RH |
14253 | break; |
14254 | case 2: | |
14255 | disp = get16 (); | |
14256 | if ((disp & 0x8000) != 0) | |
14257 | disp -= 0x10000; | |
14258 | break; | |
14259 | } | |
14260 | ||
14261 | if (!intel_syntax) | |
7967e09e | 14262 | if (modrm.mod != 0 || modrm.rm == 6) |
db6eb5be | 14263 | { |
5d669648 | 14264 | print_displacement (scratchbuf, disp); |
db6eb5be AM |
14265 | oappend (scratchbuf); |
14266 | } | |
252b5132 | 14267 | |
7967e09e | 14268 | if (modrm.mod != 0 || modrm.rm != 6) |
252b5132 RH |
14269 | { |
14270 | *obufp++ = open_char; | |
db6eb5be | 14271 | *obufp = '\0'; |
7967e09e | 14272 | oappend (index16[modrm.rm]); |
5d669648 L |
14273 | if (intel_syntax |
14274 | && (disp || modrm.mod != 0 || modrm.rm == 6)) | |
3d456fa1 | 14275 | { |
5d669648 | 14276 | if ((bfd_signed_vma) disp >= 0) |
3d456fa1 JB |
14277 | { |
14278 | *obufp++ = '+'; | |
14279 | *obufp = '\0'; | |
14280 | } | |
7967e09e | 14281 | else if (modrm.mod != 1) |
3d456fa1 JB |
14282 | { |
14283 | *obufp++ = '-'; | |
14284 | *obufp = '\0'; | |
14285 | disp = - (bfd_signed_vma) disp; | |
14286 | } | |
14287 | ||
5d669648 | 14288 | print_displacement (scratchbuf, disp); |
3d456fa1 JB |
14289 | oappend (scratchbuf); |
14290 | } | |
14291 | ||
db6eb5be AM |
14292 | *obufp++ = close_char; |
14293 | *obufp = '\0'; | |
252b5132 | 14294 | } |
3d456fa1 JB |
14295 | else if (intel_syntax) |
14296 | { | |
285ca992 | 14297 | if (!active_seg_prefix) |
3d456fa1 JB |
14298 | { |
14299 | oappend (names_seg[ds_reg - es_reg]); | |
14300 | oappend (":"); | |
14301 | } | |
14302 | print_operand_value (scratchbuf, 1, disp & 0xffff); | |
14303 | oappend (scratchbuf); | |
14304 | } | |
252b5132 | 14305 | } |
43234a1e L |
14306 | if (vex.evex && vex.b |
14307 | && (bytemode == x_mode | |
90a915bf | 14308 | || bytemode == xmmq_mode |
43234a1e L |
14309 | || bytemode == evex_half_bcst_xmmq_mode)) |
14310 | { | |
90a915bf IT |
14311 | if (vex.w |
14312 | || bytemode == xmmq_mode | |
14313 | || bytemode == evex_half_bcst_xmmq_mode) | |
b28d1bda IT |
14314 | { |
14315 | switch (vex.length) | |
14316 | { | |
14317 | case 128: | |
14318 | oappend ("{1to2}"); | |
14319 | break; | |
14320 | case 256: | |
14321 | oappend ("{1to4}"); | |
14322 | break; | |
14323 | case 512: | |
14324 | oappend ("{1to8}"); | |
14325 | break; | |
14326 | default: | |
14327 | abort (); | |
14328 | } | |
14329 | } | |
43234a1e | 14330 | else |
b28d1bda IT |
14331 | { |
14332 | switch (vex.length) | |
14333 | { | |
14334 | case 128: | |
14335 | oappend ("{1to4}"); | |
14336 | break; | |
14337 | case 256: | |
14338 | oappend ("{1to8}"); | |
14339 | break; | |
14340 | case 512: | |
14341 | oappend ("{1to16}"); | |
14342 | break; | |
14343 | default: | |
14344 | abort (); | |
14345 | } | |
14346 | } | |
43234a1e | 14347 | } |
252b5132 RH |
14348 | } |
14349 | ||
c0f3af97 | 14350 | static void |
8b3f93e7 | 14351 | OP_E (int bytemode, int sizeflag) |
c0f3af97 L |
14352 | { |
14353 | /* Skip mod/rm byte. */ | |
14354 | MODRM_CHECK; | |
14355 | codep++; | |
14356 | ||
14357 | if (modrm.mod == 3) | |
14358 | OP_E_register (bytemode, sizeflag); | |
14359 | else | |
c1e679ec | 14360 | OP_E_memory (bytemode, sizeflag); |
c0f3af97 L |
14361 | } |
14362 | ||
252b5132 | 14363 | static void |
26ca5450 | 14364 | OP_G (int bytemode, int sizeflag) |
252b5132 | 14365 | { |
52b15da3 | 14366 | int add = 0; |
c0a30a9f | 14367 | const char **names; |
161a04f6 L |
14368 | USED_REX (REX_R); |
14369 | if (rex & REX_R) | |
52b15da3 | 14370 | add += 8; |
252b5132 RH |
14371 | switch (bytemode) |
14372 | { | |
14373 | case b_mode: | |
52b15da3 JH |
14374 | USED_REX (0); |
14375 | if (rex) | |
7967e09e | 14376 | oappend (names8rex[modrm.reg + add]); |
52b15da3 | 14377 | else |
7967e09e | 14378 | oappend (names8[modrm.reg + add]); |
252b5132 RH |
14379 | break; |
14380 | case w_mode: | |
7967e09e | 14381 | oappend (names16[modrm.reg + add]); |
252b5132 RH |
14382 | break; |
14383 | case d_mode: | |
1ba585e8 IT |
14384 | case db_mode: |
14385 | case dw_mode: | |
7967e09e | 14386 | oappend (names32[modrm.reg + add]); |
52b15da3 JH |
14387 | break; |
14388 | case q_mode: | |
7967e09e | 14389 | oappend (names64[modrm.reg + add]); |
252b5132 | 14390 | break; |
7e8b059b | 14391 | case bnd_mode: |
0d96e4df L |
14392 | if (modrm.reg > 0x3) |
14393 | { | |
14394 | oappend ("(bad)"); | |
14395 | return; | |
14396 | } | |
7e8b059b L |
14397 | oappend (names_bnd[modrm.reg]); |
14398 | break; | |
252b5132 | 14399 | case v_mode: |
9306ca4a | 14400 | case dq_mode: |
42903f7f L |
14401 | case dqb_mode: |
14402 | case dqd_mode: | |
9306ca4a | 14403 | case dqw_mode: |
bc31405e | 14404 | case movsxd_mode: |
161a04f6 L |
14405 | USED_REX (REX_W); |
14406 | if (rex & REX_W) | |
7967e09e | 14407 | oappend (names64[modrm.reg + add]); |
252b5132 | 14408 | else |
f16cd0d5 | 14409 | { |
bc31405e L |
14410 | if ((sizeflag & DFLAG) |
14411 | || (bytemode != v_mode && bytemode != movsxd_mode)) | |
f16cd0d5 L |
14412 | oappend (names32[modrm.reg + add]); |
14413 | else | |
14414 | oappend (names16[modrm.reg + add]); | |
14415 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14416 | } | |
252b5132 | 14417 | break; |
c0a30a9f L |
14418 | case va_mode: |
14419 | names = (address_mode == mode_64bit | |
14420 | ? names64 : names32); | |
14421 | if (!(prefixes & PREFIX_ADDR)) | |
14422 | { | |
14423 | if (address_mode == mode_16bit) | |
14424 | names = names16; | |
14425 | } | |
14426 | else | |
14427 | { | |
14428 | /* Remove "addr16/addr32". */ | |
14429 | all_prefixes[last_addr_prefix] = 0; | |
14430 | names = (address_mode != mode_32bit | |
14431 | ? names32 : names16); | |
14432 | used_prefixes |= PREFIX_ADDR; | |
14433 | } | |
14434 | oappend (names[modrm.reg + add]); | |
14435 | break; | |
90700ea2 | 14436 | case m_mode: |
cb712a9e | 14437 | if (address_mode == mode_64bit) |
7967e09e | 14438 | oappend (names64[modrm.reg + add]); |
90700ea2 | 14439 | else |
7967e09e | 14440 | oappend (names32[modrm.reg + add]); |
90700ea2 | 14441 | break; |
1ba585e8 | 14442 | case mask_bd_mode: |
43234a1e | 14443 | case mask_mode: |
9889cbb1 L |
14444 | if ((modrm.reg + add) > 0x7) |
14445 | { | |
14446 | oappend ("(bad)"); | |
14447 | return; | |
14448 | } | |
43234a1e L |
14449 | oappend (names_mask[modrm.reg + add]); |
14450 | break; | |
252b5132 RH |
14451 | default: |
14452 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
14453 | break; | |
14454 | } | |
14455 | } | |
14456 | ||
52b15da3 | 14457 | static bfd_vma |
26ca5450 | 14458 | get64 (void) |
52b15da3 | 14459 | { |
5dd0794d | 14460 | bfd_vma x; |
52b15da3 | 14461 | #ifdef BFD64 |
5dd0794d AM |
14462 | unsigned int a; |
14463 | unsigned int b; | |
14464 | ||
52b15da3 JH |
14465 | FETCH_DATA (the_info, codep + 8); |
14466 | a = *codep++ & 0xff; | |
14467 | a |= (*codep++ & 0xff) << 8; | |
14468 | a |= (*codep++ & 0xff) << 16; | |
070fe95d | 14469 | a |= (*codep++ & 0xffu) << 24; |
5dd0794d | 14470 | b = *codep++ & 0xff; |
52b15da3 JH |
14471 | b |= (*codep++ & 0xff) << 8; |
14472 | b |= (*codep++ & 0xff) << 16; | |
070fe95d | 14473 | b |= (*codep++ & 0xffu) << 24; |
52b15da3 JH |
14474 | x = a + ((bfd_vma) b << 32); |
14475 | #else | |
6608db57 | 14476 | abort (); |
5dd0794d | 14477 | x = 0; |
52b15da3 JH |
14478 | #endif |
14479 | return x; | |
14480 | } | |
14481 | ||
14482 | static bfd_signed_vma | |
26ca5450 | 14483 | get32 (void) |
252b5132 | 14484 | { |
52b15da3 | 14485 | bfd_signed_vma x = 0; |
252b5132 RH |
14486 | |
14487 | FETCH_DATA (the_info, codep + 4); | |
52b15da3 JH |
14488 | x = *codep++ & (bfd_signed_vma) 0xff; |
14489 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 8; | |
14490 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 16; | |
14491 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 24; | |
14492 | return x; | |
14493 | } | |
14494 | ||
14495 | static bfd_signed_vma | |
26ca5450 | 14496 | get32s (void) |
52b15da3 JH |
14497 | { |
14498 | bfd_signed_vma x = 0; | |
14499 | ||
14500 | FETCH_DATA (the_info, codep + 4); | |
14501 | x = *codep++ & (bfd_signed_vma) 0xff; | |
14502 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 8; | |
14503 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 16; | |
14504 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 24; | |
14505 | ||
14506 | x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31); | |
14507 | ||
252b5132 RH |
14508 | return x; |
14509 | } | |
14510 | ||
14511 | static int | |
26ca5450 | 14512 | get16 (void) |
252b5132 RH |
14513 | { |
14514 | int x = 0; | |
14515 | ||
14516 | FETCH_DATA (the_info, codep + 2); | |
14517 | x = *codep++ & 0xff; | |
14518 | x |= (*codep++ & 0xff) << 8; | |
14519 | return x; | |
14520 | } | |
14521 | ||
14522 | static void | |
26ca5450 | 14523 | set_op (bfd_vma op, int riprel) |
252b5132 RH |
14524 | { |
14525 | op_index[op_ad] = op_ad; | |
cb712a9e | 14526 | if (address_mode == mode_64bit) |
7081ff04 AJ |
14527 | { |
14528 | op_address[op_ad] = op; | |
14529 | op_riprel[op_ad] = riprel; | |
14530 | } | |
14531 | else | |
14532 | { | |
14533 | /* Mask to get a 32-bit address. */ | |
14534 | op_address[op_ad] = op & 0xffffffff; | |
14535 | op_riprel[op_ad] = riprel & 0xffffffff; | |
14536 | } | |
252b5132 RH |
14537 | } |
14538 | ||
14539 | static void | |
26ca5450 | 14540 | OP_REG (int code, int sizeflag) |
252b5132 | 14541 | { |
2da11e11 | 14542 | const char *s; |
9b60702d | 14543 | int add; |
de882298 RM |
14544 | |
14545 | switch (code) | |
14546 | { | |
14547 | case es_reg: case ss_reg: case cs_reg: | |
14548 | case ds_reg: case fs_reg: case gs_reg: | |
14549 | oappend (names_seg[code - es_reg]); | |
14550 | return; | |
14551 | } | |
14552 | ||
161a04f6 L |
14553 | USED_REX (REX_B); |
14554 | if (rex & REX_B) | |
52b15da3 | 14555 | add = 8; |
9b60702d L |
14556 | else |
14557 | add = 0; | |
52b15da3 JH |
14558 | |
14559 | switch (code) | |
14560 | { | |
52b15da3 JH |
14561 | case ax_reg: case cx_reg: case dx_reg: case bx_reg: |
14562 | case sp_reg: case bp_reg: case si_reg: case di_reg: | |
14563 | s = names16[code - ax_reg + add]; | |
14564 | break; | |
52b15da3 JH |
14565 | case al_reg: case ah_reg: case cl_reg: case ch_reg: |
14566 | case dl_reg: case dh_reg: case bl_reg: case bh_reg: | |
14567 | USED_REX (0); | |
14568 | if (rex) | |
14569 | s = names8rex[code - al_reg + add]; | |
14570 | else | |
14571 | s = names8[code - al_reg]; | |
14572 | break; | |
6439fc28 AM |
14573 | case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg: |
14574 | case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg: | |
7bb15c6f | 14575 | if (address_mode == mode_64bit |
6c067bbb | 14576 | && ((sizeflag & DFLAG) || (rex & REX_W))) |
6439fc28 AM |
14577 | { |
14578 | s = names64[code - rAX_reg + add]; | |
14579 | break; | |
14580 | } | |
14581 | code += eAX_reg - rAX_reg; | |
6608db57 | 14582 | /* Fall through. */ |
52b15da3 JH |
14583 | case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg: |
14584 | case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg: | |
161a04f6 L |
14585 | USED_REX (REX_W); |
14586 | if (rex & REX_W) | |
52b15da3 | 14587 | s = names64[code - eAX_reg + add]; |
52b15da3 | 14588 | else |
f16cd0d5 L |
14589 | { |
14590 | if (sizeflag & DFLAG) | |
14591 | s = names32[code - eAX_reg + add]; | |
14592 | else | |
14593 | s = names16[code - eAX_reg + add]; | |
14594 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14595 | } | |
52b15da3 | 14596 | break; |
52b15da3 JH |
14597 | default: |
14598 | s = INTERNAL_DISASSEMBLER_ERROR; | |
14599 | break; | |
14600 | } | |
14601 | oappend (s); | |
14602 | } | |
14603 | ||
14604 | static void | |
26ca5450 | 14605 | OP_IMREG (int code, int sizeflag) |
52b15da3 JH |
14606 | { |
14607 | const char *s; | |
252b5132 RH |
14608 | |
14609 | switch (code) | |
14610 | { | |
14611 | case indir_dx_reg: | |
d708bcba | 14612 | if (intel_syntax) |
52fd6d94 | 14613 | s = "dx"; |
d708bcba | 14614 | else |
db6eb5be | 14615 | s = "(%dx)"; |
252b5132 RH |
14616 | break; |
14617 | case ax_reg: case cx_reg: case dx_reg: case bx_reg: | |
14618 | case sp_reg: case bp_reg: case si_reg: case di_reg: | |
14619 | s = names16[code - ax_reg]; | |
14620 | break; | |
14621 | case es_reg: case ss_reg: case cs_reg: | |
14622 | case ds_reg: case fs_reg: case gs_reg: | |
14623 | s = names_seg[code - es_reg]; | |
14624 | break; | |
14625 | case al_reg: case ah_reg: case cl_reg: case ch_reg: | |
14626 | case dl_reg: case dh_reg: case bl_reg: case bh_reg: | |
52b15da3 JH |
14627 | USED_REX (0); |
14628 | if (rex) | |
14629 | s = names8rex[code - al_reg]; | |
14630 | else | |
14631 | s = names8[code - al_reg]; | |
252b5132 RH |
14632 | break; |
14633 | case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg: | |
14634 | case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg: | |
161a04f6 L |
14635 | USED_REX (REX_W); |
14636 | if (rex & REX_W) | |
52b15da3 | 14637 | s = names64[code - eAX_reg]; |
252b5132 | 14638 | else |
f16cd0d5 L |
14639 | { |
14640 | if (sizeflag & DFLAG) | |
14641 | s = names32[code - eAX_reg]; | |
14642 | else | |
14643 | s = names16[code - eAX_reg]; | |
14644 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14645 | } | |
252b5132 | 14646 | break; |
52fd6d94 | 14647 | case z_mode_ax_reg: |
161a04f6 | 14648 | if ((rex & REX_W) || (sizeflag & DFLAG)) |
52fd6d94 JB |
14649 | s = *names32; |
14650 | else | |
14651 | s = *names16; | |
161a04f6 | 14652 | if (!(rex & REX_W)) |
52fd6d94 JB |
14653 | used_prefixes |= (prefixes & PREFIX_DATA); |
14654 | break; | |
252b5132 RH |
14655 | default: |
14656 | s = INTERNAL_DISASSEMBLER_ERROR; | |
14657 | break; | |
14658 | } | |
14659 | oappend (s); | |
14660 | } | |
14661 | ||
14662 | static void | |
26ca5450 | 14663 | OP_I (int bytemode, int sizeflag) |
252b5132 | 14664 | { |
52b15da3 JH |
14665 | bfd_signed_vma op; |
14666 | bfd_signed_vma mask = -1; | |
252b5132 RH |
14667 | |
14668 | switch (bytemode) | |
14669 | { | |
14670 | case b_mode: | |
14671 | FETCH_DATA (the_info, codep + 1); | |
52b15da3 JH |
14672 | op = *codep++; |
14673 | mask = 0xff; | |
14674 | break; | |
252b5132 | 14675 | case v_mode: |
161a04f6 L |
14676 | USED_REX (REX_W); |
14677 | if (rex & REX_W) | |
52b15da3 | 14678 | op = get32s (); |
252b5132 | 14679 | else |
52b15da3 | 14680 | { |
f16cd0d5 L |
14681 | if (sizeflag & DFLAG) |
14682 | { | |
14683 | op = get32 (); | |
14684 | mask = 0xffffffff; | |
14685 | } | |
14686 | else | |
14687 | { | |
14688 | op = get16 (); | |
14689 | mask = 0xfffff; | |
14690 | } | |
14691 | used_prefixes |= (prefixes & PREFIX_DATA); | |
52b15da3 | 14692 | } |
252b5132 | 14693 | break; |
c1dc7af5 JB |
14694 | case d_mode: |
14695 | mask = 0xffffffff; | |
14696 | op = get32 (); | |
14697 | break; | |
252b5132 | 14698 | case w_mode: |
52b15da3 | 14699 | mask = 0xfffff; |
252b5132 RH |
14700 | op = get16 (); |
14701 | break; | |
9306ca4a JB |
14702 | case const_1_mode: |
14703 | if (intel_syntax) | |
6c067bbb | 14704 | oappend ("1"); |
9306ca4a | 14705 | return; |
252b5132 RH |
14706 | default: |
14707 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
14708 | return; | |
14709 | } | |
14710 | ||
52b15da3 JH |
14711 | op &= mask; |
14712 | scratchbuf[0] = '$'; | |
d708bcba | 14713 | print_operand_value (scratchbuf + 1, 1, op); |
9ce09ba2 | 14714 | oappend_maybe_intel (scratchbuf); |
52b15da3 JH |
14715 | scratchbuf[0] = '\0'; |
14716 | } | |
14717 | ||
14718 | static void | |
26ca5450 | 14719 | OP_I64 (int bytemode, int sizeflag) |
52b15da3 | 14720 | { |
a280ab8e | 14721 | if (bytemode != v_mode || address_mode != mode_64bit || !(rex & REX_W)) |
6439fc28 AM |
14722 | { |
14723 | OP_I (bytemode, sizeflag); | |
14724 | return; | |
14725 | } | |
14726 | ||
a280ab8e | 14727 | USED_REX (REX_W); |
52b15da3 | 14728 | |
52b15da3 | 14729 | scratchbuf[0] = '$'; |
a280ab8e | 14730 | print_operand_value (scratchbuf + 1, 1, get64 ()); |
9ce09ba2 | 14731 | oappend_maybe_intel (scratchbuf); |
252b5132 RH |
14732 | scratchbuf[0] = '\0'; |
14733 | } | |
14734 | ||
14735 | static void | |
26ca5450 | 14736 | OP_sI (int bytemode, int sizeflag) |
252b5132 | 14737 | { |
52b15da3 | 14738 | bfd_signed_vma op; |
252b5132 RH |
14739 | |
14740 | switch (bytemode) | |
14741 | { | |
14742 | case b_mode: | |
e3949f17 | 14743 | case b_T_mode: |
252b5132 RH |
14744 | FETCH_DATA (the_info, codep + 1); |
14745 | op = *codep++; | |
14746 | if ((op & 0x80) != 0) | |
14747 | op -= 0x100; | |
e3949f17 L |
14748 | if (bytemode == b_T_mode) |
14749 | { | |
14750 | if (address_mode != mode_64bit | |
7bb15c6f | 14751 | || !((sizeflag & DFLAG) || (rex & REX_W))) |
e3949f17 | 14752 | { |
6c067bbb RM |
14753 | /* The operand-size prefix is overridden by a REX prefix. */ |
14754 | if ((sizeflag & DFLAG) || (rex & REX_W)) | |
e3949f17 L |
14755 | op &= 0xffffffff; |
14756 | else | |
14757 | op &= 0xffff; | |
14758 | } | |
14759 | } | |
14760 | else | |
14761 | { | |
14762 | if (!(rex & REX_W)) | |
14763 | { | |
14764 | if (sizeflag & DFLAG) | |
14765 | op &= 0xffffffff; | |
14766 | else | |
14767 | op &= 0xffff; | |
14768 | } | |
14769 | } | |
252b5132 RH |
14770 | break; |
14771 | case v_mode: | |
7bb15c6f RM |
14772 | /* The operand-size prefix is overridden by a REX prefix. */ |
14773 | if ((sizeflag & DFLAG) || (rex & REX_W)) | |
52b15da3 | 14774 | op = get32s (); |
252b5132 | 14775 | else |
d9e3625e | 14776 | op = get16 (); |
252b5132 RH |
14777 | break; |
14778 | default: | |
14779 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
14780 | return; | |
14781 | } | |
52b15da3 JH |
14782 | |
14783 | scratchbuf[0] = '$'; | |
14784 | print_operand_value (scratchbuf + 1, 1, op); | |
9ce09ba2 | 14785 | oappend_maybe_intel (scratchbuf); |
252b5132 RH |
14786 | } |
14787 | ||
14788 | static void | |
26ca5450 | 14789 | OP_J (int bytemode, int sizeflag) |
252b5132 | 14790 | { |
52b15da3 | 14791 | bfd_vma disp; |
7081ff04 | 14792 | bfd_vma mask = -1; |
65ca155d | 14793 | bfd_vma segment = 0; |
252b5132 RH |
14794 | |
14795 | switch (bytemode) | |
14796 | { | |
14797 | case b_mode: | |
14798 | FETCH_DATA (the_info, codep + 1); | |
14799 | disp = *codep++; | |
14800 | if ((disp & 0x80) != 0) | |
14801 | disp -= 0x100; | |
14802 | break; | |
14803 | case v_mode: | |
d835a58b | 14804 | if (isa64 != intel64) |
376cd056 | 14805 | case dqw_mode: |
5db04b09 L |
14806 | USED_REX (REX_W); |
14807 | if ((sizeflag & DFLAG) | |
14808 | || (address_mode == mode_64bit | |
d835a58b | 14809 | && ((isa64 == intel64 && bytemode != dqw_mode) |
376cd056 | 14810 | || (rex & REX_W)))) |
52b15da3 | 14811 | disp = get32s (); |
252b5132 RH |
14812 | else |
14813 | { | |
14814 | disp = get16 (); | |
206717e8 L |
14815 | if ((disp & 0x8000) != 0) |
14816 | disp -= 0x10000; | |
65ca155d L |
14817 | /* In 16bit mode, address is wrapped around at 64k within |
14818 | the same segment. Otherwise, a data16 prefix on a jump | |
14819 | instruction means that the pc is masked to 16 bits after | |
14820 | the displacement is added! */ | |
14821 | mask = 0xffff; | |
14822 | if ((prefixes & PREFIX_DATA) == 0) | |
4fd7268a | 14823 | segment = ((start_pc + (codep - start_codep)) |
65ca155d | 14824 | & ~((bfd_vma) 0xffff)); |
252b5132 | 14825 | } |
5db04b09 | 14826 | if (address_mode != mode_64bit |
d835a58b | 14827 | || (isa64 != intel64 && !(rex & REX_W))) |
f16cd0d5 | 14828 | used_prefixes |= (prefixes & PREFIX_DATA); |
252b5132 RH |
14829 | break; |
14830 | default: | |
14831 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
14832 | return; | |
14833 | } | |
42d5f9c6 | 14834 | disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment; |
52b15da3 JH |
14835 | set_op (disp, 0); |
14836 | print_operand_value (scratchbuf, 1, disp); | |
252b5132 RH |
14837 | oappend (scratchbuf); |
14838 | } | |
14839 | ||
252b5132 | 14840 | static void |
ed7841b3 | 14841 | OP_SEG (int bytemode, int sizeflag) |
252b5132 | 14842 | { |
ed7841b3 | 14843 | if (bytemode == w_mode) |
7967e09e | 14844 | oappend (names_seg[modrm.reg]); |
ed7841b3 | 14845 | else |
7967e09e | 14846 | OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag); |
252b5132 RH |
14847 | } |
14848 | ||
14849 | static void | |
26ca5450 | 14850 | OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag) |
252b5132 RH |
14851 | { |
14852 | int seg, offset; | |
14853 | ||
c608c12e | 14854 | if (sizeflag & DFLAG) |
252b5132 | 14855 | { |
c608c12e AM |
14856 | offset = get32 (); |
14857 | seg = get16 (); | |
252b5132 | 14858 | } |
c608c12e AM |
14859 | else |
14860 | { | |
14861 | offset = get16 (); | |
14862 | seg = get16 (); | |
14863 | } | |
7d421014 | 14864 | used_prefixes |= (prefixes & PREFIX_DATA); |
d708bcba | 14865 | if (intel_syntax) |
3f31e633 | 14866 | sprintf (scratchbuf, "0x%x:0x%x", seg, offset); |
d708bcba AM |
14867 | else |
14868 | sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset); | |
c608c12e | 14869 | oappend (scratchbuf); |
252b5132 RH |
14870 | } |
14871 | ||
252b5132 | 14872 | static void |
3f31e633 | 14873 | OP_OFF (int bytemode, int sizeflag) |
252b5132 | 14874 | { |
52b15da3 | 14875 | bfd_vma off; |
252b5132 | 14876 | |
3f31e633 JB |
14877 | if (intel_syntax && (sizeflag & SUFFIX_ALWAYS)) |
14878 | intel_operand_size (bytemode, sizeflag); | |
252b5132 RH |
14879 | append_seg (); |
14880 | ||
cb712a9e | 14881 | if ((sizeflag & AFLAG) || address_mode == mode_64bit) |
252b5132 RH |
14882 | off = get32 (); |
14883 | else | |
14884 | off = get16 (); | |
14885 | ||
14886 | if (intel_syntax) | |
14887 | { | |
285ca992 | 14888 | if (!active_seg_prefix) |
252b5132 | 14889 | { |
d708bcba | 14890 | oappend (names_seg[ds_reg - es_reg]); |
252b5132 RH |
14891 | oappend (":"); |
14892 | } | |
14893 | } | |
52b15da3 JH |
14894 | print_operand_value (scratchbuf, 1, off); |
14895 | oappend (scratchbuf); | |
14896 | } | |
6439fc28 | 14897 | |
52b15da3 | 14898 | static void |
3f31e633 | 14899 | OP_OFF64 (int bytemode, int sizeflag) |
52b15da3 JH |
14900 | { |
14901 | bfd_vma off; | |
14902 | ||
539e75ad L |
14903 | if (address_mode != mode_64bit |
14904 | || (prefixes & PREFIX_ADDR)) | |
6439fc28 AM |
14905 | { |
14906 | OP_OFF (bytemode, sizeflag); | |
14907 | return; | |
14908 | } | |
14909 | ||
3f31e633 JB |
14910 | if (intel_syntax && (sizeflag & SUFFIX_ALWAYS)) |
14911 | intel_operand_size (bytemode, sizeflag); | |
52b15da3 JH |
14912 | append_seg (); |
14913 | ||
6608db57 | 14914 | off = get64 (); |
52b15da3 JH |
14915 | |
14916 | if (intel_syntax) | |
14917 | { | |
285ca992 | 14918 | if (!active_seg_prefix) |
52b15da3 | 14919 | { |
d708bcba | 14920 | oappend (names_seg[ds_reg - es_reg]); |
52b15da3 JH |
14921 | oappend (":"); |
14922 | } | |
14923 | } | |
14924 | print_operand_value (scratchbuf, 1, off); | |
252b5132 RH |
14925 | oappend (scratchbuf); |
14926 | } | |
14927 | ||
14928 | static void | |
26ca5450 | 14929 | ptr_reg (int code, int sizeflag) |
252b5132 | 14930 | { |
2da11e11 | 14931 | const char *s; |
d708bcba | 14932 | |
1d9f512f | 14933 | *obufp++ = open_char; |
20f0a1fc | 14934 | used_prefixes |= (prefixes & PREFIX_ADDR); |
cb712a9e | 14935 | if (address_mode == mode_64bit) |
c1a64871 JH |
14936 | { |
14937 | if (!(sizeflag & AFLAG)) | |
db6eb5be | 14938 | s = names32[code - eAX_reg]; |
c1a64871 | 14939 | else |
db6eb5be | 14940 | s = names64[code - eAX_reg]; |
c1a64871 | 14941 | } |
52b15da3 | 14942 | else if (sizeflag & AFLAG) |
252b5132 RH |
14943 | s = names32[code - eAX_reg]; |
14944 | else | |
14945 | s = names16[code - eAX_reg]; | |
14946 | oappend (s); | |
1d9f512f AM |
14947 | *obufp++ = close_char; |
14948 | *obufp = 0; | |
252b5132 RH |
14949 | } |
14950 | ||
14951 | static void | |
26ca5450 | 14952 | OP_ESreg (int code, int sizeflag) |
252b5132 | 14953 | { |
9306ca4a | 14954 | if (intel_syntax) |
52fd6d94 JB |
14955 | { |
14956 | switch (codep[-1]) | |
14957 | { | |
14958 | case 0x6d: /* insw/insl */ | |
14959 | intel_operand_size (z_mode, sizeflag); | |
14960 | break; | |
14961 | case 0xa5: /* movsw/movsl/movsq */ | |
14962 | case 0xa7: /* cmpsw/cmpsl/cmpsq */ | |
14963 | case 0xab: /* stosw/stosl */ | |
14964 | case 0xaf: /* scasw/scasl */ | |
14965 | intel_operand_size (v_mode, sizeflag); | |
14966 | break; | |
14967 | default: | |
14968 | intel_operand_size (b_mode, sizeflag); | |
14969 | } | |
14970 | } | |
9ce09ba2 | 14971 | oappend_maybe_intel ("%es:"); |
252b5132 RH |
14972 | ptr_reg (code, sizeflag); |
14973 | } | |
14974 | ||
14975 | static void | |
26ca5450 | 14976 | OP_DSreg (int code, int sizeflag) |
252b5132 | 14977 | { |
9306ca4a | 14978 | if (intel_syntax) |
52fd6d94 JB |
14979 | { |
14980 | switch (codep[-1]) | |
14981 | { | |
14982 | case 0x6f: /* outsw/outsl */ | |
14983 | intel_operand_size (z_mode, sizeflag); | |
14984 | break; | |
14985 | case 0xa5: /* movsw/movsl/movsq */ | |
14986 | case 0xa7: /* cmpsw/cmpsl/cmpsq */ | |
14987 | case 0xad: /* lodsw/lodsl/lodsq */ | |
14988 | intel_operand_size (v_mode, sizeflag); | |
14989 | break; | |
14990 | default: | |
14991 | intel_operand_size (b_mode, sizeflag); | |
14992 | } | |
14993 | } | |
285ca992 L |
14994 | /* Set active_seg_prefix to PREFIX_DS if it is unset so that the |
14995 | default segment register DS is printed. */ | |
14996 | if (!active_seg_prefix) | |
14997 | active_seg_prefix = PREFIX_DS; | |
6608db57 | 14998 | append_seg (); |
252b5132 RH |
14999 | ptr_reg (code, sizeflag); |
15000 | } | |
15001 | ||
252b5132 | 15002 | static void |
26ca5450 | 15003 | OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 15004 | { |
9b60702d | 15005 | int add; |
161a04f6 | 15006 | if (rex & REX_R) |
c4a530c5 | 15007 | { |
161a04f6 | 15008 | USED_REX (REX_R); |
c4a530c5 JB |
15009 | add = 8; |
15010 | } | |
cb712a9e | 15011 | else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK)) |
c4a530c5 | 15012 | { |
f16cd0d5 | 15013 | all_prefixes[last_lock_prefix] = 0; |
c4a530c5 JB |
15014 | used_prefixes |= PREFIX_LOCK; |
15015 | add = 8; | |
15016 | } | |
9b60702d L |
15017 | else |
15018 | add = 0; | |
7967e09e | 15019 | sprintf (scratchbuf, "%%cr%d", modrm.reg + add); |
9ce09ba2 | 15020 | oappend_maybe_intel (scratchbuf); |
252b5132 RH |
15021 | } |
15022 | ||
252b5132 | 15023 | static void |
26ca5450 | 15024 | OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 15025 | { |
9b60702d | 15026 | int add; |
161a04f6 L |
15027 | USED_REX (REX_R); |
15028 | if (rex & REX_R) | |
52b15da3 | 15029 | add = 8; |
9b60702d L |
15030 | else |
15031 | add = 0; | |
d708bcba | 15032 | if (intel_syntax) |
7967e09e | 15033 | sprintf (scratchbuf, "db%d", modrm.reg + add); |
d708bcba | 15034 | else |
7967e09e | 15035 | sprintf (scratchbuf, "%%db%d", modrm.reg + add); |
252b5132 RH |
15036 | oappend (scratchbuf); |
15037 | } | |
15038 | ||
252b5132 | 15039 | static void |
26ca5450 | 15040 | OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 15041 | { |
7967e09e | 15042 | sprintf (scratchbuf, "%%tr%d", modrm.reg); |
9ce09ba2 | 15043 | oappend_maybe_intel (scratchbuf); |
252b5132 RH |
15044 | } |
15045 | ||
15046 | static void | |
6f74c397 | 15047 | OP_R (int bytemode, int sizeflag) |
252b5132 | 15048 | { |
68f34464 L |
15049 | /* Skip mod/rm byte. */ |
15050 | MODRM_CHECK; | |
15051 | codep++; | |
15052 | OP_E_register (bytemode, sizeflag); | |
252b5132 RH |
15053 | } |
15054 | ||
15055 | static void | |
26ca5450 | 15056 | OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 15057 | { |
b9733481 L |
15058 | int reg = modrm.reg; |
15059 | const char **names; | |
15060 | ||
041bd2e0 JH |
15061 | used_prefixes |= (prefixes & PREFIX_DATA); |
15062 | if (prefixes & PREFIX_DATA) | |
20f0a1fc | 15063 | { |
b9733481 | 15064 | names = names_xmm; |
161a04f6 L |
15065 | USED_REX (REX_R); |
15066 | if (rex & REX_R) | |
b9733481 | 15067 | reg += 8; |
20f0a1fc | 15068 | } |
041bd2e0 | 15069 | else |
b9733481 L |
15070 | names = names_mm; |
15071 | oappend (names[reg]); | |
252b5132 RH |
15072 | } |
15073 | ||
c608c12e | 15074 | static void |
c0f3af97 | 15075 | OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED) |
c608c12e | 15076 | { |
b9733481 L |
15077 | int reg = modrm.reg; |
15078 | const char **names; | |
15079 | ||
161a04f6 L |
15080 | USED_REX (REX_R); |
15081 | if (rex & REX_R) | |
b9733481 | 15082 | reg += 8; |
43234a1e L |
15083 | if (vex.evex) |
15084 | { | |
15085 | if (!vex.r) | |
15086 | reg += 16; | |
15087 | } | |
15088 | ||
539f890d L |
15089 | if (need_vex |
15090 | && bytemode != xmm_mode | |
43234a1e L |
15091 | && bytemode != xmmq_mode |
15092 | && bytemode != evex_half_bcst_xmmq_mode | |
15093 | && bytemode != ymm_mode | |
539f890d | 15094 | && bytemode != scalar_mode) |
c0f3af97 L |
15095 | { |
15096 | switch (vex.length) | |
15097 | { | |
15098 | case 128: | |
b9733481 | 15099 | names = names_xmm; |
c0f3af97 L |
15100 | break; |
15101 | case 256: | |
5fc35d96 IT |
15102 | if (vex.w |
15103 | || (bytemode != vex_vsib_q_w_dq_mode | |
15104 | && bytemode != vex_vsib_q_w_d_mode)) | |
6c30d220 L |
15105 | names = names_ymm; |
15106 | else | |
15107 | names = names_xmm; | |
c0f3af97 | 15108 | break; |
43234a1e L |
15109 | case 512: |
15110 | names = names_zmm; | |
15111 | break; | |
c0f3af97 L |
15112 | default: |
15113 | abort (); | |
15114 | } | |
15115 | } | |
43234a1e L |
15116 | else if (bytemode == xmmq_mode |
15117 | || bytemode == evex_half_bcst_xmmq_mode) | |
15118 | { | |
15119 | switch (vex.length) | |
15120 | { | |
15121 | case 128: | |
15122 | case 256: | |
15123 | names = names_xmm; | |
15124 | break; | |
15125 | case 512: | |
15126 | names = names_ymm; | |
15127 | break; | |
15128 | default: | |
15129 | abort (); | |
15130 | } | |
15131 | } | |
15132 | else if (bytemode == ymm_mode) | |
15133 | names = names_ymm; | |
c0f3af97 | 15134 | else |
b9733481 L |
15135 | names = names_xmm; |
15136 | oappend (names[reg]); | |
c608c12e AM |
15137 | } |
15138 | ||
252b5132 | 15139 | static void |
26ca5450 | 15140 | OP_EM (int bytemode, int sizeflag) |
252b5132 | 15141 | { |
b9733481 L |
15142 | int reg; |
15143 | const char **names; | |
15144 | ||
7967e09e | 15145 | if (modrm.mod != 3) |
252b5132 | 15146 | { |
b6169b20 L |
15147 | if (intel_syntax |
15148 | && (bytemode == v_mode || bytemode == v_swap_mode)) | |
9306ca4a JB |
15149 | { |
15150 | bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode; | |
15151 | used_prefixes |= (prefixes & PREFIX_DATA); | |
6c067bbb | 15152 | } |
252b5132 RH |
15153 | OP_E (bytemode, sizeflag); |
15154 | return; | |
15155 | } | |
15156 | ||
b6169b20 L |
15157 | if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode) |
15158 | swap_operand (); | |
15159 | ||
6608db57 | 15160 | /* Skip mod/rm byte. */ |
4bba6815 | 15161 | MODRM_CHECK; |
252b5132 | 15162 | codep++; |
041bd2e0 | 15163 | used_prefixes |= (prefixes & PREFIX_DATA); |
b9733481 | 15164 | reg = modrm.rm; |
041bd2e0 | 15165 | if (prefixes & PREFIX_DATA) |
20f0a1fc | 15166 | { |
b9733481 | 15167 | names = names_xmm; |
161a04f6 L |
15168 | USED_REX (REX_B); |
15169 | if (rex & REX_B) | |
b9733481 | 15170 | reg += 8; |
20f0a1fc | 15171 | } |
041bd2e0 | 15172 | else |
b9733481 L |
15173 | names = names_mm; |
15174 | oappend (names[reg]); | |
252b5132 RH |
15175 | } |
15176 | ||
246c51aa L |
15177 | /* cvt* are the only instructions in sse2 which have |
15178 | both SSE and MMX operands and also have 0x66 prefix | |
15179 | in their opcode. 0x66 was originally used to differentiate | |
15180 | between SSE and MMX instruction(operands). So we have to handle the | |
4d9567e0 MM |
15181 | cvt* separately using OP_EMC and OP_MXC */ |
15182 | static void | |
15183 | OP_EMC (int bytemode, int sizeflag) | |
15184 | { | |
7967e09e | 15185 | if (modrm.mod != 3) |
4d9567e0 MM |
15186 | { |
15187 | if (intel_syntax && bytemode == v_mode) | |
15188 | { | |
15189 | bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode; | |
15190 | used_prefixes |= (prefixes & PREFIX_DATA); | |
6c067bbb | 15191 | } |
4d9567e0 MM |
15192 | OP_E (bytemode, sizeflag); |
15193 | return; | |
15194 | } | |
246c51aa | 15195 | |
4d9567e0 MM |
15196 | /* Skip mod/rm byte. */ |
15197 | MODRM_CHECK; | |
15198 | codep++; | |
15199 | used_prefixes |= (prefixes & PREFIX_DATA); | |
b9733481 | 15200 | oappend (names_mm[modrm.rm]); |
4d9567e0 MM |
15201 | } |
15202 | ||
15203 | static void | |
15204 | OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
15205 | { | |
15206 | used_prefixes |= (prefixes & PREFIX_DATA); | |
b9733481 | 15207 | oappend (names_mm[modrm.reg]); |
4d9567e0 MM |
15208 | } |
15209 | ||
c608c12e | 15210 | static void |
26ca5450 | 15211 | OP_EX (int bytemode, int sizeflag) |
c608c12e | 15212 | { |
b9733481 L |
15213 | int reg; |
15214 | const char **names; | |
d6f574e0 L |
15215 | |
15216 | /* Skip mod/rm byte. */ | |
15217 | MODRM_CHECK; | |
15218 | codep++; | |
15219 | ||
7967e09e | 15220 | if (modrm.mod != 3) |
c608c12e | 15221 | { |
c1e679ec | 15222 | OP_E_memory (bytemode, sizeflag); |
c608c12e AM |
15223 | return; |
15224 | } | |
d6f574e0 | 15225 | |
b9733481 | 15226 | reg = modrm.rm; |
161a04f6 L |
15227 | USED_REX (REX_B); |
15228 | if (rex & REX_B) | |
b9733481 | 15229 | reg += 8; |
43234a1e L |
15230 | if (vex.evex) |
15231 | { | |
15232 | USED_REX (REX_X); | |
15233 | if ((rex & REX_X)) | |
15234 | reg += 16; | |
15235 | } | |
c608c12e | 15236 | |
b6169b20 | 15237 | if ((sizeflag & SUFFIX_ALWAYS) |
fa99fab2 L |
15238 | && (bytemode == x_swap_mode |
15239 | || bytemode == d_swap_mode | |
7bb15c6f | 15240 | || bytemode == d_scalar_swap_mode |
539f890d L |
15241 | || bytemode == q_swap_mode |
15242 | || bytemode == q_scalar_swap_mode)) | |
b6169b20 L |
15243 | swap_operand (); |
15244 | ||
c0f3af97 L |
15245 | if (need_vex |
15246 | && bytemode != xmm_mode | |
6c30d220 L |
15247 | && bytemode != xmmdw_mode |
15248 | && bytemode != xmmqd_mode | |
15249 | && bytemode != xmm_mb_mode | |
15250 | && bytemode != xmm_mw_mode | |
15251 | && bytemode != xmm_md_mode | |
15252 | && bytemode != xmm_mq_mode | |
539f890d | 15253 | && bytemode != xmmq_mode |
43234a1e L |
15254 | && bytemode != evex_half_bcst_xmmq_mode |
15255 | && bytemode != ymm_mode | |
7bb15c6f | 15256 | && bytemode != d_scalar_swap_mode |
1c480963 L |
15257 | && bytemode != q_scalar_swap_mode |
15258 | && bytemode != vex_scalar_w_dq_mode) | |
c0f3af97 L |
15259 | { |
15260 | switch (vex.length) | |
15261 | { | |
15262 | case 128: | |
b9733481 | 15263 | names = names_xmm; |
c0f3af97 L |
15264 | break; |
15265 | case 256: | |
b9733481 | 15266 | names = names_ymm; |
c0f3af97 | 15267 | break; |
43234a1e L |
15268 | case 512: |
15269 | names = names_zmm; | |
15270 | break; | |
c0f3af97 L |
15271 | default: |
15272 | abort (); | |
15273 | } | |
15274 | } | |
43234a1e L |
15275 | else if (bytemode == xmmq_mode |
15276 | || bytemode == evex_half_bcst_xmmq_mode) | |
15277 | { | |
15278 | switch (vex.length) | |
15279 | { | |
15280 | case 128: | |
15281 | case 256: | |
15282 | names = names_xmm; | |
15283 | break; | |
15284 | case 512: | |
15285 | names = names_ymm; | |
15286 | break; | |
15287 | default: | |
15288 | abort (); | |
15289 | } | |
15290 | } | |
15291 | else if (bytemode == ymm_mode) | |
15292 | names = names_ymm; | |
c0f3af97 | 15293 | else |
b9733481 L |
15294 | names = names_xmm; |
15295 | oappend (names[reg]); | |
c608c12e AM |
15296 | } |
15297 | ||
252b5132 | 15298 | static void |
26ca5450 | 15299 | OP_MS (int bytemode, int sizeflag) |
252b5132 | 15300 | { |
7967e09e | 15301 | if (modrm.mod == 3) |
2da11e11 AM |
15302 | OP_EM (bytemode, sizeflag); |
15303 | else | |
6608db57 | 15304 | BadOp (); |
252b5132 RH |
15305 | } |
15306 | ||
992aaec9 | 15307 | static void |
26ca5450 | 15308 | OP_XS (int bytemode, int sizeflag) |
992aaec9 | 15309 | { |
7967e09e | 15310 | if (modrm.mod == 3) |
992aaec9 AM |
15311 | OP_EX (bytemode, sizeflag); |
15312 | else | |
6608db57 | 15313 | BadOp (); |
992aaec9 AM |
15314 | } |
15315 | ||
cc0ec051 AM |
15316 | static void |
15317 | OP_M (int bytemode, int sizeflag) | |
15318 | { | |
7967e09e | 15319 | if (modrm.mod == 3) |
75413a22 L |
15320 | /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */ |
15321 | BadOp (); | |
cc0ec051 AM |
15322 | else |
15323 | OP_E (bytemode, sizeflag); | |
15324 | } | |
15325 | ||
15326 | static void | |
15327 | OP_0f07 (int bytemode, int sizeflag) | |
15328 | { | |
7967e09e | 15329 | if (modrm.mod != 3 || modrm.rm != 0) |
cc0ec051 AM |
15330 | BadOp (); |
15331 | else | |
15332 | OP_E (bytemode, sizeflag); | |
15333 | } | |
15334 | ||
46e883c5 | 15335 | /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in |
246c51aa | 15336 | 32bit mode and "xchg %rax,%rax" in 64bit mode. */ |
46e883c5 | 15337 | |
cc0ec051 | 15338 | static void |
46e883c5 | 15339 | NOP_Fixup1 (int bytemode, int sizeflag) |
cc0ec051 | 15340 | { |
8b38ad71 L |
15341 | if ((prefixes & PREFIX_DATA) != 0 |
15342 | || (rex != 0 | |
15343 | && rex != 0x48 | |
15344 | && address_mode == mode_64bit)) | |
46e883c5 L |
15345 | OP_REG (bytemode, sizeflag); |
15346 | else | |
15347 | strcpy (obuf, "nop"); | |
15348 | } | |
15349 | ||
15350 | static void | |
15351 | NOP_Fixup2 (int bytemode, int sizeflag) | |
15352 | { | |
8b38ad71 L |
15353 | if ((prefixes & PREFIX_DATA) != 0 |
15354 | || (rex != 0 | |
15355 | && rex != 0x48 | |
15356 | && address_mode == mode_64bit)) | |
46e883c5 | 15357 | OP_IMREG (bytemode, sizeflag); |
cc0ec051 AM |
15358 | } |
15359 | ||
84037f8c | 15360 | static const char *const Suffix3DNow[] = { |
252b5132 RH |
15361 | /* 00 */ NULL, NULL, NULL, NULL, |
15362 | /* 04 */ NULL, NULL, NULL, NULL, | |
15363 | /* 08 */ NULL, NULL, NULL, NULL, | |
9e525108 | 15364 | /* 0C */ "pi2fw", "pi2fd", NULL, NULL, |
252b5132 RH |
15365 | /* 10 */ NULL, NULL, NULL, NULL, |
15366 | /* 14 */ NULL, NULL, NULL, NULL, | |
15367 | /* 18 */ NULL, NULL, NULL, NULL, | |
9e525108 | 15368 | /* 1C */ "pf2iw", "pf2id", NULL, NULL, |
252b5132 RH |
15369 | /* 20 */ NULL, NULL, NULL, NULL, |
15370 | /* 24 */ NULL, NULL, NULL, NULL, | |
15371 | /* 28 */ NULL, NULL, NULL, NULL, | |
15372 | /* 2C */ NULL, NULL, NULL, NULL, | |
15373 | /* 30 */ NULL, NULL, NULL, NULL, | |
15374 | /* 34 */ NULL, NULL, NULL, NULL, | |
15375 | /* 38 */ NULL, NULL, NULL, NULL, | |
15376 | /* 3C */ NULL, NULL, NULL, NULL, | |
15377 | /* 40 */ NULL, NULL, NULL, NULL, | |
15378 | /* 44 */ NULL, NULL, NULL, NULL, | |
15379 | /* 48 */ NULL, NULL, NULL, NULL, | |
15380 | /* 4C */ NULL, NULL, NULL, NULL, | |
15381 | /* 50 */ NULL, NULL, NULL, NULL, | |
15382 | /* 54 */ NULL, NULL, NULL, NULL, | |
15383 | /* 58 */ NULL, NULL, NULL, NULL, | |
15384 | /* 5C */ NULL, NULL, NULL, NULL, | |
15385 | /* 60 */ NULL, NULL, NULL, NULL, | |
15386 | /* 64 */ NULL, NULL, NULL, NULL, | |
15387 | /* 68 */ NULL, NULL, NULL, NULL, | |
15388 | /* 6C */ NULL, NULL, NULL, NULL, | |
15389 | /* 70 */ NULL, NULL, NULL, NULL, | |
15390 | /* 74 */ NULL, NULL, NULL, NULL, | |
15391 | /* 78 */ NULL, NULL, NULL, NULL, | |
15392 | /* 7C */ NULL, NULL, NULL, NULL, | |
15393 | /* 80 */ NULL, NULL, NULL, NULL, | |
15394 | /* 84 */ NULL, NULL, NULL, NULL, | |
9e525108 AM |
15395 | /* 88 */ NULL, NULL, "pfnacc", NULL, |
15396 | /* 8C */ NULL, NULL, "pfpnacc", NULL, | |
252b5132 RH |
15397 | /* 90 */ "pfcmpge", NULL, NULL, NULL, |
15398 | /* 94 */ "pfmin", NULL, "pfrcp", "pfrsqrt", | |
15399 | /* 98 */ NULL, NULL, "pfsub", NULL, | |
15400 | /* 9C */ NULL, NULL, "pfadd", NULL, | |
15401 | /* A0 */ "pfcmpgt", NULL, NULL, NULL, | |
15402 | /* A4 */ "pfmax", NULL, "pfrcpit1", "pfrsqit1", | |
15403 | /* A8 */ NULL, NULL, "pfsubr", NULL, | |
15404 | /* AC */ NULL, NULL, "pfacc", NULL, | |
15405 | /* B0 */ "pfcmpeq", NULL, NULL, NULL, | |
9beff690 | 15406 | /* B4 */ "pfmul", NULL, "pfrcpit2", "pmulhrw", |
9e525108 | 15407 | /* B8 */ NULL, NULL, NULL, "pswapd", |
252b5132 RH |
15408 | /* BC */ NULL, NULL, NULL, "pavgusb", |
15409 | /* C0 */ NULL, NULL, NULL, NULL, | |
15410 | /* C4 */ NULL, NULL, NULL, NULL, | |
15411 | /* C8 */ NULL, NULL, NULL, NULL, | |
15412 | /* CC */ NULL, NULL, NULL, NULL, | |
15413 | /* D0 */ NULL, NULL, NULL, NULL, | |
15414 | /* D4 */ NULL, NULL, NULL, NULL, | |
15415 | /* D8 */ NULL, NULL, NULL, NULL, | |
15416 | /* DC */ NULL, NULL, NULL, NULL, | |
15417 | /* E0 */ NULL, NULL, NULL, NULL, | |
15418 | /* E4 */ NULL, NULL, NULL, NULL, | |
15419 | /* E8 */ NULL, NULL, NULL, NULL, | |
15420 | /* EC */ NULL, NULL, NULL, NULL, | |
15421 | /* F0 */ NULL, NULL, NULL, NULL, | |
15422 | /* F4 */ NULL, NULL, NULL, NULL, | |
15423 | /* F8 */ NULL, NULL, NULL, NULL, | |
15424 | /* FC */ NULL, NULL, NULL, NULL, | |
15425 | }; | |
15426 | ||
15427 | static void | |
26ca5450 | 15428 | OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 RH |
15429 | { |
15430 | const char *mnemonic; | |
15431 | ||
15432 | FETCH_DATA (the_info, codep + 1); | |
15433 | /* AMD 3DNow! instructions are specified by an opcode suffix in the | |
15434 | place where an 8-bit immediate would normally go. ie. the last | |
15435 | byte of the instruction. */ | |
ea397f5b | 15436 | obufp = mnemonicendp; |
c608c12e | 15437 | mnemonic = Suffix3DNow[*codep++ & 0xff]; |
252b5132 | 15438 | if (mnemonic) |
2da11e11 | 15439 | oappend (mnemonic); |
252b5132 RH |
15440 | else |
15441 | { | |
15442 | /* Since a variable sized modrm/sib chunk is between the start | |
15443 | of the opcode (0x0f0f) and the opcode suffix, we need to do | |
15444 | all the modrm processing first, and don't know until now that | |
15445 | we have a bad opcode. This necessitates some cleaning up. */ | |
ce518a5f L |
15446 | op_out[0][0] = '\0'; |
15447 | op_out[1][0] = '\0'; | |
6608db57 | 15448 | BadOp (); |
252b5132 | 15449 | } |
ea397f5b | 15450 | mnemonicendp = obufp; |
252b5132 | 15451 | } |
c608c12e | 15452 | |
ea397f5b L |
15453 | static struct op simd_cmp_op[] = |
15454 | { | |
15455 | { STRING_COMMA_LEN ("eq") }, | |
15456 | { STRING_COMMA_LEN ("lt") }, | |
15457 | { STRING_COMMA_LEN ("le") }, | |
15458 | { STRING_COMMA_LEN ("unord") }, | |
15459 | { STRING_COMMA_LEN ("neq") }, | |
15460 | { STRING_COMMA_LEN ("nlt") }, | |
15461 | { STRING_COMMA_LEN ("nle") }, | |
15462 | { STRING_COMMA_LEN ("ord") } | |
c608c12e AM |
15463 | }; |
15464 | ||
15465 | static void | |
ad19981d | 15466 | CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
c608c12e AM |
15467 | { |
15468 | unsigned int cmp_type; | |
15469 | ||
15470 | FETCH_DATA (the_info, codep + 1); | |
15471 | cmp_type = *codep++ & 0xff; | |
c0f3af97 | 15472 | if (cmp_type < ARRAY_SIZE (simd_cmp_op)) |
c608c12e | 15473 | { |
ad19981d | 15474 | char suffix [3]; |
ea397f5b | 15475 | char *p = mnemonicendp - 2; |
ad19981d L |
15476 | suffix[0] = p[0]; |
15477 | suffix[1] = p[1]; | |
15478 | suffix[2] = '\0'; | |
ea397f5b L |
15479 | sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix); |
15480 | mnemonicendp += simd_cmp_op[cmp_type].len; | |
c608c12e AM |
15481 | } |
15482 | else | |
15483 | { | |
ad19981d L |
15484 | /* We have a reserved extension byte. Output it directly. */ |
15485 | scratchbuf[0] = '$'; | |
15486 | print_operand_value (scratchbuf + 1, 1, cmp_type); | |
9ce09ba2 | 15487 | oappend_maybe_intel (scratchbuf); |
ad19981d | 15488 | scratchbuf[0] = '\0'; |
c608c12e AM |
15489 | } |
15490 | } | |
15491 | ||
9916071f | 15492 | static void |
7abb8d81 | 15493 | OP_Mwait (int bytemode, int sizeflag ATTRIBUTE_UNUSED) |
9916071f | 15494 | { |
7abb8d81 | 15495 | /* mwait %eax,%ecx / mwaitx %eax,%ecx,%ebx */ |
b844680a L |
15496 | if (!intel_syntax) |
15497 | { | |
081e283f JB |
15498 | strcpy (op_out[0], names32[0]); |
15499 | strcpy (op_out[1], names32[1]); | |
7abb8d81 | 15500 | if (bytemode == eBX_reg) |
081e283f | 15501 | strcpy (op_out[2], names32[3]); |
b844680a L |
15502 | two_source_ops = 1; |
15503 | } | |
15504 | /* Skip mod/rm byte. */ | |
15505 | MODRM_CHECK; | |
15506 | codep++; | |
15507 | } | |
15508 | ||
15509 | static void | |
15510 | OP_Monitor (int bytemode ATTRIBUTE_UNUSED, | |
15511 | int sizeflag ATTRIBUTE_UNUSED) | |
ca164297 | 15512 | { |
081e283f | 15513 | /* monitor %{e,r,}ax,%ecx,%edx" */ |
b844680a | 15514 | if (!intel_syntax) |
ca164297 | 15515 | { |
cb712a9e L |
15516 | const char **names = (address_mode == mode_64bit |
15517 | ? names64 : names32); | |
1d9f512f | 15518 | |
081e283f | 15519 | if (prefixes & PREFIX_ADDR) |
ca164297 | 15520 | { |
b844680a | 15521 | /* Remove "addr16/addr32". */ |
f16cd0d5 | 15522 | all_prefixes[last_addr_prefix] = 0; |
081e283f JB |
15523 | names = (address_mode != mode_32bit |
15524 | ? names32 : names16); | |
b844680a | 15525 | used_prefixes |= PREFIX_ADDR; |
ca164297 | 15526 | } |
081e283f JB |
15527 | else if (address_mode == mode_16bit) |
15528 | names = names16; | |
15529 | strcpy (op_out[0], names[0]); | |
15530 | strcpy (op_out[1], names32[1]); | |
15531 | strcpy (op_out[2], names32[2]); | |
b844680a | 15532 | two_source_ops = 1; |
ca164297 | 15533 | } |
b844680a L |
15534 | /* Skip mod/rm byte. */ |
15535 | MODRM_CHECK; | |
15536 | codep++; | |
30123838 JB |
15537 | } |
15538 | ||
6608db57 KH |
15539 | static void |
15540 | BadOp (void) | |
2da11e11 | 15541 | { |
6608db57 KH |
15542 | /* Throw away prefixes and 1st. opcode byte. */ |
15543 | codep = insn_codep + 1; | |
2da11e11 AM |
15544 | oappend ("(bad)"); |
15545 | } | |
4cc91dba | 15546 | |
35c52694 L |
15547 | static void |
15548 | REP_Fixup (int bytemode, int sizeflag) | |
15549 | { | |
15550 | /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs, | |
15551 | lods and stos. */ | |
35c52694 | 15552 | if (prefixes & PREFIX_REPZ) |
f16cd0d5 | 15553 | all_prefixes[last_repz_prefix] = REP_PREFIX; |
35c52694 L |
15554 | |
15555 | switch (bytemode) | |
15556 | { | |
15557 | case al_reg: | |
15558 | case eAX_reg: | |
15559 | case indir_dx_reg: | |
15560 | OP_IMREG (bytemode, sizeflag); | |
15561 | break; | |
15562 | case eDI_reg: | |
15563 | OP_ESreg (bytemode, sizeflag); | |
15564 | break; | |
15565 | case eSI_reg: | |
15566 | OP_DSreg (bytemode, sizeflag); | |
15567 | break; | |
15568 | default: | |
15569 | abort (); | |
15570 | break; | |
15571 | } | |
15572 | } | |
f5804c90 | 15573 | |
d835a58b JB |
15574 | static void |
15575 | SEP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
15576 | { | |
15577 | if ( isa64 != amd64 ) | |
15578 | return; | |
15579 | ||
15580 | obufp = obuf; | |
15581 | BadOp (); | |
15582 | mnemonicendp = obufp; | |
15583 | ++codep; | |
15584 | } | |
15585 | ||
7e8b059b L |
15586 | /* For BND-prefixed instructions 0xF2 prefix should be displayed as |
15587 | "bnd". */ | |
15588 | ||
15589 | static void | |
15590 | BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
15591 | { | |
15592 | if (prefixes & PREFIX_REPNZ) | |
15593 | all_prefixes[last_repnz_prefix] = BND_PREFIX; | |
15594 | } | |
15595 | ||
04ef582a L |
15596 | /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as |
15597 | "notrack". */ | |
15598 | ||
15599 | static void | |
15600 | NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED, | |
15601 | int sizeflag ATTRIBUTE_UNUSED) | |
15602 | { | |
9fef80d6 | 15603 | if (active_seg_prefix == PREFIX_DS |
04ef582a L |
15604 | && (address_mode != mode_64bit || last_data_prefix < 0)) |
15605 | { | |
4e9ac44a | 15606 | /* NOTRACK prefix is only valid on indirect branch instructions. |
9fef80d6 | 15607 | NB: DATA prefix is unsupported for Intel64. */ |
04ef582a L |
15608 | active_seg_prefix = 0; |
15609 | all_prefixes[last_seg_prefix] = NOTRACK_PREFIX; | |
15610 | } | |
15611 | } | |
15612 | ||
42164a71 L |
15613 | /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as |
15614 | "xacquire"/"xrelease" for memory operand if there is a LOCK prefix. | |
15615 | */ | |
15616 | ||
15617 | static void | |
15618 | HLE_Fixup1 (int bytemode, int sizeflag) | |
15619 | { | |
15620 | if (modrm.mod != 3 | |
15621 | && (prefixes & PREFIX_LOCK) != 0) | |
15622 | { | |
15623 | if (prefixes & PREFIX_REPZ) | |
15624 | all_prefixes[last_repz_prefix] = XRELEASE_PREFIX; | |
15625 | if (prefixes & PREFIX_REPNZ) | |
15626 | all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX; | |
15627 | } | |
15628 | ||
15629 | OP_E (bytemode, sizeflag); | |
15630 | } | |
15631 | ||
15632 | /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as | |
15633 | "xacquire"/"xrelease" for memory operand. No check for LOCK prefix. | |
15634 | */ | |
15635 | ||
15636 | static void | |
15637 | HLE_Fixup2 (int bytemode, int sizeflag) | |
15638 | { | |
15639 | if (modrm.mod != 3) | |
15640 | { | |
15641 | if (prefixes & PREFIX_REPZ) | |
15642 | all_prefixes[last_repz_prefix] = XRELEASE_PREFIX; | |
15643 | if (prefixes & PREFIX_REPNZ) | |
15644 | all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX; | |
15645 | } | |
15646 | ||
15647 | OP_E (bytemode, sizeflag); | |
15648 | } | |
15649 | ||
15650 | /* Similar to OP_E. But the 0xf3 prefixes should be displayed as | |
15651 | "xrelease" for memory operand. No check for LOCK prefix. */ | |
15652 | ||
15653 | static void | |
15654 | HLE_Fixup3 (int bytemode, int sizeflag) | |
15655 | { | |
15656 | if (modrm.mod != 3 | |
15657 | && last_repz_prefix > last_repnz_prefix | |
15658 | && (prefixes & PREFIX_REPZ) != 0) | |
15659 | all_prefixes[last_repz_prefix] = XRELEASE_PREFIX; | |
15660 | ||
15661 | OP_E (bytemode, sizeflag); | |
15662 | } | |
15663 | ||
f5804c90 L |
15664 | static void |
15665 | CMPXCHG8B_Fixup (int bytemode, int sizeflag) | |
15666 | { | |
161a04f6 L |
15667 | USED_REX (REX_W); |
15668 | if (rex & REX_W) | |
f5804c90 L |
15669 | { |
15670 | /* Change cmpxchg8b to cmpxchg16b. */ | |
ea397f5b L |
15671 | char *p = mnemonicendp - 2; |
15672 | mnemonicendp = stpcpy (p, "16b"); | |
fb9c77c7 | 15673 | bytemode = o_mode; |
f5804c90 | 15674 | } |
42164a71 L |
15675 | else if ((prefixes & PREFIX_LOCK) != 0) |
15676 | { | |
15677 | if (prefixes & PREFIX_REPZ) | |
15678 | all_prefixes[last_repz_prefix] = XRELEASE_PREFIX; | |
15679 | if (prefixes & PREFIX_REPNZ) | |
15680 | all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX; | |
15681 | } | |
15682 | ||
f5804c90 L |
15683 | OP_M (bytemode, sizeflag); |
15684 | } | |
42903f7f L |
15685 | |
15686 | static void | |
15687 | XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED) | |
15688 | { | |
b9733481 L |
15689 | const char **names; |
15690 | ||
c0f3af97 L |
15691 | if (need_vex) |
15692 | { | |
15693 | switch (vex.length) | |
15694 | { | |
15695 | case 128: | |
b9733481 | 15696 | names = names_xmm; |
c0f3af97 L |
15697 | break; |
15698 | case 256: | |
b9733481 | 15699 | names = names_ymm; |
c0f3af97 L |
15700 | break; |
15701 | default: | |
15702 | abort (); | |
15703 | } | |
15704 | } | |
15705 | else | |
b9733481 L |
15706 | names = names_xmm; |
15707 | oappend (names[reg]); | |
42903f7f | 15708 | } |
381d071f L |
15709 | |
15710 | static void | |
15711 | CRC32_Fixup (int bytemode, int sizeflag) | |
15712 | { | |
15713 | /* Add proper suffix to "crc32". */ | |
ea397f5b | 15714 | char *p = mnemonicendp; |
381d071f L |
15715 | |
15716 | switch (bytemode) | |
15717 | { | |
15718 | case b_mode: | |
20592a94 | 15719 | if (intel_syntax) |
ea397f5b | 15720 | goto skip; |
20592a94 | 15721 | |
381d071f L |
15722 | *p++ = 'b'; |
15723 | break; | |
15724 | case v_mode: | |
20592a94 | 15725 | if (intel_syntax) |
ea397f5b | 15726 | goto skip; |
20592a94 | 15727 | |
381d071f L |
15728 | USED_REX (REX_W); |
15729 | if (rex & REX_W) | |
15730 | *p++ = 'q'; | |
7bb15c6f | 15731 | else |
f16cd0d5 L |
15732 | { |
15733 | if (sizeflag & DFLAG) | |
15734 | *p++ = 'l'; | |
15735 | else | |
15736 | *p++ = 'w'; | |
15737 | used_prefixes |= (prefixes & PREFIX_DATA); | |
15738 | } | |
381d071f L |
15739 | break; |
15740 | default: | |
15741 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
15742 | break; | |
15743 | } | |
ea397f5b | 15744 | mnemonicendp = p; |
381d071f L |
15745 | *p = '\0'; |
15746 | ||
dc1e8a47 | 15747 | skip: |
381d071f L |
15748 | if (modrm.mod == 3) |
15749 | { | |
15750 | int add; | |
15751 | ||
15752 | /* Skip mod/rm byte. */ | |
15753 | MODRM_CHECK; | |
15754 | codep++; | |
15755 | ||
15756 | USED_REX (REX_B); | |
15757 | add = (rex & REX_B) ? 8 : 0; | |
15758 | if (bytemode == b_mode) | |
15759 | { | |
15760 | USED_REX (0); | |
15761 | if (rex) | |
15762 | oappend (names8rex[modrm.rm + add]); | |
15763 | else | |
15764 | oappend (names8[modrm.rm + add]); | |
15765 | } | |
15766 | else | |
15767 | { | |
15768 | USED_REX (REX_W); | |
15769 | if (rex & REX_W) | |
15770 | oappend (names64[modrm.rm + add]); | |
15771 | else if ((prefixes & PREFIX_DATA)) | |
15772 | oappend (names16[modrm.rm + add]); | |
15773 | else | |
15774 | oappend (names32[modrm.rm + add]); | |
15775 | } | |
15776 | } | |
15777 | else | |
9344ff29 | 15778 | OP_E (bytemode, sizeflag); |
381d071f | 15779 | } |
85f10a01 | 15780 | |
eacc9c89 L |
15781 | static void |
15782 | FXSAVE_Fixup (int bytemode, int sizeflag) | |
15783 | { | |
15784 | /* Add proper suffix to "fxsave" and "fxrstor". */ | |
15785 | USED_REX (REX_W); | |
15786 | if (rex & REX_W) | |
15787 | { | |
15788 | char *p = mnemonicendp; | |
15789 | *p++ = '6'; | |
15790 | *p++ = '4'; | |
15791 | *p = '\0'; | |
15792 | mnemonicendp = p; | |
15793 | } | |
15794 | OP_M (bytemode, sizeflag); | |
15795 | } | |
15796 | ||
15c7c1d8 JB |
15797 | static void |
15798 | PCMPESTR_Fixup (int bytemode, int sizeflag) | |
15799 | { | |
15800 | /* Add proper suffix to "{,v}pcmpestr{i,m}". */ | |
15801 | if (!intel_syntax) | |
15802 | { | |
15803 | char *p = mnemonicendp; | |
15804 | ||
15805 | USED_REX (REX_W); | |
15806 | if (rex & REX_W) | |
15807 | *p++ = 'q'; | |
15808 | else if (sizeflag & SUFFIX_ALWAYS) | |
15809 | *p++ = 'l'; | |
15810 | ||
15811 | *p = '\0'; | |
15812 | mnemonicendp = p; | |
15813 | } | |
15814 | ||
15815 | OP_EX (bytemode, sizeflag); | |
15816 | } | |
15817 | ||
c0f3af97 L |
15818 | /* Display the destination register operand for instructions with |
15819 | VEX. */ | |
15820 | ||
15821 | static void | |
15822 | OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED) | |
15823 | { | |
539f890d | 15824 | int reg; |
b9733481 L |
15825 | const char **names; |
15826 | ||
c0f3af97 L |
15827 | if (!need_vex) |
15828 | abort (); | |
15829 | ||
15830 | if (!need_vex_reg) | |
15831 | return; | |
15832 | ||
539f890d | 15833 | reg = vex.register_specifier; |
63c6fc6c | 15834 | vex.register_specifier = 0; |
5f847646 JB |
15835 | if (address_mode != mode_64bit) |
15836 | reg &= 7; | |
15837 | else if (vex.evex && !vex.v) | |
15838 | reg += 16; | |
43234a1e | 15839 | |
539f890d L |
15840 | if (bytemode == vex_scalar_mode) |
15841 | { | |
15842 | oappend (names_xmm[reg]); | |
15843 | return; | |
15844 | } | |
15845 | ||
c0f3af97 L |
15846 | switch (vex.length) |
15847 | { | |
15848 | case 128: | |
15849 | switch (bytemode) | |
15850 | { | |
15851 | case vex_mode: | |
15852 | case vex128_mode: | |
6c30d220 | 15853 | case vex_vsib_q_w_dq_mode: |
5fc35d96 | 15854 | case vex_vsib_q_w_d_mode: |
cb21baef L |
15855 | names = names_xmm; |
15856 | break; | |
15857 | case dq_mode: | |
390a6789 | 15858 | if (rex & REX_W) |
cb21baef L |
15859 | names = names64; |
15860 | else | |
15861 | names = names32; | |
c0f3af97 | 15862 | break; |
1ba585e8 | 15863 | case mask_bd_mode: |
43234a1e | 15864 | case mask_mode: |
9889cbb1 L |
15865 | if (reg > 0x7) |
15866 | { | |
15867 | oappend ("(bad)"); | |
15868 | return; | |
15869 | } | |
43234a1e L |
15870 | names = names_mask; |
15871 | break; | |
c0f3af97 L |
15872 | default: |
15873 | abort (); | |
15874 | return; | |
15875 | } | |
c0f3af97 L |
15876 | break; |
15877 | case 256: | |
15878 | switch (bytemode) | |
15879 | { | |
15880 | case vex_mode: | |
15881 | case vex256_mode: | |
6c30d220 L |
15882 | names = names_ymm; |
15883 | break; | |
15884 | case vex_vsib_q_w_dq_mode: | |
5fc35d96 | 15885 | case vex_vsib_q_w_d_mode: |
6c30d220 | 15886 | names = vex.w ? names_ymm : names_xmm; |
c0f3af97 | 15887 | break; |
1ba585e8 | 15888 | case mask_bd_mode: |
43234a1e | 15889 | case mask_mode: |
9889cbb1 L |
15890 | if (reg > 0x7) |
15891 | { | |
15892 | oappend ("(bad)"); | |
15893 | return; | |
15894 | } | |
43234a1e L |
15895 | names = names_mask; |
15896 | break; | |
c0f3af97 | 15897 | default: |
a37a2806 NC |
15898 | /* See PR binutils/20893 for a reproducer. */ |
15899 | oappend ("(bad)"); | |
c0f3af97 L |
15900 | return; |
15901 | } | |
c0f3af97 | 15902 | break; |
43234a1e L |
15903 | case 512: |
15904 | names = names_zmm; | |
15905 | break; | |
c0f3af97 L |
15906 | default: |
15907 | abort (); | |
15908 | break; | |
15909 | } | |
539f890d | 15910 | oappend (names[reg]); |
c0f3af97 L |
15911 | } |
15912 | ||
922d8de8 DR |
15913 | /* Get the VEX immediate byte without moving codep. */ |
15914 | ||
15915 | static unsigned char | |
ccc5981b | 15916 | get_vex_imm8 (int sizeflag, int opnum) |
922d8de8 DR |
15917 | { |
15918 | int bytes_before_imm = 0; | |
15919 | ||
922d8de8 DR |
15920 | if (modrm.mod != 3) |
15921 | { | |
15922 | /* There are SIB/displacement bytes. */ | |
15923 | if ((sizeflag & AFLAG) || address_mode == mode_64bit) | |
6c067bbb | 15924 | { |
922d8de8 | 15925 | /* 32/64 bit address mode */ |
6c067bbb | 15926 | int base = modrm.rm; |
922d8de8 DR |
15927 | |
15928 | /* Check SIB byte. */ | |
6c067bbb RM |
15929 | if (base == 4) |
15930 | { | |
15931 | FETCH_DATA (the_info, codep + 1); | |
15932 | base = *codep & 7; | |
15933 | /* When decoding the third source, don't increase | |
15934 | bytes_before_imm as this has already been incremented | |
15935 | by one in OP_E_memory while decoding the second | |
15936 | source operand. */ | |
15937 | if (opnum == 0) | |
15938 | bytes_before_imm++; | |
15939 | } | |
15940 | ||
15941 | /* Don't increase bytes_before_imm when decoding the third source, | |
15942 | it has already been incremented by OP_E_memory while decoding | |
15943 | the second source operand. */ | |
15944 | if (opnum == 0) | |
15945 | { | |
15946 | switch (modrm.mod) | |
15947 | { | |
15948 | case 0: | |
15949 | /* When modrm.rm == 5 or modrm.rm == 4 and base in | |
15950 | SIB == 5, there is a 4 byte displacement. */ | |
15951 | if (base != 5) | |
15952 | /* No displacement. */ | |
15953 | break; | |
1a0670f3 | 15954 | /* Fall through. */ |
6c067bbb RM |
15955 | case 2: |
15956 | /* 4 byte displacement. */ | |
15957 | bytes_before_imm += 4; | |
15958 | break; | |
15959 | case 1: | |
15960 | /* 1 byte displacement. */ | |
15961 | bytes_before_imm++; | |
15962 | break; | |
15963 | } | |
15964 | } | |
15965 | } | |
922d8de8 | 15966 | else |
02e647f9 SP |
15967 | { |
15968 | /* 16 bit address mode */ | |
6c067bbb RM |
15969 | /* Don't increase bytes_before_imm when decoding the third source, |
15970 | it has already been incremented by OP_E_memory while decoding | |
15971 | the second source operand. */ | |
15972 | if (opnum == 0) | |
15973 | { | |
02e647f9 SP |
15974 | switch (modrm.mod) |
15975 | { | |
15976 | case 0: | |
15977 | /* When modrm.rm == 6, there is a 2 byte displacement. */ | |
15978 | if (modrm.rm != 6) | |
15979 | /* No displacement. */ | |
15980 | break; | |
1a0670f3 | 15981 | /* Fall through. */ |
02e647f9 SP |
15982 | case 2: |
15983 | /* 2 byte displacement. */ | |
15984 | bytes_before_imm += 2; | |
15985 | break; | |
15986 | case 1: | |
15987 | /* 1 byte displacement: when decoding the third source, | |
15988 | don't increase bytes_before_imm as this has already | |
15989 | been incremented by one in OP_E_memory while decoding | |
15990 | the second source operand. */ | |
15991 | if (opnum == 0) | |
15992 | bytes_before_imm++; | |
ccc5981b | 15993 | |
02e647f9 SP |
15994 | break; |
15995 | } | |
922d8de8 DR |
15996 | } |
15997 | } | |
15998 | } | |
15999 | ||
16000 | FETCH_DATA (the_info, codep + bytes_before_imm + 1); | |
16001 | return codep [bytes_before_imm]; | |
16002 | } | |
16003 | ||
16004 | static void | |
16005 | OP_EX_VexReg (int bytemode, int sizeflag, int reg) | |
16006 | { | |
b9733481 L |
16007 | const char **names; |
16008 | ||
922d8de8 DR |
16009 | if (reg == -1 && modrm.mod != 3) |
16010 | { | |
16011 | OP_E_memory (bytemode, sizeflag); | |
16012 | return; | |
16013 | } | |
16014 | else | |
16015 | { | |
16016 | if (reg == -1) | |
16017 | { | |
16018 | reg = modrm.rm; | |
16019 | USED_REX (REX_B); | |
16020 | if (rex & REX_B) | |
16021 | reg += 8; | |
16022 | } | |
5f847646 JB |
16023 | if (address_mode != mode_64bit) |
16024 | reg &= 7; | |
922d8de8 DR |
16025 | } |
16026 | ||
16027 | switch (vex.length) | |
16028 | { | |
16029 | case 128: | |
b9733481 | 16030 | names = names_xmm; |
922d8de8 DR |
16031 | break; |
16032 | case 256: | |
b9733481 | 16033 | names = names_ymm; |
922d8de8 DR |
16034 | break; |
16035 | default: | |
16036 | abort (); | |
16037 | } | |
b9733481 | 16038 | oappend (names[reg]); |
922d8de8 DR |
16039 | } |
16040 | ||
a683cc34 SP |
16041 | static void |
16042 | OP_EX_VexImmW (int bytemode, int sizeflag) | |
16043 | { | |
16044 | int reg = -1; | |
16045 | static unsigned char vex_imm8; | |
16046 | ||
16047 | if (vex_w_done == 0) | |
16048 | { | |
16049 | vex_w_done = 1; | |
16050 | ||
16051 | /* Skip mod/rm byte. */ | |
16052 | MODRM_CHECK; | |
16053 | codep++; | |
16054 | ||
16055 | vex_imm8 = get_vex_imm8 (sizeflag, 0); | |
16056 | ||
16057 | if (vex.w) | |
16058 | reg = vex_imm8 >> 4; | |
16059 | ||
16060 | OP_EX_VexReg (bytemode, sizeflag, reg); | |
16061 | } | |
16062 | else if (vex_w_done == 1) | |
16063 | { | |
16064 | vex_w_done = 2; | |
16065 | ||
16066 | if (!vex.w) | |
16067 | reg = vex_imm8 >> 4; | |
16068 | ||
16069 | OP_EX_VexReg (bytemode, sizeflag, reg); | |
16070 | } | |
16071 | else | |
16072 | { | |
16073 | /* Output the imm8 directly. */ | |
16074 | scratchbuf[0] = '$'; | |
16075 | print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf); | |
9ce09ba2 | 16076 | oappend_maybe_intel (scratchbuf); |
a683cc34 SP |
16077 | scratchbuf[0] = '\0'; |
16078 | codep++; | |
16079 | } | |
16080 | } | |
16081 | ||
5dd85c99 SP |
16082 | static void |
16083 | OP_Vex_2src (int bytemode, int sizeflag) | |
16084 | { | |
16085 | if (modrm.mod == 3) | |
16086 | { | |
b9733481 | 16087 | int reg = modrm.rm; |
5dd85c99 | 16088 | USED_REX (REX_B); |
b9733481 L |
16089 | if (rex & REX_B) |
16090 | reg += 8; | |
16091 | oappend (names_xmm[reg]); | |
5dd85c99 SP |
16092 | } |
16093 | else | |
16094 | { | |
16095 | if (intel_syntax | |
16096 | && (bytemode == v_mode || bytemode == v_swap_mode)) | |
16097 | { | |
16098 | bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode; | |
16099 | used_prefixes |= (prefixes & PREFIX_DATA); | |
16100 | } | |
16101 | OP_E (bytemode, sizeflag); | |
16102 | } | |
16103 | } | |
16104 | ||
16105 | static void | |
16106 | OP_Vex_2src_1 (int bytemode, int sizeflag) | |
16107 | { | |
16108 | if (modrm.mod == 3) | |
16109 | { | |
16110 | /* Skip mod/rm byte. */ | |
16111 | MODRM_CHECK; | |
16112 | codep++; | |
16113 | } | |
16114 | ||
16115 | if (vex.w) | |
5f847646 JB |
16116 | { |
16117 | unsigned int reg = vex.register_specifier; | |
63c6fc6c | 16118 | vex.register_specifier = 0; |
5f847646 JB |
16119 | |
16120 | if (address_mode != mode_64bit) | |
16121 | reg &= 7; | |
16122 | oappend (names_xmm[reg]); | |
16123 | } | |
5dd85c99 SP |
16124 | else |
16125 | OP_Vex_2src (bytemode, sizeflag); | |
16126 | } | |
16127 | ||
16128 | static void | |
16129 | OP_Vex_2src_2 (int bytemode, int sizeflag) | |
16130 | { | |
16131 | if (vex.w) | |
16132 | OP_Vex_2src (bytemode, sizeflag); | |
16133 | else | |
5f847646 JB |
16134 | { |
16135 | unsigned int reg = vex.register_specifier; | |
63c6fc6c | 16136 | vex.register_specifier = 0; |
5f847646 JB |
16137 | |
16138 | if (address_mode != mode_64bit) | |
16139 | reg &= 7; | |
16140 | oappend (names_xmm[reg]); | |
16141 | } | |
5dd85c99 SP |
16142 | } |
16143 | ||
922d8de8 DR |
16144 | static void |
16145 | OP_EX_VexW (int bytemode, int sizeflag) | |
16146 | { | |
16147 | int reg = -1; | |
16148 | ||
16149 | if (!vex_w_done) | |
16150 | { | |
41effecb SP |
16151 | /* Skip mod/rm byte. */ |
16152 | MODRM_CHECK; | |
16153 | codep++; | |
16154 | ||
922d8de8 | 16155 | if (vex.w) |
ccc5981b | 16156 | reg = get_vex_imm8 (sizeflag, 0) >> 4; |
922d8de8 DR |
16157 | } |
16158 | else | |
16159 | { | |
16160 | if (!vex.w) | |
ccc5981b | 16161 | reg = get_vex_imm8 (sizeflag, 1) >> 4; |
922d8de8 DR |
16162 | } |
16163 | ||
16164 | OP_EX_VexReg (bytemode, sizeflag, reg); | |
922d8de8 | 16165 | |
3a2430e0 JB |
16166 | if (vex_w_done) |
16167 | codep++; | |
16168 | vex_w_done = 1; | |
922d8de8 DR |
16169 | } |
16170 | ||
c0f3af97 L |
16171 | static void |
16172 | OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED) | |
16173 | { | |
16174 | int reg; | |
b9733481 L |
16175 | const char **names; |
16176 | ||
c0f3af97 L |
16177 | FETCH_DATA (the_info, codep + 1); |
16178 | reg = *codep++; | |
16179 | ||
16180 | if (bytemode != x_mode) | |
16181 | abort (); | |
16182 | ||
c0f3af97 | 16183 | reg >>= 4; |
5f847646 JB |
16184 | if (address_mode != mode_64bit) |
16185 | reg &= 7; | |
dae39acc | 16186 | |
c0f3af97 L |
16187 | switch (vex.length) |
16188 | { | |
16189 | case 128: | |
b9733481 | 16190 | names = names_xmm; |
c0f3af97 L |
16191 | break; |
16192 | case 256: | |
b9733481 | 16193 | names = names_ymm; |
c0f3af97 L |
16194 | break; |
16195 | default: | |
16196 | abort (); | |
16197 | } | |
b9733481 | 16198 | oappend (names[reg]); |
c0f3af97 L |
16199 | } |
16200 | ||
922d8de8 DR |
16201 | static void |
16202 | OP_XMM_VexW (int bytemode, int sizeflag) | |
16203 | { | |
16204 | /* Turn off the REX.W bit since it is used for swapping operands | |
16205 | now. */ | |
16206 | rex &= ~REX_W; | |
16207 | OP_XMM (bytemode, sizeflag); | |
16208 | } | |
16209 | ||
c0f3af97 L |
16210 | static void |
16211 | OP_EX_Vex (int bytemode, int sizeflag) | |
16212 | { | |
16213 | if (modrm.mod != 3) | |
63c6fc6c | 16214 | need_vex_reg = 0; |
c0f3af97 L |
16215 | OP_EX (bytemode, sizeflag); |
16216 | } | |
16217 | ||
16218 | static void | |
16219 | OP_XMM_Vex (int bytemode, int sizeflag) | |
16220 | { | |
16221 | if (modrm.mod != 3) | |
63c6fc6c | 16222 | need_vex_reg = 0; |
c0f3af97 L |
16223 | OP_XMM (bytemode, sizeflag); |
16224 | } | |
16225 | ||
ea397f5b L |
16226 | static struct op vex_cmp_op[] = |
16227 | { | |
16228 | { STRING_COMMA_LEN ("eq") }, | |
16229 | { STRING_COMMA_LEN ("lt") }, | |
16230 | { STRING_COMMA_LEN ("le") }, | |
16231 | { STRING_COMMA_LEN ("unord") }, | |
16232 | { STRING_COMMA_LEN ("neq") }, | |
16233 | { STRING_COMMA_LEN ("nlt") }, | |
16234 | { STRING_COMMA_LEN ("nle") }, | |
16235 | { STRING_COMMA_LEN ("ord") }, | |
16236 | { STRING_COMMA_LEN ("eq_uq") }, | |
16237 | { STRING_COMMA_LEN ("nge") }, | |
16238 | { STRING_COMMA_LEN ("ngt") }, | |
16239 | { STRING_COMMA_LEN ("false") }, | |
16240 | { STRING_COMMA_LEN ("neq_oq") }, | |
16241 | { STRING_COMMA_LEN ("ge") }, | |
16242 | { STRING_COMMA_LEN ("gt") }, | |
16243 | { STRING_COMMA_LEN ("true") }, | |
16244 | { STRING_COMMA_LEN ("eq_os") }, | |
16245 | { STRING_COMMA_LEN ("lt_oq") }, | |
16246 | { STRING_COMMA_LEN ("le_oq") }, | |
16247 | { STRING_COMMA_LEN ("unord_s") }, | |
16248 | { STRING_COMMA_LEN ("neq_us") }, | |
16249 | { STRING_COMMA_LEN ("nlt_uq") }, | |
16250 | { STRING_COMMA_LEN ("nle_uq") }, | |
16251 | { STRING_COMMA_LEN ("ord_s") }, | |
16252 | { STRING_COMMA_LEN ("eq_us") }, | |
16253 | { STRING_COMMA_LEN ("nge_uq") }, | |
16254 | { STRING_COMMA_LEN ("ngt_uq") }, | |
16255 | { STRING_COMMA_LEN ("false_os") }, | |
16256 | { STRING_COMMA_LEN ("neq_os") }, | |
16257 | { STRING_COMMA_LEN ("ge_oq") }, | |
16258 | { STRING_COMMA_LEN ("gt_oq") }, | |
16259 | { STRING_COMMA_LEN ("true_us") }, | |
c0f3af97 L |
16260 | }; |
16261 | ||
16262 | static void | |
16263 | VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
16264 | { | |
16265 | unsigned int cmp_type; | |
16266 | ||
16267 | FETCH_DATA (the_info, codep + 1); | |
16268 | cmp_type = *codep++ & 0xff; | |
16269 | if (cmp_type < ARRAY_SIZE (vex_cmp_op)) | |
16270 | { | |
16271 | char suffix [3]; | |
ea397f5b | 16272 | char *p = mnemonicendp - 2; |
c0f3af97 L |
16273 | suffix[0] = p[0]; |
16274 | suffix[1] = p[1]; | |
16275 | suffix[2] = '\0'; | |
ea397f5b L |
16276 | sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix); |
16277 | mnemonicendp += vex_cmp_op[cmp_type].len; | |
c0f3af97 L |
16278 | } |
16279 | else | |
16280 | { | |
16281 | /* We have a reserved extension byte. Output it directly. */ | |
16282 | scratchbuf[0] = '$'; | |
16283 | print_operand_value (scratchbuf + 1, 1, cmp_type); | |
9ce09ba2 | 16284 | oappend_maybe_intel (scratchbuf); |
c0f3af97 L |
16285 | scratchbuf[0] = '\0'; |
16286 | } | |
16287 | } | |
16288 | ||
43234a1e L |
16289 | static void |
16290 | VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, | |
16291 | int sizeflag ATTRIBUTE_UNUSED) | |
16292 | { | |
16293 | unsigned int cmp_type; | |
16294 | ||
16295 | if (!vex.evex) | |
16296 | abort (); | |
16297 | ||
16298 | FETCH_DATA (the_info, codep + 1); | |
16299 | cmp_type = *codep++ & 0xff; | |
16300 | /* There are aliases for immediates 0, 1, 2, 4, 5, 6. | |
16301 | If it's the case, print suffix, otherwise - print the immediate. */ | |
16302 | if (cmp_type < ARRAY_SIZE (simd_cmp_op) | |
16303 | && cmp_type != 3 | |
16304 | && cmp_type != 7) | |
16305 | { | |
16306 | char suffix [3]; | |
16307 | char *p = mnemonicendp - 2; | |
16308 | ||
16309 | /* vpcmp* can have both one- and two-lettered suffix. */ | |
16310 | if (p[0] == 'p') | |
16311 | { | |
16312 | p++; | |
16313 | suffix[0] = p[0]; | |
16314 | suffix[1] = '\0'; | |
16315 | } | |
16316 | else | |
16317 | { | |
16318 | suffix[0] = p[0]; | |
16319 | suffix[1] = p[1]; | |
16320 | suffix[2] = '\0'; | |
16321 | } | |
16322 | ||
16323 | sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix); | |
16324 | mnemonicendp += simd_cmp_op[cmp_type].len; | |
16325 | } | |
be92cb14 JB |
16326 | else |
16327 | { | |
16328 | /* We have a reserved extension byte. Output it directly. */ | |
16329 | scratchbuf[0] = '$'; | |
16330 | print_operand_value (scratchbuf + 1, 1, cmp_type); | |
16331 | oappend_maybe_intel (scratchbuf); | |
16332 | scratchbuf[0] = '\0'; | |
16333 | } | |
16334 | } | |
16335 | ||
16336 | static const struct op xop_cmp_op[] = | |
16337 | { | |
16338 | { STRING_COMMA_LEN ("lt") }, | |
16339 | { STRING_COMMA_LEN ("le") }, | |
16340 | { STRING_COMMA_LEN ("gt") }, | |
16341 | { STRING_COMMA_LEN ("ge") }, | |
16342 | { STRING_COMMA_LEN ("eq") }, | |
16343 | { STRING_COMMA_LEN ("neq") }, | |
16344 | { STRING_COMMA_LEN ("false") }, | |
16345 | { STRING_COMMA_LEN ("true") } | |
16346 | }; | |
16347 | ||
16348 | static void | |
16349 | VPCOM_Fixup (int bytemode ATTRIBUTE_UNUSED, | |
16350 | int sizeflag ATTRIBUTE_UNUSED) | |
16351 | { | |
16352 | unsigned int cmp_type; | |
16353 | ||
16354 | FETCH_DATA (the_info, codep + 1); | |
16355 | cmp_type = *codep++ & 0xff; | |
16356 | if (cmp_type < ARRAY_SIZE (xop_cmp_op)) | |
16357 | { | |
16358 | char suffix[3]; | |
16359 | char *p = mnemonicendp - 2; | |
16360 | ||
16361 | /* vpcom* can have both one- and two-lettered suffix. */ | |
16362 | if (p[0] == 'm') | |
16363 | { | |
16364 | p++; | |
16365 | suffix[0] = p[0]; | |
16366 | suffix[1] = '\0'; | |
16367 | } | |
16368 | else | |
16369 | { | |
16370 | suffix[0] = p[0]; | |
16371 | suffix[1] = p[1]; | |
16372 | suffix[2] = '\0'; | |
16373 | } | |
16374 | ||
16375 | sprintf (p, "%s%s", xop_cmp_op[cmp_type].name, suffix); | |
16376 | mnemonicendp += xop_cmp_op[cmp_type].len; | |
16377 | } | |
43234a1e L |
16378 | else |
16379 | { | |
16380 | /* We have a reserved extension byte. Output it directly. */ | |
16381 | scratchbuf[0] = '$'; | |
16382 | print_operand_value (scratchbuf + 1, 1, cmp_type); | |
9ce09ba2 | 16383 | oappend_maybe_intel (scratchbuf); |
43234a1e L |
16384 | scratchbuf[0] = '\0'; |
16385 | } | |
16386 | } | |
16387 | ||
ea397f5b L |
16388 | static const struct op pclmul_op[] = |
16389 | { | |
16390 | { STRING_COMMA_LEN ("lql") }, | |
16391 | { STRING_COMMA_LEN ("hql") }, | |
16392 | { STRING_COMMA_LEN ("lqh") }, | |
16393 | { STRING_COMMA_LEN ("hqh") } | |
c0f3af97 L |
16394 | }; |
16395 | ||
16396 | static void | |
16397 | PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED, | |
16398 | int sizeflag ATTRIBUTE_UNUSED) | |
16399 | { | |
16400 | unsigned int pclmul_type; | |
16401 | ||
16402 | FETCH_DATA (the_info, codep + 1); | |
16403 | pclmul_type = *codep++ & 0xff; | |
16404 | switch (pclmul_type) | |
16405 | { | |
16406 | case 0x10: | |
16407 | pclmul_type = 2; | |
16408 | break; | |
16409 | case 0x11: | |
16410 | pclmul_type = 3; | |
16411 | break; | |
16412 | default: | |
16413 | break; | |
7bb15c6f | 16414 | } |
c0f3af97 L |
16415 | if (pclmul_type < ARRAY_SIZE (pclmul_op)) |
16416 | { | |
16417 | char suffix [4]; | |
ea397f5b | 16418 | char *p = mnemonicendp - 3; |
c0f3af97 L |
16419 | suffix[0] = p[0]; |
16420 | suffix[1] = p[1]; | |
16421 | suffix[2] = p[2]; | |
16422 | suffix[3] = '\0'; | |
ea397f5b L |
16423 | sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix); |
16424 | mnemonicendp += pclmul_op[pclmul_type].len; | |
c0f3af97 L |
16425 | } |
16426 | else | |
16427 | { | |
16428 | /* We have a reserved extension byte. Output it directly. */ | |
16429 | scratchbuf[0] = '$'; | |
16430 | print_operand_value (scratchbuf + 1, 1, pclmul_type); | |
9ce09ba2 | 16431 | oappend_maybe_intel (scratchbuf); |
c0f3af97 L |
16432 | scratchbuf[0] = '\0'; |
16433 | } | |
16434 | } | |
16435 | ||
f1f8f695 L |
16436 | static void |
16437 | MOVBE_Fixup (int bytemode, int sizeflag) | |
16438 | { | |
16439 | /* Add proper suffix to "movbe". */ | |
ea397f5b | 16440 | char *p = mnemonicendp; |
f1f8f695 L |
16441 | |
16442 | switch (bytemode) | |
16443 | { | |
16444 | case v_mode: | |
16445 | if (intel_syntax) | |
ea397f5b | 16446 | goto skip; |
f1f8f695 L |
16447 | |
16448 | USED_REX (REX_W); | |
16449 | if (sizeflag & SUFFIX_ALWAYS) | |
16450 | { | |
16451 | if (rex & REX_W) | |
16452 | *p++ = 'q'; | |
f1f8f695 | 16453 | else |
f16cd0d5 L |
16454 | { |
16455 | if (sizeflag & DFLAG) | |
16456 | *p++ = 'l'; | |
16457 | else | |
16458 | *p++ = 'w'; | |
16459 | used_prefixes |= (prefixes & PREFIX_DATA); | |
16460 | } | |
f1f8f695 | 16461 | } |
f1f8f695 L |
16462 | break; |
16463 | default: | |
16464 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
16465 | break; | |
16466 | } | |
ea397f5b | 16467 | mnemonicendp = p; |
f1f8f695 L |
16468 | *p = '\0'; |
16469 | ||
dc1e8a47 | 16470 | skip: |
f1f8f695 L |
16471 | OP_M (bytemode, sizeflag); |
16472 | } | |
f88c9eb0 | 16473 | |
bc31405e L |
16474 | static void |
16475 | MOVSXD_Fixup (int bytemode, int sizeflag) | |
16476 | { | |
16477 | /* Add proper suffix to "movsxd". */ | |
16478 | char *p = mnemonicendp; | |
16479 | ||
16480 | switch (bytemode) | |
16481 | { | |
16482 | case movsxd_mode: | |
16483 | if (intel_syntax) | |
16484 | { | |
16485 | *p++ = 'x'; | |
16486 | *p++ = 'd'; | |
16487 | goto skip; | |
16488 | } | |
16489 | ||
16490 | USED_REX (REX_W); | |
16491 | if (rex & REX_W) | |
16492 | { | |
16493 | *p++ = 'l'; | |
16494 | *p++ = 'q'; | |
16495 | } | |
16496 | else | |
16497 | { | |
16498 | *p++ = 'x'; | |
16499 | *p++ = 'd'; | |
16500 | } | |
16501 | break; | |
16502 | default: | |
16503 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
16504 | break; | |
16505 | } | |
16506 | ||
dc1e8a47 | 16507 | skip: |
bc31405e L |
16508 | mnemonicendp = p; |
16509 | *p = '\0'; | |
16510 | OP_E (bytemode, sizeflag); | |
16511 | } | |
16512 | ||
f88c9eb0 SP |
16513 | static void |
16514 | OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
16515 | { | |
16516 | int reg; | |
16517 | const char **names; | |
16518 | ||
16519 | /* Skip mod/rm byte. */ | |
16520 | MODRM_CHECK; | |
16521 | codep++; | |
16522 | ||
390a6789 | 16523 | if (rex & REX_W) |
f88c9eb0 | 16524 | names = names64; |
f88c9eb0 | 16525 | else |
ce7d077e | 16526 | names = names32; |
f88c9eb0 SP |
16527 | |
16528 | reg = modrm.rm; | |
16529 | USED_REX (REX_B); | |
16530 | if (rex & REX_B) | |
16531 | reg += 8; | |
16532 | ||
16533 | oappend (names[reg]); | |
16534 | } | |
16535 | ||
16536 | static void | |
16537 | OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
16538 | { | |
16539 | const char **names; | |
5f847646 | 16540 | unsigned int reg = vex.register_specifier; |
63c6fc6c | 16541 | vex.register_specifier = 0; |
f88c9eb0 | 16542 | |
390a6789 | 16543 | if (rex & REX_W) |
f88c9eb0 | 16544 | names = names64; |
f88c9eb0 | 16545 | else |
ce7d077e | 16546 | names = names32; |
f88c9eb0 | 16547 | |
5f847646 JB |
16548 | if (address_mode != mode_64bit) |
16549 | reg &= 7; | |
16550 | oappend (names[reg]); | |
f88c9eb0 | 16551 | } |
43234a1e L |
16552 | |
16553 | static void | |
16554 | OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED) | |
16555 | { | |
16556 | if (!vex.evex | |
1ba585e8 | 16557 | || (bytemode != mask_mode && bytemode != mask_bd_mode)) |
43234a1e L |
16558 | abort (); |
16559 | ||
16560 | USED_REX (REX_R); | |
16561 | if ((rex & REX_R) != 0 || !vex.r) | |
16562 | { | |
16563 | BadOp (); | |
16564 | return; | |
16565 | } | |
16566 | ||
16567 | oappend (names_mask [modrm.reg]); | |
16568 | } | |
16569 | ||
16570 | static void | |
16571 | OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED) | |
16572 | { | |
43234a1e L |
16573 | if (modrm.mod == 3 && vex.b) |
16574 | switch (bytemode) | |
16575 | { | |
70df6fc9 L |
16576 | case evex_rounding_64_mode: |
16577 | if (address_mode != mode_64bit) | |
16578 | { | |
16579 | oappend ("(bad)"); | |
16580 | break; | |
16581 | } | |
16582 | /* Fall through. */ | |
43234a1e L |
16583 | case evex_rounding_mode: |
16584 | oappend (names_rounding[vex.ll]); | |
16585 | break; | |
16586 | case evex_sae_mode: | |
16587 | oappend ("{sae}"); | |
16588 | break; | |
16589 | default: | |
6df22cf6 | 16590 | abort (); |
43234a1e L |
16591 | break; |
16592 | } | |
16593 | } |