1 /* Target-dependent code for AMD64.
3 Copyright (C) 2001-2020 Free Software Foundation, Inc.
5 Contributed by Jiri Smid, SuSE Labs.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
23 #include "opcode/i386.h"
25 #include "arch-utils.h"
27 #include "dummy-frame.h"
29 #include "frame-base.h"
30 #include "frame-unwind.h"
40 #include "amd64-tdep.h"
41 #include "i387-tdep.h"
42 #include "gdbsupport/x86-xstate.h"
44 #include "target-descriptions.h"
45 #include "arch/amd64.h"
49 #include "gdbsupport/byte-vector.h"
53 /* Note that the AMD64 architecture was previously known as x86-64.
54 The latter is (forever) engraved into the canonical system name as
55 returned by config.guess, and used as the name for the AMD64 port
56 of GNU/Linux. The BSD's have renamed their ports to amd64; they
57 don't like to shout. For GDB we prefer the amd64_-prefix over the
58 x86_64_-prefix since it's so much easier to type. */
60 /* Register information. */
62 static const char *amd64_register_names
[] =
64 "rax", "rbx", "rcx", "rdx", "rsi", "rdi", "rbp", "rsp",
66 /* %r8 is indeed register number 8. */
67 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
68 "rip", "eflags", "cs", "ss", "ds", "es", "fs", "gs",
70 /* %st0 is register number 24. */
71 "st0", "st1", "st2", "st3", "st4", "st5", "st6", "st7",
72 "fctrl", "fstat", "ftag", "fiseg", "fioff", "foseg", "fooff", "fop",
74 /* %xmm0 is register number 40. */
75 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7",
76 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15",
80 static const char *amd64_ymm_names
[] =
82 "ymm0", "ymm1", "ymm2", "ymm3",
83 "ymm4", "ymm5", "ymm6", "ymm7",
84 "ymm8", "ymm9", "ymm10", "ymm11",
85 "ymm12", "ymm13", "ymm14", "ymm15"
88 static const char *amd64_ymm_avx512_names
[] =
90 "ymm16", "ymm17", "ymm18", "ymm19",
91 "ymm20", "ymm21", "ymm22", "ymm23",
92 "ymm24", "ymm25", "ymm26", "ymm27",
93 "ymm28", "ymm29", "ymm30", "ymm31"
96 static const char *amd64_ymmh_names
[] =
98 "ymm0h", "ymm1h", "ymm2h", "ymm3h",
99 "ymm4h", "ymm5h", "ymm6h", "ymm7h",
100 "ymm8h", "ymm9h", "ymm10h", "ymm11h",
101 "ymm12h", "ymm13h", "ymm14h", "ymm15h"
104 static const char *amd64_ymmh_avx512_names
[] =
106 "ymm16h", "ymm17h", "ymm18h", "ymm19h",
107 "ymm20h", "ymm21h", "ymm22h", "ymm23h",
108 "ymm24h", "ymm25h", "ymm26h", "ymm27h",
109 "ymm28h", "ymm29h", "ymm30h", "ymm31h"
112 static const char *amd64_mpx_names
[] =
114 "bnd0raw", "bnd1raw", "bnd2raw", "bnd3raw", "bndcfgu", "bndstatus"
117 static const char *amd64_k_names
[] =
119 "k0", "k1", "k2", "k3",
120 "k4", "k5", "k6", "k7"
123 static const char *amd64_zmmh_names
[] =
125 "zmm0h", "zmm1h", "zmm2h", "zmm3h",
126 "zmm4h", "zmm5h", "zmm6h", "zmm7h",
127 "zmm8h", "zmm9h", "zmm10h", "zmm11h",
128 "zmm12h", "zmm13h", "zmm14h", "zmm15h",
129 "zmm16h", "zmm17h", "zmm18h", "zmm19h",
130 "zmm20h", "zmm21h", "zmm22h", "zmm23h",
131 "zmm24h", "zmm25h", "zmm26h", "zmm27h",
132 "zmm28h", "zmm29h", "zmm30h", "zmm31h"
135 static const char *amd64_zmm_names
[] =
137 "zmm0", "zmm1", "zmm2", "zmm3",
138 "zmm4", "zmm5", "zmm6", "zmm7",
139 "zmm8", "zmm9", "zmm10", "zmm11",
140 "zmm12", "zmm13", "zmm14", "zmm15",
141 "zmm16", "zmm17", "zmm18", "zmm19",
142 "zmm20", "zmm21", "zmm22", "zmm23",
143 "zmm24", "zmm25", "zmm26", "zmm27",
144 "zmm28", "zmm29", "zmm30", "zmm31"
147 static const char *amd64_xmm_avx512_names
[] = {
148 "xmm16", "xmm17", "xmm18", "xmm19",
149 "xmm20", "xmm21", "xmm22", "xmm23",
150 "xmm24", "xmm25", "xmm26", "xmm27",
151 "xmm28", "xmm29", "xmm30", "xmm31"
154 static const char *amd64_pkeys_names
[] = {
158 /* DWARF Register Number Mapping as defined in the System V psABI,
161 static int amd64_dwarf_regmap
[] =
163 /* General Purpose Registers RAX, RDX, RCX, RBX, RSI, RDI. */
164 AMD64_RAX_REGNUM
, AMD64_RDX_REGNUM
,
165 AMD64_RCX_REGNUM
, AMD64_RBX_REGNUM
,
166 AMD64_RSI_REGNUM
, AMD64_RDI_REGNUM
,
168 /* Frame Pointer Register RBP. */
171 /* Stack Pointer Register RSP. */
174 /* Extended Integer Registers 8 - 15. */
175 AMD64_R8_REGNUM
, /* %r8 */
176 AMD64_R9_REGNUM
, /* %r9 */
177 AMD64_R10_REGNUM
, /* %r10 */
178 AMD64_R11_REGNUM
, /* %r11 */
179 AMD64_R12_REGNUM
, /* %r12 */
180 AMD64_R13_REGNUM
, /* %r13 */
181 AMD64_R14_REGNUM
, /* %r14 */
182 AMD64_R15_REGNUM
, /* %r15 */
184 /* Return Address RA. Mapped to RIP. */
187 /* SSE Registers 0 - 7. */
188 AMD64_XMM0_REGNUM
+ 0, AMD64_XMM1_REGNUM
,
189 AMD64_XMM0_REGNUM
+ 2, AMD64_XMM0_REGNUM
+ 3,
190 AMD64_XMM0_REGNUM
+ 4, AMD64_XMM0_REGNUM
+ 5,
191 AMD64_XMM0_REGNUM
+ 6, AMD64_XMM0_REGNUM
+ 7,
193 /* Extended SSE Registers 8 - 15. */
194 AMD64_XMM0_REGNUM
+ 8, AMD64_XMM0_REGNUM
+ 9,
195 AMD64_XMM0_REGNUM
+ 10, AMD64_XMM0_REGNUM
+ 11,
196 AMD64_XMM0_REGNUM
+ 12, AMD64_XMM0_REGNUM
+ 13,
197 AMD64_XMM0_REGNUM
+ 14, AMD64_XMM0_REGNUM
+ 15,
199 /* Floating Point Registers 0-7. */
200 AMD64_ST0_REGNUM
+ 0, AMD64_ST0_REGNUM
+ 1,
201 AMD64_ST0_REGNUM
+ 2, AMD64_ST0_REGNUM
+ 3,
202 AMD64_ST0_REGNUM
+ 4, AMD64_ST0_REGNUM
+ 5,
203 AMD64_ST0_REGNUM
+ 6, AMD64_ST0_REGNUM
+ 7,
205 /* MMX Registers 0 - 7.
206 We have to handle those registers specifically, as their register
207 number within GDB depends on the target (or they may even not be
208 available at all). */
209 -1, -1, -1, -1, -1, -1, -1, -1,
211 /* Control and Status Flags Register. */
214 /* Selector Registers. */
224 /* Segment Base Address Registers. */
230 /* Special Selector Registers. */
234 /* Floating Point Control Registers. */
240 static const int amd64_dwarf_regmap_len
=
241 (sizeof (amd64_dwarf_regmap
) / sizeof (amd64_dwarf_regmap
[0]));
243 /* Convert DWARF register number REG to the appropriate register
244 number used by GDB. */
247 amd64_dwarf_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
249 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
250 int ymm0_regnum
= tdep
->ymm0_regnum
;
253 if (reg
>= 0 && reg
< amd64_dwarf_regmap_len
)
254 regnum
= amd64_dwarf_regmap
[reg
];
257 && i386_xmm_regnum_p (gdbarch
, regnum
))
258 regnum
+= ymm0_regnum
- I387_XMM0_REGNUM (tdep
);
263 /* Map architectural register numbers to gdb register numbers. */
265 static const int amd64_arch_regmap
[16] =
267 AMD64_RAX_REGNUM
, /* %rax */
268 AMD64_RCX_REGNUM
, /* %rcx */
269 AMD64_RDX_REGNUM
, /* %rdx */
270 AMD64_RBX_REGNUM
, /* %rbx */
271 AMD64_RSP_REGNUM
, /* %rsp */
272 AMD64_RBP_REGNUM
, /* %rbp */
273 AMD64_RSI_REGNUM
, /* %rsi */
274 AMD64_RDI_REGNUM
, /* %rdi */
275 AMD64_R8_REGNUM
, /* %r8 */
276 AMD64_R9_REGNUM
, /* %r9 */
277 AMD64_R10_REGNUM
, /* %r10 */
278 AMD64_R11_REGNUM
, /* %r11 */
279 AMD64_R12_REGNUM
, /* %r12 */
280 AMD64_R13_REGNUM
, /* %r13 */
281 AMD64_R14_REGNUM
, /* %r14 */
282 AMD64_R15_REGNUM
/* %r15 */
285 static const int amd64_arch_regmap_len
=
286 (sizeof (amd64_arch_regmap
) / sizeof (amd64_arch_regmap
[0]));
288 /* Convert architectural register number REG to the appropriate register
289 number used by GDB. */
292 amd64_arch_reg_to_regnum (int reg
)
294 gdb_assert (reg
>= 0 && reg
< amd64_arch_regmap_len
);
296 return amd64_arch_regmap
[reg
];
299 /* Register names for byte pseudo-registers. */
301 static const char *amd64_byte_names
[] =
303 "al", "bl", "cl", "dl", "sil", "dil", "bpl", "spl",
304 "r8l", "r9l", "r10l", "r11l", "r12l", "r13l", "r14l", "r15l",
305 "ah", "bh", "ch", "dh"
308 /* Number of lower byte registers. */
309 #define AMD64_NUM_LOWER_BYTE_REGS 16
311 /* Register names for word pseudo-registers. */
313 static const char *amd64_word_names
[] =
315 "ax", "bx", "cx", "dx", "si", "di", "bp", "",
316 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
319 /* Register names for dword pseudo-registers. */
321 static const char *amd64_dword_names
[] =
323 "eax", "ebx", "ecx", "edx", "esi", "edi", "ebp", "esp",
324 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d",
328 /* Return the name of register REGNUM. */
331 amd64_pseudo_register_name (struct gdbarch
*gdbarch
, int regnum
)
333 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
334 if (i386_byte_regnum_p (gdbarch
, regnum
))
335 return amd64_byte_names
[regnum
- tdep
->al_regnum
];
336 else if (i386_zmm_regnum_p (gdbarch
, regnum
))
337 return amd64_zmm_names
[regnum
- tdep
->zmm0_regnum
];
338 else if (i386_ymm_regnum_p (gdbarch
, regnum
))
339 return amd64_ymm_names
[regnum
- tdep
->ymm0_regnum
];
340 else if (i386_ymm_avx512_regnum_p (gdbarch
, regnum
))
341 return amd64_ymm_avx512_names
[regnum
- tdep
->ymm16_regnum
];
342 else if (i386_word_regnum_p (gdbarch
, regnum
))
343 return amd64_word_names
[regnum
- tdep
->ax_regnum
];
344 else if (i386_dword_regnum_p (gdbarch
, regnum
))
345 return amd64_dword_names
[regnum
- tdep
->eax_regnum
];
347 return i386_pseudo_register_name (gdbarch
, regnum
);
350 static struct value
*
351 amd64_pseudo_register_read_value (struct gdbarch
*gdbarch
,
352 readable_regcache
*regcache
,
355 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
357 value
*result_value
= allocate_value (register_type (gdbarch
, regnum
));
358 VALUE_LVAL (result_value
) = lval_register
;
359 VALUE_REGNUM (result_value
) = regnum
;
360 gdb_byte
*buf
= value_contents_raw (result_value
);
362 if (i386_byte_regnum_p (gdbarch
, regnum
))
364 int gpnum
= regnum
- tdep
->al_regnum
;
366 /* Extract (always little endian). */
367 if (gpnum
>= AMD64_NUM_LOWER_BYTE_REGS
)
369 gpnum
-= AMD64_NUM_LOWER_BYTE_REGS
;
370 gdb_byte raw_buf
[register_size (gdbarch
, gpnum
)];
372 /* Special handling for AH, BH, CH, DH. */
373 register_status status
= regcache
->raw_read (gpnum
, raw_buf
);
374 if (status
== REG_VALID
)
375 memcpy (buf
, raw_buf
+ 1, 1);
377 mark_value_bytes_unavailable (result_value
, 0,
378 TYPE_LENGTH (value_type (result_value
)));
382 gdb_byte raw_buf
[register_size (gdbarch
, gpnum
)];
383 register_status status
= regcache
->raw_read (gpnum
, raw_buf
);
384 if (status
== REG_VALID
)
385 memcpy (buf
, raw_buf
, 1);
387 mark_value_bytes_unavailable (result_value
, 0,
388 TYPE_LENGTH (value_type (result_value
)));
391 else if (i386_dword_regnum_p (gdbarch
, regnum
))
393 int gpnum
= regnum
- tdep
->eax_regnum
;
394 gdb_byte raw_buf
[register_size (gdbarch
, gpnum
)];
395 /* Extract (always little endian). */
396 register_status status
= regcache
->raw_read (gpnum
, raw_buf
);
397 if (status
== REG_VALID
)
398 memcpy (buf
, raw_buf
, 4);
400 mark_value_bytes_unavailable (result_value
, 0,
401 TYPE_LENGTH (value_type (result_value
)));
404 i386_pseudo_register_read_into_value (gdbarch
, regcache
, regnum
,
411 amd64_pseudo_register_write (struct gdbarch
*gdbarch
,
412 struct regcache
*regcache
,
413 int regnum
, const gdb_byte
*buf
)
415 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
417 if (i386_byte_regnum_p (gdbarch
, regnum
))
419 int gpnum
= regnum
- tdep
->al_regnum
;
421 if (gpnum
>= AMD64_NUM_LOWER_BYTE_REGS
)
423 gpnum
-= AMD64_NUM_LOWER_BYTE_REGS
;
424 gdb_byte raw_buf
[register_size (gdbarch
, gpnum
)];
426 /* Read ... AH, BH, CH, DH. */
427 regcache
->raw_read (gpnum
, raw_buf
);
428 /* ... Modify ... (always little endian). */
429 memcpy (raw_buf
+ 1, buf
, 1);
431 regcache
->raw_write (gpnum
, raw_buf
);
435 gdb_byte raw_buf
[register_size (gdbarch
, gpnum
)];
438 regcache
->raw_read (gpnum
, raw_buf
);
439 /* ... Modify ... (always little endian). */
440 memcpy (raw_buf
, buf
, 1);
442 regcache
->raw_write (gpnum
, raw_buf
);
445 else if (i386_dword_regnum_p (gdbarch
, regnum
))
447 int gpnum
= regnum
- tdep
->eax_regnum
;
448 gdb_byte raw_buf
[register_size (gdbarch
, gpnum
)];
451 regcache
->raw_read (gpnum
, raw_buf
);
452 /* ... Modify ... (always little endian). */
453 memcpy (raw_buf
, buf
, 4);
455 regcache
->raw_write (gpnum
, raw_buf
);
458 i386_pseudo_register_write (gdbarch
, regcache
, regnum
, buf
);
461 /* Implement the 'ax_pseudo_register_collect' gdbarch method. */
464 amd64_ax_pseudo_register_collect (struct gdbarch
*gdbarch
,
465 struct agent_expr
*ax
, int regnum
)
467 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
469 if (i386_byte_regnum_p (gdbarch
, regnum
))
471 int gpnum
= regnum
- tdep
->al_regnum
;
473 if (gpnum
>= AMD64_NUM_LOWER_BYTE_REGS
)
474 ax_reg_mask (ax
, gpnum
- AMD64_NUM_LOWER_BYTE_REGS
);
476 ax_reg_mask (ax
, gpnum
);
479 else if (i386_dword_regnum_p (gdbarch
, regnum
))
481 int gpnum
= regnum
- tdep
->eax_regnum
;
483 ax_reg_mask (ax
, gpnum
);
487 return i386_ax_pseudo_register_collect (gdbarch
, ax
, regnum
);
492 /* Register classes as defined in the psABI. */
506 /* Return the union class of CLASS1 and CLASS2. See the psABI for
509 static enum amd64_reg_class
510 amd64_merge_classes (enum amd64_reg_class class1
, enum amd64_reg_class class2
)
512 /* Rule (a): If both classes are equal, this is the resulting class. */
513 if (class1
== class2
)
516 /* Rule (b): If one of the classes is NO_CLASS, the resulting class
517 is the other class. */
518 if (class1
== AMD64_NO_CLASS
)
520 if (class2
== AMD64_NO_CLASS
)
523 /* Rule (c): If one of the classes is MEMORY, the result is MEMORY. */
524 if (class1
== AMD64_MEMORY
|| class2
== AMD64_MEMORY
)
527 /* Rule (d): If one of the classes is INTEGER, the result is INTEGER. */
528 if (class1
== AMD64_INTEGER
|| class2
== AMD64_INTEGER
)
529 return AMD64_INTEGER
;
531 /* Rule (e): If one of the classes is X87, X87UP, COMPLEX_X87 class,
532 MEMORY is used as class. */
533 if (class1
== AMD64_X87
|| class1
== AMD64_X87UP
534 || class1
== AMD64_COMPLEX_X87
|| class2
== AMD64_X87
535 || class2
== AMD64_X87UP
|| class2
== AMD64_COMPLEX_X87
)
538 /* Rule (f): Otherwise class SSE is used. */
542 static void amd64_classify (struct type
*type
, enum amd64_reg_class theclass
[2]);
544 /* Return true if TYPE is a structure or union with unaligned fields. */
547 amd64_has_unaligned_fields (struct type
*type
)
549 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
550 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
552 for (int i
= 0; i
< TYPE_NFIELDS (type
); i
++)
554 struct type
*subtype
= check_typedef (TYPE_FIELD_TYPE (type
, i
));
555 int bitpos
= TYPE_FIELD_BITPOS (type
, i
);
556 int align
= type_align(subtype
);
558 /* Ignore static fields, empty fields (for example nested
559 empty structures), and bitfields (these are handled by
561 if (field_is_static (&TYPE_FIELD (type
, i
))
562 || (TYPE_FIELD_BITSIZE (type
, i
) == 0
563 && TYPE_LENGTH (subtype
) == 0)
564 || TYPE_FIELD_PACKED (type
, i
))
570 int bytepos
= bitpos
/ 8;
571 if (bytepos
% align
!= 0)
574 if (amd64_has_unaligned_fields (subtype
))
582 /* Classify field I of TYPE starting at BITOFFSET according to the rules for
583 structures and union types, and store the result in THECLASS. */
586 amd64_classify_aggregate_field (struct type
*type
, int i
,
587 enum amd64_reg_class theclass
[2],
588 unsigned int bitoffset
)
590 struct type
*subtype
= check_typedef (TYPE_FIELD_TYPE (type
, i
));
591 int bitpos
= bitoffset
+ TYPE_FIELD_BITPOS (type
, i
);
592 int pos
= bitpos
/ 64;
593 enum amd64_reg_class subclass
[2];
594 int bitsize
= TYPE_FIELD_BITSIZE (type
, i
);
598 bitsize
= TYPE_LENGTH (subtype
) * 8;
599 endpos
= (bitpos
+ bitsize
- 1) / 64;
601 /* Ignore static fields, or empty fields, for example nested
603 if (field_is_static (&TYPE_FIELD (type
, i
)) || bitsize
== 0)
606 if (TYPE_CODE (subtype
) == TYPE_CODE_STRUCT
607 || TYPE_CODE (subtype
) == TYPE_CODE_UNION
)
609 /* Each field of an object is classified recursively. */
611 for (j
= 0; j
< TYPE_NFIELDS (subtype
); j
++)
612 amd64_classify_aggregate_field (subtype
, j
, theclass
, bitpos
);
616 gdb_assert (pos
== 0 || pos
== 1);
618 amd64_classify (subtype
, subclass
);
619 theclass
[pos
] = amd64_merge_classes (theclass
[pos
], subclass
[0]);
620 if (bitsize
<= 64 && pos
== 0 && endpos
== 1)
621 /* This is a bit of an odd case: We have a field that would
622 normally fit in one of the two eightbytes, except that
623 it is placed in a way that this field straddles them.
624 This has been seen with a structure containing an array.
626 The ABI is a bit unclear in this case, but we assume that
627 this field's class (stored in subclass[0]) must also be merged
628 into class[1]. In other words, our field has a piece stored
629 in the second eight-byte, and thus its class applies to
630 the second eight-byte as well.
632 In the case where the field length exceeds 8 bytes,
633 it should not be necessary to merge the field class
634 into class[1]. As LEN > 8, subclass[1] is necessarily
635 different from AMD64_NO_CLASS. If subclass[1] is equal
636 to subclass[0], then the normal class[1]/subclass[1]
637 merging will take care of everything. For subclass[1]
638 to be different from subclass[0], I can only see the case
639 where we have a SSE/SSEUP or X87/X87UP pair, which both
640 use up all 16 bytes of the aggregate, and are already
641 handled just fine (because each portion sits on its own
643 theclass
[1] = amd64_merge_classes (theclass
[1], subclass
[0]);
645 theclass
[1] = amd64_merge_classes (theclass
[1], subclass
[1]);
648 /* Classify TYPE according to the rules for aggregate (structures and
649 arrays) and union types, and store the result in CLASS. */
652 amd64_classify_aggregate (struct type
*type
, enum amd64_reg_class theclass
[2])
654 /* 1. If the size of an object is larger than two eightbytes, or it has
655 unaligned fields, it has class memory. */
656 if (TYPE_LENGTH (type
) > 16 || amd64_has_unaligned_fields (type
))
658 theclass
[0] = theclass
[1] = AMD64_MEMORY
;
662 /* 2. Both eightbytes get initialized to class NO_CLASS. */
663 theclass
[0] = theclass
[1] = AMD64_NO_CLASS
;
665 /* 3. Each field of an object is classified recursively so that
666 always two fields are considered. The resulting class is
667 calculated according to the classes of the fields in the
670 if (TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
672 struct type
*subtype
= check_typedef (TYPE_TARGET_TYPE (type
));
674 /* All fields in an array have the same type. */
675 amd64_classify (subtype
, theclass
);
676 if (TYPE_LENGTH (type
) > 8 && theclass
[1] == AMD64_NO_CLASS
)
677 theclass
[1] = theclass
[0];
683 /* Structure or union. */
684 gdb_assert (TYPE_CODE (type
) == TYPE_CODE_STRUCT
685 || TYPE_CODE (type
) == TYPE_CODE_UNION
);
687 for (i
= 0; i
< TYPE_NFIELDS (type
); i
++)
688 amd64_classify_aggregate_field (type
, i
, theclass
, 0);
691 /* 4. Then a post merger cleanup is done: */
693 /* Rule (a): If one of the classes is MEMORY, the whole argument is
695 if (theclass
[0] == AMD64_MEMORY
|| theclass
[1] == AMD64_MEMORY
)
696 theclass
[0] = theclass
[1] = AMD64_MEMORY
;
698 /* Rule (b): If SSEUP is not preceded by SSE, it is converted to
700 if (theclass
[0] == AMD64_SSEUP
)
701 theclass
[0] = AMD64_SSE
;
702 if (theclass
[1] == AMD64_SSEUP
&& theclass
[0] != AMD64_SSE
)
703 theclass
[1] = AMD64_SSE
;
706 /* Classify TYPE, and store the result in CLASS. */
709 amd64_classify (struct type
*type
, enum amd64_reg_class theclass
[2])
711 enum type_code code
= TYPE_CODE (type
);
712 int len
= TYPE_LENGTH (type
);
714 theclass
[0] = theclass
[1] = AMD64_NO_CLASS
;
716 /* Arguments of types (signed and unsigned) _Bool, char, short, int,
717 long, long long, and pointers are in the INTEGER class. Similarly,
718 range types, used by languages such as Ada, are also in the INTEGER
720 if ((code
== TYPE_CODE_INT
|| code
== TYPE_CODE_ENUM
721 || code
== TYPE_CODE_BOOL
|| code
== TYPE_CODE_RANGE
722 || code
== TYPE_CODE_CHAR
723 || code
== TYPE_CODE_PTR
|| TYPE_IS_REFERENCE (type
))
724 && (len
== 1 || len
== 2 || len
== 4 || len
== 8))
725 theclass
[0] = AMD64_INTEGER
;
727 /* Arguments of types float, double, _Decimal32, _Decimal64 and __m64
729 else if ((code
== TYPE_CODE_FLT
|| code
== TYPE_CODE_DECFLOAT
)
730 && (len
== 4 || len
== 8))
732 theclass
[0] = AMD64_SSE
;
734 /* Arguments of types __float128, _Decimal128 and __m128 are split into
735 two halves. The least significant ones belong to class SSE, the most
736 significant one to class SSEUP. */
737 else if (code
== TYPE_CODE_DECFLOAT
&& len
== 16)
738 /* FIXME: __float128, __m128. */
739 theclass
[0] = AMD64_SSE
, theclass
[1] = AMD64_SSEUP
;
741 /* The 64-bit mantissa of arguments of type long double belongs to
742 class X87, the 16-bit exponent plus 6 bytes of padding belongs to
744 else if (code
== TYPE_CODE_FLT
&& len
== 16)
745 /* Class X87 and X87UP. */
746 theclass
[0] = AMD64_X87
, theclass
[1] = AMD64_X87UP
;
748 /* Arguments of complex T where T is one of the types float or
749 double get treated as if they are implemented as:
757 else if (code
== TYPE_CODE_COMPLEX
&& len
== 8)
758 theclass
[0] = AMD64_SSE
;
759 else if (code
== TYPE_CODE_COMPLEX
&& len
== 16)
760 theclass
[0] = theclass
[1] = AMD64_SSE
;
762 /* A variable of type complex long double is classified as type
764 else if (code
== TYPE_CODE_COMPLEX
&& len
== 32)
765 theclass
[0] = AMD64_COMPLEX_X87
;
768 else if (code
== TYPE_CODE_ARRAY
|| code
== TYPE_CODE_STRUCT
769 || code
== TYPE_CODE_UNION
)
770 amd64_classify_aggregate (type
, theclass
);
773 static enum return_value_convention
774 amd64_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
775 struct type
*type
, struct regcache
*regcache
,
776 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
778 enum amd64_reg_class theclass
[2];
779 int len
= TYPE_LENGTH (type
);
780 static int integer_regnum
[] = { AMD64_RAX_REGNUM
, AMD64_RDX_REGNUM
};
781 static int sse_regnum
[] = { AMD64_XMM0_REGNUM
, AMD64_XMM1_REGNUM
};
786 gdb_assert (!(readbuf
&& writebuf
));
788 /* 1. Classify the return type with the classification algorithm. */
789 amd64_classify (type
, theclass
);
791 /* 2. If the type has class MEMORY, then the caller provides space
792 for the return value and passes the address of this storage in
793 %rdi as if it were the first argument to the function. In effect,
794 this address becomes a hidden first argument.
796 On return %rax will contain the address that has been passed in
797 by the caller in %rdi. */
798 if (theclass
[0] == AMD64_MEMORY
)
800 /* As indicated by the comment above, the ABI guarantees that we
801 can always find the return value just after the function has
808 regcache_raw_read_unsigned (regcache
, AMD64_RAX_REGNUM
, &addr
);
809 read_memory (addr
, readbuf
, TYPE_LENGTH (type
));
812 return RETURN_VALUE_ABI_RETURNS_ADDRESS
;
815 /* 8. If the class is COMPLEX_X87, the real part of the value is
816 returned in %st0 and the imaginary part in %st1. */
817 if (theclass
[0] == AMD64_COMPLEX_X87
)
821 regcache
->raw_read (AMD64_ST0_REGNUM
, readbuf
);
822 regcache
->raw_read (AMD64_ST1_REGNUM
, readbuf
+ 16);
827 i387_return_value (gdbarch
, regcache
);
828 regcache
->raw_write (AMD64_ST0_REGNUM
, writebuf
);
829 regcache
->raw_write (AMD64_ST1_REGNUM
, writebuf
+ 16);
831 /* Fix up the tag word such that both %st(0) and %st(1) are
833 regcache_raw_write_unsigned (regcache
, AMD64_FTAG_REGNUM
, 0xfff);
836 return RETURN_VALUE_REGISTER_CONVENTION
;
839 gdb_assert (theclass
[1] != AMD64_MEMORY
);
840 gdb_assert (len
<= 16);
842 for (i
= 0; len
> 0; i
++, len
-= 8)
850 /* 3. If the class is INTEGER, the next available register
851 of the sequence %rax, %rdx is used. */
852 regnum
= integer_regnum
[integer_reg
++];
856 /* 4. If the class is SSE, the next available SSE register
857 of the sequence %xmm0, %xmm1 is used. */
858 regnum
= sse_regnum
[sse_reg
++];
862 /* 5. If the class is SSEUP, the eightbyte is passed in the
863 upper half of the last used SSE register. */
864 gdb_assert (sse_reg
> 0);
865 regnum
= sse_regnum
[sse_reg
- 1];
870 /* 6. If the class is X87, the value is returned on the X87
871 stack in %st0 as 80-bit x87 number. */
872 regnum
= AMD64_ST0_REGNUM
;
874 i387_return_value (gdbarch
, regcache
);
878 /* 7. If the class is X87UP, the value is returned together
879 with the previous X87 value in %st0. */
880 gdb_assert (i
> 0 && theclass
[0] == AMD64_X87
);
881 regnum
= AMD64_ST0_REGNUM
;
890 gdb_assert (!"Unexpected register class.");
893 gdb_assert (regnum
!= -1);
896 regcache
->raw_read_part (regnum
, offset
, std::min (len
, 8),
899 regcache
->raw_write_part (regnum
, offset
, std::min (len
, 8),
903 return RETURN_VALUE_REGISTER_CONVENTION
;
908 amd64_push_arguments (struct regcache
*regcache
, int nargs
, struct value
**args
,
909 CORE_ADDR sp
, function_call_return_method return_method
)
911 static int integer_regnum
[] =
913 AMD64_RDI_REGNUM
, /* %rdi */
914 AMD64_RSI_REGNUM
, /* %rsi */
915 AMD64_RDX_REGNUM
, /* %rdx */
916 AMD64_RCX_REGNUM
, /* %rcx */
917 AMD64_R8_REGNUM
, /* %r8 */
918 AMD64_R9_REGNUM
/* %r9 */
920 static int sse_regnum
[] =
922 /* %xmm0 ... %xmm7 */
923 AMD64_XMM0_REGNUM
+ 0, AMD64_XMM1_REGNUM
,
924 AMD64_XMM0_REGNUM
+ 2, AMD64_XMM0_REGNUM
+ 3,
925 AMD64_XMM0_REGNUM
+ 4, AMD64_XMM0_REGNUM
+ 5,
926 AMD64_XMM0_REGNUM
+ 6, AMD64_XMM0_REGNUM
+ 7,
928 struct value
**stack_args
= XALLOCAVEC (struct value
*, nargs
);
929 int num_stack_args
= 0;
930 int num_elements
= 0;
936 /* Reserve a register for the "hidden" argument. */
937 if (return_method
== return_method_struct
)
940 for (i
= 0; i
< nargs
; i
++)
942 struct type
*type
= value_type (args
[i
]);
943 int len
= TYPE_LENGTH (type
);
944 enum amd64_reg_class theclass
[2];
945 int needed_integer_regs
= 0;
946 int needed_sse_regs
= 0;
949 /* Classify argument. */
950 amd64_classify (type
, theclass
);
952 /* Calculate the number of integer and SSE registers needed for
954 for (j
= 0; j
< 2; j
++)
956 if (theclass
[j
] == AMD64_INTEGER
)
957 needed_integer_regs
++;
958 else if (theclass
[j
] == AMD64_SSE
)
962 /* Check whether enough registers are available, and if the
963 argument should be passed in registers at all. */
964 if (integer_reg
+ needed_integer_regs
> ARRAY_SIZE (integer_regnum
)
965 || sse_reg
+ needed_sse_regs
> ARRAY_SIZE (sse_regnum
)
966 || (needed_integer_regs
== 0 && needed_sse_regs
== 0))
968 /* The argument will be passed on the stack. */
969 num_elements
+= ((len
+ 7) / 8);
970 stack_args
[num_stack_args
++] = args
[i
];
974 /* The argument will be passed in registers. */
975 const gdb_byte
*valbuf
= value_contents (args
[i
]);
978 gdb_assert (len
<= 16);
980 for (j
= 0; len
> 0; j
++, len
-= 8)
988 regnum
= integer_regnum
[integer_reg
++];
992 regnum
= sse_regnum
[sse_reg
++];
996 gdb_assert (sse_reg
> 0);
997 regnum
= sse_regnum
[sse_reg
- 1];
1001 case AMD64_NO_CLASS
:
1005 gdb_assert (!"Unexpected register class.");
1008 gdb_assert (regnum
!= -1);
1009 memset (buf
, 0, sizeof buf
);
1010 memcpy (buf
, valbuf
+ j
* 8, std::min (len
, 8));
1011 regcache
->raw_write_part (regnum
, offset
, 8, buf
);
1016 /* Allocate space for the arguments on the stack. */
1017 sp
-= num_elements
* 8;
1019 /* The psABI says that "The end of the input argument area shall be
1020 aligned on a 16 byte boundary." */
1023 /* Write out the arguments to the stack. */
1024 for (i
= 0; i
< num_stack_args
; i
++)
1026 struct type
*type
= value_type (stack_args
[i
]);
1027 const gdb_byte
*valbuf
= value_contents (stack_args
[i
]);
1028 int len
= TYPE_LENGTH (type
);
1030 write_memory (sp
+ element
* 8, valbuf
, len
);
1031 element
+= ((len
+ 7) / 8);
1034 /* The psABI says that "For calls that may call functions that use
1035 varargs or stdargs (prototype-less calls or calls to functions
1036 containing ellipsis (...) in the declaration) %al is used as
1037 hidden argument to specify the number of SSE registers used. */
1038 regcache_raw_write_unsigned (regcache
, AMD64_RAX_REGNUM
, sse_reg
);
1043 amd64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
1044 struct regcache
*regcache
, CORE_ADDR bp_addr
,
1045 int nargs
, struct value
**args
, CORE_ADDR sp
,
1046 function_call_return_method return_method
,
1047 CORE_ADDR struct_addr
)
1049 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1052 /* BND registers can be in arbitrary values at the moment of the
1053 inferior call. This can cause boundary violations that are not
1054 due to a real bug or even desired by the user. The best to be done
1055 is set the BND registers to allow access to the whole memory, INIT
1056 state, before pushing the inferior call. */
1057 i387_reset_bnd_regs (gdbarch
, regcache
);
1059 /* Pass arguments. */
1060 sp
= amd64_push_arguments (regcache
, nargs
, args
, sp
, return_method
);
1062 /* Pass "hidden" argument". */
1063 if (return_method
== return_method_struct
)
1065 store_unsigned_integer (buf
, 8, byte_order
, struct_addr
);
1066 regcache
->cooked_write (AMD64_RDI_REGNUM
, buf
);
1069 /* Store return address. */
1071 store_unsigned_integer (buf
, 8, byte_order
, bp_addr
);
1072 write_memory (sp
, buf
, 8);
1074 /* Finally, update the stack pointer... */
1075 store_unsigned_integer (buf
, 8, byte_order
, sp
);
1076 regcache
->cooked_write (AMD64_RSP_REGNUM
, buf
);
1078 /* ...and fake a frame pointer. */
1079 regcache
->cooked_write (AMD64_RBP_REGNUM
, buf
);
1084 /* Displaced instruction handling. */
1086 /* A partially decoded instruction.
1087 This contains enough details for displaced stepping purposes. */
1091 /* The number of opcode bytes. */
1093 /* The offset of the REX/VEX instruction encoding prefix or -1 if
1095 int enc_prefix_offset
;
1096 /* The offset to the first opcode byte. */
1098 /* The offset to the modrm byte or -1 if not present. */
1101 /* The raw instruction. */
1105 struct amd64_displaced_step_copy_insn_closure
: public displaced_step_copy_insn_closure
1107 amd64_displaced_step_copy_insn_closure (int insn_buf_len
)
1108 : insn_buf (insn_buf_len
, 0)
1111 /* For rip-relative insns, saved copy of the reg we use instead of %rip. */
1116 /* Details of the instruction. */
1117 struct amd64_insn insn_details
;
1119 /* The possibly modified insn. */
1120 gdb::byte_vector insn_buf
;
1123 typedef std::unique_ptr
<amd64_displaced_step_copy_insn_closure
>
1124 amd64_displaced_step_copy_insn_closure_up
;
1126 /* WARNING: Keep onebyte_has_modrm, twobyte_has_modrm in sync with
1127 ../opcodes/i386-dis.c (until libopcodes exports them, or an alternative,
1128 at which point delete these in favor of libopcodes' versions). */
1130 static const unsigned char onebyte_has_modrm
[256] = {
1131 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1132 /* ------------------------------- */
1133 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
1134 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
1135 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
1136 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
1137 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
1138 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
1139 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
1140 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
1141 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
1142 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
1143 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
1144 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
1145 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
1146 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
1147 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
1148 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
1149 /* ------------------------------- */
1150 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1153 static const unsigned char twobyte_has_modrm
[256] = {
1154 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1155 /* ------------------------------- */
1156 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
1157 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
1158 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
1159 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
1160 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
1161 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
1162 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
1163 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
1164 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
1165 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
1166 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
1167 /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
1168 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
1169 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
1170 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
1171 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */
1172 /* ------------------------------- */
1173 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1176 static int amd64_syscall_p (const struct amd64_insn
*insn
, int *lengthp
);
1179 rex_prefix_p (gdb_byte pfx
)
1181 return REX_PREFIX_P (pfx
);
1184 /* True if PFX is the start of the 2-byte VEX prefix. */
1187 vex2_prefix_p (gdb_byte pfx
)
1192 /* True if PFX is the start of the 3-byte VEX prefix. */
1195 vex3_prefix_p (gdb_byte pfx
)
1200 /* Skip the legacy instruction prefixes in INSN.
1201 We assume INSN is properly sentineled so we don't have to worry
1202 about falling off the end of the buffer. */
1205 amd64_skip_prefixes (gdb_byte
*insn
)
1211 case DATA_PREFIX_OPCODE
:
1212 case ADDR_PREFIX_OPCODE
:
1213 case CS_PREFIX_OPCODE
:
1214 case DS_PREFIX_OPCODE
:
1215 case ES_PREFIX_OPCODE
:
1216 case FS_PREFIX_OPCODE
:
1217 case GS_PREFIX_OPCODE
:
1218 case SS_PREFIX_OPCODE
:
1219 case LOCK_PREFIX_OPCODE
:
1220 case REPE_PREFIX_OPCODE
:
1221 case REPNE_PREFIX_OPCODE
:
1233 /* Return an integer register (other than RSP) that is unused as an input
1235 In order to not require adding a rex prefix if the insn doesn't already
1236 have one, the result is restricted to RAX ... RDI, sans RSP.
1237 The register numbering of the result follows architecture ordering,
1241 amd64_get_unused_input_int_reg (const struct amd64_insn
*details
)
1243 /* 1 bit for each reg */
1244 int used_regs_mask
= 0;
1246 /* There can be at most 3 int regs used as inputs in an insn, and we have
1247 7 to choose from (RAX ... RDI, sans RSP).
1248 This allows us to take a conservative approach and keep things simple.
1249 E.g. By avoiding RAX, we don't have to specifically watch for opcodes
1250 that implicitly specify RAX. */
1253 used_regs_mask
|= 1 << EAX_REG_NUM
;
1254 /* Similarily avoid RDX, implicit operand in divides. */
1255 used_regs_mask
|= 1 << EDX_REG_NUM
;
1257 used_regs_mask
|= 1 << ESP_REG_NUM
;
1259 /* If the opcode is one byte long and there's no ModRM byte,
1260 assume the opcode specifies a register. */
1261 if (details
->opcode_len
== 1 && details
->modrm_offset
== -1)
1262 used_regs_mask
|= 1 << (details
->raw_insn
[details
->opcode_offset
] & 7);
1264 /* Mark used regs in the modrm/sib bytes. */
1265 if (details
->modrm_offset
!= -1)
1267 int modrm
= details
->raw_insn
[details
->modrm_offset
];
1268 int mod
= MODRM_MOD_FIELD (modrm
);
1269 int reg
= MODRM_REG_FIELD (modrm
);
1270 int rm
= MODRM_RM_FIELD (modrm
);
1271 int have_sib
= mod
!= 3 && rm
== 4;
1273 /* Assume the reg field of the modrm byte specifies a register. */
1274 used_regs_mask
|= 1 << reg
;
1278 int base
= SIB_BASE_FIELD (details
->raw_insn
[details
->modrm_offset
+ 1]);
1279 int idx
= SIB_INDEX_FIELD (details
->raw_insn
[details
->modrm_offset
+ 1]);
1280 used_regs_mask
|= 1 << base
;
1281 used_regs_mask
|= 1 << idx
;
1285 used_regs_mask
|= 1 << rm
;
1289 gdb_assert (used_regs_mask
< 256);
1290 gdb_assert (used_regs_mask
!= 255);
1292 /* Finally, find a free reg. */
1296 for (i
= 0; i
< 8; ++i
)
1298 if (! (used_regs_mask
& (1 << i
)))
1302 /* We shouldn't get here. */
1303 internal_error (__FILE__
, __LINE__
, _("unable to find free reg"));
1307 /* Extract the details of INSN that we need. */
1310 amd64_get_insn_details (gdb_byte
*insn
, struct amd64_insn
*details
)
1312 gdb_byte
*start
= insn
;
1315 details
->raw_insn
= insn
;
1317 details
->opcode_len
= -1;
1318 details
->enc_prefix_offset
= -1;
1319 details
->opcode_offset
= -1;
1320 details
->modrm_offset
= -1;
1322 /* Skip legacy instruction prefixes. */
1323 insn
= amd64_skip_prefixes (insn
);
1325 /* Skip REX/VEX instruction encoding prefixes. */
1326 if (rex_prefix_p (*insn
))
1328 details
->enc_prefix_offset
= insn
- start
;
1331 else if (vex2_prefix_p (*insn
))
1333 /* Don't record the offset in this case because this prefix has
1334 no REX.B equivalent. */
1337 else if (vex3_prefix_p (*insn
))
1339 details
->enc_prefix_offset
= insn
- start
;
1343 details
->opcode_offset
= insn
- start
;
1345 if (*insn
== TWO_BYTE_OPCODE_ESCAPE
)
1347 /* Two or three-byte opcode. */
1349 need_modrm
= twobyte_has_modrm
[*insn
];
1351 /* Check for three-byte opcode. */
1361 details
->opcode_len
= 3;
1364 details
->opcode_len
= 2;
1370 /* One-byte opcode. */
1371 need_modrm
= onebyte_has_modrm
[*insn
];
1372 details
->opcode_len
= 1;
1378 details
->modrm_offset
= insn
- start
;
1382 /* Update %rip-relative addressing in INSN.
1384 %rip-relative addressing only uses a 32-bit displacement.
1385 32 bits is not enough to be guaranteed to cover the distance between where
1386 the real instruction is and where its copy is.
1387 Convert the insn to use base+disp addressing.
1388 We set base = pc + insn_length so we can leave disp unchanged. */
1391 fixup_riprel (struct gdbarch
*gdbarch
, amd64_displaced_step_copy_insn_closure
*dsc
,
1392 CORE_ADDR from
, CORE_ADDR to
, struct regcache
*regs
)
1394 const struct amd64_insn
*insn_details
= &dsc
->insn_details
;
1395 int modrm_offset
= insn_details
->modrm_offset
;
1396 gdb_byte
*insn
= insn_details
->raw_insn
+ modrm_offset
;
1399 int arch_tmp_regno
, tmp_regno
;
1400 ULONGEST orig_value
;
1402 /* %rip+disp32 addressing mode, displacement follows ModRM byte. */
1405 /* Compute the rip-relative address. */
1406 insn_length
= gdb_buffered_insn_length (gdbarch
, dsc
->insn_buf
.data (),
1407 dsc
->insn_buf
.size (), from
);
1408 rip_base
= from
+ insn_length
;
1410 /* We need a register to hold the address.
1411 Pick one not used in the insn.
1412 NOTE: arch_tmp_regno uses architecture ordering, e.g. RDI = 7. */
1413 arch_tmp_regno
= amd64_get_unused_input_int_reg (insn_details
);
1414 tmp_regno
= amd64_arch_reg_to_regnum (arch_tmp_regno
);
1416 /* Position of the not-B bit in the 3-byte VEX prefix (in byte 1). */
1417 static constexpr gdb_byte VEX3_NOT_B
= 0x20;
1419 /* REX.B should be unset (VEX.!B set) as we were using rip-relative
1420 addressing, but ensure it's unset (set for VEX) anyway, tmp_regno
1422 if (insn_details
->enc_prefix_offset
!= -1)
1424 gdb_byte
*pfx
= &dsc
->insn_buf
[insn_details
->enc_prefix_offset
];
1425 if (rex_prefix_p (pfx
[0]))
1427 else if (vex3_prefix_p (pfx
[0]))
1428 pfx
[1] |= VEX3_NOT_B
;
1430 gdb_assert_not_reached ("unhandled prefix");
1433 regcache_cooked_read_unsigned (regs
, tmp_regno
, &orig_value
);
1434 dsc
->tmp_regno
= tmp_regno
;
1435 dsc
->tmp_save
= orig_value
;
1438 /* Convert the ModRM field to be base+disp. */
1439 dsc
->insn_buf
[modrm_offset
] &= ~0xc7;
1440 dsc
->insn_buf
[modrm_offset
] |= 0x80 + arch_tmp_regno
;
1442 regcache_cooked_write_unsigned (regs
, tmp_regno
, rip_base
);
1444 if (debug_displaced
)
1445 fprintf_unfiltered (gdb_stdlog
, "displaced: %%rip-relative addressing used.\n"
1446 "displaced: using temp reg %d, old value %s, new value %s\n",
1447 dsc
->tmp_regno
, paddress (gdbarch
, dsc
->tmp_save
),
1448 paddress (gdbarch
, rip_base
));
1452 fixup_displaced_copy (struct gdbarch
*gdbarch
,
1453 amd64_displaced_step_copy_insn_closure
*dsc
,
1454 CORE_ADDR from
, CORE_ADDR to
, struct regcache
*regs
)
1456 const struct amd64_insn
*details
= &dsc
->insn_details
;
1458 if (details
->modrm_offset
!= -1)
1460 gdb_byte modrm
= details
->raw_insn
[details
->modrm_offset
];
1462 if ((modrm
& 0xc7) == 0x05)
1464 /* The insn uses rip-relative addressing.
1466 fixup_riprel (gdbarch
, dsc
, from
, to
, regs
);
1471 displaced_step_copy_insn_closure_up
1472 amd64_displaced_step_copy_insn (struct gdbarch
*gdbarch
,
1473 CORE_ADDR from
, CORE_ADDR to
,
1474 struct regcache
*regs
)
1476 int len
= gdbarch_max_insn_length (gdbarch
);
1477 /* Extra space for sentinels so fixup_{riprel,displaced_copy} don't have to
1478 continually watch for running off the end of the buffer. */
1479 int fixup_sentinel_space
= len
;
1480 std::unique_ptr
<amd64_displaced_step_copy_insn_closure
> dsc
1481 (new amd64_displaced_step_copy_insn_closure (len
+ fixup_sentinel_space
));
1482 gdb_byte
*buf
= &dsc
->insn_buf
[0];
1483 struct amd64_insn
*details
= &dsc
->insn_details
;
1485 read_memory (from
, buf
, len
);
1487 /* Set up the sentinel space so we don't have to worry about running
1488 off the end of the buffer. An excessive number of leading prefixes
1489 could otherwise cause this. */
1490 memset (buf
+ len
, 0, fixup_sentinel_space
);
1492 amd64_get_insn_details (buf
, details
);
1494 /* GDB may get control back after the insn after the syscall.
1495 Presumably this is a kernel bug.
1496 If this is a syscall, make sure there's a nop afterwards. */
1500 if (amd64_syscall_p (details
, &syscall_length
))
1501 buf
[details
->opcode_offset
+ syscall_length
] = NOP_OPCODE
;
1504 /* Modify the insn to cope with the address where it will be executed from.
1505 In particular, handle any rip-relative addressing. */
1506 fixup_displaced_copy (gdbarch
, dsc
.get (), from
, to
, regs
);
1508 write_memory (to
, buf
, len
);
1510 if (debug_displaced
)
1512 fprintf_unfiltered (gdb_stdlog
, "displaced: copy %s->%s: ",
1513 paddress (gdbarch
, from
), paddress (gdbarch
, to
));
1514 displaced_step_dump_bytes (gdb_stdlog
, buf
, len
);
1517 /* This is a work around for a problem with g++ 4.8. */
1518 return displaced_step_copy_insn_closure_up (dsc
.release ());
1522 amd64_absolute_jmp_p (const struct amd64_insn
*details
)
1524 const gdb_byte
*insn
= &details
->raw_insn
[details
->opcode_offset
];
1526 if (insn
[0] == 0xff)
1528 /* jump near, absolute indirect (/4) */
1529 if ((insn
[1] & 0x38) == 0x20)
1532 /* jump far, absolute indirect (/5) */
1533 if ((insn
[1] & 0x38) == 0x28)
1540 /* Return non-zero if the instruction DETAILS is a jump, zero otherwise. */
1543 amd64_jmp_p (const struct amd64_insn
*details
)
1545 const gdb_byte
*insn
= &details
->raw_insn
[details
->opcode_offset
];
1547 /* jump short, relative. */
1548 if (insn
[0] == 0xeb)
1551 /* jump near, relative. */
1552 if (insn
[0] == 0xe9)
1555 return amd64_absolute_jmp_p (details
);
1559 amd64_absolute_call_p (const struct amd64_insn
*details
)
1561 const gdb_byte
*insn
= &details
->raw_insn
[details
->opcode_offset
];
1563 if (insn
[0] == 0xff)
1565 /* Call near, absolute indirect (/2) */
1566 if ((insn
[1] & 0x38) == 0x10)
1569 /* Call far, absolute indirect (/3) */
1570 if ((insn
[1] & 0x38) == 0x18)
1578 amd64_ret_p (const struct amd64_insn
*details
)
1580 /* NOTE: gcc can emit "repz ; ret". */
1581 const gdb_byte
*insn
= &details
->raw_insn
[details
->opcode_offset
];
1585 case 0xc2: /* ret near, pop N bytes */
1586 case 0xc3: /* ret near */
1587 case 0xca: /* ret far, pop N bytes */
1588 case 0xcb: /* ret far */
1589 case 0xcf: /* iret */
1598 amd64_call_p (const struct amd64_insn
*details
)
1600 const gdb_byte
*insn
= &details
->raw_insn
[details
->opcode_offset
];
1602 if (amd64_absolute_call_p (details
))
1605 /* call near, relative */
1606 if (insn
[0] == 0xe8)
1612 /* Return non-zero if INSN is a system call, and set *LENGTHP to its
1613 length in bytes. Otherwise, return zero. */
1616 amd64_syscall_p (const struct amd64_insn
*details
, int *lengthp
)
1618 const gdb_byte
*insn
= &details
->raw_insn
[details
->opcode_offset
];
1620 if (insn
[0] == 0x0f && insn
[1] == 0x05)
1629 /* Classify the instruction at ADDR using PRED.
1630 Throw an error if the memory can't be read. */
1633 amd64_classify_insn_at (struct gdbarch
*gdbarch
, CORE_ADDR addr
,
1634 int (*pred
) (const struct amd64_insn
*))
1636 struct amd64_insn details
;
1638 int len
, classification
;
1640 len
= gdbarch_max_insn_length (gdbarch
);
1641 buf
= (gdb_byte
*) alloca (len
);
1643 read_code (addr
, buf
, len
);
1644 amd64_get_insn_details (buf
, &details
);
1646 classification
= pred (&details
);
1648 return classification
;
1651 /* The gdbarch insn_is_call method. */
1654 amd64_insn_is_call (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
1656 return amd64_classify_insn_at (gdbarch
, addr
, amd64_call_p
);
1659 /* The gdbarch insn_is_ret method. */
1662 amd64_insn_is_ret (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
1664 return amd64_classify_insn_at (gdbarch
, addr
, amd64_ret_p
);
1667 /* The gdbarch insn_is_jump method. */
1670 amd64_insn_is_jump (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
1672 return amd64_classify_insn_at (gdbarch
, addr
, amd64_jmp_p
);
1675 /* Fix up the state of registers and memory after having single-stepped
1676 a displaced instruction. */
1679 amd64_displaced_step_fixup (struct gdbarch
*gdbarch
,
1680 struct displaced_step_copy_insn_closure
*dsc_
,
1681 CORE_ADDR from
, CORE_ADDR to
,
1682 struct regcache
*regs
)
1684 amd64_displaced_step_copy_insn_closure
*dsc
= (amd64_displaced_step_copy_insn_closure
*) dsc_
;
1685 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1686 /* The offset we applied to the instruction's address. */
1687 ULONGEST insn_offset
= to
- from
;
1688 gdb_byte
*insn
= dsc
->insn_buf
.data ();
1689 const struct amd64_insn
*insn_details
= &dsc
->insn_details
;
1691 if (debug_displaced
)
1692 fprintf_unfiltered (gdb_stdlog
,
1693 "displaced: fixup (%s, %s), "
1694 "insn = 0x%02x 0x%02x ...\n",
1695 paddress (gdbarch
, from
), paddress (gdbarch
, to
),
1698 /* If we used a tmp reg, restore it. */
1702 if (debug_displaced
)
1703 fprintf_unfiltered (gdb_stdlog
, "displaced: restoring reg %d to %s\n",
1704 dsc
->tmp_regno
, paddress (gdbarch
, dsc
->tmp_save
));
1705 regcache_cooked_write_unsigned (regs
, dsc
->tmp_regno
, dsc
->tmp_save
);
1708 /* The list of issues to contend with here is taken from
1709 resume_execution in arch/x86/kernel/kprobes.c, Linux 2.6.28.
1710 Yay for Free Software! */
1712 /* Relocate the %rip back to the program's instruction stream,
1715 /* Except in the case of absolute or indirect jump or call
1716 instructions, or a return instruction, the new rip is relative to
1717 the displaced instruction; make it relative to the original insn.
1718 Well, signal handler returns don't need relocation either, but we use the
1719 value of %rip to recognize those; see below. */
1720 if (! amd64_absolute_jmp_p (insn_details
)
1721 && ! amd64_absolute_call_p (insn_details
)
1722 && ! amd64_ret_p (insn_details
))
1727 regcache_cooked_read_unsigned (regs
, AMD64_RIP_REGNUM
, &orig_rip
);
1729 /* A signal trampoline system call changes the %rip, resuming
1730 execution of the main program after the signal handler has
1731 returned. That makes them like 'return' instructions; we
1732 shouldn't relocate %rip.
1734 But most system calls don't, and we do need to relocate %rip.
1736 Our heuristic for distinguishing these cases: if stepping
1737 over the system call instruction left control directly after
1738 the instruction, the we relocate --- control almost certainly
1739 doesn't belong in the displaced copy. Otherwise, we assume
1740 the instruction has put control where it belongs, and leave
1741 it unrelocated. Goodness help us if there are PC-relative
1743 if (amd64_syscall_p (insn_details
, &insn_len
)
1744 && orig_rip
!= to
+ insn_len
1745 /* GDB can get control back after the insn after the syscall.
1746 Presumably this is a kernel bug.
1747 Fixup ensures its a nop, we add one to the length for it. */
1748 && orig_rip
!= to
+ insn_len
+ 1)
1750 if (debug_displaced
)
1751 fprintf_unfiltered (gdb_stdlog
,
1752 "displaced: syscall changed %%rip; "
1753 "not relocating\n");
1757 ULONGEST rip
= orig_rip
- insn_offset
;
1759 /* If we just stepped over a breakpoint insn, we don't backup
1760 the pc on purpose; this is to match behaviour without
1763 regcache_cooked_write_unsigned (regs
, AMD64_RIP_REGNUM
, rip
);
1765 if (debug_displaced
)
1766 fprintf_unfiltered (gdb_stdlog
,
1768 "relocated %%rip from %s to %s\n",
1769 paddress (gdbarch
, orig_rip
),
1770 paddress (gdbarch
, rip
));
1774 /* If the instruction was PUSHFL, then the TF bit will be set in the
1775 pushed value, and should be cleared. We'll leave this for later,
1776 since GDB already messes up the TF flag when stepping over a
1779 /* If the instruction was a call, the return address now atop the
1780 stack is the address following the copied instruction. We need
1781 to make it the address following the original instruction. */
1782 if (amd64_call_p (insn_details
))
1786 const ULONGEST retaddr_len
= 8;
1788 regcache_cooked_read_unsigned (regs
, AMD64_RSP_REGNUM
, &rsp
);
1789 retaddr
= read_memory_unsigned_integer (rsp
, retaddr_len
, byte_order
);
1790 retaddr
= (retaddr
- insn_offset
) & 0xffffffffffffffffULL
;
1791 write_memory_unsigned_integer (rsp
, retaddr_len
, byte_order
, retaddr
);
1793 if (debug_displaced
)
1794 fprintf_unfiltered (gdb_stdlog
,
1795 "displaced: relocated return addr at %s "
1797 paddress (gdbarch
, rsp
),
1798 paddress (gdbarch
, retaddr
));
1802 /* If the instruction INSN uses RIP-relative addressing, return the
1803 offset into the raw INSN where the displacement to be adjusted is
1804 found. Returns 0 if the instruction doesn't use RIP-relative
1808 rip_relative_offset (struct amd64_insn
*insn
)
1810 if (insn
->modrm_offset
!= -1)
1812 gdb_byte modrm
= insn
->raw_insn
[insn
->modrm_offset
];
1814 if ((modrm
& 0xc7) == 0x05)
1816 /* The displacement is found right after the ModRM byte. */
1817 return insn
->modrm_offset
+ 1;
1825 append_insns (CORE_ADDR
*to
, ULONGEST len
, const gdb_byte
*buf
)
1827 target_write_memory (*to
, buf
, len
);
1832 amd64_relocate_instruction (struct gdbarch
*gdbarch
,
1833 CORE_ADDR
*to
, CORE_ADDR oldloc
)
1835 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1836 int len
= gdbarch_max_insn_length (gdbarch
);
1837 /* Extra space for sentinels. */
1838 int fixup_sentinel_space
= len
;
1839 gdb_byte
*buf
= (gdb_byte
*) xmalloc (len
+ fixup_sentinel_space
);
1840 struct amd64_insn insn_details
;
1842 LONGEST rel32
, newrel
;
1846 read_memory (oldloc
, buf
, len
);
1848 /* Set up the sentinel space so we don't have to worry about running
1849 off the end of the buffer. An excessive number of leading prefixes
1850 could otherwise cause this. */
1851 memset (buf
+ len
, 0, fixup_sentinel_space
);
1854 amd64_get_insn_details (insn
, &insn_details
);
1856 insn_length
= gdb_buffered_insn_length (gdbarch
, insn
, len
, oldloc
);
1858 /* Skip legacy instruction prefixes. */
1859 insn
= amd64_skip_prefixes (insn
);
1861 /* Adjust calls with 32-bit relative addresses as push/jump, with
1862 the address pushed being the location where the original call in
1863 the user program would return to. */
1864 if (insn
[0] == 0xe8)
1866 gdb_byte push_buf
[32];
1870 /* Where "ret" in the original code will return to. */
1871 ret_addr
= oldloc
+ insn_length
;
1873 /* If pushing an address higher than or equal to 0x80000000,
1874 avoid 'pushq', as that sign extends its 32-bit operand, which
1875 would be incorrect. */
1876 if (ret_addr
<= 0x7fffffff)
1878 push_buf
[0] = 0x68; /* pushq $... */
1879 store_unsigned_integer (&push_buf
[1], 4, byte_order
, ret_addr
);
1884 push_buf
[i
++] = 0x48; /* sub $0x8,%rsp */
1885 push_buf
[i
++] = 0x83;
1886 push_buf
[i
++] = 0xec;
1887 push_buf
[i
++] = 0x08;
1889 push_buf
[i
++] = 0xc7; /* movl $imm,(%rsp) */
1890 push_buf
[i
++] = 0x04;
1891 push_buf
[i
++] = 0x24;
1892 store_unsigned_integer (&push_buf
[i
], 4, byte_order
,
1893 ret_addr
& 0xffffffff);
1896 push_buf
[i
++] = 0xc7; /* movl $imm,4(%rsp) */
1897 push_buf
[i
++] = 0x44;
1898 push_buf
[i
++] = 0x24;
1899 push_buf
[i
++] = 0x04;
1900 store_unsigned_integer (&push_buf
[i
], 4, byte_order
,
1904 gdb_assert (i
<= sizeof (push_buf
));
1905 /* Push the push. */
1906 append_insns (to
, i
, push_buf
);
1908 /* Convert the relative call to a relative jump. */
1911 /* Adjust the destination offset. */
1912 rel32
= extract_signed_integer (insn
+ 1, 4, byte_order
);
1913 newrel
= (oldloc
- *to
) + rel32
;
1914 store_signed_integer (insn
+ 1, 4, byte_order
, newrel
);
1916 if (debug_displaced
)
1917 fprintf_unfiltered (gdb_stdlog
,
1918 "Adjusted insn rel32=%s at %s to"
1919 " rel32=%s at %s\n",
1920 hex_string (rel32
), paddress (gdbarch
, oldloc
),
1921 hex_string (newrel
), paddress (gdbarch
, *to
));
1923 /* Write the adjusted jump into its displaced location. */
1924 append_insns (to
, 5, insn
);
1928 offset
= rip_relative_offset (&insn_details
);
1931 /* Adjust jumps with 32-bit relative addresses. Calls are
1932 already handled above. */
1933 if (insn
[0] == 0xe9)
1935 /* Adjust conditional jumps. */
1936 else if (insn
[0] == 0x0f && (insn
[1] & 0xf0) == 0x80)
1942 rel32
= extract_signed_integer (insn
+ offset
, 4, byte_order
);
1943 newrel
= (oldloc
- *to
) + rel32
;
1944 store_signed_integer (insn
+ offset
, 4, byte_order
, newrel
);
1945 if (debug_displaced
)
1946 fprintf_unfiltered (gdb_stdlog
,
1947 "Adjusted insn rel32=%s at %s to"
1948 " rel32=%s at %s\n",
1949 hex_string (rel32
), paddress (gdbarch
, oldloc
),
1950 hex_string (newrel
), paddress (gdbarch
, *to
));
1953 /* Write the adjusted instruction into its displaced location. */
1954 append_insns (to
, insn_length
, buf
);
1958 /* The maximum number of saved registers. This should include %rip. */
1959 #define AMD64_NUM_SAVED_REGS AMD64_NUM_GREGS
1961 struct amd64_frame_cache
1966 CORE_ADDR sp_offset
;
1969 /* Saved registers. */
1970 CORE_ADDR saved_regs
[AMD64_NUM_SAVED_REGS
];
1974 /* Do we have a frame? */
1978 /* Initialize a frame cache. */
1981 amd64_init_frame_cache (struct amd64_frame_cache
*cache
)
1988 cache
->sp_offset
= -8;
1991 /* Saved registers. We initialize these to -1 since zero is a valid
1992 offset (that's where %rbp is supposed to be stored).
1993 The values start out as being offsets, and are later converted to
1994 addresses (at which point -1 is interpreted as an address, still meaning
1996 for (i
= 0; i
< AMD64_NUM_SAVED_REGS
; i
++)
1997 cache
->saved_regs
[i
] = -1;
1998 cache
->saved_sp
= 0;
1999 cache
->saved_sp_reg
= -1;
2001 /* Frameless until proven otherwise. */
2002 cache
->frameless_p
= 1;
2005 /* Allocate and initialize a frame cache. */
2007 static struct amd64_frame_cache
*
2008 amd64_alloc_frame_cache (void)
2010 struct amd64_frame_cache
*cache
;
2012 cache
= FRAME_OBSTACK_ZALLOC (struct amd64_frame_cache
);
2013 amd64_init_frame_cache (cache
);
2017 /* GCC 4.4 and later, can put code in the prologue to realign the
2018 stack pointer. Check whether PC points to such code, and update
2019 CACHE accordingly. Return the first instruction after the code
2020 sequence or CURRENT_PC, whichever is smaller. If we don't
2021 recognize the code, return PC. */
2024 amd64_analyze_stack_align (CORE_ADDR pc
, CORE_ADDR current_pc
,
2025 struct amd64_frame_cache
*cache
)
2027 /* There are 2 code sequences to re-align stack before the frame
2030 1. Use a caller-saved saved register:
2036 2. Use a callee-saved saved register:
2043 "andq $-XXX, %rsp" can be either 4 bytes or 7 bytes:
2045 0x48 0x83 0xe4 0xf0 andq $-16, %rsp
2046 0x48 0x81 0xe4 0x00 0xff 0xff 0xff andq $-256, %rsp
2051 int offset
, offset_and
;
2053 if (target_read_code (pc
, buf
, sizeof buf
))
2056 /* Check caller-saved saved register. The first instruction has
2057 to be "leaq 8(%rsp), %reg". */
2058 if ((buf
[0] & 0xfb) == 0x48
2063 /* MOD must be binary 10 and R/M must be binary 100. */
2064 if ((buf
[2] & 0xc7) != 0x44)
2067 /* REG has register number. */
2068 reg
= (buf
[2] >> 3) & 7;
2070 /* Check the REX.R bit. */
2078 /* Check callee-saved saved register. The first instruction
2079 has to be "pushq %reg". */
2081 if ((buf
[0] & 0xf8) == 0x50)
2083 else if ((buf
[0] & 0xf6) == 0x40
2084 && (buf
[1] & 0xf8) == 0x50)
2086 /* Check the REX.B bit. */
2087 if ((buf
[0] & 1) != 0)
2096 reg
+= buf
[offset
] & 0x7;
2100 /* The next instruction has to be "leaq 16(%rsp), %reg". */
2101 if ((buf
[offset
] & 0xfb) != 0x48
2102 || buf
[offset
+ 1] != 0x8d
2103 || buf
[offset
+ 3] != 0x24
2104 || buf
[offset
+ 4] != 0x10)
2107 /* MOD must be binary 10 and R/M must be binary 100. */
2108 if ((buf
[offset
+ 2] & 0xc7) != 0x44)
2111 /* REG has register number. */
2112 r
= (buf
[offset
+ 2] >> 3) & 7;
2114 /* Check the REX.R bit. */
2115 if (buf
[offset
] == 0x4c)
2118 /* Registers in pushq and leaq have to be the same. */
2125 /* Rigister can't be %rsp nor %rbp. */
2126 if (reg
== 4 || reg
== 5)
2129 /* The next instruction has to be "andq $-XXX, %rsp". */
2130 if (buf
[offset
] != 0x48
2131 || buf
[offset
+ 2] != 0xe4
2132 || (buf
[offset
+ 1] != 0x81 && buf
[offset
+ 1] != 0x83))
2135 offset_and
= offset
;
2136 offset
+= buf
[offset
+ 1] == 0x81 ? 7 : 4;
2138 /* The next instruction has to be "pushq -8(%reg)". */
2140 if (buf
[offset
] == 0xff)
2142 else if ((buf
[offset
] & 0xf6) == 0x40
2143 && buf
[offset
+ 1] == 0xff)
2145 /* Check the REX.B bit. */
2146 if ((buf
[offset
] & 0x1) != 0)
2153 /* 8bit -8 is 0xf8. REG must be binary 110 and MOD must be binary
2155 if (buf
[offset
+ 1] != 0xf8
2156 || (buf
[offset
] & 0xf8) != 0x70)
2159 /* R/M has register. */
2160 r
+= buf
[offset
] & 7;
2162 /* Registers in leaq and pushq have to be the same. */
2166 if (current_pc
> pc
+ offset_and
)
2167 cache
->saved_sp_reg
= amd64_arch_reg_to_regnum (reg
);
2169 return std::min (pc
+ offset
+ 2, current_pc
);
2172 /* Similar to amd64_analyze_stack_align for x32. */
2175 amd64_x32_analyze_stack_align (CORE_ADDR pc
, CORE_ADDR current_pc
,
2176 struct amd64_frame_cache
*cache
)
2178 /* There are 2 code sequences to re-align stack before the frame
2181 1. Use a caller-saved saved register:
2189 [addr32] leal 8(%rsp), %reg
2191 [addr32] pushq -8(%reg)
2193 2. Use a callee-saved saved register:
2203 [addr32] leal 16(%rsp), %reg
2205 [addr32] pushq -8(%reg)
2207 "andq $-XXX, %rsp" can be either 4 bytes or 7 bytes:
2209 0x48 0x83 0xe4 0xf0 andq $-16, %rsp
2210 0x48 0x81 0xe4 0x00 0xff 0xff 0xff andq $-256, %rsp
2212 "andl $-XXX, %esp" can be either 3 bytes or 6 bytes:
2214 0x83 0xe4 0xf0 andl $-16, %esp
2215 0x81 0xe4 0x00 0xff 0xff 0xff andl $-256, %esp
2220 int offset
, offset_and
;
2222 if (target_read_memory (pc
, buf
, sizeof buf
))
2225 /* Skip optional addr32 prefix. */
2226 offset
= buf
[0] == 0x67 ? 1 : 0;
2228 /* Check caller-saved saved register. The first instruction has
2229 to be "leaq 8(%rsp), %reg" or "leal 8(%rsp), %reg". */
2230 if (((buf
[offset
] & 0xfb) == 0x48 || (buf
[offset
] & 0xfb) == 0x40)
2231 && buf
[offset
+ 1] == 0x8d
2232 && buf
[offset
+ 3] == 0x24
2233 && buf
[offset
+ 4] == 0x8)
2235 /* MOD must be binary 10 and R/M must be binary 100. */
2236 if ((buf
[offset
+ 2] & 0xc7) != 0x44)
2239 /* REG has register number. */
2240 reg
= (buf
[offset
+ 2] >> 3) & 7;
2242 /* Check the REX.R bit. */
2243 if ((buf
[offset
] & 0x4) != 0)
2250 /* Check callee-saved saved register. The first instruction
2251 has to be "pushq %reg". */
2253 if ((buf
[offset
] & 0xf6) == 0x40
2254 && (buf
[offset
+ 1] & 0xf8) == 0x50)
2256 /* Check the REX.B bit. */
2257 if ((buf
[offset
] & 1) != 0)
2262 else if ((buf
[offset
] & 0xf8) != 0x50)
2266 reg
+= buf
[offset
] & 0x7;
2270 /* Skip optional addr32 prefix. */
2271 if (buf
[offset
] == 0x67)
2274 /* The next instruction has to be "leaq 16(%rsp), %reg" or
2275 "leal 16(%rsp), %reg". */
2276 if (((buf
[offset
] & 0xfb) != 0x48 && (buf
[offset
] & 0xfb) != 0x40)
2277 || buf
[offset
+ 1] != 0x8d
2278 || buf
[offset
+ 3] != 0x24
2279 || buf
[offset
+ 4] != 0x10)
2282 /* MOD must be binary 10 and R/M must be binary 100. */
2283 if ((buf
[offset
+ 2] & 0xc7) != 0x44)
2286 /* REG has register number. */
2287 r
= (buf
[offset
+ 2] >> 3) & 7;
2289 /* Check the REX.R bit. */
2290 if ((buf
[offset
] & 0x4) != 0)
2293 /* Registers in pushq and leaq have to be the same. */
2300 /* Rigister can't be %rsp nor %rbp. */
2301 if (reg
== 4 || reg
== 5)
2304 /* The next instruction may be "andq $-XXX, %rsp" or
2305 "andl $-XXX, %esp". */
2306 if (buf
[offset
] != 0x48)
2309 if (buf
[offset
+ 2] != 0xe4
2310 || (buf
[offset
+ 1] != 0x81 && buf
[offset
+ 1] != 0x83))
2313 offset_and
= offset
;
2314 offset
+= buf
[offset
+ 1] == 0x81 ? 7 : 4;
2316 /* Skip optional addr32 prefix. */
2317 if (buf
[offset
] == 0x67)
2320 /* The next instruction has to be "pushq -8(%reg)". */
2322 if (buf
[offset
] == 0xff)
2324 else if ((buf
[offset
] & 0xf6) == 0x40
2325 && buf
[offset
+ 1] == 0xff)
2327 /* Check the REX.B bit. */
2328 if ((buf
[offset
] & 0x1) != 0)
2335 /* 8bit -8 is 0xf8. REG must be binary 110 and MOD must be binary
2337 if (buf
[offset
+ 1] != 0xf8
2338 || (buf
[offset
] & 0xf8) != 0x70)
2341 /* R/M has register. */
2342 r
+= buf
[offset
] & 7;
2344 /* Registers in leaq and pushq have to be the same. */
2348 if (current_pc
> pc
+ offset_and
)
2349 cache
->saved_sp_reg
= amd64_arch_reg_to_regnum (reg
);
2351 return std::min (pc
+ offset
+ 2, current_pc
);
2354 /* Do a limited analysis of the prologue at PC and update CACHE
2355 accordingly. Bail out early if CURRENT_PC is reached. Return the
2356 address where the analysis stopped.
2358 We will handle only functions beginning with:
2361 movq %rsp, %rbp 0x48 0x89 0xe5 (or 0x48 0x8b 0xec)
2363 or (for the X32 ABI):
2366 movl %esp, %ebp 0x89 0xe5 (or 0x8b 0xec)
2368 Any function that doesn't start with one of these sequences will be
2369 assumed to have no prologue and thus no valid frame pointer in
2373 amd64_analyze_prologue (struct gdbarch
*gdbarch
,
2374 CORE_ADDR pc
, CORE_ADDR current_pc
,
2375 struct amd64_frame_cache
*cache
)
2377 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2378 /* There are two variations of movq %rsp, %rbp. */
2379 static const gdb_byte mov_rsp_rbp_1
[3] = { 0x48, 0x89, 0xe5 };
2380 static const gdb_byte mov_rsp_rbp_2
[3] = { 0x48, 0x8b, 0xec };
2381 /* Ditto for movl %esp, %ebp. */
2382 static const gdb_byte mov_esp_ebp_1
[2] = { 0x89, 0xe5 };
2383 static const gdb_byte mov_esp_ebp_2
[2] = { 0x8b, 0xec };
2388 if (current_pc
<= pc
)
2391 if (gdbarch_ptr_bit (gdbarch
) == 32)
2392 pc
= amd64_x32_analyze_stack_align (pc
, current_pc
, cache
);
2394 pc
= amd64_analyze_stack_align (pc
, current_pc
, cache
);
2396 op
= read_code_unsigned_integer (pc
, 1, byte_order
);
2398 if (op
== 0x55) /* pushq %rbp */
2400 /* Take into account that we've executed the `pushq %rbp' that
2401 starts this instruction sequence. */
2402 cache
->saved_regs
[AMD64_RBP_REGNUM
] = 0;
2403 cache
->sp_offset
+= 8;
2405 /* If that's all, return now. */
2406 if (current_pc
<= pc
+ 1)
2409 read_code (pc
+ 1, buf
, 3);
2411 /* Check for `movq %rsp, %rbp'. */
2412 if (memcmp (buf
, mov_rsp_rbp_1
, 3) == 0
2413 || memcmp (buf
, mov_rsp_rbp_2
, 3) == 0)
2415 /* OK, we actually have a frame. */
2416 cache
->frameless_p
= 0;
2420 /* For X32, also check for `movq %esp, %ebp'. */
2421 if (gdbarch_ptr_bit (gdbarch
) == 32)
2423 if (memcmp (buf
, mov_esp_ebp_1
, 2) == 0
2424 || memcmp (buf
, mov_esp_ebp_2
, 2) == 0)
2426 /* OK, we actually have a frame. */
2427 cache
->frameless_p
= 0;
2438 /* Work around false termination of prologue - GCC PR debug/48827.
2440 START_PC is the first instruction of a function, PC is its minimal already
2441 determined advanced address. Function returns PC if it has nothing to do.
2445 <-- here is 0 lines advance - the false prologue end marker.
2446 0f 29 85 70 ff ff ff movaps %xmm0,-0x90(%rbp)
2447 0f 29 4d 80 movaps %xmm1,-0x80(%rbp)
2448 0f 29 55 90 movaps %xmm2,-0x70(%rbp)
2449 0f 29 5d a0 movaps %xmm3,-0x60(%rbp)
2450 0f 29 65 b0 movaps %xmm4,-0x50(%rbp)
2451 0f 29 6d c0 movaps %xmm5,-0x40(%rbp)
2452 0f 29 75 d0 movaps %xmm6,-0x30(%rbp)
2453 0f 29 7d e0 movaps %xmm7,-0x20(%rbp)
2457 amd64_skip_xmm_prologue (CORE_ADDR pc
, CORE_ADDR start_pc
)
2459 struct symtab_and_line start_pc_sal
, next_sal
;
2460 gdb_byte buf
[4 + 8 * 7];
2466 start_pc_sal
= find_pc_sect_line (start_pc
, NULL
, 0);
2467 if (start_pc_sal
.symtab
== NULL
2468 || producer_is_gcc_ge_4 (COMPUNIT_PRODUCER
2469 (SYMTAB_COMPUNIT (start_pc_sal
.symtab
))) < 6
2470 || start_pc_sal
.pc
!= start_pc
|| pc
>= start_pc_sal
.end
)
2473 next_sal
= find_pc_sect_line (start_pc_sal
.end
, NULL
, 0);
2474 if (next_sal
.line
!= start_pc_sal
.line
)
2477 /* START_PC can be from overlayed memory, ignored here. */
2478 if (target_read_code (next_sal
.pc
- 4, buf
, sizeof (buf
)) != 0)
2482 if (buf
[0] != 0x84 || buf
[1] != 0xc0)
2489 for (xmmreg
= 0; xmmreg
< 8; xmmreg
++)
2491 /* 0x0f 0x29 0b??000101 movaps %xmmreg?,-0x??(%rbp) */
2492 if (buf
[offset
] != 0x0f || buf
[offset
+ 1] != 0x29
2493 || (buf
[offset
+ 2] & 0x3f) != (xmmreg
<< 3 | 0x5))
2497 if ((buf
[offset
+ 2] & 0xc0) == 0x40)
2499 /* 8-bit displacement. */
2503 else if ((buf
[offset
+ 2] & 0xc0) == 0x80)
2505 /* 32-bit displacement. */
2513 if (offset
- 4 != buf
[3])
2516 return next_sal
.end
;
2519 /* Return PC of first real instruction. */
2522 amd64_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR start_pc
)
2524 struct amd64_frame_cache cache
;
2526 CORE_ADDR func_addr
;
2528 if (find_pc_partial_function (start_pc
, NULL
, &func_addr
, NULL
))
2530 CORE_ADDR post_prologue_pc
2531 = skip_prologue_using_sal (gdbarch
, func_addr
);
2532 struct compunit_symtab
*cust
= find_pc_compunit_symtab (func_addr
);
2534 /* Clang always emits a line note before the prologue and another
2535 one after. We trust clang to emit usable line notes. */
2536 if (post_prologue_pc
2538 && COMPUNIT_PRODUCER (cust
) != NULL
2539 && startswith (COMPUNIT_PRODUCER (cust
), "clang ")))
2540 return std::max (start_pc
, post_prologue_pc
);
2543 amd64_init_frame_cache (&cache
);
2544 pc
= amd64_analyze_prologue (gdbarch
, start_pc
, 0xffffffffffffffffLL
,
2546 if (cache
.frameless_p
)
2549 return amd64_skip_xmm_prologue (pc
, start_pc
);
2553 /* Normal frames. */
2556 amd64_frame_cache_1 (struct frame_info
*this_frame
,
2557 struct amd64_frame_cache
*cache
)
2559 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2560 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2564 cache
->pc
= get_frame_func (this_frame
);
2566 amd64_analyze_prologue (gdbarch
, cache
->pc
, get_frame_pc (this_frame
),
2569 if (cache
->frameless_p
)
2571 /* We didn't find a valid frame. If we're at the start of a
2572 function, or somewhere half-way its prologue, the function's
2573 frame probably hasn't been fully setup yet. Try to
2574 reconstruct the base address for the stack frame by looking
2575 at the stack pointer. For truly "frameless" functions this
2578 if (cache
->saved_sp_reg
!= -1)
2580 /* Stack pointer has been saved. */
2581 get_frame_register (this_frame
, cache
->saved_sp_reg
, buf
);
2582 cache
->saved_sp
= extract_unsigned_integer (buf
, 8, byte_order
);
2584 /* We're halfway aligning the stack. */
2585 cache
->base
= ((cache
->saved_sp
- 8) & 0xfffffffffffffff0LL
) - 8;
2586 cache
->saved_regs
[AMD64_RIP_REGNUM
] = cache
->saved_sp
- 8;
2588 /* This will be added back below. */
2589 cache
->saved_regs
[AMD64_RIP_REGNUM
] -= cache
->base
;
2593 get_frame_register (this_frame
, AMD64_RSP_REGNUM
, buf
);
2594 cache
->base
= extract_unsigned_integer (buf
, 8, byte_order
)
2600 get_frame_register (this_frame
, AMD64_RBP_REGNUM
, buf
);
2601 cache
->base
= extract_unsigned_integer (buf
, 8, byte_order
);
2604 /* Now that we have the base address for the stack frame we can
2605 calculate the value of %rsp in the calling frame. */
2606 cache
->saved_sp
= cache
->base
+ 16;
2608 /* For normal frames, %rip is stored at 8(%rbp). If we don't have a
2609 frame we find it at the same offset from the reconstructed base
2610 address. If we're halfway aligning the stack, %rip is handled
2611 differently (see above). */
2612 if (!cache
->frameless_p
|| cache
->saved_sp_reg
== -1)
2613 cache
->saved_regs
[AMD64_RIP_REGNUM
] = 8;
2615 /* Adjust all the saved registers such that they contain addresses
2616 instead of offsets. */
2617 for (i
= 0; i
< AMD64_NUM_SAVED_REGS
; i
++)
2618 if (cache
->saved_regs
[i
] != -1)
2619 cache
->saved_regs
[i
] += cache
->base
;
2624 static struct amd64_frame_cache
*
2625 amd64_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2627 struct amd64_frame_cache
*cache
;
2630 return (struct amd64_frame_cache
*) *this_cache
;
2632 cache
= amd64_alloc_frame_cache ();
2633 *this_cache
= cache
;
2637 amd64_frame_cache_1 (this_frame
, cache
);
2639 catch (const gdb_exception_error
&ex
)
2641 if (ex
.error
!= NOT_AVAILABLE_ERROR
)
2648 static enum unwind_stop_reason
2649 amd64_frame_unwind_stop_reason (struct frame_info
*this_frame
,
2652 struct amd64_frame_cache
*cache
=
2653 amd64_frame_cache (this_frame
, this_cache
);
2656 return UNWIND_UNAVAILABLE
;
2658 /* This marks the outermost frame. */
2659 if (cache
->base
== 0)
2660 return UNWIND_OUTERMOST
;
2662 return UNWIND_NO_REASON
;
2666 amd64_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
2667 struct frame_id
*this_id
)
2669 struct amd64_frame_cache
*cache
=
2670 amd64_frame_cache (this_frame
, this_cache
);
2673 (*this_id
) = frame_id_build_unavailable_stack (cache
->pc
);
2674 else if (cache
->base
== 0)
2676 /* This marks the outermost frame. */
2680 (*this_id
) = frame_id_build (cache
->base
+ 16, cache
->pc
);
2683 static struct value
*
2684 amd64_frame_prev_register (struct frame_info
*this_frame
, void **this_cache
,
2687 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2688 struct amd64_frame_cache
*cache
=
2689 amd64_frame_cache (this_frame
, this_cache
);
2691 gdb_assert (regnum
>= 0);
2693 if (regnum
== gdbarch_sp_regnum (gdbarch
) && cache
->saved_sp
)
2694 return frame_unwind_got_constant (this_frame
, regnum
, cache
->saved_sp
);
2696 if (regnum
< AMD64_NUM_SAVED_REGS
&& cache
->saved_regs
[regnum
] != -1)
2697 return frame_unwind_got_memory (this_frame
, regnum
,
2698 cache
->saved_regs
[regnum
]);
2700 return frame_unwind_got_register (this_frame
, regnum
, regnum
);
2703 static const struct frame_unwind amd64_frame_unwind
=
2706 amd64_frame_unwind_stop_reason
,
2707 amd64_frame_this_id
,
2708 amd64_frame_prev_register
,
2710 default_frame_sniffer
2713 /* Generate a bytecode expression to get the value of the saved PC. */
2716 amd64_gen_return_address (struct gdbarch
*gdbarch
,
2717 struct agent_expr
*ax
, struct axs_value
*value
,
2720 /* The following sequence assumes the traditional use of the base
2722 ax_reg (ax
, AMD64_RBP_REGNUM
);
2724 ax_simple (ax
, aop_add
);
2725 value
->type
= register_type (gdbarch
, AMD64_RIP_REGNUM
);
2726 value
->kind
= axs_lvalue_memory
;
2730 /* Signal trampolines. */
2732 /* FIXME: kettenis/20030419: Perhaps, we can unify the 32-bit and
2733 64-bit variants. This would require using identical frame caches
2734 on both platforms. */
2736 static struct amd64_frame_cache
*
2737 amd64_sigtramp_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2739 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2740 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2741 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2742 struct amd64_frame_cache
*cache
;
2748 return (struct amd64_frame_cache
*) *this_cache
;
2750 cache
= amd64_alloc_frame_cache ();
2754 get_frame_register (this_frame
, AMD64_RSP_REGNUM
, buf
);
2755 cache
->base
= extract_unsigned_integer (buf
, 8, byte_order
) - 8;
2757 addr
= tdep
->sigcontext_addr (this_frame
);
2758 gdb_assert (tdep
->sc_reg_offset
);
2759 gdb_assert (tdep
->sc_num_regs
<= AMD64_NUM_SAVED_REGS
);
2760 for (i
= 0; i
< tdep
->sc_num_regs
; i
++)
2761 if (tdep
->sc_reg_offset
[i
] != -1)
2762 cache
->saved_regs
[i
] = addr
+ tdep
->sc_reg_offset
[i
];
2766 catch (const gdb_exception_error
&ex
)
2768 if (ex
.error
!= NOT_AVAILABLE_ERROR
)
2772 *this_cache
= cache
;
2776 static enum unwind_stop_reason
2777 amd64_sigtramp_frame_unwind_stop_reason (struct frame_info
*this_frame
,
2780 struct amd64_frame_cache
*cache
=
2781 amd64_sigtramp_frame_cache (this_frame
, this_cache
);
2784 return UNWIND_UNAVAILABLE
;
2786 return UNWIND_NO_REASON
;
2790 amd64_sigtramp_frame_this_id (struct frame_info
*this_frame
,
2791 void **this_cache
, struct frame_id
*this_id
)
2793 struct amd64_frame_cache
*cache
=
2794 amd64_sigtramp_frame_cache (this_frame
, this_cache
);
2797 (*this_id
) = frame_id_build_unavailable_stack (get_frame_pc (this_frame
));
2798 else if (cache
->base
== 0)
2800 /* This marks the outermost frame. */
2804 (*this_id
) = frame_id_build (cache
->base
+ 16, get_frame_pc (this_frame
));
2807 static struct value
*
2808 amd64_sigtramp_frame_prev_register (struct frame_info
*this_frame
,
2809 void **this_cache
, int regnum
)
2811 /* Make sure we've initialized the cache. */
2812 amd64_sigtramp_frame_cache (this_frame
, this_cache
);
2814 return amd64_frame_prev_register (this_frame
, this_cache
, regnum
);
2818 amd64_sigtramp_frame_sniffer (const struct frame_unwind
*self
,
2819 struct frame_info
*this_frame
,
2822 struct gdbarch_tdep
*tdep
= gdbarch_tdep (get_frame_arch (this_frame
));
2824 /* We shouldn't even bother if we don't have a sigcontext_addr
2826 if (tdep
->sigcontext_addr
== NULL
)
2829 if (tdep
->sigtramp_p
!= NULL
)
2831 if (tdep
->sigtramp_p (this_frame
))
2835 if (tdep
->sigtramp_start
!= 0)
2837 CORE_ADDR pc
= get_frame_pc (this_frame
);
2839 gdb_assert (tdep
->sigtramp_end
!= 0);
2840 if (pc
>= tdep
->sigtramp_start
&& pc
< tdep
->sigtramp_end
)
2847 static const struct frame_unwind amd64_sigtramp_frame_unwind
=
2850 amd64_sigtramp_frame_unwind_stop_reason
,
2851 amd64_sigtramp_frame_this_id
,
2852 amd64_sigtramp_frame_prev_register
,
2854 amd64_sigtramp_frame_sniffer
2859 amd64_frame_base_address (struct frame_info
*this_frame
, void **this_cache
)
2861 struct amd64_frame_cache
*cache
=
2862 amd64_frame_cache (this_frame
, this_cache
);
2867 static const struct frame_base amd64_frame_base
=
2869 &amd64_frame_unwind
,
2870 amd64_frame_base_address
,
2871 amd64_frame_base_address
,
2872 amd64_frame_base_address
2875 /* Normal frames, but in a function epilogue. */
2877 /* Implement the stack_frame_destroyed_p gdbarch method.
2879 The epilogue is defined here as the 'ret' instruction, which will
2880 follow any instruction such as 'leave' or 'pop %ebp' that destroys
2881 the function's stack frame. */
2884 amd64_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2887 struct compunit_symtab
*cust
;
2889 cust
= find_pc_compunit_symtab (pc
);
2890 if (cust
!= NULL
&& COMPUNIT_EPILOGUE_UNWIND_VALID (cust
))
2893 if (target_read_memory (pc
, &insn
, 1))
2894 return 0; /* Can't read memory at pc. */
2896 if (insn
!= 0xc3) /* 'ret' instruction. */
2903 amd64_epilogue_frame_sniffer (const struct frame_unwind
*self
,
2904 struct frame_info
*this_frame
,
2905 void **this_prologue_cache
)
2907 if (frame_relative_level (this_frame
) == 0)
2908 return amd64_stack_frame_destroyed_p (get_frame_arch (this_frame
),
2909 get_frame_pc (this_frame
));
2914 static struct amd64_frame_cache
*
2915 amd64_epilogue_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2917 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2918 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2919 struct amd64_frame_cache
*cache
;
2923 return (struct amd64_frame_cache
*) *this_cache
;
2925 cache
= amd64_alloc_frame_cache ();
2926 *this_cache
= cache
;
2930 /* Cache base will be %esp plus cache->sp_offset (-8). */
2931 get_frame_register (this_frame
, AMD64_RSP_REGNUM
, buf
);
2932 cache
->base
= extract_unsigned_integer (buf
, 8,
2933 byte_order
) + cache
->sp_offset
;
2935 /* Cache pc will be the frame func. */
2936 cache
->pc
= get_frame_pc (this_frame
);
2938 /* The saved %esp will be at cache->base plus 16. */
2939 cache
->saved_sp
= cache
->base
+ 16;
2941 /* The saved %eip will be at cache->base plus 8. */
2942 cache
->saved_regs
[AMD64_RIP_REGNUM
] = cache
->base
+ 8;
2946 catch (const gdb_exception_error
&ex
)
2948 if (ex
.error
!= NOT_AVAILABLE_ERROR
)
2955 static enum unwind_stop_reason
2956 amd64_epilogue_frame_unwind_stop_reason (struct frame_info
*this_frame
,
2959 struct amd64_frame_cache
*cache
2960 = amd64_epilogue_frame_cache (this_frame
, this_cache
);
2963 return UNWIND_UNAVAILABLE
;
2965 return UNWIND_NO_REASON
;
2969 amd64_epilogue_frame_this_id (struct frame_info
*this_frame
,
2971 struct frame_id
*this_id
)
2973 struct amd64_frame_cache
*cache
= amd64_epilogue_frame_cache (this_frame
,
2977 (*this_id
) = frame_id_build_unavailable_stack (cache
->pc
);
2979 (*this_id
) = frame_id_build (cache
->base
+ 8, cache
->pc
);
2982 static const struct frame_unwind amd64_epilogue_frame_unwind
=
2985 amd64_epilogue_frame_unwind_stop_reason
,
2986 amd64_epilogue_frame_this_id
,
2987 amd64_frame_prev_register
,
2989 amd64_epilogue_frame_sniffer
2992 static struct frame_id
2993 amd64_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
2997 fp
= get_frame_register_unsigned (this_frame
, AMD64_RBP_REGNUM
);
2999 return frame_id_build (fp
+ 16, get_frame_pc (this_frame
));
3002 /* 16 byte align the SP per frame requirements. */
3005 amd64_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR sp
)
3007 return sp
& -(CORE_ADDR
)16;
3011 /* Supply register REGNUM from the buffer specified by FPREGS and LEN
3012 in the floating-point register set REGSET to register cache
3013 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
3016 amd64_supply_fpregset (const struct regset
*regset
, struct regcache
*regcache
,
3017 int regnum
, const void *fpregs
, size_t len
)
3019 struct gdbarch
*gdbarch
= regcache
->arch ();
3020 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3022 gdb_assert (len
>= tdep
->sizeof_fpregset
);
3023 amd64_supply_fxsave (regcache
, regnum
, fpregs
);
3026 /* Collect register REGNUM from the register cache REGCACHE and store
3027 it in the buffer specified by FPREGS and LEN as described by the
3028 floating-point register set REGSET. If REGNUM is -1, do this for
3029 all registers in REGSET. */
3032 amd64_collect_fpregset (const struct regset
*regset
,
3033 const struct regcache
*regcache
,
3034 int regnum
, void *fpregs
, size_t len
)
3036 struct gdbarch
*gdbarch
= regcache
->arch ();
3037 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3039 gdb_assert (len
>= tdep
->sizeof_fpregset
);
3040 amd64_collect_fxsave (regcache
, regnum
, fpregs
);
3043 const struct regset amd64_fpregset
=
3045 NULL
, amd64_supply_fpregset
, amd64_collect_fpregset
3049 /* Figure out where the longjmp will land. Slurp the jmp_buf out of
3050 %rdi. We expect its value to be a pointer to the jmp_buf structure
3051 from which we extract the address that we will land at. This
3052 address is copied into PC. This routine returns non-zero on
3056 amd64_get_longjmp_target (struct frame_info
*frame
, CORE_ADDR
*pc
)
3060 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
3061 int jb_pc_offset
= gdbarch_tdep (gdbarch
)->jb_pc_offset
;
3062 int len
= TYPE_LENGTH (builtin_type (gdbarch
)->builtin_func_ptr
);
3064 /* If JB_PC_OFFSET is -1, we have no way to find out where the
3065 longjmp will land. */
3066 if (jb_pc_offset
== -1)
3069 get_frame_register (frame
, AMD64_RDI_REGNUM
, buf
);
3070 jb_addr
= extract_typed_address
3071 (buf
, builtin_type (gdbarch
)->builtin_data_ptr
);
3072 if (target_read_memory (jb_addr
+ jb_pc_offset
, buf
, len
))
3075 *pc
= extract_typed_address (buf
, builtin_type (gdbarch
)->builtin_func_ptr
);
3080 static const int amd64_record_regmap
[] =
3082 AMD64_RAX_REGNUM
, AMD64_RCX_REGNUM
, AMD64_RDX_REGNUM
, AMD64_RBX_REGNUM
,
3083 AMD64_RSP_REGNUM
, AMD64_RBP_REGNUM
, AMD64_RSI_REGNUM
, AMD64_RDI_REGNUM
,
3084 AMD64_R8_REGNUM
, AMD64_R9_REGNUM
, AMD64_R10_REGNUM
, AMD64_R11_REGNUM
,
3085 AMD64_R12_REGNUM
, AMD64_R13_REGNUM
, AMD64_R14_REGNUM
, AMD64_R15_REGNUM
,
3086 AMD64_RIP_REGNUM
, AMD64_EFLAGS_REGNUM
, AMD64_CS_REGNUM
, AMD64_SS_REGNUM
,
3087 AMD64_DS_REGNUM
, AMD64_ES_REGNUM
, AMD64_FS_REGNUM
, AMD64_GS_REGNUM
3090 /* Implement the "in_indirect_branch_thunk" gdbarch function. */
3093 amd64_in_indirect_branch_thunk (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
3095 return x86_in_indirect_branch_thunk (pc
, amd64_register_names
,
3101 amd64_init_abi (struct gdbarch_info info
, struct gdbarch
*gdbarch
,
3102 const target_desc
*default_tdesc
)
3104 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3105 const struct target_desc
*tdesc
= info
.target_desc
;
3106 static const char *const stap_integer_prefixes
[] = { "$", NULL
};
3107 static const char *const stap_register_prefixes
[] = { "%", NULL
};
3108 static const char *const stap_register_indirection_prefixes
[] = { "(",
3110 static const char *const stap_register_indirection_suffixes
[] = { ")",
3113 /* AMD64 generally uses `fxsave' instead of `fsave' for saving its
3114 floating-point registers. */
3115 tdep
->sizeof_fpregset
= I387_SIZEOF_FXSAVE
;
3116 tdep
->fpregset
= &amd64_fpregset
;
3118 if (! tdesc_has_registers (tdesc
))
3119 tdesc
= default_tdesc
;
3120 tdep
->tdesc
= tdesc
;
3122 tdep
->num_core_regs
= AMD64_NUM_GREGS
+ I387_NUM_REGS
;
3123 tdep
->register_names
= amd64_register_names
;
3125 if (tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.avx512") != NULL
)
3127 tdep
->zmmh_register_names
= amd64_zmmh_names
;
3128 tdep
->k_register_names
= amd64_k_names
;
3129 tdep
->xmm_avx512_register_names
= amd64_xmm_avx512_names
;
3130 tdep
->ymm16h_register_names
= amd64_ymmh_avx512_names
;
3132 tdep
->num_zmm_regs
= 32;
3133 tdep
->num_xmm_avx512_regs
= 16;
3134 tdep
->num_ymm_avx512_regs
= 16;
3136 tdep
->zmm0h_regnum
= AMD64_ZMM0H_REGNUM
;
3137 tdep
->k0_regnum
= AMD64_K0_REGNUM
;
3138 tdep
->xmm16_regnum
= AMD64_XMM16_REGNUM
;
3139 tdep
->ymm16h_regnum
= AMD64_YMM16H_REGNUM
;
3142 if (tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.avx") != NULL
)
3144 tdep
->ymmh_register_names
= amd64_ymmh_names
;
3145 tdep
->num_ymm_regs
= 16;
3146 tdep
->ymm0h_regnum
= AMD64_YMM0H_REGNUM
;
3149 if (tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.mpx") != NULL
)
3151 tdep
->mpx_register_names
= amd64_mpx_names
;
3152 tdep
->bndcfgu_regnum
= AMD64_BNDCFGU_REGNUM
;
3153 tdep
->bnd0r_regnum
= AMD64_BND0R_REGNUM
;
3156 if (tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.segments") != NULL
)
3158 tdep
->fsbase_regnum
= AMD64_FSBASE_REGNUM
;
3161 if (tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.pkeys") != NULL
)
3163 tdep
->pkeys_register_names
= amd64_pkeys_names
;
3164 tdep
->pkru_regnum
= AMD64_PKRU_REGNUM
;
3165 tdep
->num_pkeys_regs
= 1;
3168 tdep
->num_byte_regs
= 20;
3169 tdep
->num_word_regs
= 16;
3170 tdep
->num_dword_regs
= 16;
3171 /* Avoid wiring in the MMX registers for now. */
3172 tdep
->num_mmx_regs
= 0;
3174 set_gdbarch_pseudo_register_read_value (gdbarch
,
3175 amd64_pseudo_register_read_value
);
3176 set_gdbarch_pseudo_register_write (gdbarch
,
3177 amd64_pseudo_register_write
);
3178 set_gdbarch_ax_pseudo_register_collect (gdbarch
,
3179 amd64_ax_pseudo_register_collect
);
3181 set_tdesc_pseudo_register_name (gdbarch
, amd64_pseudo_register_name
);
3183 /* AMD64 has an FPU and 16 SSE registers. */
3184 tdep
->st0_regnum
= AMD64_ST0_REGNUM
;
3185 tdep
->num_xmm_regs
= 16;
3187 /* This is what all the fuss is about. */
3188 set_gdbarch_long_bit (gdbarch
, 64);
3189 set_gdbarch_long_long_bit (gdbarch
, 64);
3190 set_gdbarch_ptr_bit (gdbarch
, 64);
3192 /* In contrast to the i386, on AMD64 a `long double' actually takes
3193 up 128 bits, even though it's still based on the i387 extended
3194 floating-point format which has only 80 significant bits. */
3195 set_gdbarch_long_double_bit (gdbarch
, 128);
3197 set_gdbarch_num_regs (gdbarch
, AMD64_NUM_REGS
);
3199 /* Register numbers of various important registers. */
3200 set_gdbarch_sp_regnum (gdbarch
, AMD64_RSP_REGNUM
); /* %rsp */
3201 set_gdbarch_pc_regnum (gdbarch
, AMD64_RIP_REGNUM
); /* %rip */
3202 set_gdbarch_ps_regnum (gdbarch
, AMD64_EFLAGS_REGNUM
); /* %eflags */
3203 set_gdbarch_fp0_regnum (gdbarch
, AMD64_ST0_REGNUM
); /* %st(0) */
3205 /* The "default" register numbering scheme for AMD64 is referred to
3206 as the "DWARF Register Number Mapping" in the System V psABI.
3207 The preferred debugging format for all known AMD64 targets is
3208 actually DWARF2, and GCC doesn't seem to support DWARF (that is
3209 DWARF-1), but we provide the same mapping just in case. This
3210 mapping is also used for stabs, which GCC does support. */
3211 set_gdbarch_stab_reg_to_regnum (gdbarch
, amd64_dwarf_reg_to_regnum
);
3212 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, amd64_dwarf_reg_to_regnum
);
3214 /* We don't override SDB_REG_RO_REGNUM, since COFF doesn't seem to
3215 be in use on any of the supported AMD64 targets. */
3217 /* Call dummy code. */
3218 set_gdbarch_push_dummy_call (gdbarch
, amd64_push_dummy_call
);
3219 set_gdbarch_frame_align (gdbarch
, amd64_frame_align
);
3220 set_gdbarch_frame_red_zone_size (gdbarch
, 128);
3222 set_gdbarch_convert_register_p (gdbarch
, i387_convert_register_p
);
3223 set_gdbarch_register_to_value (gdbarch
, i387_register_to_value
);
3224 set_gdbarch_value_to_register (gdbarch
, i387_value_to_register
);
3226 set_gdbarch_return_value (gdbarch
, amd64_return_value
);
3228 set_gdbarch_skip_prologue (gdbarch
, amd64_skip_prologue
);
3230 tdep
->record_regmap
= amd64_record_regmap
;
3232 set_gdbarch_dummy_id (gdbarch
, amd64_dummy_id
);
3234 /* Hook the function epilogue frame unwinder. This unwinder is
3235 appended to the list first, so that it supercedes the other
3236 unwinders in function epilogues. */
3237 frame_unwind_prepend_unwinder (gdbarch
, &amd64_epilogue_frame_unwind
);
3239 /* Hook the prologue-based frame unwinders. */
3240 frame_unwind_append_unwinder (gdbarch
, &amd64_sigtramp_frame_unwind
);
3241 frame_unwind_append_unwinder (gdbarch
, &amd64_frame_unwind
);
3242 frame_base_set_default (gdbarch
, &amd64_frame_base
);
3244 set_gdbarch_get_longjmp_target (gdbarch
, amd64_get_longjmp_target
);
3246 set_gdbarch_relocate_instruction (gdbarch
, amd64_relocate_instruction
);
3248 set_gdbarch_gen_return_address (gdbarch
, amd64_gen_return_address
);
3250 /* SystemTap variables and functions. */
3251 set_gdbarch_stap_integer_prefixes (gdbarch
, stap_integer_prefixes
);
3252 set_gdbarch_stap_register_prefixes (gdbarch
, stap_register_prefixes
);
3253 set_gdbarch_stap_register_indirection_prefixes (gdbarch
,
3254 stap_register_indirection_prefixes
);
3255 set_gdbarch_stap_register_indirection_suffixes (gdbarch
,
3256 stap_register_indirection_suffixes
);
3257 set_gdbarch_stap_is_single_operand (gdbarch
,
3258 i386_stap_is_single_operand
);
3259 set_gdbarch_stap_parse_special_token (gdbarch
,
3260 i386_stap_parse_special_token
);
3261 set_gdbarch_insn_is_call (gdbarch
, amd64_insn_is_call
);
3262 set_gdbarch_insn_is_ret (gdbarch
, amd64_insn_is_ret
);
3263 set_gdbarch_insn_is_jump (gdbarch
, amd64_insn_is_jump
);
3265 set_gdbarch_in_indirect_branch_thunk (gdbarch
,
3266 amd64_in_indirect_branch_thunk
);
3269 /* Initialize ARCH for x86-64, no osabi. */
3272 amd64_none_init_abi (gdbarch_info info
, gdbarch
*arch
)
3274 amd64_init_abi (info
, arch
, amd64_target_description (X86_XSTATE_SSE_MASK
,
3278 static struct type
*
3279 amd64_x32_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
3281 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3283 switch (regnum
- tdep
->eax_regnum
)
3285 case AMD64_RBP_REGNUM
: /* %ebp */
3286 case AMD64_RSP_REGNUM
: /* %esp */
3287 return builtin_type (gdbarch
)->builtin_data_ptr
;
3288 case AMD64_RIP_REGNUM
: /* %eip */
3289 return builtin_type (gdbarch
)->builtin_func_ptr
;
3292 return i386_pseudo_register_type (gdbarch
, regnum
);
3296 amd64_x32_init_abi (struct gdbarch_info info
, struct gdbarch
*gdbarch
,
3297 const target_desc
*default_tdesc
)
3299 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3301 amd64_init_abi (info
, gdbarch
, default_tdesc
);
3303 tdep
->num_dword_regs
= 17;
3304 set_tdesc_pseudo_register_type (gdbarch
, amd64_x32_pseudo_register_type
);
3306 set_gdbarch_long_bit (gdbarch
, 32);
3307 set_gdbarch_ptr_bit (gdbarch
, 32);
3310 /* Initialize ARCH for x64-32, no osabi. */
3313 amd64_x32_none_init_abi (gdbarch_info info
, gdbarch
*arch
)
3315 amd64_x32_init_abi (info
, arch
,
3316 amd64_target_description (X86_XSTATE_SSE_MASK
, true));
3319 /* Return the target description for a specified XSAVE feature mask. */
3321 const struct target_desc
*
3322 amd64_target_description (uint64_t xcr0
, bool segments
)
3324 static target_desc
*amd64_tdescs \
3325 [2/*AVX*/][2/*MPX*/][2/*AVX512*/][2/*PKRU*/][2/*segments*/] = {};
3326 target_desc
**tdesc
;
3328 tdesc
= &amd64_tdescs
[(xcr0
& X86_XSTATE_AVX
) ? 1 : 0]
3329 [(xcr0
& X86_XSTATE_MPX
) ? 1 : 0]
3330 [(xcr0
& X86_XSTATE_AVX512
) ? 1 : 0]
3331 [(xcr0
& X86_XSTATE_PKRU
) ? 1 : 0]
3335 *tdesc
= amd64_create_target_description (xcr0
, false, false,
3342 _initialize_amd64_tdep (void)
3344 gdbarch_register_osabi (bfd_arch_i386
, bfd_mach_x86_64
, GDB_OSABI_NONE
,
3345 amd64_none_init_abi
);
3346 gdbarch_register_osabi (bfd_arch_i386
, bfd_mach_x64_32
, GDB_OSABI_NONE
,
3347 amd64_x32_none_init_abi
);
3351 /* The 64-bit FXSAVE format differs from the 32-bit format in the
3352 sense that the instruction pointer and data pointer are simply
3353 64-bit offsets into the code segment and the data segment instead
3354 of a selector offset pair. The functions below store the upper 32
3355 bits of these pointers (instead of just the 16-bits of the segment
3358 /* Fill register REGNUM in REGCACHE with the appropriate
3359 floating-point or SSE register value from *FXSAVE. If REGNUM is
3360 -1, do this for all registers. This function masks off any of the
3361 reserved bits in *FXSAVE. */
3364 amd64_supply_fxsave (struct regcache
*regcache
, int regnum
,
3367 struct gdbarch
*gdbarch
= regcache
->arch ();
3368 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3370 i387_supply_fxsave (regcache
, regnum
, fxsave
);
3373 && gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
== 64)
3375 const gdb_byte
*regs
= (const gdb_byte
*) fxsave
;
3377 if (regnum
== -1 || regnum
== I387_FISEG_REGNUM (tdep
))
3378 regcache
->raw_supply (I387_FISEG_REGNUM (tdep
), regs
+ 12);
3379 if (regnum
== -1 || regnum
== I387_FOSEG_REGNUM (tdep
))
3380 regcache
->raw_supply (I387_FOSEG_REGNUM (tdep
), regs
+ 20);
3384 /* Similar to amd64_supply_fxsave, but use XSAVE extended state. */
3387 amd64_supply_xsave (struct regcache
*regcache
, int regnum
,
3390 struct gdbarch
*gdbarch
= regcache
->arch ();
3391 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3393 i387_supply_xsave (regcache
, regnum
, xsave
);
3396 && gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
== 64)
3398 const gdb_byte
*regs
= (const gdb_byte
*) xsave
;
3401 clear_bv
= i387_xsave_get_clear_bv (gdbarch
, xsave
);
3403 /* If the FISEG and FOSEG registers have not been initialised yet
3404 (their CLEAR_BV bit is set) then their default values of zero will
3405 have already been setup by I387_SUPPLY_XSAVE. */
3406 if (!(clear_bv
& X86_XSTATE_X87
))
3408 if (regnum
== -1 || regnum
== I387_FISEG_REGNUM (tdep
))
3409 regcache
->raw_supply (I387_FISEG_REGNUM (tdep
), regs
+ 12);
3410 if (regnum
== -1 || regnum
== I387_FOSEG_REGNUM (tdep
))
3411 regcache
->raw_supply (I387_FOSEG_REGNUM (tdep
), regs
+ 20);
3416 /* Fill register REGNUM (if it is a floating-point or SSE register) in
3417 *FXSAVE with the value from REGCACHE. If REGNUM is -1, do this for
3418 all registers. This function doesn't touch any of the reserved
3422 amd64_collect_fxsave (const struct regcache
*regcache
, int regnum
,
3425 struct gdbarch
*gdbarch
= regcache
->arch ();
3426 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3427 gdb_byte
*regs
= (gdb_byte
*) fxsave
;
3429 i387_collect_fxsave (regcache
, regnum
, fxsave
);
3431 if (gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
== 64)
3433 if (regnum
== -1 || regnum
== I387_FISEG_REGNUM (tdep
))
3434 regcache
->raw_collect (I387_FISEG_REGNUM (tdep
), regs
+ 12);
3435 if (regnum
== -1 || regnum
== I387_FOSEG_REGNUM (tdep
))
3436 regcache
->raw_collect (I387_FOSEG_REGNUM (tdep
), regs
+ 20);
3440 /* Similar to amd64_collect_fxsave, but use XSAVE extended state. */
3443 amd64_collect_xsave (const struct regcache
*regcache
, int regnum
,
3444 void *xsave
, int gcore
)
3446 struct gdbarch
*gdbarch
= regcache
->arch ();
3447 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3448 gdb_byte
*regs
= (gdb_byte
*) xsave
;
3450 i387_collect_xsave (regcache
, regnum
, xsave
, gcore
);
3452 if (gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
== 64)
3454 if (regnum
== -1 || regnum
== I387_FISEG_REGNUM (tdep
))
3455 regcache
->raw_collect (I387_FISEG_REGNUM (tdep
),
3457 if (regnum
== -1 || regnum
== I387_FOSEG_REGNUM (tdep
))
3458 regcache
->raw_collect (I387_FOSEG_REGNUM (tdep
),