1 /* riscv.h. RISC-V opcode list for GDB, the GNU debugger.
2 Copyright (C) 2011-2020 Free Software Foundation, Inc.
3 Contributed by Andrew Waterman
5 This file is part of GDB, GAS, and the GNU binutils.
7 GDB, GAS, and the GNU binutils are free software; you can redistribute
8 them and/or modify them under the terms of the GNU General Public
9 License as published by the Free Software Foundation; either version
10 3, or (at your option) any later version.
12 GDB, GAS, and the GNU binutils are distributed in the hope that they
13 will be useful, but WITHOUT ANY WARRANTY; without even the implied
14 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
15 the GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; see the file COPYING3. If not,
19 see <http://www.gnu.org/licenses/>. */
24 #include "riscv-opc.h"
29 typedef uint64_t insn_t
;
31 static inline unsigned int riscv_insn_length (insn_t insn
)
33 if ((insn
& 0x3) != 0x3) /* RVC. */
35 if ((insn
& 0x1f) != 0x1f) /* Base ISA and extensions in 32-bit space. */
37 if ((insn
& 0x3f) == 0x1f) /* 48-bit extensions. */
39 if ((insn
& 0x7f) == 0x3f) /* 64-bit extensions. */
41 /* Longer instructions not supported at the moment. */
45 static const char * const riscv_rm
[8] =
47 "rne", "rtz", "rdn", "rup", "rmm", 0, 0, "dyn"
50 static const char * const riscv_pred_succ
[16] =
52 0, "w", "r", "rw", "o", "ow", "or", "orw",
53 "i", "iw", "ir", "irw", "io", "iow", "ior", "iorw"
56 #define RVC_JUMP_BITS 11
57 #define RVC_JUMP_REACH ((1ULL << RVC_JUMP_BITS) * RISCV_JUMP_ALIGN)
59 #define RVC_BRANCH_BITS 8
60 #define RVC_BRANCH_REACH ((1ULL << RVC_BRANCH_BITS) * RISCV_BRANCH_ALIGN)
62 #define RV_X(x, s, n) (((x) >> (s)) & ((1 << (n)) - 1))
63 #define RV_IMM_SIGN(x) (-(((x) >> 31) & 1))
65 #define EXTRACT_ITYPE_IMM(x) \
66 (RV_X(x, 20, 12) | (RV_IMM_SIGN(x) << 12))
67 #define EXTRACT_STYPE_IMM(x) \
68 (RV_X(x, 7, 5) | (RV_X(x, 25, 7) << 5) | (RV_IMM_SIGN(x) << 12))
69 #define EXTRACT_SBTYPE_IMM(x) \
70 ((RV_X(x, 8, 4) << 1) | (RV_X(x, 25, 6) << 5) | (RV_X(x, 7, 1) << 11) | (RV_IMM_SIGN(x) << 12))
71 #define EXTRACT_UTYPE_IMM(x) \
72 ((RV_X(x, 12, 20) << 12) | (RV_IMM_SIGN(x) << 32))
73 #define EXTRACT_UJTYPE_IMM(x) \
74 ((RV_X(x, 21, 10) << 1) | (RV_X(x, 20, 1) << 11) | (RV_X(x, 12, 8) << 12) | (RV_IMM_SIGN(x) << 20))
75 #define EXTRACT_RVC_IMM(x) \
76 (RV_X(x, 2, 5) | (-RV_X(x, 12, 1) << 5))
77 #define EXTRACT_RVC_LUI_IMM(x) \
78 (EXTRACT_RVC_IMM (x) << RISCV_IMM_BITS)
79 #define EXTRACT_RVC_SIMM3(x) \
80 (RV_X(x, 10, 2) | (-RV_X(x, 12, 1) << 2))
81 #define EXTRACT_RVC_UIMM8(x) \
83 #define EXTRACT_RVC_ADDI4SPN_IMM(x) \
84 ((RV_X(x, 6, 1) << 2) | (RV_X(x, 5, 1) << 3) | (RV_X(x, 11, 2) << 4) | (RV_X(x, 7, 4) << 6))
85 #define EXTRACT_RVC_ADDI16SP_IMM(x) \
86 ((RV_X(x, 6, 1) << 4) | (RV_X(x, 2, 1) << 5) | (RV_X(x, 5, 1) << 6) | (RV_X(x, 3, 2) << 7) | (-RV_X(x, 12, 1) << 9))
87 #define EXTRACT_RVC_LW_IMM(x) \
88 ((RV_X(x, 6, 1) << 2) | (RV_X(x, 10, 3) << 3) | (RV_X(x, 5, 1) << 6))
89 #define EXTRACT_RVC_LD_IMM(x) \
90 ((RV_X(x, 10, 3) << 3) | (RV_X(x, 5, 2) << 6))
91 #define EXTRACT_RVC_LWSP_IMM(x) \
92 ((RV_X(x, 4, 3) << 2) | (RV_X(x, 12, 1) << 5) | (RV_X(x, 2, 2) << 6))
93 #define EXTRACT_RVC_LDSP_IMM(x) \
94 ((RV_X(x, 5, 2) << 3) | (RV_X(x, 12, 1) << 5) | (RV_X(x, 2, 3) << 6))
95 #define EXTRACT_RVC_SWSP_IMM(x) \
96 ((RV_X(x, 9, 4) << 2) | (RV_X(x, 7, 2) << 6))
97 #define EXTRACT_RVC_SDSP_IMM(x) \
98 ((RV_X(x, 10, 3) << 3) | (RV_X(x, 7, 3) << 6))
99 #define EXTRACT_RVC_B_IMM(x) \
100 ((RV_X(x, 3, 2) << 1) | (RV_X(x, 10, 2) << 3) | (RV_X(x, 2, 1) << 5) | (RV_X(x, 5, 2) << 6) | (-RV_X(x, 12, 1) << 8))
101 #define EXTRACT_RVC_J_IMM(x) \
102 ((RV_X(x, 3, 3) << 1) | (RV_X(x, 11, 1) << 4) | (RV_X(x, 2, 1) << 5) | (RV_X(x, 7, 1) << 6) | (RV_X(x, 6, 1) << 7) | (RV_X(x, 9, 2) << 8) | (RV_X(x, 8, 1) << 10) | (-RV_X(x, 12, 1) << 11))
104 #define ENCODE_ITYPE_IMM(x) \
105 (RV_X(x, 0, 12) << 20)
106 #define ENCODE_STYPE_IMM(x) \
107 ((RV_X(x, 0, 5) << 7) | (RV_X(x, 5, 7) << 25))
108 #define ENCODE_SBTYPE_IMM(x) \
109 ((RV_X(x, 1, 4) << 8) | (RV_X(x, 5, 6) << 25) | (RV_X(x, 11, 1) << 7) | (RV_X(x, 12, 1) << 31))
110 #define ENCODE_UTYPE_IMM(x) \
111 (RV_X(x, 12, 20) << 12)
112 #define ENCODE_UJTYPE_IMM(x) \
113 ((RV_X(x, 1, 10) << 21) | (RV_X(x, 11, 1) << 20) | (RV_X(x, 12, 8) << 12) | (RV_X(x, 20, 1) << 31))
114 #define ENCODE_RVC_IMM(x) \
115 ((RV_X(x, 0, 5) << 2) | (RV_X(x, 5, 1) << 12))
116 #define ENCODE_RVC_LUI_IMM(x) \
117 ENCODE_RVC_IMM ((x) >> RISCV_IMM_BITS)
118 #define ENCODE_RVC_SIMM3(x) \
119 (RV_X(x, 0, 3) << 10)
120 #define ENCODE_RVC_UIMM8(x) \
122 #define ENCODE_RVC_ADDI4SPN_IMM(x) \
123 ((RV_X(x, 2, 1) << 6) | (RV_X(x, 3, 1) << 5) | (RV_X(x, 4, 2) << 11) | (RV_X(x, 6, 4) << 7))
124 #define ENCODE_RVC_ADDI16SP_IMM(x) \
125 ((RV_X(x, 4, 1) << 6) | (RV_X(x, 5, 1) << 2) | (RV_X(x, 6, 1) << 5) | (RV_X(x, 7, 2) << 3) | (RV_X(x, 9, 1) << 12))
126 #define ENCODE_RVC_LW_IMM(x) \
127 ((RV_X(x, 2, 1) << 6) | (RV_X(x, 3, 3) << 10) | (RV_X(x, 6, 1) << 5))
128 #define ENCODE_RVC_LD_IMM(x) \
129 ((RV_X(x, 3, 3) << 10) | (RV_X(x, 6, 2) << 5))
130 #define ENCODE_RVC_LWSP_IMM(x) \
131 ((RV_X(x, 2, 3) << 4) | (RV_X(x, 5, 1) << 12) | (RV_X(x, 6, 2) << 2))
132 #define ENCODE_RVC_LDSP_IMM(x) \
133 ((RV_X(x, 3, 2) << 5) | (RV_X(x, 5, 1) << 12) | (RV_X(x, 6, 3) << 2))
134 #define ENCODE_RVC_SWSP_IMM(x) \
135 ((RV_X(x, 2, 4) << 9) | (RV_X(x, 6, 2) << 7))
136 #define ENCODE_RVC_SDSP_IMM(x) \
137 ((RV_X(x, 3, 3) << 10) | (RV_X(x, 6, 3) << 7))
138 #define ENCODE_RVC_B_IMM(x) \
139 ((RV_X(x, 1, 2) << 3) | (RV_X(x, 3, 2) << 10) | (RV_X(x, 5, 1) << 2) | (RV_X(x, 6, 2) << 5) | (RV_X(x, 8, 1) << 12))
140 #define ENCODE_RVC_J_IMM(x) \
141 ((RV_X(x, 1, 3) << 3) | (RV_X(x, 4, 1) << 11) | (RV_X(x, 5, 1) << 2) | (RV_X(x, 6, 1) << 7) | (RV_X(x, 7, 1) << 6) | (RV_X(x, 8, 2) << 9) | (RV_X(x, 10, 1) << 8) | (RV_X(x, 11, 1) << 12))
143 #define VALID_ITYPE_IMM(x) (EXTRACT_ITYPE_IMM(ENCODE_ITYPE_IMM(x)) == (x))
144 #define VALID_STYPE_IMM(x) (EXTRACT_STYPE_IMM(ENCODE_STYPE_IMM(x)) == (x))
145 #define VALID_SBTYPE_IMM(x) (EXTRACT_SBTYPE_IMM(ENCODE_SBTYPE_IMM(x)) == (x))
146 #define VALID_UTYPE_IMM(x) (EXTRACT_UTYPE_IMM(ENCODE_UTYPE_IMM(x)) == (x))
147 #define VALID_UJTYPE_IMM(x) (EXTRACT_UJTYPE_IMM(ENCODE_UJTYPE_IMM(x)) == (x))
148 #define VALID_RVC_IMM(x) (EXTRACT_RVC_IMM(ENCODE_RVC_IMM(x)) == (x))
149 #define VALID_RVC_LUI_IMM(x) (ENCODE_RVC_LUI_IMM(x) != 0 && EXTRACT_RVC_LUI_IMM(ENCODE_RVC_LUI_IMM(x)) == (x))
150 #define VALID_RVC_SIMM3(x) (EXTRACT_RVC_SIMM3(ENCODE_RVC_SIMM3(x)) == (x))
151 #define VALID_RVC_UIMM8(x) (EXTRACT_RVC_UIMM8(ENCODE_RVC_UIMM8(x)) == (x))
152 #define VALID_RVC_ADDI4SPN_IMM(x) (EXTRACT_RVC_ADDI4SPN_IMM(ENCODE_RVC_ADDI4SPN_IMM(x)) == (x))
153 #define VALID_RVC_ADDI16SP_IMM(x) (EXTRACT_RVC_ADDI16SP_IMM(ENCODE_RVC_ADDI16SP_IMM(x)) == (x))
154 #define VALID_RVC_LW_IMM(x) (EXTRACT_RVC_LW_IMM(ENCODE_RVC_LW_IMM(x)) == (x))
155 #define VALID_RVC_LD_IMM(x) (EXTRACT_RVC_LD_IMM(ENCODE_RVC_LD_IMM(x)) == (x))
156 #define VALID_RVC_LWSP_IMM(x) (EXTRACT_RVC_LWSP_IMM(ENCODE_RVC_LWSP_IMM(x)) == (x))
157 #define VALID_RVC_LDSP_IMM(x) (EXTRACT_RVC_LDSP_IMM(ENCODE_RVC_LDSP_IMM(x)) == (x))
158 #define VALID_RVC_SWSP_IMM(x) (EXTRACT_RVC_SWSP_IMM(ENCODE_RVC_SWSP_IMM(x)) == (x))
159 #define VALID_RVC_SDSP_IMM(x) (EXTRACT_RVC_SDSP_IMM(ENCODE_RVC_SDSP_IMM(x)) == (x))
160 #define VALID_RVC_B_IMM(x) (EXTRACT_RVC_B_IMM(ENCODE_RVC_B_IMM(x)) == (x))
161 #define VALID_RVC_J_IMM(x) (EXTRACT_RVC_J_IMM(ENCODE_RVC_J_IMM(x)) == (x))
163 #define RISCV_RTYPE(insn, rd, rs1, rs2) \
164 ((MATCH_ ## insn) | ((rd) << OP_SH_RD) | ((rs1) << OP_SH_RS1) | ((rs2) << OP_SH_RS2))
165 #define RISCV_ITYPE(insn, rd, rs1, imm) \
166 ((MATCH_ ## insn) | ((rd) << OP_SH_RD) | ((rs1) << OP_SH_RS1) | ENCODE_ITYPE_IMM(imm))
167 #define RISCV_STYPE(insn, rs1, rs2, imm) \
168 ((MATCH_ ## insn) | ((rs1) << OP_SH_RS1) | ((rs2) << OP_SH_RS2) | ENCODE_STYPE_IMM(imm))
169 #define RISCV_SBTYPE(insn, rs1, rs2, target) \
170 ((MATCH_ ## insn) | ((rs1) << OP_SH_RS1) | ((rs2) << OP_SH_RS2) | ENCODE_SBTYPE_IMM(target))
171 #define RISCV_UTYPE(insn, rd, bigimm) \
172 ((MATCH_ ## insn) | ((rd) << OP_SH_RD) | ENCODE_UTYPE_IMM(bigimm))
173 #define RISCV_UJTYPE(insn, rd, target) \
174 ((MATCH_ ## insn) | ((rd) << OP_SH_RD) | ENCODE_UJTYPE_IMM(target))
176 #define RISCV_NOP RISCV_ITYPE(ADDI, 0, 0, 0)
177 #define RVC_NOP MATCH_C_ADDI
179 #define RISCV_CONST_HIGH_PART(VALUE) \
180 (((VALUE) + (RISCV_IMM_REACH/2)) & ~(RISCV_IMM_REACH-1))
181 #define RISCV_CONST_LOW_PART(VALUE) ((VALUE) - RISCV_CONST_HIGH_PART (VALUE))
182 #define RISCV_PCREL_HIGH_PART(VALUE, PC) RISCV_CONST_HIGH_PART((VALUE) - (PC))
183 #define RISCV_PCREL_LOW_PART(VALUE, PC) RISCV_CONST_LOW_PART((VALUE) - (PC))
185 #define RISCV_JUMP_BITS RISCV_BIGIMM_BITS
186 #define RISCV_JUMP_ALIGN_BITS 1
187 #define RISCV_JUMP_ALIGN (1 << RISCV_JUMP_ALIGN_BITS)
188 #define RISCV_JUMP_REACH ((1ULL << RISCV_JUMP_BITS) * RISCV_JUMP_ALIGN)
190 #define RISCV_IMM_BITS 12
191 #define RISCV_BIGIMM_BITS (32 - RISCV_IMM_BITS)
192 #define RISCV_IMM_REACH (1LL << RISCV_IMM_BITS)
193 #define RISCV_BIGIMM_REACH (1LL << RISCV_BIGIMM_BITS)
194 #define RISCV_RVC_IMM_REACH (1LL << 6)
195 #define RISCV_BRANCH_BITS RISCV_IMM_BITS
196 #define RISCV_BRANCH_ALIGN_BITS RISCV_JUMP_ALIGN_BITS
197 #define RISCV_BRANCH_ALIGN (1 << RISCV_BRANCH_ALIGN_BITS)
198 #define RISCV_BRANCH_REACH (RISCV_IMM_REACH * RISCV_BRANCH_ALIGN)
202 #define OP_MASK_OP 0x7f
204 #define OP_MASK_RS2 0x1f
206 #define OP_MASK_RS1 0x1f
208 #define OP_MASK_RS3 0x1f
210 #define OP_MASK_RD 0x1f
212 #define OP_MASK_SHAMT 0x3f
213 #define OP_SH_SHAMT 20
214 #define OP_MASK_SHAMTW 0x1f
215 #define OP_SH_SHAMTW 20
216 #define OP_MASK_RM 0x7
218 #define OP_MASK_PRED 0xf
219 #define OP_SH_PRED 24
220 #define OP_MASK_SUCC 0xf
221 #define OP_SH_SUCC 20
222 #define OP_MASK_AQ 0x1
224 #define OP_MASK_RL 0x1
227 #define OP_MASK_CUSTOM_IMM 0x7f
228 #define OP_SH_CUSTOM_IMM 25
229 #define OP_MASK_CSR 0xfff
232 #define OP_MASK_FUNCT3 0x7
233 #define OP_SH_FUNCT3 12
234 #define OP_MASK_FUNCT7 0x7f
235 #define OP_SH_FUNCT7 25
236 #define OP_MASK_FUNCT2 0x3
237 #define OP_SH_FUNCT2 25
241 #define OP_MASK_OP2 0x3
244 #define OP_MASK_CRS2 0x1f
246 #define OP_MASK_CRS1S 0x7
247 #define OP_SH_CRS1S 7
248 #define OP_MASK_CRS2S 0x7
249 #define OP_SH_CRS2S 2
251 #define OP_MASK_CFUNCT6 0x3f
252 #define OP_SH_CFUNCT6 10
253 #define OP_MASK_CFUNCT4 0xf
254 #define OP_SH_CFUNCT4 12
255 #define OP_MASK_CFUNCT3 0x7
256 #define OP_SH_CFUNCT3 13
257 #define OP_MASK_CFUNCT2 0x3
258 #define OP_SH_CFUNCT2 5
260 /* ABI names for selected x-registers. */
274 /* These fake label defines are use by both the assembler, and
275 libopcodes. The assembler uses this when it needs to generate a fake
276 label, and libopcodes uses it to hide the fake labels in its output. */
277 #define RISCV_FAKE_LABEL_NAME ".L0 "
278 #define RISCV_FAKE_LABEL_CHAR ' '
280 /* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in
281 VALUE << SHIFT. VALUE is evaluated exactly once. */
282 #define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \
283 (STRUCT) = (((STRUCT) & ~((insn_t)(MASK) << (SHIFT))) \
284 | ((insn_t)((VALUE) & (MASK)) << (SHIFT)))
286 /* Extract bits MASK << SHIFT from STRUCT and shift them right
288 #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
289 (((STRUCT) >> (SHIFT)) & (MASK))
291 /* Extract the operand given by FIELD from integer INSN. */
292 #define EXTRACT_OPERAND(FIELD, INSN) \
293 EXTRACT_BITS ((INSN), OP_MASK_##FIELD, OP_SH_##FIELD)
295 /* The maximal number of subset can be required. */
296 #define MAX_SUBSET_NUM 4
298 /* All RISC-V instructions belong to at least one of these classes. */
300 enum riscv_insn_class
315 /* This structure holds information for a particular instruction. */
319 /* The name of the instruction. */
321 /* The requirement of xlen for the instruction, 0 if no requirement. */
322 unsigned xlen_requirement
;
323 /* Class to which this instruction belongs. Used to decide whether or
324 not this instruction is legal in the current -march context. */
325 enum riscv_insn_class insn_class
;
326 /* A string describing the arguments for this instruction. */
328 /* The basic opcode for the instruction. When assembling, this
329 opcode is modified by the arguments to produce the actual opcode
330 that is used. If pinfo is INSN_MACRO, then this is 0. */
332 /* If pinfo is not INSN_MACRO, then this is a bit mask for the
333 relevant portions of the opcode when disassembling. If the
334 actual opcode anded with the match field equals the opcode field,
335 then we have found the correct instruction. If pinfo is
336 INSN_MACRO, then this field is the macro identifier. */
338 /* A function to determine if a word corresponds to this instruction.
339 Usually, this computes ((word & mask) == match). */
340 int (*match_func
) (const struct riscv_opcode
*op
, insn_t word
);
341 /* For a macro, this is INSN_MACRO. Otherwise, it is a collection
342 of bits describing the instruction, notably any relevant hazard
347 /* The current supported ISA spec versions. */
349 enum riscv_isa_spec_class
354 ISA_SPEC_CLASS_20190608
,
355 ISA_SPEC_CLASS_20191213
358 /* This structure holds version information for specific ISA. */
360 struct riscv_ext_version
363 enum riscv_isa_spec_class isa_spec_class
;
364 unsigned int major_version
;
365 unsigned int minor_version
;
368 /* All RISC-V CSR belong to one of these classes. */
375 CSR_CLASS_I_32
, /* rv32 only */
376 CSR_CLASS_F
, /* f-ext only */
379 /* The current supported privilege spec versions. */
381 enum riscv_priv_spec_class
383 PRIV_SPEC_CLASS_NONE
,
386 PRIV_SPEC_CLASS_1P9P1
,
387 PRIV_SPEC_CLASS_1P10
,
388 PRIV_SPEC_CLASS_1P11
,
389 PRIV_SPEC_CLASS_DRAFT
392 /* This structure holds all restricted conditions for a CSR. */
394 struct riscv_csr_extra
396 /* Class to which this CSR belongs. Used to decide whether or
397 not this CSR is legal in the current -march context. */
398 enum riscv_csr_class csr_class
;
400 /* CSR may have differnet numbers in the previous priv spec. */
403 /* Record the CSR is defined/valid in which versions. */
404 enum riscv_priv_spec_class define_version
;
406 /* Record the CSR is aborted/invalid from which versions. If it isn't
407 aborted in the current version, then it should be CSR_CLASS_VDRAFT. */
408 enum riscv_priv_spec_class abort_version
;
410 /* The CSR may have more than one setting. */
411 struct riscv_csr_extra
*next
;
414 /* Instruction is a simple alias (e.g. "mv" for "addi"). */
415 #define INSN_ALIAS 0x00000001
417 /* These are for setting insn_info fields.
419 Nonbranch is the default. Noninsn is used only if there is no match.
420 There are no condjsr or dref2 instructions. So that leaves condbranch,
421 branch, jsr, and dref that we need to handle here, encoded in 3 bits. */
422 #define INSN_TYPE 0x0000000e
424 /* Instruction is an unconditional branch. */
425 #define INSN_BRANCH 0x00000002
426 /* Instruction is a conditional branch. */
427 #define INSN_CONDBRANCH 0x00000004
428 /* Instruction is a jump to subroutine. */
429 #define INSN_JSR 0x00000006
430 /* Instruction is a data reference. */
431 #define INSN_DREF 0x00000008
433 /* We have 5 data reference sizes, which we can encode in 3 bits. */
434 #define INSN_DATA_SIZE 0x00000070
435 #define INSN_DATA_SIZE_SHIFT 4
436 #define INSN_1_BYTE 0x00000010
437 #define INSN_2_BYTE 0x00000020
438 #define INSN_4_BYTE 0x00000030
439 #define INSN_8_BYTE 0x00000040
440 #define INSN_16_BYTE 0x00000050
442 /* Instruction is actually a macro. It should be ignored by the
443 disassembler, and requires special treatment by the assembler. */
444 #define INSN_MACRO 0xffffffff
446 /* This is a list of macro expanded instructions.
448 _I appended means immediate
449 _A appended means address
450 _AB appended means address with base register
451 _D appended means 64 bit floating point constant
452 _S appended means 32 bit floating point constant. */
484 extern const char * const riscv_gpr_names_numeric
[NGPR
];
485 extern const char * const riscv_gpr_names_abi
[NGPR
];
486 extern const char * const riscv_fpr_names_numeric
[NFPR
];
487 extern const char * const riscv_fpr_names_abi
[NFPR
];
489 extern const struct riscv_opcode riscv_opcodes
[];
490 extern const struct riscv_opcode riscv_insn_types
[];
491 extern const struct riscv_ext_version riscv_ext_version_table
[];
494 riscv_get_isa_spec_class (const char *, enum riscv_isa_spec_class
*);
496 riscv_get_priv_spec_class (const char *, enum riscv_priv_spec_class
*);
498 riscv_get_priv_spec_name (enum riscv_priv_spec_class
);
500 #endif /* _RISCV_H_ */