opcodes/ChangeLog

   1 2020-07-06  Jan Beulich  <jbeulich@suse.com>
   2
   3         * i386-dis.c (PREFIX_EVEX_0F3A1D, EVEX_W_0F3A1D_P_2): Delete.
   4         (VEX_W_0F3813_P_2, VEX_W_0F3A1D_P_2): New enumerators.
   5         (prefix_table): Reference VEX_W_0F3813_P_2 and VEX_W_0F3A1D_P_2
   6         respectively.
   7         (vex_w_table): New VEX_W_0F3813_P_2 and VEX_W_0F3A1D_P_2 table
   8         entries.
   9         * i386-dis-evex.h (evex_table): Reference VEX table entry for
  10         opcode 0F3A1D.
  11         * i386-dis-evex-prefix.h (PREFIX_EVEX_0F3A1D): Delete table
  12         entry.
  13         * i386-dis-evex-w.h (EVEX_W_0F3A1D_P_2): Likewise.
  14
  15 2020-07-06  Jan Beulich  <jbeulich@suse.com>
  16
  17         * i386-dis.c (PREFIX_EVEX_0F60, PREFIX_EVEX_0F61,
  18         PREFIX_EVEX_0F63, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
  19         PREFIX_EVEX_0F69, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5,
  20         PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA,
  21         PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
  22         PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3,
  23         PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8,
  24         PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC,
  25         PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
  26         PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8,
  27         PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD,
  28         PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B,
  29         PREFIX_EVEX_0F380C, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F381C,
  30         PREFIX_EVEX_0F381D, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E,
  31         PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879,
  32         PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898,
  33         PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D,
  34         PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A6,
  35         PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9,
  36         PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE,
  37         PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7,
  38         PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA,
  39         PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD,
  40         PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38CF,
  41         PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, PREFIX_EVEX_0F38DE,
  42         PREFIX_EVEX_0F38DF, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A0F,
  43         PREFIX_EVEX_0F3A44, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF,
  44         EVEX_W_0F380C_P_2, EVEX_W_0F3818_P_2, EVEX_W_0F3858_P_2,
  45         EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2, EVEX_W_0F3A04_P_2,
  46         EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2): Delete.
  47         (prefix_table): Add EXxEVexR to FMA table entries.
  48         (OP_Rounding): Move abort() invocation.
  49         * i386-dis-evex.h (evex_table): Reference VEX table for opcodes
  50         0F60, 0F61, 0F63, 0F67, 0F68, 0F69, 0FD1, 0FD5, 0FD8, 0FD9,
  51         0FDA, 0FDC, 0FDD, 0FDE, 0FE0, 0FE1, 0FE3, 0FE4, 0FE5, 0FE8,
  52         0FE9, 0FEA, 0FEC, 0FED, 0FEE, 0FF1, 0FF5, 0FF6, 0FF8, 0FF9,
  53         0FFC, 0FFD, 0F3800, 0F3804, 0F380B, 0F380C, 0F3818, 0F381C,
  54         0F381D, 0F383C, 0F383E, 0F3858, 0F3878, 0F3879, 0F3896, 0F3897,
  55         0F3898, 0F3899, 0F389C, 0F389D, 0F389E, 0F389F, 0F38A6, 0F38A7,
  56         0F38A8, 0F38A9, 0F38AC, 0F38AD, 0F38AE, 0F38AF, 0F38B6, 0F38B7,
  57         0F38B8, 0F38B9, 0F38BA, 0F38BB, 0F38BC, 0F38BD, 0F38BE, 0F38BF,
  58         0F38CF, 0F38DC, 0F38DD, 0F38DE, 0F38DF, 0F3A04, 0F3A0F, 0F3A44,
  59         0F3ACE, 0F3ACF.
  60         * i386-dis-evex-prefix.h (PREFIX_EVEX_0F60, PREFIX_EVEX_0F61,
  61         PREFIX_EVEX_0F63, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
  62         PREFIX_EVEX_0F69, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5,
  63         PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA,
  64         PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
  65         PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3,
  66         PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8,
  67         PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC,
  68         PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
  69         PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8,
  70         PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD,
  71         PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B,
  72         PREFIX_EVEX_0F380C, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F381C,
  73         PREFIX_EVEX_0F381D, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E,
  74         PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879,
  75         PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898,
  76         PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D,
  77         PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A6,
  78         PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9,
  79         PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE,
  80         PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7,
  81         PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA,
  82         PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD,
  83         PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38CF,
  84         PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, PREFIX_EVEX_0F38DE,
  85         PREFIX_EVEX_0F38DF, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A0F,
  86         PREFIX_EVEX_0F3A44, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF):
  87         Delete table entries.
  88         * i386-dis-evex-w.h (EVEX_W_0F380C_P_2, EVEX_W_0F3818_P_2,
  89         EVEX_W_0F3858_P_2, EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2,
  90         EVEX_W_0F3A04_P_2, EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2):
  91         Likewise.
  92
  93 2020-07-06  Jan Beulich  <jbeulich@suse.com>
  94
  95         * i386-dis.c (EXqScalarS): Delete.
  96         (vex_len_table): Replace EXqScalarS by EXqVexScalarS.
  97         * i386-dis-evex-w.h (vmovq): Use EXqVexScalarS.
  98
  99 2020-07-06  Jan Beulich  <jbeulich@suse.com>
 100
 101         * i386-dis.c (safe-ctype.h): Include.
 102         (EXdScalar, EXqScalar): Delete.
 103         (d_scalar_mode, q_scalar_mode): Delete.
 104         (prefix_table, vex_len_table): Use EXxmm_md in place of
 105         EXdScalar and EXxmm_mq in place of EXqScalar.
 106         (intel_operand_size, OP_E_memory, OP_EX): Remove uses of
 107         d_scalar_mode and q_scalar_mode.
 108         * i386-dis-evex-w.h (vmovss): Use EXxmm_md.
 109         (vmovsd): Use EXxmm_mq.
 110
 111 2020-07-06  Yuri Chornoivan  <yurchor@ukr.net>
 112
 113         PR 26204
 114         * arc-dis.c: Fix spelling mistake.
 115         * po/opcodes.pot: Regenerate.
 116
 117 2020-07-06  Nick Clifton  <nickc@redhat.com>
 118
 119         * po/pt_BR.po: Updated Brazilian Portugugese translation.
 120         * po/uk.po: Updated Ukranian translation.
 121
 122 2020-07-04  Nick Clifton  <nickc@redhat.com>
 123
 124         * configure: Regenerate.
 125         * po/opcodes.pot: Regenerate.
 126
 127 2020-07-04  Nick Clifton  <nickc@redhat.com>
 128
 129         Binutils 2.35 branch created.
 130
 131 2020-07-02  H.J. Lu  <hongjiu.lu@intel.com>
 132
 133         * i386-gen.c (opcode_modifiers): Add VexSwapSources.
 134         * i386-opc.h (VexSwapSources): New.
 135         (i386_opcode_modifier): Add vexswapsources.
 136         * i386-opc.tbl: Add VexSwapSources to BMI2 and BMI instructions
 137         with two source operands swapped.
 138         * i386-tbl.h: Regenerated.
 139
 140 2020-06-30  Nelson Chu  <nelson.chu@sifive.com>
 141
 142         * riscv-dis.c (print_insn_args, case 'E'): Updated.  Let the
 143         unprivileged CSR can also be initialized.
 144
 145 2020-06-29  Alan Modra  <amodra@gmail.com>
 146
 147         * arm-dis.c: Use C style comments.
 148         * cr16-opc.c: Likewise.
 149         * ft32-dis.c: Likewise.
 150         * moxie-opc.c: Likewise.
 151         * tic54x-dis.c: Likewise.
 152         * s12z-opc.c: Remove useless comment.
 153         * xgate-dis.c: Likewise.
 154
 155 2020-06-26  H.J. Lu  <hongjiu.lu@intel.com>
 156
 157         * i386-opc.tbl: Add a blank line.
 158
 159 2020-06-26  H.J. Lu  <hongjiu.lu@intel.com>
 160
 161         * i386-gen.c (opcode_modifiers): Replace VecSIB with SIB.
 162         (VecSIB128): Renamed to ...
 163         (VECSIB128): This.
 164         (VecSIB256): Renamed to ...
 165         (VECSIB256): This.
 166         (VecSIB512): Renamed to ...
 167         (VECSIB512): This.
 168         (VecSIB): Renamed to ...
 169         (SIB): This.
 170         (i386_opcode_modifier): Replace vecsib with sib.
 171         * i386-opc.tbl (VecSIB128): New.
 172         (VecSIB256): Likewise.
 173         (VecSIB512): Likewise.
 174         Replace VecSIB=1, VecSIB=2 and VecSIB=3 with VecSIB128, VecSIB256
 175         and VecSIB512, respectively.
 176
 177 2020-06-26  Jan Beulich  <jbeulich@suse.com>
 178
 179         * i386-dis.c: Adjust description of I macro.
 180         (x86_64_table): Drop use of I.
 181         (float_mem): Replace use of I.
 182         (putop): Remove handling of I. Adjust setting/clearing of "alt".
 183
 184 2020-06-26  Jan Beulich  <jbeulich@suse.com>
 185
 186         * i386-dis.c: (print_insn): Avoid straight assignment to
 187         priv.orig_sizeflag when processing -M sub-options.
 188
 189 2020-06-25  Jan Beulich  <jbeulich@suse.com>
 190
 191         * i386-dis.c: Adjust description of J macro.
 192         (dis386, x86_64_table, mod_table): Replace J.
 193         (putop): Remove handling of J.
 194
 195 2020-06-25  Jan Beulich  <jbeulich@suse.com>
 196
 197         * i386-dis.c: (float_mem): Reduce alternatives for fstpt and fldpt.
 198
 199 2020-06-25  Jan Beulich  <jbeulich@suse.com>
 200
 201         * i386-dis.c: Adjust description of "LQ" macro.
 202         (dis386_twobyte): Use LQ for sysret.
 203         (putop): Adjust handling of LQ.
 204
 205 2020-06-22  Nelson Chu  <nelson.chu@sifive.com>
 206
 207         * riscv-opc.c: Move the structures and functions to bfd/elfxx-riscv.c.
 208         * riscv-dis.c: Include elfxx-riscv.h.
 209
 210 2020-06-18  H.J. Lu  <hongjiu.lu@intel.com>
 211
 212         * i386-dis.c (prefix_table): Revert the last vmgexit change.
 213
 214 2020-06-17  Lili Cui  <lili.cui@intel.com>
 215
 216         * i386-dis.c (prefix_table): Delete the incorrect vmgexit.
 217
 218 2020-06-14  H.J. Lu  <hongjiu.lu@intel.com>
 219
 220         PR gas/26115
 221         * i386-dis.c (prefix_table): Replace xsuspldtrk with xsusldtrk.
 222         * i386-opc.tbl: Likewise.
 223         * i386-tbl.h: Regenerated.
 224
 225 2020-06-12  Nelson Chu  <nelson.chu@sifive.com>
 226
 227         * riscv-opc.c (priv_specs): Remove v1.9 and PRIV_SPEC_CLASS_1P9.
 228
 229 2020-06-11  Alex Coplan  <alex.coplan@arm.com>
 230
 231         * aarch64-opc.c (SYSREG): New macro for describing system registers.
 232         (SR_CORE): Likewise.
 233         (SR_FEAT): Likewise.
 234         (SR_RNG): Likewise.
 235         (SR_V8_1): Likewise.
 236         (SR_V8_2): Likewise.
 237         (SR_V8_3): Likewise.
 238         (SR_V8_4): Likewise.
 239         (SR_PAN): Likewise.
 240         (SR_RAS): Likewise.
 241         (SR_SSBS): Likewise.
 242         (SR_SVE): Likewise.
 243         (SR_ID_PFR2): Likewise.
 244         (SR_PROFILE): Likewise.
 245         (SR_MEMTAG): Likewise.
 246         (SR_SCXTNUM): Likewise.
 247         (aarch64_sys_regs): Refactor to store feature information in the table.
 248         (aarch64_sys_reg_supported_p): Collapse logic for system registers
 249         that now describe their own features.
 250         (aarch64_pstatefield_supported_p): Likewise.
 251
 252 2020-06-09  H.J. Lu  <hongjiu.lu@intel.com>
 253
 254         * i386-dis.c (prefix_table): Fix a typo in comments.
 255
 256 2020-06-09  Jan Beulich  <jbeulich@suse.com>
 257
 258         * i386-dis.c (rex_ignored): Delete.
 259         (ckprefix): Drop rex_ignored initialization.
 260         (get_valid_dis386): Drop setting of rex_ignored.
 261         (print_insn): Drop checking of rex_ignored. Don't record data
 262         size prefix as used with VEX-and-alike encodings.
 263
 264 2020-06-09  Jan Beulich  <jbeulich@suse.com>
 265
 266         * i386-dis.c (MOD_0F12_PREFIX_2, MOD_0F16_PREFIX_2,
 267         MOD_VEX_0F12_PREFIX_2, MOD_VEX_0F16_PREFIX_2): New enumerators.
 268         (VEX_LEN_0F12_P_2, VEX_LEN_0F16_P_2): Delete.
 269         (VEX_LEN_0F12_P_2_M_0, VEX_LEN_0F16_P_2_M_0): Define.
 270         (prefix_table): Decode MOD for cases 2 of opcodes 0F12, 0F16,
 271         VEX_0F12, and VEX_0F16.
 272         (vex_len_table): Use X for vmovlp* and vmovh*s. Drop
 273         VEX_LEN_0F12_P_2 and VEX_LEN_0F16_P_2 entries.
 274         (mod_table): Use X for movlpX and movhpX. Drop PREFIX_OPCODE
 275         from movlps and movhlps. New MOD_0F12_PREFIX_2,
 276         MOD_0F16_PREFIX_2, MOD_VEX_0F12_PREFIX_2, and
 277         MOD_VEX_0F16_PREFIX_2 entries.
 278
 279 2020-06-09  Jan Beulich  <jbeulich@suse.com>
 280
 281         * i386-dis.c (MOD_EVEX_0F12_PREFIX_2, MOD_EVEX_0F13,
 282         MOD_EVEX_0F16_PREFIX_2, MOD_EVEX_0F17, MOD_EVEX_0F2B): New enumerators.
 283         (PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
 284         PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29,
 285         PREFIX_EVEX_0F2B, PREFIX_EVEX_0F54, PREFIX_EVEX_0F55,
 286         PREFIX_EVEX_0F56, PREFIX_EVEX_0F57, PREFIX_EVEX_0FC6,
 287         EVEX_W_0F10_P_0, EVEX_W_0F10_P_2, EVEX_W_0F11_P_0,
 288         EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_2,
 289         EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0,
 290         EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2,
 291         EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0,
 292         EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2,
 293         EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0,
 294         EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2,
 295         EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0,
 296         EVEX_W_0F51_P_2, EVEX_W_0F54_P_0, EVEX_W_0F54_P_2,
 297         EVEX_W_0F55_P_0, EVEX_W_0F55_P_2, EVEX_W_0F56_P_0,
 298         EVEX_W_0F56_P_2, EVEX_W_0F57_P_0, EVEX_W_0F57_P_2,
 299         EVEX_W_0F58_P_0, EVEX_W_0F58_P_2, EVEX_W_0F59_P_0,
 300         EVEX_W_0F59_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2,
 301         EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0,
 302         EVEX_W_0F5E_P_2, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2,
 303         EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0,
 304         EVEX_W_0FC6_P_2): Delete.
 305         (print_insn): Add EVEX.W vs embedded prefix consistency check
 306         to prefix validation.
 307         * i386-dis-evex.h (evex_table): Don't further descend for
 308         vunpcklpX, vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX,
 309         and vshufpX. Continue with MOD decoding for opcodes 0F13, 0F17,
 310         and 0F2B.
 311         * i386-dis-evex-mod.h: Add/adjust vmovlpX/vmovhpX entries.
 312         * i386-dis-evex-prefix.h: Don't further descend for vmovupX,
 313         vucomisX, vcomisX, vsqrtpX, vaddpX, vmulpX, vsubpX, vminpX,
 314         vdivpX, vmaxpX, and vcmppX. Continue with MOD decoding for cases
 315         2 of PREFIX_EVEX_0F12, PREFIX_EVEX_0F16, and PREFIX_EVEX_0F29.
 316         Drop PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
 317         PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F2B,
 318         PREFIX_EVEX_0F54, PREFIX_EVEX_0F55, PREFIX_EVEX_0F56,
 319         PREFIX_EVEX_0F57, and PREFIX_EVEX_0FC6 entries.
 320         * i386-dis-evex-w.h: Drop EVEX_W_0F10_P_0, EVEX_W_0F10_P_2,
 321         EVEX_W_0F11_P_0, EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0,
 322         EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
 323         EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2,
 324         EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0,
 325         EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
 326         EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0,
 327         EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
 328         EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0,
 329         EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_2,
 330         EVEX_W_0F54_P_0, EVEX_W_0F54_P_2, EVEX_W_0F55_P_0,
 331         EVEX_W_0F55_P_2, EVEX_W_0F56_P_0, EVEX_W_0F56_P_2,
 332         EVEX_W_0F57_P_0, EVEX_W_0F57_P_2, EVEX_W_0F58_P_0,
 333         EVEX_W_0F58_P_2, EVEX_W_0F59_P_0, EVEX_W_0F59_P_2,
 334         EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2, EVEX_W_0F5D_P_0,
 335         EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_2,
 336         EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2, EVEX_W_0FC2_P_0,
 337         EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0, and EVEX_W_0FC6_P_2 entries.
 338
 339 2020-06-09  Jan Beulich  <jbeulich@suse.com>
 340
 341         * i386-dis.c (vex_table): Use PREFIX_OPCODE for vunpcklpX,
 342         vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX and vshufpX.
 343         (vex_len_table) : Likewise for vmovlpX, vmovhpX, vmovntpX, and
 344         vmovmskpX.
 345         (print_insn): Drop pointless check against bad_opcode. Split
 346         prefix validation into legacy and VEX-and-alike parts.
 347         (putop): Re-work 'X' macro handling.
 348
 349 2020-06-09  Jan Beulich  <jbeulich@suse.com>
 350
 351         * i386-dis.c (MOD_0F51): Rename to ...
 352         (MOD_0F50): ... this.
 353
 354 2020-06-08  Alex Coplan  <alex.coplan@arm.com>
 355
 356         * arm-dis.c (arm_opcodes): Add dfb.
 357         (thumb32_opcodes): Add dfb.
 358
 359 2020-06-08  Jan Beulich  <jbeulich@suse.com>
 360
 361         * i386-opc.h (reg_entry): Const-qualify reg_name field.
 362
 363 2020-06-06  Alan Modra  <amodra@gmail.com>
 364
 365         * ppc-dis.c (ppc_opts): Accept -mpwr10/-Mpwr10.
 366
 367 2020-06-05  Alan Modra  <amodra@gmail.com>
 368
 369         * cgen-dis.c (hash_insn_array): Increase size of buf.  Assert
 370         size is large enough.
 371
 372 2020-06-04  Jose E. Marchesi  <jose.marchesi@oracle.com>
 373
 374         * disassemble.c (disassemble_init_for_target): Set endian_code for
 375         bpf targets.
 376         * bpf-desc.c: Regenerate.
 377         * bpf-opc.c: Likewise.
 378         * bpf-dis.c: Likewise.
 379
 380 2020-06-03  Jose E. Marchesi  <jose.marchesi@oracle.com>
 381
 382         * cgen-opc.c (cgen_get_insn_value): Get an `endian' argument.
 383         (cgen_put_insn_value): Likewise.
 384         (cgen_lookup_insn): Pass endianness to cgen_{get,put}_insn_value.
 385         * cgen-dis.in (print_insn): Likewise.
 386         * cgen-ibld.in (insert_1): Likewise.
 387         (insert_1): Likewise.
 388         (insert_insn_normal): Likewise.
 389         (extract_1): Likewise.
 390         * bpf-dis.c: Regenerate.
 391         * bpf-ibld.c: Likewise.
 392         * bpf-ibld.c: Likewise.
 393         * cgen-dis.in: Likewise.
 394         * cgen-ibld.in: Likewise.
 395         * cgen-opc.c: Likewise.
 396         * epiphany-dis.c: Likewise.
 397         * epiphany-ibld.c: Likewise.
 398         * fr30-dis.c: Likewise.
 399         * fr30-ibld.c: Likewise.
 400         * frv-dis.c: Likewise.
 401         * frv-ibld.c: Likewise.
 402         * ip2k-dis.c: Likewise.
 403         * ip2k-ibld.c: Likewise.
 404         * iq2000-dis.c: Likewise.
 405         * iq2000-ibld.c: Likewise.
 406         * lm32-dis.c: Likewise.
 407         * lm32-ibld.c: Likewise.
 408         * m32c-dis.c: Likewise.
 409         * m32c-ibld.c: Likewise.
 410         * m32r-dis.c: Likewise.
 411         * m32r-ibld.c: Likewise.
 412         * mep-dis.c: Likewise.
 413         * mep-ibld.c: Likewise.
 414         * mt-dis.c: Likewise.
 415         * mt-ibld.c: Likewise.
 416         * or1k-dis.c: Likewise.
 417         * or1k-ibld.c: Likewise.
 418         * xc16x-dis.c: Likewise.
 419         * xc16x-ibld.c: Likewise.
 420         * xstormy16-dis.c: Likewise.
 421         * xstormy16-ibld.c: Likewise.
 422
 423 2020-06-04  Jose E. Marchesi  <jemarch@gnu.org>
 424
 425         * cgen-dis.in (cpu_desc_list): New field `insn_endian'.
 426         (print_insn_): Handle instruction endian.
 427         * bpf-dis.c: Regenerate.
 428         * bpf-desc.c: Regenerate.
 429         * epiphany-dis.c: Likewise.
 430         * epiphany-desc.c: Likewise.
 431         * fr30-dis.c: Likewise.
 432         * fr30-desc.c: Likewise.
 433         * frv-dis.c: Likewise.
 434         * frv-desc.c: Likewise.
 435         * ip2k-dis.c: Likewise.
 436         * ip2k-desc.c: Likewise.
 437         * iq2000-dis.c: Likewise.
 438         * iq2000-desc.c: Likewise.
 439         * lm32-dis.c: Likewise.
 440         * lm32-desc.c: Likewise.
 441         * m32c-dis.c: Likewise.
 442         * m32c-desc.c: Likewise.
 443         * m32r-dis.c: Likewise.
 444         * m32r-desc.c: Likewise.
 445         * mep-dis.c: Likewise.
 446         * mep-desc.c: Likewise.
 447         * mt-dis.c: Likewise.
 448         * mt-desc.c: Likewise.
 449         * or1k-dis.c: Likewise.
 450         * or1k-desc.c: Likewise.
 451         * xc16x-dis.c: Likewise.
 452         * xc16x-desc.c: Likewise.
 453         * xstormy16-dis.c: Likewise.
 454         * xstormy16-desc.c: Likewise.
 455
 456 2020-06-03  Nick Clifton  <nickc@redhat.com>
 457
 458         * po/sr.po: Updated Serbian translation.
 459
 460 2020-06-03  Nelson Chu  <nelson.chu@sifive.com>
 461
 462         * riscv-opc.c (riscv_get_isa_spec_class): Change bfd_boolean to int.
 463         (riscv_get_priv_spec_class): Likewise.
 464
 465 2020-06-01  Alan Modra  <amodra@gmail.com>
 466
 467         * bpf-desc.c: Regenerate.
 468
 469 2020-05-28  Jose E. Marchesi  <jose.marchesi@oracle.com>
 470             David Faust <david.faust@oracle.com>
 471
 472         * bpf-desc.c: Regenerate.
 473         * bpf-opc.h: Likewise.
 474         * bpf-opc.c: Likewise.
 475         * bpf-dis.c: Likewise.
 476
 477 2020-05-28  Alan Modra  <amodra@gmail.com>
 478
 479         * nios2-dis.c (nios2_print_insn_arg): Avoid shift left of negative
 480         values.
 481
 482 2020-05-28  Alan Modra  <amodra@gmail.com>
 483
 484         * ns32k-dis.c (print_insn_arg): Handle d value of 'f' for
 485         immediates.
 486         (print_insn_ns32k): Revert last change.
 487
 488 2020-05-28  Nick Clifton  <nickc@redhat.com>
 489
 490         * ns32k-dis.c (print_insn_ns32k): Change the arg_bufs array to
 491         static.
 492
 493 2020-05-26  Sandra Loosemore  <sandra@codesourcery.com>
 494
 495         Fix extraction of signed constants in nios2 disassembler (again).
 496
 497         * nios2-dis.c (nios2_print_insn_arg): Add explicit casts to
 498         extractions of signed fields.
 499
 500 2020-05-26  Stefan Schulze Frielinghaus  <stefansf@linux.ibm.com>
 501
 502         * s390-opc.txt: Relocate vector load/store instructions with
 503         additional alignment parameter and change architecture level
 504         constraint from z14 to z13.
 505
 506 2020-05-21  Alan Modra  <amodra@gmail.com>
 507
 508         * arc-ext.c: Replace "if (x) free (x)" with "free (x)" throughout.
 509         * sparc-dis.c: Likewise.
 510         * tic4x-dis.c: Likewise.
 511         * xtensa-dis.c: Likewise.
 512         * bpf-desc.c: Regenerate.
 513         * epiphany-desc.c: Regenerate.
 514         * fr30-desc.c: Regenerate.
 515         * frv-desc.c: Regenerate.
 516         * ip2k-desc.c: Regenerate.
 517         * iq2000-desc.c: Regenerate.
 518         * lm32-desc.c: Regenerate.
 519         * m32c-desc.c: Regenerate.
 520         * m32r-desc.c: Regenerate.
 521         * mep-asm.c: Regenerate.
 522         * mep-desc.c: Regenerate.
 523         * mt-desc.c: Regenerate.
 524         * or1k-desc.c: Regenerate.
 525         * xc16x-desc.c: Regenerate.
 526         * xstormy16-desc.c: Regenerate.
 527
 528 2020-05-20  Nelson Chu  <nelson.chu@sifive.com>
 529
 530         * riscv-opc.c (riscv_ext_version_table): The table used to store
 531         all information about the supported spec and the corresponding ISA
 532         versions.  Currently, only Zicsr is supported to verify the
 533         correctness of Z sub extension settings.  Others will be supported
 534         in the future patches.
 535         (struct isa_spec_t, isa_specs): List for all supported ISA spec
 536         classes and the corresponding strings.
 537         (riscv_get_isa_spec_class): New function.  Get the corresponding ISA
 538         spec class by giving a ISA spec string.
 539         * riscv-opc.c (struct priv_spec_t): New structure.
 540         (struct priv_spec_t priv_specs): List for all supported privilege spec
 541         classes and the corresponding strings.
 542         (riscv_get_priv_spec_class): New function.  Get the corresponding
 543         privilege spec class by giving a spec string.
 544         (riscv_get_priv_spec_name): New function.  Get the corresponding
 545         privilege spec string by giving a CSR version class.
 546         * riscv-dis.c: Updated since DECLARE_CSR is changed.
 547         * riscv-dis.c: Add new disassembler option -Mpriv-spec to dump the CSR
 548         according to the chosen version.  Build a hash table riscv_csr_hash to
 549         store the valid CSR for the chosen pirv verison.  Dump the direct
 550         CSR address rather than it's name if it is invalid.
 551         (parse_riscv_dis_option_without_args): New function.  Parse the options
 552         without arguments.
 553         (parse_riscv_dis_option): Call parse_riscv_dis_option_without_args to
 554         parse the options without arguments first, and then handle the options
 555         with arguments.  Add the new option -Mpriv-spec, which has argument.
 556         * riscv-dis.c (print_riscv_disassembler_options): Add description
 557         about the new OBJDUMP option.
 558
 559 2020-05-19  Peter Bergner  <bergner@linux.ibm.com>
 560
 561         * ppc-opc.c (insert_ls, extract_ls): Handle 3-bit L fields and new
 562         WC values on POWER10 sync, dcbf  and wait instructions.
 563         (insert_pl, extract_pl): New functions.
 564         (L2OPT, LS, WC): Use insert_ls and extract_ls.
 565         (LS3): New , 3-bit L for sync.
 566         (LS3, L3OPT): New, 3-bit L for sync and dcbf.
 567         (SC2, PL): New, 2-bit SC and PL for sync and wait.
 568         (XWCPL_MASK, XL3RT_MASK, XSYNCLS_MASK): New instruction masks.
 569         (XOPL3, XWCPL, XSYNCLS): New opcode macros.
 570         (powerpc_opcodes) <dcbflp, dcbfps, dcbstps pause_short, phwsync,
 571         plwsync, stcisync, stncisync, stsync, waitrsv>: New extended mnemonics.
 572         <wait>: Enable PL operand on POWER10.
 573         <dcbf>: Enable L3OPT operand on POWER10.
 574         <sync>: Enable SC2 operand on POWER10.
 575
 576 2020-05-19  Stafford Horne  <shorne@gmail.com>
 577
 578         PR 25184
 579         * or1k-asm.c: Regenerate.
 580         * or1k-desc.c: Regenerate.
 581         * or1k-desc.h: Regenerate.
 582         * or1k-dis.c: Regenerate.
 583         * or1k-ibld.c: Regenerate.
 584         * or1k-opc.c: Regenerate.
 585         * or1k-opc.h: Regenerate.
 586         * or1k-opinst.c: Regenerate.
 587
 588 2020-05-11  Alan Modra  <amodra@gmail.com>
 589
 590         * ppc-opc (powerpc_opcodes): Add xscmpeqqp, xscmpgeqp, xscmpgtqp,
 591         xsmaxcqp, xsmincqp.
 592
 593 2020-05-11  Alan Modra  <amodra@gmail.com>
 594
 595         * ppc-opc.c (powerpc_opcodes): Add lxvrbx, lxvrhx, lxvrwx, lxvrdx,
 596         stxvrbx, stxvrhx, stxvrwx, stxvrdx.
 597
 598 2020-05-11  Alan Modra  <amodra@gmail.com>
 599
 600         * ppc-opc.c (powerpc_opcodes): Add xvtlsbb.
 601
 602 2020-05-11  Alan Modra  <amodra@gmail.com>
 603
 604         * ppc-opc.c (powerpc_opcodes): Add vstribl, vstribr, vstrihl, vstrihr,
 605         vclrlb, vclrrb, vstribl., vstribr., vstrihl., vstrihr..
 606
 607 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
 608
 609         * ppc-opc.c (powerpc_opcodes) <setbc, setbcr, setnbc, setnbcr>: New
 610         mnemonics.
 611
 612 2020-05-11  Alan Modra  <amodra@gmail.com>
 613
 614         * ppc-opc.c (UIM8, P_U8XX4_MASK): Define.
 615         (powerpc_opcodes): Add vgnb, vcfuged, vpextd, vpdepd, vclzdm,
 616         vctzdm, cntlzdm, pdepd, pextd, cfuged, cnttzdm.
 617         (prefix_opcodes): Add xxeval.
 618
 619 2020-05-11  Alan Modra  <amodra@gmail.com>
 620
 621         * ppc-opc.c (powerpc_opcodes): Add xxgenpcvbm, xxgenpcvhm,
 622         xxgenpcvwm, xxgenpcvdm.
 623
 624 2020-05-11  Alan Modra  <amodra@gmail.com>
 625
 626         * ppc-opc.c (MP, VXVAM_MASK): Define.
 627         (VXVAPS_MASK): Use VXVA_MASK.
 628         (powerpc_opcodes): Add mtvsrbmi, vexpandbm, vexpandhm, vexpandwm,
 629         vexpanddm, vexpandqm, vextractbm, vextracthm, vextractwm,
 630         vextractdm, vextractqm, mtvsrbm, mtvsrhm, mtvsrwm, mtvsrdm, mtvsrqm,
 631         vcntmbb, vcntmbh, vcntmbw, vcntmbd.
 632
 633 2020-05-11  Alan Modra  <amodra@gmail.com>
 634             Peter Bergner  <bergner@linux.ibm.com>
 635
 636         * ppc-opc.c (insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a):
 637         New functions.
 638         (powerpc_operands): Define ACC, PMSK8, PMSK4, PMSK2, XMSK, YMSK,
 639         YMSK2, XA6a, XA6ap, XB6a entries.
 640         (PMMIRR, P_X_MASK, P_XX1_MASK, P_GER_MASK): Define
 641         (P_GER2_MASK, P_GER4_MASK, P_GER8_MASK, P_GER64_MASK): Define.
 642         (PPCVSX4): Define.
 643         (powerpc_opcodes): Add xxmfacc, xxmtacc, xxsetaccz,
 644         xvi8ger4pp, xvi8ger4, xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger,
 645         xvi4ger8pp, xvi4ger8, xvi16ger2spp, xvi16ger2s, xvbf16ger2pp,
 646         xvbf16ger2, xvf64gerpp, xvf64ger, xvi16ger2, xvf16ger2np,
 647         xvf32gernp, xvi8ger4spp, xvi16ger2pp, xvbf16ger2np, xvf64gernp,
 648         xvf16ger2pn, xvf32gerpn, xvbf16ger2pn, xvf64gerpn, xvf16ger2nn,
 649         xvf32gernn, xvbf16ger2nn, xvf64gernn, xvcvbf16sp, xvcvspbf16.
 650         (prefix_opcodes): Add pmxvi8ger4pp, pmxvi8ger4, pmxvf16ger2pp,
 651         pmxvf16ger2, pmxvf32gerpp, pmxvf32ger, pmxvi4ger8pp, pmxvi4ger8,
 652         pmxvi16ger2spp, pmxvi16ger2s, pmxvbf16ger2pp, pmxvbf16ger2,
 653         pmxvf64gerpp, pmxvf64ger, pmxvi16ger2, pmxvf16ger2np, pmxvf32gernp,
 654         pmxvi8ger4spp, pmxvi16ger2pp, pmxvbf16ger2np, pmxvf64gernp,
 655         pmxvf16ger2pn, pmxvf32gerpn, pmxvbf16ger2pn, pmxvf64gerpn,
 656         pmxvf16ger2nn, pmxvf32gernn, pmxvbf16ger2nn, pmxvf64gernn.
 657
 658 2020-05-11  Alan Modra  <amodra@gmail.com>
 659
 660         * ppc-opc.c (insert_imm32, extract_imm32): New functions.
 661         (insert_xts, extract_xts): New functions.
 662         (IMM32, UIM3, IX, UIM5, SH3, XTS, P8RR): Define.
 663         (P_XX4_MASK, P_UXX4_MASK, VSOP, P_VS_MASK, P_VSI_MASK): Define.
 664         (VXRC_MASK, VXSH_MASK): Define.
 665         (powerpc_opcodes): Add vinsbvlx, vsldbi, vextdubvlx, vextdubvrx,
 666         vextduhvlx, vextduhvrx, vextduwvlx, vextduwvrx, vextddvlx,
 667         vextddvrx, vinshvlx, vinswvlx, vinsw, vinsbvrx, vinshvrx,
 668         vinswvrx, vinsd, vinsblx, vsrdbi, vinshlx, vinswlx, vinsdlx,
 669         vinsbrx, vinshrx, vinswrx, vinsdrx, lxvkq.
 670         (prefix_opcodes): Add xxsplti32dx, xxspltidp, xxspltiw, xxblendvb,
 671         xxblendvh, xxblendvw, xxblendvd, xxpermx.
 672
 673 2020-05-11  Alan Modra  <amodra@gmail.com>
 674
 675         * ppc-opc.c (powerpc_opcodes): Add vrlq, vdivuq, vmsumcud, vrlqmi,
 676         vmuloud, vcmpuq, vslq, vdivsq, vcmpsq, vrlqnm, vcmpequq, vmulosd,
 677         vsrq, vdiveuq, vcmpgtuq, vmuleud, vsraq, vdivesq, vcmpgtsq, vmulesd,
 678         vcmpequq., vextsd2q, vmoduq, vcmpgtuq., vmodsq, vcmpgtsq., xscvqpuqz,
 679         xscvuqqp, xscvqpsqz, xscvsqqp, dcffixqq, dctfixqq.
 680
 681 2020-05-11  Alan Modra  <amodra@gmail.com>
 682
 683         * ppc-opc.c (insert_xtp, extract_xtp): New functions.
 684         (XTP, DQXP, DQXP_MASK): Define.
 685         (powerpc_opcodes): Add lxvp, stxvp, lxvpx, stxvpx.
 686         (prefix_opcodes): Add plxvp and pstxvp.
 687
 688 2020-05-11  Alan Modra  <amodra@gmail.com>
 689
 690         * ppc-opc.c (powerpc_opcodes): Add vdivuw, vdivud, vdivsw, vmulld,
 691         vdivsd, vmulhuw, vdiveuw, vmulhud, vdiveud, vmulhsw, vdivesw,
 692         vmulhsd, vdivesd, vmoduw, vmodud, vmodsw, vmodsd.
 693
 694 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
 695
 696         * ppc-opc.c (powerpc_opcodes) <brd, brh, brw>: New mnemonics.
 697
 698 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
 699
 700         * ppc-opc.c (insert_l1opt, extract_l1opt): New functions.
 701         (L1OPT): Define.
 702         (powerpc_opcodes) <paste.>: Add L operand for cpu POWER10.
 703
 704 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
 705
 706         * ppc-opc.c (powerpc_opcodes) <slbiag>: Add variant with L operand.
 707
 708 2020-05-11  Alan Modra  <amodra@gmail.com>
 709
 710         * ppc-dis.c (powerpc_init_dialect): Default to "power10".
 711
 712 2020-05-11  Alan Modra  <amodra@gmail.com>
 713
 714         * ppc-dis.c (ppc_opts): Add "power10" entry.
 715         (print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming.
 716         * ppc-opc.c (POWER10): Rename from POWERXX.  Update all uses.
 717
 718 2020-05-11  Nick Clifton  <nickc@redhat.com>
 719
 720         * po/fr.po: Updated French translation.
 721
 722 2020-04-30  Alex Coplan  <alex.coplan@arm.com>
 723
 724         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
 725         * aarch64-opc.c (fields): Add entry for FLD_imm16_2.
 726         (operand_general_constraint_met_p): validate
 727         AARCH64_OPND_UNDEFINED.
 728         * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry
 729         for FLD_imm16_2.
 730         * aarch64-asm-2.c: Regenerated.
 731         * aarch64-dis-2.c: Regenerated.
 732         * aarch64-opc-2.c: Regenerated.
 733
 734 2020-04-29  Nick Clifton  <nickc@redhat.com>
 735
 736         PR 22699
 737         * sh-opc.h: Also use unsigned 8-bit immediate values for the LDRC
 738         and SETRC insns.
 739
 740 2020-04-29  Nick Clifton  <nickc@redhat.com>
 741
 742         * po/sv.po: Updated Swedish translation.
 743
 744 2020-04-29  Nick Clifton  <nickc@redhat.com>
 745
 746         PR 22699
 747         * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U.  Use
 748         IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
 749         * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
 750         IMM0_8U case.
 751
 752 2020-04-21  Andreas Schwab  <schwab@linux-m68k.org>
 753
 754         PR 25848
 755         * m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
 756         cmpi only on m68020up and cpu32.
 757
 758 2020-04-20  Sudakshina Das  <sudi.das@arm.com>
 759
 760         * aarch64-asm.c (aarch64_ins_none): New.
 761         * aarch64-asm.h (ins_none): New declaration.
 762         * aarch64-dis.c (aarch64_ext_none): New.
 763         * aarch64-dis.h (ext_none): New declaration.
 764         * aarch64-opc.c (aarch64_print_operand): Update case for
 765         AARCH64_OPND_BARRIER_PSB.
 766         * aarch64-tbl.h (aarch64_opcode_table): Add tsb.
 767         (AARCH64_OPERANDS): Update inserter/extracter for
 768         AARCH64_OPND_BARRIER_PSB to use new dummy functions.
 769         * aarch64-asm-2.c: Regenerated.
 770         * aarch64-dis-2.c: Regenerated.
 771         * aarch64-opc-2.c: Regenerated.
 772
 773 2020-04-20  Sudakshina Das  <sudi.das@arm.com>
 774
 775         * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
 776         (aarch64_feature_ras, RAS): Likewise.
 777         (aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
 778         (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
 779         autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
 780         autiaz, autiasp, autibz, autibsp to be CORE_INSN.
 781         * aarch64-asm-2.c: Regenerated.
 782         * aarch64-dis-2.c: Regenerated.
 783         * aarch64-opc-2.c: Regenerated.
 784
 785 2020-04-17  Fredrik Strupe  <fredrik@strupe.net>
 786
 787         * arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
 788         (print_insn_neon): Support disassembly of conditional
 789         instructions.
 790
 791 2020-02-16  David Faust  <david.faust@oracle.com>
 792
 793         * bpf-desc.c: Regenerate.
 794         * bpf-desc.h: Likewise.
 795         * bpf-opc.c: Regenerate.
 796         * bpf-opc.h: Likewise.
 797
 798 2020-04-07  Lili Cui  <lili.cui@intel.com>
 799
 800         * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
 801         (prefix_table): New instructions (see prefixes above).
 802         (rm_table): Likewise
 803         * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
 804         CPU_ANY_TSXLDTRK_FLAGS.
 805         (cpu_flags): Add CpuTSXLDTRK.
 806         * i386-opc.h (enum): Add CpuTSXLDTRK.
 807         (i386_cpu_flags): Add cputsxldtrk.
 808         * i386-opc.tbl: Add XSUSPLDTRK insns.
 809         * i386-init.h: Regenerate.
 810         * i386-tbl.h: Likewise.
 811
 812 2020-04-02  Lili Cui  <lili.cui@intel.com>
 813
 814         * i386-dis.c (prefix_table): New instructions serialize.
 815         * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
 816         CPU_ANY_SERIALIZE_FLAGS.
 817         (cpu_flags): Add CpuSERIALIZE.
 818         * i386-opc.h (enum): Add CpuSERIALIZE.
 819         (i386_cpu_flags): Add cpuserialize.
 820         * i386-opc.tbl: Add SERIALIZE insns.
 821         * i386-init.h: Regenerate.
 822         * i386-tbl.h: Likewise.
 823
 824 2020-03-26  Alan Modra  <amodra@gmail.com>
 825
 826         * disassemble.h (opcodes_assert): Declare.
 827         (OPCODES_ASSERT): Define.
 828         * disassemble.c: Don't include assert.h.  Include opintl.h.
 829         (opcodes_assert): New function.
 830         * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
 831         (bfd_h8_disassemble): Reduce size of data array.  Correctly
 832         calculate maxlen.  Omit insn decoding when insn length exceeds
 833         maxlen.  Exit from nibble loop when looking for E, before
 834         accessing next data byte.  Move processing of E outside loop.
 835         Replace tests of maxlen in loop with assertions.
 836
 837 2020-03-26  Alan Modra  <amodra@gmail.com>
 838
 839         * arc-dis.c (find_format): Init needs_limm.  Simplify use of limm.
 840
 841 2020-03-25  Alan Modra  <amodra@gmail.com>
 842
 843         * z80-dis.c (suffix): Init mybuf.
 844
 845 2020-03-22  Alan Modra  <amodra@gmail.com>
 846
 847         * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
 848         successflly read from section.
 849
 850 2020-03-22  Alan Modra  <amodra@gmail.com>
 851
 852         * arc-dis.c (find_format): Use ISO C string concatenation rather
 853         than line continuation within a string.  Don't access needs_limm
 854         before testing opcode != NULL.
 855
 856 2020-03-22  Alan Modra  <amodra@gmail.com>
 857
 858         * ns32k-dis.c (print_insn_arg): Update comment.
 859         (print_insn_ns32k): Reduce size of index_offset array, and
 860         initialize, passing -1 to print_insn_arg for args that are not
 861         an index.  Don't exit arg loop early.  Abort on bad arg number.
 862
 863 2020-03-22  Alan Modra  <amodra@gmail.com>
 864
 865         * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
 866         * s12z-opc.c: Formatting.
 867         (operands_f): Return an int.
 868         (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
 869         (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
 870         (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
 871         (exg_sex_discrim): Likewise.
 872         (create_immediate_operand, create_bitfield_operand),
 873         (create_register_operand_with_size, create_register_all_operand),
 874         (create_register_all16_operand, create_simple_memory_operand),
 875         (create_memory_operand, create_memory_auto_operand): Don't
 876         segfault on malloc failure.
 877         (z_ext24_decode): Return an int status, negative on fail, zero
 878         on success.
 879         (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
 880         (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
 881         (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
 882         (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
 883         (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
 884         (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
 885         (loop_primitive_decode, shift_decode, psh_pul_decode),
 886         (bit_field_decode): Similarly.
 887         (z_decode_signed_value, decode_signed_value): Similarly.  Add arg
 888         to return value, update callers.
 889         (x_opr_decode_with_size): Check all reads, returning NULL on fail.
 890         Don't segfault on NULL operand.
 891         (decode_operation): Return OP_INVALID on first fail.
 892         (decode_s12z): Check all reads, returning -1 on fail.
 893
 894 2020-03-20  Alan Modra  <amodra@gmail.com>
 895
 896         * metag-dis.c (print_insn_metag): Don't ignore status from
 897         read_memory_func.
 898
 899 2020-03-20  Alan Modra  <amodra@gmail.com>
 900
 901         * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
 902         Initialize parts of buffer not written when handling a possible
 903         2-byte insn at end of section.  Don't attempt decoding of such
 904         an insn by the 4-byte machinery.
 905
 906 2020-03-20  Alan Modra  <amodra@gmail.com>
 907
 908         * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
 909         partially filled buffer.  Prevent lookup of 4-byte insns when
 910         only VLE 2-byte insns are possible due to section size.  Print
 911         ".word" rather than ".long" for 2-byte leftovers.
 912
 913 2020-03-17  Sergey Belyashov  <sergey.belyashov@gmail.com>
 914
 915         PR 25641
 916         * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
 917
 918 2020-03-13  Jan Beulich  <jbeulich@suse.com>
 919
 920         * i386-dis.c (X86_64_0D): Rename to ...
 921         (X86_64_0E): ... this.
 922
 923 2020-03-09  H.J. Lu  <hongjiu.lu@intel.com>
 924
 925         * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
 926         * Makefile.in: Regenerated.
 927
 928 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 929
 930         * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
 931         3-operand pseudos.
 932         * i386-tbl.h: Re-generate.
 933
 934 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 935
 936         * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
 937         vprot*, vpsha*, and vpshl*.
 938         * i386-tbl.h: Re-generate.
 939
 940 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 941
 942         * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
 943         vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
 944         * i386-tbl.h: Re-generate.
 945
 946 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 947
 948         * i386-gen.c (set_bitfield): Ignore zero-length field names.
 949         * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
 950         cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
 951         * i386-tbl.h: Re-generate.
 952
 953 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 954
 955         * i386-gen.c (struct template_arg, struct template_instance,
 956         struct template_param, struct template, templates,
 957         parse_template, expand_templates): New.
 958         (process_i386_opcodes): Various local variables moved to
 959         expand_templates. Call parse_template and expand_templates.
 960         * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
 961         * i386-tbl.h: Re-generate.
 962
 963 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 964
 965         * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
 966         vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
 967         register and memory source templates. Replace VexW= by VexW*
 968         where applicable.
 969         * i386-tbl.h: Re-generate.
 970
 971 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 972
 973         * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
 974         VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
 975         * i386-tbl.h: Re-generate.
 976
 977 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 978
 979         * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
 980         * i386-tbl.h: Re-generate.
 981
 982 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 983
 984         * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
 985         (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
 986         pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
 987         VexW0 on SSE2AVX variants.
 988         (vmovq): Drop NoRex64 from XMM/XMM variants.
 989         (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
 990         vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
 991         applicable use VexW0.
 992         * i386-tbl.h: Re-generate.
 993
 994 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 995
 996         * i386-gen.c (opcode_modifiers): Remove Rex64 field.
 997         * i386-opc.h (Rex64): Delete.
 998         (struct i386_opcode_modifier): Remove rex64 field.
 999         * i386-opc.tbl (crc32): Drop Rex64.
1000         Replace Rex64 with Size64 everywhere else.
1001         * i386-tbl.h: Re-generate.
1002
1003 2020-03-06  Jan Beulich  <jbeulich@suse.com>
1004
1005         * i386-dis.c (OP_E_memory): Exclude recording of used address
1006         prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
1007         addressed memory operands for MPX insns.
1008
1009 2020-03-06  Jan Beulich  <jbeulich@suse.com>
1010
1011         * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
1012         invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
1013         adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
1014         (ptwrite): Split into non-64-bit and 64-bit forms.
1015         * i386-tbl.h: Re-generate.
1016
1017 2020-03-06  Jan Beulich  <jbeulich@suse.com>
1018
1019         * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
1020         template.
1021         * i386-tbl.h: Re-generate.
1022
1023 2020-03-04  Jan Beulich  <jbeulich@suse.com>
1024
1025         * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
1026         (prefix_table): Move vmmcall here. Add vmgexit.
1027         (rm_table): Replace vmmcall entry by prefix_table[] escape.
1028         * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
1029         (cpu_flags): Add CpuSEV_ES entry.
1030         * i386-opc.h (CpuSEV_ES): New.
1031         (union i386_cpu_flags): Add cpusev_es field.
1032         * i386-opc.tbl (vmgexit): New.
1033         * i386-init.h, i386-tbl.h: Re-generate.
1034
1035 2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
1036
1037         * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
1038         with MnemonicSize.
1039         * i386-opc.h (IGNORESIZE): New.
1040         (DEFAULTSIZE): Likewise.
1041         (IgnoreSize): Removed.
1042         (DefaultSize): Likewise.
1043         (MnemonicSize): New.
1044         (i386_opcode_modifier): Replace ignoresize/defaultsize with
1045         mnemonicsize.
1046         * i386-opc.tbl (IgnoreSize): New.
1047         (DefaultSize): Likewise.
1048         * i386-tbl.h: Regenerated.
1049
1050 2020-03-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
1051
1052         PR 25627
1053         * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
1054         instructions.
1055
1056 2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
1057
1058         PR gas/25622
1059         * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
1060         vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
1061         * i386-tbl.h: Regenerated.
1062
1063 2020-02-26  Alan Modra  <amodra@gmail.com>
1064
1065         * aarch64-asm.c: Indent labels correctly.
1066         * aarch64-dis.c: Likewise.
1067         * aarch64-gen.c: Likewise.
1068         * aarch64-opc.c: Likewise.
1069         * alpha-dis.c: Likewise.
1070         * i386-dis.c: Likewise.
1071         * nds32-asm.c: Likewise.
1072         * nfp-dis.c: Likewise.
1073         * visium-dis.c: Likewise.
1074
1075 2020-02-25  Claudiu Zissulescu <claziss@gmail.com>
1076
1077         * arc-regs.h (int_vector_base): Make it available for all ARC
1078         CPUs.
1079
1080 2020-02-20  Nelson Chu  <nelson.chu@sifive.com>
1081
1082         * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
1083         changed.
1084
1085 2020-02-19  Nelson Chu  <nelson.chu@sifive.com>
1086
1087         * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
1088         c.mv/c.li if rs1 is zero.
1089
1090 2020-02-17  H.J. Lu  <hongjiu.lu@intel.com>
1091
1092         * i386-gen.c (cpu_flag_init): Replace CpuABM with
1093         CpuLZCNT|CpuPOPCNT.  Add CpuPOPCNT to CPU_SSE4_2_FLAGS.  Add
1094         CPU_POPCNT_FLAGS.
1095         (cpu_flags): Remove CpuABM.  Add CpuPOPCNT.
1096         * i386-opc.h (CpuABM): Removed.
1097         (CpuPOPCNT): New.
1098         (i386_cpu_flags): Remove cpuabm.  Add cpupopcnt.
1099         * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
1100         popcnt.  Remove CpuABM from lzcnt.
1101         * i386-init.h: Regenerated.
1102         * i386-tbl.h: Likewise.
1103
1104 2020-02-17  Jan Beulich  <jbeulich@suse.com>
1105
1106         * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
1107         Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
1108         VexW1 instead of open-coding them.
1109         * i386-tbl.h: Re-generate.
1110
1111 2020-02-17  Jan Beulich  <jbeulich@suse.com>
1112
1113         * i386-opc.tbl (AddrPrefixOpReg): Define.
1114         (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
1115         umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
1116         templates. Drop NoRex64.
1117         * i386-tbl.h: Re-generate.
1118
1119 2020-02-17  Jan Beulich  <jbeulich@suse.com>
1120
1121         PR gas/6518
1122         * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
1123         vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
1124         into Intel syntax instance (with Unpsecified) and AT&T one
1125         (without).
1126         (vcvtneps2bf16): Likewise, along with folding the two so far
1127         separate ones.
1128         * i386-tbl.h: Re-generate.
1129
1130 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
1131
1132         * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
1133         CPU_ANY_SSE4A_FLAGS.
1134
1135 2020-02-17  Alan Modra  <amodra@gmail.com>
1136
1137         * i386-gen.c (cpu_flag_init): Correct last change.
1138
1139 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
1140
1141         * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS.  Remove
1142         CPU_ANY_SSE4_FLAGS.
1143
1144 2020-02-14  H.J. Lu  <hongjiu.lu@intel.com>
1145
1146         * i386-opc.tbl (movsx): Remove Intel syntax comments.
1147         (movzx): Likewise.
1148
1149 2020-02-14  Jan Beulich  <jbeulich@suse.com>
1150
1151         PR gas/25438
1152         * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
1153         destination for Cpu64-only variant.
1154         (movzx): Fold patterns.
1155         * i386-tbl.h: Re-generate.
1156
1157 2020-02-13  Jan Beulich  <jbeulich@suse.com>
1158
1159         * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
1160         CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
1161         CPU_ANY_SSE4_FLAGS entry.
1162         * i386-init.h: Re-generate.
1163
1164 2020-02-12  Jan Beulich  <jbeulich@suse.com>
1165
1166         * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
1167         with Unspecified, making the present one AT&T syntax only.
1168         * i386-tbl.h: Re-generate.
1169
1170 2020-02-12  Jan Beulich  <jbeulich@suse.com>
1171
1172         * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
1173         * i386-tbl.h: Re-generate.
1174
1175 2020-02-12  Jan Beulich  <jbeulich@suse.com>
1176
1177         PR gas/24546
1178         * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
1179         * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
1180         Amd64 and Intel64 templates.
1181         (call, jmp): Likewise for far indirect variants. Dro
1182         Unspecified.
1183         * i386-tbl.h: Re-generate.
1184
1185 2020-02-11  Jan Beulich  <jbeulich@suse.com>
1186
1187         * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
1188         * i386-opc.h (ShortForm): Delete.
1189         (struct i386_opcode_modifier): Remove shortform field.
1190         * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
1191         fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
1192         fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
1193         ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
1194         Drop ShortForm.
1195         * i386-tbl.h: Re-generate.
1196
1197 2020-02-11  Jan Beulich  <jbeulich@suse.com>
1198
1199         * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
1200         fucompi): Drop ShortForm from operand-less templates.
1201         * i386-tbl.h: Re-generate.
1202
1203 2020-02-11  Alan Modra  <amodra@gmail.com>
1204
1205         * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
1206         * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
1207         * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
1208         * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
1209         * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
1210
1211 2020-02-10  Matthew Malcomson  <matthew.malcomson@arm.com>
1212
1213         * arm-dis.c (print_insn_cde): Define 'V' parse character.
1214         (cde_opcodes): Add VCX* instructions.
1215
1216 2020-02-10  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
1217             Matthew Malcomson  <matthew.malcomson@arm.com>
1218
1219         * arm-dis.c (struct cdeopcode32): New.
1220         (CDE_OPCODE): New macro.
1221         (cde_opcodes): New disassembly table.
1222         (regnames): New option to table.
1223         (cde_coprocs): New global variable.
1224         (print_insn_cde): New
1225         (print_insn_thumb32): Use print_insn_cde.
1226         (parse_arm_disassembler_options): Parse coprocN args.
1227
1228 2020-02-10  H.J. Lu  <hongjiu.lu@intel.com>
1229
1230         PR gas/25516
1231         * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
1232         with ISA64.
1233         * i386-opc.h (AMD64): Removed.
1234         (Intel64): Likewose.
1235         (AMD64): New.
1236         (INTEL64): Likewise.
1237         (INTEL64ONLY): Likewise.
1238         (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
1239         * i386-opc.tbl (Amd64): New.
1240         (Intel64): Likewise.
1241         (Intel64Only): Likewise.
1242         Replace AMD64 with Amd64.  Update sysenter/sysenter with
1243         Cpu64 and Intel64Only.  Remove AMD64 from sysenter/sysenter.
1244         * i386-tbl.h: Regenerated.
1245
1246 2020-02-07  Sergey Belyashov  <sergey.belyashov@gmail.com>
1247
1248         PR 25469
1249         * z80-dis.c: Add support for GBZ80 opcodes.
1250
1251 2020-02-04  Alan Modra  <amodra@gmail.com>
1252
1253         * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
1254
1255 2020-02-03  Alan Modra  <amodra@gmail.com>
1256
1257         * m32c-ibld.c: Regenerate.
1258
1259 2020-02-01  Alan Modra  <amodra@gmail.com>
1260
1261         * frv-ibld.c: Regenerate.
1262
1263 2020-01-31  Jan Beulich  <jbeulich@suse.com>
1264
1265         * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
1266         (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
1267         (OP_E_memory): Replace xmm_mdq_mode case label by
1268         vex_scalar_w_dq_mode one.
1269         * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
1270
1271 2020-01-31  Jan Beulich  <jbeulich@suse.com>
1272
1273         * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
1274         (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
1275         vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
1276         (intel_operand_size): Drop vex_w_dq_mode case label.
1277
1278 2020-01-31  Richard Sandiford  <richard.sandiford@arm.com>
1279
1280         * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
1281         Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
1282
1283 2020-01-30  Alan Modra  <amodra@gmail.com>
1284
1285         * m32c-ibld.c: Regenerate.
1286
1287 2020-01-30  Jose E. Marchesi  <jose.marchesi@oracle.com>
1288
1289         * bpf-opc.c: Regenerate.
1290
1291 2020-01-30  Jan Beulich  <jbeulich@suse.com>
1292
1293         * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
1294         (dis386): Use them to replace C2/C3 table entries.
1295         (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
1296         * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
1297         ones. Use Size64 instead of DefaultSize on Intel64 ones.
1298         * i386-tbl.h: Re-generate.
1299
1300 2020-01-30  Jan Beulich  <jbeulich@suse.com>
1301
1302         * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
1303         forms.
1304         (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
1305         DefaultSize.
1306         * i386-tbl.h: Re-generate.
1307
1308 2020-01-30  Alan Modra  <amodra@gmail.com>
1309
1310         * tic4x-dis.c (tic4x_dp): Make unsigned.
1311
1312 2020-01-27  H.J. Lu  <hongjiu.lu@intel.com>
1313             Jan Beulich  <jbeulich@suse.com>
1314
1315         PR binutils/25445
1316         * i386-dis.c (MOVSXD_Fixup): New function.
1317         (movsxd_mode): New enum.
1318         (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
1319         (intel_operand_size): Handle movsxd_mode.
1320         (OP_E_register): Likewise.
1321         (OP_G): Likewise.
1322         * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
1323         register on movsxd.  Add movsxd with 16-bit destination register
1324         for AMD64 and Intel64 ISAs.
1325         * i386-tbl.h: Regenerated.
1326
1327 2020-01-27  Tamar Christina  <tamar.christina@arm.com>
1328
1329         PR 25403
1330         * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
1331         * aarch64-asm-2.c: Regenerate
1332         * aarch64-dis-2.c: Likewise.
1333         * aarch64-opc-2.c: Likewise.
1334
1335 2020-01-21  Jan Beulich  <jbeulich@suse.com>
1336
1337         * i386-opc.tbl (sysret): Drop DefaultSize.
1338         * i386-tbl.h: Re-generate.
1339
1340 2020-01-21  Jan Beulich  <jbeulich@suse.com>
1341
1342         * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
1343         Dword.
1344         (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
1345         * i386-tbl.h: Re-generate.
1346
1347 2020-01-20  Nick Clifton  <nickc@redhat.com>
1348
1349         * po/de.po: Updated German translation.
1350         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1351         * po/uk.po: Updated Ukranian translation.
1352
1353 2020-01-20  Alan Modra  <amodra@gmail.com>
1354
1355         * hppa-dis.c (fput_const): Remove useless cast.
1356
1357 2020-01-20  Alan Modra  <amodra@gmail.com>
1358
1359         * arm-dis.c (print_insn_arm): Wrap 'T' value.
1360
1361 2020-01-18  Nick Clifton  <nickc@redhat.com>
1362
1363         * configure: Regenerate.
1364         * po/opcodes.pot: Regenerate.
1365
1366 2020-01-18  Nick Clifton  <nickc@redhat.com>
1367
1368         Binutils 2.34 branch created.
1369
1370 2020-01-17  Christian Biesinger  <cbiesinger@google.com>
1371
1372         * opintl.h: Fix spelling error (seperate).
1373
1374 2020-01-17  H.J. Lu  <hongjiu.lu@intel.com>
1375
1376         * i386-opc.tbl: Add {vex} pseudo prefix.
1377         * i386-tbl.h: Regenerated.
1378
1379 2020-01-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1380
1381         PR 25376
1382         * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
1383         (neon_opcodes): Likewise.
1384         (select_arm_features): Make sure we enable MVE bits when selecting
1385         armv8.1-m.main.  Make sure we do not enable MVE bits when not selecting
1386         any architecture.
1387
1388 2020-01-16  Jan Beulich  <jbeulich@suse.com>
1389
1390         * i386-opc.tbl: Drop stale comment from XOP section.
1391
1392 2020-01-16  Jan Beulich  <jbeulich@suse.com>
1393
1394         * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
1395         (extractps): Add VexWIG to SSE2AVX forms.
1396         * i386-tbl.h: Re-generate.
1397
1398 2020-01-16  Jan Beulich  <jbeulich@suse.com>
1399
1400         * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
1401         Size64 from and use VexW1 on SSE2AVX forms.
1402         (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
1403         VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
1404         * i386-tbl.h: Re-generate.
1405
1406 2020-01-15  Alan Modra  <amodra@gmail.com>
1407
1408         * tic4x-dis.c (tic4x_version): Make unsigned long.
1409         (optab, optab_special, registernames): New file scope vars.
1410         (tic4x_print_register): Set up registernames rather than
1411         malloc'd registertable.
1412         (tic4x_disassemble): Delete optable and optable_special.  Use
1413         optab and optab_special instead.  Throw away old optab,
1414         optab_special and registernames when info->mach changes.
1415
1416 2020-01-14  Sergey Belyashov  <sergey.belyashov@gmail.com>
1417
1418         PR 25377
1419         * z80-dis.c (suffix): Use .db instruction to generate double
1420         prefix.
1421
1422 2020-01-14  Alan Modra  <amodra@gmail.com>
1423
1424         * z8k-dis.c (unpack_instr): Formatting.  Cast unsigned short
1425         values to unsigned before shifting.
1426
1427 2020-01-13  Thomas Troeger  <tstroege@gmx.de>
1428
1429         * arm-dis.c (print_insn_arm): Fill in insn info fields for control
1430         flow instructions.
1431         (print_insn_thumb16, print_insn_thumb32): Likewise.
1432         (print_insn): Initialize the insn info.
1433         * i386-dis.c (print_insn): Initialize the insn info fields, and
1434         detect jumps.
1435
1436 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
1437
1438         * arc-opc.c (C_NE): Make it required.
1439
1440 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
1441
1442         * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
1443         reserved register name.
1444
1445 2020-01-13  Alan Modra  <amodra@gmail.com>
1446
1447         * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
1448         (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
1449
1450 2020-01-13  Alan Modra  <amodra@gmail.com>
1451
1452         * wasm32-dis.c (print_insn_wasm32): Localise variables.  Store
1453         result of wasm_read_leb128 in a uint64_t and check that bits
1454         are not lost when copying to other locals.  Use uint32_t for
1455         most locals.  Use PRId64 when printing int64_t.
1456
1457 2020-01-13  Alan Modra  <amodra@gmail.com>
1458
1459         * score-dis.c: Formatting.
1460         * score7-dis.c: Formatting.
1461
1462 2020-01-13  Alan Modra  <amodra@gmail.com>
1463
1464         * score-dis.c (print_insn_score48): Use unsigned variables for
1465         unsigned values.  Don't left shift negative values.
1466         (print_insn_score32): Likewise.
1467         * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
1468
1469 2020-01-13  Alan Modra  <amodra@gmail.com>
1470
1471         * tic4x-dis.c (tic4x_print_register): Remove dead code.
1472
1473 2020-01-13  Alan Modra  <amodra@gmail.com>
1474
1475         * fr30-ibld.c: Regenerate.
1476
1477 2020-01-13  Alan Modra  <amodra@gmail.com>
1478
1479         * xgate-dis.c (print_insn): Don't left shift signed value.
1480         (ripBits): Formatting, use 1u.
1481
1482 2020-01-10  Alan Modra  <amodra@gmail.com>
1483
1484         * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
1485         * tilegx-opc.c (parse_insn_tilegx): Likewise.  Delete raw_opval.
1486
1487 2020-01-10  Alan Modra  <amodra@gmail.com>
1488
1489         * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
1490         and XRREG value earlier to avoid a shift with negative exponent.
1491         * m10200-dis.c (disassemble): Similarly.
1492
1493 2020-01-09  Nick Clifton  <nickc@redhat.com>
1494
1495         PR 25224
1496         * z80-dis.c (ld_ii_ii): Use correct cast.
1497
1498 2020-01-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
1499
1500         PR 25224
1501         * z80-dis.c (ld_ii_ii): Use character constant when checking
1502         opcode byte value.
1503
1504 2020-01-09  Jan Beulich  <jbeulich@suse.com>
1505
1506         * i386-dis.c (SEP_Fixup): New.
1507         (SEP): Define.
1508         (dis386_twobyte): Use it for sysenter/sysexit.
1509         (enum x86_64_isa): Change amd64 enumerator to value 1.
1510         (OP_J): Compare isa64 against intel64 instead of amd64.
1511         * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
1512         forms.
1513         * i386-tbl.h: Re-generate.
1514
1515 2020-01-08  Alan Modra  <amodra@gmail.com>
1516
1517         * z8k-dis.c: Include libiberty.h
1518         (instr_data_s): Make max_fetched unsigned.
1519         (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
1520         Don't exceed byte_info bounds.
1521         (output_instr): Make num_bytes unsigned.
1522         (unpack_instr): Likewise for nibl_count and loop.
1523         * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
1524         idx unsigned.
1525         * z8k-opc.h: Regenerate.
1526
1527 2020-01-07  Shahab Vahedi  <shahab@synopsys.com>
1528
1529         * arc-tbl.h (llock): Use 'LLOCK' as class.
1530         (llockd): Likewise.
1531         (scond): Use 'SCOND' as class.
1532         (scondd): Likewise.
1533         (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
1534         (scondd): Likewise.
1535
1536 2020-01-06  Alan Modra  <amodra@gmail.com>
1537
1538         * m32c-ibld.c: Regenerate.
1539
1540 2020-01-06  Alan Modra  <amodra@gmail.com>
1541
1542         PR 25344
1543         * z80-dis.c (suffix): Don't use a local struct buffer copy.
1544         Peek at next byte to prevent recursion on repeated prefix bytes.
1545         Ensure uninitialised "mybuf" is not accessed.
1546         (print_insn_z80): Don't zero n_fetch and n_used here,..
1547         (print_insn_z80_buf): ..do it here instead.
1548
1549 2020-01-04  Alan Modra  <amodra@gmail.com>
1550
1551         * m32r-ibld.c: Regenerate.
1552
1553 2020-01-04  Alan Modra  <amodra@gmail.com>
1554
1555         * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
1556
1557 2020-01-04  Alan Modra  <amodra@gmail.com>
1558
1559         * crx-dis.c (match_opcode): Avoid shift left of signed value.
1560
1561 2020-01-04  Alan Modra  <amodra@gmail.com>
1562
1563         * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
1564
1565 2020-01-03  Jan Beulich  <jbeulich@suse.com>
1566
1567         * aarch64-tbl.h (aarch64_opcode_table): Use
1568         SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
1569
1570 2020-01-03  Jan Beulich  <jbeulich@suse.com>
1571
1572         * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
1573         forms of SUDOT and USDOT.
1574
1575 2020-01-03  Jan Beulich  <jbeulich@suse.com>
1576
1577         * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
1578         uzip{1,2}.
1579         * opcodes/aarch64-dis-2.c: Re-generate.
1580
1581 2020-01-03  Jan Beulich  <jbeulich@suse.com>
1582
1583         * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
1584         FMMLA encoding.
1585         * opcodes/aarch64-dis-2.c: Re-generate.
1586
1587 2020-01-02  Sergey Belyashov  <sergey.belyashov@gmail.com>
1588
1589         * z80-dis.c: Add support for eZ80 and Z80 instructions.
1590
1591 2020-01-01  Alan Modra  <amodra@gmail.com>
1592
1593         Update year range in copyright notice of all files.
1594
1595 For older changes see ChangeLog-2019
1596 \f
1597 Copyright (C) 2020 Free Software Foundation, Inc.
1598
1599 Copying and distribution of this file, with or without modification,
1600 are permitted in any medium without royalty provided the copyright
1601 notice and this notice are preserved.
1602
1603 Local Variables:
1604 mode: change-log
1605 left-margin: 8
1606 fill-column: 74
1607 version-control: never
1608 End: