1 2020-07-07 Jan Beulich <jbeulich@suse.com>
3 * i386-dis.c (EVEX_W_0F3826_P_1, EVEX_W_0F3826_P_2,
4 EVEX_W_0F3828_P_1, EVEX_W_0F3829_P_1, EVEX_W_0F3854_P_2,
5 EVEX_W_0F3866_P_2, EVEX_W_0F3875_P_2, EVEX_W_0F387D_P_2,
6 EVEX_W_0F388D_P_2, EVEX_W_0F3A3E_P_2, EVEX_W_0F3A3F_P_2):
9 * i386-dis-evex-w.h: Move entries for opcodes 0F3826, 0F3826,
10 0F3828, 0F3829, 0F3854, 0F3866, 0F3875, 0F387D, 0F388D, 0F3A3E,
12 * i386-dis-evex-prefix.h: ... here.
14 2020-07-06 Jan Beulich <jbeulich@suse.com>
16 * i386-dis.c (VEX_LEN_0FXOP_09_80, VEX_LEN_0FXOP_09_81): Delete.
17 (VEX_LEN_0FXOP_09_82_W_0, VEX_LEN_0FXOP_09_83_W_0,
18 VEX_W_0FXOP_09_80, VEX_W_0FXOP_09_81, VEX_W_0FXOP_09_82,
19 VEX_W_0FXOP_09_83): New enumerators.
20 (xop_table): Reference the above.
21 (vex_len_table): Replace vfrczp* entries by vfrczs* ones.
22 (vex_w_table): New VEX_W_0FXOP_09_80, VEX_W_0FXOP_09_81,
23 VEX_W_0FXOP_09_82, and VEX_W_0FXOP_09_83 entries.
24 (get_valid_dis386): Return bad_opcode for XOP.PP != 0.
26 2020-07-06 Jan Beulich <jbeulich@suse.com>
28 * i386-dis.c (EVEX_W_0F3838_P_1,
29 EVEX_W_0F3839_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3855_P_2,
30 EVEX_W_0F3868_P_3, EVEX_W_0F3871_P_2, EVEX_W_0F3873_P_2,
31 EVEX_W_0F3A50_P_2, EVEX_W_0F3A51_P_2, EVEX_W_0F3A56_P_2,
32 EVEX_W_0F3A57_P_2, EVEX_W_0F3A66_P_2, EVEX_W_0F3A67_P_2,
33 EVEX_W_0F3A71_P_2, EVEX_W_0F3A73_P_2): Delete.
34 (putop): Centralize management of last[]. Delete SAVE_LAST.
35 * i386-dis-evex-w.h: Move entries for opcodes 0F3838, 0F3839,
36 0F3840, 0F3855, 0F3868, 0F3871, 0F3873, 0F3A50, 0F3A51, 0F3A56,
37 0F3A57, 0F3A66, 0F3A67, 0F3A71, and 0F3A73 ...
38 * i386-dis-evex-prefix.h: here.
40 2020-07-06 Jan Beulich <jbeulich@suse.com>
42 * i386-dis.c (MOD_EVEX_0F381A_P_2_W_0, MOD_EVEX_0F381A_P_2_W_1,
43 MOD_EVEX_0F381B_P_2_W_0, MOD_EVEX_0F381B_P_2_W_1,
44 MOD_EVEX_0F385A_P_2_W_0, MOD_EVEX_0F385A_P_2_W_1,
45 MOD_EVEX_0F385B_P_2_W_0, MOD_EVEX_0F385B_P_2_W_1): New
47 (EVEX_LEN_0F381A_P_2_W_0, EVEX_LEN_0F381A_P_2_W_1,
48 EVEX_LEN_0F381B_P_2_W_0, EVEX_LEN_0F381B_P_2_W_1,
49 EVEX_LEN_0F385A_P_2_W_0, EVEX_LEN_0F385A_P_2_W_1,
50 EVEX_LEN_0F385B_P_2_W_0, EVEX_LEN_0F385B_P_2_W_1): Rename to ...
51 (EVEX_LEN_0F381A_P_2_W_0_M_0, EVEX_LEN_0F381A_P_2_W_1_M_0,
52 EVEX_LEN_0F381B_P_2_W_0_M_0, EVEX_LEN_0F381B_P_2_W_1_M_0,
53 EVEX_LEN_0F385A_P_2_W_0_M_0, EVEX_LEN_0F385A_P_2_W_1_M_0,
54 EVEX_LEN_0F385B_P_2_W_0_M_0, EVEX_LEN_0F385B_P_2_W_1_M_0): ...
56 * i386-dis-evex-len.h: Adjust comments.
57 * i386-dis-evex-mod.h: New MOD_EVEX_0F381A_P_2_W_0,
58 MOD_EVEX_0F381A_P_2_W_1, MOD_EVEX_0F381B_P_2_W_0,
59 MOD_EVEX_0F381B_P_2_W_1, MOD_EVEX_0F385A_P_2_W_0,
60 MOD_EVEX_0F385A_P_2_W_1, MOD_EVEX_0F385B_P_2_W_0, and
61 MOD_EVEX_0F385B_P_2_W_1 table entries.
62 * i386-dis-evex-w.h: Reference mod_table[] for
63 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2, and
66 2020-07-06 Jan Beulich <jbeulich@suse.com>
68 * i386-dis-evex-len.h (vbroadcastf32x8, vbroadcasti32x8,
69 vinsertf32x8, vinsertf64x4, vextractf32x8, vextractf64x4): Use
71 (vinserti32x8, vinserti64x4, vextracti32x8, vextracti64x4):
72 Likewise. Mark 256-bit entries invalid.
74 2020-07-06 Jan Beulich <jbeulich@suse.com>
76 * i386-dis.c (PREFIX_EVEX_0F62, PREFIX_EVEX_0F6A,
77 PREFIX_EVEX_0F6B, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D,
78 PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4,
79 PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4,
80 PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE,
81 PREFIX_EVEX_0F382B): Delete.
82 (EVEX_W_0F62_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6B_P_2,
83 EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0FD2_P_2,
84 EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FF2_P_2,
85 EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2,
86 EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F382B_P_2): Rename
88 (EVEX_W_0F62, EVEX_W_0F6A, EVEX_W_0F6B, EVEX_W_0F6C,
89 EVEX_W_0F6D, EVEX_W_0FD2, EVEX_W_0FD3, EVEX_W_0FD4,
90 EVEX_W_0FF2, EVEX_W_0FF3, EVEX_W_0FF4, EVEX_W_0FFA,
91 EVEX_W_0FFB, EVEX_W_0FFE, EVEX_W_0F382B): ... these
93 * i386-dis-evex.h (evex_table): Reference VEX_W table entries
94 for opcodes 0F62, 0F6A, 0F6B, 0F6C, 0F6D, 0FD2, 0FD3, 0FD4,
95 0FF2, 0FF3, 0FF4, 0FFA, 0FFB, 0FFE, 0F382B.
96 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F62, PREFIX_EVEX_0F6A,
97 PREFIX_EVEX_0F6B, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D,
98 PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4,
99 PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4,
100 PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE,
101 PREFIX_EVEX_0F382B): Remove table entries.
102 * i386-dis-evex-w.h: Reference VEX table entries for opcodes
103 0F62, 0F6A, 0F6B, 0F6C, 0F6D, 0FD2, 0FD3, 0FD4, 0FF2, 0FF3,
104 0FF4, 0FFA, 0FFB, 0FFE, 0F382B.
106 2020-07-06 Jan Beulich <jbeulich@suse.com>
108 * i386-dis.c (EVEX_LEN_0F3816_P_2, EVEX_LEN_0F3836_P_2,
109 EVEX_LEN_0F3A00_P_2_W_1, EVEX_LEN_0F3A01_P_2_W_1): New
111 * i386-dis-evex-len.h (evex_len_table): New EVEX_LEN_0F3816_P_2,
112 EVEX_LEN_0F3836_P_2, EVEX_LEN_0F3A00_P_2_W_1, and
113 EVEX_LEN_0F3A01_P_2_W_1 table entries.
114 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Reference the above
117 2020-07-06 Jan Beulich <jbeulich@suse.com>
119 * i386-dis.c (EVEX_LEN_0FC4_P_2, EVEX_LEN_0FC5_P_2,
120 EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2, EVEX_LEN_0F3A16_P_2,
121 EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A20_P_2,
122 EVEX_LEN_0F3A21_P_2_W_0, EVEX_LEN_0F3A22_P_2): New enumerators.
123 * i386-dis-evex-len.h (evex_len_table): New EVEX_LEN_0FC4_P_2,
124 EVEX_LEN_0FC5_P_2, EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2,
125 EVEX_LEN_0F3A16_P_2, EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A20_P_2,
126 EVEX_LEN_0F3A21_P_2_W_0, and EVEX_LEN_0F3A22_P_2 table entries.
127 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Reference the above
130 2020-07-06 Jan Beulich <jbeulich@suse.com>
132 * i386-dis.c (PREFIX_EVEX_0F3A1D, EVEX_W_0F3A1D_P_2): Delete.
133 (VEX_W_0F3813_P_2, VEX_W_0F3A1D_P_2): New enumerators.
134 (prefix_table): Reference VEX_W_0F3813_P_2 and VEX_W_0F3A1D_P_2
136 (vex_w_table): New VEX_W_0F3813_P_2 and VEX_W_0F3A1D_P_2 table
138 * i386-dis-evex.h (evex_table): Reference VEX table entry for
140 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F3A1D): Delete table
142 * i386-dis-evex-w.h (EVEX_W_0F3A1D_P_2): Likewise.
144 2020-07-06 Jan Beulich <jbeulich@suse.com>
146 * i386-dis.c (PREFIX_EVEX_0F60, PREFIX_EVEX_0F61,
147 PREFIX_EVEX_0F63, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
148 PREFIX_EVEX_0F69, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5,
149 PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA,
150 PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
151 PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3,
152 PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8,
153 PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC,
154 PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
155 PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8,
156 PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD,
157 PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B,
158 PREFIX_EVEX_0F380C, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F381C,
159 PREFIX_EVEX_0F381D, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E,
160 PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879,
161 PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898,
162 PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D,
163 PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A6,
164 PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9,
165 PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE,
166 PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7,
167 PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA,
168 PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD,
169 PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38CF,
170 PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, PREFIX_EVEX_0F38DE,
171 PREFIX_EVEX_0F38DF, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A0F,
172 PREFIX_EVEX_0F3A44, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF,
173 EVEX_W_0F380C_P_2, EVEX_W_0F3818_P_2, EVEX_W_0F3858_P_2,
174 EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2, EVEX_W_0F3A04_P_2,
175 EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2): Delete.
176 (prefix_table): Add EXxEVexR to FMA table entries.
177 (OP_Rounding): Move abort() invocation.
178 * i386-dis-evex.h (evex_table): Reference VEX table for opcodes
179 0F60, 0F61, 0F63, 0F67, 0F68, 0F69, 0FD1, 0FD5, 0FD8, 0FD9,
180 0FDA, 0FDC, 0FDD, 0FDE, 0FE0, 0FE1, 0FE3, 0FE4, 0FE5, 0FE8,
181 0FE9, 0FEA, 0FEC, 0FED, 0FEE, 0FF1, 0FF5, 0FF6, 0FF8, 0FF9,
182 0FFC, 0FFD, 0F3800, 0F3804, 0F380B, 0F380C, 0F3818, 0F381C,
183 0F381D, 0F383C, 0F383E, 0F3858, 0F3878, 0F3879, 0F3896, 0F3897,
184 0F3898, 0F3899, 0F389C, 0F389D, 0F389E, 0F389F, 0F38A6, 0F38A7,
185 0F38A8, 0F38A9, 0F38AC, 0F38AD, 0F38AE, 0F38AF, 0F38B6, 0F38B7,
186 0F38B8, 0F38B9, 0F38BA, 0F38BB, 0F38BC, 0F38BD, 0F38BE, 0F38BF,
187 0F38CF, 0F38DC, 0F38DD, 0F38DE, 0F38DF, 0F3A04, 0F3A0F, 0F3A44,
189 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F60, PREFIX_EVEX_0F61,
190 PREFIX_EVEX_0F63, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
191 PREFIX_EVEX_0F69, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5,
192 PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA,
193 PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
194 PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3,
195 PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8,
196 PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC,
197 PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
198 PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8,
199 PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD,
200 PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B,
201 PREFIX_EVEX_0F380C, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F381C,
202 PREFIX_EVEX_0F381D, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E,
203 PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879,
204 PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898,
205 PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D,
206 PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A6,
207 PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9,
208 PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE,
209 PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7,
210 PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA,
211 PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD,
212 PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38CF,
213 PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, PREFIX_EVEX_0F38DE,
214 PREFIX_EVEX_0F38DF, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A0F,
215 PREFIX_EVEX_0F3A44, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF):
216 Delete table entries.
217 * i386-dis-evex-w.h (EVEX_W_0F380C_P_2, EVEX_W_0F3818_P_2,
218 EVEX_W_0F3858_P_2, EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2,
219 EVEX_W_0F3A04_P_2, EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2):
222 2020-07-06 Jan Beulich <jbeulich@suse.com>
224 * i386-dis.c (EXqScalarS): Delete.
225 (vex_len_table): Replace EXqScalarS by EXqVexScalarS.
226 * i386-dis-evex-w.h (vmovq): Use EXqVexScalarS.
228 2020-07-06 Jan Beulich <jbeulich@suse.com>
230 * i386-dis.c (safe-ctype.h): Include.
231 (EXdScalar, EXqScalar): Delete.
232 (d_scalar_mode, q_scalar_mode): Delete.
233 (prefix_table, vex_len_table): Use EXxmm_md in place of
234 EXdScalar and EXxmm_mq in place of EXqScalar.
235 (intel_operand_size, OP_E_memory, OP_EX): Remove uses of
236 d_scalar_mode and q_scalar_mode.
237 * i386-dis-evex-w.h (vmovss): Use EXxmm_md.
238 (vmovsd): Use EXxmm_mq.
240 2020-07-06 Yuri Chornoivan <yurchor@ukr.net>
243 * arc-dis.c: Fix spelling mistake.
244 * po/opcodes.pot: Regenerate.
246 2020-07-06 Nick Clifton <nickc@redhat.com>
248 * po/pt_BR.po: Updated Brazilian Portugugese translation.
249 * po/uk.po: Updated Ukranian translation.
251 2020-07-04 Nick Clifton <nickc@redhat.com>
253 * configure: Regenerate.
254 * po/opcodes.pot: Regenerate.
256 2020-07-04 Nick Clifton <nickc@redhat.com>
258 Binutils 2.35 branch created.
260 2020-07-02 H.J. Lu <hongjiu.lu@intel.com>
262 * i386-gen.c (opcode_modifiers): Add VexSwapSources.
263 * i386-opc.h (VexSwapSources): New.
264 (i386_opcode_modifier): Add vexswapsources.
265 * i386-opc.tbl: Add VexSwapSources to BMI2 and BMI instructions
266 with two source operands swapped.
267 * i386-tbl.h: Regenerated.
269 2020-06-30 Nelson Chu <nelson.chu@sifive.com>
271 * riscv-dis.c (print_insn_args, case 'E'): Updated. Let the
272 unprivileged CSR can also be initialized.
274 2020-06-29 Alan Modra <amodra@gmail.com>
276 * arm-dis.c: Use C style comments.
277 * cr16-opc.c: Likewise.
278 * ft32-dis.c: Likewise.
279 * moxie-opc.c: Likewise.
280 * tic54x-dis.c: Likewise.
281 * s12z-opc.c: Remove useless comment.
282 * xgate-dis.c: Likewise.
284 2020-06-26 H.J. Lu <hongjiu.lu@intel.com>
286 * i386-opc.tbl: Add a blank line.
288 2020-06-26 H.J. Lu <hongjiu.lu@intel.com>
290 * i386-gen.c (opcode_modifiers): Replace VecSIB with SIB.
291 (VecSIB128): Renamed to ...
293 (VecSIB256): Renamed to ...
295 (VecSIB512): Renamed to ...
297 (VecSIB): Renamed to ...
299 (i386_opcode_modifier): Replace vecsib with sib.
300 * i386-opc.tbl (VecSIB128): New.
301 (VecSIB256): Likewise.
302 (VecSIB512): Likewise.
303 Replace VecSIB=1, VecSIB=2 and VecSIB=3 with VecSIB128, VecSIB256
304 and VecSIB512, respectively.
306 2020-06-26 Jan Beulich <jbeulich@suse.com>
308 * i386-dis.c: Adjust description of I macro.
309 (x86_64_table): Drop use of I.
310 (float_mem): Replace use of I.
311 (putop): Remove handling of I. Adjust setting/clearing of "alt".
313 2020-06-26 Jan Beulich <jbeulich@suse.com>
315 * i386-dis.c: (print_insn): Avoid straight assignment to
316 priv.orig_sizeflag when processing -M sub-options.
318 2020-06-25 Jan Beulich <jbeulich@suse.com>
320 * i386-dis.c: Adjust description of J macro.
321 (dis386, x86_64_table, mod_table): Replace J.
322 (putop): Remove handling of J.
324 2020-06-25 Jan Beulich <jbeulich@suse.com>
326 * i386-dis.c: (float_mem): Reduce alternatives for fstpt and fldpt.
328 2020-06-25 Jan Beulich <jbeulich@suse.com>
330 * i386-dis.c: Adjust description of "LQ" macro.
331 (dis386_twobyte): Use LQ for sysret.
332 (putop): Adjust handling of LQ.
334 2020-06-22 Nelson Chu <nelson.chu@sifive.com>
336 * riscv-opc.c: Move the structures and functions to bfd/elfxx-riscv.c.
337 * riscv-dis.c: Include elfxx-riscv.h.
339 2020-06-18 H.J. Lu <hongjiu.lu@intel.com>
341 * i386-dis.c (prefix_table): Revert the last vmgexit change.
343 2020-06-17 Lili Cui <lili.cui@intel.com>
345 * i386-dis.c (prefix_table): Delete the incorrect vmgexit.
347 2020-06-14 H.J. Lu <hongjiu.lu@intel.com>
350 * i386-dis.c (prefix_table): Replace xsuspldtrk with xsusldtrk.
351 * i386-opc.tbl: Likewise.
352 * i386-tbl.h: Regenerated.
354 2020-06-12 Nelson Chu <nelson.chu@sifive.com>
356 * riscv-opc.c (priv_specs): Remove v1.9 and PRIV_SPEC_CLASS_1P9.
358 2020-06-11 Alex Coplan <alex.coplan@arm.com>
360 * aarch64-opc.c (SYSREG): New macro for describing system registers.
372 (SR_ID_PFR2): Likewise.
373 (SR_PROFILE): Likewise.
374 (SR_MEMTAG): Likewise.
375 (SR_SCXTNUM): Likewise.
376 (aarch64_sys_regs): Refactor to store feature information in the table.
377 (aarch64_sys_reg_supported_p): Collapse logic for system registers
378 that now describe their own features.
379 (aarch64_pstatefield_supported_p): Likewise.
381 2020-06-09 H.J. Lu <hongjiu.lu@intel.com>
383 * i386-dis.c (prefix_table): Fix a typo in comments.
385 2020-06-09 Jan Beulich <jbeulich@suse.com>
387 * i386-dis.c (rex_ignored): Delete.
388 (ckprefix): Drop rex_ignored initialization.
389 (get_valid_dis386): Drop setting of rex_ignored.
390 (print_insn): Drop checking of rex_ignored. Don't record data
391 size prefix as used with VEX-and-alike encodings.
393 2020-06-09 Jan Beulich <jbeulich@suse.com>
395 * i386-dis.c (MOD_0F12_PREFIX_2, MOD_0F16_PREFIX_2,
396 MOD_VEX_0F12_PREFIX_2, MOD_VEX_0F16_PREFIX_2): New enumerators.
397 (VEX_LEN_0F12_P_2, VEX_LEN_0F16_P_2): Delete.
398 (VEX_LEN_0F12_P_2_M_0, VEX_LEN_0F16_P_2_M_0): Define.
399 (prefix_table): Decode MOD for cases 2 of opcodes 0F12, 0F16,
400 VEX_0F12, and VEX_0F16.
401 (vex_len_table): Use X for vmovlp* and vmovh*s. Drop
402 VEX_LEN_0F12_P_2 and VEX_LEN_0F16_P_2 entries.
403 (mod_table): Use X for movlpX and movhpX. Drop PREFIX_OPCODE
404 from movlps and movhlps. New MOD_0F12_PREFIX_2,
405 MOD_0F16_PREFIX_2, MOD_VEX_0F12_PREFIX_2, and
406 MOD_VEX_0F16_PREFIX_2 entries.
408 2020-06-09 Jan Beulich <jbeulich@suse.com>
410 * i386-dis.c (MOD_EVEX_0F12_PREFIX_2, MOD_EVEX_0F13,
411 MOD_EVEX_0F16_PREFIX_2, MOD_EVEX_0F17, MOD_EVEX_0F2B): New enumerators.
412 (PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
413 PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29,
414 PREFIX_EVEX_0F2B, PREFIX_EVEX_0F54, PREFIX_EVEX_0F55,
415 PREFIX_EVEX_0F56, PREFIX_EVEX_0F57, PREFIX_EVEX_0FC6,
416 EVEX_W_0F10_P_0, EVEX_W_0F10_P_2, EVEX_W_0F11_P_0,
417 EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_2,
418 EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0,
419 EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2,
420 EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0,
421 EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2,
422 EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0,
423 EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2,
424 EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0,
425 EVEX_W_0F51_P_2, EVEX_W_0F54_P_0, EVEX_W_0F54_P_2,
426 EVEX_W_0F55_P_0, EVEX_W_0F55_P_2, EVEX_W_0F56_P_0,
427 EVEX_W_0F56_P_2, EVEX_W_0F57_P_0, EVEX_W_0F57_P_2,
428 EVEX_W_0F58_P_0, EVEX_W_0F58_P_2, EVEX_W_0F59_P_0,
429 EVEX_W_0F59_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2,
430 EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0,
431 EVEX_W_0F5E_P_2, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2,
432 EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0,
433 EVEX_W_0FC6_P_2): Delete.
434 (print_insn): Add EVEX.W vs embedded prefix consistency check
435 to prefix validation.
436 * i386-dis-evex.h (evex_table): Don't further descend for
437 vunpcklpX, vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX,
438 and vshufpX. Continue with MOD decoding for opcodes 0F13, 0F17,
440 * i386-dis-evex-mod.h: Add/adjust vmovlpX/vmovhpX entries.
441 * i386-dis-evex-prefix.h: Don't further descend for vmovupX,
442 vucomisX, vcomisX, vsqrtpX, vaddpX, vmulpX, vsubpX, vminpX,
443 vdivpX, vmaxpX, and vcmppX. Continue with MOD decoding for cases
444 2 of PREFIX_EVEX_0F12, PREFIX_EVEX_0F16, and PREFIX_EVEX_0F29.
445 Drop PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
446 PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F2B,
447 PREFIX_EVEX_0F54, PREFIX_EVEX_0F55, PREFIX_EVEX_0F56,
448 PREFIX_EVEX_0F57, and PREFIX_EVEX_0FC6 entries.
449 * i386-dis-evex-w.h: Drop EVEX_W_0F10_P_0, EVEX_W_0F10_P_2,
450 EVEX_W_0F11_P_0, EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0,
451 EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
452 EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2,
453 EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0,
454 EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
455 EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0,
456 EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
457 EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0,
458 EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_2,
459 EVEX_W_0F54_P_0, EVEX_W_0F54_P_2, EVEX_W_0F55_P_0,
460 EVEX_W_0F55_P_2, EVEX_W_0F56_P_0, EVEX_W_0F56_P_2,
461 EVEX_W_0F57_P_0, EVEX_W_0F57_P_2, EVEX_W_0F58_P_0,
462 EVEX_W_0F58_P_2, EVEX_W_0F59_P_0, EVEX_W_0F59_P_2,
463 EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2, EVEX_W_0F5D_P_0,
464 EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_2,
465 EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2, EVEX_W_0FC2_P_0,
466 EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0, and EVEX_W_0FC6_P_2 entries.
468 2020-06-09 Jan Beulich <jbeulich@suse.com>
470 * i386-dis.c (vex_table): Use PREFIX_OPCODE for vunpcklpX,
471 vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX and vshufpX.
472 (vex_len_table) : Likewise for vmovlpX, vmovhpX, vmovntpX, and
474 (print_insn): Drop pointless check against bad_opcode. Split
475 prefix validation into legacy and VEX-and-alike parts.
476 (putop): Re-work 'X' macro handling.
478 2020-06-09 Jan Beulich <jbeulich@suse.com>
480 * i386-dis.c (MOD_0F51): Rename to ...
481 (MOD_0F50): ... this.
483 2020-06-08 Alex Coplan <alex.coplan@arm.com>
485 * arm-dis.c (arm_opcodes): Add dfb.
486 (thumb32_opcodes): Add dfb.
488 2020-06-08 Jan Beulich <jbeulich@suse.com>
490 * i386-opc.h (reg_entry): Const-qualify reg_name field.
492 2020-06-06 Alan Modra <amodra@gmail.com>
494 * ppc-dis.c (ppc_opts): Accept -mpwr10/-Mpwr10.
496 2020-06-05 Alan Modra <amodra@gmail.com>
498 * cgen-dis.c (hash_insn_array): Increase size of buf. Assert
499 size is large enough.
501 2020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com>
503 * disassemble.c (disassemble_init_for_target): Set endian_code for
505 * bpf-desc.c: Regenerate.
506 * bpf-opc.c: Likewise.
507 * bpf-dis.c: Likewise.
509 2020-06-03 Jose E. Marchesi <jose.marchesi@oracle.com>
511 * cgen-opc.c (cgen_get_insn_value): Get an `endian' argument.
512 (cgen_put_insn_value): Likewise.
513 (cgen_lookup_insn): Pass endianness to cgen_{get,put}_insn_value.
514 * cgen-dis.in (print_insn): Likewise.
515 * cgen-ibld.in (insert_1): Likewise.
516 (insert_1): Likewise.
517 (insert_insn_normal): Likewise.
518 (extract_1): Likewise.
519 * bpf-dis.c: Regenerate.
520 * bpf-ibld.c: Likewise.
521 * bpf-ibld.c: Likewise.
522 * cgen-dis.in: Likewise.
523 * cgen-ibld.in: Likewise.
524 * cgen-opc.c: Likewise.
525 * epiphany-dis.c: Likewise.
526 * epiphany-ibld.c: Likewise.
527 * fr30-dis.c: Likewise.
528 * fr30-ibld.c: Likewise.
529 * frv-dis.c: Likewise.
530 * frv-ibld.c: Likewise.
531 * ip2k-dis.c: Likewise.
532 * ip2k-ibld.c: Likewise.
533 * iq2000-dis.c: Likewise.
534 * iq2000-ibld.c: Likewise.
535 * lm32-dis.c: Likewise.
536 * lm32-ibld.c: Likewise.
537 * m32c-dis.c: Likewise.
538 * m32c-ibld.c: Likewise.
539 * m32r-dis.c: Likewise.
540 * m32r-ibld.c: Likewise.
541 * mep-dis.c: Likewise.
542 * mep-ibld.c: Likewise.
543 * mt-dis.c: Likewise.
544 * mt-ibld.c: Likewise.
545 * or1k-dis.c: Likewise.
546 * or1k-ibld.c: Likewise.
547 * xc16x-dis.c: Likewise.
548 * xc16x-ibld.c: Likewise.
549 * xstormy16-dis.c: Likewise.
550 * xstormy16-ibld.c: Likewise.
552 2020-06-04 Jose E. Marchesi <jemarch@gnu.org>
554 * cgen-dis.in (cpu_desc_list): New field `insn_endian'.
555 (print_insn_): Handle instruction endian.
556 * bpf-dis.c: Regenerate.
557 * bpf-desc.c: Regenerate.
558 * epiphany-dis.c: Likewise.
559 * epiphany-desc.c: Likewise.
560 * fr30-dis.c: Likewise.
561 * fr30-desc.c: Likewise.
562 * frv-dis.c: Likewise.
563 * frv-desc.c: Likewise.
564 * ip2k-dis.c: Likewise.
565 * ip2k-desc.c: Likewise.
566 * iq2000-dis.c: Likewise.
567 * iq2000-desc.c: Likewise.
568 * lm32-dis.c: Likewise.
569 * lm32-desc.c: Likewise.
570 * m32c-dis.c: Likewise.
571 * m32c-desc.c: Likewise.
572 * m32r-dis.c: Likewise.
573 * m32r-desc.c: Likewise.
574 * mep-dis.c: Likewise.
575 * mep-desc.c: Likewise.
576 * mt-dis.c: Likewise.
577 * mt-desc.c: Likewise.
578 * or1k-dis.c: Likewise.
579 * or1k-desc.c: Likewise.
580 * xc16x-dis.c: Likewise.
581 * xc16x-desc.c: Likewise.
582 * xstormy16-dis.c: Likewise.
583 * xstormy16-desc.c: Likewise.
585 2020-06-03 Nick Clifton <nickc@redhat.com>
587 * po/sr.po: Updated Serbian translation.
589 2020-06-03 Nelson Chu <nelson.chu@sifive.com>
591 * riscv-opc.c (riscv_get_isa_spec_class): Change bfd_boolean to int.
592 (riscv_get_priv_spec_class): Likewise.
594 2020-06-01 Alan Modra <amodra@gmail.com>
596 * bpf-desc.c: Regenerate.
598 2020-05-28 Jose E. Marchesi <jose.marchesi@oracle.com>
599 David Faust <david.faust@oracle.com>
601 * bpf-desc.c: Regenerate.
602 * bpf-opc.h: Likewise.
603 * bpf-opc.c: Likewise.
604 * bpf-dis.c: Likewise.
606 2020-05-28 Alan Modra <amodra@gmail.com>
608 * nios2-dis.c (nios2_print_insn_arg): Avoid shift left of negative
611 2020-05-28 Alan Modra <amodra@gmail.com>
613 * ns32k-dis.c (print_insn_arg): Handle d value of 'f' for
615 (print_insn_ns32k): Revert last change.
617 2020-05-28 Nick Clifton <nickc@redhat.com>
619 * ns32k-dis.c (print_insn_ns32k): Change the arg_bufs array to
622 2020-05-26 Sandra Loosemore <sandra@codesourcery.com>
624 Fix extraction of signed constants in nios2 disassembler (again).
626 * nios2-dis.c (nios2_print_insn_arg): Add explicit casts to
627 extractions of signed fields.
629 2020-05-26 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
631 * s390-opc.txt: Relocate vector load/store instructions with
632 additional alignment parameter and change architecture level
633 constraint from z14 to z13.
635 2020-05-21 Alan Modra <amodra@gmail.com>
637 * arc-ext.c: Replace "if (x) free (x)" with "free (x)" throughout.
638 * sparc-dis.c: Likewise.
639 * tic4x-dis.c: Likewise.
640 * xtensa-dis.c: Likewise.
641 * bpf-desc.c: Regenerate.
642 * epiphany-desc.c: Regenerate.
643 * fr30-desc.c: Regenerate.
644 * frv-desc.c: Regenerate.
645 * ip2k-desc.c: Regenerate.
646 * iq2000-desc.c: Regenerate.
647 * lm32-desc.c: Regenerate.
648 * m32c-desc.c: Regenerate.
649 * m32r-desc.c: Regenerate.
650 * mep-asm.c: Regenerate.
651 * mep-desc.c: Regenerate.
652 * mt-desc.c: Regenerate.
653 * or1k-desc.c: Regenerate.
654 * xc16x-desc.c: Regenerate.
655 * xstormy16-desc.c: Regenerate.
657 2020-05-20 Nelson Chu <nelson.chu@sifive.com>
659 * riscv-opc.c (riscv_ext_version_table): The table used to store
660 all information about the supported spec and the corresponding ISA
661 versions. Currently, only Zicsr is supported to verify the
662 correctness of Z sub extension settings. Others will be supported
663 in the future patches.
664 (struct isa_spec_t, isa_specs): List for all supported ISA spec
665 classes and the corresponding strings.
666 (riscv_get_isa_spec_class): New function. Get the corresponding ISA
667 spec class by giving a ISA spec string.
668 * riscv-opc.c (struct priv_spec_t): New structure.
669 (struct priv_spec_t priv_specs): List for all supported privilege spec
670 classes and the corresponding strings.
671 (riscv_get_priv_spec_class): New function. Get the corresponding
672 privilege spec class by giving a spec string.
673 (riscv_get_priv_spec_name): New function. Get the corresponding
674 privilege spec string by giving a CSR version class.
675 * riscv-dis.c: Updated since DECLARE_CSR is changed.
676 * riscv-dis.c: Add new disassembler option -Mpriv-spec to dump the CSR
677 according to the chosen version. Build a hash table riscv_csr_hash to
678 store the valid CSR for the chosen pirv verison. Dump the direct
679 CSR address rather than it's name if it is invalid.
680 (parse_riscv_dis_option_without_args): New function. Parse the options
682 (parse_riscv_dis_option): Call parse_riscv_dis_option_without_args to
683 parse the options without arguments first, and then handle the options
684 with arguments. Add the new option -Mpriv-spec, which has argument.
685 * riscv-dis.c (print_riscv_disassembler_options): Add description
686 about the new OBJDUMP option.
688 2020-05-19 Peter Bergner <bergner@linux.ibm.com>
690 * ppc-opc.c (insert_ls, extract_ls): Handle 3-bit L fields and new
691 WC values on POWER10 sync, dcbf and wait instructions.
692 (insert_pl, extract_pl): New functions.
693 (L2OPT, LS, WC): Use insert_ls and extract_ls.
694 (LS3): New , 3-bit L for sync.
695 (LS3, L3OPT): New, 3-bit L for sync and dcbf.
696 (SC2, PL): New, 2-bit SC and PL for sync and wait.
697 (XWCPL_MASK, XL3RT_MASK, XSYNCLS_MASK): New instruction masks.
698 (XOPL3, XWCPL, XSYNCLS): New opcode macros.
699 (powerpc_opcodes) <dcbflp, dcbfps, dcbstps pause_short, phwsync,
700 plwsync, stcisync, stncisync, stsync, waitrsv>: New extended mnemonics.
701 <wait>: Enable PL operand on POWER10.
702 <dcbf>: Enable L3OPT operand on POWER10.
703 <sync>: Enable SC2 operand on POWER10.
705 2020-05-19 Stafford Horne <shorne@gmail.com>
708 * or1k-asm.c: Regenerate.
709 * or1k-desc.c: Regenerate.
710 * or1k-desc.h: Regenerate.
711 * or1k-dis.c: Regenerate.
712 * or1k-ibld.c: Regenerate.
713 * or1k-opc.c: Regenerate.
714 * or1k-opc.h: Regenerate.
715 * or1k-opinst.c: Regenerate.
717 2020-05-11 Alan Modra <amodra@gmail.com>
719 * ppc-opc (powerpc_opcodes): Add xscmpeqqp, xscmpgeqp, xscmpgtqp,
722 2020-05-11 Alan Modra <amodra@gmail.com>
724 * ppc-opc.c (powerpc_opcodes): Add lxvrbx, lxvrhx, lxvrwx, lxvrdx,
725 stxvrbx, stxvrhx, stxvrwx, stxvrdx.
727 2020-05-11 Alan Modra <amodra@gmail.com>
729 * ppc-opc.c (powerpc_opcodes): Add xvtlsbb.
731 2020-05-11 Alan Modra <amodra@gmail.com>
733 * ppc-opc.c (powerpc_opcodes): Add vstribl, vstribr, vstrihl, vstrihr,
734 vclrlb, vclrrb, vstribl., vstribr., vstrihl., vstrihr..
736 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
738 * ppc-opc.c (powerpc_opcodes) <setbc, setbcr, setnbc, setnbcr>: New
741 2020-05-11 Alan Modra <amodra@gmail.com>
743 * ppc-opc.c (UIM8, P_U8XX4_MASK): Define.
744 (powerpc_opcodes): Add vgnb, vcfuged, vpextd, vpdepd, vclzdm,
745 vctzdm, cntlzdm, pdepd, pextd, cfuged, cnttzdm.
746 (prefix_opcodes): Add xxeval.
748 2020-05-11 Alan Modra <amodra@gmail.com>
750 * ppc-opc.c (powerpc_opcodes): Add xxgenpcvbm, xxgenpcvhm,
751 xxgenpcvwm, xxgenpcvdm.
753 2020-05-11 Alan Modra <amodra@gmail.com>
755 * ppc-opc.c (MP, VXVAM_MASK): Define.
756 (VXVAPS_MASK): Use VXVA_MASK.
757 (powerpc_opcodes): Add mtvsrbmi, vexpandbm, vexpandhm, vexpandwm,
758 vexpanddm, vexpandqm, vextractbm, vextracthm, vextractwm,
759 vextractdm, vextractqm, mtvsrbm, mtvsrhm, mtvsrwm, mtvsrdm, mtvsrqm,
760 vcntmbb, vcntmbh, vcntmbw, vcntmbd.
762 2020-05-11 Alan Modra <amodra@gmail.com>
763 Peter Bergner <bergner@linux.ibm.com>
765 * ppc-opc.c (insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a):
767 (powerpc_operands): Define ACC, PMSK8, PMSK4, PMSK2, XMSK, YMSK,
768 YMSK2, XA6a, XA6ap, XB6a entries.
769 (PMMIRR, P_X_MASK, P_XX1_MASK, P_GER_MASK): Define
770 (P_GER2_MASK, P_GER4_MASK, P_GER8_MASK, P_GER64_MASK): Define.
772 (powerpc_opcodes): Add xxmfacc, xxmtacc, xxsetaccz,
773 xvi8ger4pp, xvi8ger4, xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger,
774 xvi4ger8pp, xvi4ger8, xvi16ger2spp, xvi16ger2s, xvbf16ger2pp,
775 xvbf16ger2, xvf64gerpp, xvf64ger, xvi16ger2, xvf16ger2np,
776 xvf32gernp, xvi8ger4spp, xvi16ger2pp, xvbf16ger2np, xvf64gernp,
777 xvf16ger2pn, xvf32gerpn, xvbf16ger2pn, xvf64gerpn, xvf16ger2nn,
778 xvf32gernn, xvbf16ger2nn, xvf64gernn, xvcvbf16sp, xvcvspbf16.
779 (prefix_opcodes): Add pmxvi8ger4pp, pmxvi8ger4, pmxvf16ger2pp,
780 pmxvf16ger2, pmxvf32gerpp, pmxvf32ger, pmxvi4ger8pp, pmxvi4ger8,
781 pmxvi16ger2spp, pmxvi16ger2s, pmxvbf16ger2pp, pmxvbf16ger2,
782 pmxvf64gerpp, pmxvf64ger, pmxvi16ger2, pmxvf16ger2np, pmxvf32gernp,
783 pmxvi8ger4spp, pmxvi16ger2pp, pmxvbf16ger2np, pmxvf64gernp,
784 pmxvf16ger2pn, pmxvf32gerpn, pmxvbf16ger2pn, pmxvf64gerpn,
785 pmxvf16ger2nn, pmxvf32gernn, pmxvbf16ger2nn, pmxvf64gernn.
787 2020-05-11 Alan Modra <amodra@gmail.com>
789 * ppc-opc.c (insert_imm32, extract_imm32): New functions.
790 (insert_xts, extract_xts): New functions.
791 (IMM32, UIM3, IX, UIM5, SH3, XTS, P8RR): Define.
792 (P_XX4_MASK, P_UXX4_MASK, VSOP, P_VS_MASK, P_VSI_MASK): Define.
793 (VXRC_MASK, VXSH_MASK): Define.
794 (powerpc_opcodes): Add vinsbvlx, vsldbi, vextdubvlx, vextdubvrx,
795 vextduhvlx, vextduhvrx, vextduwvlx, vextduwvrx, vextddvlx,
796 vextddvrx, vinshvlx, vinswvlx, vinsw, vinsbvrx, vinshvrx,
797 vinswvrx, vinsd, vinsblx, vsrdbi, vinshlx, vinswlx, vinsdlx,
798 vinsbrx, vinshrx, vinswrx, vinsdrx, lxvkq.
799 (prefix_opcodes): Add xxsplti32dx, xxspltidp, xxspltiw, xxblendvb,
800 xxblendvh, xxblendvw, xxblendvd, xxpermx.
802 2020-05-11 Alan Modra <amodra@gmail.com>
804 * ppc-opc.c (powerpc_opcodes): Add vrlq, vdivuq, vmsumcud, vrlqmi,
805 vmuloud, vcmpuq, vslq, vdivsq, vcmpsq, vrlqnm, vcmpequq, vmulosd,
806 vsrq, vdiveuq, vcmpgtuq, vmuleud, vsraq, vdivesq, vcmpgtsq, vmulesd,
807 vcmpequq., vextsd2q, vmoduq, vcmpgtuq., vmodsq, vcmpgtsq., xscvqpuqz,
808 xscvuqqp, xscvqpsqz, xscvsqqp, dcffixqq, dctfixqq.
810 2020-05-11 Alan Modra <amodra@gmail.com>
812 * ppc-opc.c (insert_xtp, extract_xtp): New functions.
813 (XTP, DQXP, DQXP_MASK): Define.
814 (powerpc_opcodes): Add lxvp, stxvp, lxvpx, stxvpx.
815 (prefix_opcodes): Add plxvp and pstxvp.
817 2020-05-11 Alan Modra <amodra@gmail.com>
819 * ppc-opc.c (powerpc_opcodes): Add vdivuw, vdivud, vdivsw, vmulld,
820 vdivsd, vmulhuw, vdiveuw, vmulhud, vdiveud, vmulhsw, vdivesw,
821 vmulhsd, vdivesd, vmoduw, vmodud, vmodsw, vmodsd.
823 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
825 * ppc-opc.c (powerpc_opcodes) <brd, brh, brw>: New mnemonics.
827 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
829 * ppc-opc.c (insert_l1opt, extract_l1opt): New functions.
831 (powerpc_opcodes) <paste.>: Add L operand for cpu POWER10.
833 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
835 * ppc-opc.c (powerpc_opcodes) <slbiag>: Add variant with L operand.
837 2020-05-11 Alan Modra <amodra@gmail.com>
839 * ppc-dis.c (powerpc_init_dialect): Default to "power10".
841 2020-05-11 Alan Modra <amodra@gmail.com>
843 * ppc-dis.c (ppc_opts): Add "power10" entry.
844 (print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming.
845 * ppc-opc.c (POWER10): Rename from POWERXX. Update all uses.
847 2020-05-11 Nick Clifton <nickc@redhat.com>
849 * po/fr.po: Updated French translation.
851 2020-04-30 Alex Coplan <alex.coplan@arm.com>
853 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
854 * aarch64-opc.c (fields): Add entry for FLD_imm16_2.
855 (operand_general_constraint_met_p): validate
856 AARCH64_OPND_UNDEFINED.
857 * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry
859 * aarch64-asm-2.c: Regenerated.
860 * aarch64-dis-2.c: Regenerated.
861 * aarch64-opc-2.c: Regenerated.
863 2020-04-29 Nick Clifton <nickc@redhat.com>
866 * sh-opc.h: Also use unsigned 8-bit immediate values for the LDRC
869 2020-04-29 Nick Clifton <nickc@redhat.com>
871 * po/sv.po: Updated Swedish translation.
873 2020-04-29 Nick Clifton <nickc@redhat.com>
876 * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U. Use
877 IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
878 * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
881 2020-04-21 Andreas Schwab <schwab@linux-m68k.org>
884 * m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
885 cmpi only on m68020up and cpu32.
887 2020-04-20 Sudakshina Das <sudi.das@arm.com>
889 * aarch64-asm.c (aarch64_ins_none): New.
890 * aarch64-asm.h (ins_none): New declaration.
891 * aarch64-dis.c (aarch64_ext_none): New.
892 * aarch64-dis.h (ext_none): New declaration.
893 * aarch64-opc.c (aarch64_print_operand): Update case for
894 AARCH64_OPND_BARRIER_PSB.
895 * aarch64-tbl.h (aarch64_opcode_table): Add tsb.
896 (AARCH64_OPERANDS): Update inserter/extracter for
897 AARCH64_OPND_BARRIER_PSB to use new dummy functions.
898 * aarch64-asm-2.c: Regenerated.
899 * aarch64-dis-2.c: Regenerated.
900 * aarch64-opc-2.c: Regenerated.
902 2020-04-20 Sudakshina Das <sudi.das@arm.com>
904 * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
905 (aarch64_feature_ras, RAS): Likewise.
906 (aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
907 (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
908 autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
909 autiaz, autiasp, autibz, autibsp to be CORE_INSN.
910 * aarch64-asm-2.c: Regenerated.
911 * aarch64-dis-2.c: Regenerated.
912 * aarch64-opc-2.c: Regenerated.
914 2020-04-17 Fredrik Strupe <fredrik@strupe.net>
916 * arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
917 (print_insn_neon): Support disassembly of conditional
920 2020-02-16 David Faust <david.faust@oracle.com>
922 * bpf-desc.c: Regenerate.
923 * bpf-desc.h: Likewise.
924 * bpf-opc.c: Regenerate.
925 * bpf-opc.h: Likewise.
927 2020-04-07 Lili Cui <lili.cui@intel.com>
929 * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
930 (prefix_table): New instructions (see prefixes above).
932 * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
933 CPU_ANY_TSXLDTRK_FLAGS.
934 (cpu_flags): Add CpuTSXLDTRK.
935 * i386-opc.h (enum): Add CpuTSXLDTRK.
936 (i386_cpu_flags): Add cputsxldtrk.
937 * i386-opc.tbl: Add XSUSPLDTRK insns.
938 * i386-init.h: Regenerate.
939 * i386-tbl.h: Likewise.
941 2020-04-02 Lili Cui <lili.cui@intel.com>
943 * i386-dis.c (prefix_table): New instructions serialize.
944 * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
945 CPU_ANY_SERIALIZE_FLAGS.
946 (cpu_flags): Add CpuSERIALIZE.
947 * i386-opc.h (enum): Add CpuSERIALIZE.
948 (i386_cpu_flags): Add cpuserialize.
949 * i386-opc.tbl: Add SERIALIZE insns.
950 * i386-init.h: Regenerate.
951 * i386-tbl.h: Likewise.
953 2020-03-26 Alan Modra <amodra@gmail.com>
955 * disassemble.h (opcodes_assert): Declare.
956 (OPCODES_ASSERT): Define.
957 * disassemble.c: Don't include assert.h. Include opintl.h.
958 (opcodes_assert): New function.
959 * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
960 (bfd_h8_disassemble): Reduce size of data array. Correctly
961 calculate maxlen. Omit insn decoding when insn length exceeds
962 maxlen. Exit from nibble loop when looking for E, before
963 accessing next data byte. Move processing of E outside loop.
964 Replace tests of maxlen in loop with assertions.
966 2020-03-26 Alan Modra <amodra@gmail.com>
968 * arc-dis.c (find_format): Init needs_limm. Simplify use of limm.
970 2020-03-25 Alan Modra <amodra@gmail.com>
972 * z80-dis.c (suffix): Init mybuf.
974 2020-03-22 Alan Modra <amodra@gmail.com>
976 * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
977 successflly read from section.
979 2020-03-22 Alan Modra <amodra@gmail.com>
981 * arc-dis.c (find_format): Use ISO C string concatenation rather
982 than line continuation within a string. Don't access needs_limm
983 before testing opcode != NULL.
985 2020-03-22 Alan Modra <amodra@gmail.com>
987 * ns32k-dis.c (print_insn_arg): Update comment.
988 (print_insn_ns32k): Reduce size of index_offset array, and
989 initialize, passing -1 to print_insn_arg for args that are not
990 an index. Don't exit arg loop early. Abort on bad arg number.
992 2020-03-22 Alan Modra <amodra@gmail.com>
994 * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
995 * s12z-opc.c: Formatting.
996 (operands_f): Return an int.
997 (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
998 (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
999 (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
1000 (exg_sex_discrim): Likewise.
1001 (create_immediate_operand, create_bitfield_operand),
1002 (create_register_operand_with_size, create_register_all_operand),
1003 (create_register_all16_operand, create_simple_memory_operand),
1004 (create_memory_operand, create_memory_auto_operand): Don't
1005 segfault on malloc failure.
1006 (z_ext24_decode): Return an int status, negative on fail, zero
1008 (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
1009 (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
1010 (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
1011 (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
1012 (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
1013 (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
1014 (loop_primitive_decode, shift_decode, psh_pul_decode),
1015 (bit_field_decode): Similarly.
1016 (z_decode_signed_value, decode_signed_value): Similarly. Add arg
1017 to return value, update callers.
1018 (x_opr_decode_with_size): Check all reads, returning NULL on fail.
1019 Don't segfault on NULL operand.
1020 (decode_operation): Return OP_INVALID on first fail.
1021 (decode_s12z): Check all reads, returning -1 on fail.
1023 2020-03-20 Alan Modra <amodra@gmail.com>
1025 * metag-dis.c (print_insn_metag): Don't ignore status from
1028 2020-03-20 Alan Modra <amodra@gmail.com>
1030 * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
1031 Initialize parts of buffer not written when handling a possible
1032 2-byte insn at end of section. Don't attempt decoding of such
1033 an insn by the 4-byte machinery.
1035 2020-03-20 Alan Modra <amodra@gmail.com>
1037 * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
1038 partially filled buffer. Prevent lookup of 4-byte insns when
1039 only VLE 2-byte insns are possible due to section size. Print
1040 ".word" rather than ".long" for 2-byte leftovers.
1042 2020-03-17 Sergey Belyashov <sergey.belyashov@gmail.com>
1045 * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
1047 2020-03-13 Jan Beulich <jbeulich@suse.com>
1049 * i386-dis.c (X86_64_0D): Rename to ...
1050 (X86_64_0E): ... this.
1052 2020-03-09 H.J. Lu <hongjiu.lu@intel.com>
1054 * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
1055 * Makefile.in: Regenerated.
1057 2020-03-09 Jan Beulich <jbeulich@suse.com>
1059 * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
1061 * i386-tbl.h: Re-generate.
1063 2020-03-09 Jan Beulich <jbeulich@suse.com>
1065 * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
1066 vprot*, vpsha*, and vpshl*.
1067 * i386-tbl.h: Re-generate.
1069 2020-03-09 Jan Beulich <jbeulich@suse.com>
1071 * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
1072 vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
1073 * i386-tbl.h: Re-generate.
1075 2020-03-09 Jan Beulich <jbeulich@suse.com>
1077 * i386-gen.c (set_bitfield): Ignore zero-length field names.
1078 * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
1079 cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
1080 * i386-tbl.h: Re-generate.
1082 2020-03-09 Jan Beulich <jbeulich@suse.com>
1084 * i386-gen.c (struct template_arg, struct template_instance,
1085 struct template_param, struct template, templates,
1086 parse_template, expand_templates): New.
1087 (process_i386_opcodes): Various local variables moved to
1088 expand_templates. Call parse_template and expand_templates.
1089 * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
1090 * i386-tbl.h: Re-generate.
1092 2020-03-06 Jan Beulich <jbeulich@suse.com>
1094 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
1095 vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
1096 register and memory source templates. Replace VexW= by VexW*
1098 * i386-tbl.h: Re-generate.
1100 2020-03-06 Jan Beulich <jbeulich@suse.com>
1102 * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
1103 VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
1104 * i386-tbl.h: Re-generate.
1106 2020-03-06 Jan Beulich <jbeulich@suse.com>
1108 * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
1109 * i386-tbl.h: Re-generate.
1111 2020-03-06 Jan Beulich <jbeulich@suse.com>
1113 * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
1114 (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
1115 pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
1116 VexW0 on SSE2AVX variants.
1117 (vmovq): Drop NoRex64 from XMM/XMM variants.
1118 (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
1119 vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
1120 applicable use VexW0.
1121 * i386-tbl.h: Re-generate.
1123 2020-03-06 Jan Beulich <jbeulich@suse.com>
1125 * i386-gen.c (opcode_modifiers): Remove Rex64 field.
1126 * i386-opc.h (Rex64): Delete.
1127 (struct i386_opcode_modifier): Remove rex64 field.
1128 * i386-opc.tbl (crc32): Drop Rex64.
1129 Replace Rex64 with Size64 everywhere else.
1130 * i386-tbl.h: Re-generate.
1132 2020-03-06 Jan Beulich <jbeulich@suse.com>
1134 * i386-dis.c (OP_E_memory): Exclude recording of used address
1135 prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
1136 addressed memory operands for MPX insns.
1138 2020-03-06 Jan Beulich <jbeulich@suse.com>
1140 * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
1141 invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
1142 adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
1143 (ptwrite): Split into non-64-bit and 64-bit forms.
1144 * i386-tbl.h: Re-generate.
1146 2020-03-06 Jan Beulich <jbeulich@suse.com>
1148 * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
1150 * i386-tbl.h: Re-generate.
1152 2020-03-04 Jan Beulich <jbeulich@suse.com>
1154 * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
1155 (prefix_table): Move vmmcall here. Add vmgexit.
1156 (rm_table): Replace vmmcall entry by prefix_table[] escape.
1157 * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
1158 (cpu_flags): Add CpuSEV_ES entry.
1159 * i386-opc.h (CpuSEV_ES): New.
1160 (union i386_cpu_flags): Add cpusev_es field.
1161 * i386-opc.tbl (vmgexit): New.
1162 * i386-init.h, i386-tbl.h: Re-generate.
1164 2020-03-03 H.J. Lu <hongjiu.lu@intel.com>
1166 * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
1168 * i386-opc.h (IGNORESIZE): New.
1169 (DEFAULTSIZE): Likewise.
1170 (IgnoreSize): Removed.
1171 (DefaultSize): Likewise.
1172 (MnemonicSize): New.
1173 (i386_opcode_modifier): Replace ignoresize/defaultsize with
1175 * i386-opc.tbl (IgnoreSize): New.
1176 (DefaultSize): Likewise.
1177 * i386-tbl.h: Regenerated.
1179 2020-03-03 Sergey Belyashov <sergey.belyashov@gmail.com>
1182 * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
1185 2020-03-03 H.J. Lu <hongjiu.lu@intel.com>
1188 * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
1189 vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
1190 * i386-tbl.h: Regenerated.
1192 2020-02-26 Alan Modra <amodra@gmail.com>
1194 * aarch64-asm.c: Indent labels correctly.
1195 * aarch64-dis.c: Likewise.
1196 * aarch64-gen.c: Likewise.
1197 * aarch64-opc.c: Likewise.
1198 * alpha-dis.c: Likewise.
1199 * i386-dis.c: Likewise.
1200 * nds32-asm.c: Likewise.
1201 * nfp-dis.c: Likewise.
1202 * visium-dis.c: Likewise.
1204 2020-02-25 Claudiu Zissulescu <claziss@gmail.com>
1206 * arc-regs.h (int_vector_base): Make it available for all ARC
1209 2020-02-20 Nelson Chu <nelson.chu@sifive.com>
1211 * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
1214 2020-02-19 Nelson Chu <nelson.chu@sifive.com>
1216 * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
1217 c.mv/c.li if rs1 is zero.
1219 2020-02-17 H.J. Lu <hongjiu.lu@intel.com>
1221 * i386-gen.c (cpu_flag_init): Replace CpuABM with
1222 CpuLZCNT|CpuPOPCNT. Add CpuPOPCNT to CPU_SSE4_2_FLAGS. Add
1224 (cpu_flags): Remove CpuABM. Add CpuPOPCNT.
1225 * i386-opc.h (CpuABM): Removed.
1227 (i386_cpu_flags): Remove cpuabm. Add cpupopcnt.
1228 * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
1229 popcnt. Remove CpuABM from lzcnt.
1230 * i386-init.h: Regenerated.
1231 * i386-tbl.h: Likewise.
1233 2020-02-17 Jan Beulich <jbeulich@suse.com>
1235 * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
1236 Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
1237 VexW1 instead of open-coding them.
1238 * i386-tbl.h: Re-generate.
1240 2020-02-17 Jan Beulich <jbeulich@suse.com>
1242 * i386-opc.tbl (AddrPrefixOpReg): Define.
1243 (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
1244 umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
1245 templates. Drop NoRex64.
1246 * i386-tbl.h: Re-generate.
1248 2020-02-17 Jan Beulich <jbeulich@suse.com>
1251 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
1252 vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
1253 into Intel syntax instance (with Unpsecified) and AT&T one
1255 (vcvtneps2bf16): Likewise, along with folding the two so far
1257 * i386-tbl.h: Re-generate.
1259 2020-02-16 H.J. Lu <hongjiu.lu@intel.com>
1261 * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
1262 CPU_ANY_SSE4A_FLAGS.
1264 2020-02-17 Alan Modra <amodra@gmail.com>
1266 * i386-gen.c (cpu_flag_init): Correct last change.
1268 2020-02-16 H.J. Lu <hongjiu.lu@intel.com>
1270 * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS. Remove
1273 2020-02-14 H.J. Lu <hongjiu.lu@intel.com>
1275 * i386-opc.tbl (movsx): Remove Intel syntax comments.
1278 2020-02-14 Jan Beulich <jbeulich@suse.com>
1281 * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
1282 destination for Cpu64-only variant.
1283 (movzx): Fold patterns.
1284 * i386-tbl.h: Re-generate.
1286 2020-02-13 Jan Beulich <jbeulich@suse.com>
1288 * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
1289 CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
1290 CPU_ANY_SSE4_FLAGS entry.
1291 * i386-init.h: Re-generate.
1293 2020-02-12 Jan Beulich <jbeulich@suse.com>
1295 * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
1296 with Unspecified, making the present one AT&T syntax only.
1297 * i386-tbl.h: Re-generate.
1299 2020-02-12 Jan Beulich <jbeulich@suse.com>
1301 * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
1302 * i386-tbl.h: Re-generate.
1304 2020-02-12 Jan Beulich <jbeulich@suse.com>
1307 * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
1308 * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
1309 Amd64 and Intel64 templates.
1310 (call, jmp): Likewise for far indirect variants. Dro
1312 * i386-tbl.h: Re-generate.
1314 2020-02-11 Jan Beulich <jbeulich@suse.com>
1316 * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
1317 * i386-opc.h (ShortForm): Delete.
1318 (struct i386_opcode_modifier): Remove shortform field.
1319 * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
1320 fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
1321 fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
1322 ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
1324 * i386-tbl.h: Re-generate.
1326 2020-02-11 Jan Beulich <jbeulich@suse.com>
1328 * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
1329 fucompi): Drop ShortForm from operand-less templates.
1330 * i386-tbl.h: Re-generate.
1332 2020-02-11 Alan Modra <amodra@gmail.com>
1334 * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
1335 * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
1336 * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
1337 * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
1338 * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
1340 2020-02-10 Matthew Malcomson <matthew.malcomson@arm.com>
1342 * arm-dis.c (print_insn_cde): Define 'V' parse character.
1343 (cde_opcodes): Add VCX* instructions.
1345 2020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
1346 Matthew Malcomson <matthew.malcomson@arm.com>
1348 * arm-dis.c (struct cdeopcode32): New.
1349 (CDE_OPCODE): New macro.
1350 (cde_opcodes): New disassembly table.
1351 (regnames): New option to table.
1352 (cde_coprocs): New global variable.
1353 (print_insn_cde): New
1354 (print_insn_thumb32): Use print_insn_cde.
1355 (parse_arm_disassembler_options): Parse coprocN args.
1357 2020-02-10 H.J. Lu <hongjiu.lu@intel.com>
1360 * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
1362 * i386-opc.h (AMD64): Removed.
1363 (Intel64): Likewose.
1365 (INTEL64): Likewise.
1366 (INTEL64ONLY): Likewise.
1367 (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
1368 * i386-opc.tbl (Amd64): New.
1369 (Intel64): Likewise.
1370 (Intel64Only): Likewise.
1371 Replace AMD64 with Amd64. Update sysenter/sysenter with
1372 Cpu64 and Intel64Only. Remove AMD64 from sysenter/sysenter.
1373 * i386-tbl.h: Regenerated.
1375 2020-02-07 Sergey Belyashov <sergey.belyashov@gmail.com>
1378 * z80-dis.c: Add support for GBZ80 opcodes.
1380 2020-02-04 Alan Modra <amodra@gmail.com>
1382 * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
1384 2020-02-03 Alan Modra <amodra@gmail.com>
1386 * m32c-ibld.c: Regenerate.
1388 2020-02-01 Alan Modra <amodra@gmail.com>
1390 * frv-ibld.c: Regenerate.
1392 2020-01-31 Jan Beulich <jbeulich@suse.com>
1394 * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
1395 (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
1396 (OP_E_memory): Replace xmm_mdq_mode case label by
1397 vex_scalar_w_dq_mode one.
1398 * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
1400 2020-01-31 Jan Beulich <jbeulich@suse.com>
1402 * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
1403 (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
1404 vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
1405 (intel_operand_size): Drop vex_w_dq_mode case label.
1407 2020-01-31 Richard Sandiford <richard.sandiford@arm.com>
1409 * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
1410 Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
1412 2020-01-30 Alan Modra <amodra@gmail.com>
1414 * m32c-ibld.c: Regenerate.
1416 2020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com>
1418 * bpf-opc.c: Regenerate.
1420 2020-01-30 Jan Beulich <jbeulich@suse.com>
1422 * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
1423 (dis386): Use them to replace C2/C3 table entries.
1424 (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
1425 * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
1426 ones. Use Size64 instead of DefaultSize on Intel64 ones.
1427 * i386-tbl.h: Re-generate.
1429 2020-01-30 Jan Beulich <jbeulich@suse.com>
1431 * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
1433 (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
1435 * i386-tbl.h: Re-generate.
1437 2020-01-30 Alan Modra <amodra@gmail.com>
1439 * tic4x-dis.c (tic4x_dp): Make unsigned.
1441 2020-01-27 H.J. Lu <hongjiu.lu@intel.com>
1442 Jan Beulich <jbeulich@suse.com>
1445 * i386-dis.c (MOVSXD_Fixup): New function.
1446 (movsxd_mode): New enum.
1447 (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
1448 (intel_operand_size): Handle movsxd_mode.
1449 (OP_E_register): Likewise.
1451 * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
1452 register on movsxd. Add movsxd with 16-bit destination register
1453 for AMD64 and Intel64 ISAs.
1454 * i386-tbl.h: Regenerated.
1456 2020-01-27 Tamar Christina <tamar.christina@arm.com>
1459 * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
1460 * aarch64-asm-2.c: Regenerate
1461 * aarch64-dis-2.c: Likewise.
1462 * aarch64-opc-2.c: Likewise.
1464 2020-01-21 Jan Beulich <jbeulich@suse.com>
1466 * i386-opc.tbl (sysret): Drop DefaultSize.
1467 * i386-tbl.h: Re-generate.
1469 2020-01-21 Jan Beulich <jbeulich@suse.com>
1471 * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
1473 (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
1474 * i386-tbl.h: Re-generate.
1476 2020-01-20 Nick Clifton <nickc@redhat.com>
1478 * po/de.po: Updated German translation.
1479 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1480 * po/uk.po: Updated Ukranian translation.
1482 2020-01-20 Alan Modra <amodra@gmail.com>
1484 * hppa-dis.c (fput_const): Remove useless cast.
1486 2020-01-20 Alan Modra <amodra@gmail.com>
1488 * arm-dis.c (print_insn_arm): Wrap 'T' value.
1490 2020-01-18 Nick Clifton <nickc@redhat.com>
1492 * configure: Regenerate.
1493 * po/opcodes.pot: Regenerate.
1495 2020-01-18 Nick Clifton <nickc@redhat.com>
1497 Binutils 2.34 branch created.
1499 2020-01-17 Christian Biesinger <cbiesinger@google.com>
1501 * opintl.h: Fix spelling error (seperate).
1503 2020-01-17 H.J. Lu <hongjiu.lu@intel.com>
1505 * i386-opc.tbl: Add {vex} pseudo prefix.
1506 * i386-tbl.h: Regenerated.
1508 2020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1511 * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
1512 (neon_opcodes): Likewise.
1513 (select_arm_features): Make sure we enable MVE bits when selecting
1514 armv8.1-m.main. Make sure we do not enable MVE bits when not selecting
1517 2020-01-16 Jan Beulich <jbeulich@suse.com>
1519 * i386-opc.tbl: Drop stale comment from XOP section.
1521 2020-01-16 Jan Beulich <jbeulich@suse.com>
1523 * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
1524 (extractps): Add VexWIG to SSE2AVX forms.
1525 * i386-tbl.h: Re-generate.
1527 2020-01-16 Jan Beulich <jbeulich@suse.com>
1529 * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
1530 Size64 from and use VexW1 on SSE2AVX forms.
1531 (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
1532 VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
1533 * i386-tbl.h: Re-generate.
1535 2020-01-15 Alan Modra <amodra@gmail.com>
1537 * tic4x-dis.c (tic4x_version): Make unsigned long.
1538 (optab, optab_special, registernames): New file scope vars.
1539 (tic4x_print_register): Set up registernames rather than
1540 malloc'd registertable.
1541 (tic4x_disassemble): Delete optable and optable_special. Use
1542 optab and optab_special instead. Throw away old optab,
1543 optab_special and registernames when info->mach changes.
1545 2020-01-14 Sergey Belyashov <sergey.belyashov@gmail.com>
1548 * z80-dis.c (suffix): Use .db instruction to generate double
1551 2020-01-14 Alan Modra <amodra@gmail.com>
1553 * z8k-dis.c (unpack_instr): Formatting. Cast unsigned short
1554 values to unsigned before shifting.
1556 2020-01-13 Thomas Troeger <tstroege@gmx.de>
1558 * arm-dis.c (print_insn_arm): Fill in insn info fields for control
1560 (print_insn_thumb16, print_insn_thumb32): Likewise.
1561 (print_insn): Initialize the insn info.
1562 * i386-dis.c (print_insn): Initialize the insn info fields, and
1565 2012-01-13 Claudiu Zissulescu <claziss@gmail.com>
1567 * arc-opc.c (C_NE): Make it required.
1569 2012-01-13 Claudiu Zissulescu <claziss@gmail.com>
1571 * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
1572 reserved register name.
1574 2020-01-13 Alan Modra <amodra@gmail.com>
1576 * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
1577 (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
1579 2020-01-13 Alan Modra <amodra@gmail.com>
1581 * wasm32-dis.c (print_insn_wasm32): Localise variables. Store
1582 result of wasm_read_leb128 in a uint64_t and check that bits
1583 are not lost when copying to other locals. Use uint32_t for
1584 most locals. Use PRId64 when printing int64_t.
1586 2020-01-13 Alan Modra <amodra@gmail.com>
1588 * score-dis.c: Formatting.
1589 * score7-dis.c: Formatting.
1591 2020-01-13 Alan Modra <amodra@gmail.com>
1593 * score-dis.c (print_insn_score48): Use unsigned variables for
1594 unsigned values. Don't left shift negative values.
1595 (print_insn_score32): Likewise.
1596 * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
1598 2020-01-13 Alan Modra <amodra@gmail.com>
1600 * tic4x-dis.c (tic4x_print_register): Remove dead code.
1602 2020-01-13 Alan Modra <amodra@gmail.com>
1604 * fr30-ibld.c: Regenerate.
1606 2020-01-13 Alan Modra <amodra@gmail.com>
1608 * xgate-dis.c (print_insn): Don't left shift signed value.
1609 (ripBits): Formatting, use 1u.
1611 2020-01-10 Alan Modra <amodra@gmail.com>
1613 * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
1614 * tilegx-opc.c (parse_insn_tilegx): Likewise. Delete raw_opval.
1616 2020-01-10 Alan Modra <amodra@gmail.com>
1618 * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
1619 and XRREG value earlier to avoid a shift with negative exponent.
1620 * m10200-dis.c (disassemble): Similarly.
1622 2020-01-09 Nick Clifton <nickc@redhat.com>
1625 * z80-dis.c (ld_ii_ii): Use correct cast.
1627 2020-01-03 Sergey Belyashov <sergey.belyashov@gmail.com>
1630 * z80-dis.c (ld_ii_ii): Use character constant when checking
1633 2020-01-09 Jan Beulich <jbeulich@suse.com>
1635 * i386-dis.c (SEP_Fixup): New.
1637 (dis386_twobyte): Use it for sysenter/sysexit.
1638 (enum x86_64_isa): Change amd64 enumerator to value 1.
1639 (OP_J): Compare isa64 against intel64 instead of amd64.
1640 * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
1642 * i386-tbl.h: Re-generate.
1644 2020-01-08 Alan Modra <amodra@gmail.com>
1646 * z8k-dis.c: Include libiberty.h
1647 (instr_data_s): Make max_fetched unsigned.
1648 (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
1649 Don't exceed byte_info bounds.
1650 (output_instr): Make num_bytes unsigned.
1651 (unpack_instr): Likewise for nibl_count and loop.
1652 * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
1654 * z8k-opc.h: Regenerate.
1656 2020-01-07 Shahab Vahedi <shahab@synopsys.com>
1658 * arc-tbl.h (llock): Use 'LLOCK' as class.
1660 (scond): Use 'SCOND' as class.
1662 (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
1665 2020-01-06 Alan Modra <amodra@gmail.com>
1667 * m32c-ibld.c: Regenerate.
1669 2020-01-06 Alan Modra <amodra@gmail.com>
1672 * z80-dis.c (suffix): Don't use a local struct buffer copy.
1673 Peek at next byte to prevent recursion on repeated prefix bytes.
1674 Ensure uninitialised "mybuf" is not accessed.
1675 (print_insn_z80): Don't zero n_fetch and n_used here,..
1676 (print_insn_z80_buf): ..do it here instead.
1678 2020-01-04 Alan Modra <amodra@gmail.com>
1680 * m32r-ibld.c: Regenerate.
1682 2020-01-04 Alan Modra <amodra@gmail.com>
1684 * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
1686 2020-01-04 Alan Modra <amodra@gmail.com>
1688 * crx-dis.c (match_opcode): Avoid shift left of signed value.
1690 2020-01-04 Alan Modra <amodra@gmail.com>
1692 * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
1694 2020-01-03 Jan Beulich <jbeulich@suse.com>
1696 * aarch64-tbl.h (aarch64_opcode_table): Use
1697 SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
1699 2020-01-03 Jan Beulich <jbeulich@suse.com>
1701 * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
1702 forms of SUDOT and USDOT.
1704 2020-01-03 Jan Beulich <jbeulich@suse.com>
1706 * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
1708 * opcodes/aarch64-dis-2.c: Re-generate.
1710 2020-01-03 Jan Beulich <jbeulich@suse.com>
1712 * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
1714 * opcodes/aarch64-dis-2.c: Re-generate.
1716 2020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com>
1718 * z80-dis.c: Add support for eZ80 and Z80 instructions.
1720 2020-01-01 Alan Modra <amodra@gmail.com>
1722 Update year range in copyright notice of all files.
1724 For older changes see ChangeLog-2019
1726 Copyright (C) 2020 Free Software Foundation, Inc.
1728 Copying and distribution of this file, with or without modification,
1729 are permitted in any medium without royalty provided the copyright
1730 notice and this notice are preserved.
1736 version-control: never