1 2020-07-06 Jan Beulich <jbeulich@suse.com>
3 * i386-dis.c (EVEX_LEN_0FC4_P_2, EVEX_LEN_0FC5_P_2,
4 EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2, EVEX_LEN_0F3A16_P_2,
5 EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A20_P_2,
6 EVEX_LEN_0F3A21_P_2_W_0, EVEX_LEN_0F3A22_P_2): New enumerators.
7 * i386-dis-evex-len.h (evex_len_table): New EVEX_LEN_0FC4_P_2,
8 EVEX_LEN_0FC5_P_2, EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2,
9 EVEX_LEN_0F3A16_P_2, EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A20_P_2,
10 EVEX_LEN_0F3A21_P_2_W_0, and EVEX_LEN_0F3A22_P_2 table entries.
11 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Reference the above
14 2020-07-06 Jan Beulich <jbeulich@suse.com>
16 * i386-dis.c (PREFIX_EVEX_0F3A1D, EVEX_W_0F3A1D_P_2): Delete.
17 (VEX_W_0F3813_P_2, VEX_W_0F3A1D_P_2): New enumerators.
18 (prefix_table): Reference VEX_W_0F3813_P_2 and VEX_W_0F3A1D_P_2
20 (vex_w_table): New VEX_W_0F3813_P_2 and VEX_W_0F3A1D_P_2 table
22 * i386-dis-evex.h (evex_table): Reference VEX table entry for
24 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F3A1D): Delete table
26 * i386-dis-evex-w.h (EVEX_W_0F3A1D_P_2): Likewise.
28 2020-07-06 Jan Beulich <jbeulich@suse.com>
30 * i386-dis.c (PREFIX_EVEX_0F60, PREFIX_EVEX_0F61,
31 PREFIX_EVEX_0F63, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
32 PREFIX_EVEX_0F69, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5,
33 PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA,
34 PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
35 PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3,
36 PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8,
37 PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC,
38 PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
39 PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8,
40 PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD,
41 PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B,
42 PREFIX_EVEX_0F380C, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F381C,
43 PREFIX_EVEX_0F381D, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E,
44 PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879,
45 PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898,
46 PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D,
47 PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A6,
48 PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9,
49 PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE,
50 PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7,
51 PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA,
52 PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD,
53 PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38CF,
54 PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, PREFIX_EVEX_0F38DE,
55 PREFIX_EVEX_0F38DF, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A0F,
56 PREFIX_EVEX_0F3A44, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF,
57 EVEX_W_0F380C_P_2, EVEX_W_0F3818_P_2, EVEX_W_0F3858_P_2,
58 EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2, EVEX_W_0F3A04_P_2,
59 EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2): Delete.
60 (prefix_table): Add EXxEVexR to FMA table entries.
61 (OP_Rounding): Move abort() invocation.
62 * i386-dis-evex.h (evex_table): Reference VEX table for opcodes
63 0F60, 0F61, 0F63, 0F67, 0F68, 0F69, 0FD1, 0FD5, 0FD8, 0FD9,
64 0FDA, 0FDC, 0FDD, 0FDE, 0FE0, 0FE1, 0FE3, 0FE4, 0FE5, 0FE8,
65 0FE9, 0FEA, 0FEC, 0FED, 0FEE, 0FF1, 0FF5, 0FF6, 0FF8, 0FF9,
66 0FFC, 0FFD, 0F3800, 0F3804, 0F380B, 0F380C, 0F3818, 0F381C,
67 0F381D, 0F383C, 0F383E, 0F3858, 0F3878, 0F3879, 0F3896, 0F3897,
68 0F3898, 0F3899, 0F389C, 0F389D, 0F389E, 0F389F, 0F38A6, 0F38A7,
69 0F38A8, 0F38A9, 0F38AC, 0F38AD, 0F38AE, 0F38AF, 0F38B6, 0F38B7,
70 0F38B8, 0F38B9, 0F38BA, 0F38BB, 0F38BC, 0F38BD, 0F38BE, 0F38BF,
71 0F38CF, 0F38DC, 0F38DD, 0F38DE, 0F38DF, 0F3A04, 0F3A0F, 0F3A44,
73 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F60, PREFIX_EVEX_0F61,
74 PREFIX_EVEX_0F63, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
75 PREFIX_EVEX_0F69, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5,
76 PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA,
77 PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
78 PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3,
79 PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8,
80 PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC,
81 PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
82 PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8,
83 PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD,
84 PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B,
85 PREFIX_EVEX_0F380C, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F381C,
86 PREFIX_EVEX_0F381D, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E,
87 PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879,
88 PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898,
89 PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D,
90 PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A6,
91 PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9,
92 PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE,
93 PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7,
94 PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA,
95 PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD,
96 PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38CF,
97 PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, PREFIX_EVEX_0F38DE,
98 PREFIX_EVEX_0F38DF, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A0F,
99 PREFIX_EVEX_0F3A44, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF):
100 Delete table entries.
101 * i386-dis-evex-w.h (EVEX_W_0F380C_P_2, EVEX_W_0F3818_P_2,
102 EVEX_W_0F3858_P_2, EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2,
103 EVEX_W_0F3A04_P_2, EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2):
106 2020-07-06 Jan Beulich <jbeulich@suse.com>
108 * i386-dis.c (EXqScalarS): Delete.
109 (vex_len_table): Replace EXqScalarS by EXqVexScalarS.
110 * i386-dis-evex-w.h (vmovq): Use EXqVexScalarS.
112 2020-07-06 Jan Beulich <jbeulich@suse.com>
114 * i386-dis.c (safe-ctype.h): Include.
115 (EXdScalar, EXqScalar): Delete.
116 (d_scalar_mode, q_scalar_mode): Delete.
117 (prefix_table, vex_len_table): Use EXxmm_md in place of
118 EXdScalar and EXxmm_mq in place of EXqScalar.
119 (intel_operand_size, OP_E_memory, OP_EX): Remove uses of
120 d_scalar_mode and q_scalar_mode.
121 * i386-dis-evex-w.h (vmovss): Use EXxmm_md.
122 (vmovsd): Use EXxmm_mq.
124 2020-07-06 Yuri Chornoivan <yurchor@ukr.net>
127 * arc-dis.c: Fix spelling mistake.
128 * po/opcodes.pot: Regenerate.
130 2020-07-06 Nick Clifton <nickc@redhat.com>
132 * po/pt_BR.po: Updated Brazilian Portugugese translation.
133 * po/uk.po: Updated Ukranian translation.
135 2020-07-04 Nick Clifton <nickc@redhat.com>
137 * configure: Regenerate.
138 * po/opcodes.pot: Regenerate.
140 2020-07-04 Nick Clifton <nickc@redhat.com>
142 Binutils 2.35 branch created.
144 2020-07-02 H.J. Lu <hongjiu.lu@intel.com>
146 * i386-gen.c (opcode_modifiers): Add VexSwapSources.
147 * i386-opc.h (VexSwapSources): New.
148 (i386_opcode_modifier): Add vexswapsources.
149 * i386-opc.tbl: Add VexSwapSources to BMI2 and BMI instructions
150 with two source operands swapped.
151 * i386-tbl.h: Regenerated.
153 2020-06-30 Nelson Chu <nelson.chu@sifive.com>
155 * riscv-dis.c (print_insn_args, case 'E'): Updated. Let the
156 unprivileged CSR can also be initialized.
158 2020-06-29 Alan Modra <amodra@gmail.com>
160 * arm-dis.c: Use C style comments.
161 * cr16-opc.c: Likewise.
162 * ft32-dis.c: Likewise.
163 * moxie-opc.c: Likewise.
164 * tic54x-dis.c: Likewise.
165 * s12z-opc.c: Remove useless comment.
166 * xgate-dis.c: Likewise.
168 2020-06-26 H.J. Lu <hongjiu.lu@intel.com>
170 * i386-opc.tbl: Add a blank line.
172 2020-06-26 H.J. Lu <hongjiu.lu@intel.com>
174 * i386-gen.c (opcode_modifiers): Replace VecSIB with SIB.
175 (VecSIB128): Renamed to ...
177 (VecSIB256): Renamed to ...
179 (VecSIB512): Renamed to ...
181 (VecSIB): Renamed to ...
183 (i386_opcode_modifier): Replace vecsib with sib.
184 * i386-opc.tbl (VecSIB128): New.
185 (VecSIB256): Likewise.
186 (VecSIB512): Likewise.
187 Replace VecSIB=1, VecSIB=2 and VecSIB=3 with VecSIB128, VecSIB256
188 and VecSIB512, respectively.
190 2020-06-26 Jan Beulich <jbeulich@suse.com>
192 * i386-dis.c: Adjust description of I macro.
193 (x86_64_table): Drop use of I.
194 (float_mem): Replace use of I.
195 (putop): Remove handling of I. Adjust setting/clearing of "alt".
197 2020-06-26 Jan Beulich <jbeulich@suse.com>
199 * i386-dis.c: (print_insn): Avoid straight assignment to
200 priv.orig_sizeflag when processing -M sub-options.
202 2020-06-25 Jan Beulich <jbeulich@suse.com>
204 * i386-dis.c: Adjust description of J macro.
205 (dis386, x86_64_table, mod_table): Replace J.
206 (putop): Remove handling of J.
208 2020-06-25 Jan Beulich <jbeulich@suse.com>
210 * i386-dis.c: (float_mem): Reduce alternatives for fstpt and fldpt.
212 2020-06-25 Jan Beulich <jbeulich@suse.com>
214 * i386-dis.c: Adjust description of "LQ" macro.
215 (dis386_twobyte): Use LQ for sysret.
216 (putop): Adjust handling of LQ.
218 2020-06-22 Nelson Chu <nelson.chu@sifive.com>
220 * riscv-opc.c: Move the structures and functions to bfd/elfxx-riscv.c.
221 * riscv-dis.c: Include elfxx-riscv.h.
223 2020-06-18 H.J. Lu <hongjiu.lu@intel.com>
225 * i386-dis.c (prefix_table): Revert the last vmgexit change.
227 2020-06-17 Lili Cui <lili.cui@intel.com>
229 * i386-dis.c (prefix_table): Delete the incorrect vmgexit.
231 2020-06-14 H.J. Lu <hongjiu.lu@intel.com>
234 * i386-dis.c (prefix_table): Replace xsuspldtrk with xsusldtrk.
235 * i386-opc.tbl: Likewise.
236 * i386-tbl.h: Regenerated.
238 2020-06-12 Nelson Chu <nelson.chu@sifive.com>
240 * riscv-opc.c (priv_specs): Remove v1.9 and PRIV_SPEC_CLASS_1P9.
242 2020-06-11 Alex Coplan <alex.coplan@arm.com>
244 * aarch64-opc.c (SYSREG): New macro for describing system registers.
256 (SR_ID_PFR2): Likewise.
257 (SR_PROFILE): Likewise.
258 (SR_MEMTAG): Likewise.
259 (SR_SCXTNUM): Likewise.
260 (aarch64_sys_regs): Refactor to store feature information in the table.
261 (aarch64_sys_reg_supported_p): Collapse logic for system registers
262 that now describe their own features.
263 (aarch64_pstatefield_supported_p): Likewise.
265 2020-06-09 H.J. Lu <hongjiu.lu@intel.com>
267 * i386-dis.c (prefix_table): Fix a typo in comments.
269 2020-06-09 Jan Beulich <jbeulich@suse.com>
271 * i386-dis.c (rex_ignored): Delete.
272 (ckprefix): Drop rex_ignored initialization.
273 (get_valid_dis386): Drop setting of rex_ignored.
274 (print_insn): Drop checking of rex_ignored. Don't record data
275 size prefix as used with VEX-and-alike encodings.
277 2020-06-09 Jan Beulich <jbeulich@suse.com>
279 * i386-dis.c (MOD_0F12_PREFIX_2, MOD_0F16_PREFIX_2,
280 MOD_VEX_0F12_PREFIX_2, MOD_VEX_0F16_PREFIX_2): New enumerators.
281 (VEX_LEN_0F12_P_2, VEX_LEN_0F16_P_2): Delete.
282 (VEX_LEN_0F12_P_2_M_0, VEX_LEN_0F16_P_2_M_0): Define.
283 (prefix_table): Decode MOD for cases 2 of opcodes 0F12, 0F16,
284 VEX_0F12, and VEX_0F16.
285 (vex_len_table): Use X for vmovlp* and vmovh*s. Drop
286 VEX_LEN_0F12_P_2 and VEX_LEN_0F16_P_2 entries.
287 (mod_table): Use X for movlpX and movhpX. Drop PREFIX_OPCODE
288 from movlps and movhlps. New MOD_0F12_PREFIX_2,
289 MOD_0F16_PREFIX_2, MOD_VEX_0F12_PREFIX_2, and
290 MOD_VEX_0F16_PREFIX_2 entries.
292 2020-06-09 Jan Beulich <jbeulich@suse.com>
294 * i386-dis.c (MOD_EVEX_0F12_PREFIX_2, MOD_EVEX_0F13,
295 MOD_EVEX_0F16_PREFIX_2, MOD_EVEX_0F17, MOD_EVEX_0F2B): New enumerators.
296 (PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
297 PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29,
298 PREFIX_EVEX_0F2B, PREFIX_EVEX_0F54, PREFIX_EVEX_0F55,
299 PREFIX_EVEX_0F56, PREFIX_EVEX_0F57, PREFIX_EVEX_0FC6,
300 EVEX_W_0F10_P_0, EVEX_W_0F10_P_2, EVEX_W_0F11_P_0,
301 EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_2,
302 EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0,
303 EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2,
304 EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0,
305 EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2,
306 EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0,
307 EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2,
308 EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0,
309 EVEX_W_0F51_P_2, EVEX_W_0F54_P_0, EVEX_W_0F54_P_2,
310 EVEX_W_0F55_P_0, EVEX_W_0F55_P_2, EVEX_W_0F56_P_0,
311 EVEX_W_0F56_P_2, EVEX_W_0F57_P_0, EVEX_W_0F57_P_2,
312 EVEX_W_0F58_P_0, EVEX_W_0F58_P_2, EVEX_W_0F59_P_0,
313 EVEX_W_0F59_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2,
314 EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0,
315 EVEX_W_0F5E_P_2, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2,
316 EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0,
317 EVEX_W_0FC6_P_2): Delete.
318 (print_insn): Add EVEX.W vs embedded prefix consistency check
319 to prefix validation.
320 * i386-dis-evex.h (evex_table): Don't further descend for
321 vunpcklpX, vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX,
322 and vshufpX. Continue with MOD decoding for opcodes 0F13, 0F17,
324 * i386-dis-evex-mod.h: Add/adjust vmovlpX/vmovhpX entries.
325 * i386-dis-evex-prefix.h: Don't further descend for vmovupX,
326 vucomisX, vcomisX, vsqrtpX, vaddpX, vmulpX, vsubpX, vminpX,
327 vdivpX, vmaxpX, and vcmppX. Continue with MOD decoding for cases
328 2 of PREFIX_EVEX_0F12, PREFIX_EVEX_0F16, and PREFIX_EVEX_0F29.
329 Drop PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
330 PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F2B,
331 PREFIX_EVEX_0F54, PREFIX_EVEX_0F55, PREFIX_EVEX_0F56,
332 PREFIX_EVEX_0F57, and PREFIX_EVEX_0FC6 entries.
333 * i386-dis-evex-w.h: Drop EVEX_W_0F10_P_0, EVEX_W_0F10_P_2,
334 EVEX_W_0F11_P_0, EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0,
335 EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
336 EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2,
337 EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0,
338 EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
339 EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0,
340 EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
341 EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0,
342 EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_2,
343 EVEX_W_0F54_P_0, EVEX_W_0F54_P_2, EVEX_W_0F55_P_0,
344 EVEX_W_0F55_P_2, EVEX_W_0F56_P_0, EVEX_W_0F56_P_2,
345 EVEX_W_0F57_P_0, EVEX_W_0F57_P_2, EVEX_W_0F58_P_0,
346 EVEX_W_0F58_P_2, EVEX_W_0F59_P_0, EVEX_W_0F59_P_2,
347 EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2, EVEX_W_0F5D_P_0,
348 EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_2,
349 EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2, EVEX_W_0FC2_P_0,
350 EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0, and EVEX_W_0FC6_P_2 entries.
352 2020-06-09 Jan Beulich <jbeulich@suse.com>
354 * i386-dis.c (vex_table): Use PREFIX_OPCODE for vunpcklpX,
355 vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX and vshufpX.
356 (vex_len_table) : Likewise for vmovlpX, vmovhpX, vmovntpX, and
358 (print_insn): Drop pointless check against bad_opcode. Split
359 prefix validation into legacy and VEX-and-alike parts.
360 (putop): Re-work 'X' macro handling.
362 2020-06-09 Jan Beulich <jbeulich@suse.com>
364 * i386-dis.c (MOD_0F51): Rename to ...
365 (MOD_0F50): ... this.
367 2020-06-08 Alex Coplan <alex.coplan@arm.com>
369 * arm-dis.c (arm_opcodes): Add dfb.
370 (thumb32_opcodes): Add dfb.
372 2020-06-08 Jan Beulich <jbeulich@suse.com>
374 * i386-opc.h (reg_entry): Const-qualify reg_name field.
376 2020-06-06 Alan Modra <amodra@gmail.com>
378 * ppc-dis.c (ppc_opts): Accept -mpwr10/-Mpwr10.
380 2020-06-05 Alan Modra <amodra@gmail.com>
382 * cgen-dis.c (hash_insn_array): Increase size of buf. Assert
383 size is large enough.
385 2020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com>
387 * disassemble.c (disassemble_init_for_target): Set endian_code for
389 * bpf-desc.c: Regenerate.
390 * bpf-opc.c: Likewise.
391 * bpf-dis.c: Likewise.
393 2020-06-03 Jose E. Marchesi <jose.marchesi@oracle.com>
395 * cgen-opc.c (cgen_get_insn_value): Get an `endian' argument.
396 (cgen_put_insn_value): Likewise.
397 (cgen_lookup_insn): Pass endianness to cgen_{get,put}_insn_value.
398 * cgen-dis.in (print_insn): Likewise.
399 * cgen-ibld.in (insert_1): Likewise.
400 (insert_1): Likewise.
401 (insert_insn_normal): Likewise.
402 (extract_1): Likewise.
403 * bpf-dis.c: Regenerate.
404 * bpf-ibld.c: Likewise.
405 * bpf-ibld.c: Likewise.
406 * cgen-dis.in: Likewise.
407 * cgen-ibld.in: Likewise.
408 * cgen-opc.c: Likewise.
409 * epiphany-dis.c: Likewise.
410 * epiphany-ibld.c: Likewise.
411 * fr30-dis.c: Likewise.
412 * fr30-ibld.c: Likewise.
413 * frv-dis.c: Likewise.
414 * frv-ibld.c: Likewise.
415 * ip2k-dis.c: Likewise.
416 * ip2k-ibld.c: Likewise.
417 * iq2000-dis.c: Likewise.
418 * iq2000-ibld.c: Likewise.
419 * lm32-dis.c: Likewise.
420 * lm32-ibld.c: Likewise.
421 * m32c-dis.c: Likewise.
422 * m32c-ibld.c: Likewise.
423 * m32r-dis.c: Likewise.
424 * m32r-ibld.c: Likewise.
425 * mep-dis.c: Likewise.
426 * mep-ibld.c: Likewise.
427 * mt-dis.c: Likewise.
428 * mt-ibld.c: Likewise.
429 * or1k-dis.c: Likewise.
430 * or1k-ibld.c: Likewise.
431 * xc16x-dis.c: Likewise.
432 * xc16x-ibld.c: Likewise.
433 * xstormy16-dis.c: Likewise.
434 * xstormy16-ibld.c: Likewise.
436 2020-06-04 Jose E. Marchesi <jemarch@gnu.org>
438 * cgen-dis.in (cpu_desc_list): New field `insn_endian'.
439 (print_insn_): Handle instruction endian.
440 * bpf-dis.c: Regenerate.
441 * bpf-desc.c: Regenerate.
442 * epiphany-dis.c: Likewise.
443 * epiphany-desc.c: Likewise.
444 * fr30-dis.c: Likewise.
445 * fr30-desc.c: Likewise.
446 * frv-dis.c: Likewise.
447 * frv-desc.c: Likewise.
448 * ip2k-dis.c: Likewise.
449 * ip2k-desc.c: Likewise.
450 * iq2000-dis.c: Likewise.
451 * iq2000-desc.c: Likewise.
452 * lm32-dis.c: Likewise.
453 * lm32-desc.c: Likewise.
454 * m32c-dis.c: Likewise.
455 * m32c-desc.c: Likewise.
456 * m32r-dis.c: Likewise.
457 * m32r-desc.c: Likewise.
458 * mep-dis.c: Likewise.
459 * mep-desc.c: Likewise.
460 * mt-dis.c: Likewise.
461 * mt-desc.c: Likewise.
462 * or1k-dis.c: Likewise.
463 * or1k-desc.c: Likewise.
464 * xc16x-dis.c: Likewise.
465 * xc16x-desc.c: Likewise.
466 * xstormy16-dis.c: Likewise.
467 * xstormy16-desc.c: Likewise.
469 2020-06-03 Nick Clifton <nickc@redhat.com>
471 * po/sr.po: Updated Serbian translation.
473 2020-06-03 Nelson Chu <nelson.chu@sifive.com>
475 * riscv-opc.c (riscv_get_isa_spec_class): Change bfd_boolean to int.
476 (riscv_get_priv_spec_class): Likewise.
478 2020-06-01 Alan Modra <amodra@gmail.com>
480 * bpf-desc.c: Regenerate.
482 2020-05-28 Jose E. Marchesi <jose.marchesi@oracle.com>
483 David Faust <david.faust@oracle.com>
485 * bpf-desc.c: Regenerate.
486 * bpf-opc.h: Likewise.
487 * bpf-opc.c: Likewise.
488 * bpf-dis.c: Likewise.
490 2020-05-28 Alan Modra <amodra@gmail.com>
492 * nios2-dis.c (nios2_print_insn_arg): Avoid shift left of negative
495 2020-05-28 Alan Modra <amodra@gmail.com>
497 * ns32k-dis.c (print_insn_arg): Handle d value of 'f' for
499 (print_insn_ns32k): Revert last change.
501 2020-05-28 Nick Clifton <nickc@redhat.com>
503 * ns32k-dis.c (print_insn_ns32k): Change the arg_bufs array to
506 2020-05-26 Sandra Loosemore <sandra@codesourcery.com>
508 Fix extraction of signed constants in nios2 disassembler (again).
510 * nios2-dis.c (nios2_print_insn_arg): Add explicit casts to
511 extractions of signed fields.
513 2020-05-26 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
515 * s390-opc.txt: Relocate vector load/store instructions with
516 additional alignment parameter and change architecture level
517 constraint from z14 to z13.
519 2020-05-21 Alan Modra <amodra@gmail.com>
521 * arc-ext.c: Replace "if (x) free (x)" with "free (x)" throughout.
522 * sparc-dis.c: Likewise.
523 * tic4x-dis.c: Likewise.
524 * xtensa-dis.c: Likewise.
525 * bpf-desc.c: Regenerate.
526 * epiphany-desc.c: Regenerate.
527 * fr30-desc.c: Regenerate.
528 * frv-desc.c: Regenerate.
529 * ip2k-desc.c: Regenerate.
530 * iq2000-desc.c: Regenerate.
531 * lm32-desc.c: Regenerate.
532 * m32c-desc.c: Regenerate.
533 * m32r-desc.c: Regenerate.
534 * mep-asm.c: Regenerate.
535 * mep-desc.c: Regenerate.
536 * mt-desc.c: Regenerate.
537 * or1k-desc.c: Regenerate.
538 * xc16x-desc.c: Regenerate.
539 * xstormy16-desc.c: Regenerate.
541 2020-05-20 Nelson Chu <nelson.chu@sifive.com>
543 * riscv-opc.c (riscv_ext_version_table): The table used to store
544 all information about the supported spec and the corresponding ISA
545 versions. Currently, only Zicsr is supported to verify the
546 correctness of Z sub extension settings. Others will be supported
547 in the future patches.
548 (struct isa_spec_t, isa_specs): List for all supported ISA spec
549 classes and the corresponding strings.
550 (riscv_get_isa_spec_class): New function. Get the corresponding ISA
551 spec class by giving a ISA spec string.
552 * riscv-opc.c (struct priv_spec_t): New structure.
553 (struct priv_spec_t priv_specs): List for all supported privilege spec
554 classes and the corresponding strings.
555 (riscv_get_priv_spec_class): New function. Get the corresponding
556 privilege spec class by giving a spec string.
557 (riscv_get_priv_spec_name): New function. Get the corresponding
558 privilege spec string by giving a CSR version class.
559 * riscv-dis.c: Updated since DECLARE_CSR is changed.
560 * riscv-dis.c: Add new disassembler option -Mpriv-spec to dump the CSR
561 according to the chosen version. Build a hash table riscv_csr_hash to
562 store the valid CSR for the chosen pirv verison. Dump the direct
563 CSR address rather than it's name if it is invalid.
564 (parse_riscv_dis_option_without_args): New function. Parse the options
566 (parse_riscv_dis_option): Call parse_riscv_dis_option_without_args to
567 parse the options without arguments first, and then handle the options
568 with arguments. Add the new option -Mpriv-spec, which has argument.
569 * riscv-dis.c (print_riscv_disassembler_options): Add description
570 about the new OBJDUMP option.
572 2020-05-19 Peter Bergner <bergner@linux.ibm.com>
574 * ppc-opc.c (insert_ls, extract_ls): Handle 3-bit L fields and new
575 WC values on POWER10 sync, dcbf and wait instructions.
576 (insert_pl, extract_pl): New functions.
577 (L2OPT, LS, WC): Use insert_ls and extract_ls.
578 (LS3): New , 3-bit L for sync.
579 (LS3, L3OPT): New, 3-bit L for sync and dcbf.
580 (SC2, PL): New, 2-bit SC and PL for sync and wait.
581 (XWCPL_MASK, XL3RT_MASK, XSYNCLS_MASK): New instruction masks.
582 (XOPL3, XWCPL, XSYNCLS): New opcode macros.
583 (powerpc_opcodes) <dcbflp, dcbfps, dcbstps pause_short, phwsync,
584 plwsync, stcisync, stncisync, stsync, waitrsv>: New extended mnemonics.
585 <wait>: Enable PL operand on POWER10.
586 <dcbf>: Enable L3OPT operand on POWER10.
587 <sync>: Enable SC2 operand on POWER10.
589 2020-05-19 Stafford Horne <shorne@gmail.com>
592 * or1k-asm.c: Regenerate.
593 * or1k-desc.c: Regenerate.
594 * or1k-desc.h: Regenerate.
595 * or1k-dis.c: Regenerate.
596 * or1k-ibld.c: Regenerate.
597 * or1k-opc.c: Regenerate.
598 * or1k-opc.h: Regenerate.
599 * or1k-opinst.c: Regenerate.
601 2020-05-11 Alan Modra <amodra@gmail.com>
603 * ppc-opc (powerpc_opcodes): Add xscmpeqqp, xscmpgeqp, xscmpgtqp,
606 2020-05-11 Alan Modra <amodra@gmail.com>
608 * ppc-opc.c (powerpc_opcodes): Add lxvrbx, lxvrhx, lxvrwx, lxvrdx,
609 stxvrbx, stxvrhx, stxvrwx, stxvrdx.
611 2020-05-11 Alan Modra <amodra@gmail.com>
613 * ppc-opc.c (powerpc_opcodes): Add xvtlsbb.
615 2020-05-11 Alan Modra <amodra@gmail.com>
617 * ppc-opc.c (powerpc_opcodes): Add vstribl, vstribr, vstrihl, vstrihr,
618 vclrlb, vclrrb, vstribl., vstribr., vstrihl., vstrihr..
620 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
622 * ppc-opc.c (powerpc_opcodes) <setbc, setbcr, setnbc, setnbcr>: New
625 2020-05-11 Alan Modra <amodra@gmail.com>
627 * ppc-opc.c (UIM8, P_U8XX4_MASK): Define.
628 (powerpc_opcodes): Add vgnb, vcfuged, vpextd, vpdepd, vclzdm,
629 vctzdm, cntlzdm, pdepd, pextd, cfuged, cnttzdm.
630 (prefix_opcodes): Add xxeval.
632 2020-05-11 Alan Modra <amodra@gmail.com>
634 * ppc-opc.c (powerpc_opcodes): Add xxgenpcvbm, xxgenpcvhm,
635 xxgenpcvwm, xxgenpcvdm.
637 2020-05-11 Alan Modra <amodra@gmail.com>
639 * ppc-opc.c (MP, VXVAM_MASK): Define.
640 (VXVAPS_MASK): Use VXVA_MASK.
641 (powerpc_opcodes): Add mtvsrbmi, vexpandbm, vexpandhm, vexpandwm,
642 vexpanddm, vexpandqm, vextractbm, vextracthm, vextractwm,
643 vextractdm, vextractqm, mtvsrbm, mtvsrhm, mtvsrwm, mtvsrdm, mtvsrqm,
644 vcntmbb, vcntmbh, vcntmbw, vcntmbd.
646 2020-05-11 Alan Modra <amodra@gmail.com>
647 Peter Bergner <bergner@linux.ibm.com>
649 * ppc-opc.c (insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a):
651 (powerpc_operands): Define ACC, PMSK8, PMSK4, PMSK2, XMSK, YMSK,
652 YMSK2, XA6a, XA6ap, XB6a entries.
653 (PMMIRR, P_X_MASK, P_XX1_MASK, P_GER_MASK): Define
654 (P_GER2_MASK, P_GER4_MASK, P_GER8_MASK, P_GER64_MASK): Define.
656 (powerpc_opcodes): Add xxmfacc, xxmtacc, xxsetaccz,
657 xvi8ger4pp, xvi8ger4, xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger,
658 xvi4ger8pp, xvi4ger8, xvi16ger2spp, xvi16ger2s, xvbf16ger2pp,
659 xvbf16ger2, xvf64gerpp, xvf64ger, xvi16ger2, xvf16ger2np,
660 xvf32gernp, xvi8ger4spp, xvi16ger2pp, xvbf16ger2np, xvf64gernp,
661 xvf16ger2pn, xvf32gerpn, xvbf16ger2pn, xvf64gerpn, xvf16ger2nn,
662 xvf32gernn, xvbf16ger2nn, xvf64gernn, xvcvbf16sp, xvcvspbf16.
663 (prefix_opcodes): Add pmxvi8ger4pp, pmxvi8ger4, pmxvf16ger2pp,
664 pmxvf16ger2, pmxvf32gerpp, pmxvf32ger, pmxvi4ger8pp, pmxvi4ger8,
665 pmxvi16ger2spp, pmxvi16ger2s, pmxvbf16ger2pp, pmxvbf16ger2,
666 pmxvf64gerpp, pmxvf64ger, pmxvi16ger2, pmxvf16ger2np, pmxvf32gernp,
667 pmxvi8ger4spp, pmxvi16ger2pp, pmxvbf16ger2np, pmxvf64gernp,
668 pmxvf16ger2pn, pmxvf32gerpn, pmxvbf16ger2pn, pmxvf64gerpn,
669 pmxvf16ger2nn, pmxvf32gernn, pmxvbf16ger2nn, pmxvf64gernn.
671 2020-05-11 Alan Modra <amodra@gmail.com>
673 * ppc-opc.c (insert_imm32, extract_imm32): New functions.
674 (insert_xts, extract_xts): New functions.
675 (IMM32, UIM3, IX, UIM5, SH3, XTS, P8RR): Define.
676 (P_XX4_MASK, P_UXX4_MASK, VSOP, P_VS_MASK, P_VSI_MASK): Define.
677 (VXRC_MASK, VXSH_MASK): Define.
678 (powerpc_opcodes): Add vinsbvlx, vsldbi, vextdubvlx, vextdubvrx,
679 vextduhvlx, vextduhvrx, vextduwvlx, vextduwvrx, vextddvlx,
680 vextddvrx, vinshvlx, vinswvlx, vinsw, vinsbvrx, vinshvrx,
681 vinswvrx, vinsd, vinsblx, vsrdbi, vinshlx, vinswlx, vinsdlx,
682 vinsbrx, vinshrx, vinswrx, vinsdrx, lxvkq.
683 (prefix_opcodes): Add xxsplti32dx, xxspltidp, xxspltiw, xxblendvb,
684 xxblendvh, xxblendvw, xxblendvd, xxpermx.
686 2020-05-11 Alan Modra <amodra@gmail.com>
688 * ppc-opc.c (powerpc_opcodes): Add vrlq, vdivuq, vmsumcud, vrlqmi,
689 vmuloud, vcmpuq, vslq, vdivsq, vcmpsq, vrlqnm, vcmpequq, vmulosd,
690 vsrq, vdiveuq, vcmpgtuq, vmuleud, vsraq, vdivesq, vcmpgtsq, vmulesd,
691 vcmpequq., vextsd2q, vmoduq, vcmpgtuq., vmodsq, vcmpgtsq., xscvqpuqz,
692 xscvuqqp, xscvqpsqz, xscvsqqp, dcffixqq, dctfixqq.
694 2020-05-11 Alan Modra <amodra@gmail.com>
696 * ppc-opc.c (insert_xtp, extract_xtp): New functions.
697 (XTP, DQXP, DQXP_MASK): Define.
698 (powerpc_opcodes): Add lxvp, stxvp, lxvpx, stxvpx.
699 (prefix_opcodes): Add plxvp and pstxvp.
701 2020-05-11 Alan Modra <amodra@gmail.com>
703 * ppc-opc.c (powerpc_opcodes): Add vdivuw, vdivud, vdivsw, vmulld,
704 vdivsd, vmulhuw, vdiveuw, vmulhud, vdiveud, vmulhsw, vdivesw,
705 vmulhsd, vdivesd, vmoduw, vmodud, vmodsw, vmodsd.
707 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
709 * ppc-opc.c (powerpc_opcodes) <brd, brh, brw>: New mnemonics.
711 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
713 * ppc-opc.c (insert_l1opt, extract_l1opt): New functions.
715 (powerpc_opcodes) <paste.>: Add L operand for cpu POWER10.
717 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
719 * ppc-opc.c (powerpc_opcodes) <slbiag>: Add variant with L operand.
721 2020-05-11 Alan Modra <amodra@gmail.com>
723 * ppc-dis.c (powerpc_init_dialect): Default to "power10".
725 2020-05-11 Alan Modra <amodra@gmail.com>
727 * ppc-dis.c (ppc_opts): Add "power10" entry.
728 (print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming.
729 * ppc-opc.c (POWER10): Rename from POWERXX. Update all uses.
731 2020-05-11 Nick Clifton <nickc@redhat.com>
733 * po/fr.po: Updated French translation.
735 2020-04-30 Alex Coplan <alex.coplan@arm.com>
737 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
738 * aarch64-opc.c (fields): Add entry for FLD_imm16_2.
739 (operand_general_constraint_met_p): validate
740 AARCH64_OPND_UNDEFINED.
741 * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry
743 * aarch64-asm-2.c: Regenerated.
744 * aarch64-dis-2.c: Regenerated.
745 * aarch64-opc-2.c: Regenerated.
747 2020-04-29 Nick Clifton <nickc@redhat.com>
750 * sh-opc.h: Also use unsigned 8-bit immediate values for the LDRC
753 2020-04-29 Nick Clifton <nickc@redhat.com>
755 * po/sv.po: Updated Swedish translation.
757 2020-04-29 Nick Clifton <nickc@redhat.com>
760 * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U. Use
761 IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
762 * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
765 2020-04-21 Andreas Schwab <schwab@linux-m68k.org>
768 * m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
769 cmpi only on m68020up and cpu32.
771 2020-04-20 Sudakshina Das <sudi.das@arm.com>
773 * aarch64-asm.c (aarch64_ins_none): New.
774 * aarch64-asm.h (ins_none): New declaration.
775 * aarch64-dis.c (aarch64_ext_none): New.
776 * aarch64-dis.h (ext_none): New declaration.
777 * aarch64-opc.c (aarch64_print_operand): Update case for
778 AARCH64_OPND_BARRIER_PSB.
779 * aarch64-tbl.h (aarch64_opcode_table): Add tsb.
780 (AARCH64_OPERANDS): Update inserter/extracter for
781 AARCH64_OPND_BARRIER_PSB to use new dummy functions.
782 * aarch64-asm-2.c: Regenerated.
783 * aarch64-dis-2.c: Regenerated.
784 * aarch64-opc-2.c: Regenerated.
786 2020-04-20 Sudakshina Das <sudi.das@arm.com>
788 * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
789 (aarch64_feature_ras, RAS): Likewise.
790 (aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
791 (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
792 autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
793 autiaz, autiasp, autibz, autibsp to be CORE_INSN.
794 * aarch64-asm-2.c: Regenerated.
795 * aarch64-dis-2.c: Regenerated.
796 * aarch64-opc-2.c: Regenerated.
798 2020-04-17 Fredrik Strupe <fredrik@strupe.net>
800 * arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
801 (print_insn_neon): Support disassembly of conditional
804 2020-02-16 David Faust <david.faust@oracle.com>
806 * bpf-desc.c: Regenerate.
807 * bpf-desc.h: Likewise.
808 * bpf-opc.c: Regenerate.
809 * bpf-opc.h: Likewise.
811 2020-04-07 Lili Cui <lili.cui@intel.com>
813 * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
814 (prefix_table): New instructions (see prefixes above).
816 * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
817 CPU_ANY_TSXLDTRK_FLAGS.
818 (cpu_flags): Add CpuTSXLDTRK.
819 * i386-opc.h (enum): Add CpuTSXLDTRK.
820 (i386_cpu_flags): Add cputsxldtrk.
821 * i386-opc.tbl: Add XSUSPLDTRK insns.
822 * i386-init.h: Regenerate.
823 * i386-tbl.h: Likewise.
825 2020-04-02 Lili Cui <lili.cui@intel.com>
827 * i386-dis.c (prefix_table): New instructions serialize.
828 * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
829 CPU_ANY_SERIALIZE_FLAGS.
830 (cpu_flags): Add CpuSERIALIZE.
831 * i386-opc.h (enum): Add CpuSERIALIZE.
832 (i386_cpu_flags): Add cpuserialize.
833 * i386-opc.tbl: Add SERIALIZE insns.
834 * i386-init.h: Regenerate.
835 * i386-tbl.h: Likewise.
837 2020-03-26 Alan Modra <amodra@gmail.com>
839 * disassemble.h (opcodes_assert): Declare.
840 (OPCODES_ASSERT): Define.
841 * disassemble.c: Don't include assert.h. Include opintl.h.
842 (opcodes_assert): New function.
843 * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
844 (bfd_h8_disassemble): Reduce size of data array. Correctly
845 calculate maxlen. Omit insn decoding when insn length exceeds
846 maxlen. Exit from nibble loop when looking for E, before
847 accessing next data byte. Move processing of E outside loop.
848 Replace tests of maxlen in loop with assertions.
850 2020-03-26 Alan Modra <amodra@gmail.com>
852 * arc-dis.c (find_format): Init needs_limm. Simplify use of limm.
854 2020-03-25 Alan Modra <amodra@gmail.com>
856 * z80-dis.c (suffix): Init mybuf.
858 2020-03-22 Alan Modra <amodra@gmail.com>
860 * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
861 successflly read from section.
863 2020-03-22 Alan Modra <amodra@gmail.com>
865 * arc-dis.c (find_format): Use ISO C string concatenation rather
866 than line continuation within a string. Don't access needs_limm
867 before testing opcode != NULL.
869 2020-03-22 Alan Modra <amodra@gmail.com>
871 * ns32k-dis.c (print_insn_arg): Update comment.
872 (print_insn_ns32k): Reduce size of index_offset array, and
873 initialize, passing -1 to print_insn_arg for args that are not
874 an index. Don't exit arg loop early. Abort on bad arg number.
876 2020-03-22 Alan Modra <amodra@gmail.com>
878 * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
879 * s12z-opc.c: Formatting.
880 (operands_f): Return an int.
881 (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
882 (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
883 (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
884 (exg_sex_discrim): Likewise.
885 (create_immediate_operand, create_bitfield_operand),
886 (create_register_operand_with_size, create_register_all_operand),
887 (create_register_all16_operand, create_simple_memory_operand),
888 (create_memory_operand, create_memory_auto_operand): Don't
889 segfault on malloc failure.
890 (z_ext24_decode): Return an int status, negative on fail, zero
892 (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
893 (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
894 (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
895 (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
896 (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
897 (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
898 (loop_primitive_decode, shift_decode, psh_pul_decode),
899 (bit_field_decode): Similarly.
900 (z_decode_signed_value, decode_signed_value): Similarly. Add arg
901 to return value, update callers.
902 (x_opr_decode_with_size): Check all reads, returning NULL on fail.
903 Don't segfault on NULL operand.
904 (decode_operation): Return OP_INVALID on first fail.
905 (decode_s12z): Check all reads, returning -1 on fail.
907 2020-03-20 Alan Modra <amodra@gmail.com>
909 * metag-dis.c (print_insn_metag): Don't ignore status from
912 2020-03-20 Alan Modra <amodra@gmail.com>
914 * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
915 Initialize parts of buffer not written when handling a possible
916 2-byte insn at end of section. Don't attempt decoding of such
917 an insn by the 4-byte machinery.
919 2020-03-20 Alan Modra <amodra@gmail.com>
921 * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
922 partially filled buffer. Prevent lookup of 4-byte insns when
923 only VLE 2-byte insns are possible due to section size. Print
924 ".word" rather than ".long" for 2-byte leftovers.
926 2020-03-17 Sergey Belyashov <sergey.belyashov@gmail.com>
929 * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
931 2020-03-13 Jan Beulich <jbeulich@suse.com>
933 * i386-dis.c (X86_64_0D): Rename to ...
934 (X86_64_0E): ... this.
936 2020-03-09 H.J. Lu <hongjiu.lu@intel.com>
938 * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
939 * Makefile.in: Regenerated.
941 2020-03-09 Jan Beulich <jbeulich@suse.com>
943 * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
945 * i386-tbl.h: Re-generate.
947 2020-03-09 Jan Beulich <jbeulich@suse.com>
949 * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
950 vprot*, vpsha*, and vpshl*.
951 * i386-tbl.h: Re-generate.
953 2020-03-09 Jan Beulich <jbeulich@suse.com>
955 * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
956 vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
957 * i386-tbl.h: Re-generate.
959 2020-03-09 Jan Beulich <jbeulich@suse.com>
961 * i386-gen.c (set_bitfield): Ignore zero-length field names.
962 * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
963 cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
964 * i386-tbl.h: Re-generate.
966 2020-03-09 Jan Beulich <jbeulich@suse.com>
968 * i386-gen.c (struct template_arg, struct template_instance,
969 struct template_param, struct template, templates,
970 parse_template, expand_templates): New.
971 (process_i386_opcodes): Various local variables moved to
972 expand_templates. Call parse_template and expand_templates.
973 * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
974 * i386-tbl.h: Re-generate.
976 2020-03-06 Jan Beulich <jbeulich@suse.com>
978 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
979 vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
980 register and memory source templates. Replace VexW= by VexW*
982 * i386-tbl.h: Re-generate.
984 2020-03-06 Jan Beulich <jbeulich@suse.com>
986 * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
987 VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
988 * i386-tbl.h: Re-generate.
990 2020-03-06 Jan Beulich <jbeulich@suse.com>
992 * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
993 * i386-tbl.h: Re-generate.
995 2020-03-06 Jan Beulich <jbeulich@suse.com>
997 * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
998 (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
999 pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
1000 VexW0 on SSE2AVX variants.
1001 (vmovq): Drop NoRex64 from XMM/XMM variants.
1002 (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
1003 vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
1004 applicable use VexW0.
1005 * i386-tbl.h: Re-generate.
1007 2020-03-06 Jan Beulich <jbeulich@suse.com>
1009 * i386-gen.c (opcode_modifiers): Remove Rex64 field.
1010 * i386-opc.h (Rex64): Delete.
1011 (struct i386_opcode_modifier): Remove rex64 field.
1012 * i386-opc.tbl (crc32): Drop Rex64.
1013 Replace Rex64 with Size64 everywhere else.
1014 * i386-tbl.h: Re-generate.
1016 2020-03-06 Jan Beulich <jbeulich@suse.com>
1018 * i386-dis.c (OP_E_memory): Exclude recording of used address
1019 prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
1020 addressed memory operands for MPX insns.
1022 2020-03-06 Jan Beulich <jbeulich@suse.com>
1024 * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
1025 invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
1026 adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
1027 (ptwrite): Split into non-64-bit and 64-bit forms.
1028 * i386-tbl.h: Re-generate.
1030 2020-03-06 Jan Beulich <jbeulich@suse.com>
1032 * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
1034 * i386-tbl.h: Re-generate.
1036 2020-03-04 Jan Beulich <jbeulich@suse.com>
1038 * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
1039 (prefix_table): Move vmmcall here. Add vmgexit.
1040 (rm_table): Replace vmmcall entry by prefix_table[] escape.
1041 * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
1042 (cpu_flags): Add CpuSEV_ES entry.
1043 * i386-opc.h (CpuSEV_ES): New.
1044 (union i386_cpu_flags): Add cpusev_es field.
1045 * i386-opc.tbl (vmgexit): New.
1046 * i386-init.h, i386-tbl.h: Re-generate.
1048 2020-03-03 H.J. Lu <hongjiu.lu@intel.com>
1050 * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
1052 * i386-opc.h (IGNORESIZE): New.
1053 (DEFAULTSIZE): Likewise.
1054 (IgnoreSize): Removed.
1055 (DefaultSize): Likewise.
1056 (MnemonicSize): New.
1057 (i386_opcode_modifier): Replace ignoresize/defaultsize with
1059 * i386-opc.tbl (IgnoreSize): New.
1060 (DefaultSize): Likewise.
1061 * i386-tbl.h: Regenerated.
1063 2020-03-03 Sergey Belyashov <sergey.belyashov@gmail.com>
1066 * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
1069 2020-03-03 H.J. Lu <hongjiu.lu@intel.com>
1072 * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
1073 vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
1074 * i386-tbl.h: Regenerated.
1076 2020-02-26 Alan Modra <amodra@gmail.com>
1078 * aarch64-asm.c: Indent labels correctly.
1079 * aarch64-dis.c: Likewise.
1080 * aarch64-gen.c: Likewise.
1081 * aarch64-opc.c: Likewise.
1082 * alpha-dis.c: Likewise.
1083 * i386-dis.c: Likewise.
1084 * nds32-asm.c: Likewise.
1085 * nfp-dis.c: Likewise.
1086 * visium-dis.c: Likewise.
1088 2020-02-25 Claudiu Zissulescu <claziss@gmail.com>
1090 * arc-regs.h (int_vector_base): Make it available for all ARC
1093 2020-02-20 Nelson Chu <nelson.chu@sifive.com>
1095 * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
1098 2020-02-19 Nelson Chu <nelson.chu@sifive.com>
1100 * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
1101 c.mv/c.li if rs1 is zero.
1103 2020-02-17 H.J. Lu <hongjiu.lu@intel.com>
1105 * i386-gen.c (cpu_flag_init): Replace CpuABM with
1106 CpuLZCNT|CpuPOPCNT. Add CpuPOPCNT to CPU_SSE4_2_FLAGS. Add
1108 (cpu_flags): Remove CpuABM. Add CpuPOPCNT.
1109 * i386-opc.h (CpuABM): Removed.
1111 (i386_cpu_flags): Remove cpuabm. Add cpupopcnt.
1112 * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
1113 popcnt. Remove CpuABM from lzcnt.
1114 * i386-init.h: Regenerated.
1115 * i386-tbl.h: Likewise.
1117 2020-02-17 Jan Beulich <jbeulich@suse.com>
1119 * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
1120 Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
1121 VexW1 instead of open-coding them.
1122 * i386-tbl.h: Re-generate.
1124 2020-02-17 Jan Beulich <jbeulich@suse.com>
1126 * i386-opc.tbl (AddrPrefixOpReg): Define.
1127 (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
1128 umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
1129 templates. Drop NoRex64.
1130 * i386-tbl.h: Re-generate.
1132 2020-02-17 Jan Beulich <jbeulich@suse.com>
1135 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
1136 vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
1137 into Intel syntax instance (with Unpsecified) and AT&T one
1139 (vcvtneps2bf16): Likewise, along with folding the two so far
1141 * i386-tbl.h: Re-generate.
1143 2020-02-16 H.J. Lu <hongjiu.lu@intel.com>
1145 * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
1146 CPU_ANY_SSE4A_FLAGS.
1148 2020-02-17 Alan Modra <amodra@gmail.com>
1150 * i386-gen.c (cpu_flag_init): Correct last change.
1152 2020-02-16 H.J. Lu <hongjiu.lu@intel.com>
1154 * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS. Remove
1157 2020-02-14 H.J. Lu <hongjiu.lu@intel.com>
1159 * i386-opc.tbl (movsx): Remove Intel syntax comments.
1162 2020-02-14 Jan Beulich <jbeulich@suse.com>
1165 * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
1166 destination for Cpu64-only variant.
1167 (movzx): Fold patterns.
1168 * i386-tbl.h: Re-generate.
1170 2020-02-13 Jan Beulich <jbeulich@suse.com>
1172 * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
1173 CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
1174 CPU_ANY_SSE4_FLAGS entry.
1175 * i386-init.h: Re-generate.
1177 2020-02-12 Jan Beulich <jbeulich@suse.com>
1179 * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
1180 with Unspecified, making the present one AT&T syntax only.
1181 * i386-tbl.h: Re-generate.
1183 2020-02-12 Jan Beulich <jbeulich@suse.com>
1185 * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
1186 * i386-tbl.h: Re-generate.
1188 2020-02-12 Jan Beulich <jbeulich@suse.com>
1191 * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
1192 * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
1193 Amd64 and Intel64 templates.
1194 (call, jmp): Likewise for far indirect variants. Dro
1196 * i386-tbl.h: Re-generate.
1198 2020-02-11 Jan Beulich <jbeulich@suse.com>
1200 * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
1201 * i386-opc.h (ShortForm): Delete.
1202 (struct i386_opcode_modifier): Remove shortform field.
1203 * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
1204 fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
1205 fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
1206 ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
1208 * i386-tbl.h: Re-generate.
1210 2020-02-11 Jan Beulich <jbeulich@suse.com>
1212 * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
1213 fucompi): Drop ShortForm from operand-less templates.
1214 * i386-tbl.h: Re-generate.
1216 2020-02-11 Alan Modra <amodra@gmail.com>
1218 * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
1219 * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
1220 * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
1221 * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
1222 * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
1224 2020-02-10 Matthew Malcomson <matthew.malcomson@arm.com>
1226 * arm-dis.c (print_insn_cde): Define 'V' parse character.
1227 (cde_opcodes): Add VCX* instructions.
1229 2020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
1230 Matthew Malcomson <matthew.malcomson@arm.com>
1232 * arm-dis.c (struct cdeopcode32): New.
1233 (CDE_OPCODE): New macro.
1234 (cde_opcodes): New disassembly table.
1235 (regnames): New option to table.
1236 (cde_coprocs): New global variable.
1237 (print_insn_cde): New
1238 (print_insn_thumb32): Use print_insn_cde.
1239 (parse_arm_disassembler_options): Parse coprocN args.
1241 2020-02-10 H.J. Lu <hongjiu.lu@intel.com>
1244 * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
1246 * i386-opc.h (AMD64): Removed.
1247 (Intel64): Likewose.
1249 (INTEL64): Likewise.
1250 (INTEL64ONLY): Likewise.
1251 (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
1252 * i386-opc.tbl (Amd64): New.
1253 (Intel64): Likewise.
1254 (Intel64Only): Likewise.
1255 Replace AMD64 with Amd64. Update sysenter/sysenter with
1256 Cpu64 and Intel64Only. Remove AMD64 from sysenter/sysenter.
1257 * i386-tbl.h: Regenerated.
1259 2020-02-07 Sergey Belyashov <sergey.belyashov@gmail.com>
1262 * z80-dis.c: Add support for GBZ80 opcodes.
1264 2020-02-04 Alan Modra <amodra@gmail.com>
1266 * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
1268 2020-02-03 Alan Modra <amodra@gmail.com>
1270 * m32c-ibld.c: Regenerate.
1272 2020-02-01 Alan Modra <amodra@gmail.com>
1274 * frv-ibld.c: Regenerate.
1276 2020-01-31 Jan Beulich <jbeulich@suse.com>
1278 * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
1279 (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
1280 (OP_E_memory): Replace xmm_mdq_mode case label by
1281 vex_scalar_w_dq_mode one.
1282 * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
1284 2020-01-31 Jan Beulich <jbeulich@suse.com>
1286 * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
1287 (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
1288 vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
1289 (intel_operand_size): Drop vex_w_dq_mode case label.
1291 2020-01-31 Richard Sandiford <richard.sandiford@arm.com>
1293 * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
1294 Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
1296 2020-01-30 Alan Modra <amodra@gmail.com>
1298 * m32c-ibld.c: Regenerate.
1300 2020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com>
1302 * bpf-opc.c: Regenerate.
1304 2020-01-30 Jan Beulich <jbeulich@suse.com>
1306 * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
1307 (dis386): Use them to replace C2/C3 table entries.
1308 (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
1309 * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
1310 ones. Use Size64 instead of DefaultSize on Intel64 ones.
1311 * i386-tbl.h: Re-generate.
1313 2020-01-30 Jan Beulich <jbeulich@suse.com>
1315 * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
1317 (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
1319 * i386-tbl.h: Re-generate.
1321 2020-01-30 Alan Modra <amodra@gmail.com>
1323 * tic4x-dis.c (tic4x_dp): Make unsigned.
1325 2020-01-27 H.J. Lu <hongjiu.lu@intel.com>
1326 Jan Beulich <jbeulich@suse.com>
1329 * i386-dis.c (MOVSXD_Fixup): New function.
1330 (movsxd_mode): New enum.
1331 (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
1332 (intel_operand_size): Handle movsxd_mode.
1333 (OP_E_register): Likewise.
1335 * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
1336 register on movsxd. Add movsxd with 16-bit destination register
1337 for AMD64 and Intel64 ISAs.
1338 * i386-tbl.h: Regenerated.
1340 2020-01-27 Tamar Christina <tamar.christina@arm.com>
1343 * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
1344 * aarch64-asm-2.c: Regenerate
1345 * aarch64-dis-2.c: Likewise.
1346 * aarch64-opc-2.c: Likewise.
1348 2020-01-21 Jan Beulich <jbeulich@suse.com>
1350 * i386-opc.tbl (sysret): Drop DefaultSize.
1351 * i386-tbl.h: Re-generate.
1353 2020-01-21 Jan Beulich <jbeulich@suse.com>
1355 * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
1357 (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
1358 * i386-tbl.h: Re-generate.
1360 2020-01-20 Nick Clifton <nickc@redhat.com>
1362 * po/de.po: Updated German translation.
1363 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1364 * po/uk.po: Updated Ukranian translation.
1366 2020-01-20 Alan Modra <amodra@gmail.com>
1368 * hppa-dis.c (fput_const): Remove useless cast.
1370 2020-01-20 Alan Modra <amodra@gmail.com>
1372 * arm-dis.c (print_insn_arm): Wrap 'T' value.
1374 2020-01-18 Nick Clifton <nickc@redhat.com>
1376 * configure: Regenerate.
1377 * po/opcodes.pot: Regenerate.
1379 2020-01-18 Nick Clifton <nickc@redhat.com>
1381 Binutils 2.34 branch created.
1383 2020-01-17 Christian Biesinger <cbiesinger@google.com>
1385 * opintl.h: Fix spelling error (seperate).
1387 2020-01-17 H.J. Lu <hongjiu.lu@intel.com>
1389 * i386-opc.tbl: Add {vex} pseudo prefix.
1390 * i386-tbl.h: Regenerated.
1392 2020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1395 * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
1396 (neon_opcodes): Likewise.
1397 (select_arm_features): Make sure we enable MVE bits when selecting
1398 armv8.1-m.main. Make sure we do not enable MVE bits when not selecting
1401 2020-01-16 Jan Beulich <jbeulich@suse.com>
1403 * i386-opc.tbl: Drop stale comment from XOP section.
1405 2020-01-16 Jan Beulich <jbeulich@suse.com>
1407 * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
1408 (extractps): Add VexWIG to SSE2AVX forms.
1409 * i386-tbl.h: Re-generate.
1411 2020-01-16 Jan Beulich <jbeulich@suse.com>
1413 * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
1414 Size64 from and use VexW1 on SSE2AVX forms.
1415 (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
1416 VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
1417 * i386-tbl.h: Re-generate.
1419 2020-01-15 Alan Modra <amodra@gmail.com>
1421 * tic4x-dis.c (tic4x_version): Make unsigned long.
1422 (optab, optab_special, registernames): New file scope vars.
1423 (tic4x_print_register): Set up registernames rather than
1424 malloc'd registertable.
1425 (tic4x_disassemble): Delete optable and optable_special. Use
1426 optab and optab_special instead. Throw away old optab,
1427 optab_special and registernames when info->mach changes.
1429 2020-01-14 Sergey Belyashov <sergey.belyashov@gmail.com>
1432 * z80-dis.c (suffix): Use .db instruction to generate double
1435 2020-01-14 Alan Modra <amodra@gmail.com>
1437 * z8k-dis.c (unpack_instr): Formatting. Cast unsigned short
1438 values to unsigned before shifting.
1440 2020-01-13 Thomas Troeger <tstroege@gmx.de>
1442 * arm-dis.c (print_insn_arm): Fill in insn info fields for control
1444 (print_insn_thumb16, print_insn_thumb32): Likewise.
1445 (print_insn): Initialize the insn info.
1446 * i386-dis.c (print_insn): Initialize the insn info fields, and
1449 2012-01-13 Claudiu Zissulescu <claziss@gmail.com>
1451 * arc-opc.c (C_NE): Make it required.
1453 2012-01-13 Claudiu Zissulescu <claziss@gmail.com>
1455 * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
1456 reserved register name.
1458 2020-01-13 Alan Modra <amodra@gmail.com>
1460 * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
1461 (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
1463 2020-01-13 Alan Modra <amodra@gmail.com>
1465 * wasm32-dis.c (print_insn_wasm32): Localise variables. Store
1466 result of wasm_read_leb128 in a uint64_t and check that bits
1467 are not lost when copying to other locals. Use uint32_t for
1468 most locals. Use PRId64 when printing int64_t.
1470 2020-01-13 Alan Modra <amodra@gmail.com>
1472 * score-dis.c: Formatting.
1473 * score7-dis.c: Formatting.
1475 2020-01-13 Alan Modra <amodra@gmail.com>
1477 * score-dis.c (print_insn_score48): Use unsigned variables for
1478 unsigned values. Don't left shift negative values.
1479 (print_insn_score32): Likewise.
1480 * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
1482 2020-01-13 Alan Modra <amodra@gmail.com>
1484 * tic4x-dis.c (tic4x_print_register): Remove dead code.
1486 2020-01-13 Alan Modra <amodra@gmail.com>
1488 * fr30-ibld.c: Regenerate.
1490 2020-01-13 Alan Modra <amodra@gmail.com>
1492 * xgate-dis.c (print_insn): Don't left shift signed value.
1493 (ripBits): Formatting, use 1u.
1495 2020-01-10 Alan Modra <amodra@gmail.com>
1497 * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
1498 * tilegx-opc.c (parse_insn_tilegx): Likewise. Delete raw_opval.
1500 2020-01-10 Alan Modra <amodra@gmail.com>
1502 * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
1503 and XRREG value earlier to avoid a shift with negative exponent.
1504 * m10200-dis.c (disassemble): Similarly.
1506 2020-01-09 Nick Clifton <nickc@redhat.com>
1509 * z80-dis.c (ld_ii_ii): Use correct cast.
1511 2020-01-03 Sergey Belyashov <sergey.belyashov@gmail.com>
1514 * z80-dis.c (ld_ii_ii): Use character constant when checking
1517 2020-01-09 Jan Beulich <jbeulich@suse.com>
1519 * i386-dis.c (SEP_Fixup): New.
1521 (dis386_twobyte): Use it for sysenter/sysexit.
1522 (enum x86_64_isa): Change amd64 enumerator to value 1.
1523 (OP_J): Compare isa64 against intel64 instead of amd64.
1524 * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
1526 * i386-tbl.h: Re-generate.
1528 2020-01-08 Alan Modra <amodra@gmail.com>
1530 * z8k-dis.c: Include libiberty.h
1531 (instr_data_s): Make max_fetched unsigned.
1532 (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
1533 Don't exceed byte_info bounds.
1534 (output_instr): Make num_bytes unsigned.
1535 (unpack_instr): Likewise for nibl_count and loop.
1536 * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
1538 * z8k-opc.h: Regenerate.
1540 2020-01-07 Shahab Vahedi <shahab@synopsys.com>
1542 * arc-tbl.h (llock): Use 'LLOCK' as class.
1544 (scond): Use 'SCOND' as class.
1546 (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
1549 2020-01-06 Alan Modra <amodra@gmail.com>
1551 * m32c-ibld.c: Regenerate.
1553 2020-01-06 Alan Modra <amodra@gmail.com>
1556 * z80-dis.c (suffix): Don't use a local struct buffer copy.
1557 Peek at next byte to prevent recursion on repeated prefix bytes.
1558 Ensure uninitialised "mybuf" is not accessed.
1559 (print_insn_z80): Don't zero n_fetch and n_used here,..
1560 (print_insn_z80_buf): ..do it here instead.
1562 2020-01-04 Alan Modra <amodra@gmail.com>
1564 * m32r-ibld.c: Regenerate.
1566 2020-01-04 Alan Modra <amodra@gmail.com>
1568 * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
1570 2020-01-04 Alan Modra <amodra@gmail.com>
1572 * crx-dis.c (match_opcode): Avoid shift left of signed value.
1574 2020-01-04 Alan Modra <amodra@gmail.com>
1576 * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
1578 2020-01-03 Jan Beulich <jbeulich@suse.com>
1580 * aarch64-tbl.h (aarch64_opcode_table): Use
1581 SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
1583 2020-01-03 Jan Beulich <jbeulich@suse.com>
1585 * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
1586 forms of SUDOT and USDOT.
1588 2020-01-03 Jan Beulich <jbeulich@suse.com>
1590 * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
1592 * opcodes/aarch64-dis-2.c: Re-generate.
1594 2020-01-03 Jan Beulich <jbeulich@suse.com>
1596 * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
1598 * opcodes/aarch64-dis-2.c: Re-generate.
1600 2020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com>
1602 * z80-dis.c: Add support for eZ80 and Z80 instructions.
1604 2020-01-01 Alan Modra <amodra@gmail.com>
1606 Update year range in copyright notice of all files.
1608 For older changes see ChangeLog-2019
1610 Copyright (C) 2020 Free Software Foundation, Inc.
1612 Copying and distribution of this file, with or without modification,
1613 are permitted in any medium without royalty provided the copyright
1614 notice and this notice are preserved.
1620 version-control: never