1 2020-06-03 Nelson Chu <nelson.chu@sifive.com>
3 * riscv-opc.c (riscv_get_isa_spec_class): Change bfd_boolean to int.
4 (riscv_get_priv_spec_class): Likewise.
6 2020-06-01 Alan Modra <amodra@gmail.com>
8 * bpf-desc.c: Regenerate.
10 2020-05-28 Jose E. Marchesi <jose.marchesi@oracle.com>
11 David Faust <david.faust@oracle.com>
13 * bpf-desc.c: Regenerate.
14 * bpf-opc.h: Likewise.
15 * bpf-opc.c: Likewise.
16 * bpf-dis.c: Likewise.
18 2020-05-28 Alan Modra <amodra@gmail.com>
20 * nios2-dis.c (nios2_print_insn_arg): Avoid shift left of negative
23 2020-05-28 Alan Modra <amodra@gmail.com>
25 * ns32k-dis.c (print_insn_arg): Handle d value of 'f' for
27 (print_insn_ns32k): Revert last change.
29 2020-05-28 Nick Clifton <nickc@redhat.com>
31 * ns32k-dis.c (print_insn_ns32k): Change the arg_bufs array to
34 2020-05-26 Sandra Loosemore <sandra@codesourcery.com>
36 Fix extraction of signed constants in nios2 disassembler (again).
38 * nios2-dis.c (nios2_print_insn_arg): Add explicit casts to
39 extractions of signed fields.
41 2020-05-26 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
43 * s390-opc.txt: Relocate vector load/store instructions with
44 additional alignment parameter and change architecture level
45 constraint from z14 to z13.
47 2020-05-21 Alan Modra <amodra@gmail.com>
49 * arc-ext.c: Replace "if (x) free (x)" with "free (x)" throughout.
50 * sparc-dis.c: Likewise.
51 * tic4x-dis.c: Likewise.
52 * xtensa-dis.c: Likewise.
53 * bpf-desc.c: Regenerate.
54 * epiphany-desc.c: Regenerate.
55 * fr30-desc.c: Regenerate.
56 * frv-desc.c: Regenerate.
57 * ip2k-desc.c: Regenerate.
58 * iq2000-desc.c: Regenerate.
59 * lm32-desc.c: Regenerate.
60 * m32c-desc.c: Regenerate.
61 * m32r-desc.c: Regenerate.
62 * mep-asm.c: Regenerate.
63 * mep-desc.c: Regenerate.
64 * mt-desc.c: Regenerate.
65 * or1k-desc.c: Regenerate.
66 * xc16x-desc.c: Regenerate.
67 * xstormy16-desc.c: Regenerate.
69 2020-05-20 Nelson Chu <nelson.chu@sifive.com>
71 * riscv-opc.c (riscv_ext_version_table): The table used to store
72 all information about the supported spec and the corresponding ISA
73 versions. Currently, only Zicsr is supported to verify the
74 correctness of Z sub extension settings. Others will be supported
75 in the future patches.
76 (struct isa_spec_t, isa_specs): List for all supported ISA spec
77 classes and the corresponding strings.
78 (riscv_get_isa_spec_class): New function. Get the corresponding ISA
79 spec class by giving a ISA spec string.
80 * riscv-opc.c (struct priv_spec_t): New structure.
81 (struct priv_spec_t priv_specs): List for all supported privilege spec
82 classes and the corresponding strings.
83 (riscv_get_priv_spec_class): New function. Get the corresponding
84 privilege spec class by giving a spec string.
85 (riscv_get_priv_spec_name): New function. Get the corresponding
86 privilege spec string by giving a CSR version class.
87 * riscv-dis.c: Updated since DECLARE_CSR is changed.
88 * riscv-dis.c: Add new disassembler option -Mpriv-spec to dump the CSR
89 according to the chosen version. Build a hash table riscv_csr_hash to
90 store the valid CSR for the chosen pirv verison. Dump the direct
91 CSR address rather than it's name if it is invalid.
92 (parse_riscv_dis_option_without_args): New function. Parse the options
94 (parse_riscv_dis_option): Call parse_riscv_dis_option_without_args to
95 parse the options without arguments first, and then handle the options
96 with arguments. Add the new option -Mpriv-spec, which has argument.
97 * riscv-dis.c (print_riscv_disassembler_options): Add description
98 about the new OBJDUMP option.
100 2020-05-19 Peter Bergner <bergner@linux.ibm.com>
102 * ppc-opc.c (insert_ls, extract_ls): Handle 3-bit L fields and new
103 WC values on POWER10 sync, dcbf and wait instructions.
104 (insert_pl, extract_pl): New functions.
105 (L2OPT, LS, WC): Use insert_ls and extract_ls.
106 (LS3): New , 3-bit L for sync.
107 (LS3, L3OPT): New, 3-bit L for sync and dcbf.
108 (SC2, PL): New, 2-bit SC and PL for sync and wait.
109 (XWCPL_MASK, XL3RT_MASK, XSYNCLS_MASK): New instruction masks.
110 (XOPL3, XWCPL, XSYNCLS): New opcode macros.
111 (powerpc_opcodes) <dcbflp, dcbfps, dcbstps pause_short, phwsync,
112 plwsync, stcisync, stncisync, stsync, waitrsv>: New extended mnemonics.
113 <wait>: Enable PL operand on POWER10.
114 <dcbf>: Enable L3OPT operand on POWER10.
115 <sync>: Enable SC2 operand on POWER10.
117 2020-05-19 Stafford Horne <shorne@gmail.com>
120 * or1k-asm.c: Regenerate.
121 * or1k-desc.c: Regenerate.
122 * or1k-desc.h: Regenerate.
123 * or1k-dis.c: Regenerate.
124 * or1k-ibld.c: Regenerate.
125 * or1k-opc.c: Regenerate.
126 * or1k-opc.h: Regenerate.
127 * or1k-opinst.c: Regenerate.
129 2020-05-11 Alan Modra <amodra@gmail.com>
131 * ppc-opc (powerpc_opcodes): Add xscmpeqqp, xscmpgeqp, xscmpgtqp,
134 2020-05-11 Alan Modra <amodra@gmail.com>
136 * ppc-opc.c (powerpc_opcodes): Add lxvrbx, lxvrhx, lxvrwx, lxvrdx,
137 stxvrbx, stxvrhx, stxvrwx, stxvrdx.
139 2020-05-11 Alan Modra <amodra@gmail.com>
141 * ppc-opc.c (powerpc_opcodes): Add xvtlsbb.
143 2020-05-11 Alan Modra <amodra@gmail.com>
145 * ppc-opc.c (powerpc_opcodes): Add vstribl, vstribr, vstrihl, vstrihr,
146 vclrlb, vclrrb, vstribl., vstribr., vstrihl., vstrihr..
148 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
150 * ppc-opc.c (powerpc_opcodes) <setbc, setbcr, setnbc, setnbcr>: New
153 2020-05-11 Alan Modra <amodra@gmail.com>
155 * ppc-opc.c (UIM8, P_U8XX4_MASK): Define.
156 (powerpc_opcodes): Add vgnb, vcfuged, vpextd, vpdepd, vclzdm,
157 vctzdm, cntlzdm, pdepd, pextd, cfuged, cnttzdm.
158 (prefix_opcodes): Add xxeval.
160 2020-05-11 Alan Modra <amodra@gmail.com>
162 * ppc-opc.c (powerpc_opcodes): Add xxgenpcvbm, xxgenpcvhm,
163 xxgenpcvwm, xxgenpcvdm.
165 2020-05-11 Alan Modra <amodra@gmail.com>
167 * ppc-opc.c (MP, VXVAM_MASK): Define.
168 (VXVAPS_MASK): Use VXVA_MASK.
169 (powerpc_opcodes): Add mtvsrbmi, vexpandbm, vexpandhm, vexpandwm,
170 vexpanddm, vexpandqm, vextractbm, vextracthm, vextractwm,
171 vextractdm, vextractqm, mtvsrbm, mtvsrhm, mtvsrwm, mtvsrdm, mtvsrqm,
172 vcntmbb, vcntmbh, vcntmbw, vcntmbd.
174 2020-05-11 Alan Modra <amodra@gmail.com>
175 Peter Bergner <bergner@linux.ibm.com>
177 * ppc-opc.c (insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a):
179 (powerpc_operands): Define ACC, PMSK8, PMSK4, PMSK2, XMSK, YMSK,
180 YMSK2, XA6a, XA6ap, XB6a entries.
181 (PMMIRR, P_X_MASK, P_XX1_MASK, P_GER_MASK): Define
182 (P_GER2_MASK, P_GER4_MASK, P_GER8_MASK, P_GER64_MASK): Define.
184 (powerpc_opcodes): Add xxmfacc, xxmtacc, xxsetaccz,
185 xvi8ger4pp, xvi8ger4, xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger,
186 xvi4ger8pp, xvi4ger8, xvi16ger2spp, xvi16ger2s, xvbf16ger2pp,
187 xvbf16ger2, xvf64gerpp, xvf64ger, xvi16ger2, xvf16ger2np,
188 xvf32gernp, xvi8ger4spp, xvi16ger2pp, xvbf16ger2np, xvf64gernp,
189 xvf16ger2pn, xvf32gerpn, xvbf16ger2pn, xvf64gerpn, xvf16ger2nn,
190 xvf32gernn, xvbf16ger2nn, xvf64gernn, xvcvbf16sp, xvcvspbf16.
191 (prefix_opcodes): Add pmxvi8ger4pp, pmxvi8ger4, pmxvf16ger2pp,
192 pmxvf16ger2, pmxvf32gerpp, pmxvf32ger, pmxvi4ger8pp, pmxvi4ger8,
193 pmxvi16ger2spp, pmxvi16ger2s, pmxvbf16ger2pp, pmxvbf16ger2,
194 pmxvf64gerpp, pmxvf64ger, pmxvi16ger2, pmxvf16ger2np, pmxvf32gernp,
195 pmxvi8ger4spp, pmxvi16ger2pp, pmxvbf16ger2np, pmxvf64gernp,
196 pmxvf16ger2pn, pmxvf32gerpn, pmxvbf16ger2pn, pmxvf64gerpn,
197 pmxvf16ger2nn, pmxvf32gernn, pmxvbf16ger2nn, pmxvf64gernn.
199 2020-05-11 Alan Modra <amodra@gmail.com>
201 * ppc-opc.c (insert_imm32, extract_imm32): New functions.
202 (insert_xts, extract_xts): New functions.
203 (IMM32, UIM3, IX, UIM5, SH3, XTS, P8RR): Define.
204 (P_XX4_MASK, P_UXX4_MASK, VSOP, P_VS_MASK, P_VSI_MASK): Define.
205 (VXRC_MASK, VXSH_MASK): Define.
206 (powerpc_opcodes): Add vinsbvlx, vsldbi, vextdubvlx, vextdubvrx,
207 vextduhvlx, vextduhvrx, vextduwvlx, vextduwvrx, vextddvlx,
208 vextddvrx, vinshvlx, vinswvlx, vinsw, vinsbvrx, vinshvrx,
209 vinswvrx, vinsd, vinsblx, vsrdbi, vinshlx, vinswlx, vinsdlx,
210 vinsbrx, vinshrx, vinswrx, vinsdrx, lxvkq.
211 (prefix_opcodes): Add xxsplti32dx, xxspltidp, xxspltiw, xxblendvb,
212 xxblendvh, xxblendvw, xxblendvd, xxpermx.
214 2020-05-11 Alan Modra <amodra@gmail.com>
216 * ppc-opc.c (powerpc_opcodes): Add vrlq, vdivuq, vmsumcud, vrlqmi,
217 vmuloud, vcmpuq, vslq, vdivsq, vcmpsq, vrlqnm, vcmpequq, vmulosd,
218 vsrq, vdiveuq, vcmpgtuq, vmuleud, vsraq, vdivesq, vcmpgtsq, vmulesd,
219 vcmpequq., vextsd2q, vmoduq, vcmpgtuq., vmodsq, vcmpgtsq., xscvqpuqz,
220 xscvuqqp, xscvqpsqz, xscvsqqp, dcffixqq, dctfixqq.
222 2020-05-11 Alan Modra <amodra@gmail.com>
224 * ppc-opc.c (insert_xtp, extract_xtp): New functions.
225 (XTP, DQXP, DQXP_MASK): Define.
226 (powerpc_opcodes): Add lxvp, stxvp, lxvpx, stxvpx.
227 (prefix_opcodes): Add plxvp and pstxvp.
229 2020-05-11 Alan Modra <amodra@gmail.com>
231 * ppc-opc.c (powerpc_opcodes): Add vdivuw, vdivud, vdivsw, vmulld,
232 vdivsd, vmulhuw, vdiveuw, vmulhud, vdiveud, vmulhsw, vdivesw,
233 vmulhsd, vdivesd, vmoduw, vmodud, vmodsw, vmodsd.
235 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
237 * ppc-opc.c (powerpc_opcodes) <brd, brh, brw>: New mnemonics.
239 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
241 * ppc-opc.c (insert_l1opt, extract_l1opt): New functions.
243 (powerpc_opcodes) <paste.>: Add L operand for cpu POWER10.
245 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
247 * ppc-opc.c (powerpc_opcodes) <slbiag>: Add variant with L operand.
249 2020-05-11 Alan Modra <amodra@gmail.com>
251 * ppc-dis.c (powerpc_init_dialect): Default to "power10".
253 2020-05-11 Alan Modra <amodra@gmail.com>
255 * ppc-dis.c (ppc_opts): Add "power10" entry.
256 (print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming.
257 * ppc-opc.c (POWER10): Rename from POWERXX. Update all uses.
259 2020-05-11 Nick Clifton <nickc@redhat.com>
261 * po/fr.po: Updated French translation.
263 2020-04-30 Alex Coplan <alex.coplan@arm.com>
265 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
266 * aarch64-opc.c (fields): Add entry for FLD_imm16_2.
267 (operand_general_constraint_met_p): validate
268 AARCH64_OPND_UNDEFINED.
269 * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry
271 * aarch64-asm-2.c: Regenerated.
272 * aarch64-dis-2.c: Regenerated.
273 * aarch64-opc-2.c: Regenerated.
275 2020-04-29 Nick Clifton <nickc@redhat.com>
278 * sh-opc.h: Also use unsigned 8-bit immediate values for the LDRC
281 2020-04-29 Nick Clifton <nickc@redhat.com>
283 * po/sv.po: Updated Swedish translation.
285 2020-04-29 Nick Clifton <nickc@redhat.com>
288 * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U. Use
289 IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
290 * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
293 2020-04-21 Andreas Schwab <schwab@linux-m68k.org>
296 * m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
297 cmpi only on m68020up and cpu32.
299 2020-04-20 Sudakshina Das <sudi.das@arm.com>
301 * aarch64-asm.c (aarch64_ins_none): New.
302 * aarch64-asm.h (ins_none): New declaration.
303 * aarch64-dis.c (aarch64_ext_none): New.
304 * aarch64-dis.h (ext_none): New declaration.
305 * aarch64-opc.c (aarch64_print_operand): Update case for
306 AARCH64_OPND_BARRIER_PSB.
307 * aarch64-tbl.h (aarch64_opcode_table): Add tsb.
308 (AARCH64_OPERANDS): Update inserter/extracter for
309 AARCH64_OPND_BARRIER_PSB to use new dummy functions.
310 * aarch64-asm-2.c: Regenerated.
311 * aarch64-dis-2.c: Regenerated.
312 * aarch64-opc-2.c: Regenerated.
314 2020-04-20 Sudakshina Das <sudi.das@arm.com>
316 * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
317 (aarch64_feature_ras, RAS): Likewise.
318 (aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
319 (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
320 autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
321 autiaz, autiasp, autibz, autibsp to be CORE_INSN.
322 * aarch64-asm-2.c: Regenerated.
323 * aarch64-dis-2.c: Regenerated.
324 * aarch64-opc-2.c: Regenerated.
326 2020-04-17 Fredrik Strupe <fredrik@strupe.net>
328 * arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
329 (print_insn_neon): Support disassembly of conditional
332 2020-02-16 David Faust <david.faust@oracle.com>
334 * bpf-desc.c: Regenerate.
335 * bpf-desc.h: Likewise.
336 * bpf-opc.c: Regenerate.
337 * bpf-opc.h: Likewise.
339 2020-04-07 Lili Cui <lili.cui@intel.com>
341 * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
342 (prefix_table): New instructions (see prefixes above).
344 * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
345 CPU_ANY_TSXLDTRK_FLAGS.
346 (cpu_flags): Add CpuTSXLDTRK.
347 * i386-opc.h (enum): Add CpuTSXLDTRK.
348 (i386_cpu_flags): Add cputsxldtrk.
349 * i386-opc.tbl: Add XSUSPLDTRK insns.
350 * i386-init.h: Regenerate.
351 * i386-tbl.h: Likewise.
353 2020-04-02 Lili Cui <lili.cui@intel.com>
355 * i386-dis.c (prefix_table): New instructions serialize.
356 * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
357 CPU_ANY_SERIALIZE_FLAGS.
358 (cpu_flags): Add CpuSERIALIZE.
359 * i386-opc.h (enum): Add CpuSERIALIZE.
360 (i386_cpu_flags): Add cpuserialize.
361 * i386-opc.tbl: Add SERIALIZE insns.
362 * i386-init.h: Regenerate.
363 * i386-tbl.h: Likewise.
365 2020-03-26 Alan Modra <amodra@gmail.com>
367 * disassemble.h (opcodes_assert): Declare.
368 (OPCODES_ASSERT): Define.
369 * disassemble.c: Don't include assert.h. Include opintl.h.
370 (opcodes_assert): New function.
371 * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
372 (bfd_h8_disassemble): Reduce size of data array. Correctly
373 calculate maxlen. Omit insn decoding when insn length exceeds
374 maxlen. Exit from nibble loop when looking for E, before
375 accessing next data byte. Move processing of E outside loop.
376 Replace tests of maxlen in loop with assertions.
378 2020-03-26 Alan Modra <amodra@gmail.com>
380 * arc-dis.c (find_format): Init needs_limm. Simplify use of limm.
382 2020-03-25 Alan Modra <amodra@gmail.com>
384 * z80-dis.c (suffix): Init mybuf.
386 2020-03-22 Alan Modra <amodra@gmail.com>
388 * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
389 successflly read from section.
391 2020-03-22 Alan Modra <amodra@gmail.com>
393 * arc-dis.c (find_format): Use ISO C string concatenation rather
394 than line continuation within a string. Don't access needs_limm
395 before testing opcode != NULL.
397 2020-03-22 Alan Modra <amodra@gmail.com>
399 * ns32k-dis.c (print_insn_arg): Update comment.
400 (print_insn_ns32k): Reduce size of index_offset array, and
401 initialize, passing -1 to print_insn_arg for args that are not
402 an index. Don't exit arg loop early. Abort on bad arg number.
404 2020-03-22 Alan Modra <amodra@gmail.com>
406 * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
407 * s12z-opc.c: Formatting.
408 (operands_f): Return an int.
409 (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
410 (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
411 (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
412 (exg_sex_discrim): Likewise.
413 (create_immediate_operand, create_bitfield_operand),
414 (create_register_operand_with_size, create_register_all_operand),
415 (create_register_all16_operand, create_simple_memory_operand),
416 (create_memory_operand, create_memory_auto_operand): Don't
417 segfault on malloc failure.
418 (z_ext24_decode): Return an int status, negative on fail, zero
420 (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
421 (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
422 (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
423 (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
424 (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
425 (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
426 (loop_primitive_decode, shift_decode, psh_pul_decode),
427 (bit_field_decode): Similarly.
428 (z_decode_signed_value, decode_signed_value): Similarly. Add arg
429 to return value, update callers.
430 (x_opr_decode_with_size): Check all reads, returning NULL on fail.
431 Don't segfault on NULL operand.
432 (decode_operation): Return OP_INVALID on first fail.
433 (decode_s12z): Check all reads, returning -1 on fail.
435 2020-03-20 Alan Modra <amodra@gmail.com>
437 * metag-dis.c (print_insn_metag): Don't ignore status from
440 2020-03-20 Alan Modra <amodra@gmail.com>
442 * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
443 Initialize parts of buffer not written when handling a possible
444 2-byte insn at end of section. Don't attempt decoding of such
445 an insn by the 4-byte machinery.
447 2020-03-20 Alan Modra <amodra@gmail.com>
449 * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
450 partially filled buffer. Prevent lookup of 4-byte insns when
451 only VLE 2-byte insns are possible due to section size. Print
452 ".word" rather than ".long" for 2-byte leftovers.
454 2020-03-17 Sergey Belyashov <sergey.belyashov@gmail.com>
457 * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
459 2020-03-13 Jan Beulich <jbeulich@suse.com>
461 * i386-dis.c (X86_64_0D): Rename to ...
462 (X86_64_0E): ... this.
464 2020-03-09 H.J. Lu <hongjiu.lu@intel.com>
466 * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
467 * Makefile.in: Regenerated.
469 2020-03-09 Jan Beulich <jbeulich@suse.com>
471 * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
473 * i386-tbl.h: Re-generate.
475 2020-03-09 Jan Beulich <jbeulich@suse.com>
477 * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
478 vprot*, vpsha*, and vpshl*.
479 * i386-tbl.h: Re-generate.
481 2020-03-09 Jan Beulich <jbeulich@suse.com>
483 * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
484 vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
485 * i386-tbl.h: Re-generate.
487 2020-03-09 Jan Beulich <jbeulich@suse.com>
489 * i386-gen.c (set_bitfield): Ignore zero-length field names.
490 * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
491 cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
492 * i386-tbl.h: Re-generate.
494 2020-03-09 Jan Beulich <jbeulich@suse.com>
496 * i386-gen.c (struct template_arg, struct template_instance,
497 struct template_param, struct template, templates,
498 parse_template, expand_templates): New.
499 (process_i386_opcodes): Various local variables moved to
500 expand_templates. Call parse_template and expand_templates.
501 * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
502 * i386-tbl.h: Re-generate.
504 2020-03-06 Jan Beulich <jbeulich@suse.com>
506 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
507 vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
508 register and memory source templates. Replace VexW= by VexW*
510 * i386-tbl.h: Re-generate.
512 2020-03-06 Jan Beulich <jbeulich@suse.com>
514 * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
515 VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
516 * i386-tbl.h: Re-generate.
518 2020-03-06 Jan Beulich <jbeulich@suse.com>
520 * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
521 * i386-tbl.h: Re-generate.
523 2020-03-06 Jan Beulich <jbeulich@suse.com>
525 * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
526 (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
527 pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
528 VexW0 on SSE2AVX variants.
529 (vmovq): Drop NoRex64 from XMM/XMM variants.
530 (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
531 vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
532 applicable use VexW0.
533 * i386-tbl.h: Re-generate.
535 2020-03-06 Jan Beulich <jbeulich@suse.com>
537 * i386-gen.c (opcode_modifiers): Remove Rex64 field.
538 * i386-opc.h (Rex64): Delete.
539 (struct i386_opcode_modifier): Remove rex64 field.
540 * i386-opc.tbl (crc32): Drop Rex64.
541 Replace Rex64 with Size64 everywhere else.
542 * i386-tbl.h: Re-generate.
544 2020-03-06 Jan Beulich <jbeulich@suse.com>
546 * i386-dis.c (OP_E_memory): Exclude recording of used address
547 prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
548 addressed memory operands for MPX insns.
550 2020-03-06 Jan Beulich <jbeulich@suse.com>
552 * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
553 invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
554 adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
555 (ptwrite): Split into non-64-bit and 64-bit forms.
556 * i386-tbl.h: Re-generate.
558 2020-03-06 Jan Beulich <jbeulich@suse.com>
560 * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
562 * i386-tbl.h: Re-generate.
564 2020-03-04 Jan Beulich <jbeulich@suse.com>
566 * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
567 (prefix_table): Move vmmcall here. Add vmgexit.
568 (rm_table): Replace vmmcall entry by prefix_table[] escape.
569 * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
570 (cpu_flags): Add CpuSEV_ES entry.
571 * i386-opc.h (CpuSEV_ES): New.
572 (union i386_cpu_flags): Add cpusev_es field.
573 * i386-opc.tbl (vmgexit): New.
574 * i386-init.h, i386-tbl.h: Re-generate.
576 2020-03-03 H.J. Lu <hongjiu.lu@intel.com>
578 * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
580 * i386-opc.h (IGNORESIZE): New.
581 (DEFAULTSIZE): Likewise.
582 (IgnoreSize): Removed.
583 (DefaultSize): Likewise.
585 (i386_opcode_modifier): Replace ignoresize/defaultsize with
587 * i386-opc.tbl (IgnoreSize): New.
588 (DefaultSize): Likewise.
589 * i386-tbl.h: Regenerated.
591 2020-03-03 Sergey Belyashov <sergey.belyashov@gmail.com>
594 * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
597 2020-03-03 H.J. Lu <hongjiu.lu@intel.com>
600 * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
601 vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
602 * i386-tbl.h: Regenerated.
604 2020-02-26 Alan Modra <amodra@gmail.com>
606 * aarch64-asm.c: Indent labels correctly.
607 * aarch64-dis.c: Likewise.
608 * aarch64-gen.c: Likewise.
609 * aarch64-opc.c: Likewise.
610 * alpha-dis.c: Likewise.
611 * i386-dis.c: Likewise.
612 * nds32-asm.c: Likewise.
613 * nfp-dis.c: Likewise.
614 * visium-dis.c: Likewise.
616 2020-02-25 Claudiu Zissulescu <claziss@gmail.com>
618 * arc-regs.h (int_vector_base): Make it available for all ARC
621 2020-02-20 Nelson Chu <nelson.chu@sifive.com>
623 * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
626 2020-02-19 Nelson Chu <nelson.chu@sifive.com>
628 * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
629 c.mv/c.li if rs1 is zero.
631 2020-02-17 H.J. Lu <hongjiu.lu@intel.com>
633 * i386-gen.c (cpu_flag_init): Replace CpuABM with
634 CpuLZCNT|CpuPOPCNT. Add CpuPOPCNT to CPU_SSE4_2_FLAGS. Add
636 (cpu_flags): Remove CpuABM. Add CpuPOPCNT.
637 * i386-opc.h (CpuABM): Removed.
639 (i386_cpu_flags): Remove cpuabm. Add cpupopcnt.
640 * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
641 popcnt. Remove CpuABM from lzcnt.
642 * i386-init.h: Regenerated.
643 * i386-tbl.h: Likewise.
645 2020-02-17 Jan Beulich <jbeulich@suse.com>
647 * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
648 Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
649 VexW1 instead of open-coding them.
650 * i386-tbl.h: Re-generate.
652 2020-02-17 Jan Beulich <jbeulich@suse.com>
654 * i386-opc.tbl (AddrPrefixOpReg): Define.
655 (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
656 umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
657 templates. Drop NoRex64.
658 * i386-tbl.h: Re-generate.
660 2020-02-17 Jan Beulich <jbeulich@suse.com>
663 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
664 vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
665 into Intel syntax instance (with Unpsecified) and AT&T one
667 (vcvtneps2bf16): Likewise, along with folding the two so far
669 * i386-tbl.h: Re-generate.
671 2020-02-16 H.J. Lu <hongjiu.lu@intel.com>
673 * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
676 2020-02-17 Alan Modra <amodra@gmail.com>
678 * i386-gen.c (cpu_flag_init): Correct last change.
680 2020-02-16 H.J. Lu <hongjiu.lu@intel.com>
682 * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS. Remove
685 2020-02-14 H.J. Lu <hongjiu.lu@intel.com>
687 * i386-opc.tbl (movsx): Remove Intel syntax comments.
690 2020-02-14 Jan Beulich <jbeulich@suse.com>
693 * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
694 destination for Cpu64-only variant.
695 (movzx): Fold patterns.
696 * i386-tbl.h: Re-generate.
698 2020-02-13 Jan Beulich <jbeulich@suse.com>
700 * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
701 CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
702 CPU_ANY_SSE4_FLAGS entry.
703 * i386-init.h: Re-generate.
705 2020-02-12 Jan Beulich <jbeulich@suse.com>
707 * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
708 with Unspecified, making the present one AT&T syntax only.
709 * i386-tbl.h: Re-generate.
711 2020-02-12 Jan Beulich <jbeulich@suse.com>
713 * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
714 * i386-tbl.h: Re-generate.
716 2020-02-12 Jan Beulich <jbeulich@suse.com>
719 * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
720 * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
721 Amd64 and Intel64 templates.
722 (call, jmp): Likewise for far indirect variants. Dro
724 * i386-tbl.h: Re-generate.
726 2020-02-11 Jan Beulich <jbeulich@suse.com>
728 * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
729 * i386-opc.h (ShortForm): Delete.
730 (struct i386_opcode_modifier): Remove shortform field.
731 * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
732 fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
733 fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
734 ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
736 * i386-tbl.h: Re-generate.
738 2020-02-11 Jan Beulich <jbeulich@suse.com>
740 * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
741 fucompi): Drop ShortForm from operand-less templates.
742 * i386-tbl.h: Re-generate.
744 2020-02-11 Alan Modra <amodra@gmail.com>
746 * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
747 * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
748 * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
749 * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
750 * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
752 2020-02-10 Matthew Malcomson <matthew.malcomson@arm.com>
754 * arm-dis.c (print_insn_cde): Define 'V' parse character.
755 (cde_opcodes): Add VCX* instructions.
757 2020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
758 Matthew Malcomson <matthew.malcomson@arm.com>
760 * arm-dis.c (struct cdeopcode32): New.
761 (CDE_OPCODE): New macro.
762 (cde_opcodes): New disassembly table.
763 (regnames): New option to table.
764 (cde_coprocs): New global variable.
765 (print_insn_cde): New
766 (print_insn_thumb32): Use print_insn_cde.
767 (parse_arm_disassembler_options): Parse coprocN args.
769 2020-02-10 H.J. Lu <hongjiu.lu@intel.com>
772 * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
774 * i386-opc.h (AMD64): Removed.
778 (INTEL64ONLY): Likewise.
779 (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
780 * i386-opc.tbl (Amd64): New.
782 (Intel64Only): Likewise.
783 Replace AMD64 with Amd64. Update sysenter/sysenter with
784 Cpu64 and Intel64Only. Remove AMD64 from sysenter/sysenter.
785 * i386-tbl.h: Regenerated.
787 2020-02-07 Sergey Belyashov <sergey.belyashov@gmail.com>
790 * z80-dis.c: Add support for GBZ80 opcodes.
792 2020-02-04 Alan Modra <amodra@gmail.com>
794 * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
796 2020-02-03 Alan Modra <amodra@gmail.com>
798 * m32c-ibld.c: Regenerate.
800 2020-02-01 Alan Modra <amodra@gmail.com>
802 * frv-ibld.c: Regenerate.
804 2020-01-31 Jan Beulich <jbeulich@suse.com>
806 * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
807 (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
808 (OP_E_memory): Replace xmm_mdq_mode case label by
809 vex_scalar_w_dq_mode one.
810 * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
812 2020-01-31 Jan Beulich <jbeulich@suse.com>
814 * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
815 (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
816 vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
817 (intel_operand_size): Drop vex_w_dq_mode case label.
819 2020-01-31 Richard Sandiford <richard.sandiford@arm.com>
821 * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
822 Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
824 2020-01-30 Alan Modra <amodra@gmail.com>
826 * m32c-ibld.c: Regenerate.
828 2020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com>
830 * bpf-opc.c: Regenerate.
832 2020-01-30 Jan Beulich <jbeulich@suse.com>
834 * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
835 (dis386): Use them to replace C2/C3 table entries.
836 (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
837 * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
838 ones. Use Size64 instead of DefaultSize on Intel64 ones.
839 * i386-tbl.h: Re-generate.
841 2020-01-30 Jan Beulich <jbeulich@suse.com>
843 * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
845 (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
847 * i386-tbl.h: Re-generate.
849 2020-01-30 Alan Modra <amodra@gmail.com>
851 * tic4x-dis.c (tic4x_dp): Make unsigned.
853 2020-01-27 H.J. Lu <hongjiu.lu@intel.com>
854 Jan Beulich <jbeulich@suse.com>
857 * i386-dis.c (MOVSXD_Fixup): New function.
858 (movsxd_mode): New enum.
859 (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
860 (intel_operand_size): Handle movsxd_mode.
861 (OP_E_register): Likewise.
863 * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
864 register on movsxd. Add movsxd with 16-bit destination register
865 for AMD64 and Intel64 ISAs.
866 * i386-tbl.h: Regenerated.
868 2020-01-27 Tamar Christina <tamar.christina@arm.com>
871 * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
872 * aarch64-asm-2.c: Regenerate
873 * aarch64-dis-2.c: Likewise.
874 * aarch64-opc-2.c: Likewise.
876 2020-01-21 Jan Beulich <jbeulich@suse.com>
878 * i386-opc.tbl (sysret): Drop DefaultSize.
879 * i386-tbl.h: Re-generate.
881 2020-01-21 Jan Beulich <jbeulich@suse.com>
883 * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
885 (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
886 * i386-tbl.h: Re-generate.
888 2020-01-20 Nick Clifton <nickc@redhat.com>
890 * po/de.po: Updated German translation.
891 * po/pt_BR.po: Updated Brazilian Portuguese translation.
892 * po/uk.po: Updated Ukranian translation.
894 2020-01-20 Alan Modra <amodra@gmail.com>
896 * hppa-dis.c (fput_const): Remove useless cast.
898 2020-01-20 Alan Modra <amodra@gmail.com>
900 * arm-dis.c (print_insn_arm): Wrap 'T' value.
902 2020-01-18 Nick Clifton <nickc@redhat.com>
904 * configure: Regenerate.
905 * po/opcodes.pot: Regenerate.
907 2020-01-18 Nick Clifton <nickc@redhat.com>
909 Binutils 2.34 branch created.
911 2020-01-17 Christian Biesinger <cbiesinger@google.com>
913 * opintl.h: Fix spelling error (seperate).
915 2020-01-17 H.J. Lu <hongjiu.lu@intel.com>
917 * i386-opc.tbl: Add {vex} pseudo prefix.
918 * i386-tbl.h: Regenerated.
920 2020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
923 * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
924 (neon_opcodes): Likewise.
925 (select_arm_features): Make sure we enable MVE bits when selecting
926 armv8.1-m.main. Make sure we do not enable MVE bits when not selecting
929 2020-01-16 Jan Beulich <jbeulich@suse.com>
931 * i386-opc.tbl: Drop stale comment from XOP section.
933 2020-01-16 Jan Beulich <jbeulich@suse.com>
935 * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
936 (extractps): Add VexWIG to SSE2AVX forms.
937 * i386-tbl.h: Re-generate.
939 2020-01-16 Jan Beulich <jbeulich@suse.com>
941 * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
942 Size64 from and use VexW1 on SSE2AVX forms.
943 (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
944 VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
945 * i386-tbl.h: Re-generate.
947 2020-01-15 Alan Modra <amodra@gmail.com>
949 * tic4x-dis.c (tic4x_version): Make unsigned long.
950 (optab, optab_special, registernames): New file scope vars.
951 (tic4x_print_register): Set up registernames rather than
952 malloc'd registertable.
953 (tic4x_disassemble): Delete optable and optable_special. Use
954 optab and optab_special instead. Throw away old optab,
955 optab_special and registernames when info->mach changes.
957 2020-01-14 Sergey Belyashov <sergey.belyashov@gmail.com>
960 * z80-dis.c (suffix): Use .db instruction to generate double
963 2020-01-14 Alan Modra <amodra@gmail.com>
965 * z8k-dis.c (unpack_instr): Formatting. Cast unsigned short
966 values to unsigned before shifting.
968 2020-01-13 Thomas Troeger <tstroege@gmx.de>
970 * arm-dis.c (print_insn_arm): Fill in insn info fields for control
972 (print_insn_thumb16, print_insn_thumb32): Likewise.
973 (print_insn): Initialize the insn info.
974 * i386-dis.c (print_insn): Initialize the insn info fields, and
977 2012-01-13 Claudiu Zissulescu <claziss@gmail.com>
979 * arc-opc.c (C_NE): Make it required.
981 2012-01-13 Claudiu Zissulescu <claziss@gmail.com>
983 * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
984 reserved register name.
986 2020-01-13 Alan Modra <amodra@gmail.com>
988 * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
989 (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
991 2020-01-13 Alan Modra <amodra@gmail.com>
993 * wasm32-dis.c (print_insn_wasm32): Localise variables. Store
994 result of wasm_read_leb128 in a uint64_t and check that bits
995 are not lost when copying to other locals. Use uint32_t for
996 most locals. Use PRId64 when printing int64_t.
998 2020-01-13 Alan Modra <amodra@gmail.com>
1000 * score-dis.c: Formatting.
1001 * score7-dis.c: Formatting.
1003 2020-01-13 Alan Modra <amodra@gmail.com>
1005 * score-dis.c (print_insn_score48): Use unsigned variables for
1006 unsigned values. Don't left shift negative values.
1007 (print_insn_score32): Likewise.
1008 * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
1010 2020-01-13 Alan Modra <amodra@gmail.com>
1012 * tic4x-dis.c (tic4x_print_register): Remove dead code.
1014 2020-01-13 Alan Modra <amodra@gmail.com>
1016 * fr30-ibld.c: Regenerate.
1018 2020-01-13 Alan Modra <amodra@gmail.com>
1020 * xgate-dis.c (print_insn): Don't left shift signed value.
1021 (ripBits): Formatting, use 1u.
1023 2020-01-10 Alan Modra <amodra@gmail.com>
1025 * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
1026 * tilegx-opc.c (parse_insn_tilegx): Likewise. Delete raw_opval.
1028 2020-01-10 Alan Modra <amodra@gmail.com>
1030 * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
1031 and XRREG value earlier to avoid a shift with negative exponent.
1032 * m10200-dis.c (disassemble): Similarly.
1034 2020-01-09 Nick Clifton <nickc@redhat.com>
1037 * z80-dis.c (ld_ii_ii): Use correct cast.
1039 2020-01-03 Sergey Belyashov <sergey.belyashov@gmail.com>
1042 * z80-dis.c (ld_ii_ii): Use character constant when checking
1045 2020-01-09 Jan Beulich <jbeulich@suse.com>
1047 * i386-dis.c (SEP_Fixup): New.
1049 (dis386_twobyte): Use it for sysenter/sysexit.
1050 (enum x86_64_isa): Change amd64 enumerator to value 1.
1051 (OP_J): Compare isa64 against intel64 instead of amd64.
1052 * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
1054 * i386-tbl.h: Re-generate.
1056 2020-01-08 Alan Modra <amodra@gmail.com>
1058 * z8k-dis.c: Include libiberty.h
1059 (instr_data_s): Make max_fetched unsigned.
1060 (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
1061 Don't exceed byte_info bounds.
1062 (output_instr): Make num_bytes unsigned.
1063 (unpack_instr): Likewise for nibl_count and loop.
1064 * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
1066 * z8k-opc.h: Regenerate.
1068 2020-01-07 Shahab Vahedi <shahab@synopsys.com>
1070 * arc-tbl.h (llock): Use 'LLOCK' as class.
1072 (scond): Use 'SCOND' as class.
1074 (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
1077 2020-01-06 Alan Modra <amodra@gmail.com>
1079 * m32c-ibld.c: Regenerate.
1081 2020-01-06 Alan Modra <amodra@gmail.com>
1084 * z80-dis.c (suffix): Don't use a local struct buffer copy.
1085 Peek at next byte to prevent recursion on repeated prefix bytes.
1086 Ensure uninitialised "mybuf" is not accessed.
1087 (print_insn_z80): Don't zero n_fetch and n_used here,..
1088 (print_insn_z80_buf): ..do it here instead.
1090 2020-01-04 Alan Modra <amodra@gmail.com>
1092 * m32r-ibld.c: Regenerate.
1094 2020-01-04 Alan Modra <amodra@gmail.com>
1096 * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
1098 2020-01-04 Alan Modra <amodra@gmail.com>
1100 * crx-dis.c (match_opcode): Avoid shift left of signed value.
1102 2020-01-04 Alan Modra <amodra@gmail.com>
1104 * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
1106 2020-01-03 Jan Beulich <jbeulich@suse.com>
1108 * aarch64-tbl.h (aarch64_opcode_table): Use
1109 SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
1111 2020-01-03 Jan Beulich <jbeulich@suse.com>
1113 * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
1114 forms of SUDOT and USDOT.
1116 2020-01-03 Jan Beulich <jbeulich@suse.com>
1118 * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
1120 * opcodes/aarch64-dis-2.c: Re-generate.
1122 2020-01-03 Jan Beulich <jbeulich@suse.com>
1124 * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
1126 * opcodes/aarch64-dis-2.c: Re-generate.
1128 2020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com>
1130 * z80-dis.c: Add support for eZ80 and Z80 instructions.
1132 2020-01-01 Alan Modra <amodra@gmail.com>
1134 Update year range in copyright notice of all files.
1136 For older changes see ChangeLog-2019
1138 Copyright (C) 2020 Free Software Foundation, Inc.
1140 Copying and distribution of this file, with or without modification,
1141 are permitted in any medium without royalty provided the copyright
1142 notice and this notice are preserved.
1148 version-control: never