1 2019-12-16 Alan Modra <amodra@gmail.com>
3 * score-dis.c (print_insn_score16): Move rpush/rpop imm field
4 value adjustment so that it doesn't affect reg field too.
6 2019-12-16 Alan Modra <amodra@gmail.com>
8 * crx-dis.c (EXTRACT, SBM): Avoid signed overflow.
9 (get_number_of_operands, getargtype, getbits, getregname),
10 (getcopregname, getprocregname, gettrapstring, getcinvstring),
11 (getregliststring, get_word_at_PC, get_words_at_PC, build_mask),
12 (powerof2, match_opcode, make_instruction, print_arguments),
13 (print_arg): Delete forward declarations, moving static to..
14 (getregname, getcopregname, getregliststring): ..these definitions.
15 (build_mask): Return unsigned int mask.
16 (match_opcode): Use unsigned int vars.
18 2019-12-16 Alan Modra <amodra@gmail.com>
20 * bfin-dis.c (fmtconst, fmtconst_val): Avoid signed overflow.
22 2019-12-16 Alan Modra <amodra@gmail.com>
24 * nds32-dis.c (print_insn16, print_insn32): Remove forward decls.
25 (struct objdump_disasm_info): Delete.
26 (nds32_parse_audio_ext, nds32_parse_opcode): Cast result of
27 N32_IMMS to unsigned before shifting left.
29 2019-12-16 Alan Modra <amodra@gmail.com>
31 * moxie-dis.c (INST2OFFSET): Don't left shift a signed value.
32 (print_insn_moxie): Remove unnecessary cast.
34 2019-12-12 Alan Modra <amodra@gmail.com>
36 * csky-dis.c (csky_chars_to_number): Remove abort and unnecessary
39 2019-12-11 Alan Modra <amodra@gmail.com>
41 * arc-dis.c (BITS): Don't truncate high bits with shifts.
42 * nios2-dis.c (nios2_print_insn_arg): Don't sign extend with shifts.
43 * tic54x-dis.c (print_instruction): Likewise.
44 * tilegx-opc.c (parse_insn_tilegx): Likewise.
45 * tilepro-opc.c (parse_insn_tilepro): Likewise.
46 * visium-dis.c (disassem_class0): Likewise.
47 * pdp11-dis.c (sign_extend): Likewise.
49 * epiphany-ibld.c: Regenerate.
50 * lm32-ibld.c: Regenerate.
51 * m32c-ibld.c: Regenerate.
53 2019-12-11 Alan Modra <amodra@gmail.com>
55 * ns32k-dis.c (sign_extend): Correct last patch.
57 2019-12-11 Alan Modra <amodra@gmail.com>
59 * vax-dis.c (NEXTLONG): Avoid signed overflow.
61 2019-12-11 Alan Modra <amodra@gmail.com>
63 * v850-dis.c (get_operand_value): Use unsigned arithmetic. Don't
64 sign extend using shifts.
66 2019-12-11 Alan Modra <amodra@gmail.com>
68 * tic6x-dis.c (tic6x_extract_32): Avoid signed overflow.
70 2019-12-11 Alan Modra <amodra@gmail.com>
72 * tic4x-dis.c (tic4x_print_register): Formatting. Don't segfault
73 on NULL registertable entry.
74 (tic4x_hash_opcode): Use unsigned arithmetic.
76 2019-12-11 Alan Modra <amodra@gmail.com>
78 * s12z-opc.c (z_decode_signed_value): Avoid signed overflow.
80 2019-12-11 Alan Modra <amodra@gmail.com>
82 * ns32k-dis.c (bit_extract): Use unsigned arithmetic.
83 (bit_extract_simple, sign_extend): Likewise.
85 2019-12-11 Alan Modra <amodra@gmail.com>
87 * nios2-dis.c (nios2_print_insn_arg): Use 1u << 31.
89 2019-12-11 Alan Modra <amodra@gmail.com>
91 * moxie-dis.c (INST2OFFSET): Don't sign extend using shifts.
93 2019-12-11 Alan Modra <amodra@gmail.com>
95 * m68k-dis.c (COERCE32): Cast value first.
96 (NEXTLONG, NEXTULONG): Avoid signed overflow.
98 2019-12-11 Alan Modra <amodra@gmail.com>
100 * h8300-dis.c (extract_immediate): Avoid signed overflow.
101 (bfd_h8_disassemble): Likewise.
103 2019-12-11 Alan Modra <amodra@gmail.com>
105 * d30v-dis.c (print_insn): Make opind unsigned. Don't access
106 past end of operands array.
108 2019-12-11 Alan Modra <amodra@gmail.com>
110 * csky-dis.c (csky_chars_to_number): Rewrite. Avoid signed
111 overflow when collecting bytes of a number.
113 2019-12-11 Alan Modra <amodra@gmail.com>
115 * cris-dis.c (print_with_operands): Avoid signed integer
116 overflow when collecting bytes of a 32-bit integer.
118 2019-12-11 Alan Modra <amodra@gmail.com>
120 * cr16-dis.c (EXTRACT, SBM): Rewrite.
121 (cr16_match_opcode): Delete duplicate bcond test.
123 2019-12-11 Alan Modra <amodra@gmail.com>
125 * bfin-dis.c (HOST_LONG_WORD_SIZE, XFIELD): Delete.
127 (MASKBITS, SIGNEXTEND): Rewrite.
128 (fmtconst): Don't use ? expression now that SIGNEXTEND uses
129 unsigned arithmetic, instead assign result of SIGNEXTEND back
131 (fmtconst_val): Use 1u in shift expression.
133 2019-12-11 Alan Modra <amodra@gmail.com>
135 * arc-dis.c (find_format_from_table): Use ull constant when
136 shifting by up to 32.
138 2019-12-11 Alan Modra <amodra@gmail.com>
141 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Return
142 false when field is zero for sve_size_tsz_bhs.
144 2019-12-11 Alan Modra <amodra@gmail.com>
146 * epiphany-ibld.c: Regenerate.
148 2019-12-10 Alan Modra <amodra@gmail.com>
151 * disassemble.c (disassemble_free_target): New function.
153 2019-12-10 Alan Modra <amodra@gmail.com>
155 * cgen-dis.in (print_insn_@arch@): Replace insn_sets with private_data.
156 * disassemble.c (disassemble_init_for_target): Likewise.
157 * bpf-dis.c: Regenerate.
158 * epiphany-dis.c: Regenerate.
159 * fr30-dis.c: Regenerate.
160 * frv-dis.c: Regenerate.
161 * ip2k-dis.c: Regenerate.
162 * iq2000-dis.c: Regenerate.
163 * lm32-dis.c: Regenerate.
164 * m32c-dis.c: Regenerate.
165 * m32r-dis.c: Regenerate.
166 * mep-dis.c: Regenerate.
167 * mt-dis.c: Regenerate.
168 * or1k-dis.c: Regenerate.
169 * xc16x-dis.c: Regenerate.
170 * xstormy16-dis.c: Regenerate.
172 2019-12-10 Alan Modra <amodra@gmail.com>
174 * ppc-dis.c (private): Delete variable.
175 (get_powerpc_dialect): Don't segfault on NULL info->private_data.
176 (powerpc_init_dialect): Don't use global private.
178 2019-12-10 Alan Modra <amodra@gmail.com>
180 * s12z-opc.c: Formatting.
182 2019-12-08 Alan Modra <amodra@gmail.com>
184 * s12z-opc.c (exg_sex_discrim): Don't leak memory on invalid
187 2019-12-05 Jan Beulich <jbeulich@suse.com>
189 * aarch64-tbl.h (aarch64_feature_crypto,
190 aarch64_feature_crypto_v8_2, CRYPTO, CRYPTO_V8_2, CRYP_INSN,
191 CRYPTO_V8_2_INSN): Delete.
193 2019-12-05 Alan Modra <amodra@gmail.com>
196 * microblaze-dis.c (NUM_STRBUFS, STRBUF_SIZE): Define.
197 (struct string_buf): New.
198 (strbuf): New function.
199 (get_field): Use strbuf rather than strdup of local temp.
200 (get_field_imm, get_field_imm5, get_field_imm5_mbar): Likewise.
201 (get_field_rfsl, get_field_imm15): Likewise.
202 (get_field_rd, get_field_r1, get_field_r2): Update macros.
203 (get_field_special): Likewise. Don't strcpy spr. Formatting.
204 (print_insn_microblaze): Formatting. Init and pass string_buf to
207 2019-12-04 Jan Beulich <jbeulich@suse.com>
209 * i386-opc.tbl (lfs, lgs, lss): Drop No_qSuf.
210 * i386-tbl.h: Re-generate.
212 2019-12-04 Jan Beulich <jbeulich@suse.com>
214 * i386-dis.c (mod_table): Use Ev instead of Em for movdiri.
216 2019-12-04 Jan Beulich <jbeulich@suse.com>
218 * i386-opc.tbl (push, pop): Drop DefaultSize from GPR-only
220 (xbegin): Drop DefaultSize.
221 * i386-tbl.h: Re-generate.
223 2019-11-22 Mihail Ionescu <mihail.ionescu@arm.com>
225 * opcodes/arm-dis.c (arm_opcodes, thumb32_opcodes):
226 Change the coproc CRC conditions to use the extension
227 feature set, second word, base on ARM_EXT2_CRC.
229 2019-11-14 Jan Beulich <jbeulich@suse.com>
231 * i386-opc.tbl (syscall, sysret): Drop Cpu64 forms.
232 * i386-tbl.h: Re-generate.
234 2019-11-14 Jan Beulich <jbeulich@suse.com>
236 * i386-gen.c (opcode_modifiers): Remove JumpDword, JumpByte,
237 JumpInterSegment, and JumpAbsolute entries.
238 * i386-opc.h (JUMP, JUMP_DWORD, JUMP_BYTE, JUMP_INTERSEGMENT,
239 JUMP_ABSOLUTE): Define.
240 (struct i386_opcode_modifier): Extend jump field to 3 bits.
241 Remove jumpdword, jumpbyte, jumpintersegment, and jumpabsolute
243 * i386-opc.tbl (JumpByte, JumpDword, JumpAbsolute,
244 JumpInterSegment): Define.
245 * i386-tbl.h: Re-generate.
247 2019-11-14 Jan Beulich <jbeulich@suse.com>
249 * i386-gen.c (operand_type_init): Remove
250 OPERAND_TYPE_JUMPABSOLUTE entry.
251 (opcode_modifiers): Add JumpAbsolute entry.
252 (operand_types): Remove JumpAbsolute entry.
253 * i386-opc.h (JumpAbsolute): Move between enums.
254 (struct i386_opcode_modifier): Add jumpabsolute field.
255 (union i386_operand_type): Remove jumpabsolute field.
256 * i386-opc.tbl (call, lcall, jmp, ljmp): Move JumpAbsolute.
257 * i386-init.h, i386-tbl.h: Re-generate.
259 2019-11-14 Jan Beulich <jbeulich@suse.com>
261 * i386-gen.c (opcode_modifiers): Add AnySize entry.
262 (operand_types): Remove AnySize entry.
263 * i386-opc.h (AnySize): Move between enums.
264 (struct i386_opcode_modifier): Add anysize field.
265 (OTUnused): Un-comment.
266 (union i386_operand_type): Remove anysize field.
267 * i386-opc.tbl (lea, invlpg, clflush, prefetchnta, prefetcht0,
268 prefetcht1, prefetcht2, prefetchtw, bndmk, bndcl, bndcu, bndcn,
269 bndstx, bndldx, prefetchwt1, clflushopt, clwb, cldemote): Move
271 * i386-tbl.h: Re-generate.
273 2019-11-12 Nelson Chu <nelson.chu@sifive.com>
275 * riscv-opc.c (riscv_insn_types): Replace the INSN_CLASS_I with
276 INSN_CLASS_F and the INSN_CLASS_C with INSN_CLASS_F_AND_C if we
277 use the floating point register (FPR).
279 2019-11-12 Mihail Ionescu <mihail.ionescu@arm.com>
281 * opcodes/arm-dis.c (mve_opcodes): Enable VMOV imm to vec with
283 (is_mve_encoding_conflict): Update cmode conflict checks for
286 2019-11-12 Jan Beulich <jbeulich@suse.com>
288 * i386-gen.c (operand_type_init): Remove OPERAND_TYPE_ESSEG
290 (operand_types): Remove EsSeg entry.
291 (main): Replace stale use of OTMax.
292 * i386-opc.h (IS_STRING_ES_OP0, IS_STRING_ES_OP1): Define.
293 (struct i386_opcode_modifier): Expand isstring field to 2 bits.
295 (OTUnused): Comment out.
296 (union i386_operand_type): Remove esseg field.
297 * i386-opc.tbl (IsStringEsOp0, IsStringEsOp1): Define.
298 (cmps, scmp, scas, ssca, cmpsd): Add IsStringEsOp0.
299 (ins, movs, smov, movsd): Add IsStringEsOpOp1.
300 (stos, ssto): Add IsStringEsOp0/IsStringEsOpOp1.
301 * i386-init.h, i386-tbl.h: Re-generate.
303 2019-11-12 Jan Beulich <jbeulich@suse.com>
305 * i386-gen.c (operand_instances): Add RegB entry.
306 * i386-opc.h (enum operand_instance): Add RegB.
307 * i386-opc.tbl (RegC, RegD, RegB): Define.
308 (Acc, ShiftCount, InOutPortReg): Adjust definitions.
309 (monitor, mwait, invlpga, skinit, vmload, vmrun, vmsave, clzero,
310 monitorx, mwaitx): Drop ImmExt and convert encodings
312 * i386-reg.tbl (ecx, rcx): Add Instance=RegC.
313 (edx, rdx): Add Instance=RegD.
314 (ebx, rbx): Add Instance=RegB.
315 * i386-tbl.h: Re-generate.
317 2019-11-12 Jan Beulich <jbeulich@suse.com>
319 * i386-gen.c (operand_type_init): Adjust
320 OPERAND_TYPE_INOUTPORTREG, OPERAND_TYPE_SHIFTCOUNT,
321 OPERAND_TYPE_FLOATACC, OPERAND_TYPE_ACC8, OPERAND_TYPE_ACC16,
322 OPERAND_TYPE_ACC32, and OPERAND_TYPE_ACC64 entries.
323 (operand_instances): New.
324 (operand_types): Drop InOutPortReg, ShiftCount, and Acc entries.
325 (output_operand_type): New parameter "instance". Process it.
326 (process_i386_operand_type): New local variable "instance".
327 (main): Adjust static assertions.
328 * i386-opc.h (INSTANCE_WIDTH): Define.
329 (enum operand_instance): New.
330 (Acc, InOutPortReg, ShiftCount): Replace by ClassInstance.
331 (union i386_operand_type): Replace acc, inoutportreg, and
332 shiftcount by instance.
333 * i386-opc.tbl (Acc, InOutPortReg, ShiftCount): Define.
334 * i386-reg.tbl (st, al, cl, ax, dx, eax, rax, xmm0, st(0)):
336 * i386-init.h, i386-tbl.h: Re-generate.
338 2019-11-11 Jan Beulich <jbeulich@suse.com>
340 * aarch64-tbl.h (aarch64_opcode_table): Switch SVE2's
341 smaxp/sminp entries' "tied_operand" field to 2.
343 2019-11-11 Jan Beulich <jbeulich@suse.com>
345 * aarch64-opc.c (operand_general_constraint_met_p): Replace
346 "index" local variable by that of the already existing "num".
348 2019-11-08 H.J. Lu <hongjiu.lu@intel.com>
351 * i386-opc.tbl: Remove IgnoreSize from cmpsd and movsd.
352 * i386-tbl.h: Regenerated.
354 2019-11-08 Jan Beulich <jbeulich@suse.com>
356 * i386-gen.c (operand_type_init): Add Class= to
357 OPERAND_TYPE_REGMASK and OPERAND_TYPE_REGBND entries. Move up
358 OPERAND_TYPE_REGBND entry.
359 (operand_classes): Add RegMask and RegBND entries.
360 (operand_types): Drop RegMask and RegBND entry.
361 * i386-opc.h (enum operand_class): Add RegMask and RegBND.
362 (RegMask, RegBND): Delete.
363 (union i386_operand_type): Remove regmask and regbnd fields.
364 * i386-opc.tbl (RegMask, RegBND): Define.
365 * i386-reg.tbl: Replace RegMask by Class=RegMask and RegBND by
367 * i386-init.h, i386-tbl.h: Re-generate.
369 2019-11-08 Jan Beulich <jbeulich@suse.com>
371 * i386-gen.c (operand_type_init): Add Class= to
372 OPERAND_TYPE_REGMMX, OPERAND_TYPE_REGXMM, OPERAND_TYPE_REGYMM, and
373 OPERAND_TYPE_REGZMM entries.
374 (operand_classes): Add RegMMX and RegSIMD entries.
375 (operand_types): Drop RegMMX and RegSIMD entries.
376 * i386-opc.h (enum operand_class): Add RegMMX and RegSIMD.
377 (RegMMX, RegSIMD): Delete.
378 (union i386_operand_type): Remove regmmx and regsimd fields.
379 * i386-opc.tbl (RegMMX): Define.
380 (RegXMM, RegYMM, RegZMM): Add Class=.
381 * i386-reg.tbl: Replace RegMMX by Class=RegMMX and RegSIMD by
383 * i386-init.h, i386-tbl.h: Re-generate.
385 2019-11-08 Jan Beulich <jbeulich@suse.com>
387 * i386-gen.c (operand_type_init): Add Class= to
388 OPERAND_TYPE_CONTROL, OPERAND_TYPE_TEST, and OPERAND_TYPE_DEBUG
390 (operand_classes): Add RegCR, RegDR, and RegTR entries.
391 (operand_types): Drop Control, Debug, and Test entries.
392 * i386-opc.h (enum operand_class): Add RegCR, RegDR, and RegTR.
393 (Control, Debug, Test): Delete.
394 (union i386_operand_type): Remove control, debug, and test
396 * i386-opc.tbl (Control, Debug, Test): Define.
397 * i386-reg.tbl: Replace Control by Class=RegCR, Debug by
398 Class=RegDR, and Test by Class=RegTR.
399 * i386-init.h, i386-tbl.h: Re-generate.
401 2019-11-08 Jan Beulich <jbeulich@suse.com>
403 * i386-gen.c (operand_type_init): Add Class= to
404 OPERAND_TYPE_SREG entry.
405 (operand_classes): Add SReg entry.
406 (operand_types): Drop SReg entry.
407 * i386-opc.h (enum operand_class): Add SReg.
409 (union i386_operand_type): Remove sreg field.
410 * i386-opc.tbl (SReg): Define.
411 * i386-reg.tbl: Replace SReg by Class=SReg.
412 * i386-init.h, i386-tbl.h: Re-generate.
414 2019-11-08 Jan Beulich <jbeulich@suse.com>
416 * i386-gen.c (operand_type_init): Add Class=. New
417 OPERAND_TYPE_ANYIMM entry.
418 (operand_classes): New.
419 (operand_types): Drop Reg entry.
420 (output_operand_type): New parameter "class". Process it.
421 (process_i386_operand_type): New local variable "class".
422 (main): Adjust static assertions.
423 * i386-opc.h (CLASS_WIDTH): Define.
424 (enum operand_class): New.
425 (Reg): Replace by Class. Adjust comment.
426 (union i386_operand_type): Replace reg by class.
427 * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatReg): Add
429 * i386-reg.tbl: Replace Reg by Class=Reg.
430 * i386-init.h: Re-generate.
432 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
434 * opcodes/aarch64-tbl.h (V8_6_INSN): New macro for v8.6 instructions.
435 (aarch64_opcode_table): Add data gathering hint mnemonic.
436 * opcodes/aarch64-dis-2.c: Account for new instruction.
438 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
440 * arm-dis.c (neon_opcodes): Add i8mm SIMD instructions.
443 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
445 * aarch64-tbl.h (aarch64_feature_i8mm_sve, aarch64_feature_f32mm_sve,
446 aarch64_feature_f64mm_sve, aarch64_feature_i8mm, aarch64_feature_f32mm,
447 aarch64_feature_f64mm): New feature sets.
448 (INT8MATMUL_INSN, F64MATMUL_SVE_INSN, F64MATMUL_INSN,
449 F32MATMUL_SVE_INSN, F32MATMUL_INSN): New macros to define matrix multiply
451 (I8MM_SVE, F32MM_SVE, F64MM_SVE, I8MM, F32MM, F64MM): New feature set
453 (QL_MMLA64, OP_SVE_SBB): New qualifiers.
454 (OP_SVE_QQQ): New qualifier.
455 (INT8MATMUL_SVE_INSNC, F64MATMUL_SVE_INSNC,
456 F32MATMUL_SVE_INSNC): New feature set for bfloat16 instructions to support
457 the movprfx constraint.
458 (aarch64_opcode_table): Support for SVE_ADDR_RI_S4x32.
459 (aarch64_opcode_table): Define new instructions smmla,
460 ummla, usmmla, usdot, sudot, fmmla, ld1rob, ld1roh, ld1row, ld1rod,
462 * aarch64-opc.c (operand_general_constraint_met_p): Handle
463 AARCH64_OPND_SVE_ADDR_RI_S4x32.
464 (aarch64_print_operand): Handle AARCH64_OPND_SVE_ADDR_RI_S4x32.
465 * aarch64-dis-2.c (aarch64_opcode_lookup_1, aarch64_find_next_opcode):
466 Account for new instructions.
467 * opcodes/aarch64-asm-2.c (aarch64_insert_operand): Support the new
469 * aarch64-opc-2.c (aarch64_operands): Support the new S4x32 operand.
471 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
472 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
474 * arm-dis.c (select_arm_features): Update bfd_march_arm_8 with
476 (coprocessor_opcodes): Add bfloat16 vcvt{t,b}.
477 (neon_opcodes): Add bfloat SIMD instructions.
478 (print_insn_coprocessor): Add new control character %b to print
479 condition code without checking cp_num.
480 (print_insn_neon): Account for BFloat16 instructions that have no
481 special top-byte handling.
483 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
484 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
486 * arm-dis.c (print_insn_coprocessor,
487 print_insn_generic_coprocessor): Create wrapper functions around
488 the implementation of the print_insn_coprocessor control codes.
489 (print_insn_coprocessor_1): Original print_insn_coprocessor
490 function that now takes which array to look at as an argument.
491 (print_insn_arm): Use both print_insn_coprocessor and
492 print_insn_generic_coprocessor.
493 (print_insn_thumb32): As above.
495 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
496 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
498 * aarch64-asm.c (aarch64_ins_reglane): Use AARCH64_OPND_QLF_S_2H
499 in reglane special case.
500 * aarch64-dis-2.c (aarch64_opcode_lookup_1,
501 aarch64_find_next_opcode): Account for new instructions.
502 * aarch64-dis.c (aarch64_ext_reglane): Use AARCH64_OPND_QLF_S_2H
503 in reglane special case.
504 * aarch64-opc.c (struct operand_qualifier_data): Add data for
505 new AARCH64_OPND_QLF_S_2H qualifier.
506 * aarch64-tbl.h (QL_BFDOT QL_BFDOT64, QL_BFDOT64I, QL_BFMMLA2,
507 QL_BFCVT64, QL_BFCVTN64, QL_BFCVTN2_64): New qualifiers.
508 (aarch64_feature_bfloat16, aarch64_feature_bfloat16_sve): New feature
510 (BFLOAT_SVE, BFLOAT): New feature set macros.
511 (BFLOAT_SVE_INSN, BFLOAT_INSN): New macros to define BFloat16
513 (aarch64_opcode_table): Define new instructions bfdot,
514 bfmmla, bfcvt, bfcvtnt, bfdot, bfdot, bfcvtn, bfmlal[b/t]
517 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
518 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
520 * aarch64-tbl.h (ARMV8_6): New macro.
522 2019-11-07 Jan Beulich <jbeulich@suse.com>
524 * i386-dis.c (prefix_table): Add mcommit.
525 (rm_table): Add rdpru.
526 * i386-gen.c (cpu_flag_init): Adjust CPU_ZNVER2_FLAGS entry. Add
527 CPU_RDPRU_FLAGS and CPU_MCOMMIT_FLAGS entries.
528 (cpu_flags): Add CpuRDPRU and CpuMCOMMIT entries.
529 * i386-opc.h (CpuRDPRU, CpuMCOMMIT): New.
530 (union i386_cpu_flags): Add cpurdpru and cpumcommit fields.
531 * i386-opc.tbl (mcommit, rdpru): New.
532 * i386-init.h, i386-tbl.h: Re-generate.
534 2019-11-07 Jan Beulich <jbeulich@suse.com>
536 * i386-dis.c (OP_Mwait): Drop local variable "names", use
538 (OP_Monitor): Drop local variable "op1_names", re-purpose
539 "names" for it instead, and replace former "names" uses by
542 2019-11-07 Jan Beulich <jbeulich@suse.com>
545 * opcodes/i386-opc.tbl (movsd, cmpsd): Drop IgnoreSize from
547 * opcodes/i386-tbl.h: Re-generate.
549 2019-11-05 Jan Beulich <jbeulich@suse.com>
551 * i386-dis.c (OP_Mwaitx): Delete.
552 (prefix_table): Use OP_Mwait for mwaitx entry.
553 (OP_Mwait): Also handle mwaitx.
555 2019-11-05 Jan Beulich <jbeulich@suse.com>
557 * i386-dis.c (PREFIX_0F01_REG_7_MOD_3_RM_2,
558 PREFIX_0F01_REG_7_MOD_3_RM_3): New.
559 (prefix_table): Add respective entries.
560 (rm_table): Link to those entries.
562 2019-11-05 Jan Beulich <jbeulich@suse.com>
564 * i386-dis.c (REG_0F1C_MOD_0): Rename to ...
565 (REG_0F1C_P_0_MOD_0): ... this.
566 (REG_0F1E_MOD_3): Rename to ...
567 (REG_0F1E_P_1_MOD_3): ... this.
568 (RM_0F01_REG_5): Rename to ...
569 (RM_0F01_REG_5_MOD_3): ... this.
570 (RM_0F01_REG_7): Rename to ...
571 (RM_0F01_REG_7_MOD_3): ... this.
572 (RM_0F1E_MOD_3_REG_7): Rename to ...
573 (RM_0F1E_P_1_MOD_3_REG_7): ... this.
574 (RM_0FAE_REG_6): Rename to ...
575 (RM_0FAE_REG_6_MOD_3_P_0): ... this.
576 (RM_0FAE_REG_7): Rename to ...
577 (RM_0FAE_REG_7_MOD_3): ... this.
578 (PREFIX_MOD_0_0F01_REG_5): Rename to ...
579 (PREFIX_0F01_REG_5_MOD_0): ... this.
580 (PREFIX_MOD_3_0F01_REG_5_RM_0): Rename to ...
581 (PREFIX_0F01_REG_5_MOD_3_RM_0): ... this.
582 (PREFIX_MOD_3_0F01_REG_5_RM_2): Rename to ...
583 (PREFIX_0F01_REG_5_MOD_3_RM_2): ... this.
584 (PREFIX_0FAE_REG_0): Rename to ...
585 (PREFIX_0FAE_REG_0_MOD_3): ... this.
586 (PREFIX_0FAE_REG_1): Rename to ...
587 (PREFIX_0FAE_REG_1_MOD_3): ... this.
588 (PREFIX_0FAE_REG_2): Rename to ...
589 (PREFIX_0FAE_REG_2_MOD_3): ... this.
590 (PREFIX_0FAE_REG_3): Rename to ...
591 (PREFIX_0FAE_REG_3_MOD_3): ... this.
592 (PREFIX_MOD_0_0FAE_REG_4): Rename to ...
593 (PREFIX_0FAE_REG_4_MOD_0): ... this.
594 (PREFIX_MOD_3_0FAE_REG_4): Rename to ...
595 (PREFIX_0FAE_REG_4_MOD_3): ... this.
596 (PREFIX_MOD_0_0FAE_REG_5): Rename to ...
597 (PREFIX_0FAE_REG_5_MOD_0): ... this.
598 (PREFIX_MOD_3_0FAE_REG_5): Rename to ...
599 (PREFIX_0FAE_REG_5_MOD_3): ... this.
600 (PREFIX_MOD_0_0FAE_REG_6): Rename to ...
601 (PREFIX_0FAE_REG_6_MOD_0): ... this.
602 (PREFIX_MOD_1_0FAE_REG_6): Rename to ...
603 (PREFIX_0FAE_REG_6_MOD_3): ... this.
604 (PREFIX_0FAE_REG_7): Rename to ...
605 (PREFIX_0FAE_REG_7_MOD_0): ... this.
606 (PREFIX_MOD_0_0FC3): Rename to ...
607 (PREFIX_0FC3_MOD_0): ... this.
608 (PREFIX_MOD_0_0FC7_REG_6): Rename to ...
609 (PREFIX_0FC7_REG_6_MOD_0): ... this.
610 (PREFIX_MOD_3_0FC7_REG_6): Rename to ...
611 (PREFIX_0FC7_REG_6_MOD_3): ... this.
612 (PREFIX_MOD_3_0FC7_REG_7): Rename to ...
613 (PREFIX_0FC7_REG_7_MOD_3): ... this.
614 (reg_table, prefix_table, mod_table, rm_table): Adjust
617 2019-11-04 Nick Clifton <nickc@redhat.com>
619 * v850-dis.c (get_v850_sreg_name): New function. Returns the name
620 of a v850 system register. Move the v850_sreg_names array into
622 (get_v850_reg_name): Likewise for ordinary register names.
623 (get_v850_vreg_name): Likewise for vector register names.
624 (get_v850_cc_name): Likewise for condition codes.
625 * get_v850_float_cc_name): Likewise for floating point condition
627 (get_v850_cacheop_name): Likewise for cache-ops.
628 (get_v850_prefop_name): Likewise for pref-ops.
629 (disassemble): Use the new accessor functions.
631 2019-10-30 Delia Burduv <delia.burduv@arm.com>
633 * aarch64-opc.c (print_immediate_offset_address): Don't print the
634 immediate for the writeback form of ldraa/ldrab if it is 0.
635 * aarch64-tbl.h: Updated the documentation for ADDR_SIMM10.
636 * aarch64-opc-2.c: Regenerated.
638 2019-10-30 Jan Beulich <jbeulich@suse.com>
640 * i386-gen.c (operand_type_shorthands): Delete.
641 (operand_type_init): Expand previous shorthands.
642 (set_bitfield_from_shorthand): Rename back to ...
643 (set_bitfield_from_cpu_flag_init): ... this. Drop processing
644 of operand_type_init[].
645 (set_bitfield): Adjust call to the above function.
646 * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatAcc, FloatReg,
647 RegXMM, RegYMM, RegZMM): Define.
648 * i386-reg.tbl: Expand prior shorthands.
650 2019-10-30 Jan Beulich <jbeulich@suse.com>
652 * i386-gen.c (output_i386_opcode): Change order of fields
654 * i386-opc.h (struct insn_template): Move operands field.
655 Convert extension_opcode field to unsigned short.
656 * i386-tbl.h: Re-generate.
658 2019-10-30 Jan Beulich <jbeulich@suse.com>
660 * i386-gen.c (process_i386_opcode_modifier): Report bogus uses
662 * i386-opc.h (W): Extend comment.
663 * i386-opc.tbl (mov, movabs, movq): Drop W and adjust opcodes of
664 general purpose variants not allowing for byte operands.
665 * i386-tbl.h: Re-generate.
667 2019-10-29 Nick Clifton <nickc@redhat.com>
669 * tic30-dis.c (print_branch): Correct size of operand array.
671 2019-10-29 Nick Clifton <nickc@redhat.com>
673 * d30v-dis.c (print_insn): Check that operand index is valid
674 before attempting to access the operands array.
676 2019-10-29 Nick Clifton <nickc@redhat.com>
678 * ia64-opc.c (locate_opcode_ent): Prevent a negative shift when
679 locating the bit to be tested.
681 2019-10-29 Nick Clifton <nickc@redhat.com>
683 * s12z-dis.c (opr_emit_disassembly): Check for illegal register
685 (shift_size_table): Use a fixed size defined as S12Z_N_SIZES.
686 (print_insn_s12z): Check for illegal size values.
688 2019-10-28 Nick Clifton <nickc@redhat.com>
690 * csky-dis.c (csky_chars_to_number): Check for a negative
691 count. Use an unsigned integer to construct the return value.
693 2019-10-28 Nick Clifton <nickc@redhat.com>
695 * tic30-dis.c (OPERAND_BUFFER_LEN): Define. Use as length of
696 operand buffer. Set value to 15 not 13.
697 (get_register_operand): Use OPERAND_BUFFER_LEN.
698 (get_indirect_operand): Likewise.
699 (print_two_operand): Likewise.
700 (print_three_operand): Likewise.
701 (print_oar_insn): Likewise.
703 2019-10-28 Nick Clifton <nickc@redhat.com>
705 * ns32k-dis.c (bit_extract): Add sanitiy check of parameters.
706 (bit_extract_simple): Likewise.
707 (bit_copy): Likewise.
708 (pirnt_insn_ns32k): Ensure that uninitialised elements in the
709 index_offset array are not accessed.
711 2019-10-28 Nick Clifton <nickc@redhat.com>
713 * xgate-dis.c (print_insn): Fix decoding of the XGATE_OP_DYA
716 2019-10-25 Nick Clifton <nickc@redhat.com>
718 * rx-dis.c (print_insn_rx): Use parenthesis to ensure correct
719 access to opcodes.op array element.
721 2019-10-23 Nick Clifton <nickc@redhat.com>
723 * rx-dis.c (get_register_name): Fix spelling typo in error
725 (get_condition_name, get_flag_name, get_double_register_name)
726 (get_double_register_high_name, get_double_register_low_name)
727 (get_double_control_register_name, get_double_condition_name)
728 (get_opsize_name, get_size_name): Likewise.
730 2019-10-22 Nick Clifton <nickc@redhat.com>
732 * rx-dis.c (get_size_name): New function. Provides safe
733 access to name array.
734 (get_opsize_name): Likewise.
735 (print_insn_rx): Use the accessor functions.
737 2019-10-16 Nick Clifton <nickc@redhat.com>
739 * rx-dis.c (get_register_name): New function. Provides safe
740 access to name array.
741 (get_condition_name, get_flag_name, get_double_register_name)
742 (get_double_register_high_name, get_double_register_low_name)
743 (get_double_control_register_name, get_double_condition_name):
745 (print_insn_rx): Use the accessor functions.
747 2019-10-09 Nick Clifton <nickc@redhat.com>
750 * avr-dis.c (avr_operand): Fix construction of address for lds/sts
753 2019-10-07 Jan Beulich <jbeulich@suse.com>
755 * opcodes/i386-opc.tbl (movsd): Add Dword and IgnoreSize.
756 (cmpsd): Likewise. Move EsSeg to other operand.
757 * opcodes/i386-tbl.h: Re-generate.
759 2019-09-23 Alan Modra <amodra@gmail.com>
761 * m68k-dis.c: Include cpu-m68k.h
763 2019-09-23 Alan Modra <amodra@gmail.com>
765 * mips-dis.c: Include elfxx-mips.h. Move "elf-bfd.h" and
766 "elf/mips.h" earlier.
768 2018-09-20 Jan Beulich <jbeulich@suse.com>
771 * i386-opc.tbl (push, pop): Re-instate distinct Cpu64 templates
773 * i386-tbl.h: Re-generate.
775 2019-09-18 Alan Modra <amodra@gmail.com>
777 * arc-ext.c: Update throughout for bfd section macro changes.
779 2019-09-18 Simon Marchi <simon.marchi@polymtl.ca>
781 * Makefile.in: Re-generate.
782 * configure: Re-generate.
784 2019-09-17 Maxim Blinov <maxim.blinov@embecosm.com>
786 * riscv-opc.c (riscv_opcodes): Change subset field
787 to insn_class field for all instructions.
788 (riscv_insn_types): Likewise.
790 2019-09-16 Phil Blundell <pb@pbcl.net>
792 * configure: Regenerated.
794 2019-09-10 Miod Vallat <miod@online.fr>
797 * m68k-opc.c: Correct aliases for tdivsl and tdivul.
799 2019-09-09 Phil Blundell <pb@pbcl.net>
801 binutils 2.33 branch created.
803 2019-09-03 Nick Clifton <nickc@redhat.com>
806 * tic30-dis.c (get_indirect_operand): Check for bufcnt being
807 greater than zero before indexing via (bufcnt -1).
809 2019-09-03 Nick Clifton <nickc@redhat.com>
812 * mmix-dis.c (MAX_REG_NAME_LEN): Define.
813 (MAX_SPEC_REG_NAME_LEN): Define.
814 (struct mmix_dis_info): Use defined constants for array lengths.
815 (get_reg_name): New function.
816 (get_sprec_reg_name): New function.
817 (print_insn_mmix): Use new functions.
819 2019-08-27 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
821 * arm-dis.c (mve_opcodes): Add entry for MVE_VMOV_VEC_TO_VEC.
822 (is_mve_undefined): Add case for MVE_VMOV_VEC_TO_VEC.
823 (print_insn_mve): Add condition to check Qm==Qn of VORR instruction.
825 2019-08-22 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
827 * aarch64-opc.c (aarch64_sys_regs): Update encoding of tfsre0_el1,
828 tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12.
829 (aarch64_sys_reg_supported_p): Update checks for the above.
831 2019-08-12 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
833 * arm-dis.c (struct mopcode32 mve_opcodes): Modify the mask for
834 cases MVE_SQRSHRL and MVE_UQRSHLL.
835 (print_insn_mve): Add case for specifier 'k' to check
836 specific bit of the instruction.
838 2019-08-07 Phillipe Antoine <p.antoine@catenacyber.fr>
841 * arc-dis.c (arc_insn_length): Return 0 rather than aborting when
842 encountering an unknown machine type.
843 (print_insn_arc): Handle arc_insn_length returning 0. In error
844 cases return -1 rather than calling abort.
846 2019-08-07 Jan Beulich <jbeulich@suse.com>
848 * i386-opc.tbl (fld, fstp): Drop FloatMF from extended forms.
849 (fldcw, fnstcw, fstcw, fnstsw, fstsw): Replace FloatMF by
851 * i386-tbl.h: Re-generate.
853 2019-08-05 Barnaby Wilks <barnaby.wilks@arm.com>
855 * arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH
858 2019-07-30 Mel Chen <mel.chen@sifive.com>
860 * riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm,
861 fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions.
863 * riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr,
866 2019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
868 * arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes,
869 and MPY class instructions.
870 (parse_option): Add nps400 option.
871 (print_arc_disassembler_options): Add nps400 info.
873 2019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
875 * arc-ext-tbl.h (bspeek): Remove it, added to main table.
878 * arc-opc.c (RAD_CHK): Add.
879 * arc-tbl.h: Regenerate.
881 2019-07-23 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
883 * aarch64-opc.c (aarch64_sys_regs): Add gmid_el1 entry.
884 (aarch64_sys_reg_supported_p): Handle gmid_el1 encoding.
886 2019-07-22 Barnaby Wilks <barnaby.wilks@arm.com>
888 * arm-dis.c (is_mve_unpredictable): Stop marking some MVE
889 instructions as UNPREDICTABLE.
891 2019-07-19 Jose E. Marchesi <jose.marchesi@oracle.com>
893 * bpf-desc.c: Regenerated.
895 2019-07-17 Jan Beulich <jbeulich@suse.com>
897 * i386-gen.c (static_assert): Define.
899 * i386-opc.h (Opcode_Modifier_Max): Rename to ...
900 (Opcode_Modifier_Num): ... this.
903 2019-07-16 Jan Beulich <jbeulich@suse.com>
905 * i386-gen.c (operand_types): Move RegMem ...
906 (opcode_modifiers): ... here.
907 * i386-opc.h (RegMem): Move to opcode modifer enum.
908 (union i386_operand_type): Move regmem field ...
909 (struct i386_opcode_modifier): ... here.
910 * i386-opc.tbl (RegMem): Define.
911 (mov, movq): Move RegMem on segment, control, debug, and test
913 (pextrb): Move RegMem on register only flavors. Add IgnoreSize
914 to non-SSE2AVX flavor.
915 (extractps, pextrw, vcvtps2ph, vextractps, vpextrb, vpextrw):
916 Move RegMem on register only flavors. Drop IgnoreSize from
917 legacy encoding flavors.
918 (movss, movsd, vmovss, vmovsd): Drop RegMem from register only
920 (vpinsrb, vpinsrw): Drop IgnoreSize where still present on
921 register only flavors.
922 (vmovd): Move RegMem and drop IgnoreSize on register only
923 flavor. Change opcode and operand order to store form.
924 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
926 2019-07-16 Jan Beulich <jbeulich@suse.com>
928 * i386-gen.c (operand_type_init, operand_types): Replace SReg
930 * i386-opc.h (SReg2, SReg3): Replace by ...
932 (union i386_operand_type): Replace sreg fields.
933 * i386-opc.tbl (mov, ): Use SReg.
934 (push, pop): Likewies. Drop i386 and x86-64 specific segment
936 * i386-reg.tbl (cs, ds, es, fs, gs, ss, flat): Use SReg.
937 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
939 2019-07-15 Jose E. Marchesi <jose.marchesi@oracle.com>
941 * bpf-desc.c: Regenerate.
942 * bpf-opc.c: Likewise.
943 * bpf-opc.h: Likewise.
945 2019-07-14 Jose E. Marchesi <jose.marchesi@oracle.com>
947 * bpf-desc.c: Regenerate.
948 * bpf-opc.c: Likewise.
950 2019-07-10 Hans-Peter Nilsson <hp@bitrange.com>
952 * arm-dis.c (print_insn_coprocessor): Rename index to
955 2019-07-05 Kito Cheng <kito.cheng@sifive.com>
957 * riscv-opc.c (riscv_insn_types): Add r4 type.
959 * riscv-opc.c (riscv_insn_types): Add b and j type.
961 * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
962 format for sb type and correct s type.
964 2019-07-02 Richard Sandiford <richard.sandiford@arm.com>
966 * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
967 SVE FMOV alias of FCPY.
969 2019-07-02 Richard Sandiford <richard.sandiford@arm.com>
971 * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
972 to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
974 2019-07-02 Richard Sandiford <richard.sandiford@arm.com>
976 * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
977 registers in an instruction prefixed by MOVPRFX.
979 2019-07-01 Matthew Malcomson <matthew.malcomson@arm.com>
981 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
982 sve_size_13 icode to account for variant behaviour of
984 * aarch64-dis-2.c: Regenerate.
985 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
986 sve_size_13 icode to account for variant behaviour of
988 * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
989 (OP_SVE_VVV_Q_D): Add new qualifier.
990 (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
991 (struct aarch64_opcode): Split pmull{t,b} into those requiring
994 2019-07-01 Jan Beulich <jbeulich@suse.com>
996 * opcodes/i386-gen.c (operand_type_init): Remove
997 OPERAND_TYPE_VEC_IMM4 entry.
998 (operand_types): Remove Vec_Imm4.
999 * opcodes/i386-opc.h (Vec_Imm4): Delete.
1000 (union i386_operand_type): Remove vec_imm4.
1001 * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
1002 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
1004 2019-07-01 Jan Beulich <jbeulich@suse.com>
1006 * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
1007 vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
1008 rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
1009 vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
1010 xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
1011 monitorx, mwaitx): Drop ImmExt from operand-less forms.
1012 * i386-tbl.h: Re-generate.
1014 2019-07-01 Jan Beulich <jbeulich@suse.com>
1016 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
1018 * i386-tbl.h: Re-generate.
1020 2019-07-01 Jan Beulich <jbeulich@suse.com>
1022 * i386-opc.tbl (C): New.
1023 (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
1024 pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
1025 por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
1026 cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
1027 pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
1028 cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
1029 cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
1030 vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
1031 vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
1032 vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
1033 vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
1034 vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
1035 vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
1036 vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
1037 vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
1038 vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
1039 vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
1040 vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
1041 vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
1042 vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
1043 vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
1044 vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
1045 vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
1046 vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
1047 vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
1048 vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
1050 * i386-tbl.h: Re-generate.
1052 2019-07-01 Jan Beulich <jbeulich@suse.com>
1054 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
1056 * i386-tbl.h: Re-generate.
1058 2019-07-01 Jan Beulich <jbeulich@suse.com>
1060 * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
1061 * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
1062 vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
1063 * i386-tbl.h: Re-generate.
1065 2019-07-01 Jan Beulich <jbeulich@suse.com>
1067 * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
1068 Disp8MemShift from register only templates.
1069 * i386-tbl.h: Re-generate.
1071 2019-07-01 Jan Beulich <jbeulich@suse.com>
1073 * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
1074 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
1075 MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
1076 EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
1077 EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
1078 EVEX_W_0F11_P_3_M_1): Delete.
1079 (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
1080 EVEX_W_0F11_P_3): New.
1081 * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
1082 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
1083 MOD_EVEX_0F11_PREFIX_3 table entries.
1084 * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
1085 PREFIX_EVEX_0F11 table entries.
1086 * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
1087 EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
1088 EVEX_W_0F11_P_3_M_{0,1} table entries.
1090 2019-07-01 Jan Beulich <jbeulich@suse.com>
1092 * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
1095 2019-06-27 H.J. Lu <hongjiu.lu@intel.com>
1098 * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
1099 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
1100 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
1101 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
1102 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
1103 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
1104 EVEX_LEN_0F38C7_R_6_P_2_W_1.
1105 * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
1106 PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
1107 PREFIX_EVEX_0F38C6_REG_6 entries.
1108 * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
1109 EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
1110 EVEX_W_0F38C7_R_6_P_2 entries.
1111 * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
1112 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
1113 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
1114 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
1115 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
1116 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
1117 EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
1119 2019-06-27 Jan Beulich <jbeulich@suse.com>
1121 * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
1122 VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
1123 VEX_LEN_0F2D_P_3): Delete.
1124 (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
1125 vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
1126 (prefix_table): ... here.
1128 2019-06-27 Jan Beulich <jbeulich@suse.com>
1130 * i386-dis.c (Iq): Delete.
1132 (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
1134 (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
1135 vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
1136 (OP_E_memory): Also honor needindex when deciding whether an
1137 address size prefix needs printing.
1138 (OP_I): Remove handling of q_mode. Add handling of d_mode.
1140 2019-06-26 Jim Wilson <jimw@sifive.com>
1143 * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
1144 Set info->display_endian to info->endian_code.
1146 2019-06-25 Jan Beulich <jbeulich@suse.com>
1148 * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
1149 entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
1150 OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
1151 OPERAND_TYPE_ACC64 entries.
1152 * i386-init.h: Re-generate.
1154 2019-06-25 Jan Beulich <jbeulich@suse.com>
1156 * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
1158 (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
1160 * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
1162 * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
1163 entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
1165 2019-06-25 Jan Beulich <jbeulich@suse.com>
1167 * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
1170 2019-06-25 Jan Beulich <jbeulich@suse.com>
1172 * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
1173 Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
1175 * i386-opc.tbl (movnti): Add IgnoreSize.
1176 * i386-tbl.h: Re-generate.
1178 2019-06-25 Jan Beulich <jbeulich@suse.com>
1180 * i386-opc.tbl (and): Mark Imm8S form for optimization.
1181 * i386-tbl.h: Re-generate.
1183 2019-06-21 H.J. Lu <hongjiu.lu@intel.com>
1185 * i386-dis-evex.h: Break into ...
1186 * i386-dis-evex-len.h: New file.
1187 * i386-dis-evex-mod.h: Likewise.
1188 * i386-dis-evex-prefix.h: Likewise.
1189 * i386-dis-evex-reg.h: Likewise.
1190 * i386-dis-evex-w.h: Likewise.
1191 * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
1192 i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
1193 i386-dis-evex-mod.h.
1195 2019-06-19 H.J. Lu <hongjiu.lu@intel.com>
1198 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
1199 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
1201 (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
1202 EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
1203 EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
1204 EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
1205 EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
1206 EVEX_LEN_0F385B_P_2_W_1.
1207 * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
1208 (EVEX_LEN_0F3819_P_2_W_1): Likewise.
1209 (EVEX_LEN_0F381A_P_2_W_0): Likewise.
1210 (EVEX_LEN_0F381A_P_2_W_1): Likewise.
1211 (EVEX_LEN_0F381B_P_2_W_0): Likewise.
1212 (EVEX_LEN_0F381B_P_2_W_1): Likewise.
1213 (EVEX_LEN_0F385A_P_2_W_0): Likewise.
1214 (EVEX_LEN_0F385A_P_2_W_1): Likewise.
1215 (EVEX_LEN_0F385B_P_2_W_0): Likewise.
1216 (EVEX_LEN_0F385B_P_2_W_1): Likewise.
1218 2019-06-17 H.J. Lu <hongjiu.lu@intel.com>
1221 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
1222 EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
1223 EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
1224 (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
1225 EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
1226 EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
1227 EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
1228 EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
1229 EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
1230 EVEX_LEN_0F3A43_P_2_W_1.
1231 * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
1232 (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
1233 (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
1234 (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
1235 (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
1236 (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
1237 (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
1238 (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
1239 (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
1240 (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
1241 (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
1242 (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
1244 2019-06-14 Nick Clifton <nickc@redhat.com>
1246 * po/fr.po; Updated French translation.
1248 2019-06-13 Stafford Horne <shorne@gmail.com>
1250 * or1k-asm.c: Regenerated.
1251 * or1k-desc.c: Regenerated.
1252 * or1k-desc.h: Regenerated.
1253 * or1k-dis.c: Regenerated.
1254 * or1k-ibld.c: Regenerated.
1255 * or1k-opc.c: Regenerated.
1256 * or1k-opc.h: Regenerated.
1257 * or1k-opinst.c: Regenerated.
1259 2019-06-12 Peter Bergner <bergner@linux.ibm.com>
1261 * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
1263 2019-06-05 H.J. Lu <hongjiu.lu@intel.com>
1266 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
1267 EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
1268 (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
1269 EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
1270 EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
1271 EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
1272 EVEX_LEN_0F3A1B_P_2_W_1.
1273 * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
1274 (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
1275 (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
1276 (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
1277 (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
1278 (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
1279 (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
1280 (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
1282 2019-06-04 H.J. Lu <hongjiu.lu@intel.com>
1285 * i386-dis.c (print_insn): Check for unused VEX.vvvv and
1286 EVEX.vvvv when disassembling VEX and EVEX instructions.
1287 (OP_VEX): Set vex.register_specifier to 0 after readding
1288 vex.register_specifier.
1289 (OP_Vex_2src_1): Likewise.
1290 (OP_Vex_2src_2): Likewise.
1291 (OP_LWP_E): Likewise.
1292 (OP_EX_Vex): Don't check vex.register_specifier.
1293 (OP_XMM_Vex): Likewise.
1295 2019-06-04 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1296 Lili Cui <lili.cui@intel.com>
1298 * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
1299 * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
1301 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
1302 CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
1303 (cpu_flags): Add CpuAVX512_VP2INTERSECT.
1304 * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
1305 (i386_cpu_flags): Add cpuavx512_vp2intersect.
1306 * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
1307 * i386-init.h: Regenerated.
1308 * i386-tbl.h: Likewise.
1310 2019-06-04 Xuepeng Guo <xuepeng.guo@intel.com>
1311 Lili Cui <lili.cui@intel.com>
1313 * doc/c-i386.texi: Document enqcmd.
1314 * testsuite/gas/i386/enqcmd-intel.d: New file.
1315 * testsuite/gas/i386/enqcmd-inval.l: Likewise.
1316 * testsuite/gas/i386/enqcmd-inval.s: Likewise.
1317 * testsuite/gas/i386/enqcmd.d: Likewise.
1318 * testsuite/gas/i386/enqcmd.s: Likewise.
1319 * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
1320 * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
1321 * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
1322 * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
1323 * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
1324 * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
1325 enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
1328 2019-06-04 Alan Hayward <alan.hayward@arm.com>
1330 * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
1332 2019-06-03 Alan Modra <amodra@gmail.com>
1334 * ppc-dis.c (prefix_opcd_indices): Correct size.
1336 2019-05-28 H.J. Lu <hongjiu.lu@intel.com>
1339 * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
1341 * i386-tbl.h: Regenerated.
1343 2019-05-24 Alan Modra <amodra@gmail.com>
1345 * po/POTFILES.in: Regenerate.
1347 2019-05-24 Peter Bergner <bergner@linux.ibm.com>
1348 Alan Modra <amodra@gmail.com>
1350 * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
1351 (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
1352 (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
1353 (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
1354 XTOP>): Define and add entries.
1355 (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
1356 (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
1357 pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
1358 plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
1360 2019-05-24 Peter Bergner <bergner@linux.ibm.com>
1361 Alan Modra <amodra@gmail.com>
1363 * ppc-dis.c (ppc_opts): Add "future" entry.
1364 (PREFIX_OPCD_SEGS): Define.
1365 (prefix_opcd_indices): New array.
1366 (disassemble_init_powerpc): Initialize prefix_opcd_indices.
1367 (lookup_prefix): New function.
1368 (print_insn_powerpc): Handle 64-bit prefix instructions.
1369 * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
1370 (PMRR, POWERXX): Define.
1371 (prefix_opcodes): New instruction table.
1372 (prefix_num_opcodes): New constant.
1374 2019-05-23 Jose E. Marchesi <jose.marchesi@oracle.com>
1376 * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
1377 * configure: Regenerated.
1378 * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
1380 (HFILES): Add bpf-desc.h and bpf-opc.h.
1381 (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
1382 bpf-ibld.c and bpf-opc.c.
1384 * Makefile.in: Regenerated.
1385 * disassemble.c (ARCH_bpf): Define.
1386 (disassembler): Add case for bfd_arch_bpf.
1387 (disassemble_init_for_target): Likewise.
1388 (enum epbf_isa_attr): Define.
1389 * disassemble.h: extern print_insn_bpf.
1390 * bpf-asm.c: Generated.
1391 * bpf-opc.h: Likewise.
1392 * bpf-opc.c: Likewise.
1393 * bpf-ibld.c: Likewise.
1394 * bpf-dis.c: Likewise.
1395 * bpf-desc.h: Likewise.
1396 * bpf-desc.c: Likewise.
1398 2019-05-21 Sudakshina Das <sudi.das@arm.com>
1400 * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
1401 and VMSR with the new operands.
1403 2019-05-21 Sudakshina Das <sudi.das@arm.com>
1405 * arm-dis.c (enum mve_instructions): New enum
1406 for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
1408 (mve_opcodes): New instructions as above.
1409 (is_mve_encoding_conflict): Add cases for csinc, csinv,
1411 (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
1413 2019-05-21 Sudakshina Das <sudi.das@arm.com>
1415 * arm-dis.c (emun mve_instructions): Updated for new instructions.
1416 (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
1417 sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
1418 uqshl, urshrl and urshr.
1419 (is_mve_okay_in_it): Add new instructions to TRUE list.
1420 (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
1421 (print_insn_mve): Updated to accept new %j,
1422 %<bitfield>m and %<bitfield>n patterns.
1424 2019-05-21 Faraz Shahbazker <fshahbazker@wavecomp.com>
1426 * mips-opc.c (mips_builtin_opcodes): Change source register
1427 constraint for DAUI.
1429 2019-05-20 Nick Clifton <nickc@redhat.com>
1431 * po/fr.po: Updated French translation.
1433 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1434 Michael Collison <michael.collison@arm.com>
1436 * arm-dis.c (thumb32_opcodes): Add new instructions.
1437 (enum mve_instructions): Likewise.
1438 (enum mve_undefined): Add new reasons.
1439 (is_mve_encoding_conflict): Handle new instructions.
1440 (is_mve_undefined): Likewise.
1441 (is_mve_unpredictable): Likewise.
1442 (print_mve_undefined): Likewise.
1443 (print_mve_size): Likewise.
1445 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1446 Michael Collison <michael.collison@arm.com>
1448 * arm-dis.c (thumb32_opcodes): Add new instructions.
1449 (enum mve_instructions): Likewise.
1450 (is_mve_encoding_conflict): Handle new instructions.
1451 (is_mve_undefined): Likewise.
1452 (is_mve_unpredictable): Likewise.
1453 (print_mve_size): Likewise.
1455 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1456 Michael Collison <michael.collison@arm.com>
1458 * arm-dis.c (thumb32_opcodes): Add new instructions.
1459 (enum mve_instructions): Likewise.
1460 (is_mve_encoding_conflict): Likewise.
1461 (is_mve_unpredictable): Likewise.
1462 (print_mve_size): Likewise.
1464 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1465 Michael Collison <michael.collison@arm.com>
1467 * arm-dis.c (thumb32_opcodes): Add new instructions.
1468 (enum mve_instructions): Likewise.
1469 (is_mve_encoding_conflict): Handle new instructions.
1470 (is_mve_undefined): Likewise.
1471 (is_mve_unpredictable): Likewise.
1472 (print_mve_size): Likewise.
1474 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1475 Michael Collison <michael.collison@arm.com>
1477 * arm-dis.c (thumb32_opcodes): Add new instructions.
1478 (enum mve_instructions): Likewise.
1479 (is_mve_encoding_conflict): Handle new instructions.
1480 (is_mve_undefined): Likewise.
1481 (is_mve_unpredictable): Likewise.
1482 (print_mve_size): Likewise.
1483 (print_insn_mve): Likewise.
1485 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1486 Michael Collison <michael.collison@arm.com>
1488 * arm-dis.c (thumb32_opcodes): Add new instructions.
1489 (print_insn_thumb32): Handle new instructions.
1491 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1492 Michael Collison <michael.collison@arm.com>
1494 * arm-dis.c (enum mve_instructions): Add new instructions.
1495 (enum mve_undefined): Add new reasons.
1496 (is_mve_encoding_conflict): Handle new instructions.
1497 (is_mve_undefined): Likewise.
1498 (is_mve_unpredictable): Likewise.
1499 (print_mve_undefined): Likewise.
1500 (print_mve_size): Likewise.
1501 (print_mve_shift_n): Likewise.
1502 (print_insn_mve): Likewise.
1504 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1505 Michael Collison <michael.collison@arm.com>
1507 * arm-dis.c (enum mve_instructions): Add new instructions.
1508 (is_mve_encoding_conflict): Handle new instructions.
1509 (is_mve_unpredictable): Likewise.
1510 (print_mve_rotate): Likewise.
1511 (print_mve_size): Likewise.
1512 (print_insn_mve): Likewise.
1514 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1515 Michael Collison <michael.collison@arm.com>
1517 * arm-dis.c (enum mve_instructions): Add new instructions.
1518 (is_mve_encoding_conflict): Handle new instructions.
1519 (is_mve_unpredictable): Likewise.
1520 (print_mve_size): Likewise.
1521 (print_insn_mve): Likewise.
1523 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1524 Michael Collison <michael.collison@arm.com>
1526 * arm-dis.c (enum mve_instructions): Add new instructions.
1527 (enum mve_undefined): Add new reasons.
1528 (is_mve_encoding_conflict): Handle new instructions.
1529 (is_mve_undefined): Likewise.
1530 (is_mve_unpredictable): Likewise.
1531 (print_mve_undefined): Likewise.
1532 (print_mve_size): Likewise.
1533 (print_insn_mve): Likewise.
1535 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1536 Michael Collison <michael.collison@arm.com>
1538 * arm-dis.c (enum mve_instructions): Add new instructions.
1539 (is_mve_encoding_conflict): Handle new instructions.
1540 (is_mve_undefined): Likewise.
1541 (is_mve_unpredictable): Likewise.
1542 (print_mve_size): Likewise.
1543 (print_insn_mve): Likewise.
1545 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1546 Michael Collison <michael.collison@arm.com>
1548 * arm-dis.c (enum mve_instructions): Add new instructions.
1549 (enum mve_unpredictable): Add new reasons.
1550 (enum mve_undefined): Likewise.
1551 (is_mve_okay_in_it): Handle new isntructions.
1552 (is_mve_encoding_conflict): Likewise.
1553 (is_mve_undefined): Likewise.
1554 (is_mve_unpredictable): Likewise.
1555 (print_mve_vmov_index): Likewise.
1556 (print_simd_imm8): Likewise.
1557 (print_mve_undefined): Likewise.
1558 (print_mve_unpredictable): Likewise.
1559 (print_mve_size): Likewise.
1560 (print_insn_mve): Likewise.
1562 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1563 Michael Collison <michael.collison@arm.com>
1565 * arm-dis.c (enum mve_instructions): Add new instructions.
1566 (enum mve_unpredictable): Add new reasons.
1567 (enum mve_undefined): Likewise.
1568 (is_mve_encoding_conflict): Handle new instructions.
1569 (is_mve_undefined): Likewise.
1570 (is_mve_unpredictable): Likewise.
1571 (print_mve_undefined): Likewise.
1572 (print_mve_unpredictable): Likewise.
1573 (print_mve_rounding_mode): Likewise.
1574 (print_mve_vcvt_size): Likewise.
1575 (print_mve_size): Likewise.
1576 (print_insn_mve): Likewise.
1578 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1579 Michael Collison <michael.collison@arm.com>
1581 * arm-dis.c (enum mve_instructions): Add new instructions.
1582 (enum mve_unpredictable): Add new reasons.
1583 (enum mve_undefined): Likewise.
1584 (is_mve_undefined): Handle new instructions.
1585 (is_mve_unpredictable): Likewise.
1586 (print_mve_undefined): Likewise.
1587 (print_mve_unpredictable): Likewise.
1588 (print_mve_size): Likewise.
1589 (print_insn_mve): Likewise.
1591 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1592 Michael Collison <michael.collison@arm.com>
1594 * arm-dis.c (enum mve_instructions): Add new instructions.
1595 (enum mve_undefined): Add new reasons.
1596 (insns): Add new instructions.
1597 (is_mve_encoding_conflict):
1598 (print_mve_vld_str_addr): New print function.
1599 (is_mve_undefined): Handle new instructions.
1600 (is_mve_unpredictable): Likewise.
1601 (print_mve_undefined): Likewise.
1602 (print_mve_size): Likewise.
1603 (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
1604 (print_insn_mve): Handle new operands.
1606 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1607 Michael Collison <michael.collison@arm.com>
1609 * arm-dis.c (enum mve_instructions): Add new instructions.
1610 (enum mve_unpredictable): Add new reasons.
1611 (is_mve_encoding_conflict): Handle new instructions.
1612 (is_mve_unpredictable): Likewise.
1613 (mve_opcodes): Add new instructions.
1614 (print_mve_unpredictable): Handle new reasons.
1615 (print_mve_register_blocks): New print function.
1616 (print_mve_size): Handle new instructions.
1617 (print_insn_mve): Likewise.
1619 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1620 Michael Collison <michael.collison@arm.com>
1622 * arm-dis.c (enum mve_instructions): Add new instructions.
1623 (enum mve_unpredictable): Add new reasons.
1624 (enum mve_undefined): Likewise.
1625 (is_mve_encoding_conflict): Handle new instructions.
1626 (is_mve_undefined): Likewise.
1627 (is_mve_unpredictable): Likewise.
1628 (coprocessor_opcodes): Move NEON VDUP from here...
1629 (neon_opcodes): ... to here.
1630 (mve_opcodes): Add new instructions.
1631 (print_mve_undefined): Handle new reasons.
1632 (print_mve_unpredictable): Likewise.
1633 (print_mve_size): Handle new instructions.
1634 (print_insn_neon): Handle vdup.
1635 (print_insn_mve): Handle new operands.
1637 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1638 Michael Collison <michael.collison@arm.com>
1640 * arm-dis.c (enum mve_instructions): Add new instructions.
1641 (enum mve_unpredictable): Add new values.
1642 (mve_opcodes): Add new instructions.
1643 (vec_condnames): New array with vector conditions.
1644 (mve_predicatenames): New array with predicate suffixes.
1645 (mve_vec_sizename): New array with vector sizes.
1646 (enum vpt_pred_state): New enum with vector predication states.
1647 (struct vpt_block): New struct type for vpt blocks.
1648 (vpt_block_state): Global struct to keep track of state.
1649 (mve_extract_pred_mask): New helper function.
1650 (num_instructions_vpt_block): Likewise.
1651 (mark_outside_vpt_block): Likewise.
1652 (mark_inside_vpt_block): Likewise.
1653 (invert_next_predicate_state): Likewise.
1654 (update_next_predicate_state): Likewise.
1655 (update_vpt_block_state): Likewise.
1656 (is_vpt_instruction): Likewise.
1657 (is_mve_encoding_conflict): Add entries for new instructions.
1658 (is_mve_unpredictable): Likewise.
1659 (print_mve_unpredictable): Handle new cases.
1660 (print_instruction_predicate): Likewise.
1661 (print_mve_size): New function.
1662 (print_vec_condition): New function.
1663 (print_insn_mve): Handle vpt blocks and new print operands.
1665 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1667 * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
1668 8, 14 and 15 for Armv8.1-M Mainline.
1670 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1671 Michael Collison <michael.collison@arm.com>
1673 * arm-dis.c (enum mve_instructions): New enum.
1674 (enum mve_unpredictable): Likewise.
1675 (enum mve_undefined): Likewise.
1676 (struct mopcode32): New struct.
1677 (is_mve_okay_in_it): New function.
1678 (is_mve_architecture): Likewise.
1679 (arm_decode_field): Likewise.
1680 (arm_decode_field_multiple): Likewise.
1681 (is_mve_encoding_conflict): Likewise.
1682 (is_mve_undefined): Likewise.
1683 (is_mve_unpredictable): Likewise.
1684 (print_mve_undefined): Likewise.
1685 (print_mve_unpredictable): Likewise.
1686 (print_insn_coprocessor_1): Use arm_decode_field_multiple.
1687 (print_insn_mve): New function.
1688 (print_insn_thumb32): Handle MVE architecture.
1689 (select_arm_features): Force thumb for Armv8.1-m Mainline.
1691 2019-05-10 Nick Clifton <nickc@redhat.com>
1694 * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
1695 end of the table prematurely.
1697 2019-05-10 Faraz Shahbazker <fshahbazker@wavecomp.com>
1699 * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
1702 2019-05-11 Alan Modra <amodra@gmail.com>
1704 * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
1705 when -Mraw is in effect.
1707 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1709 * aarch64-dis-2.c: Regenerate.
1710 * aarch64-tbl.h (OP_SVE_BBU): New variant set.
1711 (OP_SVE_BBB): New variant set.
1712 (OP_SVE_DDDD): New variant set.
1713 (OP_SVE_HHH): New variant set.
1714 (OP_SVE_HHHU): New variant set.
1715 (OP_SVE_SSS): New variant set.
1716 (OP_SVE_SSSU): New variant set.
1717 (OP_SVE_SHH): New variant set.
1718 (OP_SVE_SBBU): New variant set.
1719 (OP_SVE_DSS): New variant set.
1720 (OP_SVE_DHHU): New variant set.
1721 (OP_SVE_VMV_HSD_BHS): New variant set.
1722 (OP_SVE_VVU_HSD_BHS): New variant set.
1723 (OP_SVE_VVVU_SD_BH): New variant set.
1724 (OP_SVE_VVVU_BHSD): New variant set.
1725 (OP_SVE_VVV_QHD_DBS): New variant set.
1726 (OP_SVE_VVV_HSD_BHS): New variant set.
1727 (OP_SVE_VVV_HSD_BHS2): New variant set.
1728 (OP_SVE_VVV_BHS_HSD): New variant set.
1729 (OP_SVE_VV_BHS_HSD): New variant set.
1730 (OP_SVE_VVV_SD): New variant set.
1731 (OP_SVE_VVU_BHS_HSD): New variant set.
1732 (OP_SVE_VZVV_SD): New variant set.
1733 (OP_SVE_VZVV_BH): New variant set.
1734 (OP_SVE_VZV_SD): New variant set.
1735 (aarch64_opcode_table): Add sve2 instructions.
1737 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1739 * aarch64-asm-2.c: Regenerated.
1740 * aarch64-dis-2.c: Regenerated.
1741 * aarch64-opc-2.c: Regenerated.
1742 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1743 for SVE_SHLIMM_UNPRED_22.
1744 (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
1745 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
1748 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1750 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1751 sve_size_tsz_bhs iclass encode.
1752 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1753 sve_size_tsz_bhs iclass decode.
1755 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1757 * aarch64-asm-2.c: Regenerated.
1758 * aarch64-dis-2.c: Regenerated.
1759 * aarch64-opc-2.c: Regenerated.
1760 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1761 for SVE_Zm4_11_INDEX.
1762 (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
1763 (fields): Handle SVE_i2h field.
1764 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
1765 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
1767 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1769 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1770 sve_shift_tsz_bhsd iclass encode.
1771 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1772 sve_shift_tsz_bhsd iclass decode.
1774 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1776 * aarch64-asm-2.c: Regenerated.
1777 * aarch64-dis-2.c: Regenerated.
1778 * aarch64-opc-2.c: Regenerated.
1779 * aarch64-asm.c (aarch64_ins_sve_shrimm):
1780 (aarch64_encode_variant_using_iclass): Handle
1781 sve_shift_tsz_hsd iclass encode.
1782 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1783 sve_shift_tsz_hsd iclass decode.
1784 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1785 for SVE_SHRIMM_UNPRED_22.
1786 (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
1787 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
1790 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1792 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1793 sve_size_013 iclass encode.
1794 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1795 sve_size_013 iclass decode.
1797 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1799 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1800 sve_size_bh iclass encode.
1801 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1802 sve_size_bh iclass decode.
1804 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1806 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1807 sve_size_sd2 iclass encode.
1808 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1809 sve_size_sd2 iclass decode.
1810 * aarch64-opc.c (fields): Handle SVE_sz2 field.
1811 * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
1813 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1815 * aarch64-asm-2.c: Regenerated.
1816 * aarch64-dis-2.c: Regenerated.
1817 * aarch64-opc-2.c: Regenerated.
1818 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1820 (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
1821 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
1823 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1825 * aarch64-asm-2.c: Regenerated.
1826 * aarch64-dis-2.c: Regenerated.
1827 * aarch64-opc-2.c: Regenerated.
1828 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1829 for SVE_Zm3_11_INDEX.
1830 (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
1831 (fields): Handle SVE_i3l and SVE_i3h2 fields.
1832 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
1834 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
1836 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1838 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1839 sve_size_hsd2 iclass encode.
1840 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1841 sve_size_hsd2 iclass decode.
1842 * aarch64-opc.c (fields): Handle SVE_size field.
1843 * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
1845 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1847 * aarch64-asm-2.c: Regenerated.
1848 * aarch64-dis-2.c: Regenerated.
1849 * aarch64-opc-2.c: Regenerated.
1850 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1852 (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
1853 (fields): Handle SVE_rot3 field.
1854 * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
1855 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
1857 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1859 * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
1862 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1865 (aarch64_feature_sve2, aarch64_feature_sve2aes,
1866 aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
1867 aarch64_feature_sve2bitperm): New feature sets.
1868 (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
1869 for feature set addresses.
1870 (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
1871 SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
1873 2019-05-06 Andrew Bennett <andrew.bennett@imgtec.com>
1874 Faraz Shahbazker <fshahbazker@wavecomp.com>
1876 * mips-dis.c (mips_calculate_combination_ases): Add ISA
1877 argument and set ASE_EVA_R6 appropriately.
1878 (set_default_mips_dis_options): Pass ISA to above.
1879 (parse_mips_dis_option): Likewise.
1880 * mips-opc.c (EVAR6): New macro.
1881 (mips_builtin_opcodes): Add llwpe, scwpe.
1883 2019-05-01 Sudakshina Das <sudi.das@arm.com>
1885 * aarch64-asm-2.c: Regenerated.
1886 * aarch64-dis-2.c: Regenerated.
1887 * aarch64-opc-2.c: Regenerated.
1888 * aarch64-opc.c (operand_general_constraint_met_p): Add case for
1889 AARCH64_OPND_TME_UIMM16.
1890 (aarch64_print_operand): Likewise.
1891 * aarch64-tbl.h (QL_IMM_NIL): New.
1894 (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
1896 2019-04-29 John Darrington <john@darrington.wattle.id.au>
1898 * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
1900 2019-04-26 Andrew Bennett <andrew.bennett@imgtec.com>
1901 Faraz Shahbazker <fshahbazker@wavecomp.com>
1903 * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
1905 2019-04-24 John Darrington <john@darrington.wattle.id.au>
1907 * s12z-opc.h: Add extern "C" bracketing to help
1908 users who wish to use this interface in c++ code.
1910 2019-04-24 John Darrington <john@darrington.wattle.id.au>
1912 * s12z-opc.c (bm_decode): Handle bit map operations with the
1915 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1917 * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
1918 specifier. Add entries for VLDR and VSTR of system registers.
1919 (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
1920 coprocessor instructions on Armv8.1-M Mainline targets. Add handling
1921 of %J and %K format specifier.
1923 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1925 * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
1926 Add new entries for VSCCLRM instruction.
1927 (print_insn_coprocessor): Handle new %C format control code.
1929 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1931 * arm-dis.c (enum isa): New enum.
1932 (struct sopcode32): New structure.
1933 (coprocessor_opcodes): change type of entries to struct sopcode32 and
1934 set isa field of all current entries to ANY.
1935 (print_insn_coprocessor): Change type of insn to struct sopcode32.
1936 Only match an entry if its isa field allows the current mode.
1938 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1940 * arm-dis.c (thumb_opcodes): Document %n control code. Add entry for
1942 (print_insn_thumb32): Add logic to print %n CLRM register list.
1944 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1946 * arm-dis.c (print_insn_thumb32): Updated to accept new %P
1949 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1951 * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
1952 (print_insn_thumb32): Edit the switch case for %Z.
1954 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1956 * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
1958 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1960 * arm-dis.c (thumb32_opcodes): New instruction bfl.
1962 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1964 * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
1966 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1968 * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
1969 Arm register with r13 and r15 unpredictable.
1970 (thumb32_opcodes): New instructions for bfx and bflx.
1972 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1974 * arm-dis.c (thumb32_opcodes): New instructions for bf.
1976 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1978 * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
1980 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1982 * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
1984 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1986 * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
1988 2019-04-12 John Darrington <john@darrington.wattle.id.au>
1990 s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
1991 "optr". ("operator" is a reserved word in c++).
1993 2019-04-11 Sudakshina Das <sudi.das@arm.com>
1995 * aarch64-opc.c (aarch64_print_operand): Add case for
1997 (verify_constraints): Likewise.
1998 * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
1999 (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
2000 to accept Rt|SP as first operand.
2001 (AARCH64_OPERANDS): Add new Rt_SP.
2002 * aarch64-asm-2.c: Regenerated.
2003 * aarch64-dis-2.c: Regenerated.
2004 * aarch64-opc-2.c: Regenerated.
2006 2019-04-11 Sudakshina Das <sudi.das@arm.com>
2008 * aarch64-asm-2.c: Regenerated.
2009 * aarch64-dis-2.c: Likewise.
2010 * aarch64-opc-2.c: Likewise.
2011 * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
2013 2019-04-09 Robert Suchanek <robert.suchanek@mips.com>
2015 * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
2017 2019-04-08 H.J. Lu <hongjiu.lu@intel.com>
2019 * i386-opc.tbl: Consolidate AVX512 BF16 entries.
2020 * i386-init.h: Regenerated.
2022 2019-04-07 Alan Modra <amodra@gmail.com>
2024 * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
2025 op_separator to control printing of spaces, comma and parens
2026 rather than need_comma, need_paren and spaces vars.
2028 2019-04-07 Alan Modra <amodra@gmail.com>
2031 * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
2032 (print_insn_neon, print_insn_arm): Likewise.
2034 2019-04-05 Xuepeng Guo <xuepeng.guo@intel.com>
2036 * i386-dis-evex.h (evex_table): Updated to support BF16
2038 * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
2039 and EVEX_W_0F3872_P_3.
2040 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
2041 (cpu_flags): Add bitfield for CpuAVX512_BF16.
2042 * i386-opc.h (enum): Add CpuAVX512_BF16.
2043 (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
2044 * i386-opc.tbl: Add AVX512 BF16 instructions.
2045 * i386-init.h: Regenerated.
2046 * i386-tbl.h: Likewise.
2048 2019-04-05 Alan Modra <amodra@gmail.com>
2050 * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
2051 (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
2052 to favour printing of "-" branch hint when using the "y" bit.
2053 Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
2055 2019-04-05 Alan Modra <amodra@gmail.com>
2057 * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
2058 opcode until first operand is output.
2060 2019-04-04 Peter Bergner <bergner@linux.ibm.com>
2063 * ppc-opc.c (valid_bo_pre_v2): Add comments.
2064 (valid_bo_post_v2): Add support for 'at' branch hints.
2065 (insert_bo): Only error on branch on ctr.
2066 (get_bo_hint_mask): New function.
2067 (insert_boe): Add new 'branch_taken' formal argument. Add support
2068 for inserting 'at' branch hints.
2069 (extract_boe): Add new 'branch_taken' formal argument. Add support
2070 for extracting 'at' branch hints.
2071 (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
2072 (BOE): Delete operand.
2073 (BOM, BOP): New operands.
2075 (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
2076 (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
2077 bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
2078 (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
2079 bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
2080 <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
2081 bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
2082 bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
2083 bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
2084 bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
2085 bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
2086 bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
2087 bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
2088 beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
2089 bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
2090 buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
2091 bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
2092 bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
2093 bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
2094 bttarl+>: New extended mnemonics.
2096 2019-03-28 Alan Modra <amodra@gmail.com>
2099 * ppc-opc.c (BTF): Define.
2100 (powerpc_opcodes): Use for mtfsb*.
2101 * ppc-dis.c (print_insn_powerpc): Print fields with both
2102 PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
2104 2019-03-25 Tamar Christina <tamar.christina@arm.com>
2106 * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
2107 (mapping_symbol_for_insn): Implement new algorithm.
2108 (print_insn): Remove duplicate code.
2110 2019-03-25 Tamar Christina <tamar.christina@arm.com>
2112 * aarch64-dis.c (print_insn_aarch64):
2115 2019-03-25 Tamar Christina <tamar.christina@arm.com>
2117 * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
2120 2019-03-25 Tamar Christina <tamar.christina@arm.com>
2122 * aarch64-dis.c (last_stop_offset): New.
2123 (print_insn_aarch64): Use stop_offset.
2125 2019-03-19 H.J. Lu <hongjiu.lu@intel.com>
2128 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
2130 * i386-init.h: Regenerated.
2132 2019-03-18 H.J. Lu <hongjiu.lu@intel.com>
2135 * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
2136 vmovdqu16, vmovdqu32 and vmovdqu64.
2137 * i386-tbl.h: Regenerated.
2139 2019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
2141 * s390-opc.txt: Rename selhhhr to selfhr. Remove optional operand
2142 from vstrszb, vstrszh, and vstrszf.
2144 2019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
2146 * s390-opc.txt: Add instruction descriptions.
2148 2019-02-08 Jim Wilson <jimw@sifive.com>
2150 * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
2153 2019-02-07 Tamar Christina <tamar.christina@arm.com>
2155 * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
2157 2019-02-07 Tamar Christina <tamar.christina@arm.com>
2160 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
2161 * aarch64-opc.c (verify_elem_sd): New.
2162 (fields): Add FLD_sz entr.
2163 * aarch64-tbl.h (_SIMD_INSN): New.
2164 (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
2165 fmulx scalar and vector by element isns.
2167 2019-02-07 Nick Clifton <nickc@redhat.com>
2169 * po/sv.po: Updated Swedish translation.
2171 2019-01-31 Andreas Krebbel <krebbel@linux.ibm.com>
2173 * s390-mkopc.c (main): Accept arch13 as cpu string.
2174 * s390-opc.c: Add new instruction formats and instruction opcode
2176 * s390-opc.txt: Add new arch13 instructions.
2178 2019-01-25 Sudakshina Das <sudi.das@arm.com>
2180 * aarch64-tbl.h (QL_LDST_AT): Update macro.
2181 (aarch64_opcode): Change encoding for stg, stzg
2183 * aarch64-asm-2.c: Regenerated.
2184 * aarch64-dis-2.c: Regenerated.
2185 * aarch64-opc-2.c: Regenerated.
2187 2019-01-25 Sudakshina Das <sudi.das@arm.com>
2189 * aarch64-asm-2.c: Regenerated.
2190 * aarch64-dis-2.c: Likewise.
2191 * aarch64-opc-2.c: Likewise.
2192 * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
2194 2019-01-25 Sudakshina Das <sudi.das@arm.com>
2195 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
2197 * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
2198 * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
2199 * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
2200 * aarch64-dis.h (ext_addr_simple_2): Likewise.
2201 * aarch64-opc.c (operand_general_constraint_met_p): Remove
2202 case for ldstgv_indexed.
2203 (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
2204 * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
2205 (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
2206 * aarch64-asm-2.c: Regenerated.
2207 * aarch64-dis-2.c: Regenerated.
2208 * aarch64-opc-2.c: Regenerated.
2210 2019-01-23 Nick Clifton <nickc@redhat.com>
2212 * po/pt_BR.po: Updated Brazilian Portuguese translation.
2214 2019-01-21 Nick Clifton <nickc@redhat.com>
2216 * po/de.po: Updated German translation.
2217 * po/uk.po: Updated Ukranian translation.
2219 2019-01-20 Chenghua Xu <paul.hua.gm@gmail.com>
2220 * mips-dis.c (mips_arch_choices): Fix typo in
2221 gs464, gs464e and gs264e descriptors.
2223 2019-01-19 Nick Clifton <nickc@redhat.com>
2225 * configure: Regenerate.
2226 * po/opcodes.pot: Regenerate.
2228 2018-06-24 Nick Clifton <nickc@redhat.com>
2230 2.32 branch created.
2232 2019-01-09 John Darrington <john@darrington.wattle.id.au>
2234 * s12z-dis.c (print_insn_s12z): Do not dereference an operand
2236 -dis.c (opr_emit_disassembly): Do not omit an index if it is
2239 2019-01-09 Andrew Paprocki <andrew@ishiboo.com>
2241 * configure: Regenerate.
2243 2019-01-07 Alan Modra <amodra@gmail.com>
2245 * configure: Regenerate.
2246 * po/POTFILES.in: Regenerate.
2248 2019-01-03 John Darrington <john@darrington.wattle.id.au>
2250 * s12z-opc.c: New file.
2251 * s12z-opc.h: New file.
2252 * s12z-dis.c: Removed all code not directly related to display
2253 of instructions. Used the interface provided by the new files
2255 * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
2256 * Makefile.in: Regenerate.
2257 * configure.ac (bfd_s12z_arch): Correct the dependencies.
2258 * configure: Regenerate.
2260 2019-01-01 Alan Modra <amodra@gmail.com>
2262 Update year range in copyright notice of all files.
2264 For older changes see ChangeLog-2018
2266 Copyright (C) 2019 Free Software Foundation, Inc.
2268 Copying and distribution of this file, with or without modification,
2269 are permitted in any medium without royalty provided the copyright
2270 notice and this notice are preserved.
2276 version-control: never