1 static const struct dis386 evex_len_table
[][3] = {
2 /* EVEX_LEN_0F6E_P_2 */
4 { "vmovK", { XMScalar
, Edq
}, 0 },
7 /* EVEX_LEN_0F7E_P_1 */
9 { VEX_W_TABLE (EVEX_W_0F7E_P_1
) },
12 /* EVEX_LEN_0F7E_P_2 */
14 { "vmovK", { Edq
, XMScalar
}, 0 },
17 /* EVEX_LEN_0FC4_P_2 */
19 { "vpinsrw", { XM
, Vex128
, Edqw
, Ib
}, 0 },
22 /* EVEX_LEN_0FC5_P_2 */
24 { "vpextrw", { Gdq
, XS
, Ib
}, 0 },
27 /* EVEX_LEN_0FD6_P_2 */
29 { VEX_W_TABLE (EVEX_W_0FD6_P_2
) },
32 /* EVEX_LEN_0F3819_P_2_W_0 */
35 { "vbroadcastf32x2", { XM
, EXxmm_mq
}, 0 },
36 { "vbroadcastf32x2", { XM
, EXxmm_mq
}, 0 },
39 /* EVEX_LEN_0F3819_P_2_W_1 */
42 { "vbroadcastsd", { XM
, EXxmm_mq
}, 0 },
43 { "vbroadcastsd", { XM
, EXxmm_mq
}, 0 },
46 /* EVEX_LEN_0F381A_P_2_W_0 */
49 { "vbroadcastf32x4", { XM
, EXxmm
}, 0 },
50 { "vbroadcastf32x4", { XM
, EXxmm
}, 0 },
53 /* EVEX_LEN_0F381A_P_2_W_1 */
56 { "vbroadcastf64x2", { XM
, EXxmm
}, 0 },
57 { "vbroadcastf64x2", { XM
, EXxmm
}, 0 },
60 /* EVEX_LEN_0F381B_P_2_W_0 */
64 { "vbroadcastf32x8", { XM
, EXxmmq
}, 0 },
67 /* EVEX_LEN_0F381B_P_2_W_1 */
71 { "vbroadcastf64x4", { XM
, EXymm
}, 0 },
74 /* EVEX_LEN_0F385A_P_2_W_0 */
77 { "vbroadcasti32x4", { XM
, EXxmm
}, 0 },
78 { "vbroadcasti32x4", { XM
, EXxmm
}, 0 },
81 /* EVEX_LEN_0F385A_P_2_W_1 */
84 { "vbroadcasti64x2", { XM
, EXxmm
}, 0 },
85 { "vbroadcasti64x2", { XM
, EXxmm
}, 0 },
88 /* EVEX_LEN_0F385B_P_2_W_0 */
92 { "vbroadcasti32x8", { XM
, EXxmmq
}, 0 },
95 /* EVEX_LEN_0F385B_P_2_W_1 */
99 { "vbroadcasti64x4", { XM
, EXymm
}, 0 },
102 /* EVEX_LEN_0F38C6_REG_1_PREFIX_2 */
106 { "vgatherpf0dp%XW", { MVexVSIBDWpX
}, 0 },
109 /* EVEX_LEN_0F38C6_REG_2_PREFIX_2 */
113 { "vgatherpf1dp%XW", { MVexVSIBDWpX
}, 0 },
116 /* EVEX_LEN_0F38C6_REG_5_PREFIX_2 */
120 { "vscatterpf0dp%XW", { MVexVSIBDWpX
}, 0 },
123 /* EVEX_LEN_0F38C6_REG_6_PREFIX_2 */
127 { "vscatterpf1dp%XW", { MVexVSIBDWpX
}, 0 },
130 /* EVEX_LEN_0F38C7_R_1_P_2_W_0 */
134 { "vgatherpf0qps", { MVexVSIBDQWpX
}, 0 },
137 /* EVEX_LEN_0F38C7_R_1_P_2_W_1 */
141 { "vgatherpf0qpd", { MVexVSIBQWpX
}, 0 },
144 /* EVEX_LEN_0F38C7_R_2_P_2_W_0 */
148 { "vgatherpf1qps", { MVexVSIBDQWpX
}, 0 },
151 /* EVEX_LEN_0F38C7_R_2_P_2_W_1 */
155 { "vgatherpf1qpd", { MVexVSIBQWpX
}, 0 },
158 /* EVEX_LEN_0F38C7_R_5_P_2_W_0 */
162 { "vscatterpf0qps", { MVexVSIBDQWpX
}, 0 },
165 /* EVEX_LEN_0F38C7_R_5_P_2_W_1 */
169 { "vscatterpf0qpd", { MVexVSIBQWpX
}, 0 },
172 /* EVEX_LEN_0F38C7_R_6_P_2_W_0 */
176 { "vscatterpf1qps", { MVexVSIBDQWpX
}, 0 },
179 /* EVEX_LEN_0F38C7_R_6_P_2_W_1 */
183 { "vscatterpf1qpd", { MVexVSIBQWpX
}, 0 },
186 /* EVEX_LEN_0F3A14_P_2 */
188 { "vpextrb", { Edqb
, XM
, Ib
}, 0 },
191 /* EVEX_LEN_0F3A15_P_2 */
193 { "vpextrw", { Edqw
, XM
, Ib
}, 0 },
196 /* EVEX_LEN_0F3A16_P_2 */
198 { "vpextrK", { Edq
, XM
, Ib
}, 0 },
201 /* EVEX_LEN_0F3A17_P_2 */
203 { "vextractps", { Edqd
, XMM
, Ib
}, 0 },
206 /* EVEX_LEN_0F3A18_P_2_W_0 */
209 { "vinsertf32x4", { XM
, Vex
, EXxmm
, Ib
}, 0 },
210 { "vinsertf32x4", { XM
, Vex
, EXxmm
, Ib
}, 0 },
213 /* EVEX_LEN_0F3A18_P_2_W_1 */
216 { "vinsertf64x2", { XM
, Vex
, EXxmm
, Ib
}, 0 },
217 { "vinsertf64x2", { XM
, Vex
, EXxmm
, Ib
}, 0 },
220 /* EVEX_LEN_0F3A19_P_2_W_0 */
223 { "vextractf32x4", { EXxmm
, XM
, Ib
}, 0 },
224 { "vextractf32x4", { EXxmm
, XM
, Ib
}, 0 },
227 /* EVEX_LEN_0F3A19_P_2_W_1 */
230 { "vextractf64x2", { EXxmm
, XM
, Ib
}, 0 },
231 { "vextractf64x2", { EXxmm
, XM
, Ib
}, 0 },
234 /* EVEX_LEN_0F3A1A_P_2_W_0 */
238 { "vinsertf32x8", { XM
, Vex
, EXxmmq
, Ib
}, 0 },
241 /* EVEX_LEN_0F3A1A_P_2_W_1 */
245 { "vinsertf64x4", { XM
, Vex
, EXxmmq
, Ib
}, 0 },
248 /* EVEX_LEN_0F3A1B_P_2_W_0 */
252 { "vextractf32x8", { EXxmmq
, XM
, Ib
}, 0 },
255 /* EVEX_LEN_0F3A1B_P_2_W_1 */
259 { "vextractf64x4", { EXxmmq
, XM
, Ib
}, 0 },
262 /* EVEX_LEN_0F3A20_P_2 */
264 { "vpinsrb", { XM
, Vex128
, Edqb
, Ib
}, 0 },
267 /* EVEX_LEN_0F3A21_P_2_W_0 */
269 { "vinsertps", { XMM
, Vex
, EXxmm_md
, Ib
}, 0 },
272 /* EVEX_LEN_0F3A22_P_2 */
274 { "vpinsrK", { XM
, Vex128
, Edq
, Ib
}, 0 },
277 /* EVEX_LEN_0F3A23_P_2_W_0 */
280 { "vshuff32x4", { XM
, Vex
, EXx
, Ib
}, 0 },
281 { "vshuff32x4", { XM
, Vex
, EXx
, Ib
}, 0 },
284 /* EVEX_LEN_0F3A23_P_2_W_1 */
287 { "vshuff64x2", { XM
, Vex
, EXx
, Ib
}, 0 },
288 { "vshuff64x2", { XM
, Vex
, EXx
, Ib
}, 0 },
291 /* EVEX_LEN_0F3A38_P_2_W_0 */
294 { "vinserti32x4", { XM
, Vex
, EXxmm
, Ib
}, 0 },
295 { "vinserti32x4", { XM
, Vex
, EXxmm
, Ib
}, 0 },
298 /* EVEX_LEN_0F3A38_P_2_W_1 */
301 { "vinserti64x2", { XM
, Vex
, EXxmm
, Ib
}, 0 },
302 { "vinserti64x2", { XM
, Vex
, EXxmm
, Ib
}, 0 },
305 /* EVEX_LEN_0F3A39_P_2_W_0 */
308 { "vextracti32x4", { EXxmm
, XM
, Ib
}, 0 },
309 { "vextracti32x4", { EXxmm
, XM
, Ib
}, 0 },
312 /* EVEX_LEN_0F3A39_P_2_W_1 */
315 { "vextracti64x2", { EXxmm
, XM
, Ib
}, 0 },
316 { "vextracti64x2", { EXxmm
, XM
, Ib
}, 0 },
319 /* EVEX_LEN_0F3A3A_P_2_W_0 */
322 { "vinserti32x8", { XM
, Vex
, EXxmmq
, Ib
}, 0 },
323 { "vinserti32x8", { XM
, Vex
, EXxmmq
, Ib
}, 0 },
326 /* EVEX_LEN_0F3A3A_P_2_W_1 */
329 { "vinserti64x4", { XM
, Vex
, EXxmmq
, Ib
}, 0 },
330 { "vinserti64x4", { XM
, Vex
, EXxmmq
, Ib
}, 0 },
333 /* EVEX_LEN_0F3A3B_P_2_W_0 */
336 { "vextracti32x8", { EXxmmq
, XM
, Ib
}, 0 },
337 { "vextracti32x8", { EXxmmq
, XM
, Ib
}, 0 },
340 /* EVEX_LEN_0F3A3B_P_2_W_1 */
343 { "vextracti64x4", { EXxmmq
, XM
, Ib
}, 0 },
344 { "vextracti64x4", { EXxmmq
, XM
, Ib
}, 0 },
347 /* EVEX_LEN_0F3A43_P_2_W_0 */
350 { "vshufi32x4", { XM
, Vex
, EXx
, Ib
}, 0 },
351 { "vshufi32x4", { XM
, Vex
, EXx
, Ib
}, 0 },
354 /* EVEX_LEN_0F3A43_P_2_W_1 */
357 { "vshufi64x2", { XM
, Vex
, EXx
, Ib
}, 0 },
358 { "vshufi64x2", { XM
, Vex
, EXx
, Ib
}, 0 },
This page took 0.039853 seconds and 4 git commands to generate.