3 { "vmovupX", { XM
, EXEvexXNoBcst
}, PREFIX_OPCODE
},
4 { VEX_W_TABLE (EVEX_W_0F10_P_1
) },
5 { "vmovupX", { XM
, EXEvexXNoBcst
}, PREFIX_OPCODE
},
6 { VEX_W_TABLE (EVEX_W_0F10_P_3
) },
10 { "vmovupX", { EXxS
, XM
}, PREFIX_OPCODE
},
11 { VEX_W_TABLE (EVEX_W_0F11_P_1
) },
12 { "vmovupX", { EXxS
, XM
}, PREFIX_OPCODE
},
13 { VEX_W_TABLE (EVEX_W_0F11_P_3
) },
15 /* PREFIX_EVEX_0F12 */
17 { MOD_TABLE (MOD_EVEX_0F12_PREFIX_0
) },
18 { VEX_W_TABLE (EVEX_W_0F12_P_1
) },
19 { MOD_TABLE (MOD_EVEX_0F12_PREFIX_2
) },
20 { VEX_W_TABLE (EVEX_W_0F12_P_3
) },
22 /* PREFIX_EVEX_0F16 */
24 { MOD_TABLE (MOD_EVEX_0F16_PREFIX_0
) },
25 { VEX_W_TABLE (EVEX_W_0F16_P_1
) },
26 { MOD_TABLE (MOD_EVEX_0F16_PREFIX_2
) },
28 /* PREFIX_EVEX_0F2A */
31 { "vcvtsi2ss%LQ", { XMScalar
, VexScalar
, EXxEVexR
, Edq
}, 0 },
33 { VEX_W_TABLE (EVEX_W_0F2A_P_3
) },
35 /* PREFIX_EVEX_0F2C */
38 { "vcvttss2si", { Gdq
, EXxmm_md
, EXxEVexS
}, 0 },
40 { "vcvttsd2si", { Gdq
, EXxmm_mq
, EXxEVexS
}, 0 },
42 /* PREFIX_EVEX_0F2D */
45 { "vcvtss2si", { Gdq
, EXxmm_md
, EXxEVexR
}, 0 },
47 { "vcvtsd2si", { Gdq
, EXxmm_mq
, EXxEVexR
}, 0 },
49 /* PREFIX_EVEX_0F2E */
51 { "vucomisX", { XMScalar
, EXxmm_md
, EXxEVexS
}, PREFIX_OPCODE
},
53 { "vucomisX", { XMScalar
, EXxmm_mq
, EXxEVexS
}, PREFIX_OPCODE
},
55 /* PREFIX_EVEX_0F2F */
57 { "vcomisX", { XMScalar
, EXxmm_md
, EXxEVexS
}, PREFIX_OPCODE
},
59 { "vcomisX", { XMScalar
, EXxmm_mq
, EXxEVexS
}, PREFIX_OPCODE
},
61 /* PREFIX_EVEX_0F51 */
63 { "vsqrtpX", { XM
, EXx
, EXxEVexR
}, PREFIX_OPCODE
},
64 { VEX_W_TABLE (EVEX_W_0F51_P_1
) },
65 { "vsqrtpX", { XM
, EXx
, EXxEVexR
}, PREFIX_OPCODE
},
66 { VEX_W_TABLE (EVEX_W_0F51_P_3
) },
68 /* PREFIX_EVEX_0F58 */
70 { "vaddpX", { XM
, Vex
, EXx
, EXxEVexR
}, PREFIX_OPCODE
},
71 { VEX_W_TABLE (EVEX_W_0F58_P_1
) },
72 { "vaddpX", { XM
, Vex
, EXx
, EXxEVexR
}, PREFIX_OPCODE
},
73 { VEX_W_TABLE (EVEX_W_0F58_P_3
) },
75 /* PREFIX_EVEX_0F59 */
77 { "vmulpX", { XM
, Vex
, EXx
, EXxEVexR
}, PREFIX_OPCODE
},
78 { VEX_W_TABLE (EVEX_W_0F59_P_1
) },
79 { "vmulpX", { XM
, Vex
, EXx
, EXxEVexR
}, PREFIX_OPCODE
},
80 { VEX_W_TABLE (EVEX_W_0F59_P_3
) },
82 /* PREFIX_EVEX_0F5A */
84 { VEX_W_TABLE (EVEX_W_0F5A_P_0
) },
85 { VEX_W_TABLE (EVEX_W_0F5A_P_1
) },
86 { VEX_W_TABLE (EVEX_W_0F5A_P_2
) },
87 { VEX_W_TABLE (EVEX_W_0F5A_P_3
) },
89 /* PREFIX_EVEX_0F5B */
91 { VEX_W_TABLE (EVEX_W_0F5B_P_0
) },
92 { VEX_W_TABLE (EVEX_W_0F5B_P_1
) },
93 { VEX_W_TABLE (EVEX_W_0F5B_P_2
) },
95 /* PREFIX_EVEX_0F5C */
97 { "vsubpX", { XM
, Vex
, EXx
, EXxEVexR
}, PREFIX_OPCODE
},
98 { VEX_W_TABLE (EVEX_W_0F5C_P_1
) },
99 { "vsubpX", { XM
, Vex
, EXx
, EXxEVexR
}, PREFIX_OPCODE
},
100 { VEX_W_TABLE (EVEX_W_0F5C_P_3
) },
102 /* PREFIX_EVEX_0F5D */
104 { "vminpX", { XM
, Vex
, EXx
, EXxEVexS
}, PREFIX_OPCODE
},
105 { VEX_W_TABLE (EVEX_W_0F5D_P_1
) },
106 { "vminpX", { XM
, Vex
, EXx
, EXxEVexS
}, PREFIX_OPCODE
},
107 { VEX_W_TABLE (EVEX_W_0F5D_P_3
) },
109 /* PREFIX_EVEX_0F5E */
111 { "vdivpX", { XM
, Vex
, EXx
, EXxEVexR
}, PREFIX_OPCODE
},
112 { VEX_W_TABLE (EVEX_W_0F5E_P_1
) },
113 { "vdivpX", { XM
, Vex
, EXx
, EXxEVexR
}, PREFIX_OPCODE
},
114 { VEX_W_TABLE (EVEX_W_0F5E_P_3
) },
116 /* PREFIX_EVEX_0F5F */
118 { "vmaxpX", { XM
, Vex
, EXx
, EXxEVexS
}, PREFIX_OPCODE
},
119 { VEX_W_TABLE (EVEX_W_0F5F_P_1
) },
120 { "vmaxpX", { XM
, Vex
, EXx
, EXxEVexS
}, PREFIX_OPCODE
},
121 { VEX_W_TABLE (EVEX_W_0F5F_P_3
) },
123 /* PREFIX_EVEX_0F62 */
127 { VEX_W_TABLE (EVEX_W_0F62_P_2
) },
129 /* PREFIX_EVEX_0F64 */
133 { "vpcmpgtb", { XMask
, Vex
, EXx
}, 0 },
135 /* PREFIX_EVEX_0F65 */
139 { "vpcmpgtw", { XMask
, Vex
, EXx
}, 0 },
141 /* PREFIX_EVEX_0F66 */
145 { VEX_W_TABLE (EVEX_W_0F66_P_2
) },
147 /* PREFIX_EVEX_0F6A */
151 { VEX_W_TABLE (EVEX_W_0F6A_P_2
) },
153 /* PREFIX_EVEX_0F6B */
157 { VEX_W_TABLE (EVEX_W_0F6B_P_2
) },
159 /* PREFIX_EVEX_0F6C */
163 { VEX_W_TABLE (EVEX_W_0F6C_P_2
) },
165 /* PREFIX_EVEX_0F6D */
169 { VEX_W_TABLE (EVEX_W_0F6D_P_2
) },
171 /* PREFIX_EVEX_0F6E */
175 { EVEX_LEN_TABLE (EVEX_LEN_0F6E_P_2
) },
177 /* PREFIX_EVEX_0F6F */
180 { VEX_W_TABLE (EVEX_W_0F6F_P_1
) },
181 { VEX_W_TABLE (EVEX_W_0F6F_P_2
) },
182 { VEX_W_TABLE (EVEX_W_0F6F_P_3
) },
184 /* PREFIX_EVEX_0F70 */
187 { "vpshufhw", { XM
, EXx
, Ib
}, 0 },
188 { VEX_W_TABLE (EVEX_W_0F70_P_2
) },
189 { "vpshuflw", { XM
, EXx
, Ib
}, 0 },
191 /* PREFIX_EVEX_0F71_REG_2 */
195 { "vpsrlw", { Vex
, EXx
, Ib
}, 0 },
197 /* PREFIX_EVEX_0F71_REG_4 */
201 { "vpsraw", { Vex
, EXx
, Ib
}, 0 },
203 /* PREFIX_EVEX_0F71_REG_6 */
207 { "vpsllw", { Vex
, EXx
, Ib
}, 0 },
209 /* PREFIX_EVEX_0F72_REG_0 */
213 { "vpror%LW", { Vex
, EXx
, Ib
}, 0 },
215 /* PREFIX_EVEX_0F72_REG_1 */
219 { "vprol%LW", { Vex
, EXx
, Ib
}, 0 },
221 /* PREFIX_EVEX_0F72_REG_2 */
225 { VEX_W_TABLE (EVEX_W_0F72_R_2_P_2
) },
227 /* PREFIX_EVEX_0F72_REG_4 */
231 { "vpsra%LW", { Vex
, EXx
, Ib
}, 0 },
233 /* PREFIX_EVEX_0F72_REG_6 */
237 { VEX_W_TABLE (EVEX_W_0F72_R_6_P_2
) },
239 /* PREFIX_EVEX_0F73_REG_2 */
243 { VEX_W_TABLE (EVEX_W_0F73_R_2_P_2
) },
245 /* PREFIX_EVEX_0F73_REG_3 */
249 { "vpsrldq", { Vex
, EXx
, Ib
}, 0 },
251 /* PREFIX_EVEX_0F73_REG_6 */
255 { VEX_W_TABLE (EVEX_W_0F73_R_6_P_2
) },
257 /* PREFIX_EVEX_0F73_REG_7 */
261 { "vpslldq", { Vex
, EXx
, Ib
}, 0 },
263 /* PREFIX_EVEX_0F74 */
267 { "vpcmpeqb", { XMask
, Vex
, EXx
}, 0 },
269 /* PREFIX_EVEX_0F75 */
273 { "vpcmpeqw", { XMask
, Vex
, EXx
}, 0 },
275 /* PREFIX_EVEX_0F76 */
279 { VEX_W_TABLE (EVEX_W_0F76_P_2
) },
281 /* PREFIX_EVEX_0F78 */
283 { VEX_W_TABLE (EVEX_W_0F78_P_0
) },
284 { "vcvttss2usi", { Gdq
, EXxmm_md
, EXxEVexS
}, 0 },
285 { VEX_W_TABLE (EVEX_W_0F78_P_2
) },
286 { "vcvttsd2usi", { Gdq
, EXxmm_mq
, EXxEVexS
}, 0 },
288 /* PREFIX_EVEX_0F79 */
290 { VEX_W_TABLE (EVEX_W_0F79_P_0
) },
291 { "vcvtss2usi", { Gdq
, EXxmm_md
, EXxEVexR
}, 0 },
292 { VEX_W_TABLE (EVEX_W_0F79_P_2
) },
293 { "vcvtsd2usi", { Gdq
, EXxmm_mq
, EXxEVexR
}, 0 },
295 /* PREFIX_EVEX_0F7A */
298 { VEX_W_TABLE (EVEX_W_0F7A_P_1
) },
299 { VEX_W_TABLE (EVEX_W_0F7A_P_2
) },
300 { VEX_W_TABLE (EVEX_W_0F7A_P_3
) },
302 /* PREFIX_EVEX_0F7B */
305 { "vcvtusi2ss%LQ", { XMScalar
, VexScalar
, EXxEVexR
, Edq
}, 0 },
306 { VEX_W_TABLE (EVEX_W_0F7B_P_2
) },
307 { VEX_W_TABLE (EVEX_W_0F7B_P_3
) },
309 /* PREFIX_EVEX_0F7E */
312 { EVEX_LEN_TABLE (EVEX_LEN_0F7E_P_1
) },
313 { EVEX_LEN_TABLE (EVEX_LEN_0F7E_P_2
) },
315 /* PREFIX_EVEX_0F7F */
318 { VEX_W_TABLE (EVEX_W_0F7F_P_1
) },
319 { VEX_W_TABLE (EVEX_W_0F7F_P_2
) },
320 { VEX_W_TABLE (EVEX_W_0F7F_P_3
) },
322 /* PREFIX_EVEX_0FC2 */
324 { "vcmppX", { XMask
, Vex
, EXx
, EXxEVexS
, VCMP
}, PREFIX_OPCODE
},
325 { VEX_W_TABLE (EVEX_W_0FC2_P_1
) },
326 { "vcmppX", { XMask
, Vex
, EXx
, EXxEVexS
, VCMP
}, PREFIX_OPCODE
},
327 { VEX_W_TABLE (EVEX_W_0FC2_P_3
) },
329 /* PREFIX_EVEX_0FC4 */
333 { EVEX_LEN_TABLE (EVEX_LEN_0FC4_P_2
) },
335 /* PREFIX_EVEX_0FC5 */
339 { EVEX_LEN_TABLE (EVEX_LEN_0FC5_P_2
) },
341 /* PREFIX_EVEX_0FD2 */
345 { VEX_W_TABLE (EVEX_W_0FD2_P_2
) },
347 /* PREFIX_EVEX_0FD3 */
351 { VEX_W_TABLE (EVEX_W_0FD3_P_2
) },
353 /* PREFIX_EVEX_0FD4 */
357 { VEX_W_TABLE (EVEX_W_0FD4_P_2
) },
359 /* PREFIX_EVEX_0FD6 */
363 { EVEX_LEN_TABLE (EVEX_LEN_0FD6_P_2
) },
365 /* PREFIX_EVEX_0FDB */
369 { "vpand%LW", { XM
, Vex
, EXx
}, 0 },
371 /* PREFIX_EVEX_0FDF */
375 { "vpandn%LW", { XM
, Vex
, EXx
}, 0 },
377 /* PREFIX_EVEX_0FE2 */
381 { "vpsra%LW", { XM
, Vex
, EXxmm
}, 0 },
383 /* PREFIX_EVEX_0FE6 */
386 { VEX_W_TABLE (EVEX_W_0FE6_P_1
) },
387 { VEX_W_TABLE (EVEX_W_0FE6_P_2
) },
388 { VEX_W_TABLE (EVEX_W_0FE6_P_3
) },
390 /* PREFIX_EVEX_0FE7 */
394 { VEX_W_TABLE (EVEX_W_0FE7_P_2
) },
396 /* PREFIX_EVEX_0FEB */
400 { "vpor%LW", { XM
, Vex
, EXx
}, 0 },
402 /* PREFIX_EVEX_0FEF */
406 { "vpxor%LW", { XM
, Vex
, EXx
}, 0 },
408 /* PREFIX_EVEX_0FF2 */
412 { VEX_W_TABLE (EVEX_W_0FF2_P_2
) },
414 /* PREFIX_EVEX_0FF3 */
418 { VEX_W_TABLE (EVEX_W_0FF3_P_2
) },
420 /* PREFIX_EVEX_0FF4 */
424 { VEX_W_TABLE (EVEX_W_0FF4_P_2
) },
426 /* PREFIX_EVEX_0FFA */
430 { VEX_W_TABLE (EVEX_W_0FFA_P_2
) },
432 /* PREFIX_EVEX_0FFB */
436 { VEX_W_TABLE (EVEX_W_0FFB_P_2
) },
438 /* PREFIX_EVEX_0FFE */
442 { VEX_W_TABLE (EVEX_W_0FFE_P_2
) },
444 /* PREFIX_EVEX_0F380D */
448 { VEX_W_TABLE (EVEX_W_0F380D_P_2
) },
450 /* PREFIX_EVEX_0F3810 */
453 { VEX_W_TABLE (EVEX_W_0F3810_P_1
) },
454 { VEX_W_TABLE (EVEX_W_0F3810_P_2
) },
456 /* PREFIX_EVEX_0F3811 */
459 { VEX_W_TABLE (EVEX_W_0F3811_P_1
) },
460 { VEX_W_TABLE (EVEX_W_0F3811_P_2
) },
462 /* PREFIX_EVEX_0F3812 */
465 { VEX_W_TABLE (EVEX_W_0F3812_P_1
) },
466 { VEX_W_TABLE (EVEX_W_0F3812_P_2
) },
468 /* PREFIX_EVEX_0F3813 */
471 { VEX_W_TABLE (EVEX_W_0F3813_P_1
) },
472 { VEX_W_TABLE (EVEX_W_0F3813_P_2
) },
474 /* PREFIX_EVEX_0F3814 */
477 { VEX_W_TABLE (EVEX_W_0F3814_P_1
) },
478 { "vprorv%LW", { XM
, Vex
, EXx
}, 0 },
480 /* PREFIX_EVEX_0F3815 */
483 { VEX_W_TABLE (EVEX_W_0F3815_P_1
) },
484 { "vprolv%LW", { XM
, Vex
, EXx
}, 0 },
486 /* PREFIX_EVEX_0F3816 */
490 { "vpermp%XW", { XM
, Vex
, EXx
}, 0 },
492 /* PREFIX_EVEX_0F3819 */
496 { VEX_W_TABLE (EVEX_W_0F3819_P_2
) },
498 /* PREFIX_EVEX_0F381A */
502 { VEX_W_TABLE (EVEX_W_0F381A_P_2
) },
504 /* PREFIX_EVEX_0F381B */
508 { VEX_W_TABLE (EVEX_W_0F381B_P_2
) },
510 /* PREFIX_EVEX_0F381E */
514 { VEX_W_TABLE (EVEX_W_0F381E_P_2
) },
516 /* PREFIX_EVEX_0F381F */
520 { VEX_W_TABLE (EVEX_W_0F381F_P_2
) },
522 /* PREFIX_EVEX_0F3820 */
525 { VEX_W_TABLE (EVEX_W_0F3820_P_1
) },
526 { "vpmovsxbw", { XM
, EXxmmq
}, 0 },
528 /* PREFIX_EVEX_0F3821 */
531 { VEX_W_TABLE (EVEX_W_0F3821_P_1
) },
532 { "vpmovsxbd", { XM
, EXxmmqd
}, 0 },
534 /* PREFIX_EVEX_0F3822 */
537 { VEX_W_TABLE (EVEX_W_0F3822_P_1
) },
538 { "vpmovsxbq", { XM
, EXxmmdw
}, 0 },
540 /* PREFIX_EVEX_0F3823 */
543 { VEX_W_TABLE (EVEX_W_0F3823_P_1
) },
544 { "vpmovsxwd", { XM
, EXxmmq
}, 0 },
546 /* PREFIX_EVEX_0F3824 */
549 { VEX_W_TABLE (EVEX_W_0F3824_P_1
) },
550 { "vpmovsxwq", { XM
, EXxmmqd
}, 0 },
552 /* PREFIX_EVEX_0F3825 */
555 { VEX_W_TABLE (EVEX_W_0F3825_P_1
) },
556 { VEX_W_TABLE (EVEX_W_0F3825_P_2
) },
558 /* PREFIX_EVEX_0F3826 */
561 { VEX_W_TABLE (EVEX_W_0F3826_P_1
) },
562 { VEX_W_TABLE (EVEX_W_0F3826_P_2
) },
564 /* PREFIX_EVEX_0F3827 */
567 { "vptestnm%LW", { XMask
, Vex
, EXx
}, 0 },
568 { "vptestm%LW", { XMask
, Vex
, EXx
}, 0 },
570 /* PREFIX_EVEX_0F3828 */
573 { VEX_W_TABLE (EVEX_W_0F3828_P_1
) },
574 { VEX_W_TABLE (EVEX_W_0F3828_P_2
) },
576 /* PREFIX_EVEX_0F3829 */
579 { VEX_W_TABLE (EVEX_W_0F3829_P_1
) },
580 { VEX_W_TABLE (EVEX_W_0F3829_P_2
) },
582 /* PREFIX_EVEX_0F382A */
585 { VEX_W_TABLE (EVEX_W_0F382A_P_1
) },
586 { VEX_W_TABLE (EVEX_W_0F382A_P_2
) },
588 /* PREFIX_EVEX_0F382B */
592 { VEX_W_TABLE (EVEX_W_0F382B_P_2
) },
594 /* PREFIX_EVEX_0F382C */
598 { "vscalefp%XW", { XM
, Vex
, EXx
, EXxEVexR
}, 0 },
600 /* PREFIX_EVEX_0F382D */
604 { "vscalefs%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
, EXxEVexR
}, 0 },
606 /* PREFIX_EVEX_0F3830 */
609 { VEX_W_TABLE (EVEX_W_0F3830_P_1
) },
610 { "vpmovzxbw", { XM
, EXxmmq
}, 0 },
612 /* PREFIX_EVEX_0F3831 */
615 { VEX_W_TABLE (EVEX_W_0F3831_P_1
) },
616 { "vpmovzxbd", { XM
, EXxmmqd
}, 0 },
618 /* PREFIX_EVEX_0F3832 */
621 { VEX_W_TABLE (EVEX_W_0F3832_P_1
) },
622 { "vpmovzxbq", { XM
, EXxmmdw
}, 0 },
624 /* PREFIX_EVEX_0F3833 */
627 { VEX_W_TABLE (EVEX_W_0F3833_P_1
) },
628 { "vpmovzxwd", { XM
, EXxmmq
}, 0 },
630 /* PREFIX_EVEX_0F3834 */
633 { VEX_W_TABLE (EVEX_W_0F3834_P_1
) },
634 { "vpmovzxwq", { XM
, EXxmmqd
}, 0 },
636 /* PREFIX_EVEX_0F3835 */
639 { VEX_W_TABLE (EVEX_W_0F3835_P_1
) },
640 { VEX_W_TABLE (EVEX_W_0F3835_P_2
) },
642 /* PREFIX_EVEX_0F3836 */
646 { "vperm%LW", { XM
, Vex
, EXx
}, 0 },
648 /* PREFIX_EVEX_0F3837 */
652 { VEX_W_TABLE (EVEX_W_0F3837_P_2
) },
654 /* PREFIX_EVEX_0F3838 */
657 { VEX_W_TABLE (EVEX_W_0F3838_P_1
) },
658 { "vpminsb", { XM
, Vex
, EXx
}, 0 },
660 /* PREFIX_EVEX_0F3839 */
663 { VEX_W_TABLE (EVEX_W_0F3839_P_1
) },
664 { "vpmins%LW", { XM
, Vex
, EXx
}, 0 },
666 /* PREFIX_EVEX_0F383A */
669 { VEX_W_TABLE (EVEX_W_0F383A_P_1
) },
670 { "vpminuw", { XM
, Vex
, EXx
}, 0 },
672 /* PREFIX_EVEX_0F383B */
676 { "vpminu%LW", { XM
, Vex
, EXx
}, 0 },
678 /* PREFIX_EVEX_0F383D */
682 { "vpmaxs%LW", { XM
, Vex
, EXx
}, 0 },
684 /* PREFIX_EVEX_0F383F */
688 { "vpmaxu%LW", { XM
, Vex
, EXx
}, 0 },
690 /* PREFIX_EVEX_0F3840 */
694 { VEX_W_TABLE (EVEX_W_0F3840_P_2
) },
696 /* PREFIX_EVEX_0F3842 */
700 { "vgetexpp%XW", { XM
, EXx
, EXxEVexS
}, 0 },
702 /* PREFIX_EVEX_0F3843 */
706 { "vgetexps%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
, EXxEVexS
}, 0 },
708 /* PREFIX_EVEX_0F3844 */
712 { "vplzcnt%LW", { XM
, EXx
}, 0 },
714 /* PREFIX_EVEX_0F3845 */
718 { "vpsrlv%LW", { XM
, Vex
, EXx
}, 0 },
720 /* PREFIX_EVEX_0F3846 */
724 { "vpsrav%LW", { XM
, Vex
, EXx
}, 0 },
726 /* PREFIX_EVEX_0F3847 */
730 { "vpsllv%LW", { XM
, Vex
, EXx
}, 0 },
732 /* PREFIX_EVEX_0F384C */
736 { "vrcp14p%XW", { XM
, EXx
}, 0 },
738 /* PREFIX_EVEX_0F384D */
742 { "vrcp14s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
744 /* PREFIX_EVEX_0F384E */
748 { "vrsqrt14p%XW", { XM
, EXx
}, 0 },
750 /* PREFIX_EVEX_0F384F */
754 { "vrsqrt14s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
756 /* PREFIX_EVEX_0F3850 */
760 { "vpdpbusd", { XM
, Vex
, EXx
}, 0 },
762 /* PREFIX_EVEX_0F3851 */
766 { "vpdpbusds", { XM
, Vex
, EXx
}, 0 },
768 /* PREFIX_EVEX_0F3852 */
771 { VEX_W_TABLE (EVEX_W_0F3852_P_1
) },
772 { "vpdpwssd", { XM
, Vex
, EXx
}, 0 },
773 { "vp4dpwssd", { XM
, Vex
, EXxmm
}, 0 },
775 /* PREFIX_EVEX_0F3853 */
779 { "vpdpwssds", { XM
, Vex
, EXx
}, 0 },
780 { "vp4dpwssds", { XM
, Vex
, EXxmm
}, 0 },
782 /* PREFIX_EVEX_0F3854 */
786 { VEX_W_TABLE (EVEX_W_0F3854_P_2
) },
788 /* PREFIX_EVEX_0F3855 */
792 { VEX_W_TABLE (EVEX_W_0F3855_P_2
) },
794 /* PREFIX_EVEX_0F3859 */
798 { VEX_W_TABLE (EVEX_W_0F3859_P_2
) },
800 /* PREFIX_EVEX_0F385A */
804 { VEX_W_TABLE (EVEX_W_0F385A_P_2
) },
806 /* PREFIX_EVEX_0F385B */
810 { VEX_W_TABLE (EVEX_W_0F385B_P_2
) },
812 /* PREFIX_EVEX_0F3862 */
816 { VEX_W_TABLE (EVEX_W_0F3862_P_2
) },
818 /* PREFIX_EVEX_0F3863 */
822 { VEX_W_TABLE (EVEX_W_0F3863_P_2
) },
824 /* PREFIX_EVEX_0F3864 */
828 { "vpblendm%LW", { XM
, Vex
, EXx
}, 0 },
830 /* PREFIX_EVEX_0F3865 */
834 { "vblendmp%XW", { XM
, Vex
, EXx
}, 0 },
836 /* PREFIX_EVEX_0F3866 */
840 { VEX_W_TABLE (EVEX_W_0F3866_P_2
) },
842 /* PREFIX_EVEX_0F3868 */
847 { VEX_W_TABLE (EVEX_W_0F3868_P_3
) },
849 /* PREFIX_EVEX_0F3870 */
853 { VEX_W_TABLE (EVEX_W_0F3870_P_2
) },
855 /* PREFIX_EVEX_0F3871 */
859 { VEX_W_TABLE (EVEX_W_0F3871_P_2
) },
861 /* PREFIX_EVEX_0F3872 */
864 { VEX_W_TABLE (EVEX_W_0F3872_P_1
) },
865 { VEX_W_TABLE (EVEX_W_0F3872_P_2
) },
866 { VEX_W_TABLE (EVEX_W_0F3872_P_3
) },
868 /* PREFIX_EVEX_0F3873 */
872 { VEX_W_TABLE (EVEX_W_0F3873_P_2
) },
874 /* PREFIX_EVEX_0F3875 */
878 { VEX_W_TABLE (EVEX_W_0F3875_P_2
) },
880 /* PREFIX_EVEX_0F3876 */
884 { "vpermi2%LW", { XM
, Vex
, EXx
}, 0 },
886 /* PREFIX_EVEX_0F3877 */
890 { "vpermi2p%XW", { XM
, Vex
, EXx
}, 0 },
892 /* PREFIX_EVEX_0F387A */
896 { VEX_W_TABLE (EVEX_W_0F387A_P_2
) },
898 /* PREFIX_EVEX_0F387B */
902 { VEX_W_TABLE (EVEX_W_0F387B_P_2
) },
904 /* PREFIX_EVEX_0F387C */
908 { "vpbroadcastK", { XM
, Rdq
}, 0 },
910 /* PREFIX_EVEX_0F387D */
914 { VEX_W_TABLE (EVEX_W_0F387D_P_2
) },
916 /* PREFIX_EVEX_0F387E */
920 { "vpermt2%LW", { XM
, Vex
, EXx
}, 0 },
922 /* PREFIX_EVEX_0F387F */
926 { "vpermt2p%XW", { XM
, Vex
, EXx
}, 0 },
928 /* PREFIX_EVEX_0F3883 */
932 { VEX_W_TABLE (EVEX_W_0F3883_P_2
) },
934 /* PREFIX_EVEX_0F3888 */
938 { "vexpandp%XW", { XM
, EXEvexXGscat
}, 0 },
940 /* PREFIX_EVEX_0F3889 */
944 { "vpexpand%LW", { XM
, EXEvexXGscat
}, 0 },
946 /* PREFIX_EVEX_0F388A */
950 { "vcompressp%XW", { EXEvexXGscat
, XM
}, 0 },
952 /* PREFIX_EVEX_0F388B */
956 { "vpcompress%LW", { EXEvexXGscat
, XM
}, 0 },
958 /* PREFIX_EVEX_0F388D */
962 { VEX_W_TABLE (EVEX_W_0F388D_P_2
) },
964 /* PREFIX_EVEX_0F388F */
968 { "vpshufbitqmb", { XMask
, Vex
, EXx
}, 0 },
970 /* PREFIX_EVEX_0F3890 */
974 { "vpgatherd%LW", { XM
, MVexVSIBDWpX
}, 0 },
976 /* PREFIX_EVEX_0F3891 */
980 { VEX_W_TABLE (EVEX_W_0F3891_P_2
) },
982 /* PREFIX_EVEX_0F3892 */
986 { "vgatherdp%XW", { XM
, MVexVSIBDWpX
}, 0 },
988 /* PREFIX_EVEX_0F3893 */
992 { VEX_W_TABLE (EVEX_W_0F3893_P_2
) },
994 /* PREFIX_EVEX_0F389A */
998 { "vfmsub132p%XW", { XM
, Vex
, EXx
, EXxEVexR
}, 0 },
999 { "v4fmaddps", { XM
, Vex
, Mxmm
}, 0 },
1001 /* PREFIX_EVEX_0F389B */
1005 { "vfmsub132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
, EXxEVexR
}, 0 },
1006 { "v4fmaddss", { XMScalar
, VexScalar
, Mxmm
}, 0 },
1008 /* PREFIX_EVEX_0F38A0 */
1012 { "vpscatterd%LW", { MVexVSIBDWpX
, XM
}, 0 },
1014 /* PREFIX_EVEX_0F38A1 */
1018 { VEX_W_TABLE (EVEX_W_0F38A1_P_2
) },
1020 /* PREFIX_EVEX_0F38A2 */
1024 { "vscatterdp%XW", { MVexVSIBDWpX
, XM
}, 0 },
1026 /* PREFIX_EVEX_0F38A3 */
1030 { VEX_W_TABLE (EVEX_W_0F38A3_P_2
) },
1032 /* PREFIX_EVEX_0F38AA */
1036 { "vfmsub213p%XW", { XM
, Vex
, EXx
, EXxEVexR
}, 0 },
1037 { "v4fnmaddps", { XM
, Vex
, Mxmm
}, 0 },
1039 /* PREFIX_EVEX_0F38AB */
1043 { "vfmsub213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
, EXxEVexR
}, 0 },
1044 { "v4fnmaddss", { XMScalar
, VexScalar
, Mxmm
}, 0 },
1046 /* PREFIX_EVEX_0F38B4 */
1050 { "vpmadd52luq", { XM
, Vex
, EXx
}, 0 },
1052 /* PREFIX_EVEX_0F38B5 */
1056 { "vpmadd52huq", { XM
, Vex
, EXx
}, 0 },
1058 /* PREFIX_EVEX_0F38C4 */
1062 { "vpconflict%LW", { XM
, EXx
}, 0 },
1064 /* PREFIX_EVEX_0F38C6_REG_1 */
1068 { EVEX_LEN_TABLE (EVEX_LEN_0F38C6_REG_1_PREFIX_2
) },
1070 /* PREFIX_EVEX_0F38C6_REG_2 */
1074 { EVEX_LEN_TABLE (EVEX_LEN_0F38C6_REG_2_PREFIX_2
) },
1076 /* PREFIX_EVEX_0F38C6_REG_5 */
1080 { EVEX_LEN_TABLE (EVEX_LEN_0F38C6_REG_5_PREFIX_2
) },
1082 /* PREFIX_EVEX_0F38C6_REG_6 */
1086 { EVEX_LEN_TABLE (EVEX_LEN_0F38C6_REG_6_PREFIX_2
) },
1088 /* PREFIX_EVEX_0F38C7_REG_1 */
1092 { VEX_W_TABLE (EVEX_W_0F38C7_R_1_P_2
) },
1094 /* PREFIX_EVEX_0F38C7_REG_2 */
1098 { VEX_W_TABLE (EVEX_W_0F38C7_R_2_P_2
) },
1100 /* PREFIX_EVEX_0F38C7_REG_5 */
1104 { VEX_W_TABLE (EVEX_W_0F38C7_R_5_P_2
) },
1106 /* PREFIX_EVEX_0F38C7_REG_6 */
1110 { VEX_W_TABLE (EVEX_W_0F38C7_R_6_P_2
) },
1112 /* PREFIX_EVEX_0F38C8 */
1116 { "vexp2p%XW", { XM
, EXx
, EXxEVexS
}, 0 },
1118 /* PREFIX_EVEX_0F38CA */
1122 { "vrcp28p%XW", { XM
, EXx
, EXxEVexS
}, 0 },
1124 /* PREFIX_EVEX_0F38CB */
1128 { "vrcp28s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
, EXxEVexS
}, 0 },
1130 /* PREFIX_EVEX_0F38CC */
1134 { "vrsqrt28p%XW", { XM
, EXx
, EXxEVexS
}, 0 },
1136 /* PREFIX_EVEX_0F38CD */
1140 { "vrsqrt28s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
, EXxEVexS
}, 0 },
1142 /* PREFIX_EVEX_0F3A00 */
1146 { VEX_W_TABLE (EVEX_W_0F3A00_P_2
) },
1148 /* PREFIX_EVEX_0F3A01 */
1152 { VEX_W_TABLE (EVEX_W_0F3A01_P_2
) },
1154 /* PREFIX_EVEX_0F3A03 */
1158 { "valign%LW", { XM
, Vex
, EXx
, Ib
}, 0 },
1160 /* PREFIX_EVEX_0F3A05 */
1164 { VEX_W_TABLE (EVEX_W_0F3A05_P_2
) },
1166 /* PREFIX_EVEX_0F3A08 */
1170 { VEX_W_TABLE (EVEX_W_0F3A08_P_2
) },
1172 /* PREFIX_EVEX_0F3A09 */
1176 { VEX_W_TABLE (EVEX_W_0F3A09_P_2
) },
1178 /* PREFIX_EVEX_0F3A0A */
1182 { VEX_W_TABLE (EVEX_W_0F3A0A_P_2
) },
1184 /* PREFIX_EVEX_0F3A0B */
1188 { VEX_W_TABLE (EVEX_W_0F3A0B_P_2
) },
1190 /* PREFIX_EVEX_0F3A14 */
1194 { EVEX_LEN_TABLE (EVEX_LEN_0F3A14_P_2
) },
1196 /* PREFIX_EVEX_0F3A15 */
1200 { EVEX_LEN_TABLE (EVEX_LEN_0F3A15_P_2
) },
1202 /* PREFIX_EVEX_0F3A16 */
1206 { EVEX_LEN_TABLE (EVEX_LEN_0F3A16_P_2
) },
1208 /* PREFIX_EVEX_0F3A17 */
1212 { EVEX_LEN_TABLE (EVEX_LEN_0F3A17_P_2
) },
1214 /* PREFIX_EVEX_0F3A18 */
1218 { VEX_W_TABLE (EVEX_W_0F3A18_P_2
) },
1220 /* PREFIX_EVEX_0F3A19 */
1224 { VEX_W_TABLE (EVEX_W_0F3A19_P_2
) },
1226 /* PREFIX_EVEX_0F3A1A */
1230 { VEX_W_TABLE (EVEX_W_0F3A1A_P_2
) },
1232 /* PREFIX_EVEX_0F3A1B */
1236 { VEX_W_TABLE (EVEX_W_0F3A1B_P_2
) },
1238 /* PREFIX_EVEX_0F3A1E */
1242 { "vpcmpu%LW", { XMask
, Vex
, EXx
, VPCMP
}, 0 },
1244 /* PREFIX_EVEX_0F3A1F */
1248 { "vpcmp%LW", { XMask
, Vex
, EXx
, VPCMP
}, 0 },
1250 /* PREFIX_EVEX_0F3A20 */
1254 { EVEX_LEN_TABLE (EVEX_LEN_0F3A20_P_2
) },
1256 /* PREFIX_EVEX_0F3A21 */
1260 { VEX_W_TABLE (EVEX_W_0F3A21_P_2
) },
1262 /* PREFIX_EVEX_0F3A22 */
1266 { EVEX_LEN_TABLE (EVEX_LEN_0F3A22_P_2
) },
1268 /* PREFIX_EVEX_0F3A23 */
1272 { VEX_W_TABLE (EVEX_W_0F3A23_P_2
) },
1274 /* PREFIX_EVEX_0F3A25 */
1278 { "vpternlog%LW", { XM
, Vex
, EXx
, Ib
}, 0 },
1280 /* PREFIX_EVEX_0F3A26 */
1284 { "vgetmantp%XW", { XM
, EXx
, EXxEVexS
, Ib
}, 0 },
1286 /* PREFIX_EVEX_0F3A27 */
1290 { "vgetmants%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
, EXxEVexS
, Ib
}, 0 },
1292 /* PREFIX_EVEX_0F3A38 */
1296 { VEX_W_TABLE (EVEX_W_0F3A38_P_2
) },
1298 /* PREFIX_EVEX_0F3A39 */
1302 { VEX_W_TABLE (EVEX_W_0F3A39_P_2
) },
1304 /* PREFIX_EVEX_0F3A3A */
1308 { VEX_W_TABLE (EVEX_W_0F3A3A_P_2
) },
1310 /* PREFIX_EVEX_0F3A3B */
1314 { VEX_W_TABLE (EVEX_W_0F3A3B_P_2
) },
1316 /* PREFIX_EVEX_0F3A3E */
1320 { VEX_W_TABLE (EVEX_W_0F3A3E_P_2
) },
1322 /* PREFIX_EVEX_0F3A3F */
1326 { VEX_W_TABLE (EVEX_W_0F3A3F_P_2
) },
1328 /* PREFIX_EVEX_0F3A42 */
1332 { VEX_W_TABLE (EVEX_W_0F3A42_P_2
) },
1334 /* PREFIX_EVEX_0F3A43 */
1338 { VEX_W_TABLE (EVEX_W_0F3A43_P_2
) },
1340 /* PREFIX_EVEX_0F3A50 */
1344 { VEX_W_TABLE (EVEX_W_0F3A50_P_2
) },
1346 /* PREFIX_EVEX_0F3A51 */
1350 { VEX_W_TABLE (EVEX_W_0F3A51_P_2
) },
1352 /* PREFIX_EVEX_0F3A54 */
1356 { "vfixupimmp%XW", { XM
, Vex
, EXx
, EXxEVexS
, Ib
}, 0 },
1358 /* PREFIX_EVEX_0F3A55 */
1362 { "vfixupimms%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
, EXxEVexS
, Ib
}, 0 },
1364 /* PREFIX_EVEX_0F3A56 */
1368 { VEX_W_TABLE (EVEX_W_0F3A56_P_2
) },
1370 /* PREFIX_EVEX_0F3A57 */
1374 { VEX_W_TABLE (EVEX_W_0F3A57_P_2
) },
1376 /* PREFIX_EVEX_0F3A66 */
1380 { VEX_W_TABLE (EVEX_W_0F3A66_P_2
) },
1382 /* PREFIX_EVEX_0F3A67 */
1386 { VEX_W_TABLE (EVEX_W_0F3A67_P_2
) },
1388 /* PREFIX_EVEX_0F3A70 */
1392 { VEX_W_TABLE (EVEX_W_0F3A70_P_2
) },
1394 /* PREFIX_EVEX_0F3A71 */
1398 { VEX_W_TABLE (EVEX_W_0F3A71_P_2
) },
1400 /* PREFIX_EVEX_0F3A72 */
1404 { VEX_W_TABLE (EVEX_W_0F3A72_P_2
) },
1406 /* PREFIX_EVEX_0F3A73 */
1410 { VEX_W_TABLE (EVEX_W_0F3A73_P_2
) },