opcodes/i386-dis.c

   1 /* Print i386 instructions for GDB, the GNU debugger.
   2    Copyright (C) 1988-2020 Free Software Foundation, Inc.
   3
   4    This file is part of the GNU opcodes library.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    It is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program; if not, write to the Free Software
  18    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  19    MA 02110-1301, USA.  */
  20
  21
  22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
  23    July 1988
  24     modified by John Hassey (hassey@dg-rtp.dg.com)
  25     x86-64 support added by Jan Hubicka (jh@suse.cz)
  26     VIA PadLock support by Michal Ludvig (mludvig@suse.cz).  */
  27
  28 /* The main tables describing the instructions is essentially a copy
  29    of the "Opcode Map" chapter (Appendix A) of the Intel 80386
  30    Programmers Manual.  Usually, there is a capital letter, followed
  31    by a small letter.  The capital letter tell the addressing mode,
  32    and the small letter tells about the operand size.  Refer to
  33    the Intel manual for details.  */
  34
  35 #include "sysdep.h"
  36 #include "disassemble.h"
  37 #include "opintl.h"
  38 #include "opcode/i386.h"
  39 #include "libiberty.h"
  40 #include "safe-ctype.h"
  41
  42 #include <setjmp.h>
  43
  44 static int print_insn (bfd_vma, disassemble_info *);
  45 static void dofloat (int);
  46 static void OP_ST (int, int);
  47 static void OP_STi (int, int);
  48 static int putop (const char *, int);
  49 static void oappend (const char *);
  50 static void append_seg (void);
  51 static void OP_indirE (int, int);
  52 static void print_operand_value (char *, int, bfd_vma);
  53 static void OP_E_register (int, int);
  54 static void OP_E_memory (int, int);
  55 static void print_displacement (char *, bfd_vma);
  56 static void OP_E (int, int);
  57 static void OP_G (int, int);
  58 static bfd_vma get64 (void);
  59 static bfd_signed_vma get32 (void);
  60 static bfd_signed_vma get32s (void);
  61 static int get16 (void);
  62 static void set_op (bfd_vma, int);
  63 static void OP_Skip_MODRM (int, int);
  64 static void OP_REG (int, int);
  65 static void OP_IMREG (int, int);
  66 static void OP_I (int, int);
  67 static void OP_I64 (int, int);
  68 static void OP_sI (int, int);
  69 static void OP_J (int, int);
  70 static void OP_SEG (int, int);
  71 static void OP_DIR (int, int);
  72 static void OP_OFF (int, int);
  73 static void OP_OFF64 (int, int);
  74 static void ptr_reg (int, int);
  75 static void OP_ESreg (int, int);
  76 static void OP_DSreg (int, int);
  77 static void OP_C (int, int);
  78 static void OP_D (int, int);
  79 static void OP_T (int, int);
  80 static void OP_R (int, int);
  81 static void OP_MMX (int, int);
  82 static void OP_XMM (int, int);
  83 static void OP_EM (int, int);
  84 static void OP_EX (int, int);
  85 static void OP_EMC (int,int);
  86 static void OP_MXC (int,int);
  87 static void OP_MS (int, int);
  88 static void OP_XS (int, int);
  89 static void OP_M (int, int);
  90 static void OP_VEX (int, int);
  91 static void OP_EX_Vex (int, int);
  92 static void OP_EX_VexW (int, int);
  93 static void OP_EX_VexImmW (int, int);
  94 static void OP_XMM_Vex (int, int);
  95 static void OP_XMM_VexW (int, int);
  96 static void OP_Rounding (int, int);
  97 static void OP_REG_VexI4 (int, int);
  98 static void PCLMUL_Fixup (int, int);
  99 static void VCMP_Fixup (int, int);
 100 static void VPCMP_Fixup (int, int);
 101 static void VPCOM_Fixup (int, int);
 102 static void OP_0f07 (int, int);
 103 static void OP_Monitor (int, int);
 104 static void OP_Mwait (int, int);
 105 static void NOP_Fixup1 (int, int);
 106 static void NOP_Fixup2 (int, int);
 107 static void OP_3DNowSuffix (int, int);
 108 static void CMP_Fixup (int, int);
 109 static void BadOp (void);
 110 static void REP_Fixup (int, int);
 111 static void SEP_Fixup (int, int);
 112 static void BND_Fixup (int, int);
 113 static void NOTRACK_Fixup (int, int);
 114 static void HLE_Fixup1 (int, int);
 115 static void HLE_Fixup2 (int, int);
 116 static void HLE_Fixup3 (int, int);
 117 static void CMPXCHG8B_Fixup (int, int);
 118 static void XMM_Fixup (int, int);
 119 static void CRC32_Fixup (int, int);
 120 static void FXSAVE_Fixup (int, int);
 121 static void PCMPESTR_Fixup (int, int);
 122 static void OP_LWPCB_E (int, int);
 123 static void OP_LWP_E (int, int);
 124 static void OP_Vex_2src_1 (int, int);
 125 static void OP_Vex_2src_2 (int, int);
 126
 127 static void MOVBE_Fixup (int, int);
 128 static void MOVSXD_Fixup (int, int);
 129
 130 static void OP_Mask (int, int);
 131
 132 struct dis_private {
 133   /* Points to first byte not fetched.  */
 134   bfd_byte *max_fetched;
 135   bfd_byte the_buffer[MAX_MNEM_SIZE];
 136   bfd_vma insn_start;
 137   int orig_sizeflag;
 138   OPCODES_SIGJMP_BUF bailout;
 139 };
 140
 141 enum address_mode
 142 {
 143   mode_16bit,
 144   mode_32bit,
 145   mode_64bit
 146 };
 147
 148 enum address_mode address_mode;
 149
 150 /* Flags for the prefixes for the current instruction.  See below.  */
 151 static int prefixes;
 152
 153 /* REX prefix the current instruction.  See below.  */
 154 static int rex;
 155 /* Bits of REX we've already used.  */
 156 static int rex_used;
 157 /* Mark parts used in the REX prefix.  When we are testing for
 158    empty prefix (for 8bit register REX extension), just mask it
 159    out.  Otherwise test for REX bit is excuse for existence of REX
 160    only in case value is nonzero.  */
 161 #define USED_REX(value)                                 \
 162   {                                                     \
 163     if (value)                                          \
 164       {                                                 \
 165         if ((rex & value))                              \
 166           rex_used |= (value) | REX_OPCODE;             \
 167       }                                                 \
 168     else                                                \
 169       rex_used |= REX_OPCODE;                           \
 170   }
 171
 172 /* Flags for prefixes which we somehow handled when printing the
 173    current instruction.  */
 174 static int used_prefixes;
 175
 176 /* Flags stored in PREFIXES.  */
 177 #define PREFIX_REPZ 1
 178 #define PREFIX_REPNZ 2
 179 #define PREFIX_LOCK 4
 180 #define PREFIX_CS 8
 181 #define PREFIX_SS 0x10
 182 #define PREFIX_DS 0x20
 183 #define PREFIX_ES 0x40
 184 #define PREFIX_FS 0x80
 185 #define PREFIX_GS 0x100
 186 #define PREFIX_DATA 0x200
 187 #define PREFIX_ADDR 0x400
 188 #define PREFIX_FWAIT 0x800
 189
 190 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
 191    to ADDR (exclusive) are valid.  Returns 1 for success, longjmps
 192    on error.  */
 193 #define FETCH_DATA(info, addr) \
 194   ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
 195    ? 1 : fetch_data ((info), (addr)))
 196
 197 static int
 198 fetch_data (struct disassemble_info *info, bfd_byte *addr)
 199 {
 200   int status;
 201   struct dis_private *priv = (struct dis_private *) info->private_data;
 202   bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
 203
 204   if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
 205     status = (*info->read_memory_func) (start,
 206                                         priv->max_fetched,
 207                                         addr - priv->max_fetched,
 208                                         info);
 209   else
 210     status = -1;
 211   if (status != 0)
 212     {
 213       /* If we did manage to read at least one byte, then
 214          print_insn_i386 will do something sensible.  Otherwise, print
 215          an error.  We do that here because this is where we know
 216          STATUS.  */
 217       if (priv->max_fetched == priv->the_buffer)
 218         (*info->memory_error_func) (status, start, info);
 219       OPCODES_SIGLONGJMP (priv->bailout, 1);
 220     }
 221   else
 222     priv->max_fetched = addr;
 223   return 1;
 224 }
 225
 226 /* Possible values for prefix requirement.  */
 227 #define PREFIX_IGNORED_SHIFT    16
 228 #define PREFIX_IGNORED_REPZ     (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
 229 #define PREFIX_IGNORED_REPNZ    (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
 230 #define PREFIX_IGNORED_DATA     (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
 231 #define PREFIX_IGNORED_ADDR     (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
 232 #define PREFIX_IGNORED_LOCK     (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
 233
 234 /* Opcode prefixes.  */
 235 #define PREFIX_OPCODE           (PREFIX_REPZ \
 236                                  | PREFIX_REPNZ \
 237                                  | PREFIX_DATA)
 238
 239 /* Prefixes ignored.  */
 240 #define PREFIX_IGNORED          (PREFIX_IGNORED_REPZ \
 241                                  | PREFIX_IGNORED_REPNZ \
 242                                  | PREFIX_IGNORED_DATA)
 243
 244 #define XX { NULL, 0 }
 245 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
 246
 247 #define Eb { OP_E, b_mode }
 248 #define Ebnd { OP_E, bnd_mode }
 249 #define EbS { OP_E, b_swap_mode }
 250 #define EbndS { OP_E, bnd_swap_mode }
 251 #define Ev { OP_E, v_mode }
 252 #define Eva { OP_E, va_mode }
 253 #define Ev_bnd { OP_E, v_bnd_mode }
 254 #define EvS { OP_E, v_swap_mode }
 255 #define Ed { OP_E, d_mode }
 256 #define Edq { OP_E, dq_mode }
 257 #define Edqw { OP_E, dqw_mode }
 258 #define Edqb { OP_E, dqb_mode }
 259 #define Edb { OP_E, db_mode }
 260 #define Edw { OP_E, dw_mode }
 261 #define Edqd { OP_E, dqd_mode }
 262 #define Eq { OP_E, q_mode }
 263 #define indirEv { OP_indirE, indir_v_mode }
 264 #define indirEp { OP_indirE, f_mode }
 265 #define stackEv { OP_E, stack_v_mode }
 266 #define Em { OP_E, m_mode }
 267 #define Ew { OP_E, w_mode }
 268 #define M { OP_M, 0 }           /* lea, lgdt, etc. */
 269 #define Ma { OP_M, a_mode }
 270 #define Mb { OP_M, b_mode }
 271 #define Md { OP_M, d_mode }
 272 #define Mo { OP_M, o_mode }
 273 #define Mp { OP_M, f_mode }             /* 32 or 48 bit memory operand for LDS, LES etc */
 274 #define Mq { OP_M, q_mode }
 275 #define Mv_bnd { OP_M, v_bndmk_mode }
 276 #define Mx { OP_M, x_mode }
 277 #define Mxmm { OP_M, xmm_mode }
 278 #define Gb { OP_G, b_mode }
 279 #define Gbnd { OP_G, bnd_mode }
 280 #define Gv { OP_G, v_mode }
 281 #define Gd { OP_G, d_mode }
 282 #define Gdq { OP_G, dq_mode }
 283 #define Gm { OP_G, m_mode }
 284 #define Gva { OP_G, va_mode }
 285 #define Gw { OP_G, w_mode }
 286 #define Rd { OP_R, d_mode }
 287 #define Rdq { OP_R, dq_mode }
 288 #define Rm { OP_R, m_mode }
 289 #define Ib { OP_I, b_mode }
 290 #define sIb { OP_sI, b_mode }   /* sign extened byte */
 291 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
 292 #define Iv { OP_I, v_mode }
 293 #define sIv { OP_sI, v_mode }
 294 #define Iv64 { OP_I64, v_mode }
 295 #define Id { OP_I, d_mode }
 296 #define Iw { OP_I, w_mode }
 297 #define I1 { OP_I, const_1_mode }
 298 #define Jb { OP_J, b_mode }
 299 #define Jv { OP_J, v_mode }
 300 #define Jdqw { OP_J, dqw_mode }
 301 #define Cm { OP_C, m_mode }
 302 #define Dm { OP_D, m_mode }
 303 #define Td { OP_T, d_mode }
 304 #define Skip_MODRM { OP_Skip_MODRM, 0 }
 305
 306 #define RMeAX { OP_REG, eAX_reg }
 307 #define RMeBX { OP_REG, eBX_reg }
 308 #define RMeCX { OP_REG, eCX_reg }
 309 #define RMeDX { OP_REG, eDX_reg }
 310 #define RMeSP { OP_REG, eSP_reg }
 311 #define RMeBP { OP_REG, eBP_reg }
 312 #define RMeSI { OP_REG, eSI_reg }
 313 #define RMeDI { OP_REG, eDI_reg }
 314 #define RMrAX { OP_REG, rAX_reg }
 315 #define RMrBX { OP_REG, rBX_reg }
 316 #define RMrCX { OP_REG, rCX_reg }
 317 #define RMrDX { OP_REG, rDX_reg }
 318 #define RMrSP { OP_REG, rSP_reg }
 319 #define RMrBP { OP_REG, rBP_reg }
 320 #define RMrSI { OP_REG, rSI_reg }
 321 #define RMrDI { OP_REG, rDI_reg }
 322 #define RMAL { OP_REG, al_reg }
 323 #define RMCL { OP_REG, cl_reg }
 324 #define RMDL { OP_REG, dl_reg }
 325 #define RMBL { OP_REG, bl_reg }
 326 #define RMAH { OP_REG, ah_reg }
 327 #define RMCH { OP_REG, ch_reg }
 328 #define RMDH { OP_REG, dh_reg }
 329 #define RMBH { OP_REG, bh_reg }
 330 #define RMAX { OP_REG, ax_reg }
 331 #define RMDX { OP_REG, dx_reg }
 332
 333 #define eAX { OP_IMREG, eAX_reg }
 334 #define eBX { OP_IMREG, eBX_reg }
 335 #define eCX { OP_IMREG, eCX_reg }
 336 #define eDX { OP_IMREG, eDX_reg }
 337 #define eSP { OP_IMREG, eSP_reg }
 338 #define eBP { OP_IMREG, eBP_reg }
 339 #define eSI { OP_IMREG, eSI_reg }
 340 #define eDI { OP_IMREG, eDI_reg }
 341 #define AL { OP_IMREG, al_reg }
 342 #define CL { OP_IMREG, cl_reg }
 343 #define DL { OP_IMREG, dl_reg }
 344 #define BL { OP_IMREG, bl_reg }
 345 #define AH { OP_IMREG, ah_reg }
 346 #define CH { OP_IMREG, ch_reg }
 347 #define DH { OP_IMREG, dh_reg }
 348 #define BH { OP_IMREG, bh_reg }
 349 #define AX { OP_IMREG, ax_reg }
 350 #define DX { OP_IMREG, dx_reg }
 351 #define zAX { OP_IMREG, z_mode_ax_reg }
 352 #define indirDX { OP_IMREG, indir_dx_reg }
 353
 354 #define Sw { OP_SEG, w_mode }
 355 #define Sv { OP_SEG, v_mode }
 356 #define Ap { OP_DIR, 0 }
 357 #define Ob { OP_OFF64, b_mode }
 358 #define Ov { OP_OFF64, v_mode }
 359 #define Xb { OP_DSreg, eSI_reg }
 360 #define Xv { OP_DSreg, eSI_reg }
 361 #define Xz { OP_DSreg, eSI_reg }
 362 #define Yb { OP_ESreg, eDI_reg }
 363 #define Yv { OP_ESreg, eDI_reg }
 364 #define DSBX { OP_DSreg, eBX_reg }
 365
 366 #define es { OP_REG, es_reg }
 367 #define ss { OP_REG, ss_reg }
 368 #define cs { OP_REG, cs_reg }
 369 #define ds { OP_REG, ds_reg }
 370 #define fs { OP_REG, fs_reg }
 371 #define gs { OP_REG, gs_reg }
 372
 373 #define MX { OP_MMX, 0 }
 374 #define XM { OP_XMM, 0 }
 375 #define XMScalar { OP_XMM, scalar_mode }
 376 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
 377 #define XMM { OP_XMM, xmm_mode }
 378 #define XMxmmq { OP_XMM, xmmq_mode }
 379 #define EM { OP_EM, v_mode }
 380 #define EMS { OP_EM, v_swap_mode }
 381 #define EMd { OP_EM, d_mode }
 382 #define EMx { OP_EM, x_mode }
 383 #define EXbScalar { OP_EX, b_scalar_mode }
 384 #define EXw { OP_EX, w_mode }
 385 #define EXwScalar { OP_EX, w_scalar_mode }
 386 #define EXd { OP_EX, d_mode }
 387 #define EXdS { OP_EX, d_swap_mode }
 388 #define EXq { OP_EX, q_mode }
 389 #define EXqS { OP_EX, q_swap_mode }
 390 #define EXx { OP_EX, x_mode }
 391 #define EXxS { OP_EX, x_swap_mode }
 392 #define EXxmm { OP_EX, xmm_mode }
 393 #define EXymm { OP_EX, ymm_mode }
 394 #define EXxmmq { OP_EX, xmmq_mode }
 395 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
 396 #define EXxmm_mb { OP_EX, xmm_mb_mode }
 397 #define EXxmm_mw { OP_EX, xmm_mw_mode }
 398 #define EXxmm_md { OP_EX, xmm_md_mode }
 399 #define EXxmm_mq { OP_EX, xmm_mq_mode }
 400 #define EXxmmdw { OP_EX, xmmdw_mode }
 401 #define EXxmmqd { OP_EX, xmmqd_mode }
 402 #define EXymmq { OP_EX, ymmq_mode }
 403 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
 404 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
 405 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
 406 #define MS { OP_MS, v_mode }
 407 #define XS { OP_XS, v_mode }
 408 #define EMCq { OP_EMC, q_mode }
 409 #define MXC { OP_MXC, 0 }
 410 #define OPSUF { OP_3DNowSuffix, 0 }
 411 #define SEP { SEP_Fixup, 0 }
 412 #define CMP { CMP_Fixup, 0 }
 413 #define XMM0 { XMM_Fixup, 0 }
 414 #define FXSAVE { FXSAVE_Fixup, 0 }
 415 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
 416 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
 417
 418 #define Vex { OP_VEX, vex_mode }
 419 #define VexScalar { OP_VEX, vex_scalar_mode }
 420 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
 421 #define Vex128 { OP_VEX, vex128_mode }
 422 #define Vex256 { OP_VEX, vex256_mode }
 423 #define VexGdq { OP_VEX, dq_mode }
 424 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
 425 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
 426 #define EXVexW { OP_EX_VexW, x_mode }
 427 #define EXdVexW { OP_EX_VexW, d_mode }
 428 #define EXqVexW { OP_EX_VexW, q_mode }
 429 #define EXVexImmW { OP_EX_VexImmW, x_mode }
 430 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
 431 #define XMVexW { OP_XMM_VexW, 0 }
 432 #define XMVexI4 { OP_REG_VexI4, x_mode }
 433 #define PCLMUL { PCLMUL_Fixup, 0 }
 434 #define VCMP { VCMP_Fixup, 0 }
 435 #define VPCMP { VPCMP_Fixup, 0 }
 436 #define VPCOM { VPCOM_Fixup, 0 }
 437
 438 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
 439 #define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode }
 440 #define EXxEVexS { OP_Rounding, evex_sae_mode }
 441
 442 #define XMask { OP_Mask, mask_mode }
 443 #define MaskG { OP_G, mask_mode }
 444 #define MaskE { OP_E, mask_mode }
 445 #define MaskBDE { OP_E, mask_bd_mode }
 446 #define MaskR { OP_R, mask_mode }
 447 #define MaskVex { OP_VEX, mask_mode }
 448
 449 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
 450 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
 451 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
 452 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
 453
 454 /* Used handle "rep" prefix for string instructions.  */
 455 #define Xbr { REP_Fixup, eSI_reg }
 456 #define Xvr { REP_Fixup, eSI_reg }
 457 #define Ybr { REP_Fixup, eDI_reg }
 458 #define Yvr { REP_Fixup, eDI_reg }
 459 #define Yzr { REP_Fixup, eDI_reg }
 460 #define indirDXr { REP_Fixup, indir_dx_reg }
 461 #define ALr { REP_Fixup, al_reg }
 462 #define eAXr { REP_Fixup, eAX_reg }
 463
 464 /* Used handle HLE prefix for lockable instructions.  */
 465 #define Ebh1 { HLE_Fixup1, b_mode }
 466 #define Evh1 { HLE_Fixup1, v_mode }
 467 #define Ebh2 { HLE_Fixup2, b_mode }
 468 #define Evh2 { HLE_Fixup2, v_mode }
 469 #define Ebh3 { HLE_Fixup3, b_mode }
 470 #define Evh3 { HLE_Fixup3, v_mode }
 471
 472 #define BND { BND_Fixup, 0 }
 473 #define NOTRACK { NOTRACK_Fixup, 0 }
 474
 475 #define cond_jump_flag { NULL, cond_jump_mode }
 476 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
 477
 478 /* bits in sizeflag */
 479 #define SUFFIX_ALWAYS 4
 480 #define AFLAG 2
 481 #define DFLAG 1
 482
 483 enum
 484 {
 485   /* byte operand */
 486   b_mode = 1,
 487   /* byte operand with operand swapped */
 488   b_swap_mode,
 489   /* byte operand, sign extend like 'T' suffix */
 490   b_T_mode,
 491   /* operand size depends on prefixes */
 492   v_mode,
 493   /* operand size depends on prefixes with operand swapped */
 494   v_swap_mode,
 495   /* operand size depends on address prefix */
 496   va_mode,
 497   /* word operand */
 498   w_mode,
 499   /* double word operand  */
 500   d_mode,
 501   /* double word operand with operand swapped */
 502   d_swap_mode,
 503   /* quad word operand */
 504   q_mode,
 505   /* quad word operand with operand swapped */
 506   q_swap_mode,
 507   /* ten-byte operand */
 508   t_mode,
 509   /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand.  In EVEX with
 510      broadcast enabled.  */
 511   x_mode,
 512   /* Similar to x_mode, but with different EVEX mem shifts.  */
 513   evex_x_gscat_mode,
 514   /* Similar to x_mode, but with disabled broadcast.  */
 515   evex_x_nobcst_mode,
 516   /* Similar to x_mode, but with operands swapped and disabled broadcast
 517      in EVEX.  */
 518   x_swap_mode,
 519   /* 16-byte XMM operand */
 520   xmm_mode,
 521   /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
 522      memory operand (depending on vector length).  Broadcast isn't
 523      allowed.  */
 524   xmmq_mode,
 525   /* Same as xmmq_mode, but broadcast is allowed.  */
 526   evex_half_bcst_xmmq_mode,
 527   /* XMM register or byte memory operand */
 528   xmm_mb_mode,
 529   /* XMM register or word memory operand */
 530   xmm_mw_mode,
 531   /* XMM register or double word memory operand */
 532   xmm_md_mode,
 533   /* XMM register or quad word memory operand */
 534   xmm_mq_mode,
 535   /* 16-byte XMM, word, double word or quad word operand.  */
 536   xmmdw_mode,
 537   /* 16-byte XMM, double word, quad word operand or xmm word operand.  */
 538   xmmqd_mode,
 539   /* 32-byte YMM operand */
 540   ymm_mode,
 541   /* quad word, ymmword or zmmword memory operand.  */
 542   ymmq_mode,
 543   /* 32-byte YMM or 16-byte word operand */
 544   ymmxmm_mode,
 545   /* d_mode in 32bit, q_mode in 64bit mode.  */
 546   m_mode,
 547   /* pair of v_mode operands */
 548   a_mode,
 549   cond_jump_mode,
 550   loop_jcxz_mode,
 551   movsxd_mode,
 552   v_bnd_mode,
 553   /* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode.  */
 554   v_bndmk_mode,
 555   /* operand size depends on REX prefixes.  */
 556   dq_mode,
 557   /* registers like dq_mode, memory like w_mode, displacements like
 558      v_mode without considering Intel64 ISA.  */
 559   dqw_mode,
 560   /* bounds operand */
 561   bnd_mode,
 562   /* bounds operand with operand swapped */
 563   bnd_swap_mode,
 564   /* 4- or 6-byte pointer operand */
 565   f_mode,
 566   const_1_mode,
 567   /* v_mode for indirect branch opcodes.  */
 568   indir_v_mode,
 569   /* v_mode for stack-related opcodes.  */
 570   stack_v_mode,
 571   /* non-quad operand size depends on prefixes */
 572   z_mode,
 573   /* 16-byte operand */
 574   o_mode,
 575   /* registers like dq_mode, memory like b_mode.  */
 576   dqb_mode,
 577   /* registers like d_mode, memory like b_mode.  */
 578   db_mode,
 579   /* registers like d_mode, memory like w_mode.  */
 580   dw_mode,
 581   /* registers like dq_mode, memory like d_mode.  */
 582   dqd_mode,
 583   /* normal vex mode */
 584   vex_mode,
 585   /* 128bit vex mode */
 586   vex128_mode,
 587   /* 256bit vex mode */
 588   vex256_mode,
 589
 590   /* Operand size depends on the VEX.W bit, with VSIB dword indices.  */
 591   vex_vsib_d_w_dq_mode,
 592   /* Similar to vex_vsib_d_w_dq_mode, with smaller memory.  */
 593   vex_vsib_d_w_d_mode,
 594   /* Operand size depends on the VEX.W bit, with VSIB qword indices.  */
 595   vex_vsib_q_w_dq_mode,
 596   /* Similar to vex_vsib_q_w_dq_mode, with smaller memory.  */
 597   vex_vsib_q_w_d_mode,
 598
 599   /* scalar, ignore vector length.  */
 600   scalar_mode,
 601   /* like b_mode, ignore vector length.  */
 602   b_scalar_mode,
 603   /* like w_mode, ignore vector length.  */
 604   w_scalar_mode,
 605   /* like d_swap_mode, ignore vector length.  */
 606   d_scalar_swap_mode,
 607   /* like q_swap_mode, ignore vector length.  */
 608   q_scalar_swap_mode,
 609   /* like vex_mode, ignore vector length.  */
 610   vex_scalar_mode,
 611   /* Operand size depends on the VEX.W bit, ignore vector length.  */
 612   vex_scalar_w_dq_mode,
 613
 614   /* Static rounding.  */
 615   evex_rounding_mode,
 616   /* Static rounding, 64-bit mode only.  */
 617   evex_rounding_64_mode,
 618   /* Supress all exceptions.  */
 619   evex_sae_mode,
 620
 621   /* Mask register operand.  */
 622   mask_mode,
 623   /* Mask register operand.  */
 624   mask_bd_mode,
 625
 626   es_reg,
 627   cs_reg,
 628   ss_reg,
 629   ds_reg,
 630   fs_reg,
 631   gs_reg,
 632
 633   eAX_reg,
 634   eCX_reg,
 635   eDX_reg,
 636   eBX_reg,
 637   eSP_reg,
 638   eBP_reg,
 639   eSI_reg,
 640   eDI_reg,
 641
 642   al_reg,
 643   cl_reg,
 644   dl_reg,
 645   bl_reg,
 646   ah_reg,
 647   ch_reg,
 648   dh_reg,
 649   bh_reg,
 650
 651   ax_reg,
 652   cx_reg,
 653   dx_reg,
 654   bx_reg,
 655   sp_reg,
 656   bp_reg,
 657   si_reg,
 658   di_reg,
 659
 660   rAX_reg,
 661   rCX_reg,
 662   rDX_reg,
 663   rBX_reg,
 664   rSP_reg,
 665   rBP_reg,
 666   rSI_reg,
 667   rDI_reg,
 668
 669   z_mode_ax_reg,
 670   indir_dx_reg
 671 };
 672
 673 enum
 674 {
 675   FLOATCODE = 1,
 676   USE_REG_TABLE,
 677   USE_MOD_TABLE,
 678   USE_RM_TABLE,
 679   USE_PREFIX_TABLE,
 680   USE_X86_64_TABLE,
 681   USE_3BYTE_TABLE,
 682   USE_XOP_8F_TABLE,
 683   USE_VEX_C4_TABLE,
 684   USE_VEX_C5_TABLE,
 685   USE_VEX_LEN_TABLE,
 686   USE_VEX_W_TABLE,
 687   USE_EVEX_TABLE,
 688   USE_EVEX_LEN_TABLE
 689 };
 690
 691 #define FLOAT                   NULL, { { NULL, FLOATCODE } }, 0
 692
 693 #define DIS386(T, I)            NULL, { { NULL, (T)}, { NULL,  (I) } }, 0
 694 #define DIS386_PREFIX(T, I, P)          NULL, { { NULL, (T)}, { NULL,  (I) } }, P
 695 #define REG_TABLE(I)            DIS386 (USE_REG_TABLE, (I))
 696 #define MOD_TABLE(I)            DIS386 (USE_MOD_TABLE, (I))
 697 #define RM_TABLE(I)             DIS386 (USE_RM_TABLE, (I))
 698 #define PREFIX_TABLE(I)         DIS386 (USE_PREFIX_TABLE, (I))
 699 #define X86_64_TABLE(I)         DIS386 (USE_X86_64_TABLE, (I))
 700 #define THREE_BYTE_TABLE(I)     DIS386 (USE_3BYTE_TABLE, (I))
 701 #define THREE_BYTE_TABLE_PREFIX(I, P)   DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
 702 #define XOP_8F_TABLE(I)         DIS386 (USE_XOP_8F_TABLE, (I))
 703 #define VEX_C4_TABLE(I)         DIS386 (USE_VEX_C4_TABLE, (I))
 704 #define VEX_C5_TABLE(I)         DIS386 (USE_VEX_C5_TABLE, (I))
 705 #define VEX_LEN_TABLE(I)        DIS386 (USE_VEX_LEN_TABLE, (I))
 706 #define VEX_W_TABLE(I)          DIS386 (USE_VEX_W_TABLE, (I))
 707 #define EVEX_TABLE(I)           DIS386 (USE_EVEX_TABLE, (I))
 708 #define EVEX_LEN_TABLE(I)       DIS386 (USE_EVEX_LEN_TABLE, (I))
 709
 710 enum
 711 {
 712   REG_80 = 0,
 713   REG_81,
 714   REG_83,
 715   REG_8F,
 716   REG_C0,
 717   REG_C1,
 718   REG_C6,
 719   REG_C7,
 720   REG_D0,
 721   REG_D1,
 722   REG_D2,
 723   REG_D3,
 724   REG_F6,
 725   REG_F7,
 726   REG_FE,
 727   REG_FF,
 728   REG_0F00,
 729   REG_0F01,
 730   REG_0F0D,
 731   REG_0F18,
 732   REG_0F1C_P_0_MOD_0,
 733   REG_0F1E_P_1_MOD_3,
 734   REG_0F71,
 735   REG_0F72,
 736   REG_0F73,
 737   REG_0FA6,
 738   REG_0FA7,
 739   REG_0FAE,
 740   REG_0FBA,
 741   REG_0FC7,
 742   REG_VEX_0F71,
 743   REG_VEX_0F72,
 744   REG_VEX_0F73,
 745   REG_VEX_0FAE,
 746   REG_VEX_0F38F3,
 747   REG_XOP_LWPCB,
 748   REG_XOP_LWP,
 749   REG_XOP_TBM_01,
 750   REG_XOP_TBM_02,
 751
 752   REG_EVEX_0F71,
 753   REG_EVEX_0F72,
 754   REG_EVEX_0F73,
 755   REG_EVEX_0F38C6,
 756   REG_EVEX_0F38C7
 757 };
 758
 759 enum
 760 {
 761   MOD_8D = 0,
 762   MOD_C6_REG_7,
 763   MOD_C7_REG_7,
 764   MOD_FF_REG_3,
 765   MOD_FF_REG_5,
 766   MOD_0F01_REG_0,
 767   MOD_0F01_REG_1,
 768   MOD_0F01_REG_2,
 769   MOD_0F01_REG_3,
 770   MOD_0F01_REG_5,
 771   MOD_0F01_REG_7,
 772   MOD_0F12_PREFIX_0,
 773   MOD_0F12_PREFIX_2,
 774   MOD_0F13,
 775   MOD_0F16_PREFIX_0,
 776   MOD_0F16_PREFIX_2,
 777   MOD_0F17,
 778   MOD_0F18_REG_0,
 779   MOD_0F18_REG_1,
 780   MOD_0F18_REG_2,
 781   MOD_0F18_REG_3,
 782   MOD_0F18_REG_4,
 783   MOD_0F18_REG_5,
 784   MOD_0F18_REG_6,
 785   MOD_0F18_REG_7,
 786   MOD_0F1A_PREFIX_0,
 787   MOD_0F1B_PREFIX_0,
 788   MOD_0F1B_PREFIX_1,
 789   MOD_0F1C_PREFIX_0,
 790   MOD_0F1E_PREFIX_1,
 791   MOD_0F24,
 792   MOD_0F26,
 793   MOD_0F2B_PREFIX_0,
 794   MOD_0F2B_PREFIX_1,
 795   MOD_0F2B_PREFIX_2,
 796   MOD_0F2B_PREFIX_3,
 797   MOD_0F50,
 798   MOD_0F71_REG_2,
 799   MOD_0F71_REG_4,
 800   MOD_0F71_REG_6,
 801   MOD_0F72_REG_2,
 802   MOD_0F72_REG_4,
 803   MOD_0F72_REG_6,
 804   MOD_0F73_REG_2,
 805   MOD_0F73_REG_3,
 806   MOD_0F73_REG_6,
 807   MOD_0F73_REG_7,
 808   MOD_0FAE_REG_0,
 809   MOD_0FAE_REG_1,
 810   MOD_0FAE_REG_2,
 811   MOD_0FAE_REG_3,
 812   MOD_0FAE_REG_4,
 813   MOD_0FAE_REG_5,
 814   MOD_0FAE_REG_6,
 815   MOD_0FAE_REG_7,
 816   MOD_0FB2,
 817   MOD_0FB4,
 818   MOD_0FB5,
 819   MOD_0FC3,
 820   MOD_0FC7_REG_3,
 821   MOD_0FC7_REG_4,
 822   MOD_0FC7_REG_5,
 823   MOD_0FC7_REG_6,
 824   MOD_0FC7_REG_7,
 825   MOD_0FD7,
 826   MOD_0FE7_PREFIX_2,
 827   MOD_0FF0_PREFIX_3,
 828   MOD_0F382A_PREFIX_2,
 829   MOD_0F38F5_PREFIX_2,
 830   MOD_0F38F6_PREFIX_0,
 831   MOD_0F38F8_PREFIX_1,
 832   MOD_0F38F8_PREFIX_2,
 833   MOD_0F38F8_PREFIX_3,
 834   MOD_0F38F9_PREFIX_0,
 835   MOD_62_32BIT,
 836   MOD_C4_32BIT,
 837   MOD_C5_32BIT,
 838   MOD_VEX_0F12_PREFIX_0,
 839   MOD_VEX_0F12_PREFIX_2,
 840   MOD_VEX_0F13,
 841   MOD_VEX_0F16_PREFIX_0,
 842   MOD_VEX_0F16_PREFIX_2,
 843   MOD_VEX_0F17,
 844   MOD_VEX_0F2B,
 845   MOD_VEX_W_0_0F41_P_0_LEN_1,
 846   MOD_VEX_W_1_0F41_P_0_LEN_1,
 847   MOD_VEX_W_0_0F41_P_2_LEN_1,
 848   MOD_VEX_W_1_0F41_P_2_LEN_1,
 849   MOD_VEX_W_0_0F42_P_0_LEN_1,
 850   MOD_VEX_W_1_0F42_P_0_LEN_1,
 851   MOD_VEX_W_0_0F42_P_2_LEN_1,
 852   MOD_VEX_W_1_0F42_P_2_LEN_1,
 853   MOD_VEX_W_0_0F44_P_0_LEN_1,
 854   MOD_VEX_W_1_0F44_P_0_LEN_1,
 855   MOD_VEX_W_0_0F44_P_2_LEN_1,
 856   MOD_VEX_W_1_0F44_P_2_LEN_1,
 857   MOD_VEX_W_0_0F45_P_0_LEN_1,
 858   MOD_VEX_W_1_0F45_P_0_LEN_1,
 859   MOD_VEX_W_0_0F45_P_2_LEN_1,
 860   MOD_VEX_W_1_0F45_P_2_LEN_1,
 861   MOD_VEX_W_0_0F46_P_0_LEN_1,
 862   MOD_VEX_W_1_0F46_P_0_LEN_1,
 863   MOD_VEX_W_0_0F46_P_2_LEN_1,
 864   MOD_VEX_W_1_0F46_P_2_LEN_1,
 865   MOD_VEX_W_0_0F47_P_0_LEN_1,
 866   MOD_VEX_W_1_0F47_P_0_LEN_1,
 867   MOD_VEX_W_0_0F47_P_2_LEN_1,
 868   MOD_VEX_W_1_0F47_P_2_LEN_1,
 869   MOD_VEX_W_0_0F4A_P_0_LEN_1,
 870   MOD_VEX_W_1_0F4A_P_0_LEN_1,
 871   MOD_VEX_W_0_0F4A_P_2_LEN_1,
 872   MOD_VEX_W_1_0F4A_P_2_LEN_1,
 873   MOD_VEX_W_0_0F4B_P_0_LEN_1,
 874   MOD_VEX_W_1_0F4B_P_0_LEN_1,
 875   MOD_VEX_W_0_0F4B_P_2_LEN_1,
 876   MOD_VEX_0F50,
 877   MOD_VEX_0F71_REG_2,
 878   MOD_VEX_0F71_REG_4,
 879   MOD_VEX_0F71_REG_6,
 880   MOD_VEX_0F72_REG_2,
 881   MOD_VEX_0F72_REG_4,
 882   MOD_VEX_0F72_REG_6,
 883   MOD_VEX_0F73_REG_2,
 884   MOD_VEX_0F73_REG_3,
 885   MOD_VEX_0F73_REG_6,
 886   MOD_VEX_0F73_REG_7,
 887   MOD_VEX_W_0_0F91_P_0_LEN_0,
 888   MOD_VEX_W_1_0F91_P_0_LEN_0,
 889   MOD_VEX_W_0_0F91_P_2_LEN_0,
 890   MOD_VEX_W_1_0F91_P_2_LEN_0,
 891   MOD_VEX_W_0_0F92_P_0_LEN_0,
 892   MOD_VEX_W_0_0F92_P_2_LEN_0,
 893   MOD_VEX_0F92_P_3_LEN_0,
 894   MOD_VEX_W_0_0F93_P_0_LEN_0,
 895   MOD_VEX_W_0_0F93_P_2_LEN_0,
 896   MOD_VEX_0F93_P_3_LEN_0,
 897   MOD_VEX_W_0_0F98_P_0_LEN_0,
 898   MOD_VEX_W_1_0F98_P_0_LEN_0,
 899   MOD_VEX_W_0_0F98_P_2_LEN_0,
 900   MOD_VEX_W_1_0F98_P_2_LEN_0,
 901   MOD_VEX_W_0_0F99_P_0_LEN_0,
 902   MOD_VEX_W_1_0F99_P_0_LEN_0,
 903   MOD_VEX_W_0_0F99_P_2_LEN_0,
 904   MOD_VEX_W_1_0F99_P_2_LEN_0,
 905   MOD_VEX_0FAE_REG_2,
 906   MOD_VEX_0FAE_REG_3,
 907   MOD_VEX_0FD7_PREFIX_2,
 908   MOD_VEX_0FE7_PREFIX_2,
 909   MOD_VEX_0FF0_PREFIX_3,
 910   MOD_VEX_0F381A_PREFIX_2,
 911   MOD_VEX_0F382A_PREFIX_2,
 912   MOD_VEX_0F382C_PREFIX_2,
 913   MOD_VEX_0F382D_PREFIX_2,
 914   MOD_VEX_0F382E_PREFIX_2,
 915   MOD_VEX_0F382F_PREFIX_2,
 916   MOD_VEX_0F385A_PREFIX_2,
 917   MOD_VEX_0F388C_PREFIX_2,
 918   MOD_VEX_0F388E_PREFIX_2,
 919   MOD_VEX_W_0_0F3A30_P_2_LEN_0,
 920   MOD_VEX_W_1_0F3A30_P_2_LEN_0,
 921   MOD_VEX_W_0_0F3A31_P_2_LEN_0,
 922   MOD_VEX_W_1_0F3A31_P_2_LEN_0,
 923   MOD_VEX_W_0_0F3A32_P_2_LEN_0,
 924   MOD_VEX_W_1_0F3A32_P_2_LEN_0,
 925   MOD_VEX_W_0_0F3A33_P_2_LEN_0,
 926   MOD_VEX_W_1_0F3A33_P_2_LEN_0,
 927
 928   MOD_EVEX_0F12_PREFIX_0,
 929   MOD_EVEX_0F12_PREFIX_2,
 930   MOD_EVEX_0F13,
 931   MOD_EVEX_0F16_PREFIX_0,
 932   MOD_EVEX_0F16_PREFIX_2,
 933   MOD_EVEX_0F17,
 934   MOD_EVEX_0F2B,
 935   MOD_EVEX_0F381A_P_2_W_0,
 936   MOD_EVEX_0F381A_P_2_W_1,
 937   MOD_EVEX_0F381B_P_2_W_0,
 938   MOD_EVEX_0F381B_P_2_W_1,
 939   MOD_EVEX_0F385A_P_2_W_0,
 940   MOD_EVEX_0F385A_P_2_W_1,
 941   MOD_EVEX_0F385B_P_2_W_0,
 942   MOD_EVEX_0F385B_P_2_W_1,
 943   MOD_EVEX_0F38C6_REG_1,
 944   MOD_EVEX_0F38C6_REG_2,
 945   MOD_EVEX_0F38C6_REG_5,
 946   MOD_EVEX_0F38C6_REG_6,
 947   MOD_EVEX_0F38C7_REG_1,
 948   MOD_EVEX_0F38C7_REG_2,
 949   MOD_EVEX_0F38C7_REG_5,
 950   MOD_EVEX_0F38C7_REG_6
 951 };
 952
 953 enum
 954 {
 955   RM_C6_REG_7 = 0,
 956   RM_C7_REG_7,
 957   RM_0F01_REG_0,
 958   RM_0F01_REG_1,
 959   RM_0F01_REG_2,
 960   RM_0F01_REG_3,
 961   RM_0F01_REG_5_MOD_3,
 962   RM_0F01_REG_7_MOD_3,
 963   RM_0F1E_P_1_MOD_3_REG_7,
 964   RM_0FAE_REG_6_MOD_3_P_0,
 965   RM_0FAE_REG_7_MOD_3,
 966 };
 967
 968 enum
 969 {
 970   PREFIX_90 = 0,
 971   PREFIX_0F01_REG_3_RM_1,
 972   PREFIX_0F01_REG_5_MOD_0,
 973   PREFIX_0F01_REG_5_MOD_3_RM_0,
 974   PREFIX_0F01_REG_5_MOD_3_RM_1,
 975   PREFIX_0F01_REG_5_MOD_3_RM_2,
 976   PREFIX_0F01_REG_7_MOD_3_RM_2,
 977   PREFIX_0F01_REG_7_MOD_3_RM_3,
 978   PREFIX_0F09,
 979   PREFIX_0F10,
 980   PREFIX_0F11,
 981   PREFIX_0F12,
 982   PREFIX_0F16,
 983   PREFIX_0F1A,
 984   PREFIX_0F1B,
 985   PREFIX_0F1C,
 986   PREFIX_0F1E,
 987   PREFIX_0F2A,
 988   PREFIX_0F2B,
 989   PREFIX_0F2C,
 990   PREFIX_0F2D,
 991   PREFIX_0F2E,
 992   PREFIX_0F2F,
 993   PREFIX_0F51,
 994   PREFIX_0F52,
 995   PREFIX_0F53,
 996   PREFIX_0F58,
 997   PREFIX_0F59,
 998   PREFIX_0F5A,
 999   PREFIX_0F5B,
1000   PREFIX_0F5C,
1001   PREFIX_0F5D,
1002   PREFIX_0F5E,
1003   PREFIX_0F5F,
1004   PREFIX_0F60,
1005   PREFIX_0F61,
1006   PREFIX_0F62,
1007   PREFIX_0F6C,
1008   PREFIX_0F6D,
1009   PREFIX_0F6F,
1010   PREFIX_0F70,
1011   PREFIX_0F73_REG_3,
1012   PREFIX_0F73_REG_7,
1013   PREFIX_0F78,
1014   PREFIX_0F79,
1015   PREFIX_0F7C,
1016   PREFIX_0F7D,
1017   PREFIX_0F7E,
1018   PREFIX_0F7F,
1019   PREFIX_0FAE_REG_0_MOD_3,
1020   PREFIX_0FAE_REG_1_MOD_3,
1021   PREFIX_0FAE_REG_2_MOD_3,
1022   PREFIX_0FAE_REG_3_MOD_3,
1023   PREFIX_0FAE_REG_4_MOD_0,
1024   PREFIX_0FAE_REG_4_MOD_3,
1025   PREFIX_0FAE_REG_5_MOD_0,
1026   PREFIX_0FAE_REG_5_MOD_3,
1027   PREFIX_0FAE_REG_6_MOD_0,
1028   PREFIX_0FAE_REG_6_MOD_3,
1029   PREFIX_0FAE_REG_7_MOD_0,
1030   PREFIX_0FB8,
1031   PREFIX_0FBC,
1032   PREFIX_0FBD,
1033   PREFIX_0FC2,
1034   PREFIX_0FC3_MOD_0,
1035   PREFIX_0FC7_REG_6_MOD_0,
1036   PREFIX_0FC7_REG_6_MOD_3,
1037   PREFIX_0FC7_REG_7_MOD_3,
1038   PREFIX_0FD0,
1039   PREFIX_0FD6,
1040   PREFIX_0FE6,
1041   PREFIX_0FE7,
1042   PREFIX_0FF0,
1043   PREFIX_0FF7,
1044   PREFIX_0F3810,
1045   PREFIX_0F3814,
1046   PREFIX_0F3815,
1047   PREFIX_0F3817,
1048   PREFIX_0F3820,
1049   PREFIX_0F3821,
1050   PREFIX_0F3822,
1051   PREFIX_0F3823,
1052   PREFIX_0F3824,
1053   PREFIX_0F3825,
1054   PREFIX_0F3828,
1055   PREFIX_0F3829,
1056   PREFIX_0F382A,
1057   PREFIX_0F382B,
1058   PREFIX_0F3830,
1059   PREFIX_0F3831,
1060   PREFIX_0F3832,
1061   PREFIX_0F3833,
1062   PREFIX_0F3834,
1063   PREFIX_0F3835,
1064   PREFIX_0F3837,
1065   PREFIX_0F3838,
1066   PREFIX_0F3839,
1067   PREFIX_0F383A,
1068   PREFIX_0F383B,
1069   PREFIX_0F383C,
1070   PREFIX_0F383D,
1071   PREFIX_0F383E,
1072   PREFIX_0F383F,
1073   PREFIX_0F3840,
1074   PREFIX_0F3841,
1075   PREFIX_0F3880,
1076   PREFIX_0F3881,
1077   PREFIX_0F3882,
1078   PREFIX_0F38C8,
1079   PREFIX_0F38C9,
1080   PREFIX_0F38CA,
1081   PREFIX_0F38CB,
1082   PREFIX_0F38CC,
1083   PREFIX_0F38CD,
1084   PREFIX_0F38CF,
1085   PREFIX_0F38DB,
1086   PREFIX_0F38DC,
1087   PREFIX_0F38DD,
1088   PREFIX_0F38DE,
1089   PREFIX_0F38DF,
1090   PREFIX_0F38F0,
1091   PREFIX_0F38F1,
1092   PREFIX_0F38F5,
1093   PREFIX_0F38F6,
1094   PREFIX_0F38F8,
1095   PREFIX_0F38F9,
1096   PREFIX_0F3A08,
1097   PREFIX_0F3A09,
1098   PREFIX_0F3A0A,
1099   PREFIX_0F3A0B,
1100   PREFIX_0F3A0C,
1101   PREFIX_0F3A0D,
1102   PREFIX_0F3A0E,
1103   PREFIX_0F3A14,
1104   PREFIX_0F3A15,
1105   PREFIX_0F3A16,
1106   PREFIX_0F3A17,
1107   PREFIX_0F3A20,
1108   PREFIX_0F3A21,
1109   PREFIX_0F3A22,
1110   PREFIX_0F3A40,
1111   PREFIX_0F3A41,
1112   PREFIX_0F3A42,
1113   PREFIX_0F3A44,
1114   PREFIX_0F3A60,
1115   PREFIX_0F3A61,
1116   PREFIX_0F3A62,
1117   PREFIX_0F3A63,
1118   PREFIX_0F3ACC,
1119   PREFIX_0F3ACE,
1120   PREFIX_0F3ACF,
1121   PREFIX_0F3ADF,
1122   PREFIX_VEX_0F10,
1123   PREFIX_VEX_0F11,
1124   PREFIX_VEX_0F12,
1125   PREFIX_VEX_0F16,
1126   PREFIX_VEX_0F2A,
1127   PREFIX_VEX_0F2C,
1128   PREFIX_VEX_0F2D,
1129   PREFIX_VEX_0F2E,
1130   PREFIX_VEX_0F2F,
1131   PREFIX_VEX_0F41,
1132   PREFIX_VEX_0F42,
1133   PREFIX_VEX_0F44,
1134   PREFIX_VEX_0F45,
1135   PREFIX_VEX_0F46,
1136   PREFIX_VEX_0F47,
1137   PREFIX_VEX_0F4A,
1138   PREFIX_VEX_0F4B,
1139   PREFIX_VEX_0F51,
1140   PREFIX_VEX_0F52,
1141   PREFIX_VEX_0F53,
1142   PREFIX_VEX_0F58,
1143   PREFIX_VEX_0F59,
1144   PREFIX_VEX_0F5A,
1145   PREFIX_VEX_0F5B,
1146   PREFIX_VEX_0F5C,
1147   PREFIX_VEX_0F5D,
1148   PREFIX_VEX_0F5E,
1149   PREFIX_VEX_0F5F,
1150   PREFIX_VEX_0F60,
1151   PREFIX_VEX_0F61,
1152   PREFIX_VEX_0F62,
1153   PREFIX_VEX_0F63,
1154   PREFIX_VEX_0F64,
1155   PREFIX_VEX_0F65,
1156   PREFIX_VEX_0F66,
1157   PREFIX_VEX_0F67,
1158   PREFIX_VEX_0F68,
1159   PREFIX_VEX_0F69,
1160   PREFIX_VEX_0F6A,
1161   PREFIX_VEX_0F6B,
1162   PREFIX_VEX_0F6C,
1163   PREFIX_VEX_0F6D,
1164   PREFIX_VEX_0F6E,
1165   PREFIX_VEX_0F6F,
1166   PREFIX_VEX_0F70,
1167   PREFIX_VEX_0F71_REG_2,
1168   PREFIX_VEX_0F71_REG_4,
1169   PREFIX_VEX_0F71_REG_6,
1170   PREFIX_VEX_0F72_REG_2,
1171   PREFIX_VEX_0F72_REG_4,
1172   PREFIX_VEX_0F72_REG_6,
1173   PREFIX_VEX_0F73_REG_2,
1174   PREFIX_VEX_0F73_REG_3,
1175   PREFIX_VEX_0F73_REG_6,
1176   PREFIX_VEX_0F73_REG_7,
1177   PREFIX_VEX_0F74,
1178   PREFIX_VEX_0F75,
1179   PREFIX_VEX_0F76,
1180   PREFIX_VEX_0F77,
1181   PREFIX_VEX_0F7C,
1182   PREFIX_VEX_0F7D,
1183   PREFIX_VEX_0F7E,
1184   PREFIX_VEX_0F7F,
1185   PREFIX_VEX_0F90,
1186   PREFIX_VEX_0F91,
1187   PREFIX_VEX_0F92,
1188   PREFIX_VEX_0F93,
1189   PREFIX_VEX_0F98,
1190   PREFIX_VEX_0F99,
1191   PREFIX_VEX_0FC2,
1192   PREFIX_VEX_0FC4,
1193   PREFIX_VEX_0FC5,
1194   PREFIX_VEX_0FD0,
1195   PREFIX_VEX_0FD1,
1196   PREFIX_VEX_0FD2,
1197   PREFIX_VEX_0FD3,
1198   PREFIX_VEX_0FD4,
1199   PREFIX_VEX_0FD5,
1200   PREFIX_VEX_0FD6,
1201   PREFIX_VEX_0FD7,
1202   PREFIX_VEX_0FD8,
1203   PREFIX_VEX_0FD9,
1204   PREFIX_VEX_0FDA,
1205   PREFIX_VEX_0FDB,
1206   PREFIX_VEX_0FDC,
1207   PREFIX_VEX_0FDD,
1208   PREFIX_VEX_0FDE,
1209   PREFIX_VEX_0FDF,
1210   PREFIX_VEX_0FE0,
1211   PREFIX_VEX_0FE1,
1212   PREFIX_VEX_0FE2,
1213   PREFIX_VEX_0FE3,
1214   PREFIX_VEX_0FE4,
1215   PREFIX_VEX_0FE5,
1216   PREFIX_VEX_0FE6,
1217   PREFIX_VEX_0FE7,
1218   PREFIX_VEX_0FE8,
1219   PREFIX_VEX_0FE9,
1220   PREFIX_VEX_0FEA,
1221   PREFIX_VEX_0FEB,
1222   PREFIX_VEX_0FEC,
1223   PREFIX_VEX_0FED,
1224   PREFIX_VEX_0FEE,
1225   PREFIX_VEX_0FEF,
1226   PREFIX_VEX_0FF0,
1227   PREFIX_VEX_0FF1,
1228   PREFIX_VEX_0FF2,
1229   PREFIX_VEX_0FF3,
1230   PREFIX_VEX_0FF4,
1231   PREFIX_VEX_0FF5,
1232   PREFIX_VEX_0FF6,
1233   PREFIX_VEX_0FF7,
1234   PREFIX_VEX_0FF8,
1235   PREFIX_VEX_0FF9,
1236   PREFIX_VEX_0FFA,
1237   PREFIX_VEX_0FFB,
1238   PREFIX_VEX_0FFC,
1239   PREFIX_VEX_0FFD,
1240   PREFIX_VEX_0FFE,
1241   PREFIX_VEX_0F3800,
1242   PREFIX_VEX_0F3801,
1243   PREFIX_VEX_0F3802,
1244   PREFIX_VEX_0F3803,
1245   PREFIX_VEX_0F3804,
1246   PREFIX_VEX_0F3805,
1247   PREFIX_VEX_0F3806,
1248   PREFIX_VEX_0F3807,
1249   PREFIX_VEX_0F3808,
1250   PREFIX_VEX_0F3809,
1251   PREFIX_VEX_0F380A,
1252   PREFIX_VEX_0F380B,
1253   PREFIX_VEX_0F380C,
1254   PREFIX_VEX_0F380D,
1255   PREFIX_VEX_0F380E,
1256   PREFIX_VEX_0F380F,
1257   PREFIX_VEX_0F3813,
1258   PREFIX_VEX_0F3816,
1259   PREFIX_VEX_0F3817,
1260   PREFIX_VEX_0F3818,
1261   PREFIX_VEX_0F3819,
1262   PREFIX_VEX_0F381A,
1263   PREFIX_VEX_0F381C,
1264   PREFIX_VEX_0F381D,
1265   PREFIX_VEX_0F381E,
1266   PREFIX_VEX_0F3820,
1267   PREFIX_VEX_0F3821,
1268   PREFIX_VEX_0F3822,
1269   PREFIX_VEX_0F3823,
1270   PREFIX_VEX_0F3824,
1271   PREFIX_VEX_0F3825,
1272   PREFIX_VEX_0F3828,
1273   PREFIX_VEX_0F3829,
1274   PREFIX_VEX_0F382A,
1275   PREFIX_VEX_0F382B,
1276   PREFIX_VEX_0F382C,
1277   PREFIX_VEX_0F382D,
1278   PREFIX_VEX_0F382E,
1279   PREFIX_VEX_0F382F,
1280   PREFIX_VEX_0F3830,
1281   PREFIX_VEX_0F3831,
1282   PREFIX_VEX_0F3832,
1283   PREFIX_VEX_0F3833,
1284   PREFIX_VEX_0F3834,
1285   PREFIX_VEX_0F3835,
1286   PREFIX_VEX_0F3836,
1287   PREFIX_VEX_0F3837,
1288   PREFIX_VEX_0F3838,
1289   PREFIX_VEX_0F3839,
1290   PREFIX_VEX_0F383A,
1291   PREFIX_VEX_0F383B,
1292   PREFIX_VEX_0F383C,
1293   PREFIX_VEX_0F383D,
1294   PREFIX_VEX_0F383E,
1295   PREFIX_VEX_0F383F,
1296   PREFIX_VEX_0F3840,
1297   PREFIX_VEX_0F3841,
1298   PREFIX_VEX_0F3845,
1299   PREFIX_VEX_0F3846,
1300   PREFIX_VEX_0F3847,
1301   PREFIX_VEX_0F3858,
1302   PREFIX_VEX_0F3859,
1303   PREFIX_VEX_0F385A,
1304   PREFIX_VEX_0F3878,
1305   PREFIX_VEX_0F3879,
1306   PREFIX_VEX_0F388C,
1307   PREFIX_VEX_0F388E,
1308   PREFIX_VEX_0F3890,
1309   PREFIX_VEX_0F3891,
1310   PREFIX_VEX_0F3892,
1311   PREFIX_VEX_0F3893,
1312   PREFIX_VEX_0F3896,
1313   PREFIX_VEX_0F3897,
1314   PREFIX_VEX_0F3898,
1315   PREFIX_VEX_0F3899,
1316   PREFIX_VEX_0F389A,
1317   PREFIX_VEX_0F389B,
1318   PREFIX_VEX_0F389C,
1319   PREFIX_VEX_0F389D,
1320   PREFIX_VEX_0F389E,
1321   PREFIX_VEX_0F389F,
1322   PREFIX_VEX_0F38A6,
1323   PREFIX_VEX_0F38A7,
1324   PREFIX_VEX_0F38A8,
1325   PREFIX_VEX_0F38A9,
1326   PREFIX_VEX_0F38AA,
1327   PREFIX_VEX_0F38AB,
1328   PREFIX_VEX_0F38AC,
1329   PREFIX_VEX_0F38AD,
1330   PREFIX_VEX_0F38AE,
1331   PREFIX_VEX_0F38AF,
1332   PREFIX_VEX_0F38B6,
1333   PREFIX_VEX_0F38B7,
1334   PREFIX_VEX_0F38B8,
1335   PREFIX_VEX_0F38B9,
1336   PREFIX_VEX_0F38BA,
1337   PREFIX_VEX_0F38BB,
1338   PREFIX_VEX_0F38BC,
1339   PREFIX_VEX_0F38BD,
1340   PREFIX_VEX_0F38BE,
1341   PREFIX_VEX_0F38BF,
1342   PREFIX_VEX_0F38CF,
1343   PREFIX_VEX_0F38DB,
1344   PREFIX_VEX_0F38DC,
1345   PREFIX_VEX_0F38DD,
1346   PREFIX_VEX_0F38DE,
1347   PREFIX_VEX_0F38DF,
1348   PREFIX_VEX_0F38F2,
1349   PREFIX_VEX_0F38F3_REG_1,
1350   PREFIX_VEX_0F38F3_REG_2,
1351   PREFIX_VEX_0F38F3_REG_3,
1352   PREFIX_VEX_0F38F5,
1353   PREFIX_VEX_0F38F6,
1354   PREFIX_VEX_0F38F7,
1355   PREFIX_VEX_0F3A00,
1356   PREFIX_VEX_0F3A01,
1357   PREFIX_VEX_0F3A02,
1358   PREFIX_VEX_0F3A04,
1359   PREFIX_VEX_0F3A05,
1360   PREFIX_VEX_0F3A06,
1361   PREFIX_VEX_0F3A08,
1362   PREFIX_VEX_0F3A09,
1363   PREFIX_VEX_0F3A0A,
1364   PREFIX_VEX_0F3A0B,
1365   PREFIX_VEX_0F3A0C,
1366   PREFIX_VEX_0F3A0D,
1367   PREFIX_VEX_0F3A0E,
1368   PREFIX_VEX_0F3A0F,
1369   PREFIX_VEX_0F3A14,
1370   PREFIX_VEX_0F3A15,
1371   PREFIX_VEX_0F3A16,
1372   PREFIX_VEX_0F3A17,
1373   PREFIX_VEX_0F3A18,
1374   PREFIX_VEX_0F3A19,
1375   PREFIX_VEX_0F3A1D,
1376   PREFIX_VEX_0F3A20,
1377   PREFIX_VEX_0F3A21,
1378   PREFIX_VEX_0F3A22,
1379   PREFIX_VEX_0F3A30,
1380   PREFIX_VEX_0F3A31,
1381   PREFIX_VEX_0F3A32,
1382   PREFIX_VEX_0F3A33,
1383   PREFIX_VEX_0F3A38,
1384   PREFIX_VEX_0F3A39,
1385   PREFIX_VEX_0F3A40,
1386   PREFIX_VEX_0F3A41,
1387   PREFIX_VEX_0F3A42,
1388   PREFIX_VEX_0F3A44,
1389   PREFIX_VEX_0F3A46,
1390   PREFIX_VEX_0F3A48,
1391   PREFIX_VEX_0F3A49,
1392   PREFIX_VEX_0F3A4A,
1393   PREFIX_VEX_0F3A4B,
1394   PREFIX_VEX_0F3A4C,
1395   PREFIX_VEX_0F3A5C,
1396   PREFIX_VEX_0F3A5D,
1397   PREFIX_VEX_0F3A5E,
1398   PREFIX_VEX_0F3A5F,
1399   PREFIX_VEX_0F3A60,
1400   PREFIX_VEX_0F3A61,
1401   PREFIX_VEX_0F3A62,
1402   PREFIX_VEX_0F3A63,
1403   PREFIX_VEX_0F3A68,
1404   PREFIX_VEX_0F3A69,
1405   PREFIX_VEX_0F3A6A,
1406   PREFIX_VEX_0F3A6B,
1407   PREFIX_VEX_0F3A6C,
1408   PREFIX_VEX_0F3A6D,
1409   PREFIX_VEX_0F3A6E,
1410   PREFIX_VEX_0F3A6F,
1411   PREFIX_VEX_0F3A78,
1412   PREFIX_VEX_0F3A79,
1413   PREFIX_VEX_0F3A7A,
1414   PREFIX_VEX_0F3A7B,
1415   PREFIX_VEX_0F3A7C,
1416   PREFIX_VEX_0F3A7D,
1417   PREFIX_VEX_0F3A7E,
1418   PREFIX_VEX_0F3A7F,
1419   PREFIX_VEX_0F3ACE,
1420   PREFIX_VEX_0F3ACF,
1421   PREFIX_VEX_0F3ADF,
1422   PREFIX_VEX_0F3AF0,
1423
1424   PREFIX_EVEX_0F10,
1425   PREFIX_EVEX_0F11,
1426   PREFIX_EVEX_0F12,
1427   PREFIX_EVEX_0F16,
1428   PREFIX_EVEX_0F2A,
1429   PREFIX_EVEX_0F2C,
1430   PREFIX_EVEX_0F2D,
1431   PREFIX_EVEX_0F2E,
1432   PREFIX_EVEX_0F2F,
1433   PREFIX_EVEX_0F51,
1434   PREFIX_EVEX_0F58,
1435   PREFIX_EVEX_0F59,
1436   PREFIX_EVEX_0F5A,
1437   PREFIX_EVEX_0F5B,
1438   PREFIX_EVEX_0F5C,
1439   PREFIX_EVEX_0F5D,
1440   PREFIX_EVEX_0F5E,
1441   PREFIX_EVEX_0F5F,
1442   PREFIX_EVEX_0F64,
1443   PREFIX_EVEX_0F65,
1444   PREFIX_EVEX_0F66,
1445   PREFIX_EVEX_0F6E,
1446   PREFIX_EVEX_0F6F,
1447   PREFIX_EVEX_0F70,
1448   PREFIX_EVEX_0F71_REG_2,
1449   PREFIX_EVEX_0F71_REG_4,
1450   PREFIX_EVEX_0F71_REG_6,
1451   PREFIX_EVEX_0F72_REG_0,
1452   PREFIX_EVEX_0F72_REG_1,
1453   PREFIX_EVEX_0F72_REG_2,
1454   PREFIX_EVEX_0F72_REG_4,
1455   PREFIX_EVEX_0F72_REG_6,
1456   PREFIX_EVEX_0F73_REG_2,
1457   PREFIX_EVEX_0F73_REG_3,
1458   PREFIX_EVEX_0F73_REG_6,
1459   PREFIX_EVEX_0F73_REG_7,
1460   PREFIX_EVEX_0F74,
1461   PREFIX_EVEX_0F75,
1462   PREFIX_EVEX_0F76,
1463   PREFIX_EVEX_0F78,
1464   PREFIX_EVEX_0F79,
1465   PREFIX_EVEX_0F7A,
1466   PREFIX_EVEX_0F7B,
1467   PREFIX_EVEX_0F7E,
1468   PREFIX_EVEX_0F7F,
1469   PREFIX_EVEX_0FC2,
1470   PREFIX_EVEX_0FC4,
1471   PREFIX_EVEX_0FC5,
1472   PREFIX_EVEX_0FD6,
1473   PREFIX_EVEX_0FDB,
1474   PREFIX_EVEX_0FDF,
1475   PREFIX_EVEX_0FE2,
1476   PREFIX_EVEX_0FE6,
1477   PREFIX_EVEX_0FE7,
1478   PREFIX_EVEX_0FEB,
1479   PREFIX_EVEX_0FEF,
1480   PREFIX_EVEX_0F380D,
1481   PREFIX_EVEX_0F3810,
1482   PREFIX_EVEX_0F3811,
1483   PREFIX_EVEX_0F3812,
1484   PREFIX_EVEX_0F3813,
1485   PREFIX_EVEX_0F3814,
1486   PREFIX_EVEX_0F3815,
1487   PREFIX_EVEX_0F3816,
1488   PREFIX_EVEX_0F3819,
1489   PREFIX_EVEX_0F381A,
1490   PREFIX_EVEX_0F381B,
1491   PREFIX_EVEX_0F381E,
1492   PREFIX_EVEX_0F381F,
1493   PREFIX_EVEX_0F3820,
1494   PREFIX_EVEX_0F3821,
1495   PREFIX_EVEX_0F3822,
1496   PREFIX_EVEX_0F3823,
1497   PREFIX_EVEX_0F3824,
1498   PREFIX_EVEX_0F3825,
1499   PREFIX_EVEX_0F3826,
1500   PREFIX_EVEX_0F3827,
1501   PREFIX_EVEX_0F3828,
1502   PREFIX_EVEX_0F3829,
1503   PREFIX_EVEX_0F382A,
1504   PREFIX_EVEX_0F382C,
1505   PREFIX_EVEX_0F382D,
1506   PREFIX_EVEX_0F3830,
1507   PREFIX_EVEX_0F3831,
1508   PREFIX_EVEX_0F3832,
1509   PREFIX_EVEX_0F3833,
1510   PREFIX_EVEX_0F3834,
1511   PREFIX_EVEX_0F3835,
1512   PREFIX_EVEX_0F3836,
1513   PREFIX_EVEX_0F3837,
1514   PREFIX_EVEX_0F3838,
1515   PREFIX_EVEX_0F3839,
1516   PREFIX_EVEX_0F383A,
1517   PREFIX_EVEX_0F383B,
1518   PREFIX_EVEX_0F383D,
1519   PREFIX_EVEX_0F383F,
1520   PREFIX_EVEX_0F3840,
1521   PREFIX_EVEX_0F3842,
1522   PREFIX_EVEX_0F3843,
1523   PREFIX_EVEX_0F3844,
1524   PREFIX_EVEX_0F3845,
1525   PREFIX_EVEX_0F3846,
1526   PREFIX_EVEX_0F3847,
1527   PREFIX_EVEX_0F384C,
1528   PREFIX_EVEX_0F384D,
1529   PREFIX_EVEX_0F384E,
1530   PREFIX_EVEX_0F384F,
1531   PREFIX_EVEX_0F3850,
1532   PREFIX_EVEX_0F3851,
1533   PREFIX_EVEX_0F3852,
1534   PREFIX_EVEX_0F3853,
1535   PREFIX_EVEX_0F3854,
1536   PREFIX_EVEX_0F3855,
1537   PREFIX_EVEX_0F3859,
1538   PREFIX_EVEX_0F385A,
1539   PREFIX_EVEX_0F385B,
1540   PREFIX_EVEX_0F3862,
1541   PREFIX_EVEX_0F3863,
1542   PREFIX_EVEX_0F3864,
1543   PREFIX_EVEX_0F3865,
1544   PREFIX_EVEX_0F3866,
1545   PREFIX_EVEX_0F3868,
1546   PREFIX_EVEX_0F3870,
1547   PREFIX_EVEX_0F3871,
1548   PREFIX_EVEX_0F3872,
1549   PREFIX_EVEX_0F3873,
1550   PREFIX_EVEX_0F3875,
1551   PREFIX_EVEX_0F3876,
1552   PREFIX_EVEX_0F3877,
1553   PREFIX_EVEX_0F387A,
1554   PREFIX_EVEX_0F387B,
1555   PREFIX_EVEX_0F387C,
1556   PREFIX_EVEX_0F387D,
1557   PREFIX_EVEX_0F387E,
1558   PREFIX_EVEX_0F387F,
1559   PREFIX_EVEX_0F3883,
1560   PREFIX_EVEX_0F3888,
1561   PREFIX_EVEX_0F3889,
1562   PREFIX_EVEX_0F388A,
1563   PREFIX_EVEX_0F388B,
1564   PREFIX_EVEX_0F388D,
1565   PREFIX_EVEX_0F388F,
1566   PREFIX_EVEX_0F3890,
1567   PREFIX_EVEX_0F3891,
1568   PREFIX_EVEX_0F3892,
1569   PREFIX_EVEX_0F3893,
1570   PREFIX_EVEX_0F389A,
1571   PREFIX_EVEX_0F389B,
1572   PREFIX_EVEX_0F38A0,
1573   PREFIX_EVEX_0F38A1,
1574   PREFIX_EVEX_0F38A2,
1575   PREFIX_EVEX_0F38A3,
1576   PREFIX_EVEX_0F38AA,
1577   PREFIX_EVEX_0F38AB,
1578   PREFIX_EVEX_0F38B4,
1579   PREFIX_EVEX_0F38B5,
1580   PREFIX_EVEX_0F38C4,
1581   PREFIX_EVEX_0F38C6_REG_1,
1582   PREFIX_EVEX_0F38C6_REG_2,
1583   PREFIX_EVEX_0F38C6_REG_5,
1584   PREFIX_EVEX_0F38C6_REG_6,
1585   PREFIX_EVEX_0F38C7_REG_1,
1586   PREFIX_EVEX_0F38C7_REG_2,
1587   PREFIX_EVEX_0F38C7_REG_5,
1588   PREFIX_EVEX_0F38C7_REG_6,
1589   PREFIX_EVEX_0F38C8,
1590   PREFIX_EVEX_0F38CA,
1591   PREFIX_EVEX_0F38CB,
1592   PREFIX_EVEX_0F38CC,
1593   PREFIX_EVEX_0F38CD,
1594
1595   PREFIX_EVEX_0F3A00,
1596   PREFIX_EVEX_0F3A01,
1597   PREFIX_EVEX_0F3A03,
1598   PREFIX_EVEX_0F3A05,
1599   PREFIX_EVEX_0F3A08,
1600   PREFIX_EVEX_0F3A09,
1601   PREFIX_EVEX_0F3A0A,
1602   PREFIX_EVEX_0F3A0B,
1603   PREFIX_EVEX_0F3A14,
1604   PREFIX_EVEX_0F3A15,
1605   PREFIX_EVEX_0F3A16,
1606   PREFIX_EVEX_0F3A17,
1607   PREFIX_EVEX_0F3A18,
1608   PREFIX_EVEX_0F3A19,
1609   PREFIX_EVEX_0F3A1A,
1610   PREFIX_EVEX_0F3A1B,
1611   PREFIX_EVEX_0F3A1E,
1612   PREFIX_EVEX_0F3A1F,
1613   PREFIX_EVEX_0F3A20,
1614   PREFIX_EVEX_0F3A21,
1615   PREFIX_EVEX_0F3A22,
1616   PREFIX_EVEX_0F3A23,
1617   PREFIX_EVEX_0F3A25,
1618   PREFIX_EVEX_0F3A26,
1619   PREFIX_EVEX_0F3A27,
1620   PREFIX_EVEX_0F3A38,
1621   PREFIX_EVEX_0F3A39,
1622   PREFIX_EVEX_0F3A3A,
1623   PREFIX_EVEX_0F3A3B,
1624   PREFIX_EVEX_0F3A3E,
1625   PREFIX_EVEX_0F3A3F,
1626   PREFIX_EVEX_0F3A42,
1627   PREFIX_EVEX_0F3A43,
1628   PREFIX_EVEX_0F3A50,
1629   PREFIX_EVEX_0F3A51,
1630   PREFIX_EVEX_0F3A54,
1631   PREFIX_EVEX_0F3A55,
1632   PREFIX_EVEX_0F3A56,
1633   PREFIX_EVEX_0F3A57,
1634   PREFIX_EVEX_0F3A66,
1635   PREFIX_EVEX_0F3A67,
1636   PREFIX_EVEX_0F3A70,
1637   PREFIX_EVEX_0F3A71,
1638   PREFIX_EVEX_0F3A72,
1639   PREFIX_EVEX_0F3A73,
1640 };
1641
1642 enum
1643 {
1644   X86_64_06 = 0,
1645   X86_64_07,
1646   X86_64_0E,
1647   X86_64_16,
1648   X86_64_17,
1649   X86_64_1E,
1650   X86_64_1F,
1651   X86_64_27,
1652   X86_64_2F,
1653   X86_64_37,
1654   X86_64_3F,
1655   X86_64_60,
1656   X86_64_61,
1657   X86_64_62,
1658   X86_64_63,
1659   X86_64_6D,
1660   X86_64_6F,
1661   X86_64_82,
1662   X86_64_9A,
1663   X86_64_C2,
1664   X86_64_C3,
1665   X86_64_C4,
1666   X86_64_C5,
1667   X86_64_CE,
1668   X86_64_D4,
1669   X86_64_D5,
1670   X86_64_E8,
1671   X86_64_E9,
1672   X86_64_EA,
1673   X86_64_0F01_REG_0,
1674   X86_64_0F01_REG_1,
1675   X86_64_0F01_REG_2,
1676   X86_64_0F01_REG_3
1677 };
1678
1679 enum
1680 {
1681   THREE_BYTE_0F38 = 0,
1682   THREE_BYTE_0F3A
1683 };
1684
1685 enum
1686 {
1687   XOP_08 = 0,
1688   XOP_09,
1689   XOP_0A
1690 };
1691
1692 enum
1693 {
1694   VEX_0F = 0,
1695   VEX_0F38,
1696   VEX_0F3A
1697 };
1698
1699 enum
1700 {
1701   EVEX_0F = 0,
1702   EVEX_0F38,
1703   EVEX_0F3A
1704 };
1705
1706 enum
1707 {
1708   VEX_LEN_0F12_P_0_M_0 = 0,
1709   VEX_LEN_0F12_P_0_M_1,
1710 #define VEX_LEN_0F12_P_2_M_0 VEX_LEN_0F12_P_0_M_0
1711   VEX_LEN_0F13_M_0,
1712   VEX_LEN_0F16_P_0_M_0,
1713   VEX_LEN_0F16_P_0_M_1,
1714 #define VEX_LEN_0F16_P_2_M_0 VEX_LEN_0F16_P_0_M_0
1715   VEX_LEN_0F17_M_0,
1716   VEX_LEN_0F41_P_0,
1717   VEX_LEN_0F41_P_2,
1718   VEX_LEN_0F42_P_0,
1719   VEX_LEN_0F42_P_2,
1720   VEX_LEN_0F44_P_0,
1721   VEX_LEN_0F44_P_2,
1722   VEX_LEN_0F45_P_0,
1723   VEX_LEN_0F45_P_2,
1724   VEX_LEN_0F46_P_0,
1725   VEX_LEN_0F46_P_2,
1726   VEX_LEN_0F47_P_0,
1727   VEX_LEN_0F47_P_2,
1728   VEX_LEN_0F4A_P_0,
1729   VEX_LEN_0F4A_P_2,
1730   VEX_LEN_0F4B_P_0,
1731   VEX_LEN_0F4B_P_2,
1732   VEX_LEN_0F6E_P_2,
1733   VEX_LEN_0F77_P_0,
1734   VEX_LEN_0F7E_P_1,
1735   VEX_LEN_0F7E_P_2,
1736   VEX_LEN_0F90_P_0,
1737   VEX_LEN_0F90_P_2,
1738   VEX_LEN_0F91_P_0,
1739   VEX_LEN_0F91_P_2,
1740   VEX_LEN_0F92_P_0,
1741   VEX_LEN_0F92_P_2,
1742   VEX_LEN_0F92_P_3,
1743   VEX_LEN_0F93_P_0,
1744   VEX_LEN_0F93_P_2,
1745   VEX_LEN_0F93_P_3,
1746   VEX_LEN_0F98_P_0,
1747   VEX_LEN_0F98_P_2,
1748   VEX_LEN_0F99_P_0,
1749   VEX_LEN_0F99_P_2,
1750   VEX_LEN_0FAE_R_2_M_0,
1751   VEX_LEN_0FAE_R_3_M_0,
1752   VEX_LEN_0FC4_P_2,
1753   VEX_LEN_0FC5_P_2,
1754   VEX_LEN_0FD6_P_2,
1755   VEX_LEN_0FF7_P_2,
1756   VEX_LEN_0F3816_P_2,
1757   VEX_LEN_0F3819_P_2,
1758   VEX_LEN_0F381A_P_2_M_0,
1759   VEX_LEN_0F3836_P_2,
1760   VEX_LEN_0F3841_P_2,
1761   VEX_LEN_0F385A_P_2_M_0,
1762   VEX_LEN_0F38DB_P_2,
1763   VEX_LEN_0F38F2_P_0,
1764   VEX_LEN_0F38F3_R_1_P_0,
1765   VEX_LEN_0F38F3_R_2_P_0,
1766   VEX_LEN_0F38F3_R_3_P_0,
1767   VEX_LEN_0F38F5_P_0,
1768   VEX_LEN_0F38F5_P_1,
1769   VEX_LEN_0F38F5_P_3,
1770   VEX_LEN_0F38F6_P_3,
1771   VEX_LEN_0F38F7_P_0,
1772   VEX_LEN_0F38F7_P_1,
1773   VEX_LEN_0F38F7_P_2,
1774   VEX_LEN_0F38F7_P_3,
1775   VEX_LEN_0F3A00_P_2,
1776   VEX_LEN_0F3A01_P_2,
1777   VEX_LEN_0F3A06_P_2,
1778   VEX_LEN_0F3A14_P_2,
1779   VEX_LEN_0F3A15_P_2,
1780   VEX_LEN_0F3A16_P_2,
1781   VEX_LEN_0F3A17_P_2,
1782   VEX_LEN_0F3A18_P_2,
1783   VEX_LEN_0F3A19_P_2,
1784   VEX_LEN_0F3A20_P_2,
1785   VEX_LEN_0F3A21_P_2,
1786   VEX_LEN_0F3A22_P_2,
1787   VEX_LEN_0F3A30_P_2,
1788   VEX_LEN_0F3A31_P_2,
1789   VEX_LEN_0F3A32_P_2,
1790   VEX_LEN_0F3A33_P_2,
1791   VEX_LEN_0F3A38_P_2,
1792   VEX_LEN_0F3A39_P_2,
1793   VEX_LEN_0F3A41_P_2,
1794   VEX_LEN_0F3A46_P_2,
1795   VEX_LEN_0F3A60_P_2,
1796   VEX_LEN_0F3A61_P_2,
1797   VEX_LEN_0F3A62_P_2,
1798   VEX_LEN_0F3A63_P_2,
1799   VEX_LEN_0F3A6A_P_2,
1800   VEX_LEN_0F3A6B_P_2,
1801   VEX_LEN_0F3A6E_P_2,
1802   VEX_LEN_0F3A6F_P_2,
1803   VEX_LEN_0F3A7A_P_2,
1804   VEX_LEN_0F3A7B_P_2,
1805   VEX_LEN_0F3A7E_P_2,
1806   VEX_LEN_0F3A7F_P_2,
1807   VEX_LEN_0F3ADF_P_2,
1808   VEX_LEN_0F3AF0_P_3,
1809   VEX_LEN_0FXOP_08_CC,
1810   VEX_LEN_0FXOP_08_CD,
1811   VEX_LEN_0FXOP_08_CE,
1812   VEX_LEN_0FXOP_08_CF,
1813   VEX_LEN_0FXOP_08_EC,
1814   VEX_LEN_0FXOP_08_ED,
1815   VEX_LEN_0FXOP_08_EE,
1816   VEX_LEN_0FXOP_08_EF,
1817   VEX_LEN_0FXOP_09_80,
1818   VEX_LEN_0FXOP_09_81
1819 };
1820
1821 enum
1822 {
1823   EVEX_LEN_0F6E_P_2 = 0,
1824   EVEX_LEN_0F7E_P_1,
1825   EVEX_LEN_0F7E_P_2,
1826   EVEX_LEN_0FC4_P_2,
1827   EVEX_LEN_0FC5_P_2,
1828   EVEX_LEN_0FD6_P_2,
1829   EVEX_LEN_0F3816_P_2,
1830   EVEX_LEN_0F3819_P_2_W_0,
1831   EVEX_LEN_0F3819_P_2_W_1,
1832   EVEX_LEN_0F381A_P_2_W_0_M_0,
1833   EVEX_LEN_0F381A_P_2_W_1_M_0,
1834   EVEX_LEN_0F381B_P_2_W_0_M_0,
1835   EVEX_LEN_0F381B_P_2_W_1_M_0,
1836   EVEX_LEN_0F3836_P_2,
1837   EVEX_LEN_0F385A_P_2_W_0_M_0,
1838   EVEX_LEN_0F385A_P_2_W_1_M_0,
1839   EVEX_LEN_0F385B_P_2_W_0_M_0,
1840   EVEX_LEN_0F385B_P_2_W_1_M_0,
1841   EVEX_LEN_0F38C6_REG_1_PREFIX_2,
1842   EVEX_LEN_0F38C6_REG_2_PREFIX_2,
1843   EVEX_LEN_0F38C6_REG_5_PREFIX_2,
1844   EVEX_LEN_0F38C6_REG_6_PREFIX_2,
1845   EVEX_LEN_0F38C7_R_1_P_2_W_0,
1846   EVEX_LEN_0F38C7_R_1_P_2_W_1,
1847   EVEX_LEN_0F38C7_R_2_P_2_W_0,
1848   EVEX_LEN_0F38C7_R_2_P_2_W_1,
1849   EVEX_LEN_0F38C7_R_5_P_2_W_0,
1850   EVEX_LEN_0F38C7_R_5_P_2_W_1,
1851   EVEX_LEN_0F38C7_R_6_P_2_W_0,
1852   EVEX_LEN_0F38C7_R_6_P_2_W_1,
1853   EVEX_LEN_0F3A00_P_2_W_1,
1854   EVEX_LEN_0F3A01_P_2_W_1,
1855   EVEX_LEN_0F3A14_P_2,
1856   EVEX_LEN_0F3A15_P_2,
1857   EVEX_LEN_0F3A16_P_2,
1858   EVEX_LEN_0F3A17_P_2,
1859   EVEX_LEN_0F3A18_P_2_W_0,
1860   EVEX_LEN_0F3A18_P_2_W_1,
1861   EVEX_LEN_0F3A19_P_2_W_0,
1862   EVEX_LEN_0F3A19_P_2_W_1,
1863   EVEX_LEN_0F3A1A_P_2_W_0,
1864   EVEX_LEN_0F3A1A_P_2_W_1,
1865   EVEX_LEN_0F3A1B_P_2_W_0,
1866   EVEX_LEN_0F3A1B_P_2_W_1,
1867   EVEX_LEN_0F3A20_P_2,
1868   EVEX_LEN_0F3A21_P_2_W_0,
1869   EVEX_LEN_0F3A22_P_2,
1870   EVEX_LEN_0F3A23_P_2_W_0,
1871   EVEX_LEN_0F3A23_P_2_W_1,
1872   EVEX_LEN_0F3A38_P_2_W_0,
1873   EVEX_LEN_0F3A38_P_2_W_1,
1874   EVEX_LEN_0F3A39_P_2_W_0,
1875   EVEX_LEN_0F3A39_P_2_W_1,
1876   EVEX_LEN_0F3A3A_P_2_W_0,
1877   EVEX_LEN_0F3A3A_P_2_W_1,
1878   EVEX_LEN_0F3A3B_P_2_W_0,
1879   EVEX_LEN_0F3A3B_P_2_W_1,
1880   EVEX_LEN_0F3A43_P_2_W_0,
1881   EVEX_LEN_0F3A43_P_2_W_1
1882 };
1883
1884 enum
1885 {
1886   VEX_W_0F41_P_0_LEN_1 = 0,
1887   VEX_W_0F41_P_2_LEN_1,
1888   VEX_W_0F42_P_0_LEN_1,
1889   VEX_W_0F42_P_2_LEN_1,
1890   VEX_W_0F44_P_0_LEN_0,
1891   VEX_W_0F44_P_2_LEN_0,
1892   VEX_W_0F45_P_0_LEN_1,
1893   VEX_W_0F45_P_2_LEN_1,
1894   VEX_W_0F46_P_0_LEN_1,
1895   VEX_W_0F46_P_2_LEN_1,
1896   VEX_W_0F47_P_0_LEN_1,
1897   VEX_W_0F47_P_2_LEN_1,
1898   VEX_W_0F4A_P_0_LEN_1,
1899   VEX_W_0F4A_P_2_LEN_1,
1900   VEX_W_0F4B_P_0_LEN_1,
1901   VEX_W_0F4B_P_2_LEN_1,
1902   VEX_W_0F90_P_0_LEN_0,
1903   VEX_W_0F90_P_2_LEN_0,
1904   VEX_W_0F91_P_0_LEN_0,
1905   VEX_W_0F91_P_2_LEN_0,
1906   VEX_W_0F92_P_0_LEN_0,
1907   VEX_W_0F92_P_2_LEN_0,
1908   VEX_W_0F93_P_0_LEN_0,
1909   VEX_W_0F93_P_2_LEN_0,
1910   VEX_W_0F98_P_0_LEN_0,
1911   VEX_W_0F98_P_2_LEN_0,
1912   VEX_W_0F99_P_0_LEN_0,
1913   VEX_W_0F99_P_2_LEN_0,
1914   VEX_W_0F380C_P_2,
1915   VEX_W_0F380D_P_2,
1916   VEX_W_0F380E_P_2,
1917   VEX_W_0F380F_P_2,
1918   VEX_W_0F3813_P_2,
1919   VEX_W_0F3816_P_2,
1920   VEX_W_0F3818_P_2,
1921   VEX_W_0F3819_P_2,
1922   VEX_W_0F381A_P_2_M_0,
1923   VEX_W_0F382C_P_2_M_0,
1924   VEX_W_0F382D_P_2_M_0,
1925   VEX_W_0F382E_P_2_M_0,
1926   VEX_W_0F382F_P_2_M_0,
1927   VEX_W_0F3836_P_2,
1928   VEX_W_0F3846_P_2,
1929   VEX_W_0F3858_P_2,
1930   VEX_W_0F3859_P_2,
1931   VEX_W_0F385A_P_2_M_0,
1932   VEX_W_0F3878_P_2,
1933   VEX_W_0F3879_P_2,
1934   VEX_W_0F38CF_P_2,
1935   VEX_W_0F3A00_P_2,
1936   VEX_W_0F3A01_P_2,
1937   VEX_W_0F3A02_P_2,
1938   VEX_W_0F3A04_P_2,
1939   VEX_W_0F3A05_P_2,
1940   VEX_W_0F3A06_P_2,
1941   VEX_W_0F3A18_P_2,
1942   VEX_W_0F3A19_P_2,
1943   VEX_W_0F3A1D_P_2,
1944   VEX_W_0F3A30_P_2_LEN_0,
1945   VEX_W_0F3A31_P_2_LEN_0,
1946   VEX_W_0F3A32_P_2_LEN_0,
1947   VEX_W_0F3A33_P_2_LEN_0,
1948   VEX_W_0F3A38_P_2,
1949   VEX_W_0F3A39_P_2,
1950   VEX_W_0F3A46_P_2,
1951   VEX_W_0F3A48_P_2,
1952   VEX_W_0F3A49_P_2,
1953   VEX_W_0F3A4A_P_2,
1954   VEX_W_0F3A4B_P_2,
1955   VEX_W_0F3A4C_P_2,
1956   VEX_W_0F3ACE_P_2,
1957   VEX_W_0F3ACF_P_2,
1958
1959   EVEX_W_0F10_P_1,
1960   EVEX_W_0F10_P_3,
1961   EVEX_W_0F11_P_1,
1962   EVEX_W_0F11_P_3,
1963   EVEX_W_0F12_P_0_M_1,
1964   EVEX_W_0F12_P_1,
1965   EVEX_W_0F12_P_3,
1966   EVEX_W_0F16_P_0_M_1,
1967   EVEX_W_0F16_P_1,
1968   EVEX_W_0F2A_P_3,
1969   EVEX_W_0F51_P_1,
1970   EVEX_W_0F51_P_3,
1971   EVEX_W_0F58_P_1,
1972   EVEX_W_0F58_P_3,
1973   EVEX_W_0F59_P_1,
1974   EVEX_W_0F59_P_3,
1975   EVEX_W_0F5A_P_0,
1976   EVEX_W_0F5A_P_1,
1977   EVEX_W_0F5A_P_2,
1978   EVEX_W_0F5A_P_3,
1979   EVEX_W_0F5B_P_0,
1980   EVEX_W_0F5B_P_1,
1981   EVEX_W_0F5B_P_2,
1982   EVEX_W_0F5C_P_1,
1983   EVEX_W_0F5C_P_3,
1984   EVEX_W_0F5D_P_1,
1985   EVEX_W_0F5D_P_3,
1986   EVEX_W_0F5E_P_1,
1987   EVEX_W_0F5E_P_3,
1988   EVEX_W_0F5F_P_1,
1989   EVEX_W_0F5F_P_3,
1990   EVEX_W_0F62,
1991   EVEX_W_0F66_P_2,
1992   EVEX_W_0F6A,
1993   EVEX_W_0F6B,
1994   EVEX_W_0F6C,
1995   EVEX_W_0F6D,
1996   EVEX_W_0F6F_P_1,
1997   EVEX_W_0F6F_P_2,
1998   EVEX_W_0F6F_P_3,
1999   EVEX_W_0F70_P_2,
2000   EVEX_W_0F72_R_2_P_2,
2001   EVEX_W_0F72_R_6_P_2,
2002   EVEX_W_0F73_R_2_P_2,
2003   EVEX_W_0F73_R_6_P_2,
2004   EVEX_W_0F76_P_2,
2005   EVEX_W_0F78_P_0,
2006   EVEX_W_0F78_P_2,
2007   EVEX_W_0F79_P_0,
2008   EVEX_W_0F79_P_2,
2009   EVEX_W_0F7A_P_1,
2010   EVEX_W_0F7A_P_2,
2011   EVEX_W_0F7A_P_3,
2012   EVEX_W_0F7B_P_2,
2013   EVEX_W_0F7B_P_3,
2014   EVEX_W_0F7E_P_1,
2015   EVEX_W_0F7F_P_1,
2016   EVEX_W_0F7F_P_2,
2017   EVEX_W_0F7F_P_3,
2018   EVEX_W_0FC2_P_1,
2019   EVEX_W_0FC2_P_3,
2020   EVEX_W_0FD2,
2021   EVEX_W_0FD3,
2022   EVEX_W_0FD4,
2023   EVEX_W_0FD6_P_2,
2024   EVEX_W_0FE6_P_1,
2025   EVEX_W_0FE6_P_2,
2026   EVEX_W_0FE6_P_3,
2027   EVEX_W_0FE7_P_2,
2028   EVEX_W_0FF2,
2029   EVEX_W_0FF3,
2030   EVEX_W_0FF4,
2031   EVEX_W_0FFA,
2032   EVEX_W_0FFB,
2033   EVEX_W_0FFE,
2034   EVEX_W_0F380D_P_2,
2035   EVEX_W_0F3810_P_1,
2036   EVEX_W_0F3810_P_2,
2037   EVEX_W_0F3811_P_1,
2038   EVEX_W_0F3811_P_2,
2039   EVEX_W_0F3812_P_1,
2040   EVEX_W_0F3812_P_2,
2041   EVEX_W_0F3813_P_1,
2042   EVEX_W_0F3813_P_2,
2043   EVEX_W_0F3814_P_1,
2044   EVEX_W_0F3815_P_1,
2045   EVEX_W_0F3819_P_2,
2046   EVEX_W_0F381A_P_2,
2047   EVEX_W_0F381B_P_2,
2048   EVEX_W_0F381E_P_2,
2049   EVEX_W_0F381F_P_2,
2050   EVEX_W_0F3820_P_1,
2051   EVEX_W_0F3821_P_1,
2052   EVEX_W_0F3822_P_1,
2053   EVEX_W_0F3823_P_1,
2054   EVEX_W_0F3824_P_1,
2055   EVEX_W_0F3825_P_1,
2056   EVEX_W_0F3825_P_2,
2057   EVEX_W_0F3826_P_1,
2058   EVEX_W_0F3826_P_2,
2059   EVEX_W_0F3828_P_1,
2060   EVEX_W_0F3828_P_2,
2061   EVEX_W_0F3829_P_1,
2062   EVEX_W_0F3829_P_2,
2063   EVEX_W_0F382A_P_1,
2064   EVEX_W_0F382A_P_2,
2065   EVEX_W_0F382B,
2066   EVEX_W_0F3830_P_1,
2067   EVEX_W_0F3831_P_1,
2068   EVEX_W_0F3832_P_1,
2069   EVEX_W_0F3833_P_1,
2070   EVEX_W_0F3834_P_1,
2071   EVEX_W_0F3835_P_1,
2072   EVEX_W_0F3835_P_2,
2073   EVEX_W_0F3837_P_2,
2074   EVEX_W_0F383A_P_1,
2075   EVEX_W_0F3852_P_1,
2076   EVEX_W_0F3854_P_2,
2077   EVEX_W_0F3859_P_2,
2078   EVEX_W_0F385A_P_2,
2079   EVEX_W_0F385B_P_2,
2080   EVEX_W_0F3862_P_2,
2081   EVEX_W_0F3863_P_2,
2082   EVEX_W_0F3866_P_2,
2083   EVEX_W_0F3870_P_2,
2084   EVEX_W_0F3872_P_1,
2085   EVEX_W_0F3872_P_2,
2086   EVEX_W_0F3872_P_3,
2087   EVEX_W_0F3875_P_2,
2088   EVEX_W_0F387A_P_2,
2089   EVEX_W_0F387B_P_2,
2090   EVEX_W_0F387D_P_2,
2091   EVEX_W_0F3883_P_2,
2092   EVEX_W_0F388D_P_2,
2093   EVEX_W_0F3891_P_2,
2094   EVEX_W_0F3893_P_2,
2095   EVEX_W_0F38A1_P_2,
2096   EVEX_W_0F38A3_P_2,
2097   EVEX_W_0F38C7_R_1_P_2,
2098   EVEX_W_0F38C7_R_2_P_2,
2099   EVEX_W_0F38C7_R_5_P_2,
2100   EVEX_W_0F38C7_R_6_P_2,
2101
2102   EVEX_W_0F3A00_P_2,
2103   EVEX_W_0F3A01_P_2,
2104   EVEX_W_0F3A05_P_2,
2105   EVEX_W_0F3A08_P_2,
2106   EVEX_W_0F3A09_P_2,
2107   EVEX_W_0F3A0A_P_2,
2108   EVEX_W_0F3A0B_P_2,
2109   EVEX_W_0F3A18_P_2,
2110   EVEX_W_0F3A19_P_2,
2111   EVEX_W_0F3A1A_P_2,
2112   EVEX_W_0F3A1B_P_2,
2113   EVEX_W_0F3A21_P_2,
2114   EVEX_W_0F3A23_P_2,
2115   EVEX_W_0F3A38_P_2,
2116   EVEX_W_0F3A39_P_2,
2117   EVEX_W_0F3A3A_P_2,
2118   EVEX_W_0F3A3B_P_2,
2119   EVEX_W_0F3A3E_P_2,
2120   EVEX_W_0F3A3F_P_2,
2121   EVEX_W_0F3A42_P_2,
2122   EVEX_W_0F3A43_P_2,
2123   EVEX_W_0F3A70_P_2,
2124   EVEX_W_0F3A72_P_2,
2125 };
2126
2127 typedef void (*op_rtn) (int bytemode, int sizeflag);
2128
2129 struct dis386 {
2130   const char *name;
2131   struct
2132     {
2133       op_rtn rtn;
2134       int bytemode;
2135     } op[MAX_OPERANDS];
2136   unsigned int prefix_requirement;
2137 };
2138
2139 /* Upper case letters in the instruction names here are macros.
2140    'A' => print 'b' if no register operands or suffix_always is true
2141    'B' => print 'b' if suffix_always is true
2142    'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2143           size prefix
2144    'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2145           suffix_always is true
2146    'E' => print 'e' if 32-bit form of jcxz
2147    'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2148    'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2149    'H' => print ",pt" or ",pn" branch hint
2150    'I' unused.
2151    'J' unused.
2152    'K' => print 'd' or 'q' if rex prefix is present.
2153    'L' => print 'l' if suffix_always is true
2154    'M' => print 'r' if intel_mnemonic is false.
2155    'N' => print 'n' if instruction has no wait "prefix"
2156    'O' => print 'd' or 'o' (or 'q' in Intel mode)
2157    'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2158           or suffix_always is true.  print 'q' if rex prefix is present.
2159    'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2160           is true
2161    'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2162    'S' => print 'w', 'l' or 'q' if suffix_always is true
2163    'T' => print 'q' in 64bit mode if instruction has no operand size
2164           prefix and behave as 'P' otherwise
2165    'U' => print 'q' in 64bit mode if instruction has no operand size
2166           prefix and behave as 'Q' otherwise
2167    'V' => print 'q' in 64bit mode if instruction has no operand size
2168           prefix and behave as 'S' otherwise
2169    'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2170    'X' => print 's', 'd' depending on data16 prefix (for XMM)
2171    'Y' unused.
2172    'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2173    '!' => change condition from true to false or from false to true.
2174    '%' => add 1 upper case letter to the macro.
2175    '^' => print 'w', 'l', or 'q' (Intel64 ISA only) depending on operand size
2176           prefix or suffix_always is true (lcall/ljmp).
2177    '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending
2178           on operand size prefix.
2179    '&' => print 'q' in 64bit mode for Intel64 ISA or if instruction
2180           has no operand size prefix for AMD64 ISA, behave as 'P'
2181           otherwise
2182
2183    2 upper case letter macros:
2184    "XY" => print 'x' or 'y' if suffix_always is true or no register
2185            operands and no broadcast.
2186    "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
2187            register operands and no broadcast.
2188    "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2189    "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory
2190            operand or no operand at all in 64bit mode, or if suffix_always
2191            is true.
2192    "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2193    "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2194    "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2195    "LW" => print 'd', 'q' depending on the VEX.W bit
2196    "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
2197            an operand size prefix, or suffix_always is true.  print
2198            'q' if rex prefix is present.
2199
2200    Many of the above letters print nothing in Intel mode.  See "putop"
2201    for the details.
2202
2203    Braces '{' and '}', and vertical bars '|', indicate alternative
2204    mnemonic strings for AT&T and Intel.  */
2205
2206 static const struct dis386 dis386[] = {
2207   /* 00 */
2208   { "addB",             { Ebh1, Gb }, 0 },
2209   { "addS",             { Evh1, Gv }, 0 },
2210   { "addB",             { Gb, EbS }, 0 },
2211   { "addS",             { Gv, EvS }, 0 },
2212   { "addB",             { AL, Ib }, 0 },
2213   { "addS",             { eAX, Iv }, 0 },
2214   { X86_64_TABLE (X86_64_06) },
2215   { X86_64_TABLE (X86_64_07) },
2216   /* 08 */
2217   { "orB",              { Ebh1, Gb }, 0 },
2218   { "orS",              { Evh1, Gv }, 0 },
2219   { "orB",              { Gb, EbS }, 0 },
2220   { "orS",              { Gv, EvS }, 0 },
2221   { "orB",              { AL, Ib }, 0 },
2222   { "orS",              { eAX, Iv }, 0 },
2223   { X86_64_TABLE (X86_64_0E) },
2224   { Bad_Opcode },       /* 0x0f extended opcode escape */
2225   /* 10 */
2226   { "adcB",             { Ebh1, Gb }, 0 },
2227   { "adcS",             { Evh1, Gv }, 0 },
2228   { "adcB",             { Gb, EbS }, 0 },
2229   { "adcS",             { Gv, EvS }, 0 },
2230   { "adcB",             { AL, Ib }, 0 },
2231   { "adcS",             { eAX, Iv }, 0 },
2232   { X86_64_TABLE (X86_64_16) },
2233   { X86_64_TABLE (X86_64_17) },
2234   /* 18 */
2235   { "sbbB",             { Ebh1, Gb }, 0 },
2236   { "sbbS",             { Evh1, Gv }, 0 },
2237   { "sbbB",             { Gb, EbS }, 0 },
2238   { "sbbS",             { Gv, EvS }, 0 },
2239   { "sbbB",             { AL, Ib }, 0 },
2240   { "sbbS",             { eAX, Iv }, 0 },
2241   { X86_64_TABLE (X86_64_1E) },
2242   { X86_64_TABLE (X86_64_1F) },
2243   /* 20 */
2244   { "andB",             { Ebh1, Gb }, 0 },
2245   { "andS",             { Evh1, Gv }, 0 },
2246   { "andB",             { Gb, EbS }, 0 },
2247   { "andS",             { Gv, EvS }, 0 },
2248   { "andB",             { AL, Ib }, 0 },
2249   { "andS",             { eAX, Iv }, 0 },
2250   { Bad_Opcode },       /* SEG ES prefix */
2251   { X86_64_TABLE (X86_64_27) },
2252   /* 28 */
2253   { "subB",             { Ebh1, Gb }, 0 },
2254   { "subS",             { Evh1, Gv }, 0 },
2255   { "subB",             { Gb, EbS }, 0 },
2256   { "subS",             { Gv, EvS }, 0 },
2257   { "subB",             { AL, Ib }, 0 },
2258   { "subS",             { eAX, Iv }, 0 },
2259   { Bad_Opcode },       /* SEG CS prefix */
2260   { X86_64_TABLE (X86_64_2F) },
2261   /* 30 */
2262   { "xorB",             { Ebh1, Gb }, 0 },
2263   { "xorS",             { Evh1, Gv }, 0 },
2264   { "xorB",             { Gb, EbS }, 0 },
2265   { "xorS",             { Gv, EvS }, 0 },
2266   { "xorB",             { AL, Ib }, 0 },
2267   { "xorS",             { eAX, Iv }, 0 },
2268   { Bad_Opcode },       /* SEG SS prefix */
2269   { X86_64_TABLE (X86_64_37) },
2270   /* 38 */
2271   { "cmpB",             { Eb, Gb }, 0 },
2272   { "cmpS",             { Ev, Gv }, 0 },
2273   { "cmpB",             { Gb, EbS }, 0 },
2274   { "cmpS",             { Gv, EvS }, 0 },
2275   { "cmpB",             { AL, Ib }, 0 },
2276   { "cmpS",             { eAX, Iv }, 0 },
2277   { Bad_Opcode },       /* SEG DS prefix */
2278   { X86_64_TABLE (X86_64_3F) },
2279   /* 40 */
2280   { "inc{S|}",          { RMeAX }, 0 },
2281   { "inc{S|}",          { RMeCX }, 0 },
2282   { "inc{S|}",          { RMeDX }, 0 },
2283   { "inc{S|}",          { RMeBX }, 0 },
2284   { "inc{S|}",          { RMeSP }, 0 },
2285   { "inc{S|}",          { RMeBP }, 0 },
2286   { "inc{S|}",          { RMeSI }, 0 },
2287   { "inc{S|}",          { RMeDI }, 0 },
2288   /* 48 */
2289   { "dec{S|}",          { RMeAX }, 0 },
2290   { "dec{S|}",          { RMeCX }, 0 },
2291   { "dec{S|}",          { RMeDX }, 0 },
2292   { "dec{S|}",          { RMeBX }, 0 },
2293   { "dec{S|}",          { RMeSP }, 0 },
2294   { "dec{S|}",          { RMeBP }, 0 },
2295   { "dec{S|}",          { RMeSI }, 0 },
2296   { "dec{S|}",          { RMeDI }, 0 },
2297   /* 50 */
2298   { "pushV",            { RMrAX }, 0 },
2299   { "pushV",            { RMrCX }, 0 },
2300   { "pushV",            { RMrDX }, 0 },
2301   { "pushV",            { RMrBX }, 0 },
2302   { "pushV",            { RMrSP }, 0 },
2303   { "pushV",            { RMrBP }, 0 },
2304   { "pushV",            { RMrSI }, 0 },
2305   { "pushV",            { RMrDI }, 0 },
2306   /* 58 */
2307   { "popV",             { RMrAX }, 0 },
2308   { "popV",             { RMrCX }, 0 },
2309   { "popV",             { RMrDX }, 0 },
2310   { "popV",             { RMrBX }, 0 },
2311   { "popV",             { RMrSP }, 0 },
2312   { "popV",             { RMrBP }, 0 },
2313   { "popV",             { RMrSI }, 0 },
2314   { "popV",             { RMrDI }, 0 },
2315   /* 60 */
2316   { X86_64_TABLE (X86_64_60) },
2317   { X86_64_TABLE (X86_64_61) },
2318   { X86_64_TABLE (X86_64_62) },
2319   { X86_64_TABLE (X86_64_63) },
2320   { Bad_Opcode },       /* seg fs */
2321   { Bad_Opcode },       /* seg gs */
2322   { Bad_Opcode },       /* op size prefix */
2323   { Bad_Opcode },       /* adr size prefix */
2324   /* 68 */
2325   { "pushT",            { sIv }, 0 },
2326   { "imulS",            { Gv, Ev, Iv }, 0 },
2327   { "pushT",            { sIbT }, 0 },
2328   { "imulS",            { Gv, Ev, sIb }, 0 },
2329   { "ins{b|}",          { Ybr, indirDX }, 0 },
2330   { X86_64_TABLE (X86_64_6D) },
2331   { "outs{b|}",         { indirDXr, Xb }, 0 },
2332   { X86_64_TABLE (X86_64_6F) },
2333   /* 70 */
2334   { "joH",              { Jb, BND, cond_jump_flag }, 0 },
2335   { "jnoH",             { Jb, BND, cond_jump_flag }, 0 },
2336   { "jbH",              { Jb, BND, cond_jump_flag }, 0 },
2337   { "jaeH",             { Jb, BND, cond_jump_flag }, 0 },
2338   { "jeH",              { Jb, BND, cond_jump_flag }, 0 },
2339   { "jneH",             { Jb, BND, cond_jump_flag }, 0 },
2340   { "jbeH",             { Jb, BND, cond_jump_flag }, 0 },
2341   { "jaH",              { Jb, BND, cond_jump_flag }, 0 },
2342   /* 78 */
2343   { "jsH",              { Jb, BND, cond_jump_flag }, 0 },
2344   { "jnsH",             { Jb, BND, cond_jump_flag }, 0 },
2345   { "jpH",              { Jb, BND, cond_jump_flag }, 0 },
2346   { "jnpH",             { Jb, BND, cond_jump_flag }, 0 },
2347   { "jlH",              { Jb, BND, cond_jump_flag }, 0 },
2348   { "jgeH",             { Jb, BND, cond_jump_flag }, 0 },
2349   { "jleH",             { Jb, BND, cond_jump_flag }, 0 },
2350   { "jgH",              { Jb, BND, cond_jump_flag }, 0 },
2351   /* 80 */
2352   { REG_TABLE (REG_80) },
2353   { REG_TABLE (REG_81) },
2354   { X86_64_TABLE (X86_64_82) },
2355   { REG_TABLE (REG_83) },
2356   { "testB",            { Eb, Gb }, 0 },
2357   { "testS",            { Ev, Gv }, 0 },
2358   { "xchgB",            { Ebh2, Gb }, 0 },
2359   { "xchgS",            { Evh2, Gv }, 0 },
2360   /* 88 */
2361   { "movB",             { Ebh3, Gb }, 0 },
2362   { "movS",             { Evh3, Gv }, 0 },
2363   { "movB",             { Gb, EbS }, 0 },
2364   { "movS",             { Gv, EvS }, 0 },
2365   { "movD",             { Sv, Sw }, 0 },
2366   { MOD_TABLE (MOD_8D) },
2367   { "movD",             { Sw, Sv }, 0 },
2368   { REG_TABLE (REG_8F) },
2369   /* 90 */
2370   { PREFIX_TABLE (PREFIX_90) },
2371   { "xchgS",            { RMeCX, eAX }, 0 },
2372   { "xchgS",            { RMeDX, eAX }, 0 },
2373   { "xchgS",            { RMeBX, eAX }, 0 },
2374   { "xchgS",            { RMeSP, eAX }, 0 },
2375   { "xchgS",            { RMeBP, eAX }, 0 },
2376   { "xchgS",            { RMeSI, eAX }, 0 },
2377   { "xchgS",            { RMeDI, eAX }, 0 },
2378   /* 98 */
2379   { "cW{t|}R",          { XX }, 0 },
2380   { "cR{t|}O",          { XX }, 0 },
2381   { X86_64_TABLE (X86_64_9A) },
2382   { Bad_Opcode },       /* fwait */
2383   { "pushfT",           { XX }, 0 },
2384   { "popfT",            { XX }, 0 },
2385   { "sahf",             { XX }, 0 },
2386   { "lahf",             { XX }, 0 },
2387   /* a0 */
2388   { "mov%LB",           { AL, Ob }, 0 },
2389   { "mov%LS",           { eAX, Ov }, 0 },
2390   { "mov%LB",           { Ob, AL }, 0 },
2391   { "mov%LS",           { Ov, eAX }, 0 },
2392   { "movs{b|}",         { Ybr, Xb }, 0 },
2393   { "movs{R|}",         { Yvr, Xv }, 0 },
2394   { "cmps{b|}",         { Xb, Yb }, 0 },
2395   { "cmps{R|}",         { Xv, Yv }, 0 },
2396   /* a8 */
2397   { "testB",            { AL, Ib }, 0 },
2398   { "testS",            { eAX, Iv }, 0 },
2399   { "stosB",            { Ybr, AL }, 0 },
2400   { "stosS",            { Yvr, eAX }, 0 },
2401   { "lodsB",            { ALr, Xb }, 0 },
2402   { "lodsS",            { eAXr, Xv }, 0 },
2403   { "scasB",            { AL, Yb }, 0 },
2404   { "scasS",            { eAX, Yv }, 0 },
2405   /* b0 */
2406   { "movB",             { RMAL, Ib }, 0 },
2407   { "movB",             { RMCL, Ib }, 0 },
2408   { "movB",             { RMDL, Ib }, 0 },
2409   { "movB",             { RMBL, Ib }, 0 },
2410   { "movB",             { RMAH, Ib }, 0 },
2411   { "movB",             { RMCH, Ib }, 0 },
2412   { "movB",             { RMDH, Ib }, 0 },
2413   { "movB",             { RMBH, Ib }, 0 },
2414   /* b8 */
2415   { "mov%LV",           { RMeAX, Iv64 }, 0 },
2416   { "mov%LV",           { RMeCX, Iv64 }, 0 },
2417   { "mov%LV",           { RMeDX, Iv64 }, 0 },
2418   { "mov%LV",           { RMeBX, Iv64 }, 0 },
2419   { "mov%LV",           { RMeSP, Iv64 }, 0 },
2420   { "mov%LV",           { RMeBP, Iv64 }, 0 },
2421   { "mov%LV",           { RMeSI, Iv64 }, 0 },
2422   { "mov%LV",           { RMeDI, Iv64 }, 0 },
2423   /* c0 */
2424   { REG_TABLE (REG_C0) },
2425   { REG_TABLE (REG_C1) },
2426   { X86_64_TABLE (X86_64_C2) },
2427   { X86_64_TABLE (X86_64_C3) },
2428   { X86_64_TABLE (X86_64_C4) },
2429   { X86_64_TABLE (X86_64_C5) },
2430   { REG_TABLE (REG_C6) },
2431   { REG_TABLE (REG_C7) },
2432   /* c8 */
2433   { "enterT",           { Iw, Ib }, 0 },
2434   { "leaveT",           { XX }, 0 },
2435   { "{l|}ret{|f}P",     { Iw }, 0 },
2436   { "{l|}ret{|f}P",     { XX }, 0 },
2437   { "int3",             { XX }, 0 },
2438   { "int",              { Ib }, 0 },
2439   { X86_64_TABLE (X86_64_CE) },
2440   { "iret%LP",          { XX }, 0 },
2441   /* d0 */
2442   { REG_TABLE (REG_D0) },
2443   { REG_TABLE (REG_D1) },
2444   { REG_TABLE (REG_D2) },
2445   { REG_TABLE (REG_D3) },
2446   { X86_64_TABLE (X86_64_D4) },
2447   { X86_64_TABLE (X86_64_D5) },
2448   { Bad_Opcode },
2449   { "xlat",             { DSBX }, 0 },
2450   /* d8 */
2451   { FLOAT },
2452   { FLOAT },
2453   { FLOAT },
2454   { FLOAT },
2455   { FLOAT },
2456   { FLOAT },
2457   { FLOAT },
2458   { FLOAT },
2459   /* e0 */
2460   { "loopneFH",         { Jb, XX, loop_jcxz_flag }, 0 },
2461   { "loopeFH",          { Jb, XX, loop_jcxz_flag }, 0 },
2462   { "loopFH",           { Jb, XX, loop_jcxz_flag }, 0 },
2463   { "jEcxzH",           { Jb, XX, loop_jcxz_flag }, 0 },
2464   { "inB",              { AL, Ib }, 0 },
2465   { "inG",              { zAX, Ib }, 0 },
2466   { "outB",             { Ib, AL }, 0 },
2467   { "outG",             { Ib, zAX }, 0 },
2468   /* e8 */
2469   { X86_64_TABLE (X86_64_E8) },
2470   { X86_64_TABLE (X86_64_E9) },
2471   { X86_64_TABLE (X86_64_EA) },
2472   { "jmp",              { Jb, BND }, 0 },
2473   { "inB",              { AL, indirDX }, 0 },
2474   { "inG",              { zAX, indirDX }, 0 },
2475   { "outB",             { indirDX, AL }, 0 },
2476   { "outG",             { indirDX, zAX }, 0 },
2477   /* f0 */
2478   { Bad_Opcode },       /* lock prefix */
2479   { "icebp",            { XX }, 0 },
2480   { Bad_Opcode },       /* repne */
2481   { Bad_Opcode },       /* repz */
2482   { "hlt",              { XX }, 0 },
2483   { "cmc",              { XX }, 0 },
2484   { REG_TABLE (REG_F6) },
2485   { REG_TABLE (REG_F7) },
2486   /* f8 */
2487   { "clc",              { XX }, 0 },
2488   { "stc",              { XX }, 0 },
2489   { "cli",              { XX }, 0 },
2490   { "sti",              { XX }, 0 },
2491   { "cld",              { XX }, 0 },
2492   { "std",              { XX }, 0 },
2493   { REG_TABLE (REG_FE) },
2494   { REG_TABLE (REG_FF) },
2495 };
2496
2497 static const struct dis386 dis386_twobyte[] = {
2498   /* 00 */
2499   { REG_TABLE (REG_0F00 ) },
2500   { REG_TABLE (REG_0F01 ) },
2501   { "larS",             { Gv, Ew }, 0 },
2502   { "lslS",             { Gv, Ew }, 0 },
2503   { Bad_Opcode },
2504   { "syscall",          { XX }, 0 },
2505   { "clts",             { XX }, 0 },
2506   { "sysret%LQ",                { XX }, 0 },
2507   /* 08 */
2508   { "invd",             { XX }, 0 },
2509   { PREFIX_TABLE (PREFIX_0F09) },
2510   { Bad_Opcode },
2511   { "ud2",              { XX }, 0 },
2512   { Bad_Opcode },
2513   { REG_TABLE (REG_0F0D) },
2514   { "femms",            { XX }, 0 },
2515   { "",                 { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix.  */
2516   /* 10 */
2517   { PREFIX_TABLE (PREFIX_0F10) },
2518   { PREFIX_TABLE (PREFIX_0F11) },
2519   { PREFIX_TABLE (PREFIX_0F12) },
2520   { MOD_TABLE (MOD_0F13) },
2521   { "unpcklpX",         { XM, EXx }, PREFIX_OPCODE },
2522   { "unpckhpX",         { XM, EXx }, PREFIX_OPCODE },
2523   { PREFIX_TABLE (PREFIX_0F16) },
2524   { MOD_TABLE (MOD_0F17) },
2525   /* 18 */
2526   { REG_TABLE (REG_0F18) },
2527   { "nopQ",             { Ev }, 0 },
2528   { PREFIX_TABLE (PREFIX_0F1A) },
2529   { PREFIX_TABLE (PREFIX_0F1B) },
2530   { PREFIX_TABLE (PREFIX_0F1C) },
2531   { "nopQ",             { Ev }, 0 },
2532   { PREFIX_TABLE (PREFIX_0F1E) },
2533   { "nopQ",             { Ev }, 0 },
2534   /* 20 */
2535   { "movZ",             { Rm, Cm }, 0 },
2536   { "movZ",             { Rm, Dm }, 0 },
2537   { "movZ",             { Cm, Rm }, 0 },
2538   { "movZ",             { Dm, Rm }, 0 },
2539   { MOD_TABLE (MOD_0F24) },
2540   { Bad_Opcode },
2541   { MOD_TABLE (MOD_0F26) },
2542   { Bad_Opcode },
2543   /* 28 */
2544   { "movapX",           { XM, EXx }, PREFIX_OPCODE },
2545   { "movapX",           { EXxS, XM }, PREFIX_OPCODE },
2546   { PREFIX_TABLE (PREFIX_0F2A) },
2547   { PREFIX_TABLE (PREFIX_0F2B) },
2548   { PREFIX_TABLE (PREFIX_0F2C) },
2549   { PREFIX_TABLE (PREFIX_0F2D) },
2550   { PREFIX_TABLE (PREFIX_0F2E) },
2551   { PREFIX_TABLE (PREFIX_0F2F) },
2552   /* 30 */
2553   { "wrmsr",            { XX }, 0 },
2554   { "rdtsc",            { XX }, 0 },
2555   { "rdmsr",            { XX }, 0 },
2556   { "rdpmc",            { XX }, 0 },
2557   { "sysenter",         { SEP }, 0 },
2558   { "sysexit",          { SEP }, 0 },
2559   { Bad_Opcode },
2560   { "getsec",           { XX }, 0 },
2561   /* 38 */
2562   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) },
2563   { Bad_Opcode },
2564   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) },
2565   { Bad_Opcode },
2566   { Bad_Opcode },
2567   { Bad_Opcode },
2568   { Bad_Opcode },
2569   { Bad_Opcode },
2570   /* 40 */
2571   { "cmovoS",           { Gv, Ev }, 0 },
2572   { "cmovnoS",          { Gv, Ev }, 0 },
2573   { "cmovbS",           { Gv, Ev }, 0 },
2574   { "cmovaeS",          { Gv, Ev }, 0 },
2575   { "cmoveS",           { Gv, Ev }, 0 },
2576   { "cmovneS",          { Gv, Ev }, 0 },
2577   { "cmovbeS",          { Gv, Ev }, 0 },
2578   { "cmovaS",           { Gv, Ev }, 0 },
2579   /* 48 */
2580   { "cmovsS",           { Gv, Ev }, 0 },
2581   { "cmovnsS",          { Gv, Ev }, 0 },
2582   { "cmovpS",           { Gv, Ev }, 0 },
2583   { "cmovnpS",          { Gv, Ev }, 0 },
2584   { "cmovlS",           { Gv, Ev }, 0 },
2585   { "cmovgeS",          { Gv, Ev }, 0 },
2586   { "cmovleS",          { Gv, Ev }, 0 },
2587   { "cmovgS",           { Gv, Ev }, 0 },
2588   /* 50 */
2589   { MOD_TABLE (MOD_0F50) },
2590   { PREFIX_TABLE (PREFIX_0F51) },
2591   { PREFIX_TABLE (PREFIX_0F52) },
2592   { PREFIX_TABLE (PREFIX_0F53) },
2593   { "andpX",            { XM, EXx }, PREFIX_OPCODE },
2594   { "andnpX",           { XM, EXx }, PREFIX_OPCODE },
2595   { "orpX",             { XM, EXx }, PREFIX_OPCODE },
2596   { "xorpX",            { XM, EXx }, PREFIX_OPCODE },
2597   /* 58 */
2598   { PREFIX_TABLE (PREFIX_0F58) },
2599   { PREFIX_TABLE (PREFIX_0F59) },
2600   { PREFIX_TABLE (PREFIX_0F5A) },
2601   { PREFIX_TABLE (PREFIX_0F5B) },
2602   { PREFIX_TABLE (PREFIX_0F5C) },
2603   { PREFIX_TABLE (PREFIX_0F5D) },
2604   { PREFIX_TABLE (PREFIX_0F5E) },
2605   { PREFIX_TABLE (PREFIX_0F5F) },
2606   /* 60 */
2607   { PREFIX_TABLE (PREFIX_0F60) },
2608   { PREFIX_TABLE (PREFIX_0F61) },
2609   { PREFIX_TABLE (PREFIX_0F62) },
2610   { "packsswb",         { MX, EM }, PREFIX_OPCODE },
2611   { "pcmpgtb",          { MX, EM }, PREFIX_OPCODE },
2612   { "pcmpgtw",          { MX, EM }, PREFIX_OPCODE },
2613   { "pcmpgtd",          { MX, EM }, PREFIX_OPCODE },
2614   { "packuswb",         { MX, EM }, PREFIX_OPCODE },
2615   /* 68 */
2616   { "punpckhbw",        { MX, EM }, PREFIX_OPCODE },
2617   { "punpckhwd",        { MX, EM }, PREFIX_OPCODE },
2618   { "punpckhdq",        { MX, EM }, PREFIX_OPCODE },
2619   { "packssdw",         { MX, EM }, PREFIX_OPCODE },
2620   { PREFIX_TABLE (PREFIX_0F6C) },
2621   { PREFIX_TABLE (PREFIX_0F6D) },
2622   { "movK",             { MX, Edq }, PREFIX_OPCODE },
2623   { PREFIX_TABLE (PREFIX_0F6F) },
2624   /* 70 */
2625   { PREFIX_TABLE (PREFIX_0F70) },
2626   { REG_TABLE (REG_0F71) },
2627   { REG_TABLE (REG_0F72) },
2628   { REG_TABLE (REG_0F73) },
2629   { "pcmpeqb",          { MX, EM }, PREFIX_OPCODE },
2630   { "pcmpeqw",          { MX, EM }, PREFIX_OPCODE },
2631   { "pcmpeqd",          { MX, EM }, PREFIX_OPCODE },
2632   { "emms",             { XX }, PREFIX_OPCODE },
2633   /* 78 */
2634   { PREFIX_TABLE (PREFIX_0F78) },
2635   { PREFIX_TABLE (PREFIX_0F79) },
2636   { Bad_Opcode },
2637   { Bad_Opcode },
2638   { PREFIX_TABLE (PREFIX_0F7C) },
2639   { PREFIX_TABLE (PREFIX_0F7D) },
2640   { PREFIX_TABLE (PREFIX_0F7E) },
2641   { PREFIX_TABLE (PREFIX_0F7F) },
2642   /* 80 */
2643   { "joH",              { Jv, BND, cond_jump_flag }, 0 },
2644   { "jnoH",             { Jv, BND, cond_jump_flag }, 0 },
2645   { "jbH",              { Jv, BND, cond_jump_flag }, 0 },
2646   { "jaeH",             { Jv, BND, cond_jump_flag }, 0 },
2647   { "jeH",              { Jv, BND, cond_jump_flag }, 0 },
2648   { "jneH",             { Jv, BND, cond_jump_flag }, 0 },
2649   { "jbeH",             { Jv, BND, cond_jump_flag }, 0 },
2650   { "jaH",              { Jv, BND, cond_jump_flag }, 0 },
2651   /* 88 */
2652   { "jsH",              { Jv, BND, cond_jump_flag }, 0 },
2653   { "jnsH",             { Jv, BND, cond_jump_flag }, 0 },
2654   { "jpH",              { Jv, BND, cond_jump_flag }, 0 },
2655   { "jnpH",             { Jv, BND, cond_jump_flag }, 0 },
2656   { "jlH",              { Jv, BND, cond_jump_flag }, 0 },
2657   { "jgeH",             { Jv, BND, cond_jump_flag }, 0 },
2658   { "jleH",             { Jv, BND, cond_jump_flag }, 0 },
2659   { "jgH",              { Jv, BND, cond_jump_flag }, 0 },
2660   /* 90 */
2661   { "seto",             { Eb }, 0 },
2662   { "setno",            { Eb }, 0 },
2663   { "setb",             { Eb }, 0 },
2664   { "setae",            { Eb }, 0 },
2665   { "sete",             { Eb }, 0 },
2666   { "setne",            { Eb }, 0 },
2667   { "setbe",            { Eb }, 0 },
2668   { "seta",             { Eb }, 0 },
2669   /* 98 */
2670   { "sets",             { Eb }, 0 },
2671   { "setns",            { Eb }, 0 },
2672   { "setp",             { Eb }, 0 },
2673   { "setnp",            { Eb }, 0 },
2674   { "setl",             { Eb }, 0 },
2675   { "setge",            { Eb }, 0 },
2676   { "setle",            { Eb }, 0 },
2677   { "setg",             { Eb }, 0 },
2678   /* a0 */
2679   { "pushT",            { fs }, 0 },
2680   { "popT",             { fs }, 0 },
2681   { "cpuid",            { XX }, 0 },
2682   { "btS",              { Ev, Gv }, 0 },
2683   { "shldS",            { Ev, Gv, Ib }, 0 },
2684   { "shldS",            { Ev, Gv, CL }, 0 },
2685   { REG_TABLE (REG_0FA6) },
2686   { REG_TABLE (REG_0FA7) },
2687   /* a8 */
2688   { "pushT",            { gs }, 0 },
2689   { "popT",             { gs }, 0 },
2690   { "rsm",              { XX }, 0 },
2691   { "btsS",             { Evh1, Gv }, 0 },
2692   { "shrdS",            { Ev, Gv, Ib }, 0 },
2693   { "shrdS",            { Ev, Gv, CL }, 0 },
2694   { REG_TABLE (REG_0FAE) },
2695   { "imulS",            { Gv, Ev }, 0 },
2696   /* b0 */
2697   { "cmpxchgB",         { Ebh1, Gb }, 0 },
2698   { "cmpxchgS",         { Evh1, Gv }, 0 },
2699   { MOD_TABLE (MOD_0FB2) },
2700   { "btrS",             { Evh1, Gv }, 0 },
2701   { MOD_TABLE (MOD_0FB4) },
2702   { MOD_TABLE (MOD_0FB5) },
2703   { "movz{bR|x}",       { Gv, Eb }, 0 },
2704   { "movz{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movzww ! */
2705   /* b8 */
2706   { PREFIX_TABLE (PREFIX_0FB8) },
2707   { "ud1S",             { Gv, Ev }, 0 },
2708   { REG_TABLE (REG_0FBA) },
2709   { "btcS",             { Evh1, Gv }, 0 },
2710   { PREFIX_TABLE (PREFIX_0FBC) },
2711   { PREFIX_TABLE (PREFIX_0FBD) },
2712   { "movs{bR|x}",       { Gv, Eb }, 0 },
2713   { "movs{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movsww ! */
2714   /* c0 */
2715   { "xaddB",            { Ebh1, Gb }, 0 },
2716   { "xaddS",            { Evh1, Gv }, 0 },
2717   { PREFIX_TABLE (PREFIX_0FC2) },
2718   { MOD_TABLE (MOD_0FC3) },
2719   { "pinsrw",           { MX, Edqw, Ib }, PREFIX_OPCODE },
2720   { "pextrw",           { Gdq, MS, Ib }, PREFIX_OPCODE },
2721   { "shufpX",           { XM, EXx, Ib }, PREFIX_OPCODE },
2722   { REG_TABLE (REG_0FC7) },
2723   /* c8 */
2724   { "bswap",            { RMeAX }, 0 },
2725   { "bswap",            { RMeCX }, 0 },
2726   { "bswap",            { RMeDX }, 0 },
2727   { "bswap",            { RMeBX }, 0 },
2728   { "bswap",            { RMeSP }, 0 },
2729   { "bswap",            { RMeBP }, 0 },
2730   { "bswap",            { RMeSI }, 0 },
2731   { "bswap",            { RMeDI }, 0 },
2732   /* d0 */
2733   { PREFIX_TABLE (PREFIX_0FD0) },
2734   { "psrlw",            { MX, EM }, PREFIX_OPCODE },
2735   { "psrld",            { MX, EM }, PREFIX_OPCODE },
2736   { "psrlq",            { MX, EM }, PREFIX_OPCODE },
2737   { "paddq",            { MX, EM }, PREFIX_OPCODE },
2738   { "pmullw",           { MX, EM }, PREFIX_OPCODE },
2739   { PREFIX_TABLE (PREFIX_0FD6) },
2740   { MOD_TABLE (MOD_0FD7) },
2741   /* d8 */
2742   { "psubusb",          { MX, EM }, PREFIX_OPCODE },
2743   { "psubusw",          { MX, EM }, PREFIX_OPCODE },
2744   { "pminub",           { MX, EM }, PREFIX_OPCODE },
2745   { "pand",             { MX, EM }, PREFIX_OPCODE },
2746   { "paddusb",          { MX, EM }, PREFIX_OPCODE },
2747   { "paddusw",          { MX, EM }, PREFIX_OPCODE },
2748   { "pmaxub",           { MX, EM }, PREFIX_OPCODE },
2749   { "pandn",            { MX, EM }, PREFIX_OPCODE },
2750   /* e0 */
2751   { "pavgb",            { MX, EM }, PREFIX_OPCODE },
2752   { "psraw",            { MX, EM }, PREFIX_OPCODE },
2753   { "psrad",            { MX, EM }, PREFIX_OPCODE },
2754   { "pavgw",            { MX, EM }, PREFIX_OPCODE },
2755   { "pmulhuw",          { MX, EM }, PREFIX_OPCODE },
2756   { "pmulhw",           { MX, EM }, PREFIX_OPCODE },
2757   { PREFIX_TABLE (PREFIX_0FE6) },
2758   { PREFIX_TABLE (PREFIX_0FE7) },
2759   /* e8 */
2760   { "psubsb",           { MX, EM }, PREFIX_OPCODE },
2761   { "psubsw",           { MX, EM }, PREFIX_OPCODE },
2762   { "pminsw",           { MX, EM }, PREFIX_OPCODE },
2763   { "por",              { MX, EM }, PREFIX_OPCODE },
2764   { "paddsb",           { MX, EM }, PREFIX_OPCODE },
2765   { "paddsw",           { MX, EM }, PREFIX_OPCODE },
2766   { "pmaxsw",           { MX, EM }, PREFIX_OPCODE },
2767   { "pxor",             { MX, EM }, PREFIX_OPCODE },
2768   /* f0 */
2769   { PREFIX_TABLE (PREFIX_0FF0) },
2770   { "psllw",            { MX, EM }, PREFIX_OPCODE },
2771   { "pslld",            { MX, EM }, PREFIX_OPCODE },
2772   { "psllq",            { MX, EM }, PREFIX_OPCODE },
2773   { "pmuludq",          { MX, EM }, PREFIX_OPCODE },
2774   { "pmaddwd",          { MX, EM }, PREFIX_OPCODE },
2775   { "psadbw",           { MX, EM }, PREFIX_OPCODE },
2776   { PREFIX_TABLE (PREFIX_0FF7) },
2777   /* f8 */
2778   { "psubb",            { MX, EM }, PREFIX_OPCODE },
2779   { "psubw",            { MX, EM }, PREFIX_OPCODE },
2780   { "psubd",            { MX, EM }, PREFIX_OPCODE },
2781   { "psubq",            { MX, EM }, PREFIX_OPCODE },
2782   { "paddb",            { MX, EM }, PREFIX_OPCODE },
2783   { "paddw",            { MX, EM }, PREFIX_OPCODE },
2784   { "paddd",            { MX, EM }, PREFIX_OPCODE },
2785   { "ud0S",             { Gv, Ev }, 0 },
2786 };
2787
2788 static const unsigned char onebyte_has_modrm[256] = {
2789   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2790   /*       -------------------------------        */
2791   /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2792   /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2793   /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2794   /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2795   /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2796   /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2797   /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2798   /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2799   /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2800   /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2801   /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2802   /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2803   /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2804   /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2805   /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2806   /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1  /* f0 */
2807   /*       -------------------------------        */
2808   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2809 };
2810
2811 static const unsigned char twobyte_has_modrm[256] = {
2812   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2813   /*       -------------------------------        */
2814   /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2815   /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2816   /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2817   /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2818   /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2819   /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2820   /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2821   /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2822   /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2823   /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2824   /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2825   /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */
2826   /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2827   /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2828   /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2829   /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1  /* ff */
2830   /*       -------------------------------        */
2831   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2832 };
2833
2834 static char obuf[100];
2835 static char *obufp;
2836 static char *mnemonicendp;
2837 static char scratchbuf[100];
2838 static unsigned char *start_codep;
2839 static unsigned char *insn_codep;
2840 static unsigned char *codep;
2841 static unsigned char *end_codep;
2842 static int last_lock_prefix;
2843 static int last_repz_prefix;
2844 static int last_repnz_prefix;
2845 static int last_data_prefix;
2846 static int last_addr_prefix;
2847 static int last_rex_prefix;
2848 static int last_seg_prefix;
2849 static int fwait_prefix;
2850 /* The active segment register prefix.  */
2851 static int active_seg_prefix;
2852 #define MAX_CODE_LENGTH 15
2853 /* We can up to 14 prefixes since the maximum instruction length is
2854    15bytes.  */
2855 static int all_prefixes[MAX_CODE_LENGTH - 1];
2856 static disassemble_info *the_info;
2857 static struct
2858   {
2859     int mod;
2860     int reg;
2861     int rm;
2862   }
2863 modrm;
2864 static unsigned char need_modrm;
2865 static struct
2866   {
2867     int scale;
2868     int index;
2869     int base;
2870   }
2871 sib;
2872 static struct
2873   {
2874     int register_specifier;
2875     int length;
2876     int prefix;
2877     int w;
2878     int evex;
2879     int r;
2880     int v;
2881     int mask_register_specifier;
2882     int zeroing;
2883     int ll;
2884     int b;
2885   }
2886 vex;
2887 static unsigned char need_vex;
2888 static unsigned char need_vex_reg;
2889 static unsigned char vex_w_done;
2890
2891 struct op
2892   {
2893     const char *name;
2894     unsigned int len;
2895   };
2896
2897 /* If we are accessing mod/rm/reg without need_modrm set, then the
2898    values are stale.  Hitting this abort likely indicates that you
2899    need to update onebyte_has_modrm or twobyte_has_modrm.  */
2900 #define MODRM_CHECK  if (!need_modrm) abort ()
2901
2902 static const char **names64;
2903 static const char **names32;
2904 static const char **names16;
2905 static const char **names8;
2906 static const char **names8rex;
2907 static const char **names_seg;
2908 static const char *index64;
2909 static const char *index32;
2910 static const char **index16;
2911 static const char **names_bnd;
2912
2913 static const char *intel_names64[] = {
2914   "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
2915   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
2916 };
2917 static const char *intel_names32[] = {
2918   "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
2919   "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
2920 };
2921 static const char *intel_names16[] = {
2922   "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
2923   "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
2924 };
2925 static const char *intel_names8[] = {
2926   "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
2927 };
2928 static const char *intel_names8rex[] = {
2929   "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
2930   "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
2931 };
2932 static const char *intel_names_seg[] = {
2933   "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
2934 };
2935 static const char *intel_index64 = "riz";
2936 static const char *intel_index32 = "eiz";
2937 static const char *intel_index16[] = {
2938   "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
2939 };
2940
2941 static const char *att_names64[] = {
2942   "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
2943   "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
2944 };
2945 static const char *att_names32[] = {
2946   "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
2947   "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
2948 };
2949 static const char *att_names16[] = {
2950   "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
2951   "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
2952 };
2953 static const char *att_names8[] = {
2954   "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
2955 };
2956 static const char *att_names8rex[] = {
2957   "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
2958   "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
2959 };
2960 static const char *att_names_seg[] = {
2961   "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
2962 };
2963 static const char *att_index64 = "%riz";
2964 static const char *att_index32 = "%eiz";
2965 static const char *att_index16[] = {
2966   "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
2967 };
2968
2969 static const char **names_mm;
2970 static const char *intel_names_mm[] = {
2971   "mm0", "mm1", "mm2", "mm3",
2972   "mm4", "mm5", "mm6", "mm7"
2973 };
2974 static const char *att_names_mm[] = {
2975   "%mm0", "%mm1", "%mm2", "%mm3",
2976   "%mm4", "%mm5", "%mm6", "%mm7"
2977 };
2978
2979 static const char *intel_names_bnd[] = {
2980   "bnd0", "bnd1", "bnd2", "bnd3"
2981 };
2982
2983 static const char *att_names_bnd[] = {
2984   "%bnd0", "%bnd1", "%bnd2", "%bnd3"
2985 };
2986
2987 static const char **names_xmm;
2988 static const char *intel_names_xmm[] = {
2989   "xmm0", "xmm1", "xmm2", "xmm3",
2990   "xmm4", "xmm5", "xmm6", "xmm7",
2991   "xmm8", "xmm9", "xmm10", "xmm11",
2992   "xmm12", "xmm13", "xmm14", "xmm15",
2993   "xmm16", "xmm17", "xmm18", "xmm19",
2994   "xmm20", "xmm21", "xmm22", "xmm23",
2995   "xmm24", "xmm25", "xmm26", "xmm27",
2996   "xmm28", "xmm29", "xmm30", "xmm31"
2997 };
2998 static const char *att_names_xmm[] = {
2999   "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3000   "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3001   "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3002   "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3003   "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3004   "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3005   "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3006   "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3007 };
3008
3009 static const char **names_ymm;
3010 static const char *intel_names_ymm[] = {
3011   "ymm0", "ymm1", "ymm2", "ymm3",
3012   "ymm4", "ymm5", "ymm6", "ymm7",
3013   "ymm8", "ymm9", "ymm10", "ymm11",
3014   "ymm12", "ymm13", "ymm14", "ymm15",
3015   "ymm16", "ymm17", "ymm18", "ymm19",
3016   "ymm20", "ymm21", "ymm22", "ymm23",
3017   "ymm24", "ymm25", "ymm26", "ymm27",
3018   "ymm28", "ymm29", "ymm30", "ymm31"
3019 };
3020 static const char *att_names_ymm[] = {
3021   "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3022   "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3023   "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3024   "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3025   "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3026   "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3027   "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3028   "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3029 };
3030
3031 static const char **names_zmm;
3032 static const char *intel_names_zmm[] = {
3033   "zmm0", "zmm1", "zmm2", "zmm3",
3034   "zmm4", "zmm5", "zmm6", "zmm7",
3035   "zmm8", "zmm9", "zmm10", "zmm11",
3036   "zmm12", "zmm13", "zmm14", "zmm15",
3037   "zmm16", "zmm17", "zmm18", "zmm19",
3038   "zmm20", "zmm21", "zmm22", "zmm23",
3039   "zmm24", "zmm25", "zmm26", "zmm27",
3040   "zmm28", "zmm29", "zmm30", "zmm31"
3041 };
3042 static const char *att_names_zmm[] = {
3043   "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3044   "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3045   "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3046   "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3047   "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3048   "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3049   "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3050   "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3051 };
3052
3053 static const char **names_mask;
3054 static const char *intel_names_mask[] = {
3055   "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3056 };
3057 static const char *att_names_mask[] = {
3058   "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3059 };
3060
3061 static const char *names_rounding[] =
3062 {
3063   "{rn-sae}",
3064   "{rd-sae}",
3065   "{ru-sae}",
3066   "{rz-sae}"
3067 };
3068
3069 static const struct dis386 reg_table[][8] = {
3070   /* REG_80 */
3071   {
3072     { "addA",   { Ebh1, Ib }, 0 },
3073     { "orA",    { Ebh1, Ib }, 0 },
3074     { "adcA",   { Ebh1, Ib }, 0 },
3075     { "sbbA",   { Ebh1, Ib }, 0 },
3076     { "andA",   { Ebh1, Ib }, 0 },
3077     { "subA",   { Ebh1, Ib }, 0 },
3078     { "xorA",   { Ebh1, Ib }, 0 },
3079     { "cmpA",   { Eb, Ib }, 0 },
3080   },
3081   /* REG_81 */
3082   {
3083     { "addQ",   { Evh1, Iv }, 0 },
3084     { "orQ",    { Evh1, Iv }, 0 },
3085     { "adcQ",   { Evh1, Iv }, 0 },
3086     { "sbbQ",   { Evh1, Iv }, 0 },
3087     { "andQ",   { Evh1, Iv }, 0 },
3088     { "subQ",   { Evh1, Iv }, 0 },
3089     { "xorQ",   { Evh1, Iv }, 0 },
3090     { "cmpQ",   { Ev, Iv }, 0 },
3091   },
3092   /* REG_83 */
3093   {
3094     { "addQ",   { Evh1, sIb }, 0 },
3095     { "orQ",    { Evh1, sIb }, 0 },
3096     { "adcQ",   { Evh1, sIb }, 0 },
3097     { "sbbQ",   { Evh1, sIb }, 0 },
3098     { "andQ",   { Evh1, sIb }, 0 },
3099     { "subQ",   { Evh1, sIb }, 0 },
3100     { "xorQ",   { Evh1, sIb }, 0 },
3101     { "cmpQ",   { Ev, sIb }, 0 },
3102   },
3103   /* REG_8F */
3104   {
3105     { "popU",   { stackEv }, 0 },
3106     { XOP_8F_TABLE (XOP_09) },
3107     { Bad_Opcode },
3108     { Bad_Opcode },
3109     { Bad_Opcode },
3110     { XOP_8F_TABLE (XOP_09) },
3111   },
3112   /* REG_C0 */
3113   {
3114     { "rolA",   { Eb, Ib }, 0 },
3115     { "rorA",   { Eb, Ib }, 0 },
3116     { "rclA",   { Eb, Ib }, 0 },
3117     { "rcrA",   { Eb, Ib }, 0 },
3118     { "shlA",   { Eb, Ib }, 0 },
3119     { "shrA",   { Eb, Ib }, 0 },
3120     { "shlA",   { Eb, Ib }, 0 },
3121     { "sarA",   { Eb, Ib }, 0 },
3122   },
3123   /* REG_C1 */
3124   {
3125     { "rolQ",   { Ev, Ib }, 0 },
3126     { "rorQ",   { Ev, Ib }, 0 },
3127     { "rclQ",   { Ev, Ib }, 0 },
3128     { "rcrQ",   { Ev, Ib }, 0 },
3129     { "shlQ",   { Ev, Ib }, 0 },
3130     { "shrQ",   { Ev, Ib }, 0 },
3131     { "shlQ",   { Ev, Ib }, 0 },
3132     { "sarQ",   { Ev, Ib }, 0 },
3133   },
3134   /* REG_C6 */
3135   {
3136     { "movA",   { Ebh3, Ib }, 0 },
3137     { Bad_Opcode },
3138     { Bad_Opcode },
3139     { Bad_Opcode },
3140     { Bad_Opcode },
3141     { Bad_Opcode },
3142     { Bad_Opcode },
3143     { MOD_TABLE (MOD_C6_REG_7) },
3144   },
3145   /* REG_C7 */
3146   {
3147     { "movQ",   { Evh3, Iv }, 0 },
3148     { Bad_Opcode },
3149     { Bad_Opcode },
3150     { Bad_Opcode },
3151     { Bad_Opcode },
3152     { Bad_Opcode },
3153     { Bad_Opcode },
3154     { MOD_TABLE (MOD_C7_REG_7) },
3155   },
3156   /* REG_D0 */
3157   {
3158     { "rolA",   { Eb, I1 }, 0 },
3159     { "rorA",   { Eb, I1 }, 0 },
3160     { "rclA",   { Eb, I1 }, 0 },
3161     { "rcrA",   { Eb, I1 }, 0 },
3162     { "shlA",   { Eb, I1 }, 0 },
3163     { "shrA",   { Eb, I1 }, 0 },
3164     { "shlA",   { Eb, I1 }, 0 },
3165     { "sarA",   { Eb, I1 }, 0 },
3166   },
3167   /* REG_D1 */
3168   {
3169     { "rolQ",   { Ev, I1 }, 0 },
3170     { "rorQ",   { Ev, I1 }, 0 },
3171     { "rclQ",   { Ev, I1 }, 0 },
3172     { "rcrQ",   { Ev, I1 }, 0 },
3173     { "shlQ",   { Ev, I1 }, 0 },
3174     { "shrQ",   { Ev, I1 }, 0 },
3175     { "shlQ",   { Ev, I1 }, 0 },
3176     { "sarQ",   { Ev, I1 }, 0 },
3177   },
3178   /* REG_D2 */
3179   {
3180     { "rolA",   { Eb, CL }, 0 },
3181     { "rorA",   { Eb, CL }, 0 },
3182     { "rclA",   { Eb, CL }, 0 },
3183     { "rcrA",   { Eb, CL }, 0 },
3184     { "shlA",   { Eb, CL }, 0 },
3185     { "shrA",   { Eb, CL }, 0 },
3186     { "shlA",   { Eb, CL }, 0 },
3187     { "sarA",   { Eb, CL }, 0 },
3188   },
3189   /* REG_D3 */
3190   {
3191     { "rolQ",   { Ev, CL }, 0 },
3192     { "rorQ",   { Ev, CL }, 0 },
3193     { "rclQ",   { Ev, CL }, 0 },
3194     { "rcrQ",   { Ev, CL }, 0 },
3195     { "shlQ",   { Ev, CL }, 0 },
3196     { "shrQ",   { Ev, CL }, 0 },
3197     { "shlQ",   { Ev, CL }, 0 },
3198     { "sarQ",   { Ev, CL }, 0 },
3199   },
3200   /* REG_F6 */
3201   {
3202     { "testA",  { Eb, Ib }, 0 },
3203     { "testA",  { Eb, Ib }, 0 },
3204     { "notA",   { Ebh1 }, 0 },
3205     { "negA",   { Ebh1 }, 0 },
3206     { "mulA",   { Eb }, 0 },    /* Don't print the implicit %al register,  */
3207     { "imulA",  { Eb }, 0 },    /* to distinguish these opcodes from other */
3208     { "divA",   { Eb }, 0 },    /* mul/imul opcodes.  Do the same for div  */
3209     { "idivA",  { Eb }, 0 },    /* and idiv for consistency.               */
3210   },
3211   /* REG_F7 */
3212   {
3213     { "testQ",  { Ev, Iv }, 0 },
3214     { "testQ",  { Ev, Iv }, 0 },
3215     { "notQ",   { Evh1 }, 0 },
3216     { "negQ",   { Evh1 }, 0 },
3217     { "mulQ",   { Ev }, 0 },    /* Don't print the implicit register.  */
3218     { "imulQ",  { Ev }, 0 },
3219     { "divQ",   { Ev }, 0 },
3220     { "idivQ",  { Ev }, 0 },
3221   },
3222   /* REG_FE */
3223   {
3224     { "incA",   { Ebh1 }, 0 },
3225     { "decA",   { Ebh1 }, 0 },
3226   },
3227   /* REG_FF */
3228   {
3229     { "incQ",   { Evh1 }, 0 },
3230     { "decQ",   { Evh1 }, 0 },
3231     { "call{&|}", { NOTRACK, indirEv, BND }, 0 },
3232     { MOD_TABLE (MOD_FF_REG_3) },
3233     { "jmp{&|}", { NOTRACK, indirEv, BND }, 0 },
3234     { MOD_TABLE (MOD_FF_REG_5) },
3235     { "pushU",  { stackEv }, 0 },
3236     { Bad_Opcode },
3237   },
3238   /* REG_0F00 */
3239   {
3240     { "sldtD",  { Sv }, 0 },
3241     { "strD",   { Sv }, 0 },
3242     { "lldt",   { Ew }, 0 },
3243     { "ltr",    { Ew }, 0 },
3244     { "verr",   { Ew }, 0 },
3245     { "verw",   { Ew }, 0 },
3246     { Bad_Opcode },
3247     { Bad_Opcode },
3248   },
3249   /* REG_0F01 */
3250   {
3251     { MOD_TABLE (MOD_0F01_REG_0) },
3252     { MOD_TABLE (MOD_0F01_REG_1) },
3253     { MOD_TABLE (MOD_0F01_REG_2) },
3254     { MOD_TABLE (MOD_0F01_REG_3) },
3255     { "smswD",  { Sv }, 0 },
3256     { MOD_TABLE (MOD_0F01_REG_5) },
3257     { "lmsw",   { Ew }, 0 },
3258     { MOD_TABLE (MOD_0F01_REG_7) },
3259   },
3260   /* REG_0F0D */
3261   {
3262     { "prefetch",       { Mb }, 0 },
3263     { "prefetchw",      { Mb }, 0 },
3264     { "prefetchwt1",    { Mb }, 0 },
3265     { "prefetch",       { Mb }, 0 },
3266     { "prefetch",       { Mb }, 0 },
3267     { "prefetch",       { Mb }, 0 },
3268     { "prefetch",       { Mb }, 0 },
3269     { "prefetch",       { Mb }, 0 },
3270   },
3271   /* REG_0F18 */
3272   {
3273     { MOD_TABLE (MOD_0F18_REG_0) },
3274     { MOD_TABLE (MOD_0F18_REG_1) },
3275     { MOD_TABLE (MOD_0F18_REG_2) },
3276     { MOD_TABLE (MOD_0F18_REG_3) },
3277     { MOD_TABLE (MOD_0F18_REG_4) },
3278     { MOD_TABLE (MOD_0F18_REG_5) },
3279     { MOD_TABLE (MOD_0F18_REG_6) },
3280     { MOD_TABLE (MOD_0F18_REG_7) },
3281   },
3282   /* REG_0F1C_P_0_MOD_0 */
3283   {
3284     { "cldemote",       { Mb }, 0 },
3285     { "nopQ",           { Ev }, 0 },
3286     { "nopQ",           { Ev }, 0 },
3287     { "nopQ",           { Ev }, 0 },
3288     { "nopQ",           { Ev }, 0 },
3289     { "nopQ",           { Ev }, 0 },
3290     { "nopQ",           { Ev }, 0 },
3291     { "nopQ",           { Ev }, 0 },
3292   },
3293   /* REG_0F1E_P_1_MOD_3 */
3294   {
3295     { "nopQ",           { Ev }, 0 },
3296     { "rdsspK",         { Rdq }, PREFIX_OPCODE },
3297     { "nopQ",           { Ev }, 0 },
3298     { "nopQ",           { Ev }, 0 },
3299     { "nopQ",           { Ev }, 0 },
3300     { "nopQ",           { Ev }, 0 },
3301     { "nopQ",           { Ev }, 0 },
3302     { RM_TABLE (RM_0F1E_P_1_MOD_3_REG_7) },
3303   },
3304   /* REG_0F71 */
3305   {
3306     { Bad_Opcode },
3307     { Bad_Opcode },
3308     { MOD_TABLE (MOD_0F71_REG_2) },
3309     { Bad_Opcode },
3310     { MOD_TABLE (MOD_0F71_REG_4) },
3311     { Bad_Opcode },
3312     { MOD_TABLE (MOD_0F71_REG_6) },
3313   },
3314   /* REG_0F72 */
3315   {
3316     { Bad_Opcode },
3317     { Bad_Opcode },
3318     { MOD_TABLE (MOD_0F72_REG_2) },
3319     { Bad_Opcode },
3320     { MOD_TABLE (MOD_0F72_REG_4) },
3321     { Bad_Opcode },
3322     { MOD_TABLE (MOD_0F72_REG_6) },
3323   },
3324   /* REG_0F73 */
3325   {
3326     { Bad_Opcode },
3327     { Bad_Opcode },
3328     { MOD_TABLE (MOD_0F73_REG_2) },
3329     { MOD_TABLE (MOD_0F73_REG_3) },
3330     { Bad_Opcode },
3331     { Bad_Opcode },
3332     { MOD_TABLE (MOD_0F73_REG_6) },
3333     { MOD_TABLE (MOD_0F73_REG_7) },
3334   },
3335   /* REG_0FA6 */
3336   {
3337     { "montmul",        { { OP_0f07, 0 } }, 0 },
3338     { "xsha1",          { { OP_0f07, 0 } }, 0 },
3339     { "xsha256",        { { OP_0f07, 0 } }, 0 },
3340   },
3341   /* REG_0FA7 */
3342   {
3343     { "xstore-rng",     { { OP_0f07, 0 } }, 0 },
3344     { "xcrypt-ecb",     { { OP_0f07, 0 } }, 0 },
3345     { "xcrypt-cbc",     { { OP_0f07, 0 } }, 0 },
3346     { "xcrypt-ctr",     { { OP_0f07, 0 } }, 0 },
3347     { "xcrypt-cfb",     { { OP_0f07, 0 } }, 0 },
3348     { "xcrypt-ofb",     { { OP_0f07, 0 } }, 0 },
3349   },
3350   /* REG_0FAE */
3351   {
3352     { MOD_TABLE (MOD_0FAE_REG_0) },
3353     { MOD_TABLE (MOD_0FAE_REG_1) },
3354     { MOD_TABLE (MOD_0FAE_REG_2) },
3355     { MOD_TABLE (MOD_0FAE_REG_3) },
3356     { MOD_TABLE (MOD_0FAE_REG_4) },
3357     { MOD_TABLE (MOD_0FAE_REG_5) },
3358     { MOD_TABLE (MOD_0FAE_REG_6) },
3359     { MOD_TABLE (MOD_0FAE_REG_7) },
3360   },
3361   /* REG_0FBA */
3362   {
3363     { Bad_Opcode },
3364     { Bad_Opcode },
3365     { Bad_Opcode },
3366     { Bad_Opcode },
3367     { "btQ",    { Ev, Ib }, 0 },
3368     { "btsQ",   { Evh1, Ib }, 0 },
3369     { "btrQ",   { Evh1, Ib }, 0 },
3370     { "btcQ",   { Evh1, Ib }, 0 },
3371   },
3372   /* REG_0FC7 */
3373   {
3374     { Bad_Opcode },
3375     { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 },
3376     { Bad_Opcode },
3377     { MOD_TABLE (MOD_0FC7_REG_3) },
3378     { MOD_TABLE (MOD_0FC7_REG_4) },
3379     { MOD_TABLE (MOD_0FC7_REG_5) },
3380     { MOD_TABLE (MOD_0FC7_REG_6) },
3381     { MOD_TABLE (MOD_0FC7_REG_7) },
3382   },
3383   /* REG_VEX_0F71 */
3384   {
3385     { Bad_Opcode },
3386     { Bad_Opcode },
3387     { MOD_TABLE (MOD_VEX_0F71_REG_2) },
3388     { Bad_Opcode },
3389     { MOD_TABLE (MOD_VEX_0F71_REG_4) },
3390     { Bad_Opcode },
3391     { MOD_TABLE (MOD_VEX_0F71_REG_6) },
3392   },
3393   /* REG_VEX_0F72 */
3394   {
3395     { Bad_Opcode },
3396     { Bad_Opcode },
3397     { MOD_TABLE (MOD_VEX_0F72_REG_2) },
3398     { Bad_Opcode },
3399     { MOD_TABLE (MOD_VEX_0F72_REG_4) },
3400     { Bad_Opcode },
3401     { MOD_TABLE (MOD_VEX_0F72_REG_6) },
3402   },
3403   /* REG_VEX_0F73 */
3404   {
3405     { Bad_Opcode },
3406     { Bad_Opcode },
3407     { MOD_TABLE (MOD_VEX_0F73_REG_2) },
3408     { MOD_TABLE (MOD_VEX_0F73_REG_3) },
3409     { Bad_Opcode },
3410     { Bad_Opcode },
3411     { MOD_TABLE (MOD_VEX_0F73_REG_6) },
3412     { MOD_TABLE (MOD_VEX_0F73_REG_7) },
3413   },
3414   /* REG_VEX_0FAE */
3415   {
3416     { Bad_Opcode },
3417     { Bad_Opcode },
3418     { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
3419     { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
3420   },
3421   /* REG_VEX_0F38F3 */
3422   {
3423     { Bad_Opcode },
3424     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) },
3425     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) },
3426     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) },
3427   },
3428   /* REG_XOP_LWPCB */
3429   {
3430     { "llwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3431     { "slwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3432   },
3433   /* REG_XOP_LWP */
3434   {
3435     { "lwpins", { { OP_LWP_E, 0 }, Ed, Id }, 0 },
3436     { "lwpval", { { OP_LWP_E, 0 }, Ed, Id }, 0 },
3437   },
3438   /* REG_XOP_TBM_01 */
3439   {
3440     { Bad_Opcode },
3441     { "blcfill",        { { OP_LWP_E, 0 }, Edq }, 0 },
3442     { "blsfill",        { { OP_LWP_E, 0 }, Edq }, 0 },
3443     { "blcs",   { { OP_LWP_E, 0 }, Edq }, 0 },
3444     { "tzmsk",  { { OP_LWP_E, 0 }, Edq }, 0 },
3445     { "blcic",  { { OP_LWP_E, 0 }, Edq }, 0 },
3446     { "blsic",  { { OP_LWP_E, 0 }, Edq }, 0 },
3447     { "t1mskc", { { OP_LWP_E, 0 }, Edq }, 0 },
3448   },
3449   /* REG_XOP_TBM_02 */
3450   {
3451     { Bad_Opcode },
3452     { "blcmsk", { { OP_LWP_E, 0 }, Edq }, 0 },
3453     { Bad_Opcode },
3454     { Bad_Opcode },
3455     { Bad_Opcode },
3456     { Bad_Opcode },
3457     { "blci",   { { OP_LWP_E, 0 }, Edq }, 0 },
3458   },
3459
3460 #include "i386-dis-evex-reg.h"
3461 };
3462
3463 static const struct dis386 prefix_table[][4] = {
3464   /* PREFIX_90 */
3465   {
3466     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3467     { "pause", { XX }, 0 },
3468     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3469     { NULL, { { NULL, 0 } }, PREFIX_IGNORED }
3470   },
3471
3472   /* PREFIX_0F01_REG_3_RM_1 */
3473   {
3474     { "vmmcall",        { Skip_MODRM }, 0 },
3475     { "vmgexit",        { Skip_MODRM }, 0 },
3476     { Bad_Opcode },
3477     { "vmgexit",        { Skip_MODRM }, 0 },
3478   },
3479
3480   /* PREFIX_0F01_REG_5_MOD_0 */
3481   {
3482     { Bad_Opcode },
3483     { "rstorssp",       { Mq }, PREFIX_OPCODE },
3484   },
3485
3486   /* PREFIX_0F01_REG_5_MOD_3_RM_0 */
3487   {
3488     { "serialize",      { Skip_MODRM }, PREFIX_OPCODE },
3489     { "setssbsy",       { Skip_MODRM }, PREFIX_OPCODE },
3490     { Bad_Opcode },
3491     { "xsusldtrk",      { Skip_MODRM }, PREFIX_OPCODE },
3492   },
3493
3494   /* PREFIX_0F01_REG_5_MOD_3_RM_1 */
3495   {
3496     { Bad_Opcode },
3497     { Bad_Opcode },
3498     { Bad_Opcode },
3499     { "xresldtrk",     { Skip_MODRM }, PREFIX_OPCODE },
3500   },
3501
3502   /* PREFIX_0F01_REG_5_MOD_3_RM_2 */
3503   {
3504     { Bad_Opcode },
3505     { "saveprevssp",    { Skip_MODRM }, PREFIX_OPCODE },
3506   },
3507
3508   /* PREFIX_0F01_REG_7_MOD_3_RM_2 */
3509   {
3510     { "monitorx",       { { OP_Monitor, 0 } }, 0  },
3511     { "mcommit",        { Skip_MODRM }, 0 },
3512   },
3513
3514   /* PREFIX_0F01_REG_7_MOD_3_RM_3 */
3515   {
3516     { "mwaitx",         { { OP_Mwait, eBX_reg } }, 0  },
3517   },
3518
3519   /* PREFIX_0F09 */
3520   {
3521     { "wbinvd",   { XX }, 0 },
3522     { "wbnoinvd", { XX }, 0 },
3523   },
3524
3525   /* PREFIX_0F10 */
3526   {
3527     { "movups", { XM, EXx }, PREFIX_OPCODE },
3528     { "movss",  { XM, EXd }, PREFIX_OPCODE },
3529     { "movupd", { XM, EXx }, PREFIX_OPCODE },
3530     { "movsd",  { XM, EXq }, PREFIX_OPCODE },
3531   },
3532
3533   /* PREFIX_0F11 */
3534   {
3535     { "movups", { EXxS, XM }, PREFIX_OPCODE },
3536     { "movss",  { EXdS, XM }, PREFIX_OPCODE },
3537     { "movupd", { EXxS, XM }, PREFIX_OPCODE },
3538     { "movsd",  { EXqS, XM }, PREFIX_OPCODE },
3539   },
3540
3541   /* PREFIX_0F12 */
3542   {
3543     { MOD_TABLE (MOD_0F12_PREFIX_0) },
3544     { "movsldup", { XM, EXx }, PREFIX_OPCODE },
3545     { MOD_TABLE (MOD_0F12_PREFIX_2) },
3546     { "movddup", { XM, EXq }, PREFIX_OPCODE },
3547   },
3548
3549   /* PREFIX_0F16 */
3550   {
3551     { MOD_TABLE (MOD_0F16_PREFIX_0) },
3552     { "movshdup", { XM, EXx }, PREFIX_OPCODE },
3553     { MOD_TABLE (MOD_0F16_PREFIX_2) },
3554   },
3555
3556   /* PREFIX_0F1A */
3557   {
3558     { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3559     { "bndcl",  { Gbnd, Ev_bnd }, 0 },
3560     { "bndmov", { Gbnd, Ebnd }, 0 },
3561     { "bndcu",  { Gbnd, Ev_bnd }, 0 },
3562   },
3563
3564   /* PREFIX_0F1B */
3565   {
3566     { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3567     { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3568     { "bndmov", { EbndS, Gbnd }, 0 },
3569     { "bndcn",  { Gbnd, Ev_bnd }, 0 },
3570   },
3571
3572   /* PREFIX_0F1C */
3573   {
3574     { MOD_TABLE (MOD_0F1C_PREFIX_0) },
3575     { "nopQ",   { Ev }, PREFIX_OPCODE },
3576     { "nopQ",   { Ev }, PREFIX_OPCODE },
3577     { "nopQ",   { Ev }, PREFIX_OPCODE },
3578   },
3579
3580   /* PREFIX_0F1E */
3581   {
3582     { "nopQ",   { Ev }, PREFIX_OPCODE },
3583     { MOD_TABLE (MOD_0F1E_PREFIX_1) },
3584     { "nopQ",   { Ev }, PREFIX_OPCODE },
3585     { "nopQ",   { Ev }, PREFIX_OPCODE },
3586   },
3587
3588   /* PREFIX_0F2A */
3589   {
3590     { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE },
3591     { "cvtsi2ss%LQ", { XM, Edq }, PREFIX_OPCODE },
3592     { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE },
3593     { "cvtsi2sd%LQ", { XM, Edq }, 0 },
3594   },
3595
3596   /* PREFIX_0F2B */
3597   {
3598     { MOD_TABLE (MOD_0F2B_PREFIX_0) },
3599     { MOD_TABLE (MOD_0F2B_PREFIX_1) },
3600     { MOD_TABLE (MOD_0F2B_PREFIX_2) },
3601     { MOD_TABLE (MOD_0F2B_PREFIX_3) },
3602   },
3603
3604   /* PREFIX_0F2C */
3605   {
3606     { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE },
3607     { "cvttss2si", { Gdq, EXd }, PREFIX_OPCODE },
3608     { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3609     { "cvttsd2si", { Gdq, EXq }, PREFIX_OPCODE },
3610   },
3611
3612   /* PREFIX_0F2D */
3613   {
3614     { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE },
3615     { "cvtss2si", { Gdq, EXd }, PREFIX_OPCODE },
3616     { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3617     { "cvtsd2si", { Gdq, EXq }, PREFIX_OPCODE },
3618   },
3619
3620   /* PREFIX_0F2E */
3621   {
3622     { "ucomiss",{ XM, EXd }, 0 },
3623     { Bad_Opcode },
3624     { "ucomisd",{ XM, EXq }, 0 },
3625   },
3626
3627   /* PREFIX_0F2F */
3628   {
3629     { "comiss", { XM, EXd }, 0 },
3630     { Bad_Opcode },
3631     { "comisd", { XM, EXq }, 0 },
3632   },
3633
3634   /* PREFIX_0F51 */
3635   {
3636     { "sqrtps", { XM, EXx }, PREFIX_OPCODE },
3637     { "sqrtss", { XM, EXd }, PREFIX_OPCODE },
3638     { "sqrtpd", { XM, EXx }, PREFIX_OPCODE },
3639     { "sqrtsd", { XM, EXq }, PREFIX_OPCODE },
3640   },
3641
3642   /* PREFIX_0F52 */
3643   {
3644     { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE },
3645     { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE },
3646   },
3647
3648   /* PREFIX_0F53 */
3649   {
3650     { "rcpps",  { XM, EXx }, PREFIX_OPCODE },
3651     { "rcpss",  { XM, EXd }, PREFIX_OPCODE },
3652   },
3653
3654   /* PREFIX_0F58 */
3655   {
3656     { "addps", { XM, EXx }, PREFIX_OPCODE },
3657     { "addss", { XM, EXd }, PREFIX_OPCODE },
3658     { "addpd", { XM, EXx }, PREFIX_OPCODE },
3659     { "addsd", { XM, EXq }, PREFIX_OPCODE },
3660   },
3661
3662   /* PREFIX_0F59 */
3663   {
3664     { "mulps",  { XM, EXx }, PREFIX_OPCODE },
3665     { "mulss",  { XM, EXd }, PREFIX_OPCODE },
3666     { "mulpd",  { XM, EXx }, PREFIX_OPCODE },
3667     { "mulsd",  { XM, EXq }, PREFIX_OPCODE },
3668   },
3669
3670   /* PREFIX_0F5A */
3671   {
3672     { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE },
3673     { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE },
3674     { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE },
3675     { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE },
3676   },
3677
3678   /* PREFIX_0F5B */
3679   {
3680     { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE },
3681     { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE },
3682     { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE },
3683   },
3684
3685   /* PREFIX_0F5C */
3686   {
3687     { "subps",  { XM, EXx }, PREFIX_OPCODE },
3688     { "subss",  { XM, EXd }, PREFIX_OPCODE },
3689     { "subpd",  { XM, EXx }, PREFIX_OPCODE },
3690     { "subsd",  { XM, EXq }, PREFIX_OPCODE },
3691   },
3692
3693   /* PREFIX_0F5D */
3694   {
3695     { "minps",  { XM, EXx }, PREFIX_OPCODE },
3696     { "minss",  { XM, EXd }, PREFIX_OPCODE },
3697     { "minpd",  { XM, EXx }, PREFIX_OPCODE },
3698     { "minsd",  { XM, EXq }, PREFIX_OPCODE },
3699   },
3700
3701   /* PREFIX_0F5E */
3702   {
3703     { "divps",  { XM, EXx }, PREFIX_OPCODE },
3704     { "divss",  { XM, EXd }, PREFIX_OPCODE },
3705     { "divpd",  { XM, EXx }, PREFIX_OPCODE },
3706     { "divsd",  { XM, EXq }, PREFIX_OPCODE },
3707   },
3708
3709   /* PREFIX_0F5F */
3710   {
3711     { "maxps",  { XM, EXx }, PREFIX_OPCODE },
3712     { "maxss",  { XM, EXd }, PREFIX_OPCODE },
3713     { "maxpd",  { XM, EXx }, PREFIX_OPCODE },
3714     { "maxsd",  { XM, EXq }, PREFIX_OPCODE },
3715   },
3716
3717   /* PREFIX_0F60 */
3718   {
3719     { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE },
3720     { Bad_Opcode },
3721     { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE },
3722   },
3723
3724   /* PREFIX_0F61 */
3725   {
3726     { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE },
3727     { Bad_Opcode },
3728     { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE },
3729   },
3730
3731   /* PREFIX_0F62 */
3732   {
3733     { "punpckldq",{ MX, EMd }, PREFIX_OPCODE },
3734     { Bad_Opcode },
3735     { "punpckldq",{ MX, EMx }, PREFIX_OPCODE },
3736   },
3737
3738   /* PREFIX_0F6C */
3739   {
3740     { Bad_Opcode },
3741     { Bad_Opcode },
3742     { "punpcklqdq", { XM, EXx }, PREFIX_OPCODE },
3743   },
3744
3745   /* PREFIX_0F6D */
3746   {
3747     { Bad_Opcode },
3748     { Bad_Opcode },
3749     { "punpckhqdq", { XM, EXx }, PREFIX_OPCODE },
3750   },
3751
3752   /* PREFIX_0F6F */
3753   {
3754     { "movq",   { MX, EM }, PREFIX_OPCODE },
3755     { "movdqu", { XM, EXx }, PREFIX_OPCODE },
3756     { "movdqa", { XM, EXx }, PREFIX_OPCODE },
3757   },
3758
3759   /* PREFIX_0F70 */
3760   {
3761     { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE },
3762     { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3763     { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE },
3764     { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3765   },
3766
3767   /* PREFIX_0F73_REG_3 */
3768   {
3769     { Bad_Opcode },
3770     { Bad_Opcode },
3771     { "psrldq", { XS, Ib }, 0 },
3772   },
3773
3774   /* PREFIX_0F73_REG_7 */
3775   {
3776     { Bad_Opcode },
3777     { Bad_Opcode },
3778     { "pslldq", { XS, Ib }, 0 },
3779   },
3780
3781   /* PREFIX_0F78 */
3782   {
3783     {"vmread",  { Em, Gm }, 0 },
3784     { Bad_Opcode },
3785     {"extrq",   { XS, Ib, Ib }, 0 },
3786     {"insertq", { XM, XS, Ib, Ib }, 0 },
3787   },
3788
3789   /* PREFIX_0F79 */
3790   {
3791     {"vmwrite", { Gm, Em }, 0 },
3792     { Bad_Opcode },
3793     {"extrq",   { XM, XS }, 0 },
3794     {"insertq", { XM, XS }, 0 },
3795   },
3796
3797   /* PREFIX_0F7C */
3798   {
3799     { Bad_Opcode },
3800     { Bad_Opcode },
3801     { "haddpd", { XM, EXx }, PREFIX_OPCODE },
3802     { "haddps", { XM, EXx }, PREFIX_OPCODE },
3803   },
3804
3805   /* PREFIX_0F7D */
3806   {
3807     { Bad_Opcode },
3808     { Bad_Opcode },
3809     { "hsubpd", { XM, EXx }, PREFIX_OPCODE },
3810     { "hsubps", { XM, EXx }, PREFIX_OPCODE },
3811   },
3812
3813   /* PREFIX_0F7E */
3814   {
3815     { "movK",   { Edq, MX }, PREFIX_OPCODE },
3816     { "movq",   { XM, EXq }, PREFIX_OPCODE },
3817     { "movK",   { Edq, XM }, PREFIX_OPCODE },
3818   },
3819
3820   /* PREFIX_0F7F */
3821   {
3822     { "movq",   { EMS, MX }, PREFIX_OPCODE },
3823     { "movdqu", { EXxS, XM }, PREFIX_OPCODE },
3824     { "movdqa", { EXxS, XM }, PREFIX_OPCODE },
3825   },
3826
3827   /* PREFIX_0FAE_REG_0_MOD_3 */
3828   {
3829     { Bad_Opcode },
3830     { "rdfsbase", { Ev }, 0 },
3831   },
3832
3833   /* PREFIX_0FAE_REG_1_MOD_3 */
3834   {
3835     { Bad_Opcode },
3836     { "rdgsbase", { Ev }, 0 },
3837   },
3838
3839   /* PREFIX_0FAE_REG_2_MOD_3 */
3840   {
3841     { Bad_Opcode },
3842     { "wrfsbase", { Ev }, 0 },
3843   },
3844
3845   /* PREFIX_0FAE_REG_3_MOD_3 */
3846   {
3847     { Bad_Opcode },
3848     { "wrgsbase", { Ev }, 0 },
3849   },
3850
3851   /* PREFIX_0FAE_REG_4_MOD_0 */
3852   {
3853     { "xsave",  { FXSAVE }, 0 },
3854     { "ptwrite%LQ", { Edq }, 0 },
3855   },
3856
3857   /* PREFIX_0FAE_REG_4_MOD_3 */
3858   {
3859     { Bad_Opcode },
3860     { "ptwrite%LQ", { Edq }, 0 },
3861   },
3862
3863   /* PREFIX_0FAE_REG_5_MOD_0 */
3864   {
3865     { "xrstor",         { FXSAVE }, PREFIX_OPCODE },
3866   },
3867
3868   /* PREFIX_0FAE_REG_5_MOD_3 */
3869   {
3870     { "lfence",         { Skip_MODRM }, 0 },
3871     { "incsspK",        { Rdq }, PREFIX_OPCODE },
3872   },
3873
3874   /* PREFIX_0FAE_REG_6_MOD_0 */
3875   {
3876     { "xsaveopt",       { FXSAVE }, PREFIX_OPCODE },
3877     { "clrssbsy",       { Mq }, PREFIX_OPCODE },
3878     { "clwb",   { Mb }, PREFIX_OPCODE },
3879   },
3880
3881   /* PREFIX_0FAE_REG_6_MOD_3 */
3882   {
3883     { RM_TABLE (RM_0FAE_REG_6_MOD_3_P_0) },
3884     { "umonitor",       { Eva }, PREFIX_OPCODE },
3885     { "tpause", { Edq }, PREFIX_OPCODE },
3886     { "umwait", { Edq }, PREFIX_OPCODE },
3887   },
3888
3889   /* PREFIX_0FAE_REG_7_MOD_0 */
3890   {
3891     { "clflush",        { Mb }, 0 },
3892     { Bad_Opcode },
3893     { "clflushopt",     { Mb }, 0 },
3894   },
3895
3896   /* PREFIX_0FB8 */
3897   {
3898     { Bad_Opcode },
3899     { "popcntS", { Gv, Ev }, 0 },
3900   },
3901
3902   /* PREFIX_0FBC */
3903   {
3904     { "bsfS",   { Gv, Ev }, 0 },
3905     { "tzcntS", { Gv, Ev }, 0 },
3906     { "bsfS",   { Gv, Ev }, 0 },
3907   },
3908
3909   /* PREFIX_0FBD */
3910   {
3911     { "bsrS",   { Gv, Ev }, 0 },
3912     { "lzcntS", { Gv, Ev }, 0 },
3913     { "bsrS",   { Gv, Ev }, 0 },
3914   },
3915
3916   /* PREFIX_0FC2 */
3917   {
3918     { "cmpps",  { XM, EXx, CMP }, PREFIX_OPCODE },
3919     { "cmpss",  { XM, EXd, CMP }, PREFIX_OPCODE },
3920     { "cmppd",  { XM, EXx, CMP }, PREFIX_OPCODE },
3921     { "cmpsd",  { XM, EXq, CMP }, PREFIX_OPCODE },
3922   },
3923
3924   /* PREFIX_0FC3_MOD_0 */
3925   {
3926     { "movntiS", { Edq, Gdq }, PREFIX_OPCODE },
3927   },
3928
3929   /* PREFIX_0FC7_REG_6_MOD_0 */
3930   {
3931     { "vmptrld",{ Mq }, 0 },
3932     { "vmxon",  { Mq }, 0 },
3933     { "vmclear",{ Mq }, 0 },
3934   },
3935
3936   /* PREFIX_0FC7_REG_6_MOD_3 */
3937   {
3938     { "rdrand", { Ev }, 0 },
3939     { Bad_Opcode },
3940     { "rdrand", { Ev }, 0 }
3941   },
3942
3943   /* PREFIX_0FC7_REG_7_MOD_3 */
3944   {
3945     { "rdseed", { Ev }, 0 },
3946     { "rdpid",  { Em }, 0 },
3947     { "rdseed", { Ev }, 0 },
3948   },
3949
3950   /* PREFIX_0FD0 */
3951   {
3952     { Bad_Opcode },
3953     { Bad_Opcode },
3954     { "addsubpd", { XM, EXx }, 0 },
3955     { "addsubps", { XM, EXx }, 0 },
3956   },
3957
3958   /* PREFIX_0FD6 */
3959   {
3960     { Bad_Opcode },
3961     { "movq2dq",{ XM, MS }, 0 },
3962     { "movq",   { EXqS, XM }, 0 },
3963     { "movdq2q",{ MX, XS }, 0 },
3964   },
3965
3966   /* PREFIX_0FE6 */
3967   {
3968     { Bad_Opcode },
3969     { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE },
3970     { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE },
3971     { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE },
3972   },
3973
3974   /* PREFIX_0FE7 */
3975   {
3976     { "movntq", { Mq, MX }, PREFIX_OPCODE },
3977     { Bad_Opcode },
3978     { MOD_TABLE (MOD_0FE7_PREFIX_2) },
3979   },
3980
3981   /* PREFIX_0FF0 */
3982   {
3983     { Bad_Opcode },
3984     { Bad_Opcode },
3985     { Bad_Opcode },
3986     { MOD_TABLE (MOD_0FF0_PREFIX_3) },
3987   },
3988
3989   /* PREFIX_0FF7 */
3990   {
3991     { "maskmovq", { MX, MS }, PREFIX_OPCODE },
3992     { Bad_Opcode },
3993     { "maskmovdqu", { XM, XS }, PREFIX_OPCODE },
3994   },
3995
3996   /* PREFIX_0F3810 */
3997   {
3998     { Bad_Opcode },
3999     { Bad_Opcode },
4000     { "pblendvb", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4001   },
4002
4003   /* PREFIX_0F3814 */
4004   {
4005     { Bad_Opcode },
4006     { Bad_Opcode },
4007     { "blendvps", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4008   },
4009
4010   /* PREFIX_0F3815 */
4011   {
4012     { Bad_Opcode },
4013     { Bad_Opcode },
4014     { "blendvpd", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4015   },
4016
4017   /* PREFIX_0F3817 */
4018   {
4019     { Bad_Opcode },
4020     { Bad_Opcode },
4021     { "ptest",  { XM, EXx }, PREFIX_OPCODE },
4022   },
4023
4024   /* PREFIX_0F3820 */
4025   {
4026     { Bad_Opcode },
4027     { Bad_Opcode },
4028     { "pmovsxbw", { XM, EXq }, PREFIX_OPCODE },
4029   },
4030
4031   /* PREFIX_0F3821 */
4032   {
4033     { Bad_Opcode },
4034     { Bad_Opcode },
4035     { "pmovsxbd", { XM, EXd }, PREFIX_OPCODE },
4036   },
4037
4038   /* PREFIX_0F3822 */
4039   {
4040     { Bad_Opcode },
4041     { Bad_Opcode },
4042     { "pmovsxbq", { XM, EXw }, PREFIX_OPCODE },
4043   },
4044
4045   /* PREFIX_0F3823 */
4046   {
4047     { Bad_Opcode },
4048     { Bad_Opcode },
4049     { "pmovsxwd", { XM, EXq }, PREFIX_OPCODE },
4050   },
4051
4052   /* PREFIX_0F3824 */
4053   {
4054     { Bad_Opcode },
4055     { Bad_Opcode },
4056     { "pmovsxwq", { XM, EXd }, PREFIX_OPCODE },
4057   },
4058
4059   /* PREFIX_0F3825 */
4060   {
4061     { Bad_Opcode },
4062     { Bad_Opcode },
4063     { "pmovsxdq", { XM, EXq }, PREFIX_OPCODE },
4064   },
4065
4066   /* PREFIX_0F3828 */
4067   {
4068     { Bad_Opcode },
4069     { Bad_Opcode },
4070     { "pmuldq", { XM, EXx }, PREFIX_OPCODE },
4071   },
4072
4073   /* PREFIX_0F3829 */
4074   {
4075     { Bad_Opcode },
4076     { Bad_Opcode },
4077     { "pcmpeqq", { XM, EXx }, PREFIX_OPCODE },
4078   },
4079
4080   /* PREFIX_0F382A */
4081   {
4082     { Bad_Opcode },
4083     { Bad_Opcode },
4084     { MOD_TABLE (MOD_0F382A_PREFIX_2) },
4085   },
4086
4087   /* PREFIX_0F382B */
4088   {
4089     { Bad_Opcode },
4090     { Bad_Opcode },
4091     { "packusdw", { XM, EXx }, PREFIX_OPCODE },
4092   },
4093
4094   /* PREFIX_0F3830 */
4095   {
4096     { Bad_Opcode },
4097     { Bad_Opcode },
4098     { "pmovzxbw", { XM, EXq }, PREFIX_OPCODE },
4099   },
4100
4101   /* PREFIX_0F3831 */
4102   {
4103     { Bad_Opcode },
4104     { Bad_Opcode },
4105     { "pmovzxbd", { XM, EXd }, PREFIX_OPCODE },
4106   },
4107
4108   /* PREFIX_0F3832 */
4109   {
4110     { Bad_Opcode },
4111     { Bad_Opcode },
4112     { "pmovzxbq", { XM, EXw }, PREFIX_OPCODE },
4113   },
4114
4115   /* PREFIX_0F3833 */
4116   {
4117     { Bad_Opcode },
4118     { Bad_Opcode },
4119     { "pmovzxwd", { XM, EXq }, PREFIX_OPCODE },
4120   },
4121
4122   /* PREFIX_0F3834 */
4123   {
4124     { Bad_Opcode },
4125     { Bad_Opcode },
4126     { "pmovzxwq", { XM, EXd }, PREFIX_OPCODE },
4127   },
4128
4129   /* PREFIX_0F3835 */
4130   {
4131     { Bad_Opcode },
4132     { Bad_Opcode },
4133     { "pmovzxdq", { XM, EXq }, PREFIX_OPCODE },
4134   },
4135
4136   /* PREFIX_0F3837 */
4137   {
4138     { Bad_Opcode },
4139     { Bad_Opcode },
4140     { "pcmpgtq", { XM, EXx }, PREFIX_OPCODE },
4141   },
4142
4143   /* PREFIX_0F3838 */
4144   {
4145     { Bad_Opcode },
4146     { Bad_Opcode },
4147     { "pminsb", { XM, EXx }, PREFIX_OPCODE },
4148   },
4149
4150   /* PREFIX_0F3839 */
4151   {
4152     { Bad_Opcode },
4153     { Bad_Opcode },
4154     { "pminsd", { XM, EXx }, PREFIX_OPCODE },
4155   },
4156
4157   /* PREFIX_0F383A */
4158   {
4159     { Bad_Opcode },
4160     { Bad_Opcode },
4161     { "pminuw", { XM, EXx }, PREFIX_OPCODE },
4162   },
4163
4164   /* PREFIX_0F383B */
4165   {
4166     { Bad_Opcode },
4167     { Bad_Opcode },
4168     { "pminud", { XM, EXx }, PREFIX_OPCODE },
4169   },
4170
4171   /* PREFIX_0F383C */
4172   {
4173     { Bad_Opcode },
4174     { Bad_Opcode },
4175     { "pmaxsb", { XM, EXx }, PREFIX_OPCODE },
4176   },
4177
4178   /* PREFIX_0F383D */
4179   {
4180     { Bad_Opcode },
4181     { Bad_Opcode },
4182     { "pmaxsd", { XM, EXx }, PREFIX_OPCODE },
4183   },
4184
4185   /* PREFIX_0F383E */
4186   {
4187     { Bad_Opcode },
4188     { Bad_Opcode },
4189     { "pmaxuw", { XM, EXx }, PREFIX_OPCODE },
4190   },
4191
4192   /* PREFIX_0F383F */
4193   {
4194     { Bad_Opcode },
4195     { Bad_Opcode },
4196     { "pmaxud", { XM, EXx }, PREFIX_OPCODE },
4197   },
4198
4199   /* PREFIX_0F3840 */
4200   {
4201     { Bad_Opcode },
4202     { Bad_Opcode },
4203     { "pmulld", { XM, EXx }, PREFIX_OPCODE },
4204   },
4205
4206   /* PREFIX_0F3841 */
4207   {
4208     { Bad_Opcode },
4209     { Bad_Opcode },
4210     { "phminposuw", { XM, EXx }, PREFIX_OPCODE },
4211   },
4212
4213   /* PREFIX_0F3880 */
4214   {
4215     { Bad_Opcode },
4216     { Bad_Opcode },
4217     { "invept", { Gm, Mo }, PREFIX_OPCODE },
4218   },
4219
4220   /* PREFIX_0F3881 */
4221   {
4222     { Bad_Opcode },
4223     { Bad_Opcode },
4224     { "invvpid", { Gm, Mo }, PREFIX_OPCODE },
4225   },
4226
4227   /* PREFIX_0F3882 */
4228   {
4229     { Bad_Opcode },
4230     { Bad_Opcode },
4231     { "invpcid", { Gm, M }, PREFIX_OPCODE },
4232   },
4233
4234   /* PREFIX_0F38C8 */
4235   {
4236     { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE },
4237   },
4238
4239   /* PREFIX_0F38C9 */
4240   {
4241     { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE },
4242   },
4243
4244   /* PREFIX_0F38CA */
4245   {
4246     { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE },
4247   },
4248
4249   /* PREFIX_0F38CB */
4250   {
4251     { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE },
4252   },
4253
4254   /* PREFIX_0F38CC */
4255   {
4256     { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE },
4257   },
4258
4259   /* PREFIX_0F38CD */
4260   {
4261     { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE },
4262   },
4263
4264   /* PREFIX_0F38CF */
4265   {
4266     { Bad_Opcode },
4267     { Bad_Opcode },
4268     { "gf2p8mulb", { XM, EXxmm }, PREFIX_OPCODE },
4269   },
4270
4271   /* PREFIX_0F38DB */
4272   {
4273     { Bad_Opcode },
4274     { Bad_Opcode },
4275     { "aesimc", { XM, EXx }, PREFIX_OPCODE },
4276   },
4277
4278   /* PREFIX_0F38DC */
4279   {
4280     { Bad_Opcode },
4281     { Bad_Opcode },
4282     { "aesenc", { XM, EXx }, PREFIX_OPCODE },
4283   },
4284
4285   /* PREFIX_0F38DD */
4286   {
4287     { Bad_Opcode },
4288     { Bad_Opcode },
4289     { "aesenclast", { XM, EXx }, PREFIX_OPCODE },
4290   },
4291
4292   /* PREFIX_0F38DE */
4293   {
4294     { Bad_Opcode },
4295     { Bad_Opcode },
4296     { "aesdec", { XM, EXx }, PREFIX_OPCODE },
4297   },
4298
4299   /* PREFIX_0F38DF */
4300   {
4301     { Bad_Opcode },
4302     { Bad_Opcode },
4303     { "aesdeclast", { XM, EXx }, PREFIX_OPCODE },
4304   },
4305
4306   /* PREFIX_0F38F0 */
4307   {
4308     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4309     { Bad_Opcode },
4310     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4311     { "crc32",  { Gdq, { CRC32_Fixup, b_mode } }, PREFIX_OPCODE },
4312   },
4313
4314   /* PREFIX_0F38F1 */
4315   {
4316     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4317     { Bad_Opcode },
4318     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4319     { "crc32",  { Gdq, { CRC32_Fixup, v_mode } }, PREFIX_OPCODE },
4320   },
4321
4322   /* PREFIX_0F38F5 */
4323   {
4324     { Bad_Opcode },
4325     { Bad_Opcode },
4326     { MOD_TABLE (MOD_0F38F5_PREFIX_2) },
4327   },
4328
4329   /* PREFIX_0F38F6 */
4330   {
4331     { MOD_TABLE (MOD_0F38F6_PREFIX_0) },
4332     { "adoxS",  { Gdq, Edq}, PREFIX_OPCODE },
4333     { "adcxS",  { Gdq, Edq}, PREFIX_OPCODE },
4334     { Bad_Opcode },
4335   },
4336
4337   /* PREFIX_0F38F8 */
4338   {
4339     { Bad_Opcode },
4340     { MOD_TABLE (MOD_0F38F8_PREFIX_1) },
4341     { MOD_TABLE (MOD_0F38F8_PREFIX_2) },
4342     { MOD_TABLE (MOD_0F38F8_PREFIX_3) },
4343   },
4344
4345   /* PREFIX_0F38F9 */
4346   {
4347     { MOD_TABLE (MOD_0F38F9_PREFIX_0) },
4348   },
4349
4350   /* PREFIX_0F3A08 */
4351   {
4352     { Bad_Opcode },
4353     { Bad_Opcode },
4354     { "roundps", { XM, EXx, Ib }, PREFIX_OPCODE },
4355   },
4356
4357   /* PREFIX_0F3A09 */
4358   {
4359     { Bad_Opcode },
4360     { Bad_Opcode },
4361     { "roundpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4362   },
4363
4364   /* PREFIX_0F3A0A */
4365   {
4366     { Bad_Opcode },
4367     { Bad_Opcode },
4368     { "roundss", { XM, EXd, Ib }, PREFIX_OPCODE },
4369   },
4370
4371   /* PREFIX_0F3A0B */
4372   {
4373     { Bad_Opcode },
4374     { Bad_Opcode },
4375     { "roundsd", { XM, EXq, Ib }, PREFIX_OPCODE },
4376   },
4377
4378   /* PREFIX_0F3A0C */
4379   {
4380     { Bad_Opcode },
4381     { Bad_Opcode },
4382     { "blendps", { XM, EXx, Ib }, PREFIX_OPCODE },
4383   },
4384
4385   /* PREFIX_0F3A0D */
4386   {
4387     { Bad_Opcode },
4388     { Bad_Opcode },
4389     { "blendpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4390   },
4391
4392   /* PREFIX_0F3A0E */
4393   {
4394     { Bad_Opcode },
4395     { Bad_Opcode },
4396     { "pblendw", { XM, EXx, Ib }, PREFIX_OPCODE },
4397   },
4398
4399   /* PREFIX_0F3A14 */
4400   {
4401     { Bad_Opcode },
4402     { Bad_Opcode },
4403     { "pextrb", { Edqb, XM, Ib }, PREFIX_OPCODE },
4404   },
4405
4406   /* PREFIX_0F3A15 */
4407   {
4408     { Bad_Opcode },
4409     { Bad_Opcode },
4410     { "pextrw", { Edqw, XM, Ib }, PREFIX_OPCODE },
4411   },
4412
4413   /* PREFIX_0F3A16 */
4414   {
4415     { Bad_Opcode },
4416     { Bad_Opcode },
4417     { "pextrK", { Edq, XM, Ib }, PREFIX_OPCODE },
4418   },
4419
4420   /* PREFIX_0F3A17 */
4421   {
4422     { Bad_Opcode },
4423     { Bad_Opcode },
4424     { "extractps", { Edqd, XM, Ib }, PREFIX_OPCODE },
4425   },
4426
4427   /* PREFIX_0F3A20 */
4428   {
4429     { Bad_Opcode },
4430     { Bad_Opcode },
4431     { "pinsrb", { XM, Edqb, Ib }, PREFIX_OPCODE },
4432   },
4433
4434   /* PREFIX_0F3A21 */
4435   {
4436     { Bad_Opcode },
4437     { Bad_Opcode },
4438     { "insertps", { XM, EXd, Ib }, PREFIX_OPCODE },
4439   },
4440
4441   /* PREFIX_0F3A22 */
4442   {
4443     { Bad_Opcode },
4444     { Bad_Opcode },
4445     { "pinsrK", { XM, Edq, Ib }, PREFIX_OPCODE },
4446   },
4447
4448   /* PREFIX_0F3A40 */
4449   {
4450     { Bad_Opcode },
4451     { Bad_Opcode },
4452     { "dpps",   { XM, EXx, Ib }, PREFIX_OPCODE },
4453   },
4454
4455   /* PREFIX_0F3A41 */
4456   {
4457     { Bad_Opcode },
4458     { Bad_Opcode },
4459     { "dppd",   { XM, EXx, Ib }, PREFIX_OPCODE },
4460   },
4461
4462   /* PREFIX_0F3A42 */
4463   {
4464     { Bad_Opcode },
4465     { Bad_Opcode },
4466     { "mpsadbw", { XM, EXx, Ib }, PREFIX_OPCODE },
4467   },
4468
4469   /* PREFIX_0F3A44 */
4470   {
4471     { Bad_Opcode },
4472     { Bad_Opcode },
4473     { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_OPCODE },
4474   },
4475
4476   /* PREFIX_0F3A60 */
4477   {
4478     { Bad_Opcode },
4479     { Bad_Opcode },
4480     { "pcmpestrm", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE },
4481   },
4482
4483   /* PREFIX_0F3A61 */
4484   {
4485     { Bad_Opcode },
4486     { Bad_Opcode },
4487     { "pcmpestri", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE },
4488   },
4489
4490   /* PREFIX_0F3A62 */
4491   {
4492     { Bad_Opcode },
4493     { Bad_Opcode },
4494     { "pcmpistrm", { XM, EXx, Ib }, PREFIX_OPCODE },
4495   },
4496
4497   /* PREFIX_0F3A63 */
4498   {
4499     { Bad_Opcode },
4500     { Bad_Opcode },
4501     { "pcmpistri", { XM, EXx, Ib }, PREFIX_OPCODE },
4502   },
4503
4504   /* PREFIX_0F3ACC */
4505   {
4506     { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4507   },
4508
4509   /* PREFIX_0F3ACE */
4510   {
4511     { Bad_Opcode },
4512     { Bad_Opcode },
4513     { "gf2p8affineqb", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4514   },
4515
4516   /* PREFIX_0F3ACF */
4517   {
4518     { Bad_Opcode },
4519     { Bad_Opcode },
4520     { "gf2p8affineinvqb", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4521   },
4522
4523   /* PREFIX_0F3ADF */
4524   {
4525     { Bad_Opcode },
4526     { Bad_Opcode },
4527     { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_OPCODE },
4528   },
4529
4530   /* PREFIX_VEX_0F10 */
4531   {
4532     { "vmovups",        { XM, EXx }, 0 },
4533     { "vmovss",         { XMVexScalar, VexScalar, EXxmm_md }, 0 },
4534     { "vmovupd",        { XM, EXx }, 0 },
4535     { "vmovsd",         { XMVexScalar, VexScalar, EXxmm_mq }, 0 },
4536   },
4537
4538   /* PREFIX_VEX_0F11 */
4539   {
4540     { "vmovups",        { EXxS, XM }, 0 },
4541     { "vmovss",         { EXdVexScalarS, VexScalar, XMScalar }, 0 },
4542     { "vmovupd",        { EXxS, XM }, 0 },
4543     { "vmovsd",         { EXqVexScalarS, VexScalar, XMScalar }, 0 },
4544   },
4545
4546   /* PREFIX_VEX_0F12 */
4547   {
4548     { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
4549     { "vmovsldup",      { XM, EXx }, 0 },
4550     { MOD_TABLE (MOD_VEX_0F12_PREFIX_2) },
4551     { "vmovddup",       { XM, EXymmq }, 0 },
4552   },
4553
4554   /* PREFIX_VEX_0F16 */
4555   {
4556     { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
4557     { "vmovshdup",      { XM, EXx }, 0 },
4558     { MOD_TABLE (MOD_VEX_0F16_PREFIX_2) },
4559   },
4560
4561   /* PREFIX_VEX_0F2A */
4562   {
4563     { Bad_Opcode },
4564     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Edq }, 0 },
4565     { Bad_Opcode },
4566     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Edq }, 0 },
4567   },
4568
4569   /* PREFIX_VEX_0F2C */
4570   {
4571     { Bad_Opcode },
4572     { "vcvttss2si",     { Gdq, EXxmm_md }, 0 },
4573     { Bad_Opcode },
4574     { "vcvttsd2si",     { Gdq, EXxmm_mq }, 0 },
4575   },
4576
4577   /* PREFIX_VEX_0F2D */
4578   {
4579     { Bad_Opcode },
4580     { "vcvtss2si",      { Gdq, EXxmm_md }, 0 },
4581     { Bad_Opcode },
4582     { "vcvtsd2si",      { Gdq, EXxmm_mq }, 0 },
4583   },
4584
4585   /* PREFIX_VEX_0F2E */
4586   {
4587     { "vucomiss",       { XMScalar, EXxmm_md }, 0 },
4588     { Bad_Opcode },
4589     { "vucomisd",       { XMScalar, EXxmm_mq }, 0 },
4590   },
4591
4592   /* PREFIX_VEX_0F2F */
4593   {
4594     { "vcomiss",        { XMScalar, EXxmm_md }, 0 },
4595     { Bad_Opcode },
4596     { "vcomisd",        { XMScalar, EXxmm_mq }, 0 },
4597   },
4598
4599   /* PREFIX_VEX_0F41 */
4600   {
4601     { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) },
4602     { Bad_Opcode },
4603     { VEX_LEN_TABLE (VEX_LEN_0F41_P_2) },
4604   },
4605
4606   /* PREFIX_VEX_0F42 */
4607   {
4608     { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) },
4609     { Bad_Opcode },
4610     { VEX_LEN_TABLE (VEX_LEN_0F42_P_2) },
4611   },
4612
4613   /* PREFIX_VEX_0F44 */
4614   {
4615     { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) },
4616     { Bad_Opcode },
4617     { VEX_LEN_TABLE (VEX_LEN_0F44_P_2) },
4618   },
4619
4620   /* PREFIX_VEX_0F45 */
4621   {
4622     { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) },
4623     { Bad_Opcode },
4624     { VEX_LEN_TABLE (VEX_LEN_0F45_P_2) },
4625   },
4626
4627   /* PREFIX_VEX_0F46 */
4628   {
4629     { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) },
4630     { Bad_Opcode },
4631     { VEX_LEN_TABLE (VEX_LEN_0F46_P_2) },
4632   },
4633
4634   /* PREFIX_VEX_0F47 */
4635   {
4636     { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) },
4637     { Bad_Opcode },
4638     { VEX_LEN_TABLE (VEX_LEN_0F47_P_2) },
4639   },
4640
4641   /* PREFIX_VEX_0F4A */
4642   {
4643     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0) },
4644     { Bad_Opcode },
4645     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2) },
4646   },
4647
4648   /* PREFIX_VEX_0F4B */
4649   {
4650     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0) },
4651     { Bad_Opcode },
4652     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) },
4653   },
4654
4655   /* PREFIX_VEX_0F51 */
4656   {
4657     { "vsqrtps",        { XM, EXx }, 0 },
4658     { "vsqrtss",        { XMScalar, VexScalar, EXxmm_md }, 0 },
4659     { "vsqrtpd",        { XM, EXx }, 0 },
4660     { "vsqrtsd",        { XMScalar, VexScalar, EXxmm_mq }, 0 },
4661   },
4662
4663   /* PREFIX_VEX_0F52 */
4664   {
4665     { "vrsqrtps",       { XM, EXx }, 0 },
4666     { "vrsqrtss",       { XMScalar, VexScalar, EXxmm_md }, 0 },
4667   },
4668
4669   /* PREFIX_VEX_0F53 */
4670   {
4671     { "vrcpps",         { XM, EXx }, 0 },
4672     { "vrcpss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
4673   },
4674
4675   /* PREFIX_VEX_0F58 */
4676   {
4677     { "vaddps",         { XM, Vex, EXx }, 0 },
4678     { "vaddss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
4679     { "vaddpd",         { XM, Vex, EXx }, 0 },
4680     { "vaddsd",         { XMScalar, VexScalar, EXxmm_mq }, 0 },
4681   },
4682
4683   /* PREFIX_VEX_0F59 */
4684   {
4685     { "vmulps",         { XM, Vex, EXx }, 0 },
4686     { "vmulss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
4687     { "vmulpd",         { XM, Vex, EXx }, 0 },
4688     { "vmulsd",         { XMScalar, VexScalar, EXxmm_mq }, 0 },
4689   },
4690
4691   /* PREFIX_VEX_0F5A */
4692   {
4693     { "vcvtps2pd",      { XM, EXxmmq }, 0 },
4694     { "vcvtss2sd",      { XMScalar, VexScalar, EXxmm_md }, 0 },
4695     { "vcvtpd2ps%XY",{ XMM, EXx }, 0 },
4696     { "vcvtsd2ss",      { XMScalar, VexScalar, EXxmm_mq }, 0 },
4697   },
4698
4699   /* PREFIX_VEX_0F5B */
4700   {
4701     { "vcvtdq2ps",      { XM, EXx }, 0 },
4702     { "vcvttps2dq",     { XM, EXx }, 0 },
4703     { "vcvtps2dq",      { XM, EXx }, 0 },
4704   },
4705
4706   /* PREFIX_VEX_0F5C */
4707   {
4708     { "vsubps",         { XM, Vex, EXx }, 0 },
4709     { "vsubss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
4710     { "vsubpd",         { XM, Vex, EXx }, 0 },
4711     { "vsubsd",         { XMScalar, VexScalar, EXxmm_mq }, 0 },
4712   },
4713
4714   /* PREFIX_VEX_0F5D */
4715   {
4716     { "vminps",         { XM, Vex, EXx }, 0 },
4717     { "vminss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
4718     { "vminpd",         { XM, Vex, EXx }, 0 },
4719     { "vminsd",         { XMScalar, VexScalar, EXxmm_mq }, 0 },
4720   },
4721
4722   /* PREFIX_VEX_0F5E */
4723   {
4724     { "vdivps",         { XM, Vex, EXx }, 0 },
4725     { "vdivss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
4726     { "vdivpd",         { XM, Vex, EXx }, 0 },
4727     { "vdivsd",         { XMScalar, VexScalar, EXxmm_mq }, 0 },
4728   },
4729
4730   /* PREFIX_VEX_0F5F */
4731   {
4732     { "vmaxps",         { XM, Vex, EXx }, 0 },
4733     { "vmaxss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
4734     { "vmaxpd",         { XM, Vex, EXx }, 0 },
4735     { "vmaxsd",         { XMScalar, VexScalar, EXxmm_mq }, 0 },
4736   },
4737
4738   /* PREFIX_VEX_0F60 */
4739   {
4740     { Bad_Opcode },
4741     { Bad_Opcode },
4742     { "vpunpcklbw",     { XM, Vex, EXx }, 0 },
4743   },
4744
4745   /* PREFIX_VEX_0F61 */
4746   {
4747     { Bad_Opcode },
4748     { Bad_Opcode },
4749     { "vpunpcklwd",     { XM, Vex, EXx }, 0 },
4750   },
4751
4752   /* PREFIX_VEX_0F62 */
4753   {
4754     { Bad_Opcode },
4755     { Bad_Opcode },
4756     { "vpunpckldq",     { XM, Vex, EXx }, 0 },
4757   },
4758
4759   /* PREFIX_VEX_0F63 */
4760   {
4761     { Bad_Opcode },
4762     { Bad_Opcode },
4763     { "vpacksswb",      { XM, Vex, EXx }, 0 },
4764   },
4765
4766   /* PREFIX_VEX_0F64 */
4767   {
4768     { Bad_Opcode },
4769     { Bad_Opcode },
4770     { "vpcmpgtb",       { XM, Vex, EXx }, 0 },
4771   },
4772
4773   /* PREFIX_VEX_0F65 */
4774   {
4775     { Bad_Opcode },
4776     { Bad_Opcode },
4777     { "vpcmpgtw",       { XM, Vex, EXx }, 0 },
4778   },
4779
4780   /* PREFIX_VEX_0F66 */
4781   {
4782     { Bad_Opcode },
4783     { Bad_Opcode },
4784     { "vpcmpgtd",       { XM, Vex, EXx }, 0 },
4785   },
4786
4787   /* PREFIX_VEX_0F67 */
4788   {
4789     { Bad_Opcode },
4790     { Bad_Opcode },
4791     { "vpackuswb",      { XM, Vex, EXx }, 0 },
4792   },
4793
4794   /* PREFIX_VEX_0F68 */
4795   {
4796     { Bad_Opcode },
4797     { Bad_Opcode },
4798     { "vpunpckhbw",     { XM, Vex, EXx }, 0 },
4799   },
4800
4801   /* PREFIX_VEX_0F69 */
4802   {
4803     { Bad_Opcode },
4804     { Bad_Opcode },
4805     { "vpunpckhwd",     { XM, Vex, EXx }, 0 },
4806   },
4807
4808   /* PREFIX_VEX_0F6A */
4809   {
4810     { Bad_Opcode },
4811     { Bad_Opcode },
4812     { "vpunpckhdq",     { XM, Vex, EXx }, 0 },
4813   },
4814
4815   /* PREFIX_VEX_0F6B */
4816   {
4817     { Bad_Opcode },
4818     { Bad_Opcode },
4819     { "vpackssdw",      { XM, Vex, EXx }, 0 },
4820   },
4821
4822   /* PREFIX_VEX_0F6C */
4823   {
4824     { Bad_Opcode },
4825     { Bad_Opcode },
4826     { "vpunpcklqdq",    { XM, Vex, EXx }, 0 },
4827   },
4828
4829   /* PREFIX_VEX_0F6D */
4830   {
4831     { Bad_Opcode },
4832     { Bad_Opcode },
4833     { "vpunpckhqdq",    { XM, Vex, EXx }, 0 },
4834   },
4835
4836   /* PREFIX_VEX_0F6E */
4837   {
4838     { Bad_Opcode },
4839     { Bad_Opcode },
4840     { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) },
4841   },
4842
4843   /* PREFIX_VEX_0F6F */
4844   {
4845     { Bad_Opcode },
4846     { "vmovdqu",        { XM, EXx }, 0 },
4847     { "vmovdqa",        { XM, EXx }, 0 },
4848   },
4849
4850   /* PREFIX_VEX_0F70 */
4851   {
4852     { Bad_Opcode },
4853     { "vpshufhw",       { XM, EXx, Ib }, 0 },
4854     { "vpshufd",        { XM, EXx, Ib }, 0 },
4855     { "vpshuflw",       { XM, EXx, Ib }, 0 },
4856   },
4857
4858   /* PREFIX_VEX_0F71_REG_2 */
4859   {
4860     { Bad_Opcode },
4861     { Bad_Opcode },
4862     { "vpsrlw",         { Vex, XS, Ib }, 0 },
4863   },
4864
4865   /* PREFIX_VEX_0F71_REG_4 */
4866   {
4867     { Bad_Opcode },
4868     { Bad_Opcode },
4869     { "vpsraw",         { Vex, XS, Ib }, 0 },
4870   },
4871
4872   /* PREFIX_VEX_0F71_REG_6 */
4873   {
4874     { Bad_Opcode },
4875     { Bad_Opcode },
4876     { "vpsllw",         { Vex, XS, Ib }, 0 },
4877   },
4878
4879   /* PREFIX_VEX_0F72_REG_2 */
4880   {
4881     { Bad_Opcode },
4882     { Bad_Opcode },
4883     { "vpsrld",         { Vex, XS, Ib }, 0 },
4884   },
4885
4886   /* PREFIX_VEX_0F72_REG_4 */
4887   {
4888     { Bad_Opcode },
4889     { Bad_Opcode },
4890     { "vpsrad",         { Vex, XS, Ib }, 0 },
4891   },
4892
4893   /* PREFIX_VEX_0F72_REG_6 */
4894   {
4895     { Bad_Opcode },
4896     { Bad_Opcode },
4897     { "vpslld",         { Vex, XS, Ib }, 0 },
4898   },
4899
4900   /* PREFIX_VEX_0F73_REG_2 */
4901   {
4902     { Bad_Opcode },
4903     { Bad_Opcode },
4904     { "vpsrlq",         { Vex, XS, Ib }, 0 },
4905   },
4906
4907   /* PREFIX_VEX_0F73_REG_3 */
4908   {
4909     { Bad_Opcode },
4910     { Bad_Opcode },
4911     { "vpsrldq",        { Vex, XS, Ib }, 0 },
4912   },
4913
4914   /* PREFIX_VEX_0F73_REG_6 */
4915   {
4916     { Bad_Opcode },
4917     { Bad_Opcode },
4918     { "vpsllq",         { Vex, XS, Ib }, 0 },
4919   },
4920
4921   /* PREFIX_VEX_0F73_REG_7 */
4922   {
4923     { Bad_Opcode },
4924     { Bad_Opcode },
4925     { "vpslldq",        { Vex, XS, Ib }, 0 },
4926   },
4927
4928   /* PREFIX_VEX_0F74 */
4929   {
4930     { Bad_Opcode },
4931     { Bad_Opcode },
4932     { "vpcmpeqb",       { XM, Vex, EXx }, 0 },
4933   },
4934
4935   /* PREFIX_VEX_0F75 */
4936   {
4937     { Bad_Opcode },
4938     { Bad_Opcode },
4939     { "vpcmpeqw",       { XM, Vex, EXx }, 0 },
4940   },
4941
4942   /* PREFIX_VEX_0F76 */
4943   {
4944     { Bad_Opcode },
4945     { Bad_Opcode },
4946     { "vpcmpeqd",       { XM, Vex, EXx }, 0 },
4947   },
4948
4949   /* PREFIX_VEX_0F77 */
4950   {
4951     { VEX_LEN_TABLE (VEX_LEN_0F77_P_0) },
4952   },
4953
4954   /* PREFIX_VEX_0F7C */
4955   {
4956     { Bad_Opcode },
4957     { Bad_Opcode },
4958     { "vhaddpd",        { XM, Vex, EXx }, 0 },
4959     { "vhaddps",        { XM, Vex, EXx }, 0 },
4960   },
4961
4962   /* PREFIX_VEX_0F7D */
4963   {
4964     { Bad_Opcode },
4965     { Bad_Opcode },
4966     { "vhsubpd",        { XM, Vex, EXx }, 0 },
4967     { "vhsubps",        { XM, Vex, EXx }, 0 },
4968   },
4969
4970   /* PREFIX_VEX_0F7E */
4971   {
4972     { Bad_Opcode },
4973     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
4974     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
4975   },
4976
4977   /* PREFIX_VEX_0F7F */
4978   {
4979     { Bad_Opcode },
4980     { "vmovdqu",        { EXxS, XM }, 0 },
4981     { "vmovdqa",        { EXxS, XM }, 0 },
4982   },
4983
4984   /* PREFIX_VEX_0F90 */
4985   {
4986     { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) },
4987     { Bad_Opcode },
4988     { VEX_LEN_TABLE (VEX_LEN_0F90_P_2) },
4989   },
4990
4991   /* PREFIX_VEX_0F91 */
4992   {
4993     { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) },
4994     { Bad_Opcode },
4995     { VEX_LEN_TABLE (VEX_LEN_0F91_P_2) },
4996   },
4997
4998   /* PREFIX_VEX_0F92 */
4999   {
5000     { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) },
5001     { Bad_Opcode },
5002     { VEX_LEN_TABLE (VEX_LEN_0F92_P_2) },
5003     { VEX_LEN_TABLE (VEX_LEN_0F92_P_3) },
5004   },
5005
5006   /* PREFIX_VEX_0F93 */
5007   {
5008     { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) },
5009     { Bad_Opcode },
5010     { VEX_LEN_TABLE (VEX_LEN_0F93_P_2) },
5011     { VEX_LEN_TABLE (VEX_LEN_0F93_P_3) },
5012   },
5013
5014   /* PREFIX_VEX_0F98 */
5015   {
5016     { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) },
5017     { Bad_Opcode },
5018     { VEX_LEN_TABLE (VEX_LEN_0F98_P_2) },
5019   },
5020
5021   /* PREFIX_VEX_0F99 */
5022   {
5023     { VEX_LEN_TABLE (VEX_LEN_0F99_P_0) },
5024     { Bad_Opcode },
5025     { VEX_LEN_TABLE (VEX_LEN_0F99_P_2) },
5026   },
5027
5028   /* PREFIX_VEX_0FC2 */
5029   {
5030     { "vcmpps",         { XM, Vex, EXx, VCMP }, 0 },
5031     { "vcmpss",         { XMScalar, VexScalar, EXxmm_md, VCMP }, 0 },
5032     { "vcmppd",         { XM, Vex, EXx, VCMP }, 0 },
5033     { "vcmpsd",         { XMScalar, VexScalar, EXxmm_mq, VCMP }, 0 },
5034   },
5035
5036   /* PREFIX_VEX_0FC4 */
5037   {
5038     { Bad_Opcode },
5039     { Bad_Opcode },
5040     { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) },
5041   },
5042
5043   /* PREFIX_VEX_0FC5 */
5044   {
5045     { Bad_Opcode },
5046     { Bad_Opcode },
5047     { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) },
5048   },
5049
5050   /* PREFIX_VEX_0FD0 */
5051   {
5052     { Bad_Opcode },
5053     { Bad_Opcode },
5054     { "vaddsubpd",      { XM, Vex, EXx }, 0 },
5055     { "vaddsubps",      { XM, Vex, EXx }, 0 },
5056   },
5057
5058   /* PREFIX_VEX_0FD1 */
5059   {
5060     { Bad_Opcode },
5061     { Bad_Opcode },
5062     { "vpsrlw",         { XM, Vex, EXxmm }, 0 },
5063   },
5064
5065   /* PREFIX_VEX_0FD2 */
5066   {
5067     { Bad_Opcode },
5068     { Bad_Opcode },
5069     { "vpsrld",         { XM, Vex, EXxmm }, 0 },
5070   },
5071
5072   /* PREFIX_VEX_0FD3 */
5073   {
5074     { Bad_Opcode },
5075     { Bad_Opcode },
5076     { "vpsrlq",         { XM, Vex, EXxmm }, 0 },
5077   },
5078
5079   /* PREFIX_VEX_0FD4 */
5080   {
5081     { Bad_Opcode },
5082     { Bad_Opcode },
5083     { "vpaddq",         { XM, Vex, EXx }, 0 },
5084   },
5085
5086   /* PREFIX_VEX_0FD5 */
5087   {
5088     { Bad_Opcode },
5089     { Bad_Opcode },
5090     { "vpmullw",        { XM, Vex, EXx }, 0 },
5091   },
5092
5093   /* PREFIX_VEX_0FD6 */
5094   {
5095     { Bad_Opcode },
5096     { Bad_Opcode },
5097     { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) },
5098   },
5099
5100   /* PREFIX_VEX_0FD7 */
5101   {
5102     { Bad_Opcode },
5103     { Bad_Opcode },
5104     { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) },
5105   },
5106
5107   /* PREFIX_VEX_0FD8 */
5108   {
5109     { Bad_Opcode },
5110     { Bad_Opcode },
5111     { "vpsubusb",       { XM, Vex, EXx }, 0 },
5112   },
5113
5114   /* PREFIX_VEX_0FD9 */
5115   {
5116     { Bad_Opcode },
5117     { Bad_Opcode },
5118     { "vpsubusw",       { XM, Vex, EXx }, 0 },
5119   },
5120
5121   /* PREFIX_VEX_0FDA */
5122   {
5123     { Bad_Opcode },
5124     { Bad_Opcode },
5125     { "vpminub",        { XM, Vex, EXx }, 0 },
5126   },
5127
5128   /* PREFIX_VEX_0FDB */
5129   {
5130     { Bad_Opcode },
5131     { Bad_Opcode },
5132     { "vpand",          { XM, Vex, EXx }, 0 },
5133   },
5134
5135   /* PREFIX_VEX_0FDC */
5136   {
5137     { Bad_Opcode },
5138     { Bad_Opcode },
5139     { "vpaddusb",       { XM, Vex, EXx }, 0 },
5140   },
5141
5142   /* PREFIX_VEX_0FDD */
5143   {
5144     { Bad_Opcode },
5145     { Bad_Opcode },
5146     { "vpaddusw",       { XM, Vex, EXx }, 0 },
5147   },
5148
5149   /* PREFIX_VEX_0FDE */
5150   {
5151     { Bad_Opcode },
5152     { Bad_Opcode },
5153     { "vpmaxub",        { XM, Vex, EXx }, 0 },
5154   },
5155
5156   /* PREFIX_VEX_0FDF */
5157   {
5158     { Bad_Opcode },
5159     { Bad_Opcode },
5160     { "vpandn",         { XM, Vex, EXx }, 0 },
5161   },
5162
5163   /* PREFIX_VEX_0FE0 */
5164   {
5165     { Bad_Opcode },
5166     { Bad_Opcode },
5167     { "vpavgb",         { XM, Vex, EXx }, 0 },
5168   },
5169
5170   /* PREFIX_VEX_0FE1 */
5171   {
5172     { Bad_Opcode },
5173     { Bad_Opcode },
5174     { "vpsraw",         { XM, Vex, EXxmm }, 0 },
5175   },
5176
5177   /* PREFIX_VEX_0FE2 */
5178   {
5179     { Bad_Opcode },
5180     { Bad_Opcode },
5181     { "vpsrad",         { XM, Vex, EXxmm }, 0 },
5182   },
5183
5184   /* PREFIX_VEX_0FE3 */
5185   {
5186     { Bad_Opcode },
5187     { Bad_Opcode },
5188     { "vpavgw",         { XM, Vex, EXx }, 0 },
5189   },
5190
5191   /* PREFIX_VEX_0FE4 */
5192   {
5193     { Bad_Opcode },
5194     { Bad_Opcode },
5195     { "vpmulhuw",       { XM, Vex, EXx }, 0 },
5196   },
5197
5198   /* PREFIX_VEX_0FE5 */
5199   {
5200     { Bad_Opcode },
5201     { Bad_Opcode },
5202     { "vpmulhw",        { XM, Vex, EXx }, 0 },
5203   },
5204
5205   /* PREFIX_VEX_0FE6 */
5206   {
5207     { Bad_Opcode },
5208     { "vcvtdq2pd",      { XM, EXxmmq }, 0 },
5209     { "vcvttpd2dq%XY",  { XMM, EXx }, 0 },
5210     { "vcvtpd2dq%XY",   { XMM, EXx }, 0 },
5211   },
5212
5213   /* PREFIX_VEX_0FE7 */
5214   {
5215     { Bad_Opcode },
5216     { Bad_Opcode },
5217     { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) },
5218   },
5219
5220   /* PREFIX_VEX_0FE8 */
5221   {
5222     { Bad_Opcode },
5223     { Bad_Opcode },
5224     { "vpsubsb",        { XM, Vex, EXx }, 0 },
5225   },
5226
5227   /* PREFIX_VEX_0FE9 */
5228   {
5229     { Bad_Opcode },
5230     { Bad_Opcode },
5231     { "vpsubsw",        { XM, Vex, EXx }, 0 },
5232   },
5233
5234   /* PREFIX_VEX_0FEA */
5235   {
5236     { Bad_Opcode },
5237     { Bad_Opcode },
5238     { "vpminsw",        { XM, Vex, EXx }, 0 },
5239   },
5240
5241   /* PREFIX_VEX_0FEB */
5242   {
5243     { Bad_Opcode },
5244     { Bad_Opcode },
5245     { "vpor",           { XM, Vex, EXx }, 0 },
5246   },
5247
5248   /* PREFIX_VEX_0FEC */
5249   {
5250     { Bad_Opcode },
5251     { Bad_Opcode },
5252     { "vpaddsb",        { XM, Vex, EXx }, 0 },
5253   },
5254
5255   /* PREFIX_VEX_0FED */
5256   {
5257     { Bad_Opcode },
5258     { Bad_Opcode },
5259     { "vpaddsw",        { XM, Vex, EXx }, 0 },
5260   },
5261
5262   /* PREFIX_VEX_0FEE */
5263   {
5264     { Bad_Opcode },
5265     { Bad_Opcode },
5266     { "vpmaxsw",        { XM, Vex, EXx }, 0 },
5267   },
5268
5269   /* PREFIX_VEX_0FEF */
5270   {
5271     { Bad_Opcode },
5272     { Bad_Opcode },
5273     { "vpxor",          { XM, Vex, EXx }, 0 },
5274   },
5275
5276   /* PREFIX_VEX_0FF0 */
5277   {
5278     { Bad_Opcode },
5279     { Bad_Opcode },
5280     { Bad_Opcode },
5281     { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
5282   },
5283
5284   /* PREFIX_VEX_0FF1 */
5285   {
5286     { Bad_Opcode },
5287     { Bad_Opcode },
5288     { "vpsllw",         { XM, Vex, EXxmm }, 0 },
5289   },
5290
5291   /* PREFIX_VEX_0FF2 */
5292   {
5293     { Bad_Opcode },
5294     { Bad_Opcode },
5295     { "vpslld",         { XM, Vex, EXxmm }, 0 },
5296   },
5297
5298   /* PREFIX_VEX_0FF3 */
5299   {
5300     { Bad_Opcode },
5301     { Bad_Opcode },
5302     { "vpsllq",         { XM, Vex, EXxmm }, 0 },
5303   },
5304
5305   /* PREFIX_VEX_0FF4 */
5306   {
5307     { Bad_Opcode },
5308     { Bad_Opcode },
5309     { "vpmuludq",       { XM, Vex, EXx }, 0 },
5310   },
5311
5312   /* PREFIX_VEX_0FF5 */
5313   {
5314     { Bad_Opcode },
5315     { Bad_Opcode },
5316     { "vpmaddwd",       { XM, Vex, EXx }, 0 },
5317   },
5318
5319   /* PREFIX_VEX_0FF6 */
5320   {
5321     { Bad_Opcode },
5322     { Bad_Opcode },
5323     { "vpsadbw",        { XM, Vex, EXx }, 0 },
5324   },
5325
5326   /* PREFIX_VEX_0FF7 */
5327   {
5328     { Bad_Opcode },
5329     { Bad_Opcode },
5330     { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) },
5331   },
5332
5333   /* PREFIX_VEX_0FF8 */
5334   {
5335     { Bad_Opcode },
5336     { Bad_Opcode },
5337     { "vpsubb",         { XM, Vex, EXx }, 0 },
5338   },
5339
5340   /* PREFIX_VEX_0FF9 */
5341   {
5342     { Bad_Opcode },
5343     { Bad_Opcode },
5344     { "vpsubw",         { XM, Vex, EXx }, 0 },
5345   },
5346
5347   /* PREFIX_VEX_0FFA */
5348   {
5349     { Bad_Opcode },
5350     { Bad_Opcode },
5351     { "vpsubd",         { XM, Vex, EXx }, 0 },
5352   },
5353
5354   /* PREFIX_VEX_0FFB */
5355   {
5356     { Bad_Opcode },
5357     { Bad_Opcode },
5358     { "vpsubq",         { XM, Vex, EXx }, 0 },
5359   },
5360
5361   /* PREFIX_VEX_0FFC */
5362   {
5363     { Bad_Opcode },
5364     { Bad_Opcode },
5365     { "vpaddb",         { XM, Vex, EXx }, 0 },
5366   },
5367
5368   /* PREFIX_VEX_0FFD */
5369   {
5370     { Bad_Opcode },
5371     { Bad_Opcode },
5372     { "vpaddw",         { XM, Vex, EXx }, 0 },
5373   },
5374
5375   /* PREFIX_VEX_0FFE */
5376   {
5377     { Bad_Opcode },
5378     { Bad_Opcode },
5379     { "vpaddd",         { XM, Vex, EXx }, 0 },
5380   },
5381
5382   /* PREFIX_VEX_0F3800 */
5383   {
5384     { Bad_Opcode },
5385     { Bad_Opcode },
5386     { "vpshufb",        { XM, Vex, EXx }, 0 },
5387   },
5388
5389   /* PREFIX_VEX_0F3801 */
5390   {
5391     { Bad_Opcode },
5392     { Bad_Opcode },
5393     { "vphaddw",        { XM, Vex, EXx }, 0 },
5394   },
5395
5396   /* PREFIX_VEX_0F3802 */
5397   {
5398     { Bad_Opcode },
5399     { Bad_Opcode },
5400     { "vphaddd",        { XM, Vex, EXx }, 0 },
5401   },
5402
5403   /* PREFIX_VEX_0F3803 */
5404   {
5405     { Bad_Opcode },
5406     { Bad_Opcode },
5407     { "vphaddsw",       { XM, Vex, EXx }, 0 },
5408   },
5409
5410   /* PREFIX_VEX_0F3804 */
5411   {
5412     { Bad_Opcode },
5413     { Bad_Opcode },
5414     { "vpmaddubsw",     { XM, Vex, EXx }, 0 },
5415   },
5416
5417   /* PREFIX_VEX_0F3805 */
5418   {
5419     { Bad_Opcode },
5420     { Bad_Opcode },
5421     { "vphsubw",        { XM, Vex, EXx }, 0 },
5422   },
5423
5424   /* PREFIX_VEX_0F3806 */
5425   {
5426     { Bad_Opcode },
5427     { Bad_Opcode },
5428     { "vphsubd",        { XM, Vex, EXx }, 0 },
5429   },
5430
5431   /* PREFIX_VEX_0F3807 */
5432   {
5433     { Bad_Opcode },
5434     { Bad_Opcode },
5435     { "vphsubsw",       { XM, Vex, EXx }, 0 },
5436   },
5437
5438   /* PREFIX_VEX_0F3808 */
5439   {
5440     { Bad_Opcode },
5441     { Bad_Opcode },
5442     { "vpsignb",        { XM, Vex, EXx }, 0 },
5443   },
5444
5445   /* PREFIX_VEX_0F3809 */
5446   {
5447     { Bad_Opcode },
5448     { Bad_Opcode },
5449     { "vpsignw",        { XM, Vex, EXx }, 0 },
5450   },
5451
5452   /* PREFIX_VEX_0F380A */
5453   {
5454     { Bad_Opcode },
5455     { Bad_Opcode },
5456     { "vpsignd",        { XM, Vex, EXx }, 0 },
5457   },
5458
5459   /* PREFIX_VEX_0F380B */
5460   {
5461     { Bad_Opcode },
5462     { Bad_Opcode },
5463     { "vpmulhrsw",      { XM, Vex, EXx }, 0 },
5464   },
5465
5466   /* PREFIX_VEX_0F380C */
5467   {
5468     { Bad_Opcode },
5469     { Bad_Opcode },
5470     { VEX_W_TABLE (VEX_W_0F380C_P_2) },
5471   },
5472
5473   /* PREFIX_VEX_0F380D */
5474   {
5475     { Bad_Opcode },
5476     { Bad_Opcode },
5477     { VEX_W_TABLE (VEX_W_0F380D_P_2) },
5478   },
5479
5480   /* PREFIX_VEX_0F380E */
5481   {
5482     { Bad_Opcode },
5483     { Bad_Opcode },
5484     { VEX_W_TABLE (VEX_W_0F380E_P_2) },
5485   },
5486
5487   /* PREFIX_VEX_0F380F */
5488   {
5489     { Bad_Opcode },
5490     { Bad_Opcode },
5491     { VEX_W_TABLE (VEX_W_0F380F_P_2) },
5492   },
5493
5494   /* PREFIX_VEX_0F3813 */
5495   {
5496     { Bad_Opcode },
5497     { Bad_Opcode },
5498     { VEX_W_TABLE (VEX_W_0F3813_P_2) },
5499   },
5500
5501   /* PREFIX_VEX_0F3816 */
5502   {
5503     { Bad_Opcode },
5504     { Bad_Opcode },
5505     { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) },
5506   },
5507
5508   /* PREFIX_VEX_0F3817 */
5509   {
5510     { Bad_Opcode },
5511     { Bad_Opcode },
5512     { "vptest",         { XM, EXx }, 0 },
5513   },
5514
5515   /* PREFIX_VEX_0F3818 */
5516   {
5517     { Bad_Opcode },
5518     { Bad_Opcode },
5519     { VEX_W_TABLE (VEX_W_0F3818_P_2) },
5520   },
5521
5522   /* PREFIX_VEX_0F3819 */
5523   {
5524     { Bad_Opcode },
5525     { Bad_Opcode },
5526     { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) },
5527   },
5528
5529   /* PREFIX_VEX_0F381A */
5530   {
5531     { Bad_Opcode },
5532     { Bad_Opcode },
5533     { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) },
5534   },
5535
5536   /* PREFIX_VEX_0F381C */
5537   {
5538     { Bad_Opcode },
5539     { Bad_Opcode },
5540     { "vpabsb",         { XM, EXx }, 0 },
5541   },
5542
5543   /* PREFIX_VEX_0F381D */
5544   {
5545     { Bad_Opcode },
5546     { Bad_Opcode },
5547     { "vpabsw",         { XM, EXx }, 0 },
5548   },
5549
5550   /* PREFIX_VEX_0F381E */
5551   {
5552     { Bad_Opcode },
5553     { Bad_Opcode },
5554     { "vpabsd",         { XM, EXx }, 0 },
5555   },
5556
5557   /* PREFIX_VEX_0F3820 */
5558   {
5559     { Bad_Opcode },
5560     { Bad_Opcode },
5561     { "vpmovsxbw",      { XM, EXxmmq }, 0 },
5562   },
5563
5564   /* PREFIX_VEX_0F3821 */
5565   {
5566     { Bad_Opcode },
5567     { Bad_Opcode },
5568     { "vpmovsxbd",      { XM, EXxmmqd }, 0 },
5569   },
5570
5571   /* PREFIX_VEX_0F3822 */
5572   {
5573     { Bad_Opcode },
5574     { Bad_Opcode },
5575     { "vpmovsxbq",      { XM, EXxmmdw }, 0 },
5576   },
5577
5578   /* PREFIX_VEX_0F3823 */
5579   {
5580     { Bad_Opcode },
5581     { Bad_Opcode },
5582     { "vpmovsxwd",      { XM, EXxmmq }, 0 },
5583   },
5584
5585   /* PREFIX_VEX_0F3824 */
5586   {
5587     { Bad_Opcode },
5588     { Bad_Opcode },
5589     { "vpmovsxwq",      { XM, EXxmmqd }, 0 },
5590   },
5591
5592   /* PREFIX_VEX_0F3825 */
5593   {
5594     { Bad_Opcode },
5595     { Bad_Opcode },
5596     { "vpmovsxdq",      { XM, EXxmmq }, 0 },
5597   },
5598
5599   /* PREFIX_VEX_0F3828 */
5600   {
5601     { Bad_Opcode },
5602     { Bad_Opcode },
5603     { "vpmuldq",        { XM, Vex, EXx }, 0 },
5604   },
5605
5606   /* PREFIX_VEX_0F3829 */
5607   {
5608     { Bad_Opcode },
5609     { Bad_Opcode },
5610     { "vpcmpeqq",       { XM, Vex, EXx }, 0 },
5611   },
5612
5613   /* PREFIX_VEX_0F382A */
5614   {
5615     { Bad_Opcode },
5616     { Bad_Opcode },
5617     { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) },
5618   },
5619
5620   /* PREFIX_VEX_0F382B */
5621   {
5622     { Bad_Opcode },
5623     { Bad_Opcode },
5624     { "vpackusdw",      { XM, Vex, EXx }, 0 },
5625   },
5626
5627   /* PREFIX_VEX_0F382C */
5628   {
5629     { Bad_Opcode },
5630     { Bad_Opcode },
5631      { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) },
5632   },
5633
5634   /* PREFIX_VEX_0F382D */
5635   {
5636     { Bad_Opcode },
5637     { Bad_Opcode },
5638      { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) },
5639   },
5640
5641   /* PREFIX_VEX_0F382E */
5642   {
5643     { Bad_Opcode },
5644     { Bad_Opcode },
5645      { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) },
5646   },
5647
5648   /* PREFIX_VEX_0F382F */
5649   {
5650     { Bad_Opcode },
5651     { Bad_Opcode },
5652      { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) },
5653   },
5654
5655   /* PREFIX_VEX_0F3830 */
5656   {
5657     { Bad_Opcode },
5658     { Bad_Opcode },
5659     { "vpmovzxbw",      { XM, EXxmmq }, 0 },
5660   },
5661
5662   /* PREFIX_VEX_0F3831 */
5663   {
5664     { Bad_Opcode },
5665     { Bad_Opcode },
5666     { "vpmovzxbd",      { XM, EXxmmqd }, 0 },
5667   },
5668
5669   /* PREFIX_VEX_0F3832 */
5670   {
5671     { Bad_Opcode },
5672     { Bad_Opcode },
5673     { "vpmovzxbq",      { XM, EXxmmdw }, 0 },
5674   },
5675
5676   /* PREFIX_VEX_0F3833 */
5677   {
5678     { Bad_Opcode },
5679     { Bad_Opcode },
5680     { "vpmovzxwd",      { XM, EXxmmq }, 0 },
5681   },
5682
5683   /* PREFIX_VEX_0F3834 */
5684   {
5685     { Bad_Opcode },
5686     { Bad_Opcode },
5687     { "vpmovzxwq",      { XM, EXxmmqd }, 0 },
5688   },
5689
5690   /* PREFIX_VEX_0F3835 */
5691   {
5692     { Bad_Opcode },
5693     { Bad_Opcode },
5694     { "vpmovzxdq",      { XM, EXxmmq }, 0 },
5695   },
5696
5697   /* PREFIX_VEX_0F3836 */
5698   {
5699     { Bad_Opcode },
5700     { Bad_Opcode },
5701     { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) },
5702   },
5703
5704   /* PREFIX_VEX_0F3837 */
5705   {
5706     { Bad_Opcode },
5707     { Bad_Opcode },
5708     { "vpcmpgtq",       { XM, Vex, EXx }, 0 },
5709   },
5710
5711   /* PREFIX_VEX_0F3838 */
5712   {
5713     { Bad_Opcode },
5714     { Bad_Opcode },
5715     { "vpminsb",        { XM, Vex, EXx }, 0 },
5716   },
5717
5718   /* PREFIX_VEX_0F3839 */
5719   {
5720     { Bad_Opcode },
5721     { Bad_Opcode },
5722     { "vpminsd",        { XM, Vex, EXx }, 0 },
5723   },
5724
5725   /* PREFIX_VEX_0F383A */
5726   {
5727     { Bad_Opcode },
5728     { Bad_Opcode },
5729     { "vpminuw",        { XM, Vex, EXx }, 0 },
5730   },
5731
5732   /* PREFIX_VEX_0F383B */
5733   {
5734     { Bad_Opcode },
5735     { Bad_Opcode },
5736     { "vpminud",        { XM, Vex, EXx }, 0 },
5737   },
5738
5739   /* PREFIX_VEX_0F383C */
5740   {
5741     { Bad_Opcode },
5742     { Bad_Opcode },
5743     { "vpmaxsb",        { XM, Vex, EXx }, 0 },
5744   },
5745
5746   /* PREFIX_VEX_0F383D */
5747   {
5748     { Bad_Opcode },
5749     { Bad_Opcode },
5750     { "vpmaxsd",        { XM, Vex, EXx }, 0 },
5751   },
5752
5753   /* PREFIX_VEX_0F383E */
5754   {
5755     { Bad_Opcode },
5756     { Bad_Opcode },
5757     { "vpmaxuw",        { XM, Vex, EXx }, 0 },
5758   },
5759
5760   /* PREFIX_VEX_0F383F */
5761   {
5762     { Bad_Opcode },
5763     { Bad_Opcode },
5764     { "vpmaxud",        { XM, Vex, EXx }, 0 },
5765   },
5766
5767   /* PREFIX_VEX_0F3840 */
5768   {
5769     { Bad_Opcode },
5770     { Bad_Opcode },
5771     { "vpmulld",        { XM, Vex, EXx }, 0 },
5772   },
5773
5774   /* PREFIX_VEX_0F3841 */
5775   {
5776     { Bad_Opcode },
5777     { Bad_Opcode },
5778     { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) },
5779   },
5780
5781   /* PREFIX_VEX_0F3845 */
5782   {
5783     { Bad_Opcode },
5784     { Bad_Opcode },
5785     { "vpsrlv%LW", { XM, Vex, EXx }, 0 },
5786   },
5787
5788   /* PREFIX_VEX_0F3846 */
5789   {
5790     { Bad_Opcode },
5791     { Bad_Opcode },
5792     { VEX_W_TABLE (VEX_W_0F3846_P_2) },
5793   },
5794
5795   /* PREFIX_VEX_0F3847 */
5796   {
5797     { Bad_Opcode },
5798     { Bad_Opcode },
5799     { "vpsllv%LW", { XM, Vex, EXx }, 0 },
5800   },
5801
5802   /* PREFIX_VEX_0F3858 */
5803   {
5804     { Bad_Opcode },
5805     { Bad_Opcode },
5806     { VEX_W_TABLE (VEX_W_0F3858_P_2) },
5807   },
5808
5809   /* PREFIX_VEX_0F3859 */
5810   {
5811     { Bad_Opcode },
5812     { Bad_Opcode },
5813     { VEX_W_TABLE (VEX_W_0F3859_P_2) },
5814   },
5815
5816   /* PREFIX_VEX_0F385A */
5817   {
5818     { Bad_Opcode },
5819     { Bad_Opcode },
5820     { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) },
5821   },
5822
5823   /* PREFIX_VEX_0F3878 */
5824   {
5825     { Bad_Opcode },
5826     { Bad_Opcode },
5827     { VEX_W_TABLE (VEX_W_0F3878_P_2) },
5828   },
5829
5830   /* PREFIX_VEX_0F3879 */
5831   {
5832     { Bad_Opcode },
5833     { Bad_Opcode },
5834     { VEX_W_TABLE (VEX_W_0F3879_P_2) },
5835   },
5836
5837   /* PREFIX_VEX_0F388C */
5838   {
5839     { Bad_Opcode },
5840     { Bad_Opcode },
5841     { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) },
5842   },
5843
5844   /* PREFIX_VEX_0F388E */
5845   {
5846     { Bad_Opcode },
5847     { Bad_Opcode },
5848     { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) },
5849   },
5850
5851   /* PREFIX_VEX_0F3890 */
5852   {
5853     { Bad_Opcode },
5854     { Bad_Opcode },
5855     { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex }, 0 },
5856   },
5857
5858   /* PREFIX_VEX_0F3891 */
5859   {
5860     { Bad_Opcode },
5861     { Bad_Opcode },
5862     { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
5863   },
5864
5865   /* PREFIX_VEX_0F3892 */
5866   {
5867     { Bad_Opcode },
5868     { Bad_Opcode },
5869     { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex }, 0 },
5870   },
5871
5872   /* PREFIX_VEX_0F3893 */
5873   {
5874     { Bad_Opcode },
5875     { Bad_Opcode },
5876     { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
5877   },
5878
5879   /* PREFIX_VEX_0F3896 */
5880   {
5881     { Bad_Opcode },
5882     { Bad_Opcode },
5883     { "vfmaddsub132p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
5884   },
5885
5886   /* PREFIX_VEX_0F3897 */
5887   {
5888     { Bad_Opcode },
5889     { Bad_Opcode },
5890     { "vfmsubadd132p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
5891   },
5892
5893   /* PREFIX_VEX_0F3898 */
5894   {
5895     { Bad_Opcode },
5896     { Bad_Opcode },
5897     { "vfmadd132p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
5898   },
5899
5900   /* PREFIX_VEX_0F3899 */
5901   {
5902     { Bad_Opcode },
5903     { Bad_Opcode },
5904     { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
5905   },
5906
5907   /* PREFIX_VEX_0F389A */
5908   {
5909     { Bad_Opcode },
5910     { Bad_Opcode },
5911     { "vfmsub132p%XW", { XM, Vex, EXx }, 0 },
5912   },
5913
5914   /* PREFIX_VEX_0F389B */
5915   {
5916     { Bad_Opcode },
5917     { Bad_Opcode },
5918     { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
5919   },
5920
5921   /* PREFIX_VEX_0F389C */
5922   {
5923     { Bad_Opcode },
5924     { Bad_Opcode },
5925     { "vfnmadd132p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
5926   },
5927
5928   /* PREFIX_VEX_0F389D */
5929   {
5930     { Bad_Opcode },
5931     { Bad_Opcode },
5932     { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
5933   },
5934
5935   /* PREFIX_VEX_0F389E */
5936   {
5937     { Bad_Opcode },
5938     { Bad_Opcode },
5939     { "vfnmsub132p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
5940   },
5941
5942   /* PREFIX_VEX_0F389F */
5943   {
5944     { Bad_Opcode },
5945     { Bad_Opcode },
5946     { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
5947   },
5948
5949   /* PREFIX_VEX_0F38A6 */
5950   {
5951     { Bad_Opcode },
5952     { Bad_Opcode },
5953     { "vfmaddsub213p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
5954     { Bad_Opcode },
5955   },
5956
5957   /* PREFIX_VEX_0F38A7 */
5958   {
5959     { Bad_Opcode },
5960     { Bad_Opcode },
5961     { "vfmsubadd213p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
5962   },
5963
5964   /* PREFIX_VEX_0F38A8 */
5965   {
5966     { Bad_Opcode },
5967     { Bad_Opcode },
5968     { "vfmadd213p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
5969   },
5970
5971   /* PREFIX_VEX_0F38A9 */
5972   {
5973     { Bad_Opcode },
5974     { Bad_Opcode },
5975     { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
5976   },
5977
5978   /* PREFIX_VEX_0F38AA */
5979   {
5980     { Bad_Opcode },
5981     { Bad_Opcode },
5982     { "vfmsub213p%XW", { XM, Vex, EXx }, 0 },
5983   },
5984
5985   /* PREFIX_VEX_0F38AB */
5986   {
5987     { Bad_Opcode },
5988     { Bad_Opcode },
5989     { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
5990   },
5991
5992   /* PREFIX_VEX_0F38AC */
5993   {
5994     { Bad_Opcode },
5995     { Bad_Opcode },
5996     { "vfnmadd213p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
5997   },
5998
5999   /* PREFIX_VEX_0F38AD */
6000   {
6001     { Bad_Opcode },
6002     { Bad_Opcode },
6003     { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
6004   },
6005
6006   /* PREFIX_VEX_0F38AE */
6007   {
6008     { Bad_Opcode },
6009     { Bad_Opcode },
6010     { "vfnmsub213p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6011   },
6012
6013   /* PREFIX_VEX_0F38AF */
6014   {
6015     { Bad_Opcode },
6016     { Bad_Opcode },
6017     { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
6018   },
6019
6020   /* PREFIX_VEX_0F38B6 */
6021   {
6022     { Bad_Opcode },
6023     { Bad_Opcode },
6024     { "vfmaddsub231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6025   },
6026
6027   /* PREFIX_VEX_0F38B7 */
6028   {
6029     { Bad_Opcode },
6030     { Bad_Opcode },
6031     { "vfmsubadd231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6032   },
6033
6034   /* PREFIX_VEX_0F38B8 */
6035   {
6036     { Bad_Opcode },
6037     { Bad_Opcode },
6038     { "vfmadd231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6039   },
6040
6041   /* PREFIX_VEX_0F38B9 */
6042   {
6043     { Bad_Opcode },
6044     { Bad_Opcode },
6045     { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
6046   },
6047
6048   /* PREFIX_VEX_0F38BA */
6049   {
6050     { Bad_Opcode },
6051     { Bad_Opcode },
6052     { "vfmsub231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6053   },
6054
6055   /* PREFIX_VEX_0F38BB */
6056   {
6057     { Bad_Opcode },
6058     { Bad_Opcode },
6059     { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
6060   },
6061
6062   /* PREFIX_VEX_0F38BC */
6063   {
6064     { Bad_Opcode },
6065     { Bad_Opcode },
6066     { "vfnmadd231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6067   },
6068
6069   /* PREFIX_VEX_0F38BD */
6070   {
6071     { Bad_Opcode },
6072     { Bad_Opcode },
6073     { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
6074   },
6075
6076   /* PREFIX_VEX_0F38BE */
6077   {
6078     { Bad_Opcode },
6079     { Bad_Opcode },
6080     { "vfnmsub231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6081   },
6082
6083   /* PREFIX_VEX_0F38BF */
6084   {
6085     { Bad_Opcode },
6086     { Bad_Opcode },
6087     { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
6088   },
6089
6090   /* PREFIX_VEX_0F38CF */
6091   {
6092     { Bad_Opcode },
6093     { Bad_Opcode },
6094     { VEX_W_TABLE (VEX_W_0F38CF_P_2) },
6095   },
6096
6097   /* PREFIX_VEX_0F38DB */
6098   {
6099     { Bad_Opcode },
6100     { Bad_Opcode },
6101     { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) },
6102   },
6103
6104   /* PREFIX_VEX_0F38DC */
6105   {
6106     { Bad_Opcode },
6107     { Bad_Opcode },
6108     { "vaesenc",        { XM, Vex, EXx }, 0 },
6109   },
6110
6111   /* PREFIX_VEX_0F38DD */
6112   {
6113     { Bad_Opcode },
6114     { Bad_Opcode },
6115     { "vaesenclast",    { XM, Vex, EXx }, 0 },
6116   },
6117
6118   /* PREFIX_VEX_0F38DE */
6119   {
6120     { Bad_Opcode },
6121     { Bad_Opcode },
6122     { "vaesdec",        { XM, Vex, EXx }, 0 },
6123   },
6124
6125   /* PREFIX_VEX_0F38DF */
6126   {
6127     { Bad_Opcode },
6128     { Bad_Opcode },
6129     { "vaesdeclast",    { XM, Vex, EXx }, 0 },
6130   },
6131
6132   /* PREFIX_VEX_0F38F2 */
6133   {
6134     { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) },
6135   },
6136
6137   /* PREFIX_VEX_0F38F3_REG_1 */
6138   {
6139     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) },
6140   },
6141
6142   /* PREFIX_VEX_0F38F3_REG_2 */
6143   {
6144     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) },
6145   },
6146
6147   /* PREFIX_VEX_0F38F3_REG_3 */
6148   {
6149     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) },
6150   },
6151
6152   /* PREFIX_VEX_0F38F5 */
6153   {
6154     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) },
6155     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) },
6156     { Bad_Opcode },
6157     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) },
6158   },
6159
6160   /* PREFIX_VEX_0F38F6 */
6161   {
6162     { Bad_Opcode },
6163     { Bad_Opcode },
6164     { Bad_Opcode },
6165     { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) },
6166   },
6167
6168   /* PREFIX_VEX_0F38F7 */
6169   {
6170     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) },
6171     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) },
6172     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) },
6173     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) },
6174   },
6175
6176   /* PREFIX_VEX_0F3A00 */
6177   {
6178     { Bad_Opcode },
6179     { Bad_Opcode },
6180     { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) },
6181   },
6182
6183   /* PREFIX_VEX_0F3A01 */
6184   {
6185     { Bad_Opcode },
6186     { Bad_Opcode },
6187     { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) },
6188   },
6189
6190   /* PREFIX_VEX_0F3A02 */
6191   {
6192     { Bad_Opcode },
6193     { Bad_Opcode },
6194     { VEX_W_TABLE (VEX_W_0F3A02_P_2) },
6195   },
6196
6197   /* PREFIX_VEX_0F3A04 */
6198   {
6199     { Bad_Opcode },
6200     { Bad_Opcode },
6201     { VEX_W_TABLE (VEX_W_0F3A04_P_2) },
6202   },
6203
6204   /* PREFIX_VEX_0F3A05 */
6205   {
6206     { Bad_Opcode },
6207     { Bad_Opcode },
6208     { VEX_W_TABLE (VEX_W_0F3A05_P_2) },
6209   },
6210
6211   /* PREFIX_VEX_0F3A06 */
6212   {
6213     { Bad_Opcode },
6214     { Bad_Opcode },
6215     { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) },
6216   },
6217
6218   /* PREFIX_VEX_0F3A08 */
6219   {
6220     { Bad_Opcode },
6221     { Bad_Opcode },
6222     { "vroundps",       { XM, EXx, Ib }, 0 },
6223   },
6224
6225   /* PREFIX_VEX_0F3A09 */
6226   {
6227     { Bad_Opcode },
6228     { Bad_Opcode },
6229     { "vroundpd",       { XM, EXx, Ib }, 0 },
6230   },
6231
6232   /* PREFIX_VEX_0F3A0A */
6233   {
6234     { Bad_Opcode },
6235     { Bad_Opcode },
6236     { "vroundss",       { XMScalar, VexScalar, EXxmm_md, Ib }, 0 },
6237   },
6238
6239   /* PREFIX_VEX_0F3A0B */
6240   {
6241     { Bad_Opcode },
6242     { Bad_Opcode },
6243     { "vroundsd",       { XMScalar, VexScalar, EXxmm_mq, Ib }, 0 },
6244   },
6245
6246   /* PREFIX_VEX_0F3A0C */
6247   {
6248     { Bad_Opcode },
6249     { Bad_Opcode },
6250     { "vblendps",       { XM, Vex, EXx, Ib }, 0 },
6251   },
6252
6253   /* PREFIX_VEX_0F3A0D */
6254   {
6255     { Bad_Opcode },
6256     { Bad_Opcode },
6257     { "vblendpd",       { XM, Vex, EXx, Ib }, 0 },
6258   },
6259
6260   /* PREFIX_VEX_0F3A0E */
6261   {
6262     { Bad_Opcode },
6263     { Bad_Opcode },
6264     { "vpblendw",       { XM, Vex, EXx, Ib }, 0 },
6265   },
6266
6267   /* PREFIX_VEX_0F3A0F */
6268   {
6269     { Bad_Opcode },
6270     { Bad_Opcode },
6271     { "vpalignr",       { XM, Vex, EXx, Ib }, 0 },
6272   },
6273
6274   /* PREFIX_VEX_0F3A14 */
6275   {
6276     { Bad_Opcode },
6277     { Bad_Opcode },
6278     { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) },
6279   },
6280
6281   /* PREFIX_VEX_0F3A15 */
6282   {
6283     { Bad_Opcode },
6284     { Bad_Opcode },
6285     { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) },
6286   },
6287
6288   /* PREFIX_VEX_0F3A16 */
6289   {
6290     { Bad_Opcode },
6291     { Bad_Opcode },
6292     { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) },
6293   },
6294
6295   /* PREFIX_VEX_0F3A17 */
6296   {
6297     { Bad_Opcode },
6298     { Bad_Opcode },
6299     { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) },
6300   },
6301
6302   /* PREFIX_VEX_0F3A18 */
6303   {
6304     { Bad_Opcode },
6305     { Bad_Opcode },
6306     { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) },
6307   },
6308
6309   /* PREFIX_VEX_0F3A19 */
6310   {
6311     { Bad_Opcode },
6312     { Bad_Opcode },
6313     { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) },
6314   },
6315
6316   /* PREFIX_VEX_0F3A1D */
6317   {
6318     { Bad_Opcode },
6319     { Bad_Opcode },
6320     { VEX_W_TABLE (VEX_W_0F3A1D_P_2) },
6321   },
6322
6323   /* PREFIX_VEX_0F3A20 */
6324   {
6325     { Bad_Opcode },
6326     { Bad_Opcode },
6327     { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) },
6328   },
6329
6330   /* PREFIX_VEX_0F3A21 */
6331   {
6332     { Bad_Opcode },
6333     { Bad_Opcode },
6334     { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) },
6335   },
6336
6337   /* PREFIX_VEX_0F3A22 */
6338   {
6339     { Bad_Opcode },
6340     { Bad_Opcode },
6341     { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) },
6342   },
6343
6344   /* PREFIX_VEX_0F3A30 */
6345   {
6346     { Bad_Opcode },
6347     { Bad_Opcode },
6348     { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2) },
6349   },
6350
6351   /* PREFIX_VEX_0F3A31 */
6352   {
6353     { Bad_Opcode },
6354     { Bad_Opcode },
6355     { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2) },
6356   },
6357
6358   /* PREFIX_VEX_0F3A32 */
6359   {
6360     { Bad_Opcode },
6361     { Bad_Opcode },
6362     { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2) },
6363   },
6364
6365   /* PREFIX_VEX_0F3A33 */
6366   {
6367     { Bad_Opcode },
6368     { Bad_Opcode },
6369     { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2) },
6370   },
6371
6372   /* PREFIX_VEX_0F3A38 */
6373   {
6374     { Bad_Opcode },
6375     { Bad_Opcode },
6376     { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) },
6377   },
6378
6379   /* PREFIX_VEX_0F3A39 */
6380   {
6381     { Bad_Opcode },
6382     { Bad_Opcode },
6383     { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) },
6384   },
6385
6386   /* PREFIX_VEX_0F3A40 */
6387   {
6388     { Bad_Opcode },
6389     { Bad_Opcode },
6390     { "vdpps",          { XM, Vex, EXx, Ib }, 0 },
6391   },
6392
6393   /* PREFIX_VEX_0F3A41 */
6394   {
6395     { Bad_Opcode },
6396     { Bad_Opcode },
6397     { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) },
6398   },
6399
6400   /* PREFIX_VEX_0F3A42 */
6401   {
6402     { Bad_Opcode },
6403     { Bad_Opcode },
6404     { "vmpsadbw",       { XM, Vex, EXx, Ib }, 0 },
6405   },
6406
6407   /* PREFIX_VEX_0F3A44 */
6408   {
6409     { Bad_Opcode },
6410     { Bad_Opcode },
6411     { "vpclmulqdq",     { XM, Vex, EXx, PCLMUL }, 0 },
6412   },
6413
6414   /* PREFIX_VEX_0F3A46 */
6415   {
6416     { Bad_Opcode },
6417     { Bad_Opcode },
6418     { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) },
6419   },
6420
6421   /* PREFIX_VEX_0F3A48 */
6422   {
6423     { Bad_Opcode },
6424     { Bad_Opcode },
6425     { VEX_W_TABLE (VEX_W_0F3A48_P_2) },
6426   },
6427
6428   /* PREFIX_VEX_0F3A49 */
6429   {
6430     { Bad_Opcode },
6431     { Bad_Opcode },
6432     { VEX_W_TABLE (VEX_W_0F3A49_P_2) },
6433   },
6434
6435   /* PREFIX_VEX_0F3A4A */
6436   {
6437     { Bad_Opcode },
6438     { Bad_Opcode },
6439     { VEX_W_TABLE (VEX_W_0F3A4A_P_2) },
6440   },
6441
6442   /* PREFIX_VEX_0F3A4B */
6443   {
6444     { Bad_Opcode },
6445     { Bad_Opcode },
6446     { VEX_W_TABLE (VEX_W_0F3A4B_P_2) },
6447   },
6448
6449   /* PREFIX_VEX_0F3A4C */
6450   {
6451     { Bad_Opcode },
6452     { Bad_Opcode },
6453     { VEX_W_TABLE (VEX_W_0F3A4C_P_2) },
6454   },
6455
6456   /* PREFIX_VEX_0F3A5C */
6457   {
6458     { Bad_Opcode },
6459     { Bad_Opcode },
6460     { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6461   },
6462
6463   /* PREFIX_VEX_0F3A5D */
6464   {
6465     { Bad_Opcode },
6466     { Bad_Opcode },
6467     { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6468   },
6469
6470   /* PREFIX_VEX_0F3A5E */
6471   {
6472     { Bad_Opcode },
6473     { Bad_Opcode },
6474     { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6475   },
6476
6477   /* PREFIX_VEX_0F3A5F */
6478   {
6479     { Bad_Opcode },
6480     { Bad_Opcode },
6481     { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6482   },
6483
6484   /* PREFIX_VEX_0F3A60 */
6485   {
6486     { Bad_Opcode },
6487     { Bad_Opcode },
6488     { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) },
6489     { Bad_Opcode },
6490   },
6491
6492   /* PREFIX_VEX_0F3A61 */
6493   {
6494     { Bad_Opcode },
6495     { Bad_Opcode },
6496     { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) },
6497   },
6498
6499   /* PREFIX_VEX_0F3A62 */
6500   {
6501     { Bad_Opcode },
6502     { Bad_Opcode },
6503     { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) },
6504   },
6505
6506   /* PREFIX_VEX_0F3A63 */
6507   {
6508     { Bad_Opcode },
6509     { Bad_Opcode },
6510     { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) },
6511   },
6512
6513   /* PREFIX_VEX_0F3A68 */
6514   {
6515     { Bad_Opcode },
6516     { Bad_Opcode },
6517     { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6518   },
6519
6520   /* PREFIX_VEX_0F3A69 */
6521   {
6522     { Bad_Opcode },
6523     { Bad_Opcode },
6524     { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6525   },
6526
6527   /* PREFIX_VEX_0F3A6A */
6528   {
6529     { Bad_Opcode },
6530     { Bad_Opcode },
6531     { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) },
6532   },
6533
6534   /* PREFIX_VEX_0F3A6B */
6535   {
6536     { Bad_Opcode },
6537     { Bad_Opcode },
6538     { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) },
6539   },
6540
6541   /* PREFIX_VEX_0F3A6C */
6542   {
6543     { Bad_Opcode },
6544     { Bad_Opcode },
6545     { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6546   },
6547
6548   /* PREFIX_VEX_0F3A6D */
6549   {
6550     { Bad_Opcode },
6551     { Bad_Opcode },
6552     { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6553   },
6554
6555   /* PREFIX_VEX_0F3A6E */
6556   {
6557     { Bad_Opcode },
6558     { Bad_Opcode },
6559     { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) },
6560   },
6561
6562   /* PREFIX_VEX_0F3A6F */
6563   {
6564     { Bad_Opcode },
6565     { Bad_Opcode },
6566     { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) },
6567   },
6568
6569   /* PREFIX_VEX_0F3A78 */
6570   {
6571     { Bad_Opcode },
6572     { Bad_Opcode },
6573     { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6574   },
6575
6576   /* PREFIX_VEX_0F3A79 */
6577   {
6578     { Bad_Opcode },
6579     { Bad_Opcode },
6580     { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6581   },
6582
6583   /* PREFIX_VEX_0F3A7A */
6584   {
6585     { Bad_Opcode },
6586     { Bad_Opcode },
6587     { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) },
6588   },
6589
6590   /* PREFIX_VEX_0F3A7B */
6591   {
6592     { Bad_Opcode },
6593     { Bad_Opcode },
6594     { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) },
6595   },
6596
6597   /* PREFIX_VEX_0F3A7C */
6598   {
6599     { Bad_Opcode },
6600     { Bad_Opcode },
6601     { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6602     { Bad_Opcode },
6603   },
6604
6605   /* PREFIX_VEX_0F3A7D */
6606   {
6607     { Bad_Opcode },
6608     { Bad_Opcode },
6609     { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6610   },
6611
6612   /* PREFIX_VEX_0F3A7E */
6613   {
6614     { Bad_Opcode },
6615     { Bad_Opcode },
6616     { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) },
6617   },
6618
6619   /* PREFIX_VEX_0F3A7F */
6620   {
6621     { Bad_Opcode },
6622     { Bad_Opcode },
6623     { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) },
6624   },
6625
6626   /* PREFIX_VEX_0F3ACE */
6627   {
6628     { Bad_Opcode },
6629     { Bad_Opcode },
6630     { VEX_W_TABLE (VEX_W_0F3ACE_P_2) },
6631   },
6632
6633   /* PREFIX_VEX_0F3ACF */
6634   {
6635     { Bad_Opcode },
6636     { Bad_Opcode },
6637     { VEX_W_TABLE (VEX_W_0F3ACF_P_2) },
6638   },
6639
6640   /* PREFIX_VEX_0F3ADF */
6641   {
6642     { Bad_Opcode },
6643     { Bad_Opcode },
6644     { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) },
6645   },
6646
6647   /* PREFIX_VEX_0F3AF0 */
6648   {
6649     { Bad_Opcode },
6650     { Bad_Opcode },
6651     { Bad_Opcode },
6652     { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) },
6653   },
6654
6655 #include "i386-dis-evex-prefix.h"
6656 };
6657
6658 static const struct dis386 x86_64_table[][2] = {
6659   /* X86_64_06 */
6660   {
6661     { "pushP", { es }, 0 },
6662   },
6663
6664   /* X86_64_07 */
6665   {
6666     { "popP", { es }, 0 },
6667   },
6668
6669   /* X86_64_0E */
6670   {
6671     { "pushP", { cs }, 0 },
6672   },
6673
6674   /* X86_64_16 */
6675   {
6676     { "pushP", { ss }, 0 },
6677   },
6678
6679   /* X86_64_17 */
6680   {
6681     { "popP", { ss }, 0 },
6682   },
6683
6684   /* X86_64_1E */
6685   {
6686     { "pushP", { ds }, 0 },
6687   },
6688
6689   /* X86_64_1F */
6690   {
6691     { "popP", { ds }, 0 },
6692   },
6693
6694   /* X86_64_27 */
6695   {
6696     { "daa", { XX }, 0 },
6697   },
6698
6699   /* X86_64_2F */
6700   {
6701     { "das", { XX }, 0 },
6702   },
6703
6704   /* X86_64_37 */
6705   {
6706     { "aaa", { XX }, 0 },
6707   },
6708
6709   /* X86_64_3F */
6710   {
6711     { "aas", { XX }, 0 },
6712   },
6713
6714   /* X86_64_60 */
6715   {
6716     { "pushaP", { XX }, 0 },
6717   },
6718
6719   /* X86_64_61 */
6720   {
6721     { "popaP", { XX }, 0 },
6722   },
6723
6724   /* X86_64_62 */
6725   {
6726     { MOD_TABLE (MOD_62_32BIT) },
6727     { EVEX_TABLE (EVEX_0F) },
6728   },
6729
6730   /* X86_64_63 */
6731   {
6732     { "arpl", { Ew, Gw }, 0 },
6733     { "movs", { { OP_G, movsxd_mode }, { MOVSXD_Fixup, movsxd_mode } }, 0 },
6734   },
6735
6736   /* X86_64_6D */
6737   {
6738     { "ins{R|}", { Yzr, indirDX }, 0 },
6739     { "ins{G|}", { Yzr, indirDX }, 0 },
6740   },
6741
6742   /* X86_64_6F */
6743   {
6744     { "outs{R|}", { indirDXr, Xz }, 0 },
6745     { "outs{G|}", { indirDXr, Xz }, 0 },
6746   },
6747
6748   /* X86_64_82 */
6749   {
6750     /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode.  */
6751     { REG_TABLE (REG_80) },
6752   },
6753
6754   /* X86_64_9A */
6755   {
6756     { "{l|}call{T|}", { Ap }, 0 },
6757   },
6758
6759   /* X86_64_C2 */
6760   {
6761     { "retP",           { Iw, BND }, 0 },
6762     { "ret@",           { Iw, BND }, 0 },
6763   },
6764
6765   /* X86_64_C3 */
6766   {
6767     { "retP",           { BND }, 0 },
6768     { "ret@",           { BND }, 0 },
6769   },
6770
6771   /* X86_64_C4 */
6772   {
6773     { MOD_TABLE (MOD_C4_32BIT) },
6774     { VEX_C4_TABLE (VEX_0F) },
6775   },
6776
6777   /* X86_64_C5 */
6778   {
6779     { MOD_TABLE (MOD_C5_32BIT) },
6780     { VEX_C5_TABLE (VEX_0F) },
6781   },
6782
6783   /* X86_64_CE */
6784   {
6785     { "into", { XX }, 0 },
6786   },
6787
6788   /* X86_64_D4 */
6789   {
6790     { "aam", { Ib }, 0 },
6791   },
6792
6793   /* X86_64_D5 */
6794   {
6795     { "aad", { Ib }, 0 },
6796   },
6797
6798   /* X86_64_E8 */
6799   {
6800     { "callP",          { Jv, BND }, 0 },
6801     { "call@",          { Jv, BND }, 0 }
6802   },
6803
6804   /* X86_64_E9 */
6805   {
6806     { "jmpP",           { Jv, BND }, 0 },
6807     { "jmp@",           { Jv, BND }, 0 }
6808   },
6809
6810   /* X86_64_EA */
6811   {
6812     { "{l|}jmp{T|}", { Ap }, 0 },
6813   },
6814
6815   /* X86_64_0F01_REG_0 */
6816   {
6817     { "sgdt{Q|Q}", { M }, 0 },
6818     { "sgdt", { M }, 0 },
6819   },
6820
6821   /* X86_64_0F01_REG_1 */
6822   {
6823     { "sidt{Q|Q}", { M }, 0 },
6824     { "sidt", { M }, 0 },
6825   },
6826
6827   /* X86_64_0F01_REG_2 */
6828   {
6829     { "lgdt{Q|Q}", { M }, 0 },
6830     { "lgdt", { M }, 0 },
6831   },
6832
6833   /* X86_64_0F01_REG_3 */
6834   {
6835     { "lidt{Q|Q}", { M }, 0 },
6836     { "lidt", { M }, 0 },
6837   },
6838 };
6839
6840 static const struct dis386 three_byte_table[][256] = {
6841
6842   /* THREE_BYTE_0F38 */
6843   {
6844     /* 00 */
6845     { "pshufb",         { MX, EM }, PREFIX_OPCODE },
6846     { "phaddw",         { MX, EM }, PREFIX_OPCODE },
6847     { "phaddd",         { MX, EM }, PREFIX_OPCODE },
6848     { "phaddsw",        { MX, EM }, PREFIX_OPCODE },
6849     { "pmaddubsw",      { MX, EM }, PREFIX_OPCODE },
6850     { "phsubw",         { MX, EM }, PREFIX_OPCODE },
6851     { "phsubd",         { MX, EM }, PREFIX_OPCODE },
6852     { "phsubsw",        { MX, EM }, PREFIX_OPCODE },
6853     /* 08 */
6854     { "psignb",         { MX, EM }, PREFIX_OPCODE },
6855     { "psignw",         { MX, EM }, PREFIX_OPCODE },
6856     { "psignd",         { MX, EM }, PREFIX_OPCODE },
6857     { "pmulhrsw",       { MX, EM }, PREFIX_OPCODE },
6858     { Bad_Opcode },
6859     { Bad_Opcode },
6860     { Bad_Opcode },
6861     { Bad_Opcode },
6862     /* 10 */
6863     { PREFIX_TABLE (PREFIX_0F3810) },
6864     { Bad_Opcode },
6865     { Bad_Opcode },
6866     { Bad_Opcode },
6867     { PREFIX_TABLE (PREFIX_0F3814) },
6868     { PREFIX_TABLE (PREFIX_0F3815) },
6869     { Bad_Opcode },
6870     { PREFIX_TABLE (PREFIX_0F3817) },
6871     /* 18 */
6872     { Bad_Opcode },
6873     { Bad_Opcode },
6874     { Bad_Opcode },
6875     { Bad_Opcode },
6876     { "pabsb",          { MX, EM }, PREFIX_OPCODE },
6877     { "pabsw",          { MX, EM }, PREFIX_OPCODE },
6878     { "pabsd",          { MX, EM }, PREFIX_OPCODE },
6879     { Bad_Opcode },
6880     /* 20 */
6881     { PREFIX_TABLE (PREFIX_0F3820) },
6882     { PREFIX_TABLE (PREFIX_0F3821) },
6883     { PREFIX_TABLE (PREFIX_0F3822) },
6884     { PREFIX_TABLE (PREFIX_0F3823) },
6885     { PREFIX_TABLE (PREFIX_0F3824) },
6886     { PREFIX_TABLE (PREFIX_0F3825) },
6887     { Bad_Opcode },
6888     { Bad_Opcode },
6889     /* 28 */
6890     { PREFIX_TABLE (PREFIX_0F3828) },
6891     { PREFIX_TABLE (PREFIX_0F3829) },
6892     { PREFIX_TABLE (PREFIX_0F382A) },
6893     { PREFIX_TABLE (PREFIX_0F382B) },
6894     { Bad_Opcode },
6895     { Bad_Opcode },
6896     { Bad_Opcode },
6897     { Bad_Opcode },
6898     /* 30 */
6899     { PREFIX_TABLE (PREFIX_0F3830) },
6900     { PREFIX_TABLE (PREFIX_0F3831) },
6901     { PREFIX_TABLE (PREFIX_0F3832) },
6902     { PREFIX_TABLE (PREFIX_0F3833) },
6903     { PREFIX_TABLE (PREFIX_0F3834) },
6904     { PREFIX_TABLE (PREFIX_0F3835) },
6905     { Bad_Opcode },
6906     { PREFIX_TABLE (PREFIX_0F3837) },
6907     /* 38 */
6908     { PREFIX_TABLE (PREFIX_0F3838) },
6909     { PREFIX_TABLE (PREFIX_0F3839) },
6910     { PREFIX_TABLE (PREFIX_0F383A) },
6911     { PREFIX_TABLE (PREFIX_0F383B) },
6912     { PREFIX_TABLE (PREFIX_0F383C) },
6913     { PREFIX_TABLE (PREFIX_0F383D) },
6914     { PREFIX_TABLE (PREFIX_0F383E) },
6915     { PREFIX_TABLE (PREFIX_0F383F) },
6916     /* 40 */
6917     { PREFIX_TABLE (PREFIX_0F3840) },
6918     { PREFIX_TABLE (PREFIX_0F3841) },
6919     { Bad_Opcode },
6920     { Bad_Opcode },
6921     { Bad_Opcode },
6922     { Bad_Opcode },
6923     { Bad_Opcode },
6924     { Bad_Opcode },
6925     /* 48 */
6926     { Bad_Opcode },
6927     { Bad_Opcode },
6928     { Bad_Opcode },
6929     { Bad_Opcode },
6930     { Bad_Opcode },
6931     { Bad_Opcode },
6932     { Bad_Opcode },
6933     { Bad_Opcode },
6934     /* 50 */
6935     { Bad_Opcode },
6936     { Bad_Opcode },
6937     { Bad_Opcode },
6938     { Bad_Opcode },
6939     { Bad_Opcode },
6940     { Bad_Opcode },
6941     { Bad_Opcode },
6942     { Bad_Opcode },
6943     /* 58 */
6944     { Bad_Opcode },
6945     { Bad_Opcode },
6946     { Bad_Opcode },
6947     { Bad_Opcode },
6948     { Bad_Opcode },
6949     { Bad_Opcode },
6950     { Bad_Opcode },
6951     { Bad_Opcode },
6952     /* 60 */
6953     { Bad_Opcode },
6954     { Bad_Opcode },
6955     { Bad_Opcode },
6956     { Bad_Opcode },
6957     { Bad_Opcode },
6958     { Bad_Opcode },
6959     { Bad_Opcode },
6960     { Bad_Opcode },
6961     /* 68 */
6962     { Bad_Opcode },
6963     { Bad_Opcode },
6964     { Bad_Opcode },
6965     { Bad_Opcode },
6966     { Bad_Opcode },
6967     { Bad_Opcode },
6968     { Bad_Opcode },
6969     { Bad_Opcode },
6970     /* 70 */
6971     { Bad_Opcode },
6972     { Bad_Opcode },
6973     { Bad_Opcode },
6974     { Bad_Opcode },
6975     { Bad_Opcode },
6976     { Bad_Opcode },
6977     { Bad_Opcode },
6978     { Bad_Opcode },
6979     /* 78 */
6980     { Bad_Opcode },
6981     { Bad_Opcode },
6982     { Bad_Opcode },
6983     { Bad_Opcode },
6984     { Bad_Opcode },
6985     { Bad_Opcode },
6986     { Bad_Opcode },
6987     { Bad_Opcode },
6988     /* 80 */
6989     { PREFIX_TABLE (PREFIX_0F3880) },
6990     { PREFIX_TABLE (PREFIX_0F3881) },
6991     { PREFIX_TABLE (PREFIX_0F3882) },
6992     { Bad_Opcode },
6993     { Bad_Opcode },
6994     { Bad_Opcode },
6995     { Bad_Opcode },
6996     { Bad_Opcode },
6997     /* 88 */
6998     { Bad_Opcode },
6999     { Bad_Opcode },
7000     { Bad_Opcode },
7001     { Bad_Opcode },
7002     { Bad_Opcode },
7003     { Bad_Opcode },
7004     { Bad_Opcode },
7005     { Bad_Opcode },
7006     /* 90 */
7007     { Bad_Opcode },
7008     { Bad_Opcode },
7009     { Bad_Opcode },
7010     { Bad_Opcode },
7011     { Bad_Opcode },
7012     { Bad_Opcode },
7013     { Bad_Opcode },
7014     { Bad_Opcode },
7015     /* 98 */
7016     { Bad_Opcode },
7017     { Bad_Opcode },
7018     { Bad_Opcode },
7019     { Bad_Opcode },
7020     { Bad_Opcode },
7021     { Bad_Opcode },
7022     { Bad_Opcode },
7023     { Bad_Opcode },
7024     /* a0 */
7025     { Bad_Opcode },
7026     { Bad_Opcode },
7027     { Bad_Opcode },
7028     { Bad_Opcode },
7029     { Bad_Opcode },
7030     { Bad_Opcode },
7031     { Bad_Opcode },
7032     { Bad_Opcode },
7033     /* a8 */
7034     { Bad_Opcode },
7035     { Bad_Opcode },
7036     { Bad_Opcode },
7037     { Bad_Opcode },
7038     { Bad_Opcode },
7039     { Bad_Opcode },
7040     { Bad_Opcode },
7041     { Bad_Opcode },
7042     /* b0 */
7043     { Bad_Opcode },
7044     { Bad_Opcode },
7045     { Bad_Opcode },
7046     { Bad_Opcode },
7047     { Bad_Opcode },
7048     { Bad_Opcode },
7049     { Bad_Opcode },
7050     { Bad_Opcode },
7051     /* b8 */
7052     { Bad_Opcode },
7053     { Bad_Opcode },
7054     { Bad_Opcode },
7055     { Bad_Opcode },
7056     { Bad_Opcode },
7057     { Bad_Opcode },
7058     { Bad_Opcode },
7059     { Bad_Opcode },
7060     /* c0 */
7061     { Bad_Opcode },
7062     { Bad_Opcode },
7063     { Bad_Opcode },
7064     { Bad_Opcode },
7065     { Bad_Opcode },
7066     { Bad_Opcode },
7067     { Bad_Opcode },
7068     { Bad_Opcode },
7069     /* c8 */
7070     { PREFIX_TABLE (PREFIX_0F38C8) },
7071     { PREFIX_TABLE (PREFIX_0F38C9) },
7072     { PREFIX_TABLE (PREFIX_0F38CA) },
7073     { PREFIX_TABLE (PREFIX_0F38CB) },
7074     { PREFIX_TABLE (PREFIX_0F38CC) },
7075     { PREFIX_TABLE (PREFIX_0F38CD) },
7076     { Bad_Opcode },
7077     { PREFIX_TABLE (PREFIX_0F38CF) },
7078     /* d0 */
7079     { Bad_Opcode },
7080     { Bad_Opcode },
7081     { Bad_Opcode },
7082     { Bad_Opcode },
7083     { Bad_Opcode },
7084     { Bad_Opcode },
7085     { Bad_Opcode },
7086     { Bad_Opcode },
7087     /* d8 */
7088     { Bad_Opcode },
7089     { Bad_Opcode },
7090     { Bad_Opcode },
7091     { PREFIX_TABLE (PREFIX_0F38DB) },
7092     { PREFIX_TABLE (PREFIX_0F38DC) },
7093     { PREFIX_TABLE (PREFIX_0F38DD) },
7094     { PREFIX_TABLE (PREFIX_0F38DE) },
7095     { PREFIX_TABLE (PREFIX_0F38DF) },
7096     /* e0 */
7097     { Bad_Opcode },
7098     { Bad_Opcode },
7099     { Bad_Opcode },
7100     { Bad_Opcode },
7101     { Bad_Opcode },
7102     { Bad_Opcode },
7103     { Bad_Opcode },
7104     { Bad_Opcode },
7105     /* e8 */
7106     { Bad_Opcode },
7107     { Bad_Opcode },
7108     { Bad_Opcode },
7109     { Bad_Opcode },
7110     { Bad_Opcode },
7111     { Bad_Opcode },
7112     { Bad_Opcode },
7113     { Bad_Opcode },
7114     /* f0 */
7115     { PREFIX_TABLE (PREFIX_0F38F0) },
7116     { PREFIX_TABLE (PREFIX_0F38F1) },
7117     { Bad_Opcode },
7118     { Bad_Opcode },
7119     { Bad_Opcode },
7120     { PREFIX_TABLE (PREFIX_0F38F5) },
7121     { PREFIX_TABLE (PREFIX_0F38F6) },
7122     { Bad_Opcode },
7123     /* f8 */
7124     { PREFIX_TABLE (PREFIX_0F38F8) },
7125     { PREFIX_TABLE (PREFIX_0F38F9) },
7126     { Bad_Opcode },
7127     { Bad_Opcode },
7128     { Bad_Opcode },
7129     { Bad_Opcode },
7130     { Bad_Opcode },
7131     { Bad_Opcode },
7132   },
7133   /* THREE_BYTE_0F3A */
7134   {
7135     /* 00 */
7136     { Bad_Opcode },
7137     { Bad_Opcode },
7138     { Bad_Opcode },
7139     { Bad_Opcode },
7140     { Bad_Opcode },
7141     { Bad_Opcode },
7142     { Bad_Opcode },
7143     { Bad_Opcode },
7144     /* 08 */
7145     { PREFIX_TABLE (PREFIX_0F3A08) },
7146     { PREFIX_TABLE (PREFIX_0F3A09) },
7147     { PREFIX_TABLE (PREFIX_0F3A0A) },
7148     { PREFIX_TABLE (PREFIX_0F3A0B) },
7149     { PREFIX_TABLE (PREFIX_0F3A0C) },
7150     { PREFIX_TABLE (PREFIX_0F3A0D) },
7151     { PREFIX_TABLE (PREFIX_0F3A0E) },
7152     { "palignr",        { MX, EM, Ib }, PREFIX_OPCODE },
7153     /* 10 */
7154     { Bad_Opcode },
7155     { Bad_Opcode },
7156     { Bad_Opcode },
7157     { Bad_Opcode },
7158     { PREFIX_TABLE (PREFIX_0F3A14) },
7159     { PREFIX_TABLE (PREFIX_0F3A15) },
7160     { PREFIX_TABLE (PREFIX_0F3A16) },
7161     { PREFIX_TABLE (PREFIX_0F3A17) },
7162     /* 18 */
7163     { Bad_Opcode },
7164     { Bad_Opcode },
7165     { Bad_Opcode },
7166     { Bad_Opcode },
7167     { Bad_Opcode },
7168     { Bad_Opcode },
7169     { Bad_Opcode },
7170     { Bad_Opcode },
7171     /* 20 */
7172     { PREFIX_TABLE (PREFIX_0F3A20) },
7173     { PREFIX_TABLE (PREFIX_0F3A21) },
7174     { PREFIX_TABLE (PREFIX_0F3A22) },
7175     { Bad_Opcode },
7176     { Bad_Opcode },
7177     { Bad_Opcode },
7178     { Bad_Opcode },
7179     { Bad_Opcode },
7180     /* 28 */
7181     { Bad_Opcode },
7182     { Bad_Opcode },
7183     { Bad_Opcode },
7184     { Bad_Opcode },
7185     { Bad_Opcode },
7186     { Bad_Opcode },
7187     { Bad_Opcode },
7188     { Bad_Opcode },
7189     /* 30 */
7190     { Bad_Opcode },
7191     { Bad_Opcode },
7192     { Bad_Opcode },
7193     { Bad_Opcode },
7194     { Bad_Opcode },
7195     { Bad_Opcode },
7196     { Bad_Opcode },
7197     { Bad_Opcode },
7198     /* 38 */
7199     { Bad_Opcode },
7200     { Bad_Opcode },
7201     { Bad_Opcode },
7202     { Bad_Opcode },
7203     { Bad_Opcode },
7204     { Bad_Opcode },
7205     { Bad_Opcode },
7206     { Bad_Opcode },
7207     /* 40 */
7208     { PREFIX_TABLE (PREFIX_0F3A40) },
7209     { PREFIX_TABLE (PREFIX_0F3A41) },
7210     { PREFIX_TABLE (PREFIX_0F3A42) },
7211     { Bad_Opcode },
7212     { PREFIX_TABLE (PREFIX_0F3A44) },
7213     { Bad_Opcode },
7214     { Bad_Opcode },
7215     { Bad_Opcode },
7216     /* 48 */
7217     { Bad_Opcode },
7218     { Bad_Opcode },
7219     { Bad_Opcode },
7220     { Bad_Opcode },
7221     { Bad_Opcode },
7222     { Bad_Opcode },
7223     { Bad_Opcode },
7224     { Bad_Opcode },
7225     /* 50 */
7226     { Bad_Opcode },
7227     { Bad_Opcode },
7228     { Bad_Opcode },
7229     { Bad_Opcode },
7230     { Bad_Opcode },
7231     { Bad_Opcode },
7232     { Bad_Opcode },
7233     { Bad_Opcode },
7234     /* 58 */
7235     { Bad_Opcode },
7236     { Bad_Opcode },
7237     { Bad_Opcode },
7238     { Bad_Opcode },
7239     { Bad_Opcode },
7240     { Bad_Opcode },
7241     { Bad_Opcode },
7242     { Bad_Opcode },
7243     /* 60 */
7244     { PREFIX_TABLE (PREFIX_0F3A60) },
7245     { PREFIX_TABLE (PREFIX_0F3A61) },
7246     { PREFIX_TABLE (PREFIX_0F3A62) },
7247     { PREFIX_TABLE (PREFIX_0F3A63) },
7248     { Bad_Opcode },
7249     { Bad_Opcode },
7250     { Bad_Opcode },
7251     { Bad_Opcode },
7252     /* 68 */
7253     { Bad_Opcode },
7254     { Bad_Opcode },
7255     { Bad_Opcode },
7256     { Bad_Opcode },
7257     { Bad_Opcode },
7258     { Bad_Opcode },
7259     { Bad_Opcode },
7260     { Bad_Opcode },
7261     /* 70 */
7262     { Bad_Opcode },
7263     { Bad_Opcode },
7264     { Bad_Opcode },
7265     { Bad_Opcode },
7266     { Bad_Opcode },
7267     { Bad_Opcode },
7268     { Bad_Opcode },
7269     { Bad_Opcode },
7270     /* 78 */
7271     { Bad_Opcode },
7272     { Bad_Opcode },
7273     { Bad_Opcode },
7274     { Bad_Opcode },
7275     { Bad_Opcode },
7276     { Bad_Opcode },
7277     { Bad_Opcode },
7278     { Bad_Opcode },
7279     /* 80 */
7280     { Bad_Opcode },
7281     { Bad_Opcode },
7282     { Bad_Opcode },
7283     { Bad_Opcode },
7284     { Bad_Opcode },
7285     { Bad_Opcode },
7286     { Bad_Opcode },
7287     { Bad_Opcode },
7288     /* 88 */
7289     { Bad_Opcode },
7290     { Bad_Opcode },
7291     { Bad_Opcode },
7292     { Bad_Opcode },
7293     { Bad_Opcode },
7294     { Bad_Opcode },
7295     { Bad_Opcode },
7296     { Bad_Opcode },
7297     /* 90 */
7298     { Bad_Opcode },
7299     { Bad_Opcode },
7300     { Bad_Opcode },
7301     { Bad_Opcode },
7302     { Bad_Opcode },
7303     { Bad_Opcode },
7304     { Bad_Opcode },
7305     { Bad_Opcode },
7306     /* 98 */
7307     { Bad_Opcode },
7308     { Bad_Opcode },
7309     { Bad_Opcode },
7310     { Bad_Opcode },
7311     { Bad_Opcode },
7312     { Bad_Opcode },
7313     { Bad_Opcode },
7314     { Bad_Opcode },
7315     /* a0 */
7316     { Bad_Opcode },
7317     { Bad_Opcode },
7318     { Bad_Opcode },
7319     { Bad_Opcode },
7320     { Bad_Opcode },
7321     { Bad_Opcode },
7322     { Bad_Opcode },
7323     { Bad_Opcode },
7324     /* a8 */
7325     { Bad_Opcode },
7326     { Bad_Opcode },
7327     { Bad_Opcode },
7328     { Bad_Opcode },
7329     { Bad_Opcode },
7330     { Bad_Opcode },
7331     { Bad_Opcode },
7332     { Bad_Opcode },
7333     /* b0 */
7334     { Bad_Opcode },
7335     { Bad_Opcode },
7336     { Bad_Opcode },
7337     { Bad_Opcode },
7338     { Bad_Opcode },
7339     { Bad_Opcode },
7340     { Bad_Opcode },
7341     { Bad_Opcode },
7342     /* b8 */
7343     { Bad_Opcode },
7344     { Bad_Opcode },
7345     { Bad_Opcode },
7346     { Bad_Opcode },
7347     { Bad_Opcode },
7348     { Bad_Opcode },
7349     { Bad_Opcode },
7350     { Bad_Opcode },
7351     /* c0 */
7352     { Bad_Opcode },
7353     { Bad_Opcode },
7354     { Bad_Opcode },
7355     { Bad_Opcode },
7356     { Bad_Opcode },
7357     { Bad_Opcode },
7358     { Bad_Opcode },
7359     { Bad_Opcode },
7360     /* c8 */
7361     { Bad_Opcode },
7362     { Bad_Opcode },
7363     { Bad_Opcode },
7364     { Bad_Opcode },
7365     { PREFIX_TABLE (PREFIX_0F3ACC) },
7366     { Bad_Opcode },
7367     { PREFIX_TABLE (PREFIX_0F3ACE) },
7368     { PREFIX_TABLE (PREFIX_0F3ACF) },
7369     /* d0 */
7370     { Bad_Opcode },
7371     { Bad_Opcode },
7372     { Bad_Opcode },
7373     { Bad_Opcode },
7374     { Bad_Opcode },
7375     { Bad_Opcode },
7376     { Bad_Opcode },
7377     { Bad_Opcode },
7378     /* d8 */
7379     { Bad_Opcode },
7380     { Bad_Opcode },
7381     { Bad_Opcode },
7382     { Bad_Opcode },
7383     { Bad_Opcode },
7384     { Bad_Opcode },
7385     { Bad_Opcode },
7386     { PREFIX_TABLE (PREFIX_0F3ADF) },
7387     /* e0 */
7388     { Bad_Opcode },
7389     { Bad_Opcode },
7390     { Bad_Opcode },
7391     { Bad_Opcode },
7392     { Bad_Opcode },
7393     { Bad_Opcode },
7394     { Bad_Opcode },
7395     { Bad_Opcode },
7396     /* e8 */
7397     { Bad_Opcode },
7398     { Bad_Opcode },
7399     { Bad_Opcode },
7400     { Bad_Opcode },
7401     { Bad_Opcode },
7402     { Bad_Opcode },
7403     { Bad_Opcode },
7404     { Bad_Opcode },
7405     /* f0 */
7406     { Bad_Opcode },
7407     { Bad_Opcode },
7408     { Bad_Opcode },
7409     { Bad_Opcode },
7410     { Bad_Opcode },
7411     { Bad_Opcode },
7412     { Bad_Opcode },
7413     { Bad_Opcode },
7414     /* f8 */
7415     { Bad_Opcode },
7416     { Bad_Opcode },
7417     { Bad_Opcode },
7418     { Bad_Opcode },
7419     { Bad_Opcode },
7420     { Bad_Opcode },
7421     { Bad_Opcode },
7422     { Bad_Opcode },
7423   },
7424 };
7425
7426 static const struct dis386 xop_table[][256] = {
7427   /* XOP_08 */
7428   {
7429     /* 00 */
7430     { Bad_Opcode },
7431     { Bad_Opcode },
7432     { Bad_Opcode },
7433     { Bad_Opcode },
7434     { Bad_Opcode },
7435     { Bad_Opcode },
7436     { Bad_Opcode },
7437     { Bad_Opcode },
7438     /* 08 */
7439     { Bad_Opcode },
7440     { Bad_Opcode },
7441     { Bad_Opcode },
7442     { Bad_Opcode },
7443     { Bad_Opcode },
7444     { Bad_Opcode },
7445     { Bad_Opcode },
7446     { Bad_Opcode },
7447     /* 10 */
7448     { Bad_Opcode },
7449     { Bad_Opcode },
7450     { Bad_Opcode },
7451     { Bad_Opcode },
7452     { Bad_Opcode },
7453     { Bad_Opcode },
7454     { Bad_Opcode },
7455     { Bad_Opcode },
7456     /* 18 */
7457     { Bad_Opcode },
7458     { Bad_Opcode },
7459     { Bad_Opcode },
7460     { Bad_Opcode },
7461     { Bad_Opcode },
7462     { Bad_Opcode },
7463     { Bad_Opcode },
7464     { Bad_Opcode },
7465     /* 20 */
7466     { Bad_Opcode },
7467     { Bad_Opcode },
7468     { Bad_Opcode },
7469     { Bad_Opcode },
7470     { Bad_Opcode },
7471     { Bad_Opcode },
7472     { Bad_Opcode },
7473     { Bad_Opcode },
7474     /* 28 */
7475     { Bad_Opcode },
7476     { Bad_Opcode },
7477     { Bad_Opcode },
7478     { Bad_Opcode },
7479     { Bad_Opcode },
7480     { Bad_Opcode },
7481     { Bad_Opcode },
7482     { Bad_Opcode },
7483     /* 30 */
7484     { Bad_Opcode },
7485     { Bad_Opcode },
7486     { Bad_Opcode },
7487     { Bad_Opcode },
7488     { Bad_Opcode },
7489     { Bad_Opcode },
7490     { Bad_Opcode },
7491     { Bad_Opcode },
7492     /* 38 */
7493     { Bad_Opcode },
7494     { Bad_Opcode },
7495     { Bad_Opcode },
7496     { Bad_Opcode },
7497     { Bad_Opcode },
7498     { Bad_Opcode },
7499     { Bad_Opcode },
7500     { Bad_Opcode },
7501     /* 40 */
7502     { Bad_Opcode },
7503     { Bad_Opcode },
7504     { Bad_Opcode },
7505     { Bad_Opcode },
7506     { Bad_Opcode },
7507     { Bad_Opcode },
7508     { Bad_Opcode },
7509     { Bad_Opcode },
7510     /* 48 */
7511     { Bad_Opcode },
7512     { Bad_Opcode },
7513     { Bad_Opcode },
7514     { Bad_Opcode },
7515     { Bad_Opcode },
7516     { Bad_Opcode },
7517     { Bad_Opcode },
7518     { Bad_Opcode },
7519     /* 50 */
7520     { Bad_Opcode },
7521     { Bad_Opcode },
7522     { Bad_Opcode },
7523     { Bad_Opcode },
7524     { Bad_Opcode },
7525     { Bad_Opcode },
7526     { Bad_Opcode },
7527     { Bad_Opcode },
7528     /* 58 */
7529     { Bad_Opcode },
7530     { Bad_Opcode },
7531     { Bad_Opcode },
7532     { Bad_Opcode },
7533     { Bad_Opcode },
7534     { Bad_Opcode },
7535     { Bad_Opcode },
7536     { Bad_Opcode },
7537     /* 60 */
7538     { Bad_Opcode },
7539     { Bad_Opcode },
7540     { Bad_Opcode },
7541     { Bad_Opcode },
7542     { Bad_Opcode },
7543     { Bad_Opcode },
7544     { Bad_Opcode },
7545     { Bad_Opcode },
7546     /* 68 */
7547     { Bad_Opcode },
7548     { Bad_Opcode },
7549     { Bad_Opcode },
7550     { Bad_Opcode },
7551     { Bad_Opcode },
7552     { Bad_Opcode },
7553     { Bad_Opcode },
7554     { Bad_Opcode },
7555     /* 70 */
7556     { Bad_Opcode },
7557     { Bad_Opcode },
7558     { Bad_Opcode },
7559     { Bad_Opcode },
7560     { Bad_Opcode },
7561     { Bad_Opcode },
7562     { Bad_Opcode },
7563     { Bad_Opcode },
7564     /* 78 */
7565     { Bad_Opcode },
7566     { Bad_Opcode },
7567     { Bad_Opcode },
7568     { Bad_Opcode },
7569     { Bad_Opcode },
7570     { Bad_Opcode },
7571     { Bad_Opcode },
7572     { Bad_Opcode },
7573     /* 80 */
7574     { Bad_Opcode },
7575     { Bad_Opcode },
7576     { Bad_Opcode },
7577     { Bad_Opcode },
7578     { Bad_Opcode },
7579     { "vpmacssww",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7580     { "vpmacsswd",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7581     { "vpmacssdql",     { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7582     /* 88 */
7583     { Bad_Opcode },
7584     { Bad_Opcode },
7585     { Bad_Opcode },
7586     { Bad_Opcode },
7587     { Bad_Opcode },
7588     { Bad_Opcode },
7589     { "vpmacssdd",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7590     { "vpmacssdqh",     { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7591     /* 90 */
7592     { Bad_Opcode },
7593     { Bad_Opcode },
7594     { Bad_Opcode },
7595     { Bad_Opcode },
7596     { Bad_Opcode },
7597     { "vpmacsww",       { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7598     { "vpmacswd",       { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7599     { "vpmacsdql",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7600     /* 98 */
7601     { Bad_Opcode },
7602     { Bad_Opcode },
7603     { Bad_Opcode },
7604     { Bad_Opcode },
7605     { Bad_Opcode },
7606     { Bad_Opcode },
7607     { "vpmacsdd",       { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7608     { "vpmacsdqh",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7609     /* a0 */
7610     { Bad_Opcode },
7611     { Bad_Opcode },
7612     { "vpcmov",         { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7613     { "vpperm",         { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7614     { Bad_Opcode },
7615     { Bad_Opcode },
7616     { "vpmadcsswd",     { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7617     { Bad_Opcode },
7618     /* a8 */
7619     { Bad_Opcode },
7620     { Bad_Opcode },
7621     { Bad_Opcode },
7622     { Bad_Opcode },
7623     { Bad_Opcode },
7624     { Bad_Opcode },
7625     { Bad_Opcode },
7626     { Bad_Opcode },
7627     /* b0 */
7628     { Bad_Opcode },
7629     { Bad_Opcode },
7630     { Bad_Opcode },
7631     { Bad_Opcode },
7632     { Bad_Opcode },
7633     { Bad_Opcode },
7634     { "vpmadcswd",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7635     { Bad_Opcode },
7636     /* b8 */
7637     { Bad_Opcode },
7638     { Bad_Opcode },
7639     { Bad_Opcode },
7640     { Bad_Opcode },
7641     { Bad_Opcode },
7642     { Bad_Opcode },
7643     { Bad_Opcode },
7644     { Bad_Opcode },
7645     /* c0 */
7646     { "vprotb",         { XM, Vex_2src_1, Ib }, 0 },
7647     { "vprotw",         { XM, Vex_2src_1, Ib }, 0 },
7648     { "vprotd",         { XM, Vex_2src_1, Ib }, 0 },
7649     { "vprotq",         { XM, Vex_2src_1, Ib }, 0 },
7650     { Bad_Opcode },
7651     { Bad_Opcode },
7652     { Bad_Opcode },
7653     { Bad_Opcode },
7654     /* c8 */
7655     { Bad_Opcode },
7656     { Bad_Opcode },
7657     { Bad_Opcode },
7658     { Bad_Opcode },
7659     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
7660     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
7661     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
7662     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
7663     /* d0 */
7664     { Bad_Opcode },
7665     { Bad_Opcode },
7666     { Bad_Opcode },
7667     { Bad_Opcode },
7668     { Bad_Opcode },
7669     { Bad_Opcode },
7670     { Bad_Opcode },
7671     { Bad_Opcode },
7672     /* d8 */
7673     { Bad_Opcode },
7674     { Bad_Opcode },
7675     { Bad_Opcode },
7676     { Bad_Opcode },
7677     { Bad_Opcode },
7678     { Bad_Opcode },
7679     { Bad_Opcode },
7680     { Bad_Opcode },
7681     /* e0 */
7682     { Bad_Opcode },
7683     { Bad_Opcode },
7684     { Bad_Opcode },
7685     { Bad_Opcode },
7686     { Bad_Opcode },
7687     { Bad_Opcode },
7688     { Bad_Opcode },
7689     { Bad_Opcode },
7690     /* e8 */
7691     { Bad_Opcode },
7692     { Bad_Opcode },
7693     { Bad_Opcode },
7694     { Bad_Opcode },
7695     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
7696     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
7697     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
7698     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
7699     /* f0 */
7700     { Bad_Opcode },
7701     { Bad_Opcode },
7702     { Bad_Opcode },
7703     { Bad_Opcode },
7704     { Bad_Opcode },
7705     { Bad_Opcode },
7706     { Bad_Opcode },
7707     { Bad_Opcode },
7708     /* f8 */
7709     { Bad_Opcode },
7710     { Bad_Opcode },
7711     { Bad_Opcode },
7712     { Bad_Opcode },
7713     { Bad_Opcode },
7714     { Bad_Opcode },
7715     { Bad_Opcode },
7716     { Bad_Opcode },
7717   },
7718   /* XOP_09 */
7719   {
7720     /* 00 */
7721     { Bad_Opcode },
7722     { REG_TABLE (REG_XOP_TBM_01) },
7723     { REG_TABLE (REG_XOP_TBM_02) },
7724     { Bad_Opcode },
7725     { Bad_Opcode },
7726     { Bad_Opcode },
7727     { Bad_Opcode },
7728     { Bad_Opcode },
7729     /* 08 */
7730     { Bad_Opcode },
7731     { Bad_Opcode },
7732     { Bad_Opcode },
7733     { Bad_Opcode },
7734     { Bad_Opcode },
7735     { Bad_Opcode },
7736     { Bad_Opcode },
7737     { Bad_Opcode },
7738     /* 10 */
7739     { Bad_Opcode },
7740     { Bad_Opcode },
7741     { REG_TABLE (REG_XOP_LWPCB) },
7742     { Bad_Opcode },
7743     { Bad_Opcode },
7744     { Bad_Opcode },
7745     { Bad_Opcode },
7746     { Bad_Opcode },
7747     /* 18 */
7748     { Bad_Opcode },
7749     { Bad_Opcode },
7750     { Bad_Opcode },
7751     { Bad_Opcode },
7752     { Bad_Opcode },
7753     { Bad_Opcode },
7754     { Bad_Opcode },
7755     { Bad_Opcode },
7756     /* 20 */
7757     { Bad_Opcode },
7758     { Bad_Opcode },
7759     { Bad_Opcode },
7760     { Bad_Opcode },
7761     { Bad_Opcode },
7762     { Bad_Opcode },
7763     { Bad_Opcode },
7764     { Bad_Opcode },
7765     /* 28 */
7766     { Bad_Opcode },
7767     { Bad_Opcode },
7768     { Bad_Opcode },
7769     { Bad_Opcode },
7770     { Bad_Opcode },
7771     { Bad_Opcode },
7772     { Bad_Opcode },
7773     { Bad_Opcode },
7774     /* 30 */
7775     { Bad_Opcode },
7776     { Bad_Opcode },
7777     { Bad_Opcode },
7778     { Bad_Opcode },
7779     { Bad_Opcode },
7780     { Bad_Opcode },
7781     { Bad_Opcode },
7782     { Bad_Opcode },
7783     /* 38 */
7784     { Bad_Opcode },
7785     { Bad_Opcode },
7786     { Bad_Opcode },
7787     { Bad_Opcode },
7788     { Bad_Opcode },
7789     { Bad_Opcode },
7790     { Bad_Opcode },
7791     { Bad_Opcode },
7792     /* 40 */
7793     { Bad_Opcode },
7794     { Bad_Opcode },
7795     { Bad_Opcode },
7796     { Bad_Opcode },
7797     { Bad_Opcode },
7798     { Bad_Opcode },
7799     { Bad_Opcode },
7800     { Bad_Opcode },
7801     /* 48 */
7802     { Bad_Opcode },
7803     { Bad_Opcode },
7804     { Bad_Opcode },
7805     { Bad_Opcode },
7806     { Bad_Opcode },
7807     { Bad_Opcode },
7808     { Bad_Opcode },
7809     { Bad_Opcode },
7810     /* 50 */
7811     { Bad_Opcode },
7812     { Bad_Opcode },
7813     { Bad_Opcode },
7814     { Bad_Opcode },
7815     { Bad_Opcode },
7816     { Bad_Opcode },
7817     { Bad_Opcode },
7818     { Bad_Opcode },
7819     /* 58 */
7820     { Bad_Opcode },
7821     { Bad_Opcode },
7822     { Bad_Opcode },
7823     { Bad_Opcode },
7824     { Bad_Opcode },
7825     { Bad_Opcode },
7826     { Bad_Opcode },
7827     { Bad_Opcode },
7828     /* 60 */
7829     { Bad_Opcode },
7830     { Bad_Opcode },
7831     { Bad_Opcode },
7832     { Bad_Opcode },
7833     { Bad_Opcode },
7834     { Bad_Opcode },
7835     { Bad_Opcode },
7836     { Bad_Opcode },
7837     /* 68 */
7838     { Bad_Opcode },
7839     { Bad_Opcode },
7840     { Bad_Opcode },
7841     { Bad_Opcode },
7842     { Bad_Opcode },
7843     { Bad_Opcode },
7844     { Bad_Opcode },
7845     { Bad_Opcode },
7846     /* 70 */
7847     { Bad_Opcode },
7848     { Bad_Opcode },
7849     { Bad_Opcode },
7850     { Bad_Opcode },
7851     { Bad_Opcode },
7852     { Bad_Opcode },
7853     { Bad_Opcode },
7854     { Bad_Opcode },
7855     /* 78 */
7856     { Bad_Opcode },
7857     { Bad_Opcode },
7858     { Bad_Opcode },
7859     { Bad_Opcode },
7860     { Bad_Opcode },
7861     { Bad_Opcode },
7862     { Bad_Opcode },
7863     { Bad_Opcode },
7864     /* 80 */
7865     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) },
7866     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) },
7867     { "vfrczss",        { XM, EXd }, 0 },
7868     { "vfrczsd",        { XM, EXq }, 0 },
7869     { Bad_Opcode },
7870     { Bad_Opcode },
7871     { Bad_Opcode },
7872     { Bad_Opcode },
7873     /* 88 */
7874     { Bad_Opcode },
7875     { Bad_Opcode },
7876     { Bad_Opcode },
7877     { Bad_Opcode },
7878     { Bad_Opcode },
7879     { Bad_Opcode },
7880     { Bad_Opcode },
7881     { Bad_Opcode },
7882     /* 90 */
7883     { "vprotb",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7884     { "vprotw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7885     { "vprotd",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7886     { "vprotq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7887     { "vpshlb",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7888     { "vpshlw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7889     { "vpshld",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7890     { "vpshlq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7891     /* 98 */
7892     { "vpshab",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7893     { "vpshaw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7894     { "vpshad",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7895     { "vpshaq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7896     { Bad_Opcode },
7897     { Bad_Opcode },
7898     { Bad_Opcode },
7899     { Bad_Opcode },
7900     /* a0 */
7901     { Bad_Opcode },
7902     { Bad_Opcode },
7903     { Bad_Opcode },
7904     { Bad_Opcode },
7905     { Bad_Opcode },
7906     { Bad_Opcode },
7907     { Bad_Opcode },
7908     { Bad_Opcode },
7909     /* a8 */
7910     { Bad_Opcode },
7911     { Bad_Opcode },
7912     { Bad_Opcode },
7913     { Bad_Opcode },
7914     { Bad_Opcode },
7915     { Bad_Opcode },
7916     { Bad_Opcode },
7917     { Bad_Opcode },
7918     /* b0 */
7919     { Bad_Opcode },
7920     { Bad_Opcode },
7921     { Bad_Opcode },
7922     { Bad_Opcode },
7923     { Bad_Opcode },
7924     { Bad_Opcode },
7925     { Bad_Opcode },
7926     { Bad_Opcode },
7927     /* b8 */
7928     { Bad_Opcode },
7929     { Bad_Opcode },
7930     { Bad_Opcode },
7931     { Bad_Opcode },
7932     { Bad_Opcode },
7933     { Bad_Opcode },
7934     { Bad_Opcode },
7935     { Bad_Opcode },
7936     /* c0 */
7937     { Bad_Opcode },
7938     { "vphaddbw",       { XM, EXxmm }, 0 },
7939     { "vphaddbd",       { XM, EXxmm }, 0 },
7940     { "vphaddbq",       { XM, EXxmm }, 0 },
7941     { Bad_Opcode },
7942     { Bad_Opcode },
7943     { "vphaddwd",       { XM, EXxmm }, 0 },
7944     { "vphaddwq",       { XM, EXxmm }, 0 },
7945     /* c8 */
7946     { Bad_Opcode },
7947     { Bad_Opcode },
7948     { Bad_Opcode },
7949     { "vphadddq",       { XM, EXxmm }, 0 },
7950     { Bad_Opcode },
7951     { Bad_Opcode },
7952     { Bad_Opcode },
7953     { Bad_Opcode },
7954     /* d0 */
7955     { Bad_Opcode },
7956     { "vphaddubw",      { XM, EXxmm }, 0 },
7957     { "vphaddubd",      { XM, EXxmm }, 0 },
7958     { "vphaddubq",      { XM, EXxmm }, 0 },
7959     { Bad_Opcode },
7960     { Bad_Opcode },
7961     { "vphadduwd",      { XM, EXxmm }, 0 },
7962     { "vphadduwq",      { XM, EXxmm }, 0 },
7963     /* d8 */
7964     { Bad_Opcode },
7965     { Bad_Opcode },
7966     { Bad_Opcode },
7967     { "vphaddudq",      { XM, EXxmm }, 0 },
7968     { Bad_Opcode },
7969     { Bad_Opcode },
7970     { Bad_Opcode },
7971     { Bad_Opcode },
7972     /* e0 */
7973     { Bad_Opcode },
7974     { "vphsubbw",       { XM, EXxmm }, 0 },
7975     { "vphsubwd",       { XM, EXxmm }, 0 },
7976     { "vphsubdq",       { XM, EXxmm }, 0 },
7977     { Bad_Opcode },
7978     { Bad_Opcode },
7979     { Bad_Opcode },
7980     { Bad_Opcode },
7981     /* e8 */
7982     { Bad_Opcode },
7983     { Bad_Opcode },
7984     { Bad_Opcode },
7985     { Bad_Opcode },
7986     { Bad_Opcode },
7987     { Bad_Opcode },
7988     { Bad_Opcode },
7989     { Bad_Opcode },
7990     /* f0 */
7991     { Bad_Opcode },
7992     { Bad_Opcode },
7993     { Bad_Opcode },
7994     { Bad_Opcode },
7995     { Bad_Opcode },
7996     { Bad_Opcode },
7997     { Bad_Opcode },
7998     { Bad_Opcode },
7999     /* f8 */
8000     { Bad_Opcode },
8001     { Bad_Opcode },
8002     { Bad_Opcode },
8003     { Bad_Opcode },
8004     { Bad_Opcode },
8005     { Bad_Opcode },
8006     { Bad_Opcode },
8007     { Bad_Opcode },
8008   },
8009   /* XOP_0A */
8010   {
8011     /* 00 */
8012     { Bad_Opcode },
8013     { Bad_Opcode },
8014     { Bad_Opcode },
8015     { Bad_Opcode },
8016     { Bad_Opcode },
8017     { Bad_Opcode },
8018     { Bad_Opcode },
8019     { Bad_Opcode },
8020     /* 08 */
8021     { Bad_Opcode },
8022     { Bad_Opcode },
8023     { Bad_Opcode },
8024     { Bad_Opcode },
8025     { Bad_Opcode },
8026     { Bad_Opcode },
8027     { Bad_Opcode },
8028     { Bad_Opcode },
8029     /* 10 */
8030     { "bextrS", { Gdq, Edq, Id }, 0 },
8031     { Bad_Opcode },
8032     { REG_TABLE (REG_XOP_LWP) },
8033     { Bad_Opcode },
8034     { Bad_Opcode },
8035     { Bad_Opcode },
8036     { Bad_Opcode },
8037     { Bad_Opcode },
8038     /* 18 */
8039     { Bad_Opcode },
8040     { Bad_Opcode },
8041     { Bad_Opcode },
8042     { Bad_Opcode },
8043     { Bad_Opcode },
8044     { Bad_Opcode },
8045     { Bad_Opcode },
8046     { Bad_Opcode },
8047     /* 20 */
8048     { Bad_Opcode },
8049     { Bad_Opcode },
8050     { Bad_Opcode },
8051     { Bad_Opcode },
8052     { Bad_Opcode },
8053     { Bad_Opcode },
8054     { Bad_Opcode },
8055     { Bad_Opcode },
8056     /* 28 */
8057     { Bad_Opcode },
8058     { Bad_Opcode },
8059     { Bad_Opcode },
8060     { Bad_Opcode },
8061     { Bad_Opcode },
8062     { Bad_Opcode },
8063     { Bad_Opcode },
8064     { Bad_Opcode },
8065     /* 30 */
8066     { Bad_Opcode },
8067     { Bad_Opcode },
8068     { Bad_Opcode },
8069     { Bad_Opcode },
8070     { Bad_Opcode },
8071     { Bad_Opcode },
8072     { Bad_Opcode },
8073     { Bad_Opcode },
8074     /* 38 */
8075     { Bad_Opcode },
8076     { Bad_Opcode },
8077     { Bad_Opcode },
8078     { Bad_Opcode },
8079     { Bad_Opcode },
8080     { Bad_Opcode },
8081     { Bad_Opcode },
8082     { Bad_Opcode },
8083     /* 40 */
8084     { Bad_Opcode },
8085     { Bad_Opcode },
8086     { Bad_Opcode },
8087     { Bad_Opcode },
8088     { Bad_Opcode },
8089     { Bad_Opcode },
8090     { Bad_Opcode },
8091     { Bad_Opcode },
8092     /* 48 */
8093     { Bad_Opcode },
8094     { Bad_Opcode },
8095     { Bad_Opcode },
8096     { Bad_Opcode },
8097     { Bad_Opcode },
8098     { Bad_Opcode },
8099     { Bad_Opcode },
8100     { Bad_Opcode },
8101     /* 50 */
8102     { Bad_Opcode },
8103     { Bad_Opcode },
8104     { Bad_Opcode },
8105     { Bad_Opcode },
8106     { Bad_Opcode },
8107     { Bad_Opcode },
8108     { Bad_Opcode },
8109     { Bad_Opcode },
8110     /* 58 */
8111     { Bad_Opcode },
8112     { Bad_Opcode },
8113     { Bad_Opcode },
8114     { Bad_Opcode },
8115     { Bad_Opcode },
8116     { Bad_Opcode },
8117     { Bad_Opcode },
8118     { Bad_Opcode },
8119     /* 60 */
8120     { Bad_Opcode },
8121     { Bad_Opcode },
8122     { Bad_Opcode },
8123     { Bad_Opcode },
8124     { Bad_Opcode },
8125     { Bad_Opcode },
8126     { Bad_Opcode },
8127     { Bad_Opcode },
8128     /* 68 */
8129     { Bad_Opcode },
8130     { Bad_Opcode },
8131     { Bad_Opcode },
8132     { Bad_Opcode },
8133     { Bad_Opcode },
8134     { Bad_Opcode },
8135     { Bad_Opcode },
8136     { Bad_Opcode },
8137     /* 70 */
8138     { Bad_Opcode },
8139     { Bad_Opcode },
8140     { Bad_Opcode },
8141     { Bad_Opcode },
8142     { Bad_Opcode },
8143     { Bad_Opcode },
8144     { Bad_Opcode },
8145     { Bad_Opcode },
8146     /* 78 */
8147     { Bad_Opcode },
8148     { Bad_Opcode },
8149     { Bad_Opcode },
8150     { Bad_Opcode },
8151     { Bad_Opcode },
8152     { Bad_Opcode },
8153     { Bad_Opcode },
8154     { Bad_Opcode },
8155     /* 80 */
8156     { Bad_Opcode },
8157     { Bad_Opcode },
8158     { Bad_Opcode },
8159     { Bad_Opcode },
8160     { Bad_Opcode },
8161     { Bad_Opcode },
8162     { Bad_Opcode },
8163     { Bad_Opcode },
8164     /* 88 */
8165     { Bad_Opcode },
8166     { Bad_Opcode },
8167     { Bad_Opcode },
8168     { Bad_Opcode },
8169     { Bad_Opcode },
8170     { Bad_Opcode },
8171     { Bad_Opcode },
8172     { Bad_Opcode },
8173     /* 90 */
8174     { Bad_Opcode },
8175     { Bad_Opcode },
8176     { Bad_Opcode },
8177     { Bad_Opcode },
8178     { Bad_Opcode },
8179     { Bad_Opcode },
8180     { Bad_Opcode },
8181     { Bad_Opcode },
8182     /* 98 */
8183     { Bad_Opcode },
8184     { Bad_Opcode },
8185     { Bad_Opcode },
8186     { Bad_Opcode },
8187     { Bad_Opcode },
8188     { Bad_Opcode },
8189     { Bad_Opcode },
8190     { Bad_Opcode },
8191     /* a0 */
8192     { Bad_Opcode },
8193     { Bad_Opcode },
8194     { Bad_Opcode },
8195     { Bad_Opcode },
8196     { Bad_Opcode },
8197     { Bad_Opcode },
8198     { Bad_Opcode },
8199     { Bad_Opcode },
8200     /* a8 */
8201     { Bad_Opcode },
8202     { Bad_Opcode },
8203     { Bad_Opcode },
8204     { Bad_Opcode },
8205     { Bad_Opcode },
8206     { Bad_Opcode },
8207     { Bad_Opcode },
8208     { Bad_Opcode },
8209     /* b0 */
8210     { Bad_Opcode },
8211     { Bad_Opcode },
8212     { Bad_Opcode },
8213     { Bad_Opcode },
8214     { Bad_Opcode },
8215     { Bad_Opcode },
8216     { Bad_Opcode },
8217     { Bad_Opcode },
8218     /* b8 */
8219     { Bad_Opcode },
8220     { Bad_Opcode },
8221     { Bad_Opcode },
8222     { Bad_Opcode },
8223     { Bad_Opcode },
8224     { Bad_Opcode },
8225     { Bad_Opcode },
8226     { Bad_Opcode },
8227     /* c0 */
8228     { Bad_Opcode },
8229     { Bad_Opcode },
8230     { Bad_Opcode },
8231     { Bad_Opcode },
8232     { Bad_Opcode },
8233     { Bad_Opcode },
8234     { Bad_Opcode },
8235     { Bad_Opcode },
8236     /* c8 */
8237     { Bad_Opcode },
8238     { Bad_Opcode },
8239     { Bad_Opcode },
8240     { Bad_Opcode },
8241     { Bad_Opcode },
8242     { Bad_Opcode },
8243     { Bad_Opcode },
8244     { Bad_Opcode },
8245     /* d0 */
8246     { Bad_Opcode },
8247     { Bad_Opcode },
8248     { Bad_Opcode },
8249     { Bad_Opcode },
8250     { Bad_Opcode },
8251     { Bad_Opcode },
8252     { Bad_Opcode },
8253     { Bad_Opcode },
8254     /* d8 */
8255     { Bad_Opcode },
8256     { Bad_Opcode },
8257     { Bad_Opcode },
8258     { Bad_Opcode },
8259     { Bad_Opcode },
8260     { Bad_Opcode },
8261     { Bad_Opcode },
8262     { Bad_Opcode },
8263     /* e0 */
8264     { Bad_Opcode },
8265     { Bad_Opcode },
8266     { Bad_Opcode },
8267     { Bad_Opcode },
8268     { Bad_Opcode },
8269     { Bad_Opcode },
8270     { Bad_Opcode },
8271     { Bad_Opcode },
8272     /* e8 */
8273     { Bad_Opcode },
8274     { Bad_Opcode },
8275     { Bad_Opcode },
8276     { Bad_Opcode },
8277     { Bad_Opcode },
8278     { Bad_Opcode },
8279     { Bad_Opcode },
8280     { Bad_Opcode },
8281     /* f0 */
8282     { Bad_Opcode },
8283     { Bad_Opcode },
8284     { Bad_Opcode },
8285     { Bad_Opcode },
8286     { Bad_Opcode },
8287     { Bad_Opcode },
8288     { Bad_Opcode },
8289     { Bad_Opcode },
8290     /* f8 */
8291     { Bad_Opcode },
8292     { Bad_Opcode },
8293     { Bad_Opcode },
8294     { Bad_Opcode },
8295     { Bad_Opcode },
8296     { Bad_Opcode },
8297     { Bad_Opcode },
8298     { Bad_Opcode },
8299   },
8300 };
8301
8302 static const struct dis386 vex_table[][256] = {
8303   /* VEX_0F */
8304   {
8305     /* 00 */
8306     { Bad_Opcode },
8307     { Bad_Opcode },
8308     { Bad_Opcode },
8309     { Bad_Opcode },
8310     { Bad_Opcode },
8311     { Bad_Opcode },
8312     { Bad_Opcode },
8313     { Bad_Opcode },
8314     /* 08 */
8315     { Bad_Opcode },
8316     { Bad_Opcode },
8317     { Bad_Opcode },
8318     { Bad_Opcode },
8319     { Bad_Opcode },
8320     { Bad_Opcode },
8321     { Bad_Opcode },
8322     { Bad_Opcode },
8323     /* 10 */
8324     { PREFIX_TABLE (PREFIX_VEX_0F10) },
8325     { PREFIX_TABLE (PREFIX_VEX_0F11) },
8326     { PREFIX_TABLE (PREFIX_VEX_0F12) },
8327     { MOD_TABLE (MOD_VEX_0F13) },
8328     { "vunpcklpX",      { XM, Vex, EXx }, PREFIX_OPCODE },
8329     { "vunpckhpX",      { XM, Vex, EXx }, PREFIX_OPCODE },
8330     { PREFIX_TABLE (PREFIX_VEX_0F16) },
8331     { MOD_TABLE (MOD_VEX_0F17) },
8332     /* 18 */
8333     { Bad_Opcode },
8334     { Bad_Opcode },
8335     { Bad_Opcode },
8336     { Bad_Opcode },
8337     { Bad_Opcode },
8338     { Bad_Opcode },
8339     { Bad_Opcode },
8340     { Bad_Opcode },
8341     /* 20 */
8342     { Bad_Opcode },
8343     { Bad_Opcode },
8344     { Bad_Opcode },
8345     { Bad_Opcode },
8346     { Bad_Opcode },
8347     { Bad_Opcode },
8348     { Bad_Opcode },
8349     { Bad_Opcode },
8350     /* 28 */
8351     { "vmovapX",        { XM, EXx }, PREFIX_OPCODE },
8352     { "vmovapX",        { EXxS, XM }, PREFIX_OPCODE },
8353     { PREFIX_TABLE (PREFIX_VEX_0F2A) },
8354     { MOD_TABLE (MOD_VEX_0F2B) },
8355     { PREFIX_TABLE (PREFIX_VEX_0F2C) },
8356     { PREFIX_TABLE (PREFIX_VEX_0F2D) },
8357     { PREFIX_TABLE (PREFIX_VEX_0F2E) },
8358     { PREFIX_TABLE (PREFIX_VEX_0F2F) },
8359     /* 30 */
8360     { Bad_Opcode },
8361     { Bad_Opcode },
8362     { Bad_Opcode },
8363     { Bad_Opcode },
8364     { Bad_Opcode },
8365     { Bad_Opcode },
8366     { Bad_Opcode },
8367     { Bad_Opcode },
8368     /* 38 */
8369     { Bad_Opcode },
8370     { Bad_Opcode },
8371     { Bad_Opcode },
8372     { Bad_Opcode },
8373     { Bad_Opcode },
8374     { Bad_Opcode },
8375     { Bad_Opcode },
8376     { Bad_Opcode },
8377     /* 40 */
8378     { Bad_Opcode },
8379     { PREFIX_TABLE (PREFIX_VEX_0F41) },
8380     { PREFIX_TABLE (PREFIX_VEX_0F42) },
8381     { Bad_Opcode },
8382     { PREFIX_TABLE (PREFIX_VEX_0F44) },
8383     { PREFIX_TABLE (PREFIX_VEX_0F45) },
8384     { PREFIX_TABLE (PREFIX_VEX_0F46) },
8385     { PREFIX_TABLE (PREFIX_VEX_0F47) },
8386     /* 48 */
8387     { Bad_Opcode },
8388     { Bad_Opcode },
8389     { PREFIX_TABLE (PREFIX_VEX_0F4A) },
8390     { PREFIX_TABLE (PREFIX_VEX_0F4B) },
8391     { Bad_Opcode },
8392     { Bad_Opcode },
8393     { Bad_Opcode },
8394     { Bad_Opcode },
8395     /* 50 */
8396     { MOD_TABLE (MOD_VEX_0F50) },
8397     { PREFIX_TABLE (PREFIX_VEX_0F51) },
8398     { PREFIX_TABLE (PREFIX_VEX_0F52) },
8399     { PREFIX_TABLE (PREFIX_VEX_0F53) },
8400     { "vandpX",         { XM, Vex, EXx }, PREFIX_OPCODE },
8401     { "vandnpX",        { XM, Vex, EXx }, PREFIX_OPCODE },
8402     { "vorpX",          { XM, Vex, EXx }, PREFIX_OPCODE },
8403     { "vxorpX",         { XM, Vex, EXx }, PREFIX_OPCODE },
8404     /* 58 */
8405     { PREFIX_TABLE (PREFIX_VEX_0F58) },
8406     { PREFIX_TABLE (PREFIX_VEX_0F59) },
8407     { PREFIX_TABLE (PREFIX_VEX_0F5A) },
8408     { PREFIX_TABLE (PREFIX_VEX_0F5B) },
8409     { PREFIX_TABLE (PREFIX_VEX_0F5C) },
8410     { PREFIX_TABLE (PREFIX_VEX_0F5D) },
8411     { PREFIX_TABLE (PREFIX_VEX_0F5E) },
8412     { PREFIX_TABLE (PREFIX_VEX_0F5F) },
8413     /* 60 */
8414     { PREFIX_TABLE (PREFIX_VEX_0F60) },
8415     { PREFIX_TABLE (PREFIX_VEX_0F61) },
8416     { PREFIX_TABLE (PREFIX_VEX_0F62) },
8417     { PREFIX_TABLE (PREFIX_VEX_0F63) },
8418     { PREFIX_TABLE (PREFIX_VEX_0F64) },
8419     { PREFIX_TABLE (PREFIX_VEX_0F65) },
8420     { PREFIX_TABLE (PREFIX_VEX_0F66) },
8421     { PREFIX_TABLE (PREFIX_VEX_0F67) },
8422     /* 68 */
8423     { PREFIX_TABLE (PREFIX_VEX_0F68) },
8424     { PREFIX_TABLE (PREFIX_VEX_0F69) },
8425     { PREFIX_TABLE (PREFIX_VEX_0F6A) },
8426     { PREFIX_TABLE (PREFIX_VEX_0F6B) },
8427     { PREFIX_TABLE (PREFIX_VEX_0F6C) },
8428     { PREFIX_TABLE (PREFIX_VEX_0F6D) },
8429     { PREFIX_TABLE (PREFIX_VEX_0F6E) },
8430     { PREFIX_TABLE (PREFIX_VEX_0F6F) },
8431     /* 70 */
8432     { PREFIX_TABLE (PREFIX_VEX_0F70) },
8433     { REG_TABLE (REG_VEX_0F71) },
8434     { REG_TABLE (REG_VEX_0F72) },
8435     { REG_TABLE (REG_VEX_0F73) },
8436     { PREFIX_TABLE (PREFIX_VEX_0F74) },
8437     { PREFIX_TABLE (PREFIX_VEX_0F75) },
8438     { PREFIX_TABLE (PREFIX_VEX_0F76) },
8439     { PREFIX_TABLE (PREFIX_VEX_0F77) },
8440     /* 78 */
8441     { Bad_Opcode },
8442     { Bad_Opcode },
8443     { Bad_Opcode },
8444     { Bad_Opcode },
8445     { PREFIX_TABLE (PREFIX_VEX_0F7C) },
8446     { PREFIX_TABLE (PREFIX_VEX_0F7D) },
8447     { PREFIX_TABLE (PREFIX_VEX_0F7E) },
8448     { PREFIX_TABLE (PREFIX_VEX_0F7F) },
8449     /* 80 */
8450     { Bad_Opcode },
8451     { Bad_Opcode },
8452     { Bad_Opcode },
8453     { Bad_Opcode },
8454     { Bad_Opcode },
8455     { Bad_Opcode },
8456     { Bad_Opcode },
8457     { Bad_Opcode },
8458     /* 88 */
8459     { Bad_Opcode },
8460     { Bad_Opcode },
8461     { Bad_Opcode },
8462     { Bad_Opcode },
8463     { Bad_Opcode },
8464     { Bad_Opcode },
8465     { Bad_Opcode },
8466     { Bad_Opcode },
8467     /* 90 */
8468     { PREFIX_TABLE (PREFIX_VEX_0F90) },
8469     { PREFIX_TABLE (PREFIX_VEX_0F91) },
8470     { PREFIX_TABLE (PREFIX_VEX_0F92) },
8471     { PREFIX_TABLE (PREFIX_VEX_0F93) },
8472     { Bad_Opcode },
8473     { Bad_Opcode },
8474     { Bad_Opcode },
8475     { Bad_Opcode },
8476     /* 98 */
8477     { PREFIX_TABLE (PREFIX_VEX_0F98) },
8478     { PREFIX_TABLE (PREFIX_VEX_0F99) },
8479     { Bad_Opcode },
8480     { Bad_Opcode },
8481     { Bad_Opcode },
8482     { Bad_Opcode },
8483     { Bad_Opcode },
8484     { Bad_Opcode },
8485     /* a0 */
8486     { Bad_Opcode },
8487     { Bad_Opcode },
8488     { Bad_Opcode },
8489     { Bad_Opcode },
8490     { Bad_Opcode },
8491     { Bad_Opcode },
8492     { Bad_Opcode },
8493     { Bad_Opcode },
8494     /* a8 */
8495     { Bad_Opcode },
8496     { Bad_Opcode },
8497     { Bad_Opcode },
8498     { Bad_Opcode },
8499     { Bad_Opcode },
8500     { Bad_Opcode },
8501     { REG_TABLE (REG_VEX_0FAE) },
8502     { Bad_Opcode },
8503     /* b0 */
8504     { Bad_Opcode },
8505     { Bad_Opcode },
8506     { Bad_Opcode },
8507     { Bad_Opcode },
8508     { Bad_Opcode },
8509     { Bad_Opcode },
8510     { Bad_Opcode },
8511     { Bad_Opcode },
8512     /* b8 */
8513     { Bad_Opcode },
8514     { Bad_Opcode },
8515     { Bad_Opcode },
8516     { Bad_Opcode },
8517     { Bad_Opcode },
8518     { Bad_Opcode },
8519     { Bad_Opcode },
8520     { Bad_Opcode },
8521     /* c0 */
8522     { Bad_Opcode },
8523     { Bad_Opcode },
8524     { PREFIX_TABLE (PREFIX_VEX_0FC2) },
8525     { Bad_Opcode },
8526     { PREFIX_TABLE (PREFIX_VEX_0FC4) },
8527     { PREFIX_TABLE (PREFIX_VEX_0FC5) },
8528     { "vshufpX",        { XM, Vex, EXx, Ib }, PREFIX_OPCODE },
8529     { Bad_Opcode },
8530     /* c8 */
8531     { Bad_Opcode },
8532     { Bad_Opcode },
8533     { Bad_Opcode },
8534     { Bad_Opcode },
8535     { Bad_Opcode },
8536     { Bad_Opcode },
8537     { Bad_Opcode },
8538     { Bad_Opcode },
8539     /* d0 */
8540     { PREFIX_TABLE (PREFIX_VEX_0FD0) },
8541     { PREFIX_TABLE (PREFIX_VEX_0FD1) },
8542     { PREFIX_TABLE (PREFIX_VEX_0FD2) },
8543     { PREFIX_TABLE (PREFIX_VEX_0FD3) },
8544     { PREFIX_TABLE (PREFIX_VEX_0FD4) },
8545     { PREFIX_TABLE (PREFIX_VEX_0FD5) },
8546     { PREFIX_TABLE (PREFIX_VEX_0FD6) },
8547     { PREFIX_TABLE (PREFIX_VEX_0FD7) },
8548     /* d8 */
8549     { PREFIX_TABLE (PREFIX_VEX_0FD8) },
8550     { PREFIX_TABLE (PREFIX_VEX_0FD9) },
8551     { PREFIX_TABLE (PREFIX_VEX_0FDA) },
8552     { PREFIX_TABLE (PREFIX_VEX_0FDB) },
8553     { PREFIX_TABLE (PREFIX_VEX_0FDC) },
8554     { PREFIX_TABLE (PREFIX_VEX_0FDD) },
8555     { PREFIX_TABLE (PREFIX_VEX_0FDE) },
8556     { PREFIX_TABLE (PREFIX_VEX_0FDF) },
8557     /* e0 */
8558     { PREFIX_TABLE (PREFIX_VEX_0FE0) },
8559     { PREFIX_TABLE (PREFIX_VEX_0FE1) },
8560     { PREFIX_TABLE (PREFIX_VEX_0FE2) },
8561     { PREFIX_TABLE (PREFIX_VEX_0FE3) },
8562     { PREFIX_TABLE (PREFIX_VEX_0FE4) },
8563     { PREFIX_TABLE (PREFIX_VEX_0FE5) },
8564     { PREFIX_TABLE (PREFIX_VEX_0FE6) },
8565     { PREFIX_TABLE (PREFIX_VEX_0FE7) },
8566     /* e8 */
8567     { PREFIX_TABLE (PREFIX_VEX_0FE8) },
8568     { PREFIX_TABLE (PREFIX_VEX_0FE9) },
8569     { PREFIX_TABLE (PREFIX_VEX_0FEA) },
8570     { PREFIX_TABLE (PREFIX_VEX_0FEB) },
8571     { PREFIX_TABLE (PREFIX_VEX_0FEC) },
8572     { PREFIX_TABLE (PREFIX_VEX_0FED) },
8573     { PREFIX_TABLE (PREFIX_VEX_0FEE) },
8574     { PREFIX_TABLE (PREFIX_VEX_0FEF) },
8575     /* f0 */
8576     { PREFIX_TABLE (PREFIX_VEX_0FF0) },
8577     { PREFIX_TABLE (PREFIX_VEX_0FF1) },
8578     { PREFIX_TABLE (PREFIX_VEX_0FF2) },
8579     { PREFIX_TABLE (PREFIX_VEX_0FF3) },
8580     { PREFIX_TABLE (PREFIX_VEX_0FF4) },
8581     { PREFIX_TABLE (PREFIX_VEX_0FF5) },
8582     { PREFIX_TABLE (PREFIX_VEX_0FF6) },
8583     { PREFIX_TABLE (PREFIX_VEX_0FF7) },
8584     /* f8 */
8585     { PREFIX_TABLE (PREFIX_VEX_0FF8) },
8586     { PREFIX_TABLE (PREFIX_VEX_0FF9) },
8587     { PREFIX_TABLE (PREFIX_VEX_0FFA) },
8588     { PREFIX_TABLE (PREFIX_VEX_0FFB) },
8589     { PREFIX_TABLE (PREFIX_VEX_0FFC) },
8590     { PREFIX_TABLE (PREFIX_VEX_0FFD) },
8591     { PREFIX_TABLE (PREFIX_VEX_0FFE) },
8592     { Bad_Opcode },
8593   },
8594   /* VEX_0F38 */
8595   {
8596     /* 00 */
8597     { PREFIX_TABLE (PREFIX_VEX_0F3800) },
8598     { PREFIX_TABLE (PREFIX_VEX_0F3801) },
8599     { PREFIX_TABLE (PREFIX_VEX_0F3802) },
8600     { PREFIX_TABLE (PREFIX_VEX_0F3803) },
8601     { PREFIX_TABLE (PREFIX_VEX_0F3804) },
8602     { PREFIX_TABLE (PREFIX_VEX_0F3805) },
8603     { PREFIX_TABLE (PREFIX_VEX_0F3806) },
8604     { PREFIX_TABLE (PREFIX_VEX_0F3807) },
8605     /* 08 */
8606     { PREFIX_TABLE (PREFIX_VEX_0F3808) },
8607     { PREFIX_TABLE (PREFIX_VEX_0F3809) },
8608     { PREFIX_TABLE (PREFIX_VEX_0F380A) },
8609     { PREFIX_TABLE (PREFIX_VEX_0F380B) },
8610     { PREFIX_TABLE (PREFIX_VEX_0F380C) },
8611     { PREFIX_TABLE (PREFIX_VEX_0F380D) },
8612     { PREFIX_TABLE (PREFIX_VEX_0F380E) },
8613     { PREFIX_TABLE (PREFIX_VEX_0F380F) },
8614     /* 10 */
8615     { Bad_Opcode },
8616     { Bad_Opcode },
8617     { Bad_Opcode },
8618     { PREFIX_TABLE (PREFIX_VEX_0F3813) },
8619     { Bad_Opcode },
8620     { Bad_Opcode },
8621     { PREFIX_TABLE (PREFIX_VEX_0F3816) },
8622     { PREFIX_TABLE (PREFIX_VEX_0F3817) },
8623     /* 18 */
8624     { PREFIX_TABLE (PREFIX_VEX_0F3818) },
8625     { PREFIX_TABLE (PREFIX_VEX_0F3819) },
8626     { PREFIX_TABLE (PREFIX_VEX_0F381A) },
8627     { Bad_Opcode },
8628     { PREFIX_TABLE (PREFIX_VEX_0F381C) },
8629     { PREFIX_TABLE (PREFIX_VEX_0F381D) },
8630     { PREFIX_TABLE (PREFIX_VEX_0F381E) },
8631     { Bad_Opcode },
8632     /* 20 */
8633     { PREFIX_TABLE (PREFIX_VEX_0F3820) },
8634     { PREFIX_TABLE (PREFIX_VEX_0F3821) },
8635     { PREFIX_TABLE (PREFIX_VEX_0F3822) },
8636     { PREFIX_TABLE (PREFIX_VEX_0F3823) },
8637     { PREFIX_TABLE (PREFIX_VEX_0F3824) },
8638     { PREFIX_TABLE (PREFIX_VEX_0F3825) },
8639     { Bad_Opcode },
8640     { Bad_Opcode },
8641     /* 28 */
8642     { PREFIX_TABLE (PREFIX_VEX_0F3828) },
8643     { PREFIX_TABLE (PREFIX_VEX_0F3829) },
8644     { PREFIX_TABLE (PREFIX_VEX_0F382A) },
8645     { PREFIX_TABLE (PREFIX_VEX_0F382B) },
8646     { PREFIX_TABLE (PREFIX_VEX_0F382C) },
8647     { PREFIX_TABLE (PREFIX_VEX_0F382D) },
8648     { PREFIX_TABLE (PREFIX_VEX_0F382E) },
8649     { PREFIX_TABLE (PREFIX_VEX_0F382F) },
8650     /* 30 */
8651     { PREFIX_TABLE (PREFIX_VEX_0F3830) },
8652     { PREFIX_TABLE (PREFIX_VEX_0F3831) },
8653     { PREFIX_TABLE (PREFIX_VEX_0F3832) },
8654     { PREFIX_TABLE (PREFIX_VEX_0F3833) },
8655     { PREFIX_TABLE (PREFIX_VEX_0F3834) },
8656     { PREFIX_TABLE (PREFIX_VEX_0F3835) },
8657     { PREFIX_TABLE (PREFIX_VEX_0F3836) },
8658     { PREFIX_TABLE (PREFIX_VEX_0F3837) },
8659     /* 38 */
8660     { PREFIX_TABLE (PREFIX_VEX_0F3838) },
8661     { PREFIX_TABLE (PREFIX_VEX_0F3839) },
8662     { PREFIX_TABLE (PREFIX_VEX_0F383A) },
8663     { PREFIX_TABLE (PREFIX_VEX_0F383B) },
8664     { PREFIX_TABLE (PREFIX_VEX_0F383C) },
8665     { PREFIX_TABLE (PREFIX_VEX_0F383D) },
8666     { PREFIX_TABLE (PREFIX_VEX_0F383E) },
8667     { PREFIX_TABLE (PREFIX_VEX_0F383F) },
8668     /* 40 */
8669     { PREFIX_TABLE (PREFIX_VEX_0F3840) },
8670     { PREFIX_TABLE (PREFIX_VEX_0F3841) },
8671     { Bad_Opcode },
8672     { Bad_Opcode },
8673     { Bad_Opcode },
8674     { PREFIX_TABLE (PREFIX_VEX_0F3845) },
8675     { PREFIX_TABLE (PREFIX_VEX_0F3846) },
8676     { PREFIX_TABLE (PREFIX_VEX_0F3847) },
8677     /* 48 */
8678     { Bad_Opcode },
8679     { Bad_Opcode },
8680     { Bad_Opcode },
8681     { Bad_Opcode },
8682     { Bad_Opcode },
8683     { Bad_Opcode },
8684     { Bad_Opcode },
8685     { Bad_Opcode },
8686     /* 50 */
8687     { Bad_Opcode },
8688     { Bad_Opcode },
8689     { Bad_Opcode },
8690     { Bad_Opcode },
8691     { Bad_Opcode },
8692     { Bad_Opcode },
8693     { Bad_Opcode },
8694     { Bad_Opcode },
8695     /* 58 */
8696     { PREFIX_TABLE (PREFIX_VEX_0F3858) },
8697     { PREFIX_TABLE (PREFIX_VEX_0F3859) },
8698     { PREFIX_TABLE (PREFIX_VEX_0F385A) },
8699     { Bad_Opcode },
8700     { Bad_Opcode },
8701     { Bad_Opcode },
8702     { Bad_Opcode },
8703     { Bad_Opcode },
8704     /* 60 */
8705     { Bad_Opcode },
8706     { Bad_Opcode },
8707     { Bad_Opcode },
8708     { Bad_Opcode },
8709     { Bad_Opcode },
8710     { Bad_Opcode },
8711     { Bad_Opcode },
8712     { Bad_Opcode },
8713     /* 68 */
8714     { Bad_Opcode },
8715     { Bad_Opcode },
8716     { Bad_Opcode },
8717     { Bad_Opcode },
8718     { Bad_Opcode },
8719     { Bad_Opcode },
8720     { Bad_Opcode },
8721     { Bad_Opcode },
8722     /* 70 */
8723     { Bad_Opcode },
8724     { Bad_Opcode },
8725     { Bad_Opcode },
8726     { Bad_Opcode },
8727     { Bad_Opcode },
8728     { Bad_Opcode },
8729     { Bad_Opcode },
8730     { Bad_Opcode },
8731     /* 78 */
8732     { PREFIX_TABLE (PREFIX_VEX_0F3878) },
8733     { PREFIX_TABLE (PREFIX_VEX_0F3879) },
8734     { Bad_Opcode },
8735     { Bad_Opcode },
8736     { Bad_Opcode },
8737     { Bad_Opcode },
8738     { Bad_Opcode },
8739     { Bad_Opcode },
8740     /* 80 */
8741     { Bad_Opcode },
8742     { Bad_Opcode },
8743     { Bad_Opcode },
8744     { Bad_Opcode },
8745     { Bad_Opcode },
8746     { Bad_Opcode },
8747     { Bad_Opcode },
8748     { Bad_Opcode },
8749     /* 88 */
8750     { Bad_Opcode },
8751     { Bad_Opcode },
8752     { Bad_Opcode },
8753     { Bad_Opcode },
8754     { PREFIX_TABLE (PREFIX_VEX_0F388C) },
8755     { Bad_Opcode },
8756     { PREFIX_TABLE (PREFIX_VEX_0F388E) },
8757     { Bad_Opcode },
8758     /* 90 */
8759     { PREFIX_TABLE (PREFIX_VEX_0F3890) },
8760     { PREFIX_TABLE (PREFIX_VEX_0F3891) },
8761     { PREFIX_TABLE (PREFIX_VEX_0F3892) },
8762     { PREFIX_TABLE (PREFIX_VEX_0F3893) },
8763     { Bad_Opcode },
8764     { Bad_Opcode },
8765     { PREFIX_TABLE (PREFIX_VEX_0F3896) },
8766     { PREFIX_TABLE (PREFIX_VEX_0F3897) },
8767     /* 98 */
8768     { PREFIX_TABLE (PREFIX_VEX_0F3898) },
8769     { PREFIX_TABLE (PREFIX_VEX_0F3899) },
8770     { PREFIX_TABLE (PREFIX_VEX_0F389A) },
8771     { PREFIX_TABLE (PREFIX_VEX_0F389B) },
8772     { PREFIX_TABLE (PREFIX_VEX_0F389C) },
8773     { PREFIX_TABLE (PREFIX_VEX_0F389D) },
8774     { PREFIX_TABLE (PREFIX_VEX_0F389E) },
8775     { PREFIX_TABLE (PREFIX_VEX_0F389F) },
8776     /* a0 */
8777     { Bad_Opcode },
8778     { Bad_Opcode },
8779     { Bad_Opcode },
8780     { Bad_Opcode },
8781     { Bad_Opcode },
8782     { Bad_Opcode },
8783     { PREFIX_TABLE (PREFIX_VEX_0F38A6) },
8784     { PREFIX_TABLE (PREFIX_VEX_0F38A7) },
8785     /* a8 */
8786     { PREFIX_TABLE (PREFIX_VEX_0F38A8) },
8787     { PREFIX_TABLE (PREFIX_VEX_0F38A9) },
8788     { PREFIX_TABLE (PREFIX_VEX_0F38AA) },
8789     { PREFIX_TABLE (PREFIX_VEX_0F38AB) },
8790     { PREFIX_TABLE (PREFIX_VEX_0F38AC) },
8791     { PREFIX_TABLE (PREFIX_VEX_0F38AD) },
8792     { PREFIX_TABLE (PREFIX_VEX_0F38AE) },
8793     { PREFIX_TABLE (PREFIX_VEX_0F38AF) },
8794     /* b0 */
8795     { Bad_Opcode },
8796     { Bad_Opcode },
8797     { Bad_Opcode },
8798     { Bad_Opcode },
8799     { Bad_Opcode },
8800     { Bad_Opcode },
8801     { PREFIX_TABLE (PREFIX_VEX_0F38B6) },
8802     { PREFIX_TABLE (PREFIX_VEX_0F38B7) },
8803     /* b8 */
8804     { PREFIX_TABLE (PREFIX_VEX_0F38B8) },
8805     { PREFIX_TABLE (PREFIX_VEX_0F38B9) },
8806     { PREFIX_TABLE (PREFIX_VEX_0F38BA) },
8807     { PREFIX_TABLE (PREFIX_VEX_0F38BB) },
8808     { PREFIX_TABLE (PREFIX_VEX_0F38BC) },
8809     { PREFIX_TABLE (PREFIX_VEX_0F38BD) },
8810     { PREFIX_TABLE (PREFIX_VEX_0F38BE) },
8811     { PREFIX_TABLE (PREFIX_VEX_0F38BF) },
8812     /* c0 */
8813     { Bad_Opcode },
8814     { Bad_Opcode },
8815     { Bad_Opcode },
8816     { Bad_Opcode },
8817     { Bad_Opcode },
8818     { Bad_Opcode },
8819     { Bad_Opcode },
8820     { Bad_Opcode },
8821     /* c8 */
8822     { Bad_Opcode },
8823     { Bad_Opcode },
8824     { Bad_Opcode },
8825     { Bad_Opcode },
8826     { Bad_Opcode },
8827     { Bad_Opcode },
8828     { Bad_Opcode },
8829     { PREFIX_TABLE (PREFIX_VEX_0F38CF) },
8830     /* d0 */
8831     { Bad_Opcode },
8832     { Bad_Opcode },
8833     { Bad_Opcode },
8834     { Bad_Opcode },
8835     { Bad_Opcode },
8836     { Bad_Opcode },
8837     { Bad_Opcode },
8838     { Bad_Opcode },
8839     /* d8 */
8840     { Bad_Opcode },
8841     { Bad_Opcode },
8842     { Bad_Opcode },
8843     { PREFIX_TABLE (PREFIX_VEX_0F38DB) },
8844     { PREFIX_TABLE (PREFIX_VEX_0F38DC) },
8845     { PREFIX_TABLE (PREFIX_VEX_0F38DD) },
8846     { PREFIX_TABLE (PREFIX_VEX_0F38DE) },
8847     { PREFIX_TABLE (PREFIX_VEX_0F38DF) },
8848     /* e0 */
8849     { Bad_Opcode },
8850     { Bad_Opcode },
8851     { Bad_Opcode },
8852     { Bad_Opcode },
8853     { Bad_Opcode },
8854     { Bad_Opcode },
8855     { Bad_Opcode },
8856     { Bad_Opcode },
8857     /* e8 */
8858     { Bad_Opcode },
8859     { Bad_Opcode },
8860     { Bad_Opcode },
8861     { Bad_Opcode },
8862     { Bad_Opcode },
8863     { Bad_Opcode },
8864     { Bad_Opcode },
8865     { Bad_Opcode },
8866     /* f0 */
8867     { Bad_Opcode },
8868     { Bad_Opcode },
8869     { PREFIX_TABLE (PREFIX_VEX_0F38F2) },
8870     { REG_TABLE (REG_VEX_0F38F3) },
8871     { Bad_Opcode },
8872     { PREFIX_TABLE (PREFIX_VEX_0F38F5) },
8873     { PREFIX_TABLE (PREFIX_VEX_0F38F6) },
8874     { PREFIX_TABLE (PREFIX_VEX_0F38F7) },
8875     /* f8 */
8876     { Bad_Opcode },
8877     { Bad_Opcode },
8878     { Bad_Opcode },
8879     { Bad_Opcode },
8880     { Bad_Opcode },
8881     { Bad_Opcode },
8882     { Bad_Opcode },
8883     { Bad_Opcode },
8884   },
8885   /* VEX_0F3A */
8886   {
8887     /* 00 */
8888     { PREFIX_TABLE (PREFIX_VEX_0F3A00) },
8889     { PREFIX_TABLE (PREFIX_VEX_0F3A01) },
8890     { PREFIX_TABLE (PREFIX_VEX_0F3A02) },
8891     { Bad_Opcode },
8892     { PREFIX_TABLE (PREFIX_VEX_0F3A04) },
8893     { PREFIX_TABLE (PREFIX_VEX_0F3A05) },
8894     { PREFIX_TABLE (PREFIX_VEX_0F3A06) },
8895     { Bad_Opcode },
8896     /* 08 */
8897     { PREFIX_TABLE (PREFIX_VEX_0F3A08) },
8898     { PREFIX_TABLE (PREFIX_VEX_0F3A09) },
8899     { PREFIX_TABLE (PREFIX_VEX_0F3A0A) },
8900     { PREFIX_TABLE (PREFIX_VEX_0F3A0B) },
8901     { PREFIX_TABLE (PREFIX_VEX_0F3A0C) },
8902     { PREFIX_TABLE (PREFIX_VEX_0F3A0D) },
8903     { PREFIX_TABLE (PREFIX_VEX_0F3A0E) },
8904     { PREFIX_TABLE (PREFIX_VEX_0F3A0F) },
8905     /* 10 */
8906     { Bad_Opcode },
8907     { Bad_Opcode },
8908     { Bad_Opcode },
8909     { Bad_Opcode },
8910     { PREFIX_TABLE (PREFIX_VEX_0F3A14) },
8911     { PREFIX_TABLE (PREFIX_VEX_0F3A15) },
8912     { PREFIX_TABLE (PREFIX_VEX_0F3A16) },
8913     { PREFIX_TABLE (PREFIX_VEX_0F3A17) },
8914     /* 18 */
8915     { PREFIX_TABLE (PREFIX_VEX_0F3A18) },
8916     { PREFIX_TABLE (PREFIX_VEX_0F3A19) },
8917     { Bad_Opcode },
8918     { Bad_Opcode },
8919     { Bad_Opcode },
8920     { PREFIX_TABLE (PREFIX_VEX_0F3A1D) },
8921     { Bad_Opcode },
8922     { Bad_Opcode },
8923     /* 20 */
8924     { PREFIX_TABLE (PREFIX_VEX_0F3A20) },
8925     { PREFIX_TABLE (PREFIX_VEX_0F3A21) },
8926     { PREFIX_TABLE (PREFIX_VEX_0F3A22) },
8927     { Bad_Opcode },
8928     { Bad_Opcode },
8929     { Bad_Opcode },
8930     { Bad_Opcode },
8931     { Bad_Opcode },
8932     /* 28 */
8933     { Bad_Opcode },
8934     { Bad_Opcode },
8935     { Bad_Opcode },
8936     { Bad_Opcode },
8937     { Bad_Opcode },
8938     { Bad_Opcode },
8939     { Bad_Opcode },
8940     { Bad_Opcode },
8941     /* 30 */
8942     { PREFIX_TABLE (PREFIX_VEX_0F3A30) },
8943     { PREFIX_TABLE (PREFIX_VEX_0F3A31) },
8944     { PREFIX_TABLE (PREFIX_VEX_0F3A32) },
8945     { PREFIX_TABLE (PREFIX_VEX_0F3A33) },
8946     { Bad_Opcode },
8947     { Bad_Opcode },
8948     { Bad_Opcode },
8949     { Bad_Opcode },
8950     /* 38 */
8951     { PREFIX_TABLE (PREFIX_VEX_0F3A38) },
8952     { PREFIX_TABLE (PREFIX_VEX_0F3A39) },
8953     { Bad_Opcode },
8954     { Bad_Opcode },
8955     { Bad_Opcode },
8956     { Bad_Opcode },
8957     { Bad_Opcode },
8958     { Bad_Opcode },
8959     /* 40 */
8960     { PREFIX_TABLE (PREFIX_VEX_0F3A40) },
8961     { PREFIX_TABLE (PREFIX_VEX_0F3A41) },
8962     { PREFIX_TABLE (PREFIX_VEX_0F3A42) },
8963     { Bad_Opcode },
8964     { PREFIX_TABLE (PREFIX_VEX_0F3A44) },
8965     { Bad_Opcode },
8966     { PREFIX_TABLE (PREFIX_VEX_0F3A46) },
8967     { Bad_Opcode },
8968     /* 48 */
8969     { PREFIX_TABLE (PREFIX_VEX_0F3A48) },
8970     { PREFIX_TABLE (PREFIX_VEX_0F3A49) },
8971     { PREFIX_TABLE (PREFIX_VEX_0F3A4A) },
8972     { PREFIX_TABLE (PREFIX_VEX_0F3A4B) },
8973     { PREFIX_TABLE (PREFIX_VEX_0F3A4C) },
8974     { Bad_Opcode },
8975     { Bad_Opcode },
8976     { Bad_Opcode },
8977     /* 50 */
8978     { Bad_Opcode },
8979     { Bad_Opcode },
8980     { Bad_Opcode },
8981     { Bad_Opcode },
8982     { Bad_Opcode },
8983     { Bad_Opcode },
8984     { Bad_Opcode },
8985     { Bad_Opcode },
8986     /* 58 */
8987     { Bad_Opcode },
8988     { Bad_Opcode },
8989     { Bad_Opcode },
8990     { Bad_Opcode },
8991     { PREFIX_TABLE (PREFIX_VEX_0F3A5C) },
8992     { PREFIX_TABLE (PREFIX_VEX_0F3A5D) },
8993     { PREFIX_TABLE (PREFIX_VEX_0F3A5E) },
8994     { PREFIX_TABLE (PREFIX_VEX_0F3A5F) },
8995     /* 60 */
8996     { PREFIX_TABLE (PREFIX_VEX_0F3A60) },
8997     { PREFIX_TABLE (PREFIX_VEX_0F3A61) },
8998     { PREFIX_TABLE (PREFIX_VEX_0F3A62) },
8999     { PREFIX_TABLE (PREFIX_VEX_0F3A63) },
9000     { Bad_Opcode },
9001     { Bad_Opcode },
9002     { Bad_Opcode },
9003     { Bad_Opcode },
9004     /* 68 */
9005     { PREFIX_TABLE (PREFIX_VEX_0F3A68) },
9006     { PREFIX_TABLE (PREFIX_VEX_0F3A69) },
9007     { PREFIX_TABLE (PREFIX_VEX_0F3A6A) },
9008     { PREFIX_TABLE (PREFIX_VEX_0F3A6B) },
9009     { PREFIX_TABLE (PREFIX_VEX_0F3A6C) },
9010     { PREFIX_TABLE (PREFIX_VEX_0F3A6D) },
9011     { PREFIX_TABLE (PREFIX_VEX_0F3A6E) },
9012     { PREFIX_TABLE (PREFIX_VEX_0F3A6F) },
9013     /* 70 */
9014     { Bad_Opcode },
9015     { Bad_Opcode },
9016     { Bad_Opcode },
9017     { Bad_Opcode },
9018     { Bad_Opcode },
9019     { Bad_Opcode },
9020     { Bad_Opcode },
9021     { Bad_Opcode },
9022     /* 78 */
9023     { PREFIX_TABLE (PREFIX_VEX_0F3A78) },
9024     { PREFIX_TABLE (PREFIX_VEX_0F3A79) },
9025     { PREFIX_TABLE (PREFIX_VEX_0F3A7A) },
9026     { PREFIX_TABLE (PREFIX_VEX_0F3A7B) },
9027     { PREFIX_TABLE (PREFIX_VEX_0F3A7C) },
9028     { PREFIX_TABLE (PREFIX_VEX_0F3A7D) },
9029     { PREFIX_TABLE (PREFIX_VEX_0F3A7E) },
9030     { PREFIX_TABLE (PREFIX_VEX_0F3A7F) },
9031     /* 80 */
9032     { Bad_Opcode },
9033     { Bad_Opcode },
9034     { Bad_Opcode },
9035     { Bad_Opcode },
9036     { Bad_Opcode },
9037     { Bad_Opcode },
9038     { Bad_Opcode },
9039     { Bad_Opcode },
9040     /* 88 */
9041     { Bad_Opcode },
9042     { Bad_Opcode },
9043     { Bad_Opcode },
9044     { Bad_Opcode },
9045     { Bad_Opcode },
9046     { Bad_Opcode },
9047     { Bad_Opcode },
9048     { Bad_Opcode },
9049     /* 90 */
9050     { Bad_Opcode },
9051     { Bad_Opcode },
9052     { Bad_Opcode },
9053     { Bad_Opcode },
9054     { Bad_Opcode },
9055     { Bad_Opcode },
9056     { Bad_Opcode },
9057     { Bad_Opcode },
9058     /* 98 */
9059     { Bad_Opcode },
9060     { Bad_Opcode },
9061     { Bad_Opcode },
9062     { Bad_Opcode },
9063     { Bad_Opcode },
9064     { Bad_Opcode },
9065     { Bad_Opcode },
9066     { Bad_Opcode },
9067     /* a0 */
9068     { Bad_Opcode },
9069     { Bad_Opcode },
9070     { Bad_Opcode },
9071     { Bad_Opcode },
9072     { Bad_Opcode },
9073     { Bad_Opcode },
9074     { Bad_Opcode },
9075     { Bad_Opcode },
9076     /* a8 */
9077     { Bad_Opcode },
9078     { Bad_Opcode },
9079     { Bad_Opcode },
9080     { Bad_Opcode },
9081     { Bad_Opcode },
9082     { Bad_Opcode },
9083     { Bad_Opcode },
9084     { Bad_Opcode },
9085     /* b0 */
9086     { Bad_Opcode },
9087     { Bad_Opcode },
9088     { Bad_Opcode },
9089     { Bad_Opcode },
9090     { Bad_Opcode },
9091     { Bad_Opcode },
9092     { Bad_Opcode },
9093     { Bad_Opcode },
9094     /* b8 */
9095     { Bad_Opcode },
9096     { Bad_Opcode },
9097     { Bad_Opcode },
9098     { Bad_Opcode },
9099     { Bad_Opcode },
9100     { Bad_Opcode },
9101     { Bad_Opcode },
9102     { Bad_Opcode },
9103     /* c0 */
9104     { Bad_Opcode },
9105     { Bad_Opcode },
9106     { Bad_Opcode },
9107     { Bad_Opcode },
9108     { Bad_Opcode },
9109     { Bad_Opcode },
9110     { Bad_Opcode },
9111     { Bad_Opcode },
9112     /* c8 */
9113     { Bad_Opcode },
9114     { Bad_Opcode },
9115     { Bad_Opcode },
9116     { Bad_Opcode },
9117     { Bad_Opcode },
9118     { Bad_Opcode },
9119     { PREFIX_TABLE(PREFIX_VEX_0F3ACE) },
9120     { PREFIX_TABLE(PREFIX_VEX_0F3ACF) },
9121     /* d0 */
9122     { Bad_Opcode },
9123     { Bad_Opcode },
9124     { Bad_Opcode },
9125     { Bad_Opcode },
9126     { Bad_Opcode },
9127     { Bad_Opcode },
9128     { Bad_Opcode },
9129     { Bad_Opcode },
9130     /* d8 */
9131     { Bad_Opcode },
9132     { Bad_Opcode },
9133     { Bad_Opcode },
9134     { Bad_Opcode },
9135     { Bad_Opcode },
9136     { Bad_Opcode },
9137     { Bad_Opcode },
9138     { PREFIX_TABLE (PREFIX_VEX_0F3ADF) },
9139     /* e0 */
9140     { Bad_Opcode },
9141     { Bad_Opcode },
9142     { Bad_Opcode },
9143     { Bad_Opcode },
9144     { Bad_Opcode },
9145     { Bad_Opcode },
9146     { Bad_Opcode },
9147     { Bad_Opcode },
9148     /* e8 */
9149     { Bad_Opcode },
9150     { Bad_Opcode },
9151     { Bad_Opcode },
9152     { Bad_Opcode },
9153     { Bad_Opcode },
9154     { Bad_Opcode },
9155     { Bad_Opcode },
9156     { Bad_Opcode },
9157     /* f0 */
9158     { PREFIX_TABLE (PREFIX_VEX_0F3AF0) },
9159     { Bad_Opcode },
9160     { Bad_Opcode },
9161     { Bad_Opcode },
9162     { Bad_Opcode },
9163     { Bad_Opcode },
9164     { Bad_Opcode },
9165     { Bad_Opcode },
9166     /* f8 */
9167     { Bad_Opcode },
9168     { Bad_Opcode },
9169     { Bad_Opcode },
9170     { Bad_Opcode },
9171     { Bad_Opcode },
9172     { Bad_Opcode },
9173     { Bad_Opcode },
9174     { Bad_Opcode },
9175   },
9176 };
9177
9178 #include "i386-dis-evex.h"
9179
9180 static const struct dis386 vex_len_table[][2] = {
9181   /* VEX_LEN_0F12_P_0_M_0 / VEX_LEN_0F12_P_2_M_0 */
9182   {
9183     { "vmovlpX",        { XM, Vex128, EXq }, 0 },
9184   },
9185
9186   /* VEX_LEN_0F12_P_0_M_1 */
9187   {
9188     { "vmovhlps",       { XM, Vex128, EXq }, 0 },
9189   },
9190
9191   /* VEX_LEN_0F13_M_0 */
9192   {
9193     { "vmovlpX",        { EXq, XM }, PREFIX_OPCODE },
9194   },
9195
9196   /* VEX_LEN_0F16_P_0_M_0 / VEX_LEN_0F16_P_2_M_0 */
9197   {
9198     { "vmovhpX",        { XM, Vex128, EXq }, 0 },
9199   },
9200
9201   /* VEX_LEN_0F16_P_0_M_1 */
9202   {
9203     { "vmovlhps",       { XM, Vex128, EXq }, 0 },
9204   },
9205
9206   /* VEX_LEN_0F17_M_0 */
9207   {
9208     { "vmovhpX",        { EXq, XM }, PREFIX_OPCODE },
9209   },
9210
9211   /* VEX_LEN_0F41_P_0 */
9212   {
9213     { Bad_Opcode },
9214     { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) },
9215   },
9216   /* VEX_LEN_0F41_P_2 */
9217   {
9218     { Bad_Opcode },
9219     { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) },
9220   },
9221   /* VEX_LEN_0F42_P_0 */
9222   {
9223     { Bad_Opcode },
9224     { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) },
9225   },
9226   /* VEX_LEN_0F42_P_2 */
9227   {
9228     { Bad_Opcode },
9229     { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) },
9230   },
9231   /* VEX_LEN_0F44_P_0 */
9232   {
9233     { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) },
9234   },
9235   /* VEX_LEN_0F44_P_2 */
9236   {
9237     { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) },
9238   },
9239   /* VEX_LEN_0F45_P_0 */
9240   {
9241     { Bad_Opcode },
9242     { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) },
9243   },
9244   /* VEX_LEN_0F45_P_2 */
9245   {
9246     { Bad_Opcode },
9247     { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) },
9248   },
9249   /* VEX_LEN_0F46_P_0 */
9250   {
9251     { Bad_Opcode },
9252     { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) },
9253   },
9254   /* VEX_LEN_0F46_P_2 */
9255   {
9256     { Bad_Opcode },
9257     { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) },
9258   },
9259   /* VEX_LEN_0F47_P_0 */
9260   {
9261     { Bad_Opcode },
9262     { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) },
9263   },
9264   /* VEX_LEN_0F47_P_2 */
9265   {
9266     { Bad_Opcode },
9267     { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) },
9268   },
9269   /* VEX_LEN_0F4A_P_0 */
9270   {
9271     { Bad_Opcode },
9272     { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) },
9273   },
9274   /* VEX_LEN_0F4A_P_2 */
9275   {
9276     { Bad_Opcode },
9277     { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) },
9278   },
9279   /* VEX_LEN_0F4B_P_0 */
9280   {
9281     { Bad_Opcode },
9282     { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) },
9283   },
9284   /* VEX_LEN_0F4B_P_2 */
9285   {
9286     { Bad_Opcode },
9287     { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) },
9288   },
9289
9290   /* VEX_LEN_0F6E_P_2 */
9291   {
9292     { "vmovK",          { XMScalar, Edq }, 0 },
9293   },
9294
9295   /* VEX_LEN_0F77_P_1 */
9296   {
9297     { "vzeroupper",     { XX }, 0 },
9298     { "vzeroall",       { XX }, 0 },
9299   },
9300
9301   /* VEX_LEN_0F7E_P_1 */
9302   {
9303     { "vmovq",          { XMScalar, EXxmm_mq }, 0 },
9304   },
9305
9306   /* VEX_LEN_0F7E_P_2 */
9307   {
9308     { "vmovK",          { Edq, XMScalar }, 0 },
9309   },
9310
9311   /* VEX_LEN_0F90_P_0 */
9312   {
9313     { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) },
9314   },
9315
9316   /* VEX_LEN_0F90_P_2 */
9317   {
9318     { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) },
9319   },
9320
9321   /* VEX_LEN_0F91_P_0 */
9322   {
9323     { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) },
9324   },
9325
9326   /* VEX_LEN_0F91_P_2 */
9327   {
9328     { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) },
9329   },
9330
9331   /* VEX_LEN_0F92_P_0 */
9332   {
9333     { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) },
9334   },
9335
9336   /* VEX_LEN_0F92_P_2 */
9337   {
9338     { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) },
9339   },
9340
9341   /* VEX_LEN_0F92_P_3 */
9342   {
9343     { MOD_TABLE (MOD_VEX_0F92_P_3_LEN_0) },
9344   },
9345
9346   /* VEX_LEN_0F93_P_0 */
9347   {
9348     { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) },
9349   },
9350
9351   /* VEX_LEN_0F93_P_2 */
9352   {
9353     { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) },
9354   },
9355
9356   /* VEX_LEN_0F93_P_3 */
9357   {
9358     { MOD_TABLE (MOD_VEX_0F93_P_3_LEN_0) },
9359   },
9360
9361   /* VEX_LEN_0F98_P_0 */
9362   {
9363     { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) },
9364   },
9365
9366   /* VEX_LEN_0F98_P_2 */
9367   {
9368     { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) },
9369   },
9370
9371   /* VEX_LEN_0F99_P_0 */
9372   {
9373     { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) },
9374   },
9375
9376   /* VEX_LEN_0F99_P_2 */
9377   {
9378     { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0) },
9379   },
9380
9381   /* VEX_LEN_0FAE_R_2_M_0 */
9382   {
9383     { "vldmxcsr",       { Md }, 0 },
9384   },
9385
9386   /* VEX_LEN_0FAE_R_3_M_0 */
9387   {
9388     { "vstmxcsr",       { Md }, 0 },
9389   },
9390
9391   /* VEX_LEN_0FC4_P_2 */
9392   {
9393     { "vpinsrw",        { XM, Vex128, Edqw, Ib }, 0 },
9394   },
9395
9396   /* VEX_LEN_0FC5_P_2 */
9397   {
9398     { "vpextrw",        { Gdq, XS, Ib }, 0 },
9399   },
9400
9401   /* VEX_LEN_0FD6_P_2 */
9402   {
9403     { "vmovq",          { EXqVexScalarS, XMScalar }, 0 },
9404   },
9405
9406   /* VEX_LEN_0FF7_P_2 */
9407   {
9408     { "vmaskmovdqu",    { XM, XS }, 0 },
9409   },
9410
9411   /* VEX_LEN_0F3816_P_2 */
9412   {
9413     { Bad_Opcode },
9414     { VEX_W_TABLE (VEX_W_0F3816_P_2) },
9415   },
9416
9417   /* VEX_LEN_0F3819_P_2 */
9418   {
9419     { Bad_Opcode },
9420     { VEX_W_TABLE (VEX_W_0F3819_P_2) },
9421   },
9422
9423   /* VEX_LEN_0F381A_P_2_M_0 */
9424   {
9425     { Bad_Opcode },
9426     { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) },
9427   },
9428
9429   /* VEX_LEN_0F3836_P_2 */
9430   {
9431     { Bad_Opcode },
9432     { VEX_W_TABLE (VEX_W_0F3836_P_2) },
9433   },
9434
9435   /* VEX_LEN_0F3841_P_2 */
9436   {
9437     { "vphminposuw",    { XM, EXx }, 0 },
9438   },
9439
9440   /* VEX_LEN_0F385A_P_2_M_0 */
9441   {
9442     { Bad_Opcode },
9443     { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) },
9444   },
9445
9446   /* VEX_LEN_0F38DB_P_2 */
9447   {
9448     { "vaesimc",        { XM, EXx }, 0 },
9449   },
9450
9451   /* VEX_LEN_0F38F2_P_0 */
9452   {
9453     { "andnS",          { Gdq, VexGdq, Edq }, 0 },
9454   },
9455
9456   /* VEX_LEN_0F38F3_R_1_P_0 */
9457   {
9458     { "blsrS",          { VexGdq, Edq }, 0 },
9459   },
9460
9461   /* VEX_LEN_0F38F3_R_2_P_0 */
9462   {
9463     { "blsmskS",        { VexGdq, Edq }, 0 },
9464   },
9465
9466   /* VEX_LEN_0F38F3_R_3_P_0 */
9467   {
9468     { "blsiS",          { VexGdq, Edq }, 0 },
9469   },
9470
9471   /* VEX_LEN_0F38F5_P_0 */
9472   {
9473     { "bzhiS",          { Gdq, Edq, VexGdq }, 0 },
9474   },
9475
9476   /* VEX_LEN_0F38F5_P_1 */
9477   {
9478     { "pextS",          { Gdq, VexGdq, Edq }, 0 },
9479   },
9480
9481   /* VEX_LEN_0F38F5_P_3 */
9482   {
9483     { "pdepS",          { Gdq, VexGdq, Edq }, 0 },
9484   },
9485
9486   /* VEX_LEN_0F38F6_P_3 */
9487   {
9488     { "mulxS",          { Gdq, VexGdq, Edq }, 0 },
9489   },
9490
9491   /* VEX_LEN_0F38F7_P_0 */
9492   {
9493     { "bextrS",         { Gdq, Edq, VexGdq }, 0 },
9494   },
9495
9496   /* VEX_LEN_0F38F7_P_1 */
9497   {
9498     { "sarxS",          { Gdq, Edq, VexGdq }, 0 },
9499   },
9500
9501   /* VEX_LEN_0F38F7_P_2 */
9502   {
9503     { "shlxS",          { Gdq, Edq, VexGdq }, 0 },
9504   },
9505
9506   /* VEX_LEN_0F38F7_P_3 */
9507   {
9508     { "shrxS",          { Gdq, Edq, VexGdq }, 0 },
9509   },
9510
9511   /* VEX_LEN_0F3A00_P_2 */
9512   {
9513     { Bad_Opcode },
9514     { VEX_W_TABLE (VEX_W_0F3A00_P_2) },
9515   },
9516
9517   /* VEX_LEN_0F3A01_P_2 */
9518   {
9519     { Bad_Opcode },
9520     { VEX_W_TABLE (VEX_W_0F3A01_P_2) },
9521   },
9522
9523   /* VEX_LEN_0F3A06_P_2 */
9524   {
9525     { Bad_Opcode },
9526     { VEX_W_TABLE (VEX_W_0F3A06_P_2) },
9527   },
9528
9529   /* VEX_LEN_0F3A14_P_2 */
9530   {
9531     { "vpextrb",        { Edqb, XM, Ib }, 0 },
9532   },
9533
9534   /* VEX_LEN_0F3A15_P_2 */
9535   {
9536     { "vpextrw",        { Edqw, XM, Ib }, 0 },
9537   },
9538
9539   /* VEX_LEN_0F3A16_P_2  */
9540   {
9541     { "vpextrK",        { Edq, XM, Ib }, 0 },
9542   },
9543
9544   /* VEX_LEN_0F3A17_P_2 */
9545   {
9546     { "vextractps",     { Edqd, XM, Ib }, 0 },
9547   },
9548
9549   /* VEX_LEN_0F3A18_P_2 */
9550   {
9551     { Bad_Opcode },
9552     { VEX_W_TABLE (VEX_W_0F3A18_P_2) },
9553   },
9554
9555   /* VEX_LEN_0F3A19_P_2 */
9556   {
9557     { Bad_Opcode },
9558     { VEX_W_TABLE (VEX_W_0F3A19_P_2) },
9559   },
9560
9561   /* VEX_LEN_0F3A20_P_2 */
9562   {
9563     { "vpinsrb",        { XM, Vex128, Edqb, Ib }, 0 },
9564   },
9565
9566   /* VEX_LEN_0F3A21_P_2 */
9567   {
9568     { "vinsertps",      { XM, Vex128, EXd, Ib }, 0 },
9569   },
9570
9571   /* VEX_LEN_0F3A22_P_2 */
9572   {
9573     { "vpinsrK",        { XM, Vex128, Edq, Ib }, 0 },
9574   },
9575
9576   /* VEX_LEN_0F3A30_P_2 */
9577   {
9578     { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) },
9579   },
9580
9581   /* VEX_LEN_0F3A31_P_2 */
9582   {
9583     { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0) },
9584   },
9585
9586   /* VEX_LEN_0F3A32_P_2 */
9587   {
9588     { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) },
9589   },
9590
9591   /* VEX_LEN_0F3A33_P_2 */
9592   {
9593     { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0) },
9594   },
9595
9596   /* VEX_LEN_0F3A38_P_2 */
9597   {
9598     { Bad_Opcode },
9599     { VEX_W_TABLE (VEX_W_0F3A38_P_2) },
9600   },
9601
9602   /* VEX_LEN_0F3A39_P_2 */
9603   {
9604     { Bad_Opcode },
9605     { VEX_W_TABLE (VEX_W_0F3A39_P_2) },
9606   },
9607
9608   /* VEX_LEN_0F3A41_P_2 */
9609   {
9610     { "vdppd",          { XM, Vex128, EXx, Ib }, 0 },
9611   },
9612
9613   /* VEX_LEN_0F3A46_P_2 */
9614   {
9615     { Bad_Opcode },
9616     { VEX_W_TABLE (VEX_W_0F3A46_P_2) },
9617   },
9618
9619   /* VEX_LEN_0F3A60_P_2 */
9620   {
9621     { "vpcmpestrm",     { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 },
9622   },
9623
9624   /* VEX_LEN_0F3A61_P_2 */
9625   {
9626     { "vpcmpestri",     { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 },
9627   },
9628
9629   /* VEX_LEN_0F3A62_P_2 */
9630   {
9631     { "vpcmpistrm",     { XM, EXx, Ib }, 0 },
9632   },
9633
9634   /* VEX_LEN_0F3A63_P_2 */
9635   {
9636     { "vpcmpistri",     { XM, EXx, Ib }, 0 },
9637   },
9638
9639   /* VEX_LEN_0F3A6A_P_2 */
9640   {
9641     { "vfmaddss",       { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
9642   },
9643
9644   /* VEX_LEN_0F3A6B_P_2 */
9645   {
9646     { "vfmaddsd",       { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
9647   },
9648
9649   /* VEX_LEN_0F3A6E_P_2 */
9650   {
9651     { "vfmsubss",       { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
9652   },
9653
9654   /* VEX_LEN_0F3A6F_P_2 */
9655   {
9656     { "vfmsubsd",       { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
9657   },
9658
9659   /* VEX_LEN_0F3A7A_P_2 */
9660   {
9661     { "vfnmaddss",      { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
9662   },
9663
9664   /* VEX_LEN_0F3A7B_P_2 */
9665   {
9666     { "vfnmaddsd",      { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
9667   },
9668
9669   /* VEX_LEN_0F3A7E_P_2 */
9670   {
9671     { "vfnmsubss",      { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
9672   },
9673
9674   /* VEX_LEN_0F3A7F_P_2 */
9675   {
9676     { "vfnmsubsd",      { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
9677   },
9678
9679   /* VEX_LEN_0F3ADF_P_2 */
9680   {
9681     { "vaeskeygenassist", { XM, EXx, Ib }, 0 },
9682   },
9683
9684   /* VEX_LEN_0F3AF0_P_3 */
9685   {
9686     { "rorxS",          { Gdq, Edq, Ib }, 0 },
9687   },
9688
9689   /* VEX_LEN_0FXOP_08_CC */
9690   {
9691      { "vpcomb",        { XM, Vex128, EXx, VPCOM }, 0 },
9692   },
9693
9694   /* VEX_LEN_0FXOP_08_CD */
9695   {
9696      { "vpcomw",        { XM, Vex128, EXx, VPCOM }, 0 },
9697   },
9698
9699   /* VEX_LEN_0FXOP_08_CE */
9700   {
9701      { "vpcomd",        { XM, Vex128, EXx, VPCOM }, 0 },
9702   },
9703
9704   /* VEX_LEN_0FXOP_08_CF */
9705   {
9706      { "vpcomq",        { XM, Vex128, EXx, VPCOM }, 0 },
9707   },
9708
9709   /* VEX_LEN_0FXOP_08_EC */
9710   {
9711      { "vpcomub",       { XM, Vex128, EXx, VPCOM }, 0 },
9712   },
9713
9714   /* VEX_LEN_0FXOP_08_ED */
9715   {
9716      { "vpcomuw",       { XM, Vex128, EXx, VPCOM }, 0 },
9717   },
9718
9719   /* VEX_LEN_0FXOP_08_EE */
9720   {
9721      { "vpcomud",       { XM, Vex128, EXx, VPCOM }, 0 },
9722   },
9723
9724   /* VEX_LEN_0FXOP_08_EF */
9725   {
9726      { "vpcomuq",       { XM, Vex128, EXx, VPCOM }, 0 },
9727   },
9728
9729   /* VEX_LEN_0FXOP_09_80 */
9730   {
9731     { "vfrczps",        { XM, EXxmm }, 0 },
9732     { "vfrczps",        { XM, EXymmq }, 0 },
9733   },
9734
9735   /* VEX_LEN_0FXOP_09_81 */
9736   {
9737     { "vfrczpd",        { XM, EXxmm }, 0 },
9738     { "vfrczpd",        { XM, EXymmq }, 0 },
9739   },
9740 };
9741
9742 #include "i386-dis-evex-len.h"
9743
9744 static const struct dis386 vex_w_table[][2] = {
9745   {
9746     /* VEX_W_0F41_P_0_LEN_1 */
9747     { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1) },
9748     { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1) },
9749   },
9750   {
9751     /* VEX_W_0F41_P_2_LEN_1 */
9752     { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1) },
9753     { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1) }
9754   },
9755   {
9756     /* VEX_W_0F42_P_0_LEN_1 */
9757     { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1) },
9758     { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1) },
9759   },
9760   {
9761     /* VEX_W_0F42_P_2_LEN_1 */
9762     { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1) },
9763     { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1) },
9764   },
9765   {
9766     /* VEX_W_0F44_P_0_LEN_0 */
9767     { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1) },
9768     { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1) },
9769   },
9770   {
9771     /* VEX_W_0F44_P_2_LEN_0 */
9772     { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1) },
9773     { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1) },
9774   },
9775   {
9776     /* VEX_W_0F45_P_0_LEN_1 */
9777     { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1) },
9778     { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1) },
9779   },
9780   {
9781     /* VEX_W_0F45_P_2_LEN_1 */
9782     { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1) },
9783     { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1) },
9784   },
9785   {
9786     /* VEX_W_0F46_P_0_LEN_1 */
9787     { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1) },
9788     { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1) },
9789   },
9790   {
9791     /* VEX_W_0F46_P_2_LEN_1 */
9792     { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1) },
9793     { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1) },
9794   },
9795   {
9796     /* VEX_W_0F47_P_0_LEN_1 */
9797     { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1) },
9798     { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1) },
9799   },
9800   {
9801     /* VEX_W_0F47_P_2_LEN_1 */
9802     { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1) },
9803     { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1) },
9804   },
9805   {
9806     /* VEX_W_0F4A_P_0_LEN_1 */
9807     { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1) },
9808     { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1) },
9809   },
9810   {
9811     /* VEX_W_0F4A_P_2_LEN_1 */
9812     { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1) },
9813     { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1) },
9814   },
9815   {
9816     /* VEX_W_0F4B_P_0_LEN_1 */
9817     { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1) },
9818     { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1) },
9819   },
9820   {
9821     /* VEX_W_0F4B_P_2_LEN_1 */
9822     { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1) },
9823   },
9824   {
9825     /* VEX_W_0F90_P_0_LEN_0 */
9826     { "kmovw",          { MaskG, MaskE }, 0 },
9827     { "kmovq",          { MaskG, MaskE }, 0 },
9828   },
9829   {
9830     /* VEX_W_0F90_P_2_LEN_0 */
9831     { "kmovb",          { MaskG, MaskBDE }, 0 },
9832     { "kmovd",          { MaskG, MaskBDE }, 0 },
9833   },
9834   {
9835     /* VEX_W_0F91_P_0_LEN_0 */
9836     { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0) },
9837     { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0) },
9838   },
9839   {
9840     /* VEX_W_0F91_P_2_LEN_0 */
9841     { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0) },
9842     { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0) },
9843   },
9844   {
9845     /* VEX_W_0F92_P_0_LEN_0 */
9846     { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0) },
9847   },
9848   {
9849     /* VEX_W_0F92_P_2_LEN_0 */
9850     { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0) },
9851   },
9852   {
9853     /* VEX_W_0F93_P_0_LEN_0 */
9854     { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0) },
9855   },
9856   {
9857     /* VEX_W_0F93_P_2_LEN_0 */
9858     { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0) },
9859   },
9860   {
9861     /* VEX_W_0F98_P_0_LEN_0 */
9862     { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0) },
9863     { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0) },
9864   },
9865   {
9866     /* VEX_W_0F98_P_2_LEN_0 */
9867     { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0) },
9868     { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0) },
9869   },
9870   {
9871     /* VEX_W_0F99_P_0_LEN_0 */
9872     { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0) },
9873     { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0) },
9874   },
9875   {
9876     /* VEX_W_0F99_P_2_LEN_0 */
9877     { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0) },
9878     { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0) },
9879   },
9880   {
9881     /* VEX_W_0F380C_P_2  */
9882     { "vpermilps",      { XM, Vex, EXx }, 0 },
9883   },
9884   {
9885     /* VEX_W_0F380D_P_2  */
9886     { "vpermilpd",      { XM, Vex, EXx }, 0 },
9887   },
9888   {
9889     /* VEX_W_0F380E_P_2  */
9890     { "vtestps",        { XM, EXx }, 0 },
9891   },
9892   {
9893     /* VEX_W_0F380F_P_2  */
9894     { "vtestpd",        { XM, EXx }, 0 },
9895   },
9896   {
9897     /* VEX_W_0F3813_P_2 */
9898     { "vcvtph2ps", { XM, EXxmmq }, 0 },
9899   },
9900   {
9901     /* VEX_W_0F3816_P_2  */
9902     { "vpermps",        { XM, Vex, EXx }, 0 },
9903   },
9904   {
9905     /* VEX_W_0F3818_P_2 */
9906     { "vbroadcastss",   { XM, EXxmm_md }, 0 },
9907   },
9908   {
9909     /* VEX_W_0F3819_P_2 */
9910     { "vbroadcastsd",   { XM, EXxmm_mq }, 0 },
9911   },
9912   {
9913     /* VEX_W_0F381A_P_2_M_0 */
9914     { "vbroadcastf128", { XM, Mxmm }, 0 },
9915   },
9916   {
9917     /* VEX_W_0F382C_P_2_M_0 */
9918     { "vmaskmovps",     { XM, Vex, Mx }, 0 },
9919   },
9920   {
9921     /* VEX_W_0F382D_P_2_M_0 */
9922     { "vmaskmovpd",     { XM, Vex, Mx }, 0 },
9923   },
9924   {
9925     /* VEX_W_0F382E_P_2_M_0 */
9926     { "vmaskmovps",     { Mx, Vex, XM }, 0 },
9927   },
9928   {
9929     /* VEX_W_0F382F_P_2_M_0 */
9930     { "vmaskmovpd",     { Mx, Vex, XM }, 0 },
9931   },
9932   {
9933     /* VEX_W_0F3836_P_2  */
9934     { "vpermd",         { XM, Vex, EXx }, 0 },
9935   },
9936   {
9937     /* VEX_W_0F3846_P_2 */
9938     { "vpsravd",        { XM, Vex, EXx }, 0 },
9939   },
9940   {
9941     /* VEX_W_0F3858_P_2 */
9942     { "vpbroadcastd", { XM, EXxmm_md }, 0 },
9943   },
9944   {
9945     /* VEX_W_0F3859_P_2 */
9946     { "vpbroadcastq",   { XM, EXxmm_mq }, 0 },
9947   },
9948   {
9949     /* VEX_W_0F385A_P_2_M_0 */
9950     { "vbroadcasti128", { XM, Mxmm }, 0 },
9951   },
9952   {
9953     /* VEX_W_0F3878_P_2 */
9954     { "vpbroadcastb",   { XM, EXxmm_mb }, 0 },
9955   },
9956   {
9957     /* VEX_W_0F3879_P_2 */
9958     { "vpbroadcastw",   { XM, EXxmm_mw }, 0 },
9959   },
9960   {
9961     /* VEX_W_0F38CF_P_2 */
9962     { "vgf2p8mulb", { XM, Vex, EXx }, 0 },
9963   },
9964   {
9965     /* VEX_W_0F3A00_P_2 */
9966     { Bad_Opcode },
9967     { "vpermq",         { XM, EXx, Ib }, 0 },
9968   },
9969   {
9970     /* VEX_W_0F3A01_P_2 */
9971     { Bad_Opcode },
9972     { "vpermpd",        { XM, EXx, Ib }, 0 },
9973   },
9974   {
9975     /* VEX_W_0F3A02_P_2 */
9976     { "vpblendd",       { XM, Vex, EXx, Ib }, 0 },
9977   },
9978   {
9979     /* VEX_W_0F3A04_P_2 */
9980     { "vpermilps",      { XM, EXx, Ib }, 0 },
9981   },
9982   {
9983     /* VEX_W_0F3A05_P_2 */
9984     { "vpermilpd",      { XM, EXx, Ib }, 0 },
9985   },
9986   {
9987     /* VEX_W_0F3A06_P_2 */
9988     { "vperm2f128",     { XM, Vex256, EXx, Ib }, 0 },
9989   },
9990   {
9991     /* VEX_W_0F3A18_P_2 */
9992     { "vinsertf128",    { XM, Vex256, EXxmm, Ib }, 0 },
9993   },
9994   {
9995     /* VEX_W_0F3A19_P_2 */
9996     { "vextractf128",   { EXxmm, XM, Ib }, 0 },
9997   },
9998   {
9999     /* VEX_W_0F3A1D_P_2 */
10000     { "vcvtps2ph", { EXxmmq, XM, EXxEVexS, Ib }, 0 },
10001   },
10002   {
10003     /* VEX_W_0F3A30_P_2_LEN_0 */
10004     { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0) },
10005     { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0) },
10006   },
10007   {
10008     /* VEX_W_0F3A31_P_2_LEN_0 */
10009     { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0) },
10010     { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0) },
10011   },
10012   {
10013     /* VEX_W_0F3A32_P_2_LEN_0 */
10014     { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0) },
10015     { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0) },
10016   },
10017   {
10018     /* VEX_W_0F3A33_P_2_LEN_0 */
10019     { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0) },
10020     { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0) },
10021   },
10022   {
10023     /* VEX_W_0F3A38_P_2 */
10024     { "vinserti128",    { XM, Vex256, EXxmm, Ib }, 0 },
10025   },
10026   {
10027     /* VEX_W_0F3A39_P_2 */
10028     { "vextracti128",   { EXxmm, XM, Ib }, 0 },
10029   },
10030   {
10031     /* VEX_W_0F3A46_P_2 */
10032     { "vperm2i128",     { XM, Vex256, EXx, Ib }, 0 },
10033   },
10034   {
10035     /* VEX_W_0F3A48_P_2 */
10036     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
10037     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
10038   },
10039   {
10040     /* VEX_W_0F3A49_P_2 */
10041     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
10042     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
10043   },
10044   {
10045     /* VEX_W_0F3A4A_P_2 */
10046     { "vblendvps",      { XM, Vex, EXx, XMVexI4 }, 0 },
10047   },
10048   {
10049     /* VEX_W_0F3A4B_P_2 */
10050     { "vblendvpd",      { XM, Vex, EXx, XMVexI4 }, 0 },
10051   },
10052   {
10053     /* VEX_W_0F3A4C_P_2 */
10054     { "vpblendvb",      { XM, Vex, EXx, XMVexI4 }, 0 },
10055   },
10056   {
10057     /* VEX_W_0F3ACE_P_2 */
10058     { Bad_Opcode },
10059     { "vgf2p8affineqb", { XM, Vex, EXx, Ib }, 0 },
10060   },
10061   {
10062     /* VEX_W_0F3ACF_P_2 */
10063     { Bad_Opcode },
10064     { "vgf2p8affineinvqb",  { XM, Vex, EXx, Ib }, 0 },
10065   },
10066
10067 #include "i386-dis-evex-w.h"
10068 };
10069
10070 static const struct dis386 mod_table[][2] = {
10071   {
10072     /* MOD_8D */
10073     { "leaS",           { Gv, M }, 0 },
10074   },
10075   {
10076     /* MOD_C6_REG_7 */
10077     { Bad_Opcode },
10078     { RM_TABLE (RM_C6_REG_7) },
10079   },
10080   {
10081     /* MOD_C7_REG_7 */
10082     { Bad_Opcode },
10083     { RM_TABLE (RM_C7_REG_7) },
10084   },
10085   {
10086     /* MOD_FF_REG_3 */
10087     { "{l|}call^", { indirEp }, 0 },
10088   },
10089   {
10090     /* MOD_FF_REG_5 */
10091     { "{l|}jmp^", { indirEp }, 0 },
10092   },
10093   {
10094     /* MOD_0F01_REG_0 */
10095     { X86_64_TABLE (X86_64_0F01_REG_0) },
10096     { RM_TABLE (RM_0F01_REG_0) },
10097   },
10098   {
10099     /* MOD_0F01_REG_1 */
10100     { X86_64_TABLE (X86_64_0F01_REG_1) },
10101     { RM_TABLE (RM_0F01_REG_1) },
10102   },
10103   {
10104     /* MOD_0F01_REG_2 */
10105     { X86_64_TABLE (X86_64_0F01_REG_2) },
10106     { RM_TABLE (RM_0F01_REG_2) },
10107   },
10108   {
10109     /* MOD_0F01_REG_3 */
10110     { X86_64_TABLE (X86_64_0F01_REG_3) },
10111     { RM_TABLE (RM_0F01_REG_3) },
10112   },
10113   {
10114     /* MOD_0F01_REG_5 */
10115     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_0) },
10116     { RM_TABLE (RM_0F01_REG_5_MOD_3) },
10117   },
10118   {
10119     /* MOD_0F01_REG_7 */
10120     { "invlpg",         { Mb }, 0 },
10121     { RM_TABLE (RM_0F01_REG_7_MOD_3) },
10122   },
10123   {
10124     /* MOD_0F12_PREFIX_0 */
10125     { "movlpX",         { XM, EXq }, 0 },
10126     { "movhlps",        { XM, EXq }, 0 },
10127   },
10128   {
10129     /* MOD_0F12_PREFIX_2 */
10130     { "movlpX", { XM, EXq }, 0 },
10131   },
10132   {
10133     /* MOD_0F13 */
10134     { "movlpX",         { EXq, XM }, PREFIX_OPCODE },
10135   },
10136   {
10137     /* MOD_0F16_PREFIX_0 */
10138     { "movhpX",         { XM, EXq }, 0 },
10139     { "movlhps",        { XM, EXq }, 0 },
10140   },
10141   {
10142     /* MOD_0F16_PREFIX_2 */
10143     { "movhpX", { XM, EXq }, 0 },
10144   },
10145   {
10146     /* MOD_0F17 */
10147     { "movhpX",         { EXq, XM }, PREFIX_OPCODE },
10148   },
10149   {
10150     /* MOD_0F18_REG_0 */
10151     { "prefetchnta",    { Mb }, 0 },
10152   },
10153   {
10154     /* MOD_0F18_REG_1 */
10155     { "prefetcht0",     { Mb }, 0 },
10156   },
10157   {
10158     /* MOD_0F18_REG_2 */
10159     { "prefetcht1",     { Mb }, 0 },
10160   },
10161   {
10162     /* MOD_0F18_REG_3 */
10163     { "prefetcht2",     { Mb }, 0 },
10164   },
10165   {
10166     /* MOD_0F18_REG_4 */
10167     { "nop/reserved",   { Mb }, 0 },
10168   },
10169   {
10170     /* MOD_0F18_REG_5 */
10171     { "nop/reserved",   { Mb }, 0 },
10172   },
10173   {
10174     /* MOD_0F18_REG_6 */
10175     { "nop/reserved",   { Mb }, 0 },
10176   },
10177   {
10178     /* MOD_0F18_REG_7 */
10179     { "nop/reserved",   { Mb }, 0 },
10180   },
10181   {
10182     /* MOD_0F1A_PREFIX_0 */
10183     { "bndldx",         { Gbnd, Mv_bnd }, 0 },
10184     { "nopQ",           { Ev }, 0 },
10185   },
10186   {
10187     /* MOD_0F1B_PREFIX_0 */
10188     { "bndstx",         { Mv_bnd, Gbnd }, 0 },
10189     { "nopQ",           { Ev }, 0 },
10190   },
10191   {
10192     /* MOD_0F1B_PREFIX_1 */
10193     { "bndmk",          { Gbnd, Mv_bnd }, 0 },
10194     { "nopQ",           { Ev }, 0 },
10195   },
10196   {
10197     /* MOD_0F1C_PREFIX_0 */
10198     { REG_TABLE (REG_0F1C_P_0_MOD_0) },
10199     { "nopQ",           { Ev }, 0 },
10200   },
10201   {
10202     /* MOD_0F1E_PREFIX_1 */
10203     { "nopQ",           { Ev }, 0 },
10204     { REG_TABLE (REG_0F1E_P_1_MOD_3) },
10205   },
10206   {
10207     /* MOD_0F24 */
10208     { Bad_Opcode },
10209     { "movL",           { Rd, Td }, 0 },
10210   },
10211   {
10212     /* MOD_0F26 */
10213     { Bad_Opcode },
10214     { "movL",           { Td, Rd }, 0 },
10215   },
10216   {
10217     /* MOD_0F2B_PREFIX_0 */
10218     {"movntps",         { Mx, XM }, PREFIX_OPCODE },
10219   },
10220   {
10221     /* MOD_0F2B_PREFIX_1 */
10222     {"movntss",         { Md, XM }, PREFIX_OPCODE },
10223   },
10224   {
10225     /* MOD_0F2B_PREFIX_2 */
10226     {"movntpd",         { Mx, XM }, PREFIX_OPCODE },
10227   },
10228   {
10229     /* MOD_0F2B_PREFIX_3 */
10230     {"movntsd",         { Mq, XM }, PREFIX_OPCODE },
10231   },
10232   {
10233     /* MOD_0F50 */
10234     { Bad_Opcode },
10235     { "movmskpX",       { Gdq, XS }, PREFIX_OPCODE },
10236   },
10237   {
10238     /* MOD_0F71_REG_2 */
10239     { Bad_Opcode },
10240     { "psrlw",          { MS, Ib }, 0 },
10241   },
10242   {
10243     /* MOD_0F71_REG_4 */
10244     { Bad_Opcode },
10245     { "psraw",          { MS, Ib }, 0 },
10246   },
10247   {
10248     /* MOD_0F71_REG_6 */
10249     { Bad_Opcode },
10250     { "psllw",          { MS, Ib }, 0 },
10251   },
10252   {
10253     /* MOD_0F72_REG_2 */
10254     { Bad_Opcode },
10255     { "psrld",          { MS, Ib }, 0 },
10256   },
10257   {
10258     /* MOD_0F72_REG_4 */
10259     { Bad_Opcode },
10260     { "psrad",          { MS, Ib }, 0 },
10261   },
10262   {
10263     /* MOD_0F72_REG_6 */
10264     { Bad_Opcode },
10265     { "pslld",          { MS, Ib }, 0 },
10266   },
10267   {
10268     /* MOD_0F73_REG_2 */
10269     { Bad_Opcode },
10270     { "psrlq",          { MS, Ib }, 0 },
10271   },
10272   {
10273     /* MOD_0F73_REG_3 */
10274     { Bad_Opcode },
10275     { PREFIX_TABLE (PREFIX_0F73_REG_3) },
10276   },
10277   {
10278     /* MOD_0F73_REG_6 */
10279     { Bad_Opcode },
10280     { "psllq",          { MS, Ib }, 0 },
10281   },
10282   {
10283     /* MOD_0F73_REG_7 */
10284     { Bad_Opcode },
10285     { PREFIX_TABLE (PREFIX_0F73_REG_7) },
10286   },
10287   {
10288     /* MOD_0FAE_REG_0 */
10289     { "fxsave",         { FXSAVE }, 0 },
10290     { PREFIX_TABLE (PREFIX_0FAE_REG_0_MOD_3) },
10291   },
10292   {
10293     /* MOD_0FAE_REG_1 */
10294     { "fxrstor",        { FXSAVE }, 0 },
10295     { PREFIX_TABLE (PREFIX_0FAE_REG_1_MOD_3) },
10296   },
10297   {
10298     /* MOD_0FAE_REG_2 */
10299     { "ldmxcsr",        { Md }, 0 },
10300     { PREFIX_TABLE (PREFIX_0FAE_REG_2_MOD_3) },
10301   },
10302   {
10303     /* MOD_0FAE_REG_3 */
10304     { "stmxcsr",        { Md }, 0 },
10305     { PREFIX_TABLE (PREFIX_0FAE_REG_3_MOD_3) },
10306   },
10307   {
10308     /* MOD_0FAE_REG_4 */
10309     { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_0) },
10310     { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_3) },
10311   },
10312   {
10313     /* MOD_0FAE_REG_5 */
10314     { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_0) },
10315     { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_3) },
10316   },
10317   {
10318     /* MOD_0FAE_REG_6 */
10319     { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_0) },
10320     { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_3) },
10321   },
10322   {
10323     /* MOD_0FAE_REG_7 */
10324     { PREFIX_TABLE (PREFIX_0FAE_REG_7_MOD_0) },
10325     { RM_TABLE (RM_0FAE_REG_7_MOD_3) },
10326   },
10327   {
10328     /* MOD_0FB2 */
10329     { "lssS",           { Gv, Mp }, 0 },
10330   },
10331   {
10332     /* MOD_0FB4 */
10333     { "lfsS",           { Gv, Mp }, 0 },
10334   },
10335   {
10336     /* MOD_0FB5 */
10337     { "lgsS",           { Gv, Mp }, 0 },
10338   },
10339   {
10340     /* MOD_0FC3 */
10341     { PREFIX_TABLE (PREFIX_0FC3_MOD_0) },
10342   },
10343   {
10344     /* MOD_0FC7_REG_3 */
10345     { "xrstors",        { FXSAVE }, 0 },
10346   },
10347   {
10348     /* MOD_0FC7_REG_4 */
10349     { "xsavec",         { FXSAVE }, 0 },
10350   },
10351   {
10352     /* MOD_0FC7_REG_5 */
10353     { "xsaves",         { FXSAVE }, 0 },
10354   },
10355   {
10356     /* MOD_0FC7_REG_6 */
10357     { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_0) },
10358     { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_3) }
10359   },
10360   {
10361     /* MOD_0FC7_REG_7 */
10362     { "vmptrst",        { Mq }, 0 },
10363     { PREFIX_TABLE (PREFIX_0FC7_REG_7_MOD_3) }
10364   },
10365   {
10366     /* MOD_0FD7 */
10367     { Bad_Opcode },
10368     { "pmovmskb",       { Gdq, MS }, 0 },
10369   },
10370   {
10371     /* MOD_0FE7_PREFIX_2 */
10372     { "movntdq",        { Mx, XM }, 0 },
10373   },
10374   {
10375     /* MOD_0FF0_PREFIX_3 */
10376     { "lddqu",          { XM, M }, 0 },
10377   },
10378   {
10379     /* MOD_0F382A_PREFIX_2 */
10380     { "movntdqa",       { XM, Mx }, 0 },
10381   },
10382   {
10383     /* MOD_0F38F5_PREFIX_2 */
10384     { "wrussK",         { M, Gdq }, PREFIX_OPCODE },
10385   },
10386   {
10387     /* MOD_0F38F6_PREFIX_0 */
10388     { "wrssK",          { M, Gdq }, PREFIX_OPCODE },
10389   },
10390   {
10391     /* MOD_0F38F8_PREFIX_1 */
10392     { "enqcmds",        { Gva, M }, PREFIX_OPCODE },
10393   },
10394   {
10395     /* MOD_0F38F8_PREFIX_2 */
10396     { "movdir64b",      { Gva, M }, PREFIX_OPCODE },
10397   },
10398   {
10399     /* MOD_0F38F8_PREFIX_3 */
10400     { "enqcmd",         { Gva, M }, PREFIX_OPCODE },
10401   },
10402   {
10403     /* MOD_0F38F9_PREFIX_0 */
10404     { "movdiri",        { Ev, Gv }, PREFIX_OPCODE },
10405   },
10406   {
10407     /* MOD_62_32BIT */
10408     { "bound{S|}",      { Gv, Ma }, 0 },
10409     { EVEX_TABLE (EVEX_0F) },
10410   },
10411   {
10412     /* MOD_C4_32BIT */
10413     { "lesS",           { Gv, Mp }, 0 },
10414     { VEX_C4_TABLE (VEX_0F) },
10415   },
10416   {
10417     /* MOD_C5_32BIT */
10418     { "ldsS",           { Gv, Mp }, 0 },
10419     { VEX_C5_TABLE (VEX_0F) },
10420   },
10421   {
10422     /* MOD_VEX_0F12_PREFIX_0 */
10423     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
10424     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
10425   },
10426   {
10427     /* MOD_VEX_0F12_PREFIX_2 */
10428     { VEX_LEN_TABLE (VEX_LEN_0F12_P_2_M_0) },
10429   },
10430   {
10431     /* MOD_VEX_0F13 */
10432     { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
10433   },
10434   {
10435     /* MOD_VEX_0F16_PREFIX_0 */
10436     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
10437     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
10438   },
10439   {
10440     /* MOD_VEX_0F16_PREFIX_2 */
10441     { VEX_LEN_TABLE (VEX_LEN_0F16_P_2_M_0) },
10442   },
10443   {
10444     /* MOD_VEX_0F17 */
10445     { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
10446   },
10447   {
10448     /* MOD_VEX_0F2B */
10449     { "vmovntpX",       { Mx, XM }, PREFIX_OPCODE },
10450   },
10451   {
10452     /* MOD_VEX_W_0_0F41_P_0_LEN_1 */
10453     { Bad_Opcode },
10454     { "kandw",          { MaskG, MaskVex, MaskR }, 0 },
10455   },
10456   {
10457     /* MOD_VEX_W_1_0F41_P_0_LEN_1 */
10458     { Bad_Opcode },
10459     { "kandq",          { MaskG, MaskVex, MaskR }, 0 },
10460   },
10461   {
10462     /* MOD_VEX_W_0_0F41_P_2_LEN_1 */
10463     { Bad_Opcode },
10464     { "kandb",          { MaskG, MaskVex, MaskR }, 0 },
10465   },
10466   {
10467     /* MOD_VEX_W_1_0F41_P_2_LEN_1 */
10468     { Bad_Opcode },
10469     { "kandd",          { MaskG, MaskVex, MaskR }, 0 },
10470   },
10471   {
10472     /* MOD_VEX_W_0_0F42_P_0_LEN_1 */
10473     { Bad_Opcode },
10474     { "kandnw",         { MaskG, MaskVex, MaskR }, 0 },
10475   },
10476   {
10477     /* MOD_VEX_W_1_0F42_P_0_LEN_1 */
10478     { Bad_Opcode },
10479     { "kandnq",         { MaskG, MaskVex, MaskR }, 0 },
10480   },
10481   {
10482     /* MOD_VEX_W_0_0F42_P_2_LEN_1 */
10483     { Bad_Opcode },
10484     { "kandnb",         { MaskG, MaskVex, MaskR }, 0 },
10485   },
10486   {
10487     /* MOD_VEX_W_1_0F42_P_2_LEN_1 */
10488     { Bad_Opcode },
10489     { "kandnd",         { MaskG, MaskVex, MaskR }, 0 },
10490   },
10491   {
10492     /* MOD_VEX_W_0_0F44_P_0_LEN_0 */
10493     { Bad_Opcode },
10494     { "knotw",          { MaskG, MaskR }, 0 },
10495   },
10496   {
10497     /* MOD_VEX_W_1_0F44_P_0_LEN_0 */
10498     { Bad_Opcode },
10499     { "knotq",          { MaskG, MaskR }, 0 },
10500   },
10501   {
10502     /* MOD_VEX_W_0_0F44_P_2_LEN_0 */
10503     { Bad_Opcode },
10504     { "knotb",          { MaskG, MaskR }, 0 },
10505   },
10506   {
10507     /* MOD_VEX_W_1_0F44_P_2_LEN_0 */
10508     { Bad_Opcode },
10509     { "knotd",          { MaskG, MaskR }, 0 },
10510   },
10511   {
10512     /* MOD_VEX_W_0_0F45_P_0_LEN_1 */
10513     { Bad_Opcode },
10514     { "korw",       { MaskG, MaskVex, MaskR }, 0 },
10515   },
10516   {
10517     /* MOD_VEX_W_1_0F45_P_0_LEN_1 */
10518     { Bad_Opcode },
10519     { "korq",       { MaskG, MaskVex, MaskR }, 0 },
10520   },
10521   {
10522     /* MOD_VEX_W_0_0F45_P_2_LEN_1 */
10523     { Bad_Opcode },
10524     { "korb",       { MaskG, MaskVex, MaskR }, 0 },
10525   },
10526   {
10527     /* MOD_VEX_W_1_0F45_P_2_LEN_1 */
10528     { Bad_Opcode },
10529     { "kord",       { MaskG, MaskVex, MaskR }, 0 },
10530   },
10531  {
10532     /* MOD_VEX_W_0_0F46_P_0_LEN_1 */
10533     { Bad_Opcode },
10534     { "kxnorw",     { MaskG, MaskVex, MaskR }, 0 },
10535   },
10536   {
10537     /* MOD_VEX_W_1_0F46_P_0_LEN_1 */
10538     { Bad_Opcode },
10539     { "kxnorq",     { MaskG, MaskVex, MaskR }, 0 },
10540   },
10541   {
10542     /* MOD_VEX_W_0_0F46_P_2_LEN_1 */
10543     { Bad_Opcode },
10544     { "kxnorb",     { MaskG, MaskVex, MaskR }, 0 },
10545   },
10546   {
10547     /* MOD_VEX_W_1_0F46_P_2_LEN_1 */
10548     { Bad_Opcode },
10549     { "kxnord",     { MaskG, MaskVex, MaskR }, 0 },
10550   },
10551   {
10552     /* MOD_VEX_W_0_0F47_P_0_LEN_1 */
10553     { Bad_Opcode },
10554     { "kxorw",      { MaskG, MaskVex, MaskR }, 0 },
10555   },
10556   {
10557     /* MOD_VEX_W_1_0F47_P_0_LEN_1 */
10558     { Bad_Opcode },
10559     { "kxorq",      { MaskG, MaskVex, MaskR }, 0 },
10560   },
10561   {
10562     /* MOD_VEX_W_0_0F47_P_2_LEN_1 */
10563     { Bad_Opcode },
10564     { "kxorb",      { MaskG, MaskVex, MaskR }, 0 },
10565   },
10566   {
10567     /* MOD_VEX_W_1_0F47_P_2_LEN_1 */
10568     { Bad_Opcode },
10569     { "kxord",      { MaskG, MaskVex, MaskR }, 0 },
10570   },
10571   {
10572     /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */
10573     { Bad_Opcode },
10574     { "kaddw",          { MaskG, MaskVex, MaskR }, 0 },
10575   },
10576   {
10577     /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */
10578     { Bad_Opcode },
10579     { "kaddq",          { MaskG, MaskVex, MaskR }, 0 },
10580   },
10581   {
10582     /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */
10583     { Bad_Opcode },
10584     { "kaddb",          { MaskG, MaskVex, MaskR }, 0 },
10585   },
10586   {
10587     /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */
10588     { Bad_Opcode },
10589     { "kaddd",          { MaskG, MaskVex, MaskR }, 0 },
10590   },
10591   {
10592     /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */
10593     { Bad_Opcode },
10594     { "kunpckwd",   { MaskG, MaskVex, MaskR }, 0 },
10595   },
10596   {
10597     /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */
10598     { Bad_Opcode },
10599     { "kunpckdq",   { MaskG, MaskVex, MaskR }, 0 },
10600   },
10601   {
10602     /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */
10603     { Bad_Opcode },
10604     { "kunpckbw",   { MaskG, MaskVex, MaskR }, 0 },
10605   },
10606   {
10607     /* MOD_VEX_0F50 */
10608     { Bad_Opcode },
10609     { "vmovmskpX",      { Gdq, XS }, PREFIX_OPCODE },
10610   },
10611   {
10612     /* MOD_VEX_0F71_REG_2 */
10613     { Bad_Opcode },
10614     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) },
10615   },
10616   {
10617     /* MOD_VEX_0F71_REG_4 */
10618     { Bad_Opcode },
10619     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) },
10620   },
10621   {
10622     /* MOD_VEX_0F71_REG_6 */
10623     { Bad_Opcode },
10624     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) },
10625   },
10626   {
10627     /* MOD_VEX_0F72_REG_2 */
10628     { Bad_Opcode },
10629     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) },
10630   },
10631   {
10632     /* MOD_VEX_0F72_REG_4 */
10633     { Bad_Opcode },
10634     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) },
10635   },
10636   {
10637     /* MOD_VEX_0F72_REG_6 */
10638     { Bad_Opcode },
10639     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) },
10640   },
10641   {
10642     /* MOD_VEX_0F73_REG_2 */
10643     { Bad_Opcode },
10644     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) },
10645   },
10646   {
10647     /* MOD_VEX_0F73_REG_3 */
10648     { Bad_Opcode },
10649     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) },
10650   },
10651   {
10652     /* MOD_VEX_0F73_REG_6 */
10653     { Bad_Opcode },
10654     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) },
10655   },
10656   {
10657     /* MOD_VEX_0F73_REG_7 */
10658     { Bad_Opcode },
10659     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) },
10660   },
10661   {
10662     /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
10663     { "kmovw",          { Ew, MaskG }, 0 },
10664     { Bad_Opcode },
10665   },
10666   {
10667     /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
10668     { "kmovq",          { Eq, MaskG }, 0 },
10669     { Bad_Opcode },
10670   },
10671   {
10672     /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
10673     { "kmovb",          { Eb, MaskG }, 0 },
10674     { Bad_Opcode },
10675   },
10676   {
10677     /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
10678     { "kmovd",          { Ed, MaskG }, 0 },
10679     { Bad_Opcode },
10680   },
10681   {
10682     /* MOD_VEX_W_0_0F92_P_0_LEN_0 */
10683     { Bad_Opcode },
10684     { "kmovw",          { MaskG, Rdq }, 0 },
10685   },
10686   {
10687     /* MOD_VEX_W_0_0F92_P_2_LEN_0 */
10688     { Bad_Opcode },
10689     { "kmovb",          { MaskG, Rdq }, 0 },
10690   },
10691   {
10692     /* MOD_VEX_0F92_P_3_LEN_0 */
10693     { Bad_Opcode },
10694     { "kmovK",          { MaskG, Rdq }, 0 },
10695   },
10696   {
10697     /* MOD_VEX_W_0_0F93_P_0_LEN_0 */
10698     { Bad_Opcode },
10699     { "kmovw",          { Gdq, MaskR }, 0 },
10700   },
10701   {
10702     /* MOD_VEX_W_0_0F93_P_2_LEN_0 */
10703     { Bad_Opcode },
10704     { "kmovb",          { Gdq, MaskR }, 0 },
10705   },
10706   {
10707     /* MOD_VEX_0F93_P_3_LEN_0 */
10708     { Bad_Opcode },
10709     { "kmovK",          { Gdq, MaskR }, 0 },
10710   },
10711   {
10712     /* MOD_VEX_W_0_0F98_P_0_LEN_0 */
10713     { Bad_Opcode },
10714     { "kortestw", { MaskG, MaskR }, 0 },
10715   },
10716   {
10717     /* MOD_VEX_W_1_0F98_P_0_LEN_0 */
10718     { Bad_Opcode },
10719     { "kortestq", { MaskG, MaskR }, 0 },
10720   },
10721   {
10722     /* MOD_VEX_W_0_0F98_P_2_LEN_0 */
10723     { Bad_Opcode },
10724     { "kortestb", { MaskG, MaskR }, 0 },
10725   },
10726   {
10727     /* MOD_VEX_W_1_0F98_P_2_LEN_0 */
10728     { Bad_Opcode },
10729     { "kortestd", { MaskG, MaskR }, 0 },
10730   },
10731   {
10732     /* MOD_VEX_W_0_0F99_P_0_LEN_0 */
10733     { Bad_Opcode },
10734     { "ktestw", { MaskG, MaskR }, 0 },
10735   },
10736   {
10737     /* MOD_VEX_W_1_0F99_P_0_LEN_0 */
10738     { Bad_Opcode },
10739     { "ktestq", { MaskG, MaskR }, 0 },
10740   },
10741   {
10742     /* MOD_VEX_W_0_0F99_P_2_LEN_0 */
10743     { Bad_Opcode },
10744     { "ktestb", { MaskG, MaskR }, 0 },
10745   },
10746   {
10747     /* MOD_VEX_W_1_0F99_P_2_LEN_0 */
10748     { Bad_Opcode },
10749     { "ktestd", { MaskG, MaskR }, 0 },
10750   },
10751   {
10752     /* MOD_VEX_0FAE_REG_2 */
10753     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
10754   },
10755   {
10756     /* MOD_VEX_0FAE_REG_3 */
10757     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
10758   },
10759   {
10760     /* MOD_VEX_0FD7_PREFIX_2 */
10761     { Bad_Opcode },
10762     { "vpmovmskb",      { Gdq, XS }, 0 },
10763   },
10764   {
10765     /* MOD_VEX_0FE7_PREFIX_2 */
10766     { "vmovntdq",       { Mx, XM }, 0 },
10767   },
10768   {
10769     /* MOD_VEX_0FF0_PREFIX_3 */
10770     { "vlddqu",         { XM, M }, 0 },
10771   },
10772   {
10773     /* MOD_VEX_0F381A_PREFIX_2 */
10774     { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) },
10775   },
10776   {
10777     /* MOD_VEX_0F382A_PREFIX_2 */
10778     { "vmovntdqa",      { XM, Mx }, 0 },
10779   },
10780   {
10781     /* MOD_VEX_0F382C_PREFIX_2 */
10782     { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) },
10783   },
10784   {
10785     /* MOD_VEX_0F382D_PREFIX_2 */
10786     { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) },
10787   },
10788   {
10789     /* MOD_VEX_0F382E_PREFIX_2 */
10790     { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) },
10791   },
10792   {
10793     /* MOD_VEX_0F382F_PREFIX_2 */
10794     { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) },
10795   },
10796   {
10797     /* MOD_VEX_0F385A_PREFIX_2 */
10798     { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) },
10799   },
10800   {
10801     /* MOD_VEX_0F388C_PREFIX_2 */
10802     { "vpmaskmov%LW",   { XM, Vex, Mx }, 0 },
10803   },
10804   {
10805     /* MOD_VEX_0F388E_PREFIX_2 */
10806     { "vpmaskmov%LW",   { Mx, Vex, XM }, 0 },
10807   },
10808   {
10809     /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */
10810     { Bad_Opcode },
10811     { "kshiftrb",       { MaskG, MaskR, Ib }, 0 },
10812   },
10813   {
10814     /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */
10815     { Bad_Opcode },
10816     { "kshiftrw",       { MaskG, MaskR, Ib }, 0 },
10817   },
10818   {
10819     /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */
10820     { Bad_Opcode },
10821     { "kshiftrd",       { MaskG, MaskR, Ib }, 0 },
10822   },
10823   {
10824     /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */
10825     { Bad_Opcode },
10826     { "kshiftrq",       { MaskG, MaskR, Ib }, 0 },
10827   },
10828   {
10829     /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */
10830     { Bad_Opcode },
10831     { "kshiftlb",       { MaskG, MaskR, Ib }, 0 },
10832   },
10833   {
10834     /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */
10835     { Bad_Opcode },
10836     { "kshiftlw",       { MaskG, MaskR, Ib }, 0 },
10837   },
10838   {
10839     /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */
10840     { Bad_Opcode },
10841     { "kshiftld",       { MaskG, MaskR, Ib }, 0 },
10842   },
10843   {
10844     /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */
10845     { Bad_Opcode },
10846     { "kshiftlq",       { MaskG, MaskR, Ib }, 0 },
10847   },
10848
10849 #include "i386-dis-evex-mod.h"
10850 };
10851
10852 static const struct dis386 rm_table[][8] = {
10853   {
10854     /* RM_C6_REG_7 */
10855     { "xabort",         { Skip_MODRM, Ib }, 0 },
10856   },
10857   {
10858     /* RM_C7_REG_7 */
10859     { "xbeginT",        { Skip_MODRM, Jdqw }, 0 },
10860   },
10861   {
10862     /* RM_0F01_REG_0 */
10863     { "enclv",          { Skip_MODRM }, 0 },
10864     { "vmcall",         { Skip_MODRM }, 0 },
10865     { "vmlaunch",       { Skip_MODRM }, 0 },
10866     { "vmresume",       { Skip_MODRM }, 0 },
10867     { "vmxoff",         { Skip_MODRM }, 0 },
10868     { "pconfig",        { Skip_MODRM }, 0 },
10869   },
10870   {
10871     /* RM_0F01_REG_1 */
10872     { "monitor",        { { OP_Monitor, 0 } }, 0 },
10873     { "mwait",          { { OP_Mwait, 0 } }, 0 },
10874     { "clac",           { Skip_MODRM }, 0 },
10875     { "stac",           { Skip_MODRM }, 0 },
10876     { Bad_Opcode },
10877     { Bad_Opcode },
10878     { Bad_Opcode },
10879     { "encls",          { Skip_MODRM }, 0 },
10880   },
10881   {
10882     /* RM_0F01_REG_2 */
10883     { "xgetbv",         { Skip_MODRM }, 0 },
10884     { "xsetbv",         { Skip_MODRM }, 0 },
10885     { Bad_Opcode },
10886     { Bad_Opcode },
10887     { "vmfunc",         { Skip_MODRM }, 0 },
10888     { "xend",           { Skip_MODRM }, 0 },
10889     { "xtest",          { Skip_MODRM }, 0 },
10890     { "enclu",          { Skip_MODRM }, 0 },
10891   },
10892   {
10893     /* RM_0F01_REG_3 */
10894     { "vmrun",          { Skip_MODRM }, 0 },
10895     { PREFIX_TABLE (PREFIX_0F01_REG_3_RM_1) },
10896     { "vmload",         { Skip_MODRM }, 0 },
10897     { "vmsave",         { Skip_MODRM }, 0 },
10898     { "stgi",           { Skip_MODRM }, 0 },
10899     { "clgi",           { Skip_MODRM }, 0 },
10900     { "skinit",         { Skip_MODRM }, 0 },
10901     { "invlpga",        { Skip_MODRM }, 0 },
10902   },
10903   {
10904     /* RM_0F01_REG_5_MOD_3 */
10905     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_0) },
10906     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_1) },
10907     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_2) },
10908     { Bad_Opcode },
10909     { Bad_Opcode },
10910     { Bad_Opcode },
10911     { "rdpkru",         { Skip_MODRM }, 0 },
10912     { "wrpkru",         { Skip_MODRM }, 0 },
10913   },
10914   {
10915     /* RM_0F01_REG_7_MOD_3 */
10916     { "swapgs",         { Skip_MODRM }, 0  },
10917     { "rdtscp",         { Skip_MODRM }, 0  },
10918     { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_2) },
10919     { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_3) },
10920     { "clzero",         { Skip_MODRM }, 0  },
10921     { "rdpru",          { Skip_MODRM }, 0  },
10922   },
10923   {
10924     /* RM_0F1E_P_1_MOD_3_REG_7 */
10925     { "nopQ",           { Ev }, 0 },
10926     { "nopQ",           { Ev }, 0 },
10927     { "endbr64",        { Skip_MODRM },  PREFIX_OPCODE },
10928     { "endbr32",        { Skip_MODRM },  PREFIX_OPCODE },
10929     { "nopQ",           { Ev }, 0 },
10930     { "nopQ",           { Ev }, 0 },
10931     { "nopQ",           { Ev }, 0 },
10932     { "nopQ",           { Ev }, 0 },
10933   },
10934   {
10935     /* RM_0FAE_REG_6_MOD_3 */
10936     { "mfence",         { Skip_MODRM }, 0 },
10937   },
10938   {
10939     /* RM_0FAE_REG_7_MOD_3 */
10940     { "sfence",         { Skip_MODRM }, 0 },
10941
10942   },
10943 };
10944
10945 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
10946
10947 /* We use the high bit to indicate different name for the same
10948    prefix.  */
10949 #define REP_PREFIX      (0xf3 | 0x100)
10950 #define XACQUIRE_PREFIX (0xf2 | 0x200)
10951 #define XRELEASE_PREFIX (0xf3 | 0x400)
10952 #define BND_PREFIX      (0xf2 | 0x400)
10953 #define NOTRACK_PREFIX  (0x3e | 0x100)
10954
10955 /* Remember if the current op is a jump instruction.  */
10956 static bfd_boolean op_is_jump = FALSE;
10957
10958 static int
10959 ckprefix (void)
10960 {
10961   int newrex, i, length;
10962   rex = 0;
10963   prefixes = 0;
10964   used_prefixes = 0;
10965   rex_used = 0;
10966   last_lock_prefix = -1;
10967   last_repz_prefix = -1;
10968   last_repnz_prefix = -1;
10969   last_data_prefix = -1;
10970   last_addr_prefix = -1;
10971   last_rex_prefix = -1;
10972   last_seg_prefix = -1;
10973   fwait_prefix = -1;
10974   active_seg_prefix = 0;
10975   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
10976     all_prefixes[i] = 0;
10977   i = 0;
10978   length = 0;
10979   /* The maximum instruction length is 15bytes.  */
10980   while (length < MAX_CODE_LENGTH - 1)
10981     {
10982       FETCH_DATA (the_info, codep + 1);
10983       newrex = 0;
10984       switch (*codep)
10985         {
10986         /* REX prefixes family.  */
10987         case 0x40:
10988         case 0x41:
10989         case 0x42:
10990         case 0x43:
10991         case 0x44:
10992         case 0x45:
10993         case 0x46:
10994         case 0x47:
10995         case 0x48:
10996         case 0x49:
10997         case 0x4a:
10998         case 0x4b:
10999         case 0x4c:
11000         case 0x4d:
11001         case 0x4e:
11002         case 0x4f:
11003           if (address_mode == mode_64bit)
11004             newrex = *codep;
11005           else
11006             return 1;
11007           last_rex_prefix = i;
11008           break;
11009         case 0xf3:
11010           prefixes |= PREFIX_REPZ;
11011           last_repz_prefix = i;
11012           break;
11013         case 0xf2:
11014           prefixes |= PREFIX_REPNZ;
11015           last_repnz_prefix = i;
11016           break;
11017         case 0xf0:
11018           prefixes |= PREFIX_LOCK;
11019           last_lock_prefix = i;
11020           break;
11021         case 0x2e:
11022           prefixes |= PREFIX_CS;
11023           last_seg_prefix = i;
11024           active_seg_prefix = PREFIX_CS;
11025           break;
11026         case 0x36:
11027           prefixes |= PREFIX_SS;
11028           last_seg_prefix = i;
11029           active_seg_prefix = PREFIX_SS;
11030           break;
11031         case 0x3e:
11032           prefixes |= PREFIX_DS;
11033           last_seg_prefix = i;
11034           active_seg_prefix = PREFIX_DS;
11035           break;
11036         case 0x26:
11037           prefixes |= PREFIX_ES;
11038           last_seg_prefix = i;
11039           active_seg_prefix = PREFIX_ES;
11040           break;
11041         case 0x64:
11042           prefixes |= PREFIX_FS;
11043           last_seg_prefix = i;
11044           active_seg_prefix = PREFIX_FS;
11045           break;
11046         case 0x65:
11047           prefixes |= PREFIX_GS;
11048           last_seg_prefix = i;
11049           active_seg_prefix = PREFIX_GS;
11050           break;
11051         case 0x66:
11052           prefixes |= PREFIX_DATA;
11053           last_data_prefix = i;
11054           break;
11055         case 0x67:
11056           prefixes |= PREFIX_ADDR;
11057           last_addr_prefix = i;
11058           break;
11059         case FWAIT_OPCODE:
11060           /* fwait is really an instruction.  If there are prefixes
11061              before the fwait, they belong to the fwait, *not* to the
11062              following instruction.  */
11063           fwait_prefix = i;
11064           if (prefixes || rex)
11065             {
11066               prefixes |= PREFIX_FWAIT;
11067               codep++;
11068               /* This ensures that the previous REX prefixes are noticed
11069                  as unused prefixes, as in the return case below.  */
11070               rex_used = rex;
11071               return 1;
11072             }
11073           prefixes = PREFIX_FWAIT;
11074           break;
11075         default:
11076           return 1;
11077         }
11078       /* Rex is ignored when followed by another prefix.  */
11079       if (rex)
11080         {
11081           rex_used = rex;
11082           return 1;
11083         }
11084       if (*codep != FWAIT_OPCODE)
11085         all_prefixes[i++] = *codep;
11086       rex = newrex;
11087       codep++;
11088       length++;
11089     }
11090   return 0;
11091 }
11092
11093 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
11094    prefix byte.  */
11095
11096 static const char *
11097 prefix_name (int pref, int sizeflag)
11098 {
11099   static const char *rexes [16] =
11100     {
11101       "rex",            /* 0x40 */
11102       "rex.B",          /* 0x41 */
11103       "rex.X",          /* 0x42 */
11104       "rex.XB",         /* 0x43 */
11105       "rex.R",          /* 0x44 */
11106       "rex.RB",         /* 0x45 */
11107       "rex.RX",         /* 0x46 */
11108       "rex.RXB",        /* 0x47 */
11109       "rex.W",          /* 0x48 */
11110       "rex.WB",         /* 0x49 */
11111       "rex.WX",         /* 0x4a */
11112       "rex.WXB",        /* 0x4b */
11113       "rex.WR",         /* 0x4c */
11114       "rex.WRB",        /* 0x4d */
11115       "rex.WRX",        /* 0x4e */
11116       "rex.WRXB",       /* 0x4f */
11117     };
11118
11119   switch (pref)
11120     {
11121     /* REX prefixes family.  */
11122     case 0x40:
11123     case 0x41:
11124     case 0x42:
11125     case 0x43:
11126     case 0x44:
11127     case 0x45:
11128     case 0x46:
11129     case 0x47:
11130     case 0x48:
11131     case 0x49:
11132     case 0x4a:
11133     case 0x4b:
11134     case 0x4c:
11135     case 0x4d:
11136     case 0x4e:
11137     case 0x4f:
11138       return rexes [pref - 0x40];
11139     case 0xf3:
11140       return "repz";
11141     case 0xf2:
11142       return "repnz";
11143     case 0xf0:
11144       return "lock";
11145     case 0x2e:
11146       return "cs";
11147     case 0x36:
11148       return "ss";
11149     case 0x3e:
11150       return "ds";
11151     case 0x26:
11152       return "es";
11153     case 0x64:
11154       return "fs";
11155     case 0x65:
11156       return "gs";
11157     case 0x66:
11158       return (sizeflag & DFLAG) ? "data16" : "data32";
11159     case 0x67:
11160       if (address_mode == mode_64bit)
11161         return (sizeflag & AFLAG) ? "addr32" : "addr64";
11162       else
11163         return (sizeflag & AFLAG) ? "addr16" : "addr32";
11164     case FWAIT_OPCODE:
11165       return "fwait";
11166     case REP_PREFIX:
11167       return "rep";
11168     case XACQUIRE_PREFIX:
11169       return "xacquire";
11170     case XRELEASE_PREFIX:
11171       return "xrelease";
11172     case BND_PREFIX:
11173       return "bnd";
11174     case NOTRACK_PREFIX:
11175       return "notrack";
11176     default:
11177       return NULL;
11178     }
11179 }
11180
11181 static char op_out[MAX_OPERANDS][100];
11182 static int op_ad, op_index[MAX_OPERANDS];
11183 static int two_source_ops;
11184 static bfd_vma op_address[MAX_OPERANDS];
11185 static bfd_vma op_riprel[MAX_OPERANDS];
11186 static bfd_vma start_pc;
11187
11188 /*
11189  *   On the 386's of 1988, the maximum length of an instruction is 15 bytes.
11190  *   (see topic "Redundant prefixes" in the "Differences from 8086"
11191  *   section of the "Virtual 8086 Mode" chapter.)
11192  * 'pc' should be the address of this instruction, it will
11193  *   be used to print the target address if this is a relative jump or call
11194  * The function returns the length of this instruction in bytes.
11195  */
11196
11197 static char intel_syntax;
11198 static char intel_mnemonic = !SYSV386_COMPAT;
11199 static char open_char;
11200 static char close_char;
11201 static char separator_char;
11202 static char scale_char;
11203
11204 enum x86_64_isa
11205 {
11206   amd64 = 1,
11207   intel64
11208 };
11209
11210 static enum x86_64_isa isa64;
11211
11212 /* Here for backwards compatibility.  When gdb stops using
11213    print_insn_i386_att and print_insn_i386_intel these functions can
11214    disappear, and print_insn_i386 be merged into print_insn.  */
11215 int
11216 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
11217 {
11218   intel_syntax = 0;
11219
11220   return print_insn (pc, info);
11221 }
11222
11223 int
11224 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
11225 {
11226   intel_syntax = 1;
11227
11228   return print_insn (pc, info);
11229 }
11230
11231 int
11232 print_insn_i386 (bfd_vma pc, disassemble_info *info)
11233 {
11234   intel_syntax = -1;
11235
11236   return print_insn (pc, info);
11237 }
11238
11239 void
11240 print_i386_disassembler_options (FILE *stream)
11241 {
11242   fprintf (stream, _("\n\
11243 The following i386/x86-64 specific disassembler options are supported for use\n\
11244 with the -M switch (multiple options should be separated by commas):\n"));
11245
11246   fprintf (stream, _("  x86-64      Disassemble in 64bit mode\n"));
11247   fprintf (stream, _("  i386        Disassemble in 32bit mode\n"));
11248   fprintf (stream, _("  i8086       Disassemble in 16bit mode\n"));
11249   fprintf (stream, _("  att         Display instruction in AT&T syntax\n"));
11250   fprintf (stream, _("  intel       Display instruction in Intel syntax\n"));
11251   fprintf (stream, _("  att-mnemonic\n"
11252                      "              Display instruction in AT&T mnemonic\n"));
11253   fprintf (stream, _("  intel-mnemonic\n"
11254                      "              Display instruction in Intel mnemonic\n"));
11255   fprintf (stream, _("  addr64      Assume 64bit address size\n"));
11256   fprintf (stream, _("  addr32      Assume 32bit address size\n"));
11257   fprintf (stream, _("  addr16      Assume 16bit address size\n"));
11258   fprintf (stream, _("  data32      Assume 32bit data size\n"));
11259   fprintf (stream, _("  data16      Assume 16bit data size\n"));
11260   fprintf (stream, _("  suffix      Always display instruction suffix in AT&T syntax\n"));
11261   fprintf (stream, _("  amd64       Display instruction in AMD64 ISA\n"));
11262   fprintf (stream, _("  intel64     Display instruction in Intel64 ISA\n"));
11263 }
11264
11265 /* Bad opcode.  */
11266 static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 };
11267
11268 /* Get a pointer to struct dis386 with a valid name.  */
11269
11270 static const struct dis386 *
11271 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
11272 {
11273   int vindex, vex_table_index;
11274
11275   if (dp->name != NULL)
11276     return dp;
11277
11278   switch (dp->op[0].bytemode)
11279     {
11280     case USE_REG_TABLE:
11281       dp = &reg_table[dp->op[1].bytemode][modrm.reg];
11282       break;
11283
11284     case USE_MOD_TABLE:
11285       vindex = modrm.mod == 0x3 ? 1 : 0;
11286       dp = &mod_table[dp->op[1].bytemode][vindex];
11287       break;
11288
11289     case USE_RM_TABLE:
11290       dp = &rm_table[dp->op[1].bytemode][modrm.rm];
11291       break;
11292
11293     case USE_PREFIX_TABLE:
11294       if (need_vex)
11295         {
11296           /* The prefix in VEX is implicit.  */
11297           switch (vex.prefix)
11298             {
11299             case 0:
11300               vindex = 0;
11301               break;
11302             case REPE_PREFIX_OPCODE:
11303               vindex = 1;
11304               break;
11305             case DATA_PREFIX_OPCODE:
11306               vindex = 2;
11307               break;
11308             case REPNE_PREFIX_OPCODE:
11309               vindex = 3;
11310               break;
11311             default:
11312               abort ();
11313               break;
11314             }
11315         }
11316       else
11317         {
11318           int last_prefix = -1;
11319           int prefix = 0;
11320           vindex = 0;
11321           /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
11322              When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
11323              last one wins.  */
11324           if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
11325             {
11326               if (last_repz_prefix > last_repnz_prefix)
11327                 {
11328                   vindex = 1;
11329                   prefix = PREFIX_REPZ;
11330                   last_prefix = last_repz_prefix;
11331                 }
11332               else
11333                 {
11334                   vindex = 3;
11335                   prefix = PREFIX_REPNZ;
11336                   last_prefix = last_repnz_prefix;
11337                 }
11338
11339               /* Check if prefix should be ignored.  */
11340               if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement
11341                      & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT)
11342                    & prefix) != 0)
11343                 vindex = 0;
11344             }
11345
11346           if (vindex == 0 && (prefixes & PREFIX_DATA) != 0)
11347             {
11348               vindex = 2;
11349               prefix = PREFIX_DATA;
11350               last_prefix = last_data_prefix;
11351             }
11352
11353           if (vindex != 0)
11354             {
11355               used_prefixes |= prefix;
11356               all_prefixes[last_prefix] = 0;
11357             }
11358         }
11359       dp = &prefix_table[dp->op[1].bytemode][vindex];
11360       break;
11361
11362     case USE_X86_64_TABLE:
11363       vindex = address_mode == mode_64bit ? 1 : 0;
11364       dp = &x86_64_table[dp->op[1].bytemode][vindex];
11365       break;
11366
11367     case USE_3BYTE_TABLE:
11368       FETCH_DATA (info, codep + 2);
11369       vindex = *codep++;
11370       dp = &three_byte_table[dp->op[1].bytemode][vindex];
11371       end_codep = codep;
11372       modrm.mod = (*codep >> 6) & 3;
11373       modrm.reg = (*codep >> 3) & 7;
11374       modrm.rm = *codep & 7;
11375       break;
11376
11377     case USE_VEX_LEN_TABLE:
11378       if (!need_vex)
11379         abort ();
11380
11381       switch (vex.length)
11382         {
11383         case 128:
11384           vindex = 0;
11385           break;
11386         case 256:
11387           vindex = 1;
11388           break;
11389         default:
11390           abort ();
11391           break;
11392         }
11393
11394       dp = &vex_len_table[dp->op[1].bytemode][vindex];
11395       break;
11396
11397     case USE_EVEX_LEN_TABLE:
11398       if (!vex.evex)
11399         abort ();
11400
11401       switch (vex.length)
11402         {
11403         case 128:
11404           vindex = 0;
11405           break;
11406         case 256:
11407           vindex = 1;
11408           break;
11409         case 512:
11410           vindex = 2;
11411           break;
11412         default:
11413           abort ();
11414           break;
11415         }
11416
11417       dp = &evex_len_table[dp->op[1].bytemode][vindex];
11418       break;
11419
11420     case USE_XOP_8F_TABLE:
11421       FETCH_DATA (info, codep + 3);
11422       rex = ~(*codep >> 5) & 0x7;
11423
11424       /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm".  */
11425       switch ((*codep & 0x1f))
11426         {
11427         default:
11428           dp = &bad_opcode;
11429           return dp;
11430         case 0x8:
11431           vex_table_index = XOP_08;
11432           break;
11433         case 0x9:
11434           vex_table_index = XOP_09;
11435           break;
11436         case 0xa:
11437           vex_table_index = XOP_0A;
11438           break;
11439         }
11440       codep++;
11441       vex.w = *codep & 0x80;
11442       if (vex.w && address_mode == mode_64bit)
11443         rex |= REX_W;
11444
11445       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11446       if (address_mode != mode_64bit)
11447         {
11448           /* In 16/32-bit mode REX_B is silently ignored.  */
11449           rex &= ~REX_B;
11450         }
11451
11452       vex.length = (*codep & 0x4) ? 256 : 128;
11453       switch ((*codep & 0x3))
11454         {
11455         case 0:
11456           break;
11457         case 1:
11458           vex.prefix = DATA_PREFIX_OPCODE;
11459           break;
11460         case 2:
11461           vex.prefix = REPE_PREFIX_OPCODE;
11462           break;
11463         case 3:
11464           vex.prefix = REPNE_PREFIX_OPCODE;
11465           break;
11466         }
11467       need_vex = 1;
11468       need_vex_reg = 1;
11469       codep++;
11470       vindex = *codep++;
11471       dp = &xop_table[vex_table_index][vindex];
11472
11473       end_codep = codep;
11474       FETCH_DATA (info, codep + 1);
11475       modrm.mod = (*codep >> 6) & 3;
11476       modrm.reg = (*codep >> 3) & 7;
11477       modrm.rm = *codep & 7;
11478       break;
11479
11480     case USE_VEX_C4_TABLE:
11481       /* VEX prefix.  */
11482       FETCH_DATA (info, codep + 3);
11483       rex = ~(*codep >> 5) & 0x7;
11484       switch ((*codep & 0x1f))
11485         {
11486         default:
11487           dp = &bad_opcode;
11488           return dp;
11489         case 0x1:
11490           vex_table_index = VEX_0F;
11491           break;
11492         case 0x2:
11493           vex_table_index = VEX_0F38;
11494           break;
11495         case 0x3:
11496           vex_table_index = VEX_0F3A;
11497           break;
11498         }
11499       codep++;
11500       vex.w = *codep & 0x80;
11501       if (address_mode == mode_64bit)
11502         {
11503           if (vex.w)
11504             rex |= REX_W;
11505         }
11506       else
11507         {
11508           /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
11509              is ignored, other REX bits are 0 and the highest bit in
11510              VEX.vvvv is also ignored (but we mustn't clear it here).  */
11511           rex = 0;
11512         }
11513       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11514       vex.length = (*codep & 0x4) ? 256 : 128;
11515       switch ((*codep & 0x3))
11516         {
11517         case 0:
11518           break;
11519         case 1:
11520           vex.prefix = DATA_PREFIX_OPCODE;
11521           break;
11522         case 2:
11523           vex.prefix = REPE_PREFIX_OPCODE;
11524           break;
11525         case 3:
11526           vex.prefix = REPNE_PREFIX_OPCODE;
11527           break;
11528         }
11529       need_vex = 1;
11530       need_vex_reg = 1;
11531       codep++;
11532       vindex = *codep++;
11533       dp = &vex_table[vex_table_index][vindex];
11534       end_codep = codep;
11535       /* There is no MODRM byte for VEX0F 77.  */
11536       if (vex_table_index != VEX_0F || vindex != 0x77)
11537         {
11538           FETCH_DATA (info, codep + 1);
11539           modrm.mod = (*codep >> 6) & 3;
11540           modrm.reg = (*codep >> 3) & 7;
11541           modrm.rm = *codep & 7;
11542         }
11543       break;
11544
11545     case USE_VEX_C5_TABLE:
11546       /* VEX prefix.  */
11547       FETCH_DATA (info, codep + 2);
11548       rex = (*codep & 0x80) ? 0 : REX_R;
11549
11550       /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
11551          VEX.vvvv is 1.  */
11552       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11553       vex.length = (*codep & 0x4) ? 256 : 128;
11554       switch ((*codep & 0x3))
11555         {
11556         case 0:
11557           break;
11558         case 1:
11559           vex.prefix = DATA_PREFIX_OPCODE;
11560           break;
11561         case 2:
11562           vex.prefix = REPE_PREFIX_OPCODE;
11563           break;
11564         case 3:
11565           vex.prefix = REPNE_PREFIX_OPCODE;
11566           break;
11567         }
11568       need_vex = 1;
11569       need_vex_reg = 1;
11570       codep++;
11571       vindex = *codep++;
11572       dp = &vex_table[dp->op[1].bytemode][vindex];
11573       end_codep = codep;
11574       /* There is no MODRM byte for VEX 77.  */
11575       if (vindex != 0x77)
11576         {
11577           FETCH_DATA (info, codep + 1);
11578           modrm.mod = (*codep >> 6) & 3;
11579           modrm.reg = (*codep >> 3) & 7;
11580           modrm.rm = *codep & 7;
11581         }
11582       break;
11583
11584     case USE_VEX_W_TABLE:
11585       if (!need_vex)
11586         abort ();
11587
11588       dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
11589       break;
11590
11591     case USE_EVEX_TABLE:
11592       two_source_ops = 0;
11593       /* EVEX prefix.  */
11594       vex.evex = 1;
11595       FETCH_DATA (info, codep + 4);
11596       /* The first byte after 0x62.  */
11597       rex = ~(*codep >> 5) & 0x7;
11598       vex.r = *codep & 0x10;
11599       switch ((*codep & 0xf))
11600         {
11601         default:
11602           return &bad_opcode;
11603         case 0x1:
11604           vex_table_index = EVEX_0F;
11605           break;
11606         case 0x2:
11607           vex_table_index = EVEX_0F38;
11608           break;
11609         case 0x3:
11610           vex_table_index = EVEX_0F3A;
11611           break;
11612         }
11613
11614       /* The second byte after 0x62.  */
11615       codep++;
11616       vex.w = *codep & 0x80;
11617       if (vex.w && address_mode == mode_64bit)
11618         rex |= REX_W;
11619
11620       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11621
11622       /* The U bit.  */
11623       if (!(*codep & 0x4))
11624         return &bad_opcode;
11625
11626       switch ((*codep & 0x3))
11627         {
11628         case 0:
11629           break;
11630         case 1:
11631           vex.prefix = DATA_PREFIX_OPCODE;
11632           break;
11633         case 2:
11634           vex.prefix = REPE_PREFIX_OPCODE;
11635           break;
11636         case 3:
11637           vex.prefix = REPNE_PREFIX_OPCODE;
11638           break;
11639         }
11640
11641       /* The third byte after 0x62.  */
11642       codep++;
11643
11644       /* Remember the static rounding bits.  */
11645       vex.ll = (*codep >> 5) & 3;
11646       vex.b = (*codep & 0x10) != 0;
11647
11648       vex.v = *codep & 0x8;
11649       vex.mask_register_specifier = *codep & 0x7;
11650       vex.zeroing = *codep & 0x80;
11651
11652       if (address_mode != mode_64bit)
11653         {
11654           /* In 16/32-bit mode silently ignore following bits.  */
11655           rex &= ~REX_B;
11656           vex.r = 1;
11657           vex.v = 1;
11658         }
11659
11660       need_vex = 1;
11661       need_vex_reg = 1;
11662       codep++;
11663       vindex = *codep++;
11664       dp = &evex_table[vex_table_index][vindex];
11665       end_codep = codep;
11666       FETCH_DATA (info, codep + 1);
11667       modrm.mod = (*codep >> 6) & 3;
11668       modrm.reg = (*codep >> 3) & 7;
11669       modrm.rm = *codep & 7;
11670
11671       /* Set vector length.  */
11672       if (modrm.mod == 3 && vex.b)
11673         vex.length = 512;
11674       else
11675         {
11676           switch (vex.ll)
11677             {
11678             case 0x0:
11679               vex.length = 128;
11680               break;
11681             case 0x1:
11682               vex.length = 256;
11683               break;
11684             case 0x2:
11685               vex.length = 512;
11686               break;
11687             default:
11688               return &bad_opcode;
11689             }
11690         }
11691       break;
11692
11693     case 0:
11694       dp = &bad_opcode;
11695       break;
11696
11697     default:
11698       abort ();
11699     }
11700
11701   if (dp->name != NULL)
11702     return dp;
11703   else
11704     return get_valid_dis386 (dp, info);
11705 }
11706
11707 static void
11708 get_sib (disassemble_info *info, int sizeflag)
11709 {
11710   /* If modrm.mod == 3, operand must be register.  */
11711   if (need_modrm
11712       && ((sizeflag & AFLAG) || address_mode == mode_64bit)
11713       && modrm.mod != 3
11714       && modrm.rm == 4)
11715     {
11716       FETCH_DATA (info, codep + 2);
11717       sib.index = (codep [1] >> 3) & 7;
11718       sib.scale = (codep [1] >> 6) & 3;
11719       sib.base = codep [1] & 7;
11720     }
11721 }
11722
11723 static int
11724 print_insn (bfd_vma pc, disassemble_info *info)
11725 {
11726   const struct dis386 *dp;
11727   int i;
11728   char *op_txt[MAX_OPERANDS];
11729   int needcomma;
11730   int sizeflag, orig_sizeflag;
11731   const char *p;
11732   struct dis_private priv;
11733   int prefix_length;
11734
11735   priv.orig_sizeflag = AFLAG | DFLAG;
11736   if ((info->mach & bfd_mach_i386_i386) != 0)
11737     address_mode = mode_32bit;
11738   else if (info->mach == bfd_mach_i386_i8086)
11739     {
11740       address_mode = mode_16bit;
11741       priv.orig_sizeflag = 0;
11742     }
11743   else
11744     address_mode = mode_64bit;
11745
11746   if (intel_syntax == (char) -1)
11747     intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0;
11748
11749   for (p = info->disassembler_options; p != NULL; )
11750     {
11751       if (CONST_STRNEQ (p, "amd64"))
11752         isa64 = amd64;
11753       else if (CONST_STRNEQ (p, "intel64"))
11754         isa64 = intel64;
11755       else if (CONST_STRNEQ (p, "x86-64"))
11756         {
11757           address_mode = mode_64bit;
11758           priv.orig_sizeflag |= AFLAG | DFLAG;
11759         }
11760       else if (CONST_STRNEQ (p, "i386"))
11761         {
11762           address_mode = mode_32bit;
11763           priv.orig_sizeflag |= AFLAG | DFLAG;
11764         }
11765       else if (CONST_STRNEQ (p, "i8086"))
11766         {
11767           address_mode = mode_16bit;
11768           priv.orig_sizeflag &= ~(AFLAG | DFLAG);
11769         }
11770       else if (CONST_STRNEQ (p, "intel"))
11771         {
11772           intel_syntax = 1;
11773           if (CONST_STRNEQ (p + 5, "-mnemonic"))
11774             intel_mnemonic = 1;
11775         }
11776       else if (CONST_STRNEQ (p, "att"))
11777         {
11778           intel_syntax = 0;
11779           if (CONST_STRNEQ (p + 3, "-mnemonic"))
11780             intel_mnemonic = 0;
11781         }
11782       else if (CONST_STRNEQ (p, "addr"))
11783         {
11784           if (address_mode == mode_64bit)
11785             {
11786               if (p[4] == '3' && p[5] == '2')
11787                 priv.orig_sizeflag &= ~AFLAG;
11788               else if (p[4] == '6' && p[5] == '4')
11789                 priv.orig_sizeflag |= AFLAG;
11790             }
11791           else
11792             {
11793               if (p[4] == '1' && p[5] == '6')
11794                 priv.orig_sizeflag &= ~AFLAG;
11795               else if (p[4] == '3' && p[5] == '2')
11796                 priv.orig_sizeflag |= AFLAG;
11797             }
11798         }
11799       else if (CONST_STRNEQ (p, "data"))
11800         {
11801           if (p[4] == '1' && p[5] == '6')
11802             priv.orig_sizeflag &= ~DFLAG;
11803           else if (p[4] == '3' && p[5] == '2')
11804             priv.orig_sizeflag |= DFLAG;
11805         }
11806       else if (CONST_STRNEQ (p, "suffix"))
11807         priv.orig_sizeflag |= SUFFIX_ALWAYS;
11808
11809       p = strchr (p, ',');
11810       if (p != NULL)
11811         p++;
11812     }
11813
11814   if (address_mode == mode_64bit && sizeof (bfd_vma) < 8)
11815     {
11816       (*info->fprintf_func) (info->stream,
11817                              _("64-bit address is disabled"));
11818       return -1;
11819     }
11820
11821   if (intel_syntax)
11822     {
11823       names64 = intel_names64;
11824       names32 = intel_names32;
11825       names16 = intel_names16;
11826       names8 = intel_names8;
11827       names8rex = intel_names8rex;
11828       names_seg = intel_names_seg;
11829       names_mm = intel_names_mm;
11830       names_bnd = intel_names_bnd;
11831       names_xmm = intel_names_xmm;
11832       names_ymm = intel_names_ymm;
11833       names_zmm = intel_names_zmm;
11834       index64 = intel_index64;
11835       index32 = intel_index32;
11836       names_mask = intel_names_mask;
11837       index16 = intel_index16;
11838       open_char = '[';
11839       close_char = ']';
11840       separator_char = '+';
11841       scale_char = '*';
11842     }
11843   else
11844     {
11845       names64 = att_names64;
11846       names32 = att_names32;
11847       names16 = att_names16;
11848       names8 = att_names8;
11849       names8rex = att_names8rex;
11850       names_seg = att_names_seg;
11851       names_mm = att_names_mm;
11852       names_bnd = att_names_bnd;
11853       names_xmm = att_names_xmm;
11854       names_ymm = att_names_ymm;
11855       names_zmm = att_names_zmm;
11856       index64 = att_index64;
11857       index32 = att_index32;
11858       names_mask = att_names_mask;
11859       index16 = att_index16;
11860       open_char = '(';
11861       close_char =  ')';
11862       separator_char = ',';
11863       scale_char = ',';
11864     }
11865
11866   /* The output looks better if we put 7 bytes on a line, since that
11867      puts most long word instructions on a single line.  Use 8 bytes
11868      for Intel L1OM.  */
11869   if ((info->mach & bfd_mach_l1om) != 0)
11870     info->bytes_per_line = 8;
11871   else
11872     info->bytes_per_line = 7;
11873
11874   info->private_data = &priv;
11875   priv.max_fetched = priv.the_buffer;
11876   priv.insn_start = pc;
11877
11878   obuf[0] = 0;
11879   for (i = 0; i < MAX_OPERANDS; ++i)
11880     {
11881       op_out[i][0] = 0;
11882       op_index[i] = -1;
11883     }
11884
11885   the_info = info;
11886   start_pc = pc;
11887   start_codep = priv.the_buffer;
11888   codep = priv.the_buffer;
11889
11890   if (OPCODES_SIGSETJMP (priv.bailout) != 0)
11891     {
11892       const char *name;
11893
11894       /* Getting here means we tried for data but didn't get it.  That
11895          means we have an incomplete instruction of some sort.  Just
11896          print the first byte as a prefix or a .byte pseudo-op.  */
11897       if (codep > priv.the_buffer)
11898         {
11899           name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
11900           if (name != NULL)
11901             (*info->fprintf_func) (info->stream, "%s", name);
11902           else
11903             {
11904               /* Just print the first byte as a .byte instruction.  */
11905               (*info->fprintf_func) (info->stream, ".byte 0x%x",
11906                                      (unsigned int) priv.the_buffer[0]);
11907             }
11908
11909           return 1;
11910         }
11911
11912       return -1;
11913     }
11914
11915   obufp = obuf;
11916   sizeflag = priv.orig_sizeflag;
11917
11918   if (!ckprefix () || rex_used)
11919     {
11920       /* Too many prefixes or unused REX prefixes.  */
11921       for (i = 0;
11922            i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i];
11923            i++)
11924         (*info->fprintf_func) (info->stream, "%s%s",
11925                                i == 0 ? "" : " ",
11926                                prefix_name (all_prefixes[i], sizeflag));
11927       return i;
11928     }
11929
11930   insn_codep = codep;
11931
11932   FETCH_DATA (info, codep + 1);
11933   two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
11934
11935   if (((prefixes & PREFIX_FWAIT)
11936        && ((*codep < 0xd8) || (*codep > 0xdf))))
11937     {
11938       /* Handle prefixes before fwait.  */
11939       for (i = 0; i < fwait_prefix && all_prefixes[i];
11940            i++)
11941         (*info->fprintf_func) (info->stream, "%s ",
11942                                prefix_name (all_prefixes[i], sizeflag));
11943       (*info->fprintf_func) (info->stream, "fwait");
11944       return i + 1;
11945     }
11946
11947   if (*codep == 0x0f)
11948     {
11949       unsigned char threebyte;
11950
11951       codep++;
11952       FETCH_DATA (info, codep + 1);
11953       threebyte = *codep;
11954       dp = &dis386_twobyte[threebyte];
11955       need_modrm = twobyte_has_modrm[*codep];
11956       codep++;
11957     }
11958   else
11959     {
11960       dp = &dis386[*codep];
11961       need_modrm = onebyte_has_modrm[*codep];
11962       codep++;
11963     }
11964
11965   /* Save sizeflag for printing the extra prefixes later before updating
11966      it for mnemonic and operand processing.  The prefix names depend
11967      only on the address mode.  */
11968   orig_sizeflag = sizeflag;
11969   if (prefixes & PREFIX_ADDR)
11970     sizeflag ^= AFLAG;
11971   if ((prefixes & PREFIX_DATA))
11972     sizeflag ^= DFLAG;
11973
11974   end_codep = codep;
11975   if (need_modrm)
11976     {
11977       FETCH_DATA (info, codep + 1);
11978       modrm.mod = (*codep >> 6) & 3;
11979       modrm.reg = (*codep >> 3) & 7;
11980       modrm.rm = *codep & 7;
11981     }
11982
11983   need_vex = 0;
11984   need_vex_reg = 0;
11985   vex_w_done = 0;
11986   memset (&vex, 0, sizeof (vex));
11987
11988   if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
11989     {
11990       get_sib (info, sizeflag);
11991       dofloat (sizeflag);
11992     }
11993   else
11994     {
11995       dp = get_valid_dis386 (dp, info);
11996       if (dp != NULL && putop (dp->name, sizeflag) == 0)
11997         {
11998           get_sib (info, sizeflag);
11999           for (i = 0; i < MAX_OPERANDS; ++i)
12000             {
12001               obufp = op_out[i];
12002               op_ad = MAX_OPERANDS - 1 - i;
12003               if (dp->op[i].rtn)
12004                 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
12005               /* For EVEX instruction after the last operand masking
12006                  should be printed.  */
12007               if (i == 0 && vex.evex)
12008                 {
12009                   /* Don't print {%k0}.  */
12010                   if (vex.mask_register_specifier)
12011                     {
12012                       oappend ("{");
12013                       oappend (names_mask[vex.mask_register_specifier]);
12014                       oappend ("}");
12015                     }
12016                   if (vex.zeroing)
12017                     oappend ("{z}");
12018                 }
12019             }
12020         }
12021     }
12022
12023   /* Clear instruction information.  */
12024   if (the_info)
12025     {
12026       the_info->insn_info_valid = 0;
12027       the_info->branch_delay_insns = 0;
12028       the_info->data_size = 0;
12029       the_info->insn_type = dis_noninsn;
12030       the_info->target = 0;
12031       the_info->target2 = 0;
12032     }
12033
12034   /* Reset jump operation indicator.  */
12035   op_is_jump = FALSE;
12036
12037   {
12038     int jump_detection = 0;
12039
12040     /* Extract flags.  */
12041     for (i = 0; i < MAX_OPERANDS; ++i)
12042       {
12043         if ((dp->op[i].rtn == OP_J)
12044             || (dp->op[i].rtn == OP_indirE))
12045           jump_detection |= 1;
12046         else if ((dp->op[i].rtn == BND_Fixup)
12047                  || (!dp->op[i].rtn && !dp->op[i].bytemode))
12048           jump_detection |= 2;
12049         else if ((dp->op[i].bytemode == cond_jump_mode)
12050                  || (dp->op[i].bytemode == loop_jcxz_mode))
12051           jump_detection |= 4;
12052       }
12053
12054     /* Determine if this is a jump or branch.  */
12055     if ((jump_detection & 0x3) == 0x3)
12056       {
12057         op_is_jump = TRUE;
12058         if (jump_detection & 0x4)
12059           the_info->insn_type = dis_condbranch;
12060         else
12061           the_info->insn_type =
12062             (dp->name && !strncmp(dp->name, "call", 4))
12063             ? dis_jsr : dis_branch;
12064       }
12065   }
12066
12067   /* If VEX.vvvv and EVEX.vvvv are unused, they must be all 1s, which
12068      are all 0s in inverted form.  */
12069   if (need_vex && vex.register_specifier != 0)
12070     {
12071       (*info->fprintf_func) (info->stream, "(bad)");
12072       return end_codep - priv.the_buffer;
12073     }
12074
12075   /* Check if the REX prefix is used.  */
12076   if ((rex ^ rex_used) == 0 && !need_vex && last_rex_prefix >= 0)
12077     all_prefixes[last_rex_prefix] = 0;
12078
12079   /* Check if the SEG prefix is used.  */
12080   if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
12081                    | PREFIX_FS | PREFIX_GS)) != 0
12082       && (used_prefixes & active_seg_prefix) != 0)
12083     all_prefixes[last_seg_prefix] = 0;
12084
12085   /* Check if the ADDR prefix is used.  */
12086   if ((prefixes & PREFIX_ADDR) != 0
12087       && (used_prefixes & PREFIX_ADDR) != 0)
12088     all_prefixes[last_addr_prefix] = 0;
12089
12090   /* Check if the DATA prefix is used.  */
12091   if ((prefixes & PREFIX_DATA) != 0
12092       && (used_prefixes & PREFIX_DATA) != 0
12093       && !need_vex)
12094     all_prefixes[last_data_prefix] = 0;
12095
12096   /* Print the extra prefixes.  */
12097   prefix_length = 0;
12098   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
12099     if (all_prefixes[i])
12100       {
12101         const char *name;
12102         name = prefix_name (all_prefixes[i], orig_sizeflag);
12103         if (name == NULL)
12104           abort ();
12105         prefix_length += strlen (name) + 1;
12106         (*info->fprintf_func) (info->stream, "%s ", name);
12107       }
12108
12109   /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
12110      unused, opcode is invalid.  Since the PREFIX_DATA prefix may be
12111      used by putop and MMX/SSE operand and may be overriden by the
12112      PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
12113      separately.  */
12114   if (dp->prefix_requirement == PREFIX_OPCODE
12115       && (((need_vex
12116             ? vex.prefix == REPE_PREFIX_OPCODE
12117               || vex.prefix == REPNE_PREFIX_OPCODE
12118             : (prefixes
12119                & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
12120            && (used_prefixes
12121                & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
12122           || (((need_vex
12123                 ? vex.prefix == DATA_PREFIX_OPCODE
12124                 : ((prefixes
12125                     & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
12126                    == PREFIX_DATA))
12127                && (used_prefixes & PREFIX_DATA) == 0))
12128           || (vex.evex && !vex.w != !(used_prefixes & PREFIX_DATA))))
12129     {
12130       (*info->fprintf_func) (info->stream, "(bad)");
12131       return end_codep - priv.the_buffer;
12132     }
12133
12134   /* Check maximum code length.  */
12135   if ((codep - start_codep) > MAX_CODE_LENGTH)
12136     {
12137       (*info->fprintf_func) (info->stream, "(bad)");
12138       return MAX_CODE_LENGTH;
12139     }
12140
12141   obufp = mnemonicendp;
12142   for (i = strlen (obuf) + prefix_length; i < 6; i++)
12143     oappend (" ");
12144   oappend (" ");
12145   (*info->fprintf_func) (info->stream, "%s", obuf);
12146
12147   /* The enter and bound instructions are printed with operands in the same
12148      order as the intel book; everything else is printed in reverse order.  */
12149   if (intel_syntax || two_source_ops)
12150     {
12151       bfd_vma riprel;
12152
12153       for (i = 0; i < MAX_OPERANDS; ++i)
12154         op_txt[i] = op_out[i];
12155
12156       if (intel_syntax && dp && dp->op[2].rtn == OP_Rounding
12157           && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL)
12158         {
12159           op_txt[2] = op_out[3];
12160           op_txt[3] = op_out[2];
12161         }
12162
12163       for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
12164         {
12165           op_ad = op_index[i];
12166           op_index[i] = op_index[MAX_OPERANDS - 1 - i];
12167           op_index[MAX_OPERANDS - 1 - i] = op_ad;
12168           riprel = op_riprel[i];
12169           op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
12170           op_riprel[MAX_OPERANDS - 1 - i] = riprel;
12171         }
12172     }
12173   else
12174     {
12175       for (i = 0; i < MAX_OPERANDS; ++i)
12176         op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
12177     }
12178
12179   needcomma = 0;
12180   for (i = 0; i < MAX_OPERANDS; ++i)
12181     if (*op_txt[i])
12182       {
12183         if (needcomma)
12184           (*info->fprintf_func) (info->stream, ",");
12185         if (op_index[i] != -1 && !op_riprel[i])
12186           {
12187             bfd_vma target = (bfd_vma) op_address[op_index[i]];
12188
12189             if (the_info && op_is_jump)
12190               {
12191                 the_info->insn_info_valid = 1;
12192                 the_info->branch_delay_insns = 0;
12193                 the_info->data_size = 0;
12194                 the_info->target = target;
12195                 the_info->target2 = 0;
12196               }
12197             (*info->print_address_func) (target, info);
12198           }
12199         else
12200           (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
12201         needcomma = 1;
12202       }
12203
12204   for (i = 0; i < MAX_OPERANDS; i++)
12205     if (op_index[i] != -1 && op_riprel[i])
12206       {
12207         (*info->fprintf_func) (info->stream, "        # ");
12208         (*info->print_address_func) ((bfd_vma) (start_pc + (codep - start_codep)
12209                                                 + op_address[op_index[i]]), info);
12210         break;
12211       }
12212   return codep - priv.the_buffer;
12213 }
12214
12215 static const char *float_mem[] = {
12216   /* d8 */
12217   "fadd{s|}",
12218   "fmul{s|}",
12219   "fcom{s|}",
12220   "fcomp{s|}",
12221   "fsub{s|}",
12222   "fsubr{s|}",
12223   "fdiv{s|}",
12224   "fdivr{s|}",
12225   /* d9 */
12226   "fld{s|}",
12227   "(bad)",
12228   "fst{s|}",
12229   "fstp{s|}",
12230   "fldenv{C|C}",
12231   "fldcw",
12232   "fNstenv{C|C}",
12233   "fNstcw",
12234   /* da */
12235   "fiadd{l|}",
12236   "fimul{l|}",
12237   "ficom{l|}",
12238   "ficomp{l|}",
12239   "fisub{l|}",
12240   "fisubr{l|}",
12241   "fidiv{l|}",
12242   "fidivr{l|}",
12243   /* db */
12244   "fild{l|}",
12245   "fisttp{l|}",
12246   "fist{l|}",
12247   "fistp{l|}",
12248   "(bad)",
12249   "fld{t|}",
12250   "(bad)",
12251   "fstp{t|}",
12252   /* dc */
12253   "fadd{l|}",
12254   "fmul{l|}",
12255   "fcom{l|}",
12256   "fcomp{l|}",
12257   "fsub{l|}",
12258   "fsubr{l|}",
12259   "fdiv{l|}",
12260   "fdivr{l|}",
12261   /* dd */
12262   "fld{l|}",
12263   "fisttp{ll|}",
12264   "fst{l||}",
12265   "fstp{l|}",
12266   "frstor{C|C}",
12267   "(bad)",
12268   "fNsave{C|C}",
12269   "fNstsw",
12270   /* de */
12271   "fiadd{s|}",
12272   "fimul{s|}",
12273   "ficom{s|}",
12274   "ficomp{s|}",
12275   "fisub{s|}",
12276   "fisubr{s|}",
12277   "fidiv{s|}",
12278   "fidivr{s|}",
12279   /* df */
12280   "fild{s|}",
12281   "fisttp{s|}",
12282   "fist{s|}",
12283   "fistp{s|}",
12284   "fbld",
12285   "fild{ll|}",
12286   "fbstp",
12287   "fistp{ll|}",
12288 };
12289
12290 static const unsigned char float_mem_mode[] = {
12291   /* d8 */
12292   d_mode,
12293   d_mode,
12294   d_mode,
12295   d_mode,
12296   d_mode,
12297   d_mode,
12298   d_mode,
12299   d_mode,
12300   /* d9 */
12301   d_mode,
12302   0,
12303   d_mode,
12304   d_mode,
12305   0,
12306   w_mode,
12307   0,
12308   w_mode,
12309   /* da */
12310   d_mode,
12311   d_mode,
12312   d_mode,
12313   d_mode,
12314   d_mode,
12315   d_mode,
12316   d_mode,
12317   d_mode,
12318   /* db */
12319   d_mode,
12320   d_mode,
12321   d_mode,
12322   d_mode,
12323   0,
12324   t_mode,
12325   0,
12326   t_mode,
12327   /* dc */
12328   q_mode,
12329   q_mode,
12330   q_mode,
12331   q_mode,
12332   q_mode,
12333   q_mode,
12334   q_mode,
12335   q_mode,
12336   /* dd */
12337   q_mode,
12338   q_mode,
12339   q_mode,
12340   q_mode,
12341   0,
12342   0,
12343   0,
12344   w_mode,
12345   /* de */
12346   w_mode,
12347   w_mode,
12348   w_mode,
12349   w_mode,
12350   w_mode,
12351   w_mode,
12352   w_mode,
12353   w_mode,
12354   /* df */
12355   w_mode,
12356   w_mode,
12357   w_mode,
12358   w_mode,
12359   t_mode,
12360   q_mode,
12361   t_mode,
12362   q_mode
12363 };
12364
12365 #define ST { OP_ST, 0 }
12366 #define STi { OP_STi, 0 }
12367
12368 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
12369 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
12370 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
12371 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
12372 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
12373 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
12374 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
12375 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
12376 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
12377
12378 static const struct dis386 float_reg[][8] = {
12379   /* d8 */
12380   {
12381     { "fadd",   { ST, STi }, 0 },
12382     { "fmul",   { ST, STi }, 0 },
12383     { "fcom",   { STi }, 0 },
12384     { "fcomp",  { STi }, 0 },
12385     { "fsub",   { ST, STi }, 0 },
12386     { "fsubr",  { ST, STi }, 0 },
12387     { "fdiv",   { ST, STi }, 0 },
12388     { "fdivr",  { ST, STi }, 0 },
12389   },
12390   /* d9 */
12391   {
12392     { "fld",    { STi }, 0 },
12393     { "fxch",   { STi }, 0 },
12394     { FGRPd9_2 },
12395     { Bad_Opcode },
12396     { FGRPd9_4 },
12397     { FGRPd9_5 },
12398     { FGRPd9_6 },
12399     { FGRPd9_7 },
12400   },
12401   /* da */
12402   {
12403     { "fcmovb", { ST, STi }, 0 },
12404     { "fcmove", { ST, STi }, 0 },
12405     { "fcmovbe",{ ST, STi }, 0 },
12406     { "fcmovu", { ST, STi }, 0 },
12407     { Bad_Opcode },
12408     { FGRPda_5 },
12409     { Bad_Opcode },
12410     { Bad_Opcode },
12411   },
12412   /* db */
12413   {
12414     { "fcmovnb",{ ST, STi }, 0 },
12415     { "fcmovne",{ ST, STi }, 0 },
12416     { "fcmovnbe",{ ST, STi }, 0 },
12417     { "fcmovnu",{ ST, STi }, 0 },
12418     { FGRPdb_4 },
12419     { "fucomi", { ST, STi }, 0 },
12420     { "fcomi",  { ST, STi }, 0 },
12421     { Bad_Opcode },
12422   },
12423   /* dc */
12424   {
12425     { "fadd",   { STi, ST }, 0 },
12426     { "fmul",   { STi, ST }, 0 },
12427     { Bad_Opcode },
12428     { Bad_Opcode },
12429     { "fsub{!M|r}",     { STi, ST }, 0 },
12430     { "fsub{M|}",       { STi, ST }, 0 },
12431     { "fdiv{!M|r}",     { STi, ST }, 0 },
12432     { "fdiv{M|}",       { STi, ST }, 0 },
12433   },
12434   /* dd */
12435   {
12436     { "ffree",  { STi }, 0 },
12437     { Bad_Opcode },
12438     { "fst",    { STi }, 0 },
12439     { "fstp",   { STi }, 0 },
12440     { "fucom",  { STi }, 0 },
12441     { "fucomp", { STi }, 0 },
12442     { Bad_Opcode },
12443     { Bad_Opcode },
12444   },
12445   /* de */
12446   {
12447     { "faddp",  { STi, ST }, 0 },
12448     { "fmulp",  { STi, ST }, 0 },
12449     { Bad_Opcode },
12450     { FGRPde_3 },
12451     { "fsub{!M|r}p",    { STi, ST }, 0 },
12452     { "fsub{M|}p",      { STi, ST }, 0 },
12453     { "fdiv{!M|r}p",    { STi, ST }, 0 },
12454     { "fdiv{M|}p",      { STi, ST }, 0 },
12455   },
12456   /* df */
12457   {
12458     { "ffreep", { STi }, 0 },
12459     { Bad_Opcode },
12460     { Bad_Opcode },
12461     { Bad_Opcode },
12462     { FGRPdf_4 },
12463     { "fucomip", { ST, STi }, 0 },
12464     { "fcomip", { ST, STi }, 0 },
12465     { Bad_Opcode },
12466   },
12467 };
12468
12469 static char *fgrps[][8] = {
12470   /* Bad opcode 0 */
12471   {
12472     "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12473   },
12474
12475   /* d9_2  1 */
12476   {
12477     "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12478   },
12479
12480   /* d9_4  2 */
12481   {
12482     "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
12483   },
12484
12485   /* d9_5  3 */
12486   {
12487     "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
12488   },
12489
12490   /* d9_6  4 */
12491   {
12492     "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
12493   },
12494
12495   /* d9_7  5 */
12496   {
12497     "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
12498   },
12499
12500   /* da_5  6 */
12501   {
12502     "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12503   },
12504
12505   /* db_4  7 */
12506   {
12507     "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
12508     "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
12509   },
12510
12511   /* de_3  8 */
12512   {
12513     "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12514   },
12515
12516   /* df_4  9 */
12517   {
12518     "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12519   },
12520 };
12521
12522 static void
12523 swap_operand (void)
12524 {
12525   mnemonicendp[0] = '.';
12526   mnemonicendp[1] = 's';
12527   mnemonicendp += 2;
12528 }
12529
12530 static void
12531 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
12532                int sizeflag ATTRIBUTE_UNUSED)
12533 {
12534   /* Skip mod/rm byte.  */
12535   MODRM_CHECK;
12536   codep++;
12537 }
12538
12539 static void
12540 dofloat (int sizeflag)
12541 {
12542   const struct dis386 *dp;
12543   unsigned char floatop;
12544
12545   floatop = codep[-1];
12546
12547   if (modrm.mod != 3)
12548     {
12549       int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
12550
12551       putop (float_mem[fp_indx], sizeflag);
12552       obufp = op_out[0];
12553       op_ad = 2;
12554       OP_E (float_mem_mode[fp_indx], sizeflag);
12555       return;
12556     }
12557   /* Skip mod/rm byte.  */
12558   MODRM_CHECK;
12559   codep++;
12560
12561   dp = &float_reg[floatop - 0xd8][modrm.reg];
12562   if (dp->name == NULL)
12563     {
12564       putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
12565
12566       /* Instruction fnstsw is only one with strange arg.  */
12567       if (floatop == 0xdf && codep[-1] == 0xe0)
12568         strcpy (op_out[0], names16[0]);
12569     }
12570   else
12571     {
12572       putop (dp->name, sizeflag);
12573
12574       obufp = op_out[0];
12575       op_ad = 2;
12576       if (dp->op[0].rtn)
12577         (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
12578
12579       obufp = op_out[1];
12580       op_ad = 1;
12581       if (dp->op[1].rtn)
12582         (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
12583     }
12584 }
12585
12586 /* Like oappend (below), but S is a string starting with '%'.
12587    In Intel syntax, the '%' is elided.  */
12588 static void
12589 oappend_maybe_intel (const char *s)
12590 {
12591   oappend (s + intel_syntax);
12592 }
12593
12594 static void
12595 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12596 {
12597   oappend_maybe_intel ("%st");
12598 }
12599
12600 static void
12601 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12602 {
12603   sprintf (scratchbuf, "%%st(%d)", modrm.rm);
12604   oappend_maybe_intel (scratchbuf);
12605 }
12606
12607 /* Capital letters in template are macros.  */
12608 static int
12609 putop (const char *in_template, int sizeflag)
12610 {
12611   const char *p;
12612   int alt = 0;
12613   int cond = 1;
12614   unsigned int l = 0, len = 0;
12615   char last[4];
12616
12617   for (p = in_template; *p; p++)
12618     {
12619       if (len > l)
12620         {
12621           if (l >= sizeof (last) || !ISUPPER (*p))
12622             abort ();
12623           last[l++] = *p;
12624           continue;
12625         }
12626       switch (*p)
12627         {
12628         default:
12629           *obufp++ = *p;
12630           break;
12631         case '%':
12632           len++;
12633           break;
12634         case '!':
12635           cond = 0;
12636           break;
12637         case '{':
12638           if (intel_syntax)
12639             {
12640               while (*++p != '|')
12641                 if (*p == '}' || *p == '\0')
12642                   abort ();
12643               alt = 1;
12644             }
12645           break;
12646         case '|':
12647           while (*++p != '}')
12648             {
12649               if (*p == '\0')
12650                 abort ();
12651             }
12652           break;
12653         case '}':
12654           alt = 0;
12655           break;
12656         case 'A':
12657           if (intel_syntax)
12658             break;
12659           if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
12660             *obufp++ = 'b';
12661           break;
12662         case 'B':
12663           if (l == 0)
12664             {
12665             case_B:
12666               if (intel_syntax)
12667                 break;
12668               if (sizeflag & SUFFIX_ALWAYS)
12669                 *obufp++ = 'b';
12670             }
12671           else if (l == 1 && last[0] == 'L')
12672             {
12673               if (address_mode == mode_64bit
12674                   && !(prefixes & PREFIX_ADDR))
12675                 {
12676                   *obufp++ = 'a';
12677                   *obufp++ = 'b';
12678                   *obufp++ = 's';
12679                 }
12680
12681               goto case_B;
12682             }
12683           else
12684             abort ();
12685           break;
12686         case 'C':
12687           if (intel_syntax && !alt)
12688             break;
12689           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
12690             {
12691               if (sizeflag & DFLAG)
12692                 *obufp++ = intel_syntax ? 'd' : 'l';
12693               else
12694                 *obufp++ = intel_syntax ? 'w' : 's';
12695               used_prefixes |= (prefixes & PREFIX_DATA);
12696             }
12697           break;
12698         case 'D':
12699           if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
12700             break;
12701           USED_REX (REX_W);
12702           if (modrm.mod == 3)
12703             {
12704               if (rex & REX_W)
12705                 *obufp++ = 'q';
12706               else
12707                 {
12708                   if (sizeflag & DFLAG)
12709                     *obufp++ = intel_syntax ? 'd' : 'l';
12710                   else
12711                     *obufp++ = 'w';
12712                   used_prefixes |= (prefixes & PREFIX_DATA);
12713                 }
12714             }
12715           else
12716             *obufp++ = 'w';
12717           break;
12718         case 'E':               /* For jcxz/jecxz */
12719           if (address_mode == mode_64bit)
12720             {
12721               if (sizeflag & AFLAG)
12722                 *obufp++ = 'r';
12723               else
12724                 *obufp++ = 'e';
12725             }
12726           else
12727             if (sizeflag & AFLAG)
12728               *obufp++ = 'e';
12729           used_prefixes |= (prefixes & PREFIX_ADDR);
12730           break;
12731         case 'F':
12732           if (intel_syntax)
12733             break;
12734           if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
12735             {
12736               if (sizeflag & AFLAG)
12737                 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
12738               else
12739                 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
12740               used_prefixes |= (prefixes & PREFIX_ADDR);
12741             }
12742           break;
12743         case 'G':
12744           if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
12745             break;
12746           if ((rex & REX_W) || (sizeflag & DFLAG))
12747             *obufp++ = 'l';
12748           else
12749             *obufp++ = 'w';
12750           if (!(rex & REX_W))
12751             used_prefixes |= (prefixes & PREFIX_DATA);
12752           break;
12753         case 'H':
12754           if (intel_syntax)
12755             break;
12756           if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
12757               || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
12758             {
12759               used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
12760               *obufp++ = ',';
12761               *obufp++ = 'p';
12762               if (prefixes & PREFIX_DS)
12763                 *obufp++ = 't';
12764               else
12765                 *obufp++ = 'n';
12766             }
12767           break;
12768         case 'K':
12769           USED_REX (REX_W);
12770           if (rex & REX_W)
12771             *obufp++ = 'q';
12772           else
12773             *obufp++ = 'd';
12774           break;
12775         case 'Z':
12776           if (l != 0)
12777             {
12778               if (l != 1 || last[0] != 'X')
12779                 abort ();
12780               if (!need_vex || !vex.evex)
12781                 abort ();
12782               if (intel_syntax
12783                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
12784                 break;
12785               switch (vex.length)
12786                 {
12787                 case 128:
12788                   *obufp++ = 'x';
12789                   break;
12790                 case 256:
12791                   *obufp++ = 'y';
12792                   break;
12793                 case 512:
12794                   *obufp++ = 'z';
12795                   break;
12796                 default:
12797                   abort ();
12798                 }
12799               break;
12800             }
12801           if (intel_syntax)
12802             break;
12803           if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
12804             {
12805               *obufp++ = 'q';
12806               break;
12807             }
12808           /* Fall through.  */
12809           goto case_L;
12810         case 'L':
12811           if (l != 0)
12812             abort ();
12813         case_L:
12814           if (intel_syntax)
12815             break;
12816           if (sizeflag & SUFFIX_ALWAYS)
12817             *obufp++ = 'l';
12818           break;
12819         case 'M':
12820           if (intel_mnemonic != cond)
12821             *obufp++ = 'r';
12822           break;
12823         case 'N':
12824           if ((prefixes & PREFIX_FWAIT) == 0)
12825             *obufp++ = 'n';
12826           else
12827             used_prefixes |= PREFIX_FWAIT;
12828           break;
12829         case 'O':
12830           USED_REX (REX_W);
12831           if (rex & REX_W)
12832             *obufp++ = 'o';
12833           else if (intel_syntax && (sizeflag & DFLAG))
12834             *obufp++ = 'q';
12835           else
12836             *obufp++ = 'd';
12837           if (!(rex & REX_W))
12838             used_prefixes |= (prefixes & PREFIX_DATA);
12839           break;
12840         case '&':
12841           if (!intel_syntax
12842               && address_mode == mode_64bit
12843               && isa64 == intel64)
12844             {
12845               *obufp++ = 'q';
12846               break;
12847             }
12848           /* Fall through.  */
12849         case 'T':
12850           if (!intel_syntax
12851               && address_mode == mode_64bit
12852               && ((sizeflag & DFLAG) || (rex & REX_W)))
12853             {
12854               *obufp++ = 'q';
12855               break;
12856             }
12857           /* Fall through.  */
12858           goto case_P;
12859         case 'P':
12860           if (l == 0)
12861             {
12862             case_P:
12863               if (intel_syntax)
12864                 {
12865                   if ((rex & REX_W) == 0
12866                       && (prefixes & PREFIX_DATA))
12867                     {
12868                       if ((sizeflag & DFLAG) == 0)
12869                         *obufp++ = 'w';
12870                       used_prefixes |= (prefixes & PREFIX_DATA);
12871                     }
12872                   break;
12873                 }
12874               if ((prefixes & PREFIX_DATA)
12875                   || (rex & REX_W)
12876                   || (sizeflag & SUFFIX_ALWAYS))
12877                 {
12878                   USED_REX (REX_W);
12879                   if (rex & REX_W)
12880                     *obufp++ = 'q';
12881                   else
12882                     {
12883                       if (sizeflag & DFLAG)
12884                         *obufp++ = 'l';
12885                       else
12886                         *obufp++ = 'w';
12887                       used_prefixes |= (prefixes & PREFIX_DATA);
12888                     }
12889                 }
12890             }
12891           else if (l == 1 && last[0] == 'L')
12892             {
12893               if ((prefixes & PREFIX_DATA)
12894                   || (rex & REX_W)
12895                   || (sizeflag & SUFFIX_ALWAYS))
12896                 {
12897                   USED_REX (REX_W);
12898                   if (rex & REX_W)
12899                     *obufp++ = 'q';
12900                   else
12901                     {
12902                       if (sizeflag & DFLAG)
12903                         *obufp++ = intel_syntax ? 'd' : 'l';
12904                       else
12905                         *obufp++ = 'w';
12906                       used_prefixes |= (prefixes & PREFIX_DATA);
12907                     }
12908                 }
12909             }
12910           else
12911             abort ();
12912           break;
12913         case 'U':
12914           if (intel_syntax)
12915             break;
12916           if (address_mode == mode_64bit
12917               && ((sizeflag & DFLAG) || (rex & REX_W)))
12918             {
12919               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
12920                 *obufp++ = 'q';
12921               break;
12922             }
12923           /* Fall through.  */
12924           goto case_Q;
12925         case 'Q':
12926           if (l == 0)
12927             {
12928             case_Q:
12929               if (intel_syntax && !alt)
12930                 break;
12931               USED_REX (REX_W);
12932               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
12933                 {
12934                   if (rex & REX_W)
12935                     *obufp++ = 'q';
12936                   else
12937                     {
12938                       if (sizeflag & DFLAG)
12939                         *obufp++ = intel_syntax ? 'd' : 'l';
12940                       else
12941                         *obufp++ = 'w';
12942                       used_prefixes |= (prefixes & PREFIX_DATA);
12943                     }
12944                 }
12945             }
12946           else if (l == 1 && last[0] == 'L')
12947             {
12948               if ((intel_syntax && need_modrm)
12949                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
12950                 break;
12951               if ((rex & REX_W))
12952                 {
12953                   USED_REX (REX_W);
12954                   *obufp++ = 'q';
12955                 }
12956               else if((address_mode == mode_64bit && need_modrm)
12957                       || (sizeflag & SUFFIX_ALWAYS))
12958                 *obufp++ = intel_syntax? 'd' : 'l';
12959             }
12960           else
12961             abort ();
12962           break;
12963         case 'R':
12964           USED_REX (REX_W);
12965           if (rex & REX_W)
12966             *obufp++ = 'q';
12967           else if (sizeflag & DFLAG)
12968             {
12969               if (intel_syntax)
12970                   *obufp++ = 'd';
12971               else
12972                   *obufp++ = 'l';
12973             }
12974           else
12975             *obufp++ = 'w';
12976           if (intel_syntax && !p[1]
12977               && ((rex & REX_W) || (sizeflag & DFLAG)))
12978             *obufp++ = 'e';
12979           if (!(rex & REX_W))
12980             used_prefixes |= (prefixes & PREFIX_DATA);
12981           break;
12982         case 'V':
12983           if (l == 0)
12984             {
12985               if (intel_syntax)
12986                 break;
12987               if (address_mode == mode_64bit
12988                   && ((sizeflag & DFLAG) || (rex & REX_W)))
12989                 {
12990                   if (sizeflag & SUFFIX_ALWAYS)
12991                     *obufp++ = 'q';
12992                   break;
12993                 }
12994             }
12995           else if (l == 1 && last[0] == 'L')
12996             {
12997               if (rex & REX_W)
12998                 {
12999                   *obufp++ = 'a';
13000                   *obufp++ = 'b';
13001                   *obufp++ = 's';
13002                 }
13003             }
13004           else
13005             abort ();
13006           /* Fall through.  */
13007           goto case_S;
13008         case 'S':
13009           if (l == 0)
13010             {
13011             case_S:
13012               if (intel_syntax)
13013                 break;
13014               if (sizeflag & SUFFIX_ALWAYS)
13015                 {
13016                   if (rex & REX_W)
13017                     *obufp++ = 'q';
13018                   else
13019                     {
13020                       if (sizeflag & DFLAG)
13021                         *obufp++ = 'l';
13022                       else
13023                         *obufp++ = 'w';
13024                       used_prefixes |= (prefixes & PREFIX_DATA);
13025                     }
13026                 }
13027             }
13028           else if (l == 1 && last[0] == 'L')
13029             {
13030               if (address_mode == mode_64bit
13031                   && !(prefixes & PREFIX_ADDR))
13032                 {
13033                   *obufp++ = 'a';
13034                   *obufp++ = 'b';
13035                   *obufp++ = 's';
13036                 }
13037
13038               goto case_S;
13039             }
13040           else
13041             abort ();
13042           break;
13043         case 'X':
13044           if (l != 0)
13045             abort ();
13046           if (need_vex
13047               ? vex.prefix == DATA_PREFIX_OPCODE
13048               : prefixes & PREFIX_DATA)
13049             {
13050               *obufp++ = 'd';
13051               used_prefixes |= PREFIX_DATA;
13052             }
13053           else
13054             *obufp++ = 's';
13055           break;
13056         case 'Y':
13057           if (l == 1 && last[0] == 'X')
13058             {
13059               if (!need_vex)
13060                 abort ();
13061               if (intel_syntax
13062                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
13063                 break;
13064               switch (vex.length)
13065                 {
13066                 case 128:
13067                   *obufp++ = 'x';
13068                   break;
13069                 case 256:
13070                   *obufp++ = 'y';
13071                   break;
13072                 case 512:
13073                   if (!vex.evex)
13074                 default:
13075                     abort ();
13076                 }
13077             }
13078           else
13079             abort ();
13080           break;
13081         case 'W':
13082           if (l == 0)
13083             {
13084               /* operand size flag for cwtl, cbtw */
13085               USED_REX (REX_W);
13086               if (rex & REX_W)
13087                 {
13088                   if (intel_syntax)
13089                     *obufp++ = 'd';
13090                   else
13091                     *obufp++ = 'l';
13092                 }
13093               else if (sizeflag & DFLAG)
13094                 *obufp++ = 'w';
13095               else
13096                 *obufp++ = 'b';
13097               if (!(rex & REX_W))
13098                 used_prefixes |= (prefixes & PREFIX_DATA);
13099             }
13100           else if (l == 1)
13101             {
13102               if (!need_vex)
13103                 abort ();
13104               if (last[0] == 'X')
13105                 *obufp++ = vex.w ? 'd': 's';
13106               else if (last[0] == 'L')
13107                 *obufp++ = vex.w ? 'q': 'd';
13108               else
13109                 abort ();
13110             }
13111           else
13112             abort ();
13113           break;
13114         case '^':
13115           if (intel_syntax)
13116             break;
13117           if (isa64 == intel64 && (rex & REX_W))
13118             {
13119               USED_REX (REX_W);
13120               *obufp++ = 'q';
13121               break;
13122             }
13123           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
13124             {
13125               if (sizeflag & DFLAG)
13126                 *obufp++ = 'l';
13127               else
13128                 *obufp++ = 'w';
13129               used_prefixes |= (prefixes & PREFIX_DATA);
13130             }
13131           break;
13132         case '@':
13133           if (intel_syntax)
13134             break;
13135           if (address_mode == mode_64bit
13136               && (isa64 == intel64
13137                   || ((sizeflag & DFLAG) || (rex & REX_W))))
13138               *obufp++ = 'q';
13139           else if ((prefixes & PREFIX_DATA))
13140             {
13141               if (!(sizeflag & DFLAG))
13142                 *obufp++ = 'w';
13143               used_prefixes |= (prefixes & PREFIX_DATA);
13144             }
13145           break;
13146         }
13147
13148       if (len == l)
13149         len = l = 0;
13150     }
13151   *obufp = 0;
13152   mnemonicendp = obufp;
13153   return 0;
13154 }
13155
13156 static void
13157 oappend (const char *s)
13158 {
13159   obufp = stpcpy (obufp, s);
13160 }
13161
13162 static void
13163 append_seg (void)
13164 {
13165   /* Only print the active segment register.  */
13166   if (!active_seg_prefix)
13167     return;
13168
13169   used_prefixes |= active_seg_prefix;
13170   switch (active_seg_prefix)
13171     {
13172     case PREFIX_CS:
13173       oappend_maybe_intel ("%cs:");
13174       break;
13175     case PREFIX_DS:
13176       oappend_maybe_intel ("%ds:");
13177       break;
13178     case PREFIX_SS:
13179       oappend_maybe_intel ("%ss:");
13180       break;
13181     case PREFIX_ES:
13182       oappend_maybe_intel ("%es:");
13183       break;
13184     case PREFIX_FS:
13185       oappend_maybe_intel ("%fs:");
13186       break;
13187     case PREFIX_GS:
13188       oappend_maybe_intel ("%gs:");
13189       break;
13190     default:
13191       break;
13192     }
13193 }
13194
13195 static void
13196 OP_indirE (int bytemode, int sizeflag)
13197 {
13198   if (!intel_syntax)
13199     oappend ("*");
13200   OP_E (bytemode, sizeflag);
13201 }
13202
13203 static void
13204 print_operand_value (char *buf, int hex, bfd_vma disp)
13205 {
13206   if (address_mode == mode_64bit)
13207     {
13208       if (hex)
13209         {
13210           char tmp[30];
13211           int i;
13212           buf[0] = '0';
13213           buf[1] = 'x';
13214           sprintf_vma (tmp, disp);
13215           for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
13216           strcpy (buf + 2, tmp + i);
13217         }
13218       else
13219         {
13220           bfd_signed_vma v = disp;
13221           char tmp[30];
13222           int i;
13223           if (v < 0)
13224             {
13225               *(buf++) = '-';
13226               v = -disp;
13227               /* Check for possible overflow on 0x8000000000000000.  */
13228               if (v < 0)
13229                 {
13230                   strcpy (buf, "9223372036854775808");
13231                   return;
13232                 }
13233             }
13234           if (!v)
13235             {
13236               strcpy (buf, "0");
13237               return;
13238             }
13239
13240           i = 0;
13241           tmp[29] = 0;
13242           while (v)
13243             {
13244               tmp[28 - i] = (v % 10) + '0';
13245               v /= 10;
13246               i++;
13247             }
13248           strcpy (buf, tmp + 29 - i);
13249         }
13250     }
13251   else
13252     {
13253       if (hex)
13254         sprintf (buf, "0x%x", (unsigned int) disp);
13255       else
13256         sprintf (buf, "%d", (int) disp);
13257     }
13258 }
13259
13260 /* Put DISP in BUF as signed hex number.  */
13261
13262 static void
13263 print_displacement (char *buf, bfd_vma disp)
13264 {
13265   bfd_signed_vma val = disp;
13266   char tmp[30];
13267   int i, j = 0;
13268
13269   if (val < 0)
13270     {
13271       buf[j++] = '-';
13272       val = -disp;
13273
13274       /* Check for possible overflow.  */
13275       if (val < 0)
13276         {
13277           switch (address_mode)
13278             {
13279             case mode_64bit:
13280               strcpy (buf + j, "0x8000000000000000");
13281               break;
13282             case mode_32bit:
13283               strcpy (buf + j, "0x80000000");
13284               break;
13285             case mode_16bit:
13286               strcpy (buf + j, "0x8000");
13287               break;
13288             }
13289           return;
13290         }
13291     }
13292
13293   buf[j++] = '0';
13294   buf[j++] = 'x';
13295
13296   sprintf_vma (tmp, (bfd_vma) val);
13297   for (i = 0; tmp[i] == '0'; i++)
13298     continue;
13299   if (tmp[i] == '\0')
13300     i--;
13301   strcpy (buf + j, tmp + i);
13302 }
13303
13304 static void
13305 intel_operand_size (int bytemode, int sizeflag)
13306 {
13307   if (vex.evex
13308       && vex.b
13309       && (bytemode == x_mode
13310           || bytemode == evex_half_bcst_xmmq_mode))
13311     {
13312       if (vex.w)
13313         oappend ("QWORD PTR ");
13314       else
13315         oappend ("DWORD PTR ");
13316       return;
13317     }
13318   switch (bytemode)
13319     {
13320     case b_mode:
13321     case b_swap_mode:
13322     case dqb_mode:
13323     case db_mode:
13324       oappend ("BYTE PTR ");
13325       break;
13326     case w_mode:
13327     case dw_mode:
13328     case dqw_mode:
13329       oappend ("WORD PTR ");
13330       break;
13331     case indir_v_mode:
13332       if (address_mode == mode_64bit && isa64 == intel64)
13333         {
13334           oappend ("QWORD PTR ");
13335           break;
13336         }
13337       /* Fall through.  */
13338     case stack_v_mode:
13339       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
13340         {
13341           oappend ("QWORD PTR ");
13342           break;
13343         }
13344       /* Fall through.  */
13345     case v_mode:
13346     case v_swap_mode:
13347     case dq_mode:
13348       USED_REX (REX_W);
13349       if (rex & REX_W)
13350         oappend ("QWORD PTR ");
13351       else
13352         {
13353           if ((sizeflag & DFLAG) || bytemode == dq_mode)
13354             oappend ("DWORD PTR ");
13355           else
13356             oappend ("WORD PTR ");
13357           used_prefixes |= (prefixes & PREFIX_DATA);
13358         }
13359       break;
13360     case z_mode:
13361       if ((rex & REX_W) || (sizeflag & DFLAG))
13362         *obufp++ = 'D';
13363       oappend ("WORD PTR ");
13364       if (!(rex & REX_W))
13365         used_prefixes |= (prefixes & PREFIX_DATA);
13366       break;
13367     case a_mode:
13368       if (sizeflag & DFLAG)
13369         oappend ("QWORD PTR ");
13370       else
13371         oappend ("DWORD PTR ");
13372       used_prefixes |= (prefixes & PREFIX_DATA);
13373       break;
13374     case movsxd_mode:
13375       if (!(sizeflag & DFLAG) && isa64 == intel64)
13376         oappend ("WORD PTR ");
13377       else
13378         oappend ("DWORD PTR ");
13379       used_prefixes |= (prefixes & PREFIX_DATA);
13380       break;
13381     case d_mode:
13382     case d_scalar_swap_mode:
13383     case d_swap_mode:
13384     case dqd_mode:
13385       oappend ("DWORD PTR ");
13386       break;
13387     case q_mode:
13388     case q_scalar_swap_mode:
13389     case q_swap_mode:
13390       oappend ("QWORD PTR ");
13391       break;
13392     case m_mode:
13393       if (address_mode == mode_64bit)
13394         oappend ("QWORD PTR ");
13395       else
13396         oappend ("DWORD PTR ");
13397       break;
13398     case f_mode:
13399       if (sizeflag & DFLAG)
13400         oappend ("FWORD PTR ");
13401       else
13402         oappend ("DWORD PTR ");
13403       used_prefixes |= (prefixes & PREFIX_DATA);
13404       break;
13405     case t_mode:
13406       oappend ("TBYTE PTR ");
13407       break;
13408     case x_mode:
13409     case x_swap_mode:
13410     case evex_x_gscat_mode:
13411     case evex_x_nobcst_mode:
13412     case b_scalar_mode:
13413     case w_scalar_mode:
13414       if (need_vex)
13415         {
13416           switch (vex.length)
13417             {
13418             case 128:
13419               oappend ("XMMWORD PTR ");
13420               break;
13421             case 256:
13422               oappend ("YMMWORD PTR ");
13423               break;
13424             case 512:
13425               oappend ("ZMMWORD PTR ");
13426               break;
13427             default:
13428               abort ();
13429             }
13430         }
13431       else
13432         oappend ("XMMWORD PTR ");
13433       break;
13434     case xmm_mode:
13435       oappend ("XMMWORD PTR ");
13436       break;
13437     case ymm_mode:
13438       oappend ("YMMWORD PTR ");
13439       break;
13440     case xmmq_mode:
13441     case evex_half_bcst_xmmq_mode:
13442       if (!need_vex)
13443         abort ();
13444
13445       switch (vex.length)
13446         {
13447         case 128:
13448           oappend ("QWORD PTR ");
13449           break;
13450         case 256:
13451           oappend ("XMMWORD PTR ");
13452           break;
13453         case 512:
13454           oappend ("YMMWORD PTR ");
13455           break;
13456         default:
13457           abort ();
13458         }
13459       break;
13460     case xmm_mb_mode:
13461       if (!need_vex)
13462         abort ();
13463
13464       switch (vex.length)
13465         {
13466         case 128:
13467         case 256:
13468         case 512:
13469           oappend ("BYTE PTR ");
13470           break;
13471         default:
13472           abort ();
13473         }
13474       break;
13475     case xmm_mw_mode:
13476       if (!need_vex)
13477         abort ();
13478
13479       switch (vex.length)
13480         {
13481         case 128:
13482         case 256:
13483         case 512:
13484           oappend ("WORD PTR ");
13485           break;
13486         default:
13487           abort ();
13488         }
13489       break;
13490     case xmm_md_mode:
13491       if (!need_vex)
13492         abort ();
13493
13494       switch (vex.length)
13495         {
13496         case 128:
13497         case 256:
13498         case 512:
13499           oappend ("DWORD PTR ");
13500           break;
13501         default:
13502           abort ();
13503         }
13504       break;
13505     case xmm_mq_mode:
13506       if (!need_vex)
13507         abort ();
13508
13509       switch (vex.length)
13510         {
13511         case 128:
13512         case 256:
13513         case 512:
13514           oappend ("QWORD PTR ");
13515           break;
13516         default:
13517           abort ();
13518         }
13519       break;
13520     case xmmdw_mode:
13521       if (!need_vex)
13522         abort ();
13523
13524       switch (vex.length)
13525         {
13526         case 128:
13527           oappend ("WORD PTR ");
13528           break;
13529         case 256:
13530           oappend ("DWORD PTR ");
13531           break;
13532         case 512:
13533           oappend ("QWORD PTR ");
13534           break;
13535         default:
13536           abort ();
13537         }
13538       break;
13539     case xmmqd_mode:
13540       if (!need_vex)
13541         abort ();
13542
13543       switch (vex.length)
13544         {
13545         case 128:
13546           oappend ("DWORD PTR ");
13547           break;
13548         case 256:
13549           oappend ("QWORD PTR ");
13550           break;
13551         case 512:
13552           oappend ("XMMWORD PTR ");
13553           break;
13554         default:
13555           abort ();
13556         }
13557       break;
13558     case ymmq_mode:
13559       if (!need_vex)
13560         abort ();
13561
13562       switch (vex.length)
13563         {
13564         case 128:
13565           oappend ("QWORD PTR ");
13566           break;
13567         case 256:
13568           oappend ("YMMWORD PTR ");
13569           break;
13570         case 512:
13571           oappend ("ZMMWORD PTR ");
13572           break;
13573         default:
13574           abort ();
13575         }
13576       break;
13577     case ymmxmm_mode:
13578       if (!need_vex)
13579         abort ();
13580
13581       switch (vex.length)
13582         {
13583         case 128:
13584         case 256:
13585           oappend ("XMMWORD PTR ");
13586           break;
13587         default:
13588           abort ();
13589         }
13590       break;
13591     case o_mode:
13592       oappend ("OWORD PTR ");
13593       break;
13594     case vex_scalar_w_dq_mode:
13595       if (!need_vex)
13596         abort ();
13597
13598       if (vex.w)
13599         oappend ("QWORD PTR ");
13600       else
13601         oappend ("DWORD PTR ");
13602       break;
13603     case vex_vsib_d_w_dq_mode:
13604     case vex_vsib_q_w_dq_mode:
13605       if (!need_vex)
13606         abort ();
13607
13608       if (!vex.evex)
13609         {
13610           if (vex.w)
13611             oappend ("QWORD PTR ");
13612           else
13613             oappend ("DWORD PTR ");
13614         }
13615       else
13616         {
13617           switch (vex.length)
13618             {
13619             case 128:
13620               oappend ("XMMWORD PTR ");
13621               break;
13622             case 256:
13623               oappend ("YMMWORD PTR ");
13624               break;
13625             case 512:
13626               oappend ("ZMMWORD PTR ");
13627               break;
13628             default:
13629               abort ();
13630             }
13631         }
13632       break;
13633     case vex_vsib_q_w_d_mode:
13634     case vex_vsib_d_w_d_mode:
13635       if (!need_vex || !vex.evex)
13636         abort ();
13637
13638       switch (vex.length)
13639         {
13640         case 128:
13641           oappend ("QWORD PTR ");
13642           break;
13643         case 256:
13644           oappend ("XMMWORD PTR ");
13645           break;
13646         case 512:
13647           oappend ("YMMWORD PTR ");
13648           break;
13649         default:
13650           abort ();
13651         }
13652
13653       break;
13654     case mask_bd_mode:
13655       if (!need_vex || vex.length != 128)
13656         abort ();
13657       if (vex.w)
13658         oappend ("DWORD PTR ");
13659       else
13660         oappend ("BYTE PTR ");
13661       break;
13662     case mask_mode:
13663       if (!need_vex)
13664         abort ();
13665       if (vex.w)
13666         oappend ("QWORD PTR ");
13667       else
13668         oappend ("WORD PTR ");
13669       break;
13670     case v_bnd_mode:
13671     case v_bndmk_mode:
13672     default:
13673       break;
13674     }
13675 }
13676
13677 static void
13678 OP_E_register (int bytemode, int sizeflag)
13679 {
13680   int reg = modrm.rm;
13681   const char **names;
13682
13683   USED_REX (REX_B);
13684   if ((rex & REX_B))
13685     reg += 8;
13686
13687   if ((sizeflag & SUFFIX_ALWAYS)
13688       && (bytemode == b_swap_mode
13689           || bytemode == bnd_swap_mode
13690           || bytemode == v_swap_mode))
13691     swap_operand ();
13692
13693   switch (bytemode)
13694     {
13695     case b_mode:
13696     case b_swap_mode:
13697       USED_REX (0);
13698       if (rex)
13699         names = names8rex;
13700       else
13701         names = names8;
13702       break;
13703     case w_mode:
13704       names = names16;
13705       break;
13706     case d_mode:
13707     case dw_mode:
13708     case db_mode:
13709       names = names32;
13710       break;
13711     case q_mode:
13712       names = names64;
13713       break;
13714     case m_mode:
13715     case v_bnd_mode:
13716       names = address_mode == mode_64bit ? names64 : names32;
13717       break;
13718     case bnd_mode:
13719     case bnd_swap_mode:
13720       if (reg > 0x3)
13721         {
13722           oappend ("(bad)");
13723           return;
13724         }
13725       names = names_bnd;
13726       break;
13727     case indir_v_mode:
13728       if (address_mode == mode_64bit && isa64 == intel64)
13729         {
13730           names = names64;
13731           break;
13732         }
13733       /* Fall through.  */
13734     case stack_v_mode:
13735       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
13736         {
13737           names = names64;
13738           break;
13739         }
13740       bytemode = v_mode;
13741       /* Fall through.  */
13742     case v_mode:
13743     case v_swap_mode:
13744     case dq_mode:
13745     case dqb_mode:
13746     case dqd_mode:
13747     case dqw_mode:
13748       USED_REX (REX_W);
13749       if (rex & REX_W)
13750         names = names64;
13751       else
13752         {
13753           if ((sizeflag & DFLAG)
13754               || (bytemode != v_mode
13755                   && bytemode != v_swap_mode))
13756             names = names32;
13757           else
13758             names = names16;
13759           used_prefixes |= (prefixes & PREFIX_DATA);
13760         }
13761       break;
13762     case movsxd_mode:
13763       if (!(sizeflag & DFLAG) && isa64 == intel64)
13764         names = names16;
13765       else
13766         names = names32;
13767       used_prefixes |= (prefixes & PREFIX_DATA);
13768       break;
13769     case va_mode:
13770       names = (address_mode == mode_64bit
13771                ? names64 : names32);
13772       if (!(prefixes & PREFIX_ADDR))
13773         names = (address_mode == mode_16bit
13774                      ? names16 : names);
13775       else
13776         {
13777           /* Remove "addr16/addr32".  */
13778           all_prefixes[last_addr_prefix] = 0;
13779           names = (address_mode != mode_32bit
13780                        ? names32 : names16);
13781           used_prefixes |= PREFIX_ADDR;
13782         }
13783       break;
13784     case mask_bd_mode:
13785     case mask_mode:
13786       if (reg > 0x7)
13787         {
13788           oappend ("(bad)");
13789           return;
13790         }
13791       names = names_mask;
13792       break;
13793     case 0:
13794       return;
13795     default:
13796       oappend (INTERNAL_DISASSEMBLER_ERROR);
13797       return;
13798     }
13799   oappend (names[reg]);
13800 }
13801
13802 static void
13803 OP_E_memory (int bytemode, int sizeflag)
13804 {
13805   bfd_vma disp = 0;
13806   int add = (rex & REX_B) ? 8 : 0;
13807   int riprel = 0;
13808   int shift;
13809
13810   if (vex.evex)
13811     {
13812       /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0.  */
13813       if (vex.b
13814           && bytemode != x_mode
13815           && bytemode != xmmq_mode
13816           && bytemode != evex_half_bcst_xmmq_mode)
13817         {
13818           BadOp ();
13819           return;
13820         }
13821       switch (bytemode)
13822         {
13823         case dqw_mode:
13824         case dw_mode:
13825           shift = 1;
13826           break;
13827         case dqb_mode:
13828         case db_mode:
13829           shift = 0;
13830           break;
13831         case dq_mode:
13832           if (address_mode != mode_64bit)
13833             {
13834               shift = 2;
13835               break;
13836             }
13837             /* fall through */
13838         case vex_scalar_w_dq_mode:
13839         case vex_vsib_d_w_dq_mode:
13840         case vex_vsib_d_w_d_mode:
13841         case vex_vsib_q_w_dq_mode:
13842         case vex_vsib_q_w_d_mode:
13843         case evex_x_gscat_mode:
13844           shift = vex.w ? 3 : 2;
13845           break;
13846         case x_mode:
13847         case evex_half_bcst_xmmq_mode:
13848         case xmmq_mode:
13849           if (vex.b)
13850             {
13851               shift = vex.w ? 3 : 2;
13852               break;
13853             }
13854           /* Fall through.  */
13855         case xmmqd_mode:
13856         case xmmdw_mode:
13857         case ymmq_mode:
13858         case evex_x_nobcst_mode:
13859         case x_swap_mode:
13860           switch (vex.length)
13861             {
13862             case 128:
13863               shift = 4;
13864               break;
13865             case 256:
13866               shift = 5;
13867               break;
13868             case 512:
13869               shift = 6;
13870               break;
13871             default:
13872               abort ();
13873             }
13874           break;
13875         case ymm_mode:
13876           shift = 5;
13877           break;
13878         case xmm_mode:
13879           shift = 4;
13880           break;
13881         case xmm_mq_mode:
13882         case q_mode:
13883         case q_swap_mode:
13884         case q_scalar_swap_mode:
13885           shift = 3;
13886           break;
13887         case dqd_mode:
13888         case xmm_md_mode:
13889         case d_mode:
13890         case d_swap_mode:
13891         case d_scalar_swap_mode:
13892           shift = 2;
13893           break;
13894         case w_scalar_mode:
13895         case xmm_mw_mode:
13896           shift = 1;
13897           break;
13898         case b_scalar_mode:
13899         case xmm_mb_mode:
13900           shift = 0;
13901           break;
13902         default:
13903           abort ();
13904         }
13905       /* Make necessary corrections to shift for modes that need it.
13906          For these modes we currently have shift 4, 5 or 6 depending on
13907          vex.length (it corresponds to xmmword, ymmword or zmmword
13908          operand).  We might want to make it 3, 4 or 5 (e.g. for
13909          xmmq_mode).  In case of broadcast enabled the corrections
13910          aren't needed, as element size is always 32 or 64 bits.  */
13911       if (!vex.b
13912           && (bytemode == xmmq_mode
13913               || bytemode == evex_half_bcst_xmmq_mode))
13914         shift -= 1;
13915       else if (bytemode == xmmqd_mode)
13916         shift -= 2;
13917       else if (bytemode == xmmdw_mode)
13918         shift -= 3;
13919       else if (bytemode == ymmq_mode && vex.length == 128)
13920         shift -= 1;
13921     }
13922   else
13923     shift = 0;
13924
13925   USED_REX (REX_B);
13926   if (intel_syntax)
13927     intel_operand_size (bytemode, sizeflag);
13928   append_seg ();
13929
13930   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
13931     {
13932       /* 32/64 bit address mode */
13933       int havedisp;
13934       int havesib;
13935       int havebase;
13936       int haveindex;
13937       int needindex;
13938       int needaddr32;
13939       int base, rbase;
13940       int vindex = 0;
13941       int scale = 0;
13942       int addr32flag = !((sizeflag & AFLAG)
13943                          || bytemode == v_bnd_mode
13944                          || bytemode == v_bndmk_mode
13945                          || bytemode == bnd_mode
13946                          || bytemode == bnd_swap_mode);
13947       const char **indexes64 = names64;
13948       const char **indexes32 = names32;
13949
13950       havesib = 0;
13951       havebase = 1;
13952       haveindex = 0;
13953       base = modrm.rm;
13954
13955       if (base == 4)
13956         {
13957           havesib = 1;
13958           vindex = sib.index;
13959           USED_REX (REX_X);
13960           if (rex & REX_X)
13961             vindex += 8;
13962           switch (bytemode)
13963             {
13964             case vex_vsib_d_w_dq_mode:
13965             case vex_vsib_d_w_d_mode:
13966             case vex_vsib_q_w_dq_mode:
13967             case vex_vsib_q_w_d_mode:
13968               if (!need_vex)
13969                 abort ();
13970               if (vex.evex)
13971                 {
13972                   if (!vex.v)
13973                     vindex += 16;
13974                 }
13975
13976               haveindex = 1;
13977               switch (vex.length)
13978                 {
13979                 case 128:
13980                   indexes64 = indexes32 = names_xmm;
13981                   break;
13982                 case 256:
13983                   if (!vex.w
13984                       || bytemode == vex_vsib_q_w_dq_mode
13985                       || bytemode == vex_vsib_q_w_d_mode)
13986                     indexes64 = indexes32 = names_ymm;
13987                   else
13988                     indexes64 = indexes32 = names_xmm;
13989                   break;
13990                 case 512:
13991                   if (!vex.w
13992                       || bytemode == vex_vsib_q_w_dq_mode
13993                       || bytemode == vex_vsib_q_w_d_mode)
13994                     indexes64 = indexes32 = names_zmm;
13995                   else
13996                     indexes64 = indexes32 = names_ymm;
13997                   break;
13998                 default:
13999                   abort ();
14000                 }
14001               break;
14002             default:
14003               haveindex = vindex != 4;
14004               break;
14005             }
14006           scale = sib.scale;
14007           base = sib.base;
14008           codep++;
14009         }
14010       rbase = base + add;
14011
14012       switch (modrm.mod)
14013         {
14014         case 0:
14015           if (base == 5)
14016             {
14017               havebase = 0;
14018               if (address_mode == mode_64bit && !havesib)
14019                 riprel = 1;
14020               disp = get32s ();
14021               if (riprel && bytemode == v_bndmk_mode)
14022                 {
14023                   oappend ("(bad)");
14024                   return;
14025                 }
14026             }
14027           break;
14028         case 1:
14029           FETCH_DATA (the_info, codep + 1);
14030           disp = *codep++;
14031           if ((disp & 0x80) != 0)
14032             disp -= 0x100;
14033           if (vex.evex && shift > 0)
14034             disp <<= shift;
14035           break;
14036         case 2:
14037           disp = get32s ();
14038           break;
14039         }
14040
14041       needindex = 0;
14042       needaddr32 = 0;
14043       if (havesib
14044           && !havebase
14045           && !haveindex
14046           && address_mode != mode_16bit)
14047         {
14048           if (address_mode == mode_64bit)
14049             {
14050               /* Display eiz instead of addr32.  */
14051               needindex = addr32flag;
14052               needaddr32 = 1;
14053             }
14054           else
14055             {
14056               /* In 32-bit mode, we need index register to tell [offset]
14057                  from [eiz*1 + offset].  */
14058               needindex = 1;
14059             }
14060         }
14061
14062       havedisp = (havebase
14063                   || needindex
14064                   || (havesib && (haveindex || scale != 0)));
14065
14066       if (!intel_syntax)
14067         if (modrm.mod != 0 || base == 5)
14068           {
14069             if (havedisp || riprel)
14070               print_displacement (scratchbuf, disp);
14071             else
14072               print_operand_value (scratchbuf, 1, disp);
14073             oappend (scratchbuf);
14074             if (riprel)
14075               {
14076                 set_op (disp, 1);
14077                 oappend (!addr32flag ? "(%rip)" : "(%eip)");
14078               }
14079           }
14080
14081       if ((havebase || haveindex || needindex || needaddr32 || riprel)
14082           && (address_mode != mode_64bit
14083               || ((bytemode != v_bnd_mode)
14084                   && (bytemode != v_bndmk_mode)
14085                   && (bytemode != bnd_mode)
14086                   && (bytemode != bnd_swap_mode))))
14087         used_prefixes |= PREFIX_ADDR;
14088
14089       if (havedisp || (intel_syntax && riprel))
14090         {
14091           *obufp++ = open_char;
14092           if (intel_syntax && riprel)
14093             {
14094               set_op (disp, 1);
14095               oappend (!addr32flag ? "rip" : "eip");
14096             }
14097           *obufp = '\0';
14098           if (havebase)
14099             oappend (address_mode == mode_64bit && !addr32flag
14100                      ? names64[rbase] : names32[rbase]);
14101           if (havesib)
14102             {
14103               /* ESP/RSP won't allow index.  If base isn't ESP/RSP,
14104                  print index to tell base + index from base.  */
14105               if (scale != 0
14106                   || needindex
14107                   || haveindex
14108                   || (havebase && base != ESP_REG_NUM))
14109                 {
14110                   if (!intel_syntax || havebase)
14111                     {
14112                       *obufp++ = separator_char;
14113                       *obufp = '\0';
14114                     }
14115                   if (haveindex)
14116                     oappend (address_mode == mode_64bit && !addr32flag
14117                              ? indexes64[vindex] : indexes32[vindex]);
14118                   else
14119                     oappend (address_mode == mode_64bit && !addr32flag
14120                              ? index64 : index32);
14121
14122                   *obufp++ = scale_char;
14123                   *obufp = '\0';
14124                   sprintf (scratchbuf, "%d", 1 << scale);
14125                   oappend (scratchbuf);
14126                 }
14127             }
14128           if (intel_syntax
14129               && (disp || modrm.mod != 0 || base == 5))
14130             {
14131               if (!havedisp || (bfd_signed_vma) disp >= 0)
14132                 {
14133                   *obufp++ = '+';
14134                   *obufp = '\0';
14135                 }
14136               else if (modrm.mod != 1 && disp != -disp)
14137                 {
14138                   *obufp++ = '-';
14139                   *obufp = '\0';
14140                   disp = - (bfd_signed_vma) disp;
14141                 }
14142
14143               if (havedisp)
14144                 print_displacement (scratchbuf, disp);
14145               else
14146                 print_operand_value (scratchbuf, 1, disp);
14147               oappend (scratchbuf);
14148             }
14149
14150           *obufp++ = close_char;
14151           *obufp = '\0';
14152         }
14153       else if (intel_syntax)
14154         {
14155           if (modrm.mod != 0 || base == 5)
14156             {
14157               if (!active_seg_prefix)
14158                 {
14159                   oappend (names_seg[ds_reg - es_reg]);
14160                   oappend (":");
14161                 }
14162               print_operand_value (scratchbuf, 1, disp);
14163               oappend (scratchbuf);
14164             }
14165         }
14166     }
14167   else if (bytemode == v_bnd_mode
14168            || bytemode == v_bndmk_mode
14169            || bytemode == bnd_mode
14170            || bytemode == bnd_swap_mode)
14171     {
14172       oappend ("(bad)");
14173       return;
14174     }
14175   else
14176     {
14177       /* 16 bit address mode */
14178       used_prefixes |= prefixes & PREFIX_ADDR;
14179       switch (modrm.mod)
14180         {
14181         case 0:
14182           if (modrm.rm == 6)
14183             {
14184               disp = get16 ();
14185               if ((disp & 0x8000) != 0)
14186                 disp -= 0x10000;
14187             }
14188           break;
14189         case 1:
14190           FETCH_DATA (the_info, codep + 1);
14191           disp = *codep++;
14192           if ((disp & 0x80) != 0)
14193             disp -= 0x100;
14194           if (vex.evex && shift > 0)
14195             disp <<= shift;
14196           break;
14197         case 2:
14198           disp = get16 ();
14199           if ((disp & 0x8000) != 0)
14200             disp -= 0x10000;
14201           break;
14202         }
14203
14204       if (!intel_syntax)
14205         if (modrm.mod != 0 || modrm.rm == 6)
14206           {
14207             print_displacement (scratchbuf, disp);
14208             oappend (scratchbuf);
14209           }
14210
14211       if (modrm.mod != 0 || modrm.rm != 6)
14212         {
14213           *obufp++ = open_char;
14214           *obufp = '\0';
14215           oappend (index16[modrm.rm]);
14216           if (intel_syntax
14217               && (disp || modrm.mod != 0 || modrm.rm == 6))
14218             {
14219               if ((bfd_signed_vma) disp >= 0)
14220                 {
14221                   *obufp++ = '+';
14222                   *obufp = '\0';
14223                 }
14224               else if (modrm.mod != 1)
14225                 {
14226                   *obufp++ = '-';
14227                   *obufp = '\0';
14228                   disp = - (bfd_signed_vma) disp;
14229                 }
14230
14231               print_displacement (scratchbuf, disp);
14232               oappend (scratchbuf);
14233             }
14234
14235           *obufp++ = close_char;
14236           *obufp = '\0';
14237         }
14238       else if (intel_syntax)
14239         {
14240           if (!active_seg_prefix)
14241             {
14242               oappend (names_seg[ds_reg - es_reg]);
14243               oappend (":");
14244             }
14245           print_operand_value (scratchbuf, 1, disp & 0xffff);
14246           oappend (scratchbuf);
14247         }
14248     }
14249   if (vex.evex && vex.b
14250       && (bytemode == x_mode
14251           || bytemode == xmmq_mode
14252           || bytemode == evex_half_bcst_xmmq_mode))
14253     {
14254       if (vex.w
14255           || bytemode == xmmq_mode
14256           || bytemode == evex_half_bcst_xmmq_mode)
14257         {
14258           switch (vex.length)
14259             {
14260             case 128:
14261               oappend ("{1to2}");
14262               break;
14263             case 256:
14264               oappend ("{1to4}");
14265               break;
14266             case 512:
14267               oappend ("{1to8}");
14268               break;
14269             default:
14270               abort ();
14271             }
14272         }
14273       else
14274         {
14275           switch (vex.length)
14276             {
14277             case 128:
14278               oappend ("{1to4}");
14279               break;
14280             case 256:
14281               oappend ("{1to8}");
14282               break;
14283             case 512:
14284               oappend ("{1to16}");
14285               break;
14286             default:
14287               abort ();
14288             }
14289         }
14290     }
14291 }
14292
14293 static void
14294 OP_E (int bytemode, int sizeflag)
14295 {
14296   /* Skip mod/rm byte.  */
14297   MODRM_CHECK;
14298   codep++;
14299
14300   if (modrm.mod == 3)
14301     OP_E_register (bytemode, sizeflag);
14302   else
14303     OP_E_memory (bytemode, sizeflag);
14304 }
14305
14306 static void
14307 OP_G (int bytemode, int sizeflag)
14308 {
14309   int add = 0;
14310   const char **names;
14311   USED_REX (REX_R);
14312   if (rex & REX_R)
14313     add += 8;
14314   switch (bytemode)
14315     {
14316     case b_mode:
14317       USED_REX (0);
14318       if (rex)
14319         oappend (names8rex[modrm.reg + add]);
14320       else
14321         oappend (names8[modrm.reg + add]);
14322       break;
14323     case w_mode:
14324       oappend (names16[modrm.reg + add]);
14325       break;
14326     case d_mode:
14327     case db_mode:
14328     case dw_mode:
14329       oappend (names32[modrm.reg + add]);
14330       break;
14331     case q_mode:
14332       oappend (names64[modrm.reg + add]);
14333       break;
14334     case bnd_mode:
14335       if (modrm.reg > 0x3)
14336         {
14337           oappend ("(bad)");
14338           return;
14339         }
14340       oappend (names_bnd[modrm.reg]);
14341       break;
14342     case v_mode:
14343     case dq_mode:
14344     case dqb_mode:
14345     case dqd_mode:
14346     case dqw_mode:
14347     case movsxd_mode:
14348       USED_REX (REX_W);
14349       if (rex & REX_W)
14350         oappend (names64[modrm.reg + add]);
14351       else
14352         {
14353           if ((sizeflag & DFLAG)
14354               || (bytemode != v_mode && bytemode != movsxd_mode))
14355             oappend (names32[modrm.reg + add]);
14356           else
14357             oappend (names16[modrm.reg + add]);
14358           used_prefixes |= (prefixes & PREFIX_DATA);
14359         }
14360       break;
14361     case va_mode:
14362       names = (address_mode == mode_64bit
14363                ? names64 : names32);
14364       if (!(prefixes & PREFIX_ADDR))
14365         {
14366           if (address_mode == mode_16bit)
14367             names = names16;
14368         }
14369       else
14370         {
14371           /* Remove "addr16/addr32".  */
14372           all_prefixes[last_addr_prefix] = 0;
14373           names = (address_mode != mode_32bit
14374                        ? names32 : names16);
14375           used_prefixes |= PREFIX_ADDR;
14376         }
14377       oappend (names[modrm.reg + add]);
14378       break;
14379     case m_mode:
14380       if (address_mode == mode_64bit)
14381         oappend (names64[modrm.reg + add]);
14382       else
14383         oappend (names32[modrm.reg + add]);
14384       break;
14385     case mask_bd_mode:
14386     case mask_mode:
14387       if ((modrm.reg + add) > 0x7)
14388         {
14389           oappend ("(bad)");
14390           return;
14391         }
14392       oappend (names_mask[modrm.reg + add]);
14393       break;
14394     default:
14395       oappend (INTERNAL_DISASSEMBLER_ERROR);
14396       break;
14397     }
14398 }
14399
14400 static bfd_vma
14401 get64 (void)
14402 {
14403   bfd_vma x;
14404 #ifdef BFD64
14405   unsigned int a;
14406   unsigned int b;
14407
14408   FETCH_DATA (the_info, codep + 8);
14409   a = *codep++ & 0xff;
14410   a |= (*codep++ & 0xff) << 8;
14411   a |= (*codep++ & 0xff) << 16;
14412   a |= (*codep++ & 0xffu) << 24;
14413   b = *codep++ & 0xff;
14414   b |= (*codep++ & 0xff) << 8;
14415   b |= (*codep++ & 0xff) << 16;
14416   b |= (*codep++ & 0xffu) << 24;
14417   x = a + ((bfd_vma) b << 32);
14418 #else
14419   abort ();
14420   x = 0;
14421 #endif
14422   return x;
14423 }
14424
14425 static bfd_signed_vma
14426 get32 (void)
14427 {
14428   bfd_signed_vma x = 0;
14429
14430   FETCH_DATA (the_info, codep + 4);
14431   x = *codep++ & (bfd_signed_vma) 0xff;
14432   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
14433   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
14434   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
14435   return x;
14436 }
14437
14438 static bfd_signed_vma
14439 get32s (void)
14440 {
14441   bfd_signed_vma x = 0;
14442
14443   FETCH_DATA (the_info, codep + 4);
14444   x = *codep++ & (bfd_signed_vma) 0xff;
14445   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
14446   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
14447   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
14448
14449   x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
14450
14451   return x;
14452 }
14453
14454 static int
14455 get16 (void)
14456 {
14457   int x = 0;
14458
14459   FETCH_DATA (the_info, codep + 2);
14460   x = *codep++ & 0xff;
14461   x |= (*codep++ & 0xff) << 8;
14462   return x;
14463 }
14464
14465 static void
14466 set_op (bfd_vma op, int riprel)
14467 {
14468   op_index[op_ad] = op_ad;
14469   if (address_mode == mode_64bit)
14470     {
14471       op_address[op_ad] = op;
14472       op_riprel[op_ad] = riprel;
14473     }
14474   else
14475     {
14476       /* Mask to get a 32-bit address.  */
14477       op_address[op_ad] = op & 0xffffffff;
14478       op_riprel[op_ad] = riprel & 0xffffffff;
14479     }
14480 }
14481
14482 static void
14483 OP_REG (int code, int sizeflag)
14484 {
14485   const char *s;
14486   int add;
14487
14488   switch (code)
14489     {
14490     case es_reg: case ss_reg: case cs_reg:
14491     case ds_reg: case fs_reg: case gs_reg:
14492       oappend (names_seg[code - es_reg]);
14493       return;
14494     }
14495
14496   USED_REX (REX_B);
14497   if (rex & REX_B)
14498     add = 8;
14499   else
14500     add = 0;
14501
14502   switch (code)
14503     {
14504     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
14505     case sp_reg: case bp_reg: case si_reg: case di_reg:
14506       s = names16[code - ax_reg + add];
14507       break;
14508     case al_reg: case ah_reg: case cl_reg: case ch_reg:
14509     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
14510       USED_REX (0);
14511       if (rex)
14512         s = names8rex[code - al_reg + add];
14513       else
14514         s = names8[code - al_reg];
14515       break;
14516     case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
14517     case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
14518       if (address_mode == mode_64bit
14519           && ((sizeflag & DFLAG) || (rex & REX_W)))
14520         {
14521           s = names64[code - rAX_reg + add];
14522           break;
14523         }
14524       code += eAX_reg - rAX_reg;
14525       /* Fall through.  */
14526     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
14527     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
14528       USED_REX (REX_W);
14529       if (rex & REX_W)
14530         s = names64[code - eAX_reg + add];
14531       else
14532         {
14533           if (sizeflag & DFLAG)
14534             s = names32[code - eAX_reg + add];
14535           else
14536             s = names16[code - eAX_reg + add];
14537           used_prefixes |= (prefixes & PREFIX_DATA);
14538         }
14539       break;
14540     default:
14541       s = INTERNAL_DISASSEMBLER_ERROR;
14542       break;
14543     }
14544   oappend (s);
14545 }
14546
14547 static void
14548 OP_IMREG (int code, int sizeflag)
14549 {
14550   const char *s;
14551
14552   switch (code)
14553     {
14554     case indir_dx_reg:
14555       if (intel_syntax)
14556         s = "dx";
14557       else
14558         s = "(%dx)";
14559       break;
14560     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
14561     case sp_reg: case bp_reg: case si_reg: case di_reg:
14562       s = names16[code - ax_reg];
14563       break;
14564     case es_reg: case ss_reg: case cs_reg:
14565     case ds_reg: case fs_reg: case gs_reg:
14566       s = names_seg[code - es_reg];
14567       break;
14568     case al_reg: case ah_reg: case cl_reg: case ch_reg:
14569     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
14570       USED_REX (0);
14571       if (rex)
14572         s = names8rex[code - al_reg];
14573       else
14574         s = names8[code - al_reg];
14575       break;
14576     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
14577     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
14578       USED_REX (REX_W);
14579       if (rex & REX_W)
14580         s = names64[code - eAX_reg];
14581       else
14582         {
14583           if (sizeflag & DFLAG)
14584             s = names32[code - eAX_reg];
14585           else
14586             s = names16[code - eAX_reg];
14587           used_prefixes |= (prefixes & PREFIX_DATA);
14588         }
14589       break;
14590     case z_mode_ax_reg:
14591       if ((rex & REX_W) || (sizeflag & DFLAG))
14592         s = *names32;
14593       else
14594         s = *names16;
14595       if (!(rex & REX_W))
14596         used_prefixes |= (prefixes & PREFIX_DATA);
14597       break;
14598     default:
14599       s = INTERNAL_DISASSEMBLER_ERROR;
14600       break;
14601     }
14602   oappend (s);
14603 }
14604
14605 static void
14606 OP_I (int bytemode, int sizeflag)
14607 {
14608   bfd_signed_vma op;
14609   bfd_signed_vma mask = -1;
14610
14611   switch (bytemode)
14612     {
14613     case b_mode:
14614       FETCH_DATA (the_info, codep + 1);
14615       op = *codep++;
14616       mask = 0xff;
14617       break;
14618     case v_mode:
14619       USED_REX (REX_W);
14620       if (rex & REX_W)
14621         op = get32s ();
14622       else
14623         {
14624           if (sizeflag & DFLAG)
14625             {
14626               op = get32 ();
14627               mask = 0xffffffff;
14628             }
14629           else
14630             {
14631               op = get16 ();
14632               mask = 0xfffff;
14633             }
14634           used_prefixes |= (prefixes & PREFIX_DATA);
14635         }
14636       break;
14637     case d_mode:
14638       mask = 0xffffffff;
14639       op = get32 ();
14640       break;
14641     case w_mode:
14642       mask = 0xfffff;
14643       op = get16 ();
14644       break;
14645     case const_1_mode:
14646       if (intel_syntax)
14647         oappend ("1");
14648       return;
14649     default:
14650       oappend (INTERNAL_DISASSEMBLER_ERROR);
14651       return;
14652     }
14653
14654   op &= mask;
14655   scratchbuf[0] = '$';
14656   print_operand_value (scratchbuf + 1, 1, op);
14657   oappend_maybe_intel (scratchbuf);
14658   scratchbuf[0] = '\0';
14659 }
14660
14661 static void
14662 OP_I64 (int bytemode, int sizeflag)
14663 {
14664   if (bytemode != v_mode || address_mode != mode_64bit || !(rex & REX_W))
14665     {
14666       OP_I (bytemode, sizeflag);
14667       return;
14668     }
14669
14670   USED_REX (REX_W);
14671
14672   scratchbuf[0] = '$';
14673   print_operand_value (scratchbuf + 1, 1, get64 ());
14674   oappend_maybe_intel (scratchbuf);
14675   scratchbuf[0] = '\0';
14676 }
14677
14678 static void
14679 OP_sI (int bytemode, int sizeflag)
14680 {
14681   bfd_signed_vma op;
14682
14683   switch (bytemode)
14684     {
14685     case b_mode:
14686     case b_T_mode:
14687       FETCH_DATA (the_info, codep + 1);
14688       op = *codep++;
14689       if ((op & 0x80) != 0)
14690         op -= 0x100;
14691       if (bytemode == b_T_mode)
14692         {
14693           if (address_mode != mode_64bit
14694               || !((sizeflag & DFLAG) || (rex & REX_W)))
14695             {
14696               /* The operand-size prefix is overridden by a REX prefix.  */
14697               if ((sizeflag & DFLAG) || (rex & REX_W))
14698                 op &= 0xffffffff;
14699               else
14700                 op &= 0xffff;
14701           }
14702         }
14703       else
14704         {
14705           if (!(rex & REX_W))
14706             {
14707               if (sizeflag & DFLAG)
14708                 op &= 0xffffffff;
14709               else
14710                 op &= 0xffff;
14711             }
14712         }
14713       break;
14714     case v_mode:
14715       /* The operand-size prefix is overridden by a REX prefix.  */
14716       if ((sizeflag & DFLAG) || (rex & REX_W))
14717         op = get32s ();
14718       else
14719         op = get16 ();
14720       break;
14721     default:
14722       oappend (INTERNAL_DISASSEMBLER_ERROR);
14723       return;
14724     }
14725
14726   scratchbuf[0] = '$';
14727   print_operand_value (scratchbuf + 1, 1, op);
14728   oappend_maybe_intel (scratchbuf);
14729 }
14730
14731 static void
14732 OP_J (int bytemode, int sizeflag)
14733 {
14734   bfd_vma disp;
14735   bfd_vma mask = -1;
14736   bfd_vma segment = 0;
14737
14738   switch (bytemode)
14739     {
14740     case b_mode:
14741       FETCH_DATA (the_info, codep + 1);
14742       disp = *codep++;
14743       if ((disp & 0x80) != 0)
14744         disp -= 0x100;
14745       break;
14746     case v_mode:
14747       if (isa64 != intel64)
14748     case dqw_mode:
14749         USED_REX (REX_W);
14750       if ((sizeflag & DFLAG)
14751           || (address_mode == mode_64bit
14752               && ((isa64 == intel64 && bytemode != dqw_mode)
14753                   || (rex & REX_W))))
14754         disp = get32s ();
14755       else
14756         {
14757           disp = get16 ();
14758           if ((disp & 0x8000) != 0)
14759             disp -= 0x10000;
14760           /* In 16bit mode, address is wrapped around at 64k within
14761              the same segment.  Otherwise, a data16 prefix on a jump
14762              instruction means that the pc is masked to 16 bits after
14763              the displacement is added!  */
14764           mask = 0xffff;
14765           if ((prefixes & PREFIX_DATA) == 0)
14766             segment = ((start_pc + (codep - start_codep))
14767                        & ~((bfd_vma) 0xffff));
14768         }
14769       if (address_mode != mode_64bit
14770           || (isa64 != intel64 && !(rex & REX_W)))
14771         used_prefixes |= (prefixes & PREFIX_DATA);
14772       break;
14773     default:
14774       oappend (INTERNAL_DISASSEMBLER_ERROR);
14775       return;
14776     }
14777   disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment;
14778   set_op (disp, 0);
14779   print_operand_value (scratchbuf, 1, disp);
14780   oappend (scratchbuf);
14781 }
14782
14783 static void
14784 OP_SEG (int bytemode, int sizeflag)
14785 {
14786   if (bytemode == w_mode)
14787     oappend (names_seg[modrm.reg]);
14788   else
14789     OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
14790 }
14791
14792 static void
14793 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
14794 {
14795   int seg, offset;
14796
14797   if (sizeflag & DFLAG)
14798     {
14799       offset = get32 ();
14800       seg = get16 ();
14801     }
14802   else
14803     {
14804       offset = get16 ();
14805       seg = get16 ();
14806     }
14807   used_prefixes |= (prefixes & PREFIX_DATA);
14808   if (intel_syntax)
14809     sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
14810   else
14811     sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
14812   oappend (scratchbuf);
14813 }
14814
14815 static void
14816 OP_OFF (int bytemode, int sizeflag)
14817 {
14818   bfd_vma off;
14819
14820   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
14821     intel_operand_size (bytemode, sizeflag);
14822   append_seg ();
14823
14824   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
14825     off = get32 ();
14826   else
14827     off = get16 ();
14828
14829   if (intel_syntax)
14830     {
14831       if (!active_seg_prefix)
14832         {
14833           oappend (names_seg[ds_reg - es_reg]);
14834           oappend (":");
14835         }
14836     }
14837   print_operand_value (scratchbuf, 1, off);
14838   oappend (scratchbuf);
14839 }
14840
14841 static void
14842 OP_OFF64 (int bytemode, int sizeflag)
14843 {
14844   bfd_vma off;
14845
14846   if (address_mode != mode_64bit
14847       || (prefixes & PREFIX_ADDR))
14848     {
14849       OP_OFF (bytemode, sizeflag);
14850       return;
14851     }
14852
14853   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
14854     intel_operand_size (bytemode, sizeflag);
14855   append_seg ();
14856
14857   off = get64 ();
14858
14859   if (intel_syntax)
14860     {
14861       if (!active_seg_prefix)
14862         {
14863           oappend (names_seg[ds_reg - es_reg]);
14864           oappend (":");
14865         }
14866     }
14867   print_operand_value (scratchbuf, 1, off);
14868   oappend (scratchbuf);
14869 }
14870
14871 static void
14872 ptr_reg (int code, int sizeflag)
14873 {
14874   const char *s;
14875
14876   *obufp++ = open_char;
14877   used_prefixes |= (prefixes & PREFIX_ADDR);
14878   if (address_mode == mode_64bit)
14879     {
14880       if (!(sizeflag & AFLAG))
14881         s = names32[code - eAX_reg];
14882       else
14883         s = names64[code - eAX_reg];
14884     }
14885   else if (sizeflag & AFLAG)
14886     s = names32[code - eAX_reg];
14887   else
14888     s = names16[code - eAX_reg];
14889   oappend (s);
14890   *obufp++ = close_char;
14891   *obufp = 0;
14892 }
14893
14894 static void
14895 OP_ESreg (int code, int sizeflag)
14896 {
14897   if (intel_syntax)
14898     {
14899       switch (codep[-1])
14900         {
14901         case 0x6d:      /* insw/insl */
14902           intel_operand_size (z_mode, sizeflag);
14903           break;
14904         case 0xa5:      /* movsw/movsl/movsq */
14905         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
14906         case 0xab:      /* stosw/stosl */
14907         case 0xaf:      /* scasw/scasl */
14908           intel_operand_size (v_mode, sizeflag);
14909           break;
14910         default:
14911           intel_operand_size (b_mode, sizeflag);
14912         }
14913     }
14914   oappend_maybe_intel ("%es:");
14915   ptr_reg (code, sizeflag);
14916 }
14917
14918 static void
14919 OP_DSreg (int code, int sizeflag)
14920 {
14921   if (intel_syntax)
14922     {
14923       switch (codep[-1])
14924         {
14925         case 0x6f:      /* outsw/outsl */
14926           intel_operand_size (z_mode, sizeflag);
14927           break;
14928         case 0xa5:      /* movsw/movsl/movsq */
14929         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
14930         case 0xad:      /* lodsw/lodsl/lodsq */
14931           intel_operand_size (v_mode, sizeflag);
14932           break;
14933         default:
14934           intel_operand_size (b_mode, sizeflag);
14935         }
14936     }
14937   /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
14938      default segment register DS is printed.  */
14939   if (!active_seg_prefix)
14940     active_seg_prefix = PREFIX_DS;
14941   append_seg ();
14942   ptr_reg (code, sizeflag);
14943 }
14944
14945 static void
14946 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14947 {
14948   int add;
14949   if (rex & REX_R)
14950     {
14951       USED_REX (REX_R);
14952       add = 8;
14953     }
14954   else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
14955     {
14956       all_prefixes[last_lock_prefix] = 0;
14957       used_prefixes |= PREFIX_LOCK;
14958       add = 8;
14959     }
14960   else
14961     add = 0;
14962   sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
14963   oappend_maybe_intel (scratchbuf);
14964 }
14965
14966 static void
14967 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14968 {
14969   int add;
14970   USED_REX (REX_R);
14971   if (rex & REX_R)
14972     add = 8;
14973   else
14974     add = 0;
14975   if (intel_syntax)
14976     sprintf (scratchbuf, "db%d", modrm.reg + add);
14977   else
14978     sprintf (scratchbuf, "%%db%d", modrm.reg + add);
14979   oappend (scratchbuf);
14980 }
14981
14982 static void
14983 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14984 {
14985   sprintf (scratchbuf, "%%tr%d", modrm.reg);
14986   oappend_maybe_intel (scratchbuf);
14987 }
14988
14989 static void
14990 OP_R (int bytemode, int sizeflag)
14991 {
14992   /* Skip mod/rm byte.  */
14993   MODRM_CHECK;
14994   codep++;
14995   OP_E_register (bytemode, sizeflag);
14996 }
14997
14998 static void
14999 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15000 {
15001   int reg = modrm.reg;
15002   const char **names;
15003
15004   used_prefixes |= (prefixes & PREFIX_DATA);
15005   if (prefixes & PREFIX_DATA)
15006     {
15007       names = names_xmm;
15008       USED_REX (REX_R);
15009       if (rex & REX_R)
15010         reg += 8;
15011     }
15012   else
15013     names = names_mm;
15014   oappend (names[reg]);
15015 }
15016
15017 static void
15018 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
15019 {
15020   int reg = modrm.reg;
15021   const char **names;
15022
15023   USED_REX (REX_R);
15024   if (rex & REX_R)
15025     reg += 8;
15026   if (vex.evex)
15027     {
15028       if (!vex.r)
15029         reg += 16;
15030     }
15031
15032   if (need_vex
15033       && bytemode != xmm_mode
15034       && bytemode != xmmq_mode
15035       && bytemode != evex_half_bcst_xmmq_mode
15036       && bytemode != ymm_mode
15037       && bytemode != scalar_mode)
15038     {
15039       switch (vex.length)
15040         {
15041         case 128:
15042           names = names_xmm;
15043           break;
15044         case 256:
15045           if (vex.w
15046               || (bytemode != vex_vsib_q_w_dq_mode
15047                   && bytemode != vex_vsib_q_w_d_mode))
15048             names = names_ymm;
15049           else
15050             names = names_xmm;
15051           break;
15052         case 512:
15053           names = names_zmm;
15054           break;
15055         default:
15056           abort ();
15057         }
15058     }
15059   else if (bytemode == xmmq_mode
15060            || bytemode == evex_half_bcst_xmmq_mode)
15061     {
15062       switch (vex.length)
15063         {
15064         case 128:
15065         case 256:
15066           names = names_xmm;
15067           break;
15068         case 512:
15069           names = names_ymm;
15070           break;
15071         default:
15072           abort ();
15073         }
15074     }
15075   else if (bytemode == ymm_mode)
15076     names = names_ymm;
15077   else
15078     names = names_xmm;
15079   oappend (names[reg]);
15080 }
15081
15082 static void
15083 OP_EM (int bytemode, int sizeflag)
15084 {
15085   int reg;
15086   const char **names;
15087
15088   if (modrm.mod != 3)
15089     {
15090       if (intel_syntax
15091           && (bytemode == v_mode || bytemode == v_swap_mode))
15092         {
15093           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
15094           used_prefixes |= (prefixes & PREFIX_DATA);
15095         }
15096       OP_E (bytemode, sizeflag);
15097       return;
15098     }
15099
15100   if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
15101     swap_operand ();
15102
15103   /* Skip mod/rm byte.  */
15104   MODRM_CHECK;
15105   codep++;
15106   used_prefixes |= (prefixes & PREFIX_DATA);
15107   reg = modrm.rm;
15108   if (prefixes & PREFIX_DATA)
15109     {
15110       names = names_xmm;
15111       USED_REX (REX_B);
15112       if (rex & REX_B)
15113         reg += 8;
15114     }
15115   else
15116     names = names_mm;
15117   oappend (names[reg]);
15118 }
15119
15120 /* cvt* are the only instructions in sse2 which have
15121    both SSE and MMX operands and also have 0x66 prefix
15122    in their opcode. 0x66 was originally used to differentiate
15123    between SSE and MMX instruction(operands). So we have to handle the
15124    cvt* separately using OP_EMC and OP_MXC */
15125 static void
15126 OP_EMC (int bytemode, int sizeflag)
15127 {
15128   if (modrm.mod != 3)
15129     {
15130       if (intel_syntax && bytemode == v_mode)
15131         {
15132           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
15133           used_prefixes |= (prefixes & PREFIX_DATA);
15134         }
15135       OP_E (bytemode, sizeflag);
15136       return;
15137     }
15138
15139   /* Skip mod/rm byte.  */
15140   MODRM_CHECK;
15141   codep++;
15142   used_prefixes |= (prefixes & PREFIX_DATA);
15143   oappend (names_mm[modrm.rm]);
15144 }
15145
15146 static void
15147 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15148 {
15149   used_prefixes |= (prefixes & PREFIX_DATA);
15150   oappend (names_mm[modrm.reg]);
15151 }
15152
15153 static void
15154 OP_EX (int bytemode, int sizeflag)
15155 {
15156   int reg;
15157   const char **names;
15158
15159   /* Skip mod/rm byte.  */
15160   MODRM_CHECK;
15161   codep++;
15162
15163   if (modrm.mod != 3)
15164     {
15165       OP_E_memory (bytemode, sizeflag);
15166       return;
15167     }
15168
15169   reg = modrm.rm;
15170   USED_REX (REX_B);
15171   if (rex & REX_B)
15172     reg += 8;
15173   if (vex.evex)
15174     {
15175       USED_REX (REX_X);
15176       if ((rex & REX_X))
15177         reg += 16;
15178     }
15179
15180   if ((sizeflag & SUFFIX_ALWAYS)
15181       && (bytemode == x_swap_mode
15182           || bytemode == d_swap_mode
15183           || bytemode == d_scalar_swap_mode
15184           || bytemode == q_swap_mode
15185           || bytemode == q_scalar_swap_mode))
15186     swap_operand ();
15187
15188   if (need_vex
15189       && bytemode != xmm_mode
15190       && bytemode != xmmdw_mode
15191       && bytemode != xmmqd_mode
15192       && bytemode != xmm_mb_mode
15193       && bytemode != xmm_mw_mode
15194       && bytemode != xmm_md_mode
15195       && bytemode != xmm_mq_mode
15196       && bytemode != xmmq_mode
15197       && bytemode != evex_half_bcst_xmmq_mode
15198       && bytemode != ymm_mode
15199       && bytemode != d_scalar_swap_mode
15200       && bytemode != q_scalar_swap_mode
15201       && bytemode != vex_scalar_w_dq_mode)
15202     {
15203       switch (vex.length)
15204         {
15205         case 128:
15206           names = names_xmm;
15207           break;
15208         case 256:
15209           names = names_ymm;
15210           break;
15211         case 512:
15212           names = names_zmm;
15213           break;
15214         default:
15215           abort ();
15216         }
15217     }
15218   else if (bytemode == xmmq_mode
15219            || bytemode == evex_half_bcst_xmmq_mode)
15220     {
15221       switch (vex.length)
15222         {
15223         case 128:
15224         case 256:
15225           names = names_xmm;
15226           break;
15227         case 512:
15228           names = names_ymm;
15229           break;
15230         default:
15231           abort ();
15232         }
15233     }
15234   else if (bytemode == ymm_mode)
15235     names = names_ymm;
15236   else
15237     names = names_xmm;
15238   oappend (names[reg]);
15239 }
15240
15241 static void
15242 OP_MS (int bytemode, int sizeflag)
15243 {
15244   if (modrm.mod == 3)
15245     OP_EM (bytemode, sizeflag);
15246   else
15247     BadOp ();
15248 }
15249
15250 static void
15251 OP_XS (int bytemode, int sizeflag)
15252 {
15253   if (modrm.mod == 3)
15254     OP_EX (bytemode, sizeflag);
15255   else
15256     BadOp ();
15257 }
15258
15259 static void
15260 OP_M (int bytemode, int sizeflag)
15261 {
15262   if (modrm.mod == 3)
15263     /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
15264     BadOp ();
15265   else
15266     OP_E (bytemode, sizeflag);
15267 }
15268
15269 static void
15270 OP_0f07 (int bytemode, int sizeflag)
15271 {
15272   if (modrm.mod != 3 || modrm.rm != 0)
15273     BadOp ();
15274   else
15275     OP_E (bytemode, sizeflag);
15276 }
15277
15278 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
15279    32bit mode and "xchg %rax,%rax" in 64bit mode.  */
15280
15281 static void
15282 NOP_Fixup1 (int bytemode, int sizeflag)
15283 {
15284   if ((prefixes & PREFIX_DATA) != 0
15285       || (rex != 0
15286           && rex != 0x48
15287           && address_mode == mode_64bit))
15288     OP_REG (bytemode, sizeflag);
15289   else
15290     strcpy (obuf, "nop");
15291 }
15292
15293 static void
15294 NOP_Fixup2 (int bytemode, int sizeflag)
15295 {
15296   if ((prefixes & PREFIX_DATA) != 0
15297       || (rex != 0
15298           && rex != 0x48
15299           && address_mode == mode_64bit))
15300     OP_IMREG (bytemode, sizeflag);
15301 }
15302
15303 static const char *const Suffix3DNow[] = {
15304 /* 00 */        NULL,           NULL,           NULL,           NULL,
15305 /* 04 */        NULL,           NULL,           NULL,           NULL,
15306 /* 08 */        NULL,           NULL,           NULL,           NULL,
15307 /* 0C */        "pi2fw",        "pi2fd",        NULL,           NULL,
15308 /* 10 */        NULL,           NULL,           NULL,           NULL,
15309 /* 14 */        NULL,           NULL,           NULL,           NULL,
15310 /* 18 */        NULL,           NULL,           NULL,           NULL,
15311 /* 1C */        "pf2iw",        "pf2id",        NULL,           NULL,
15312 /* 20 */        NULL,           NULL,           NULL,           NULL,
15313 /* 24 */        NULL,           NULL,           NULL,           NULL,
15314 /* 28 */        NULL,           NULL,           NULL,           NULL,
15315 /* 2C */        NULL,           NULL,           NULL,           NULL,
15316 /* 30 */        NULL,           NULL,           NULL,           NULL,
15317 /* 34 */        NULL,           NULL,           NULL,           NULL,
15318 /* 38 */        NULL,           NULL,           NULL,           NULL,
15319 /* 3C */        NULL,           NULL,           NULL,           NULL,
15320 /* 40 */        NULL,           NULL,           NULL,           NULL,
15321 /* 44 */        NULL,           NULL,           NULL,           NULL,
15322 /* 48 */        NULL,           NULL,           NULL,           NULL,
15323 /* 4C */        NULL,           NULL,           NULL,           NULL,
15324 /* 50 */        NULL,           NULL,           NULL,           NULL,
15325 /* 54 */        NULL,           NULL,           NULL,           NULL,
15326 /* 58 */        NULL,           NULL,           NULL,           NULL,
15327 /* 5C */        NULL,           NULL,           NULL,           NULL,
15328 /* 60 */        NULL,           NULL,           NULL,           NULL,
15329 /* 64 */        NULL,           NULL,           NULL,           NULL,
15330 /* 68 */        NULL,           NULL,           NULL,           NULL,
15331 /* 6C */        NULL,           NULL,           NULL,           NULL,
15332 /* 70 */        NULL,           NULL,           NULL,           NULL,
15333 /* 74 */        NULL,           NULL,           NULL,           NULL,
15334 /* 78 */        NULL,           NULL,           NULL,           NULL,
15335 /* 7C */        NULL,           NULL,           NULL,           NULL,
15336 /* 80 */        NULL,           NULL,           NULL,           NULL,
15337 /* 84 */        NULL,           NULL,           NULL,           NULL,
15338 /* 88 */        NULL,           NULL,           "pfnacc",       NULL,
15339 /* 8C */        NULL,           NULL,           "pfpnacc",      NULL,
15340 /* 90 */        "pfcmpge",      NULL,           NULL,           NULL,
15341 /* 94 */        "pfmin",        NULL,           "pfrcp",        "pfrsqrt",
15342 /* 98 */        NULL,           NULL,           "pfsub",        NULL,
15343 /* 9C */        NULL,           NULL,           "pfadd",        NULL,
15344 /* A0 */        "pfcmpgt",      NULL,           NULL,           NULL,
15345 /* A4 */        "pfmax",        NULL,           "pfrcpit1",     "pfrsqit1",
15346 /* A8 */        NULL,           NULL,           "pfsubr",       NULL,
15347 /* AC */        NULL,           NULL,           "pfacc",        NULL,
15348 /* B0 */        "pfcmpeq",      NULL,           NULL,           NULL,
15349 /* B4 */        "pfmul",        NULL,           "pfrcpit2",     "pmulhrw",
15350 /* B8 */        NULL,           NULL,           NULL,           "pswapd",
15351 /* BC */        NULL,           NULL,           NULL,           "pavgusb",
15352 /* C0 */        NULL,           NULL,           NULL,           NULL,
15353 /* C4 */        NULL,           NULL,           NULL,           NULL,
15354 /* C8 */        NULL,           NULL,           NULL,           NULL,
15355 /* CC */        NULL,           NULL,           NULL,           NULL,
15356 /* D0 */        NULL,           NULL,           NULL,           NULL,
15357 /* D4 */        NULL,           NULL,           NULL,           NULL,
15358 /* D8 */        NULL,           NULL,           NULL,           NULL,
15359 /* DC */        NULL,           NULL,           NULL,           NULL,
15360 /* E0 */        NULL,           NULL,           NULL,           NULL,
15361 /* E4 */        NULL,           NULL,           NULL,           NULL,
15362 /* E8 */        NULL,           NULL,           NULL,           NULL,
15363 /* EC */        NULL,           NULL,           NULL,           NULL,
15364 /* F0 */        NULL,           NULL,           NULL,           NULL,
15365 /* F4 */        NULL,           NULL,           NULL,           NULL,
15366 /* F8 */        NULL,           NULL,           NULL,           NULL,
15367 /* FC */        NULL,           NULL,           NULL,           NULL,
15368 };
15369
15370 static void
15371 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15372 {
15373   const char *mnemonic;
15374
15375   FETCH_DATA (the_info, codep + 1);
15376   /* AMD 3DNow! instructions are specified by an opcode suffix in the
15377      place where an 8-bit immediate would normally go.  ie. the last
15378      byte of the instruction.  */
15379   obufp = mnemonicendp;
15380   mnemonic = Suffix3DNow[*codep++ & 0xff];
15381   if (mnemonic)
15382     oappend (mnemonic);
15383   else
15384     {
15385       /* Since a variable sized modrm/sib chunk is between the start
15386          of the opcode (0x0f0f) and the opcode suffix, we need to do
15387          all the modrm processing first, and don't know until now that
15388          we have a bad opcode.  This necessitates some cleaning up.  */
15389       op_out[0][0] = '\0';
15390       op_out[1][0] = '\0';
15391       BadOp ();
15392     }
15393   mnemonicendp = obufp;
15394 }
15395
15396 static struct op simd_cmp_op[] =
15397 {
15398   { STRING_COMMA_LEN ("eq") },
15399   { STRING_COMMA_LEN ("lt") },
15400   { STRING_COMMA_LEN ("le") },
15401   { STRING_COMMA_LEN ("unord") },
15402   { STRING_COMMA_LEN ("neq") },
15403   { STRING_COMMA_LEN ("nlt") },
15404   { STRING_COMMA_LEN ("nle") },
15405   { STRING_COMMA_LEN ("ord") }
15406 };
15407
15408 static void
15409 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15410 {
15411   unsigned int cmp_type;
15412
15413   FETCH_DATA (the_info, codep + 1);
15414   cmp_type = *codep++ & 0xff;
15415   if (cmp_type < ARRAY_SIZE (simd_cmp_op))
15416     {
15417       char suffix [3];
15418       char *p = mnemonicendp - 2;
15419       suffix[0] = p[0];
15420       suffix[1] = p[1];
15421       suffix[2] = '\0';
15422       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
15423       mnemonicendp += simd_cmp_op[cmp_type].len;
15424     }
15425   else
15426     {
15427       /* We have a reserved extension byte.  Output it directly.  */
15428       scratchbuf[0] = '$';
15429       print_operand_value (scratchbuf + 1, 1, cmp_type);
15430       oappend_maybe_intel (scratchbuf);
15431       scratchbuf[0] = '\0';
15432     }
15433 }
15434
15435 static void
15436 OP_Mwait (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
15437 {
15438   /* mwait %eax,%ecx / mwaitx %eax,%ecx,%ebx  */
15439   if (!intel_syntax)
15440     {
15441       strcpy (op_out[0], names32[0]);
15442       strcpy (op_out[1], names32[1]);
15443       if (bytemode == eBX_reg)
15444         strcpy (op_out[2], names32[3]);
15445       two_source_ops = 1;
15446     }
15447   /* Skip mod/rm byte.  */
15448   MODRM_CHECK;
15449   codep++;
15450 }
15451
15452 static void
15453 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
15454             int sizeflag ATTRIBUTE_UNUSED)
15455 {
15456   /* monitor %{e,r,}ax,%ecx,%edx"  */
15457   if (!intel_syntax)
15458     {
15459       const char **names = (address_mode == mode_64bit
15460                             ? names64 : names32);
15461
15462       if (prefixes & PREFIX_ADDR)
15463         {
15464           /* Remove "addr16/addr32".  */
15465           all_prefixes[last_addr_prefix] = 0;
15466           names = (address_mode != mode_32bit
15467                    ? names32 : names16);
15468           used_prefixes |= PREFIX_ADDR;
15469         }
15470       else if (address_mode == mode_16bit)
15471         names = names16;
15472       strcpy (op_out[0], names[0]);
15473       strcpy (op_out[1], names32[1]);
15474       strcpy (op_out[2], names32[2]);
15475       two_source_ops = 1;
15476     }
15477   /* Skip mod/rm byte.  */
15478   MODRM_CHECK;
15479   codep++;
15480 }
15481
15482 static void
15483 BadOp (void)
15484 {
15485   /* Throw away prefixes and 1st. opcode byte.  */
15486   codep = insn_codep + 1;
15487   oappend ("(bad)");
15488 }
15489
15490 static void
15491 REP_Fixup (int bytemode, int sizeflag)
15492 {
15493   /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
15494      lods and stos.  */
15495   if (prefixes & PREFIX_REPZ)
15496     all_prefixes[last_repz_prefix] = REP_PREFIX;
15497
15498   switch (bytemode)
15499     {
15500     case al_reg:
15501     case eAX_reg:
15502     case indir_dx_reg:
15503       OP_IMREG (bytemode, sizeflag);
15504       break;
15505     case eDI_reg:
15506       OP_ESreg (bytemode, sizeflag);
15507       break;
15508     case eSI_reg:
15509       OP_DSreg (bytemode, sizeflag);
15510       break;
15511     default:
15512       abort ();
15513       break;
15514     }
15515 }
15516
15517 static void
15518 SEP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15519 {
15520   if ( isa64 != amd64 )
15521     return;
15522
15523   obufp = obuf;
15524   BadOp ();
15525   mnemonicendp = obufp;
15526   ++codep;
15527 }
15528
15529 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
15530    "bnd".  */
15531
15532 static void
15533 BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15534 {
15535   if (prefixes & PREFIX_REPNZ)
15536     all_prefixes[last_repnz_prefix] = BND_PREFIX;
15537 }
15538
15539 /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
15540    "notrack".  */
15541
15542 static void
15543 NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED,
15544                int sizeflag ATTRIBUTE_UNUSED)
15545 {
15546   if (active_seg_prefix == PREFIX_DS
15547       && (address_mode != mode_64bit || last_data_prefix < 0))
15548     {
15549       /* NOTRACK prefix is only valid on indirect branch instructions.
15550          NB: DATA prefix is unsupported for Intel64.  */
15551       active_seg_prefix = 0;
15552       all_prefixes[last_seg_prefix] = NOTRACK_PREFIX;
15553     }
15554 }
15555
15556 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
15557    "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
15558  */
15559
15560 static void
15561 HLE_Fixup1 (int bytemode, int sizeflag)
15562 {
15563   if (modrm.mod != 3
15564       && (prefixes & PREFIX_LOCK) != 0)
15565     {
15566       if (prefixes & PREFIX_REPZ)
15567         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15568       if (prefixes & PREFIX_REPNZ)
15569         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15570     }
15571
15572   OP_E (bytemode, sizeflag);
15573 }
15574
15575 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
15576    "xacquire"/"xrelease" for memory operand.  No check for LOCK prefix.
15577  */
15578
15579 static void
15580 HLE_Fixup2 (int bytemode, int sizeflag)
15581 {
15582   if (modrm.mod != 3)
15583     {
15584       if (prefixes & PREFIX_REPZ)
15585         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15586       if (prefixes & PREFIX_REPNZ)
15587         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15588     }
15589
15590   OP_E (bytemode, sizeflag);
15591 }
15592
15593 /* Similar to OP_E.  But the 0xf3 prefixes should be displayed as
15594    "xrelease" for memory operand.  No check for LOCK prefix.   */
15595
15596 static void
15597 HLE_Fixup3 (int bytemode, int sizeflag)
15598 {
15599   if (modrm.mod != 3
15600       && last_repz_prefix > last_repnz_prefix
15601       && (prefixes & PREFIX_REPZ) != 0)
15602     all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15603
15604   OP_E (bytemode, sizeflag);
15605 }
15606
15607 static void
15608 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
15609 {
15610   USED_REX (REX_W);
15611   if (rex & REX_W)
15612     {
15613       /* Change cmpxchg8b to cmpxchg16b.  */
15614       char *p = mnemonicendp - 2;
15615       mnemonicendp = stpcpy (p, "16b");
15616       bytemode = o_mode;
15617     }
15618   else if ((prefixes & PREFIX_LOCK) != 0)
15619     {
15620       if (prefixes & PREFIX_REPZ)
15621         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15622       if (prefixes & PREFIX_REPNZ)
15623         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15624     }
15625
15626   OP_M (bytemode, sizeflag);
15627 }
15628
15629 static void
15630 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
15631 {
15632   const char **names;
15633
15634   if (need_vex)
15635     {
15636       switch (vex.length)
15637         {
15638         case 128:
15639           names = names_xmm;
15640           break;
15641         case 256:
15642           names = names_ymm;
15643           break;
15644         default:
15645           abort ();
15646         }
15647     }
15648   else
15649     names = names_xmm;
15650   oappend (names[reg]);
15651 }
15652
15653 static void
15654 CRC32_Fixup (int bytemode, int sizeflag)
15655 {
15656   /* Add proper suffix to "crc32".  */
15657   char *p = mnemonicendp;
15658
15659   switch (bytemode)
15660     {
15661     case b_mode:
15662       if (intel_syntax)
15663         goto skip;
15664
15665       *p++ = 'b';
15666       break;
15667     case v_mode:
15668       if (intel_syntax)
15669         goto skip;
15670
15671       USED_REX (REX_W);
15672       if (rex & REX_W)
15673         *p++ = 'q';
15674       else
15675         {
15676           if (sizeflag & DFLAG)
15677             *p++ = 'l';
15678           else
15679             *p++ = 'w';
15680           used_prefixes |= (prefixes & PREFIX_DATA);
15681         }
15682       break;
15683     default:
15684       oappend (INTERNAL_DISASSEMBLER_ERROR);
15685       break;
15686     }
15687   mnemonicendp = p;
15688   *p = '\0';
15689
15690  skip:
15691   if (modrm.mod == 3)
15692     {
15693       int add;
15694
15695       /* Skip mod/rm byte.  */
15696       MODRM_CHECK;
15697       codep++;
15698
15699       USED_REX (REX_B);
15700       add = (rex & REX_B) ? 8 : 0;
15701       if (bytemode == b_mode)
15702         {
15703           USED_REX (0);
15704           if (rex)
15705             oappend (names8rex[modrm.rm + add]);
15706           else
15707             oappend (names8[modrm.rm + add]);
15708         }
15709       else
15710         {
15711           USED_REX (REX_W);
15712           if (rex & REX_W)
15713             oappend (names64[modrm.rm + add]);
15714           else if ((prefixes & PREFIX_DATA))
15715             oappend (names16[modrm.rm + add]);
15716           else
15717             oappend (names32[modrm.rm + add]);
15718         }
15719     }
15720   else
15721     OP_E (bytemode, sizeflag);
15722 }
15723
15724 static void
15725 FXSAVE_Fixup (int bytemode, int sizeflag)
15726 {
15727   /* Add proper suffix to "fxsave" and "fxrstor".  */
15728   USED_REX (REX_W);
15729   if (rex & REX_W)
15730     {
15731       char *p = mnemonicendp;
15732       *p++ = '6';
15733       *p++ = '4';
15734       *p = '\0';
15735       mnemonicendp = p;
15736     }
15737   OP_M (bytemode, sizeflag);
15738 }
15739
15740 static void
15741 PCMPESTR_Fixup (int bytemode, int sizeflag)
15742 {
15743   /* Add proper suffix to "{,v}pcmpestr{i,m}".  */
15744   if (!intel_syntax)
15745     {
15746       char *p = mnemonicendp;
15747
15748       USED_REX (REX_W);
15749       if (rex & REX_W)
15750         *p++ = 'q';
15751       else if (sizeflag & SUFFIX_ALWAYS)
15752         *p++ = 'l';
15753
15754       *p = '\0';
15755       mnemonicendp = p;
15756     }
15757
15758   OP_EX (bytemode, sizeflag);
15759 }
15760
15761 /* Display the destination register operand for instructions with
15762    VEX. */
15763
15764 static void
15765 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
15766 {
15767   int reg;
15768   const char **names;
15769
15770   if (!need_vex)
15771     abort ();
15772
15773   if (!need_vex_reg)
15774     return;
15775
15776   reg = vex.register_specifier;
15777   vex.register_specifier = 0;
15778   if (address_mode != mode_64bit)
15779     reg &= 7;
15780   else if (vex.evex && !vex.v)
15781     reg += 16;
15782
15783   if (bytemode == vex_scalar_mode)
15784     {
15785       oappend (names_xmm[reg]);
15786       return;
15787     }
15788
15789   switch (vex.length)
15790     {
15791     case 128:
15792       switch (bytemode)
15793         {
15794         case vex_mode:
15795         case vex128_mode:
15796         case vex_vsib_q_w_dq_mode:
15797         case vex_vsib_q_w_d_mode:
15798           names = names_xmm;
15799           break;
15800         case dq_mode:
15801           if (rex & REX_W)
15802             names = names64;
15803           else
15804             names = names32;
15805           break;
15806         case mask_bd_mode:
15807         case mask_mode:
15808           if (reg > 0x7)
15809             {
15810               oappend ("(bad)");
15811               return;
15812             }
15813           names = names_mask;
15814           break;
15815         default:
15816           abort ();
15817           return;
15818         }
15819       break;
15820     case 256:
15821       switch (bytemode)
15822         {
15823         case vex_mode:
15824         case vex256_mode:
15825           names = names_ymm;
15826           break;
15827         case vex_vsib_q_w_dq_mode:
15828         case vex_vsib_q_w_d_mode:
15829           names = vex.w ? names_ymm : names_xmm;
15830           break;
15831         case mask_bd_mode:
15832         case mask_mode:
15833           if (reg > 0x7)
15834             {
15835               oappend ("(bad)");
15836               return;
15837             }
15838           names = names_mask;
15839           break;
15840         default:
15841           /* See PR binutils/20893 for a reproducer.  */
15842           oappend ("(bad)");
15843           return;
15844         }
15845       break;
15846     case 512:
15847       names = names_zmm;
15848       break;
15849     default:
15850       abort ();
15851       break;
15852     }
15853   oappend (names[reg]);
15854 }
15855
15856 /* Get the VEX immediate byte without moving codep.  */
15857
15858 static unsigned char
15859 get_vex_imm8 (int sizeflag, int opnum)
15860 {
15861   int bytes_before_imm = 0;
15862
15863   if (modrm.mod != 3)
15864     {
15865       /* There are SIB/displacement bytes.  */
15866       if ((sizeflag & AFLAG) || address_mode == mode_64bit)
15867         {
15868           /* 32/64 bit address mode */
15869           int base = modrm.rm;
15870
15871           /* Check SIB byte.  */
15872           if (base == 4)
15873             {
15874               FETCH_DATA (the_info, codep + 1);
15875               base = *codep & 7;
15876               /* When decoding the third source, don't increase
15877                  bytes_before_imm as this has already been incremented
15878                  by one in OP_E_memory while decoding the second
15879                  source operand.  */
15880               if (opnum == 0)
15881                 bytes_before_imm++;
15882             }
15883
15884           /* Don't increase bytes_before_imm when decoding the third source,
15885              it has already been incremented by OP_E_memory while decoding
15886              the second source operand.  */
15887           if (opnum == 0)
15888             {
15889               switch (modrm.mod)
15890                 {
15891                   case 0:
15892                     /* When modrm.rm == 5 or modrm.rm == 4 and base in
15893                        SIB == 5, there is a 4 byte displacement.  */
15894                     if (base != 5)
15895                       /* No displacement. */
15896                       break;
15897                     /* Fall through.  */
15898                   case 2:
15899                     /* 4 byte displacement.  */
15900                     bytes_before_imm += 4;
15901                     break;
15902                   case 1:
15903                     /* 1 byte displacement.  */
15904                     bytes_before_imm++;
15905                     break;
15906                 }
15907             }
15908         }
15909       else
15910         {
15911           /* 16 bit address mode */
15912           /* Don't increase bytes_before_imm when decoding the third source,
15913              it has already been incremented by OP_E_memory while decoding
15914              the second source operand.  */
15915           if (opnum == 0)
15916             {
15917               switch (modrm.mod)
15918                 {
15919                 case 0:
15920                   /* When modrm.rm == 6, there is a 2 byte displacement.  */
15921                   if (modrm.rm != 6)
15922                     /* No displacement. */
15923                     break;
15924                   /* Fall through.  */
15925                 case 2:
15926                   /* 2 byte displacement.  */
15927                   bytes_before_imm += 2;
15928                   break;
15929                 case 1:
15930                   /* 1 byte displacement: when decoding the third source,
15931                      don't increase bytes_before_imm as this has already
15932                      been incremented by one in OP_E_memory while decoding
15933                      the second source operand.  */
15934                   if (opnum == 0)
15935                     bytes_before_imm++;
15936
15937                   break;
15938                 }
15939             }
15940         }
15941     }
15942
15943   FETCH_DATA (the_info, codep + bytes_before_imm + 1);
15944   return codep [bytes_before_imm];
15945 }
15946
15947 static void
15948 OP_EX_VexReg (int bytemode, int sizeflag, int reg)
15949 {
15950   const char **names;
15951
15952   if (reg == -1 && modrm.mod != 3)
15953     {
15954       OP_E_memory (bytemode, sizeflag);
15955       return;
15956     }
15957   else
15958     {
15959       if (reg == -1)
15960         {
15961           reg = modrm.rm;
15962           USED_REX (REX_B);
15963           if (rex & REX_B)
15964             reg += 8;
15965         }
15966       if (address_mode != mode_64bit)
15967         reg &= 7;
15968     }
15969
15970   switch (vex.length)
15971     {
15972     case 128:
15973       names = names_xmm;
15974       break;
15975     case 256:
15976       names = names_ymm;
15977       break;
15978     default:
15979       abort ();
15980     }
15981   oappend (names[reg]);
15982 }
15983
15984 static void
15985 OP_EX_VexImmW (int bytemode, int sizeflag)
15986 {
15987   int reg = -1;
15988   static unsigned char vex_imm8;
15989
15990   if (vex_w_done == 0)
15991     {
15992       vex_w_done = 1;
15993
15994       /* Skip mod/rm byte.  */
15995       MODRM_CHECK;
15996       codep++;
15997
15998       vex_imm8 = get_vex_imm8 (sizeflag, 0);
15999
16000       if (vex.w)
16001           reg = vex_imm8 >> 4;
16002
16003       OP_EX_VexReg (bytemode, sizeflag, reg);
16004     }
16005   else if (vex_w_done == 1)
16006     {
16007       vex_w_done = 2;
16008
16009       if (!vex.w)
16010           reg = vex_imm8 >> 4;
16011
16012       OP_EX_VexReg (bytemode, sizeflag, reg);
16013     }
16014   else
16015     {
16016       /* Output the imm8 directly.  */
16017       scratchbuf[0] = '$';
16018       print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf);
16019       oappend_maybe_intel (scratchbuf);
16020       scratchbuf[0] = '\0';
16021       codep++;
16022     }
16023 }
16024
16025 static void
16026 OP_Vex_2src (int bytemode, int sizeflag)
16027 {
16028   if (modrm.mod == 3)
16029     {
16030       int reg = modrm.rm;
16031       USED_REX (REX_B);
16032       if (rex & REX_B)
16033         reg += 8;
16034       oappend (names_xmm[reg]);
16035     }
16036   else
16037     {
16038       if (intel_syntax
16039           && (bytemode == v_mode || bytemode == v_swap_mode))
16040         {
16041           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16042           used_prefixes |= (prefixes & PREFIX_DATA);
16043         }
16044       OP_E (bytemode, sizeflag);
16045     }
16046 }
16047
16048 static void
16049 OP_Vex_2src_1 (int bytemode, int sizeflag)
16050 {
16051   if (modrm.mod == 3)
16052     {
16053       /* Skip mod/rm byte.   */
16054       MODRM_CHECK;
16055       codep++;
16056     }
16057
16058   if (vex.w)
16059     {
16060       unsigned int reg = vex.register_specifier;
16061       vex.register_specifier = 0;
16062
16063       if (address_mode != mode_64bit)
16064         reg &= 7;
16065       oappend (names_xmm[reg]);
16066     }
16067   else
16068     OP_Vex_2src (bytemode, sizeflag);
16069 }
16070
16071 static void
16072 OP_Vex_2src_2 (int bytemode, int sizeflag)
16073 {
16074   if (vex.w)
16075     OP_Vex_2src (bytemode, sizeflag);
16076   else
16077     {
16078       unsigned int reg = vex.register_specifier;
16079       vex.register_specifier = 0;
16080
16081       if (address_mode != mode_64bit)
16082         reg &= 7;
16083       oappend (names_xmm[reg]);
16084     }
16085 }
16086
16087 static void
16088 OP_EX_VexW (int bytemode, int sizeflag)
16089 {
16090   int reg = -1;
16091
16092   if (!vex_w_done)
16093     {
16094       /* Skip mod/rm byte.  */
16095       MODRM_CHECK;
16096       codep++;
16097
16098       if (vex.w)
16099         reg = get_vex_imm8 (sizeflag, 0) >> 4;
16100     }
16101   else
16102     {
16103       if (!vex.w)
16104         reg = get_vex_imm8 (sizeflag, 1) >> 4;
16105     }
16106
16107   OP_EX_VexReg (bytemode, sizeflag, reg);
16108
16109   if (vex_w_done)
16110     codep++;
16111   vex_w_done = 1;
16112 }
16113
16114 static void
16115 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16116 {
16117   int reg;
16118   const char **names;
16119
16120   FETCH_DATA (the_info, codep + 1);
16121   reg = *codep++;
16122
16123   if (bytemode != x_mode)
16124     abort ();
16125
16126   reg >>= 4;
16127   if (address_mode != mode_64bit)
16128     reg &= 7;
16129
16130   switch (vex.length)
16131     {
16132     case 128:
16133       names = names_xmm;
16134       break;
16135     case 256:
16136       names = names_ymm;
16137       break;
16138     default:
16139       abort ();
16140     }
16141   oappend (names[reg]);
16142 }
16143
16144 static void
16145 OP_XMM_VexW (int bytemode, int sizeflag)
16146 {
16147   /* Turn off the REX.W bit since it is used for swapping operands
16148      now.  */
16149   rex &= ~REX_W;
16150   OP_XMM (bytemode, sizeflag);
16151 }
16152
16153 static void
16154 OP_EX_Vex (int bytemode, int sizeflag)
16155 {
16156   if (modrm.mod != 3)
16157     need_vex_reg = 0;
16158   OP_EX (bytemode, sizeflag);
16159 }
16160
16161 static void
16162 OP_XMM_Vex (int bytemode, int sizeflag)
16163 {
16164   if (modrm.mod != 3)
16165     need_vex_reg = 0;
16166   OP_XMM (bytemode, sizeflag);
16167 }
16168
16169 static struct op vex_cmp_op[] =
16170 {
16171   { STRING_COMMA_LEN ("eq") },
16172   { STRING_COMMA_LEN ("lt") },
16173   { STRING_COMMA_LEN ("le") },
16174   { STRING_COMMA_LEN ("unord") },
16175   { STRING_COMMA_LEN ("neq") },
16176   { STRING_COMMA_LEN ("nlt") },
16177   { STRING_COMMA_LEN ("nle") },
16178   { STRING_COMMA_LEN ("ord") },
16179   { STRING_COMMA_LEN ("eq_uq") },
16180   { STRING_COMMA_LEN ("nge") },
16181   { STRING_COMMA_LEN ("ngt") },
16182   { STRING_COMMA_LEN ("false") },
16183   { STRING_COMMA_LEN ("neq_oq") },
16184   { STRING_COMMA_LEN ("ge") },
16185   { STRING_COMMA_LEN ("gt") },
16186   { STRING_COMMA_LEN ("true") },
16187   { STRING_COMMA_LEN ("eq_os") },
16188   { STRING_COMMA_LEN ("lt_oq") },
16189   { STRING_COMMA_LEN ("le_oq") },
16190   { STRING_COMMA_LEN ("unord_s") },
16191   { STRING_COMMA_LEN ("neq_us") },
16192   { STRING_COMMA_LEN ("nlt_uq") },
16193   { STRING_COMMA_LEN ("nle_uq") },
16194   { STRING_COMMA_LEN ("ord_s") },
16195   { STRING_COMMA_LEN ("eq_us") },
16196   { STRING_COMMA_LEN ("nge_uq") },
16197   { STRING_COMMA_LEN ("ngt_uq") },
16198   { STRING_COMMA_LEN ("false_os") },
16199   { STRING_COMMA_LEN ("neq_os") },
16200   { STRING_COMMA_LEN ("ge_oq") },
16201   { STRING_COMMA_LEN ("gt_oq") },
16202   { STRING_COMMA_LEN ("true_us") },
16203 };
16204
16205 static void
16206 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16207 {
16208   unsigned int cmp_type;
16209
16210   FETCH_DATA (the_info, codep + 1);
16211   cmp_type = *codep++ & 0xff;
16212   if (cmp_type < ARRAY_SIZE (vex_cmp_op))
16213     {
16214       char suffix [3];
16215       char *p = mnemonicendp - 2;
16216       suffix[0] = p[0];
16217       suffix[1] = p[1];
16218       suffix[2] = '\0';
16219       sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
16220       mnemonicendp += vex_cmp_op[cmp_type].len;
16221     }
16222   else
16223     {
16224       /* We have a reserved extension byte.  Output it directly.  */
16225       scratchbuf[0] = '$';
16226       print_operand_value (scratchbuf + 1, 1, cmp_type);
16227       oappend_maybe_intel (scratchbuf);
16228       scratchbuf[0] = '\0';
16229     }
16230 }
16231
16232 static void
16233 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED,
16234              int sizeflag ATTRIBUTE_UNUSED)
16235 {
16236   unsigned int cmp_type;
16237
16238   if (!vex.evex)
16239     abort ();
16240
16241   FETCH_DATA (the_info, codep + 1);
16242   cmp_type = *codep++ & 0xff;
16243   /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
16244      If it's the case, print suffix, otherwise - print the immediate.  */
16245   if (cmp_type < ARRAY_SIZE (simd_cmp_op)
16246       && cmp_type != 3
16247       && cmp_type != 7)
16248     {
16249       char suffix [3];
16250       char *p = mnemonicendp - 2;
16251
16252       /* vpcmp* can have both one- and two-lettered suffix.  */
16253       if (p[0] == 'p')
16254         {
16255           p++;
16256           suffix[0] = p[0];
16257           suffix[1] = '\0';
16258         }
16259       else
16260         {
16261           suffix[0] = p[0];
16262           suffix[1] = p[1];
16263           suffix[2] = '\0';
16264         }
16265
16266       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
16267       mnemonicendp += simd_cmp_op[cmp_type].len;
16268     }
16269   else
16270     {
16271       /* We have a reserved extension byte.  Output it directly.  */
16272       scratchbuf[0] = '$';
16273       print_operand_value (scratchbuf + 1, 1, cmp_type);
16274       oappend_maybe_intel (scratchbuf);
16275       scratchbuf[0] = '\0';
16276     }
16277 }
16278
16279 static const struct op xop_cmp_op[] =
16280 {
16281   { STRING_COMMA_LEN ("lt") },
16282   { STRING_COMMA_LEN ("le") },
16283   { STRING_COMMA_LEN ("gt") },
16284   { STRING_COMMA_LEN ("ge") },
16285   { STRING_COMMA_LEN ("eq") },
16286   { STRING_COMMA_LEN ("neq") },
16287   { STRING_COMMA_LEN ("false") },
16288   { STRING_COMMA_LEN ("true") }
16289 };
16290
16291 static void
16292 VPCOM_Fixup (int bytemode ATTRIBUTE_UNUSED,
16293              int sizeflag ATTRIBUTE_UNUSED)
16294 {
16295   unsigned int cmp_type;
16296
16297   FETCH_DATA (the_info, codep + 1);
16298   cmp_type = *codep++ & 0xff;
16299   if (cmp_type < ARRAY_SIZE (xop_cmp_op))
16300     {
16301       char suffix[3];
16302       char *p = mnemonicendp - 2;
16303
16304       /* vpcom* can have both one- and two-lettered suffix.  */
16305       if (p[0] == 'm')
16306         {
16307           p++;
16308           suffix[0] = p[0];
16309           suffix[1] = '\0';
16310         }
16311       else
16312         {
16313           suffix[0] = p[0];
16314           suffix[1] = p[1];
16315           suffix[2] = '\0';
16316         }
16317
16318       sprintf (p, "%s%s", xop_cmp_op[cmp_type].name, suffix);
16319       mnemonicendp += xop_cmp_op[cmp_type].len;
16320     }
16321   else
16322     {
16323       /* We have a reserved extension byte.  Output it directly.  */
16324       scratchbuf[0] = '$';
16325       print_operand_value (scratchbuf + 1, 1, cmp_type);
16326       oappend_maybe_intel (scratchbuf);
16327       scratchbuf[0] = '\0';
16328     }
16329 }
16330
16331 static const struct op pclmul_op[] =
16332 {
16333   { STRING_COMMA_LEN ("lql") },
16334   { STRING_COMMA_LEN ("hql") },
16335   { STRING_COMMA_LEN ("lqh") },
16336   { STRING_COMMA_LEN ("hqh") }
16337 };
16338
16339 static void
16340 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
16341               int sizeflag ATTRIBUTE_UNUSED)
16342 {
16343   unsigned int pclmul_type;
16344
16345   FETCH_DATA (the_info, codep + 1);
16346   pclmul_type = *codep++ & 0xff;
16347   switch (pclmul_type)
16348     {
16349     case 0x10:
16350       pclmul_type = 2;
16351       break;
16352     case 0x11:
16353       pclmul_type = 3;
16354       break;
16355     default:
16356       break;
16357     }
16358   if (pclmul_type < ARRAY_SIZE (pclmul_op))
16359     {
16360       char suffix [4];
16361       char *p = mnemonicendp - 3;
16362       suffix[0] = p[0];
16363       suffix[1] = p[1];
16364       suffix[2] = p[2];
16365       suffix[3] = '\0';
16366       sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
16367       mnemonicendp += pclmul_op[pclmul_type].len;
16368     }
16369   else
16370     {
16371       /* We have a reserved extension byte.  Output it directly.  */
16372       scratchbuf[0] = '$';
16373       print_operand_value (scratchbuf + 1, 1, pclmul_type);
16374       oappend_maybe_intel (scratchbuf);
16375       scratchbuf[0] = '\0';
16376     }
16377 }
16378
16379 static void
16380 MOVBE_Fixup (int bytemode, int sizeflag)
16381 {
16382   /* Add proper suffix to "movbe".  */
16383   char *p = mnemonicendp;
16384
16385   switch (bytemode)
16386     {
16387     case v_mode:
16388       if (intel_syntax)
16389         goto skip;
16390
16391       USED_REX (REX_W);
16392       if (sizeflag & SUFFIX_ALWAYS)
16393         {
16394           if (rex & REX_W)
16395             *p++ = 'q';
16396           else
16397             {
16398               if (sizeflag & DFLAG)
16399                 *p++ = 'l';
16400               else
16401                 *p++ = 'w';
16402               used_prefixes |= (prefixes & PREFIX_DATA);
16403             }
16404         }
16405       break;
16406     default:
16407       oappend (INTERNAL_DISASSEMBLER_ERROR);
16408       break;
16409     }
16410   mnemonicendp = p;
16411   *p = '\0';
16412
16413  skip:
16414   OP_M (bytemode, sizeflag);
16415 }
16416
16417 static void
16418 MOVSXD_Fixup (int bytemode, int sizeflag)
16419 {
16420   /* Add proper suffix to "movsxd".  */
16421   char *p = mnemonicendp;
16422
16423   switch (bytemode)
16424     {
16425     case movsxd_mode:
16426       if (intel_syntax)
16427         {
16428           *p++ = 'x';
16429           *p++ = 'd';
16430           goto skip;
16431         }
16432
16433       USED_REX (REX_W);
16434       if (rex & REX_W)
16435         {
16436           *p++ = 'l';
16437           *p++ = 'q';
16438         }
16439       else
16440         {
16441           *p++ = 'x';
16442           *p++ = 'd';
16443         }
16444       break;
16445     default:
16446       oappend (INTERNAL_DISASSEMBLER_ERROR);
16447       break;
16448     }
16449
16450  skip:
16451   mnemonicendp = p;
16452   *p = '\0';
16453   OP_E (bytemode, sizeflag);
16454 }
16455
16456 static void
16457 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16458 {
16459   int reg;
16460   const char **names;
16461
16462   /* Skip mod/rm byte.  */
16463   MODRM_CHECK;
16464   codep++;
16465
16466   if (rex & REX_W)
16467     names = names64;
16468   else
16469     names = names32;
16470
16471   reg = modrm.rm;
16472   USED_REX (REX_B);
16473   if (rex & REX_B)
16474     reg += 8;
16475
16476   oappend (names[reg]);
16477 }
16478
16479 static void
16480 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16481 {
16482   const char **names;
16483   unsigned int reg = vex.register_specifier;
16484   vex.register_specifier = 0;
16485
16486   if (rex & REX_W)
16487     names = names64;
16488   else
16489     names = names32;
16490
16491   if (address_mode != mode_64bit)
16492     reg &= 7;
16493   oappend (names[reg]);
16494 }
16495
16496 static void
16497 OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16498 {
16499   if (!vex.evex
16500       || (bytemode != mask_mode && bytemode != mask_bd_mode))
16501     abort ();
16502
16503   USED_REX (REX_R);
16504   if ((rex & REX_R) != 0 || !vex.r)
16505     {
16506       BadOp ();
16507       return;
16508     }
16509
16510   oappend (names_mask [modrm.reg]);
16511 }
16512
16513 static void
16514 OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16515 {
16516   if (modrm.mod == 3 && vex.b)
16517     switch (bytemode)
16518       {
16519       case evex_rounding_64_mode:
16520         if (address_mode != mode_64bit)
16521           {
16522             oappend ("(bad)");
16523             break;
16524           }
16525         /* Fall through.  */
16526       case evex_rounding_mode:
16527         oappend (names_rounding[vex.ll]);
16528         break;
16529       case evex_sae_mode:
16530         oappend ("{sae}");
16531         break;
16532       default:
16533         abort ();
16534         break;
16535       }
16536 }