1 /* Print i386 instructions for GDB, the GNU debugger.
2 Copyright (C) 1988-2020 Free Software Foundation, Inc.
4 This file is part of the GNU opcodes library.
6 This library is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 It is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
24 modified by John Hassey (hassey@dg-rtp.dg.com)
25 x86-64 support added by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */
28 /* The main tables describing the instructions is essentially a copy
29 of the "Opcode Map" chapter (Appendix A) of the Intel 80386
30 Programmers Manual. Usually, there is a capital letter, followed
31 by a small letter. The capital letter tell the addressing mode,
32 and the small letter tells about the operand size. Refer to
33 the Intel manual for details. */
36 #include "disassemble.h"
38 #include "opcode/i386.h"
39 #include "libiberty.h"
40 #include "safe-ctype.h"
44 static int print_insn (bfd_vma
, disassemble_info
*);
45 static void dofloat (int);
46 static void OP_ST (int, int);
47 static void OP_STi (int, int);
48 static int putop (const char *, int);
49 static void oappend (const char *);
50 static void append_seg (void);
51 static void OP_indirE (int, int);
52 static void print_operand_value (char *, int, bfd_vma
);
53 static void OP_E_register (int, int);
54 static void OP_E_memory (int, int);
55 static void print_displacement (char *, bfd_vma
);
56 static void OP_E (int, int);
57 static void OP_G (int, int);
58 static bfd_vma
get64 (void);
59 static bfd_signed_vma
get32 (void);
60 static bfd_signed_vma
get32s (void);
61 static int get16 (void);
62 static void set_op (bfd_vma
, int);
63 static void OP_Skip_MODRM (int, int);
64 static void OP_REG (int, int);
65 static void OP_IMREG (int, int);
66 static void OP_I (int, int);
67 static void OP_I64 (int, int);
68 static void OP_sI (int, int);
69 static void OP_J (int, int);
70 static void OP_SEG (int, int);
71 static void OP_DIR (int, int);
72 static void OP_OFF (int, int);
73 static void OP_OFF64 (int, int);
74 static void ptr_reg (int, int);
75 static void OP_ESreg (int, int);
76 static void OP_DSreg (int, int);
77 static void OP_C (int, int);
78 static void OP_D (int, int);
79 static void OP_T (int, int);
80 static void OP_R (int, int);
81 static void OP_MMX (int, int);
82 static void OP_XMM (int, int);
83 static void OP_EM (int, int);
84 static void OP_EX (int, int);
85 static void OP_EMC (int,int);
86 static void OP_MXC (int,int);
87 static void OP_MS (int, int);
88 static void OP_XS (int, int);
89 static void OP_M (int, int);
90 static void OP_VEX (int, int);
91 static void OP_EX_Vex (int, int);
92 static void OP_EX_VexW (int, int);
93 static void OP_EX_VexImmW (int, int);
94 static void OP_XMM_Vex (int, int);
95 static void OP_XMM_VexW (int, int);
96 static void OP_Rounding (int, int);
97 static void OP_REG_VexI4 (int, int);
98 static void PCLMUL_Fixup (int, int);
99 static void VCMP_Fixup (int, int);
100 static void VPCMP_Fixup (int, int);
101 static void VPCOM_Fixup (int, int);
102 static void OP_0f07 (int, int);
103 static void OP_Monitor (int, int);
104 static void OP_Mwait (int, int);
105 static void NOP_Fixup1 (int, int);
106 static void NOP_Fixup2 (int, int);
107 static void OP_3DNowSuffix (int, int);
108 static void CMP_Fixup (int, int);
109 static void BadOp (void);
110 static void REP_Fixup (int, int);
111 static void SEP_Fixup (int, int);
112 static void BND_Fixup (int, int);
113 static void NOTRACK_Fixup (int, int);
114 static void HLE_Fixup1 (int, int);
115 static void HLE_Fixup2 (int, int);
116 static void HLE_Fixup3 (int, int);
117 static void CMPXCHG8B_Fixup (int, int);
118 static void XMM_Fixup (int, int);
119 static void CRC32_Fixup (int, int);
120 static void FXSAVE_Fixup (int, int);
121 static void PCMPESTR_Fixup (int, int);
122 static void OP_LWPCB_E (int, int);
123 static void OP_LWP_E (int, int);
124 static void OP_Vex_2src_1 (int, int);
125 static void OP_Vex_2src_2 (int, int);
127 static void MOVBE_Fixup (int, int);
128 static void MOVSXD_Fixup (int, int);
130 static void OP_Mask (int, int);
133 /* Points to first byte not fetched. */
134 bfd_byte
*max_fetched
;
135 bfd_byte the_buffer
[MAX_MNEM_SIZE
];
138 OPCODES_SIGJMP_BUF bailout
;
148 enum address_mode address_mode
;
150 /* Flags for the prefixes for the current instruction. See below. */
153 /* REX prefix the current instruction. See below. */
155 /* Bits of REX we've already used. */
157 /* Mark parts used in the REX prefix. When we are testing for
158 empty prefix (for 8bit register REX extension), just mask it
159 out. Otherwise test for REX bit is excuse for existence of REX
160 only in case value is nonzero. */
161 #define USED_REX(value) \
166 rex_used |= (value) | REX_OPCODE; \
169 rex_used |= REX_OPCODE; \
172 /* Flags for prefixes which we somehow handled when printing the
173 current instruction. */
174 static int used_prefixes
;
176 /* Flags stored in PREFIXES. */
177 #define PREFIX_REPZ 1
178 #define PREFIX_REPNZ 2
179 #define PREFIX_LOCK 4
181 #define PREFIX_SS 0x10
182 #define PREFIX_DS 0x20
183 #define PREFIX_ES 0x40
184 #define PREFIX_FS 0x80
185 #define PREFIX_GS 0x100
186 #define PREFIX_DATA 0x200
187 #define PREFIX_ADDR 0x400
188 #define PREFIX_FWAIT 0x800
190 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
191 to ADDR (exclusive) are valid. Returns 1 for success, longjmps
193 #define FETCH_DATA(info, addr) \
194 ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
195 ? 1 : fetch_data ((info), (addr)))
198 fetch_data (struct disassemble_info
*info
, bfd_byte
*addr
)
201 struct dis_private
*priv
= (struct dis_private
*) info
->private_data
;
202 bfd_vma start
= priv
->insn_start
+ (priv
->max_fetched
- priv
->the_buffer
);
204 if (addr
<= priv
->the_buffer
+ MAX_MNEM_SIZE
)
205 status
= (*info
->read_memory_func
) (start
,
207 addr
- priv
->max_fetched
,
213 /* If we did manage to read at least one byte, then
214 print_insn_i386 will do something sensible. Otherwise, print
215 an error. We do that here because this is where we know
217 if (priv
->max_fetched
== priv
->the_buffer
)
218 (*info
->memory_error_func
) (status
, start
, info
);
219 OPCODES_SIGLONGJMP (priv
->bailout
, 1);
222 priv
->max_fetched
= addr
;
226 /* Possible values for prefix requirement. */
227 #define PREFIX_IGNORED_SHIFT 16
228 #define PREFIX_IGNORED_REPZ (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
229 #define PREFIX_IGNORED_REPNZ (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
230 #define PREFIX_IGNORED_DATA (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
231 #define PREFIX_IGNORED_ADDR (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
232 #define PREFIX_IGNORED_LOCK (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
234 /* Opcode prefixes. */
235 #define PREFIX_OPCODE (PREFIX_REPZ \
239 /* Prefixes ignored. */
240 #define PREFIX_IGNORED (PREFIX_IGNORED_REPZ \
241 | PREFIX_IGNORED_REPNZ \
242 | PREFIX_IGNORED_DATA)
244 #define XX { NULL, 0 }
245 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
247 #define Eb { OP_E, b_mode }
248 #define Ebnd { OP_E, bnd_mode }
249 #define EbS { OP_E, b_swap_mode }
250 #define EbndS { OP_E, bnd_swap_mode }
251 #define Ev { OP_E, v_mode }
252 #define Eva { OP_E, va_mode }
253 #define Ev_bnd { OP_E, v_bnd_mode }
254 #define EvS { OP_E, v_swap_mode }
255 #define Ed { OP_E, d_mode }
256 #define Edq { OP_E, dq_mode }
257 #define Edqw { OP_E, dqw_mode }
258 #define Edqb { OP_E, dqb_mode }
259 #define Edb { OP_E, db_mode }
260 #define Edw { OP_E, dw_mode }
261 #define Edqd { OP_E, dqd_mode }
262 #define Eq { OP_E, q_mode }
263 #define indirEv { OP_indirE, indir_v_mode }
264 #define indirEp { OP_indirE, f_mode }
265 #define stackEv { OP_E, stack_v_mode }
266 #define Em { OP_E, m_mode }
267 #define Ew { OP_E, w_mode }
268 #define M { OP_M, 0 } /* lea, lgdt, etc. */
269 #define Ma { OP_M, a_mode }
270 #define Mb { OP_M, b_mode }
271 #define Md { OP_M, d_mode }
272 #define Mo { OP_M, o_mode }
273 #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */
274 #define Mq { OP_M, q_mode }
275 #define Mv_bnd { OP_M, v_bndmk_mode }
276 #define Mx { OP_M, x_mode }
277 #define Mxmm { OP_M, xmm_mode }
278 #define Gb { OP_G, b_mode }
279 #define Gbnd { OP_G, bnd_mode }
280 #define Gv { OP_G, v_mode }
281 #define Gd { OP_G, d_mode }
282 #define Gdq { OP_G, dq_mode }
283 #define Gm { OP_G, m_mode }
284 #define Gva { OP_G, va_mode }
285 #define Gw { OP_G, w_mode }
286 #define Rd { OP_R, d_mode }
287 #define Rdq { OP_R, dq_mode }
288 #define Rm { OP_R, m_mode }
289 #define Ib { OP_I, b_mode }
290 #define sIb { OP_sI, b_mode } /* sign extened byte */
291 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
292 #define Iv { OP_I, v_mode }
293 #define sIv { OP_sI, v_mode }
294 #define Iv64 { OP_I64, v_mode }
295 #define Id { OP_I, d_mode }
296 #define Iw { OP_I, w_mode }
297 #define I1 { OP_I, const_1_mode }
298 #define Jb { OP_J, b_mode }
299 #define Jv { OP_J, v_mode }
300 #define Jdqw { OP_J, dqw_mode }
301 #define Cm { OP_C, m_mode }
302 #define Dm { OP_D, m_mode }
303 #define Td { OP_T, d_mode }
304 #define Skip_MODRM { OP_Skip_MODRM, 0 }
306 #define RMeAX { OP_REG, eAX_reg }
307 #define RMeBX { OP_REG, eBX_reg }
308 #define RMeCX { OP_REG, eCX_reg }
309 #define RMeDX { OP_REG, eDX_reg }
310 #define RMeSP { OP_REG, eSP_reg }
311 #define RMeBP { OP_REG, eBP_reg }
312 #define RMeSI { OP_REG, eSI_reg }
313 #define RMeDI { OP_REG, eDI_reg }
314 #define RMrAX { OP_REG, rAX_reg }
315 #define RMrBX { OP_REG, rBX_reg }
316 #define RMrCX { OP_REG, rCX_reg }
317 #define RMrDX { OP_REG, rDX_reg }
318 #define RMrSP { OP_REG, rSP_reg }
319 #define RMrBP { OP_REG, rBP_reg }
320 #define RMrSI { OP_REG, rSI_reg }
321 #define RMrDI { OP_REG, rDI_reg }
322 #define RMAL { OP_REG, al_reg }
323 #define RMCL { OP_REG, cl_reg }
324 #define RMDL { OP_REG, dl_reg }
325 #define RMBL { OP_REG, bl_reg }
326 #define RMAH { OP_REG, ah_reg }
327 #define RMCH { OP_REG, ch_reg }
328 #define RMDH { OP_REG, dh_reg }
329 #define RMBH { OP_REG, bh_reg }
330 #define RMAX { OP_REG, ax_reg }
331 #define RMDX { OP_REG, dx_reg }
333 #define eAX { OP_IMREG, eAX_reg }
334 #define eBX { OP_IMREG, eBX_reg }
335 #define eCX { OP_IMREG, eCX_reg }
336 #define eDX { OP_IMREG, eDX_reg }
337 #define eSP { OP_IMREG, eSP_reg }
338 #define eBP { OP_IMREG, eBP_reg }
339 #define eSI { OP_IMREG, eSI_reg }
340 #define eDI { OP_IMREG, eDI_reg }
341 #define AL { OP_IMREG, al_reg }
342 #define CL { OP_IMREG, cl_reg }
343 #define DL { OP_IMREG, dl_reg }
344 #define BL { OP_IMREG, bl_reg }
345 #define AH { OP_IMREG, ah_reg }
346 #define CH { OP_IMREG, ch_reg }
347 #define DH { OP_IMREG, dh_reg }
348 #define BH { OP_IMREG, bh_reg }
349 #define AX { OP_IMREG, ax_reg }
350 #define DX { OP_IMREG, dx_reg }
351 #define zAX { OP_IMREG, z_mode_ax_reg }
352 #define indirDX { OP_IMREG, indir_dx_reg }
354 #define Sw { OP_SEG, w_mode }
355 #define Sv { OP_SEG, v_mode }
356 #define Ap { OP_DIR, 0 }
357 #define Ob { OP_OFF64, b_mode }
358 #define Ov { OP_OFF64, v_mode }
359 #define Xb { OP_DSreg, eSI_reg }
360 #define Xv { OP_DSreg, eSI_reg }
361 #define Xz { OP_DSreg, eSI_reg }
362 #define Yb { OP_ESreg, eDI_reg }
363 #define Yv { OP_ESreg, eDI_reg }
364 #define DSBX { OP_DSreg, eBX_reg }
366 #define es { OP_REG, es_reg }
367 #define ss { OP_REG, ss_reg }
368 #define cs { OP_REG, cs_reg }
369 #define ds { OP_REG, ds_reg }
370 #define fs { OP_REG, fs_reg }
371 #define gs { OP_REG, gs_reg }
373 #define MX { OP_MMX, 0 }
374 #define XM { OP_XMM, 0 }
375 #define XMScalar { OP_XMM, scalar_mode }
376 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
377 #define XMM { OP_XMM, xmm_mode }
378 #define XMxmmq { OP_XMM, xmmq_mode }
379 #define EM { OP_EM, v_mode }
380 #define EMS { OP_EM, v_swap_mode }
381 #define EMd { OP_EM, d_mode }
382 #define EMx { OP_EM, x_mode }
383 #define EXbScalar { OP_EX, b_scalar_mode }
384 #define EXw { OP_EX, w_mode }
385 #define EXwScalar { OP_EX, w_scalar_mode }
386 #define EXd { OP_EX, d_mode }
387 #define EXdS { OP_EX, d_swap_mode }
388 #define EXq { OP_EX, q_mode }
389 #define EXqS { OP_EX, q_swap_mode }
390 #define EXx { OP_EX, x_mode }
391 #define EXxS { OP_EX, x_swap_mode }
392 #define EXxmm { OP_EX, xmm_mode }
393 #define EXymm { OP_EX, ymm_mode }
394 #define EXxmmq { OP_EX, xmmq_mode }
395 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
396 #define EXxmm_mb { OP_EX, xmm_mb_mode }
397 #define EXxmm_mw { OP_EX, xmm_mw_mode }
398 #define EXxmm_md { OP_EX, xmm_md_mode }
399 #define EXxmm_mq { OP_EX, xmm_mq_mode }
400 #define EXxmmdw { OP_EX, xmmdw_mode }
401 #define EXxmmqd { OP_EX, xmmqd_mode }
402 #define EXymmq { OP_EX, ymmq_mode }
403 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
404 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
405 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
406 #define MS { OP_MS, v_mode }
407 #define XS { OP_XS, v_mode }
408 #define EMCq { OP_EMC, q_mode }
409 #define MXC { OP_MXC, 0 }
410 #define OPSUF { OP_3DNowSuffix, 0 }
411 #define SEP { SEP_Fixup, 0 }
412 #define CMP { CMP_Fixup, 0 }
413 #define XMM0 { XMM_Fixup, 0 }
414 #define FXSAVE { FXSAVE_Fixup, 0 }
415 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
416 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
418 #define Vex { OP_VEX, vex_mode }
419 #define VexScalar { OP_VEX, vex_scalar_mode }
420 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
421 #define Vex128 { OP_VEX, vex128_mode }
422 #define Vex256 { OP_VEX, vex256_mode }
423 #define VexGdq { OP_VEX, dq_mode }
424 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
425 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
426 #define EXVexW { OP_EX_VexW, x_mode }
427 #define EXdVexW { OP_EX_VexW, d_mode }
428 #define EXqVexW { OP_EX_VexW, q_mode }
429 #define EXVexImmW { OP_EX_VexImmW, x_mode }
430 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
431 #define XMVexW { OP_XMM_VexW, 0 }
432 #define XMVexI4 { OP_REG_VexI4, x_mode }
433 #define PCLMUL { PCLMUL_Fixup, 0 }
434 #define VCMP { VCMP_Fixup, 0 }
435 #define VPCMP { VPCMP_Fixup, 0 }
436 #define VPCOM { VPCOM_Fixup, 0 }
438 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
439 #define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode }
440 #define EXxEVexS { OP_Rounding, evex_sae_mode }
442 #define XMask { OP_Mask, mask_mode }
443 #define MaskG { OP_G, mask_mode }
444 #define MaskE { OP_E, mask_mode }
445 #define MaskBDE { OP_E, mask_bd_mode }
446 #define MaskR { OP_R, mask_mode }
447 #define MaskVex { OP_VEX, mask_mode }
449 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
450 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
451 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
452 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
454 /* Used handle "rep" prefix for string instructions. */
455 #define Xbr { REP_Fixup, eSI_reg }
456 #define Xvr { REP_Fixup, eSI_reg }
457 #define Ybr { REP_Fixup, eDI_reg }
458 #define Yvr { REP_Fixup, eDI_reg }
459 #define Yzr { REP_Fixup, eDI_reg }
460 #define indirDXr { REP_Fixup, indir_dx_reg }
461 #define ALr { REP_Fixup, al_reg }
462 #define eAXr { REP_Fixup, eAX_reg }
464 /* Used handle HLE prefix for lockable instructions. */
465 #define Ebh1 { HLE_Fixup1, b_mode }
466 #define Evh1 { HLE_Fixup1, v_mode }
467 #define Ebh2 { HLE_Fixup2, b_mode }
468 #define Evh2 { HLE_Fixup2, v_mode }
469 #define Ebh3 { HLE_Fixup3, b_mode }
470 #define Evh3 { HLE_Fixup3, v_mode }
472 #define BND { BND_Fixup, 0 }
473 #define NOTRACK { NOTRACK_Fixup, 0 }
475 #define cond_jump_flag { NULL, cond_jump_mode }
476 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
478 /* bits in sizeflag */
479 #define SUFFIX_ALWAYS 4
487 /* byte operand with operand swapped */
489 /* byte operand, sign extend like 'T' suffix */
491 /* operand size depends on prefixes */
493 /* operand size depends on prefixes with operand swapped */
495 /* operand size depends on address prefix */
499 /* double word operand */
501 /* double word operand with operand swapped */
503 /* quad word operand */
505 /* quad word operand with operand swapped */
507 /* ten-byte operand */
509 /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand. In EVEX with
510 broadcast enabled. */
512 /* Similar to x_mode, but with different EVEX mem shifts. */
514 /* Similar to x_mode, but with disabled broadcast. */
516 /* Similar to x_mode, but with operands swapped and disabled broadcast
519 /* 16-byte XMM operand */
521 /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
522 memory operand (depending on vector length). Broadcast isn't
525 /* Same as xmmq_mode, but broadcast is allowed. */
526 evex_half_bcst_xmmq_mode
,
527 /* XMM register or byte memory operand */
529 /* XMM register or word memory operand */
531 /* XMM register or double word memory operand */
533 /* XMM register or quad word memory operand */
535 /* 16-byte XMM, word, double word or quad word operand. */
537 /* 16-byte XMM, double word, quad word operand or xmm word operand. */
539 /* 32-byte YMM operand */
541 /* quad word, ymmword or zmmword memory operand. */
543 /* 32-byte YMM or 16-byte word operand */
545 /* d_mode in 32bit, q_mode in 64bit mode. */
547 /* pair of v_mode operands */
553 /* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode. */
555 /* operand size depends on REX prefixes. */
557 /* registers like dq_mode, memory like w_mode, displacements like
558 v_mode without considering Intel64 ISA. */
562 /* bounds operand with operand swapped */
564 /* 4- or 6-byte pointer operand */
567 /* v_mode for indirect branch opcodes. */
569 /* v_mode for stack-related opcodes. */
571 /* non-quad operand size depends on prefixes */
573 /* 16-byte operand */
575 /* registers like dq_mode, memory like b_mode. */
577 /* registers like d_mode, memory like b_mode. */
579 /* registers like d_mode, memory like w_mode. */
581 /* registers like dq_mode, memory like d_mode. */
583 /* normal vex mode */
585 /* 128bit vex mode */
587 /* 256bit vex mode */
590 /* Operand size depends on the VEX.W bit, with VSIB dword indices. */
591 vex_vsib_d_w_dq_mode
,
592 /* Similar to vex_vsib_d_w_dq_mode, with smaller memory. */
594 /* Operand size depends on the VEX.W bit, with VSIB qword indices. */
595 vex_vsib_q_w_dq_mode
,
596 /* Similar to vex_vsib_q_w_dq_mode, with smaller memory. */
599 /* scalar, ignore vector length. */
601 /* like b_mode, ignore vector length. */
603 /* like w_mode, ignore vector length. */
605 /* like d_swap_mode, ignore vector length. */
607 /* like q_swap_mode, ignore vector length. */
609 /* like vex_mode, ignore vector length. */
611 /* Operand size depends on the VEX.W bit, ignore vector length. */
612 vex_scalar_w_dq_mode
,
614 /* Static rounding. */
616 /* Static rounding, 64-bit mode only. */
617 evex_rounding_64_mode
,
618 /* Supress all exceptions. */
621 /* Mask register operand. */
623 /* Mask register operand. */
691 #define FLOAT NULL, { { NULL, FLOATCODE } }, 0
693 #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }, 0
694 #define DIS386_PREFIX(T, I, P) NULL, { { NULL, (T)}, { NULL, (I) } }, P
695 #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I))
696 #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I))
697 #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I))
698 #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I))
699 #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I))
700 #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I))
701 #define THREE_BYTE_TABLE_PREFIX(I, P) DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
702 #define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I))
703 #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I))
704 #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I))
705 #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I))
706 #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I))
707 #define EVEX_TABLE(I) DIS386 (USE_EVEX_TABLE, (I))
708 #define EVEX_LEN_TABLE(I) DIS386 (USE_EVEX_LEN_TABLE, (I))
838 MOD_VEX_0F12_PREFIX_0
,
839 MOD_VEX_0F12_PREFIX_2
,
841 MOD_VEX_0F16_PREFIX_0
,
842 MOD_VEX_0F16_PREFIX_2
,
845 MOD_VEX_W_0_0F41_P_0_LEN_1
,
846 MOD_VEX_W_1_0F41_P_0_LEN_1
,
847 MOD_VEX_W_0_0F41_P_2_LEN_1
,
848 MOD_VEX_W_1_0F41_P_2_LEN_1
,
849 MOD_VEX_W_0_0F42_P_0_LEN_1
,
850 MOD_VEX_W_1_0F42_P_0_LEN_1
,
851 MOD_VEX_W_0_0F42_P_2_LEN_1
,
852 MOD_VEX_W_1_0F42_P_2_LEN_1
,
853 MOD_VEX_W_0_0F44_P_0_LEN_1
,
854 MOD_VEX_W_1_0F44_P_0_LEN_1
,
855 MOD_VEX_W_0_0F44_P_2_LEN_1
,
856 MOD_VEX_W_1_0F44_P_2_LEN_1
,
857 MOD_VEX_W_0_0F45_P_0_LEN_1
,
858 MOD_VEX_W_1_0F45_P_0_LEN_1
,
859 MOD_VEX_W_0_0F45_P_2_LEN_1
,
860 MOD_VEX_W_1_0F45_P_2_LEN_1
,
861 MOD_VEX_W_0_0F46_P_0_LEN_1
,
862 MOD_VEX_W_1_0F46_P_0_LEN_1
,
863 MOD_VEX_W_0_0F46_P_2_LEN_1
,
864 MOD_VEX_W_1_0F46_P_2_LEN_1
,
865 MOD_VEX_W_0_0F47_P_0_LEN_1
,
866 MOD_VEX_W_1_0F47_P_0_LEN_1
,
867 MOD_VEX_W_0_0F47_P_2_LEN_1
,
868 MOD_VEX_W_1_0F47_P_2_LEN_1
,
869 MOD_VEX_W_0_0F4A_P_0_LEN_1
,
870 MOD_VEX_W_1_0F4A_P_0_LEN_1
,
871 MOD_VEX_W_0_0F4A_P_2_LEN_1
,
872 MOD_VEX_W_1_0F4A_P_2_LEN_1
,
873 MOD_VEX_W_0_0F4B_P_0_LEN_1
,
874 MOD_VEX_W_1_0F4B_P_0_LEN_1
,
875 MOD_VEX_W_0_0F4B_P_2_LEN_1
,
887 MOD_VEX_W_0_0F91_P_0_LEN_0
,
888 MOD_VEX_W_1_0F91_P_0_LEN_0
,
889 MOD_VEX_W_0_0F91_P_2_LEN_0
,
890 MOD_VEX_W_1_0F91_P_2_LEN_0
,
891 MOD_VEX_W_0_0F92_P_0_LEN_0
,
892 MOD_VEX_W_0_0F92_P_2_LEN_0
,
893 MOD_VEX_0F92_P_3_LEN_0
,
894 MOD_VEX_W_0_0F93_P_0_LEN_0
,
895 MOD_VEX_W_0_0F93_P_2_LEN_0
,
896 MOD_VEX_0F93_P_3_LEN_0
,
897 MOD_VEX_W_0_0F98_P_0_LEN_0
,
898 MOD_VEX_W_1_0F98_P_0_LEN_0
,
899 MOD_VEX_W_0_0F98_P_2_LEN_0
,
900 MOD_VEX_W_1_0F98_P_2_LEN_0
,
901 MOD_VEX_W_0_0F99_P_0_LEN_0
,
902 MOD_VEX_W_1_0F99_P_0_LEN_0
,
903 MOD_VEX_W_0_0F99_P_2_LEN_0
,
904 MOD_VEX_W_1_0F99_P_2_LEN_0
,
907 MOD_VEX_0FD7_PREFIX_2
,
908 MOD_VEX_0FE7_PREFIX_2
,
909 MOD_VEX_0FF0_PREFIX_3
,
910 MOD_VEX_0F381A_PREFIX_2
,
911 MOD_VEX_0F382A_PREFIX_2
,
912 MOD_VEX_0F382C_PREFIX_2
,
913 MOD_VEX_0F382D_PREFIX_2
,
914 MOD_VEX_0F382E_PREFIX_2
,
915 MOD_VEX_0F382F_PREFIX_2
,
916 MOD_VEX_0F385A_PREFIX_2
,
917 MOD_VEX_0F388C_PREFIX_2
,
918 MOD_VEX_0F388E_PREFIX_2
,
919 MOD_VEX_W_0_0F3A30_P_2_LEN_0
,
920 MOD_VEX_W_1_0F3A30_P_2_LEN_0
,
921 MOD_VEX_W_0_0F3A31_P_2_LEN_0
,
922 MOD_VEX_W_1_0F3A31_P_2_LEN_0
,
923 MOD_VEX_W_0_0F3A32_P_2_LEN_0
,
924 MOD_VEX_W_1_0F3A32_P_2_LEN_0
,
925 MOD_VEX_W_0_0F3A33_P_2_LEN_0
,
926 MOD_VEX_W_1_0F3A33_P_2_LEN_0
,
928 MOD_EVEX_0F12_PREFIX_0
,
929 MOD_EVEX_0F12_PREFIX_2
,
931 MOD_EVEX_0F16_PREFIX_0
,
932 MOD_EVEX_0F16_PREFIX_2
,
935 MOD_EVEX_0F381A_P_2_W_0
,
936 MOD_EVEX_0F381A_P_2_W_1
,
937 MOD_EVEX_0F381B_P_2_W_0
,
938 MOD_EVEX_0F381B_P_2_W_1
,
939 MOD_EVEX_0F385A_P_2_W_0
,
940 MOD_EVEX_0F385A_P_2_W_1
,
941 MOD_EVEX_0F385B_P_2_W_0
,
942 MOD_EVEX_0F385B_P_2_W_1
,
943 MOD_EVEX_0F38C6_REG_1
,
944 MOD_EVEX_0F38C6_REG_2
,
945 MOD_EVEX_0F38C6_REG_5
,
946 MOD_EVEX_0F38C6_REG_6
,
947 MOD_EVEX_0F38C7_REG_1
,
948 MOD_EVEX_0F38C7_REG_2
,
949 MOD_EVEX_0F38C7_REG_5
,
950 MOD_EVEX_0F38C7_REG_6
963 RM_0F1E_P_1_MOD_3_REG_7
,
964 RM_0FAE_REG_6_MOD_3_P_0
,
971 PREFIX_0F01_REG_3_RM_1
,
972 PREFIX_0F01_REG_5_MOD_0
,
973 PREFIX_0F01_REG_5_MOD_3_RM_0
,
974 PREFIX_0F01_REG_5_MOD_3_RM_1
,
975 PREFIX_0F01_REG_5_MOD_3_RM_2
,
976 PREFIX_0F01_REG_7_MOD_3_RM_2
,
977 PREFIX_0F01_REG_7_MOD_3_RM_3
,
1019 PREFIX_0FAE_REG_0_MOD_3
,
1020 PREFIX_0FAE_REG_1_MOD_3
,
1021 PREFIX_0FAE_REG_2_MOD_3
,
1022 PREFIX_0FAE_REG_3_MOD_3
,
1023 PREFIX_0FAE_REG_4_MOD_0
,
1024 PREFIX_0FAE_REG_4_MOD_3
,
1025 PREFIX_0FAE_REG_5_MOD_0
,
1026 PREFIX_0FAE_REG_5_MOD_3
,
1027 PREFIX_0FAE_REG_6_MOD_0
,
1028 PREFIX_0FAE_REG_6_MOD_3
,
1029 PREFIX_0FAE_REG_7_MOD_0
,
1035 PREFIX_0FC7_REG_6_MOD_0
,
1036 PREFIX_0FC7_REG_6_MOD_3
,
1037 PREFIX_0FC7_REG_7_MOD_3
,
1167 PREFIX_VEX_0F71_REG_2
,
1168 PREFIX_VEX_0F71_REG_4
,
1169 PREFIX_VEX_0F71_REG_6
,
1170 PREFIX_VEX_0F72_REG_2
,
1171 PREFIX_VEX_0F72_REG_4
,
1172 PREFIX_VEX_0F72_REG_6
,
1173 PREFIX_VEX_0F73_REG_2
,
1174 PREFIX_VEX_0F73_REG_3
,
1175 PREFIX_VEX_0F73_REG_6
,
1176 PREFIX_VEX_0F73_REG_7
,
1349 PREFIX_VEX_0F38F3_REG_1
,
1350 PREFIX_VEX_0F38F3_REG_2
,
1351 PREFIX_VEX_0F38F3_REG_3
,
1448 PREFIX_EVEX_0F71_REG_2
,
1449 PREFIX_EVEX_0F71_REG_4
,
1450 PREFIX_EVEX_0F71_REG_6
,
1451 PREFIX_EVEX_0F72_REG_0
,
1452 PREFIX_EVEX_0F72_REG_1
,
1453 PREFIX_EVEX_0F72_REG_2
,
1454 PREFIX_EVEX_0F72_REG_4
,
1455 PREFIX_EVEX_0F72_REG_6
,
1456 PREFIX_EVEX_0F73_REG_2
,
1457 PREFIX_EVEX_0F73_REG_3
,
1458 PREFIX_EVEX_0F73_REG_6
,
1459 PREFIX_EVEX_0F73_REG_7
,
1581 PREFIX_EVEX_0F38C6_REG_1
,
1582 PREFIX_EVEX_0F38C6_REG_2
,
1583 PREFIX_EVEX_0F38C6_REG_5
,
1584 PREFIX_EVEX_0F38C6_REG_6
,
1585 PREFIX_EVEX_0F38C7_REG_1
,
1586 PREFIX_EVEX_0F38C7_REG_2
,
1587 PREFIX_EVEX_0F38C7_REG_5
,
1588 PREFIX_EVEX_0F38C7_REG_6
,
1681 THREE_BYTE_0F38
= 0,
1708 VEX_LEN_0F12_P_0_M_0
= 0,
1709 VEX_LEN_0F12_P_0_M_1
,
1710 #define VEX_LEN_0F12_P_2_M_0 VEX_LEN_0F12_P_0_M_0
1712 VEX_LEN_0F16_P_0_M_0
,
1713 VEX_LEN_0F16_P_0_M_1
,
1714 #define VEX_LEN_0F16_P_2_M_0 VEX_LEN_0F16_P_0_M_0
1750 VEX_LEN_0FAE_R_2_M_0
,
1751 VEX_LEN_0FAE_R_3_M_0
,
1758 VEX_LEN_0F381A_P_2_M_0
,
1761 VEX_LEN_0F385A_P_2_M_0
,
1764 VEX_LEN_0F38F3_R_1_P_0
,
1765 VEX_LEN_0F38F3_R_2_P_0
,
1766 VEX_LEN_0F38F3_R_3_P_0
,
1809 VEX_LEN_0FXOP_08_CC
,
1810 VEX_LEN_0FXOP_08_CD
,
1811 VEX_LEN_0FXOP_08_CE
,
1812 VEX_LEN_0FXOP_08_CF
,
1813 VEX_LEN_0FXOP_08_EC
,
1814 VEX_LEN_0FXOP_08_ED
,
1815 VEX_LEN_0FXOP_08_EE
,
1816 VEX_LEN_0FXOP_08_EF
,
1817 VEX_LEN_0FXOP_09_80
,
1823 EVEX_LEN_0F6E_P_2
= 0,
1829 EVEX_LEN_0F3816_P_2
,
1830 EVEX_LEN_0F3819_P_2_W_0
,
1831 EVEX_LEN_0F3819_P_2_W_1
,
1832 EVEX_LEN_0F381A_P_2_W_0_M_0
,
1833 EVEX_LEN_0F381A_P_2_W_1_M_0
,
1834 EVEX_LEN_0F381B_P_2_W_0_M_0
,
1835 EVEX_LEN_0F381B_P_2_W_1_M_0
,
1836 EVEX_LEN_0F3836_P_2
,
1837 EVEX_LEN_0F385A_P_2_W_0_M_0
,
1838 EVEX_LEN_0F385A_P_2_W_1_M_0
,
1839 EVEX_LEN_0F385B_P_2_W_0_M_0
,
1840 EVEX_LEN_0F385B_P_2_W_1_M_0
,
1841 EVEX_LEN_0F38C6_REG_1_PREFIX_2
,
1842 EVEX_LEN_0F38C6_REG_2_PREFIX_2
,
1843 EVEX_LEN_0F38C6_REG_5_PREFIX_2
,
1844 EVEX_LEN_0F38C6_REG_6_PREFIX_2
,
1845 EVEX_LEN_0F38C7_R_1_P_2_W_0
,
1846 EVEX_LEN_0F38C7_R_1_P_2_W_1
,
1847 EVEX_LEN_0F38C7_R_2_P_2_W_0
,
1848 EVEX_LEN_0F38C7_R_2_P_2_W_1
,
1849 EVEX_LEN_0F38C7_R_5_P_2_W_0
,
1850 EVEX_LEN_0F38C7_R_5_P_2_W_1
,
1851 EVEX_LEN_0F38C7_R_6_P_2_W_0
,
1852 EVEX_LEN_0F38C7_R_6_P_2_W_1
,
1853 EVEX_LEN_0F3A00_P_2_W_1
,
1854 EVEX_LEN_0F3A01_P_2_W_1
,
1855 EVEX_LEN_0F3A14_P_2
,
1856 EVEX_LEN_0F3A15_P_2
,
1857 EVEX_LEN_0F3A16_P_2
,
1858 EVEX_LEN_0F3A17_P_2
,
1859 EVEX_LEN_0F3A18_P_2_W_0
,
1860 EVEX_LEN_0F3A18_P_2_W_1
,
1861 EVEX_LEN_0F3A19_P_2_W_0
,
1862 EVEX_LEN_0F3A19_P_2_W_1
,
1863 EVEX_LEN_0F3A1A_P_2_W_0
,
1864 EVEX_LEN_0F3A1A_P_2_W_1
,
1865 EVEX_LEN_0F3A1B_P_2_W_0
,
1866 EVEX_LEN_0F3A1B_P_2_W_1
,
1867 EVEX_LEN_0F3A20_P_2
,
1868 EVEX_LEN_0F3A21_P_2_W_0
,
1869 EVEX_LEN_0F3A22_P_2
,
1870 EVEX_LEN_0F3A23_P_2_W_0
,
1871 EVEX_LEN_0F3A23_P_2_W_1
,
1872 EVEX_LEN_0F3A38_P_2_W_0
,
1873 EVEX_LEN_0F3A38_P_2_W_1
,
1874 EVEX_LEN_0F3A39_P_2_W_0
,
1875 EVEX_LEN_0F3A39_P_2_W_1
,
1876 EVEX_LEN_0F3A3A_P_2_W_0
,
1877 EVEX_LEN_0F3A3A_P_2_W_1
,
1878 EVEX_LEN_0F3A3B_P_2_W_0
,
1879 EVEX_LEN_0F3A3B_P_2_W_1
,
1880 EVEX_LEN_0F3A43_P_2_W_0
,
1881 EVEX_LEN_0F3A43_P_2_W_1
1886 VEX_W_0F41_P_0_LEN_1
= 0,
1887 VEX_W_0F41_P_2_LEN_1
,
1888 VEX_W_0F42_P_0_LEN_1
,
1889 VEX_W_0F42_P_2_LEN_1
,
1890 VEX_W_0F44_P_0_LEN_0
,
1891 VEX_W_0F44_P_2_LEN_0
,
1892 VEX_W_0F45_P_0_LEN_1
,
1893 VEX_W_0F45_P_2_LEN_1
,
1894 VEX_W_0F46_P_0_LEN_1
,
1895 VEX_W_0F46_P_2_LEN_1
,
1896 VEX_W_0F47_P_0_LEN_1
,
1897 VEX_W_0F47_P_2_LEN_1
,
1898 VEX_W_0F4A_P_0_LEN_1
,
1899 VEX_W_0F4A_P_2_LEN_1
,
1900 VEX_W_0F4B_P_0_LEN_1
,
1901 VEX_W_0F4B_P_2_LEN_1
,
1902 VEX_W_0F90_P_0_LEN_0
,
1903 VEX_W_0F90_P_2_LEN_0
,
1904 VEX_W_0F91_P_0_LEN_0
,
1905 VEX_W_0F91_P_2_LEN_0
,
1906 VEX_W_0F92_P_0_LEN_0
,
1907 VEX_W_0F92_P_2_LEN_0
,
1908 VEX_W_0F93_P_0_LEN_0
,
1909 VEX_W_0F93_P_2_LEN_0
,
1910 VEX_W_0F98_P_0_LEN_0
,
1911 VEX_W_0F98_P_2_LEN_0
,
1912 VEX_W_0F99_P_0_LEN_0
,
1913 VEX_W_0F99_P_2_LEN_0
,
1922 VEX_W_0F381A_P_2_M_0
,
1923 VEX_W_0F382C_P_2_M_0
,
1924 VEX_W_0F382D_P_2_M_0
,
1925 VEX_W_0F382E_P_2_M_0
,
1926 VEX_W_0F382F_P_2_M_0
,
1931 VEX_W_0F385A_P_2_M_0
,
1944 VEX_W_0F3A30_P_2_LEN_0
,
1945 VEX_W_0F3A31_P_2_LEN_0
,
1946 VEX_W_0F3A32_P_2_LEN_0
,
1947 VEX_W_0F3A33_P_2_LEN_0
,
1963 EVEX_W_0F12_P_0_M_1
,
1966 EVEX_W_0F16_P_0_M_1
,
2000 EVEX_W_0F72_R_2_P_2
,
2001 EVEX_W_0F72_R_6_P_2
,
2002 EVEX_W_0F73_R_2_P_2
,
2003 EVEX_W_0F73_R_6_P_2
,
2097 EVEX_W_0F38C7_R_1_P_2
,
2098 EVEX_W_0F38C7_R_2_P_2
,
2099 EVEX_W_0F38C7_R_5_P_2
,
2100 EVEX_W_0F38C7_R_6_P_2
,
2127 typedef void (*op_rtn
) (int bytemode
, int sizeflag
);
2136 unsigned int prefix_requirement
;
2139 /* Upper case letters in the instruction names here are macros.
2140 'A' => print 'b' if no register operands or suffix_always is true
2141 'B' => print 'b' if suffix_always is true
2142 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2144 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2145 suffix_always is true
2146 'E' => print 'e' if 32-bit form of jcxz
2147 'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2148 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2149 'H' => print ",pt" or ",pn" branch hint
2152 'K' => print 'd' or 'q' if rex prefix is present.
2153 'L' => print 'l' if suffix_always is true
2154 'M' => print 'r' if intel_mnemonic is false.
2155 'N' => print 'n' if instruction has no wait "prefix"
2156 'O' => print 'd' or 'o' (or 'q' in Intel mode)
2157 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2158 or suffix_always is true. print 'q' if rex prefix is present.
2159 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2161 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2162 'S' => print 'w', 'l' or 'q' if suffix_always is true
2163 'T' => print 'q' in 64bit mode if instruction has no operand size
2164 prefix and behave as 'P' otherwise
2165 'U' => print 'q' in 64bit mode if instruction has no operand size
2166 prefix and behave as 'Q' otherwise
2167 'V' => print 'q' in 64bit mode if instruction has no operand size
2168 prefix and behave as 'S' otherwise
2169 'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2170 'X' => print 's', 'd' depending on data16 prefix (for XMM)
2172 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2173 '!' => change condition from true to false or from false to true.
2174 '%' => add 1 upper case letter to the macro.
2175 '^' => print 'w', 'l', or 'q' (Intel64 ISA only) depending on operand size
2176 prefix or suffix_always is true (lcall/ljmp).
2177 '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending
2178 on operand size prefix.
2179 '&' => print 'q' in 64bit mode for Intel64 ISA or if instruction
2180 has no operand size prefix for AMD64 ISA, behave as 'P'
2183 2 upper case letter macros:
2184 "XY" => print 'x' or 'y' if suffix_always is true or no register
2185 operands and no broadcast.
2186 "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
2187 register operands and no broadcast.
2188 "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2189 "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory
2190 operand or no operand at all in 64bit mode, or if suffix_always
2192 "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2193 "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2194 "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2195 "LW" => print 'd', 'q' depending on the VEX.W bit
2196 "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
2197 an operand size prefix, or suffix_always is true. print
2198 'q' if rex prefix is present.
2200 Many of the above letters print nothing in Intel mode. See "putop"
2203 Braces '{' and '}', and vertical bars '|', indicate alternative
2204 mnemonic strings for AT&T and Intel. */
2206 static const struct dis386 dis386
[] = {
2208 { "addB", { Ebh1
, Gb
}, 0 },
2209 { "addS", { Evh1
, Gv
}, 0 },
2210 { "addB", { Gb
, EbS
}, 0 },
2211 { "addS", { Gv
, EvS
}, 0 },
2212 { "addB", { AL
, Ib
}, 0 },
2213 { "addS", { eAX
, Iv
}, 0 },
2214 { X86_64_TABLE (X86_64_06
) },
2215 { X86_64_TABLE (X86_64_07
) },
2217 { "orB", { Ebh1
, Gb
}, 0 },
2218 { "orS", { Evh1
, Gv
}, 0 },
2219 { "orB", { Gb
, EbS
}, 0 },
2220 { "orS", { Gv
, EvS
}, 0 },
2221 { "orB", { AL
, Ib
}, 0 },
2222 { "orS", { eAX
, Iv
}, 0 },
2223 { X86_64_TABLE (X86_64_0E
) },
2224 { Bad_Opcode
}, /* 0x0f extended opcode escape */
2226 { "adcB", { Ebh1
, Gb
}, 0 },
2227 { "adcS", { Evh1
, Gv
}, 0 },
2228 { "adcB", { Gb
, EbS
}, 0 },
2229 { "adcS", { Gv
, EvS
}, 0 },
2230 { "adcB", { AL
, Ib
}, 0 },
2231 { "adcS", { eAX
, Iv
}, 0 },
2232 { X86_64_TABLE (X86_64_16
) },
2233 { X86_64_TABLE (X86_64_17
) },
2235 { "sbbB", { Ebh1
, Gb
}, 0 },
2236 { "sbbS", { Evh1
, Gv
}, 0 },
2237 { "sbbB", { Gb
, EbS
}, 0 },
2238 { "sbbS", { Gv
, EvS
}, 0 },
2239 { "sbbB", { AL
, Ib
}, 0 },
2240 { "sbbS", { eAX
, Iv
}, 0 },
2241 { X86_64_TABLE (X86_64_1E
) },
2242 { X86_64_TABLE (X86_64_1F
) },
2244 { "andB", { Ebh1
, Gb
}, 0 },
2245 { "andS", { Evh1
, Gv
}, 0 },
2246 { "andB", { Gb
, EbS
}, 0 },
2247 { "andS", { Gv
, EvS
}, 0 },
2248 { "andB", { AL
, Ib
}, 0 },
2249 { "andS", { eAX
, Iv
}, 0 },
2250 { Bad_Opcode
}, /* SEG ES prefix */
2251 { X86_64_TABLE (X86_64_27
) },
2253 { "subB", { Ebh1
, Gb
}, 0 },
2254 { "subS", { Evh1
, Gv
}, 0 },
2255 { "subB", { Gb
, EbS
}, 0 },
2256 { "subS", { Gv
, EvS
}, 0 },
2257 { "subB", { AL
, Ib
}, 0 },
2258 { "subS", { eAX
, Iv
}, 0 },
2259 { Bad_Opcode
}, /* SEG CS prefix */
2260 { X86_64_TABLE (X86_64_2F
) },
2262 { "xorB", { Ebh1
, Gb
}, 0 },
2263 { "xorS", { Evh1
, Gv
}, 0 },
2264 { "xorB", { Gb
, EbS
}, 0 },
2265 { "xorS", { Gv
, EvS
}, 0 },
2266 { "xorB", { AL
, Ib
}, 0 },
2267 { "xorS", { eAX
, Iv
}, 0 },
2268 { Bad_Opcode
}, /* SEG SS prefix */
2269 { X86_64_TABLE (X86_64_37
) },
2271 { "cmpB", { Eb
, Gb
}, 0 },
2272 { "cmpS", { Ev
, Gv
}, 0 },
2273 { "cmpB", { Gb
, EbS
}, 0 },
2274 { "cmpS", { Gv
, EvS
}, 0 },
2275 { "cmpB", { AL
, Ib
}, 0 },
2276 { "cmpS", { eAX
, Iv
}, 0 },
2277 { Bad_Opcode
}, /* SEG DS prefix */
2278 { X86_64_TABLE (X86_64_3F
) },
2280 { "inc{S|}", { RMeAX
}, 0 },
2281 { "inc{S|}", { RMeCX
}, 0 },
2282 { "inc{S|}", { RMeDX
}, 0 },
2283 { "inc{S|}", { RMeBX
}, 0 },
2284 { "inc{S|}", { RMeSP
}, 0 },
2285 { "inc{S|}", { RMeBP
}, 0 },
2286 { "inc{S|}", { RMeSI
}, 0 },
2287 { "inc{S|}", { RMeDI
}, 0 },
2289 { "dec{S|}", { RMeAX
}, 0 },
2290 { "dec{S|}", { RMeCX
}, 0 },
2291 { "dec{S|}", { RMeDX
}, 0 },
2292 { "dec{S|}", { RMeBX
}, 0 },
2293 { "dec{S|}", { RMeSP
}, 0 },
2294 { "dec{S|}", { RMeBP
}, 0 },
2295 { "dec{S|}", { RMeSI
}, 0 },
2296 { "dec{S|}", { RMeDI
}, 0 },
2298 { "pushV", { RMrAX
}, 0 },
2299 { "pushV", { RMrCX
}, 0 },
2300 { "pushV", { RMrDX
}, 0 },
2301 { "pushV", { RMrBX
}, 0 },
2302 { "pushV", { RMrSP
}, 0 },
2303 { "pushV", { RMrBP
}, 0 },
2304 { "pushV", { RMrSI
}, 0 },
2305 { "pushV", { RMrDI
}, 0 },
2307 { "popV", { RMrAX
}, 0 },
2308 { "popV", { RMrCX
}, 0 },
2309 { "popV", { RMrDX
}, 0 },
2310 { "popV", { RMrBX
}, 0 },
2311 { "popV", { RMrSP
}, 0 },
2312 { "popV", { RMrBP
}, 0 },
2313 { "popV", { RMrSI
}, 0 },
2314 { "popV", { RMrDI
}, 0 },
2316 { X86_64_TABLE (X86_64_60
) },
2317 { X86_64_TABLE (X86_64_61
) },
2318 { X86_64_TABLE (X86_64_62
) },
2319 { X86_64_TABLE (X86_64_63
) },
2320 { Bad_Opcode
}, /* seg fs */
2321 { Bad_Opcode
}, /* seg gs */
2322 { Bad_Opcode
}, /* op size prefix */
2323 { Bad_Opcode
}, /* adr size prefix */
2325 { "pushT", { sIv
}, 0 },
2326 { "imulS", { Gv
, Ev
, Iv
}, 0 },
2327 { "pushT", { sIbT
}, 0 },
2328 { "imulS", { Gv
, Ev
, sIb
}, 0 },
2329 { "ins{b|}", { Ybr
, indirDX
}, 0 },
2330 { X86_64_TABLE (X86_64_6D
) },
2331 { "outs{b|}", { indirDXr
, Xb
}, 0 },
2332 { X86_64_TABLE (X86_64_6F
) },
2334 { "joH", { Jb
, BND
, cond_jump_flag
}, 0 },
2335 { "jnoH", { Jb
, BND
, cond_jump_flag
}, 0 },
2336 { "jbH", { Jb
, BND
, cond_jump_flag
}, 0 },
2337 { "jaeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2338 { "jeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2339 { "jneH", { Jb
, BND
, cond_jump_flag
}, 0 },
2340 { "jbeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2341 { "jaH", { Jb
, BND
, cond_jump_flag
}, 0 },
2343 { "jsH", { Jb
, BND
, cond_jump_flag
}, 0 },
2344 { "jnsH", { Jb
, BND
, cond_jump_flag
}, 0 },
2345 { "jpH", { Jb
, BND
, cond_jump_flag
}, 0 },
2346 { "jnpH", { Jb
, BND
, cond_jump_flag
}, 0 },
2347 { "jlH", { Jb
, BND
, cond_jump_flag
}, 0 },
2348 { "jgeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2349 { "jleH", { Jb
, BND
, cond_jump_flag
}, 0 },
2350 { "jgH", { Jb
, BND
, cond_jump_flag
}, 0 },
2352 { REG_TABLE (REG_80
) },
2353 { REG_TABLE (REG_81
) },
2354 { X86_64_TABLE (X86_64_82
) },
2355 { REG_TABLE (REG_83
) },
2356 { "testB", { Eb
, Gb
}, 0 },
2357 { "testS", { Ev
, Gv
}, 0 },
2358 { "xchgB", { Ebh2
, Gb
}, 0 },
2359 { "xchgS", { Evh2
, Gv
}, 0 },
2361 { "movB", { Ebh3
, Gb
}, 0 },
2362 { "movS", { Evh3
, Gv
}, 0 },
2363 { "movB", { Gb
, EbS
}, 0 },
2364 { "movS", { Gv
, EvS
}, 0 },
2365 { "movD", { Sv
, Sw
}, 0 },
2366 { MOD_TABLE (MOD_8D
) },
2367 { "movD", { Sw
, Sv
}, 0 },
2368 { REG_TABLE (REG_8F
) },
2370 { PREFIX_TABLE (PREFIX_90
) },
2371 { "xchgS", { RMeCX
, eAX
}, 0 },
2372 { "xchgS", { RMeDX
, eAX
}, 0 },
2373 { "xchgS", { RMeBX
, eAX
}, 0 },
2374 { "xchgS", { RMeSP
, eAX
}, 0 },
2375 { "xchgS", { RMeBP
, eAX
}, 0 },
2376 { "xchgS", { RMeSI
, eAX
}, 0 },
2377 { "xchgS", { RMeDI
, eAX
}, 0 },
2379 { "cW{t|}R", { XX
}, 0 },
2380 { "cR{t|}O", { XX
}, 0 },
2381 { X86_64_TABLE (X86_64_9A
) },
2382 { Bad_Opcode
}, /* fwait */
2383 { "pushfT", { XX
}, 0 },
2384 { "popfT", { XX
}, 0 },
2385 { "sahf", { XX
}, 0 },
2386 { "lahf", { XX
}, 0 },
2388 { "mov%LB", { AL
, Ob
}, 0 },
2389 { "mov%LS", { eAX
, Ov
}, 0 },
2390 { "mov%LB", { Ob
, AL
}, 0 },
2391 { "mov%LS", { Ov
, eAX
}, 0 },
2392 { "movs{b|}", { Ybr
, Xb
}, 0 },
2393 { "movs{R|}", { Yvr
, Xv
}, 0 },
2394 { "cmps{b|}", { Xb
, Yb
}, 0 },
2395 { "cmps{R|}", { Xv
, Yv
}, 0 },
2397 { "testB", { AL
, Ib
}, 0 },
2398 { "testS", { eAX
, Iv
}, 0 },
2399 { "stosB", { Ybr
, AL
}, 0 },
2400 { "stosS", { Yvr
, eAX
}, 0 },
2401 { "lodsB", { ALr
, Xb
}, 0 },
2402 { "lodsS", { eAXr
, Xv
}, 0 },
2403 { "scasB", { AL
, Yb
}, 0 },
2404 { "scasS", { eAX
, Yv
}, 0 },
2406 { "movB", { RMAL
, Ib
}, 0 },
2407 { "movB", { RMCL
, Ib
}, 0 },
2408 { "movB", { RMDL
, Ib
}, 0 },
2409 { "movB", { RMBL
, Ib
}, 0 },
2410 { "movB", { RMAH
, Ib
}, 0 },
2411 { "movB", { RMCH
, Ib
}, 0 },
2412 { "movB", { RMDH
, Ib
}, 0 },
2413 { "movB", { RMBH
, Ib
}, 0 },
2415 { "mov%LV", { RMeAX
, Iv64
}, 0 },
2416 { "mov%LV", { RMeCX
, Iv64
}, 0 },
2417 { "mov%LV", { RMeDX
, Iv64
}, 0 },
2418 { "mov%LV", { RMeBX
, Iv64
}, 0 },
2419 { "mov%LV", { RMeSP
, Iv64
}, 0 },
2420 { "mov%LV", { RMeBP
, Iv64
}, 0 },
2421 { "mov%LV", { RMeSI
, Iv64
}, 0 },
2422 { "mov%LV", { RMeDI
, Iv64
}, 0 },
2424 { REG_TABLE (REG_C0
) },
2425 { REG_TABLE (REG_C1
) },
2426 { X86_64_TABLE (X86_64_C2
) },
2427 { X86_64_TABLE (X86_64_C3
) },
2428 { X86_64_TABLE (X86_64_C4
) },
2429 { X86_64_TABLE (X86_64_C5
) },
2430 { REG_TABLE (REG_C6
) },
2431 { REG_TABLE (REG_C7
) },
2433 { "enterT", { Iw
, Ib
}, 0 },
2434 { "leaveT", { XX
}, 0 },
2435 { "{l|}ret{|f}P", { Iw
}, 0 },
2436 { "{l|}ret{|f}P", { XX
}, 0 },
2437 { "int3", { XX
}, 0 },
2438 { "int", { Ib
}, 0 },
2439 { X86_64_TABLE (X86_64_CE
) },
2440 { "iret%LP", { XX
}, 0 },
2442 { REG_TABLE (REG_D0
) },
2443 { REG_TABLE (REG_D1
) },
2444 { REG_TABLE (REG_D2
) },
2445 { REG_TABLE (REG_D3
) },
2446 { X86_64_TABLE (X86_64_D4
) },
2447 { X86_64_TABLE (X86_64_D5
) },
2449 { "xlat", { DSBX
}, 0 },
2460 { "loopneFH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2461 { "loopeFH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2462 { "loopFH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2463 { "jEcxzH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2464 { "inB", { AL
, Ib
}, 0 },
2465 { "inG", { zAX
, Ib
}, 0 },
2466 { "outB", { Ib
, AL
}, 0 },
2467 { "outG", { Ib
, zAX
}, 0 },
2469 { X86_64_TABLE (X86_64_E8
) },
2470 { X86_64_TABLE (X86_64_E9
) },
2471 { X86_64_TABLE (X86_64_EA
) },
2472 { "jmp", { Jb
, BND
}, 0 },
2473 { "inB", { AL
, indirDX
}, 0 },
2474 { "inG", { zAX
, indirDX
}, 0 },
2475 { "outB", { indirDX
, AL
}, 0 },
2476 { "outG", { indirDX
, zAX
}, 0 },
2478 { Bad_Opcode
}, /* lock prefix */
2479 { "icebp", { XX
}, 0 },
2480 { Bad_Opcode
}, /* repne */
2481 { Bad_Opcode
}, /* repz */
2482 { "hlt", { XX
}, 0 },
2483 { "cmc", { XX
}, 0 },
2484 { REG_TABLE (REG_F6
) },
2485 { REG_TABLE (REG_F7
) },
2487 { "clc", { XX
}, 0 },
2488 { "stc", { XX
}, 0 },
2489 { "cli", { XX
}, 0 },
2490 { "sti", { XX
}, 0 },
2491 { "cld", { XX
}, 0 },
2492 { "std", { XX
}, 0 },
2493 { REG_TABLE (REG_FE
) },
2494 { REG_TABLE (REG_FF
) },
2497 static const struct dis386 dis386_twobyte
[] = {
2499 { REG_TABLE (REG_0F00
) },
2500 { REG_TABLE (REG_0F01
) },
2501 { "larS", { Gv
, Ew
}, 0 },
2502 { "lslS", { Gv
, Ew
}, 0 },
2504 { "syscall", { XX
}, 0 },
2505 { "clts", { XX
}, 0 },
2506 { "sysret%LQ", { XX
}, 0 },
2508 { "invd", { XX
}, 0 },
2509 { PREFIX_TABLE (PREFIX_0F09
) },
2511 { "ud2", { XX
}, 0 },
2513 { REG_TABLE (REG_0F0D
) },
2514 { "femms", { XX
}, 0 },
2515 { "", { MX
, EM
, OPSUF
}, 0 }, /* See OP_3DNowSuffix. */
2517 { PREFIX_TABLE (PREFIX_0F10
) },
2518 { PREFIX_TABLE (PREFIX_0F11
) },
2519 { PREFIX_TABLE (PREFIX_0F12
) },
2520 { MOD_TABLE (MOD_0F13
) },
2521 { "unpcklpX", { XM
, EXx
}, PREFIX_OPCODE
},
2522 { "unpckhpX", { XM
, EXx
}, PREFIX_OPCODE
},
2523 { PREFIX_TABLE (PREFIX_0F16
) },
2524 { MOD_TABLE (MOD_0F17
) },
2526 { REG_TABLE (REG_0F18
) },
2527 { "nopQ", { Ev
}, 0 },
2528 { PREFIX_TABLE (PREFIX_0F1A
) },
2529 { PREFIX_TABLE (PREFIX_0F1B
) },
2530 { PREFIX_TABLE (PREFIX_0F1C
) },
2531 { "nopQ", { Ev
}, 0 },
2532 { PREFIX_TABLE (PREFIX_0F1E
) },
2533 { "nopQ", { Ev
}, 0 },
2535 { "movZ", { Rm
, Cm
}, 0 },
2536 { "movZ", { Rm
, Dm
}, 0 },
2537 { "movZ", { Cm
, Rm
}, 0 },
2538 { "movZ", { Dm
, Rm
}, 0 },
2539 { MOD_TABLE (MOD_0F24
) },
2541 { MOD_TABLE (MOD_0F26
) },
2544 { "movapX", { XM
, EXx
}, PREFIX_OPCODE
},
2545 { "movapX", { EXxS
, XM
}, PREFIX_OPCODE
},
2546 { PREFIX_TABLE (PREFIX_0F2A
) },
2547 { PREFIX_TABLE (PREFIX_0F2B
) },
2548 { PREFIX_TABLE (PREFIX_0F2C
) },
2549 { PREFIX_TABLE (PREFIX_0F2D
) },
2550 { PREFIX_TABLE (PREFIX_0F2E
) },
2551 { PREFIX_TABLE (PREFIX_0F2F
) },
2553 { "wrmsr", { XX
}, 0 },
2554 { "rdtsc", { XX
}, 0 },
2555 { "rdmsr", { XX
}, 0 },
2556 { "rdpmc", { XX
}, 0 },
2557 { "sysenter", { SEP
}, 0 },
2558 { "sysexit", { SEP
}, 0 },
2560 { "getsec", { XX
}, 0 },
2562 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38
, PREFIX_OPCODE
) },
2564 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A
, PREFIX_OPCODE
) },
2571 { "cmovoS", { Gv
, Ev
}, 0 },
2572 { "cmovnoS", { Gv
, Ev
}, 0 },
2573 { "cmovbS", { Gv
, Ev
}, 0 },
2574 { "cmovaeS", { Gv
, Ev
}, 0 },
2575 { "cmoveS", { Gv
, Ev
}, 0 },
2576 { "cmovneS", { Gv
, Ev
}, 0 },
2577 { "cmovbeS", { Gv
, Ev
}, 0 },
2578 { "cmovaS", { Gv
, Ev
}, 0 },
2580 { "cmovsS", { Gv
, Ev
}, 0 },
2581 { "cmovnsS", { Gv
, Ev
}, 0 },
2582 { "cmovpS", { Gv
, Ev
}, 0 },
2583 { "cmovnpS", { Gv
, Ev
}, 0 },
2584 { "cmovlS", { Gv
, Ev
}, 0 },
2585 { "cmovgeS", { Gv
, Ev
}, 0 },
2586 { "cmovleS", { Gv
, Ev
}, 0 },
2587 { "cmovgS", { Gv
, Ev
}, 0 },
2589 { MOD_TABLE (MOD_0F50
) },
2590 { PREFIX_TABLE (PREFIX_0F51
) },
2591 { PREFIX_TABLE (PREFIX_0F52
) },
2592 { PREFIX_TABLE (PREFIX_0F53
) },
2593 { "andpX", { XM
, EXx
}, PREFIX_OPCODE
},
2594 { "andnpX", { XM
, EXx
}, PREFIX_OPCODE
},
2595 { "orpX", { XM
, EXx
}, PREFIX_OPCODE
},
2596 { "xorpX", { XM
, EXx
}, PREFIX_OPCODE
},
2598 { PREFIX_TABLE (PREFIX_0F58
) },
2599 { PREFIX_TABLE (PREFIX_0F59
) },
2600 { PREFIX_TABLE (PREFIX_0F5A
) },
2601 { PREFIX_TABLE (PREFIX_0F5B
) },
2602 { PREFIX_TABLE (PREFIX_0F5C
) },
2603 { PREFIX_TABLE (PREFIX_0F5D
) },
2604 { PREFIX_TABLE (PREFIX_0F5E
) },
2605 { PREFIX_TABLE (PREFIX_0F5F
) },
2607 { PREFIX_TABLE (PREFIX_0F60
) },
2608 { PREFIX_TABLE (PREFIX_0F61
) },
2609 { PREFIX_TABLE (PREFIX_0F62
) },
2610 { "packsswb", { MX
, EM
}, PREFIX_OPCODE
},
2611 { "pcmpgtb", { MX
, EM
}, PREFIX_OPCODE
},
2612 { "pcmpgtw", { MX
, EM
}, PREFIX_OPCODE
},
2613 { "pcmpgtd", { MX
, EM
}, PREFIX_OPCODE
},
2614 { "packuswb", { MX
, EM
}, PREFIX_OPCODE
},
2616 { "punpckhbw", { MX
, EM
}, PREFIX_OPCODE
},
2617 { "punpckhwd", { MX
, EM
}, PREFIX_OPCODE
},
2618 { "punpckhdq", { MX
, EM
}, PREFIX_OPCODE
},
2619 { "packssdw", { MX
, EM
}, PREFIX_OPCODE
},
2620 { PREFIX_TABLE (PREFIX_0F6C
) },
2621 { PREFIX_TABLE (PREFIX_0F6D
) },
2622 { "movK", { MX
, Edq
}, PREFIX_OPCODE
},
2623 { PREFIX_TABLE (PREFIX_0F6F
) },
2625 { PREFIX_TABLE (PREFIX_0F70
) },
2626 { REG_TABLE (REG_0F71
) },
2627 { REG_TABLE (REG_0F72
) },
2628 { REG_TABLE (REG_0F73
) },
2629 { "pcmpeqb", { MX
, EM
}, PREFIX_OPCODE
},
2630 { "pcmpeqw", { MX
, EM
}, PREFIX_OPCODE
},
2631 { "pcmpeqd", { MX
, EM
}, PREFIX_OPCODE
},
2632 { "emms", { XX
}, PREFIX_OPCODE
},
2634 { PREFIX_TABLE (PREFIX_0F78
) },
2635 { PREFIX_TABLE (PREFIX_0F79
) },
2638 { PREFIX_TABLE (PREFIX_0F7C
) },
2639 { PREFIX_TABLE (PREFIX_0F7D
) },
2640 { PREFIX_TABLE (PREFIX_0F7E
) },
2641 { PREFIX_TABLE (PREFIX_0F7F
) },
2643 { "joH", { Jv
, BND
, cond_jump_flag
}, 0 },
2644 { "jnoH", { Jv
, BND
, cond_jump_flag
}, 0 },
2645 { "jbH", { Jv
, BND
, cond_jump_flag
}, 0 },
2646 { "jaeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2647 { "jeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2648 { "jneH", { Jv
, BND
, cond_jump_flag
}, 0 },
2649 { "jbeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2650 { "jaH", { Jv
, BND
, cond_jump_flag
}, 0 },
2652 { "jsH", { Jv
, BND
, cond_jump_flag
}, 0 },
2653 { "jnsH", { Jv
, BND
, cond_jump_flag
}, 0 },
2654 { "jpH", { Jv
, BND
, cond_jump_flag
}, 0 },
2655 { "jnpH", { Jv
, BND
, cond_jump_flag
}, 0 },
2656 { "jlH", { Jv
, BND
, cond_jump_flag
}, 0 },
2657 { "jgeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2658 { "jleH", { Jv
, BND
, cond_jump_flag
}, 0 },
2659 { "jgH", { Jv
, BND
, cond_jump_flag
}, 0 },
2661 { "seto", { Eb
}, 0 },
2662 { "setno", { Eb
}, 0 },
2663 { "setb", { Eb
}, 0 },
2664 { "setae", { Eb
}, 0 },
2665 { "sete", { Eb
}, 0 },
2666 { "setne", { Eb
}, 0 },
2667 { "setbe", { Eb
}, 0 },
2668 { "seta", { Eb
}, 0 },
2670 { "sets", { Eb
}, 0 },
2671 { "setns", { Eb
}, 0 },
2672 { "setp", { Eb
}, 0 },
2673 { "setnp", { Eb
}, 0 },
2674 { "setl", { Eb
}, 0 },
2675 { "setge", { Eb
}, 0 },
2676 { "setle", { Eb
}, 0 },
2677 { "setg", { Eb
}, 0 },
2679 { "pushT", { fs
}, 0 },
2680 { "popT", { fs
}, 0 },
2681 { "cpuid", { XX
}, 0 },
2682 { "btS", { Ev
, Gv
}, 0 },
2683 { "shldS", { Ev
, Gv
, Ib
}, 0 },
2684 { "shldS", { Ev
, Gv
, CL
}, 0 },
2685 { REG_TABLE (REG_0FA6
) },
2686 { REG_TABLE (REG_0FA7
) },
2688 { "pushT", { gs
}, 0 },
2689 { "popT", { gs
}, 0 },
2690 { "rsm", { XX
}, 0 },
2691 { "btsS", { Evh1
, Gv
}, 0 },
2692 { "shrdS", { Ev
, Gv
, Ib
}, 0 },
2693 { "shrdS", { Ev
, Gv
, CL
}, 0 },
2694 { REG_TABLE (REG_0FAE
) },
2695 { "imulS", { Gv
, Ev
}, 0 },
2697 { "cmpxchgB", { Ebh1
, Gb
}, 0 },
2698 { "cmpxchgS", { Evh1
, Gv
}, 0 },
2699 { MOD_TABLE (MOD_0FB2
) },
2700 { "btrS", { Evh1
, Gv
}, 0 },
2701 { MOD_TABLE (MOD_0FB4
) },
2702 { MOD_TABLE (MOD_0FB5
) },
2703 { "movz{bR|x}", { Gv
, Eb
}, 0 },
2704 { "movz{wR|x}", { Gv
, Ew
}, 0 }, /* yes, there really is movzww ! */
2706 { PREFIX_TABLE (PREFIX_0FB8
) },
2707 { "ud1S", { Gv
, Ev
}, 0 },
2708 { REG_TABLE (REG_0FBA
) },
2709 { "btcS", { Evh1
, Gv
}, 0 },
2710 { PREFIX_TABLE (PREFIX_0FBC
) },
2711 { PREFIX_TABLE (PREFIX_0FBD
) },
2712 { "movs{bR|x}", { Gv
, Eb
}, 0 },
2713 { "movs{wR|x}", { Gv
, Ew
}, 0 }, /* yes, there really is movsww ! */
2715 { "xaddB", { Ebh1
, Gb
}, 0 },
2716 { "xaddS", { Evh1
, Gv
}, 0 },
2717 { PREFIX_TABLE (PREFIX_0FC2
) },
2718 { MOD_TABLE (MOD_0FC3
) },
2719 { "pinsrw", { MX
, Edqw
, Ib
}, PREFIX_OPCODE
},
2720 { "pextrw", { Gdq
, MS
, Ib
}, PREFIX_OPCODE
},
2721 { "shufpX", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
2722 { REG_TABLE (REG_0FC7
) },
2724 { "bswap", { RMeAX
}, 0 },
2725 { "bswap", { RMeCX
}, 0 },
2726 { "bswap", { RMeDX
}, 0 },
2727 { "bswap", { RMeBX
}, 0 },
2728 { "bswap", { RMeSP
}, 0 },
2729 { "bswap", { RMeBP
}, 0 },
2730 { "bswap", { RMeSI
}, 0 },
2731 { "bswap", { RMeDI
}, 0 },
2733 { PREFIX_TABLE (PREFIX_0FD0
) },
2734 { "psrlw", { MX
, EM
}, PREFIX_OPCODE
},
2735 { "psrld", { MX
, EM
}, PREFIX_OPCODE
},
2736 { "psrlq", { MX
, EM
}, PREFIX_OPCODE
},
2737 { "paddq", { MX
, EM
}, PREFIX_OPCODE
},
2738 { "pmullw", { MX
, EM
}, PREFIX_OPCODE
},
2739 { PREFIX_TABLE (PREFIX_0FD6
) },
2740 { MOD_TABLE (MOD_0FD7
) },
2742 { "psubusb", { MX
, EM
}, PREFIX_OPCODE
},
2743 { "psubusw", { MX
, EM
}, PREFIX_OPCODE
},
2744 { "pminub", { MX
, EM
}, PREFIX_OPCODE
},
2745 { "pand", { MX
, EM
}, PREFIX_OPCODE
},
2746 { "paddusb", { MX
, EM
}, PREFIX_OPCODE
},
2747 { "paddusw", { MX
, EM
}, PREFIX_OPCODE
},
2748 { "pmaxub", { MX
, EM
}, PREFIX_OPCODE
},
2749 { "pandn", { MX
, EM
}, PREFIX_OPCODE
},
2751 { "pavgb", { MX
, EM
}, PREFIX_OPCODE
},
2752 { "psraw", { MX
, EM
}, PREFIX_OPCODE
},
2753 { "psrad", { MX
, EM
}, PREFIX_OPCODE
},
2754 { "pavgw", { MX
, EM
}, PREFIX_OPCODE
},
2755 { "pmulhuw", { MX
, EM
}, PREFIX_OPCODE
},
2756 { "pmulhw", { MX
, EM
}, PREFIX_OPCODE
},
2757 { PREFIX_TABLE (PREFIX_0FE6
) },
2758 { PREFIX_TABLE (PREFIX_0FE7
) },
2760 { "psubsb", { MX
, EM
}, PREFIX_OPCODE
},
2761 { "psubsw", { MX
, EM
}, PREFIX_OPCODE
},
2762 { "pminsw", { MX
, EM
}, PREFIX_OPCODE
},
2763 { "por", { MX
, EM
}, PREFIX_OPCODE
},
2764 { "paddsb", { MX
, EM
}, PREFIX_OPCODE
},
2765 { "paddsw", { MX
, EM
}, PREFIX_OPCODE
},
2766 { "pmaxsw", { MX
, EM
}, PREFIX_OPCODE
},
2767 { "pxor", { MX
, EM
}, PREFIX_OPCODE
},
2769 { PREFIX_TABLE (PREFIX_0FF0
) },
2770 { "psllw", { MX
, EM
}, PREFIX_OPCODE
},
2771 { "pslld", { MX
, EM
}, PREFIX_OPCODE
},
2772 { "psllq", { MX
, EM
}, PREFIX_OPCODE
},
2773 { "pmuludq", { MX
, EM
}, PREFIX_OPCODE
},
2774 { "pmaddwd", { MX
, EM
}, PREFIX_OPCODE
},
2775 { "psadbw", { MX
, EM
}, PREFIX_OPCODE
},
2776 { PREFIX_TABLE (PREFIX_0FF7
) },
2778 { "psubb", { MX
, EM
}, PREFIX_OPCODE
},
2779 { "psubw", { MX
, EM
}, PREFIX_OPCODE
},
2780 { "psubd", { MX
, EM
}, PREFIX_OPCODE
},
2781 { "psubq", { MX
, EM
}, PREFIX_OPCODE
},
2782 { "paddb", { MX
, EM
}, PREFIX_OPCODE
},
2783 { "paddw", { MX
, EM
}, PREFIX_OPCODE
},
2784 { "paddd", { MX
, EM
}, PREFIX_OPCODE
},
2785 { "ud0S", { Gv
, Ev
}, 0 },
2788 static const unsigned char onebyte_has_modrm
[256] = {
2789 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2790 /* ------------------------------- */
2791 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2792 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2793 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2794 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2795 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2796 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2797 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2798 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2799 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2800 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2801 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2802 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2803 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2804 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2805 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2806 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
2807 /* ------------------------------- */
2808 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2811 static const unsigned char twobyte_has_modrm
[256] = {
2812 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2813 /* ------------------------------- */
2814 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2815 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2816 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2817 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2818 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2819 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2820 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2821 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2822 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2823 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2824 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2825 /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */
2826 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2827 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2828 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2829 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1 /* ff */
2830 /* ------------------------------- */
2831 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2834 static char obuf
[100];
2836 static char *mnemonicendp
;
2837 static char scratchbuf
[100];
2838 static unsigned char *start_codep
;
2839 static unsigned char *insn_codep
;
2840 static unsigned char *codep
;
2841 static unsigned char *end_codep
;
2842 static int last_lock_prefix
;
2843 static int last_repz_prefix
;
2844 static int last_repnz_prefix
;
2845 static int last_data_prefix
;
2846 static int last_addr_prefix
;
2847 static int last_rex_prefix
;
2848 static int last_seg_prefix
;
2849 static int fwait_prefix
;
2850 /* The active segment register prefix. */
2851 static int active_seg_prefix
;
2852 #define MAX_CODE_LENGTH 15
2853 /* We can up to 14 prefixes since the maximum instruction length is
2855 static int all_prefixes
[MAX_CODE_LENGTH
- 1];
2856 static disassemble_info
*the_info
;
2864 static unsigned char need_modrm
;
2874 int register_specifier
;
2881 int mask_register_specifier
;
2887 static unsigned char need_vex
;
2888 static unsigned char need_vex_reg
;
2889 static unsigned char vex_w_done
;
2897 /* If we are accessing mod/rm/reg without need_modrm set, then the
2898 values are stale. Hitting this abort likely indicates that you
2899 need to update onebyte_has_modrm or twobyte_has_modrm. */
2900 #define MODRM_CHECK if (!need_modrm) abort ()
2902 static const char **names64
;
2903 static const char **names32
;
2904 static const char **names16
;
2905 static const char **names8
;
2906 static const char **names8rex
;
2907 static const char **names_seg
;
2908 static const char *index64
;
2909 static const char *index32
;
2910 static const char **index16
;
2911 static const char **names_bnd
;
2913 static const char *intel_names64
[] = {
2914 "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
2915 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
2917 static const char *intel_names32
[] = {
2918 "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
2919 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
2921 static const char *intel_names16
[] = {
2922 "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
2923 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
2925 static const char *intel_names8
[] = {
2926 "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
2928 static const char *intel_names8rex
[] = {
2929 "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
2930 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
2932 static const char *intel_names_seg
[] = {
2933 "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
2935 static const char *intel_index64
= "riz";
2936 static const char *intel_index32
= "eiz";
2937 static const char *intel_index16
[] = {
2938 "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
2941 static const char *att_names64
[] = {
2942 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
2943 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
2945 static const char *att_names32
[] = {
2946 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
2947 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
2949 static const char *att_names16
[] = {
2950 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
2951 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
2953 static const char *att_names8
[] = {
2954 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
2956 static const char *att_names8rex
[] = {
2957 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
2958 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
2960 static const char *att_names_seg
[] = {
2961 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
2963 static const char *att_index64
= "%riz";
2964 static const char *att_index32
= "%eiz";
2965 static const char *att_index16
[] = {
2966 "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
2969 static const char **names_mm
;
2970 static const char *intel_names_mm
[] = {
2971 "mm0", "mm1", "mm2", "mm3",
2972 "mm4", "mm5", "mm6", "mm7"
2974 static const char *att_names_mm
[] = {
2975 "%mm0", "%mm1", "%mm2", "%mm3",
2976 "%mm4", "%mm5", "%mm6", "%mm7"
2979 static const char *intel_names_bnd
[] = {
2980 "bnd0", "bnd1", "bnd2", "bnd3"
2983 static const char *att_names_bnd
[] = {
2984 "%bnd0", "%bnd1", "%bnd2", "%bnd3"
2987 static const char **names_xmm
;
2988 static const char *intel_names_xmm
[] = {
2989 "xmm0", "xmm1", "xmm2", "xmm3",
2990 "xmm4", "xmm5", "xmm6", "xmm7",
2991 "xmm8", "xmm9", "xmm10", "xmm11",
2992 "xmm12", "xmm13", "xmm14", "xmm15",
2993 "xmm16", "xmm17", "xmm18", "xmm19",
2994 "xmm20", "xmm21", "xmm22", "xmm23",
2995 "xmm24", "xmm25", "xmm26", "xmm27",
2996 "xmm28", "xmm29", "xmm30", "xmm31"
2998 static const char *att_names_xmm
[] = {
2999 "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3000 "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3001 "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3002 "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3003 "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3004 "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3005 "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3006 "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3009 static const char **names_ymm
;
3010 static const char *intel_names_ymm
[] = {
3011 "ymm0", "ymm1", "ymm2", "ymm3",
3012 "ymm4", "ymm5", "ymm6", "ymm7",
3013 "ymm8", "ymm9", "ymm10", "ymm11",
3014 "ymm12", "ymm13", "ymm14", "ymm15",
3015 "ymm16", "ymm17", "ymm18", "ymm19",
3016 "ymm20", "ymm21", "ymm22", "ymm23",
3017 "ymm24", "ymm25", "ymm26", "ymm27",
3018 "ymm28", "ymm29", "ymm30", "ymm31"
3020 static const char *att_names_ymm
[] = {
3021 "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3022 "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3023 "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3024 "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3025 "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3026 "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3027 "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3028 "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3031 static const char **names_zmm
;
3032 static const char *intel_names_zmm
[] = {
3033 "zmm0", "zmm1", "zmm2", "zmm3",
3034 "zmm4", "zmm5", "zmm6", "zmm7",
3035 "zmm8", "zmm9", "zmm10", "zmm11",
3036 "zmm12", "zmm13", "zmm14", "zmm15",
3037 "zmm16", "zmm17", "zmm18", "zmm19",
3038 "zmm20", "zmm21", "zmm22", "zmm23",
3039 "zmm24", "zmm25", "zmm26", "zmm27",
3040 "zmm28", "zmm29", "zmm30", "zmm31"
3042 static const char *att_names_zmm
[] = {
3043 "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3044 "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3045 "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3046 "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3047 "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3048 "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3049 "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3050 "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3053 static const char **names_mask
;
3054 static const char *intel_names_mask
[] = {
3055 "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3057 static const char *att_names_mask
[] = {
3058 "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3061 static const char *names_rounding
[] =
3069 static const struct dis386 reg_table
[][8] = {
3072 { "addA", { Ebh1
, Ib
}, 0 },
3073 { "orA", { Ebh1
, Ib
}, 0 },
3074 { "adcA", { Ebh1
, Ib
}, 0 },
3075 { "sbbA", { Ebh1
, Ib
}, 0 },
3076 { "andA", { Ebh1
, Ib
}, 0 },
3077 { "subA", { Ebh1
, Ib
}, 0 },
3078 { "xorA", { Ebh1
, Ib
}, 0 },
3079 { "cmpA", { Eb
, Ib
}, 0 },
3083 { "addQ", { Evh1
, Iv
}, 0 },
3084 { "orQ", { Evh1
, Iv
}, 0 },
3085 { "adcQ", { Evh1
, Iv
}, 0 },
3086 { "sbbQ", { Evh1
, Iv
}, 0 },
3087 { "andQ", { Evh1
, Iv
}, 0 },
3088 { "subQ", { Evh1
, Iv
}, 0 },
3089 { "xorQ", { Evh1
, Iv
}, 0 },
3090 { "cmpQ", { Ev
, Iv
}, 0 },
3094 { "addQ", { Evh1
, sIb
}, 0 },
3095 { "orQ", { Evh1
, sIb
}, 0 },
3096 { "adcQ", { Evh1
, sIb
}, 0 },
3097 { "sbbQ", { Evh1
, sIb
}, 0 },
3098 { "andQ", { Evh1
, sIb
}, 0 },
3099 { "subQ", { Evh1
, sIb
}, 0 },
3100 { "xorQ", { Evh1
, sIb
}, 0 },
3101 { "cmpQ", { Ev
, sIb
}, 0 },
3105 { "popU", { stackEv
}, 0 },
3106 { XOP_8F_TABLE (XOP_09
) },
3110 { XOP_8F_TABLE (XOP_09
) },
3114 { "rolA", { Eb
, Ib
}, 0 },
3115 { "rorA", { Eb
, Ib
}, 0 },
3116 { "rclA", { Eb
, Ib
}, 0 },
3117 { "rcrA", { Eb
, Ib
}, 0 },
3118 { "shlA", { Eb
, Ib
}, 0 },
3119 { "shrA", { Eb
, Ib
}, 0 },
3120 { "shlA", { Eb
, Ib
}, 0 },
3121 { "sarA", { Eb
, Ib
}, 0 },
3125 { "rolQ", { Ev
, Ib
}, 0 },
3126 { "rorQ", { Ev
, Ib
}, 0 },
3127 { "rclQ", { Ev
, Ib
}, 0 },
3128 { "rcrQ", { Ev
, Ib
}, 0 },
3129 { "shlQ", { Ev
, Ib
}, 0 },
3130 { "shrQ", { Ev
, Ib
}, 0 },
3131 { "shlQ", { Ev
, Ib
}, 0 },
3132 { "sarQ", { Ev
, Ib
}, 0 },
3136 { "movA", { Ebh3
, Ib
}, 0 },
3143 { MOD_TABLE (MOD_C6_REG_7
) },
3147 { "movQ", { Evh3
, Iv
}, 0 },
3154 { MOD_TABLE (MOD_C7_REG_7
) },
3158 { "rolA", { Eb
, I1
}, 0 },
3159 { "rorA", { Eb
, I1
}, 0 },
3160 { "rclA", { Eb
, I1
}, 0 },
3161 { "rcrA", { Eb
, I1
}, 0 },
3162 { "shlA", { Eb
, I1
}, 0 },
3163 { "shrA", { Eb
, I1
}, 0 },
3164 { "shlA", { Eb
, I1
}, 0 },
3165 { "sarA", { Eb
, I1
}, 0 },
3169 { "rolQ", { Ev
, I1
}, 0 },
3170 { "rorQ", { Ev
, I1
}, 0 },
3171 { "rclQ", { Ev
, I1
}, 0 },
3172 { "rcrQ", { Ev
, I1
}, 0 },
3173 { "shlQ", { Ev
, I1
}, 0 },
3174 { "shrQ", { Ev
, I1
}, 0 },
3175 { "shlQ", { Ev
, I1
}, 0 },
3176 { "sarQ", { Ev
, I1
}, 0 },
3180 { "rolA", { Eb
, CL
}, 0 },
3181 { "rorA", { Eb
, CL
}, 0 },
3182 { "rclA", { Eb
, CL
}, 0 },
3183 { "rcrA", { Eb
, CL
}, 0 },
3184 { "shlA", { Eb
, CL
}, 0 },
3185 { "shrA", { Eb
, CL
}, 0 },
3186 { "shlA", { Eb
, CL
}, 0 },
3187 { "sarA", { Eb
, CL
}, 0 },
3191 { "rolQ", { Ev
, CL
}, 0 },
3192 { "rorQ", { Ev
, CL
}, 0 },
3193 { "rclQ", { Ev
, CL
}, 0 },
3194 { "rcrQ", { Ev
, CL
}, 0 },
3195 { "shlQ", { Ev
, CL
}, 0 },
3196 { "shrQ", { Ev
, CL
}, 0 },
3197 { "shlQ", { Ev
, CL
}, 0 },
3198 { "sarQ", { Ev
, CL
}, 0 },
3202 { "testA", { Eb
, Ib
}, 0 },
3203 { "testA", { Eb
, Ib
}, 0 },
3204 { "notA", { Ebh1
}, 0 },
3205 { "negA", { Ebh1
}, 0 },
3206 { "mulA", { Eb
}, 0 }, /* Don't print the implicit %al register, */
3207 { "imulA", { Eb
}, 0 }, /* to distinguish these opcodes from other */
3208 { "divA", { Eb
}, 0 }, /* mul/imul opcodes. Do the same for div */
3209 { "idivA", { Eb
}, 0 }, /* and idiv for consistency. */
3213 { "testQ", { Ev
, Iv
}, 0 },
3214 { "testQ", { Ev
, Iv
}, 0 },
3215 { "notQ", { Evh1
}, 0 },
3216 { "negQ", { Evh1
}, 0 },
3217 { "mulQ", { Ev
}, 0 }, /* Don't print the implicit register. */
3218 { "imulQ", { Ev
}, 0 },
3219 { "divQ", { Ev
}, 0 },
3220 { "idivQ", { Ev
}, 0 },
3224 { "incA", { Ebh1
}, 0 },
3225 { "decA", { Ebh1
}, 0 },
3229 { "incQ", { Evh1
}, 0 },
3230 { "decQ", { Evh1
}, 0 },
3231 { "call{&|}", { NOTRACK
, indirEv
, BND
}, 0 },
3232 { MOD_TABLE (MOD_FF_REG_3
) },
3233 { "jmp{&|}", { NOTRACK
, indirEv
, BND
}, 0 },
3234 { MOD_TABLE (MOD_FF_REG_5
) },
3235 { "pushU", { stackEv
}, 0 },
3240 { "sldtD", { Sv
}, 0 },
3241 { "strD", { Sv
}, 0 },
3242 { "lldt", { Ew
}, 0 },
3243 { "ltr", { Ew
}, 0 },
3244 { "verr", { Ew
}, 0 },
3245 { "verw", { Ew
}, 0 },
3251 { MOD_TABLE (MOD_0F01_REG_0
) },
3252 { MOD_TABLE (MOD_0F01_REG_1
) },
3253 { MOD_TABLE (MOD_0F01_REG_2
) },
3254 { MOD_TABLE (MOD_0F01_REG_3
) },
3255 { "smswD", { Sv
}, 0 },
3256 { MOD_TABLE (MOD_0F01_REG_5
) },
3257 { "lmsw", { Ew
}, 0 },
3258 { MOD_TABLE (MOD_0F01_REG_7
) },
3262 { "prefetch", { Mb
}, 0 },
3263 { "prefetchw", { Mb
}, 0 },
3264 { "prefetchwt1", { Mb
}, 0 },
3265 { "prefetch", { Mb
}, 0 },
3266 { "prefetch", { Mb
}, 0 },
3267 { "prefetch", { Mb
}, 0 },
3268 { "prefetch", { Mb
}, 0 },
3269 { "prefetch", { Mb
}, 0 },
3273 { MOD_TABLE (MOD_0F18_REG_0
) },
3274 { MOD_TABLE (MOD_0F18_REG_1
) },
3275 { MOD_TABLE (MOD_0F18_REG_2
) },
3276 { MOD_TABLE (MOD_0F18_REG_3
) },
3277 { MOD_TABLE (MOD_0F18_REG_4
) },
3278 { MOD_TABLE (MOD_0F18_REG_5
) },
3279 { MOD_TABLE (MOD_0F18_REG_6
) },
3280 { MOD_TABLE (MOD_0F18_REG_7
) },
3282 /* REG_0F1C_P_0_MOD_0 */
3284 { "cldemote", { Mb
}, 0 },
3285 { "nopQ", { Ev
}, 0 },
3286 { "nopQ", { Ev
}, 0 },
3287 { "nopQ", { Ev
}, 0 },
3288 { "nopQ", { Ev
}, 0 },
3289 { "nopQ", { Ev
}, 0 },
3290 { "nopQ", { Ev
}, 0 },
3291 { "nopQ", { Ev
}, 0 },
3293 /* REG_0F1E_P_1_MOD_3 */
3295 { "nopQ", { Ev
}, 0 },
3296 { "rdsspK", { Rdq
}, PREFIX_OPCODE
},
3297 { "nopQ", { Ev
}, 0 },
3298 { "nopQ", { Ev
}, 0 },
3299 { "nopQ", { Ev
}, 0 },
3300 { "nopQ", { Ev
}, 0 },
3301 { "nopQ", { Ev
}, 0 },
3302 { RM_TABLE (RM_0F1E_P_1_MOD_3_REG_7
) },
3308 { MOD_TABLE (MOD_0F71_REG_2
) },
3310 { MOD_TABLE (MOD_0F71_REG_4
) },
3312 { MOD_TABLE (MOD_0F71_REG_6
) },
3318 { MOD_TABLE (MOD_0F72_REG_2
) },
3320 { MOD_TABLE (MOD_0F72_REG_4
) },
3322 { MOD_TABLE (MOD_0F72_REG_6
) },
3328 { MOD_TABLE (MOD_0F73_REG_2
) },
3329 { MOD_TABLE (MOD_0F73_REG_3
) },
3332 { MOD_TABLE (MOD_0F73_REG_6
) },
3333 { MOD_TABLE (MOD_0F73_REG_7
) },
3337 { "montmul", { { OP_0f07
, 0 } }, 0 },
3338 { "xsha1", { { OP_0f07
, 0 } }, 0 },
3339 { "xsha256", { { OP_0f07
, 0 } }, 0 },
3343 { "xstore-rng", { { OP_0f07
, 0 } }, 0 },
3344 { "xcrypt-ecb", { { OP_0f07
, 0 } }, 0 },
3345 { "xcrypt-cbc", { { OP_0f07
, 0 } }, 0 },
3346 { "xcrypt-ctr", { { OP_0f07
, 0 } }, 0 },
3347 { "xcrypt-cfb", { { OP_0f07
, 0 } }, 0 },
3348 { "xcrypt-ofb", { { OP_0f07
, 0 } }, 0 },
3352 { MOD_TABLE (MOD_0FAE_REG_0
) },
3353 { MOD_TABLE (MOD_0FAE_REG_1
) },
3354 { MOD_TABLE (MOD_0FAE_REG_2
) },
3355 { MOD_TABLE (MOD_0FAE_REG_3
) },
3356 { MOD_TABLE (MOD_0FAE_REG_4
) },
3357 { MOD_TABLE (MOD_0FAE_REG_5
) },
3358 { MOD_TABLE (MOD_0FAE_REG_6
) },
3359 { MOD_TABLE (MOD_0FAE_REG_7
) },
3367 { "btQ", { Ev
, Ib
}, 0 },
3368 { "btsQ", { Evh1
, Ib
}, 0 },
3369 { "btrQ", { Evh1
, Ib
}, 0 },
3370 { "btcQ", { Evh1
, Ib
}, 0 },
3375 { "cmpxchg8b", { { CMPXCHG8B_Fixup
, q_mode
} }, 0 },
3377 { MOD_TABLE (MOD_0FC7_REG_3
) },
3378 { MOD_TABLE (MOD_0FC7_REG_4
) },
3379 { MOD_TABLE (MOD_0FC7_REG_5
) },
3380 { MOD_TABLE (MOD_0FC7_REG_6
) },
3381 { MOD_TABLE (MOD_0FC7_REG_7
) },
3387 { MOD_TABLE (MOD_VEX_0F71_REG_2
) },
3389 { MOD_TABLE (MOD_VEX_0F71_REG_4
) },
3391 { MOD_TABLE (MOD_VEX_0F71_REG_6
) },
3397 { MOD_TABLE (MOD_VEX_0F72_REG_2
) },
3399 { MOD_TABLE (MOD_VEX_0F72_REG_4
) },
3401 { MOD_TABLE (MOD_VEX_0F72_REG_6
) },
3407 { MOD_TABLE (MOD_VEX_0F73_REG_2
) },
3408 { MOD_TABLE (MOD_VEX_0F73_REG_3
) },
3411 { MOD_TABLE (MOD_VEX_0F73_REG_6
) },
3412 { MOD_TABLE (MOD_VEX_0F73_REG_7
) },
3418 { MOD_TABLE (MOD_VEX_0FAE_REG_2
) },
3419 { MOD_TABLE (MOD_VEX_0FAE_REG_3
) },
3421 /* REG_VEX_0F38F3 */
3424 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1
) },
3425 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2
) },
3426 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3
) },
3430 { "llwpcb", { { OP_LWPCB_E
, 0 } }, 0 },
3431 { "slwpcb", { { OP_LWPCB_E
, 0 } }, 0 },
3435 { "lwpins", { { OP_LWP_E
, 0 }, Ed
, Id
}, 0 },
3436 { "lwpval", { { OP_LWP_E
, 0 }, Ed
, Id
}, 0 },
3438 /* REG_XOP_TBM_01 */
3441 { "blcfill", { { OP_LWP_E
, 0 }, Edq
}, 0 },
3442 { "blsfill", { { OP_LWP_E
, 0 }, Edq
}, 0 },
3443 { "blcs", { { OP_LWP_E
, 0 }, Edq
}, 0 },
3444 { "tzmsk", { { OP_LWP_E
, 0 }, Edq
}, 0 },
3445 { "blcic", { { OP_LWP_E
, 0 }, Edq
}, 0 },
3446 { "blsic", { { OP_LWP_E
, 0 }, Edq
}, 0 },
3447 { "t1mskc", { { OP_LWP_E
, 0 }, Edq
}, 0 },
3449 /* REG_XOP_TBM_02 */
3452 { "blcmsk", { { OP_LWP_E
, 0 }, Edq
}, 0 },
3457 { "blci", { { OP_LWP_E
, 0 }, Edq
}, 0 },
3460 #include "i386-dis-evex-reg.h"
3463 static const struct dis386 prefix_table
[][4] = {
3466 { "xchgS", { { NOP_Fixup1
, eAX_reg
}, { NOP_Fixup2
, eAX_reg
} }, 0 },
3467 { "pause", { XX
}, 0 },
3468 { "xchgS", { { NOP_Fixup1
, eAX_reg
}, { NOP_Fixup2
, eAX_reg
} }, 0 },
3469 { NULL
, { { NULL
, 0 } }, PREFIX_IGNORED
}
3472 /* PREFIX_0F01_REG_3_RM_1 */
3474 { "vmmcall", { Skip_MODRM
}, 0 },
3475 { "vmgexit", { Skip_MODRM
}, 0 },
3477 { "vmgexit", { Skip_MODRM
}, 0 },
3480 /* PREFIX_0F01_REG_5_MOD_0 */
3483 { "rstorssp", { Mq
}, PREFIX_OPCODE
},
3486 /* PREFIX_0F01_REG_5_MOD_3_RM_0 */
3488 { "serialize", { Skip_MODRM
}, PREFIX_OPCODE
},
3489 { "setssbsy", { Skip_MODRM
}, PREFIX_OPCODE
},
3491 { "xsusldtrk", { Skip_MODRM
}, PREFIX_OPCODE
},
3494 /* PREFIX_0F01_REG_5_MOD_3_RM_1 */
3499 { "xresldtrk", { Skip_MODRM
}, PREFIX_OPCODE
},
3502 /* PREFIX_0F01_REG_5_MOD_3_RM_2 */
3505 { "saveprevssp", { Skip_MODRM
}, PREFIX_OPCODE
},
3508 /* PREFIX_0F01_REG_7_MOD_3_RM_2 */
3510 { "monitorx", { { OP_Monitor
, 0 } }, 0 },
3511 { "mcommit", { Skip_MODRM
}, 0 },
3514 /* PREFIX_0F01_REG_7_MOD_3_RM_3 */
3516 { "mwaitx", { { OP_Mwait
, eBX_reg
} }, 0 },
3521 { "wbinvd", { XX
}, 0 },
3522 { "wbnoinvd", { XX
}, 0 },
3527 { "movups", { XM
, EXx
}, PREFIX_OPCODE
},
3528 { "movss", { XM
, EXd
}, PREFIX_OPCODE
},
3529 { "movupd", { XM
, EXx
}, PREFIX_OPCODE
},
3530 { "movsd", { XM
, EXq
}, PREFIX_OPCODE
},
3535 { "movups", { EXxS
, XM
}, PREFIX_OPCODE
},
3536 { "movss", { EXdS
, XM
}, PREFIX_OPCODE
},
3537 { "movupd", { EXxS
, XM
}, PREFIX_OPCODE
},
3538 { "movsd", { EXqS
, XM
}, PREFIX_OPCODE
},
3543 { MOD_TABLE (MOD_0F12_PREFIX_0
) },
3544 { "movsldup", { XM
, EXx
}, PREFIX_OPCODE
},
3545 { MOD_TABLE (MOD_0F12_PREFIX_2
) },
3546 { "movddup", { XM
, EXq
}, PREFIX_OPCODE
},
3551 { MOD_TABLE (MOD_0F16_PREFIX_0
) },
3552 { "movshdup", { XM
, EXx
}, PREFIX_OPCODE
},
3553 { MOD_TABLE (MOD_0F16_PREFIX_2
) },
3558 { MOD_TABLE (MOD_0F1A_PREFIX_0
) },
3559 { "bndcl", { Gbnd
, Ev_bnd
}, 0 },
3560 { "bndmov", { Gbnd
, Ebnd
}, 0 },
3561 { "bndcu", { Gbnd
, Ev_bnd
}, 0 },
3566 { MOD_TABLE (MOD_0F1B_PREFIX_0
) },
3567 { MOD_TABLE (MOD_0F1B_PREFIX_1
) },
3568 { "bndmov", { EbndS
, Gbnd
}, 0 },
3569 { "bndcn", { Gbnd
, Ev_bnd
}, 0 },
3574 { MOD_TABLE (MOD_0F1C_PREFIX_0
) },
3575 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3576 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3577 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3582 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3583 { MOD_TABLE (MOD_0F1E_PREFIX_1
) },
3584 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3585 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3590 { "cvtpi2ps", { XM
, EMCq
}, PREFIX_OPCODE
},
3591 { "cvtsi2ss%LQ", { XM
, Edq
}, PREFIX_OPCODE
},
3592 { "cvtpi2pd", { XM
, EMCq
}, PREFIX_OPCODE
},
3593 { "cvtsi2sd%LQ", { XM
, Edq
}, 0 },
3598 { MOD_TABLE (MOD_0F2B_PREFIX_0
) },
3599 { MOD_TABLE (MOD_0F2B_PREFIX_1
) },
3600 { MOD_TABLE (MOD_0F2B_PREFIX_2
) },
3601 { MOD_TABLE (MOD_0F2B_PREFIX_3
) },
3606 { "cvttps2pi", { MXC
, EXq
}, PREFIX_OPCODE
},
3607 { "cvttss2si", { Gdq
, EXd
}, PREFIX_OPCODE
},
3608 { "cvttpd2pi", { MXC
, EXx
}, PREFIX_OPCODE
},
3609 { "cvttsd2si", { Gdq
, EXq
}, PREFIX_OPCODE
},
3614 { "cvtps2pi", { MXC
, EXq
}, PREFIX_OPCODE
},
3615 { "cvtss2si", { Gdq
, EXd
}, PREFIX_OPCODE
},
3616 { "cvtpd2pi", { MXC
, EXx
}, PREFIX_OPCODE
},
3617 { "cvtsd2si", { Gdq
, EXq
}, PREFIX_OPCODE
},
3622 { "ucomiss",{ XM
, EXd
}, 0 },
3624 { "ucomisd",{ XM
, EXq
}, 0 },
3629 { "comiss", { XM
, EXd
}, 0 },
3631 { "comisd", { XM
, EXq
}, 0 },
3636 { "sqrtps", { XM
, EXx
}, PREFIX_OPCODE
},
3637 { "sqrtss", { XM
, EXd
}, PREFIX_OPCODE
},
3638 { "sqrtpd", { XM
, EXx
}, PREFIX_OPCODE
},
3639 { "sqrtsd", { XM
, EXq
}, PREFIX_OPCODE
},
3644 { "rsqrtps",{ XM
, EXx
}, PREFIX_OPCODE
},
3645 { "rsqrtss",{ XM
, EXd
}, PREFIX_OPCODE
},
3650 { "rcpps", { XM
, EXx
}, PREFIX_OPCODE
},
3651 { "rcpss", { XM
, EXd
}, PREFIX_OPCODE
},
3656 { "addps", { XM
, EXx
}, PREFIX_OPCODE
},
3657 { "addss", { XM
, EXd
}, PREFIX_OPCODE
},
3658 { "addpd", { XM
, EXx
}, PREFIX_OPCODE
},
3659 { "addsd", { XM
, EXq
}, PREFIX_OPCODE
},
3664 { "mulps", { XM
, EXx
}, PREFIX_OPCODE
},
3665 { "mulss", { XM
, EXd
}, PREFIX_OPCODE
},
3666 { "mulpd", { XM
, EXx
}, PREFIX_OPCODE
},
3667 { "mulsd", { XM
, EXq
}, PREFIX_OPCODE
},
3672 { "cvtps2pd", { XM
, EXq
}, PREFIX_OPCODE
},
3673 { "cvtss2sd", { XM
, EXd
}, PREFIX_OPCODE
},
3674 { "cvtpd2ps", { XM
, EXx
}, PREFIX_OPCODE
},
3675 { "cvtsd2ss", { XM
, EXq
}, PREFIX_OPCODE
},
3680 { "cvtdq2ps", { XM
, EXx
}, PREFIX_OPCODE
},
3681 { "cvttps2dq", { XM
, EXx
}, PREFIX_OPCODE
},
3682 { "cvtps2dq", { XM
, EXx
}, PREFIX_OPCODE
},
3687 { "subps", { XM
, EXx
}, PREFIX_OPCODE
},
3688 { "subss", { XM
, EXd
}, PREFIX_OPCODE
},
3689 { "subpd", { XM
, EXx
}, PREFIX_OPCODE
},
3690 { "subsd", { XM
, EXq
}, PREFIX_OPCODE
},
3695 { "minps", { XM
, EXx
}, PREFIX_OPCODE
},
3696 { "minss", { XM
, EXd
}, PREFIX_OPCODE
},
3697 { "minpd", { XM
, EXx
}, PREFIX_OPCODE
},
3698 { "minsd", { XM
, EXq
}, PREFIX_OPCODE
},
3703 { "divps", { XM
, EXx
}, PREFIX_OPCODE
},
3704 { "divss", { XM
, EXd
}, PREFIX_OPCODE
},
3705 { "divpd", { XM
, EXx
}, PREFIX_OPCODE
},
3706 { "divsd", { XM
, EXq
}, PREFIX_OPCODE
},
3711 { "maxps", { XM
, EXx
}, PREFIX_OPCODE
},
3712 { "maxss", { XM
, EXd
}, PREFIX_OPCODE
},
3713 { "maxpd", { XM
, EXx
}, PREFIX_OPCODE
},
3714 { "maxsd", { XM
, EXq
}, PREFIX_OPCODE
},
3719 { "punpcklbw",{ MX
, EMd
}, PREFIX_OPCODE
},
3721 { "punpcklbw",{ MX
, EMx
}, PREFIX_OPCODE
},
3726 { "punpcklwd",{ MX
, EMd
}, PREFIX_OPCODE
},
3728 { "punpcklwd",{ MX
, EMx
}, PREFIX_OPCODE
},
3733 { "punpckldq",{ MX
, EMd
}, PREFIX_OPCODE
},
3735 { "punpckldq",{ MX
, EMx
}, PREFIX_OPCODE
},
3742 { "punpcklqdq", { XM
, EXx
}, PREFIX_OPCODE
},
3749 { "punpckhqdq", { XM
, EXx
}, PREFIX_OPCODE
},
3754 { "movq", { MX
, EM
}, PREFIX_OPCODE
},
3755 { "movdqu", { XM
, EXx
}, PREFIX_OPCODE
},
3756 { "movdqa", { XM
, EXx
}, PREFIX_OPCODE
},
3761 { "pshufw", { MX
, EM
, Ib
}, PREFIX_OPCODE
},
3762 { "pshufhw",{ XM
, EXx
, Ib
}, PREFIX_OPCODE
},
3763 { "pshufd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
3764 { "pshuflw",{ XM
, EXx
, Ib
}, PREFIX_OPCODE
},
3767 /* PREFIX_0F73_REG_3 */
3771 { "psrldq", { XS
, Ib
}, 0 },
3774 /* PREFIX_0F73_REG_7 */
3778 { "pslldq", { XS
, Ib
}, 0 },
3783 {"vmread", { Em
, Gm
}, 0 },
3785 {"extrq", { XS
, Ib
, Ib
}, 0 },
3786 {"insertq", { XM
, XS
, Ib
, Ib
}, 0 },
3791 {"vmwrite", { Gm
, Em
}, 0 },
3793 {"extrq", { XM
, XS
}, 0 },
3794 {"insertq", { XM
, XS
}, 0 },
3801 { "haddpd", { XM
, EXx
}, PREFIX_OPCODE
},
3802 { "haddps", { XM
, EXx
}, PREFIX_OPCODE
},
3809 { "hsubpd", { XM
, EXx
}, PREFIX_OPCODE
},
3810 { "hsubps", { XM
, EXx
}, PREFIX_OPCODE
},
3815 { "movK", { Edq
, MX
}, PREFIX_OPCODE
},
3816 { "movq", { XM
, EXq
}, PREFIX_OPCODE
},
3817 { "movK", { Edq
, XM
}, PREFIX_OPCODE
},
3822 { "movq", { EMS
, MX
}, PREFIX_OPCODE
},
3823 { "movdqu", { EXxS
, XM
}, PREFIX_OPCODE
},
3824 { "movdqa", { EXxS
, XM
}, PREFIX_OPCODE
},
3827 /* PREFIX_0FAE_REG_0_MOD_3 */
3830 { "rdfsbase", { Ev
}, 0 },
3833 /* PREFIX_0FAE_REG_1_MOD_3 */
3836 { "rdgsbase", { Ev
}, 0 },
3839 /* PREFIX_0FAE_REG_2_MOD_3 */
3842 { "wrfsbase", { Ev
}, 0 },
3845 /* PREFIX_0FAE_REG_3_MOD_3 */
3848 { "wrgsbase", { Ev
}, 0 },
3851 /* PREFIX_0FAE_REG_4_MOD_0 */
3853 { "xsave", { FXSAVE
}, 0 },
3854 { "ptwrite%LQ", { Edq
}, 0 },
3857 /* PREFIX_0FAE_REG_4_MOD_3 */
3860 { "ptwrite%LQ", { Edq
}, 0 },
3863 /* PREFIX_0FAE_REG_5_MOD_0 */
3865 { "xrstor", { FXSAVE
}, PREFIX_OPCODE
},
3868 /* PREFIX_0FAE_REG_5_MOD_3 */
3870 { "lfence", { Skip_MODRM
}, 0 },
3871 { "incsspK", { Rdq
}, PREFIX_OPCODE
},
3874 /* PREFIX_0FAE_REG_6_MOD_0 */
3876 { "xsaveopt", { FXSAVE
}, PREFIX_OPCODE
},
3877 { "clrssbsy", { Mq
}, PREFIX_OPCODE
},
3878 { "clwb", { Mb
}, PREFIX_OPCODE
},
3881 /* PREFIX_0FAE_REG_6_MOD_3 */
3883 { RM_TABLE (RM_0FAE_REG_6_MOD_3_P_0
) },
3884 { "umonitor", { Eva
}, PREFIX_OPCODE
},
3885 { "tpause", { Edq
}, PREFIX_OPCODE
},
3886 { "umwait", { Edq
}, PREFIX_OPCODE
},
3889 /* PREFIX_0FAE_REG_7_MOD_0 */
3891 { "clflush", { Mb
}, 0 },
3893 { "clflushopt", { Mb
}, 0 },
3899 { "popcntS", { Gv
, Ev
}, 0 },
3904 { "bsfS", { Gv
, Ev
}, 0 },
3905 { "tzcntS", { Gv
, Ev
}, 0 },
3906 { "bsfS", { Gv
, Ev
}, 0 },
3911 { "bsrS", { Gv
, Ev
}, 0 },
3912 { "lzcntS", { Gv
, Ev
}, 0 },
3913 { "bsrS", { Gv
, Ev
}, 0 },
3918 { "cmpps", { XM
, EXx
, CMP
}, PREFIX_OPCODE
},
3919 { "cmpss", { XM
, EXd
, CMP
}, PREFIX_OPCODE
},
3920 { "cmppd", { XM
, EXx
, CMP
}, PREFIX_OPCODE
},
3921 { "cmpsd", { XM
, EXq
, CMP
}, PREFIX_OPCODE
},
3924 /* PREFIX_0FC3_MOD_0 */
3926 { "movntiS", { Edq
, Gdq
}, PREFIX_OPCODE
},
3929 /* PREFIX_0FC7_REG_6_MOD_0 */
3931 { "vmptrld",{ Mq
}, 0 },
3932 { "vmxon", { Mq
}, 0 },
3933 { "vmclear",{ Mq
}, 0 },
3936 /* PREFIX_0FC7_REG_6_MOD_3 */
3938 { "rdrand", { Ev
}, 0 },
3940 { "rdrand", { Ev
}, 0 }
3943 /* PREFIX_0FC7_REG_7_MOD_3 */
3945 { "rdseed", { Ev
}, 0 },
3946 { "rdpid", { Em
}, 0 },
3947 { "rdseed", { Ev
}, 0 },
3954 { "addsubpd", { XM
, EXx
}, 0 },
3955 { "addsubps", { XM
, EXx
}, 0 },
3961 { "movq2dq",{ XM
, MS
}, 0 },
3962 { "movq", { EXqS
, XM
}, 0 },
3963 { "movdq2q",{ MX
, XS
}, 0 },
3969 { "cvtdq2pd", { XM
, EXq
}, PREFIX_OPCODE
},
3970 { "cvttpd2dq", { XM
, EXx
}, PREFIX_OPCODE
},
3971 { "cvtpd2dq", { XM
, EXx
}, PREFIX_OPCODE
},
3976 { "movntq", { Mq
, MX
}, PREFIX_OPCODE
},
3978 { MOD_TABLE (MOD_0FE7_PREFIX_2
) },
3986 { MOD_TABLE (MOD_0FF0_PREFIX_3
) },
3991 { "maskmovq", { MX
, MS
}, PREFIX_OPCODE
},
3993 { "maskmovdqu", { XM
, XS
}, PREFIX_OPCODE
},
4000 { "pblendvb", { XM
, EXx
, XMM0
}, PREFIX_OPCODE
},
4007 { "blendvps", { XM
, EXx
, XMM0
}, PREFIX_OPCODE
},
4014 { "blendvpd", { XM
, EXx
, XMM0
}, PREFIX_OPCODE
},
4021 { "ptest", { XM
, EXx
}, PREFIX_OPCODE
},
4028 { "pmovsxbw", { XM
, EXq
}, PREFIX_OPCODE
},
4035 { "pmovsxbd", { XM
, EXd
}, PREFIX_OPCODE
},
4042 { "pmovsxbq", { XM
, EXw
}, PREFIX_OPCODE
},
4049 { "pmovsxwd", { XM
, EXq
}, PREFIX_OPCODE
},
4056 { "pmovsxwq", { XM
, EXd
}, PREFIX_OPCODE
},
4063 { "pmovsxdq", { XM
, EXq
}, PREFIX_OPCODE
},
4070 { "pmuldq", { XM
, EXx
}, PREFIX_OPCODE
},
4077 { "pcmpeqq", { XM
, EXx
}, PREFIX_OPCODE
},
4084 { MOD_TABLE (MOD_0F382A_PREFIX_2
) },
4091 { "packusdw", { XM
, EXx
}, PREFIX_OPCODE
},
4098 { "pmovzxbw", { XM
, EXq
}, PREFIX_OPCODE
},
4105 { "pmovzxbd", { XM
, EXd
}, PREFIX_OPCODE
},
4112 { "pmovzxbq", { XM
, EXw
}, PREFIX_OPCODE
},
4119 { "pmovzxwd", { XM
, EXq
}, PREFIX_OPCODE
},
4126 { "pmovzxwq", { XM
, EXd
}, PREFIX_OPCODE
},
4133 { "pmovzxdq", { XM
, EXq
}, PREFIX_OPCODE
},
4140 { "pcmpgtq", { XM
, EXx
}, PREFIX_OPCODE
},
4147 { "pminsb", { XM
, EXx
}, PREFIX_OPCODE
},
4154 { "pminsd", { XM
, EXx
}, PREFIX_OPCODE
},
4161 { "pminuw", { XM
, EXx
}, PREFIX_OPCODE
},
4168 { "pminud", { XM
, EXx
}, PREFIX_OPCODE
},
4175 { "pmaxsb", { XM
, EXx
}, PREFIX_OPCODE
},
4182 { "pmaxsd", { XM
, EXx
}, PREFIX_OPCODE
},
4189 { "pmaxuw", { XM
, EXx
}, PREFIX_OPCODE
},
4196 { "pmaxud", { XM
, EXx
}, PREFIX_OPCODE
},
4203 { "pmulld", { XM
, EXx
}, PREFIX_OPCODE
},
4210 { "phminposuw", { XM
, EXx
}, PREFIX_OPCODE
},
4217 { "invept", { Gm
, Mo
}, PREFIX_OPCODE
},
4224 { "invvpid", { Gm
, Mo
}, PREFIX_OPCODE
},
4231 { "invpcid", { Gm
, M
}, PREFIX_OPCODE
},
4236 { "sha1nexte", { XM
, EXxmm
}, PREFIX_OPCODE
},
4241 { "sha1msg1", { XM
, EXxmm
}, PREFIX_OPCODE
},
4246 { "sha1msg2", { XM
, EXxmm
}, PREFIX_OPCODE
},
4251 { "sha256rnds2", { XM
, EXxmm
, XMM0
}, PREFIX_OPCODE
},
4256 { "sha256msg1", { XM
, EXxmm
}, PREFIX_OPCODE
},
4261 { "sha256msg2", { XM
, EXxmm
}, PREFIX_OPCODE
},
4268 { "gf2p8mulb", { XM
, EXxmm
}, PREFIX_OPCODE
},
4275 { "aesimc", { XM
, EXx
}, PREFIX_OPCODE
},
4282 { "aesenc", { XM
, EXx
}, PREFIX_OPCODE
},
4289 { "aesenclast", { XM
, EXx
}, PREFIX_OPCODE
},
4296 { "aesdec", { XM
, EXx
}, PREFIX_OPCODE
},
4303 { "aesdeclast", { XM
, EXx
}, PREFIX_OPCODE
},
4308 { "movbeS", { Gv
, { MOVBE_Fixup
, v_mode
} }, PREFIX_OPCODE
},
4310 { "movbeS", { Gv
, { MOVBE_Fixup
, v_mode
} }, PREFIX_OPCODE
},
4311 { "crc32", { Gdq
, { CRC32_Fixup
, b_mode
} }, PREFIX_OPCODE
},
4316 { "movbeS", { { MOVBE_Fixup
, v_mode
}, Gv
}, PREFIX_OPCODE
},
4318 { "movbeS", { { MOVBE_Fixup
, v_mode
}, Gv
}, PREFIX_OPCODE
},
4319 { "crc32", { Gdq
, { CRC32_Fixup
, v_mode
} }, PREFIX_OPCODE
},
4326 { MOD_TABLE (MOD_0F38F5_PREFIX_2
) },
4331 { MOD_TABLE (MOD_0F38F6_PREFIX_0
) },
4332 { "adoxS", { Gdq
, Edq
}, PREFIX_OPCODE
},
4333 { "adcxS", { Gdq
, Edq
}, PREFIX_OPCODE
},
4340 { MOD_TABLE (MOD_0F38F8_PREFIX_1
) },
4341 { MOD_TABLE (MOD_0F38F8_PREFIX_2
) },
4342 { MOD_TABLE (MOD_0F38F8_PREFIX_3
) },
4347 { MOD_TABLE (MOD_0F38F9_PREFIX_0
) },
4354 { "roundps", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4361 { "roundpd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4368 { "roundss", { XM
, EXd
, Ib
}, PREFIX_OPCODE
},
4375 { "roundsd", { XM
, EXq
, Ib
}, PREFIX_OPCODE
},
4382 { "blendps", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4389 { "blendpd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4396 { "pblendw", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4403 { "pextrb", { Edqb
, XM
, Ib
}, PREFIX_OPCODE
},
4410 { "pextrw", { Edqw
, XM
, Ib
}, PREFIX_OPCODE
},
4417 { "pextrK", { Edq
, XM
, Ib
}, PREFIX_OPCODE
},
4424 { "extractps", { Edqd
, XM
, Ib
}, PREFIX_OPCODE
},
4431 { "pinsrb", { XM
, Edqb
, Ib
}, PREFIX_OPCODE
},
4438 { "insertps", { XM
, EXd
, Ib
}, PREFIX_OPCODE
},
4445 { "pinsrK", { XM
, Edq
, Ib
}, PREFIX_OPCODE
},
4452 { "dpps", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4459 { "dppd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4466 { "mpsadbw", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4473 { "pclmulqdq", { XM
, EXx
, PCLMUL
}, PREFIX_OPCODE
},
4480 { "pcmpestrm", { XM
, { PCMPESTR_Fixup
, x_mode
}, Ib
}, PREFIX_OPCODE
},
4487 { "pcmpestri", { XM
, { PCMPESTR_Fixup
, x_mode
}, Ib
}, PREFIX_OPCODE
},
4494 { "pcmpistrm", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4501 { "pcmpistri", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4506 { "sha1rnds4", { XM
, EXxmm
, Ib
}, PREFIX_OPCODE
},
4513 { "gf2p8affineqb", { XM
, EXxmm
, Ib
}, PREFIX_OPCODE
},
4520 { "gf2p8affineinvqb", { XM
, EXxmm
, Ib
}, PREFIX_OPCODE
},
4527 { "aeskeygenassist", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4530 /* PREFIX_VEX_0F10 */
4532 { "vmovups", { XM
, EXx
}, 0 },
4533 { "vmovss", { XMVexScalar
, VexScalar
, EXxmm_md
}, 0 },
4534 { "vmovupd", { XM
, EXx
}, 0 },
4535 { "vmovsd", { XMVexScalar
, VexScalar
, EXxmm_mq
}, 0 },
4538 /* PREFIX_VEX_0F11 */
4540 { "vmovups", { EXxS
, XM
}, 0 },
4541 { "vmovss", { EXdVexScalarS
, VexScalar
, XMScalar
}, 0 },
4542 { "vmovupd", { EXxS
, XM
}, 0 },
4543 { "vmovsd", { EXqVexScalarS
, VexScalar
, XMScalar
}, 0 },
4546 /* PREFIX_VEX_0F12 */
4548 { MOD_TABLE (MOD_VEX_0F12_PREFIX_0
) },
4549 { "vmovsldup", { XM
, EXx
}, 0 },
4550 { MOD_TABLE (MOD_VEX_0F12_PREFIX_2
) },
4551 { "vmovddup", { XM
, EXymmq
}, 0 },
4554 /* PREFIX_VEX_0F16 */
4556 { MOD_TABLE (MOD_VEX_0F16_PREFIX_0
) },
4557 { "vmovshdup", { XM
, EXx
}, 0 },
4558 { MOD_TABLE (MOD_VEX_0F16_PREFIX_2
) },
4561 /* PREFIX_VEX_0F2A */
4564 { "vcvtsi2ss%LQ", { XMScalar
, VexScalar
, Edq
}, 0 },
4566 { "vcvtsi2sd%LQ", { XMScalar
, VexScalar
, Edq
}, 0 },
4569 /* PREFIX_VEX_0F2C */
4572 { "vcvttss2si", { Gdq
, EXxmm_md
}, 0 },
4574 { "vcvttsd2si", { Gdq
, EXxmm_mq
}, 0 },
4577 /* PREFIX_VEX_0F2D */
4580 { "vcvtss2si", { Gdq
, EXxmm_md
}, 0 },
4582 { "vcvtsd2si", { Gdq
, EXxmm_mq
}, 0 },
4585 /* PREFIX_VEX_0F2E */
4587 { "vucomiss", { XMScalar
, EXxmm_md
}, 0 },
4589 { "vucomisd", { XMScalar
, EXxmm_mq
}, 0 },
4592 /* PREFIX_VEX_0F2F */
4594 { "vcomiss", { XMScalar
, EXxmm_md
}, 0 },
4596 { "vcomisd", { XMScalar
, EXxmm_mq
}, 0 },
4599 /* PREFIX_VEX_0F41 */
4601 { VEX_LEN_TABLE (VEX_LEN_0F41_P_0
) },
4603 { VEX_LEN_TABLE (VEX_LEN_0F41_P_2
) },
4606 /* PREFIX_VEX_0F42 */
4608 { VEX_LEN_TABLE (VEX_LEN_0F42_P_0
) },
4610 { VEX_LEN_TABLE (VEX_LEN_0F42_P_2
) },
4613 /* PREFIX_VEX_0F44 */
4615 { VEX_LEN_TABLE (VEX_LEN_0F44_P_0
) },
4617 { VEX_LEN_TABLE (VEX_LEN_0F44_P_2
) },
4620 /* PREFIX_VEX_0F45 */
4622 { VEX_LEN_TABLE (VEX_LEN_0F45_P_0
) },
4624 { VEX_LEN_TABLE (VEX_LEN_0F45_P_2
) },
4627 /* PREFIX_VEX_0F46 */
4629 { VEX_LEN_TABLE (VEX_LEN_0F46_P_0
) },
4631 { VEX_LEN_TABLE (VEX_LEN_0F46_P_2
) },
4634 /* PREFIX_VEX_0F47 */
4636 { VEX_LEN_TABLE (VEX_LEN_0F47_P_0
) },
4638 { VEX_LEN_TABLE (VEX_LEN_0F47_P_2
) },
4641 /* PREFIX_VEX_0F4A */
4643 { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0
) },
4645 { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2
) },
4648 /* PREFIX_VEX_0F4B */
4650 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0
) },
4652 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2
) },
4655 /* PREFIX_VEX_0F51 */
4657 { "vsqrtps", { XM
, EXx
}, 0 },
4658 { "vsqrtss", { XMScalar
, VexScalar
, EXxmm_md
}, 0 },
4659 { "vsqrtpd", { XM
, EXx
}, 0 },
4660 { "vsqrtsd", { XMScalar
, VexScalar
, EXxmm_mq
}, 0 },
4663 /* PREFIX_VEX_0F52 */
4665 { "vrsqrtps", { XM
, EXx
}, 0 },
4666 { "vrsqrtss", { XMScalar
, VexScalar
, EXxmm_md
}, 0 },
4669 /* PREFIX_VEX_0F53 */
4671 { "vrcpps", { XM
, EXx
}, 0 },
4672 { "vrcpss", { XMScalar
, VexScalar
, EXxmm_md
}, 0 },
4675 /* PREFIX_VEX_0F58 */
4677 { "vaddps", { XM
, Vex
, EXx
}, 0 },
4678 { "vaddss", { XMScalar
, VexScalar
, EXxmm_md
}, 0 },
4679 { "vaddpd", { XM
, Vex
, EXx
}, 0 },
4680 { "vaddsd", { XMScalar
, VexScalar
, EXxmm_mq
}, 0 },
4683 /* PREFIX_VEX_0F59 */
4685 { "vmulps", { XM
, Vex
, EXx
}, 0 },
4686 { "vmulss", { XMScalar
, VexScalar
, EXxmm_md
}, 0 },
4687 { "vmulpd", { XM
, Vex
, EXx
}, 0 },
4688 { "vmulsd", { XMScalar
, VexScalar
, EXxmm_mq
}, 0 },
4691 /* PREFIX_VEX_0F5A */
4693 { "vcvtps2pd", { XM
, EXxmmq
}, 0 },
4694 { "vcvtss2sd", { XMScalar
, VexScalar
, EXxmm_md
}, 0 },
4695 { "vcvtpd2ps%XY",{ XMM
, EXx
}, 0 },
4696 { "vcvtsd2ss", { XMScalar
, VexScalar
, EXxmm_mq
}, 0 },
4699 /* PREFIX_VEX_0F5B */
4701 { "vcvtdq2ps", { XM
, EXx
}, 0 },
4702 { "vcvttps2dq", { XM
, EXx
}, 0 },
4703 { "vcvtps2dq", { XM
, EXx
}, 0 },
4706 /* PREFIX_VEX_0F5C */
4708 { "vsubps", { XM
, Vex
, EXx
}, 0 },
4709 { "vsubss", { XMScalar
, VexScalar
, EXxmm_md
}, 0 },
4710 { "vsubpd", { XM
, Vex
, EXx
}, 0 },
4711 { "vsubsd", { XMScalar
, VexScalar
, EXxmm_mq
}, 0 },
4714 /* PREFIX_VEX_0F5D */
4716 { "vminps", { XM
, Vex
, EXx
}, 0 },
4717 { "vminss", { XMScalar
, VexScalar
, EXxmm_md
}, 0 },
4718 { "vminpd", { XM
, Vex
, EXx
}, 0 },
4719 { "vminsd", { XMScalar
, VexScalar
, EXxmm_mq
}, 0 },
4722 /* PREFIX_VEX_0F5E */
4724 { "vdivps", { XM
, Vex
, EXx
}, 0 },
4725 { "vdivss", { XMScalar
, VexScalar
, EXxmm_md
}, 0 },
4726 { "vdivpd", { XM
, Vex
, EXx
}, 0 },
4727 { "vdivsd", { XMScalar
, VexScalar
, EXxmm_mq
}, 0 },
4730 /* PREFIX_VEX_0F5F */
4732 { "vmaxps", { XM
, Vex
, EXx
}, 0 },
4733 { "vmaxss", { XMScalar
, VexScalar
, EXxmm_md
}, 0 },
4734 { "vmaxpd", { XM
, Vex
, EXx
}, 0 },
4735 { "vmaxsd", { XMScalar
, VexScalar
, EXxmm_mq
}, 0 },
4738 /* PREFIX_VEX_0F60 */
4742 { "vpunpcklbw", { XM
, Vex
, EXx
}, 0 },
4745 /* PREFIX_VEX_0F61 */
4749 { "vpunpcklwd", { XM
, Vex
, EXx
}, 0 },
4752 /* PREFIX_VEX_0F62 */
4756 { "vpunpckldq", { XM
, Vex
, EXx
}, 0 },
4759 /* PREFIX_VEX_0F63 */
4763 { "vpacksswb", { XM
, Vex
, EXx
}, 0 },
4766 /* PREFIX_VEX_0F64 */
4770 { "vpcmpgtb", { XM
, Vex
, EXx
}, 0 },
4773 /* PREFIX_VEX_0F65 */
4777 { "vpcmpgtw", { XM
, Vex
, EXx
}, 0 },
4780 /* PREFIX_VEX_0F66 */
4784 { "vpcmpgtd", { XM
, Vex
, EXx
}, 0 },
4787 /* PREFIX_VEX_0F67 */
4791 { "vpackuswb", { XM
, Vex
, EXx
}, 0 },
4794 /* PREFIX_VEX_0F68 */
4798 { "vpunpckhbw", { XM
, Vex
, EXx
}, 0 },
4801 /* PREFIX_VEX_0F69 */
4805 { "vpunpckhwd", { XM
, Vex
, EXx
}, 0 },
4808 /* PREFIX_VEX_0F6A */
4812 { "vpunpckhdq", { XM
, Vex
, EXx
}, 0 },
4815 /* PREFIX_VEX_0F6B */
4819 { "vpackssdw", { XM
, Vex
, EXx
}, 0 },
4822 /* PREFIX_VEX_0F6C */
4826 { "vpunpcklqdq", { XM
, Vex
, EXx
}, 0 },
4829 /* PREFIX_VEX_0F6D */
4833 { "vpunpckhqdq", { XM
, Vex
, EXx
}, 0 },
4836 /* PREFIX_VEX_0F6E */
4840 { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2
) },
4843 /* PREFIX_VEX_0F6F */
4846 { "vmovdqu", { XM
, EXx
}, 0 },
4847 { "vmovdqa", { XM
, EXx
}, 0 },
4850 /* PREFIX_VEX_0F70 */
4853 { "vpshufhw", { XM
, EXx
, Ib
}, 0 },
4854 { "vpshufd", { XM
, EXx
, Ib
}, 0 },
4855 { "vpshuflw", { XM
, EXx
, Ib
}, 0 },
4858 /* PREFIX_VEX_0F71_REG_2 */
4862 { "vpsrlw", { Vex
, XS
, Ib
}, 0 },
4865 /* PREFIX_VEX_0F71_REG_4 */
4869 { "vpsraw", { Vex
, XS
, Ib
}, 0 },
4872 /* PREFIX_VEX_0F71_REG_6 */
4876 { "vpsllw", { Vex
, XS
, Ib
}, 0 },
4879 /* PREFIX_VEX_0F72_REG_2 */
4883 { "vpsrld", { Vex
, XS
, Ib
}, 0 },
4886 /* PREFIX_VEX_0F72_REG_4 */
4890 { "vpsrad", { Vex
, XS
, Ib
}, 0 },
4893 /* PREFIX_VEX_0F72_REG_6 */
4897 { "vpslld", { Vex
, XS
, Ib
}, 0 },
4900 /* PREFIX_VEX_0F73_REG_2 */
4904 { "vpsrlq", { Vex
, XS
, Ib
}, 0 },
4907 /* PREFIX_VEX_0F73_REG_3 */
4911 { "vpsrldq", { Vex
, XS
, Ib
}, 0 },
4914 /* PREFIX_VEX_0F73_REG_6 */
4918 { "vpsllq", { Vex
, XS
, Ib
}, 0 },
4921 /* PREFIX_VEX_0F73_REG_7 */
4925 { "vpslldq", { Vex
, XS
, Ib
}, 0 },
4928 /* PREFIX_VEX_0F74 */
4932 { "vpcmpeqb", { XM
, Vex
, EXx
}, 0 },
4935 /* PREFIX_VEX_0F75 */
4939 { "vpcmpeqw", { XM
, Vex
, EXx
}, 0 },
4942 /* PREFIX_VEX_0F76 */
4946 { "vpcmpeqd", { XM
, Vex
, EXx
}, 0 },
4949 /* PREFIX_VEX_0F77 */
4951 { VEX_LEN_TABLE (VEX_LEN_0F77_P_0
) },
4954 /* PREFIX_VEX_0F7C */
4958 { "vhaddpd", { XM
, Vex
, EXx
}, 0 },
4959 { "vhaddps", { XM
, Vex
, EXx
}, 0 },
4962 /* PREFIX_VEX_0F7D */
4966 { "vhsubpd", { XM
, Vex
, EXx
}, 0 },
4967 { "vhsubps", { XM
, Vex
, EXx
}, 0 },
4970 /* PREFIX_VEX_0F7E */
4973 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1
) },
4974 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2
) },
4977 /* PREFIX_VEX_0F7F */
4980 { "vmovdqu", { EXxS
, XM
}, 0 },
4981 { "vmovdqa", { EXxS
, XM
}, 0 },
4984 /* PREFIX_VEX_0F90 */
4986 { VEX_LEN_TABLE (VEX_LEN_0F90_P_0
) },
4988 { VEX_LEN_TABLE (VEX_LEN_0F90_P_2
) },
4991 /* PREFIX_VEX_0F91 */
4993 { VEX_LEN_TABLE (VEX_LEN_0F91_P_0
) },
4995 { VEX_LEN_TABLE (VEX_LEN_0F91_P_2
) },
4998 /* PREFIX_VEX_0F92 */
5000 { VEX_LEN_TABLE (VEX_LEN_0F92_P_0
) },
5002 { VEX_LEN_TABLE (VEX_LEN_0F92_P_2
) },
5003 { VEX_LEN_TABLE (VEX_LEN_0F92_P_3
) },
5006 /* PREFIX_VEX_0F93 */
5008 { VEX_LEN_TABLE (VEX_LEN_0F93_P_0
) },
5010 { VEX_LEN_TABLE (VEX_LEN_0F93_P_2
) },
5011 { VEX_LEN_TABLE (VEX_LEN_0F93_P_3
) },
5014 /* PREFIX_VEX_0F98 */
5016 { VEX_LEN_TABLE (VEX_LEN_0F98_P_0
) },
5018 { VEX_LEN_TABLE (VEX_LEN_0F98_P_2
) },
5021 /* PREFIX_VEX_0F99 */
5023 { VEX_LEN_TABLE (VEX_LEN_0F99_P_0
) },
5025 { VEX_LEN_TABLE (VEX_LEN_0F99_P_2
) },
5028 /* PREFIX_VEX_0FC2 */
5030 { "vcmpps", { XM
, Vex
, EXx
, VCMP
}, 0 },
5031 { "vcmpss", { XMScalar
, VexScalar
, EXxmm_md
, VCMP
}, 0 },
5032 { "vcmppd", { XM
, Vex
, EXx
, VCMP
}, 0 },
5033 { "vcmpsd", { XMScalar
, VexScalar
, EXxmm_mq
, VCMP
}, 0 },
5036 /* PREFIX_VEX_0FC4 */
5040 { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2
) },
5043 /* PREFIX_VEX_0FC5 */
5047 { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2
) },
5050 /* PREFIX_VEX_0FD0 */
5054 { "vaddsubpd", { XM
, Vex
, EXx
}, 0 },
5055 { "vaddsubps", { XM
, Vex
, EXx
}, 0 },
5058 /* PREFIX_VEX_0FD1 */
5062 { "vpsrlw", { XM
, Vex
, EXxmm
}, 0 },
5065 /* PREFIX_VEX_0FD2 */
5069 { "vpsrld", { XM
, Vex
, EXxmm
}, 0 },
5072 /* PREFIX_VEX_0FD3 */
5076 { "vpsrlq", { XM
, Vex
, EXxmm
}, 0 },
5079 /* PREFIX_VEX_0FD4 */
5083 { "vpaddq", { XM
, Vex
, EXx
}, 0 },
5086 /* PREFIX_VEX_0FD5 */
5090 { "vpmullw", { XM
, Vex
, EXx
}, 0 },
5093 /* PREFIX_VEX_0FD6 */
5097 { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2
) },
5100 /* PREFIX_VEX_0FD7 */
5104 { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2
) },
5107 /* PREFIX_VEX_0FD8 */
5111 { "vpsubusb", { XM
, Vex
, EXx
}, 0 },
5114 /* PREFIX_VEX_0FD9 */
5118 { "vpsubusw", { XM
, Vex
, EXx
}, 0 },
5121 /* PREFIX_VEX_0FDA */
5125 { "vpminub", { XM
, Vex
, EXx
}, 0 },
5128 /* PREFIX_VEX_0FDB */
5132 { "vpand", { XM
, Vex
, EXx
}, 0 },
5135 /* PREFIX_VEX_0FDC */
5139 { "vpaddusb", { XM
, Vex
, EXx
}, 0 },
5142 /* PREFIX_VEX_0FDD */
5146 { "vpaddusw", { XM
, Vex
, EXx
}, 0 },
5149 /* PREFIX_VEX_0FDE */
5153 { "vpmaxub", { XM
, Vex
, EXx
}, 0 },
5156 /* PREFIX_VEX_0FDF */
5160 { "vpandn", { XM
, Vex
, EXx
}, 0 },
5163 /* PREFIX_VEX_0FE0 */
5167 { "vpavgb", { XM
, Vex
, EXx
}, 0 },
5170 /* PREFIX_VEX_0FE1 */
5174 { "vpsraw", { XM
, Vex
, EXxmm
}, 0 },
5177 /* PREFIX_VEX_0FE2 */
5181 { "vpsrad", { XM
, Vex
, EXxmm
}, 0 },
5184 /* PREFIX_VEX_0FE3 */
5188 { "vpavgw", { XM
, Vex
, EXx
}, 0 },
5191 /* PREFIX_VEX_0FE4 */
5195 { "vpmulhuw", { XM
, Vex
, EXx
}, 0 },
5198 /* PREFIX_VEX_0FE5 */
5202 { "vpmulhw", { XM
, Vex
, EXx
}, 0 },
5205 /* PREFIX_VEX_0FE6 */
5208 { "vcvtdq2pd", { XM
, EXxmmq
}, 0 },
5209 { "vcvttpd2dq%XY", { XMM
, EXx
}, 0 },
5210 { "vcvtpd2dq%XY", { XMM
, EXx
}, 0 },
5213 /* PREFIX_VEX_0FE7 */
5217 { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2
) },
5220 /* PREFIX_VEX_0FE8 */
5224 { "vpsubsb", { XM
, Vex
, EXx
}, 0 },
5227 /* PREFIX_VEX_0FE9 */
5231 { "vpsubsw", { XM
, Vex
, EXx
}, 0 },
5234 /* PREFIX_VEX_0FEA */
5238 { "vpminsw", { XM
, Vex
, EXx
}, 0 },
5241 /* PREFIX_VEX_0FEB */
5245 { "vpor", { XM
, Vex
, EXx
}, 0 },
5248 /* PREFIX_VEX_0FEC */
5252 { "vpaddsb", { XM
, Vex
, EXx
}, 0 },
5255 /* PREFIX_VEX_0FED */
5259 { "vpaddsw", { XM
, Vex
, EXx
}, 0 },
5262 /* PREFIX_VEX_0FEE */
5266 { "vpmaxsw", { XM
, Vex
, EXx
}, 0 },
5269 /* PREFIX_VEX_0FEF */
5273 { "vpxor", { XM
, Vex
, EXx
}, 0 },
5276 /* PREFIX_VEX_0FF0 */
5281 { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3
) },
5284 /* PREFIX_VEX_0FF1 */
5288 { "vpsllw", { XM
, Vex
, EXxmm
}, 0 },
5291 /* PREFIX_VEX_0FF2 */
5295 { "vpslld", { XM
, Vex
, EXxmm
}, 0 },
5298 /* PREFIX_VEX_0FF3 */
5302 { "vpsllq", { XM
, Vex
, EXxmm
}, 0 },
5305 /* PREFIX_VEX_0FF4 */
5309 { "vpmuludq", { XM
, Vex
, EXx
}, 0 },
5312 /* PREFIX_VEX_0FF5 */
5316 { "vpmaddwd", { XM
, Vex
, EXx
}, 0 },
5319 /* PREFIX_VEX_0FF6 */
5323 { "vpsadbw", { XM
, Vex
, EXx
}, 0 },
5326 /* PREFIX_VEX_0FF7 */
5330 { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2
) },
5333 /* PREFIX_VEX_0FF8 */
5337 { "vpsubb", { XM
, Vex
, EXx
}, 0 },
5340 /* PREFIX_VEX_0FF9 */
5344 { "vpsubw", { XM
, Vex
, EXx
}, 0 },
5347 /* PREFIX_VEX_0FFA */
5351 { "vpsubd", { XM
, Vex
, EXx
}, 0 },
5354 /* PREFIX_VEX_0FFB */
5358 { "vpsubq", { XM
, Vex
, EXx
}, 0 },
5361 /* PREFIX_VEX_0FFC */
5365 { "vpaddb", { XM
, Vex
, EXx
}, 0 },
5368 /* PREFIX_VEX_0FFD */
5372 { "vpaddw", { XM
, Vex
, EXx
}, 0 },
5375 /* PREFIX_VEX_0FFE */
5379 { "vpaddd", { XM
, Vex
, EXx
}, 0 },
5382 /* PREFIX_VEX_0F3800 */
5386 { "vpshufb", { XM
, Vex
, EXx
}, 0 },
5389 /* PREFIX_VEX_0F3801 */
5393 { "vphaddw", { XM
, Vex
, EXx
}, 0 },
5396 /* PREFIX_VEX_0F3802 */
5400 { "vphaddd", { XM
, Vex
, EXx
}, 0 },
5403 /* PREFIX_VEX_0F3803 */
5407 { "vphaddsw", { XM
, Vex
, EXx
}, 0 },
5410 /* PREFIX_VEX_0F3804 */
5414 { "vpmaddubsw", { XM
, Vex
, EXx
}, 0 },
5417 /* PREFIX_VEX_0F3805 */
5421 { "vphsubw", { XM
, Vex
, EXx
}, 0 },
5424 /* PREFIX_VEX_0F3806 */
5428 { "vphsubd", { XM
, Vex
, EXx
}, 0 },
5431 /* PREFIX_VEX_0F3807 */
5435 { "vphsubsw", { XM
, Vex
, EXx
}, 0 },
5438 /* PREFIX_VEX_0F3808 */
5442 { "vpsignb", { XM
, Vex
, EXx
}, 0 },
5445 /* PREFIX_VEX_0F3809 */
5449 { "vpsignw", { XM
, Vex
, EXx
}, 0 },
5452 /* PREFIX_VEX_0F380A */
5456 { "vpsignd", { XM
, Vex
, EXx
}, 0 },
5459 /* PREFIX_VEX_0F380B */
5463 { "vpmulhrsw", { XM
, Vex
, EXx
}, 0 },
5466 /* PREFIX_VEX_0F380C */
5470 { VEX_W_TABLE (VEX_W_0F380C_P_2
) },
5473 /* PREFIX_VEX_0F380D */
5477 { VEX_W_TABLE (VEX_W_0F380D_P_2
) },
5480 /* PREFIX_VEX_0F380E */
5484 { VEX_W_TABLE (VEX_W_0F380E_P_2
) },
5487 /* PREFIX_VEX_0F380F */
5491 { VEX_W_TABLE (VEX_W_0F380F_P_2
) },
5494 /* PREFIX_VEX_0F3813 */
5498 { VEX_W_TABLE (VEX_W_0F3813_P_2
) },
5501 /* PREFIX_VEX_0F3816 */
5505 { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2
) },
5508 /* PREFIX_VEX_0F3817 */
5512 { "vptest", { XM
, EXx
}, 0 },
5515 /* PREFIX_VEX_0F3818 */
5519 { VEX_W_TABLE (VEX_W_0F3818_P_2
) },
5522 /* PREFIX_VEX_0F3819 */
5526 { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2
) },
5529 /* PREFIX_VEX_0F381A */
5533 { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2
) },
5536 /* PREFIX_VEX_0F381C */
5540 { "vpabsb", { XM
, EXx
}, 0 },
5543 /* PREFIX_VEX_0F381D */
5547 { "vpabsw", { XM
, EXx
}, 0 },
5550 /* PREFIX_VEX_0F381E */
5554 { "vpabsd", { XM
, EXx
}, 0 },
5557 /* PREFIX_VEX_0F3820 */
5561 { "vpmovsxbw", { XM
, EXxmmq
}, 0 },
5564 /* PREFIX_VEX_0F3821 */
5568 { "vpmovsxbd", { XM
, EXxmmqd
}, 0 },
5571 /* PREFIX_VEX_0F3822 */
5575 { "vpmovsxbq", { XM
, EXxmmdw
}, 0 },
5578 /* PREFIX_VEX_0F3823 */
5582 { "vpmovsxwd", { XM
, EXxmmq
}, 0 },
5585 /* PREFIX_VEX_0F3824 */
5589 { "vpmovsxwq", { XM
, EXxmmqd
}, 0 },
5592 /* PREFIX_VEX_0F3825 */
5596 { "vpmovsxdq", { XM
, EXxmmq
}, 0 },
5599 /* PREFIX_VEX_0F3828 */
5603 { "vpmuldq", { XM
, Vex
, EXx
}, 0 },
5606 /* PREFIX_VEX_0F3829 */
5610 { "vpcmpeqq", { XM
, Vex
, EXx
}, 0 },
5613 /* PREFIX_VEX_0F382A */
5617 { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2
) },
5620 /* PREFIX_VEX_0F382B */
5624 { "vpackusdw", { XM
, Vex
, EXx
}, 0 },
5627 /* PREFIX_VEX_0F382C */
5631 { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2
) },
5634 /* PREFIX_VEX_0F382D */
5638 { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2
) },
5641 /* PREFIX_VEX_0F382E */
5645 { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2
) },
5648 /* PREFIX_VEX_0F382F */
5652 { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2
) },
5655 /* PREFIX_VEX_0F3830 */
5659 { "vpmovzxbw", { XM
, EXxmmq
}, 0 },
5662 /* PREFIX_VEX_0F3831 */
5666 { "vpmovzxbd", { XM
, EXxmmqd
}, 0 },
5669 /* PREFIX_VEX_0F3832 */
5673 { "vpmovzxbq", { XM
, EXxmmdw
}, 0 },
5676 /* PREFIX_VEX_0F3833 */
5680 { "vpmovzxwd", { XM
, EXxmmq
}, 0 },
5683 /* PREFIX_VEX_0F3834 */
5687 { "vpmovzxwq", { XM
, EXxmmqd
}, 0 },
5690 /* PREFIX_VEX_0F3835 */
5694 { "vpmovzxdq", { XM
, EXxmmq
}, 0 },
5697 /* PREFIX_VEX_0F3836 */
5701 { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2
) },
5704 /* PREFIX_VEX_0F3837 */
5708 { "vpcmpgtq", { XM
, Vex
, EXx
}, 0 },
5711 /* PREFIX_VEX_0F3838 */
5715 { "vpminsb", { XM
, Vex
, EXx
}, 0 },
5718 /* PREFIX_VEX_0F3839 */
5722 { "vpminsd", { XM
, Vex
, EXx
}, 0 },
5725 /* PREFIX_VEX_0F383A */
5729 { "vpminuw", { XM
, Vex
, EXx
}, 0 },
5732 /* PREFIX_VEX_0F383B */
5736 { "vpminud", { XM
, Vex
, EXx
}, 0 },
5739 /* PREFIX_VEX_0F383C */
5743 { "vpmaxsb", { XM
, Vex
, EXx
}, 0 },
5746 /* PREFIX_VEX_0F383D */
5750 { "vpmaxsd", { XM
, Vex
, EXx
}, 0 },
5753 /* PREFIX_VEX_0F383E */
5757 { "vpmaxuw", { XM
, Vex
, EXx
}, 0 },
5760 /* PREFIX_VEX_0F383F */
5764 { "vpmaxud", { XM
, Vex
, EXx
}, 0 },
5767 /* PREFIX_VEX_0F3840 */
5771 { "vpmulld", { XM
, Vex
, EXx
}, 0 },
5774 /* PREFIX_VEX_0F3841 */
5778 { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2
) },
5781 /* PREFIX_VEX_0F3845 */
5785 { "vpsrlv%LW", { XM
, Vex
, EXx
}, 0 },
5788 /* PREFIX_VEX_0F3846 */
5792 { VEX_W_TABLE (VEX_W_0F3846_P_2
) },
5795 /* PREFIX_VEX_0F3847 */
5799 { "vpsllv%LW", { XM
, Vex
, EXx
}, 0 },
5802 /* PREFIX_VEX_0F3858 */
5806 { VEX_W_TABLE (VEX_W_0F3858_P_2
) },
5809 /* PREFIX_VEX_0F3859 */
5813 { VEX_W_TABLE (VEX_W_0F3859_P_2
) },
5816 /* PREFIX_VEX_0F385A */
5820 { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2
) },
5823 /* PREFIX_VEX_0F3878 */
5827 { VEX_W_TABLE (VEX_W_0F3878_P_2
) },
5830 /* PREFIX_VEX_0F3879 */
5834 { VEX_W_TABLE (VEX_W_0F3879_P_2
) },
5837 /* PREFIX_VEX_0F388C */
5841 { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2
) },
5844 /* PREFIX_VEX_0F388E */
5848 { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2
) },
5851 /* PREFIX_VEX_0F3890 */
5855 { "vpgatherd%LW", { XM
, MVexVSIBDWpX
, Vex
}, 0 },
5858 /* PREFIX_VEX_0F3891 */
5862 { "vpgatherq%LW", { XMGatherQ
, MVexVSIBQWpX
, VexGatherQ
}, 0 },
5865 /* PREFIX_VEX_0F3892 */
5869 { "vgatherdp%XW", { XM
, MVexVSIBDWpX
, Vex
}, 0 },
5872 /* PREFIX_VEX_0F3893 */
5876 { "vgatherqp%XW", { XMGatherQ
, MVexVSIBQWpX
, VexGatherQ
}, 0 },
5879 /* PREFIX_VEX_0F3896 */
5883 { "vfmaddsub132p%XW", { XM
, Vex
, EXx
, EXxEVexR
}, 0 },
5886 /* PREFIX_VEX_0F3897 */
5890 { "vfmsubadd132p%XW", { XM
, Vex
, EXx
, EXxEVexR
}, 0 },
5893 /* PREFIX_VEX_0F3898 */
5897 { "vfmadd132p%XW", { XM
, Vex
, EXx
, EXxEVexR
}, 0 },
5900 /* PREFIX_VEX_0F3899 */
5904 { "vfmadd132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
, EXxEVexR
}, 0 },
5907 /* PREFIX_VEX_0F389A */
5911 { "vfmsub132p%XW", { XM
, Vex
, EXx
}, 0 },
5914 /* PREFIX_VEX_0F389B */
5918 { "vfmsub132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
5921 /* PREFIX_VEX_0F389C */
5925 { "vfnmadd132p%XW", { XM
, Vex
, EXx
, EXxEVexR
}, 0 },
5928 /* PREFIX_VEX_0F389D */
5932 { "vfnmadd132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
, EXxEVexR
}, 0 },
5935 /* PREFIX_VEX_0F389E */
5939 { "vfnmsub132p%XW", { XM
, Vex
, EXx
, EXxEVexR
}, 0 },
5942 /* PREFIX_VEX_0F389F */
5946 { "vfnmsub132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
, EXxEVexR
}, 0 },
5949 /* PREFIX_VEX_0F38A6 */
5953 { "vfmaddsub213p%XW", { XM
, Vex
, EXx
, EXxEVexR
}, 0 },
5957 /* PREFIX_VEX_0F38A7 */
5961 { "vfmsubadd213p%XW", { XM
, Vex
, EXx
, EXxEVexR
}, 0 },
5964 /* PREFIX_VEX_0F38A8 */
5968 { "vfmadd213p%XW", { XM
, Vex
, EXx
, EXxEVexR
}, 0 },
5971 /* PREFIX_VEX_0F38A9 */
5975 { "vfmadd213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
, EXxEVexR
}, 0 },
5978 /* PREFIX_VEX_0F38AA */
5982 { "vfmsub213p%XW", { XM
, Vex
, EXx
}, 0 },
5985 /* PREFIX_VEX_0F38AB */
5989 { "vfmsub213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
5992 /* PREFIX_VEX_0F38AC */
5996 { "vfnmadd213p%XW", { XM
, Vex
, EXx
, EXxEVexR
}, 0 },
5999 /* PREFIX_VEX_0F38AD */
6003 { "vfnmadd213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
, EXxEVexR
}, 0 },
6006 /* PREFIX_VEX_0F38AE */
6010 { "vfnmsub213p%XW", { XM
, Vex
, EXx
, EXxEVexR
}, 0 },
6013 /* PREFIX_VEX_0F38AF */
6017 { "vfnmsub213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
, EXxEVexR
}, 0 },
6020 /* PREFIX_VEX_0F38B6 */
6024 { "vfmaddsub231p%XW", { XM
, Vex
, EXx
, EXxEVexR
}, 0 },
6027 /* PREFIX_VEX_0F38B7 */
6031 { "vfmsubadd231p%XW", { XM
, Vex
, EXx
, EXxEVexR
}, 0 },
6034 /* PREFIX_VEX_0F38B8 */
6038 { "vfmadd231p%XW", { XM
, Vex
, EXx
, EXxEVexR
}, 0 },
6041 /* PREFIX_VEX_0F38B9 */
6045 { "vfmadd231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
, EXxEVexR
}, 0 },
6048 /* PREFIX_VEX_0F38BA */
6052 { "vfmsub231p%XW", { XM
, Vex
, EXx
, EXxEVexR
}, 0 },
6055 /* PREFIX_VEX_0F38BB */
6059 { "vfmsub231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
, EXxEVexR
}, 0 },
6062 /* PREFIX_VEX_0F38BC */
6066 { "vfnmadd231p%XW", { XM
, Vex
, EXx
, EXxEVexR
}, 0 },
6069 /* PREFIX_VEX_0F38BD */
6073 { "vfnmadd231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
, EXxEVexR
}, 0 },
6076 /* PREFIX_VEX_0F38BE */
6080 { "vfnmsub231p%XW", { XM
, Vex
, EXx
, EXxEVexR
}, 0 },
6083 /* PREFIX_VEX_0F38BF */
6087 { "vfnmsub231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
, EXxEVexR
}, 0 },
6090 /* PREFIX_VEX_0F38CF */
6094 { VEX_W_TABLE (VEX_W_0F38CF_P_2
) },
6097 /* PREFIX_VEX_0F38DB */
6101 { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2
) },
6104 /* PREFIX_VEX_0F38DC */
6108 { "vaesenc", { XM
, Vex
, EXx
}, 0 },
6111 /* PREFIX_VEX_0F38DD */
6115 { "vaesenclast", { XM
, Vex
, EXx
}, 0 },
6118 /* PREFIX_VEX_0F38DE */
6122 { "vaesdec", { XM
, Vex
, EXx
}, 0 },
6125 /* PREFIX_VEX_0F38DF */
6129 { "vaesdeclast", { XM
, Vex
, EXx
}, 0 },
6132 /* PREFIX_VEX_0F38F2 */
6134 { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0
) },
6137 /* PREFIX_VEX_0F38F3_REG_1 */
6139 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0
) },
6142 /* PREFIX_VEX_0F38F3_REG_2 */
6144 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0
) },
6147 /* PREFIX_VEX_0F38F3_REG_3 */
6149 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0
) },
6152 /* PREFIX_VEX_0F38F5 */
6154 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0
) },
6155 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1
) },
6157 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3
) },
6160 /* PREFIX_VEX_0F38F6 */
6165 { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3
) },
6168 /* PREFIX_VEX_0F38F7 */
6170 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0
) },
6171 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1
) },
6172 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2
) },
6173 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3
) },
6176 /* PREFIX_VEX_0F3A00 */
6180 { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2
) },
6183 /* PREFIX_VEX_0F3A01 */
6187 { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2
) },
6190 /* PREFIX_VEX_0F3A02 */
6194 { VEX_W_TABLE (VEX_W_0F3A02_P_2
) },
6197 /* PREFIX_VEX_0F3A04 */
6201 { VEX_W_TABLE (VEX_W_0F3A04_P_2
) },
6204 /* PREFIX_VEX_0F3A05 */
6208 { VEX_W_TABLE (VEX_W_0F3A05_P_2
) },
6211 /* PREFIX_VEX_0F3A06 */
6215 { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2
) },
6218 /* PREFIX_VEX_0F3A08 */
6222 { "vroundps", { XM
, EXx
, Ib
}, 0 },
6225 /* PREFIX_VEX_0F3A09 */
6229 { "vroundpd", { XM
, EXx
, Ib
}, 0 },
6232 /* PREFIX_VEX_0F3A0A */
6236 { "vroundss", { XMScalar
, VexScalar
, EXxmm_md
, Ib
}, 0 },
6239 /* PREFIX_VEX_0F3A0B */
6243 { "vroundsd", { XMScalar
, VexScalar
, EXxmm_mq
, Ib
}, 0 },
6246 /* PREFIX_VEX_0F3A0C */
6250 { "vblendps", { XM
, Vex
, EXx
, Ib
}, 0 },
6253 /* PREFIX_VEX_0F3A0D */
6257 { "vblendpd", { XM
, Vex
, EXx
, Ib
}, 0 },
6260 /* PREFIX_VEX_0F3A0E */
6264 { "vpblendw", { XM
, Vex
, EXx
, Ib
}, 0 },
6267 /* PREFIX_VEX_0F3A0F */
6271 { "vpalignr", { XM
, Vex
, EXx
, Ib
}, 0 },
6274 /* PREFIX_VEX_0F3A14 */
6278 { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2
) },
6281 /* PREFIX_VEX_0F3A15 */
6285 { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2
) },
6288 /* PREFIX_VEX_0F3A16 */
6292 { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2
) },
6295 /* PREFIX_VEX_0F3A17 */
6299 { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2
) },
6302 /* PREFIX_VEX_0F3A18 */
6306 { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2
) },
6309 /* PREFIX_VEX_0F3A19 */
6313 { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2
) },
6316 /* PREFIX_VEX_0F3A1D */
6320 { VEX_W_TABLE (VEX_W_0F3A1D_P_2
) },
6323 /* PREFIX_VEX_0F3A20 */
6327 { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2
) },
6330 /* PREFIX_VEX_0F3A21 */
6334 { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2
) },
6337 /* PREFIX_VEX_0F3A22 */
6341 { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2
) },
6344 /* PREFIX_VEX_0F3A30 */
6348 { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2
) },
6351 /* PREFIX_VEX_0F3A31 */
6355 { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2
) },
6358 /* PREFIX_VEX_0F3A32 */
6362 { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2
) },
6365 /* PREFIX_VEX_0F3A33 */
6369 { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2
) },
6372 /* PREFIX_VEX_0F3A38 */
6376 { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2
) },
6379 /* PREFIX_VEX_0F3A39 */
6383 { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2
) },
6386 /* PREFIX_VEX_0F3A40 */
6390 { "vdpps", { XM
, Vex
, EXx
, Ib
}, 0 },
6393 /* PREFIX_VEX_0F3A41 */
6397 { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2
) },
6400 /* PREFIX_VEX_0F3A42 */
6404 { "vmpsadbw", { XM
, Vex
, EXx
, Ib
}, 0 },
6407 /* PREFIX_VEX_0F3A44 */
6411 { "vpclmulqdq", { XM
, Vex
, EXx
, PCLMUL
}, 0 },
6414 /* PREFIX_VEX_0F3A46 */
6418 { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2
) },
6421 /* PREFIX_VEX_0F3A48 */
6425 { VEX_W_TABLE (VEX_W_0F3A48_P_2
) },
6428 /* PREFIX_VEX_0F3A49 */
6432 { VEX_W_TABLE (VEX_W_0F3A49_P_2
) },
6435 /* PREFIX_VEX_0F3A4A */
6439 { VEX_W_TABLE (VEX_W_0F3A4A_P_2
) },
6442 /* PREFIX_VEX_0F3A4B */
6446 { VEX_W_TABLE (VEX_W_0F3A4B_P_2
) },
6449 /* PREFIX_VEX_0F3A4C */
6453 { VEX_W_TABLE (VEX_W_0F3A4C_P_2
) },
6456 /* PREFIX_VEX_0F3A5C */
6460 { "vfmaddsubps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6463 /* PREFIX_VEX_0F3A5D */
6467 { "vfmaddsubpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6470 /* PREFIX_VEX_0F3A5E */
6474 { "vfmsubaddps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6477 /* PREFIX_VEX_0F3A5F */
6481 { "vfmsubaddpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6484 /* PREFIX_VEX_0F3A60 */
6488 { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2
) },
6492 /* PREFIX_VEX_0F3A61 */
6496 { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2
) },
6499 /* PREFIX_VEX_0F3A62 */
6503 { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2
) },
6506 /* PREFIX_VEX_0F3A63 */
6510 { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2
) },
6513 /* PREFIX_VEX_0F3A68 */
6517 { "vfmaddps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6520 /* PREFIX_VEX_0F3A69 */
6524 { "vfmaddpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6527 /* PREFIX_VEX_0F3A6A */
6531 { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2
) },
6534 /* PREFIX_VEX_0F3A6B */
6538 { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2
) },
6541 /* PREFIX_VEX_0F3A6C */
6545 { "vfmsubps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6548 /* PREFIX_VEX_0F3A6D */
6552 { "vfmsubpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6555 /* PREFIX_VEX_0F3A6E */
6559 { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2
) },
6562 /* PREFIX_VEX_0F3A6F */
6566 { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2
) },
6569 /* PREFIX_VEX_0F3A78 */
6573 { "vfnmaddps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6576 /* PREFIX_VEX_0F3A79 */
6580 { "vfnmaddpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6583 /* PREFIX_VEX_0F3A7A */
6587 { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2
) },
6590 /* PREFIX_VEX_0F3A7B */
6594 { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2
) },
6597 /* PREFIX_VEX_0F3A7C */
6601 { "vfnmsubps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6605 /* PREFIX_VEX_0F3A7D */
6609 { "vfnmsubpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6612 /* PREFIX_VEX_0F3A7E */
6616 { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2
) },
6619 /* PREFIX_VEX_0F3A7F */
6623 { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2
) },
6626 /* PREFIX_VEX_0F3ACE */
6630 { VEX_W_TABLE (VEX_W_0F3ACE_P_2
) },
6633 /* PREFIX_VEX_0F3ACF */
6637 { VEX_W_TABLE (VEX_W_0F3ACF_P_2
) },
6640 /* PREFIX_VEX_0F3ADF */
6644 { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2
) },
6647 /* PREFIX_VEX_0F3AF0 */
6652 { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3
) },
6655 #include "i386-dis-evex-prefix.h"
6658 static const struct dis386 x86_64_table
[][2] = {
6661 { "pushP", { es
}, 0 },
6666 { "popP", { es
}, 0 },
6671 { "pushP", { cs
}, 0 },
6676 { "pushP", { ss
}, 0 },
6681 { "popP", { ss
}, 0 },
6686 { "pushP", { ds
}, 0 },
6691 { "popP", { ds
}, 0 },
6696 { "daa", { XX
}, 0 },
6701 { "das", { XX
}, 0 },
6706 { "aaa", { XX
}, 0 },
6711 { "aas", { XX
}, 0 },
6716 { "pushaP", { XX
}, 0 },
6721 { "popaP", { XX
}, 0 },
6726 { MOD_TABLE (MOD_62_32BIT
) },
6727 { EVEX_TABLE (EVEX_0F
) },
6732 { "arpl", { Ew
, Gw
}, 0 },
6733 { "movs", { { OP_G
, movsxd_mode
}, { MOVSXD_Fixup
, movsxd_mode
} }, 0 },
6738 { "ins{R|}", { Yzr
, indirDX
}, 0 },
6739 { "ins{G|}", { Yzr
, indirDX
}, 0 },
6744 { "outs{R|}", { indirDXr
, Xz
}, 0 },
6745 { "outs{G|}", { indirDXr
, Xz
}, 0 },
6750 /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode. */
6751 { REG_TABLE (REG_80
) },
6756 { "{l|}call{T|}", { Ap
}, 0 },
6761 { "retP", { Iw
, BND
}, 0 },
6762 { "ret@", { Iw
, BND
}, 0 },
6767 { "retP", { BND
}, 0 },
6768 { "ret@", { BND
}, 0 },
6773 { MOD_TABLE (MOD_C4_32BIT
) },
6774 { VEX_C4_TABLE (VEX_0F
) },
6779 { MOD_TABLE (MOD_C5_32BIT
) },
6780 { VEX_C5_TABLE (VEX_0F
) },
6785 { "into", { XX
}, 0 },
6790 { "aam", { Ib
}, 0 },
6795 { "aad", { Ib
}, 0 },
6800 { "callP", { Jv
, BND
}, 0 },
6801 { "call@", { Jv
, BND
}, 0 }
6806 { "jmpP", { Jv
, BND
}, 0 },
6807 { "jmp@", { Jv
, BND
}, 0 }
6812 { "{l|}jmp{T|}", { Ap
}, 0 },
6815 /* X86_64_0F01_REG_0 */
6817 { "sgdt{Q|Q}", { M
}, 0 },
6818 { "sgdt", { M
}, 0 },
6821 /* X86_64_0F01_REG_1 */
6823 { "sidt{Q|Q}", { M
}, 0 },
6824 { "sidt", { M
}, 0 },
6827 /* X86_64_0F01_REG_2 */
6829 { "lgdt{Q|Q}", { M
}, 0 },
6830 { "lgdt", { M
}, 0 },
6833 /* X86_64_0F01_REG_3 */
6835 { "lidt{Q|Q}", { M
}, 0 },
6836 { "lidt", { M
}, 0 },
6840 static const struct dis386 three_byte_table
[][256] = {
6842 /* THREE_BYTE_0F38 */
6845 { "pshufb", { MX
, EM
}, PREFIX_OPCODE
},
6846 { "phaddw", { MX
, EM
}, PREFIX_OPCODE
},
6847 { "phaddd", { MX
, EM
}, PREFIX_OPCODE
},
6848 { "phaddsw", { MX
, EM
}, PREFIX_OPCODE
},
6849 { "pmaddubsw", { MX
, EM
}, PREFIX_OPCODE
},
6850 { "phsubw", { MX
, EM
}, PREFIX_OPCODE
},
6851 { "phsubd", { MX
, EM
}, PREFIX_OPCODE
},
6852 { "phsubsw", { MX
, EM
}, PREFIX_OPCODE
},
6854 { "psignb", { MX
, EM
}, PREFIX_OPCODE
},
6855 { "psignw", { MX
, EM
}, PREFIX_OPCODE
},
6856 { "psignd", { MX
, EM
}, PREFIX_OPCODE
},
6857 { "pmulhrsw", { MX
, EM
}, PREFIX_OPCODE
},
6863 { PREFIX_TABLE (PREFIX_0F3810
) },
6867 { PREFIX_TABLE (PREFIX_0F3814
) },
6868 { PREFIX_TABLE (PREFIX_0F3815
) },
6870 { PREFIX_TABLE (PREFIX_0F3817
) },
6876 { "pabsb", { MX
, EM
}, PREFIX_OPCODE
},
6877 { "pabsw", { MX
, EM
}, PREFIX_OPCODE
},
6878 { "pabsd", { MX
, EM
}, PREFIX_OPCODE
},
6881 { PREFIX_TABLE (PREFIX_0F3820
) },
6882 { PREFIX_TABLE (PREFIX_0F3821
) },
6883 { PREFIX_TABLE (PREFIX_0F3822
) },
6884 { PREFIX_TABLE (PREFIX_0F3823
) },
6885 { PREFIX_TABLE (PREFIX_0F3824
) },
6886 { PREFIX_TABLE (PREFIX_0F3825
) },
6890 { PREFIX_TABLE (PREFIX_0F3828
) },
6891 { PREFIX_TABLE (PREFIX_0F3829
) },
6892 { PREFIX_TABLE (PREFIX_0F382A
) },
6893 { PREFIX_TABLE (PREFIX_0F382B
) },
6899 { PREFIX_TABLE (PREFIX_0F3830
) },
6900 { PREFIX_TABLE (PREFIX_0F3831
) },
6901 { PREFIX_TABLE (PREFIX_0F3832
) },
6902 { PREFIX_TABLE (PREFIX_0F3833
) },
6903 { PREFIX_TABLE (PREFIX_0F3834
) },
6904 { PREFIX_TABLE (PREFIX_0F3835
) },
6906 { PREFIX_TABLE (PREFIX_0F3837
) },
6908 { PREFIX_TABLE (PREFIX_0F3838
) },
6909 { PREFIX_TABLE (PREFIX_0F3839
) },
6910 { PREFIX_TABLE (PREFIX_0F383A
) },
6911 { PREFIX_TABLE (PREFIX_0F383B
) },
6912 { PREFIX_TABLE (PREFIX_0F383C
) },
6913 { PREFIX_TABLE (PREFIX_0F383D
) },
6914 { PREFIX_TABLE (PREFIX_0F383E
) },
6915 { PREFIX_TABLE (PREFIX_0F383F
) },
6917 { PREFIX_TABLE (PREFIX_0F3840
) },
6918 { PREFIX_TABLE (PREFIX_0F3841
) },
6989 { PREFIX_TABLE (PREFIX_0F3880
) },
6990 { PREFIX_TABLE (PREFIX_0F3881
) },
6991 { PREFIX_TABLE (PREFIX_0F3882
) },
7070 { PREFIX_TABLE (PREFIX_0F38C8
) },
7071 { PREFIX_TABLE (PREFIX_0F38C9
) },
7072 { PREFIX_TABLE (PREFIX_0F38CA
) },
7073 { PREFIX_TABLE (PREFIX_0F38CB
) },
7074 { PREFIX_TABLE (PREFIX_0F38CC
) },
7075 { PREFIX_TABLE (PREFIX_0F38CD
) },
7077 { PREFIX_TABLE (PREFIX_0F38CF
) },
7091 { PREFIX_TABLE (PREFIX_0F38DB
) },
7092 { PREFIX_TABLE (PREFIX_0F38DC
) },
7093 { PREFIX_TABLE (PREFIX_0F38DD
) },
7094 { PREFIX_TABLE (PREFIX_0F38DE
) },
7095 { PREFIX_TABLE (PREFIX_0F38DF
) },
7115 { PREFIX_TABLE (PREFIX_0F38F0
) },
7116 { PREFIX_TABLE (PREFIX_0F38F1
) },
7120 { PREFIX_TABLE (PREFIX_0F38F5
) },
7121 { PREFIX_TABLE (PREFIX_0F38F6
) },
7124 { PREFIX_TABLE (PREFIX_0F38F8
) },
7125 { PREFIX_TABLE (PREFIX_0F38F9
) },
7133 /* THREE_BYTE_0F3A */
7145 { PREFIX_TABLE (PREFIX_0F3A08
) },
7146 { PREFIX_TABLE (PREFIX_0F3A09
) },
7147 { PREFIX_TABLE (PREFIX_0F3A0A
) },
7148 { PREFIX_TABLE (PREFIX_0F3A0B
) },
7149 { PREFIX_TABLE (PREFIX_0F3A0C
) },
7150 { PREFIX_TABLE (PREFIX_0F3A0D
) },
7151 { PREFIX_TABLE (PREFIX_0F3A0E
) },
7152 { "palignr", { MX
, EM
, Ib
}, PREFIX_OPCODE
},
7158 { PREFIX_TABLE (PREFIX_0F3A14
) },
7159 { PREFIX_TABLE (PREFIX_0F3A15
) },
7160 { PREFIX_TABLE (PREFIX_0F3A16
) },
7161 { PREFIX_TABLE (PREFIX_0F3A17
) },
7172 { PREFIX_TABLE (PREFIX_0F3A20
) },
7173 { PREFIX_TABLE (PREFIX_0F3A21
) },
7174 { PREFIX_TABLE (PREFIX_0F3A22
) },
7208 { PREFIX_TABLE (PREFIX_0F3A40
) },
7209 { PREFIX_TABLE (PREFIX_0F3A41
) },
7210 { PREFIX_TABLE (PREFIX_0F3A42
) },
7212 { PREFIX_TABLE (PREFIX_0F3A44
) },
7244 { PREFIX_TABLE (PREFIX_0F3A60
) },
7245 { PREFIX_TABLE (PREFIX_0F3A61
) },
7246 { PREFIX_TABLE (PREFIX_0F3A62
) },
7247 { PREFIX_TABLE (PREFIX_0F3A63
) },
7365 { PREFIX_TABLE (PREFIX_0F3ACC
) },
7367 { PREFIX_TABLE (PREFIX_0F3ACE
) },
7368 { PREFIX_TABLE (PREFIX_0F3ACF
) },
7386 { PREFIX_TABLE (PREFIX_0F3ADF
) },
7426 static const struct dis386 xop_table
[][256] = {
7579 { "vpmacssww", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7580 { "vpmacsswd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7581 { "vpmacssdql", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7589 { "vpmacssdd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7590 { "vpmacssdqh", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7597 { "vpmacsww", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7598 { "vpmacswd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7599 { "vpmacsdql", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7607 { "vpmacsdd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7608 { "vpmacsdqh", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7612 { "vpcmov", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7613 { "vpperm", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7616 { "vpmadcsswd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7634 { "vpmadcswd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7646 { "vprotb", { XM
, Vex_2src_1
, Ib
}, 0 },
7647 { "vprotw", { XM
, Vex_2src_1
, Ib
}, 0 },
7648 { "vprotd", { XM
, Vex_2src_1
, Ib
}, 0 },
7649 { "vprotq", { XM
, Vex_2src_1
, Ib
}, 0 },
7659 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC
) },
7660 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD
) },
7661 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE
) },
7662 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF
) },
7695 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC
) },
7696 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED
) },
7697 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE
) },
7698 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF
) },
7722 { REG_TABLE (REG_XOP_TBM_01
) },
7723 { REG_TABLE (REG_XOP_TBM_02
) },
7741 { REG_TABLE (REG_XOP_LWPCB
) },
7865 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80
) },
7866 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81
) },
7867 { "vfrczss", { XM
, EXd
}, 0 },
7868 { "vfrczsd", { XM
, EXq
}, 0 },
7883 { "vprotb", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
7884 { "vprotw", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
7885 { "vprotd", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
7886 { "vprotq", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
7887 { "vpshlb", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
7888 { "vpshlw", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
7889 { "vpshld", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
7890 { "vpshlq", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
7892 { "vpshab", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
7893 { "vpshaw", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
7894 { "vpshad", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
7895 { "vpshaq", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
7938 { "vphaddbw", { XM
, EXxmm
}, 0 },
7939 { "vphaddbd", { XM
, EXxmm
}, 0 },
7940 { "vphaddbq", { XM
, EXxmm
}, 0 },
7943 { "vphaddwd", { XM
, EXxmm
}, 0 },
7944 { "vphaddwq", { XM
, EXxmm
}, 0 },
7949 { "vphadddq", { XM
, EXxmm
}, 0 },
7956 { "vphaddubw", { XM
, EXxmm
}, 0 },
7957 { "vphaddubd", { XM
, EXxmm
}, 0 },
7958 { "vphaddubq", { XM
, EXxmm
}, 0 },
7961 { "vphadduwd", { XM
, EXxmm
}, 0 },
7962 { "vphadduwq", { XM
, EXxmm
}, 0 },
7967 { "vphaddudq", { XM
, EXxmm
}, 0 },
7974 { "vphsubbw", { XM
, EXxmm
}, 0 },
7975 { "vphsubwd", { XM
, EXxmm
}, 0 },
7976 { "vphsubdq", { XM
, EXxmm
}, 0 },
8030 { "bextrS", { Gdq
, Edq
, Id
}, 0 },
8032 { REG_TABLE (REG_XOP_LWP
) },
8302 static const struct dis386 vex_table
[][256] = {
8324 { PREFIX_TABLE (PREFIX_VEX_0F10
) },
8325 { PREFIX_TABLE (PREFIX_VEX_0F11
) },
8326 { PREFIX_TABLE (PREFIX_VEX_0F12
) },
8327 { MOD_TABLE (MOD_VEX_0F13
) },
8328 { "vunpcklpX", { XM
, Vex
, EXx
}, PREFIX_OPCODE
},
8329 { "vunpckhpX", { XM
, Vex
, EXx
}, PREFIX_OPCODE
},
8330 { PREFIX_TABLE (PREFIX_VEX_0F16
) },
8331 { MOD_TABLE (MOD_VEX_0F17
) },
8351 { "vmovapX", { XM
, EXx
}, PREFIX_OPCODE
},
8352 { "vmovapX", { EXxS
, XM
}, PREFIX_OPCODE
},
8353 { PREFIX_TABLE (PREFIX_VEX_0F2A
) },
8354 { MOD_TABLE (MOD_VEX_0F2B
) },
8355 { PREFIX_TABLE (PREFIX_VEX_0F2C
) },
8356 { PREFIX_TABLE (PREFIX_VEX_0F2D
) },
8357 { PREFIX_TABLE (PREFIX_VEX_0F2E
) },
8358 { PREFIX_TABLE (PREFIX_VEX_0F2F
) },
8379 { PREFIX_TABLE (PREFIX_VEX_0F41
) },
8380 { PREFIX_TABLE (PREFIX_VEX_0F42
) },
8382 { PREFIX_TABLE (PREFIX_VEX_0F44
) },
8383 { PREFIX_TABLE (PREFIX_VEX_0F45
) },
8384 { PREFIX_TABLE (PREFIX_VEX_0F46
) },
8385 { PREFIX_TABLE (PREFIX_VEX_0F47
) },
8389 { PREFIX_TABLE (PREFIX_VEX_0F4A
) },
8390 { PREFIX_TABLE (PREFIX_VEX_0F4B
) },
8396 { MOD_TABLE (MOD_VEX_0F50
) },
8397 { PREFIX_TABLE (PREFIX_VEX_0F51
) },
8398 { PREFIX_TABLE (PREFIX_VEX_0F52
) },
8399 { PREFIX_TABLE (PREFIX_VEX_0F53
) },
8400 { "vandpX", { XM
, Vex
, EXx
}, PREFIX_OPCODE
},
8401 { "vandnpX", { XM
, Vex
, EXx
}, PREFIX_OPCODE
},
8402 { "vorpX", { XM
, Vex
, EXx
}, PREFIX_OPCODE
},
8403 { "vxorpX", { XM
, Vex
, EXx
}, PREFIX_OPCODE
},
8405 { PREFIX_TABLE (PREFIX_VEX_0F58
) },
8406 { PREFIX_TABLE (PREFIX_VEX_0F59
) },
8407 { PREFIX_TABLE (PREFIX_VEX_0F5A
) },
8408 { PREFIX_TABLE (PREFIX_VEX_0F5B
) },
8409 { PREFIX_TABLE (PREFIX_VEX_0F5C
) },
8410 { PREFIX_TABLE (PREFIX_VEX_0F5D
) },
8411 { PREFIX_TABLE (PREFIX_VEX_0F5E
) },
8412 { PREFIX_TABLE (PREFIX_VEX_0F5F
) },
8414 { PREFIX_TABLE (PREFIX_VEX_0F60
) },
8415 { PREFIX_TABLE (PREFIX_VEX_0F61
) },
8416 { PREFIX_TABLE (PREFIX_VEX_0F62
) },
8417 { PREFIX_TABLE (PREFIX_VEX_0F63
) },
8418 { PREFIX_TABLE (PREFIX_VEX_0F64
) },
8419 { PREFIX_TABLE (PREFIX_VEX_0F65
) },
8420 { PREFIX_TABLE (PREFIX_VEX_0F66
) },
8421 { PREFIX_TABLE (PREFIX_VEX_0F67
) },
8423 { PREFIX_TABLE (PREFIX_VEX_0F68
) },
8424 { PREFIX_TABLE (PREFIX_VEX_0F69
) },
8425 { PREFIX_TABLE (PREFIX_VEX_0F6A
) },
8426 { PREFIX_TABLE (PREFIX_VEX_0F6B
) },
8427 { PREFIX_TABLE (PREFIX_VEX_0F6C
) },
8428 { PREFIX_TABLE (PREFIX_VEX_0F6D
) },
8429 { PREFIX_TABLE (PREFIX_VEX_0F6E
) },
8430 { PREFIX_TABLE (PREFIX_VEX_0F6F
) },
8432 { PREFIX_TABLE (PREFIX_VEX_0F70
) },
8433 { REG_TABLE (REG_VEX_0F71
) },
8434 { REG_TABLE (REG_VEX_0F72
) },
8435 { REG_TABLE (REG_VEX_0F73
) },
8436 { PREFIX_TABLE (PREFIX_VEX_0F74
) },
8437 { PREFIX_TABLE (PREFIX_VEX_0F75
) },
8438 { PREFIX_TABLE (PREFIX_VEX_0F76
) },
8439 { PREFIX_TABLE (PREFIX_VEX_0F77
) },
8445 { PREFIX_TABLE (PREFIX_VEX_0F7C
) },
8446 { PREFIX_TABLE (PREFIX_VEX_0F7D
) },
8447 { PREFIX_TABLE (PREFIX_VEX_0F7E
) },
8448 { PREFIX_TABLE (PREFIX_VEX_0F7F
) },
8468 { PREFIX_TABLE (PREFIX_VEX_0F90
) },
8469 { PREFIX_TABLE (PREFIX_VEX_0F91
) },
8470 { PREFIX_TABLE (PREFIX_VEX_0F92
) },
8471 { PREFIX_TABLE (PREFIX_VEX_0F93
) },
8477 { PREFIX_TABLE (PREFIX_VEX_0F98
) },
8478 { PREFIX_TABLE (PREFIX_VEX_0F99
) },
8501 { REG_TABLE (REG_VEX_0FAE
) },
8524 { PREFIX_TABLE (PREFIX_VEX_0FC2
) },
8526 { PREFIX_TABLE (PREFIX_VEX_0FC4
) },
8527 { PREFIX_TABLE (PREFIX_VEX_0FC5
) },
8528 { "vshufpX", { XM
, Vex
, EXx
, Ib
}, PREFIX_OPCODE
},
8540 { PREFIX_TABLE (PREFIX_VEX_0FD0
) },
8541 { PREFIX_TABLE (PREFIX_VEX_0FD1
) },
8542 { PREFIX_TABLE (PREFIX_VEX_0FD2
) },
8543 { PREFIX_TABLE (PREFIX_VEX_0FD3
) },
8544 { PREFIX_TABLE (PREFIX_VEX_0FD4
) },
8545 { PREFIX_TABLE (PREFIX_VEX_0FD5
) },
8546 { PREFIX_TABLE (PREFIX_VEX_0FD6
) },
8547 { PREFIX_TABLE (PREFIX_VEX_0FD7
) },
8549 { PREFIX_TABLE (PREFIX_VEX_0FD8
) },
8550 { PREFIX_TABLE (PREFIX_VEX_0FD9
) },
8551 { PREFIX_TABLE (PREFIX_VEX_0FDA
) },
8552 { PREFIX_TABLE (PREFIX_VEX_0FDB
) },
8553 { PREFIX_TABLE (PREFIX_VEX_0FDC
) },
8554 { PREFIX_TABLE (PREFIX_VEX_0FDD
) },
8555 { PREFIX_TABLE (PREFIX_VEX_0FDE
) },
8556 { PREFIX_TABLE (PREFIX_VEX_0FDF
) },
8558 { PREFIX_TABLE (PREFIX_VEX_0FE0
) },
8559 { PREFIX_TABLE (PREFIX_VEX_0FE1
) },
8560 { PREFIX_TABLE (PREFIX_VEX_0FE2
) },
8561 { PREFIX_TABLE (PREFIX_VEX_0FE3
) },
8562 { PREFIX_TABLE (PREFIX_VEX_0FE4
) },
8563 { PREFIX_TABLE (PREFIX_VEX_0FE5
) },
8564 { PREFIX_TABLE (PREFIX_VEX_0FE6
) },
8565 { PREFIX_TABLE (PREFIX_VEX_0FE7
) },
8567 { PREFIX_TABLE (PREFIX_VEX_0FE8
) },
8568 { PREFIX_TABLE (PREFIX_VEX_0FE9
) },
8569 { PREFIX_TABLE (PREFIX_VEX_0FEA
) },
8570 { PREFIX_TABLE (PREFIX_VEX_0FEB
) },
8571 { PREFIX_TABLE (PREFIX_VEX_0FEC
) },
8572 { PREFIX_TABLE (PREFIX_VEX_0FED
) },
8573 { PREFIX_TABLE (PREFIX_VEX_0FEE
) },
8574 { PREFIX_TABLE (PREFIX_VEX_0FEF
) },
8576 { PREFIX_TABLE (PREFIX_VEX_0FF0
) },
8577 { PREFIX_TABLE (PREFIX_VEX_0FF1
) },
8578 { PREFIX_TABLE (PREFIX_VEX_0FF2
) },
8579 { PREFIX_TABLE (PREFIX_VEX_0FF3
) },
8580 { PREFIX_TABLE (PREFIX_VEX_0FF4
) },
8581 { PREFIX_TABLE (PREFIX_VEX_0FF5
) },
8582 { PREFIX_TABLE (PREFIX_VEX_0FF6
) },
8583 { PREFIX_TABLE (PREFIX_VEX_0FF7
) },
8585 { PREFIX_TABLE (PREFIX_VEX_0FF8
) },
8586 { PREFIX_TABLE (PREFIX_VEX_0FF9
) },
8587 { PREFIX_TABLE (PREFIX_VEX_0FFA
) },
8588 { PREFIX_TABLE (PREFIX_VEX_0FFB
) },
8589 { PREFIX_TABLE (PREFIX_VEX_0FFC
) },
8590 { PREFIX_TABLE (PREFIX_VEX_0FFD
) },
8591 { PREFIX_TABLE (PREFIX_VEX_0FFE
) },
8597 { PREFIX_TABLE (PREFIX_VEX_0F3800
) },
8598 { PREFIX_TABLE (PREFIX_VEX_0F3801
) },
8599 { PREFIX_TABLE (PREFIX_VEX_0F3802
) },
8600 { PREFIX_TABLE (PREFIX_VEX_0F3803
) },
8601 { PREFIX_TABLE (PREFIX_VEX_0F3804
) },
8602 { PREFIX_TABLE (PREFIX_VEX_0F3805
) },
8603 { PREFIX_TABLE (PREFIX_VEX_0F3806
) },
8604 { PREFIX_TABLE (PREFIX_VEX_0F3807
) },
8606 { PREFIX_TABLE (PREFIX_VEX_0F3808
) },
8607 { PREFIX_TABLE (PREFIX_VEX_0F3809
) },
8608 { PREFIX_TABLE (PREFIX_VEX_0F380A
) },
8609 { PREFIX_TABLE (PREFIX_VEX_0F380B
) },
8610 { PREFIX_TABLE (PREFIX_VEX_0F380C
) },
8611 { PREFIX_TABLE (PREFIX_VEX_0F380D
) },
8612 { PREFIX_TABLE (PREFIX_VEX_0F380E
) },
8613 { PREFIX_TABLE (PREFIX_VEX_0F380F
) },
8618 { PREFIX_TABLE (PREFIX_VEX_0F3813
) },
8621 { PREFIX_TABLE (PREFIX_VEX_0F3816
) },
8622 { PREFIX_TABLE (PREFIX_VEX_0F3817
) },
8624 { PREFIX_TABLE (PREFIX_VEX_0F3818
) },
8625 { PREFIX_TABLE (PREFIX_VEX_0F3819
) },
8626 { PREFIX_TABLE (PREFIX_VEX_0F381A
) },
8628 { PREFIX_TABLE (PREFIX_VEX_0F381C
) },
8629 { PREFIX_TABLE (PREFIX_VEX_0F381D
) },
8630 { PREFIX_TABLE (PREFIX_VEX_0F381E
) },
8633 { PREFIX_TABLE (PREFIX_VEX_0F3820
) },
8634 { PREFIX_TABLE (PREFIX_VEX_0F3821
) },
8635 { PREFIX_TABLE (PREFIX_VEX_0F3822
) },
8636 { PREFIX_TABLE (PREFIX_VEX_0F3823
) },
8637 { PREFIX_TABLE (PREFIX_VEX_0F3824
) },
8638 { PREFIX_TABLE (PREFIX_VEX_0F3825
) },
8642 { PREFIX_TABLE (PREFIX_VEX_0F3828
) },
8643 { PREFIX_TABLE (PREFIX_VEX_0F3829
) },
8644 { PREFIX_TABLE (PREFIX_VEX_0F382A
) },
8645 { PREFIX_TABLE (PREFIX_VEX_0F382B
) },
8646 { PREFIX_TABLE (PREFIX_VEX_0F382C
) },
8647 { PREFIX_TABLE (PREFIX_VEX_0F382D
) },
8648 { PREFIX_TABLE (PREFIX_VEX_0F382E
) },
8649 { PREFIX_TABLE (PREFIX_VEX_0F382F
) },
8651 { PREFIX_TABLE (PREFIX_VEX_0F3830
) },
8652 { PREFIX_TABLE (PREFIX_VEX_0F3831
) },
8653 { PREFIX_TABLE (PREFIX_VEX_0F3832
) },
8654 { PREFIX_TABLE (PREFIX_VEX_0F3833
) },
8655 { PREFIX_TABLE (PREFIX_VEX_0F3834
) },
8656 { PREFIX_TABLE (PREFIX_VEX_0F3835
) },
8657 { PREFIX_TABLE (PREFIX_VEX_0F3836
) },
8658 { PREFIX_TABLE (PREFIX_VEX_0F3837
) },
8660 { PREFIX_TABLE (PREFIX_VEX_0F3838
) },
8661 { PREFIX_TABLE (PREFIX_VEX_0F3839
) },
8662 { PREFIX_TABLE (PREFIX_VEX_0F383A
) },
8663 { PREFIX_TABLE (PREFIX_VEX_0F383B
) },
8664 { PREFIX_TABLE (PREFIX_VEX_0F383C
) },
8665 { PREFIX_TABLE (PREFIX_VEX_0F383D
) },
8666 { PREFIX_TABLE (PREFIX_VEX_0F383E
) },
8667 { PREFIX_TABLE (PREFIX_VEX_0F383F
) },
8669 { PREFIX_TABLE (PREFIX_VEX_0F3840
) },
8670 { PREFIX_TABLE (PREFIX_VEX_0F3841
) },
8674 { PREFIX_TABLE (PREFIX_VEX_0F3845
) },
8675 { PREFIX_TABLE (PREFIX_VEX_0F3846
) },
8676 { PREFIX_TABLE (PREFIX_VEX_0F3847
) },
8696 { PREFIX_TABLE (PREFIX_VEX_0F3858
) },
8697 { PREFIX_TABLE (PREFIX_VEX_0F3859
) },
8698 { PREFIX_TABLE (PREFIX_VEX_0F385A
) },
8732 { PREFIX_TABLE (PREFIX_VEX_0F3878
) },
8733 { PREFIX_TABLE (PREFIX_VEX_0F3879
) },
8754 { PREFIX_TABLE (PREFIX_VEX_0F388C
) },
8756 { PREFIX_TABLE (PREFIX_VEX_0F388E
) },
8759 { PREFIX_TABLE (PREFIX_VEX_0F3890
) },
8760 { PREFIX_TABLE (PREFIX_VEX_0F3891
) },
8761 { PREFIX_TABLE (PREFIX_VEX_0F3892
) },
8762 { PREFIX_TABLE (PREFIX_VEX_0F3893
) },
8765 { PREFIX_TABLE (PREFIX_VEX_0F3896
) },
8766 { PREFIX_TABLE (PREFIX_VEX_0F3897
) },
8768 { PREFIX_TABLE (PREFIX_VEX_0F3898
) },
8769 { PREFIX_TABLE (PREFIX_VEX_0F3899
) },
8770 { PREFIX_TABLE (PREFIX_VEX_0F389A
) },
8771 { PREFIX_TABLE (PREFIX_VEX_0F389B
) },
8772 { PREFIX_TABLE (PREFIX_VEX_0F389C
) },
8773 { PREFIX_TABLE (PREFIX_VEX_0F389D
) },
8774 { PREFIX_TABLE (PREFIX_VEX_0F389E
) },
8775 { PREFIX_TABLE (PREFIX_VEX_0F389F
) },
8783 { PREFIX_TABLE (PREFIX_VEX_0F38A6
) },
8784 { PREFIX_TABLE (PREFIX_VEX_0F38A7
) },
8786 { PREFIX_TABLE (PREFIX_VEX_0F38A8
) },
8787 { PREFIX_TABLE (PREFIX_VEX_0F38A9
) },
8788 { PREFIX_TABLE (PREFIX_VEX_0F38AA
) },
8789 { PREFIX_TABLE (PREFIX_VEX_0F38AB
) },
8790 { PREFIX_TABLE (PREFIX_VEX_0F38AC
) },
8791 { PREFIX_TABLE (PREFIX_VEX_0F38AD
) },
8792 { PREFIX_TABLE (PREFIX_VEX_0F38AE
) },
8793 { PREFIX_TABLE (PREFIX_VEX_0F38AF
) },
8801 { PREFIX_TABLE (PREFIX_VEX_0F38B6
) },
8802 { PREFIX_TABLE (PREFIX_VEX_0F38B7
) },
8804 { PREFIX_TABLE (PREFIX_VEX_0F38B8
) },
8805 { PREFIX_TABLE (PREFIX_VEX_0F38B9
) },
8806 { PREFIX_TABLE (PREFIX_VEX_0F38BA
) },
8807 { PREFIX_TABLE (PREFIX_VEX_0F38BB
) },
8808 { PREFIX_TABLE (PREFIX_VEX_0F38BC
) },
8809 { PREFIX_TABLE (PREFIX_VEX_0F38BD
) },
8810 { PREFIX_TABLE (PREFIX_VEX_0F38BE
) },
8811 { PREFIX_TABLE (PREFIX_VEX_0F38BF
) },
8829 { PREFIX_TABLE (PREFIX_VEX_0F38CF
) },
8843 { PREFIX_TABLE (PREFIX_VEX_0F38DB
) },
8844 { PREFIX_TABLE (PREFIX_VEX_0F38DC
) },
8845 { PREFIX_TABLE (PREFIX_VEX_0F38DD
) },
8846 { PREFIX_TABLE (PREFIX_VEX_0F38DE
) },
8847 { PREFIX_TABLE (PREFIX_VEX_0F38DF
) },
8869 { PREFIX_TABLE (PREFIX_VEX_0F38F2
) },
8870 { REG_TABLE (REG_VEX_0F38F3
) },
8872 { PREFIX_TABLE (PREFIX_VEX_0F38F5
) },
8873 { PREFIX_TABLE (PREFIX_VEX_0F38F6
) },
8874 { PREFIX_TABLE (PREFIX_VEX_0F38F7
) },
8888 { PREFIX_TABLE (PREFIX_VEX_0F3A00
) },
8889 { PREFIX_TABLE (PREFIX_VEX_0F3A01
) },
8890 { PREFIX_TABLE (PREFIX_VEX_0F3A02
) },
8892 { PREFIX_TABLE (PREFIX_VEX_0F3A04
) },
8893 { PREFIX_TABLE (PREFIX_VEX_0F3A05
) },
8894 { PREFIX_TABLE (PREFIX_VEX_0F3A06
) },
8897 { PREFIX_TABLE (PREFIX_VEX_0F3A08
) },
8898 { PREFIX_TABLE (PREFIX_VEX_0F3A09
) },
8899 { PREFIX_TABLE (PREFIX_VEX_0F3A0A
) },
8900 { PREFIX_TABLE (PREFIX_VEX_0F3A0B
) },
8901 { PREFIX_TABLE (PREFIX_VEX_0F3A0C
) },
8902 { PREFIX_TABLE (PREFIX_VEX_0F3A0D
) },
8903 { PREFIX_TABLE (PREFIX_VEX_0F3A0E
) },
8904 { PREFIX_TABLE (PREFIX_VEX_0F3A0F
) },
8910 { PREFIX_TABLE (PREFIX_VEX_0F3A14
) },
8911 { PREFIX_TABLE (PREFIX_VEX_0F3A15
) },
8912 { PREFIX_TABLE (PREFIX_VEX_0F3A16
) },
8913 { PREFIX_TABLE (PREFIX_VEX_0F3A17
) },
8915 { PREFIX_TABLE (PREFIX_VEX_0F3A18
) },
8916 { PREFIX_TABLE (PREFIX_VEX_0F3A19
) },
8920 { PREFIX_TABLE (PREFIX_VEX_0F3A1D
) },
8924 { PREFIX_TABLE (PREFIX_VEX_0F3A20
) },
8925 { PREFIX_TABLE (PREFIX_VEX_0F3A21
) },
8926 { PREFIX_TABLE (PREFIX_VEX_0F3A22
) },
8942 { PREFIX_TABLE (PREFIX_VEX_0F3A30
) },
8943 { PREFIX_TABLE (PREFIX_VEX_0F3A31
) },
8944 { PREFIX_TABLE (PREFIX_VEX_0F3A32
) },
8945 { PREFIX_TABLE (PREFIX_VEX_0F3A33
) },
8951 { PREFIX_TABLE (PREFIX_VEX_0F3A38
) },
8952 { PREFIX_TABLE (PREFIX_VEX_0F3A39
) },
8960 { PREFIX_TABLE (PREFIX_VEX_0F3A40
) },
8961 { PREFIX_TABLE (PREFIX_VEX_0F3A41
) },
8962 { PREFIX_TABLE (PREFIX_VEX_0F3A42
) },
8964 { PREFIX_TABLE (PREFIX_VEX_0F3A44
) },
8966 { PREFIX_TABLE (PREFIX_VEX_0F3A46
) },
8969 { PREFIX_TABLE (PREFIX_VEX_0F3A48
) },
8970 { PREFIX_TABLE (PREFIX_VEX_0F3A49
) },
8971 { PREFIX_TABLE (PREFIX_VEX_0F3A4A
) },
8972 { PREFIX_TABLE (PREFIX_VEX_0F3A4B
) },
8973 { PREFIX_TABLE (PREFIX_VEX_0F3A4C
) },
8991 { PREFIX_TABLE (PREFIX_VEX_0F3A5C
) },
8992 { PREFIX_TABLE (PREFIX_VEX_0F3A5D
) },
8993 { PREFIX_TABLE (PREFIX_VEX_0F3A5E
) },
8994 { PREFIX_TABLE (PREFIX_VEX_0F3A5F
) },
8996 { PREFIX_TABLE (PREFIX_VEX_0F3A60
) },
8997 { PREFIX_TABLE (PREFIX_VEX_0F3A61
) },
8998 { PREFIX_TABLE (PREFIX_VEX_0F3A62
) },
8999 { PREFIX_TABLE (PREFIX_VEX_0F3A63
) },
9005 { PREFIX_TABLE (PREFIX_VEX_0F3A68
) },
9006 { PREFIX_TABLE (PREFIX_VEX_0F3A69
) },
9007 { PREFIX_TABLE (PREFIX_VEX_0F3A6A
) },
9008 { PREFIX_TABLE (PREFIX_VEX_0F3A6B
) },
9009 { PREFIX_TABLE (PREFIX_VEX_0F3A6C
) },
9010 { PREFIX_TABLE (PREFIX_VEX_0F3A6D
) },
9011 { PREFIX_TABLE (PREFIX_VEX_0F3A6E
) },
9012 { PREFIX_TABLE (PREFIX_VEX_0F3A6F
) },
9023 { PREFIX_TABLE (PREFIX_VEX_0F3A78
) },
9024 { PREFIX_TABLE (PREFIX_VEX_0F3A79
) },
9025 { PREFIX_TABLE (PREFIX_VEX_0F3A7A
) },
9026 { PREFIX_TABLE (PREFIX_VEX_0F3A7B
) },
9027 { PREFIX_TABLE (PREFIX_VEX_0F3A7C
) },
9028 { PREFIX_TABLE (PREFIX_VEX_0F3A7D
) },
9029 { PREFIX_TABLE (PREFIX_VEX_0F3A7E
) },
9030 { PREFIX_TABLE (PREFIX_VEX_0F3A7F
) },
9119 { PREFIX_TABLE(PREFIX_VEX_0F3ACE
) },
9120 { PREFIX_TABLE(PREFIX_VEX_0F3ACF
) },
9138 { PREFIX_TABLE (PREFIX_VEX_0F3ADF
) },
9158 { PREFIX_TABLE (PREFIX_VEX_0F3AF0
) },
9178 #include "i386-dis-evex.h"
9180 static const struct dis386 vex_len_table
[][2] = {
9181 /* VEX_LEN_0F12_P_0_M_0 / VEX_LEN_0F12_P_2_M_0 */
9183 { "vmovlpX", { XM
, Vex128
, EXq
}, 0 },
9186 /* VEX_LEN_0F12_P_0_M_1 */
9188 { "vmovhlps", { XM
, Vex128
, EXq
}, 0 },
9191 /* VEX_LEN_0F13_M_0 */
9193 { "vmovlpX", { EXq
, XM
}, PREFIX_OPCODE
},
9196 /* VEX_LEN_0F16_P_0_M_0 / VEX_LEN_0F16_P_2_M_0 */
9198 { "vmovhpX", { XM
, Vex128
, EXq
}, 0 },
9201 /* VEX_LEN_0F16_P_0_M_1 */
9203 { "vmovlhps", { XM
, Vex128
, EXq
}, 0 },
9206 /* VEX_LEN_0F17_M_0 */
9208 { "vmovhpX", { EXq
, XM
}, PREFIX_OPCODE
},
9211 /* VEX_LEN_0F41_P_0 */
9214 { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1
) },
9216 /* VEX_LEN_0F41_P_2 */
9219 { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1
) },
9221 /* VEX_LEN_0F42_P_0 */
9224 { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1
) },
9226 /* VEX_LEN_0F42_P_2 */
9229 { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1
) },
9231 /* VEX_LEN_0F44_P_0 */
9233 { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0
) },
9235 /* VEX_LEN_0F44_P_2 */
9237 { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0
) },
9239 /* VEX_LEN_0F45_P_0 */
9242 { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1
) },
9244 /* VEX_LEN_0F45_P_2 */
9247 { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1
) },
9249 /* VEX_LEN_0F46_P_0 */
9252 { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1
) },
9254 /* VEX_LEN_0F46_P_2 */
9257 { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1
) },
9259 /* VEX_LEN_0F47_P_0 */
9262 { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1
) },
9264 /* VEX_LEN_0F47_P_2 */
9267 { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1
) },
9269 /* VEX_LEN_0F4A_P_0 */
9272 { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1
) },
9274 /* VEX_LEN_0F4A_P_2 */
9277 { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1
) },
9279 /* VEX_LEN_0F4B_P_0 */
9282 { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1
) },
9284 /* VEX_LEN_0F4B_P_2 */
9287 { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1
) },
9290 /* VEX_LEN_0F6E_P_2 */
9292 { "vmovK", { XMScalar
, Edq
}, 0 },
9295 /* VEX_LEN_0F77_P_1 */
9297 { "vzeroupper", { XX
}, 0 },
9298 { "vzeroall", { XX
}, 0 },
9301 /* VEX_LEN_0F7E_P_1 */
9303 { "vmovq", { XMScalar
, EXxmm_mq
}, 0 },
9306 /* VEX_LEN_0F7E_P_2 */
9308 { "vmovK", { Edq
, XMScalar
}, 0 },
9311 /* VEX_LEN_0F90_P_0 */
9313 { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0
) },
9316 /* VEX_LEN_0F90_P_2 */
9318 { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0
) },
9321 /* VEX_LEN_0F91_P_0 */
9323 { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0
) },
9326 /* VEX_LEN_0F91_P_2 */
9328 { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0
) },
9331 /* VEX_LEN_0F92_P_0 */
9333 { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0
) },
9336 /* VEX_LEN_0F92_P_2 */
9338 { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0
) },
9341 /* VEX_LEN_0F92_P_3 */
9343 { MOD_TABLE (MOD_VEX_0F92_P_3_LEN_0
) },
9346 /* VEX_LEN_0F93_P_0 */
9348 { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0
) },
9351 /* VEX_LEN_0F93_P_2 */
9353 { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0
) },
9356 /* VEX_LEN_0F93_P_3 */
9358 { MOD_TABLE (MOD_VEX_0F93_P_3_LEN_0
) },
9361 /* VEX_LEN_0F98_P_0 */
9363 { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0
) },
9366 /* VEX_LEN_0F98_P_2 */
9368 { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0
) },
9371 /* VEX_LEN_0F99_P_0 */
9373 { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0
) },
9376 /* VEX_LEN_0F99_P_2 */
9378 { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0
) },
9381 /* VEX_LEN_0FAE_R_2_M_0 */
9383 { "vldmxcsr", { Md
}, 0 },
9386 /* VEX_LEN_0FAE_R_3_M_0 */
9388 { "vstmxcsr", { Md
}, 0 },
9391 /* VEX_LEN_0FC4_P_2 */
9393 { "vpinsrw", { XM
, Vex128
, Edqw
, Ib
}, 0 },
9396 /* VEX_LEN_0FC5_P_2 */
9398 { "vpextrw", { Gdq
, XS
, Ib
}, 0 },
9401 /* VEX_LEN_0FD6_P_2 */
9403 { "vmovq", { EXqVexScalarS
, XMScalar
}, 0 },
9406 /* VEX_LEN_0FF7_P_2 */
9408 { "vmaskmovdqu", { XM
, XS
}, 0 },
9411 /* VEX_LEN_0F3816_P_2 */
9414 { VEX_W_TABLE (VEX_W_0F3816_P_2
) },
9417 /* VEX_LEN_0F3819_P_2 */
9420 { VEX_W_TABLE (VEX_W_0F3819_P_2
) },
9423 /* VEX_LEN_0F381A_P_2_M_0 */
9426 { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0
) },
9429 /* VEX_LEN_0F3836_P_2 */
9432 { VEX_W_TABLE (VEX_W_0F3836_P_2
) },
9435 /* VEX_LEN_0F3841_P_2 */
9437 { "vphminposuw", { XM
, EXx
}, 0 },
9440 /* VEX_LEN_0F385A_P_2_M_0 */
9443 { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0
) },
9446 /* VEX_LEN_0F38DB_P_2 */
9448 { "vaesimc", { XM
, EXx
}, 0 },
9451 /* VEX_LEN_0F38F2_P_0 */
9453 { "andnS", { Gdq
, VexGdq
, Edq
}, 0 },
9456 /* VEX_LEN_0F38F3_R_1_P_0 */
9458 { "blsrS", { VexGdq
, Edq
}, 0 },
9461 /* VEX_LEN_0F38F3_R_2_P_0 */
9463 { "blsmskS", { VexGdq
, Edq
}, 0 },
9466 /* VEX_LEN_0F38F3_R_3_P_0 */
9468 { "blsiS", { VexGdq
, Edq
}, 0 },
9471 /* VEX_LEN_0F38F5_P_0 */
9473 { "bzhiS", { Gdq
, Edq
, VexGdq
}, 0 },
9476 /* VEX_LEN_0F38F5_P_1 */
9478 { "pextS", { Gdq
, VexGdq
, Edq
}, 0 },
9481 /* VEX_LEN_0F38F5_P_3 */
9483 { "pdepS", { Gdq
, VexGdq
, Edq
}, 0 },
9486 /* VEX_LEN_0F38F6_P_3 */
9488 { "mulxS", { Gdq
, VexGdq
, Edq
}, 0 },
9491 /* VEX_LEN_0F38F7_P_0 */
9493 { "bextrS", { Gdq
, Edq
, VexGdq
}, 0 },
9496 /* VEX_LEN_0F38F7_P_1 */
9498 { "sarxS", { Gdq
, Edq
, VexGdq
}, 0 },
9501 /* VEX_LEN_0F38F7_P_2 */
9503 { "shlxS", { Gdq
, Edq
, VexGdq
}, 0 },
9506 /* VEX_LEN_0F38F7_P_3 */
9508 { "shrxS", { Gdq
, Edq
, VexGdq
}, 0 },
9511 /* VEX_LEN_0F3A00_P_2 */
9514 { VEX_W_TABLE (VEX_W_0F3A00_P_2
) },
9517 /* VEX_LEN_0F3A01_P_2 */
9520 { VEX_W_TABLE (VEX_W_0F3A01_P_2
) },
9523 /* VEX_LEN_0F3A06_P_2 */
9526 { VEX_W_TABLE (VEX_W_0F3A06_P_2
) },
9529 /* VEX_LEN_0F3A14_P_2 */
9531 { "vpextrb", { Edqb
, XM
, Ib
}, 0 },
9534 /* VEX_LEN_0F3A15_P_2 */
9536 { "vpextrw", { Edqw
, XM
, Ib
}, 0 },
9539 /* VEX_LEN_0F3A16_P_2 */
9541 { "vpextrK", { Edq
, XM
, Ib
}, 0 },
9544 /* VEX_LEN_0F3A17_P_2 */
9546 { "vextractps", { Edqd
, XM
, Ib
}, 0 },
9549 /* VEX_LEN_0F3A18_P_2 */
9552 { VEX_W_TABLE (VEX_W_0F3A18_P_2
) },
9555 /* VEX_LEN_0F3A19_P_2 */
9558 { VEX_W_TABLE (VEX_W_0F3A19_P_2
) },
9561 /* VEX_LEN_0F3A20_P_2 */
9563 { "vpinsrb", { XM
, Vex128
, Edqb
, Ib
}, 0 },
9566 /* VEX_LEN_0F3A21_P_2 */
9568 { "vinsertps", { XM
, Vex128
, EXd
, Ib
}, 0 },
9571 /* VEX_LEN_0F3A22_P_2 */
9573 { "vpinsrK", { XM
, Vex128
, Edq
, Ib
}, 0 },
9576 /* VEX_LEN_0F3A30_P_2 */
9578 { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0
) },
9581 /* VEX_LEN_0F3A31_P_2 */
9583 { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0
) },
9586 /* VEX_LEN_0F3A32_P_2 */
9588 { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0
) },
9591 /* VEX_LEN_0F3A33_P_2 */
9593 { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0
) },
9596 /* VEX_LEN_0F3A38_P_2 */
9599 { VEX_W_TABLE (VEX_W_0F3A38_P_2
) },
9602 /* VEX_LEN_0F3A39_P_2 */
9605 { VEX_W_TABLE (VEX_W_0F3A39_P_2
) },
9608 /* VEX_LEN_0F3A41_P_2 */
9610 { "vdppd", { XM
, Vex128
, EXx
, Ib
}, 0 },
9613 /* VEX_LEN_0F3A46_P_2 */
9616 { VEX_W_TABLE (VEX_W_0F3A46_P_2
) },
9619 /* VEX_LEN_0F3A60_P_2 */
9621 { "vpcmpestrm", { XM
, { PCMPESTR_Fixup
, x_mode
}, Ib
}, 0 },
9624 /* VEX_LEN_0F3A61_P_2 */
9626 { "vpcmpestri", { XM
, { PCMPESTR_Fixup
, x_mode
}, Ib
}, 0 },
9629 /* VEX_LEN_0F3A62_P_2 */
9631 { "vpcmpistrm", { XM
, EXx
, Ib
}, 0 },
9634 /* VEX_LEN_0F3A63_P_2 */
9636 { "vpcmpistri", { XM
, EXx
, Ib
}, 0 },
9639 /* VEX_LEN_0F3A6A_P_2 */
9641 { "vfmaddss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
}, 0 },
9644 /* VEX_LEN_0F3A6B_P_2 */
9646 { "vfmaddsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
}, 0 },
9649 /* VEX_LEN_0F3A6E_P_2 */
9651 { "vfmsubss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
}, 0 },
9654 /* VEX_LEN_0F3A6F_P_2 */
9656 { "vfmsubsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
}, 0 },
9659 /* VEX_LEN_0F3A7A_P_2 */
9661 { "vfnmaddss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
}, 0 },
9664 /* VEX_LEN_0F3A7B_P_2 */
9666 { "vfnmaddsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
}, 0 },
9669 /* VEX_LEN_0F3A7E_P_2 */
9671 { "vfnmsubss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
}, 0 },
9674 /* VEX_LEN_0F3A7F_P_2 */
9676 { "vfnmsubsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
}, 0 },
9679 /* VEX_LEN_0F3ADF_P_2 */
9681 { "vaeskeygenassist", { XM
, EXx
, Ib
}, 0 },
9684 /* VEX_LEN_0F3AF0_P_3 */
9686 { "rorxS", { Gdq
, Edq
, Ib
}, 0 },
9689 /* VEX_LEN_0FXOP_08_CC */
9691 { "vpcomb", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9694 /* VEX_LEN_0FXOP_08_CD */
9696 { "vpcomw", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9699 /* VEX_LEN_0FXOP_08_CE */
9701 { "vpcomd", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9704 /* VEX_LEN_0FXOP_08_CF */
9706 { "vpcomq", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9709 /* VEX_LEN_0FXOP_08_EC */
9711 { "vpcomub", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9714 /* VEX_LEN_0FXOP_08_ED */
9716 { "vpcomuw", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9719 /* VEX_LEN_0FXOP_08_EE */
9721 { "vpcomud", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9724 /* VEX_LEN_0FXOP_08_EF */
9726 { "vpcomuq", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9729 /* VEX_LEN_0FXOP_09_80 */
9731 { "vfrczps", { XM
, EXxmm
}, 0 },
9732 { "vfrczps", { XM
, EXymmq
}, 0 },
9735 /* VEX_LEN_0FXOP_09_81 */
9737 { "vfrczpd", { XM
, EXxmm
}, 0 },
9738 { "vfrczpd", { XM
, EXymmq
}, 0 },
9742 #include "i386-dis-evex-len.h"
9744 static const struct dis386 vex_w_table
[][2] = {
9746 /* VEX_W_0F41_P_0_LEN_1 */
9747 { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1
) },
9748 { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1
) },
9751 /* VEX_W_0F41_P_2_LEN_1 */
9752 { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1
) },
9753 { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1
) }
9756 /* VEX_W_0F42_P_0_LEN_1 */
9757 { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1
) },
9758 { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1
) },
9761 /* VEX_W_0F42_P_2_LEN_1 */
9762 { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1
) },
9763 { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1
) },
9766 /* VEX_W_0F44_P_0_LEN_0 */
9767 { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1
) },
9768 { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1
) },
9771 /* VEX_W_0F44_P_2_LEN_0 */
9772 { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1
) },
9773 { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1
) },
9776 /* VEX_W_0F45_P_0_LEN_1 */
9777 { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1
) },
9778 { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1
) },
9781 /* VEX_W_0F45_P_2_LEN_1 */
9782 { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1
) },
9783 { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1
) },
9786 /* VEX_W_0F46_P_0_LEN_1 */
9787 { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1
) },
9788 { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1
) },
9791 /* VEX_W_0F46_P_2_LEN_1 */
9792 { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1
) },
9793 { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1
) },
9796 /* VEX_W_0F47_P_0_LEN_1 */
9797 { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1
) },
9798 { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1
) },
9801 /* VEX_W_0F47_P_2_LEN_1 */
9802 { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1
) },
9803 { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1
) },
9806 /* VEX_W_0F4A_P_0_LEN_1 */
9807 { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1
) },
9808 { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1
) },
9811 /* VEX_W_0F4A_P_2_LEN_1 */
9812 { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1
) },
9813 { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1
) },
9816 /* VEX_W_0F4B_P_0_LEN_1 */
9817 { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1
) },
9818 { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1
) },
9821 /* VEX_W_0F4B_P_2_LEN_1 */
9822 { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1
) },
9825 /* VEX_W_0F90_P_0_LEN_0 */
9826 { "kmovw", { MaskG
, MaskE
}, 0 },
9827 { "kmovq", { MaskG
, MaskE
}, 0 },
9830 /* VEX_W_0F90_P_2_LEN_0 */
9831 { "kmovb", { MaskG
, MaskBDE
}, 0 },
9832 { "kmovd", { MaskG
, MaskBDE
}, 0 },
9835 /* VEX_W_0F91_P_0_LEN_0 */
9836 { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0
) },
9837 { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0
) },
9840 /* VEX_W_0F91_P_2_LEN_0 */
9841 { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0
) },
9842 { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0
) },
9845 /* VEX_W_0F92_P_0_LEN_0 */
9846 { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0
) },
9849 /* VEX_W_0F92_P_2_LEN_0 */
9850 { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0
) },
9853 /* VEX_W_0F93_P_0_LEN_0 */
9854 { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0
) },
9857 /* VEX_W_0F93_P_2_LEN_0 */
9858 { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0
) },
9861 /* VEX_W_0F98_P_0_LEN_0 */
9862 { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0
) },
9863 { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0
) },
9866 /* VEX_W_0F98_P_2_LEN_0 */
9867 { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0
) },
9868 { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0
) },
9871 /* VEX_W_0F99_P_0_LEN_0 */
9872 { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0
) },
9873 { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0
) },
9876 /* VEX_W_0F99_P_2_LEN_0 */
9877 { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0
) },
9878 { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0
) },
9881 /* VEX_W_0F380C_P_2 */
9882 { "vpermilps", { XM
, Vex
, EXx
}, 0 },
9885 /* VEX_W_0F380D_P_2 */
9886 { "vpermilpd", { XM
, Vex
, EXx
}, 0 },
9889 /* VEX_W_0F380E_P_2 */
9890 { "vtestps", { XM
, EXx
}, 0 },
9893 /* VEX_W_0F380F_P_2 */
9894 { "vtestpd", { XM
, EXx
}, 0 },
9897 /* VEX_W_0F3813_P_2 */
9898 { "vcvtph2ps", { XM
, EXxmmq
}, 0 },
9901 /* VEX_W_0F3816_P_2 */
9902 { "vpermps", { XM
, Vex
, EXx
}, 0 },
9905 /* VEX_W_0F3818_P_2 */
9906 { "vbroadcastss", { XM
, EXxmm_md
}, 0 },
9909 /* VEX_W_0F3819_P_2 */
9910 { "vbroadcastsd", { XM
, EXxmm_mq
}, 0 },
9913 /* VEX_W_0F381A_P_2_M_0 */
9914 { "vbroadcastf128", { XM
, Mxmm
}, 0 },
9917 /* VEX_W_0F382C_P_2_M_0 */
9918 { "vmaskmovps", { XM
, Vex
, Mx
}, 0 },
9921 /* VEX_W_0F382D_P_2_M_0 */
9922 { "vmaskmovpd", { XM
, Vex
, Mx
}, 0 },
9925 /* VEX_W_0F382E_P_2_M_0 */
9926 { "vmaskmovps", { Mx
, Vex
, XM
}, 0 },
9929 /* VEX_W_0F382F_P_2_M_0 */
9930 { "vmaskmovpd", { Mx
, Vex
, XM
}, 0 },
9933 /* VEX_W_0F3836_P_2 */
9934 { "vpermd", { XM
, Vex
, EXx
}, 0 },
9937 /* VEX_W_0F3846_P_2 */
9938 { "vpsravd", { XM
, Vex
, EXx
}, 0 },
9941 /* VEX_W_0F3858_P_2 */
9942 { "vpbroadcastd", { XM
, EXxmm_md
}, 0 },
9945 /* VEX_W_0F3859_P_2 */
9946 { "vpbroadcastq", { XM
, EXxmm_mq
}, 0 },
9949 /* VEX_W_0F385A_P_2_M_0 */
9950 { "vbroadcasti128", { XM
, Mxmm
}, 0 },
9953 /* VEX_W_0F3878_P_2 */
9954 { "vpbroadcastb", { XM
, EXxmm_mb
}, 0 },
9957 /* VEX_W_0F3879_P_2 */
9958 { "vpbroadcastw", { XM
, EXxmm_mw
}, 0 },
9961 /* VEX_W_0F38CF_P_2 */
9962 { "vgf2p8mulb", { XM
, Vex
, EXx
}, 0 },
9965 /* VEX_W_0F3A00_P_2 */
9967 { "vpermq", { XM
, EXx
, Ib
}, 0 },
9970 /* VEX_W_0F3A01_P_2 */
9972 { "vpermpd", { XM
, EXx
, Ib
}, 0 },
9975 /* VEX_W_0F3A02_P_2 */
9976 { "vpblendd", { XM
, Vex
, EXx
, Ib
}, 0 },
9979 /* VEX_W_0F3A04_P_2 */
9980 { "vpermilps", { XM
, EXx
, Ib
}, 0 },
9983 /* VEX_W_0F3A05_P_2 */
9984 { "vpermilpd", { XM
, EXx
, Ib
}, 0 },
9987 /* VEX_W_0F3A06_P_2 */
9988 { "vperm2f128", { XM
, Vex256
, EXx
, Ib
}, 0 },
9991 /* VEX_W_0F3A18_P_2 */
9992 { "vinsertf128", { XM
, Vex256
, EXxmm
, Ib
}, 0 },
9995 /* VEX_W_0F3A19_P_2 */
9996 { "vextractf128", { EXxmm
, XM
, Ib
}, 0 },
9999 /* VEX_W_0F3A1D_P_2 */
10000 { "vcvtps2ph", { EXxmmq
, XM
, EXxEVexS
, Ib
}, 0 },
10003 /* VEX_W_0F3A30_P_2_LEN_0 */
10004 { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0
) },
10005 { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0
) },
10008 /* VEX_W_0F3A31_P_2_LEN_0 */
10009 { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0
) },
10010 { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0
) },
10013 /* VEX_W_0F3A32_P_2_LEN_0 */
10014 { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0
) },
10015 { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0
) },
10018 /* VEX_W_0F3A33_P_2_LEN_0 */
10019 { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0
) },
10020 { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0
) },
10023 /* VEX_W_0F3A38_P_2 */
10024 { "vinserti128", { XM
, Vex256
, EXxmm
, Ib
}, 0 },
10027 /* VEX_W_0F3A39_P_2 */
10028 { "vextracti128", { EXxmm
, XM
, Ib
}, 0 },
10031 /* VEX_W_0F3A46_P_2 */
10032 { "vperm2i128", { XM
, Vex256
, EXx
, Ib
}, 0 },
10035 /* VEX_W_0F3A48_P_2 */
10036 { "vpermil2ps", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
}, 0 },
10037 { "vpermil2ps", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
}, 0 },
10040 /* VEX_W_0F3A49_P_2 */
10041 { "vpermil2pd", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
}, 0 },
10042 { "vpermil2pd", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
}, 0 },
10045 /* VEX_W_0F3A4A_P_2 */
10046 { "vblendvps", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
10049 /* VEX_W_0F3A4B_P_2 */
10050 { "vblendvpd", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
10053 /* VEX_W_0F3A4C_P_2 */
10054 { "vpblendvb", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
10057 /* VEX_W_0F3ACE_P_2 */
10059 { "vgf2p8affineqb", { XM
, Vex
, EXx
, Ib
}, 0 },
10062 /* VEX_W_0F3ACF_P_2 */
10064 { "vgf2p8affineinvqb", { XM
, Vex
, EXx
, Ib
}, 0 },
10067 #include "i386-dis-evex-w.h"
10070 static const struct dis386 mod_table
[][2] = {
10073 { "leaS", { Gv
, M
}, 0 },
10078 { RM_TABLE (RM_C6_REG_7
) },
10083 { RM_TABLE (RM_C7_REG_7
) },
10087 { "{l|}call^", { indirEp
}, 0 },
10091 { "{l|}jmp^", { indirEp
}, 0 },
10094 /* MOD_0F01_REG_0 */
10095 { X86_64_TABLE (X86_64_0F01_REG_0
) },
10096 { RM_TABLE (RM_0F01_REG_0
) },
10099 /* MOD_0F01_REG_1 */
10100 { X86_64_TABLE (X86_64_0F01_REG_1
) },
10101 { RM_TABLE (RM_0F01_REG_1
) },
10104 /* MOD_0F01_REG_2 */
10105 { X86_64_TABLE (X86_64_0F01_REG_2
) },
10106 { RM_TABLE (RM_0F01_REG_2
) },
10109 /* MOD_0F01_REG_3 */
10110 { X86_64_TABLE (X86_64_0F01_REG_3
) },
10111 { RM_TABLE (RM_0F01_REG_3
) },
10114 /* MOD_0F01_REG_5 */
10115 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_0
) },
10116 { RM_TABLE (RM_0F01_REG_5_MOD_3
) },
10119 /* MOD_0F01_REG_7 */
10120 { "invlpg", { Mb
}, 0 },
10121 { RM_TABLE (RM_0F01_REG_7_MOD_3
) },
10124 /* MOD_0F12_PREFIX_0 */
10125 { "movlpX", { XM
, EXq
}, 0 },
10126 { "movhlps", { XM
, EXq
}, 0 },
10129 /* MOD_0F12_PREFIX_2 */
10130 { "movlpX", { XM
, EXq
}, 0 },
10134 { "movlpX", { EXq
, XM
}, PREFIX_OPCODE
},
10137 /* MOD_0F16_PREFIX_0 */
10138 { "movhpX", { XM
, EXq
}, 0 },
10139 { "movlhps", { XM
, EXq
}, 0 },
10142 /* MOD_0F16_PREFIX_2 */
10143 { "movhpX", { XM
, EXq
}, 0 },
10147 { "movhpX", { EXq
, XM
}, PREFIX_OPCODE
},
10150 /* MOD_0F18_REG_0 */
10151 { "prefetchnta", { Mb
}, 0 },
10154 /* MOD_0F18_REG_1 */
10155 { "prefetcht0", { Mb
}, 0 },
10158 /* MOD_0F18_REG_2 */
10159 { "prefetcht1", { Mb
}, 0 },
10162 /* MOD_0F18_REG_3 */
10163 { "prefetcht2", { Mb
}, 0 },
10166 /* MOD_0F18_REG_4 */
10167 { "nop/reserved", { Mb
}, 0 },
10170 /* MOD_0F18_REG_5 */
10171 { "nop/reserved", { Mb
}, 0 },
10174 /* MOD_0F18_REG_6 */
10175 { "nop/reserved", { Mb
}, 0 },
10178 /* MOD_0F18_REG_7 */
10179 { "nop/reserved", { Mb
}, 0 },
10182 /* MOD_0F1A_PREFIX_0 */
10183 { "bndldx", { Gbnd
, Mv_bnd
}, 0 },
10184 { "nopQ", { Ev
}, 0 },
10187 /* MOD_0F1B_PREFIX_0 */
10188 { "bndstx", { Mv_bnd
, Gbnd
}, 0 },
10189 { "nopQ", { Ev
}, 0 },
10192 /* MOD_0F1B_PREFIX_1 */
10193 { "bndmk", { Gbnd
, Mv_bnd
}, 0 },
10194 { "nopQ", { Ev
}, 0 },
10197 /* MOD_0F1C_PREFIX_0 */
10198 { REG_TABLE (REG_0F1C_P_0_MOD_0
) },
10199 { "nopQ", { Ev
}, 0 },
10202 /* MOD_0F1E_PREFIX_1 */
10203 { "nopQ", { Ev
}, 0 },
10204 { REG_TABLE (REG_0F1E_P_1_MOD_3
) },
10209 { "movL", { Rd
, Td
}, 0 },
10214 { "movL", { Td
, Rd
}, 0 },
10217 /* MOD_0F2B_PREFIX_0 */
10218 {"movntps", { Mx
, XM
}, PREFIX_OPCODE
},
10221 /* MOD_0F2B_PREFIX_1 */
10222 {"movntss", { Md
, XM
}, PREFIX_OPCODE
},
10225 /* MOD_0F2B_PREFIX_2 */
10226 {"movntpd", { Mx
, XM
}, PREFIX_OPCODE
},
10229 /* MOD_0F2B_PREFIX_3 */
10230 {"movntsd", { Mq
, XM
}, PREFIX_OPCODE
},
10235 { "movmskpX", { Gdq
, XS
}, PREFIX_OPCODE
},
10238 /* MOD_0F71_REG_2 */
10240 { "psrlw", { MS
, Ib
}, 0 },
10243 /* MOD_0F71_REG_4 */
10245 { "psraw", { MS
, Ib
}, 0 },
10248 /* MOD_0F71_REG_6 */
10250 { "psllw", { MS
, Ib
}, 0 },
10253 /* MOD_0F72_REG_2 */
10255 { "psrld", { MS
, Ib
}, 0 },
10258 /* MOD_0F72_REG_4 */
10260 { "psrad", { MS
, Ib
}, 0 },
10263 /* MOD_0F72_REG_6 */
10265 { "pslld", { MS
, Ib
}, 0 },
10268 /* MOD_0F73_REG_2 */
10270 { "psrlq", { MS
, Ib
}, 0 },
10273 /* MOD_0F73_REG_3 */
10275 { PREFIX_TABLE (PREFIX_0F73_REG_3
) },
10278 /* MOD_0F73_REG_6 */
10280 { "psllq", { MS
, Ib
}, 0 },
10283 /* MOD_0F73_REG_7 */
10285 { PREFIX_TABLE (PREFIX_0F73_REG_7
) },
10288 /* MOD_0FAE_REG_0 */
10289 { "fxsave", { FXSAVE
}, 0 },
10290 { PREFIX_TABLE (PREFIX_0FAE_REG_0_MOD_3
) },
10293 /* MOD_0FAE_REG_1 */
10294 { "fxrstor", { FXSAVE
}, 0 },
10295 { PREFIX_TABLE (PREFIX_0FAE_REG_1_MOD_3
) },
10298 /* MOD_0FAE_REG_2 */
10299 { "ldmxcsr", { Md
}, 0 },
10300 { PREFIX_TABLE (PREFIX_0FAE_REG_2_MOD_3
) },
10303 /* MOD_0FAE_REG_3 */
10304 { "stmxcsr", { Md
}, 0 },
10305 { PREFIX_TABLE (PREFIX_0FAE_REG_3_MOD_3
) },
10308 /* MOD_0FAE_REG_4 */
10309 { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_0
) },
10310 { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_3
) },
10313 /* MOD_0FAE_REG_5 */
10314 { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_0
) },
10315 { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_3
) },
10318 /* MOD_0FAE_REG_6 */
10319 { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_0
) },
10320 { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_3
) },
10323 /* MOD_0FAE_REG_7 */
10324 { PREFIX_TABLE (PREFIX_0FAE_REG_7_MOD_0
) },
10325 { RM_TABLE (RM_0FAE_REG_7_MOD_3
) },
10329 { "lssS", { Gv
, Mp
}, 0 },
10333 { "lfsS", { Gv
, Mp
}, 0 },
10337 { "lgsS", { Gv
, Mp
}, 0 },
10341 { PREFIX_TABLE (PREFIX_0FC3_MOD_0
) },
10344 /* MOD_0FC7_REG_3 */
10345 { "xrstors", { FXSAVE
}, 0 },
10348 /* MOD_0FC7_REG_4 */
10349 { "xsavec", { FXSAVE
}, 0 },
10352 /* MOD_0FC7_REG_5 */
10353 { "xsaves", { FXSAVE
}, 0 },
10356 /* MOD_0FC7_REG_6 */
10357 { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_0
) },
10358 { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_3
) }
10361 /* MOD_0FC7_REG_7 */
10362 { "vmptrst", { Mq
}, 0 },
10363 { PREFIX_TABLE (PREFIX_0FC7_REG_7_MOD_3
) }
10368 { "pmovmskb", { Gdq
, MS
}, 0 },
10371 /* MOD_0FE7_PREFIX_2 */
10372 { "movntdq", { Mx
, XM
}, 0 },
10375 /* MOD_0FF0_PREFIX_3 */
10376 { "lddqu", { XM
, M
}, 0 },
10379 /* MOD_0F382A_PREFIX_2 */
10380 { "movntdqa", { XM
, Mx
}, 0 },
10383 /* MOD_0F38F5_PREFIX_2 */
10384 { "wrussK", { M
, Gdq
}, PREFIX_OPCODE
},
10387 /* MOD_0F38F6_PREFIX_0 */
10388 { "wrssK", { M
, Gdq
}, PREFIX_OPCODE
},
10391 /* MOD_0F38F8_PREFIX_1 */
10392 { "enqcmds", { Gva
, M
}, PREFIX_OPCODE
},
10395 /* MOD_0F38F8_PREFIX_2 */
10396 { "movdir64b", { Gva
, M
}, PREFIX_OPCODE
},
10399 /* MOD_0F38F8_PREFIX_3 */
10400 { "enqcmd", { Gva
, M
}, PREFIX_OPCODE
},
10403 /* MOD_0F38F9_PREFIX_0 */
10404 { "movdiri", { Ev
, Gv
}, PREFIX_OPCODE
},
10408 { "bound{S|}", { Gv
, Ma
}, 0 },
10409 { EVEX_TABLE (EVEX_0F
) },
10413 { "lesS", { Gv
, Mp
}, 0 },
10414 { VEX_C4_TABLE (VEX_0F
) },
10418 { "ldsS", { Gv
, Mp
}, 0 },
10419 { VEX_C5_TABLE (VEX_0F
) },
10422 /* MOD_VEX_0F12_PREFIX_0 */
10423 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0
) },
10424 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1
) },
10427 /* MOD_VEX_0F12_PREFIX_2 */
10428 { VEX_LEN_TABLE (VEX_LEN_0F12_P_2_M_0
) },
10432 { VEX_LEN_TABLE (VEX_LEN_0F13_M_0
) },
10435 /* MOD_VEX_0F16_PREFIX_0 */
10436 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0
) },
10437 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1
) },
10440 /* MOD_VEX_0F16_PREFIX_2 */
10441 { VEX_LEN_TABLE (VEX_LEN_0F16_P_2_M_0
) },
10445 { VEX_LEN_TABLE (VEX_LEN_0F17_M_0
) },
10449 { "vmovntpX", { Mx
, XM
}, PREFIX_OPCODE
},
10452 /* MOD_VEX_W_0_0F41_P_0_LEN_1 */
10454 { "kandw", { MaskG
, MaskVex
, MaskR
}, 0 },
10457 /* MOD_VEX_W_1_0F41_P_0_LEN_1 */
10459 { "kandq", { MaskG
, MaskVex
, MaskR
}, 0 },
10462 /* MOD_VEX_W_0_0F41_P_2_LEN_1 */
10464 { "kandb", { MaskG
, MaskVex
, MaskR
}, 0 },
10467 /* MOD_VEX_W_1_0F41_P_2_LEN_1 */
10469 { "kandd", { MaskG
, MaskVex
, MaskR
}, 0 },
10472 /* MOD_VEX_W_0_0F42_P_0_LEN_1 */
10474 { "kandnw", { MaskG
, MaskVex
, MaskR
}, 0 },
10477 /* MOD_VEX_W_1_0F42_P_0_LEN_1 */
10479 { "kandnq", { MaskG
, MaskVex
, MaskR
}, 0 },
10482 /* MOD_VEX_W_0_0F42_P_2_LEN_1 */
10484 { "kandnb", { MaskG
, MaskVex
, MaskR
}, 0 },
10487 /* MOD_VEX_W_1_0F42_P_2_LEN_1 */
10489 { "kandnd", { MaskG
, MaskVex
, MaskR
}, 0 },
10492 /* MOD_VEX_W_0_0F44_P_0_LEN_0 */
10494 { "knotw", { MaskG
, MaskR
}, 0 },
10497 /* MOD_VEX_W_1_0F44_P_0_LEN_0 */
10499 { "knotq", { MaskG
, MaskR
}, 0 },
10502 /* MOD_VEX_W_0_0F44_P_2_LEN_0 */
10504 { "knotb", { MaskG
, MaskR
}, 0 },
10507 /* MOD_VEX_W_1_0F44_P_2_LEN_0 */
10509 { "knotd", { MaskG
, MaskR
}, 0 },
10512 /* MOD_VEX_W_0_0F45_P_0_LEN_1 */
10514 { "korw", { MaskG
, MaskVex
, MaskR
}, 0 },
10517 /* MOD_VEX_W_1_0F45_P_0_LEN_1 */
10519 { "korq", { MaskG
, MaskVex
, MaskR
}, 0 },
10522 /* MOD_VEX_W_0_0F45_P_2_LEN_1 */
10524 { "korb", { MaskG
, MaskVex
, MaskR
}, 0 },
10527 /* MOD_VEX_W_1_0F45_P_2_LEN_1 */
10529 { "kord", { MaskG
, MaskVex
, MaskR
}, 0 },
10532 /* MOD_VEX_W_0_0F46_P_0_LEN_1 */
10534 { "kxnorw", { MaskG
, MaskVex
, MaskR
}, 0 },
10537 /* MOD_VEX_W_1_0F46_P_0_LEN_1 */
10539 { "kxnorq", { MaskG
, MaskVex
, MaskR
}, 0 },
10542 /* MOD_VEX_W_0_0F46_P_2_LEN_1 */
10544 { "kxnorb", { MaskG
, MaskVex
, MaskR
}, 0 },
10547 /* MOD_VEX_W_1_0F46_P_2_LEN_1 */
10549 { "kxnord", { MaskG
, MaskVex
, MaskR
}, 0 },
10552 /* MOD_VEX_W_0_0F47_P_0_LEN_1 */
10554 { "kxorw", { MaskG
, MaskVex
, MaskR
}, 0 },
10557 /* MOD_VEX_W_1_0F47_P_0_LEN_1 */
10559 { "kxorq", { MaskG
, MaskVex
, MaskR
}, 0 },
10562 /* MOD_VEX_W_0_0F47_P_2_LEN_1 */
10564 { "kxorb", { MaskG
, MaskVex
, MaskR
}, 0 },
10567 /* MOD_VEX_W_1_0F47_P_2_LEN_1 */
10569 { "kxord", { MaskG
, MaskVex
, MaskR
}, 0 },
10572 /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */
10574 { "kaddw", { MaskG
, MaskVex
, MaskR
}, 0 },
10577 /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */
10579 { "kaddq", { MaskG
, MaskVex
, MaskR
}, 0 },
10582 /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */
10584 { "kaddb", { MaskG
, MaskVex
, MaskR
}, 0 },
10587 /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */
10589 { "kaddd", { MaskG
, MaskVex
, MaskR
}, 0 },
10592 /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */
10594 { "kunpckwd", { MaskG
, MaskVex
, MaskR
}, 0 },
10597 /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */
10599 { "kunpckdq", { MaskG
, MaskVex
, MaskR
}, 0 },
10602 /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */
10604 { "kunpckbw", { MaskG
, MaskVex
, MaskR
}, 0 },
10609 { "vmovmskpX", { Gdq
, XS
}, PREFIX_OPCODE
},
10612 /* MOD_VEX_0F71_REG_2 */
10614 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2
) },
10617 /* MOD_VEX_0F71_REG_4 */
10619 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4
) },
10622 /* MOD_VEX_0F71_REG_6 */
10624 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6
) },
10627 /* MOD_VEX_0F72_REG_2 */
10629 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2
) },
10632 /* MOD_VEX_0F72_REG_4 */
10634 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4
) },
10637 /* MOD_VEX_0F72_REG_6 */
10639 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6
) },
10642 /* MOD_VEX_0F73_REG_2 */
10644 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2
) },
10647 /* MOD_VEX_0F73_REG_3 */
10649 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3
) },
10652 /* MOD_VEX_0F73_REG_6 */
10654 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6
) },
10657 /* MOD_VEX_0F73_REG_7 */
10659 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7
) },
10662 /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
10663 { "kmovw", { Ew
, MaskG
}, 0 },
10667 /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
10668 { "kmovq", { Eq
, MaskG
}, 0 },
10672 /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
10673 { "kmovb", { Eb
, MaskG
}, 0 },
10677 /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
10678 { "kmovd", { Ed
, MaskG
}, 0 },
10682 /* MOD_VEX_W_0_0F92_P_0_LEN_0 */
10684 { "kmovw", { MaskG
, Rdq
}, 0 },
10687 /* MOD_VEX_W_0_0F92_P_2_LEN_0 */
10689 { "kmovb", { MaskG
, Rdq
}, 0 },
10692 /* MOD_VEX_0F92_P_3_LEN_0 */
10694 { "kmovK", { MaskG
, Rdq
}, 0 },
10697 /* MOD_VEX_W_0_0F93_P_0_LEN_0 */
10699 { "kmovw", { Gdq
, MaskR
}, 0 },
10702 /* MOD_VEX_W_0_0F93_P_2_LEN_0 */
10704 { "kmovb", { Gdq
, MaskR
}, 0 },
10707 /* MOD_VEX_0F93_P_3_LEN_0 */
10709 { "kmovK", { Gdq
, MaskR
}, 0 },
10712 /* MOD_VEX_W_0_0F98_P_0_LEN_0 */
10714 { "kortestw", { MaskG
, MaskR
}, 0 },
10717 /* MOD_VEX_W_1_0F98_P_0_LEN_0 */
10719 { "kortestq", { MaskG
, MaskR
}, 0 },
10722 /* MOD_VEX_W_0_0F98_P_2_LEN_0 */
10724 { "kortestb", { MaskG
, MaskR
}, 0 },
10727 /* MOD_VEX_W_1_0F98_P_2_LEN_0 */
10729 { "kortestd", { MaskG
, MaskR
}, 0 },
10732 /* MOD_VEX_W_0_0F99_P_0_LEN_0 */
10734 { "ktestw", { MaskG
, MaskR
}, 0 },
10737 /* MOD_VEX_W_1_0F99_P_0_LEN_0 */
10739 { "ktestq", { MaskG
, MaskR
}, 0 },
10742 /* MOD_VEX_W_0_0F99_P_2_LEN_0 */
10744 { "ktestb", { MaskG
, MaskR
}, 0 },
10747 /* MOD_VEX_W_1_0F99_P_2_LEN_0 */
10749 { "ktestd", { MaskG
, MaskR
}, 0 },
10752 /* MOD_VEX_0FAE_REG_2 */
10753 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0
) },
10756 /* MOD_VEX_0FAE_REG_3 */
10757 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0
) },
10760 /* MOD_VEX_0FD7_PREFIX_2 */
10762 { "vpmovmskb", { Gdq
, XS
}, 0 },
10765 /* MOD_VEX_0FE7_PREFIX_2 */
10766 { "vmovntdq", { Mx
, XM
}, 0 },
10769 /* MOD_VEX_0FF0_PREFIX_3 */
10770 { "vlddqu", { XM
, M
}, 0 },
10773 /* MOD_VEX_0F381A_PREFIX_2 */
10774 { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0
) },
10777 /* MOD_VEX_0F382A_PREFIX_2 */
10778 { "vmovntdqa", { XM
, Mx
}, 0 },
10781 /* MOD_VEX_0F382C_PREFIX_2 */
10782 { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0
) },
10785 /* MOD_VEX_0F382D_PREFIX_2 */
10786 { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0
) },
10789 /* MOD_VEX_0F382E_PREFIX_2 */
10790 { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0
) },
10793 /* MOD_VEX_0F382F_PREFIX_2 */
10794 { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0
) },
10797 /* MOD_VEX_0F385A_PREFIX_2 */
10798 { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0
) },
10801 /* MOD_VEX_0F388C_PREFIX_2 */
10802 { "vpmaskmov%LW", { XM
, Vex
, Mx
}, 0 },
10805 /* MOD_VEX_0F388E_PREFIX_2 */
10806 { "vpmaskmov%LW", { Mx
, Vex
, XM
}, 0 },
10809 /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */
10811 { "kshiftrb", { MaskG
, MaskR
, Ib
}, 0 },
10814 /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */
10816 { "kshiftrw", { MaskG
, MaskR
, Ib
}, 0 },
10819 /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */
10821 { "kshiftrd", { MaskG
, MaskR
, Ib
}, 0 },
10824 /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */
10826 { "kshiftrq", { MaskG
, MaskR
, Ib
}, 0 },
10829 /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */
10831 { "kshiftlb", { MaskG
, MaskR
, Ib
}, 0 },
10834 /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */
10836 { "kshiftlw", { MaskG
, MaskR
, Ib
}, 0 },
10839 /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */
10841 { "kshiftld", { MaskG
, MaskR
, Ib
}, 0 },
10844 /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */
10846 { "kshiftlq", { MaskG
, MaskR
, Ib
}, 0 },
10849 #include "i386-dis-evex-mod.h"
10852 static const struct dis386 rm_table
[][8] = {
10855 { "xabort", { Skip_MODRM
, Ib
}, 0 },
10859 { "xbeginT", { Skip_MODRM
, Jdqw
}, 0 },
10862 /* RM_0F01_REG_0 */
10863 { "enclv", { Skip_MODRM
}, 0 },
10864 { "vmcall", { Skip_MODRM
}, 0 },
10865 { "vmlaunch", { Skip_MODRM
}, 0 },
10866 { "vmresume", { Skip_MODRM
}, 0 },
10867 { "vmxoff", { Skip_MODRM
}, 0 },
10868 { "pconfig", { Skip_MODRM
}, 0 },
10871 /* RM_0F01_REG_1 */
10872 { "monitor", { { OP_Monitor
, 0 } }, 0 },
10873 { "mwait", { { OP_Mwait
, 0 } }, 0 },
10874 { "clac", { Skip_MODRM
}, 0 },
10875 { "stac", { Skip_MODRM
}, 0 },
10879 { "encls", { Skip_MODRM
}, 0 },
10882 /* RM_0F01_REG_2 */
10883 { "xgetbv", { Skip_MODRM
}, 0 },
10884 { "xsetbv", { Skip_MODRM
}, 0 },
10887 { "vmfunc", { Skip_MODRM
}, 0 },
10888 { "xend", { Skip_MODRM
}, 0 },
10889 { "xtest", { Skip_MODRM
}, 0 },
10890 { "enclu", { Skip_MODRM
}, 0 },
10893 /* RM_0F01_REG_3 */
10894 { "vmrun", { Skip_MODRM
}, 0 },
10895 { PREFIX_TABLE (PREFIX_0F01_REG_3_RM_1
) },
10896 { "vmload", { Skip_MODRM
}, 0 },
10897 { "vmsave", { Skip_MODRM
}, 0 },
10898 { "stgi", { Skip_MODRM
}, 0 },
10899 { "clgi", { Skip_MODRM
}, 0 },
10900 { "skinit", { Skip_MODRM
}, 0 },
10901 { "invlpga", { Skip_MODRM
}, 0 },
10904 /* RM_0F01_REG_5_MOD_3 */
10905 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_0
) },
10906 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_1
) },
10907 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_2
) },
10911 { "rdpkru", { Skip_MODRM
}, 0 },
10912 { "wrpkru", { Skip_MODRM
}, 0 },
10915 /* RM_0F01_REG_7_MOD_3 */
10916 { "swapgs", { Skip_MODRM
}, 0 },
10917 { "rdtscp", { Skip_MODRM
}, 0 },
10918 { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_2
) },
10919 { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_3
) },
10920 { "clzero", { Skip_MODRM
}, 0 },
10921 { "rdpru", { Skip_MODRM
}, 0 },
10924 /* RM_0F1E_P_1_MOD_3_REG_7 */
10925 { "nopQ", { Ev
}, 0 },
10926 { "nopQ", { Ev
}, 0 },
10927 { "endbr64", { Skip_MODRM
}, PREFIX_OPCODE
},
10928 { "endbr32", { Skip_MODRM
}, PREFIX_OPCODE
},
10929 { "nopQ", { Ev
}, 0 },
10930 { "nopQ", { Ev
}, 0 },
10931 { "nopQ", { Ev
}, 0 },
10932 { "nopQ", { Ev
}, 0 },
10935 /* RM_0FAE_REG_6_MOD_3 */
10936 { "mfence", { Skip_MODRM
}, 0 },
10939 /* RM_0FAE_REG_7_MOD_3 */
10940 { "sfence", { Skip_MODRM
}, 0 },
10945 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
10947 /* We use the high bit to indicate different name for the same
10949 #define REP_PREFIX (0xf3 | 0x100)
10950 #define XACQUIRE_PREFIX (0xf2 | 0x200)
10951 #define XRELEASE_PREFIX (0xf3 | 0x400)
10952 #define BND_PREFIX (0xf2 | 0x400)
10953 #define NOTRACK_PREFIX (0x3e | 0x100)
10955 /* Remember if the current op is a jump instruction. */
10956 static bfd_boolean op_is_jump
= FALSE
;
10961 int newrex
, i
, length
;
10966 last_lock_prefix
= -1;
10967 last_repz_prefix
= -1;
10968 last_repnz_prefix
= -1;
10969 last_data_prefix
= -1;
10970 last_addr_prefix
= -1;
10971 last_rex_prefix
= -1;
10972 last_seg_prefix
= -1;
10974 active_seg_prefix
= 0;
10975 for (i
= 0; i
< (int) ARRAY_SIZE (all_prefixes
); i
++)
10976 all_prefixes
[i
] = 0;
10979 /* The maximum instruction length is 15bytes. */
10980 while (length
< MAX_CODE_LENGTH
- 1)
10982 FETCH_DATA (the_info
, codep
+ 1);
10986 /* REX prefixes family. */
11003 if (address_mode
== mode_64bit
)
11007 last_rex_prefix
= i
;
11010 prefixes
|= PREFIX_REPZ
;
11011 last_repz_prefix
= i
;
11014 prefixes
|= PREFIX_REPNZ
;
11015 last_repnz_prefix
= i
;
11018 prefixes
|= PREFIX_LOCK
;
11019 last_lock_prefix
= i
;
11022 prefixes
|= PREFIX_CS
;
11023 last_seg_prefix
= i
;
11024 active_seg_prefix
= PREFIX_CS
;
11027 prefixes
|= PREFIX_SS
;
11028 last_seg_prefix
= i
;
11029 active_seg_prefix
= PREFIX_SS
;
11032 prefixes
|= PREFIX_DS
;
11033 last_seg_prefix
= i
;
11034 active_seg_prefix
= PREFIX_DS
;
11037 prefixes
|= PREFIX_ES
;
11038 last_seg_prefix
= i
;
11039 active_seg_prefix
= PREFIX_ES
;
11042 prefixes
|= PREFIX_FS
;
11043 last_seg_prefix
= i
;
11044 active_seg_prefix
= PREFIX_FS
;
11047 prefixes
|= PREFIX_GS
;
11048 last_seg_prefix
= i
;
11049 active_seg_prefix
= PREFIX_GS
;
11052 prefixes
|= PREFIX_DATA
;
11053 last_data_prefix
= i
;
11056 prefixes
|= PREFIX_ADDR
;
11057 last_addr_prefix
= i
;
11060 /* fwait is really an instruction. If there are prefixes
11061 before the fwait, they belong to the fwait, *not* to the
11062 following instruction. */
11064 if (prefixes
|| rex
)
11066 prefixes
|= PREFIX_FWAIT
;
11068 /* This ensures that the previous REX prefixes are noticed
11069 as unused prefixes, as in the return case below. */
11073 prefixes
= PREFIX_FWAIT
;
11078 /* Rex is ignored when followed by another prefix. */
11084 if (*codep
!= FWAIT_OPCODE
)
11085 all_prefixes
[i
++] = *codep
;
11093 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
11096 static const char *
11097 prefix_name (int pref
, int sizeflag
)
11099 static const char *rexes
[16] =
11102 "rex.B", /* 0x41 */
11103 "rex.X", /* 0x42 */
11104 "rex.XB", /* 0x43 */
11105 "rex.R", /* 0x44 */
11106 "rex.RB", /* 0x45 */
11107 "rex.RX", /* 0x46 */
11108 "rex.RXB", /* 0x47 */
11109 "rex.W", /* 0x48 */
11110 "rex.WB", /* 0x49 */
11111 "rex.WX", /* 0x4a */
11112 "rex.WXB", /* 0x4b */
11113 "rex.WR", /* 0x4c */
11114 "rex.WRB", /* 0x4d */
11115 "rex.WRX", /* 0x4e */
11116 "rex.WRXB", /* 0x4f */
11121 /* REX prefixes family. */
11138 return rexes
[pref
- 0x40];
11158 return (sizeflag
& DFLAG
) ? "data16" : "data32";
11160 if (address_mode
== mode_64bit
)
11161 return (sizeflag
& AFLAG
) ? "addr32" : "addr64";
11163 return (sizeflag
& AFLAG
) ? "addr16" : "addr32";
11168 case XACQUIRE_PREFIX
:
11170 case XRELEASE_PREFIX
:
11174 case NOTRACK_PREFIX
:
11181 static char op_out
[MAX_OPERANDS
][100];
11182 static int op_ad
, op_index
[MAX_OPERANDS
];
11183 static int two_source_ops
;
11184 static bfd_vma op_address
[MAX_OPERANDS
];
11185 static bfd_vma op_riprel
[MAX_OPERANDS
];
11186 static bfd_vma start_pc
;
11189 * On the 386's of 1988, the maximum length of an instruction is 15 bytes.
11190 * (see topic "Redundant prefixes" in the "Differences from 8086"
11191 * section of the "Virtual 8086 Mode" chapter.)
11192 * 'pc' should be the address of this instruction, it will
11193 * be used to print the target address if this is a relative jump or call
11194 * The function returns the length of this instruction in bytes.
11197 static char intel_syntax
;
11198 static char intel_mnemonic
= !SYSV386_COMPAT
;
11199 static char open_char
;
11200 static char close_char
;
11201 static char separator_char
;
11202 static char scale_char
;
11210 static enum x86_64_isa isa64
;
11212 /* Here for backwards compatibility. When gdb stops using
11213 print_insn_i386_att and print_insn_i386_intel these functions can
11214 disappear, and print_insn_i386 be merged into print_insn. */
11216 print_insn_i386_att (bfd_vma pc
, disassemble_info
*info
)
11220 return print_insn (pc
, info
);
11224 print_insn_i386_intel (bfd_vma pc
, disassemble_info
*info
)
11228 return print_insn (pc
, info
);
11232 print_insn_i386 (bfd_vma pc
, disassemble_info
*info
)
11236 return print_insn (pc
, info
);
11240 print_i386_disassembler_options (FILE *stream
)
11242 fprintf (stream
, _("\n\
11243 The following i386/x86-64 specific disassembler options are supported for use\n\
11244 with the -M switch (multiple options should be separated by commas):\n"));
11246 fprintf (stream
, _(" x86-64 Disassemble in 64bit mode\n"));
11247 fprintf (stream
, _(" i386 Disassemble in 32bit mode\n"));
11248 fprintf (stream
, _(" i8086 Disassemble in 16bit mode\n"));
11249 fprintf (stream
, _(" att Display instruction in AT&T syntax\n"));
11250 fprintf (stream
, _(" intel Display instruction in Intel syntax\n"));
11251 fprintf (stream
, _(" att-mnemonic\n"
11252 " Display instruction in AT&T mnemonic\n"));
11253 fprintf (stream
, _(" intel-mnemonic\n"
11254 " Display instruction in Intel mnemonic\n"));
11255 fprintf (stream
, _(" addr64 Assume 64bit address size\n"));
11256 fprintf (stream
, _(" addr32 Assume 32bit address size\n"));
11257 fprintf (stream
, _(" addr16 Assume 16bit address size\n"));
11258 fprintf (stream
, _(" data32 Assume 32bit data size\n"));
11259 fprintf (stream
, _(" data16 Assume 16bit data size\n"));
11260 fprintf (stream
, _(" suffix Always display instruction suffix in AT&T syntax\n"));
11261 fprintf (stream
, _(" amd64 Display instruction in AMD64 ISA\n"));
11262 fprintf (stream
, _(" intel64 Display instruction in Intel64 ISA\n"));
11266 static const struct dis386 bad_opcode
= { "(bad)", { XX
}, 0 };
11268 /* Get a pointer to struct dis386 with a valid name. */
11270 static const struct dis386
*
11271 get_valid_dis386 (const struct dis386
*dp
, disassemble_info
*info
)
11273 int vindex
, vex_table_index
;
11275 if (dp
->name
!= NULL
)
11278 switch (dp
->op
[0].bytemode
)
11280 case USE_REG_TABLE
:
11281 dp
= ®_table
[dp
->op
[1].bytemode
][modrm
.reg
];
11284 case USE_MOD_TABLE
:
11285 vindex
= modrm
.mod
== 0x3 ? 1 : 0;
11286 dp
= &mod_table
[dp
->op
[1].bytemode
][vindex
];
11290 dp
= &rm_table
[dp
->op
[1].bytemode
][modrm
.rm
];
11293 case USE_PREFIX_TABLE
:
11296 /* The prefix in VEX is implicit. */
11297 switch (vex
.prefix
)
11302 case REPE_PREFIX_OPCODE
:
11305 case DATA_PREFIX_OPCODE
:
11308 case REPNE_PREFIX_OPCODE
:
11318 int last_prefix
= -1;
11321 /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
11322 When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
11324 if ((prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
)) != 0)
11326 if (last_repz_prefix
> last_repnz_prefix
)
11329 prefix
= PREFIX_REPZ
;
11330 last_prefix
= last_repz_prefix
;
11335 prefix
= PREFIX_REPNZ
;
11336 last_prefix
= last_repnz_prefix
;
11339 /* Check if prefix should be ignored. */
11340 if ((((prefix_table
[dp
->op
[1].bytemode
][vindex
].prefix_requirement
11341 & PREFIX_IGNORED
) >> PREFIX_IGNORED_SHIFT
)
11346 if (vindex
== 0 && (prefixes
& PREFIX_DATA
) != 0)
11349 prefix
= PREFIX_DATA
;
11350 last_prefix
= last_data_prefix
;
11355 used_prefixes
|= prefix
;
11356 all_prefixes
[last_prefix
] = 0;
11359 dp
= &prefix_table
[dp
->op
[1].bytemode
][vindex
];
11362 case USE_X86_64_TABLE
:
11363 vindex
= address_mode
== mode_64bit
? 1 : 0;
11364 dp
= &x86_64_table
[dp
->op
[1].bytemode
][vindex
];
11367 case USE_3BYTE_TABLE
:
11368 FETCH_DATA (info
, codep
+ 2);
11370 dp
= &three_byte_table
[dp
->op
[1].bytemode
][vindex
];
11372 modrm
.mod
= (*codep
>> 6) & 3;
11373 modrm
.reg
= (*codep
>> 3) & 7;
11374 modrm
.rm
= *codep
& 7;
11377 case USE_VEX_LEN_TABLE
:
11381 switch (vex
.length
)
11394 dp
= &vex_len_table
[dp
->op
[1].bytemode
][vindex
];
11397 case USE_EVEX_LEN_TABLE
:
11401 switch (vex
.length
)
11417 dp
= &evex_len_table
[dp
->op
[1].bytemode
][vindex
];
11420 case USE_XOP_8F_TABLE
:
11421 FETCH_DATA (info
, codep
+ 3);
11422 rex
= ~(*codep
>> 5) & 0x7;
11424 /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */
11425 switch ((*codep
& 0x1f))
11431 vex_table_index
= XOP_08
;
11434 vex_table_index
= XOP_09
;
11437 vex_table_index
= XOP_0A
;
11441 vex
.w
= *codep
& 0x80;
11442 if (vex
.w
&& address_mode
== mode_64bit
)
11445 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
11446 if (address_mode
!= mode_64bit
)
11448 /* In 16/32-bit mode REX_B is silently ignored. */
11452 vex
.length
= (*codep
& 0x4) ? 256 : 128;
11453 switch ((*codep
& 0x3))
11458 vex
.prefix
= DATA_PREFIX_OPCODE
;
11461 vex
.prefix
= REPE_PREFIX_OPCODE
;
11464 vex
.prefix
= REPNE_PREFIX_OPCODE
;
11471 dp
= &xop_table
[vex_table_index
][vindex
];
11474 FETCH_DATA (info
, codep
+ 1);
11475 modrm
.mod
= (*codep
>> 6) & 3;
11476 modrm
.reg
= (*codep
>> 3) & 7;
11477 modrm
.rm
= *codep
& 7;
11480 case USE_VEX_C4_TABLE
:
11482 FETCH_DATA (info
, codep
+ 3);
11483 rex
= ~(*codep
>> 5) & 0x7;
11484 switch ((*codep
& 0x1f))
11490 vex_table_index
= VEX_0F
;
11493 vex_table_index
= VEX_0F38
;
11496 vex_table_index
= VEX_0F3A
;
11500 vex
.w
= *codep
& 0x80;
11501 if (address_mode
== mode_64bit
)
11508 /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
11509 is ignored, other REX bits are 0 and the highest bit in
11510 VEX.vvvv is also ignored (but we mustn't clear it here). */
11513 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
11514 vex
.length
= (*codep
& 0x4) ? 256 : 128;
11515 switch ((*codep
& 0x3))
11520 vex
.prefix
= DATA_PREFIX_OPCODE
;
11523 vex
.prefix
= REPE_PREFIX_OPCODE
;
11526 vex
.prefix
= REPNE_PREFIX_OPCODE
;
11533 dp
= &vex_table
[vex_table_index
][vindex
];
11535 /* There is no MODRM byte for VEX0F 77. */
11536 if (vex_table_index
!= VEX_0F
|| vindex
!= 0x77)
11538 FETCH_DATA (info
, codep
+ 1);
11539 modrm
.mod
= (*codep
>> 6) & 3;
11540 modrm
.reg
= (*codep
>> 3) & 7;
11541 modrm
.rm
= *codep
& 7;
11545 case USE_VEX_C5_TABLE
:
11547 FETCH_DATA (info
, codep
+ 2);
11548 rex
= (*codep
& 0x80) ? 0 : REX_R
;
11550 /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
11552 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
11553 vex
.length
= (*codep
& 0x4) ? 256 : 128;
11554 switch ((*codep
& 0x3))
11559 vex
.prefix
= DATA_PREFIX_OPCODE
;
11562 vex
.prefix
= REPE_PREFIX_OPCODE
;
11565 vex
.prefix
= REPNE_PREFIX_OPCODE
;
11572 dp
= &vex_table
[dp
->op
[1].bytemode
][vindex
];
11574 /* There is no MODRM byte for VEX 77. */
11575 if (vindex
!= 0x77)
11577 FETCH_DATA (info
, codep
+ 1);
11578 modrm
.mod
= (*codep
>> 6) & 3;
11579 modrm
.reg
= (*codep
>> 3) & 7;
11580 modrm
.rm
= *codep
& 7;
11584 case USE_VEX_W_TABLE
:
11588 dp
= &vex_w_table
[dp
->op
[1].bytemode
][vex
.w
? 1 : 0];
11591 case USE_EVEX_TABLE
:
11592 two_source_ops
= 0;
11595 FETCH_DATA (info
, codep
+ 4);
11596 /* The first byte after 0x62. */
11597 rex
= ~(*codep
>> 5) & 0x7;
11598 vex
.r
= *codep
& 0x10;
11599 switch ((*codep
& 0xf))
11602 return &bad_opcode
;
11604 vex_table_index
= EVEX_0F
;
11607 vex_table_index
= EVEX_0F38
;
11610 vex_table_index
= EVEX_0F3A
;
11614 /* The second byte after 0x62. */
11616 vex
.w
= *codep
& 0x80;
11617 if (vex
.w
&& address_mode
== mode_64bit
)
11620 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
11623 if (!(*codep
& 0x4))
11624 return &bad_opcode
;
11626 switch ((*codep
& 0x3))
11631 vex
.prefix
= DATA_PREFIX_OPCODE
;
11634 vex
.prefix
= REPE_PREFIX_OPCODE
;
11637 vex
.prefix
= REPNE_PREFIX_OPCODE
;
11641 /* The third byte after 0x62. */
11644 /* Remember the static rounding bits. */
11645 vex
.ll
= (*codep
>> 5) & 3;
11646 vex
.b
= (*codep
& 0x10) != 0;
11648 vex
.v
= *codep
& 0x8;
11649 vex
.mask_register_specifier
= *codep
& 0x7;
11650 vex
.zeroing
= *codep
& 0x80;
11652 if (address_mode
!= mode_64bit
)
11654 /* In 16/32-bit mode silently ignore following bits. */
11664 dp
= &evex_table
[vex_table_index
][vindex
];
11666 FETCH_DATA (info
, codep
+ 1);
11667 modrm
.mod
= (*codep
>> 6) & 3;
11668 modrm
.reg
= (*codep
>> 3) & 7;
11669 modrm
.rm
= *codep
& 7;
11671 /* Set vector length. */
11672 if (modrm
.mod
== 3 && vex
.b
)
11688 return &bad_opcode
;
11701 if (dp
->name
!= NULL
)
11704 return get_valid_dis386 (dp
, info
);
11708 get_sib (disassemble_info
*info
, int sizeflag
)
11710 /* If modrm.mod == 3, operand must be register. */
11712 && ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
11716 FETCH_DATA (info
, codep
+ 2);
11717 sib
.index
= (codep
[1] >> 3) & 7;
11718 sib
.scale
= (codep
[1] >> 6) & 3;
11719 sib
.base
= codep
[1] & 7;
11724 print_insn (bfd_vma pc
, disassemble_info
*info
)
11726 const struct dis386
*dp
;
11728 char *op_txt
[MAX_OPERANDS
];
11730 int sizeflag
, orig_sizeflag
;
11732 struct dis_private priv
;
11735 priv
.orig_sizeflag
= AFLAG
| DFLAG
;
11736 if ((info
->mach
& bfd_mach_i386_i386
) != 0)
11737 address_mode
= mode_32bit
;
11738 else if (info
->mach
== bfd_mach_i386_i8086
)
11740 address_mode
= mode_16bit
;
11741 priv
.orig_sizeflag
= 0;
11744 address_mode
= mode_64bit
;
11746 if (intel_syntax
== (char) -1)
11747 intel_syntax
= (info
->mach
& bfd_mach_i386_intel_syntax
) != 0;
11749 for (p
= info
->disassembler_options
; p
!= NULL
; )
11751 if (CONST_STRNEQ (p
, "amd64"))
11753 else if (CONST_STRNEQ (p
, "intel64"))
11755 else if (CONST_STRNEQ (p
, "x86-64"))
11757 address_mode
= mode_64bit
;
11758 priv
.orig_sizeflag
|= AFLAG
| DFLAG
;
11760 else if (CONST_STRNEQ (p
, "i386"))
11762 address_mode
= mode_32bit
;
11763 priv
.orig_sizeflag
|= AFLAG
| DFLAG
;
11765 else if (CONST_STRNEQ (p
, "i8086"))
11767 address_mode
= mode_16bit
;
11768 priv
.orig_sizeflag
&= ~(AFLAG
| DFLAG
);
11770 else if (CONST_STRNEQ (p
, "intel"))
11773 if (CONST_STRNEQ (p
+ 5, "-mnemonic"))
11774 intel_mnemonic
= 1;
11776 else if (CONST_STRNEQ (p
, "att"))
11779 if (CONST_STRNEQ (p
+ 3, "-mnemonic"))
11780 intel_mnemonic
= 0;
11782 else if (CONST_STRNEQ (p
, "addr"))
11784 if (address_mode
== mode_64bit
)
11786 if (p
[4] == '3' && p
[5] == '2')
11787 priv
.orig_sizeflag
&= ~AFLAG
;
11788 else if (p
[4] == '6' && p
[5] == '4')
11789 priv
.orig_sizeflag
|= AFLAG
;
11793 if (p
[4] == '1' && p
[5] == '6')
11794 priv
.orig_sizeflag
&= ~AFLAG
;
11795 else if (p
[4] == '3' && p
[5] == '2')
11796 priv
.orig_sizeflag
|= AFLAG
;
11799 else if (CONST_STRNEQ (p
, "data"))
11801 if (p
[4] == '1' && p
[5] == '6')
11802 priv
.orig_sizeflag
&= ~DFLAG
;
11803 else if (p
[4] == '3' && p
[5] == '2')
11804 priv
.orig_sizeflag
|= DFLAG
;
11806 else if (CONST_STRNEQ (p
, "suffix"))
11807 priv
.orig_sizeflag
|= SUFFIX_ALWAYS
;
11809 p
= strchr (p
, ',');
11814 if (address_mode
== mode_64bit
&& sizeof (bfd_vma
) < 8)
11816 (*info
->fprintf_func
) (info
->stream
,
11817 _("64-bit address is disabled"));
11823 names64
= intel_names64
;
11824 names32
= intel_names32
;
11825 names16
= intel_names16
;
11826 names8
= intel_names8
;
11827 names8rex
= intel_names8rex
;
11828 names_seg
= intel_names_seg
;
11829 names_mm
= intel_names_mm
;
11830 names_bnd
= intel_names_bnd
;
11831 names_xmm
= intel_names_xmm
;
11832 names_ymm
= intel_names_ymm
;
11833 names_zmm
= intel_names_zmm
;
11834 index64
= intel_index64
;
11835 index32
= intel_index32
;
11836 names_mask
= intel_names_mask
;
11837 index16
= intel_index16
;
11840 separator_char
= '+';
11845 names64
= att_names64
;
11846 names32
= att_names32
;
11847 names16
= att_names16
;
11848 names8
= att_names8
;
11849 names8rex
= att_names8rex
;
11850 names_seg
= att_names_seg
;
11851 names_mm
= att_names_mm
;
11852 names_bnd
= att_names_bnd
;
11853 names_xmm
= att_names_xmm
;
11854 names_ymm
= att_names_ymm
;
11855 names_zmm
= att_names_zmm
;
11856 index64
= att_index64
;
11857 index32
= att_index32
;
11858 names_mask
= att_names_mask
;
11859 index16
= att_index16
;
11862 separator_char
= ',';
11866 /* The output looks better if we put 7 bytes on a line, since that
11867 puts most long word instructions on a single line. Use 8 bytes
11869 if ((info
->mach
& bfd_mach_l1om
) != 0)
11870 info
->bytes_per_line
= 8;
11872 info
->bytes_per_line
= 7;
11874 info
->private_data
= &priv
;
11875 priv
.max_fetched
= priv
.the_buffer
;
11876 priv
.insn_start
= pc
;
11879 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
11887 start_codep
= priv
.the_buffer
;
11888 codep
= priv
.the_buffer
;
11890 if (OPCODES_SIGSETJMP (priv
.bailout
) != 0)
11894 /* Getting here means we tried for data but didn't get it. That
11895 means we have an incomplete instruction of some sort. Just
11896 print the first byte as a prefix or a .byte pseudo-op. */
11897 if (codep
> priv
.the_buffer
)
11899 name
= prefix_name (priv
.the_buffer
[0], priv
.orig_sizeflag
);
11901 (*info
->fprintf_func
) (info
->stream
, "%s", name
);
11904 /* Just print the first byte as a .byte instruction. */
11905 (*info
->fprintf_func
) (info
->stream
, ".byte 0x%x",
11906 (unsigned int) priv
.the_buffer
[0]);
11916 sizeflag
= priv
.orig_sizeflag
;
11918 if (!ckprefix () || rex_used
)
11920 /* Too many prefixes or unused REX prefixes. */
11922 i
< (int) ARRAY_SIZE (all_prefixes
) && all_prefixes
[i
];
11924 (*info
->fprintf_func
) (info
->stream
, "%s%s",
11926 prefix_name (all_prefixes
[i
], sizeflag
));
11930 insn_codep
= codep
;
11932 FETCH_DATA (info
, codep
+ 1);
11933 two_source_ops
= (*codep
== 0x62) || (*codep
== 0xc8);
11935 if (((prefixes
& PREFIX_FWAIT
)
11936 && ((*codep
< 0xd8) || (*codep
> 0xdf))))
11938 /* Handle prefixes before fwait. */
11939 for (i
= 0; i
< fwait_prefix
&& all_prefixes
[i
];
11941 (*info
->fprintf_func
) (info
->stream
, "%s ",
11942 prefix_name (all_prefixes
[i
], sizeflag
));
11943 (*info
->fprintf_func
) (info
->stream
, "fwait");
11947 if (*codep
== 0x0f)
11949 unsigned char threebyte
;
11952 FETCH_DATA (info
, codep
+ 1);
11953 threebyte
= *codep
;
11954 dp
= &dis386_twobyte
[threebyte
];
11955 need_modrm
= twobyte_has_modrm
[*codep
];
11960 dp
= &dis386
[*codep
];
11961 need_modrm
= onebyte_has_modrm
[*codep
];
11965 /* Save sizeflag for printing the extra prefixes later before updating
11966 it for mnemonic and operand processing. The prefix names depend
11967 only on the address mode. */
11968 orig_sizeflag
= sizeflag
;
11969 if (prefixes
& PREFIX_ADDR
)
11971 if ((prefixes
& PREFIX_DATA
))
11977 FETCH_DATA (info
, codep
+ 1);
11978 modrm
.mod
= (*codep
>> 6) & 3;
11979 modrm
.reg
= (*codep
>> 3) & 7;
11980 modrm
.rm
= *codep
& 7;
11986 memset (&vex
, 0, sizeof (vex
));
11988 if (dp
->name
== NULL
&& dp
->op
[0].bytemode
== FLOATCODE
)
11990 get_sib (info
, sizeflag
);
11991 dofloat (sizeflag
);
11995 dp
= get_valid_dis386 (dp
, info
);
11996 if (dp
!= NULL
&& putop (dp
->name
, sizeflag
) == 0)
11998 get_sib (info
, sizeflag
);
11999 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
12002 op_ad
= MAX_OPERANDS
- 1 - i
;
12004 (*dp
->op
[i
].rtn
) (dp
->op
[i
].bytemode
, sizeflag
);
12005 /* For EVEX instruction after the last operand masking
12006 should be printed. */
12007 if (i
== 0 && vex
.evex
)
12009 /* Don't print {%k0}. */
12010 if (vex
.mask_register_specifier
)
12013 oappend (names_mask
[vex
.mask_register_specifier
]);
12023 /* Clear instruction information. */
12026 the_info
->insn_info_valid
= 0;
12027 the_info
->branch_delay_insns
= 0;
12028 the_info
->data_size
= 0;
12029 the_info
->insn_type
= dis_noninsn
;
12030 the_info
->target
= 0;
12031 the_info
->target2
= 0;
12034 /* Reset jump operation indicator. */
12035 op_is_jump
= FALSE
;
12038 int jump_detection
= 0;
12040 /* Extract flags. */
12041 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
12043 if ((dp
->op
[i
].rtn
== OP_J
)
12044 || (dp
->op
[i
].rtn
== OP_indirE
))
12045 jump_detection
|= 1;
12046 else if ((dp
->op
[i
].rtn
== BND_Fixup
)
12047 || (!dp
->op
[i
].rtn
&& !dp
->op
[i
].bytemode
))
12048 jump_detection
|= 2;
12049 else if ((dp
->op
[i
].bytemode
== cond_jump_mode
)
12050 || (dp
->op
[i
].bytemode
== loop_jcxz_mode
))
12051 jump_detection
|= 4;
12054 /* Determine if this is a jump or branch. */
12055 if ((jump_detection
& 0x3) == 0x3)
12058 if (jump_detection
& 0x4)
12059 the_info
->insn_type
= dis_condbranch
;
12061 the_info
->insn_type
=
12062 (dp
->name
&& !strncmp(dp
->name
, "call", 4))
12063 ? dis_jsr
: dis_branch
;
12067 /* If VEX.vvvv and EVEX.vvvv are unused, they must be all 1s, which
12068 are all 0s in inverted form. */
12069 if (need_vex
&& vex
.register_specifier
!= 0)
12071 (*info
->fprintf_func
) (info
->stream
, "(bad)");
12072 return end_codep
- priv
.the_buffer
;
12075 /* Check if the REX prefix is used. */
12076 if ((rex
^ rex_used
) == 0 && !need_vex
&& last_rex_prefix
>= 0)
12077 all_prefixes
[last_rex_prefix
] = 0;
12079 /* Check if the SEG prefix is used. */
12080 if ((prefixes
& (PREFIX_CS
| PREFIX_SS
| PREFIX_DS
| PREFIX_ES
12081 | PREFIX_FS
| PREFIX_GS
)) != 0
12082 && (used_prefixes
& active_seg_prefix
) != 0)
12083 all_prefixes
[last_seg_prefix
] = 0;
12085 /* Check if the ADDR prefix is used. */
12086 if ((prefixes
& PREFIX_ADDR
) != 0
12087 && (used_prefixes
& PREFIX_ADDR
) != 0)
12088 all_prefixes
[last_addr_prefix
] = 0;
12090 /* Check if the DATA prefix is used. */
12091 if ((prefixes
& PREFIX_DATA
) != 0
12092 && (used_prefixes
& PREFIX_DATA
) != 0
12094 all_prefixes
[last_data_prefix
] = 0;
12096 /* Print the extra prefixes. */
12098 for (i
= 0; i
< (int) ARRAY_SIZE (all_prefixes
); i
++)
12099 if (all_prefixes
[i
])
12102 name
= prefix_name (all_prefixes
[i
], orig_sizeflag
);
12105 prefix_length
+= strlen (name
) + 1;
12106 (*info
->fprintf_func
) (info
->stream
, "%s ", name
);
12109 /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
12110 unused, opcode is invalid. Since the PREFIX_DATA prefix may be
12111 used by putop and MMX/SSE operand and may be overriden by the
12112 PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
12114 if (dp
->prefix_requirement
== PREFIX_OPCODE
12116 ? vex
.prefix
== REPE_PREFIX_OPCODE
12117 || vex
.prefix
== REPNE_PREFIX_OPCODE
12119 & (PREFIX_REPZ
| PREFIX_REPNZ
)) != 0)
12121 & (PREFIX_REPZ
| PREFIX_REPNZ
)) == 0)
12123 ? vex
.prefix
== DATA_PREFIX_OPCODE
12125 & (PREFIX_REPZ
| PREFIX_REPNZ
| PREFIX_DATA
))
12127 && (used_prefixes
& PREFIX_DATA
) == 0))
12128 || (vex
.evex
&& !vex
.w
!= !(used_prefixes
& PREFIX_DATA
))))
12130 (*info
->fprintf_func
) (info
->stream
, "(bad)");
12131 return end_codep
- priv
.the_buffer
;
12134 /* Check maximum code length. */
12135 if ((codep
- start_codep
) > MAX_CODE_LENGTH
)
12137 (*info
->fprintf_func
) (info
->stream
, "(bad)");
12138 return MAX_CODE_LENGTH
;
12141 obufp
= mnemonicendp
;
12142 for (i
= strlen (obuf
) + prefix_length
; i
< 6; i
++)
12145 (*info
->fprintf_func
) (info
->stream
, "%s", obuf
);
12147 /* The enter and bound instructions are printed with operands in the same
12148 order as the intel book; everything else is printed in reverse order. */
12149 if (intel_syntax
|| two_source_ops
)
12153 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
12154 op_txt
[i
] = op_out
[i
];
12156 if (intel_syntax
&& dp
&& dp
->op
[2].rtn
== OP_Rounding
12157 && dp
->op
[3].rtn
== OP_E
&& dp
->op
[4].rtn
== NULL
)
12159 op_txt
[2] = op_out
[3];
12160 op_txt
[3] = op_out
[2];
12163 for (i
= 0; i
< (MAX_OPERANDS
>> 1); ++i
)
12165 op_ad
= op_index
[i
];
12166 op_index
[i
] = op_index
[MAX_OPERANDS
- 1 - i
];
12167 op_index
[MAX_OPERANDS
- 1 - i
] = op_ad
;
12168 riprel
= op_riprel
[i
];
12169 op_riprel
[i
] = op_riprel
[MAX_OPERANDS
- 1 - i
];
12170 op_riprel
[MAX_OPERANDS
- 1 - i
] = riprel
;
12175 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
12176 op_txt
[MAX_OPERANDS
- 1 - i
] = op_out
[i
];
12180 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
12184 (*info
->fprintf_func
) (info
->stream
, ",");
12185 if (op_index
[i
] != -1 && !op_riprel
[i
])
12187 bfd_vma target
= (bfd_vma
) op_address
[op_index
[i
]];
12189 if (the_info
&& op_is_jump
)
12191 the_info
->insn_info_valid
= 1;
12192 the_info
->branch_delay_insns
= 0;
12193 the_info
->data_size
= 0;
12194 the_info
->target
= target
;
12195 the_info
->target2
= 0;
12197 (*info
->print_address_func
) (target
, info
);
12200 (*info
->fprintf_func
) (info
->stream
, "%s", op_txt
[i
]);
12204 for (i
= 0; i
< MAX_OPERANDS
; i
++)
12205 if (op_index
[i
] != -1 && op_riprel
[i
])
12207 (*info
->fprintf_func
) (info
->stream
, " # ");
12208 (*info
->print_address_func
) ((bfd_vma
) (start_pc
+ (codep
- start_codep
)
12209 + op_address
[op_index
[i
]]), info
);
12212 return codep
- priv
.the_buffer
;
12215 static const char *float_mem
[] = {
12290 static const unsigned char float_mem_mode
[] = {
12365 #define ST { OP_ST, 0 }
12366 #define STi { OP_STi, 0 }
12368 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
12369 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
12370 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
12371 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
12372 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
12373 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
12374 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
12375 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
12376 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
12378 static const struct dis386 float_reg
[][8] = {
12381 { "fadd", { ST
, STi
}, 0 },
12382 { "fmul", { ST
, STi
}, 0 },
12383 { "fcom", { STi
}, 0 },
12384 { "fcomp", { STi
}, 0 },
12385 { "fsub", { ST
, STi
}, 0 },
12386 { "fsubr", { ST
, STi
}, 0 },
12387 { "fdiv", { ST
, STi
}, 0 },
12388 { "fdivr", { ST
, STi
}, 0 },
12392 { "fld", { STi
}, 0 },
12393 { "fxch", { STi
}, 0 },
12403 { "fcmovb", { ST
, STi
}, 0 },
12404 { "fcmove", { ST
, STi
}, 0 },
12405 { "fcmovbe",{ ST
, STi
}, 0 },
12406 { "fcmovu", { ST
, STi
}, 0 },
12414 { "fcmovnb",{ ST
, STi
}, 0 },
12415 { "fcmovne",{ ST
, STi
}, 0 },
12416 { "fcmovnbe",{ ST
, STi
}, 0 },
12417 { "fcmovnu",{ ST
, STi
}, 0 },
12419 { "fucomi", { ST
, STi
}, 0 },
12420 { "fcomi", { ST
, STi
}, 0 },
12425 { "fadd", { STi
, ST
}, 0 },
12426 { "fmul", { STi
, ST
}, 0 },
12429 { "fsub{!M|r}", { STi
, ST
}, 0 },
12430 { "fsub{M|}", { STi
, ST
}, 0 },
12431 { "fdiv{!M|r}", { STi
, ST
}, 0 },
12432 { "fdiv{M|}", { STi
, ST
}, 0 },
12436 { "ffree", { STi
}, 0 },
12438 { "fst", { STi
}, 0 },
12439 { "fstp", { STi
}, 0 },
12440 { "fucom", { STi
}, 0 },
12441 { "fucomp", { STi
}, 0 },
12447 { "faddp", { STi
, ST
}, 0 },
12448 { "fmulp", { STi
, ST
}, 0 },
12451 { "fsub{!M|r}p", { STi
, ST
}, 0 },
12452 { "fsub{M|}p", { STi
, ST
}, 0 },
12453 { "fdiv{!M|r}p", { STi
, ST
}, 0 },
12454 { "fdiv{M|}p", { STi
, ST
}, 0 },
12458 { "ffreep", { STi
}, 0 },
12463 { "fucomip", { ST
, STi
}, 0 },
12464 { "fcomip", { ST
, STi
}, 0 },
12469 static char *fgrps
[][8] = {
12472 "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12477 "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12482 "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
12487 "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
12492 "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
12497 "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
12502 "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12507 "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
12508 "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
12513 "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12518 "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12523 swap_operand (void)
12525 mnemonicendp
[0] = '.';
12526 mnemonicendp
[1] = 's';
12531 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED
,
12532 int sizeflag ATTRIBUTE_UNUSED
)
12534 /* Skip mod/rm byte. */
12540 dofloat (int sizeflag
)
12542 const struct dis386
*dp
;
12543 unsigned char floatop
;
12545 floatop
= codep
[-1];
12547 if (modrm
.mod
!= 3)
12549 int fp_indx
= (floatop
- 0xd8) * 8 + modrm
.reg
;
12551 putop (float_mem
[fp_indx
], sizeflag
);
12554 OP_E (float_mem_mode
[fp_indx
], sizeflag
);
12557 /* Skip mod/rm byte. */
12561 dp
= &float_reg
[floatop
- 0xd8][modrm
.reg
];
12562 if (dp
->name
== NULL
)
12564 putop (fgrps
[dp
->op
[0].bytemode
][modrm
.rm
], sizeflag
);
12566 /* Instruction fnstsw is only one with strange arg. */
12567 if (floatop
== 0xdf && codep
[-1] == 0xe0)
12568 strcpy (op_out
[0], names16
[0]);
12572 putop (dp
->name
, sizeflag
);
12577 (*dp
->op
[0].rtn
) (dp
->op
[0].bytemode
, sizeflag
);
12582 (*dp
->op
[1].rtn
) (dp
->op
[1].bytemode
, sizeflag
);
12586 /* Like oappend (below), but S is a string starting with '%'.
12587 In Intel syntax, the '%' is elided. */
12589 oappend_maybe_intel (const char *s
)
12591 oappend (s
+ intel_syntax
);
12595 OP_ST (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
12597 oappend_maybe_intel ("%st");
12601 OP_STi (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
12603 sprintf (scratchbuf
, "%%st(%d)", modrm
.rm
);
12604 oappend_maybe_intel (scratchbuf
);
12607 /* Capital letters in template are macros. */
12609 putop (const char *in_template
, int sizeflag
)
12614 unsigned int l
= 0, len
= 0;
12617 for (p
= in_template
; *p
; p
++)
12621 if (l
>= sizeof (last
) || !ISUPPER (*p
))
12640 while (*++p
!= '|')
12641 if (*p
== '}' || *p
== '\0')
12647 while (*++p
!= '}')
12659 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
12668 if (sizeflag
& SUFFIX_ALWAYS
)
12671 else if (l
== 1 && last
[0] == 'L')
12673 if (address_mode
== mode_64bit
12674 && !(prefixes
& PREFIX_ADDR
))
12687 if (intel_syntax
&& !alt
)
12689 if ((prefixes
& PREFIX_DATA
) || (sizeflag
& SUFFIX_ALWAYS
))
12691 if (sizeflag
& DFLAG
)
12692 *obufp
++ = intel_syntax
? 'd' : 'l';
12694 *obufp
++ = intel_syntax
? 'w' : 's';
12695 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12699 if (intel_syntax
|| !(sizeflag
& SUFFIX_ALWAYS
))
12702 if (modrm
.mod
== 3)
12708 if (sizeflag
& DFLAG
)
12709 *obufp
++ = intel_syntax
? 'd' : 'l';
12712 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12718 case 'E': /* For jcxz/jecxz */
12719 if (address_mode
== mode_64bit
)
12721 if (sizeflag
& AFLAG
)
12727 if (sizeflag
& AFLAG
)
12729 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
12734 if ((prefixes
& PREFIX_ADDR
) || (sizeflag
& SUFFIX_ALWAYS
))
12736 if (sizeflag
& AFLAG
)
12737 *obufp
++ = address_mode
== mode_64bit
? 'q' : 'l';
12739 *obufp
++ = address_mode
== mode_64bit
? 'l' : 'w';
12740 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
12744 if (intel_syntax
|| (obufp
[-1] != 's' && !(sizeflag
& SUFFIX_ALWAYS
)))
12746 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
12750 if (!(rex
& REX_W
))
12751 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12756 if ((prefixes
& (PREFIX_CS
| PREFIX_DS
)) == PREFIX_CS
12757 || (prefixes
& (PREFIX_CS
| PREFIX_DS
)) == PREFIX_DS
)
12759 used_prefixes
|= prefixes
& (PREFIX_CS
| PREFIX_DS
);
12762 if (prefixes
& PREFIX_DS
)
12778 if (l
!= 1 || last
[0] != 'X')
12780 if (!need_vex
|| !vex
.evex
)
12783 || ((modrm
.mod
== 3 || vex
.b
) && !(sizeflag
& SUFFIX_ALWAYS
)))
12785 switch (vex
.length
)
12803 if (address_mode
== mode_64bit
&& (sizeflag
& SUFFIX_ALWAYS
))
12808 /* Fall through. */
12816 if (sizeflag
& SUFFIX_ALWAYS
)
12820 if (intel_mnemonic
!= cond
)
12824 if ((prefixes
& PREFIX_FWAIT
) == 0)
12827 used_prefixes
|= PREFIX_FWAIT
;
12833 else if (intel_syntax
&& (sizeflag
& DFLAG
))
12837 if (!(rex
& REX_W
))
12838 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12842 && address_mode
== mode_64bit
12843 && isa64
== intel64
)
12848 /* Fall through. */
12851 && address_mode
== mode_64bit
12852 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
12857 /* Fall through. */
12865 if ((rex
& REX_W
) == 0
12866 && (prefixes
& PREFIX_DATA
))
12868 if ((sizeflag
& DFLAG
) == 0)
12870 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12874 if ((prefixes
& PREFIX_DATA
)
12876 || (sizeflag
& SUFFIX_ALWAYS
))
12883 if (sizeflag
& DFLAG
)
12887 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12891 else if (l
== 1 && last
[0] == 'L')
12893 if ((prefixes
& PREFIX_DATA
)
12895 || (sizeflag
& SUFFIX_ALWAYS
))
12902 if (sizeflag
& DFLAG
)
12903 *obufp
++ = intel_syntax
? 'd' : 'l';
12906 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12916 if (address_mode
== mode_64bit
12917 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
12919 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
12923 /* Fall through. */
12929 if (intel_syntax
&& !alt
)
12932 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
12938 if (sizeflag
& DFLAG
)
12939 *obufp
++ = intel_syntax
? 'd' : 'l';
12942 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12946 else if (l
== 1 && last
[0] == 'L')
12948 if ((intel_syntax
&& need_modrm
)
12949 || (modrm
.mod
== 3 && !(sizeflag
& SUFFIX_ALWAYS
)))
12956 else if((address_mode
== mode_64bit
&& need_modrm
)
12957 || (sizeflag
& SUFFIX_ALWAYS
))
12958 *obufp
++ = intel_syntax
? 'd' : 'l';
12967 else if (sizeflag
& DFLAG
)
12976 if (intel_syntax
&& !p
[1]
12977 && ((rex
& REX_W
) || (sizeflag
& DFLAG
)))
12979 if (!(rex
& REX_W
))
12980 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12987 if (address_mode
== mode_64bit
12988 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
12990 if (sizeflag
& SUFFIX_ALWAYS
)
12995 else if (l
== 1 && last
[0] == 'L')
13006 /* Fall through. */
13014 if (sizeflag
& SUFFIX_ALWAYS
)
13020 if (sizeflag
& DFLAG
)
13024 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13028 else if (l
== 1 && last
[0] == 'L')
13030 if (address_mode
== mode_64bit
13031 && !(prefixes
& PREFIX_ADDR
))
13047 ? vex
.prefix
== DATA_PREFIX_OPCODE
13048 : prefixes
& PREFIX_DATA
)
13051 used_prefixes
|= PREFIX_DATA
;
13057 if (l
== 1 && last
[0] == 'X')
13062 || ((modrm
.mod
== 3 || vex
.b
) && !(sizeflag
& SUFFIX_ALWAYS
)))
13064 switch (vex
.length
)
13084 /* operand size flag for cwtl, cbtw */
13093 else if (sizeflag
& DFLAG
)
13097 if (!(rex
& REX_W
))
13098 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13104 if (last
[0] == 'X')
13105 *obufp
++ = vex
.w
? 'd': 's';
13106 else if (last
[0] == 'L')
13107 *obufp
++ = vex
.w
? 'q': 'd';
13117 if (isa64
== intel64
&& (rex
& REX_W
))
13123 if ((prefixes
& PREFIX_DATA
) || (sizeflag
& SUFFIX_ALWAYS
))
13125 if (sizeflag
& DFLAG
)
13129 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13135 if (address_mode
== mode_64bit
13136 && (isa64
== intel64
13137 || ((sizeflag
& DFLAG
) || (rex
& REX_W
))))
13139 else if ((prefixes
& PREFIX_DATA
))
13141 if (!(sizeflag
& DFLAG
))
13143 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13152 mnemonicendp
= obufp
;
13157 oappend (const char *s
)
13159 obufp
= stpcpy (obufp
, s
);
13165 /* Only print the active segment register. */
13166 if (!active_seg_prefix
)
13169 used_prefixes
|= active_seg_prefix
;
13170 switch (active_seg_prefix
)
13173 oappend_maybe_intel ("%cs:");
13176 oappend_maybe_intel ("%ds:");
13179 oappend_maybe_intel ("%ss:");
13182 oappend_maybe_intel ("%es:");
13185 oappend_maybe_intel ("%fs:");
13188 oappend_maybe_intel ("%gs:");
13196 OP_indirE (int bytemode
, int sizeflag
)
13200 OP_E (bytemode
, sizeflag
);
13204 print_operand_value (char *buf
, int hex
, bfd_vma disp
)
13206 if (address_mode
== mode_64bit
)
13214 sprintf_vma (tmp
, disp
);
13215 for (i
= 0; tmp
[i
] == '0' && tmp
[i
+ 1]; i
++);
13216 strcpy (buf
+ 2, tmp
+ i
);
13220 bfd_signed_vma v
= disp
;
13227 /* Check for possible overflow on 0x8000000000000000. */
13230 strcpy (buf
, "9223372036854775808");
13244 tmp
[28 - i
] = (v
% 10) + '0';
13248 strcpy (buf
, tmp
+ 29 - i
);
13254 sprintf (buf
, "0x%x", (unsigned int) disp
);
13256 sprintf (buf
, "%d", (int) disp
);
13260 /* Put DISP in BUF as signed hex number. */
13263 print_displacement (char *buf
, bfd_vma disp
)
13265 bfd_signed_vma val
= disp
;
13274 /* Check for possible overflow. */
13277 switch (address_mode
)
13280 strcpy (buf
+ j
, "0x8000000000000000");
13283 strcpy (buf
+ j
, "0x80000000");
13286 strcpy (buf
+ j
, "0x8000");
13296 sprintf_vma (tmp
, (bfd_vma
) val
);
13297 for (i
= 0; tmp
[i
] == '0'; i
++)
13299 if (tmp
[i
] == '\0')
13301 strcpy (buf
+ j
, tmp
+ i
);
13305 intel_operand_size (int bytemode
, int sizeflag
)
13309 && (bytemode
== x_mode
13310 || bytemode
== evex_half_bcst_xmmq_mode
))
13313 oappend ("QWORD PTR ");
13315 oappend ("DWORD PTR ");
13324 oappend ("BYTE PTR ");
13329 oappend ("WORD PTR ");
13332 if (address_mode
== mode_64bit
&& isa64
== intel64
)
13334 oappend ("QWORD PTR ");
13337 /* Fall through. */
13339 if (address_mode
== mode_64bit
&& ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
13341 oappend ("QWORD PTR ");
13344 /* Fall through. */
13350 oappend ("QWORD PTR ");
13353 if ((sizeflag
& DFLAG
) || bytemode
== dq_mode
)
13354 oappend ("DWORD PTR ");
13356 oappend ("WORD PTR ");
13357 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13361 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
13363 oappend ("WORD PTR ");
13364 if (!(rex
& REX_W
))
13365 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13368 if (sizeflag
& DFLAG
)
13369 oappend ("QWORD PTR ");
13371 oappend ("DWORD PTR ");
13372 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13375 if (!(sizeflag
& DFLAG
) && isa64
== intel64
)
13376 oappend ("WORD PTR ");
13378 oappend ("DWORD PTR ");
13379 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13382 case d_scalar_swap_mode
:
13385 oappend ("DWORD PTR ");
13388 case q_scalar_swap_mode
:
13390 oappend ("QWORD PTR ");
13393 if (address_mode
== mode_64bit
)
13394 oappend ("QWORD PTR ");
13396 oappend ("DWORD PTR ");
13399 if (sizeflag
& DFLAG
)
13400 oappend ("FWORD PTR ");
13402 oappend ("DWORD PTR ");
13403 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13406 oappend ("TBYTE PTR ");
13410 case evex_x_gscat_mode
:
13411 case evex_x_nobcst_mode
:
13412 case b_scalar_mode
:
13413 case w_scalar_mode
:
13416 switch (vex
.length
)
13419 oappend ("XMMWORD PTR ");
13422 oappend ("YMMWORD PTR ");
13425 oappend ("ZMMWORD PTR ");
13432 oappend ("XMMWORD PTR ");
13435 oappend ("XMMWORD PTR ");
13438 oappend ("YMMWORD PTR ");
13441 case evex_half_bcst_xmmq_mode
:
13445 switch (vex
.length
)
13448 oappend ("QWORD PTR ");
13451 oappend ("XMMWORD PTR ");
13454 oappend ("YMMWORD PTR ");
13464 switch (vex
.length
)
13469 oappend ("BYTE PTR ");
13479 switch (vex
.length
)
13484 oappend ("WORD PTR ");
13494 switch (vex
.length
)
13499 oappend ("DWORD PTR ");
13509 switch (vex
.length
)
13514 oappend ("QWORD PTR ");
13524 switch (vex
.length
)
13527 oappend ("WORD PTR ");
13530 oappend ("DWORD PTR ");
13533 oappend ("QWORD PTR ");
13543 switch (vex
.length
)
13546 oappend ("DWORD PTR ");
13549 oappend ("QWORD PTR ");
13552 oappend ("XMMWORD PTR ");
13562 switch (vex
.length
)
13565 oappend ("QWORD PTR ");
13568 oappend ("YMMWORD PTR ");
13571 oappend ("ZMMWORD PTR ");
13581 switch (vex
.length
)
13585 oappend ("XMMWORD PTR ");
13592 oappend ("OWORD PTR ");
13594 case vex_scalar_w_dq_mode
:
13599 oappend ("QWORD PTR ");
13601 oappend ("DWORD PTR ");
13603 case vex_vsib_d_w_dq_mode
:
13604 case vex_vsib_q_w_dq_mode
:
13611 oappend ("QWORD PTR ");
13613 oappend ("DWORD PTR ");
13617 switch (vex
.length
)
13620 oappend ("XMMWORD PTR ");
13623 oappend ("YMMWORD PTR ");
13626 oappend ("ZMMWORD PTR ");
13633 case vex_vsib_q_w_d_mode
:
13634 case vex_vsib_d_w_d_mode
:
13635 if (!need_vex
|| !vex
.evex
)
13638 switch (vex
.length
)
13641 oappend ("QWORD PTR ");
13644 oappend ("XMMWORD PTR ");
13647 oappend ("YMMWORD PTR ");
13655 if (!need_vex
|| vex
.length
!= 128)
13658 oappend ("DWORD PTR ");
13660 oappend ("BYTE PTR ");
13666 oappend ("QWORD PTR ");
13668 oappend ("WORD PTR ");
13678 OP_E_register (int bytemode
, int sizeflag
)
13680 int reg
= modrm
.rm
;
13681 const char **names
;
13687 if ((sizeflag
& SUFFIX_ALWAYS
)
13688 && (bytemode
== b_swap_mode
13689 || bytemode
== bnd_swap_mode
13690 || bytemode
== v_swap_mode
))
13716 names
= address_mode
== mode_64bit
? names64
: names32
;
13719 case bnd_swap_mode
:
13728 if (address_mode
== mode_64bit
&& isa64
== intel64
)
13733 /* Fall through. */
13735 if (address_mode
== mode_64bit
&& ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
13741 /* Fall through. */
13753 if ((sizeflag
& DFLAG
)
13754 || (bytemode
!= v_mode
13755 && bytemode
!= v_swap_mode
))
13759 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13763 if (!(sizeflag
& DFLAG
) && isa64
== intel64
)
13767 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13770 names
= (address_mode
== mode_64bit
13771 ? names64
: names32
);
13772 if (!(prefixes
& PREFIX_ADDR
))
13773 names
= (address_mode
== mode_16bit
13774 ? names16
: names
);
13777 /* Remove "addr16/addr32". */
13778 all_prefixes
[last_addr_prefix
] = 0;
13779 names
= (address_mode
!= mode_32bit
13780 ? names32
: names16
);
13781 used_prefixes
|= PREFIX_ADDR
;
13791 names
= names_mask
;
13796 oappend (INTERNAL_DISASSEMBLER_ERROR
);
13799 oappend (names
[reg
]);
13803 OP_E_memory (int bytemode
, int sizeflag
)
13806 int add
= (rex
& REX_B
) ? 8 : 0;
13812 /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0. */
13814 && bytemode
!= x_mode
13815 && bytemode
!= xmmq_mode
13816 && bytemode
!= evex_half_bcst_xmmq_mode
)
13832 if (address_mode
!= mode_64bit
)
13838 case vex_scalar_w_dq_mode
:
13839 case vex_vsib_d_w_dq_mode
:
13840 case vex_vsib_d_w_d_mode
:
13841 case vex_vsib_q_w_dq_mode
:
13842 case vex_vsib_q_w_d_mode
:
13843 case evex_x_gscat_mode
:
13844 shift
= vex
.w
? 3 : 2;
13847 case evex_half_bcst_xmmq_mode
:
13851 shift
= vex
.w
? 3 : 2;
13854 /* Fall through. */
13858 case evex_x_nobcst_mode
:
13860 switch (vex
.length
)
13884 case q_scalar_swap_mode
:
13891 case d_scalar_swap_mode
:
13894 case w_scalar_mode
:
13898 case b_scalar_mode
:
13905 /* Make necessary corrections to shift for modes that need it.
13906 For these modes we currently have shift 4, 5 or 6 depending on
13907 vex.length (it corresponds to xmmword, ymmword or zmmword
13908 operand). We might want to make it 3, 4 or 5 (e.g. for
13909 xmmq_mode). In case of broadcast enabled the corrections
13910 aren't needed, as element size is always 32 or 64 bits. */
13912 && (bytemode
== xmmq_mode
13913 || bytemode
== evex_half_bcst_xmmq_mode
))
13915 else if (bytemode
== xmmqd_mode
)
13917 else if (bytemode
== xmmdw_mode
)
13919 else if (bytemode
== ymmq_mode
&& vex
.length
== 128)
13927 intel_operand_size (bytemode
, sizeflag
);
13930 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
13932 /* 32/64 bit address mode */
13942 int addr32flag
= !((sizeflag
& AFLAG
)
13943 || bytemode
== v_bnd_mode
13944 || bytemode
== v_bndmk_mode
13945 || bytemode
== bnd_mode
13946 || bytemode
== bnd_swap_mode
);
13947 const char **indexes64
= names64
;
13948 const char **indexes32
= names32
;
13958 vindex
= sib
.index
;
13964 case vex_vsib_d_w_dq_mode
:
13965 case vex_vsib_d_w_d_mode
:
13966 case vex_vsib_q_w_dq_mode
:
13967 case vex_vsib_q_w_d_mode
:
13977 switch (vex
.length
)
13980 indexes64
= indexes32
= names_xmm
;
13984 || bytemode
== vex_vsib_q_w_dq_mode
13985 || bytemode
== vex_vsib_q_w_d_mode
)
13986 indexes64
= indexes32
= names_ymm
;
13988 indexes64
= indexes32
= names_xmm
;
13992 || bytemode
== vex_vsib_q_w_dq_mode
13993 || bytemode
== vex_vsib_q_w_d_mode
)
13994 indexes64
= indexes32
= names_zmm
;
13996 indexes64
= indexes32
= names_ymm
;
14003 haveindex
= vindex
!= 4;
14010 rbase
= base
+ add
;
14018 if (address_mode
== mode_64bit
&& !havesib
)
14021 if (riprel
&& bytemode
== v_bndmk_mode
)
14029 FETCH_DATA (the_info
, codep
+ 1);
14031 if ((disp
& 0x80) != 0)
14033 if (vex
.evex
&& shift
> 0)
14046 && address_mode
!= mode_16bit
)
14048 if (address_mode
== mode_64bit
)
14050 /* Display eiz instead of addr32. */
14051 needindex
= addr32flag
;
14056 /* In 32-bit mode, we need index register to tell [offset]
14057 from [eiz*1 + offset]. */
14062 havedisp
= (havebase
14064 || (havesib
&& (haveindex
|| scale
!= 0)));
14067 if (modrm
.mod
!= 0 || base
== 5)
14069 if (havedisp
|| riprel
)
14070 print_displacement (scratchbuf
, disp
);
14072 print_operand_value (scratchbuf
, 1, disp
);
14073 oappend (scratchbuf
);
14077 oappend (!addr32flag
? "(%rip)" : "(%eip)");
14081 if ((havebase
|| haveindex
|| needindex
|| needaddr32
|| riprel
)
14082 && (address_mode
!= mode_64bit
14083 || ((bytemode
!= v_bnd_mode
)
14084 && (bytemode
!= v_bndmk_mode
)
14085 && (bytemode
!= bnd_mode
)
14086 && (bytemode
!= bnd_swap_mode
))))
14087 used_prefixes
|= PREFIX_ADDR
;
14089 if (havedisp
|| (intel_syntax
&& riprel
))
14091 *obufp
++ = open_char
;
14092 if (intel_syntax
&& riprel
)
14095 oappend (!addr32flag
? "rip" : "eip");
14099 oappend (address_mode
== mode_64bit
&& !addr32flag
14100 ? names64
[rbase
] : names32
[rbase
]);
14103 /* ESP/RSP won't allow index. If base isn't ESP/RSP,
14104 print index to tell base + index from base. */
14108 || (havebase
&& base
!= ESP_REG_NUM
))
14110 if (!intel_syntax
|| havebase
)
14112 *obufp
++ = separator_char
;
14116 oappend (address_mode
== mode_64bit
&& !addr32flag
14117 ? indexes64
[vindex
] : indexes32
[vindex
]);
14119 oappend (address_mode
== mode_64bit
&& !addr32flag
14120 ? index64
: index32
);
14122 *obufp
++ = scale_char
;
14124 sprintf (scratchbuf
, "%d", 1 << scale
);
14125 oappend (scratchbuf
);
14129 && (disp
|| modrm
.mod
!= 0 || base
== 5))
14131 if (!havedisp
|| (bfd_signed_vma
) disp
>= 0)
14136 else if (modrm
.mod
!= 1 && disp
!= -disp
)
14140 disp
= - (bfd_signed_vma
) disp
;
14144 print_displacement (scratchbuf
, disp
);
14146 print_operand_value (scratchbuf
, 1, disp
);
14147 oappend (scratchbuf
);
14150 *obufp
++ = close_char
;
14153 else if (intel_syntax
)
14155 if (modrm
.mod
!= 0 || base
== 5)
14157 if (!active_seg_prefix
)
14159 oappend (names_seg
[ds_reg
- es_reg
]);
14162 print_operand_value (scratchbuf
, 1, disp
);
14163 oappend (scratchbuf
);
14167 else if (bytemode
== v_bnd_mode
14168 || bytemode
== v_bndmk_mode
14169 || bytemode
== bnd_mode
14170 || bytemode
== bnd_swap_mode
)
14177 /* 16 bit address mode */
14178 used_prefixes
|= prefixes
& PREFIX_ADDR
;
14185 if ((disp
& 0x8000) != 0)
14190 FETCH_DATA (the_info
, codep
+ 1);
14192 if ((disp
& 0x80) != 0)
14194 if (vex
.evex
&& shift
> 0)
14199 if ((disp
& 0x8000) != 0)
14205 if (modrm
.mod
!= 0 || modrm
.rm
== 6)
14207 print_displacement (scratchbuf
, disp
);
14208 oappend (scratchbuf
);
14211 if (modrm
.mod
!= 0 || modrm
.rm
!= 6)
14213 *obufp
++ = open_char
;
14215 oappend (index16
[modrm
.rm
]);
14217 && (disp
|| modrm
.mod
!= 0 || modrm
.rm
== 6))
14219 if ((bfd_signed_vma
) disp
>= 0)
14224 else if (modrm
.mod
!= 1)
14228 disp
= - (bfd_signed_vma
) disp
;
14231 print_displacement (scratchbuf
, disp
);
14232 oappend (scratchbuf
);
14235 *obufp
++ = close_char
;
14238 else if (intel_syntax
)
14240 if (!active_seg_prefix
)
14242 oappend (names_seg
[ds_reg
- es_reg
]);
14245 print_operand_value (scratchbuf
, 1, disp
& 0xffff);
14246 oappend (scratchbuf
);
14249 if (vex
.evex
&& vex
.b
14250 && (bytemode
== x_mode
14251 || bytemode
== xmmq_mode
14252 || bytemode
== evex_half_bcst_xmmq_mode
))
14255 || bytemode
== xmmq_mode
14256 || bytemode
== evex_half_bcst_xmmq_mode
)
14258 switch (vex
.length
)
14261 oappend ("{1to2}");
14264 oappend ("{1to4}");
14267 oappend ("{1to8}");
14275 switch (vex
.length
)
14278 oappend ("{1to4}");
14281 oappend ("{1to8}");
14284 oappend ("{1to16}");
14294 OP_E (int bytemode
, int sizeflag
)
14296 /* Skip mod/rm byte. */
14300 if (modrm
.mod
== 3)
14301 OP_E_register (bytemode
, sizeflag
);
14303 OP_E_memory (bytemode
, sizeflag
);
14307 OP_G (int bytemode
, int sizeflag
)
14310 const char **names
;
14319 oappend (names8rex
[modrm
.reg
+ add
]);
14321 oappend (names8
[modrm
.reg
+ add
]);
14324 oappend (names16
[modrm
.reg
+ add
]);
14329 oappend (names32
[modrm
.reg
+ add
]);
14332 oappend (names64
[modrm
.reg
+ add
]);
14335 if (modrm
.reg
> 0x3)
14340 oappend (names_bnd
[modrm
.reg
]);
14350 oappend (names64
[modrm
.reg
+ add
]);
14353 if ((sizeflag
& DFLAG
)
14354 || (bytemode
!= v_mode
&& bytemode
!= movsxd_mode
))
14355 oappend (names32
[modrm
.reg
+ add
]);
14357 oappend (names16
[modrm
.reg
+ add
]);
14358 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14362 names
= (address_mode
== mode_64bit
14363 ? names64
: names32
);
14364 if (!(prefixes
& PREFIX_ADDR
))
14366 if (address_mode
== mode_16bit
)
14371 /* Remove "addr16/addr32". */
14372 all_prefixes
[last_addr_prefix
] = 0;
14373 names
= (address_mode
!= mode_32bit
14374 ? names32
: names16
);
14375 used_prefixes
|= PREFIX_ADDR
;
14377 oappend (names
[modrm
.reg
+ add
]);
14380 if (address_mode
== mode_64bit
)
14381 oappend (names64
[modrm
.reg
+ add
]);
14383 oappend (names32
[modrm
.reg
+ add
]);
14387 if ((modrm
.reg
+ add
) > 0x7)
14392 oappend (names_mask
[modrm
.reg
+ add
]);
14395 oappend (INTERNAL_DISASSEMBLER_ERROR
);
14408 FETCH_DATA (the_info
, codep
+ 8);
14409 a
= *codep
++ & 0xff;
14410 a
|= (*codep
++ & 0xff) << 8;
14411 a
|= (*codep
++ & 0xff) << 16;
14412 a
|= (*codep
++ & 0xffu
) << 24;
14413 b
= *codep
++ & 0xff;
14414 b
|= (*codep
++ & 0xff) << 8;
14415 b
|= (*codep
++ & 0xff) << 16;
14416 b
|= (*codep
++ & 0xffu
) << 24;
14417 x
= a
+ ((bfd_vma
) b
<< 32);
14425 static bfd_signed_vma
14428 bfd_signed_vma x
= 0;
14430 FETCH_DATA (the_info
, codep
+ 4);
14431 x
= *codep
++ & (bfd_signed_vma
) 0xff;
14432 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 8;
14433 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 16;
14434 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 24;
14438 static bfd_signed_vma
14441 bfd_signed_vma x
= 0;
14443 FETCH_DATA (the_info
, codep
+ 4);
14444 x
= *codep
++ & (bfd_signed_vma
) 0xff;
14445 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 8;
14446 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 16;
14447 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 24;
14449 x
= (x
^ ((bfd_signed_vma
) 1 << 31)) - ((bfd_signed_vma
) 1 << 31);
14459 FETCH_DATA (the_info
, codep
+ 2);
14460 x
= *codep
++ & 0xff;
14461 x
|= (*codep
++ & 0xff) << 8;
14466 set_op (bfd_vma op
, int riprel
)
14468 op_index
[op_ad
] = op_ad
;
14469 if (address_mode
== mode_64bit
)
14471 op_address
[op_ad
] = op
;
14472 op_riprel
[op_ad
] = riprel
;
14476 /* Mask to get a 32-bit address. */
14477 op_address
[op_ad
] = op
& 0xffffffff;
14478 op_riprel
[op_ad
] = riprel
& 0xffffffff;
14483 OP_REG (int code
, int sizeflag
)
14490 case es_reg
: case ss_reg
: case cs_reg
:
14491 case ds_reg
: case fs_reg
: case gs_reg
:
14492 oappend (names_seg
[code
- es_reg
]);
14504 case ax_reg
: case cx_reg
: case dx_reg
: case bx_reg
:
14505 case sp_reg
: case bp_reg
: case si_reg
: case di_reg
:
14506 s
= names16
[code
- ax_reg
+ add
];
14508 case al_reg
: case ah_reg
: case cl_reg
: case ch_reg
:
14509 case dl_reg
: case dh_reg
: case bl_reg
: case bh_reg
:
14512 s
= names8rex
[code
- al_reg
+ add
];
14514 s
= names8
[code
- al_reg
];
14516 case rAX_reg
: case rCX_reg
: case rDX_reg
: case rBX_reg
:
14517 case rSP_reg
: case rBP_reg
: case rSI_reg
: case rDI_reg
:
14518 if (address_mode
== mode_64bit
14519 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
14521 s
= names64
[code
- rAX_reg
+ add
];
14524 code
+= eAX_reg
- rAX_reg
;
14525 /* Fall through. */
14526 case eAX_reg
: case eCX_reg
: case eDX_reg
: case eBX_reg
:
14527 case eSP_reg
: case eBP_reg
: case eSI_reg
: case eDI_reg
:
14530 s
= names64
[code
- eAX_reg
+ add
];
14533 if (sizeflag
& DFLAG
)
14534 s
= names32
[code
- eAX_reg
+ add
];
14536 s
= names16
[code
- eAX_reg
+ add
];
14537 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14541 s
= INTERNAL_DISASSEMBLER_ERROR
;
14548 OP_IMREG (int code
, int sizeflag
)
14560 case ax_reg
: case cx_reg
: case dx_reg
: case bx_reg
:
14561 case sp_reg
: case bp_reg
: case si_reg
: case di_reg
:
14562 s
= names16
[code
- ax_reg
];
14564 case es_reg
: case ss_reg
: case cs_reg
:
14565 case ds_reg
: case fs_reg
: case gs_reg
:
14566 s
= names_seg
[code
- es_reg
];
14568 case al_reg
: case ah_reg
: case cl_reg
: case ch_reg
:
14569 case dl_reg
: case dh_reg
: case bl_reg
: case bh_reg
:
14572 s
= names8rex
[code
- al_reg
];
14574 s
= names8
[code
- al_reg
];
14576 case eAX_reg
: case eCX_reg
: case eDX_reg
: case eBX_reg
:
14577 case eSP_reg
: case eBP_reg
: case eSI_reg
: case eDI_reg
:
14580 s
= names64
[code
- eAX_reg
];
14583 if (sizeflag
& DFLAG
)
14584 s
= names32
[code
- eAX_reg
];
14586 s
= names16
[code
- eAX_reg
];
14587 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14590 case z_mode_ax_reg
:
14591 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
14595 if (!(rex
& REX_W
))
14596 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14599 s
= INTERNAL_DISASSEMBLER_ERROR
;
14606 OP_I (int bytemode
, int sizeflag
)
14609 bfd_signed_vma mask
= -1;
14614 FETCH_DATA (the_info
, codep
+ 1);
14624 if (sizeflag
& DFLAG
)
14634 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14650 oappend (INTERNAL_DISASSEMBLER_ERROR
);
14655 scratchbuf
[0] = '$';
14656 print_operand_value (scratchbuf
+ 1, 1, op
);
14657 oappend_maybe_intel (scratchbuf
);
14658 scratchbuf
[0] = '\0';
14662 OP_I64 (int bytemode
, int sizeflag
)
14664 if (bytemode
!= v_mode
|| address_mode
!= mode_64bit
|| !(rex
& REX_W
))
14666 OP_I (bytemode
, sizeflag
);
14672 scratchbuf
[0] = '$';
14673 print_operand_value (scratchbuf
+ 1, 1, get64 ());
14674 oappend_maybe_intel (scratchbuf
);
14675 scratchbuf
[0] = '\0';
14679 OP_sI (int bytemode
, int sizeflag
)
14687 FETCH_DATA (the_info
, codep
+ 1);
14689 if ((op
& 0x80) != 0)
14691 if (bytemode
== b_T_mode
)
14693 if (address_mode
!= mode_64bit
14694 || !((sizeflag
& DFLAG
) || (rex
& REX_W
)))
14696 /* The operand-size prefix is overridden by a REX prefix. */
14697 if ((sizeflag
& DFLAG
) || (rex
& REX_W
))
14705 if (!(rex
& REX_W
))
14707 if (sizeflag
& DFLAG
)
14715 /* The operand-size prefix is overridden by a REX prefix. */
14716 if ((sizeflag
& DFLAG
) || (rex
& REX_W
))
14722 oappend (INTERNAL_DISASSEMBLER_ERROR
);
14726 scratchbuf
[0] = '$';
14727 print_operand_value (scratchbuf
+ 1, 1, op
);
14728 oappend_maybe_intel (scratchbuf
);
14732 OP_J (int bytemode
, int sizeflag
)
14736 bfd_vma segment
= 0;
14741 FETCH_DATA (the_info
, codep
+ 1);
14743 if ((disp
& 0x80) != 0)
14747 if (isa64
!= intel64
)
14750 if ((sizeflag
& DFLAG
)
14751 || (address_mode
== mode_64bit
14752 && ((isa64
== intel64
&& bytemode
!= dqw_mode
)
14753 || (rex
& REX_W
))))
14758 if ((disp
& 0x8000) != 0)
14760 /* In 16bit mode, address is wrapped around at 64k within
14761 the same segment. Otherwise, a data16 prefix on a jump
14762 instruction means that the pc is masked to 16 bits after
14763 the displacement is added! */
14765 if ((prefixes
& PREFIX_DATA
) == 0)
14766 segment
= ((start_pc
+ (codep
- start_codep
))
14767 & ~((bfd_vma
) 0xffff));
14769 if (address_mode
!= mode_64bit
14770 || (isa64
!= intel64
&& !(rex
& REX_W
)))
14771 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14774 oappend (INTERNAL_DISASSEMBLER_ERROR
);
14777 disp
= ((start_pc
+ (codep
- start_codep
) + disp
) & mask
) | segment
;
14779 print_operand_value (scratchbuf
, 1, disp
);
14780 oappend (scratchbuf
);
14784 OP_SEG (int bytemode
, int sizeflag
)
14786 if (bytemode
== w_mode
)
14787 oappend (names_seg
[modrm
.reg
]);
14789 OP_E (modrm
.mod
== 3 ? bytemode
: w_mode
, sizeflag
);
14793 OP_DIR (int dummy ATTRIBUTE_UNUSED
, int sizeflag
)
14797 if (sizeflag
& DFLAG
)
14807 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14809 sprintf (scratchbuf
, "0x%x:0x%x", seg
, offset
);
14811 sprintf (scratchbuf
, "$0x%x,$0x%x", seg
, offset
);
14812 oappend (scratchbuf
);
14816 OP_OFF (int bytemode
, int sizeflag
)
14820 if (intel_syntax
&& (sizeflag
& SUFFIX_ALWAYS
))
14821 intel_operand_size (bytemode
, sizeflag
);
14824 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
14831 if (!active_seg_prefix
)
14833 oappend (names_seg
[ds_reg
- es_reg
]);
14837 print_operand_value (scratchbuf
, 1, off
);
14838 oappend (scratchbuf
);
14842 OP_OFF64 (int bytemode
, int sizeflag
)
14846 if (address_mode
!= mode_64bit
14847 || (prefixes
& PREFIX_ADDR
))
14849 OP_OFF (bytemode
, sizeflag
);
14853 if (intel_syntax
&& (sizeflag
& SUFFIX_ALWAYS
))
14854 intel_operand_size (bytemode
, sizeflag
);
14861 if (!active_seg_prefix
)
14863 oappend (names_seg
[ds_reg
- es_reg
]);
14867 print_operand_value (scratchbuf
, 1, off
);
14868 oappend (scratchbuf
);
14872 ptr_reg (int code
, int sizeflag
)
14876 *obufp
++ = open_char
;
14877 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
14878 if (address_mode
== mode_64bit
)
14880 if (!(sizeflag
& AFLAG
))
14881 s
= names32
[code
- eAX_reg
];
14883 s
= names64
[code
- eAX_reg
];
14885 else if (sizeflag
& AFLAG
)
14886 s
= names32
[code
- eAX_reg
];
14888 s
= names16
[code
- eAX_reg
];
14890 *obufp
++ = close_char
;
14895 OP_ESreg (int code
, int sizeflag
)
14901 case 0x6d: /* insw/insl */
14902 intel_operand_size (z_mode
, sizeflag
);
14904 case 0xa5: /* movsw/movsl/movsq */
14905 case 0xa7: /* cmpsw/cmpsl/cmpsq */
14906 case 0xab: /* stosw/stosl */
14907 case 0xaf: /* scasw/scasl */
14908 intel_operand_size (v_mode
, sizeflag
);
14911 intel_operand_size (b_mode
, sizeflag
);
14914 oappend_maybe_intel ("%es:");
14915 ptr_reg (code
, sizeflag
);
14919 OP_DSreg (int code
, int sizeflag
)
14925 case 0x6f: /* outsw/outsl */
14926 intel_operand_size (z_mode
, sizeflag
);
14928 case 0xa5: /* movsw/movsl/movsq */
14929 case 0xa7: /* cmpsw/cmpsl/cmpsq */
14930 case 0xad: /* lodsw/lodsl/lodsq */
14931 intel_operand_size (v_mode
, sizeflag
);
14934 intel_operand_size (b_mode
, sizeflag
);
14937 /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
14938 default segment register DS is printed. */
14939 if (!active_seg_prefix
)
14940 active_seg_prefix
= PREFIX_DS
;
14942 ptr_reg (code
, sizeflag
);
14946 OP_C (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
14954 else if (address_mode
!= mode_64bit
&& (prefixes
& PREFIX_LOCK
))
14956 all_prefixes
[last_lock_prefix
] = 0;
14957 used_prefixes
|= PREFIX_LOCK
;
14962 sprintf (scratchbuf
, "%%cr%d", modrm
.reg
+ add
);
14963 oappend_maybe_intel (scratchbuf
);
14967 OP_D (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
14976 sprintf (scratchbuf
, "db%d", modrm
.reg
+ add
);
14978 sprintf (scratchbuf
, "%%db%d", modrm
.reg
+ add
);
14979 oappend (scratchbuf
);
14983 OP_T (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
14985 sprintf (scratchbuf
, "%%tr%d", modrm
.reg
);
14986 oappend_maybe_intel (scratchbuf
);
14990 OP_R (int bytemode
, int sizeflag
)
14992 /* Skip mod/rm byte. */
14995 OP_E_register (bytemode
, sizeflag
);
14999 OP_MMX (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15001 int reg
= modrm
.reg
;
15002 const char **names
;
15004 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15005 if (prefixes
& PREFIX_DATA
)
15014 oappend (names
[reg
]);
15018 OP_XMM (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
15020 int reg
= modrm
.reg
;
15021 const char **names
;
15033 && bytemode
!= xmm_mode
15034 && bytemode
!= xmmq_mode
15035 && bytemode
!= evex_half_bcst_xmmq_mode
15036 && bytemode
!= ymm_mode
15037 && bytemode
!= scalar_mode
)
15039 switch (vex
.length
)
15046 || (bytemode
!= vex_vsib_q_w_dq_mode
15047 && bytemode
!= vex_vsib_q_w_d_mode
))
15059 else if (bytemode
== xmmq_mode
15060 || bytemode
== evex_half_bcst_xmmq_mode
)
15062 switch (vex
.length
)
15075 else if (bytemode
== ymm_mode
)
15079 oappend (names
[reg
]);
15083 OP_EM (int bytemode
, int sizeflag
)
15086 const char **names
;
15088 if (modrm
.mod
!= 3)
15091 && (bytemode
== v_mode
|| bytemode
== v_swap_mode
))
15093 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
15094 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15096 OP_E (bytemode
, sizeflag
);
15100 if ((sizeflag
& SUFFIX_ALWAYS
) && bytemode
== v_swap_mode
)
15103 /* Skip mod/rm byte. */
15106 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15108 if (prefixes
& PREFIX_DATA
)
15117 oappend (names
[reg
]);
15120 /* cvt* are the only instructions in sse2 which have
15121 both SSE and MMX operands and also have 0x66 prefix
15122 in their opcode. 0x66 was originally used to differentiate
15123 between SSE and MMX instruction(operands). So we have to handle the
15124 cvt* separately using OP_EMC and OP_MXC */
15126 OP_EMC (int bytemode
, int sizeflag
)
15128 if (modrm
.mod
!= 3)
15130 if (intel_syntax
&& bytemode
== v_mode
)
15132 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
15133 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15135 OP_E (bytemode
, sizeflag
);
15139 /* Skip mod/rm byte. */
15142 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15143 oappend (names_mm
[modrm
.rm
]);
15147 OP_MXC (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15149 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15150 oappend (names_mm
[modrm
.reg
]);
15154 OP_EX (int bytemode
, int sizeflag
)
15157 const char **names
;
15159 /* Skip mod/rm byte. */
15163 if (modrm
.mod
!= 3)
15165 OP_E_memory (bytemode
, sizeflag
);
15180 if ((sizeflag
& SUFFIX_ALWAYS
)
15181 && (bytemode
== x_swap_mode
15182 || bytemode
== d_swap_mode
15183 || bytemode
== d_scalar_swap_mode
15184 || bytemode
== q_swap_mode
15185 || bytemode
== q_scalar_swap_mode
))
15189 && bytemode
!= xmm_mode
15190 && bytemode
!= xmmdw_mode
15191 && bytemode
!= xmmqd_mode
15192 && bytemode
!= xmm_mb_mode
15193 && bytemode
!= xmm_mw_mode
15194 && bytemode
!= xmm_md_mode
15195 && bytemode
!= xmm_mq_mode
15196 && bytemode
!= xmmq_mode
15197 && bytemode
!= evex_half_bcst_xmmq_mode
15198 && bytemode
!= ymm_mode
15199 && bytemode
!= d_scalar_swap_mode
15200 && bytemode
!= q_scalar_swap_mode
15201 && bytemode
!= vex_scalar_w_dq_mode
)
15203 switch (vex
.length
)
15218 else if (bytemode
== xmmq_mode
15219 || bytemode
== evex_half_bcst_xmmq_mode
)
15221 switch (vex
.length
)
15234 else if (bytemode
== ymm_mode
)
15238 oappend (names
[reg
]);
15242 OP_MS (int bytemode
, int sizeflag
)
15244 if (modrm
.mod
== 3)
15245 OP_EM (bytemode
, sizeflag
);
15251 OP_XS (int bytemode
, int sizeflag
)
15253 if (modrm
.mod
== 3)
15254 OP_EX (bytemode
, sizeflag
);
15260 OP_M (int bytemode
, int sizeflag
)
15262 if (modrm
.mod
== 3)
15263 /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
15266 OP_E (bytemode
, sizeflag
);
15270 OP_0f07 (int bytemode
, int sizeflag
)
15272 if (modrm
.mod
!= 3 || modrm
.rm
!= 0)
15275 OP_E (bytemode
, sizeflag
);
15278 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
15279 32bit mode and "xchg %rax,%rax" in 64bit mode. */
15282 NOP_Fixup1 (int bytemode
, int sizeflag
)
15284 if ((prefixes
& PREFIX_DATA
) != 0
15287 && address_mode
== mode_64bit
))
15288 OP_REG (bytemode
, sizeflag
);
15290 strcpy (obuf
, "nop");
15294 NOP_Fixup2 (int bytemode
, int sizeflag
)
15296 if ((prefixes
& PREFIX_DATA
) != 0
15299 && address_mode
== mode_64bit
))
15300 OP_IMREG (bytemode
, sizeflag
);
15303 static const char *const Suffix3DNow
[] = {
15304 /* 00 */ NULL
, NULL
, NULL
, NULL
,
15305 /* 04 */ NULL
, NULL
, NULL
, NULL
,
15306 /* 08 */ NULL
, NULL
, NULL
, NULL
,
15307 /* 0C */ "pi2fw", "pi2fd", NULL
, NULL
,
15308 /* 10 */ NULL
, NULL
, NULL
, NULL
,
15309 /* 14 */ NULL
, NULL
, NULL
, NULL
,
15310 /* 18 */ NULL
, NULL
, NULL
, NULL
,
15311 /* 1C */ "pf2iw", "pf2id", NULL
, NULL
,
15312 /* 20 */ NULL
, NULL
, NULL
, NULL
,
15313 /* 24 */ NULL
, NULL
, NULL
, NULL
,
15314 /* 28 */ NULL
, NULL
, NULL
, NULL
,
15315 /* 2C */ NULL
, NULL
, NULL
, NULL
,
15316 /* 30 */ NULL
, NULL
, NULL
, NULL
,
15317 /* 34 */ NULL
, NULL
, NULL
, NULL
,
15318 /* 38 */ NULL
, NULL
, NULL
, NULL
,
15319 /* 3C */ NULL
, NULL
, NULL
, NULL
,
15320 /* 40 */ NULL
, NULL
, NULL
, NULL
,
15321 /* 44 */ NULL
, NULL
, NULL
, NULL
,
15322 /* 48 */ NULL
, NULL
, NULL
, NULL
,
15323 /* 4C */ NULL
, NULL
, NULL
, NULL
,
15324 /* 50 */ NULL
, NULL
, NULL
, NULL
,
15325 /* 54 */ NULL
, NULL
, NULL
, NULL
,
15326 /* 58 */ NULL
, NULL
, NULL
, NULL
,
15327 /* 5C */ NULL
, NULL
, NULL
, NULL
,
15328 /* 60 */ NULL
, NULL
, NULL
, NULL
,
15329 /* 64 */ NULL
, NULL
, NULL
, NULL
,
15330 /* 68 */ NULL
, NULL
, NULL
, NULL
,
15331 /* 6C */ NULL
, NULL
, NULL
, NULL
,
15332 /* 70 */ NULL
, NULL
, NULL
, NULL
,
15333 /* 74 */ NULL
, NULL
, NULL
, NULL
,
15334 /* 78 */ NULL
, NULL
, NULL
, NULL
,
15335 /* 7C */ NULL
, NULL
, NULL
, NULL
,
15336 /* 80 */ NULL
, NULL
, NULL
, NULL
,
15337 /* 84 */ NULL
, NULL
, NULL
, NULL
,
15338 /* 88 */ NULL
, NULL
, "pfnacc", NULL
,
15339 /* 8C */ NULL
, NULL
, "pfpnacc", NULL
,
15340 /* 90 */ "pfcmpge", NULL
, NULL
, NULL
,
15341 /* 94 */ "pfmin", NULL
, "pfrcp", "pfrsqrt",
15342 /* 98 */ NULL
, NULL
, "pfsub", NULL
,
15343 /* 9C */ NULL
, NULL
, "pfadd", NULL
,
15344 /* A0 */ "pfcmpgt", NULL
, NULL
, NULL
,
15345 /* A4 */ "pfmax", NULL
, "pfrcpit1", "pfrsqit1",
15346 /* A8 */ NULL
, NULL
, "pfsubr", NULL
,
15347 /* AC */ NULL
, NULL
, "pfacc", NULL
,
15348 /* B0 */ "pfcmpeq", NULL
, NULL
, NULL
,
15349 /* B4 */ "pfmul", NULL
, "pfrcpit2", "pmulhrw",
15350 /* B8 */ NULL
, NULL
, NULL
, "pswapd",
15351 /* BC */ NULL
, NULL
, NULL
, "pavgusb",
15352 /* C0 */ NULL
, NULL
, NULL
, NULL
,
15353 /* C4 */ NULL
, NULL
, NULL
, NULL
,
15354 /* C8 */ NULL
, NULL
, NULL
, NULL
,
15355 /* CC */ NULL
, NULL
, NULL
, NULL
,
15356 /* D0 */ NULL
, NULL
, NULL
, NULL
,
15357 /* D4 */ NULL
, NULL
, NULL
, NULL
,
15358 /* D8 */ NULL
, NULL
, NULL
, NULL
,
15359 /* DC */ NULL
, NULL
, NULL
, NULL
,
15360 /* E0 */ NULL
, NULL
, NULL
, NULL
,
15361 /* E4 */ NULL
, NULL
, NULL
, NULL
,
15362 /* E8 */ NULL
, NULL
, NULL
, NULL
,
15363 /* EC */ NULL
, NULL
, NULL
, NULL
,
15364 /* F0 */ NULL
, NULL
, NULL
, NULL
,
15365 /* F4 */ NULL
, NULL
, NULL
, NULL
,
15366 /* F8 */ NULL
, NULL
, NULL
, NULL
,
15367 /* FC */ NULL
, NULL
, NULL
, NULL
,
15371 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15373 const char *mnemonic
;
15375 FETCH_DATA (the_info
, codep
+ 1);
15376 /* AMD 3DNow! instructions are specified by an opcode suffix in the
15377 place where an 8-bit immediate would normally go. ie. the last
15378 byte of the instruction. */
15379 obufp
= mnemonicendp
;
15380 mnemonic
= Suffix3DNow
[*codep
++ & 0xff];
15382 oappend (mnemonic
);
15385 /* Since a variable sized modrm/sib chunk is between the start
15386 of the opcode (0x0f0f) and the opcode suffix, we need to do
15387 all the modrm processing first, and don't know until now that
15388 we have a bad opcode. This necessitates some cleaning up. */
15389 op_out
[0][0] = '\0';
15390 op_out
[1][0] = '\0';
15393 mnemonicendp
= obufp
;
15396 static struct op simd_cmp_op
[] =
15398 { STRING_COMMA_LEN ("eq") },
15399 { STRING_COMMA_LEN ("lt") },
15400 { STRING_COMMA_LEN ("le") },
15401 { STRING_COMMA_LEN ("unord") },
15402 { STRING_COMMA_LEN ("neq") },
15403 { STRING_COMMA_LEN ("nlt") },
15404 { STRING_COMMA_LEN ("nle") },
15405 { STRING_COMMA_LEN ("ord") }
15409 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15411 unsigned int cmp_type
;
15413 FETCH_DATA (the_info
, codep
+ 1);
15414 cmp_type
= *codep
++ & 0xff;
15415 if (cmp_type
< ARRAY_SIZE (simd_cmp_op
))
15418 char *p
= mnemonicendp
- 2;
15422 sprintf (p
, "%s%s", simd_cmp_op
[cmp_type
].name
, suffix
);
15423 mnemonicendp
+= simd_cmp_op
[cmp_type
].len
;
15427 /* We have a reserved extension byte. Output it directly. */
15428 scratchbuf
[0] = '$';
15429 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
15430 oappend_maybe_intel (scratchbuf
);
15431 scratchbuf
[0] = '\0';
15436 OP_Mwait (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
15438 /* mwait %eax,%ecx / mwaitx %eax,%ecx,%ebx */
15441 strcpy (op_out
[0], names32
[0]);
15442 strcpy (op_out
[1], names32
[1]);
15443 if (bytemode
== eBX_reg
)
15444 strcpy (op_out
[2], names32
[3]);
15445 two_source_ops
= 1;
15447 /* Skip mod/rm byte. */
15453 OP_Monitor (int bytemode ATTRIBUTE_UNUSED
,
15454 int sizeflag ATTRIBUTE_UNUSED
)
15456 /* monitor %{e,r,}ax,%ecx,%edx" */
15459 const char **names
= (address_mode
== mode_64bit
15460 ? names64
: names32
);
15462 if (prefixes
& PREFIX_ADDR
)
15464 /* Remove "addr16/addr32". */
15465 all_prefixes
[last_addr_prefix
] = 0;
15466 names
= (address_mode
!= mode_32bit
15467 ? names32
: names16
);
15468 used_prefixes
|= PREFIX_ADDR
;
15470 else if (address_mode
== mode_16bit
)
15472 strcpy (op_out
[0], names
[0]);
15473 strcpy (op_out
[1], names32
[1]);
15474 strcpy (op_out
[2], names32
[2]);
15475 two_source_ops
= 1;
15477 /* Skip mod/rm byte. */
15485 /* Throw away prefixes and 1st. opcode byte. */
15486 codep
= insn_codep
+ 1;
15491 REP_Fixup (int bytemode
, int sizeflag
)
15493 /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
15495 if (prefixes
& PREFIX_REPZ
)
15496 all_prefixes
[last_repz_prefix
] = REP_PREFIX
;
15503 OP_IMREG (bytemode
, sizeflag
);
15506 OP_ESreg (bytemode
, sizeflag
);
15509 OP_DSreg (bytemode
, sizeflag
);
15518 SEP_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15520 if ( isa64
!= amd64
)
15525 mnemonicendp
= obufp
;
15529 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
15533 BND_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15535 if (prefixes
& PREFIX_REPNZ
)
15536 all_prefixes
[last_repnz_prefix
] = BND_PREFIX
;
15539 /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
15543 NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED
,
15544 int sizeflag ATTRIBUTE_UNUSED
)
15546 if (active_seg_prefix
== PREFIX_DS
15547 && (address_mode
!= mode_64bit
|| last_data_prefix
< 0))
15549 /* NOTRACK prefix is only valid on indirect branch instructions.
15550 NB: DATA prefix is unsupported for Intel64. */
15551 active_seg_prefix
= 0;
15552 all_prefixes
[last_seg_prefix
] = NOTRACK_PREFIX
;
15556 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
15557 "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
15561 HLE_Fixup1 (int bytemode
, int sizeflag
)
15564 && (prefixes
& PREFIX_LOCK
) != 0)
15566 if (prefixes
& PREFIX_REPZ
)
15567 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
15568 if (prefixes
& PREFIX_REPNZ
)
15569 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
15572 OP_E (bytemode
, sizeflag
);
15575 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
15576 "xacquire"/"xrelease" for memory operand. No check for LOCK prefix.
15580 HLE_Fixup2 (int bytemode
, int sizeflag
)
15582 if (modrm
.mod
!= 3)
15584 if (prefixes
& PREFIX_REPZ
)
15585 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
15586 if (prefixes
& PREFIX_REPNZ
)
15587 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
15590 OP_E (bytemode
, sizeflag
);
15593 /* Similar to OP_E. But the 0xf3 prefixes should be displayed as
15594 "xrelease" for memory operand. No check for LOCK prefix. */
15597 HLE_Fixup3 (int bytemode
, int sizeflag
)
15600 && last_repz_prefix
> last_repnz_prefix
15601 && (prefixes
& PREFIX_REPZ
) != 0)
15602 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
15604 OP_E (bytemode
, sizeflag
);
15608 CMPXCHG8B_Fixup (int bytemode
, int sizeflag
)
15613 /* Change cmpxchg8b to cmpxchg16b. */
15614 char *p
= mnemonicendp
- 2;
15615 mnemonicendp
= stpcpy (p
, "16b");
15618 else if ((prefixes
& PREFIX_LOCK
) != 0)
15620 if (prefixes
& PREFIX_REPZ
)
15621 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
15622 if (prefixes
& PREFIX_REPNZ
)
15623 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
15626 OP_M (bytemode
, sizeflag
);
15630 XMM_Fixup (int reg
, int sizeflag ATTRIBUTE_UNUSED
)
15632 const char **names
;
15636 switch (vex
.length
)
15650 oappend (names
[reg
]);
15654 CRC32_Fixup (int bytemode
, int sizeflag
)
15656 /* Add proper suffix to "crc32". */
15657 char *p
= mnemonicendp
;
15676 if (sizeflag
& DFLAG
)
15680 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15684 oappend (INTERNAL_DISASSEMBLER_ERROR
);
15691 if (modrm
.mod
== 3)
15695 /* Skip mod/rm byte. */
15700 add
= (rex
& REX_B
) ? 8 : 0;
15701 if (bytemode
== b_mode
)
15705 oappend (names8rex
[modrm
.rm
+ add
]);
15707 oappend (names8
[modrm
.rm
+ add
]);
15713 oappend (names64
[modrm
.rm
+ add
]);
15714 else if ((prefixes
& PREFIX_DATA
))
15715 oappend (names16
[modrm
.rm
+ add
]);
15717 oappend (names32
[modrm
.rm
+ add
]);
15721 OP_E (bytemode
, sizeflag
);
15725 FXSAVE_Fixup (int bytemode
, int sizeflag
)
15727 /* Add proper suffix to "fxsave" and "fxrstor". */
15731 char *p
= mnemonicendp
;
15737 OP_M (bytemode
, sizeflag
);
15741 PCMPESTR_Fixup (int bytemode
, int sizeflag
)
15743 /* Add proper suffix to "{,v}pcmpestr{i,m}". */
15746 char *p
= mnemonicendp
;
15751 else if (sizeflag
& SUFFIX_ALWAYS
)
15758 OP_EX (bytemode
, sizeflag
);
15761 /* Display the destination register operand for instructions with
15765 OP_VEX (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
15768 const char **names
;
15776 reg
= vex
.register_specifier
;
15777 vex
.register_specifier
= 0;
15778 if (address_mode
!= mode_64bit
)
15780 else if (vex
.evex
&& !vex
.v
)
15783 if (bytemode
== vex_scalar_mode
)
15785 oappend (names_xmm
[reg
]);
15789 switch (vex
.length
)
15796 case vex_vsib_q_w_dq_mode
:
15797 case vex_vsib_q_w_d_mode
:
15813 names
= names_mask
;
15827 case vex_vsib_q_w_dq_mode
:
15828 case vex_vsib_q_w_d_mode
:
15829 names
= vex
.w
? names_ymm
: names_xmm
;
15838 names
= names_mask
;
15841 /* See PR binutils/20893 for a reproducer. */
15853 oappend (names
[reg
]);
15856 /* Get the VEX immediate byte without moving codep. */
15858 static unsigned char
15859 get_vex_imm8 (int sizeflag
, int opnum
)
15861 int bytes_before_imm
= 0;
15863 if (modrm
.mod
!= 3)
15865 /* There are SIB/displacement bytes. */
15866 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
15868 /* 32/64 bit address mode */
15869 int base
= modrm
.rm
;
15871 /* Check SIB byte. */
15874 FETCH_DATA (the_info
, codep
+ 1);
15876 /* When decoding the third source, don't increase
15877 bytes_before_imm as this has already been incremented
15878 by one in OP_E_memory while decoding the second
15881 bytes_before_imm
++;
15884 /* Don't increase bytes_before_imm when decoding the third source,
15885 it has already been incremented by OP_E_memory while decoding
15886 the second source operand. */
15892 /* When modrm.rm == 5 or modrm.rm == 4 and base in
15893 SIB == 5, there is a 4 byte displacement. */
15895 /* No displacement. */
15897 /* Fall through. */
15899 /* 4 byte displacement. */
15900 bytes_before_imm
+= 4;
15903 /* 1 byte displacement. */
15904 bytes_before_imm
++;
15911 /* 16 bit address mode */
15912 /* Don't increase bytes_before_imm when decoding the third source,
15913 it has already been incremented by OP_E_memory while decoding
15914 the second source operand. */
15920 /* When modrm.rm == 6, there is a 2 byte displacement. */
15922 /* No displacement. */
15924 /* Fall through. */
15926 /* 2 byte displacement. */
15927 bytes_before_imm
+= 2;
15930 /* 1 byte displacement: when decoding the third source,
15931 don't increase bytes_before_imm as this has already
15932 been incremented by one in OP_E_memory while decoding
15933 the second source operand. */
15935 bytes_before_imm
++;
15943 FETCH_DATA (the_info
, codep
+ bytes_before_imm
+ 1);
15944 return codep
[bytes_before_imm
];
15948 OP_EX_VexReg (int bytemode
, int sizeflag
, int reg
)
15950 const char **names
;
15952 if (reg
== -1 && modrm
.mod
!= 3)
15954 OP_E_memory (bytemode
, sizeflag
);
15966 if (address_mode
!= mode_64bit
)
15970 switch (vex
.length
)
15981 oappend (names
[reg
]);
15985 OP_EX_VexImmW (int bytemode
, int sizeflag
)
15988 static unsigned char vex_imm8
;
15990 if (vex_w_done
== 0)
15994 /* Skip mod/rm byte. */
15998 vex_imm8
= get_vex_imm8 (sizeflag
, 0);
16001 reg
= vex_imm8
>> 4;
16003 OP_EX_VexReg (bytemode
, sizeflag
, reg
);
16005 else if (vex_w_done
== 1)
16010 reg
= vex_imm8
>> 4;
16012 OP_EX_VexReg (bytemode
, sizeflag
, reg
);
16016 /* Output the imm8 directly. */
16017 scratchbuf
[0] = '$';
16018 print_operand_value (scratchbuf
+ 1, 1, vex_imm8
& 0xf);
16019 oappend_maybe_intel (scratchbuf
);
16020 scratchbuf
[0] = '\0';
16026 OP_Vex_2src (int bytemode
, int sizeflag
)
16028 if (modrm
.mod
== 3)
16030 int reg
= modrm
.rm
;
16034 oappend (names_xmm
[reg
]);
16039 && (bytemode
== v_mode
|| bytemode
== v_swap_mode
))
16041 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
16042 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16044 OP_E (bytemode
, sizeflag
);
16049 OP_Vex_2src_1 (int bytemode
, int sizeflag
)
16051 if (modrm
.mod
== 3)
16053 /* Skip mod/rm byte. */
16060 unsigned int reg
= vex
.register_specifier
;
16061 vex
.register_specifier
= 0;
16063 if (address_mode
!= mode_64bit
)
16065 oappend (names_xmm
[reg
]);
16068 OP_Vex_2src (bytemode
, sizeflag
);
16072 OP_Vex_2src_2 (int bytemode
, int sizeflag
)
16075 OP_Vex_2src (bytemode
, sizeflag
);
16078 unsigned int reg
= vex
.register_specifier
;
16079 vex
.register_specifier
= 0;
16081 if (address_mode
!= mode_64bit
)
16083 oappend (names_xmm
[reg
]);
16088 OP_EX_VexW (int bytemode
, int sizeflag
)
16094 /* Skip mod/rm byte. */
16099 reg
= get_vex_imm8 (sizeflag
, 0) >> 4;
16104 reg
= get_vex_imm8 (sizeflag
, 1) >> 4;
16107 OP_EX_VexReg (bytemode
, sizeflag
, reg
);
16115 OP_REG_VexI4 (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
16118 const char **names
;
16120 FETCH_DATA (the_info
, codep
+ 1);
16123 if (bytemode
!= x_mode
)
16127 if (address_mode
!= mode_64bit
)
16130 switch (vex
.length
)
16141 oappend (names
[reg
]);
16145 OP_XMM_VexW (int bytemode
, int sizeflag
)
16147 /* Turn off the REX.W bit since it is used for swapping operands
16150 OP_XMM (bytemode
, sizeflag
);
16154 OP_EX_Vex (int bytemode
, int sizeflag
)
16156 if (modrm
.mod
!= 3)
16158 OP_EX (bytemode
, sizeflag
);
16162 OP_XMM_Vex (int bytemode
, int sizeflag
)
16164 if (modrm
.mod
!= 3)
16166 OP_XMM (bytemode
, sizeflag
);
16169 static struct op vex_cmp_op
[] =
16171 { STRING_COMMA_LEN ("eq") },
16172 { STRING_COMMA_LEN ("lt") },
16173 { STRING_COMMA_LEN ("le") },
16174 { STRING_COMMA_LEN ("unord") },
16175 { STRING_COMMA_LEN ("neq") },
16176 { STRING_COMMA_LEN ("nlt") },
16177 { STRING_COMMA_LEN ("nle") },
16178 { STRING_COMMA_LEN ("ord") },
16179 { STRING_COMMA_LEN ("eq_uq") },
16180 { STRING_COMMA_LEN ("nge") },
16181 { STRING_COMMA_LEN ("ngt") },
16182 { STRING_COMMA_LEN ("false") },
16183 { STRING_COMMA_LEN ("neq_oq") },
16184 { STRING_COMMA_LEN ("ge") },
16185 { STRING_COMMA_LEN ("gt") },
16186 { STRING_COMMA_LEN ("true") },
16187 { STRING_COMMA_LEN ("eq_os") },
16188 { STRING_COMMA_LEN ("lt_oq") },
16189 { STRING_COMMA_LEN ("le_oq") },
16190 { STRING_COMMA_LEN ("unord_s") },
16191 { STRING_COMMA_LEN ("neq_us") },
16192 { STRING_COMMA_LEN ("nlt_uq") },
16193 { STRING_COMMA_LEN ("nle_uq") },
16194 { STRING_COMMA_LEN ("ord_s") },
16195 { STRING_COMMA_LEN ("eq_us") },
16196 { STRING_COMMA_LEN ("nge_uq") },
16197 { STRING_COMMA_LEN ("ngt_uq") },
16198 { STRING_COMMA_LEN ("false_os") },
16199 { STRING_COMMA_LEN ("neq_os") },
16200 { STRING_COMMA_LEN ("ge_oq") },
16201 { STRING_COMMA_LEN ("gt_oq") },
16202 { STRING_COMMA_LEN ("true_us") },
16206 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16208 unsigned int cmp_type
;
16210 FETCH_DATA (the_info
, codep
+ 1);
16211 cmp_type
= *codep
++ & 0xff;
16212 if (cmp_type
< ARRAY_SIZE (vex_cmp_op
))
16215 char *p
= mnemonicendp
- 2;
16219 sprintf (p
, "%s%s", vex_cmp_op
[cmp_type
].name
, suffix
);
16220 mnemonicendp
+= vex_cmp_op
[cmp_type
].len
;
16224 /* We have a reserved extension byte. Output it directly. */
16225 scratchbuf
[0] = '$';
16226 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
16227 oappend_maybe_intel (scratchbuf
);
16228 scratchbuf
[0] = '\0';
16233 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED
,
16234 int sizeflag ATTRIBUTE_UNUSED
)
16236 unsigned int cmp_type
;
16241 FETCH_DATA (the_info
, codep
+ 1);
16242 cmp_type
= *codep
++ & 0xff;
16243 /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
16244 If it's the case, print suffix, otherwise - print the immediate. */
16245 if (cmp_type
< ARRAY_SIZE (simd_cmp_op
)
16250 char *p
= mnemonicendp
- 2;
16252 /* vpcmp* can have both one- and two-lettered suffix. */
16266 sprintf (p
, "%s%s", simd_cmp_op
[cmp_type
].name
, suffix
);
16267 mnemonicendp
+= simd_cmp_op
[cmp_type
].len
;
16271 /* We have a reserved extension byte. Output it directly. */
16272 scratchbuf
[0] = '$';
16273 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
16274 oappend_maybe_intel (scratchbuf
);
16275 scratchbuf
[0] = '\0';
16279 static const struct op xop_cmp_op
[] =
16281 { STRING_COMMA_LEN ("lt") },
16282 { STRING_COMMA_LEN ("le") },
16283 { STRING_COMMA_LEN ("gt") },
16284 { STRING_COMMA_LEN ("ge") },
16285 { STRING_COMMA_LEN ("eq") },
16286 { STRING_COMMA_LEN ("neq") },
16287 { STRING_COMMA_LEN ("false") },
16288 { STRING_COMMA_LEN ("true") }
16292 VPCOM_Fixup (int bytemode ATTRIBUTE_UNUSED
,
16293 int sizeflag ATTRIBUTE_UNUSED
)
16295 unsigned int cmp_type
;
16297 FETCH_DATA (the_info
, codep
+ 1);
16298 cmp_type
= *codep
++ & 0xff;
16299 if (cmp_type
< ARRAY_SIZE (xop_cmp_op
))
16302 char *p
= mnemonicendp
- 2;
16304 /* vpcom* can have both one- and two-lettered suffix. */
16318 sprintf (p
, "%s%s", xop_cmp_op
[cmp_type
].name
, suffix
);
16319 mnemonicendp
+= xop_cmp_op
[cmp_type
].len
;
16323 /* We have a reserved extension byte. Output it directly. */
16324 scratchbuf
[0] = '$';
16325 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
16326 oappend_maybe_intel (scratchbuf
);
16327 scratchbuf
[0] = '\0';
16331 static const struct op pclmul_op
[] =
16333 { STRING_COMMA_LEN ("lql") },
16334 { STRING_COMMA_LEN ("hql") },
16335 { STRING_COMMA_LEN ("lqh") },
16336 { STRING_COMMA_LEN ("hqh") }
16340 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED
,
16341 int sizeflag ATTRIBUTE_UNUSED
)
16343 unsigned int pclmul_type
;
16345 FETCH_DATA (the_info
, codep
+ 1);
16346 pclmul_type
= *codep
++ & 0xff;
16347 switch (pclmul_type
)
16358 if (pclmul_type
< ARRAY_SIZE (pclmul_op
))
16361 char *p
= mnemonicendp
- 3;
16366 sprintf (p
, "%s%s", pclmul_op
[pclmul_type
].name
, suffix
);
16367 mnemonicendp
+= pclmul_op
[pclmul_type
].len
;
16371 /* We have a reserved extension byte. Output it directly. */
16372 scratchbuf
[0] = '$';
16373 print_operand_value (scratchbuf
+ 1, 1, pclmul_type
);
16374 oappend_maybe_intel (scratchbuf
);
16375 scratchbuf
[0] = '\0';
16380 MOVBE_Fixup (int bytemode
, int sizeflag
)
16382 /* Add proper suffix to "movbe". */
16383 char *p
= mnemonicendp
;
16392 if (sizeflag
& SUFFIX_ALWAYS
)
16398 if (sizeflag
& DFLAG
)
16402 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16407 oappend (INTERNAL_DISASSEMBLER_ERROR
);
16414 OP_M (bytemode
, sizeflag
);
16418 MOVSXD_Fixup (int bytemode
, int sizeflag
)
16420 /* Add proper suffix to "movsxd". */
16421 char *p
= mnemonicendp
;
16446 oappend (INTERNAL_DISASSEMBLER_ERROR
);
16453 OP_E (bytemode
, sizeflag
);
16457 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16460 const char **names
;
16462 /* Skip mod/rm byte. */
16476 oappend (names
[reg
]);
16480 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16482 const char **names
;
16483 unsigned int reg
= vex
.register_specifier
;
16484 vex
.register_specifier
= 0;
16491 if (address_mode
!= mode_64bit
)
16493 oappend (names
[reg
]);
16497 OP_Mask (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
16500 || (bytemode
!= mask_mode
&& bytemode
!= mask_bd_mode
))
16504 if ((rex
& REX_R
) != 0 || !vex
.r
)
16510 oappend (names_mask
[modrm
.reg
]);
16514 OP_Rounding (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
16516 if (modrm
.mod
== 3 && vex
.b
)
16519 case evex_rounding_64_mode
:
16520 if (address_mode
!= mode_64bit
)
16525 /* Fall through. */
16526 case evex_rounding_mode
:
16527 oappend (names_rounding
[vex
.ll
]);
16529 case evex_sae_mode
: