opcodes/i386-dis.c

   1 /* Print i386 instructions for GDB, the GNU debugger.
   2    Copyright (C) 1988-2020 Free Software Foundation, Inc.
   3
   4    This file is part of the GNU opcodes library.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    It is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program; if not, write to the Free Software
  18    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  19    MA 02110-1301, USA.  */
  20
  21
  22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
  23    July 1988
  24     modified by John Hassey (hassey@dg-rtp.dg.com)
  25     x86-64 support added by Jan Hubicka (jh@suse.cz)
  26     VIA PadLock support by Michal Ludvig (mludvig@suse.cz).  */
  27
  28 /* The main tables describing the instructions is essentially a copy
  29    of the "Opcode Map" chapter (Appendix A) of the Intel 80386
  30    Programmers Manual.  Usually, there is a capital letter, followed
  31    by a small letter.  The capital letter tell the addressing mode,
  32    and the small letter tells about the operand size.  Refer to
  33    the Intel manual for details.  */
  34
  35 #include "sysdep.h"
  36 #include "disassemble.h"
  37 #include "opintl.h"
  38 #include "opcode/i386.h"
  39 #include "libiberty.h"
  40 #include "safe-ctype.h"
  41
  42 #include <setjmp.h>
  43
  44 static int print_insn (bfd_vma, disassemble_info *);
  45 static void dofloat (int);
  46 static void OP_ST (int, int);
  47 static void OP_STi (int, int);
  48 static int putop (const char *, int);
  49 static void oappend (const char *);
  50 static void append_seg (void);
  51 static void OP_indirE (int, int);
  52 static void print_operand_value (char *, int, bfd_vma);
  53 static void OP_E_register (int, int);
  54 static void OP_E_memory (int, int);
  55 static void print_displacement (char *, bfd_vma);
  56 static void OP_E (int, int);
  57 static void OP_G (int, int);
  58 static bfd_vma get64 (void);
  59 static bfd_signed_vma get32 (void);
  60 static bfd_signed_vma get32s (void);
  61 static int get16 (void);
  62 static void set_op (bfd_vma, int);
  63 static void OP_Skip_MODRM (int, int);
  64 static void OP_REG (int, int);
  65 static void OP_IMREG (int, int);
  66 static void OP_I (int, int);
  67 static void OP_I64 (int, int);
  68 static void OP_sI (int, int);
  69 static void OP_J (int, int);
  70 static void OP_SEG (int, int);
  71 static void OP_DIR (int, int);
  72 static void OP_OFF (int, int);
  73 static void OP_OFF64 (int, int);
  74 static void ptr_reg (int, int);
  75 static void OP_ESreg (int, int);
  76 static void OP_DSreg (int, int);
  77 static void OP_C (int, int);
  78 static void OP_D (int, int);
  79 static void OP_T (int, int);
  80 static void OP_R (int, int);
  81 static void OP_MMX (int, int);
  82 static void OP_XMM (int, int);
  83 static void OP_EM (int, int);
  84 static void OP_EX (int, int);
  85 static void OP_EMC (int,int);
  86 static void OP_MXC (int,int);
  87 static void OP_MS (int, int);
  88 static void OP_XS (int, int);
  89 static void OP_M (int, int);
  90 static void OP_VEX (int, int);
  91 static void OP_VexW (int, int);
  92 static void OP_EX_Vex (int, int);
  93 static void OP_XMM_Vex (int, int);
  94 static void OP_Rounding (int, int);
  95 static void OP_REG_VexI4 (int, int);
  96 static void OP_VexI4 (int, int);
  97 static void PCLMUL_Fixup (int, int);
  98 static void VCMP_Fixup (int, int);
  99 static void VPCMP_Fixup (int, int);
 100 static void VPCOM_Fixup (int, int);
 101 static void OP_0f07 (int, int);
 102 static void OP_Monitor (int, int);
 103 static void OP_Mwait (int, int);
 104 static void NOP_Fixup1 (int, int);
 105 static void NOP_Fixup2 (int, int);
 106 static void OP_3DNowSuffix (int, int);
 107 static void CMP_Fixup (int, int);
 108 static void BadOp (void);
 109 static void REP_Fixup (int, int);
 110 static void SEP_Fixup (int, int);
 111 static void BND_Fixup (int, int);
 112 static void NOTRACK_Fixup (int, int);
 113 static void HLE_Fixup1 (int, int);
 114 static void HLE_Fixup2 (int, int);
 115 static void HLE_Fixup3 (int, int);
 116 static void CMPXCHG8B_Fixup (int, int);
 117 static void XMM_Fixup (int, int);
 118 static void CRC32_Fixup (int, int);
 119 static void FXSAVE_Fixup (int, int);
 120 static void PCMPESTR_Fixup (int, int);
 121
 122 static void MOVBE_Fixup (int, int);
 123 static void MOVSXD_Fixup (int, int);
 124
 125 static void OP_Mask (int, int);
 126
 127 struct dis_private {
 128   /* Points to first byte not fetched.  */
 129   bfd_byte *max_fetched;
 130   bfd_byte the_buffer[MAX_MNEM_SIZE];
 131   bfd_vma insn_start;
 132   int orig_sizeflag;
 133   OPCODES_SIGJMP_BUF bailout;
 134 };
 135
 136 enum address_mode
 137 {
 138   mode_16bit,
 139   mode_32bit,
 140   mode_64bit
 141 };
 142
 143 enum address_mode address_mode;
 144
 145 /* Flags for the prefixes for the current instruction.  See below.  */
 146 static int prefixes;
 147
 148 /* REX prefix the current instruction.  See below.  */
 149 static int rex;
 150 /* Bits of REX we've already used.  */
 151 static int rex_used;
 152 /* Mark parts used in the REX prefix.  When we are testing for
 153    empty prefix (for 8bit register REX extension), just mask it
 154    out.  Otherwise test for REX bit is excuse for existence of REX
 155    only in case value is nonzero.  */
 156 #define USED_REX(value)                                 \
 157   {                                                     \
 158     if (value)                                          \
 159       {                                                 \
 160         if ((rex & value))                              \
 161           rex_used |= (value) | REX_OPCODE;             \
 162       }                                                 \
 163     else                                                \
 164       rex_used |= REX_OPCODE;                           \
 165   }
 166
 167 /* Flags for prefixes which we somehow handled when printing the
 168    current instruction.  */
 169 static int used_prefixes;
 170
 171 /* Flags stored in PREFIXES.  */
 172 #define PREFIX_REPZ 1
 173 #define PREFIX_REPNZ 2
 174 #define PREFIX_LOCK 4
 175 #define PREFIX_CS 8
 176 #define PREFIX_SS 0x10
 177 #define PREFIX_DS 0x20
 178 #define PREFIX_ES 0x40
 179 #define PREFIX_FS 0x80
 180 #define PREFIX_GS 0x100
 181 #define PREFIX_DATA 0x200
 182 #define PREFIX_ADDR 0x400
 183 #define PREFIX_FWAIT 0x800
 184
 185 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
 186    to ADDR (exclusive) are valid.  Returns 1 for success, longjmps
 187    on error.  */
 188 #define FETCH_DATA(info, addr) \
 189   ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
 190    ? 1 : fetch_data ((info), (addr)))
 191
 192 static int
 193 fetch_data (struct disassemble_info *info, bfd_byte *addr)
 194 {
 195   int status;
 196   struct dis_private *priv = (struct dis_private *) info->private_data;
 197   bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
 198
 199   if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
 200     status = (*info->read_memory_func) (start,
 201                                         priv->max_fetched,
 202                                         addr - priv->max_fetched,
 203                                         info);
 204   else
 205     status = -1;
 206   if (status != 0)
 207     {
 208       /* If we did manage to read at least one byte, then
 209          print_insn_i386 will do something sensible.  Otherwise, print
 210          an error.  We do that here because this is where we know
 211          STATUS.  */
 212       if (priv->max_fetched == priv->the_buffer)
 213         (*info->memory_error_func) (status, start, info);
 214       OPCODES_SIGLONGJMP (priv->bailout, 1);
 215     }
 216   else
 217     priv->max_fetched = addr;
 218   return 1;
 219 }
 220
 221 /* Possible values for prefix requirement.  */
 222 #define PREFIX_IGNORED_SHIFT    16
 223 #define PREFIX_IGNORED_REPZ     (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
 224 #define PREFIX_IGNORED_REPNZ    (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
 225 #define PREFIX_IGNORED_DATA     (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
 226 #define PREFIX_IGNORED_ADDR     (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
 227 #define PREFIX_IGNORED_LOCK     (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
 228
 229 /* Opcode prefixes.  */
 230 #define PREFIX_OPCODE           (PREFIX_REPZ \
 231                                  | PREFIX_REPNZ \
 232                                  | PREFIX_DATA)
 233
 234 /* Prefixes ignored.  */
 235 #define PREFIX_IGNORED          (PREFIX_IGNORED_REPZ \
 236                                  | PREFIX_IGNORED_REPNZ \
 237                                  | PREFIX_IGNORED_DATA)
 238
 239 #define XX { NULL, 0 }
 240 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
 241
 242 #define Eb { OP_E, b_mode }
 243 #define Ebnd { OP_E, bnd_mode }
 244 #define EbS { OP_E, b_swap_mode }
 245 #define EbndS { OP_E, bnd_swap_mode }
 246 #define Ev { OP_E, v_mode }
 247 #define Eva { OP_E, va_mode }
 248 #define Ev_bnd { OP_E, v_bnd_mode }
 249 #define EvS { OP_E, v_swap_mode }
 250 #define Ed { OP_E, d_mode }
 251 #define Edq { OP_E, dq_mode }
 252 #define Edqw { OP_E, dqw_mode }
 253 #define Edqb { OP_E, dqb_mode }
 254 #define Edb { OP_E, db_mode }
 255 #define Edw { OP_E, dw_mode }
 256 #define Edqd { OP_E, dqd_mode }
 257 #define Eq { OP_E, q_mode }
 258 #define indirEv { OP_indirE, indir_v_mode }
 259 #define indirEp { OP_indirE, f_mode }
 260 #define stackEv { OP_E, stack_v_mode }
 261 #define Em { OP_E, m_mode }
 262 #define Ew { OP_E, w_mode }
 263 #define M { OP_M, 0 }           /* lea, lgdt, etc. */
 264 #define Ma { OP_M, a_mode }
 265 #define Mb { OP_M, b_mode }
 266 #define Md { OP_M, d_mode }
 267 #define Mo { OP_M, o_mode }
 268 #define Mp { OP_M, f_mode }             /* 32 or 48 bit memory operand for LDS, LES etc */
 269 #define Mq { OP_M, q_mode }
 270 #define Mv_bnd { OP_M, v_bndmk_mode }
 271 #define Mx { OP_M, x_mode }
 272 #define Mxmm { OP_M, xmm_mode }
 273 #define Gb { OP_G, b_mode }
 274 #define Gbnd { OP_G, bnd_mode }
 275 #define Gv { OP_G, v_mode }
 276 #define Gd { OP_G, d_mode }
 277 #define Gdq { OP_G, dq_mode }
 278 #define Gm { OP_G, m_mode }
 279 #define Gva { OP_G, va_mode }
 280 #define Gw { OP_G, w_mode }
 281 #define Rd { OP_R, d_mode }
 282 #define Rdq { OP_R, dq_mode }
 283 #define Rm { OP_R, m_mode }
 284 #define Ib { OP_I, b_mode }
 285 #define sIb { OP_sI, b_mode }   /* sign extened byte */
 286 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
 287 #define Iv { OP_I, v_mode }
 288 #define sIv { OP_sI, v_mode }
 289 #define Iv64 { OP_I64, v_mode }
 290 #define Id { OP_I, d_mode }
 291 #define Iw { OP_I, w_mode }
 292 #define I1 { OP_I, const_1_mode }
 293 #define Jb { OP_J, b_mode }
 294 #define Jv { OP_J, v_mode }
 295 #define Jdqw { OP_J, dqw_mode }
 296 #define Cm { OP_C, m_mode }
 297 #define Dm { OP_D, m_mode }
 298 #define Td { OP_T, d_mode }
 299 #define Skip_MODRM { OP_Skip_MODRM, 0 }
 300
 301 #define RMeAX { OP_REG, eAX_reg }
 302 #define RMeBX { OP_REG, eBX_reg }
 303 #define RMeCX { OP_REG, eCX_reg }
 304 #define RMeDX { OP_REG, eDX_reg }
 305 #define RMeSP { OP_REG, eSP_reg }
 306 #define RMeBP { OP_REG, eBP_reg }
 307 #define RMeSI { OP_REG, eSI_reg }
 308 #define RMeDI { OP_REG, eDI_reg }
 309 #define RMrAX { OP_REG, rAX_reg }
 310 #define RMrBX { OP_REG, rBX_reg }
 311 #define RMrCX { OP_REG, rCX_reg }
 312 #define RMrDX { OP_REG, rDX_reg }
 313 #define RMrSP { OP_REG, rSP_reg }
 314 #define RMrBP { OP_REG, rBP_reg }
 315 #define RMrSI { OP_REG, rSI_reg }
 316 #define RMrDI { OP_REG, rDI_reg }
 317 #define RMAL { OP_REG, al_reg }
 318 #define RMCL { OP_REG, cl_reg }
 319 #define RMDL { OP_REG, dl_reg }
 320 #define RMBL { OP_REG, bl_reg }
 321 #define RMAH { OP_REG, ah_reg }
 322 #define RMCH { OP_REG, ch_reg }
 323 #define RMDH { OP_REG, dh_reg }
 324 #define RMBH { OP_REG, bh_reg }
 325 #define RMAX { OP_REG, ax_reg }
 326 #define RMDX { OP_REG, dx_reg }
 327
 328 #define eAX { OP_IMREG, eAX_reg }
 329 #define eBX { OP_IMREG, eBX_reg }
 330 #define eCX { OP_IMREG, eCX_reg }
 331 #define eDX { OP_IMREG, eDX_reg }
 332 #define eSP { OP_IMREG, eSP_reg }
 333 #define eBP { OP_IMREG, eBP_reg }
 334 #define eSI { OP_IMREG, eSI_reg }
 335 #define eDI { OP_IMREG, eDI_reg }
 336 #define AL { OP_IMREG, al_reg }
 337 #define CL { OP_IMREG, cl_reg }
 338 #define DL { OP_IMREG, dl_reg }
 339 #define BL { OP_IMREG, bl_reg }
 340 #define AH { OP_IMREG, ah_reg }
 341 #define CH { OP_IMREG, ch_reg }
 342 #define DH { OP_IMREG, dh_reg }
 343 #define BH { OP_IMREG, bh_reg }
 344 #define AX { OP_IMREG, ax_reg }
 345 #define DX { OP_IMREG, dx_reg }
 346 #define zAX { OP_IMREG, z_mode_ax_reg }
 347 #define indirDX { OP_IMREG, indir_dx_reg }
 348
 349 #define Sw { OP_SEG, w_mode }
 350 #define Sv { OP_SEG, v_mode }
 351 #define Ap { OP_DIR, 0 }
 352 #define Ob { OP_OFF64, b_mode }
 353 #define Ov { OP_OFF64, v_mode }
 354 #define Xb { OP_DSreg, eSI_reg }
 355 #define Xv { OP_DSreg, eSI_reg }
 356 #define Xz { OP_DSreg, eSI_reg }
 357 #define Yb { OP_ESreg, eDI_reg }
 358 #define Yv { OP_ESreg, eDI_reg }
 359 #define DSBX { OP_DSreg, eBX_reg }
 360
 361 #define es { OP_REG, es_reg }
 362 #define ss { OP_REG, ss_reg }
 363 #define cs { OP_REG, cs_reg }
 364 #define ds { OP_REG, ds_reg }
 365 #define fs { OP_REG, fs_reg }
 366 #define gs { OP_REG, gs_reg }
 367
 368 #define MX { OP_MMX, 0 }
 369 #define XM { OP_XMM, 0 }
 370 #define XMScalar { OP_XMM, scalar_mode }
 371 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
 372 #define XMM { OP_XMM, xmm_mode }
 373 #define XMxmmq { OP_XMM, xmmq_mode }
 374 #define EM { OP_EM, v_mode }
 375 #define EMS { OP_EM, v_swap_mode }
 376 #define EMd { OP_EM, d_mode }
 377 #define EMx { OP_EM, x_mode }
 378 #define EXbScalar { OP_EX, b_scalar_mode }
 379 #define EXw { OP_EX, w_mode }
 380 #define EXwScalar { OP_EX, w_scalar_mode }
 381 #define EXd { OP_EX, d_mode }
 382 #define EXdS { OP_EX, d_swap_mode }
 383 #define EXq { OP_EX, q_mode }
 384 #define EXqS { OP_EX, q_swap_mode }
 385 #define EXx { OP_EX, x_mode }
 386 #define EXxS { OP_EX, x_swap_mode }
 387 #define EXxmm { OP_EX, xmm_mode }
 388 #define EXymm { OP_EX, ymm_mode }
 389 #define EXxmmq { OP_EX, xmmq_mode }
 390 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
 391 #define EXxmm_mb { OP_EX, xmm_mb_mode }
 392 #define EXxmm_mw { OP_EX, xmm_mw_mode }
 393 #define EXxmm_md { OP_EX, xmm_md_mode }
 394 #define EXxmm_mq { OP_EX, xmm_mq_mode }
 395 #define EXxmmdw { OP_EX, xmmdw_mode }
 396 #define EXxmmqd { OP_EX, xmmqd_mode }
 397 #define EXymmq { OP_EX, ymmq_mode }
 398 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
 399 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
 400 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
 401 #define MS { OP_MS, v_mode }
 402 #define XS { OP_XS, v_mode }
 403 #define EMCq { OP_EMC, q_mode }
 404 #define MXC { OP_MXC, 0 }
 405 #define OPSUF { OP_3DNowSuffix, 0 }
 406 #define SEP { SEP_Fixup, 0 }
 407 #define CMP { CMP_Fixup, 0 }
 408 #define XMM0 { XMM_Fixup, 0 }
 409 #define FXSAVE { FXSAVE_Fixup, 0 }
 410
 411 #define Vex { OP_VEX, vex_mode }
 412 #define VexW { OP_VexW, vex_mode }
 413 #define VexScalar { OP_VEX, vex_scalar_mode }
 414 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
 415 #define Vex128 { OP_VEX, vex128_mode }
 416 #define Vex256 { OP_VEX, vex256_mode }
 417 #define VexGdq { OP_VEX, dq_mode }
 418 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
 419 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
 420 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
 421 #define XMVexI4 { OP_REG_VexI4, x_mode }
 422 #define XMVexScalarI4 { OP_REG_VexI4, scalar_mode }
 423 #define VexI4 { OP_VexI4, 0 }
 424 #define PCLMUL { PCLMUL_Fixup, 0 }
 425 #define VCMP { VCMP_Fixup, 0 }
 426 #define VPCMP { VPCMP_Fixup, 0 }
 427 #define VPCOM { VPCOM_Fixup, 0 }
 428
 429 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
 430 #define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode }
 431 #define EXxEVexS { OP_Rounding, evex_sae_mode }
 432
 433 #define XMask { OP_Mask, mask_mode }
 434 #define MaskG { OP_G, mask_mode }
 435 #define MaskE { OP_E, mask_mode }
 436 #define MaskBDE { OP_E, mask_bd_mode }
 437 #define MaskR { OP_R, mask_mode }
 438 #define MaskVex { OP_VEX, mask_mode }
 439
 440 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
 441 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
 442 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
 443 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
 444
 445 /* Used handle "rep" prefix for string instructions.  */
 446 #define Xbr { REP_Fixup, eSI_reg }
 447 #define Xvr { REP_Fixup, eSI_reg }
 448 #define Ybr { REP_Fixup, eDI_reg }
 449 #define Yvr { REP_Fixup, eDI_reg }
 450 #define Yzr { REP_Fixup, eDI_reg }
 451 #define indirDXr { REP_Fixup, indir_dx_reg }
 452 #define ALr { REP_Fixup, al_reg }
 453 #define eAXr { REP_Fixup, eAX_reg }
 454
 455 /* Used handle HLE prefix for lockable instructions.  */
 456 #define Ebh1 { HLE_Fixup1, b_mode }
 457 #define Evh1 { HLE_Fixup1, v_mode }
 458 #define Ebh2 { HLE_Fixup2, b_mode }
 459 #define Evh2 { HLE_Fixup2, v_mode }
 460 #define Ebh3 { HLE_Fixup3, b_mode }
 461 #define Evh3 { HLE_Fixup3, v_mode }
 462
 463 #define BND { BND_Fixup, 0 }
 464 #define NOTRACK { NOTRACK_Fixup, 0 }
 465
 466 #define cond_jump_flag { NULL, cond_jump_mode }
 467 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
 468
 469 /* bits in sizeflag */
 470 #define SUFFIX_ALWAYS 4
 471 #define AFLAG 2
 472 #define DFLAG 1
 473
 474 enum
 475 {
 476   /* byte operand */
 477   b_mode = 1,
 478   /* byte operand with operand swapped */
 479   b_swap_mode,
 480   /* byte operand, sign extend like 'T' suffix */
 481   b_T_mode,
 482   /* operand size depends on prefixes */
 483   v_mode,
 484   /* operand size depends on prefixes with operand swapped */
 485   v_swap_mode,
 486   /* operand size depends on address prefix */
 487   va_mode,
 488   /* word operand */
 489   w_mode,
 490   /* double word operand  */
 491   d_mode,
 492   /* double word operand with operand swapped */
 493   d_swap_mode,
 494   /* quad word operand */
 495   q_mode,
 496   /* quad word operand with operand swapped */
 497   q_swap_mode,
 498   /* ten-byte operand */
 499   t_mode,
 500   /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand.  In EVEX with
 501      broadcast enabled.  */
 502   x_mode,
 503   /* Similar to x_mode, but with different EVEX mem shifts.  */
 504   evex_x_gscat_mode,
 505   /* Similar to x_mode, but with disabled broadcast.  */
 506   evex_x_nobcst_mode,
 507   /* Similar to x_mode, but with operands swapped and disabled broadcast
 508      in EVEX.  */
 509   x_swap_mode,
 510   /* 16-byte XMM operand */
 511   xmm_mode,
 512   /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
 513      memory operand (depending on vector length).  Broadcast isn't
 514      allowed.  */
 515   xmmq_mode,
 516   /* Same as xmmq_mode, but broadcast is allowed.  */
 517   evex_half_bcst_xmmq_mode,
 518   /* XMM register or byte memory operand */
 519   xmm_mb_mode,
 520   /* XMM register or word memory operand */
 521   xmm_mw_mode,
 522   /* XMM register or double word memory operand */
 523   xmm_md_mode,
 524   /* XMM register or quad word memory operand */
 525   xmm_mq_mode,
 526   /* 16-byte XMM, word, double word or quad word operand.  */
 527   xmmdw_mode,
 528   /* 16-byte XMM, double word, quad word operand or xmm word operand.  */
 529   xmmqd_mode,
 530   /* 32-byte YMM operand */
 531   ymm_mode,
 532   /* quad word, ymmword or zmmword memory operand.  */
 533   ymmq_mode,
 534   /* 32-byte YMM or 16-byte word operand */
 535   ymmxmm_mode,
 536   /* d_mode in 32bit, q_mode in 64bit mode.  */
 537   m_mode,
 538   /* pair of v_mode operands */
 539   a_mode,
 540   cond_jump_mode,
 541   loop_jcxz_mode,
 542   movsxd_mode,
 543   v_bnd_mode,
 544   /* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode.  */
 545   v_bndmk_mode,
 546   /* operand size depends on REX prefixes.  */
 547   dq_mode,
 548   /* registers like dq_mode, memory like w_mode, displacements like
 549      v_mode without considering Intel64 ISA.  */
 550   dqw_mode,
 551   /* bounds operand */
 552   bnd_mode,
 553   /* bounds operand with operand swapped */
 554   bnd_swap_mode,
 555   /* 4- or 6-byte pointer operand */
 556   f_mode,
 557   const_1_mode,
 558   /* v_mode for indirect branch opcodes.  */
 559   indir_v_mode,
 560   /* v_mode for stack-related opcodes.  */
 561   stack_v_mode,
 562   /* non-quad operand size depends on prefixes */
 563   z_mode,
 564   /* 16-byte operand */
 565   o_mode,
 566   /* registers like dq_mode, memory like b_mode.  */
 567   dqb_mode,
 568   /* registers like d_mode, memory like b_mode.  */
 569   db_mode,
 570   /* registers like d_mode, memory like w_mode.  */
 571   dw_mode,
 572   /* registers like dq_mode, memory like d_mode.  */
 573   dqd_mode,
 574   /* normal vex mode */
 575   vex_mode,
 576   /* 128bit vex mode */
 577   vex128_mode,
 578   /* 256bit vex mode */
 579   vex256_mode,
 580
 581   /* Operand size depends on the VEX.W bit, with VSIB dword indices.  */
 582   vex_vsib_d_w_dq_mode,
 583   /* Similar to vex_vsib_d_w_dq_mode, with smaller memory.  */
 584   vex_vsib_d_w_d_mode,
 585   /* Operand size depends on the VEX.W bit, with VSIB qword indices.  */
 586   vex_vsib_q_w_dq_mode,
 587   /* Similar to vex_vsib_q_w_dq_mode, with smaller memory.  */
 588   vex_vsib_q_w_d_mode,
 589
 590   /* scalar, ignore vector length.  */
 591   scalar_mode,
 592   /* like b_mode, ignore vector length.  */
 593   b_scalar_mode,
 594   /* like w_mode, ignore vector length.  */
 595   w_scalar_mode,
 596   /* like d_swap_mode, ignore vector length.  */
 597   d_scalar_swap_mode,
 598   /* like q_swap_mode, ignore vector length.  */
 599   q_scalar_swap_mode,
 600   /* like vex_mode, ignore vector length.  */
 601   vex_scalar_mode,
 602   /* Operand size depends on the VEX.W bit, ignore vector length.  */
 603   vex_scalar_w_dq_mode,
 604
 605   /* Static rounding.  */
 606   evex_rounding_mode,
 607   /* Static rounding, 64-bit mode only.  */
 608   evex_rounding_64_mode,
 609   /* Supress all exceptions.  */
 610   evex_sae_mode,
 611
 612   /* Mask register operand.  */
 613   mask_mode,
 614   /* Mask register operand.  */
 615   mask_bd_mode,
 616
 617   es_reg,
 618   cs_reg,
 619   ss_reg,
 620   ds_reg,
 621   fs_reg,
 622   gs_reg,
 623
 624   eAX_reg,
 625   eCX_reg,
 626   eDX_reg,
 627   eBX_reg,
 628   eSP_reg,
 629   eBP_reg,
 630   eSI_reg,
 631   eDI_reg,
 632
 633   al_reg,
 634   cl_reg,
 635   dl_reg,
 636   bl_reg,
 637   ah_reg,
 638   ch_reg,
 639   dh_reg,
 640   bh_reg,
 641
 642   ax_reg,
 643   cx_reg,
 644   dx_reg,
 645   bx_reg,
 646   sp_reg,
 647   bp_reg,
 648   si_reg,
 649   di_reg,
 650
 651   rAX_reg,
 652   rCX_reg,
 653   rDX_reg,
 654   rBX_reg,
 655   rSP_reg,
 656   rBP_reg,
 657   rSI_reg,
 658   rDI_reg,
 659
 660   z_mode_ax_reg,
 661   indir_dx_reg
 662 };
 663
 664 enum
 665 {
 666   FLOATCODE = 1,
 667   USE_REG_TABLE,
 668   USE_MOD_TABLE,
 669   USE_RM_TABLE,
 670   USE_PREFIX_TABLE,
 671   USE_X86_64_TABLE,
 672   USE_3BYTE_TABLE,
 673   USE_XOP_8F_TABLE,
 674   USE_VEX_C4_TABLE,
 675   USE_VEX_C5_TABLE,
 676   USE_VEX_LEN_TABLE,
 677   USE_VEX_W_TABLE,
 678   USE_EVEX_TABLE,
 679   USE_EVEX_LEN_TABLE
 680 };
 681
 682 #define FLOAT                   NULL, { { NULL, FLOATCODE } }, 0
 683
 684 #define DIS386(T, I)            NULL, { { NULL, (T)}, { NULL,  (I) } }, 0
 685 #define DIS386_PREFIX(T, I, P)          NULL, { { NULL, (T)}, { NULL,  (I) } }, P
 686 #define REG_TABLE(I)            DIS386 (USE_REG_TABLE, (I))
 687 #define MOD_TABLE(I)            DIS386 (USE_MOD_TABLE, (I))
 688 #define RM_TABLE(I)             DIS386 (USE_RM_TABLE, (I))
 689 #define PREFIX_TABLE(I)         DIS386 (USE_PREFIX_TABLE, (I))
 690 #define X86_64_TABLE(I)         DIS386 (USE_X86_64_TABLE, (I))
 691 #define THREE_BYTE_TABLE(I)     DIS386 (USE_3BYTE_TABLE, (I))
 692 #define THREE_BYTE_TABLE_PREFIX(I, P)   DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
 693 #define XOP_8F_TABLE(I)         DIS386 (USE_XOP_8F_TABLE, (I))
 694 #define VEX_C4_TABLE(I)         DIS386 (USE_VEX_C4_TABLE, (I))
 695 #define VEX_C5_TABLE(I)         DIS386 (USE_VEX_C5_TABLE, (I))
 696 #define VEX_LEN_TABLE(I)        DIS386 (USE_VEX_LEN_TABLE, (I))
 697 #define VEX_W_TABLE(I)          DIS386 (USE_VEX_W_TABLE, (I))
 698 #define EVEX_TABLE(I)           DIS386 (USE_EVEX_TABLE, (I))
 699 #define EVEX_LEN_TABLE(I)       DIS386 (USE_EVEX_LEN_TABLE, (I))
 700
 701 enum
 702 {
 703   REG_80 = 0,
 704   REG_81,
 705   REG_83,
 706   REG_8F,
 707   REG_C0,
 708   REG_C1,
 709   REG_C6,
 710   REG_C7,
 711   REG_D0,
 712   REG_D1,
 713   REG_D2,
 714   REG_D3,
 715   REG_F6,
 716   REG_F7,
 717   REG_FE,
 718   REG_FF,
 719   REG_0F00,
 720   REG_0F01,
 721   REG_0F0D,
 722   REG_0F18,
 723   REG_0F1C_P_0_MOD_0,
 724   REG_0F1E_P_1_MOD_3,
 725   REG_0F71,
 726   REG_0F72,
 727   REG_0F73,
 728   REG_0FA6,
 729   REG_0FA7,
 730   REG_0FAE,
 731   REG_0FBA,
 732   REG_0FC7,
 733   REG_VEX_0F71,
 734   REG_VEX_0F72,
 735   REG_VEX_0F73,
 736   REG_VEX_0FAE,
 737   REG_VEX_0F38F3,
 738
 739   REG_0FXOP_09_01_L_0,
 740   REG_0FXOP_09_02_L_0,
 741   REG_0FXOP_09_12_M_1_L_0,
 742   REG_0FXOP_0A_12_L_0,
 743
 744   REG_EVEX_0F71,
 745   REG_EVEX_0F72,
 746   REG_EVEX_0F73,
 747   REG_EVEX_0F38C6,
 748   REG_EVEX_0F38C7
 749 };
 750
 751 enum
 752 {
 753   MOD_8D = 0,
 754   MOD_C6_REG_7,
 755   MOD_C7_REG_7,
 756   MOD_FF_REG_3,
 757   MOD_FF_REG_5,
 758   MOD_0F01_REG_0,
 759   MOD_0F01_REG_1,
 760   MOD_0F01_REG_2,
 761   MOD_0F01_REG_3,
 762   MOD_0F01_REG_5,
 763   MOD_0F01_REG_7,
 764   MOD_0F12_PREFIX_0,
 765   MOD_0F12_PREFIX_2,
 766   MOD_0F13,
 767   MOD_0F16_PREFIX_0,
 768   MOD_0F16_PREFIX_2,
 769   MOD_0F17,
 770   MOD_0F18_REG_0,
 771   MOD_0F18_REG_1,
 772   MOD_0F18_REG_2,
 773   MOD_0F18_REG_3,
 774   MOD_0F18_REG_4,
 775   MOD_0F18_REG_5,
 776   MOD_0F18_REG_6,
 777   MOD_0F18_REG_7,
 778   MOD_0F1A_PREFIX_0,
 779   MOD_0F1B_PREFIX_0,
 780   MOD_0F1B_PREFIX_1,
 781   MOD_0F1C_PREFIX_0,
 782   MOD_0F1E_PREFIX_1,
 783   MOD_0F24,
 784   MOD_0F26,
 785   MOD_0F2B_PREFIX_0,
 786   MOD_0F2B_PREFIX_1,
 787   MOD_0F2B_PREFIX_2,
 788   MOD_0F2B_PREFIX_3,
 789   MOD_0F50,
 790   MOD_0F71_REG_2,
 791   MOD_0F71_REG_4,
 792   MOD_0F71_REG_6,
 793   MOD_0F72_REG_2,
 794   MOD_0F72_REG_4,
 795   MOD_0F72_REG_6,
 796   MOD_0F73_REG_2,
 797   MOD_0F73_REG_3,
 798   MOD_0F73_REG_6,
 799   MOD_0F73_REG_7,
 800   MOD_0FAE_REG_0,
 801   MOD_0FAE_REG_1,
 802   MOD_0FAE_REG_2,
 803   MOD_0FAE_REG_3,
 804   MOD_0FAE_REG_4,
 805   MOD_0FAE_REG_5,
 806   MOD_0FAE_REG_6,
 807   MOD_0FAE_REG_7,
 808   MOD_0FB2,
 809   MOD_0FB4,
 810   MOD_0FB5,
 811   MOD_0FC3,
 812   MOD_0FC7_REG_3,
 813   MOD_0FC7_REG_4,
 814   MOD_0FC7_REG_5,
 815   MOD_0FC7_REG_6,
 816   MOD_0FC7_REG_7,
 817   MOD_0FD7,
 818   MOD_0FE7_PREFIX_2,
 819   MOD_0FF0_PREFIX_3,
 820   MOD_0F382A_PREFIX_2,
 821   MOD_0F38F5_PREFIX_2,
 822   MOD_0F38F6_PREFIX_0,
 823   MOD_0F38F8_PREFIX_1,
 824   MOD_0F38F8_PREFIX_2,
 825   MOD_0F38F8_PREFIX_3,
 826   MOD_0F38F9_PREFIX_0,
 827   MOD_62_32BIT,
 828   MOD_C4_32BIT,
 829   MOD_C5_32BIT,
 830   MOD_VEX_0F12_PREFIX_0,
 831   MOD_VEX_0F12_PREFIX_2,
 832   MOD_VEX_0F13,
 833   MOD_VEX_0F16_PREFIX_0,
 834   MOD_VEX_0F16_PREFIX_2,
 835   MOD_VEX_0F17,
 836   MOD_VEX_0F2B,
 837   MOD_VEX_W_0_0F41_P_0_LEN_1,
 838   MOD_VEX_W_1_0F41_P_0_LEN_1,
 839   MOD_VEX_W_0_0F41_P_2_LEN_1,
 840   MOD_VEX_W_1_0F41_P_2_LEN_1,
 841   MOD_VEX_W_0_0F42_P_0_LEN_1,
 842   MOD_VEX_W_1_0F42_P_0_LEN_1,
 843   MOD_VEX_W_0_0F42_P_2_LEN_1,
 844   MOD_VEX_W_1_0F42_P_2_LEN_1,
 845   MOD_VEX_W_0_0F44_P_0_LEN_1,
 846   MOD_VEX_W_1_0F44_P_0_LEN_1,
 847   MOD_VEX_W_0_0F44_P_2_LEN_1,
 848   MOD_VEX_W_1_0F44_P_2_LEN_1,
 849   MOD_VEX_W_0_0F45_P_0_LEN_1,
 850   MOD_VEX_W_1_0F45_P_0_LEN_1,
 851   MOD_VEX_W_0_0F45_P_2_LEN_1,
 852   MOD_VEX_W_1_0F45_P_2_LEN_1,
 853   MOD_VEX_W_0_0F46_P_0_LEN_1,
 854   MOD_VEX_W_1_0F46_P_0_LEN_1,
 855   MOD_VEX_W_0_0F46_P_2_LEN_1,
 856   MOD_VEX_W_1_0F46_P_2_LEN_1,
 857   MOD_VEX_W_0_0F47_P_0_LEN_1,
 858   MOD_VEX_W_1_0F47_P_0_LEN_1,
 859   MOD_VEX_W_0_0F47_P_2_LEN_1,
 860   MOD_VEX_W_1_0F47_P_2_LEN_1,
 861   MOD_VEX_W_0_0F4A_P_0_LEN_1,
 862   MOD_VEX_W_1_0F4A_P_0_LEN_1,
 863   MOD_VEX_W_0_0F4A_P_2_LEN_1,
 864   MOD_VEX_W_1_0F4A_P_2_LEN_1,
 865   MOD_VEX_W_0_0F4B_P_0_LEN_1,
 866   MOD_VEX_W_1_0F4B_P_0_LEN_1,
 867   MOD_VEX_W_0_0F4B_P_2_LEN_1,
 868   MOD_VEX_0F50,
 869   MOD_VEX_0F71_REG_2,
 870   MOD_VEX_0F71_REG_4,
 871   MOD_VEX_0F71_REG_6,
 872   MOD_VEX_0F72_REG_2,
 873   MOD_VEX_0F72_REG_4,
 874   MOD_VEX_0F72_REG_6,
 875   MOD_VEX_0F73_REG_2,
 876   MOD_VEX_0F73_REG_3,
 877   MOD_VEX_0F73_REG_6,
 878   MOD_VEX_0F73_REG_7,
 879   MOD_VEX_W_0_0F91_P_0_LEN_0,
 880   MOD_VEX_W_1_0F91_P_0_LEN_0,
 881   MOD_VEX_W_0_0F91_P_2_LEN_0,
 882   MOD_VEX_W_1_0F91_P_2_LEN_0,
 883   MOD_VEX_W_0_0F92_P_0_LEN_0,
 884   MOD_VEX_W_0_0F92_P_2_LEN_0,
 885   MOD_VEX_0F92_P_3_LEN_0,
 886   MOD_VEX_W_0_0F93_P_0_LEN_0,
 887   MOD_VEX_W_0_0F93_P_2_LEN_0,
 888   MOD_VEX_0F93_P_3_LEN_0,
 889   MOD_VEX_W_0_0F98_P_0_LEN_0,
 890   MOD_VEX_W_1_0F98_P_0_LEN_0,
 891   MOD_VEX_W_0_0F98_P_2_LEN_0,
 892   MOD_VEX_W_1_0F98_P_2_LEN_0,
 893   MOD_VEX_W_0_0F99_P_0_LEN_0,
 894   MOD_VEX_W_1_0F99_P_0_LEN_0,
 895   MOD_VEX_W_0_0F99_P_2_LEN_0,
 896   MOD_VEX_W_1_0F99_P_2_LEN_0,
 897   MOD_VEX_0FAE_REG_2,
 898   MOD_VEX_0FAE_REG_3,
 899   MOD_VEX_0FD7_PREFIX_2,
 900   MOD_VEX_0FE7_PREFIX_2,
 901   MOD_VEX_0FF0_PREFIX_3,
 902   MOD_VEX_0F381A_PREFIX_2,
 903   MOD_VEX_0F382A_PREFIX_2,
 904   MOD_VEX_0F382C_PREFIX_2,
 905   MOD_VEX_0F382D_PREFIX_2,
 906   MOD_VEX_0F382E_PREFIX_2,
 907   MOD_VEX_0F382F_PREFIX_2,
 908   MOD_VEX_0F385A_PREFIX_2,
 909   MOD_VEX_0F388C_PREFIX_2,
 910   MOD_VEX_0F388E_PREFIX_2,
 911   MOD_VEX_W_0_0F3A30_P_2_LEN_0,
 912   MOD_VEX_W_1_0F3A30_P_2_LEN_0,
 913   MOD_VEX_W_0_0F3A31_P_2_LEN_0,
 914   MOD_VEX_W_1_0F3A31_P_2_LEN_0,
 915   MOD_VEX_W_0_0F3A32_P_2_LEN_0,
 916   MOD_VEX_W_1_0F3A32_P_2_LEN_0,
 917   MOD_VEX_W_0_0F3A33_P_2_LEN_0,
 918   MOD_VEX_W_1_0F3A33_P_2_LEN_0,
 919
 920   MOD_VEX_0FXOP_09_12,
 921
 922   MOD_EVEX_0F12_PREFIX_0,
 923   MOD_EVEX_0F12_PREFIX_2,
 924   MOD_EVEX_0F13,
 925   MOD_EVEX_0F16_PREFIX_0,
 926   MOD_EVEX_0F16_PREFIX_2,
 927   MOD_EVEX_0F17,
 928   MOD_EVEX_0F2B,
 929   MOD_EVEX_0F381A_P_2_W_0,
 930   MOD_EVEX_0F381A_P_2_W_1,
 931   MOD_EVEX_0F381B_P_2_W_0,
 932   MOD_EVEX_0F381B_P_2_W_1,
 933   MOD_EVEX_0F385A_P_2_W_0,
 934   MOD_EVEX_0F385A_P_2_W_1,
 935   MOD_EVEX_0F385B_P_2_W_0,
 936   MOD_EVEX_0F385B_P_2_W_1,
 937   MOD_EVEX_0F38C6_REG_1,
 938   MOD_EVEX_0F38C6_REG_2,
 939   MOD_EVEX_0F38C6_REG_5,
 940   MOD_EVEX_0F38C6_REG_6,
 941   MOD_EVEX_0F38C7_REG_1,
 942   MOD_EVEX_0F38C7_REG_2,
 943   MOD_EVEX_0F38C7_REG_5,
 944   MOD_EVEX_0F38C7_REG_6
 945 };
 946
 947 enum
 948 {
 949   RM_C6_REG_7 = 0,
 950   RM_C7_REG_7,
 951   RM_0F01_REG_0,
 952   RM_0F01_REG_1,
 953   RM_0F01_REG_2,
 954   RM_0F01_REG_3,
 955   RM_0F01_REG_5_MOD_3,
 956   RM_0F01_REG_7_MOD_3,
 957   RM_0F1E_P_1_MOD_3_REG_7,
 958   RM_0FAE_REG_6_MOD_3_P_0,
 959   RM_0FAE_REG_7_MOD_3,
 960 };
 961
 962 enum
 963 {
 964   PREFIX_90 = 0,
 965   PREFIX_0F01_REG_3_RM_1,
 966   PREFIX_0F01_REG_5_MOD_0,
 967   PREFIX_0F01_REG_5_MOD_3_RM_0,
 968   PREFIX_0F01_REG_5_MOD_3_RM_1,
 969   PREFIX_0F01_REG_5_MOD_3_RM_2,
 970   PREFIX_0F01_REG_7_MOD_3_RM_2,
 971   PREFIX_0F01_REG_7_MOD_3_RM_3,
 972   PREFIX_0F09,
 973   PREFIX_0F10,
 974   PREFIX_0F11,
 975   PREFIX_0F12,
 976   PREFIX_0F16,
 977   PREFIX_0F1A,
 978   PREFIX_0F1B,
 979   PREFIX_0F1C,
 980   PREFIX_0F1E,
 981   PREFIX_0F2A,
 982   PREFIX_0F2B,
 983   PREFIX_0F2C,
 984   PREFIX_0F2D,
 985   PREFIX_0F2E,
 986   PREFIX_0F2F,
 987   PREFIX_0F51,
 988   PREFIX_0F52,
 989   PREFIX_0F53,
 990   PREFIX_0F58,
 991   PREFIX_0F59,
 992   PREFIX_0F5A,
 993   PREFIX_0F5B,
 994   PREFIX_0F5C,
 995   PREFIX_0F5D,
 996   PREFIX_0F5E,
 997   PREFIX_0F5F,
 998   PREFIX_0F60,
 999   PREFIX_0F61,
1000   PREFIX_0F62,
1001   PREFIX_0F6C,
1002   PREFIX_0F6D,
1003   PREFIX_0F6F,
1004   PREFIX_0F70,
1005   PREFIX_0F73_REG_3,
1006   PREFIX_0F73_REG_7,
1007   PREFIX_0F78,
1008   PREFIX_0F79,
1009   PREFIX_0F7C,
1010   PREFIX_0F7D,
1011   PREFIX_0F7E,
1012   PREFIX_0F7F,
1013   PREFIX_0FAE_REG_0_MOD_3,
1014   PREFIX_0FAE_REG_1_MOD_3,
1015   PREFIX_0FAE_REG_2_MOD_3,
1016   PREFIX_0FAE_REG_3_MOD_3,
1017   PREFIX_0FAE_REG_4_MOD_0,
1018   PREFIX_0FAE_REG_4_MOD_3,
1019   PREFIX_0FAE_REG_5_MOD_0,
1020   PREFIX_0FAE_REG_5_MOD_3,
1021   PREFIX_0FAE_REG_6_MOD_0,
1022   PREFIX_0FAE_REG_6_MOD_3,
1023   PREFIX_0FAE_REG_7_MOD_0,
1024   PREFIX_0FB8,
1025   PREFIX_0FBC,
1026   PREFIX_0FBD,
1027   PREFIX_0FC2,
1028   PREFIX_0FC3_MOD_0,
1029   PREFIX_0FC7_REG_6_MOD_0,
1030   PREFIX_0FC7_REG_6_MOD_3,
1031   PREFIX_0FC7_REG_7_MOD_3,
1032   PREFIX_0FD0,
1033   PREFIX_0FD6,
1034   PREFIX_0FE6,
1035   PREFIX_0FE7,
1036   PREFIX_0FF0,
1037   PREFIX_0FF7,
1038   PREFIX_0F3810,
1039   PREFIX_0F3814,
1040   PREFIX_0F3815,
1041   PREFIX_0F3817,
1042   PREFIX_0F3820,
1043   PREFIX_0F3821,
1044   PREFIX_0F3822,
1045   PREFIX_0F3823,
1046   PREFIX_0F3824,
1047   PREFIX_0F3825,
1048   PREFIX_0F3828,
1049   PREFIX_0F3829,
1050   PREFIX_0F382A,
1051   PREFIX_0F382B,
1052   PREFIX_0F3830,
1053   PREFIX_0F3831,
1054   PREFIX_0F3832,
1055   PREFIX_0F3833,
1056   PREFIX_0F3834,
1057   PREFIX_0F3835,
1058   PREFIX_0F3837,
1059   PREFIX_0F3838,
1060   PREFIX_0F3839,
1061   PREFIX_0F383A,
1062   PREFIX_0F383B,
1063   PREFIX_0F383C,
1064   PREFIX_0F383D,
1065   PREFIX_0F383E,
1066   PREFIX_0F383F,
1067   PREFIX_0F3840,
1068   PREFIX_0F3841,
1069   PREFIX_0F3880,
1070   PREFIX_0F3881,
1071   PREFIX_0F3882,
1072   PREFIX_0F38C8,
1073   PREFIX_0F38C9,
1074   PREFIX_0F38CA,
1075   PREFIX_0F38CB,
1076   PREFIX_0F38CC,
1077   PREFIX_0F38CD,
1078   PREFIX_0F38CF,
1079   PREFIX_0F38DB,
1080   PREFIX_0F38DC,
1081   PREFIX_0F38DD,
1082   PREFIX_0F38DE,
1083   PREFIX_0F38DF,
1084   PREFIX_0F38F0,
1085   PREFIX_0F38F1,
1086   PREFIX_0F38F5,
1087   PREFIX_0F38F6,
1088   PREFIX_0F38F8,
1089   PREFIX_0F38F9,
1090   PREFIX_0F3A08,
1091   PREFIX_0F3A09,
1092   PREFIX_0F3A0A,
1093   PREFIX_0F3A0B,
1094   PREFIX_0F3A0C,
1095   PREFIX_0F3A0D,
1096   PREFIX_0F3A0E,
1097   PREFIX_0F3A14,
1098   PREFIX_0F3A15,
1099   PREFIX_0F3A16,
1100   PREFIX_0F3A17,
1101   PREFIX_0F3A20,
1102   PREFIX_0F3A21,
1103   PREFIX_0F3A22,
1104   PREFIX_0F3A40,
1105   PREFIX_0F3A41,
1106   PREFIX_0F3A42,
1107   PREFIX_0F3A44,
1108   PREFIX_0F3A60,
1109   PREFIX_0F3A61,
1110   PREFIX_0F3A62,
1111   PREFIX_0F3A63,
1112   PREFIX_0F3ACC,
1113   PREFIX_0F3ACE,
1114   PREFIX_0F3ACF,
1115   PREFIX_0F3ADF,
1116   PREFIX_VEX_0F10,
1117   PREFIX_VEX_0F11,
1118   PREFIX_VEX_0F12,
1119   PREFIX_VEX_0F16,
1120   PREFIX_VEX_0F2A,
1121   PREFIX_VEX_0F2C,
1122   PREFIX_VEX_0F2D,
1123   PREFIX_VEX_0F2E,
1124   PREFIX_VEX_0F2F,
1125   PREFIX_VEX_0F41,
1126   PREFIX_VEX_0F42,
1127   PREFIX_VEX_0F44,
1128   PREFIX_VEX_0F45,
1129   PREFIX_VEX_0F46,
1130   PREFIX_VEX_0F47,
1131   PREFIX_VEX_0F4A,
1132   PREFIX_VEX_0F4B,
1133   PREFIX_VEX_0F51,
1134   PREFIX_VEX_0F52,
1135   PREFIX_VEX_0F53,
1136   PREFIX_VEX_0F58,
1137   PREFIX_VEX_0F59,
1138   PREFIX_VEX_0F5A,
1139   PREFIX_VEX_0F5B,
1140   PREFIX_VEX_0F5C,
1141   PREFIX_VEX_0F5D,
1142   PREFIX_VEX_0F5E,
1143   PREFIX_VEX_0F5F,
1144   PREFIX_VEX_0F60,
1145   PREFIX_VEX_0F61,
1146   PREFIX_VEX_0F62,
1147   PREFIX_VEX_0F63,
1148   PREFIX_VEX_0F64,
1149   PREFIX_VEX_0F65,
1150   PREFIX_VEX_0F66,
1151   PREFIX_VEX_0F67,
1152   PREFIX_VEX_0F68,
1153   PREFIX_VEX_0F69,
1154   PREFIX_VEX_0F6A,
1155   PREFIX_VEX_0F6B,
1156   PREFIX_VEX_0F6C,
1157   PREFIX_VEX_0F6D,
1158   PREFIX_VEX_0F6E,
1159   PREFIX_VEX_0F6F,
1160   PREFIX_VEX_0F70,
1161   PREFIX_VEX_0F71_REG_2,
1162   PREFIX_VEX_0F71_REG_4,
1163   PREFIX_VEX_0F71_REG_6,
1164   PREFIX_VEX_0F72_REG_2,
1165   PREFIX_VEX_0F72_REG_4,
1166   PREFIX_VEX_0F72_REG_6,
1167   PREFIX_VEX_0F73_REG_2,
1168   PREFIX_VEX_0F73_REG_3,
1169   PREFIX_VEX_0F73_REG_6,
1170   PREFIX_VEX_0F73_REG_7,
1171   PREFIX_VEX_0F74,
1172   PREFIX_VEX_0F75,
1173   PREFIX_VEX_0F76,
1174   PREFIX_VEX_0F77,
1175   PREFIX_VEX_0F7C,
1176   PREFIX_VEX_0F7D,
1177   PREFIX_VEX_0F7E,
1178   PREFIX_VEX_0F7F,
1179   PREFIX_VEX_0F90,
1180   PREFIX_VEX_0F91,
1181   PREFIX_VEX_0F92,
1182   PREFIX_VEX_0F93,
1183   PREFIX_VEX_0F98,
1184   PREFIX_VEX_0F99,
1185   PREFIX_VEX_0FC2,
1186   PREFIX_VEX_0FC4,
1187   PREFIX_VEX_0FC5,
1188   PREFIX_VEX_0FD0,
1189   PREFIX_VEX_0FD1,
1190   PREFIX_VEX_0FD2,
1191   PREFIX_VEX_0FD3,
1192   PREFIX_VEX_0FD4,
1193   PREFIX_VEX_0FD5,
1194   PREFIX_VEX_0FD6,
1195   PREFIX_VEX_0FD7,
1196   PREFIX_VEX_0FD8,
1197   PREFIX_VEX_0FD9,
1198   PREFIX_VEX_0FDA,
1199   PREFIX_VEX_0FDB,
1200   PREFIX_VEX_0FDC,
1201   PREFIX_VEX_0FDD,
1202   PREFIX_VEX_0FDE,
1203   PREFIX_VEX_0FDF,
1204   PREFIX_VEX_0FE0,
1205   PREFIX_VEX_0FE1,
1206   PREFIX_VEX_0FE2,
1207   PREFIX_VEX_0FE3,
1208   PREFIX_VEX_0FE4,
1209   PREFIX_VEX_0FE5,
1210   PREFIX_VEX_0FE6,
1211   PREFIX_VEX_0FE7,
1212   PREFIX_VEX_0FE8,
1213   PREFIX_VEX_0FE9,
1214   PREFIX_VEX_0FEA,
1215   PREFIX_VEX_0FEB,
1216   PREFIX_VEX_0FEC,
1217   PREFIX_VEX_0FED,
1218   PREFIX_VEX_0FEE,
1219   PREFIX_VEX_0FEF,
1220   PREFIX_VEX_0FF0,
1221   PREFIX_VEX_0FF1,
1222   PREFIX_VEX_0FF2,
1223   PREFIX_VEX_0FF3,
1224   PREFIX_VEX_0FF4,
1225   PREFIX_VEX_0FF5,
1226   PREFIX_VEX_0FF6,
1227   PREFIX_VEX_0FF7,
1228   PREFIX_VEX_0FF8,
1229   PREFIX_VEX_0FF9,
1230   PREFIX_VEX_0FFA,
1231   PREFIX_VEX_0FFB,
1232   PREFIX_VEX_0FFC,
1233   PREFIX_VEX_0FFD,
1234   PREFIX_VEX_0FFE,
1235   PREFIX_VEX_0F3800,
1236   PREFIX_VEX_0F3801,
1237   PREFIX_VEX_0F3802,
1238   PREFIX_VEX_0F3803,
1239   PREFIX_VEX_0F3804,
1240   PREFIX_VEX_0F3805,
1241   PREFIX_VEX_0F3806,
1242   PREFIX_VEX_0F3807,
1243   PREFIX_VEX_0F3808,
1244   PREFIX_VEX_0F3809,
1245   PREFIX_VEX_0F380A,
1246   PREFIX_VEX_0F380B,
1247   PREFIX_VEX_0F380C,
1248   PREFIX_VEX_0F380D,
1249   PREFIX_VEX_0F380E,
1250   PREFIX_VEX_0F380F,
1251   PREFIX_VEX_0F3813,
1252   PREFIX_VEX_0F3816,
1253   PREFIX_VEX_0F3817,
1254   PREFIX_VEX_0F3818,
1255   PREFIX_VEX_0F3819,
1256   PREFIX_VEX_0F381A,
1257   PREFIX_VEX_0F381C,
1258   PREFIX_VEX_0F381D,
1259   PREFIX_VEX_0F381E,
1260   PREFIX_VEX_0F3820,
1261   PREFIX_VEX_0F3821,
1262   PREFIX_VEX_0F3822,
1263   PREFIX_VEX_0F3823,
1264   PREFIX_VEX_0F3824,
1265   PREFIX_VEX_0F3825,
1266   PREFIX_VEX_0F3828,
1267   PREFIX_VEX_0F3829,
1268   PREFIX_VEX_0F382A,
1269   PREFIX_VEX_0F382B,
1270   PREFIX_VEX_0F382C,
1271   PREFIX_VEX_0F382D,
1272   PREFIX_VEX_0F382E,
1273   PREFIX_VEX_0F382F,
1274   PREFIX_VEX_0F3830,
1275   PREFIX_VEX_0F3831,
1276   PREFIX_VEX_0F3832,
1277   PREFIX_VEX_0F3833,
1278   PREFIX_VEX_0F3834,
1279   PREFIX_VEX_0F3835,
1280   PREFIX_VEX_0F3836,
1281   PREFIX_VEX_0F3837,
1282   PREFIX_VEX_0F3838,
1283   PREFIX_VEX_0F3839,
1284   PREFIX_VEX_0F383A,
1285   PREFIX_VEX_0F383B,
1286   PREFIX_VEX_0F383C,
1287   PREFIX_VEX_0F383D,
1288   PREFIX_VEX_0F383E,
1289   PREFIX_VEX_0F383F,
1290   PREFIX_VEX_0F3840,
1291   PREFIX_VEX_0F3841,
1292   PREFIX_VEX_0F3845,
1293   PREFIX_VEX_0F3846,
1294   PREFIX_VEX_0F3847,
1295   PREFIX_VEX_0F3858,
1296   PREFIX_VEX_0F3859,
1297   PREFIX_VEX_0F385A,
1298   PREFIX_VEX_0F3878,
1299   PREFIX_VEX_0F3879,
1300   PREFIX_VEX_0F388C,
1301   PREFIX_VEX_0F388E,
1302   PREFIX_VEX_0F3890,
1303   PREFIX_VEX_0F3891,
1304   PREFIX_VEX_0F3892,
1305   PREFIX_VEX_0F3893,
1306   PREFIX_VEX_0F3896,
1307   PREFIX_VEX_0F3897,
1308   PREFIX_VEX_0F3898,
1309   PREFIX_VEX_0F3899,
1310   PREFIX_VEX_0F389A,
1311   PREFIX_VEX_0F389B,
1312   PREFIX_VEX_0F389C,
1313   PREFIX_VEX_0F389D,
1314   PREFIX_VEX_0F389E,
1315   PREFIX_VEX_0F389F,
1316   PREFIX_VEX_0F38A6,
1317   PREFIX_VEX_0F38A7,
1318   PREFIX_VEX_0F38A8,
1319   PREFIX_VEX_0F38A9,
1320   PREFIX_VEX_0F38AA,
1321   PREFIX_VEX_0F38AB,
1322   PREFIX_VEX_0F38AC,
1323   PREFIX_VEX_0F38AD,
1324   PREFIX_VEX_0F38AE,
1325   PREFIX_VEX_0F38AF,
1326   PREFIX_VEX_0F38B6,
1327   PREFIX_VEX_0F38B7,
1328   PREFIX_VEX_0F38B8,
1329   PREFIX_VEX_0F38B9,
1330   PREFIX_VEX_0F38BA,
1331   PREFIX_VEX_0F38BB,
1332   PREFIX_VEX_0F38BC,
1333   PREFIX_VEX_0F38BD,
1334   PREFIX_VEX_0F38BE,
1335   PREFIX_VEX_0F38BF,
1336   PREFIX_VEX_0F38CF,
1337   PREFIX_VEX_0F38DB,
1338   PREFIX_VEX_0F38DC,
1339   PREFIX_VEX_0F38DD,
1340   PREFIX_VEX_0F38DE,
1341   PREFIX_VEX_0F38DF,
1342   PREFIX_VEX_0F38F2,
1343   PREFIX_VEX_0F38F3_REG_1,
1344   PREFIX_VEX_0F38F3_REG_2,
1345   PREFIX_VEX_0F38F3_REG_3,
1346   PREFIX_VEX_0F38F5,
1347   PREFIX_VEX_0F38F6,
1348   PREFIX_VEX_0F38F7,
1349   PREFIX_VEX_0F3A00,
1350   PREFIX_VEX_0F3A01,
1351   PREFIX_VEX_0F3A02,
1352   PREFIX_VEX_0F3A04,
1353   PREFIX_VEX_0F3A05,
1354   PREFIX_VEX_0F3A06,
1355   PREFIX_VEX_0F3A08,
1356   PREFIX_VEX_0F3A09,
1357   PREFIX_VEX_0F3A0A,
1358   PREFIX_VEX_0F3A0B,
1359   PREFIX_VEX_0F3A0C,
1360   PREFIX_VEX_0F3A0D,
1361   PREFIX_VEX_0F3A0E,
1362   PREFIX_VEX_0F3A0F,
1363   PREFIX_VEX_0F3A14,
1364   PREFIX_VEX_0F3A15,
1365   PREFIX_VEX_0F3A16,
1366   PREFIX_VEX_0F3A17,
1367   PREFIX_VEX_0F3A18,
1368   PREFIX_VEX_0F3A19,
1369   PREFIX_VEX_0F3A1D,
1370   PREFIX_VEX_0F3A20,
1371   PREFIX_VEX_0F3A21,
1372   PREFIX_VEX_0F3A22,
1373   PREFIX_VEX_0F3A30,
1374   PREFIX_VEX_0F3A31,
1375   PREFIX_VEX_0F3A32,
1376   PREFIX_VEX_0F3A33,
1377   PREFIX_VEX_0F3A38,
1378   PREFIX_VEX_0F3A39,
1379   PREFIX_VEX_0F3A40,
1380   PREFIX_VEX_0F3A41,
1381   PREFIX_VEX_0F3A42,
1382   PREFIX_VEX_0F3A44,
1383   PREFIX_VEX_0F3A46,
1384   PREFIX_VEX_0F3A48,
1385   PREFIX_VEX_0F3A49,
1386   PREFIX_VEX_0F3A4A,
1387   PREFIX_VEX_0F3A4B,
1388   PREFIX_VEX_0F3A4C,
1389   PREFIX_VEX_0F3A5C,
1390   PREFIX_VEX_0F3A5D,
1391   PREFIX_VEX_0F3A5E,
1392   PREFIX_VEX_0F3A5F,
1393   PREFIX_VEX_0F3A60,
1394   PREFIX_VEX_0F3A61,
1395   PREFIX_VEX_0F3A62,
1396   PREFIX_VEX_0F3A63,
1397   PREFIX_VEX_0F3A68,
1398   PREFIX_VEX_0F3A69,
1399   PREFIX_VEX_0F3A6A,
1400   PREFIX_VEX_0F3A6B,
1401   PREFIX_VEX_0F3A6C,
1402   PREFIX_VEX_0F3A6D,
1403   PREFIX_VEX_0F3A6E,
1404   PREFIX_VEX_0F3A6F,
1405   PREFIX_VEX_0F3A78,
1406   PREFIX_VEX_0F3A79,
1407   PREFIX_VEX_0F3A7A,
1408   PREFIX_VEX_0F3A7B,
1409   PREFIX_VEX_0F3A7C,
1410   PREFIX_VEX_0F3A7D,
1411   PREFIX_VEX_0F3A7E,
1412   PREFIX_VEX_0F3A7F,
1413   PREFIX_VEX_0F3ACE,
1414   PREFIX_VEX_0F3ACF,
1415   PREFIX_VEX_0F3ADF,
1416   PREFIX_VEX_0F3AF0,
1417
1418   PREFIX_EVEX_0F10,
1419   PREFIX_EVEX_0F11,
1420   PREFIX_EVEX_0F12,
1421   PREFIX_EVEX_0F16,
1422   PREFIX_EVEX_0F2A,
1423   PREFIX_EVEX_0F2C,
1424   PREFIX_EVEX_0F2D,
1425   PREFIX_EVEX_0F2E,
1426   PREFIX_EVEX_0F2F,
1427   PREFIX_EVEX_0F51,
1428   PREFIX_EVEX_0F58,
1429   PREFIX_EVEX_0F59,
1430   PREFIX_EVEX_0F5A,
1431   PREFIX_EVEX_0F5B,
1432   PREFIX_EVEX_0F5C,
1433   PREFIX_EVEX_0F5D,
1434   PREFIX_EVEX_0F5E,
1435   PREFIX_EVEX_0F5F,
1436   PREFIX_EVEX_0F64,
1437   PREFIX_EVEX_0F65,
1438   PREFIX_EVEX_0F66,
1439   PREFIX_EVEX_0F6E,
1440   PREFIX_EVEX_0F6F,
1441   PREFIX_EVEX_0F70,
1442   PREFIX_EVEX_0F71_REG_2,
1443   PREFIX_EVEX_0F71_REG_4,
1444   PREFIX_EVEX_0F71_REG_6,
1445   PREFIX_EVEX_0F72_REG_0,
1446   PREFIX_EVEX_0F72_REG_1,
1447   PREFIX_EVEX_0F72_REG_2,
1448   PREFIX_EVEX_0F72_REG_4,
1449   PREFIX_EVEX_0F72_REG_6,
1450   PREFIX_EVEX_0F73_REG_2,
1451   PREFIX_EVEX_0F73_REG_3,
1452   PREFIX_EVEX_0F73_REG_6,
1453   PREFIX_EVEX_0F73_REG_7,
1454   PREFIX_EVEX_0F74,
1455   PREFIX_EVEX_0F75,
1456   PREFIX_EVEX_0F76,
1457   PREFIX_EVEX_0F78,
1458   PREFIX_EVEX_0F79,
1459   PREFIX_EVEX_0F7A,
1460   PREFIX_EVEX_0F7B,
1461   PREFIX_EVEX_0F7E,
1462   PREFIX_EVEX_0F7F,
1463   PREFIX_EVEX_0FC2,
1464   PREFIX_EVEX_0FC4,
1465   PREFIX_EVEX_0FC5,
1466   PREFIX_EVEX_0FD6,
1467   PREFIX_EVEX_0FDB,
1468   PREFIX_EVEX_0FDF,
1469   PREFIX_EVEX_0FE2,
1470   PREFIX_EVEX_0FE6,
1471   PREFIX_EVEX_0FE7,
1472   PREFIX_EVEX_0FEB,
1473   PREFIX_EVEX_0FEF,
1474   PREFIX_EVEX_0F380D,
1475   PREFIX_EVEX_0F3810,
1476   PREFIX_EVEX_0F3811,
1477   PREFIX_EVEX_0F3812,
1478   PREFIX_EVEX_0F3813,
1479   PREFIX_EVEX_0F3814,
1480   PREFIX_EVEX_0F3815,
1481   PREFIX_EVEX_0F3816,
1482   PREFIX_EVEX_0F3819,
1483   PREFIX_EVEX_0F381A,
1484   PREFIX_EVEX_0F381B,
1485   PREFIX_EVEX_0F381E,
1486   PREFIX_EVEX_0F381F,
1487   PREFIX_EVEX_0F3820,
1488   PREFIX_EVEX_0F3821,
1489   PREFIX_EVEX_0F3822,
1490   PREFIX_EVEX_0F3823,
1491   PREFIX_EVEX_0F3824,
1492   PREFIX_EVEX_0F3825,
1493   PREFIX_EVEX_0F3826,
1494   PREFIX_EVEX_0F3827,
1495   PREFIX_EVEX_0F3828,
1496   PREFIX_EVEX_0F3829,
1497   PREFIX_EVEX_0F382A,
1498   PREFIX_EVEX_0F382C,
1499   PREFIX_EVEX_0F382D,
1500   PREFIX_EVEX_0F3830,
1501   PREFIX_EVEX_0F3831,
1502   PREFIX_EVEX_0F3832,
1503   PREFIX_EVEX_0F3833,
1504   PREFIX_EVEX_0F3834,
1505   PREFIX_EVEX_0F3835,
1506   PREFIX_EVEX_0F3836,
1507   PREFIX_EVEX_0F3837,
1508   PREFIX_EVEX_0F3838,
1509   PREFIX_EVEX_0F3839,
1510   PREFIX_EVEX_0F383A,
1511   PREFIX_EVEX_0F383B,
1512   PREFIX_EVEX_0F383D,
1513   PREFIX_EVEX_0F383F,
1514   PREFIX_EVEX_0F3840,
1515   PREFIX_EVEX_0F3842,
1516   PREFIX_EVEX_0F3843,
1517   PREFIX_EVEX_0F3844,
1518   PREFIX_EVEX_0F3845,
1519   PREFIX_EVEX_0F3846,
1520   PREFIX_EVEX_0F3847,
1521   PREFIX_EVEX_0F384C,
1522   PREFIX_EVEX_0F384D,
1523   PREFIX_EVEX_0F384E,
1524   PREFIX_EVEX_0F384F,
1525   PREFIX_EVEX_0F3850,
1526   PREFIX_EVEX_0F3851,
1527   PREFIX_EVEX_0F3852,
1528   PREFIX_EVEX_0F3853,
1529   PREFIX_EVEX_0F3854,
1530   PREFIX_EVEX_0F3855,
1531   PREFIX_EVEX_0F3859,
1532   PREFIX_EVEX_0F385A,
1533   PREFIX_EVEX_0F385B,
1534   PREFIX_EVEX_0F3862,
1535   PREFIX_EVEX_0F3863,
1536   PREFIX_EVEX_0F3864,
1537   PREFIX_EVEX_0F3865,
1538   PREFIX_EVEX_0F3866,
1539   PREFIX_EVEX_0F3868,
1540   PREFIX_EVEX_0F3870,
1541   PREFIX_EVEX_0F3871,
1542   PREFIX_EVEX_0F3872,
1543   PREFIX_EVEX_0F3873,
1544   PREFIX_EVEX_0F3875,
1545   PREFIX_EVEX_0F3876,
1546   PREFIX_EVEX_0F3877,
1547   PREFIX_EVEX_0F387A,
1548   PREFIX_EVEX_0F387B,
1549   PREFIX_EVEX_0F387C,
1550   PREFIX_EVEX_0F387D,
1551   PREFIX_EVEX_0F387E,
1552   PREFIX_EVEX_0F387F,
1553   PREFIX_EVEX_0F3883,
1554   PREFIX_EVEX_0F3888,
1555   PREFIX_EVEX_0F3889,
1556   PREFIX_EVEX_0F388A,
1557   PREFIX_EVEX_0F388B,
1558   PREFIX_EVEX_0F388D,
1559   PREFIX_EVEX_0F388F,
1560   PREFIX_EVEX_0F3890,
1561   PREFIX_EVEX_0F3891,
1562   PREFIX_EVEX_0F3892,
1563   PREFIX_EVEX_0F3893,
1564   PREFIX_EVEX_0F389A,
1565   PREFIX_EVEX_0F389B,
1566   PREFIX_EVEX_0F38A0,
1567   PREFIX_EVEX_0F38A1,
1568   PREFIX_EVEX_0F38A2,
1569   PREFIX_EVEX_0F38A3,
1570   PREFIX_EVEX_0F38AA,
1571   PREFIX_EVEX_0F38AB,
1572   PREFIX_EVEX_0F38B4,
1573   PREFIX_EVEX_0F38B5,
1574   PREFIX_EVEX_0F38C4,
1575   PREFIX_EVEX_0F38C6_REG_1,
1576   PREFIX_EVEX_0F38C6_REG_2,
1577   PREFIX_EVEX_0F38C6_REG_5,
1578   PREFIX_EVEX_0F38C6_REG_6,
1579   PREFIX_EVEX_0F38C7_REG_1,
1580   PREFIX_EVEX_0F38C7_REG_2,
1581   PREFIX_EVEX_0F38C7_REG_5,
1582   PREFIX_EVEX_0F38C7_REG_6,
1583   PREFIX_EVEX_0F38C8,
1584   PREFIX_EVEX_0F38CA,
1585   PREFIX_EVEX_0F38CB,
1586   PREFIX_EVEX_0F38CC,
1587   PREFIX_EVEX_0F38CD,
1588
1589   PREFIX_EVEX_0F3A00,
1590   PREFIX_EVEX_0F3A01,
1591   PREFIX_EVEX_0F3A03,
1592   PREFIX_EVEX_0F3A05,
1593   PREFIX_EVEX_0F3A08,
1594   PREFIX_EVEX_0F3A09,
1595   PREFIX_EVEX_0F3A0A,
1596   PREFIX_EVEX_0F3A0B,
1597   PREFIX_EVEX_0F3A14,
1598   PREFIX_EVEX_0F3A15,
1599   PREFIX_EVEX_0F3A16,
1600   PREFIX_EVEX_0F3A17,
1601   PREFIX_EVEX_0F3A18,
1602   PREFIX_EVEX_0F3A19,
1603   PREFIX_EVEX_0F3A1A,
1604   PREFIX_EVEX_0F3A1B,
1605   PREFIX_EVEX_0F3A1E,
1606   PREFIX_EVEX_0F3A1F,
1607   PREFIX_EVEX_0F3A20,
1608   PREFIX_EVEX_0F3A21,
1609   PREFIX_EVEX_0F3A22,
1610   PREFIX_EVEX_0F3A23,
1611   PREFIX_EVEX_0F3A25,
1612   PREFIX_EVEX_0F3A26,
1613   PREFIX_EVEX_0F3A27,
1614   PREFIX_EVEX_0F3A38,
1615   PREFIX_EVEX_0F3A39,
1616   PREFIX_EVEX_0F3A3A,
1617   PREFIX_EVEX_0F3A3B,
1618   PREFIX_EVEX_0F3A3E,
1619   PREFIX_EVEX_0F3A3F,
1620   PREFIX_EVEX_0F3A42,
1621   PREFIX_EVEX_0F3A43,
1622   PREFIX_EVEX_0F3A50,
1623   PREFIX_EVEX_0F3A51,
1624   PREFIX_EVEX_0F3A54,
1625   PREFIX_EVEX_0F3A55,
1626   PREFIX_EVEX_0F3A56,
1627   PREFIX_EVEX_0F3A57,
1628   PREFIX_EVEX_0F3A66,
1629   PREFIX_EVEX_0F3A67,
1630   PREFIX_EVEX_0F3A70,
1631   PREFIX_EVEX_0F3A71,
1632   PREFIX_EVEX_0F3A72,
1633   PREFIX_EVEX_0F3A73,
1634 };
1635
1636 enum
1637 {
1638   X86_64_06 = 0,
1639   X86_64_07,
1640   X86_64_0E,
1641   X86_64_16,
1642   X86_64_17,
1643   X86_64_1E,
1644   X86_64_1F,
1645   X86_64_27,
1646   X86_64_2F,
1647   X86_64_37,
1648   X86_64_3F,
1649   X86_64_60,
1650   X86_64_61,
1651   X86_64_62,
1652   X86_64_63,
1653   X86_64_6D,
1654   X86_64_6F,
1655   X86_64_82,
1656   X86_64_9A,
1657   X86_64_C2,
1658   X86_64_C3,
1659   X86_64_C4,
1660   X86_64_C5,
1661   X86_64_CE,
1662   X86_64_D4,
1663   X86_64_D5,
1664   X86_64_E8,
1665   X86_64_E9,
1666   X86_64_EA,
1667   X86_64_0F01_REG_0,
1668   X86_64_0F01_REG_1,
1669   X86_64_0F01_REG_2,
1670   X86_64_0F01_REG_3
1671 };
1672
1673 enum
1674 {
1675   THREE_BYTE_0F38 = 0,
1676   THREE_BYTE_0F3A
1677 };
1678
1679 enum
1680 {
1681   XOP_08 = 0,
1682   XOP_09,
1683   XOP_0A
1684 };
1685
1686 enum
1687 {
1688   VEX_0F = 0,
1689   VEX_0F38,
1690   VEX_0F3A
1691 };
1692
1693 enum
1694 {
1695   EVEX_0F = 0,
1696   EVEX_0F38,
1697   EVEX_0F3A
1698 };
1699
1700 enum
1701 {
1702   VEX_LEN_0F12_P_0_M_0 = 0,
1703   VEX_LEN_0F12_P_0_M_1,
1704 #define VEX_LEN_0F12_P_2_M_0 VEX_LEN_0F12_P_0_M_0
1705   VEX_LEN_0F13_M_0,
1706   VEX_LEN_0F16_P_0_M_0,
1707   VEX_LEN_0F16_P_0_M_1,
1708 #define VEX_LEN_0F16_P_2_M_0 VEX_LEN_0F16_P_0_M_0
1709   VEX_LEN_0F17_M_0,
1710   VEX_LEN_0F41_P_0,
1711   VEX_LEN_0F41_P_2,
1712   VEX_LEN_0F42_P_0,
1713   VEX_LEN_0F42_P_2,
1714   VEX_LEN_0F44_P_0,
1715   VEX_LEN_0F44_P_2,
1716   VEX_LEN_0F45_P_0,
1717   VEX_LEN_0F45_P_2,
1718   VEX_LEN_0F46_P_0,
1719   VEX_LEN_0F46_P_2,
1720   VEX_LEN_0F47_P_0,
1721   VEX_LEN_0F47_P_2,
1722   VEX_LEN_0F4A_P_0,
1723   VEX_LEN_0F4A_P_2,
1724   VEX_LEN_0F4B_P_0,
1725   VEX_LEN_0F4B_P_2,
1726   VEX_LEN_0F6E_P_2,
1727   VEX_LEN_0F77_P_0,
1728   VEX_LEN_0F7E_P_1,
1729   VEX_LEN_0F7E_P_2,
1730   VEX_LEN_0F90_P_0,
1731   VEX_LEN_0F90_P_2,
1732   VEX_LEN_0F91_P_0,
1733   VEX_LEN_0F91_P_2,
1734   VEX_LEN_0F92_P_0,
1735   VEX_LEN_0F92_P_2,
1736   VEX_LEN_0F92_P_3,
1737   VEX_LEN_0F93_P_0,
1738   VEX_LEN_0F93_P_2,
1739   VEX_LEN_0F93_P_3,
1740   VEX_LEN_0F98_P_0,
1741   VEX_LEN_0F98_P_2,
1742   VEX_LEN_0F99_P_0,
1743   VEX_LEN_0F99_P_2,
1744   VEX_LEN_0FAE_R_2_M_0,
1745   VEX_LEN_0FAE_R_3_M_0,
1746   VEX_LEN_0FC4_P_2,
1747   VEX_LEN_0FC5_P_2,
1748   VEX_LEN_0FD6_P_2,
1749   VEX_LEN_0FF7_P_2,
1750   VEX_LEN_0F3816_P_2,
1751   VEX_LEN_0F3819_P_2,
1752   VEX_LEN_0F381A_P_2_M_0,
1753   VEX_LEN_0F3836_P_2,
1754   VEX_LEN_0F3841_P_2,
1755   VEX_LEN_0F385A_P_2_M_0,
1756   VEX_LEN_0F38DB_P_2,
1757   VEX_LEN_0F38F2_P_0,
1758   VEX_LEN_0F38F3_R_1_P_0,
1759   VEX_LEN_0F38F3_R_2_P_0,
1760   VEX_LEN_0F38F3_R_3_P_0,
1761   VEX_LEN_0F38F5_P_0,
1762   VEX_LEN_0F38F5_P_1,
1763   VEX_LEN_0F38F5_P_3,
1764   VEX_LEN_0F38F6_P_3,
1765   VEX_LEN_0F38F7_P_0,
1766   VEX_LEN_0F38F7_P_1,
1767   VEX_LEN_0F38F7_P_2,
1768   VEX_LEN_0F38F7_P_3,
1769   VEX_LEN_0F3A00_P_2,
1770   VEX_LEN_0F3A01_P_2,
1771   VEX_LEN_0F3A06_P_2,
1772   VEX_LEN_0F3A14_P_2,
1773   VEX_LEN_0F3A15_P_2,
1774   VEX_LEN_0F3A16_P_2,
1775   VEX_LEN_0F3A17_P_2,
1776   VEX_LEN_0F3A18_P_2,
1777   VEX_LEN_0F3A19_P_2,
1778   VEX_LEN_0F3A20_P_2,
1779   VEX_LEN_0F3A21_P_2,
1780   VEX_LEN_0F3A22_P_2,
1781   VEX_LEN_0F3A30_P_2,
1782   VEX_LEN_0F3A31_P_2,
1783   VEX_LEN_0F3A32_P_2,
1784   VEX_LEN_0F3A33_P_2,
1785   VEX_LEN_0F3A38_P_2,
1786   VEX_LEN_0F3A39_P_2,
1787   VEX_LEN_0F3A41_P_2,
1788   VEX_LEN_0F3A46_P_2,
1789   VEX_LEN_0F3A60_P_2,
1790   VEX_LEN_0F3A61_P_2,
1791   VEX_LEN_0F3A62_P_2,
1792   VEX_LEN_0F3A63_P_2,
1793   VEX_LEN_0F3ADF_P_2,
1794   VEX_LEN_0F3AF0_P_3,
1795   VEX_LEN_0FXOP_08_85,
1796   VEX_LEN_0FXOP_08_86,
1797   VEX_LEN_0FXOP_08_87,
1798   VEX_LEN_0FXOP_08_8E,
1799   VEX_LEN_0FXOP_08_8F,
1800   VEX_LEN_0FXOP_08_95,
1801   VEX_LEN_0FXOP_08_96,
1802   VEX_LEN_0FXOP_08_97,
1803   VEX_LEN_0FXOP_08_9E,
1804   VEX_LEN_0FXOP_08_9F,
1805   VEX_LEN_0FXOP_08_A3,
1806   VEX_LEN_0FXOP_08_A6,
1807   VEX_LEN_0FXOP_08_B6,
1808   VEX_LEN_0FXOP_08_C0,
1809   VEX_LEN_0FXOP_08_C1,
1810   VEX_LEN_0FXOP_08_C2,
1811   VEX_LEN_0FXOP_08_C3,
1812   VEX_LEN_0FXOP_08_CC,
1813   VEX_LEN_0FXOP_08_CD,
1814   VEX_LEN_0FXOP_08_CE,
1815   VEX_LEN_0FXOP_08_CF,
1816   VEX_LEN_0FXOP_08_EC,
1817   VEX_LEN_0FXOP_08_ED,
1818   VEX_LEN_0FXOP_08_EE,
1819   VEX_LEN_0FXOP_08_EF,
1820   VEX_LEN_0FXOP_09_01,
1821   VEX_LEN_0FXOP_09_02,
1822   VEX_LEN_0FXOP_09_12_M_1,
1823   VEX_LEN_0FXOP_09_82_W_0,
1824   VEX_LEN_0FXOP_09_83_W_0,
1825   VEX_LEN_0FXOP_09_90,
1826   VEX_LEN_0FXOP_09_91,
1827   VEX_LEN_0FXOP_09_92,
1828   VEX_LEN_0FXOP_09_93,
1829   VEX_LEN_0FXOP_09_94,
1830   VEX_LEN_0FXOP_09_95,
1831   VEX_LEN_0FXOP_09_96,
1832   VEX_LEN_0FXOP_09_97,
1833   VEX_LEN_0FXOP_09_98,
1834   VEX_LEN_0FXOP_09_99,
1835   VEX_LEN_0FXOP_09_9A,
1836   VEX_LEN_0FXOP_09_9B,
1837   VEX_LEN_0FXOP_09_C1,
1838   VEX_LEN_0FXOP_09_C2,
1839   VEX_LEN_0FXOP_09_C3,
1840   VEX_LEN_0FXOP_09_C6,
1841   VEX_LEN_0FXOP_09_C7,
1842   VEX_LEN_0FXOP_09_CB,
1843   VEX_LEN_0FXOP_09_D1,
1844   VEX_LEN_0FXOP_09_D2,
1845   VEX_LEN_0FXOP_09_D3,
1846   VEX_LEN_0FXOP_09_D6,
1847   VEX_LEN_0FXOP_09_D7,
1848   VEX_LEN_0FXOP_09_DB,
1849   VEX_LEN_0FXOP_09_E1,
1850   VEX_LEN_0FXOP_09_E2,
1851   VEX_LEN_0FXOP_09_E3,
1852   VEX_LEN_0FXOP_0A_12,
1853 };
1854
1855 enum
1856 {
1857   EVEX_LEN_0F6E_P_2 = 0,
1858   EVEX_LEN_0F7E_P_1,
1859   EVEX_LEN_0F7E_P_2,
1860   EVEX_LEN_0FC4_P_2,
1861   EVEX_LEN_0FC5_P_2,
1862   EVEX_LEN_0FD6_P_2,
1863   EVEX_LEN_0F3816_P_2,
1864   EVEX_LEN_0F3819_P_2_W_0,
1865   EVEX_LEN_0F3819_P_2_W_1,
1866   EVEX_LEN_0F381A_P_2_W_0_M_0,
1867   EVEX_LEN_0F381A_P_2_W_1_M_0,
1868   EVEX_LEN_0F381B_P_2_W_0_M_0,
1869   EVEX_LEN_0F381B_P_2_W_1_M_0,
1870   EVEX_LEN_0F3836_P_2,
1871   EVEX_LEN_0F385A_P_2_W_0_M_0,
1872   EVEX_LEN_0F385A_P_2_W_1_M_0,
1873   EVEX_LEN_0F385B_P_2_W_0_M_0,
1874   EVEX_LEN_0F385B_P_2_W_1_M_0,
1875   EVEX_LEN_0F38C6_REG_1_PREFIX_2,
1876   EVEX_LEN_0F38C6_REG_2_PREFIX_2,
1877   EVEX_LEN_0F38C6_REG_5_PREFIX_2,
1878   EVEX_LEN_0F38C6_REG_6_PREFIX_2,
1879   EVEX_LEN_0F38C7_R_1_P_2_W_0,
1880   EVEX_LEN_0F38C7_R_1_P_2_W_1,
1881   EVEX_LEN_0F38C7_R_2_P_2_W_0,
1882   EVEX_LEN_0F38C7_R_2_P_2_W_1,
1883   EVEX_LEN_0F38C7_R_5_P_2_W_0,
1884   EVEX_LEN_0F38C7_R_5_P_2_W_1,
1885   EVEX_LEN_0F38C7_R_6_P_2_W_0,
1886   EVEX_LEN_0F38C7_R_6_P_2_W_1,
1887   EVEX_LEN_0F3A00_P_2_W_1,
1888   EVEX_LEN_0F3A01_P_2_W_1,
1889   EVEX_LEN_0F3A14_P_2,
1890   EVEX_LEN_0F3A15_P_2,
1891   EVEX_LEN_0F3A16_P_2,
1892   EVEX_LEN_0F3A17_P_2,
1893   EVEX_LEN_0F3A18_P_2_W_0,
1894   EVEX_LEN_0F3A18_P_2_W_1,
1895   EVEX_LEN_0F3A19_P_2_W_0,
1896   EVEX_LEN_0F3A19_P_2_W_1,
1897   EVEX_LEN_0F3A1A_P_2_W_0,
1898   EVEX_LEN_0F3A1A_P_2_W_1,
1899   EVEX_LEN_0F3A1B_P_2_W_0,
1900   EVEX_LEN_0F3A1B_P_2_W_1,
1901   EVEX_LEN_0F3A20_P_2,
1902   EVEX_LEN_0F3A21_P_2_W_0,
1903   EVEX_LEN_0F3A22_P_2,
1904   EVEX_LEN_0F3A23_P_2_W_0,
1905   EVEX_LEN_0F3A23_P_2_W_1,
1906   EVEX_LEN_0F3A38_P_2_W_0,
1907   EVEX_LEN_0F3A38_P_2_W_1,
1908   EVEX_LEN_0F3A39_P_2_W_0,
1909   EVEX_LEN_0F3A39_P_2_W_1,
1910   EVEX_LEN_0F3A3A_P_2_W_0,
1911   EVEX_LEN_0F3A3A_P_2_W_1,
1912   EVEX_LEN_0F3A3B_P_2_W_0,
1913   EVEX_LEN_0F3A3B_P_2_W_1,
1914   EVEX_LEN_0F3A43_P_2_W_0,
1915   EVEX_LEN_0F3A43_P_2_W_1
1916 };
1917
1918 enum
1919 {
1920   VEX_W_0F41_P_0_LEN_1 = 0,
1921   VEX_W_0F41_P_2_LEN_1,
1922   VEX_W_0F42_P_0_LEN_1,
1923   VEX_W_0F42_P_2_LEN_1,
1924   VEX_W_0F44_P_0_LEN_0,
1925   VEX_W_0F44_P_2_LEN_0,
1926   VEX_W_0F45_P_0_LEN_1,
1927   VEX_W_0F45_P_2_LEN_1,
1928   VEX_W_0F46_P_0_LEN_1,
1929   VEX_W_0F46_P_2_LEN_1,
1930   VEX_W_0F47_P_0_LEN_1,
1931   VEX_W_0F47_P_2_LEN_1,
1932   VEX_W_0F4A_P_0_LEN_1,
1933   VEX_W_0F4A_P_2_LEN_1,
1934   VEX_W_0F4B_P_0_LEN_1,
1935   VEX_W_0F4B_P_2_LEN_1,
1936   VEX_W_0F90_P_0_LEN_0,
1937   VEX_W_0F90_P_2_LEN_0,
1938   VEX_W_0F91_P_0_LEN_0,
1939   VEX_W_0F91_P_2_LEN_0,
1940   VEX_W_0F92_P_0_LEN_0,
1941   VEX_W_0F92_P_2_LEN_0,
1942   VEX_W_0F93_P_0_LEN_0,
1943   VEX_W_0F93_P_2_LEN_0,
1944   VEX_W_0F98_P_0_LEN_0,
1945   VEX_W_0F98_P_2_LEN_0,
1946   VEX_W_0F99_P_0_LEN_0,
1947   VEX_W_0F99_P_2_LEN_0,
1948   VEX_W_0F380C_P_2,
1949   VEX_W_0F380D_P_2,
1950   VEX_W_0F380E_P_2,
1951   VEX_W_0F380F_P_2,
1952   VEX_W_0F3813_P_2,
1953   VEX_W_0F3816_P_2,
1954   VEX_W_0F3818_P_2,
1955   VEX_W_0F3819_P_2,
1956   VEX_W_0F381A_P_2_M_0,
1957   VEX_W_0F382C_P_2_M_0,
1958   VEX_W_0F382D_P_2_M_0,
1959   VEX_W_0F382E_P_2_M_0,
1960   VEX_W_0F382F_P_2_M_0,
1961   VEX_W_0F3836_P_2,
1962   VEX_W_0F3846_P_2,
1963   VEX_W_0F3858_P_2,
1964   VEX_W_0F3859_P_2,
1965   VEX_W_0F385A_P_2_M_0,
1966   VEX_W_0F3878_P_2,
1967   VEX_W_0F3879_P_2,
1968   VEX_W_0F38CF_P_2,
1969   VEX_W_0F3A00_P_2,
1970   VEX_W_0F3A01_P_2,
1971   VEX_W_0F3A02_P_2,
1972   VEX_W_0F3A04_P_2,
1973   VEX_W_0F3A05_P_2,
1974   VEX_W_0F3A06_P_2,
1975   VEX_W_0F3A18_P_2,
1976   VEX_W_0F3A19_P_2,
1977   VEX_W_0F3A1D_P_2,
1978   VEX_W_0F3A30_P_2_LEN_0,
1979   VEX_W_0F3A31_P_2_LEN_0,
1980   VEX_W_0F3A32_P_2_LEN_0,
1981   VEX_W_0F3A33_P_2_LEN_0,
1982   VEX_W_0F3A38_P_2,
1983   VEX_W_0F3A39_P_2,
1984   VEX_W_0F3A46_P_2,
1985   VEX_W_0F3A4A_P_2,
1986   VEX_W_0F3A4B_P_2,
1987   VEX_W_0F3A4C_P_2,
1988   VEX_W_0F3ACE_P_2,
1989   VEX_W_0F3ACF_P_2,
1990
1991   VEX_W_0FXOP_08_85_L_0,
1992   VEX_W_0FXOP_08_86_L_0,
1993   VEX_W_0FXOP_08_87_L_0,
1994   VEX_W_0FXOP_08_8E_L_0,
1995   VEX_W_0FXOP_08_8F_L_0,
1996   VEX_W_0FXOP_08_95_L_0,
1997   VEX_W_0FXOP_08_96_L_0,
1998   VEX_W_0FXOP_08_97_L_0,
1999   VEX_W_0FXOP_08_9E_L_0,
2000   VEX_W_0FXOP_08_9F_L_0,
2001   VEX_W_0FXOP_08_A6_L_0,
2002   VEX_W_0FXOP_08_B6_L_0,
2003   VEX_W_0FXOP_08_C0_L_0,
2004   VEX_W_0FXOP_08_C1_L_0,
2005   VEX_W_0FXOP_08_C2_L_0,
2006   VEX_W_0FXOP_08_C3_L_0,
2007   VEX_W_0FXOP_08_CC_L_0,
2008   VEX_W_0FXOP_08_CD_L_0,
2009   VEX_W_0FXOP_08_CE_L_0,
2010   VEX_W_0FXOP_08_CF_L_0,
2011   VEX_W_0FXOP_08_EC_L_0,
2012   VEX_W_0FXOP_08_ED_L_0,
2013   VEX_W_0FXOP_08_EE_L_0,
2014   VEX_W_0FXOP_08_EF_L_0,
2015
2016   VEX_W_0FXOP_09_80,
2017   VEX_W_0FXOP_09_81,
2018   VEX_W_0FXOP_09_82,
2019   VEX_W_0FXOP_09_83,
2020   VEX_W_0FXOP_09_C1_L_0,
2021   VEX_W_0FXOP_09_C2_L_0,
2022   VEX_W_0FXOP_09_C3_L_0,
2023   VEX_W_0FXOP_09_C6_L_0,
2024   VEX_W_0FXOP_09_C7_L_0,
2025   VEX_W_0FXOP_09_CB_L_0,
2026   VEX_W_0FXOP_09_D1_L_0,
2027   VEX_W_0FXOP_09_D2_L_0,
2028   VEX_W_0FXOP_09_D3_L_0,
2029   VEX_W_0FXOP_09_D6_L_0,
2030   VEX_W_0FXOP_09_D7_L_0,
2031   VEX_W_0FXOP_09_DB_L_0,
2032   VEX_W_0FXOP_09_E1_L_0,
2033   VEX_W_0FXOP_09_E2_L_0,
2034   VEX_W_0FXOP_09_E3_L_0,
2035
2036   EVEX_W_0F10_P_1,
2037   EVEX_W_0F10_P_3,
2038   EVEX_W_0F11_P_1,
2039   EVEX_W_0F11_P_3,
2040   EVEX_W_0F12_P_0_M_1,
2041   EVEX_W_0F12_P_1,
2042   EVEX_W_0F12_P_3,
2043   EVEX_W_0F16_P_0_M_1,
2044   EVEX_W_0F16_P_1,
2045   EVEX_W_0F2A_P_3,
2046   EVEX_W_0F51_P_1,
2047   EVEX_W_0F51_P_3,
2048   EVEX_W_0F58_P_1,
2049   EVEX_W_0F58_P_3,
2050   EVEX_W_0F59_P_1,
2051   EVEX_W_0F59_P_3,
2052   EVEX_W_0F5A_P_0,
2053   EVEX_W_0F5A_P_1,
2054   EVEX_W_0F5A_P_2,
2055   EVEX_W_0F5A_P_3,
2056   EVEX_W_0F5B_P_0,
2057   EVEX_W_0F5B_P_1,
2058   EVEX_W_0F5B_P_2,
2059   EVEX_W_0F5C_P_1,
2060   EVEX_W_0F5C_P_3,
2061   EVEX_W_0F5D_P_1,
2062   EVEX_W_0F5D_P_3,
2063   EVEX_W_0F5E_P_1,
2064   EVEX_W_0F5E_P_3,
2065   EVEX_W_0F5F_P_1,
2066   EVEX_W_0F5F_P_3,
2067   EVEX_W_0F62,
2068   EVEX_W_0F66_P_2,
2069   EVEX_W_0F6A,
2070   EVEX_W_0F6B,
2071   EVEX_W_0F6C,
2072   EVEX_W_0F6D,
2073   EVEX_W_0F6F_P_1,
2074   EVEX_W_0F6F_P_2,
2075   EVEX_W_0F6F_P_3,
2076   EVEX_W_0F70_P_2,
2077   EVEX_W_0F72_R_2_P_2,
2078   EVEX_W_0F72_R_6_P_2,
2079   EVEX_W_0F73_R_2_P_2,
2080   EVEX_W_0F73_R_6_P_2,
2081   EVEX_W_0F76_P_2,
2082   EVEX_W_0F78_P_0,
2083   EVEX_W_0F78_P_2,
2084   EVEX_W_0F79_P_0,
2085   EVEX_W_0F79_P_2,
2086   EVEX_W_0F7A_P_1,
2087   EVEX_W_0F7A_P_2,
2088   EVEX_W_0F7A_P_3,
2089   EVEX_W_0F7B_P_2,
2090   EVEX_W_0F7B_P_3,
2091   EVEX_W_0F7E_P_1,
2092   EVEX_W_0F7F_P_1,
2093   EVEX_W_0F7F_P_2,
2094   EVEX_W_0F7F_P_3,
2095   EVEX_W_0FC2_P_1,
2096   EVEX_W_0FC2_P_3,
2097   EVEX_W_0FD2,
2098   EVEX_W_0FD3,
2099   EVEX_W_0FD4,
2100   EVEX_W_0FD6_P_2,
2101   EVEX_W_0FE6_P_1,
2102   EVEX_W_0FE6_P_2,
2103   EVEX_W_0FE6_P_3,
2104   EVEX_W_0FE7_P_2,
2105   EVEX_W_0FF2,
2106   EVEX_W_0FF3,
2107   EVEX_W_0FF4,
2108   EVEX_W_0FFA,
2109   EVEX_W_0FFB,
2110   EVEX_W_0FFE,
2111   EVEX_W_0F380D_P_2,
2112   EVEX_W_0F3810_P_1,
2113   EVEX_W_0F3810_P_2,
2114   EVEX_W_0F3811_P_1,
2115   EVEX_W_0F3811_P_2,
2116   EVEX_W_0F3812_P_1,
2117   EVEX_W_0F3812_P_2,
2118   EVEX_W_0F3813_P_1,
2119   EVEX_W_0F3813_P_2,
2120   EVEX_W_0F3814_P_1,
2121   EVEX_W_0F3815_P_1,
2122   EVEX_W_0F3819_P_2,
2123   EVEX_W_0F381A_P_2,
2124   EVEX_W_0F381B_P_2,
2125   EVEX_W_0F381E_P_2,
2126   EVEX_W_0F381F_P_2,
2127   EVEX_W_0F3820_P_1,
2128   EVEX_W_0F3821_P_1,
2129   EVEX_W_0F3822_P_1,
2130   EVEX_W_0F3823_P_1,
2131   EVEX_W_0F3824_P_1,
2132   EVEX_W_0F3825_P_1,
2133   EVEX_W_0F3825_P_2,
2134   EVEX_W_0F3828_P_2,
2135   EVEX_W_0F3829_P_2,
2136   EVEX_W_0F382A_P_1,
2137   EVEX_W_0F382A_P_2,
2138   EVEX_W_0F382B,
2139   EVEX_W_0F3830_P_1,
2140   EVEX_W_0F3831_P_1,
2141   EVEX_W_0F3832_P_1,
2142   EVEX_W_0F3833_P_1,
2143   EVEX_W_0F3834_P_1,
2144   EVEX_W_0F3835_P_1,
2145   EVEX_W_0F3835_P_2,
2146   EVEX_W_0F3837_P_2,
2147   EVEX_W_0F383A_P_1,
2148   EVEX_W_0F3852_P_1,
2149   EVEX_W_0F3859_P_2,
2150   EVEX_W_0F385A_P_2,
2151   EVEX_W_0F385B_P_2,
2152   EVEX_W_0F3862_P_2,
2153   EVEX_W_0F3863_P_2,
2154   EVEX_W_0F3870_P_2,
2155   EVEX_W_0F3872_P_1,
2156   EVEX_W_0F3872_P_2,
2157   EVEX_W_0F3872_P_3,
2158   EVEX_W_0F387A_P_2,
2159   EVEX_W_0F387B_P_2,
2160   EVEX_W_0F3883_P_2,
2161   EVEX_W_0F3891_P_2,
2162   EVEX_W_0F3893_P_2,
2163   EVEX_W_0F38A1_P_2,
2164   EVEX_W_0F38A3_P_2,
2165   EVEX_W_0F38C7_R_1_P_2,
2166   EVEX_W_0F38C7_R_2_P_2,
2167   EVEX_W_0F38C7_R_5_P_2,
2168   EVEX_W_0F38C7_R_6_P_2,
2169
2170   EVEX_W_0F3A00_P_2,
2171   EVEX_W_0F3A01_P_2,
2172   EVEX_W_0F3A05_P_2,
2173   EVEX_W_0F3A08_P_2,
2174   EVEX_W_0F3A09_P_2,
2175   EVEX_W_0F3A0A_P_2,
2176   EVEX_W_0F3A0B_P_2,
2177   EVEX_W_0F3A18_P_2,
2178   EVEX_W_0F3A19_P_2,
2179   EVEX_W_0F3A1A_P_2,
2180   EVEX_W_0F3A1B_P_2,
2181   EVEX_W_0F3A21_P_2,
2182   EVEX_W_0F3A23_P_2,
2183   EVEX_W_0F3A38_P_2,
2184   EVEX_W_0F3A39_P_2,
2185   EVEX_W_0F3A3A_P_2,
2186   EVEX_W_0F3A3B_P_2,
2187   EVEX_W_0F3A42_P_2,
2188   EVEX_W_0F3A43_P_2,
2189   EVEX_W_0F3A70_P_2,
2190   EVEX_W_0F3A72_P_2,
2191 };
2192
2193 typedef void (*op_rtn) (int bytemode, int sizeflag);
2194
2195 struct dis386 {
2196   const char *name;
2197   struct
2198     {
2199       op_rtn rtn;
2200       int bytemode;
2201     } op[MAX_OPERANDS];
2202   unsigned int prefix_requirement;
2203 };
2204
2205 /* Upper case letters in the instruction names here are macros.
2206    'A' => print 'b' if no register operands or suffix_always is true
2207    'B' => print 'b' if suffix_always is true
2208    'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2209           size prefix
2210    'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2211           suffix_always is true
2212    'E' => print 'e' if 32-bit form of jcxz
2213    'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2214    'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2215    'H' => print ",pt" or ",pn" branch hint
2216    'I' unused.
2217    'J' unused.
2218    'K' => print 'd' or 'q' if rex prefix is present.
2219    'L' => print 'l' if suffix_always is true
2220    'M' => print 'r' if intel_mnemonic is false.
2221    'N' => print 'n' if instruction has no wait "prefix"
2222    'O' => print 'd' or 'o' (or 'q' in Intel mode)
2223    'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2224           or suffix_always is true.  print 'q' if rex prefix is present.
2225    'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2226           is true
2227    'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2228    'S' => print 'w', 'l' or 'q' if suffix_always is true
2229    'T' => print 'q' in 64bit mode if instruction has no operand size
2230           prefix and behave as 'P' otherwise
2231    'U' => print 'q' in 64bit mode if instruction has no operand size
2232           prefix and behave as 'Q' otherwise
2233    'V' => print 'q' in 64bit mode if instruction has no operand size
2234           prefix and behave as 'S' otherwise
2235    'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2236    'X' => print 's', 'd' depending on data16 prefix (for XMM)
2237    'Y' unused.
2238    'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2239    '!' => change condition from true to false or from false to true.
2240    '%' => add 1 upper case letter to the macro.
2241    '^' => print 'w', 'l', or 'q' (Intel64 ISA only) depending on operand size
2242           prefix or suffix_always is true (lcall/ljmp).
2243    '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending
2244           on operand size prefix.
2245    '&' => print 'q' in 64bit mode for Intel64 ISA or if instruction
2246           has no operand size prefix for AMD64 ISA, behave as 'P'
2247           otherwise
2248
2249    2 upper case letter macros:
2250    "XY" => print 'x' or 'y' if suffix_always is true or no register
2251            operands and no broadcast.
2252    "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
2253            register operands and no broadcast.
2254    "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2255    "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory
2256            operand or no operand at all in 64bit mode, or if suffix_always
2257            is true.
2258    "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2259    "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2260    "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2261    "LW" => print 'd', 'q' depending on the VEX.W bit
2262    "BW" => print 'b' or 'w' depending on the EVEX.W bit
2263    "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
2264            an operand size prefix, or suffix_always is true.  print
2265            'q' if rex prefix is present.
2266
2267    Many of the above letters print nothing in Intel mode.  See "putop"
2268    for the details.
2269
2270    Braces '{' and '}', and vertical bars '|', indicate alternative
2271    mnemonic strings for AT&T and Intel.  */
2272
2273 static const struct dis386 dis386[] = {
2274   /* 00 */
2275   { "addB",             { Ebh1, Gb }, 0 },
2276   { "addS",             { Evh1, Gv }, 0 },
2277   { "addB",             { Gb, EbS }, 0 },
2278   { "addS",             { Gv, EvS }, 0 },
2279   { "addB",             { AL, Ib }, 0 },
2280   { "addS",             { eAX, Iv }, 0 },
2281   { X86_64_TABLE (X86_64_06) },
2282   { X86_64_TABLE (X86_64_07) },
2283   /* 08 */
2284   { "orB",              { Ebh1, Gb }, 0 },
2285   { "orS",              { Evh1, Gv }, 0 },
2286   { "orB",              { Gb, EbS }, 0 },
2287   { "orS",              { Gv, EvS }, 0 },
2288   { "orB",              { AL, Ib }, 0 },
2289   { "orS",              { eAX, Iv }, 0 },
2290   { X86_64_TABLE (X86_64_0E) },
2291   { Bad_Opcode },       /* 0x0f extended opcode escape */
2292   /* 10 */
2293   { "adcB",             { Ebh1, Gb }, 0 },
2294   { "adcS",             { Evh1, Gv }, 0 },
2295   { "adcB",             { Gb, EbS }, 0 },
2296   { "adcS",             { Gv, EvS }, 0 },
2297   { "adcB",             { AL, Ib }, 0 },
2298   { "adcS",             { eAX, Iv }, 0 },
2299   { X86_64_TABLE (X86_64_16) },
2300   { X86_64_TABLE (X86_64_17) },
2301   /* 18 */
2302   { "sbbB",             { Ebh1, Gb }, 0 },
2303   { "sbbS",             { Evh1, Gv }, 0 },
2304   { "sbbB",             { Gb, EbS }, 0 },
2305   { "sbbS",             { Gv, EvS }, 0 },
2306   { "sbbB",             { AL, Ib }, 0 },
2307   { "sbbS",             { eAX, Iv }, 0 },
2308   { X86_64_TABLE (X86_64_1E) },
2309   { X86_64_TABLE (X86_64_1F) },
2310   /* 20 */
2311   { "andB",             { Ebh1, Gb }, 0 },
2312   { "andS",             { Evh1, Gv }, 0 },
2313   { "andB",             { Gb, EbS }, 0 },
2314   { "andS",             { Gv, EvS }, 0 },
2315   { "andB",             { AL, Ib }, 0 },
2316   { "andS",             { eAX, Iv }, 0 },
2317   { Bad_Opcode },       /* SEG ES prefix */
2318   { X86_64_TABLE (X86_64_27) },
2319   /* 28 */
2320   { "subB",             { Ebh1, Gb }, 0 },
2321   { "subS",             { Evh1, Gv }, 0 },
2322   { "subB",             { Gb, EbS }, 0 },
2323   { "subS",             { Gv, EvS }, 0 },
2324   { "subB",             { AL, Ib }, 0 },
2325   { "subS",             { eAX, Iv }, 0 },
2326   { Bad_Opcode },       /* SEG CS prefix */
2327   { X86_64_TABLE (X86_64_2F) },
2328   /* 30 */
2329   { "xorB",             { Ebh1, Gb }, 0 },
2330   { "xorS",             { Evh1, Gv }, 0 },
2331   { "xorB",             { Gb, EbS }, 0 },
2332   { "xorS",             { Gv, EvS }, 0 },
2333   { "xorB",             { AL, Ib }, 0 },
2334   { "xorS",             { eAX, Iv }, 0 },
2335   { Bad_Opcode },       /* SEG SS prefix */
2336   { X86_64_TABLE (X86_64_37) },
2337   /* 38 */
2338   { "cmpB",             { Eb, Gb }, 0 },
2339   { "cmpS",             { Ev, Gv }, 0 },
2340   { "cmpB",             { Gb, EbS }, 0 },
2341   { "cmpS",             { Gv, EvS }, 0 },
2342   { "cmpB",             { AL, Ib }, 0 },
2343   { "cmpS",             { eAX, Iv }, 0 },
2344   { Bad_Opcode },       /* SEG DS prefix */
2345   { X86_64_TABLE (X86_64_3F) },
2346   /* 40 */
2347   { "inc{S|}",          { RMeAX }, 0 },
2348   { "inc{S|}",          { RMeCX }, 0 },
2349   { "inc{S|}",          { RMeDX }, 0 },
2350   { "inc{S|}",          { RMeBX }, 0 },
2351   { "inc{S|}",          { RMeSP }, 0 },
2352   { "inc{S|}",          { RMeBP }, 0 },
2353   { "inc{S|}",          { RMeSI }, 0 },
2354   { "inc{S|}",          { RMeDI }, 0 },
2355   /* 48 */
2356   { "dec{S|}",          { RMeAX }, 0 },
2357   { "dec{S|}",          { RMeCX }, 0 },
2358   { "dec{S|}",          { RMeDX }, 0 },
2359   { "dec{S|}",          { RMeBX }, 0 },
2360   { "dec{S|}",          { RMeSP }, 0 },
2361   { "dec{S|}",          { RMeBP }, 0 },
2362   { "dec{S|}",          { RMeSI }, 0 },
2363   { "dec{S|}",          { RMeDI }, 0 },
2364   /* 50 */
2365   { "pushV",            { RMrAX }, 0 },
2366   { "pushV",            { RMrCX }, 0 },
2367   { "pushV",            { RMrDX }, 0 },
2368   { "pushV",            { RMrBX }, 0 },
2369   { "pushV",            { RMrSP }, 0 },
2370   { "pushV",            { RMrBP }, 0 },
2371   { "pushV",            { RMrSI }, 0 },
2372   { "pushV",            { RMrDI }, 0 },
2373   /* 58 */
2374   { "popV",             { RMrAX }, 0 },
2375   { "popV",             { RMrCX }, 0 },
2376   { "popV",             { RMrDX }, 0 },
2377   { "popV",             { RMrBX }, 0 },
2378   { "popV",             { RMrSP }, 0 },
2379   { "popV",             { RMrBP }, 0 },
2380   { "popV",             { RMrSI }, 0 },
2381   { "popV",             { RMrDI }, 0 },
2382   /* 60 */
2383   { X86_64_TABLE (X86_64_60) },
2384   { X86_64_TABLE (X86_64_61) },
2385   { X86_64_TABLE (X86_64_62) },
2386   { X86_64_TABLE (X86_64_63) },
2387   { Bad_Opcode },       /* seg fs */
2388   { Bad_Opcode },       /* seg gs */
2389   { Bad_Opcode },       /* op size prefix */
2390   { Bad_Opcode },       /* adr size prefix */
2391   /* 68 */
2392   { "pushT",            { sIv }, 0 },
2393   { "imulS",            { Gv, Ev, Iv }, 0 },
2394   { "pushT",            { sIbT }, 0 },
2395   { "imulS",            { Gv, Ev, sIb }, 0 },
2396   { "ins{b|}",          { Ybr, indirDX }, 0 },
2397   { X86_64_TABLE (X86_64_6D) },
2398   { "outs{b|}",         { indirDXr, Xb }, 0 },
2399   { X86_64_TABLE (X86_64_6F) },
2400   /* 70 */
2401   { "joH",              { Jb, BND, cond_jump_flag }, 0 },
2402   { "jnoH",             { Jb, BND, cond_jump_flag }, 0 },
2403   { "jbH",              { Jb, BND, cond_jump_flag }, 0 },
2404   { "jaeH",             { Jb, BND, cond_jump_flag }, 0 },
2405   { "jeH",              { Jb, BND, cond_jump_flag }, 0 },
2406   { "jneH",             { Jb, BND, cond_jump_flag }, 0 },
2407   { "jbeH",             { Jb, BND, cond_jump_flag }, 0 },
2408   { "jaH",              { Jb, BND, cond_jump_flag }, 0 },
2409   /* 78 */
2410   { "jsH",              { Jb, BND, cond_jump_flag }, 0 },
2411   { "jnsH",             { Jb, BND, cond_jump_flag }, 0 },
2412   { "jpH",              { Jb, BND, cond_jump_flag }, 0 },
2413   { "jnpH",             { Jb, BND, cond_jump_flag }, 0 },
2414   { "jlH",              { Jb, BND, cond_jump_flag }, 0 },
2415   { "jgeH",             { Jb, BND, cond_jump_flag }, 0 },
2416   { "jleH",             { Jb, BND, cond_jump_flag }, 0 },
2417   { "jgH",              { Jb, BND, cond_jump_flag }, 0 },
2418   /* 80 */
2419   { REG_TABLE (REG_80) },
2420   { REG_TABLE (REG_81) },
2421   { X86_64_TABLE (X86_64_82) },
2422   { REG_TABLE (REG_83) },
2423   { "testB",            { Eb, Gb }, 0 },
2424   { "testS",            { Ev, Gv }, 0 },
2425   { "xchgB",            { Ebh2, Gb }, 0 },
2426   { "xchgS",            { Evh2, Gv }, 0 },
2427   /* 88 */
2428   { "movB",             { Ebh3, Gb }, 0 },
2429   { "movS",             { Evh3, Gv }, 0 },
2430   { "movB",             { Gb, EbS }, 0 },
2431   { "movS",             { Gv, EvS }, 0 },
2432   { "movD",             { Sv, Sw }, 0 },
2433   { MOD_TABLE (MOD_8D) },
2434   { "movD",             { Sw, Sv }, 0 },
2435   { REG_TABLE (REG_8F) },
2436   /* 90 */
2437   { PREFIX_TABLE (PREFIX_90) },
2438   { "xchgS",            { RMeCX, eAX }, 0 },
2439   { "xchgS",            { RMeDX, eAX }, 0 },
2440   { "xchgS",            { RMeBX, eAX }, 0 },
2441   { "xchgS",            { RMeSP, eAX }, 0 },
2442   { "xchgS",            { RMeBP, eAX }, 0 },
2443   { "xchgS",            { RMeSI, eAX }, 0 },
2444   { "xchgS",            { RMeDI, eAX }, 0 },
2445   /* 98 */
2446   { "cW{t|}R",          { XX }, 0 },
2447   { "cR{t|}O",          { XX }, 0 },
2448   { X86_64_TABLE (X86_64_9A) },
2449   { Bad_Opcode },       /* fwait */
2450   { "pushfT",           { XX }, 0 },
2451   { "popfT",            { XX }, 0 },
2452   { "sahf",             { XX }, 0 },
2453   { "lahf",             { XX }, 0 },
2454   /* a0 */
2455   { "mov%LB",           { AL, Ob }, 0 },
2456   { "mov%LS",           { eAX, Ov }, 0 },
2457   { "mov%LB",           { Ob, AL }, 0 },
2458   { "mov%LS",           { Ov, eAX }, 0 },
2459   { "movs{b|}",         { Ybr, Xb }, 0 },
2460   { "movs{R|}",         { Yvr, Xv }, 0 },
2461   { "cmps{b|}",         { Xb, Yb }, 0 },
2462   { "cmps{R|}",         { Xv, Yv }, 0 },
2463   /* a8 */
2464   { "testB",            { AL, Ib }, 0 },
2465   { "testS",            { eAX, Iv }, 0 },
2466   { "stosB",            { Ybr, AL }, 0 },
2467   { "stosS",            { Yvr, eAX }, 0 },
2468   { "lodsB",            { ALr, Xb }, 0 },
2469   { "lodsS",            { eAXr, Xv }, 0 },
2470   { "scasB",            { AL, Yb }, 0 },
2471   { "scasS",            { eAX, Yv }, 0 },
2472   /* b0 */
2473   { "movB",             { RMAL, Ib }, 0 },
2474   { "movB",             { RMCL, Ib }, 0 },
2475   { "movB",             { RMDL, Ib }, 0 },
2476   { "movB",             { RMBL, Ib }, 0 },
2477   { "movB",             { RMAH, Ib }, 0 },
2478   { "movB",             { RMCH, Ib }, 0 },
2479   { "movB",             { RMDH, Ib }, 0 },
2480   { "movB",             { RMBH, Ib }, 0 },
2481   /* b8 */
2482   { "mov%LV",           { RMeAX, Iv64 }, 0 },
2483   { "mov%LV",           { RMeCX, Iv64 }, 0 },
2484   { "mov%LV",           { RMeDX, Iv64 }, 0 },
2485   { "mov%LV",           { RMeBX, Iv64 }, 0 },
2486   { "mov%LV",           { RMeSP, Iv64 }, 0 },
2487   { "mov%LV",           { RMeBP, Iv64 }, 0 },
2488   { "mov%LV",           { RMeSI, Iv64 }, 0 },
2489   { "mov%LV",           { RMeDI, Iv64 }, 0 },
2490   /* c0 */
2491   { REG_TABLE (REG_C0) },
2492   { REG_TABLE (REG_C1) },
2493   { X86_64_TABLE (X86_64_C2) },
2494   { X86_64_TABLE (X86_64_C3) },
2495   { X86_64_TABLE (X86_64_C4) },
2496   { X86_64_TABLE (X86_64_C5) },
2497   { REG_TABLE (REG_C6) },
2498   { REG_TABLE (REG_C7) },
2499   /* c8 */
2500   { "enterT",           { Iw, Ib }, 0 },
2501   { "leaveT",           { XX }, 0 },
2502   { "{l|}ret{|f}P",     { Iw }, 0 },
2503   { "{l|}ret{|f}P",     { XX }, 0 },
2504   { "int3",             { XX }, 0 },
2505   { "int",              { Ib }, 0 },
2506   { X86_64_TABLE (X86_64_CE) },
2507   { "iret%LP",          { XX }, 0 },
2508   /* d0 */
2509   { REG_TABLE (REG_D0) },
2510   { REG_TABLE (REG_D1) },
2511   { REG_TABLE (REG_D2) },
2512   { REG_TABLE (REG_D3) },
2513   { X86_64_TABLE (X86_64_D4) },
2514   { X86_64_TABLE (X86_64_D5) },
2515   { Bad_Opcode },
2516   { "xlat",             { DSBX }, 0 },
2517   /* d8 */
2518   { FLOAT },
2519   { FLOAT },
2520   { FLOAT },
2521   { FLOAT },
2522   { FLOAT },
2523   { FLOAT },
2524   { FLOAT },
2525   { FLOAT },
2526   /* e0 */
2527   { "loopneFH",         { Jb, XX, loop_jcxz_flag }, 0 },
2528   { "loopeFH",          { Jb, XX, loop_jcxz_flag }, 0 },
2529   { "loopFH",           { Jb, XX, loop_jcxz_flag }, 0 },
2530   { "jEcxzH",           { Jb, XX, loop_jcxz_flag }, 0 },
2531   { "inB",              { AL, Ib }, 0 },
2532   { "inG",              { zAX, Ib }, 0 },
2533   { "outB",             { Ib, AL }, 0 },
2534   { "outG",             { Ib, zAX }, 0 },
2535   /* e8 */
2536   { X86_64_TABLE (X86_64_E8) },
2537   { X86_64_TABLE (X86_64_E9) },
2538   { X86_64_TABLE (X86_64_EA) },
2539   { "jmp",              { Jb, BND }, 0 },
2540   { "inB",              { AL, indirDX }, 0 },
2541   { "inG",              { zAX, indirDX }, 0 },
2542   { "outB",             { indirDX, AL }, 0 },
2543   { "outG",             { indirDX, zAX }, 0 },
2544   /* f0 */
2545   { Bad_Opcode },       /* lock prefix */
2546   { "icebp",            { XX }, 0 },
2547   { Bad_Opcode },       /* repne */
2548   { Bad_Opcode },       /* repz */
2549   { "hlt",              { XX }, 0 },
2550   { "cmc",              { XX }, 0 },
2551   { REG_TABLE (REG_F6) },
2552   { REG_TABLE (REG_F7) },
2553   /* f8 */
2554   { "clc",              { XX }, 0 },
2555   { "stc",              { XX }, 0 },
2556   { "cli",              { XX }, 0 },
2557   { "sti",              { XX }, 0 },
2558   { "cld",              { XX }, 0 },
2559   { "std",              { XX }, 0 },
2560   { REG_TABLE (REG_FE) },
2561   { REG_TABLE (REG_FF) },
2562 };
2563
2564 static const struct dis386 dis386_twobyte[] = {
2565   /* 00 */
2566   { REG_TABLE (REG_0F00 ) },
2567   { REG_TABLE (REG_0F01 ) },
2568   { "larS",             { Gv, Ew }, 0 },
2569   { "lslS",             { Gv, Ew }, 0 },
2570   { Bad_Opcode },
2571   { "syscall",          { XX }, 0 },
2572   { "clts",             { XX }, 0 },
2573   { "sysret%LQ",                { XX }, 0 },
2574   /* 08 */
2575   { "invd",             { XX }, 0 },
2576   { PREFIX_TABLE (PREFIX_0F09) },
2577   { Bad_Opcode },
2578   { "ud2",              { XX }, 0 },
2579   { Bad_Opcode },
2580   { REG_TABLE (REG_0F0D) },
2581   { "femms",            { XX }, 0 },
2582   { "",                 { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix.  */
2583   /* 10 */
2584   { PREFIX_TABLE (PREFIX_0F10) },
2585   { PREFIX_TABLE (PREFIX_0F11) },
2586   { PREFIX_TABLE (PREFIX_0F12) },
2587   { MOD_TABLE (MOD_0F13) },
2588   { "unpcklpX",         { XM, EXx }, PREFIX_OPCODE },
2589   { "unpckhpX",         { XM, EXx }, PREFIX_OPCODE },
2590   { PREFIX_TABLE (PREFIX_0F16) },
2591   { MOD_TABLE (MOD_0F17) },
2592   /* 18 */
2593   { REG_TABLE (REG_0F18) },
2594   { "nopQ",             { Ev }, 0 },
2595   { PREFIX_TABLE (PREFIX_0F1A) },
2596   { PREFIX_TABLE (PREFIX_0F1B) },
2597   { PREFIX_TABLE (PREFIX_0F1C) },
2598   { "nopQ",             { Ev }, 0 },
2599   { PREFIX_TABLE (PREFIX_0F1E) },
2600   { "nopQ",             { Ev }, 0 },
2601   /* 20 */
2602   { "movZ",             { Rm, Cm }, 0 },
2603   { "movZ",             { Rm, Dm }, 0 },
2604   { "movZ",             { Cm, Rm }, 0 },
2605   { "movZ",             { Dm, Rm }, 0 },
2606   { MOD_TABLE (MOD_0F24) },
2607   { Bad_Opcode },
2608   { MOD_TABLE (MOD_0F26) },
2609   { Bad_Opcode },
2610   /* 28 */
2611   { "movapX",           { XM, EXx }, PREFIX_OPCODE },
2612   { "movapX",           { EXxS, XM }, PREFIX_OPCODE },
2613   { PREFIX_TABLE (PREFIX_0F2A) },
2614   { PREFIX_TABLE (PREFIX_0F2B) },
2615   { PREFIX_TABLE (PREFIX_0F2C) },
2616   { PREFIX_TABLE (PREFIX_0F2D) },
2617   { PREFIX_TABLE (PREFIX_0F2E) },
2618   { PREFIX_TABLE (PREFIX_0F2F) },
2619   /* 30 */
2620   { "wrmsr",            { XX }, 0 },
2621   { "rdtsc",            { XX }, 0 },
2622   { "rdmsr",            { XX }, 0 },
2623   { "rdpmc",            { XX }, 0 },
2624   { "sysenter",         { SEP }, 0 },
2625   { "sysexit",          { SEP }, 0 },
2626   { Bad_Opcode },
2627   { "getsec",           { XX }, 0 },
2628   /* 38 */
2629   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) },
2630   { Bad_Opcode },
2631   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) },
2632   { Bad_Opcode },
2633   { Bad_Opcode },
2634   { Bad_Opcode },
2635   { Bad_Opcode },
2636   { Bad_Opcode },
2637   /* 40 */
2638   { "cmovoS",           { Gv, Ev }, 0 },
2639   { "cmovnoS",          { Gv, Ev }, 0 },
2640   { "cmovbS",           { Gv, Ev }, 0 },
2641   { "cmovaeS",          { Gv, Ev }, 0 },
2642   { "cmoveS",           { Gv, Ev }, 0 },
2643   { "cmovneS",          { Gv, Ev }, 0 },
2644   { "cmovbeS",          { Gv, Ev }, 0 },
2645   { "cmovaS",           { Gv, Ev }, 0 },
2646   /* 48 */
2647   { "cmovsS",           { Gv, Ev }, 0 },
2648   { "cmovnsS",          { Gv, Ev }, 0 },
2649   { "cmovpS",           { Gv, Ev }, 0 },
2650   { "cmovnpS",          { Gv, Ev }, 0 },
2651   { "cmovlS",           { Gv, Ev }, 0 },
2652   { "cmovgeS",          { Gv, Ev }, 0 },
2653   { "cmovleS",          { Gv, Ev }, 0 },
2654   { "cmovgS",           { Gv, Ev }, 0 },
2655   /* 50 */
2656   { MOD_TABLE (MOD_0F50) },
2657   { PREFIX_TABLE (PREFIX_0F51) },
2658   { PREFIX_TABLE (PREFIX_0F52) },
2659   { PREFIX_TABLE (PREFIX_0F53) },
2660   { "andpX",            { XM, EXx }, PREFIX_OPCODE },
2661   { "andnpX",           { XM, EXx }, PREFIX_OPCODE },
2662   { "orpX",             { XM, EXx }, PREFIX_OPCODE },
2663   { "xorpX",            { XM, EXx }, PREFIX_OPCODE },
2664   /* 58 */
2665   { PREFIX_TABLE (PREFIX_0F58) },
2666   { PREFIX_TABLE (PREFIX_0F59) },
2667   { PREFIX_TABLE (PREFIX_0F5A) },
2668   { PREFIX_TABLE (PREFIX_0F5B) },
2669   { PREFIX_TABLE (PREFIX_0F5C) },
2670   { PREFIX_TABLE (PREFIX_0F5D) },
2671   { PREFIX_TABLE (PREFIX_0F5E) },
2672   { PREFIX_TABLE (PREFIX_0F5F) },
2673   /* 60 */
2674   { PREFIX_TABLE (PREFIX_0F60) },
2675   { PREFIX_TABLE (PREFIX_0F61) },
2676   { PREFIX_TABLE (PREFIX_0F62) },
2677   { "packsswb",         { MX, EM }, PREFIX_OPCODE },
2678   { "pcmpgtb",          { MX, EM }, PREFIX_OPCODE },
2679   { "pcmpgtw",          { MX, EM }, PREFIX_OPCODE },
2680   { "pcmpgtd",          { MX, EM }, PREFIX_OPCODE },
2681   { "packuswb",         { MX, EM }, PREFIX_OPCODE },
2682   /* 68 */
2683   { "punpckhbw",        { MX, EM }, PREFIX_OPCODE },
2684   { "punpckhwd",        { MX, EM }, PREFIX_OPCODE },
2685   { "punpckhdq",        { MX, EM }, PREFIX_OPCODE },
2686   { "packssdw",         { MX, EM }, PREFIX_OPCODE },
2687   { PREFIX_TABLE (PREFIX_0F6C) },
2688   { PREFIX_TABLE (PREFIX_0F6D) },
2689   { "movK",             { MX, Edq }, PREFIX_OPCODE },
2690   { PREFIX_TABLE (PREFIX_0F6F) },
2691   /* 70 */
2692   { PREFIX_TABLE (PREFIX_0F70) },
2693   { REG_TABLE (REG_0F71) },
2694   { REG_TABLE (REG_0F72) },
2695   { REG_TABLE (REG_0F73) },
2696   { "pcmpeqb",          { MX, EM }, PREFIX_OPCODE },
2697   { "pcmpeqw",          { MX, EM }, PREFIX_OPCODE },
2698   { "pcmpeqd",          { MX, EM }, PREFIX_OPCODE },
2699   { "emms",             { XX }, PREFIX_OPCODE },
2700   /* 78 */
2701   { PREFIX_TABLE (PREFIX_0F78) },
2702   { PREFIX_TABLE (PREFIX_0F79) },
2703   { Bad_Opcode },
2704   { Bad_Opcode },
2705   { PREFIX_TABLE (PREFIX_0F7C) },
2706   { PREFIX_TABLE (PREFIX_0F7D) },
2707   { PREFIX_TABLE (PREFIX_0F7E) },
2708   { PREFIX_TABLE (PREFIX_0F7F) },
2709   /* 80 */
2710   { "joH",              { Jv, BND, cond_jump_flag }, 0 },
2711   { "jnoH",             { Jv, BND, cond_jump_flag }, 0 },
2712   { "jbH",              { Jv, BND, cond_jump_flag }, 0 },
2713   { "jaeH",             { Jv, BND, cond_jump_flag }, 0 },
2714   { "jeH",              { Jv, BND, cond_jump_flag }, 0 },
2715   { "jneH",             { Jv, BND, cond_jump_flag }, 0 },
2716   { "jbeH",             { Jv, BND, cond_jump_flag }, 0 },
2717   { "jaH",              { Jv, BND, cond_jump_flag }, 0 },
2718   /* 88 */
2719   { "jsH",              { Jv, BND, cond_jump_flag }, 0 },
2720   { "jnsH",             { Jv, BND, cond_jump_flag }, 0 },
2721   { "jpH",              { Jv, BND, cond_jump_flag }, 0 },
2722   { "jnpH",             { Jv, BND, cond_jump_flag }, 0 },
2723   { "jlH",              { Jv, BND, cond_jump_flag }, 0 },
2724   { "jgeH",             { Jv, BND, cond_jump_flag }, 0 },
2725   { "jleH",             { Jv, BND, cond_jump_flag }, 0 },
2726   { "jgH",              { Jv, BND, cond_jump_flag }, 0 },
2727   /* 90 */
2728   { "seto",             { Eb }, 0 },
2729   { "setno",            { Eb }, 0 },
2730   { "setb",             { Eb }, 0 },
2731   { "setae",            { Eb }, 0 },
2732   { "sete",             { Eb }, 0 },
2733   { "setne",            { Eb }, 0 },
2734   { "setbe",            { Eb }, 0 },
2735   { "seta",             { Eb }, 0 },
2736   /* 98 */
2737   { "sets",             { Eb }, 0 },
2738   { "setns",            { Eb }, 0 },
2739   { "setp",             { Eb }, 0 },
2740   { "setnp",            { Eb }, 0 },
2741   { "setl",             { Eb }, 0 },
2742   { "setge",            { Eb }, 0 },
2743   { "setle",            { Eb }, 0 },
2744   { "setg",             { Eb }, 0 },
2745   /* a0 */
2746   { "pushT",            { fs }, 0 },
2747   { "popT",             { fs }, 0 },
2748   { "cpuid",            { XX }, 0 },
2749   { "btS",              { Ev, Gv }, 0 },
2750   { "shldS",            { Ev, Gv, Ib }, 0 },
2751   { "shldS",            { Ev, Gv, CL }, 0 },
2752   { REG_TABLE (REG_0FA6) },
2753   { REG_TABLE (REG_0FA7) },
2754   /* a8 */
2755   { "pushT",            { gs }, 0 },
2756   { "popT",             { gs }, 0 },
2757   { "rsm",              { XX }, 0 },
2758   { "btsS",             { Evh1, Gv }, 0 },
2759   { "shrdS",            { Ev, Gv, Ib }, 0 },
2760   { "shrdS",            { Ev, Gv, CL }, 0 },
2761   { REG_TABLE (REG_0FAE) },
2762   { "imulS",            { Gv, Ev }, 0 },
2763   /* b0 */
2764   { "cmpxchgB",         { Ebh1, Gb }, 0 },
2765   { "cmpxchgS",         { Evh1, Gv }, 0 },
2766   { MOD_TABLE (MOD_0FB2) },
2767   { "btrS",             { Evh1, Gv }, 0 },
2768   { MOD_TABLE (MOD_0FB4) },
2769   { MOD_TABLE (MOD_0FB5) },
2770   { "movz{bR|x}",       { Gv, Eb }, 0 },
2771   { "movz{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movzww ! */
2772   /* b8 */
2773   { PREFIX_TABLE (PREFIX_0FB8) },
2774   { "ud1S",             { Gv, Ev }, 0 },
2775   { REG_TABLE (REG_0FBA) },
2776   { "btcS",             { Evh1, Gv }, 0 },
2777   { PREFIX_TABLE (PREFIX_0FBC) },
2778   { PREFIX_TABLE (PREFIX_0FBD) },
2779   { "movs{bR|x}",       { Gv, Eb }, 0 },
2780   { "movs{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movsww ! */
2781   /* c0 */
2782   { "xaddB",            { Ebh1, Gb }, 0 },
2783   { "xaddS",            { Evh1, Gv }, 0 },
2784   { PREFIX_TABLE (PREFIX_0FC2) },
2785   { MOD_TABLE (MOD_0FC3) },
2786   { "pinsrw",           { MX, Edqw, Ib }, PREFIX_OPCODE },
2787   { "pextrw",           { Gdq, MS, Ib }, PREFIX_OPCODE },
2788   { "shufpX",           { XM, EXx, Ib }, PREFIX_OPCODE },
2789   { REG_TABLE (REG_0FC7) },
2790   /* c8 */
2791   { "bswap",            { RMeAX }, 0 },
2792   { "bswap",            { RMeCX }, 0 },
2793   { "bswap",            { RMeDX }, 0 },
2794   { "bswap",            { RMeBX }, 0 },
2795   { "bswap",            { RMeSP }, 0 },
2796   { "bswap",            { RMeBP }, 0 },
2797   { "bswap",            { RMeSI }, 0 },
2798   { "bswap",            { RMeDI }, 0 },
2799   /* d0 */
2800   { PREFIX_TABLE (PREFIX_0FD0) },
2801   { "psrlw",            { MX, EM }, PREFIX_OPCODE },
2802   { "psrld",            { MX, EM }, PREFIX_OPCODE },
2803   { "psrlq",            { MX, EM }, PREFIX_OPCODE },
2804   { "paddq",            { MX, EM }, PREFIX_OPCODE },
2805   { "pmullw",           { MX, EM }, PREFIX_OPCODE },
2806   { PREFIX_TABLE (PREFIX_0FD6) },
2807   { MOD_TABLE (MOD_0FD7) },
2808   /* d8 */
2809   { "psubusb",          { MX, EM }, PREFIX_OPCODE },
2810   { "psubusw",          { MX, EM }, PREFIX_OPCODE },
2811   { "pminub",           { MX, EM }, PREFIX_OPCODE },
2812   { "pand",             { MX, EM }, PREFIX_OPCODE },
2813   { "paddusb",          { MX, EM }, PREFIX_OPCODE },
2814   { "paddusw",          { MX, EM }, PREFIX_OPCODE },
2815   { "pmaxub",           { MX, EM }, PREFIX_OPCODE },
2816   { "pandn",            { MX, EM }, PREFIX_OPCODE },
2817   /* e0 */
2818   { "pavgb",            { MX, EM }, PREFIX_OPCODE },
2819   { "psraw",            { MX, EM }, PREFIX_OPCODE },
2820   { "psrad",            { MX, EM }, PREFIX_OPCODE },
2821   { "pavgw",            { MX, EM }, PREFIX_OPCODE },
2822   { "pmulhuw",          { MX, EM }, PREFIX_OPCODE },
2823   { "pmulhw",           { MX, EM }, PREFIX_OPCODE },
2824   { PREFIX_TABLE (PREFIX_0FE6) },
2825   { PREFIX_TABLE (PREFIX_0FE7) },
2826   /* e8 */
2827   { "psubsb",           { MX, EM }, PREFIX_OPCODE },
2828   { "psubsw",           { MX, EM }, PREFIX_OPCODE },
2829   { "pminsw",           { MX, EM }, PREFIX_OPCODE },
2830   { "por",              { MX, EM }, PREFIX_OPCODE },
2831   { "paddsb",           { MX, EM }, PREFIX_OPCODE },
2832   { "paddsw",           { MX, EM }, PREFIX_OPCODE },
2833   { "pmaxsw",           { MX, EM }, PREFIX_OPCODE },
2834   { "pxor",             { MX, EM }, PREFIX_OPCODE },
2835   /* f0 */
2836   { PREFIX_TABLE (PREFIX_0FF0) },
2837   { "psllw",            { MX, EM }, PREFIX_OPCODE },
2838   { "pslld",            { MX, EM }, PREFIX_OPCODE },
2839   { "psllq",            { MX, EM }, PREFIX_OPCODE },
2840   { "pmuludq",          { MX, EM }, PREFIX_OPCODE },
2841   { "pmaddwd",          { MX, EM }, PREFIX_OPCODE },
2842   { "psadbw",           { MX, EM }, PREFIX_OPCODE },
2843   { PREFIX_TABLE (PREFIX_0FF7) },
2844   /* f8 */
2845   { "psubb",            { MX, EM }, PREFIX_OPCODE },
2846   { "psubw",            { MX, EM }, PREFIX_OPCODE },
2847   { "psubd",            { MX, EM }, PREFIX_OPCODE },
2848   { "psubq",            { MX, EM }, PREFIX_OPCODE },
2849   { "paddb",            { MX, EM }, PREFIX_OPCODE },
2850   { "paddw",            { MX, EM }, PREFIX_OPCODE },
2851   { "paddd",            { MX, EM }, PREFIX_OPCODE },
2852   { "ud0S",             { Gv, Ev }, 0 },
2853 };
2854
2855 static const unsigned char onebyte_has_modrm[256] = {
2856   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2857   /*       -------------------------------        */
2858   /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2859   /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2860   /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2861   /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2862   /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2863   /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2864   /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2865   /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2866   /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2867   /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2868   /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2869   /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2870   /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2871   /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2872   /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2873   /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1  /* f0 */
2874   /*       -------------------------------        */
2875   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2876 };
2877
2878 static const unsigned char twobyte_has_modrm[256] = {
2879   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2880   /*       -------------------------------        */
2881   /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2882   /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2883   /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2884   /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2885   /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2886   /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2887   /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2888   /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2889   /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2890   /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2891   /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2892   /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */
2893   /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2894   /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2895   /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2896   /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1  /* ff */
2897   /*       -------------------------------        */
2898   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2899 };
2900
2901 static char obuf[100];
2902 static char *obufp;
2903 static char *mnemonicendp;
2904 static char scratchbuf[100];
2905 static unsigned char *start_codep;
2906 static unsigned char *insn_codep;
2907 static unsigned char *codep;
2908 static unsigned char *end_codep;
2909 static int last_lock_prefix;
2910 static int last_repz_prefix;
2911 static int last_repnz_prefix;
2912 static int last_data_prefix;
2913 static int last_addr_prefix;
2914 static int last_rex_prefix;
2915 static int last_seg_prefix;
2916 static int fwait_prefix;
2917 /* The active segment register prefix.  */
2918 static int active_seg_prefix;
2919 #define MAX_CODE_LENGTH 15
2920 /* We can up to 14 prefixes since the maximum instruction length is
2921    15bytes.  */
2922 static int all_prefixes[MAX_CODE_LENGTH - 1];
2923 static disassemble_info *the_info;
2924 static struct
2925   {
2926     int mod;
2927     int reg;
2928     int rm;
2929   }
2930 modrm;
2931 static unsigned char need_modrm;
2932 static struct
2933   {
2934     int scale;
2935     int index;
2936     int base;
2937   }
2938 sib;
2939 static struct
2940   {
2941     int register_specifier;
2942     int length;
2943     int prefix;
2944     int w;
2945     int evex;
2946     int r;
2947     int v;
2948     int mask_register_specifier;
2949     int zeroing;
2950     int ll;
2951     int b;
2952   }
2953 vex;
2954 static unsigned char need_vex;
2955 static unsigned char need_vex_reg;
2956
2957 struct op
2958   {
2959     const char *name;
2960     unsigned int len;
2961   };
2962
2963 /* If we are accessing mod/rm/reg without need_modrm set, then the
2964    values are stale.  Hitting this abort likely indicates that you
2965    need to update onebyte_has_modrm or twobyte_has_modrm.  */
2966 #define MODRM_CHECK  if (!need_modrm) abort ()
2967
2968 static const char **names64;
2969 static const char **names32;
2970 static const char **names16;
2971 static const char **names8;
2972 static const char **names8rex;
2973 static const char **names_seg;
2974 static const char *index64;
2975 static const char *index32;
2976 static const char **index16;
2977 static const char **names_bnd;
2978
2979 static const char *intel_names64[] = {
2980   "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
2981   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
2982 };
2983 static const char *intel_names32[] = {
2984   "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
2985   "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
2986 };
2987 static const char *intel_names16[] = {
2988   "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
2989   "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
2990 };
2991 static const char *intel_names8[] = {
2992   "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
2993 };
2994 static const char *intel_names8rex[] = {
2995   "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
2996   "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
2997 };
2998 static const char *intel_names_seg[] = {
2999   "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
3000 };
3001 static const char *intel_index64 = "riz";
3002 static const char *intel_index32 = "eiz";
3003 static const char *intel_index16[] = {
3004   "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
3005 };
3006
3007 static const char *att_names64[] = {
3008   "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
3009   "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
3010 };
3011 static const char *att_names32[] = {
3012   "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
3013   "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
3014 };
3015 static const char *att_names16[] = {
3016   "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
3017   "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
3018 };
3019 static const char *att_names8[] = {
3020   "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
3021 };
3022 static const char *att_names8rex[] = {
3023   "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
3024   "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
3025 };
3026 static const char *att_names_seg[] = {
3027   "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
3028 };
3029 static const char *att_index64 = "%riz";
3030 static const char *att_index32 = "%eiz";
3031 static const char *att_index16[] = {
3032   "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
3033 };
3034
3035 static const char **names_mm;
3036 static const char *intel_names_mm[] = {
3037   "mm0", "mm1", "mm2", "mm3",
3038   "mm4", "mm5", "mm6", "mm7"
3039 };
3040 static const char *att_names_mm[] = {
3041   "%mm0", "%mm1", "%mm2", "%mm3",
3042   "%mm4", "%mm5", "%mm6", "%mm7"
3043 };
3044
3045 static const char *intel_names_bnd[] = {
3046   "bnd0", "bnd1", "bnd2", "bnd3"
3047 };
3048
3049 static const char *att_names_bnd[] = {
3050   "%bnd0", "%bnd1", "%bnd2", "%bnd3"
3051 };
3052
3053 static const char **names_xmm;
3054 static const char *intel_names_xmm[] = {
3055   "xmm0", "xmm1", "xmm2", "xmm3",
3056   "xmm4", "xmm5", "xmm6", "xmm7",
3057   "xmm8", "xmm9", "xmm10", "xmm11",
3058   "xmm12", "xmm13", "xmm14", "xmm15",
3059   "xmm16", "xmm17", "xmm18", "xmm19",
3060   "xmm20", "xmm21", "xmm22", "xmm23",
3061   "xmm24", "xmm25", "xmm26", "xmm27",
3062   "xmm28", "xmm29", "xmm30", "xmm31"
3063 };
3064 static const char *att_names_xmm[] = {
3065   "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3066   "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3067   "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3068   "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3069   "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3070   "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3071   "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3072   "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3073 };
3074
3075 static const char **names_ymm;
3076 static const char *intel_names_ymm[] = {
3077   "ymm0", "ymm1", "ymm2", "ymm3",
3078   "ymm4", "ymm5", "ymm6", "ymm7",
3079   "ymm8", "ymm9", "ymm10", "ymm11",
3080   "ymm12", "ymm13", "ymm14", "ymm15",
3081   "ymm16", "ymm17", "ymm18", "ymm19",
3082   "ymm20", "ymm21", "ymm22", "ymm23",
3083   "ymm24", "ymm25", "ymm26", "ymm27",
3084   "ymm28", "ymm29", "ymm30", "ymm31"
3085 };
3086 static const char *att_names_ymm[] = {
3087   "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3088   "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3089   "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3090   "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3091   "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3092   "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3093   "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3094   "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3095 };
3096
3097 static const char **names_zmm;
3098 static const char *intel_names_zmm[] = {
3099   "zmm0", "zmm1", "zmm2", "zmm3",
3100   "zmm4", "zmm5", "zmm6", "zmm7",
3101   "zmm8", "zmm9", "zmm10", "zmm11",
3102   "zmm12", "zmm13", "zmm14", "zmm15",
3103   "zmm16", "zmm17", "zmm18", "zmm19",
3104   "zmm20", "zmm21", "zmm22", "zmm23",
3105   "zmm24", "zmm25", "zmm26", "zmm27",
3106   "zmm28", "zmm29", "zmm30", "zmm31"
3107 };
3108 static const char *att_names_zmm[] = {
3109   "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3110   "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3111   "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3112   "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3113   "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3114   "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3115   "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3116   "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3117 };
3118
3119 static const char **names_mask;
3120 static const char *intel_names_mask[] = {
3121   "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3122 };
3123 static const char *att_names_mask[] = {
3124   "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3125 };
3126
3127 static const char *names_rounding[] =
3128 {
3129   "{rn-sae}",
3130   "{rd-sae}",
3131   "{ru-sae}",
3132   "{rz-sae}"
3133 };
3134
3135 static const struct dis386 reg_table[][8] = {
3136   /* REG_80 */
3137   {
3138     { "addA",   { Ebh1, Ib }, 0 },
3139     { "orA",    { Ebh1, Ib }, 0 },
3140     { "adcA",   { Ebh1, Ib }, 0 },
3141     { "sbbA",   { Ebh1, Ib }, 0 },
3142     { "andA",   { Ebh1, Ib }, 0 },
3143     { "subA",   { Ebh1, Ib }, 0 },
3144     { "xorA",   { Ebh1, Ib }, 0 },
3145     { "cmpA",   { Eb, Ib }, 0 },
3146   },
3147   /* REG_81 */
3148   {
3149     { "addQ",   { Evh1, Iv }, 0 },
3150     { "orQ",    { Evh1, Iv }, 0 },
3151     { "adcQ",   { Evh1, Iv }, 0 },
3152     { "sbbQ",   { Evh1, Iv }, 0 },
3153     { "andQ",   { Evh1, Iv }, 0 },
3154     { "subQ",   { Evh1, Iv }, 0 },
3155     { "xorQ",   { Evh1, Iv }, 0 },
3156     { "cmpQ",   { Ev, Iv }, 0 },
3157   },
3158   /* REG_83 */
3159   {
3160     { "addQ",   { Evh1, sIb }, 0 },
3161     { "orQ",    { Evh1, sIb }, 0 },
3162     { "adcQ",   { Evh1, sIb }, 0 },
3163     { "sbbQ",   { Evh1, sIb }, 0 },
3164     { "andQ",   { Evh1, sIb }, 0 },
3165     { "subQ",   { Evh1, sIb }, 0 },
3166     { "xorQ",   { Evh1, sIb }, 0 },
3167     { "cmpQ",   { Ev, sIb }, 0 },
3168   },
3169   /* REG_8F */
3170   {
3171     { "popU",   { stackEv }, 0 },
3172     { XOP_8F_TABLE (XOP_09) },
3173     { Bad_Opcode },
3174     { Bad_Opcode },
3175     { Bad_Opcode },
3176     { XOP_8F_TABLE (XOP_09) },
3177   },
3178   /* REG_C0 */
3179   {
3180     { "rolA",   { Eb, Ib }, 0 },
3181     { "rorA",   { Eb, Ib }, 0 },
3182     { "rclA",   { Eb, Ib }, 0 },
3183     { "rcrA",   { Eb, Ib }, 0 },
3184     { "shlA",   { Eb, Ib }, 0 },
3185     { "shrA",   { Eb, Ib }, 0 },
3186     { "shlA",   { Eb, Ib }, 0 },
3187     { "sarA",   { Eb, Ib }, 0 },
3188   },
3189   /* REG_C1 */
3190   {
3191     { "rolQ",   { Ev, Ib }, 0 },
3192     { "rorQ",   { Ev, Ib }, 0 },
3193     { "rclQ",   { Ev, Ib }, 0 },
3194     { "rcrQ",   { Ev, Ib }, 0 },
3195     { "shlQ",   { Ev, Ib }, 0 },
3196     { "shrQ",   { Ev, Ib }, 0 },
3197     { "shlQ",   { Ev, Ib }, 0 },
3198     { "sarQ",   { Ev, Ib }, 0 },
3199   },
3200   /* REG_C6 */
3201   {
3202     { "movA",   { Ebh3, Ib }, 0 },
3203     { Bad_Opcode },
3204     { Bad_Opcode },
3205     { Bad_Opcode },
3206     { Bad_Opcode },
3207     { Bad_Opcode },
3208     { Bad_Opcode },
3209     { MOD_TABLE (MOD_C6_REG_7) },
3210   },
3211   /* REG_C7 */
3212   {
3213     { "movQ",   { Evh3, Iv }, 0 },
3214     { Bad_Opcode },
3215     { Bad_Opcode },
3216     { Bad_Opcode },
3217     { Bad_Opcode },
3218     { Bad_Opcode },
3219     { Bad_Opcode },
3220     { MOD_TABLE (MOD_C7_REG_7) },
3221   },
3222   /* REG_D0 */
3223   {
3224     { "rolA",   { Eb, I1 }, 0 },
3225     { "rorA",   { Eb, I1 }, 0 },
3226     { "rclA",   { Eb, I1 }, 0 },
3227     { "rcrA",   { Eb, I1 }, 0 },
3228     { "shlA",   { Eb, I1 }, 0 },
3229     { "shrA",   { Eb, I1 }, 0 },
3230     { "shlA",   { Eb, I1 }, 0 },
3231     { "sarA",   { Eb, I1 }, 0 },
3232   },
3233   /* REG_D1 */
3234   {
3235     { "rolQ",   { Ev, I1 }, 0 },
3236     { "rorQ",   { Ev, I1 }, 0 },
3237     { "rclQ",   { Ev, I1 }, 0 },
3238     { "rcrQ",   { Ev, I1 }, 0 },
3239     { "shlQ",   { Ev, I1 }, 0 },
3240     { "shrQ",   { Ev, I1 }, 0 },
3241     { "shlQ",   { Ev, I1 }, 0 },
3242     { "sarQ",   { Ev, I1 }, 0 },
3243   },
3244   /* REG_D2 */
3245   {
3246     { "rolA",   { Eb, CL }, 0 },
3247     { "rorA",   { Eb, CL }, 0 },
3248     { "rclA",   { Eb, CL }, 0 },
3249     { "rcrA",   { Eb, CL }, 0 },
3250     { "shlA",   { Eb, CL }, 0 },
3251     { "shrA",   { Eb, CL }, 0 },
3252     { "shlA",   { Eb, CL }, 0 },
3253     { "sarA",   { Eb, CL }, 0 },
3254   },
3255   /* REG_D3 */
3256   {
3257     { "rolQ",   { Ev, CL }, 0 },
3258     { "rorQ",   { Ev, CL }, 0 },
3259     { "rclQ",   { Ev, CL }, 0 },
3260     { "rcrQ",   { Ev, CL }, 0 },
3261     { "shlQ",   { Ev, CL }, 0 },
3262     { "shrQ",   { Ev, CL }, 0 },
3263     { "shlQ",   { Ev, CL }, 0 },
3264     { "sarQ",   { Ev, CL }, 0 },
3265   },
3266   /* REG_F6 */
3267   {
3268     { "testA",  { Eb, Ib }, 0 },
3269     { "testA",  { Eb, Ib }, 0 },
3270     { "notA",   { Ebh1 }, 0 },
3271     { "negA",   { Ebh1 }, 0 },
3272     { "mulA",   { Eb }, 0 },    /* Don't print the implicit %al register,  */
3273     { "imulA",  { Eb }, 0 },    /* to distinguish these opcodes from other */
3274     { "divA",   { Eb }, 0 },    /* mul/imul opcodes.  Do the same for div  */
3275     { "idivA",  { Eb }, 0 },    /* and idiv for consistency.               */
3276   },
3277   /* REG_F7 */
3278   {
3279     { "testQ",  { Ev, Iv }, 0 },
3280     { "testQ",  { Ev, Iv }, 0 },
3281     { "notQ",   { Evh1 }, 0 },
3282     { "negQ",   { Evh1 }, 0 },
3283     { "mulQ",   { Ev }, 0 },    /* Don't print the implicit register.  */
3284     { "imulQ",  { Ev }, 0 },
3285     { "divQ",   { Ev }, 0 },
3286     { "idivQ",  { Ev }, 0 },
3287   },
3288   /* REG_FE */
3289   {
3290     { "incA",   { Ebh1 }, 0 },
3291     { "decA",   { Ebh1 }, 0 },
3292   },
3293   /* REG_FF */
3294   {
3295     { "incQ",   { Evh1 }, 0 },
3296     { "decQ",   { Evh1 }, 0 },
3297     { "call{&|}", { NOTRACK, indirEv, BND }, 0 },
3298     { MOD_TABLE (MOD_FF_REG_3) },
3299     { "jmp{&|}", { NOTRACK, indirEv, BND }, 0 },
3300     { MOD_TABLE (MOD_FF_REG_5) },
3301     { "pushU",  { stackEv }, 0 },
3302     { Bad_Opcode },
3303   },
3304   /* REG_0F00 */
3305   {
3306     { "sldtD",  { Sv }, 0 },
3307     { "strD",   { Sv }, 0 },
3308     { "lldt",   { Ew }, 0 },
3309     { "ltr",    { Ew }, 0 },
3310     { "verr",   { Ew }, 0 },
3311     { "verw",   { Ew }, 0 },
3312     { Bad_Opcode },
3313     { Bad_Opcode },
3314   },
3315   /* REG_0F01 */
3316   {
3317     { MOD_TABLE (MOD_0F01_REG_0) },
3318     { MOD_TABLE (MOD_0F01_REG_1) },
3319     { MOD_TABLE (MOD_0F01_REG_2) },
3320     { MOD_TABLE (MOD_0F01_REG_3) },
3321     { "smswD",  { Sv }, 0 },
3322     { MOD_TABLE (MOD_0F01_REG_5) },
3323     { "lmsw",   { Ew }, 0 },
3324     { MOD_TABLE (MOD_0F01_REG_7) },
3325   },
3326   /* REG_0F0D */
3327   {
3328     { "prefetch",       { Mb }, 0 },
3329     { "prefetchw",      { Mb }, 0 },
3330     { "prefetchwt1",    { Mb }, 0 },
3331     { "prefetch",       { Mb }, 0 },
3332     { "prefetch",       { Mb }, 0 },
3333     { "prefetch",       { Mb }, 0 },
3334     { "prefetch",       { Mb }, 0 },
3335     { "prefetch",       { Mb }, 0 },
3336   },
3337   /* REG_0F18 */
3338   {
3339     { MOD_TABLE (MOD_0F18_REG_0) },
3340     { MOD_TABLE (MOD_0F18_REG_1) },
3341     { MOD_TABLE (MOD_0F18_REG_2) },
3342     { MOD_TABLE (MOD_0F18_REG_3) },
3343     { MOD_TABLE (MOD_0F18_REG_4) },
3344     { MOD_TABLE (MOD_0F18_REG_5) },
3345     { MOD_TABLE (MOD_0F18_REG_6) },
3346     { MOD_TABLE (MOD_0F18_REG_7) },
3347   },
3348   /* REG_0F1C_P_0_MOD_0 */
3349   {
3350     { "cldemote",       { Mb }, 0 },
3351     { "nopQ",           { Ev }, 0 },
3352     { "nopQ",           { Ev }, 0 },
3353     { "nopQ",           { Ev }, 0 },
3354     { "nopQ",           { Ev }, 0 },
3355     { "nopQ",           { Ev }, 0 },
3356     { "nopQ",           { Ev }, 0 },
3357     { "nopQ",           { Ev }, 0 },
3358   },
3359   /* REG_0F1E_P_1_MOD_3 */
3360   {
3361     { "nopQ",           { Ev }, 0 },
3362     { "rdsspK",         { Rdq }, PREFIX_OPCODE },
3363     { "nopQ",           { Ev }, 0 },
3364     { "nopQ",           { Ev }, 0 },
3365     { "nopQ",           { Ev }, 0 },
3366     { "nopQ",           { Ev }, 0 },
3367     { "nopQ",           { Ev }, 0 },
3368     { RM_TABLE (RM_0F1E_P_1_MOD_3_REG_7) },
3369   },
3370   /* REG_0F71 */
3371   {
3372     { Bad_Opcode },
3373     { Bad_Opcode },
3374     { MOD_TABLE (MOD_0F71_REG_2) },
3375     { Bad_Opcode },
3376     { MOD_TABLE (MOD_0F71_REG_4) },
3377     { Bad_Opcode },
3378     { MOD_TABLE (MOD_0F71_REG_6) },
3379   },
3380   /* REG_0F72 */
3381   {
3382     { Bad_Opcode },
3383     { Bad_Opcode },
3384     { MOD_TABLE (MOD_0F72_REG_2) },
3385     { Bad_Opcode },
3386     { MOD_TABLE (MOD_0F72_REG_4) },
3387     { Bad_Opcode },
3388     { MOD_TABLE (MOD_0F72_REG_6) },
3389   },
3390   /* REG_0F73 */
3391   {
3392     { Bad_Opcode },
3393     { Bad_Opcode },
3394     { MOD_TABLE (MOD_0F73_REG_2) },
3395     { MOD_TABLE (MOD_0F73_REG_3) },
3396     { Bad_Opcode },
3397     { Bad_Opcode },
3398     { MOD_TABLE (MOD_0F73_REG_6) },
3399     { MOD_TABLE (MOD_0F73_REG_7) },
3400   },
3401   /* REG_0FA6 */
3402   {
3403     { "montmul",        { { OP_0f07, 0 } }, 0 },
3404     { "xsha1",          { { OP_0f07, 0 } }, 0 },
3405     { "xsha256",        { { OP_0f07, 0 } }, 0 },
3406   },
3407   /* REG_0FA7 */
3408   {
3409     { "xstore-rng",     { { OP_0f07, 0 } }, 0 },
3410     { "xcrypt-ecb",     { { OP_0f07, 0 } }, 0 },
3411     { "xcrypt-cbc",     { { OP_0f07, 0 } }, 0 },
3412     { "xcrypt-ctr",     { { OP_0f07, 0 } }, 0 },
3413     { "xcrypt-cfb",     { { OP_0f07, 0 } }, 0 },
3414     { "xcrypt-ofb",     { { OP_0f07, 0 } }, 0 },
3415   },
3416   /* REG_0FAE */
3417   {
3418     { MOD_TABLE (MOD_0FAE_REG_0) },
3419     { MOD_TABLE (MOD_0FAE_REG_1) },
3420     { MOD_TABLE (MOD_0FAE_REG_2) },
3421     { MOD_TABLE (MOD_0FAE_REG_3) },
3422     { MOD_TABLE (MOD_0FAE_REG_4) },
3423     { MOD_TABLE (MOD_0FAE_REG_5) },
3424     { MOD_TABLE (MOD_0FAE_REG_6) },
3425     { MOD_TABLE (MOD_0FAE_REG_7) },
3426   },
3427   /* REG_0FBA */
3428   {
3429     { Bad_Opcode },
3430     { Bad_Opcode },
3431     { Bad_Opcode },
3432     { Bad_Opcode },
3433     { "btQ",    { Ev, Ib }, 0 },
3434     { "btsQ",   { Evh1, Ib }, 0 },
3435     { "btrQ",   { Evh1, Ib }, 0 },
3436     { "btcQ",   { Evh1, Ib }, 0 },
3437   },
3438   /* REG_0FC7 */
3439   {
3440     { Bad_Opcode },
3441     { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 },
3442     { Bad_Opcode },
3443     { MOD_TABLE (MOD_0FC7_REG_3) },
3444     { MOD_TABLE (MOD_0FC7_REG_4) },
3445     { MOD_TABLE (MOD_0FC7_REG_5) },
3446     { MOD_TABLE (MOD_0FC7_REG_6) },
3447     { MOD_TABLE (MOD_0FC7_REG_7) },
3448   },
3449   /* REG_VEX_0F71 */
3450   {
3451     { Bad_Opcode },
3452     { Bad_Opcode },
3453     { MOD_TABLE (MOD_VEX_0F71_REG_2) },
3454     { Bad_Opcode },
3455     { MOD_TABLE (MOD_VEX_0F71_REG_4) },
3456     { Bad_Opcode },
3457     { MOD_TABLE (MOD_VEX_0F71_REG_6) },
3458   },
3459   /* REG_VEX_0F72 */
3460   {
3461     { Bad_Opcode },
3462     { Bad_Opcode },
3463     { MOD_TABLE (MOD_VEX_0F72_REG_2) },
3464     { Bad_Opcode },
3465     { MOD_TABLE (MOD_VEX_0F72_REG_4) },
3466     { Bad_Opcode },
3467     { MOD_TABLE (MOD_VEX_0F72_REG_6) },
3468   },
3469   /* REG_VEX_0F73 */
3470   {
3471     { Bad_Opcode },
3472     { Bad_Opcode },
3473     { MOD_TABLE (MOD_VEX_0F73_REG_2) },
3474     { MOD_TABLE (MOD_VEX_0F73_REG_3) },
3475     { Bad_Opcode },
3476     { Bad_Opcode },
3477     { MOD_TABLE (MOD_VEX_0F73_REG_6) },
3478     { MOD_TABLE (MOD_VEX_0F73_REG_7) },
3479   },
3480   /* REG_VEX_0FAE */
3481   {
3482     { Bad_Opcode },
3483     { Bad_Opcode },
3484     { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
3485     { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
3486   },
3487   /* REG_VEX_0F38F3 */
3488   {
3489     { Bad_Opcode },
3490     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) },
3491     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) },
3492     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) },
3493   },
3494   /* REG_0FXOP_09_01_L_0 */
3495   {
3496     { Bad_Opcode },
3497     { "blcfill",        { VexGdq, Edq }, 0 },
3498     { "blsfill",        { VexGdq, Edq }, 0 },
3499     { "blcs",   { VexGdq, Edq }, 0 },
3500     { "tzmsk",  { VexGdq, Edq }, 0 },
3501     { "blcic",  { VexGdq, Edq }, 0 },
3502     { "blsic",  { VexGdq, Edq }, 0 },
3503     { "t1mskc", { VexGdq, Edq }, 0 },
3504   },
3505   /* REG_0FXOP_09_02_L_0 */
3506   {
3507     { Bad_Opcode },
3508     { "blcmsk", { VexGdq, Edq }, 0 },
3509     { Bad_Opcode },
3510     { Bad_Opcode },
3511     { Bad_Opcode },
3512     { Bad_Opcode },
3513     { "blci",   { VexGdq, Edq }, 0 },
3514   },
3515   /* REG_0FXOP_09_12_M_1_L_0 */
3516   {
3517     { "llwpcb", { Edq }, 0 },
3518     { "slwpcb", { Edq }, 0 },
3519   },
3520   /* REG_0FXOP_0A_12_L_0 */
3521   {
3522     { "lwpins", { VexGdq, Ed, Id }, 0 },
3523     { "lwpval", { VexGdq, Ed, Id }, 0 },
3524   },
3525
3526 #include "i386-dis-evex-reg.h"
3527 };
3528
3529 static const struct dis386 prefix_table[][4] = {
3530   /* PREFIX_90 */
3531   {
3532     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3533     { "pause", { XX }, 0 },
3534     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3535     { NULL, { { NULL, 0 } }, PREFIX_IGNORED }
3536   },
3537
3538   /* PREFIX_0F01_REG_3_RM_1 */
3539   {
3540     { "vmmcall",        { Skip_MODRM }, 0 },
3541     { "vmgexit",        { Skip_MODRM }, 0 },
3542     { Bad_Opcode },
3543     { "vmgexit",        { Skip_MODRM }, 0 },
3544   },
3545
3546   /* PREFIX_0F01_REG_5_MOD_0 */
3547   {
3548     { Bad_Opcode },
3549     { "rstorssp",       { Mq }, PREFIX_OPCODE },
3550   },
3551
3552   /* PREFIX_0F01_REG_5_MOD_3_RM_0 */
3553   {
3554     { "serialize",      { Skip_MODRM }, PREFIX_OPCODE },
3555     { "setssbsy",       { Skip_MODRM }, PREFIX_OPCODE },
3556     { Bad_Opcode },
3557     { "xsusldtrk",      { Skip_MODRM }, PREFIX_OPCODE },
3558   },
3559
3560   /* PREFIX_0F01_REG_5_MOD_3_RM_1 */
3561   {
3562     { Bad_Opcode },
3563     { Bad_Opcode },
3564     { Bad_Opcode },
3565     { "xresldtrk",     { Skip_MODRM }, PREFIX_OPCODE },
3566   },
3567
3568   /* PREFIX_0F01_REG_5_MOD_3_RM_2 */
3569   {
3570     { Bad_Opcode },
3571     { "saveprevssp",    { Skip_MODRM }, PREFIX_OPCODE },
3572   },
3573
3574   /* PREFIX_0F01_REG_7_MOD_3_RM_2 */
3575   {
3576     { "monitorx",       { { OP_Monitor, 0 } }, 0  },
3577     { "mcommit",        { Skip_MODRM }, 0 },
3578   },
3579
3580   /* PREFIX_0F01_REG_7_MOD_3_RM_3 */
3581   {
3582     { "mwaitx",         { { OP_Mwait, eBX_reg } }, 0  },
3583   },
3584
3585   /* PREFIX_0F09 */
3586   {
3587     { "wbinvd",   { XX }, 0 },
3588     { "wbnoinvd", { XX }, 0 },
3589   },
3590
3591   /* PREFIX_0F10 */
3592   {
3593     { "movups", { XM, EXx }, PREFIX_OPCODE },
3594     { "movss",  { XM, EXd }, PREFIX_OPCODE },
3595     { "movupd", { XM, EXx }, PREFIX_OPCODE },
3596     { "movsd",  { XM, EXq }, PREFIX_OPCODE },
3597   },
3598
3599   /* PREFIX_0F11 */
3600   {
3601     { "movups", { EXxS, XM }, PREFIX_OPCODE },
3602     { "movss",  { EXdS, XM }, PREFIX_OPCODE },
3603     { "movupd", { EXxS, XM }, PREFIX_OPCODE },
3604     { "movsd",  { EXqS, XM }, PREFIX_OPCODE },
3605   },
3606
3607   /* PREFIX_0F12 */
3608   {
3609     { MOD_TABLE (MOD_0F12_PREFIX_0) },
3610     { "movsldup", { XM, EXx }, PREFIX_OPCODE },
3611     { MOD_TABLE (MOD_0F12_PREFIX_2) },
3612     { "movddup", { XM, EXq }, PREFIX_OPCODE },
3613   },
3614
3615   /* PREFIX_0F16 */
3616   {
3617     { MOD_TABLE (MOD_0F16_PREFIX_0) },
3618     { "movshdup", { XM, EXx }, PREFIX_OPCODE },
3619     { MOD_TABLE (MOD_0F16_PREFIX_2) },
3620   },
3621
3622   /* PREFIX_0F1A */
3623   {
3624     { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3625     { "bndcl",  { Gbnd, Ev_bnd }, 0 },
3626     { "bndmov", { Gbnd, Ebnd }, 0 },
3627     { "bndcu",  { Gbnd, Ev_bnd }, 0 },
3628   },
3629
3630   /* PREFIX_0F1B */
3631   {
3632     { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3633     { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3634     { "bndmov", { EbndS, Gbnd }, 0 },
3635     { "bndcn",  { Gbnd, Ev_bnd }, 0 },
3636   },
3637
3638   /* PREFIX_0F1C */
3639   {
3640     { MOD_TABLE (MOD_0F1C_PREFIX_0) },
3641     { "nopQ",   { Ev }, PREFIX_OPCODE },
3642     { "nopQ",   { Ev }, PREFIX_OPCODE },
3643     { "nopQ",   { Ev }, PREFIX_OPCODE },
3644   },
3645
3646   /* PREFIX_0F1E */
3647   {
3648     { "nopQ",   { Ev }, PREFIX_OPCODE },
3649     { MOD_TABLE (MOD_0F1E_PREFIX_1) },
3650     { "nopQ",   { Ev }, PREFIX_OPCODE },
3651     { "nopQ",   { Ev }, PREFIX_OPCODE },
3652   },
3653
3654   /* PREFIX_0F2A */
3655   {
3656     { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE },
3657     { "cvtsi2ss%LQ", { XM, Edq }, PREFIX_OPCODE },
3658     { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE },
3659     { "cvtsi2sd%LQ", { XM, Edq }, 0 },
3660   },
3661
3662   /* PREFIX_0F2B */
3663   {
3664     { MOD_TABLE (MOD_0F2B_PREFIX_0) },
3665     { MOD_TABLE (MOD_0F2B_PREFIX_1) },
3666     { MOD_TABLE (MOD_0F2B_PREFIX_2) },
3667     { MOD_TABLE (MOD_0F2B_PREFIX_3) },
3668   },
3669
3670   /* PREFIX_0F2C */
3671   {
3672     { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE },
3673     { "cvttss2si", { Gdq, EXd }, PREFIX_OPCODE },
3674     { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3675     { "cvttsd2si", { Gdq, EXq }, PREFIX_OPCODE },
3676   },
3677
3678   /* PREFIX_0F2D */
3679   {
3680     { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE },
3681     { "cvtss2si", { Gdq, EXd }, PREFIX_OPCODE },
3682     { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3683     { "cvtsd2si", { Gdq, EXq }, PREFIX_OPCODE },
3684   },
3685
3686   /* PREFIX_0F2E */
3687   {
3688     { "ucomiss",{ XM, EXd }, 0 },
3689     { Bad_Opcode },
3690     { "ucomisd",{ XM, EXq }, 0 },
3691   },
3692
3693   /* PREFIX_0F2F */
3694   {
3695     { "comiss", { XM, EXd }, 0 },
3696     { Bad_Opcode },
3697     { "comisd", { XM, EXq }, 0 },
3698   },
3699
3700   /* PREFIX_0F51 */
3701   {
3702     { "sqrtps", { XM, EXx }, PREFIX_OPCODE },
3703     { "sqrtss", { XM, EXd }, PREFIX_OPCODE },
3704     { "sqrtpd", { XM, EXx }, PREFIX_OPCODE },
3705     { "sqrtsd", { XM, EXq }, PREFIX_OPCODE },
3706   },
3707
3708   /* PREFIX_0F52 */
3709   {
3710     { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE },
3711     { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE },
3712   },
3713
3714   /* PREFIX_0F53 */
3715   {
3716     { "rcpps",  { XM, EXx }, PREFIX_OPCODE },
3717     { "rcpss",  { XM, EXd }, PREFIX_OPCODE },
3718   },
3719
3720   /* PREFIX_0F58 */
3721   {
3722     { "addps", { XM, EXx }, PREFIX_OPCODE },
3723     { "addss", { XM, EXd }, PREFIX_OPCODE },
3724     { "addpd", { XM, EXx }, PREFIX_OPCODE },
3725     { "addsd", { XM, EXq }, PREFIX_OPCODE },
3726   },
3727
3728   /* PREFIX_0F59 */
3729   {
3730     { "mulps",  { XM, EXx }, PREFIX_OPCODE },
3731     { "mulss",  { XM, EXd }, PREFIX_OPCODE },
3732     { "mulpd",  { XM, EXx }, PREFIX_OPCODE },
3733     { "mulsd",  { XM, EXq }, PREFIX_OPCODE },
3734   },
3735
3736   /* PREFIX_0F5A */
3737   {
3738     { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE },
3739     { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE },
3740     { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE },
3741     { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE },
3742   },
3743
3744   /* PREFIX_0F5B */
3745   {
3746     { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE },
3747     { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE },
3748     { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE },
3749   },
3750
3751   /* PREFIX_0F5C */
3752   {
3753     { "subps",  { XM, EXx }, PREFIX_OPCODE },
3754     { "subss",  { XM, EXd }, PREFIX_OPCODE },
3755     { "subpd",  { XM, EXx }, PREFIX_OPCODE },
3756     { "subsd",  { XM, EXq }, PREFIX_OPCODE },
3757   },
3758
3759   /* PREFIX_0F5D */
3760   {
3761     { "minps",  { XM, EXx }, PREFIX_OPCODE },
3762     { "minss",  { XM, EXd }, PREFIX_OPCODE },
3763     { "minpd",  { XM, EXx }, PREFIX_OPCODE },
3764     { "minsd",  { XM, EXq }, PREFIX_OPCODE },
3765   },
3766
3767   /* PREFIX_0F5E */
3768   {
3769     { "divps",  { XM, EXx }, PREFIX_OPCODE },
3770     { "divss",  { XM, EXd }, PREFIX_OPCODE },
3771     { "divpd",  { XM, EXx }, PREFIX_OPCODE },
3772     { "divsd",  { XM, EXq }, PREFIX_OPCODE },
3773   },
3774
3775   /* PREFIX_0F5F */
3776   {
3777     { "maxps",  { XM, EXx }, PREFIX_OPCODE },
3778     { "maxss",  { XM, EXd }, PREFIX_OPCODE },
3779     { "maxpd",  { XM, EXx }, PREFIX_OPCODE },
3780     { "maxsd",  { XM, EXq }, PREFIX_OPCODE },
3781   },
3782
3783   /* PREFIX_0F60 */
3784   {
3785     { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE },
3786     { Bad_Opcode },
3787     { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE },
3788   },
3789
3790   /* PREFIX_0F61 */
3791   {
3792     { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE },
3793     { Bad_Opcode },
3794     { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE },
3795   },
3796
3797   /* PREFIX_0F62 */
3798   {
3799     { "punpckldq",{ MX, EMd }, PREFIX_OPCODE },
3800     { Bad_Opcode },
3801     { "punpckldq",{ MX, EMx }, PREFIX_OPCODE },
3802   },
3803
3804   /* PREFIX_0F6C */
3805   {
3806     { Bad_Opcode },
3807     { Bad_Opcode },
3808     { "punpcklqdq", { XM, EXx }, PREFIX_OPCODE },
3809   },
3810
3811   /* PREFIX_0F6D */
3812   {
3813     { Bad_Opcode },
3814     { Bad_Opcode },
3815     { "punpckhqdq", { XM, EXx }, PREFIX_OPCODE },
3816   },
3817
3818   /* PREFIX_0F6F */
3819   {
3820     { "movq",   { MX, EM }, PREFIX_OPCODE },
3821     { "movdqu", { XM, EXx }, PREFIX_OPCODE },
3822     { "movdqa", { XM, EXx }, PREFIX_OPCODE },
3823   },
3824
3825   /* PREFIX_0F70 */
3826   {
3827     { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE },
3828     { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3829     { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE },
3830     { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3831   },
3832
3833   /* PREFIX_0F73_REG_3 */
3834   {
3835     { Bad_Opcode },
3836     { Bad_Opcode },
3837     { "psrldq", { XS, Ib }, 0 },
3838   },
3839
3840   /* PREFIX_0F73_REG_7 */
3841   {
3842     { Bad_Opcode },
3843     { Bad_Opcode },
3844     { "pslldq", { XS, Ib }, 0 },
3845   },
3846
3847   /* PREFIX_0F78 */
3848   {
3849     {"vmread",  { Em, Gm }, 0 },
3850     { Bad_Opcode },
3851     {"extrq",   { XS, Ib, Ib }, 0 },
3852     {"insertq", { XM, XS, Ib, Ib }, 0 },
3853   },
3854
3855   /* PREFIX_0F79 */
3856   {
3857     {"vmwrite", { Gm, Em }, 0 },
3858     { Bad_Opcode },
3859     {"extrq",   { XM, XS }, 0 },
3860     {"insertq", { XM, XS }, 0 },
3861   },
3862
3863   /* PREFIX_0F7C */
3864   {
3865     { Bad_Opcode },
3866     { Bad_Opcode },
3867     { "haddpd", { XM, EXx }, PREFIX_OPCODE },
3868     { "haddps", { XM, EXx }, PREFIX_OPCODE },
3869   },
3870
3871   /* PREFIX_0F7D */
3872   {
3873     { Bad_Opcode },
3874     { Bad_Opcode },
3875     { "hsubpd", { XM, EXx }, PREFIX_OPCODE },
3876     { "hsubps", { XM, EXx }, PREFIX_OPCODE },
3877   },
3878
3879   /* PREFIX_0F7E */
3880   {
3881     { "movK",   { Edq, MX }, PREFIX_OPCODE },
3882     { "movq",   { XM, EXq }, PREFIX_OPCODE },
3883     { "movK",   { Edq, XM }, PREFIX_OPCODE },
3884   },
3885
3886   /* PREFIX_0F7F */
3887   {
3888     { "movq",   { EMS, MX }, PREFIX_OPCODE },
3889     { "movdqu", { EXxS, XM }, PREFIX_OPCODE },
3890     { "movdqa", { EXxS, XM }, PREFIX_OPCODE },
3891   },
3892
3893   /* PREFIX_0FAE_REG_0_MOD_3 */
3894   {
3895     { Bad_Opcode },
3896     { "rdfsbase", { Ev }, 0 },
3897   },
3898
3899   /* PREFIX_0FAE_REG_1_MOD_3 */
3900   {
3901     { Bad_Opcode },
3902     { "rdgsbase", { Ev }, 0 },
3903   },
3904
3905   /* PREFIX_0FAE_REG_2_MOD_3 */
3906   {
3907     { Bad_Opcode },
3908     { "wrfsbase", { Ev }, 0 },
3909   },
3910
3911   /* PREFIX_0FAE_REG_3_MOD_3 */
3912   {
3913     { Bad_Opcode },
3914     { "wrgsbase", { Ev }, 0 },
3915   },
3916
3917   /* PREFIX_0FAE_REG_4_MOD_0 */
3918   {
3919     { "xsave",  { FXSAVE }, 0 },
3920     { "ptwrite%LQ", { Edq }, 0 },
3921   },
3922
3923   /* PREFIX_0FAE_REG_4_MOD_3 */
3924   {
3925     { Bad_Opcode },
3926     { "ptwrite%LQ", { Edq }, 0 },
3927   },
3928
3929   /* PREFIX_0FAE_REG_5_MOD_0 */
3930   {
3931     { "xrstor",         { FXSAVE }, PREFIX_OPCODE },
3932   },
3933
3934   /* PREFIX_0FAE_REG_5_MOD_3 */
3935   {
3936     { "lfence",         { Skip_MODRM }, 0 },
3937     { "incsspK",        { Rdq }, PREFIX_OPCODE },
3938   },
3939
3940   /* PREFIX_0FAE_REG_6_MOD_0 */
3941   {
3942     { "xsaveopt",       { FXSAVE }, PREFIX_OPCODE },
3943     { "clrssbsy",       { Mq }, PREFIX_OPCODE },
3944     { "clwb",   { Mb }, PREFIX_OPCODE },
3945   },
3946
3947   /* PREFIX_0FAE_REG_6_MOD_3 */
3948   {
3949     { RM_TABLE (RM_0FAE_REG_6_MOD_3_P_0) },
3950     { "umonitor",       { Eva }, PREFIX_OPCODE },
3951     { "tpause", { Edq }, PREFIX_OPCODE },
3952     { "umwait", { Edq }, PREFIX_OPCODE },
3953   },
3954
3955   /* PREFIX_0FAE_REG_7_MOD_0 */
3956   {
3957     { "clflush",        { Mb }, 0 },
3958     { Bad_Opcode },
3959     { "clflushopt",     { Mb }, 0 },
3960   },
3961
3962   /* PREFIX_0FB8 */
3963   {
3964     { Bad_Opcode },
3965     { "popcntS", { Gv, Ev }, 0 },
3966   },
3967
3968   /* PREFIX_0FBC */
3969   {
3970     { "bsfS",   { Gv, Ev }, 0 },
3971     { "tzcntS", { Gv, Ev }, 0 },
3972     { "bsfS",   { Gv, Ev }, 0 },
3973   },
3974
3975   /* PREFIX_0FBD */
3976   {
3977     { "bsrS",   { Gv, Ev }, 0 },
3978     { "lzcntS", { Gv, Ev }, 0 },
3979     { "bsrS",   { Gv, Ev }, 0 },
3980   },
3981
3982   /* PREFIX_0FC2 */
3983   {
3984     { "cmpps",  { XM, EXx, CMP }, PREFIX_OPCODE },
3985     { "cmpss",  { XM, EXd, CMP }, PREFIX_OPCODE },
3986     { "cmppd",  { XM, EXx, CMP }, PREFIX_OPCODE },
3987     { "cmpsd",  { XM, EXq, CMP }, PREFIX_OPCODE },
3988   },
3989
3990   /* PREFIX_0FC3_MOD_0 */
3991   {
3992     { "movntiS", { Edq, Gdq }, PREFIX_OPCODE },
3993   },
3994
3995   /* PREFIX_0FC7_REG_6_MOD_0 */
3996   {
3997     { "vmptrld",{ Mq }, 0 },
3998     { "vmxon",  { Mq }, 0 },
3999     { "vmclear",{ Mq }, 0 },
4000   },
4001
4002   /* PREFIX_0FC7_REG_6_MOD_3 */
4003   {
4004     { "rdrand", { Ev }, 0 },
4005     { Bad_Opcode },
4006     { "rdrand", { Ev }, 0 }
4007   },
4008
4009   /* PREFIX_0FC7_REG_7_MOD_3 */
4010   {
4011     { "rdseed", { Ev }, 0 },
4012     { "rdpid",  { Em }, 0 },
4013     { "rdseed", { Ev }, 0 },
4014   },
4015
4016   /* PREFIX_0FD0 */
4017   {
4018     { Bad_Opcode },
4019     { Bad_Opcode },
4020     { "addsubpd", { XM, EXx }, 0 },
4021     { "addsubps", { XM, EXx }, 0 },
4022   },
4023
4024   /* PREFIX_0FD6 */
4025   {
4026     { Bad_Opcode },
4027     { "movq2dq",{ XM, MS }, 0 },
4028     { "movq",   { EXqS, XM }, 0 },
4029     { "movdq2q",{ MX, XS }, 0 },
4030   },
4031
4032   /* PREFIX_0FE6 */
4033   {
4034     { Bad_Opcode },
4035     { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE },
4036     { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE },
4037     { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE },
4038   },
4039
4040   /* PREFIX_0FE7 */
4041   {
4042     { "movntq", { Mq, MX }, PREFIX_OPCODE },
4043     { Bad_Opcode },
4044     { MOD_TABLE (MOD_0FE7_PREFIX_2) },
4045   },
4046
4047   /* PREFIX_0FF0 */
4048   {
4049     { Bad_Opcode },
4050     { Bad_Opcode },
4051     { Bad_Opcode },
4052     { MOD_TABLE (MOD_0FF0_PREFIX_3) },
4053   },
4054
4055   /* PREFIX_0FF7 */
4056   {
4057     { "maskmovq", { MX, MS }, PREFIX_OPCODE },
4058     { Bad_Opcode },
4059     { "maskmovdqu", { XM, XS }, PREFIX_OPCODE },
4060   },
4061
4062   /* PREFIX_0F3810 */
4063   {
4064     { Bad_Opcode },
4065     { Bad_Opcode },
4066     { "pblendvb", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4067   },
4068
4069   /* PREFIX_0F3814 */
4070   {
4071     { Bad_Opcode },
4072     { Bad_Opcode },
4073     { "blendvps", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4074   },
4075
4076   /* PREFIX_0F3815 */
4077   {
4078     { Bad_Opcode },
4079     { Bad_Opcode },
4080     { "blendvpd", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4081   },
4082
4083   /* PREFIX_0F3817 */
4084   {
4085     { Bad_Opcode },
4086     { Bad_Opcode },
4087     { "ptest",  { XM, EXx }, PREFIX_OPCODE },
4088   },
4089
4090   /* PREFIX_0F3820 */
4091   {
4092     { Bad_Opcode },
4093     { Bad_Opcode },
4094     { "pmovsxbw", { XM, EXq }, PREFIX_OPCODE },
4095   },
4096
4097   /* PREFIX_0F3821 */
4098   {
4099     { Bad_Opcode },
4100     { Bad_Opcode },
4101     { "pmovsxbd", { XM, EXd }, PREFIX_OPCODE },
4102   },
4103
4104   /* PREFIX_0F3822 */
4105   {
4106     { Bad_Opcode },
4107     { Bad_Opcode },
4108     { "pmovsxbq", { XM, EXw }, PREFIX_OPCODE },
4109   },
4110
4111   /* PREFIX_0F3823 */
4112   {
4113     { Bad_Opcode },
4114     { Bad_Opcode },
4115     { "pmovsxwd", { XM, EXq }, PREFIX_OPCODE },
4116   },
4117
4118   /* PREFIX_0F3824 */
4119   {
4120     { Bad_Opcode },
4121     { Bad_Opcode },
4122     { "pmovsxwq", { XM, EXd }, PREFIX_OPCODE },
4123   },
4124
4125   /* PREFIX_0F3825 */
4126   {
4127     { Bad_Opcode },
4128     { Bad_Opcode },
4129     { "pmovsxdq", { XM, EXq }, PREFIX_OPCODE },
4130   },
4131
4132   /* PREFIX_0F3828 */
4133   {
4134     { Bad_Opcode },
4135     { Bad_Opcode },
4136     { "pmuldq", { XM, EXx }, PREFIX_OPCODE },
4137   },
4138
4139   /* PREFIX_0F3829 */
4140   {
4141     { Bad_Opcode },
4142     { Bad_Opcode },
4143     { "pcmpeqq", { XM, EXx }, PREFIX_OPCODE },
4144   },
4145
4146   /* PREFIX_0F382A */
4147   {
4148     { Bad_Opcode },
4149     { Bad_Opcode },
4150     { MOD_TABLE (MOD_0F382A_PREFIX_2) },
4151   },
4152
4153   /* PREFIX_0F382B */
4154   {
4155     { Bad_Opcode },
4156     { Bad_Opcode },
4157     { "packusdw", { XM, EXx }, PREFIX_OPCODE },
4158   },
4159
4160   /* PREFIX_0F3830 */
4161   {
4162     { Bad_Opcode },
4163     { Bad_Opcode },
4164     { "pmovzxbw", { XM, EXq }, PREFIX_OPCODE },
4165   },
4166
4167   /* PREFIX_0F3831 */
4168   {
4169     { Bad_Opcode },
4170     { Bad_Opcode },
4171     { "pmovzxbd", { XM, EXd }, PREFIX_OPCODE },
4172   },
4173
4174   /* PREFIX_0F3832 */
4175   {
4176     { Bad_Opcode },
4177     { Bad_Opcode },
4178     { "pmovzxbq", { XM, EXw }, PREFIX_OPCODE },
4179   },
4180
4181   /* PREFIX_0F3833 */
4182   {
4183     { Bad_Opcode },
4184     { Bad_Opcode },
4185     { "pmovzxwd", { XM, EXq }, PREFIX_OPCODE },
4186   },
4187
4188   /* PREFIX_0F3834 */
4189   {
4190     { Bad_Opcode },
4191     { Bad_Opcode },
4192     { "pmovzxwq", { XM, EXd }, PREFIX_OPCODE },
4193   },
4194
4195   /* PREFIX_0F3835 */
4196   {
4197     { Bad_Opcode },
4198     { Bad_Opcode },
4199     { "pmovzxdq", { XM, EXq }, PREFIX_OPCODE },
4200   },
4201
4202   /* PREFIX_0F3837 */
4203   {
4204     { Bad_Opcode },
4205     { Bad_Opcode },
4206     { "pcmpgtq", { XM, EXx }, PREFIX_OPCODE },
4207   },
4208
4209   /* PREFIX_0F3838 */
4210   {
4211     { Bad_Opcode },
4212     { Bad_Opcode },
4213     { "pminsb", { XM, EXx }, PREFIX_OPCODE },
4214   },
4215
4216   /* PREFIX_0F3839 */
4217   {
4218     { Bad_Opcode },
4219     { Bad_Opcode },
4220     { "pminsd", { XM, EXx }, PREFIX_OPCODE },
4221   },
4222
4223   /* PREFIX_0F383A */
4224   {
4225     { Bad_Opcode },
4226     { Bad_Opcode },
4227     { "pminuw", { XM, EXx }, PREFIX_OPCODE },
4228   },
4229
4230   /* PREFIX_0F383B */
4231   {
4232     { Bad_Opcode },
4233     { Bad_Opcode },
4234     { "pminud", { XM, EXx }, PREFIX_OPCODE },
4235   },
4236
4237   /* PREFIX_0F383C */
4238   {
4239     { Bad_Opcode },
4240     { Bad_Opcode },
4241     { "pmaxsb", { XM, EXx }, PREFIX_OPCODE },
4242   },
4243
4244   /* PREFIX_0F383D */
4245   {
4246     { Bad_Opcode },
4247     { Bad_Opcode },
4248     { "pmaxsd", { XM, EXx }, PREFIX_OPCODE },
4249   },
4250
4251   /* PREFIX_0F383E */
4252   {
4253     { Bad_Opcode },
4254     { Bad_Opcode },
4255     { "pmaxuw", { XM, EXx }, PREFIX_OPCODE },
4256   },
4257
4258   /* PREFIX_0F383F */
4259   {
4260     { Bad_Opcode },
4261     { Bad_Opcode },
4262     { "pmaxud", { XM, EXx }, PREFIX_OPCODE },
4263   },
4264
4265   /* PREFIX_0F3840 */
4266   {
4267     { Bad_Opcode },
4268     { Bad_Opcode },
4269     { "pmulld", { XM, EXx }, PREFIX_OPCODE },
4270   },
4271
4272   /* PREFIX_0F3841 */
4273   {
4274     { Bad_Opcode },
4275     { Bad_Opcode },
4276     { "phminposuw", { XM, EXx }, PREFIX_OPCODE },
4277   },
4278
4279   /* PREFIX_0F3880 */
4280   {
4281     { Bad_Opcode },
4282     { Bad_Opcode },
4283     { "invept", { Gm, Mo }, PREFIX_OPCODE },
4284   },
4285
4286   /* PREFIX_0F3881 */
4287   {
4288     { Bad_Opcode },
4289     { Bad_Opcode },
4290     { "invvpid", { Gm, Mo }, PREFIX_OPCODE },
4291   },
4292
4293   /* PREFIX_0F3882 */
4294   {
4295     { Bad_Opcode },
4296     { Bad_Opcode },
4297     { "invpcid", { Gm, M }, PREFIX_OPCODE },
4298   },
4299
4300   /* PREFIX_0F38C8 */
4301   {
4302     { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE },
4303   },
4304
4305   /* PREFIX_0F38C9 */
4306   {
4307     { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE },
4308   },
4309
4310   /* PREFIX_0F38CA */
4311   {
4312     { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE },
4313   },
4314
4315   /* PREFIX_0F38CB */
4316   {
4317     { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE },
4318   },
4319
4320   /* PREFIX_0F38CC */
4321   {
4322     { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE },
4323   },
4324
4325   /* PREFIX_0F38CD */
4326   {
4327     { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE },
4328   },
4329
4330   /* PREFIX_0F38CF */
4331   {
4332     { Bad_Opcode },
4333     { Bad_Opcode },
4334     { "gf2p8mulb", { XM, EXxmm }, PREFIX_OPCODE },
4335   },
4336
4337   /* PREFIX_0F38DB */
4338   {
4339     { Bad_Opcode },
4340     { Bad_Opcode },
4341     { "aesimc", { XM, EXx }, PREFIX_OPCODE },
4342   },
4343
4344   /* PREFIX_0F38DC */
4345   {
4346     { Bad_Opcode },
4347     { Bad_Opcode },
4348     { "aesenc", { XM, EXx }, PREFIX_OPCODE },
4349   },
4350
4351   /* PREFIX_0F38DD */
4352   {
4353     { Bad_Opcode },
4354     { Bad_Opcode },
4355     { "aesenclast", { XM, EXx }, PREFIX_OPCODE },
4356   },
4357
4358   /* PREFIX_0F38DE */
4359   {
4360     { Bad_Opcode },
4361     { Bad_Opcode },
4362     { "aesdec", { XM, EXx }, PREFIX_OPCODE },
4363   },
4364
4365   /* PREFIX_0F38DF */
4366   {
4367     { Bad_Opcode },
4368     { Bad_Opcode },
4369     { "aesdeclast", { XM, EXx }, PREFIX_OPCODE },
4370   },
4371
4372   /* PREFIX_0F38F0 */
4373   {
4374     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4375     { Bad_Opcode },
4376     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4377     { "crc32",  { Gdq, { CRC32_Fixup, b_mode } }, PREFIX_OPCODE },
4378   },
4379
4380   /* PREFIX_0F38F1 */
4381   {
4382     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4383     { Bad_Opcode },
4384     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4385     { "crc32",  { Gdq, { CRC32_Fixup, v_mode } }, PREFIX_OPCODE },
4386   },
4387
4388   /* PREFIX_0F38F5 */
4389   {
4390     { Bad_Opcode },
4391     { Bad_Opcode },
4392     { MOD_TABLE (MOD_0F38F5_PREFIX_2) },
4393   },
4394
4395   /* PREFIX_0F38F6 */
4396   {
4397     { MOD_TABLE (MOD_0F38F6_PREFIX_0) },
4398     { "adoxS",  { Gdq, Edq}, PREFIX_OPCODE },
4399     { "adcxS",  { Gdq, Edq}, PREFIX_OPCODE },
4400     { Bad_Opcode },
4401   },
4402
4403   /* PREFIX_0F38F8 */
4404   {
4405     { Bad_Opcode },
4406     { MOD_TABLE (MOD_0F38F8_PREFIX_1) },
4407     { MOD_TABLE (MOD_0F38F8_PREFIX_2) },
4408     { MOD_TABLE (MOD_0F38F8_PREFIX_3) },
4409   },
4410
4411   /* PREFIX_0F38F9 */
4412   {
4413     { MOD_TABLE (MOD_0F38F9_PREFIX_0) },
4414   },
4415
4416   /* PREFIX_0F3A08 */
4417   {
4418     { Bad_Opcode },
4419     { Bad_Opcode },
4420     { "roundps", { XM, EXx, Ib }, PREFIX_OPCODE },
4421   },
4422
4423   /* PREFIX_0F3A09 */
4424   {
4425     { Bad_Opcode },
4426     { Bad_Opcode },
4427     { "roundpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4428   },
4429
4430   /* PREFIX_0F3A0A */
4431   {
4432     { Bad_Opcode },
4433     { Bad_Opcode },
4434     { "roundss", { XM, EXd, Ib }, PREFIX_OPCODE },
4435   },
4436
4437   /* PREFIX_0F3A0B */
4438   {
4439     { Bad_Opcode },
4440     { Bad_Opcode },
4441     { "roundsd", { XM, EXq, Ib }, PREFIX_OPCODE },
4442   },
4443
4444   /* PREFIX_0F3A0C */
4445   {
4446     { Bad_Opcode },
4447     { Bad_Opcode },
4448     { "blendps", { XM, EXx, Ib }, PREFIX_OPCODE },
4449   },
4450
4451   /* PREFIX_0F3A0D */
4452   {
4453     { Bad_Opcode },
4454     { Bad_Opcode },
4455     { "blendpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4456   },
4457
4458   /* PREFIX_0F3A0E */
4459   {
4460     { Bad_Opcode },
4461     { Bad_Opcode },
4462     { "pblendw", { XM, EXx, Ib }, PREFIX_OPCODE },
4463   },
4464
4465   /* PREFIX_0F3A14 */
4466   {
4467     { Bad_Opcode },
4468     { Bad_Opcode },
4469     { "pextrb", { Edqb, XM, Ib }, PREFIX_OPCODE },
4470   },
4471
4472   /* PREFIX_0F3A15 */
4473   {
4474     { Bad_Opcode },
4475     { Bad_Opcode },
4476     { "pextrw", { Edqw, XM, Ib }, PREFIX_OPCODE },
4477   },
4478
4479   /* PREFIX_0F3A16 */
4480   {
4481     { Bad_Opcode },
4482     { Bad_Opcode },
4483     { "pextrK", { Edq, XM, Ib }, PREFIX_OPCODE },
4484   },
4485
4486   /* PREFIX_0F3A17 */
4487   {
4488     { Bad_Opcode },
4489     { Bad_Opcode },
4490     { "extractps", { Edqd, XM, Ib }, PREFIX_OPCODE },
4491   },
4492
4493   /* PREFIX_0F3A20 */
4494   {
4495     { Bad_Opcode },
4496     { Bad_Opcode },
4497     { "pinsrb", { XM, Edqb, Ib }, PREFIX_OPCODE },
4498   },
4499
4500   /* PREFIX_0F3A21 */
4501   {
4502     { Bad_Opcode },
4503     { Bad_Opcode },
4504     { "insertps", { XM, EXd, Ib }, PREFIX_OPCODE },
4505   },
4506
4507   /* PREFIX_0F3A22 */
4508   {
4509     { Bad_Opcode },
4510     { Bad_Opcode },
4511     { "pinsrK", { XM, Edq, Ib }, PREFIX_OPCODE },
4512   },
4513
4514   /* PREFIX_0F3A40 */
4515   {
4516     { Bad_Opcode },
4517     { Bad_Opcode },
4518     { "dpps",   { XM, EXx, Ib }, PREFIX_OPCODE },
4519   },
4520
4521   /* PREFIX_0F3A41 */
4522   {
4523     { Bad_Opcode },
4524     { Bad_Opcode },
4525     { "dppd",   { XM, EXx, Ib }, PREFIX_OPCODE },
4526   },
4527
4528   /* PREFIX_0F3A42 */
4529   {
4530     { Bad_Opcode },
4531     { Bad_Opcode },
4532     { "mpsadbw", { XM, EXx, Ib }, PREFIX_OPCODE },
4533   },
4534
4535   /* PREFIX_0F3A44 */
4536   {
4537     { Bad_Opcode },
4538     { Bad_Opcode },
4539     { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_OPCODE },
4540   },
4541
4542   /* PREFIX_0F3A60 */
4543   {
4544     { Bad_Opcode },
4545     { Bad_Opcode },
4546     { "pcmpestrm", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE },
4547   },
4548
4549   /* PREFIX_0F3A61 */
4550   {
4551     { Bad_Opcode },
4552     { Bad_Opcode },
4553     { "pcmpestri", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE },
4554   },
4555
4556   /* PREFIX_0F3A62 */
4557   {
4558     { Bad_Opcode },
4559     { Bad_Opcode },
4560     { "pcmpistrm", { XM, EXx, Ib }, PREFIX_OPCODE },
4561   },
4562
4563   /* PREFIX_0F3A63 */
4564   {
4565     { Bad_Opcode },
4566     { Bad_Opcode },
4567     { "pcmpistri", { XM, EXx, Ib }, PREFIX_OPCODE },
4568   },
4569
4570   /* PREFIX_0F3ACC */
4571   {
4572     { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4573   },
4574
4575   /* PREFIX_0F3ACE */
4576   {
4577     { Bad_Opcode },
4578     { Bad_Opcode },
4579     { "gf2p8affineqb", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4580   },
4581
4582   /* PREFIX_0F3ACF */
4583   {
4584     { Bad_Opcode },
4585     { Bad_Opcode },
4586     { "gf2p8affineinvqb", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4587   },
4588
4589   /* PREFIX_0F3ADF */
4590   {
4591     { Bad_Opcode },
4592     { Bad_Opcode },
4593     { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_OPCODE },
4594   },
4595
4596   /* PREFIX_VEX_0F10 */
4597   {
4598     { "vmovups",        { XM, EXx }, 0 },
4599     { "vmovss",         { XMVexScalar, VexScalar, EXxmm_md }, 0 },
4600     { "vmovupd",        { XM, EXx }, 0 },
4601     { "vmovsd",         { XMVexScalar, VexScalar, EXxmm_mq }, 0 },
4602   },
4603
4604   /* PREFIX_VEX_0F11 */
4605   {
4606     { "vmovups",        { EXxS, XM }, 0 },
4607     { "vmovss",         { EXdVexScalarS, VexScalar, XMScalar }, 0 },
4608     { "vmovupd",        { EXxS, XM }, 0 },
4609     { "vmovsd",         { EXqVexScalarS, VexScalar, XMScalar }, 0 },
4610   },
4611
4612   /* PREFIX_VEX_0F12 */
4613   {
4614     { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
4615     { "vmovsldup",      { XM, EXx }, 0 },
4616     { MOD_TABLE (MOD_VEX_0F12_PREFIX_2) },
4617     { "vmovddup",       { XM, EXymmq }, 0 },
4618   },
4619
4620   /* PREFIX_VEX_0F16 */
4621   {
4622     { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
4623     { "vmovshdup",      { XM, EXx }, 0 },
4624     { MOD_TABLE (MOD_VEX_0F16_PREFIX_2) },
4625   },
4626
4627   /* PREFIX_VEX_0F2A */
4628   {
4629     { Bad_Opcode },
4630     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Edq }, 0 },
4631     { Bad_Opcode },
4632     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Edq }, 0 },
4633   },
4634
4635   /* PREFIX_VEX_0F2C */
4636   {
4637     { Bad_Opcode },
4638     { "vcvttss2si",     { Gdq, EXxmm_md }, 0 },
4639     { Bad_Opcode },
4640     { "vcvttsd2si",     { Gdq, EXxmm_mq }, 0 },
4641   },
4642
4643   /* PREFIX_VEX_0F2D */
4644   {
4645     { Bad_Opcode },
4646     { "vcvtss2si",      { Gdq, EXxmm_md }, 0 },
4647     { Bad_Opcode },
4648     { "vcvtsd2si",      { Gdq, EXxmm_mq }, 0 },
4649   },
4650
4651   /* PREFIX_VEX_0F2E */
4652   {
4653     { "vucomiss",       { XMScalar, EXxmm_md }, 0 },
4654     { Bad_Opcode },
4655     { "vucomisd",       { XMScalar, EXxmm_mq }, 0 },
4656   },
4657
4658   /* PREFIX_VEX_0F2F */
4659   {
4660     { "vcomiss",        { XMScalar, EXxmm_md }, 0 },
4661     { Bad_Opcode },
4662     { "vcomisd",        { XMScalar, EXxmm_mq }, 0 },
4663   },
4664
4665   /* PREFIX_VEX_0F41 */
4666   {
4667     { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) },
4668     { Bad_Opcode },
4669     { VEX_LEN_TABLE (VEX_LEN_0F41_P_2) },
4670   },
4671
4672   /* PREFIX_VEX_0F42 */
4673   {
4674     { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) },
4675     { Bad_Opcode },
4676     { VEX_LEN_TABLE (VEX_LEN_0F42_P_2) },
4677   },
4678
4679   /* PREFIX_VEX_0F44 */
4680   {
4681     { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) },
4682     { Bad_Opcode },
4683     { VEX_LEN_TABLE (VEX_LEN_0F44_P_2) },
4684   },
4685
4686   /* PREFIX_VEX_0F45 */
4687   {
4688     { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) },
4689     { Bad_Opcode },
4690     { VEX_LEN_TABLE (VEX_LEN_0F45_P_2) },
4691   },
4692
4693   /* PREFIX_VEX_0F46 */
4694   {
4695     { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) },
4696     { Bad_Opcode },
4697     { VEX_LEN_TABLE (VEX_LEN_0F46_P_2) },
4698   },
4699
4700   /* PREFIX_VEX_0F47 */
4701   {
4702     { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) },
4703     { Bad_Opcode },
4704     { VEX_LEN_TABLE (VEX_LEN_0F47_P_2) },
4705   },
4706
4707   /* PREFIX_VEX_0F4A */
4708   {
4709     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0) },
4710     { Bad_Opcode },
4711     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2) },
4712   },
4713
4714   /* PREFIX_VEX_0F4B */
4715   {
4716     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0) },
4717     { Bad_Opcode },
4718     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) },
4719   },
4720
4721   /* PREFIX_VEX_0F51 */
4722   {
4723     { "vsqrtps",        { XM, EXx }, 0 },
4724     { "vsqrtss",        { XMScalar, VexScalar, EXxmm_md }, 0 },
4725     { "vsqrtpd",        { XM, EXx }, 0 },
4726     { "vsqrtsd",        { XMScalar, VexScalar, EXxmm_mq }, 0 },
4727   },
4728
4729   /* PREFIX_VEX_0F52 */
4730   {
4731     { "vrsqrtps",       { XM, EXx }, 0 },
4732     { "vrsqrtss",       { XMScalar, VexScalar, EXxmm_md }, 0 },
4733   },
4734
4735   /* PREFIX_VEX_0F53 */
4736   {
4737     { "vrcpps",         { XM, EXx }, 0 },
4738     { "vrcpss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
4739   },
4740
4741   /* PREFIX_VEX_0F58 */
4742   {
4743     { "vaddps",         { XM, Vex, EXx }, 0 },
4744     { "vaddss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
4745     { "vaddpd",         { XM, Vex, EXx }, 0 },
4746     { "vaddsd",         { XMScalar, VexScalar, EXxmm_mq }, 0 },
4747   },
4748
4749   /* PREFIX_VEX_0F59 */
4750   {
4751     { "vmulps",         { XM, Vex, EXx }, 0 },
4752     { "vmulss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
4753     { "vmulpd",         { XM, Vex, EXx }, 0 },
4754     { "vmulsd",         { XMScalar, VexScalar, EXxmm_mq }, 0 },
4755   },
4756
4757   /* PREFIX_VEX_0F5A */
4758   {
4759     { "vcvtps2pd",      { XM, EXxmmq }, 0 },
4760     { "vcvtss2sd",      { XMScalar, VexScalar, EXxmm_md }, 0 },
4761     { "vcvtpd2ps%XY",{ XMM, EXx }, 0 },
4762     { "vcvtsd2ss",      { XMScalar, VexScalar, EXxmm_mq }, 0 },
4763   },
4764
4765   /* PREFIX_VEX_0F5B */
4766   {
4767     { "vcvtdq2ps",      { XM, EXx }, 0 },
4768     { "vcvttps2dq",     { XM, EXx }, 0 },
4769     { "vcvtps2dq",      { XM, EXx }, 0 },
4770   },
4771
4772   /* PREFIX_VEX_0F5C */
4773   {
4774     { "vsubps",         { XM, Vex, EXx }, 0 },
4775     { "vsubss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
4776     { "vsubpd",         { XM, Vex, EXx }, 0 },
4777     { "vsubsd",         { XMScalar, VexScalar, EXxmm_mq }, 0 },
4778   },
4779
4780   /* PREFIX_VEX_0F5D */
4781   {
4782     { "vminps",         { XM, Vex, EXx }, 0 },
4783     { "vminss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
4784     { "vminpd",         { XM, Vex, EXx }, 0 },
4785     { "vminsd",         { XMScalar, VexScalar, EXxmm_mq }, 0 },
4786   },
4787
4788   /* PREFIX_VEX_0F5E */
4789   {
4790     { "vdivps",         { XM, Vex, EXx }, 0 },
4791     { "vdivss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
4792     { "vdivpd",         { XM, Vex, EXx }, 0 },
4793     { "vdivsd",         { XMScalar, VexScalar, EXxmm_mq }, 0 },
4794   },
4795
4796   /* PREFIX_VEX_0F5F */
4797   {
4798     { "vmaxps",         { XM, Vex, EXx }, 0 },
4799     { "vmaxss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
4800     { "vmaxpd",         { XM, Vex, EXx }, 0 },
4801     { "vmaxsd",         { XMScalar, VexScalar, EXxmm_mq }, 0 },
4802   },
4803
4804   /* PREFIX_VEX_0F60 */
4805   {
4806     { Bad_Opcode },
4807     { Bad_Opcode },
4808     { "vpunpcklbw",     { XM, Vex, EXx }, 0 },
4809   },
4810
4811   /* PREFIX_VEX_0F61 */
4812   {
4813     { Bad_Opcode },
4814     { Bad_Opcode },
4815     { "vpunpcklwd",     { XM, Vex, EXx }, 0 },
4816   },
4817
4818   /* PREFIX_VEX_0F62 */
4819   {
4820     { Bad_Opcode },
4821     { Bad_Opcode },
4822     { "vpunpckldq",     { XM, Vex, EXx }, 0 },
4823   },
4824
4825   /* PREFIX_VEX_0F63 */
4826   {
4827     { Bad_Opcode },
4828     { Bad_Opcode },
4829     { "vpacksswb",      { XM, Vex, EXx }, 0 },
4830   },
4831
4832   /* PREFIX_VEX_0F64 */
4833   {
4834     { Bad_Opcode },
4835     { Bad_Opcode },
4836     { "vpcmpgtb",       { XM, Vex, EXx }, 0 },
4837   },
4838
4839   /* PREFIX_VEX_0F65 */
4840   {
4841     { Bad_Opcode },
4842     { Bad_Opcode },
4843     { "vpcmpgtw",       { XM, Vex, EXx }, 0 },
4844   },
4845
4846   /* PREFIX_VEX_0F66 */
4847   {
4848     { Bad_Opcode },
4849     { Bad_Opcode },
4850     { "vpcmpgtd",       { XM, Vex, EXx }, 0 },
4851   },
4852
4853   /* PREFIX_VEX_0F67 */
4854   {
4855     { Bad_Opcode },
4856     { Bad_Opcode },
4857     { "vpackuswb",      { XM, Vex, EXx }, 0 },
4858   },
4859
4860   /* PREFIX_VEX_0F68 */
4861   {
4862     { Bad_Opcode },
4863     { Bad_Opcode },
4864     { "vpunpckhbw",     { XM, Vex, EXx }, 0 },
4865   },
4866
4867   /* PREFIX_VEX_0F69 */
4868   {
4869     { Bad_Opcode },
4870     { Bad_Opcode },
4871     { "vpunpckhwd",     { XM, Vex, EXx }, 0 },
4872   },
4873
4874   /* PREFIX_VEX_0F6A */
4875   {
4876     { Bad_Opcode },
4877     { Bad_Opcode },
4878     { "vpunpckhdq",     { XM, Vex, EXx }, 0 },
4879   },
4880
4881   /* PREFIX_VEX_0F6B */
4882   {
4883     { Bad_Opcode },
4884     { Bad_Opcode },
4885     { "vpackssdw",      { XM, Vex, EXx }, 0 },
4886   },
4887
4888   /* PREFIX_VEX_0F6C */
4889   {
4890     { Bad_Opcode },
4891     { Bad_Opcode },
4892     { "vpunpcklqdq",    { XM, Vex, EXx }, 0 },
4893   },
4894
4895   /* PREFIX_VEX_0F6D */
4896   {
4897     { Bad_Opcode },
4898     { Bad_Opcode },
4899     { "vpunpckhqdq",    { XM, Vex, EXx }, 0 },
4900   },
4901
4902   /* PREFIX_VEX_0F6E */
4903   {
4904     { Bad_Opcode },
4905     { Bad_Opcode },
4906     { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) },
4907   },
4908
4909   /* PREFIX_VEX_0F6F */
4910   {
4911     { Bad_Opcode },
4912     { "vmovdqu",        { XM, EXx }, 0 },
4913     { "vmovdqa",        { XM, EXx }, 0 },
4914   },
4915
4916   /* PREFIX_VEX_0F70 */
4917   {
4918     { Bad_Opcode },
4919     { "vpshufhw",       { XM, EXx, Ib }, 0 },
4920     { "vpshufd",        { XM, EXx, Ib }, 0 },
4921     { "vpshuflw",       { XM, EXx, Ib }, 0 },
4922   },
4923
4924   /* PREFIX_VEX_0F71_REG_2 */
4925   {
4926     { Bad_Opcode },
4927     { Bad_Opcode },
4928     { "vpsrlw",         { Vex, XS, Ib }, 0 },
4929   },
4930
4931   /* PREFIX_VEX_0F71_REG_4 */
4932   {
4933     { Bad_Opcode },
4934     { Bad_Opcode },
4935     { "vpsraw",         { Vex, XS, Ib }, 0 },
4936   },
4937
4938   /* PREFIX_VEX_0F71_REG_6 */
4939   {
4940     { Bad_Opcode },
4941     { Bad_Opcode },
4942     { "vpsllw",         { Vex, XS, Ib }, 0 },
4943   },
4944
4945   /* PREFIX_VEX_0F72_REG_2 */
4946   {
4947     { Bad_Opcode },
4948     { Bad_Opcode },
4949     { "vpsrld",         { Vex, XS, Ib }, 0 },
4950   },
4951
4952   /* PREFIX_VEX_0F72_REG_4 */
4953   {
4954     { Bad_Opcode },
4955     { Bad_Opcode },
4956     { "vpsrad",         { Vex, XS, Ib }, 0 },
4957   },
4958
4959   /* PREFIX_VEX_0F72_REG_6 */
4960   {
4961     { Bad_Opcode },
4962     { Bad_Opcode },
4963     { "vpslld",         { Vex, XS, Ib }, 0 },
4964   },
4965
4966   /* PREFIX_VEX_0F73_REG_2 */
4967   {
4968     { Bad_Opcode },
4969     { Bad_Opcode },
4970     { "vpsrlq",         { Vex, XS, Ib }, 0 },
4971   },
4972
4973   /* PREFIX_VEX_0F73_REG_3 */
4974   {
4975     { Bad_Opcode },
4976     { Bad_Opcode },
4977     { "vpsrldq",        { Vex, XS, Ib }, 0 },
4978   },
4979
4980   /* PREFIX_VEX_0F73_REG_6 */
4981   {
4982     { Bad_Opcode },
4983     { Bad_Opcode },
4984     { "vpsllq",         { Vex, XS, Ib }, 0 },
4985   },
4986
4987   /* PREFIX_VEX_0F73_REG_7 */
4988   {
4989     { Bad_Opcode },
4990     { Bad_Opcode },
4991     { "vpslldq",        { Vex, XS, Ib }, 0 },
4992   },
4993
4994   /* PREFIX_VEX_0F74 */
4995   {
4996     { Bad_Opcode },
4997     { Bad_Opcode },
4998     { "vpcmpeqb",       { XM, Vex, EXx }, 0 },
4999   },
5000
5001   /* PREFIX_VEX_0F75 */
5002   {
5003     { Bad_Opcode },
5004     { Bad_Opcode },
5005     { "vpcmpeqw",       { XM, Vex, EXx }, 0 },
5006   },
5007
5008   /* PREFIX_VEX_0F76 */
5009   {
5010     { Bad_Opcode },
5011     { Bad_Opcode },
5012     { "vpcmpeqd",       { XM, Vex, EXx }, 0 },
5013   },
5014
5015   /* PREFIX_VEX_0F77 */
5016   {
5017     { VEX_LEN_TABLE (VEX_LEN_0F77_P_0) },
5018   },
5019
5020   /* PREFIX_VEX_0F7C */
5021   {
5022     { Bad_Opcode },
5023     { Bad_Opcode },
5024     { "vhaddpd",        { XM, Vex, EXx }, 0 },
5025     { "vhaddps",        { XM, Vex, EXx }, 0 },
5026   },
5027
5028   /* PREFIX_VEX_0F7D */
5029   {
5030     { Bad_Opcode },
5031     { Bad_Opcode },
5032     { "vhsubpd",        { XM, Vex, EXx }, 0 },
5033     { "vhsubps",        { XM, Vex, EXx }, 0 },
5034   },
5035
5036   /* PREFIX_VEX_0F7E */
5037   {
5038     { Bad_Opcode },
5039     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
5040     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
5041   },
5042
5043   /* PREFIX_VEX_0F7F */
5044   {
5045     { Bad_Opcode },
5046     { "vmovdqu",        { EXxS, XM }, 0 },
5047     { "vmovdqa",        { EXxS, XM }, 0 },
5048   },
5049
5050   /* PREFIX_VEX_0F90 */
5051   {
5052     { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) },
5053     { Bad_Opcode },
5054     { VEX_LEN_TABLE (VEX_LEN_0F90_P_2) },
5055   },
5056
5057   /* PREFIX_VEX_0F91 */
5058   {
5059     { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) },
5060     { Bad_Opcode },
5061     { VEX_LEN_TABLE (VEX_LEN_0F91_P_2) },
5062   },
5063
5064   /* PREFIX_VEX_0F92 */
5065   {
5066     { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) },
5067     { Bad_Opcode },
5068     { VEX_LEN_TABLE (VEX_LEN_0F92_P_2) },
5069     { VEX_LEN_TABLE (VEX_LEN_0F92_P_3) },
5070   },
5071
5072   /* PREFIX_VEX_0F93 */
5073   {
5074     { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) },
5075     { Bad_Opcode },
5076     { VEX_LEN_TABLE (VEX_LEN_0F93_P_2) },
5077     { VEX_LEN_TABLE (VEX_LEN_0F93_P_3) },
5078   },
5079
5080   /* PREFIX_VEX_0F98 */
5081   {
5082     { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) },
5083     { Bad_Opcode },
5084     { VEX_LEN_TABLE (VEX_LEN_0F98_P_2) },
5085   },
5086
5087   /* PREFIX_VEX_0F99 */
5088   {
5089     { VEX_LEN_TABLE (VEX_LEN_0F99_P_0) },
5090     { Bad_Opcode },
5091     { VEX_LEN_TABLE (VEX_LEN_0F99_P_2) },
5092   },
5093
5094   /* PREFIX_VEX_0FC2 */
5095   {
5096     { "vcmpps",         { XM, Vex, EXx, VCMP }, 0 },
5097     { "vcmpss",         { XMScalar, VexScalar, EXxmm_md, VCMP }, 0 },
5098     { "vcmppd",         { XM, Vex, EXx, VCMP }, 0 },
5099     { "vcmpsd",         { XMScalar, VexScalar, EXxmm_mq, VCMP }, 0 },
5100   },
5101
5102   /* PREFIX_VEX_0FC4 */
5103   {
5104     { Bad_Opcode },
5105     { Bad_Opcode },
5106     { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) },
5107   },
5108
5109   /* PREFIX_VEX_0FC5 */
5110   {
5111     { Bad_Opcode },
5112     { Bad_Opcode },
5113     { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) },
5114   },
5115
5116   /* PREFIX_VEX_0FD0 */
5117   {
5118     { Bad_Opcode },
5119     { Bad_Opcode },
5120     { "vaddsubpd",      { XM, Vex, EXx }, 0 },
5121     { "vaddsubps",      { XM, Vex, EXx }, 0 },
5122   },
5123
5124   /* PREFIX_VEX_0FD1 */
5125   {
5126     { Bad_Opcode },
5127     { Bad_Opcode },
5128     { "vpsrlw",         { XM, Vex, EXxmm }, 0 },
5129   },
5130
5131   /* PREFIX_VEX_0FD2 */
5132   {
5133     { Bad_Opcode },
5134     { Bad_Opcode },
5135     { "vpsrld",         { XM, Vex, EXxmm }, 0 },
5136   },
5137
5138   /* PREFIX_VEX_0FD3 */
5139   {
5140     { Bad_Opcode },
5141     { Bad_Opcode },
5142     { "vpsrlq",         { XM, Vex, EXxmm }, 0 },
5143   },
5144
5145   /* PREFIX_VEX_0FD4 */
5146   {
5147     { Bad_Opcode },
5148     { Bad_Opcode },
5149     { "vpaddq",         { XM, Vex, EXx }, 0 },
5150   },
5151
5152   /* PREFIX_VEX_0FD5 */
5153   {
5154     { Bad_Opcode },
5155     { Bad_Opcode },
5156     { "vpmullw",        { XM, Vex, EXx }, 0 },
5157   },
5158
5159   /* PREFIX_VEX_0FD6 */
5160   {
5161     { Bad_Opcode },
5162     { Bad_Opcode },
5163     { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) },
5164   },
5165
5166   /* PREFIX_VEX_0FD7 */
5167   {
5168     { Bad_Opcode },
5169     { Bad_Opcode },
5170     { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) },
5171   },
5172
5173   /* PREFIX_VEX_0FD8 */
5174   {
5175     { Bad_Opcode },
5176     { Bad_Opcode },
5177     { "vpsubusb",       { XM, Vex, EXx }, 0 },
5178   },
5179
5180   /* PREFIX_VEX_0FD9 */
5181   {
5182     { Bad_Opcode },
5183     { Bad_Opcode },
5184     { "vpsubusw",       { XM, Vex, EXx }, 0 },
5185   },
5186
5187   /* PREFIX_VEX_0FDA */
5188   {
5189     { Bad_Opcode },
5190     { Bad_Opcode },
5191     { "vpminub",        { XM, Vex, EXx }, 0 },
5192   },
5193
5194   /* PREFIX_VEX_0FDB */
5195   {
5196     { Bad_Opcode },
5197     { Bad_Opcode },
5198     { "vpand",          { XM, Vex, EXx }, 0 },
5199   },
5200
5201   /* PREFIX_VEX_0FDC */
5202   {
5203     { Bad_Opcode },
5204     { Bad_Opcode },
5205     { "vpaddusb",       { XM, Vex, EXx }, 0 },
5206   },
5207
5208   /* PREFIX_VEX_0FDD */
5209   {
5210     { Bad_Opcode },
5211     { Bad_Opcode },
5212     { "vpaddusw",       { XM, Vex, EXx }, 0 },
5213   },
5214
5215   /* PREFIX_VEX_0FDE */
5216   {
5217     { Bad_Opcode },
5218     { Bad_Opcode },
5219     { "vpmaxub",        { XM, Vex, EXx }, 0 },
5220   },
5221
5222   /* PREFIX_VEX_0FDF */
5223   {
5224     { Bad_Opcode },
5225     { Bad_Opcode },
5226     { "vpandn",         { XM, Vex, EXx }, 0 },
5227   },
5228
5229   /* PREFIX_VEX_0FE0 */
5230   {
5231     { Bad_Opcode },
5232     { Bad_Opcode },
5233     { "vpavgb",         { XM, Vex, EXx }, 0 },
5234   },
5235
5236   /* PREFIX_VEX_0FE1 */
5237   {
5238     { Bad_Opcode },
5239     { Bad_Opcode },
5240     { "vpsraw",         { XM, Vex, EXxmm }, 0 },
5241   },
5242
5243   /* PREFIX_VEX_0FE2 */
5244   {
5245     { Bad_Opcode },
5246     { Bad_Opcode },
5247     { "vpsrad",         { XM, Vex, EXxmm }, 0 },
5248   },
5249
5250   /* PREFIX_VEX_0FE3 */
5251   {
5252     { Bad_Opcode },
5253     { Bad_Opcode },
5254     { "vpavgw",         { XM, Vex, EXx }, 0 },
5255   },
5256
5257   /* PREFIX_VEX_0FE4 */
5258   {
5259     { Bad_Opcode },
5260     { Bad_Opcode },
5261     { "vpmulhuw",       { XM, Vex, EXx }, 0 },
5262   },
5263
5264   /* PREFIX_VEX_0FE5 */
5265   {
5266     { Bad_Opcode },
5267     { Bad_Opcode },
5268     { "vpmulhw",        { XM, Vex, EXx }, 0 },
5269   },
5270
5271   /* PREFIX_VEX_0FE6 */
5272   {
5273     { Bad_Opcode },
5274     { "vcvtdq2pd",      { XM, EXxmmq }, 0 },
5275     { "vcvttpd2dq%XY",  { XMM, EXx }, 0 },
5276     { "vcvtpd2dq%XY",   { XMM, EXx }, 0 },
5277   },
5278
5279   /* PREFIX_VEX_0FE7 */
5280   {
5281     { Bad_Opcode },
5282     { Bad_Opcode },
5283     { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) },
5284   },
5285
5286   /* PREFIX_VEX_0FE8 */
5287   {
5288     { Bad_Opcode },
5289     { Bad_Opcode },
5290     { "vpsubsb",        { XM, Vex, EXx }, 0 },
5291   },
5292
5293   /* PREFIX_VEX_0FE9 */
5294   {
5295     { Bad_Opcode },
5296     { Bad_Opcode },
5297     { "vpsubsw",        { XM, Vex, EXx }, 0 },
5298   },
5299
5300   /* PREFIX_VEX_0FEA */
5301   {
5302     { Bad_Opcode },
5303     { Bad_Opcode },
5304     { "vpminsw",        { XM, Vex, EXx }, 0 },
5305   },
5306
5307   /* PREFIX_VEX_0FEB */
5308   {
5309     { Bad_Opcode },
5310     { Bad_Opcode },
5311     { "vpor",           { XM, Vex, EXx }, 0 },
5312   },
5313
5314   /* PREFIX_VEX_0FEC */
5315   {
5316     { Bad_Opcode },
5317     { Bad_Opcode },
5318     { "vpaddsb",        { XM, Vex, EXx }, 0 },
5319   },
5320
5321   /* PREFIX_VEX_0FED */
5322   {
5323     { Bad_Opcode },
5324     { Bad_Opcode },
5325     { "vpaddsw",        { XM, Vex, EXx }, 0 },
5326   },
5327
5328   /* PREFIX_VEX_0FEE */
5329   {
5330     { Bad_Opcode },
5331     { Bad_Opcode },
5332     { "vpmaxsw",        { XM, Vex, EXx }, 0 },
5333   },
5334
5335   /* PREFIX_VEX_0FEF */
5336   {
5337     { Bad_Opcode },
5338     { Bad_Opcode },
5339     { "vpxor",          { XM, Vex, EXx }, 0 },
5340   },
5341
5342   /* PREFIX_VEX_0FF0 */
5343   {
5344     { Bad_Opcode },
5345     { Bad_Opcode },
5346     { Bad_Opcode },
5347     { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
5348   },
5349
5350   /* PREFIX_VEX_0FF1 */
5351   {
5352     { Bad_Opcode },
5353     { Bad_Opcode },
5354     { "vpsllw",         { XM, Vex, EXxmm }, 0 },
5355   },
5356
5357   /* PREFIX_VEX_0FF2 */
5358   {
5359     { Bad_Opcode },
5360     { Bad_Opcode },
5361     { "vpslld",         { XM, Vex, EXxmm }, 0 },
5362   },
5363
5364   /* PREFIX_VEX_0FF3 */
5365   {
5366     { Bad_Opcode },
5367     { Bad_Opcode },
5368     { "vpsllq",         { XM, Vex, EXxmm }, 0 },
5369   },
5370
5371   /* PREFIX_VEX_0FF4 */
5372   {
5373     { Bad_Opcode },
5374     { Bad_Opcode },
5375     { "vpmuludq",       { XM, Vex, EXx }, 0 },
5376   },
5377
5378   /* PREFIX_VEX_0FF5 */
5379   {
5380     { Bad_Opcode },
5381     { Bad_Opcode },
5382     { "vpmaddwd",       { XM, Vex, EXx }, 0 },
5383   },
5384
5385   /* PREFIX_VEX_0FF6 */
5386   {
5387     { Bad_Opcode },
5388     { Bad_Opcode },
5389     { "vpsadbw",        { XM, Vex, EXx }, 0 },
5390   },
5391
5392   /* PREFIX_VEX_0FF7 */
5393   {
5394     { Bad_Opcode },
5395     { Bad_Opcode },
5396     { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) },
5397   },
5398
5399   /* PREFIX_VEX_0FF8 */
5400   {
5401     { Bad_Opcode },
5402     { Bad_Opcode },
5403     { "vpsubb",         { XM, Vex, EXx }, 0 },
5404   },
5405
5406   /* PREFIX_VEX_0FF9 */
5407   {
5408     { Bad_Opcode },
5409     { Bad_Opcode },
5410     { "vpsubw",         { XM, Vex, EXx }, 0 },
5411   },
5412
5413   /* PREFIX_VEX_0FFA */
5414   {
5415     { Bad_Opcode },
5416     { Bad_Opcode },
5417     { "vpsubd",         { XM, Vex, EXx }, 0 },
5418   },
5419
5420   /* PREFIX_VEX_0FFB */
5421   {
5422     { Bad_Opcode },
5423     { Bad_Opcode },
5424     { "vpsubq",         { XM, Vex, EXx }, 0 },
5425   },
5426
5427   /* PREFIX_VEX_0FFC */
5428   {
5429     { Bad_Opcode },
5430     { Bad_Opcode },
5431     { "vpaddb",         { XM, Vex, EXx }, 0 },
5432   },
5433
5434   /* PREFIX_VEX_0FFD */
5435   {
5436     { Bad_Opcode },
5437     { Bad_Opcode },
5438     { "vpaddw",         { XM, Vex, EXx }, 0 },
5439   },
5440
5441   /* PREFIX_VEX_0FFE */
5442   {
5443     { Bad_Opcode },
5444     { Bad_Opcode },
5445     { "vpaddd",         { XM, Vex, EXx }, 0 },
5446   },
5447
5448   /* PREFIX_VEX_0F3800 */
5449   {
5450     { Bad_Opcode },
5451     { Bad_Opcode },
5452     { "vpshufb",        { XM, Vex, EXx }, 0 },
5453   },
5454
5455   /* PREFIX_VEX_0F3801 */
5456   {
5457     { Bad_Opcode },
5458     { Bad_Opcode },
5459     { "vphaddw",        { XM, Vex, EXx }, 0 },
5460   },
5461
5462   /* PREFIX_VEX_0F3802 */
5463   {
5464     { Bad_Opcode },
5465     { Bad_Opcode },
5466     { "vphaddd",        { XM, Vex, EXx }, 0 },
5467   },
5468
5469   /* PREFIX_VEX_0F3803 */
5470   {
5471     { Bad_Opcode },
5472     { Bad_Opcode },
5473     { "vphaddsw",       { XM, Vex, EXx }, 0 },
5474   },
5475
5476   /* PREFIX_VEX_0F3804 */
5477   {
5478     { Bad_Opcode },
5479     { Bad_Opcode },
5480     { "vpmaddubsw",     { XM, Vex, EXx }, 0 },
5481   },
5482
5483   /* PREFIX_VEX_0F3805 */
5484   {
5485     { Bad_Opcode },
5486     { Bad_Opcode },
5487     { "vphsubw",        { XM, Vex, EXx }, 0 },
5488   },
5489
5490   /* PREFIX_VEX_0F3806 */
5491   {
5492     { Bad_Opcode },
5493     { Bad_Opcode },
5494     { "vphsubd",        { XM, Vex, EXx }, 0 },
5495   },
5496
5497   /* PREFIX_VEX_0F3807 */
5498   {
5499     { Bad_Opcode },
5500     { Bad_Opcode },
5501     { "vphsubsw",       { XM, Vex, EXx }, 0 },
5502   },
5503
5504   /* PREFIX_VEX_0F3808 */
5505   {
5506     { Bad_Opcode },
5507     { Bad_Opcode },
5508     { "vpsignb",        { XM, Vex, EXx }, 0 },
5509   },
5510
5511   /* PREFIX_VEX_0F3809 */
5512   {
5513     { Bad_Opcode },
5514     { Bad_Opcode },
5515     { "vpsignw",        { XM, Vex, EXx }, 0 },
5516   },
5517
5518   /* PREFIX_VEX_0F380A */
5519   {
5520     { Bad_Opcode },
5521     { Bad_Opcode },
5522     { "vpsignd",        { XM, Vex, EXx }, 0 },
5523   },
5524
5525   /* PREFIX_VEX_0F380B */
5526   {
5527     { Bad_Opcode },
5528     { Bad_Opcode },
5529     { "vpmulhrsw",      { XM, Vex, EXx }, 0 },
5530   },
5531
5532   /* PREFIX_VEX_0F380C */
5533   {
5534     { Bad_Opcode },
5535     { Bad_Opcode },
5536     { VEX_W_TABLE (VEX_W_0F380C_P_2) },
5537   },
5538
5539   /* PREFIX_VEX_0F380D */
5540   {
5541     { Bad_Opcode },
5542     { Bad_Opcode },
5543     { VEX_W_TABLE (VEX_W_0F380D_P_2) },
5544   },
5545
5546   /* PREFIX_VEX_0F380E */
5547   {
5548     { Bad_Opcode },
5549     { Bad_Opcode },
5550     { VEX_W_TABLE (VEX_W_0F380E_P_2) },
5551   },
5552
5553   /* PREFIX_VEX_0F380F */
5554   {
5555     { Bad_Opcode },
5556     { Bad_Opcode },
5557     { VEX_W_TABLE (VEX_W_0F380F_P_2) },
5558   },
5559
5560   /* PREFIX_VEX_0F3813 */
5561   {
5562     { Bad_Opcode },
5563     { Bad_Opcode },
5564     { VEX_W_TABLE (VEX_W_0F3813_P_2) },
5565   },
5566
5567   /* PREFIX_VEX_0F3816 */
5568   {
5569     { Bad_Opcode },
5570     { Bad_Opcode },
5571     { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) },
5572   },
5573
5574   /* PREFIX_VEX_0F3817 */
5575   {
5576     { Bad_Opcode },
5577     { Bad_Opcode },
5578     { "vptest",         { XM, EXx }, 0 },
5579   },
5580
5581   /* PREFIX_VEX_0F3818 */
5582   {
5583     { Bad_Opcode },
5584     { Bad_Opcode },
5585     { VEX_W_TABLE (VEX_W_0F3818_P_2) },
5586   },
5587
5588   /* PREFIX_VEX_0F3819 */
5589   {
5590     { Bad_Opcode },
5591     { Bad_Opcode },
5592     { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) },
5593   },
5594
5595   /* PREFIX_VEX_0F381A */
5596   {
5597     { Bad_Opcode },
5598     { Bad_Opcode },
5599     { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) },
5600   },
5601
5602   /* PREFIX_VEX_0F381C */
5603   {
5604     { Bad_Opcode },
5605     { Bad_Opcode },
5606     { "vpabsb",         { XM, EXx }, 0 },
5607   },
5608
5609   /* PREFIX_VEX_0F381D */
5610   {
5611     { Bad_Opcode },
5612     { Bad_Opcode },
5613     { "vpabsw",         { XM, EXx }, 0 },
5614   },
5615
5616   /* PREFIX_VEX_0F381E */
5617   {
5618     { Bad_Opcode },
5619     { Bad_Opcode },
5620     { "vpabsd",         { XM, EXx }, 0 },
5621   },
5622
5623   /* PREFIX_VEX_0F3820 */
5624   {
5625     { Bad_Opcode },
5626     { Bad_Opcode },
5627     { "vpmovsxbw",      { XM, EXxmmq }, 0 },
5628   },
5629
5630   /* PREFIX_VEX_0F3821 */
5631   {
5632     { Bad_Opcode },
5633     { Bad_Opcode },
5634     { "vpmovsxbd",      { XM, EXxmmqd }, 0 },
5635   },
5636
5637   /* PREFIX_VEX_0F3822 */
5638   {
5639     { Bad_Opcode },
5640     { Bad_Opcode },
5641     { "vpmovsxbq",      { XM, EXxmmdw }, 0 },
5642   },
5643
5644   /* PREFIX_VEX_0F3823 */
5645   {
5646     { Bad_Opcode },
5647     { Bad_Opcode },
5648     { "vpmovsxwd",      { XM, EXxmmq }, 0 },
5649   },
5650
5651   /* PREFIX_VEX_0F3824 */
5652   {
5653     { Bad_Opcode },
5654     { Bad_Opcode },
5655     { "vpmovsxwq",      { XM, EXxmmqd }, 0 },
5656   },
5657
5658   /* PREFIX_VEX_0F3825 */
5659   {
5660     { Bad_Opcode },
5661     { Bad_Opcode },
5662     { "vpmovsxdq",      { XM, EXxmmq }, 0 },
5663   },
5664
5665   /* PREFIX_VEX_0F3828 */
5666   {
5667     { Bad_Opcode },
5668     { Bad_Opcode },
5669     { "vpmuldq",        { XM, Vex, EXx }, 0 },
5670   },
5671
5672   /* PREFIX_VEX_0F3829 */
5673   {
5674     { Bad_Opcode },
5675     { Bad_Opcode },
5676     { "vpcmpeqq",       { XM, Vex, EXx }, 0 },
5677   },
5678
5679   /* PREFIX_VEX_0F382A */
5680   {
5681     { Bad_Opcode },
5682     { Bad_Opcode },
5683     { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) },
5684   },
5685
5686   /* PREFIX_VEX_0F382B */
5687   {
5688     { Bad_Opcode },
5689     { Bad_Opcode },
5690     { "vpackusdw",      { XM, Vex, EXx }, 0 },
5691   },
5692
5693   /* PREFIX_VEX_0F382C */
5694   {
5695     { Bad_Opcode },
5696     { Bad_Opcode },
5697      { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) },
5698   },
5699
5700   /* PREFIX_VEX_0F382D */
5701   {
5702     { Bad_Opcode },
5703     { Bad_Opcode },
5704      { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) },
5705   },
5706
5707   /* PREFIX_VEX_0F382E */
5708   {
5709     { Bad_Opcode },
5710     { Bad_Opcode },
5711      { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) },
5712   },
5713
5714   /* PREFIX_VEX_0F382F */
5715   {
5716     { Bad_Opcode },
5717     { Bad_Opcode },
5718      { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) },
5719   },
5720
5721   /* PREFIX_VEX_0F3830 */
5722   {
5723     { Bad_Opcode },
5724     { Bad_Opcode },
5725     { "vpmovzxbw",      { XM, EXxmmq }, 0 },
5726   },
5727
5728   /* PREFIX_VEX_0F3831 */
5729   {
5730     { Bad_Opcode },
5731     { Bad_Opcode },
5732     { "vpmovzxbd",      { XM, EXxmmqd }, 0 },
5733   },
5734
5735   /* PREFIX_VEX_0F3832 */
5736   {
5737     { Bad_Opcode },
5738     { Bad_Opcode },
5739     { "vpmovzxbq",      { XM, EXxmmdw }, 0 },
5740   },
5741
5742   /* PREFIX_VEX_0F3833 */
5743   {
5744     { Bad_Opcode },
5745     { Bad_Opcode },
5746     { "vpmovzxwd",      { XM, EXxmmq }, 0 },
5747   },
5748
5749   /* PREFIX_VEX_0F3834 */
5750   {
5751     { Bad_Opcode },
5752     { Bad_Opcode },
5753     { "vpmovzxwq",      { XM, EXxmmqd }, 0 },
5754   },
5755
5756   /* PREFIX_VEX_0F3835 */
5757   {
5758     { Bad_Opcode },
5759     { Bad_Opcode },
5760     { "vpmovzxdq",      { XM, EXxmmq }, 0 },
5761   },
5762
5763   /* PREFIX_VEX_0F3836 */
5764   {
5765     { Bad_Opcode },
5766     { Bad_Opcode },
5767     { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) },
5768   },
5769
5770   /* PREFIX_VEX_0F3837 */
5771   {
5772     { Bad_Opcode },
5773     { Bad_Opcode },
5774     { "vpcmpgtq",       { XM, Vex, EXx }, 0 },
5775   },
5776
5777   /* PREFIX_VEX_0F3838 */
5778   {
5779     { Bad_Opcode },
5780     { Bad_Opcode },
5781     { "vpminsb",        { XM, Vex, EXx }, 0 },
5782   },
5783
5784   /* PREFIX_VEX_0F3839 */
5785   {
5786     { Bad_Opcode },
5787     { Bad_Opcode },
5788     { "vpminsd",        { XM, Vex, EXx }, 0 },
5789   },
5790
5791   /* PREFIX_VEX_0F383A */
5792   {
5793     { Bad_Opcode },
5794     { Bad_Opcode },
5795     { "vpminuw",        { XM, Vex, EXx }, 0 },
5796   },
5797
5798   /* PREFIX_VEX_0F383B */
5799   {
5800     { Bad_Opcode },
5801     { Bad_Opcode },
5802     { "vpminud",        { XM, Vex, EXx }, 0 },
5803   },
5804
5805   /* PREFIX_VEX_0F383C */
5806   {
5807     { Bad_Opcode },
5808     { Bad_Opcode },
5809     { "vpmaxsb",        { XM, Vex, EXx }, 0 },
5810   },
5811
5812   /* PREFIX_VEX_0F383D */
5813   {
5814     { Bad_Opcode },
5815     { Bad_Opcode },
5816     { "vpmaxsd",        { XM, Vex, EXx }, 0 },
5817   },
5818
5819   /* PREFIX_VEX_0F383E */
5820   {
5821     { Bad_Opcode },
5822     { Bad_Opcode },
5823     { "vpmaxuw",        { XM, Vex, EXx }, 0 },
5824   },
5825
5826   /* PREFIX_VEX_0F383F */
5827   {
5828     { Bad_Opcode },
5829     { Bad_Opcode },
5830     { "vpmaxud",        { XM, Vex, EXx }, 0 },
5831   },
5832
5833   /* PREFIX_VEX_0F3840 */
5834   {
5835     { Bad_Opcode },
5836     { Bad_Opcode },
5837     { "vpmulld",        { XM, Vex, EXx }, 0 },
5838   },
5839
5840   /* PREFIX_VEX_0F3841 */
5841   {
5842     { Bad_Opcode },
5843     { Bad_Opcode },
5844     { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) },
5845   },
5846
5847   /* PREFIX_VEX_0F3845 */
5848   {
5849     { Bad_Opcode },
5850     { Bad_Opcode },
5851     { "vpsrlv%LW", { XM, Vex, EXx }, 0 },
5852   },
5853
5854   /* PREFIX_VEX_0F3846 */
5855   {
5856     { Bad_Opcode },
5857     { Bad_Opcode },
5858     { VEX_W_TABLE (VEX_W_0F3846_P_2) },
5859   },
5860
5861   /* PREFIX_VEX_0F3847 */
5862   {
5863     { Bad_Opcode },
5864     { Bad_Opcode },
5865     { "vpsllv%LW", { XM, Vex, EXx }, 0 },
5866   },
5867
5868   /* PREFIX_VEX_0F3858 */
5869   {
5870     { Bad_Opcode },
5871     { Bad_Opcode },
5872     { VEX_W_TABLE (VEX_W_0F3858_P_2) },
5873   },
5874
5875   /* PREFIX_VEX_0F3859 */
5876   {
5877     { Bad_Opcode },
5878     { Bad_Opcode },
5879     { VEX_W_TABLE (VEX_W_0F3859_P_2) },
5880   },
5881
5882   /* PREFIX_VEX_0F385A */
5883   {
5884     { Bad_Opcode },
5885     { Bad_Opcode },
5886     { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) },
5887   },
5888
5889   /* PREFIX_VEX_0F3878 */
5890   {
5891     { Bad_Opcode },
5892     { Bad_Opcode },
5893     { VEX_W_TABLE (VEX_W_0F3878_P_2) },
5894   },
5895
5896   /* PREFIX_VEX_0F3879 */
5897   {
5898     { Bad_Opcode },
5899     { Bad_Opcode },
5900     { VEX_W_TABLE (VEX_W_0F3879_P_2) },
5901   },
5902
5903   /* PREFIX_VEX_0F388C */
5904   {
5905     { Bad_Opcode },
5906     { Bad_Opcode },
5907     { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) },
5908   },
5909
5910   /* PREFIX_VEX_0F388E */
5911   {
5912     { Bad_Opcode },
5913     { Bad_Opcode },
5914     { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) },
5915   },
5916
5917   /* PREFIX_VEX_0F3890 */
5918   {
5919     { Bad_Opcode },
5920     { Bad_Opcode },
5921     { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex }, 0 },
5922   },
5923
5924   /* PREFIX_VEX_0F3891 */
5925   {
5926     { Bad_Opcode },
5927     { Bad_Opcode },
5928     { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
5929   },
5930
5931   /* PREFIX_VEX_0F3892 */
5932   {
5933     { Bad_Opcode },
5934     { Bad_Opcode },
5935     { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex }, 0 },
5936   },
5937
5938   /* PREFIX_VEX_0F3893 */
5939   {
5940     { Bad_Opcode },
5941     { Bad_Opcode },
5942     { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
5943   },
5944
5945   /* PREFIX_VEX_0F3896 */
5946   {
5947     { Bad_Opcode },
5948     { Bad_Opcode },
5949     { "vfmaddsub132p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
5950   },
5951
5952   /* PREFIX_VEX_0F3897 */
5953   {
5954     { Bad_Opcode },
5955     { Bad_Opcode },
5956     { "vfmsubadd132p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
5957   },
5958
5959   /* PREFIX_VEX_0F3898 */
5960   {
5961     { Bad_Opcode },
5962     { Bad_Opcode },
5963     { "vfmadd132p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
5964   },
5965
5966   /* PREFIX_VEX_0F3899 */
5967   {
5968     { Bad_Opcode },
5969     { Bad_Opcode },
5970     { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
5971   },
5972
5973   /* PREFIX_VEX_0F389A */
5974   {
5975     { Bad_Opcode },
5976     { Bad_Opcode },
5977     { "vfmsub132p%XW", { XM, Vex, EXx }, 0 },
5978   },
5979
5980   /* PREFIX_VEX_0F389B */
5981   {
5982     { Bad_Opcode },
5983     { Bad_Opcode },
5984     { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
5985   },
5986
5987   /* PREFIX_VEX_0F389C */
5988   {
5989     { Bad_Opcode },
5990     { Bad_Opcode },
5991     { "vfnmadd132p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
5992   },
5993
5994   /* PREFIX_VEX_0F389D */
5995   {
5996     { Bad_Opcode },
5997     { Bad_Opcode },
5998     { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
5999   },
6000
6001   /* PREFIX_VEX_0F389E */
6002   {
6003     { Bad_Opcode },
6004     { Bad_Opcode },
6005     { "vfnmsub132p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6006   },
6007
6008   /* PREFIX_VEX_0F389F */
6009   {
6010     { Bad_Opcode },
6011     { Bad_Opcode },
6012     { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
6013   },
6014
6015   /* PREFIX_VEX_0F38A6 */
6016   {
6017     { Bad_Opcode },
6018     { Bad_Opcode },
6019     { "vfmaddsub213p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6020     { Bad_Opcode },
6021   },
6022
6023   /* PREFIX_VEX_0F38A7 */
6024   {
6025     { Bad_Opcode },
6026     { Bad_Opcode },
6027     { "vfmsubadd213p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6028   },
6029
6030   /* PREFIX_VEX_0F38A8 */
6031   {
6032     { Bad_Opcode },
6033     { Bad_Opcode },
6034     { "vfmadd213p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6035   },
6036
6037   /* PREFIX_VEX_0F38A9 */
6038   {
6039     { Bad_Opcode },
6040     { Bad_Opcode },
6041     { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
6042   },
6043
6044   /* PREFIX_VEX_0F38AA */
6045   {
6046     { Bad_Opcode },
6047     { Bad_Opcode },
6048     { "vfmsub213p%XW", { XM, Vex, EXx }, 0 },
6049   },
6050
6051   /* PREFIX_VEX_0F38AB */
6052   {
6053     { Bad_Opcode },
6054     { Bad_Opcode },
6055     { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6056   },
6057
6058   /* PREFIX_VEX_0F38AC */
6059   {
6060     { Bad_Opcode },
6061     { Bad_Opcode },
6062     { "vfnmadd213p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6063   },
6064
6065   /* PREFIX_VEX_0F38AD */
6066   {
6067     { Bad_Opcode },
6068     { Bad_Opcode },
6069     { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
6070   },
6071
6072   /* PREFIX_VEX_0F38AE */
6073   {
6074     { Bad_Opcode },
6075     { Bad_Opcode },
6076     { "vfnmsub213p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6077   },
6078
6079   /* PREFIX_VEX_0F38AF */
6080   {
6081     { Bad_Opcode },
6082     { Bad_Opcode },
6083     { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
6084   },
6085
6086   /* PREFIX_VEX_0F38B6 */
6087   {
6088     { Bad_Opcode },
6089     { Bad_Opcode },
6090     { "vfmaddsub231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6091   },
6092
6093   /* PREFIX_VEX_0F38B7 */
6094   {
6095     { Bad_Opcode },
6096     { Bad_Opcode },
6097     { "vfmsubadd231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6098   },
6099
6100   /* PREFIX_VEX_0F38B8 */
6101   {
6102     { Bad_Opcode },
6103     { Bad_Opcode },
6104     { "vfmadd231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6105   },
6106
6107   /* PREFIX_VEX_0F38B9 */
6108   {
6109     { Bad_Opcode },
6110     { Bad_Opcode },
6111     { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
6112   },
6113
6114   /* PREFIX_VEX_0F38BA */
6115   {
6116     { Bad_Opcode },
6117     { Bad_Opcode },
6118     { "vfmsub231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6119   },
6120
6121   /* PREFIX_VEX_0F38BB */
6122   {
6123     { Bad_Opcode },
6124     { Bad_Opcode },
6125     { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
6126   },
6127
6128   /* PREFIX_VEX_0F38BC */
6129   {
6130     { Bad_Opcode },
6131     { Bad_Opcode },
6132     { "vfnmadd231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6133   },
6134
6135   /* PREFIX_VEX_0F38BD */
6136   {
6137     { Bad_Opcode },
6138     { Bad_Opcode },
6139     { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
6140   },
6141
6142   /* PREFIX_VEX_0F38BE */
6143   {
6144     { Bad_Opcode },
6145     { Bad_Opcode },
6146     { "vfnmsub231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6147   },
6148
6149   /* PREFIX_VEX_0F38BF */
6150   {
6151     { Bad_Opcode },
6152     { Bad_Opcode },
6153     { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
6154   },
6155
6156   /* PREFIX_VEX_0F38CF */
6157   {
6158     { Bad_Opcode },
6159     { Bad_Opcode },
6160     { VEX_W_TABLE (VEX_W_0F38CF_P_2) },
6161   },
6162
6163   /* PREFIX_VEX_0F38DB */
6164   {
6165     { Bad_Opcode },
6166     { Bad_Opcode },
6167     { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) },
6168   },
6169
6170   /* PREFIX_VEX_0F38DC */
6171   {
6172     { Bad_Opcode },
6173     { Bad_Opcode },
6174     { "vaesenc",        { XM, Vex, EXx }, 0 },
6175   },
6176
6177   /* PREFIX_VEX_0F38DD */
6178   {
6179     { Bad_Opcode },
6180     { Bad_Opcode },
6181     { "vaesenclast",    { XM, Vex, EXx }, 0 },
6182   },
6183
6184   /* PREFIX_VEX_0F38DE */
6185   {
6186     { Bad_Opcode },
6187     { Bad_Opcode },
6188     { "vaesdec",        { XM, Vex, EXx }, 0 },
6189   },
6190
6191   /* PREFIX_VEX_0F38DF */
6192   {
6193     { Bad_Opcode },
6194     { Bad_Opcode },
6195     { "vaesdeclast",    { XM, Vex, EXx }, 0 },
6196   },
6197
6198   /* PREFIX_VEX_0F38F2 */
6199   {
6200     { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) },
6201   },
6202
6203   /* PREFIX_VEX_0F38F3_REG_1 */
6204   {
6205     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) },
6206   },
6207
6208   /* PREFIX_VEX_0F38F3_REG_2 */
6209   {
6210     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) },
6211   },
6212
6213   /* PREFIX_VEX_0F38F3_REG_3 */
6214   {
6215     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) },
6216   },
6217
6218   /* PREFIX_VEX_0F38F5 */
6219   {
6220     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) },
6221     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) },
6222     { Bad_Opcode },
6223     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) },
6224   },
6225
6226   /* PREFIX_VEX_0F38F6 */
6227   {
6228     { Bad_Opcode },
6229     { Bad_Opcode },
6230     { Bad_Opcode },
6231     { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) },
6232   },
6233
6234   /* PREFIX_VEX_0F38F7 */
6235   {
6236     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) },
6237     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) },
6238     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) },
6239     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) },
6240   },
6241
6242   /* PREFIX_VEX_0F3A00 */
6243   {
6244     { Bad_Opcode },
6245     { Bad_Opcode },
6246     { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) },
6247   },
6248
6249   /* PREFIX_VEX_0F3A01 */
6250   {
6251     { Bad_Opcode },
6252     { Bad_Opcode },
6253     { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) },
6254   },
6255
6256   /* PREFIX_VEX_0F3A02 */
6257   {
6258     { Bad_Opcode },
6259     { Bad_Opcode },
6260     { VEX_W_TABLE (VEX_W_0F3A02_P_2) },
6261   },
6262
6263   /* PREFIX_VEX_0F3A04 */
6264   {
6265     { Bad_Opcode },
6266     { Bad_Opcode },
6267     { VEX_W_TABLE (VEX_W_0F3A04_P_2) },
6268   },
6269
6270   /* PREFIX_VEX_0F3A05 */
6271   {
6272     { Bad_Opcode },
6273     { Bad_Opcode },
6274     { VEX_W_TABLE (VEX_W_0F3A05_P_2) },
6275   },
6276
6277   /* PREFIX_VEX_0F3A06 */
6278   {
6279     { Bad_Opcode },
6280     { Bad_Opcode },
6281     { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) },
6282   },
6283
6284   /* PREFIX_VEX_0F3A08 */
6285   {
6286     { Bad_Opcode },
6287     { Bad_Opcode },
6288     { "vroundps",       { XM, EXx, Ib }, 0 },
6289   },
6290
6291   /* PREFIX_VEX_0F3A09 */
6292   {
6293     { Bad_Opcode },
6294     { Bad_Opcode },
6295     { "vroundpd",       { XM, EXx, Ib }, 0 },
6296   },
6297
6298   /* PREFIX_VEX_0F3A0A */
6299   {
6300     { Bad_Opcode },
6301     { Bad_Opcode },
6302     { "vroundss",       { XMScalar, VexScalar, EXxmm_md, Ib }, 0 },
6303   },
6304
6305   /* PREFIX_VEX_0F3A0B */
6306   {
6307     { Bad_Opcode },
6308     { Bad_Opcode },
6309     { "vroundsd",       { XMScalar, VexScalar, EXxmm_mq, Ib }, 0 },
6310   },
6311
6312   /* PREFIX_VEX_0F3A0C */
6313   {
6314     { Bad_Opcode },
6315     { Bad_Opcode },
6316     { "vblendps",       { XM, Vex, EXx, Ib }, 0 },
6317   },
6318
6319   /* PREFIX_VEX_0F3A0D */
6320   {
6321     { Bad_Opcode },
6322     { Bad_Opcode },
6323     { "vblendpd",       { XM, Vex, EXx, Ib }, 0 },
6324   },
6325
6326   /* PREFIX_VEX_0F3A0E */
6327   {
6328     { Bad_Opcode },
6329     { Bad_Opcode },
6330     { "vpblendw",       { XM, Vex, EXx, Ib }, 0 },
6331   },
6332
6333   /* PREFIX_VEX_0F3A0F */
6334   {
6335     { Bad_Opcode },
6336     { Bad_Opcode },
6337     { "vpalignr",       { XM, Vex, EXx, Ib }, 0 },
6338   },
6339
6340   /* PREFIX_VEX_0F3A14 */
6341   {
6342     { Bad_Opcode },
6343     { Bad_Opcode },
6344     { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) },
6345   },
6346
6347   /* PREFIX_VEX_0F3A15 */
6348   {
6349     { Bad_Opcode },
6350     { Bad_Opcode },
6351     { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) },
6352   },
6353
6354   /* PREFIX_VEX_0F3A16 */
6355   {
6356     { Bad_Opcode },
6357     { Bad_Opcode },
6358     { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) },
6359   },
6360
6361   /* PREFIX_VEX_0F3A17 */
6362   {
6363     { Bad_Opcode },
6364     { Bad_Opcode },
6365     { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) },
6366   },
6367
6368   /* PREFIX_VEX_0F3A18 */
6369   {
6370     { Bad_Opcode },
6371     { Bad_Opcode },
6372     { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) },
6373   },
6374
6375   /* PREFIX_VEX_0F3A19 */
6376   {
6377     { Bad_Opcode },
6378     { Bad_Opcode },
6379     { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) },
6380   },
6381
6382   /* PREFIX_VEX_0F3A1D */
6383   {
6384     { Bad_Opcode },
6385     { Bad_Opcode },
6386     { VEX_W_TABLE (VEX_W_0F3A1D_P_2) },
6387   },
6388
6389   /* PREFIX_VEX_0F3A20 */
6390   {
6391     { Bad_Opcode },
6392     { Bad_Opcode },
6393     { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) },
6394   },
6395
6396   /* PREFIX_VEX_0F3A21 */
6397   {
6398     { Bad_Opcode },
6399     { Bad_Opcode },
6400     { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) },
6401   },
6402
6403   /* PREFIX_VEX_0F3A22 */
6404   {
6405     { Bad_Opcode },
6406     { Bad_Opcode },
6407     { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) },
6408   },
6409
6410   /* PREFIX_VEX_0F3A30 */
6411   {
6412     { Bad_Opcode },
6413     { Bad_Opcode },
6414     { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2) },
6415   },
6416
6417   /* PREFIX_VEX_0F3A31 */
6418   {
6419     { Bad_Opcode },
6420     { Bad_Opcode },
6421     { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2) },
6422   },
6423
6424   /* PREFIX_VEX_0F3A32 */
6425   {
6426     { Bad_Opcode },
6427     { Bad_Opcode },
6428     { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2) },
6429   },
6430
6431   /* PREFIX_VEX_0F3A33 */
6432   {
6433     { Bad_Opcode },
6434     { Bad_Opcode },
6435     { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2) },
6436   },
6437
6438   /* PREFIX_VEX_0F3A38 */
6439   {
6440     { Bad_Opcode },
6441     { Bad_Opcode },
6442     { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) },
6443   },
6444
6445   /* PREFIX_VEX_0F3A39 */
6446   {
6447     { Bad_Opcode },
6448     { Bad_Opcode },
6449     { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) },
6450   },
6451
6452   /* PREFIX_VEX_0F3A40 */
6453   {
6454     { Bad_Opcode },
6455     { Bad_Opcode },
6456     { "vdpps",          { XM, Vex, EXx, Ib }, 0 },
6457   },
6458
6459   /* PREFIX_VEX_0F3A41 */
6460   {
6461     { Bad_Opcode },
6462     { Bad_Opcode },
6463     { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) },
6464   },
6465
6466   /* PREFIX_VEX_0F3A42 */
6467   {
6468     { Bad_Opcode },
6469     { Bad_Opcode },
6470     { "vmpsadbw",       { XM, Vex, EXx, Ib }, 0 },
6471   },
6472
6473   /* PREFIX_VEX_0F3A44 */
6474   {
6475     { Bad_Opcode },
6476     { Bad_Opcode },
6477     { "vpclmulqdq",     { XM, Vex, EXx, PCLMUL }, 0 },
6478   },
6479
6480   /* PREFIX_VEX_0F3A46 */
6481   {
6482     { Bad_Opcode },
6483     { Bad_Opcode },
6484     { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) },
6485   },
6486
6487   /* PREFIX_VEX_0F3A48 */
6488   {
6489     { Bad_Opcode },
6490     { Bad_Opcode },
6491     { "vpermil2ps",     { XM, Vex, EXx, XMVexI4, VexI4 }, 0 },
6492   },
6493
6494   /* PREFIX_VEX_0F3A49 */
6495   {
6496     { Bad_Opcode },
6497     { Bad_Opcode },
6498     { "vpermil2pd",     { XM, Vex, EXx, XMVexI4, VexI4 }, 0 },
6499   },
6500
6501   /* PREFIX_VEX_0F3A4A */
6502   {
6503     { Bad_Opcode },
6504     { Bad_Opcode },
6505     { VEX_W_TABLE (VEX_W_0F3A4A_P_2) },
6506   },
6507
6508   /* PREFIX_VEX_0F3A4B */
6509   {
6510     { Bad_Opcode },
6511     { Bad_Opcode },
6512     { VEX_W_TABLE (VEX_W_0F3A4B_P_2) },
6513   },
6514
6515   /* PREFIX_VEX_0F3A4C */
6516   {
6517     { Bad_Opcode },
6518     { Bad_Opcode },
6519     { VEX_W_TABLE (VEX_W_0F3A4C_P_2) },
6520   },
6521
6522   /* PREFIX_VEX_0F3A5C */
6523   {
6524     { Bad_Opcode },
6525     { Bad_Opcode },
6526     { "vfmaddsubps", { XM, Vex, EXx, XMVexI4 }, 0 },
6527   },
6528
6529   /* PREFIX_VEX_0F3A5D */
6530   {
6531     { Bad_Opcode },
6532     { Bad_Opcode },
6533     { "vfmaddsubpd", { XM, Vex, EXx, XMVexI4 }, 0 },
6534   },
6535
6536   /* PREFIX_VEX_0F3A5E */
6537   {
6538     { Bad_Opcode },
6539     { Bad_Opcode },
6540     { "vfmsubaddps", { XM, Vex, EXx, XMVexI4 }, 0 },
6541   },
6542
6543   /* PREFIX_VEX_0F3A5F */
6544   {
6545     { Bad_Opcode },
6546     { Bad_Opcode },
6547     { "vfmsubaddpd", { XM, Vex, EXx, XMVexI4 }, 0 },
6548   },
6549
6550   /* PREFIX_VEX_0F3A60 */
6551   {
6552     { Bad_Opcode },
6553     { Bad_Opcode },
6554     { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) },
6555     { Bad_Opcode },
6556   },
6557
6558   /* PREFIX_VEX_0F3A61 */
6559   {
6560     { Bad_Opcode },
6561     { Bad_Opcode },
6562     { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) },
6563   },
6564
6565   /* PREFIX_VEX_0F3A62 */
6566   {
6567     { Bad_Opcode },
6568     { Bad_Opcode },
6569     { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) },
6570   },
6571
6572   /* PREFIX_VEX_0F3A63 */
6573   {
6574     { Bad_Opcode },
6575     { Bad_Opcode },
6576     { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) },
6577   },
6578
6579   /* PREFIX_VEX_0F3A68 */
6580   {
6581     { Bad_Opcode },
6582     { Bad_Opcode },
6583     { "vfmaddps", { XM, Vex, EXx, XMVexI4 }, 0 },
6584   },
6585
6586   /* PREFIX_VEX_0F3A69 */
6587   {
6588     { Bad_Opcode },
6589     { Bad_Opcode },
6590     { "vfmaddpd", { XM, Vex, EXx, XMVexI4 }, 0 },
6591   },
6592
6593   /* PREFIX_VEX_0F3A6A */
6594   {
6595     { Bad_Opcode },
6596     { Bad_Opcode },
6597     { "vfmaddss",       { XMScalar, VexScalar, EXxmm_md, XMVexScalarI4 }, 0 },
6598   },
6599
6600   /* PREFIX_VEX_0F3A6B */
6601   {
6602     { Bad_Opcode },
6603     { Bad_Opcode },
6604     { "vfmaddsd",       { XMScalar, VexScalar, EXxmm_mq, XMVexScalarI4 }, 0 },
6605   },
6606
6607   /* PREFIX_VEX_0F3A6C */
6608   {
6609     { Bad_Opcode },
6610     { Bad_Opcode },
6611     { "vfmsubps", { XM, Vex, EXx, XMVexI4 }, 0 },
6612   },
6613
6614   /* PREFIX_VEX_0F3A6D */
6615   {
6616     { Bad_Opcode },
6617     { Bad_Opcode },
6618     { "vfmsubpd", { XM, Vex, EXx, XMVexI4 }, 0 },
6619   },
6620
6621   /* PREFIX_VEX_0F3A6E */
6622   {
6623     { Bad_Opcode },
6624     { Bad_Opcode },
6625     { "vfmsubss",       { XMScalar, VexScalar, EXxmm_md, XMVexScalarI4 }, 0 },
6626   },
6627
6628   /* PREFIX_VEX_0F3A6F */
6629   {
6630     { Bad_Opcode },
6631     { Bad_Opcode },
6632     { "vfmsubsd",       { XMScalar, VexScalar, EXxmm_mq, XMVexScalarI4 }, 0 },
6633   },
6634
6635   /* PREFIX_VEX_0F3A78 */
6636   {
6637     { Bad_Opcode },
6638     { Bad_Opcode },
6639     { "vfnmaddps", { XM, Vex, EXx, XMVexI4 }, 0 },
6640   },
6641
6642   /* PREFIX_VEX_0F3A79 */
6643   {
6644     { Bad_Opcode },
6645     { Bad_Opcode },
6646     { "vfnmaddpd", { XM, Vex, EXx, XMVexI4 }, 0 },
6647   },
6648
6649   /* PREFIX_VEX_0F3A7A */
6650   {
6651     { Bad_Opcode },
6652     { Bad_Opcode },
6653     { "vfnmaddss",      { XMScalar, VexScalar, EXxmm_md, XMVexScalarI4 }, 0 },
6654   },
6655
6656   /* PREFIX_VEX_0F3A7B */
6657   {
6658     { Bad_Opcode },
6659     { Bad_Opcode },
6660     { "vfnmaddsd",      { XMScalar, VexScalar, EXxmm_mq, XMVexScalarI4 }, 0 },
6661   },
6662
6663   /* PREFIX_VEX_0F3A7C */
6664   {
6665     { Bad_Opcode },
6666     { Bad_Opcode },
6667     { "vfnmsubps", { XM, Vex, EXx, XMVexI4 }, 0 },
6668     { Bad_Opcode },
6669   },
6670
6671   /* PREFIX_VEX_0F3A7D */
6672   {
6673     { Bad_Opcode },
6674     { Bad_Opcode },
6675     { "vfnmsubpd", { XM, Vex, EXx, XMVexI4 }, 0 },
6676   },
6677
6678   /* PREFIX_VEX_0F3A7E */
6679   {
6680     { Bad_Opcode },
6681     { Bad_Opcode },
6682     { "vfnmsubss",      { XMScalar, VexScalar, EXxmm_md, XMVexScalarI4 }, 0 },
6683   },
6684
6685   /* PREFIX_VEX_0F3A7F */
6686   {
6687     { Bad_Opcode },
6688     { Bad_Opcode },
6689     { "vfnmsubsd",      { XMScalar, VexScalar, EXxmm_mq, XMVexScalarI4 }, 0 },
6690   },
6691
6692   /* PREFIX_VEX_0F3ACE */
6693   {
6694     { Bad_Opcode },
6695     { Bad_Opcode },
6696     { VEX_W_TABLE (VEX_W_0F3ACE_P_2) },
6697   },
6698
6699   /* PREFIX_VEX_0F3ACF */
6700   {
6701     { Bad_Opcode },
6702     { Bad_Opcode },
6703     { VEX_W_TABLE (VEX_W_0F3ACF_P_2) },
6704   },
6705
6706   /* PREFIX_VEX_0F3ADF */
6707   {
6708     { Bad_Opcode },
6709     { Bad_Opcode },
6710     { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) },
6711   },
6712
6713   /* PREFIX_VEX_0F3AF0 */
6714   {
6715     { Bad_Opcode },
6716     { Bad_Opcode },
6717     { Bad_Opcode },
6718     { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) },
6719   },
6720
6721 #include "i386-dis-evex-prefix.h"
6722 };
6723
6724 static const struct dis386 x86_64_table[][2] = {
6725   /* X86_64_06 */
6726   {
6727     { "pushP", { es }, 0 },
6728   },
6729
6730   /* X86_64_07 */
6731   {
6732     { "popP", { es }, 0 },
6733   },
6734
6735   /* X86_64_0E */
6736   {
6737     { "pushP", { cs }, 0 },
6738   },
6739
6740   /* X86_64_16 */
6741   {
6742     { "pushP", { ss }, 0 },
6743   },
6744
6745   /* X86_64_17 */
6746   {
6747     { "popP", { ss }, 0 },
6748   },
6749
6750   /* X86_64_1E */
6751   {
6752     { "pushP", { ds }, 0 },
6753   },
6754
6755   /* X86_64_1F */
6756   {
6757     { "popP", { ds }, 0 },
6758   },
6759
6760   /* X86_64_27 */
6761   {
6762     { "daa", { XX }, 0 },
6763   },
6764
6765   /* X86_64_2F */
6766   {
6767     { "das", { XX }, 0 },
6768   },
6769
6770   /* X86_64_37 */
6771   {
6772     { "aaa", { XX }, 0 },
6773   },
6774
6775   /* X86_64_3F */
6776   {
6777     { "aas", { XX }, 0 },
6778   },
6779
6780   /* X86_64_60 */
6781   {
6782     { "pushaP", { XX }, 0 },
6783   },
6784
6785   /* X86_64_61 */
6786   {
6787     { "popaP", { XX }, 0 },
6788   },
6789
6790   /* X86_64_62 */
6791   {
6792     { MOD_TABLE (MOD_62_32BIT) },
6793     { EVEX_TABLE (EVEX_0F) },
6794   },
6795
6796   /* X86_64_63 */
6797   {
6798     { "arpl", { Ew, Gw }, 0 },
6799     { "movs", { { OP_G, movsxd_mode }, { MOVSXD_Fixup, movsxd_mode } }, 0 },
6800   },
6801
6802   /* X86_64_6D */
6803   {
6804     { "ins{R|}", { Yzr, indirDX }, 0 },
6805     { "ins{G|}", { Yzr, indirDX }, 0 },
6806   },
6807
6808   /* X86_64_6F */
6809   {
6810     { "outs{R|}", { indirDXr, Xz }, 0 },
6811     { "outs{G|}", { indirDXr, Xz }, 0 },
6812   },
6813
6814   /* X86_64_82 */
6815   {
6816     /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode.  */
6817     { REG_TABLE (REG_80) },
6818   },
6819
6820   /* X86_64_9A */
6821   {
6822     { "{l|}call{T|}", { Ap }, 0 },
6823   },
6824
6825   /* X86_64_C2 */
6826   {
6827     { "retP",           { Iw, BND }, 0 },
6828     { "ret@",           { Iw, BND }, 0 },
6829   },
6830
6831   /* X86_64_C3 */
6832   {
6833     { "retP",           { BND }, 0 },
6834     { "ret@",           { BND }, 0 },
6835   },
6836
6837   /* X86_64_C4 */
6838   {
6839     { MOD_TABLE (MOD_C4_32BIT) },
6840     { VEX_C4_TABLE (VEX_0F) },
6841   },
6842
6843   /* X86_64_C5 */
6844   {
6845     { MOD_TABLE (MOD_C5_32BIT) },
6846     { VEX_C5_TABLE (VEX_0F) },
6847   },
6848
6849   /* X86_64_CE */
6850   {
6851     { "into", { XX }, 0 },
6852   },
6853
6854   /* X86_64_D4 */
6855   {
6856     { "aam", { Ib }, 0 },
6857   },
6858
6859   /* X86_64_D5 */
6860   {
6861     { "aad", { Ib }, 0 },
6862   },
6863
6864   /* X86_64_E8 */
6865   {
6866     { "callP",          { Jv, BND }, 0 },
6867     { "call@",          { Jv, BND }, 0 }
6868   },
6869
6870   /* X86_64_E9 */
6871   {
6872     { "jmpP",           { Jv, BND }, 0 },
6873     { "jmp@",           { Jv, BND }, 0 }
6874   },
6875
6876   /* X86_64_EA */
6877   {
6878     { "{l|}jmp{T|}", { Ap }, 0 },
6879   },
6880
6881   /* X86_64_0F01_REG_0 */
6882   {
6883     { "sgdt{Q|Q}", { M }, 0 },
6884     { "sgdt", { M }, 0 },
6885   },
6886
6887   /* X86_64_0F01_REG_1 */
6888   {
6889     { "sidt{Q|Q}", { M }, 0 },
6890     { "sidt", { M }, 0 },
6891   },
6892
6893   /* X86_64_0F01_REG_2 */
6894   {
6895     { "lgdt{Q|Q}", { M }, 0 },
6896     { "lgdt", { M }, 0 },
6897   },
6898
6899   /* X86_64_0F01_REG_3 */
6900   {
6901     { "lidt{Q|Q}", { M }, 0 },
6902     { "lidt", { M }, 0 },
6903   },
6904 };
6905
6906 static const struct dis386 three_byte_table[][256] = {
6907
6908   /* THREE_BYTE_0F38 */
6909   {
6910     /* 00 */
6911     { "pshufb",         { MX, EM }, PREFIX_OPCODE },
6912     { "phaddw",         { MX, EM }, PREFIX_OPCODE },
6913     { "phaddd",         { MX, EM }, PREFIX_OPCODE },
6914     { "phaddsw",        { MX, EM }, PREFIX_OPCODE },
6915     { "pmaddubsw",      { MX, EM }, PREFIX_OPCODE },
6916     { "phsubw",         { MX, EM }, PREFIX_OPCODE },
6917     { "phsubd",         { MX, EM }, PREFIX_OPCODE },
6918     { "phsubsw",        { MX, EM }, PREFIX_OPCODE },
6919     /* 08 */
6920     { "psignb",         { MX, EM }, PREFIX_OPCODE },
6921     { "psignw",         { MX, EM }, PREFIX_OPCODE },
6922     { "psignd",         { MX, EM }, PREFIX_OPCODE },
6923     { "pmulhrsw",       { MX, EM }, PREFIX_OPCODE },
6924     { Bad_Opcode },
6925     { Bad_Opcode },
6926     { Bad_Opcode },
6927     { Bad_Opcode },
6928     /* 10 */
6929     { PREFIX_TABLE (PREFIX_0F3810) },
6930     { Bad_Opcode },
6931     { Bad_Opcode },
6932     { Bad_Opcode },
6933     { PREFIX_TABLE (PREFIX_0F3814) },
6934     { PREFIX_TABLE (PREFIX_0F3815) },
6935     { Bad_Opcode },
6936     { PREFIX_TABLE (PREFIX_0F3817) },
6937     /* 18 */
6938     { Bad_Opcode },
6939     { Bad_Opcode },
6940     { Bad_Opcode },
6941     { Bad_Opcode },
6942     { "pabsb",          { MX, EM }, PREFIX_OPCODE },
6943     { "pabsw",          { MX, EM }, PREFIX_OPCODE },
6944     { "pabsd",          { MX, EM }, PREFIX_OPCODE },
6945     { Bad_Opcode },
6946     /* 20 */
6947     { PREFIX_TABLE (PREFIX_0F3820) },
6948     { PREFIX_TABLE (PREFIX_0F3821) },
6949     { PREFIX_TABLE (PREFIX_0F3822) },
6950     { PREFIX_TABLE (PREFIX_0F3823) },
6951     { PREFIX_TABLE (PREFIX_0F3824) },
6952     { PREFIX_TABLE (PREFIX_0F3825) },
6953     { Bad_Opcode },
6954     { Bad_Opcode },
6955     /* 28 */
6956     { PREFIX_TABLE (PREFIX_0F3828) },
6957     { PREFIX_TABLE (PREFIX_0F3829) },
6958     { PREFIX_TABLE (PREFIX_0F382A) },
6959     { PREFIX_TABLE (PREFIX_0F382B) },
6960     { Bad_Opcode },
6961     { Bad_Opcode },
6962     { Bad_Opcode },
6963     { Bad_Opcode },
6964     /* 30 */
6965     { PREFIX_TABLE (PREFIX_0F3830) },
6966     { PREFIX_TABLE (PREFIX_0F3831) },
6967     { PREFIX_TABLE (PREFIX_0F3832) },
6968     { PREFIX_TABLE (PREFIX_0F3833) },
6969     { PREFIX_TABLE (PREFIX_0F3834) },
6970     { PREFIX_TABLE (PREFIX_0F3835) },
6971     { Bad_Opcode },
6972     { PREFIX_TABLE (PREFIX_0F3837) },
6973     /* 38 */
6974     { PREFIX_TABLE (PREFIX_0F3838) },
6975     { PREFIX_TABLE (PREFIX_0F3839) },
6976     { PREFIX_TABLE (PREFIX_0F383A) },
6977     { PREFIX_TABLE (PREFIX_0F383B) },
6978     { PREFIX_TABLE (PREFIX_0F383C) },
6979     { PREFIX_TABLE (PREFIX_0F383D) },
6980     { PREFIX_TABLE (PREFIX_0F383E) },
6981     { PREFIX_TABLE (PREFIX_0F383F) },
6982     /* 40 */
6983     { PREFIX_TABLE (PREFIX_0F3840) },
6984     { PREFIX_TABLE (PREFIX_0F3841) },
6985     { Bad_Opcode },
6986     { Bad_Opcode },
6987     { Bad_Opcode },
6988     { Bad_Opcode },
6989     { Bad_Opcode },
6990     { Bad_Opcode },
6991     /* 48 */
6992     { Bad_Opcode },
6993     { Bad_Opcode },
6994     { Bad_Opcode },
6995     { Bad_Opcode },
6996     { Bad_Opcode },
6997     { Bad_Opcode },
6998     { Bad_Opcode },
6999     { Bad_Opcode },
7000     /* 50 */
7001     { Bad_Opcode },
7002     { Bad_Opcode },
7003     { Bad_Opcode },
7004     { Bad_Opcode },
7005     { Bad_Opcode },
7006     { Bad_Opcode },
7007     { Bad_Opcode },
7008     { Bad_Opcode },
7009     /* 58 */
7010     { Bad_Opcode },
7011     { Bad_Opcode },
7012     { Bad_Opcode },
7013     { Bad_Opcode },
7014     { Bad_Opcode },
7015     { Bad_Opcode },
7016     { Bad_Opcode },
7017     { Bad_Opcode },
7018     /* 60 */
7019     { Bad_Opcode },
7020     { Bad_Opcode },
7021     { Bad_Opcode },
7022     { Bad_Opcode },
7023     { Bad_Opcode },
7024     { Bad_Opcode },
7025     { Bad_Opcode },
7026     { Bad_Opcode },
7027     /* 68 */
7028     { Bad_Opcode },
7029     { Bad_Opcode },
7030     { Bad_Opcode },
7031     { Bad_Opcode },
7032     { Bad_Opcode },
7033     { Bad_Opcode },
7034     { Bad_Opcode },
7035     { Bad_Opcode },
7036     /* 70 */
7037     { Bad_Opcode },
7038     { Bad_Opcode },
7039     { Bad_Opcode },
7040     { Bad_Opcode },
7041     { Bad_Opcode },
7042     { Bad_Opcode },
7043     { Bad_Opcode },
7044     { Bad_Opcode },
7045     /* 78 */
7046     { Bad_Opcode },
7047     { Bad_Opcode },
7048     { Bad_Opcode },
7049     { Bad_Opcode },
7050     { Bad_Opcode },
7051     { Bad_Opcode },
7052     { Bad_Opcode },
7053     { Bad_Opcode },
7054     /* 80 */
7055     { PREFIX_TABLE (PREFIX_0F3880) },
7056     { PREFIX_TABLE (PREFIX_0F3881) },
7057     { PREFIX_TABLE (PREFIX_0F3882) },
7058     { Bad_Opcode },
7059     { Bad_Opcode },
7060     { Bad_Opcode },
7061     { Bad_Opcode },
7062     { Bad_Opcode },
7063     /* 88 */
7064     { Bad_Opcode },
7065     { Bad_Opcode },
7066     { Bad_Opcode },
7067     { Bad_Opcode },
7068     { Bad_Opcode },
7069     { Bad_Opcode },
7070     { Bad_Opcode },
7071     { Bad_Opcode },
7072     /* 90 */
7073     { Bad_Opcode },
7074     { Bad_Opcode },
7075     { Bad_Opcode },
7076     { Bad_Opcode },
7077     { Bad_Opcode },
7078     { Bad_Opcode },
7079     { Bad_Opcode },
7080     { Bad_Opcode },
7081     /* 98 */
7082     { Bad_Opcode },
7083     { Bad_Opcode },
7084     { Bad_Opcode },
7085     { Bad_Opcode },
7086     { Bad_Opcode },
7087     { Bad_Opcode },
7088     { Bad_Opcode },
7089     { Bad_Opcode },
7090     /* a0 */
7091     { Bad_Opcode },
7092     { Bad_Opcode },
7093     { Bad_Opcode },
7094     { Bad_Opcode },
7095     { Bad_Opcode },
7096     { Bad_Opcode },
7097     { Bad_Opcode },
7098     { Bad_Opcode },
7099     /* a8 */
7100     { Bad_Opcode },
7101     { Bad_Opcode },
7102     { Bad_Opcode },
7103     { Bad_Opcode },
7104     { Bad_Opcode },
7105     { Bad_Opcode },
7106     { Bad_Opcode },
7107     { Bad_Opcode },
7108     /* b0 */
7109     { Bad_Opcode },
7110     { Bad_Opcode },
7111     { Bad_Opcode },
7112     { Bad_Opcode },
7113     { Bad_Opcode },
7114     { Bad_Opcode },
7115     { Bad_Opcode },
7116     { Bad_Opcode },
7117     /* b8 */
7118     { Bad_Opcode },
7119     { Bad_Opcode },
7120     { Bad_Opcode },
7121     { Bad_Opcode },
7122     { Bad_Opcode },
7123     { Bad_Opcode },
7124     { Bad_Opcode },
7125     { Bad_Opcode },
7126     /* c0 */
7127     { Bad_Opcode },
7128     { Bad_Opcode },
7129     { Bad_Opcode },
7130     { Bad_Opcode },
7131     { Bad_Opcode },
7132     { Bad_Opcode },
7133     { Bad_Opcode },
7134     { Bad_Opcode },
7135     /* c8 */
7136     { PREFIX_TABLE (PREFIX_0F38C8) },
7137     { PREFIX_TABLE (PREFIX_0F38C9) },
7138     { PREFIX_TABLE (PREFIX_0F38CA) },
7139     { PREFIX_TABLE (PREFIX_0F38CB) },
7140     { PREFIX_TABLE (PREFIX_0F38CC) },
7141     { PREFIX_TABLE (PREFIX_0F38CD) },
7142     { Bad_Opcode },
7143     { PREFIX_TABLE (PREFIX_0F38CF) },
7144     /* d0 */
7145     { Bad_Opcode },
7146     { Bad_Opcode },
7147     { Bad_Opcode },
7148     { Bad_Opcode },
7149     { Bad_Opcode },
7150     { Bad_Opcode },
7151     { Bad_Opcode },
7152     { Bad_Opcode },
7153     /* d8 */
7154     { Bad_Opcode },
7155     { Bad_Opcode },
7156     { Bad_Opcode },
7157     { PREFIX_TABLE (PREFIX_0F38DB) },
7158     { PREFIX_TABLE (PREFIX_0F38DC) },
7159     { PREFIX_TABLE (PREFIX_0F38DD) },
7160     { PREFIX_TABLE (PREFIX_0F38DE) },
7161     { PREFIX_TABLE (PREFIX_0F38DF) },
7162     /* e0 */
7163     { Bad_Opcode },
7164     { Bad_Opcode },
7165     { Bad_Opcode },
7166     { Bad_Opcode },
7167     { Bad_Opcode },
7168     { Bad_Opcode },
7169     { Bad_Opcode },
7170     { Bad_Opcode },
7171     /* e8 */
7172     { Bad_Opcode },
7173     { Bad_Opcode },
7174     { Bad_Opcode },
7175     { Bad_Opcode },
7176     { Bad_Opcode },
7177     { Bad_Opcode },
7178     { Bad_Opcode },
7179     { Bad_Opcode },
7180     /* f0 */
7181     { PREFIX_TABLE (PREFIX_0F38F0) },
7182     { PREFIX_TABLE (PREFIX_0F38F1) },
7183     { Bad_Opcode },
7184     { Bad_Opcode },
7185     { Bad_Opcode },
7186     { PREFIX_TABLE (PREFIX_0F38F5) },
7187     { PREFIX_TABLE (PREFIX_0F38F6) },
7188     { Bad_Opcode },
7189     /* f8 */
7190     { PREFIX_TABLE (PREFIX_0F38F8) },
7191     { PREFIX_TABLE (PREFIX_0F38F9) },
7192     { Bad_Opcode },
7193     { Bad_Opcode },
7194     { Bad_Opcode },
7195     { Bad_Opcode },
7196     { Bad_Opcode },
7197     { Bad_Opcode },
7198   },
7199   /* THREE_BYTE_0F3A */
7200   {
7201     /* 00 */
7202     { Bad_Opcode },
7203     { Bad_Opcode },
7204     { Bad_Opcode },
7205     { Bad_Opcode },
7206     { Bad_Opcode },
7207     { Bad_Opcode },
7208     { Bad_Opcode },
7209     { Bad_Opcode },
7210     /* 08 */
7211     { PREFIX_TABLE (PREFIX_0F3A08) },
7212     { PREFIX_TABLE (PREFIX_0F3A09) },
7213     { PREFIX_TABLE (PREFIX_0F3A0A) },
7214     { PREFIX_TABLE (PREFIX_0F3A0B) },
7215     { PREFIX_TABLE (PREFIX_0F3A0C) },
7216     { PREFIX_TABLE (PREFIX_0F3A0D) },
7217     { PREFIX_TABLE (PREFIX_0F3A0E) },
7218     { "palignr",        { MX, EM, Ib }, PREFIX_OPCODE },
7219     /* 10 */
7220     { Bad_Opcode },
7221     { Bad_Opcode },
7222     { Bad_Opcode },
7223     { Bad_Opcode },
7224     { PREFIX_TABLE (PREFIX_0F3A14) },
7225     { PREFIX_TABLE (PREFIX_0F3A15) },
7226     { PREFIX_TABLE (PREFIX_0F3A16) },
7227     { PREFIX_TABLE (PREFIX_0F3A17) },
7228     /* 18 */
7229     { Bad_Opcode },
7230     { Bad_Opcode },
7231     { Bad_Opcode },
7232     { Bad_Opcode },
7233     { Bad_Opcode },
7234     { Bad_Opcode },
7235     { Bad_Opcode },
7236     { Bad_Opcode },
7237     /* 20 */
7238     { PREFIX_TABLE (PREFIX_0F3A20) },
7239     { PREFIX_TABLE (PREFIX_0F3A21) },
7240     { PREFIX_TABLE (PREFIX_0F3A22) },
7241     { Bad_Opcode },
7242     { Bad_Opcode },
7243     { Bad_Opcode },
7244     { Bad_Opcode },
7245     { Bad_Opcode },
7246     /* 28 */
7247     { Bad_Opcode },
7248     { Bad_Opcode },
7249     { Bad_Opcode },
7250     { Bad_Opcode },
7251     { Bad_Opcode },
7252     { Bad_Opcode },
7253     { Bad_Opcode },
7254     { Bad_Opcode },
7255     /* 30 */
7256     { Bad_Opcode },
7257     { Bad_Opcode },
7258     { Bad_Opcode },
7259     { Bad_Opcode },
7260     { Bad_Opcode },
7261     { Bad_Opcode },
7262     { Bad_Opcode },
7263     { Bad_Opcode },
7264     /* 38 */
7265     { Bad_Opcode },
7266     { Bad_Opcode },
7267     { Bad_Opcode },
7268     { Bad_Opcode },
7269     { Bad_Opcode },
7270     { Bad_Opcode },
7271     { Bad_Opcode },
7272     { Bad_Opcode },
7273     /* 40 */
7274     { PREFIX_TABLE (PREFIX_0F3A40) },
7275     { PREFIX_TABLE (PREFIX_0F3A41) },
7276     { PREFIX_TABLE (PREFIX_0F3A42) },
7277     { Bad_Opcode },
7278     { PREFIX_TABLE (PREFIX_0F3A44) },
7279     { Bad_Opcode },
7280     { Bad_Opcode },
7281     { Bad_Opcode },
7282     /* 48 */
7283     { Bad_Opcode },
7284     { Bad_Opcode },
7285     { Bad_Opcode },
7286     { Bad_Opcode },
7287     { Bad_Opcode },
7288     { Bad_Opcode },
7289     { Bad_Opcode },
7290     { Bad_Opcode },
7291     /* 50 */
7292     { Bad_Opcode },
7293     { Bad_Opcode },
7294     { Bad_Opcode },
7295     { Bad_Opcode },
7296     { Bad_Opcode },
7297     { Bad_Opcode },
7298     { Bad_Opcode },
7299     { Bad_Opcode },
7300     /* 58 */
7301     { Bad_Opcode },
7302     { Bad_Opcode },
7303     { Bad_Opcode },
7304     { Bad_Opcode },
7305     { Bad_Opcode },
7306     { Bad_Opcode },
7307     { Bad_Opcode },
7308     { Bad_Opcode },
7309     /* 60 */
7310     { PREFIX_TABLE (PREFIX_0F3A60) },
7311     { PREFIX_TABLE (PREFIX_0F3A61) },
7312     { PREFIX_TABLE (PREFIX_0F3A62) },
7313     { PREFIX_TABLE (PREFIX_0F3A63) },
7314     { Bad_Opcode },
7315     { Bad_Opcode },
7316     { Bad_Opcode },
7317     { Bad_Opcode },
7318     /* 68 */
7319     { Bad_Opcode },
7320     { Bad_Opcode },
7321     { Bad_Opcode },
7322     { Bad_Opcode },
7323     { Bad_Opcode },
7324     { Bad_Opcode },
7325     { Bad_Opcode },
7326     { Bad_Opcode },
7327     /* 70 */
7328     { Bad_Opcode },
7329     { Bad_Opcode },
7330     { Bad_Opcode },
7331     { Bad_Opcode },
7332     { Bad_Opcode },
7333     { Bad_Opcode },
7334     { Bad_Opcode },
7335     { Bad_Opcode },
7336     /* 78 */
7337     { Bad_Opcode },
7338     { Bad_Opcode },
7339     { Bad_Opcode },
7340     { Bad_Opcode },
7341     { Bad_Opcode },
7342     { Bad_Opcode },
7343     { Bad_Opcode },
7344     { Bad_Opcode },
7345     /* 80 */
7346     { Bad_Opcode },
7347     { Bad_Opcode },
7348     { Bad_Opcode },
7349     { Bad_Opcode },
7350     { Bad_Opcode },
7351     { Bad_Opcode },
7352     { Bad_Opcode },
7353     { Bad_Opcode },
7354     /* 88 */
7355     { Bad_Opcode },
7356     { Bad_Opcode },
7357     { Bad_Opcode },
7358     { Bad_Opcode },
7359     { Bad_Opcode },
7360     { Bad_Opcode },
7361     { Bad_Opcode },
7362     { Bad_Opcode },
7363     /* 90 */
7364     { Bad_Opcode },
7365     { Bad_Opcode },
7366     { Bad_Opcode },
7367     { Bad_Opcode },
7368     { Bad_Opcode },
7369     { Bad_Opcode },
7370     { Bad_Opcode },
7371     { Bad_Opcode },
7372     /* 98 */
7373     { Bad_Opcode },
7374     { Bad_Opcode },
7375     { Bad_Opcode },
7376     { Bad_Opcode },
7377     { Bad_Opcode },
7378     { Bad_Opcode },
7379     { Bad_Opcode },
7380     { Bad_Opcode },
7381     /* a0 */
7382     { Bad_Opcode },
7383     { Bad_Opcode },
7384     { Bad_Opcode },
7385     { Bad_Opcode },
7386     { Bad_Opcode },
7387     { Bad_Opcode },
7388     { Bad_Opcode },
7389     { Bad_Opcode },
7390     /* a8 */
7391     { Bad_Opcode },
7392     { Bad_Opcode },
7393     { Bad_Opcode },
7394     { Bad_Opcode },
7395     { Bad_Opcode },
7396     { Bad_Opcode },
7397     { Bad_Opcode },
7398     { Bad_Opcode },
7399     /* b0 */
7400     { Bad_Opcode },
7401     { Bad_Opcode },
7402     { Bad_Opcode },
7403     { Bad_Opcode },
7404     { Bad_Opcode },
7405     { Bad_Opcode },
7406     { Bad_Opcode },
7407     { Bad_Opcode },
7408     /* b8 */
7409     { Bad_Opcode },
7410     { Bad_Opcode },
7411     { Bad_Opcode },
7412     { Bad_Opcode },
7413     { Bad_Opcode },
7414     { Bad_Opcode },
7415     { Bad_Opcode },
7416     { Bad_Opcode },
7417     /* c0 */
7418     { Bad_Opcode },
7419     { Bad_Opcode },
7420     { Bad_Opcode },
7421     { Bad_Opcode },
7422     { Bad_Opcode },
7423     { Bad_Opcode },
7424     { Bad_Opcode },
7425     { Bad_Opcode },
7426     /* c8 */
7427     { Bad_Opcode },
7428     { Bad_Opcode },
7429     { Bad_Opcode },
7430     { Bad_Opcode },
7431     { PREFIX_TABLE (PREFIX_0F3ACC) },
7432     { Bad_Opcode },
7433     { PREFIX_TABLE (PREFIX_0F3ACE) },
7434     { PREFIX_TABLE (PREFIX_0F3ACF) },
7435     /* d0 */
7436     { Bad_Opcode },
7437     { Bad_Opcode },
7438     { Bad_Opcode },
7439     { Bad_Opcode },
7440     { Bad_Opcode },
7441     { Bad_Opcode },
7442     { Bad_Opcode },
7443     { Bad_Opcode },
7444     /* d8 */
7445     { Bad_Opcode },
7446     { Bad_Opcode },
7447     { Bad_Opcode },
7448     { Bad_Opcode },
7449     { Bad_Opcode },
7450     { Bad_Opcode },
7451     { Bad_Opcode },
7452     { PREFIX_TABLE (PREFIX_0F3ADF) },
7453     /* e0 */
7454     { Bad_Opcode },
7455     { Bad_Opcode },
7456     { Bad_Opcode },
7457     { Bad_Opcode },
7458     { Bad_Opcode },
7459     { Bad_Opcode },
7460     { Bad_Opcode },
7461     { Bad_Opcode },
7462     /* e8 */
7463     { Bad_Opcode },
7464     { Bad_Opcode },
7465     { Bad_Opcode },
7466     { Bad_Opcode },
7467     { Bad_Opcode },
7468     { Bad_Opcode },
7469     { Bad_Opcode },
7470     { Bad_Opcode },
7471     /* f0 */
7472     { Bad_Opcode },
7473     { Bad_Opcode },
7474     { Bad_Opcode },
7475     { Bad_Opcode },
7476     { Bad_Opcode },
7477     { Bad_Opcode },
7478     { Bad_Opcode },
7479     { Bad_Opcode },
7480     /* f8 */
7481     { Bad_Opcode },
7482     { Bad_Opcode },
7483     { Bad_Opcode },
7484     { Bad_Opcode },
7485     { Bad_Opcode },
7486     { Bad_Opcode },
7487     { Bad_Opcode },
7488     { Bad_Opcode },
7489   },
7490 };
7491
7492 static const struct dis386 xop_table[][256] = {
7493   /* XOP_08 */
7494   {
7495     /* 00 */
7496     { Bad_Opcode },
7497     { Bad_Opcode },
7498     { Bad_Opcode },
7499     { Bad_Opcode },
7500     { Bad_Opcode },
7501     { Bad_Opcode },
7502     { Bad_Opcode },
7503     { Bad_Opcode },
7504     /* 08 */
7505     { Bad_Opcode },
7506     { Bad_Opcode },
7507     { Bad_Opcode },
7508     { Bad_Opcode },
7509     { Bad_Opcode },
7510     { Bad_Opcode },
7511     { Bad_Opcode },
7512     { Bad_Opcode },
7513     /* 10 */
7514     { Bad_Opcode },
7515     { Bad_Opcode },
7516     { Bad_Opcode },
7517     { Bad_Opcode },
7518     { Bad_Opcode },
7519     { Bad_Opcode },
7520     { Bad_Opcode },
7521     { Bad_Opcode },
7522     /* 18 */
7523     { Bad_Opcode },
7524     { Bad_Opcode },
7525     { Bad_Opcode },
7526     { Bad_Opcode },
7527     { Bad_Opcode },
7528     { Bad_Opcode },
7529     { Bad_Opcode },
7530     { Bad_Opcode },
7531     /* 20 */
7532     { Bad_Opcode },
7533     { Bad_Opcode },
7534     { Bad_Opcode },
7535     { Bad_Opcode },
7536     { Bad_Opcode },
7537     { Bad_Opcode },
7538     { Bad_Opcode },
7539     { Bad_Opcode },
7540     /* 28 */
7541     { Bad_Opcode },
7542     { Bad_Opcode },
7543     { Bad_Opcode },
7544     { Bad_Opcode },
7545     { Bad_Opcode },
7546     { Bad_Opcode },
7547     { Bad_Opcode },
7548     { Bad_Opcode },
7549     /* 30 */
7550     { Bad_Opcode },
7551     { Bad_Opcode },
7552     { Bad_Opcode },
7553     { Bad_Opcode },
7554     { Bad_Opcode },
7555     { Bad_Opcode },
7556     { Bad_Opcode },
7557     { Bad_Opcode },
7558     /* 38 */
7559     { Bad_Opcode },
7560     { Bad_Opcode },
7561     { Bad_Opcode },
7562     { Bad_Opcode },
7563     { Bad_Opcode },
7564     { Bad_Opcode },
7565     { Bad_Opcode },
7566     { Bad_Opcode },
7567     /* 40 */
7568     { Bad_Opcode },
7569     { Bad_Opcode },
7570     { Bad_Opcode },
7571     { Bad_Opcode },
7572     { Bad_Opcode },
7573     { Bad_Opcode },
7574     { Bad_Opcode },
7575     { Bad_Opcode },
7576     /* 48 */
7577     { Bad_Opcode },
7578     { Bad_Opcode },
7579     { Bad_Opcode },
7580     { Bad_Opcode },
7581     { Bad_Opcode },
7582     { Bad_Opcode },
7583     { Bad_Opcode },
7584     { Bad_Opcode },
7585     /* 50 */
7586     { Bad_Opcode },
7587     { Bad_Opcode },
7588     { Bad_Opcode },
7589     { Bad_Opcode },
7590     { Bad_Opcode },
7591     { Bad_Opcode },
7592     { Bad_Opcode },
7593     { Bad_Opcode },
7594     /* 58 */
7595     { Bad_Opcode },
7596     { Bad_Opcode },
7597     { Bad_Opcode },
7598     { Bad_Opcode },
7599     { Bad_Opcode },
7600     { Bad_Opcode },
7601     { Bad_Opcode },
7602     { Bad_Opcode },
7603     /* 60 */
7604     { Bad_Opcode },
7605     { Bad_Opcode },
7606     { Bad_Opcode },
7607     { Bad_Opcode },
7608     { Bad_Opcode },
7609     { Bad_Opcode },
7610     { Bad_Opcode },
7611     { Bad_Opcode },
7612     /* 68 */
7613     { Bad_Opcode },
7614     { Bad_Opcode },
7615     { Bad_Opcode },
7616     { Bad_Opcode },
7617     { Bad_Opcode },
7618     { Bad_Opcode },
7619     { Bad_Opcode },
7620     { Bad_Opcode },
7621     /* 70 */
7622     { Bad_Opcode },
7623     { Bad_Opcode },
7624     { Bad_Opcode },
7625     { Bad_Opcode },
7626     { Bad_Opcode },
7627     { Bad_Opcode },
7628     { Bad_Opcode },
7629     { Bad_Opcode },
7630     /* 78 */
7631     { Bad_Opcode },
7632     { Bad_Opcode },
7633     { Bad_Opcode },
7634     { Bad_Opcode },
7635     { Bad_Opcode },
7636     { Bad_Opcode },
7637     { Bad_Opcode },
7638     { Bad_Opcode },
7639     /* 80 */
7640     { Bad_Opcode },
7641     { Bad_Opcode },
7642     { Bad_Opcode },
7643     { Bad_Opcode },
7644     { Bad_Opcode },
7645     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_85) },
7646     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_86) },
7647     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_87) },
7648     /* 88 */
7649     { Bad_Opcode },
7650     { Bad_Opcode },
7651     { Bad_Opcode },
7652     { Bad_Opcode },
7653     { Bad_Opcode },
7654     { Bad_Opcode },
7655     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_8E) },
7656     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_8F) },
7657     /* 90 */
7658     { Bad_Opcode },
7659     { Bad_Opcode },
7660     { Bad_Opcode },
7661     { Bad_Opcode },
7662     { Bad_Opcode },
7663     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_95) },
7664     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_96) },
7665     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_97) },
7666     /* 98 */
7667     { Bad_Opcode },
7668     { Bad_Opcode },
7669     { Bad_Opcode },
7670     { Bad_Opcode },
7671     { Bad_Opcode },
7672     { Bad_Opcode },
7673     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_9E) },
7674     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_9F) },
7675     /* a0 */
7676     { Bad_Opcode },
7677     { Bad_Opcode },
7678     { "vpcmov",         { XM, Vex, EXx, XMVexI4 }, 0 },
7679     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_A3) },
7680     { Bad_Opcode },
7681     { Bad_Opcode },
7682     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_A6) },
7683     { Bad_Opcode },
7684     /* a8 */
7685     { Bad_Opcode },
7686     { Bad_Opcode },
7687     { Bad_Opcode },
7688     { Bad_Opcode },
7689     { Bad_Opcode },
7690     { Bad_Opcode },
7691     { Bad_Opcode },
7692     { Bad_Opcode },
7693     /* b0 */
7694     { Bad_Opcode },
7695     { Bad_Opcode },
7696     { Bad_Opcode },
7697     { Bad_Opcode },
7698     { Bad_Opcode },
7699     { Bad_Opcode },
7700     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_B6) },
7701     { Bad_Opcode },
7702     /* b8 */
7703     { Bad_Opcode },
7704     { Bad_Opcode },
7705     { Bad_Opcode },
7706     { Bad_Opcode },
7707     { Bad_Opcode },
7708     { Bad_Opcode },
7709     { Bad_Opcode },
7710     { Bad_Opcode },
7711     /* c0 */
7712     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C0) },
7713     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C1) },
7714     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C2) },
7715     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C3) },
7716     { Bad_Opcode },
7717     { Bad_Opcode },
7718     { Bad_Opcode },
7719     { Bad_Opcode },
7720     /* c8 */
7721     { Bad_Opcode },
7722     { Bad_Opcode },
7723     { Bad_Opcode },
7724     { Bad_Opcode },
7725     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
7726     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
7727     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
7728     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
7729     /* d0 */
7730     { Bad_Opcode },
7731     { Bad_Opcode },
7732     { Bad_Opcode },
7733     { Bad_Opcode },
7734     { Bad_Opcode },
7735     { Bad_Opcode },
7736     { Bad_Opcode },
7737     { Bad_Opcode },
7738     /* d8 */
7739     { Bad_Opcode },
7740     { Bad_Opcode },
7741     { Bad_Opcode },
7742     { Bad_Opcode },
7743     { Bad_Opcode },
7744     { Bad_Opcode },
7745     { Bad_Opcode },
7746     { Bad_Opcode },
7747     /* e0 */
7748     { Bad_Opcode },
7749     { Bad_Opcode },
7750     { Bad_Opcode },
7751     { Bad_Opcode },
7752     { Bad_Opcode },
7753     { Bad_Opcode },
7754     { Bad_Opcode },
7755     { Bad_Opcode },
7756     /* e8 */
7757     { Bad_Opcode },
7758     { Bad_Opcode },
7759     { Bad_Opcode },
7760     { Bad_Opcode },
7761     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
7762     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
7763     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
7764     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
7765     /* f0 */
7766     { Bad_Opcode },
7767     { Bad_Opcode },
7768     { Bad_Opcode },
7769     { Bad_Opcode },
7770     { Bad_Opcode },
7771     { Bad_Opcode },
7772     { Bad_Opcode },
7773     { Bad_Opcode },
7774     /* f8 */
7775     { Bad_Opcode },
7776     { Bad_Opcode },
7777     { Bad_Opcode },
7778     { Bad_Opcode },
7779     { Bad_Opcode },
7780     { Bad_Opcode },
7781     { Bad_Opcode },
7782     { Bad_Opcode },
7783   },
7784   /* XOP_09 */
7785   {
7786     /* 00 */
7787     { Bad_Opcode },
7788     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_01) },
7789     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_02) },
7790     { Bad_Opcode },
7791     { Bad_Opcode },
7792     { Bad_Opcode },
7793     { Bad_Opcode },
7794     { Bad_Opcode },
7795     /* 08 */
7796     { Bad_Opcode },
7797     { Bad_Opcode },
7798     { Bad_Opcode },
7799     { Bad_Opcode },
7800     { Bad_Opcode },
7801     { Bad_Opcode },
7802     { Bad_Opcode },
7803     { Bad_Opcode },
7804     /* 10 */
7805     { Bad_Opcode },
7806     { Bad_Opcode },
7807     { MOD_TABLE (MOD_VEX_0FXOP_09_12) },
7808     { Bad_Opcode },
7809     { Bad_Opcode },
7810     { Bad_Opcode },
7811     { Bad_Opcode },
7812     { Bad_Opcode },
7813     /* 18 */
7814     { Bad_Opcode },
7815     { Bad_Opcode },
7816     { Bad_Opcode },
7817     { Bad_Opcode },
7818     { Bad_Opcode },
7819     { Bad_Opcode },
7820     { Bad_Opcode },
7821     { Bad_Opcode },
7822     /* 20 */
7823     { Bad_Opcode },
7824     { Bad_Opcode },
7825     { Bad_Opcode },
7826     { Bad_Opcode },
7827     { Bad_Opcode },
7828     { Bad_Opcode },
7829     { Bad_Opcode },
7830     { Bad_Opcode },
7831     /* 28 */
7832     { Bad_Opcode },
7833     { Bad_Opcode },
7834     { Bad_Opcode },
7835     { Bad_Opcode },
7836     { Bad_Opcode },
7837     { Bad_Opcode },
7838     { Bad_Opcode },
7839     { Bad_Opcode },
7840     /* 30 */
7841     { Bad_Opcode },
7842     { Bad_Opcode },
7843     { Bad_Opcode },
7844     { Bad_Opcode },
7845     { Bad_Opcode },
7846     { Bad_Opcode },
7847     { Bad_Opcode },
7848     { Bad_Opcode },
7849     /* 38 */
7850     { Bad_Opcode },
7851     { Bad_Opcode },
7852     { Bad_Opcode },
7853     { Bad_Opcode },
7854     { Bad_Opcode },
7855     { Bad_Opcode },
7856     { Bad_Opcode },
7857     { Bad_Opcode },
7858     /* 40 */
7859     { Bad_Opcode },
7860     { Bad_Opcode },
7861     { Bad_Opcode },
7862     { Bad_Opcode },
7863     { Bad_Opcode },
7864     { Bad_Opcode },
7865     { Bad_Opcode },
7866     { Bad_Opcode },
7867     /* 48 */
7868     { Bad_Opcode },
7869     { Bad_Opcode },
7870     { Bad_Opcode },
7871     { Bad_Opcode },
7872     { Bad_Opcode },
7873     { Bad_Opcode },
7874     { Bad_Opcode },
7875     { Bad_Opcode },
7876     /* 50 */
7877     { Bad_Opcode },
7878     { Bad_Opcode },
7879     { Bad_Opcode },
7880     { Bad_Opcode },
7881     { Bad_Opcode },
7882     { Bad_Opcode },
7883     { Bad_Opcode },
7884     { Bad_Opcode },
7885     /* 58 */
7886     { Bad_Opcode },
7887     { Bad_Opcode },
7888     { Bad_Opcode },
7889     { Bad_Opcode },
7890     { Bad_Opcode },
7891     { Bad_Opcode },
7892     { Bad_Opcode },
7893     { Bad_Opcode },
7894     /* 60 */
7895     { Bad_Opcode },
7896     { Bad_Opcode },
7897     { Bad_Opcode },
7898     { Bad_Opcode },
7899     { Bad_Opcode },
7900     { Bad_Opcode },
7901     { Bad_Opcode },
7902     { Bad_Opcode },
7903     /* 68 */
7904     { Bad_Opcode },
7905     { Bad_Opcode },
7906     { Bad_Opcode },
7907     { Bad_Opcode },
7908     { Bad_Opcode },
7909     { Bad_Opcode },
7910     { Bad_Opcode },
7911     { Bad_Opcode },
7912     /* 70 */
7913     { Bad_Opcode },
7914     { Bad_Opcode },
7915     { Bad_Opcode },
7916     { Bad_Opcode },
7917     { Bad_Opcode },
7918     { Bad_Opcode },
7919     { Bad_Opcode },
7920     { Bad_Opcode },
7921     /* 78 */
7922     { Bad_Opcode },
7923     { Bad_Opcode },
7924     { Bad_Opcode },
7925     { Bad_Opcode },
7926     { Bad_Opcode },
7927     { Bad_Opcode },
7928     { Bad_Opcode },
7929     { Bad_Opcode },
7930     /* 80 */
7931     { VEX_W_TABLE (VEX_W_0FXOP_09_80) },
7932     { VEX_W_TABLE (VEX_W_0FXOP_09_81) },
7933     { VEX_W_TABLE (VEX_W_0FXOP_09_82) },
7934     { VEX_W_TABLE (VEX_W_0FXOP_09_83) },
7935     { Bad_Opcode },
7936     { Bad_Opcode },
7937     { Bad_Opcode },
7938     { Bad_Opcode },
7939     /* 88 */
7940     { Bad_Opcode },
7941     { Bad_Opcode },
7942     { Bad_Opcode },
7943     { Bad_Opcode },
7944     { Bad_Opcode },
7945     { Bad_Opcode },
7946     { Bad_Opcode },
7947     { Bad_Opcode },
7948     /* 90 */
7949     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_90) },
7950     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_91) },
7951     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_92) },
7952     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_93) },
7953     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_94) },
7954     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_95) },
7955     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_96) },
7956     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_97) },
7957     /* 98 */
7958     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_98) },
7959     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_99) },
7960     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_9A) },
7961     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_9B) },
7962     { Bad_Opcode },
7963     { Bad_Opcode },
7964     { Bad_Opcode },
7965     { Bad_Opcode },
7966     /* a0 */
7967     { Bad_Opcode },
7968     { Bad_Opcode },
7969     { Bad_Opcode },
7970     { Bad_Opcode },
7971     { Bad_Opcode },
7972     { Bad_Opcode },
7973     { Bad_Opcode },
7974     { Bad_Opcode },
7975     /* a8 */
7976     { Bad_Opcode },
7977     { Bad_Opcode },
7978     { Bad_Opcode },
7979     { Bad_Opcode },
7980     { Bad_Opcode },
7981     { Bad_Opcode },
7982     { Bad_Opcode },
7983     { Bad_Opcode },
7984     /* b0 */
7985     { Bad_Opcode },
7986     { Bad_Opcode },
7987     { Bad_Opcode },
7988     { Bad_Opcode },
7989     { Bad_Opcode },
7990     { Bad_Opcode },
7991     { Bad_Opcode },
7992     { Bad_Opcode },
7993     /* b8 */
7994     { Bad_Opcode },
7995     { Bad_Opcode },
7996     { Bad_Opcode },
7997     { Bad_Opcode },
7998     { Bad_Opcode },
7999     { Bad_Opcode },
8000     { Bad_Opcode },
8001     { Bad_Opcode },
8002     /* c0 */
8003     { Bad_Opcode },
8004     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C1) },
8005     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C2) },
8006     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C3) },
8007     { Bad_Opcode },
8008     { Bad_Opcode },
8009     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C6) },
8010     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C7) },
8011     /* c8 */
8012     { Bad_Opcode },
8013     { Bad_Opcode },
8014     { Bad_Opcode },
8015     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_CB) },
8016     { Bad_Opcode },
8017     { Bad_Opcode },
8018     { Bad_Opcode },
8019     { Bad_Opcode },
8020     /* d0 */
8021     { Bad_Opcode },
8022     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D1) },
8023     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D2) },
8024     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D3) },
8025     { Bad_Opcode },
8026     { Bad_Opcode },
8027     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D6) },
8028     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D7) },
8029     /* d8 */
8030     { Bad_Opcode },
8031     { Bad_Opcode },
8032     { Bad_Opcode },
8033     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_DB) },
8034     { Bad_Opcode },
8035     { Bad_Opcode },
8036     { Bad_Opcode },
8037     { Bad_Opcode },
8038     /* e0 */
8039     { Bad_Opcode },
8040     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E1) },
8041     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E2) },
8042     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E3) },
8043     { Bad_Opcode },
8044     { Bad_Opcode },
8045     { Bad_Opcode },
8046     { Bad_Opcode },
8047     /* e8 */
8048     { Bad_Opcode },
8049     { Bad_Opcode },
8050     { Bad_Opcode },
8051     { Bad_Opcode },
8052     { Bad_Opcode },
8053     { Bad_Opcode },
8054     { Bad_Opcode },
8055     { Bad_Opcode },
8056     /* f0 */
8057     { Bad_Opcode },
8058     { Bad_Opcode },
8059     { Bad_Opcode },
8060     { Bad_Opcode },
8061     { Bad_Opcode },
8062     { Bad_Opcode },
8063     { Bad_Opcode },
8064     { Bad_Opcode },
8065     /* f8 */
8066     { Bad_Opcode },
8067     { Bad_Opcode },
8068     { Bad_Opcode },
8069     { Bad_Opcode },
8070     { Bad_Opcode },
8071     { Bad_Opcode },
8072     { Bad_Opcode },
8073     { Bad_Opcode },
8074   },
8075   /* XOP_0A */
8076   {
8077     /* 00 */
8078     { Bad_Opcode },
8079     { Bad_Opcode },
8080     { Bad_Opcode },
8081     { Bad_Opcode },
8082     { Bad_Opcode },
8083     { Bad_Opcode },
8084     { Bad_Opcode },
8085     { Bad_Opcode },
8086     /* 08 */
8087     { Bad_Opcode },
8088     { Bad_Opcode },
8089     { Bad_Opcode },
8090     { Bad_Opcode },
8091     { Bad_Opcode },
8092     { Bad_Opcode },
8093     { Bad_Opcode },
8094     { Bad_Opcode },
8095     /* 10 */
8096     { "bextrS", { Gdq, Edq, Id }, 0 },
8097     { Bad_Opcode },
8098     { VEX_LEN_TABLE (VEX_LEN_0FXOP_0A_12) },
8099     { Bad_Opcode },
8100     { Bad_Opcode },
8101     { Bad_Opcode },
8102     { Bad_Opcode },
8103     { Bad_Opcode },
8104     /* 18 */
8105     { Bad_Opcode },
8106     { Bad_Opcode },
8107     { Bad_Opcode },
8108     { Bad_Opcode },
8109     { Bad_Opcode },
8110     { Bad_Opcode },
8111     { Bad_Opcode },
8112     { Bad_Opcode },
8113     /* 20 */
8114     { Bad_Opcode },
8115     { Bad_Opcode },
8116     { Bad_Opcode },
8117     { Bad_Opcode },
8118     { Bad_Opcode },
8119     { Bad_Opcode },
8120     { Bad_Opcode },
8121     { Bad_Opcode },
8122     /* 28 */
8123     { Bad_Opcode },
8124     { Bad_Opcode },
8125     { Bad_Opcode },
8126     { Bad_Opcode },
8127     { Bad_Opcode },
8128     { Bad_Opcode },
8129     { Bad_Opcode },
8130     { Bad_Opcode },
8131     /* 30 */
8132     { Bad_Opcode },
8133     { Bad_Opcode },
8134     { Bad_Opcode },
8135     { Bad_Opcode },
8136     { Bad_Opcode },
8137     { Bad_Opcode },
8138     { Bad_Opcode },
8139     { Bad_Opcode },
8140     /* 38 */
8141     { Bad_Opcode },
8142     { Bad_Opcode },
8143     { Bad_Opcode },
8144     { Bad_Opcode },
8145     { Bad_Opcode },
8146     { Bad_Opcode },
8147     { Bad_Opcode },
8148     { Bad_Opcode },
8149     /* 40 */
8150     { Bad_Opcode },
8151     { Bad_Opcode },
8152     { Bad_Opcode },
8153     { Bad_Opcode },
8154     { Bad_Opcode },
8155     { Bad_Opcode },
8156     { Bad_Opcode },
8157     { Bad_Opcode },
8158     /* 48 */
8159     { Bad_Opcode },
8160     { Bad_Opcode },
8161     { Bad_Opcode },
8162     { Bad_Opcode },
8163     { Bad_Opcode },
8164     { Bad_Opcode },
8165     { Bad_Opcode },
8166     { Bad_Opcode },
8167     /* 50 */
8168     { Bad_Opcode },
8169     { Bad_Opcode },
8170     { Bad_Opcode },
8171     { Bad_Opcode },
8172     { Bad_Opcode },
8173     { Bad_Opcode },
8174     { Bad_Opcode },
8175     { Bad_Opcode },
8176     /* 58 */
8177     { Bad_Opcode },
8178     { Bad_Opcode },
8179     { Bad_Opcode },
8180     { Bad_Opcode },
8181     { Bad_Opcode },
8182     { Bad_Opcode },
8183     { Bad_Opcode },
8184     { Bad_Opcode },
8185     /* 60 */
8186     { Bad_Opcode },
8187     { Bad_Opcode },
8188     { Bad_Opcode },
8189     { Bad_Opcode },
8190     { Bad_Opcode },
8191     { Bad_Opcode },
8192     { Bad_Opcode },
8193     { Bad_Opcode },
8194     /* 68 */
8195     { Bad_Opcode },
8196     { Bad_Opcode },
8197     { Bad_Opcode },
8198     { Bad_Opcode },
8199     { Bad_Opcode },
8200     { Bad_Opcode },
8201     { Bad_Opcode },
8202     { Bad_Opcode },
8203     /* 70 */
8204     { Bad_Opcode },
8205     { Bad_Opcode },
8206     { Bad_Opcode },
8207     { Bad_Opcode },
8208     { Bad_Opcode },
8209     { Bad_Opcode },
8210     { Bad_Opcode },
8211     { Bad_Opcode },
8212     /* 78 */
8213     { Bad_Opcode },
8214     { Bad_Opcode },
8215     { Bad_Opcode },
8216     { Bad_Opcode },
8217     { Bad_Opcode },
8218     { Bad_Opcode },
8219     { Bad_Opcode },
8220     { Bad_Opcode },
8221     /* 80 */
8222     { Bad_Opcode },
8223     { Bad_Opcode },
8224     { Bad_Opcode },
8225     { Bad_Opcode },
8226     { Bad_Opcode },
8227     { Bad_Opcode },
8228     { Bad_Opcode },
8229     { Bad_Opcode },
8230     /* 88 */
8231     { Bad_Opcode },
8232     { Bad_Opcode },
8233     { Bad_Opcode },
8234     { Bad_Opcode },
8235     { Bad_Opcode },
8236     { Bad_Opcode },
8237     { Bad_Opcode },
8238     { Bad_Opcode },
8239     /* 90 */
8240     { Bad_Opcode },
8241     { Bad_Opcode },
8242     { Bad_Opcode },
8243     { Bad_Opcode },
8244     { Bad_Opcode },
8245     { Bad_Opcode },
8246     { Bad_Opcode },
8247     { Bad_Opcode },
8248     /* 98 */
8249     { Bad_Opcode },
8250     { Bad_Opcode },
8251     { Bad_Opcode },
8252     { Bad_Opcode },
8253     { Bad_Opcode },
8254     { Bad_Opcode },
8255     { Bad_Opcode },
8256     { Bad_Opcode },
8257     /* a0 */
8258     { Bad_Opcode },
8259     { Bad_Opcode },
8260     { Bad_Opcode },
8261     { Bad_Opcode },
8262     { Bad_Opcode },
8263     { Bad_Opcode },
8264     { Bad_Opcode },
8265     { Bad_Opcode },
8266     /* a8 */
8267     { Bad_Opcode },
8268     { Bad_Opcode },
8269     { Bad_Opcode },
8270     { Bad_Opcode },
8271     { Bad_Opcode },
8272     { Bad_Opcode },
8273     { Bad_Opcode },
8274     { Bad_Opcode },
8275     /* b0 */
8276     { Bad_Opcode },
8277     { Bad_Opcode },
8278     { Bad_Opcode },
8279     { Bad_Opcode },
8280     { Bad_Opcode },
8281     { Bad_Opcode },
8282     { Bad_Opcode },
8283     { Bad_Opcode },
8284     /* b8 */
8285     { Bad_Opcode },
8286     { Bad_Opcode },
8287     { Bad_Opcode },
8288     { Bad_Opcode },
8289     { Bad_Opcode },
8290     { Bad_Opcode },
8291     { Bad_Opcode },
8292     { Bad_Opcode },
8293     /* c0 */
8294     { Bad_Opcode },
8295     { Bad_Opcode },
8296     { Bad_Opcode },
8297     { Bad_Opcode },
8298     { Bad_Opcode },
8299     { Bad_Opcode },
8300     { Bad_Opcode },
8301     { Bad_Opcode },
8302     /* c8 */
8303     { Bad_Opcode },
8304     { Bad_Opcode },
8305     { Bad_Opcode },
8306     { Bad_Opcode },
8307     { Bad_Opcode },
8308     { Bad_Opcode },
8309     { Bad_Opcode },
8310     { Bad_Opcode },
8311     /* d0 */
8312     { Bad_Opcode },
8313     { Bad_Opcode },
8314     { Bad_Opcode },
8315     { Bad_Opcode },
8316     { Bad_Opcode },
8317     { Bad_Opcode },
8318     { Bad_Opcode },
8319     { Bad_Opcode },
8320     /* d8 */
8321     { Bad_Opcode },
8322     { Bad_Opcode },
8323     { Bad_Opcode },
8324     { Bad_Opcode },
8325     { Bad_Opcode },
8326     { Bad_Opcode },
8327     { Bad_Opcode },
8328     { Bad_Opcode },
8329     /* e0 */
8330     { Bad_Opcode },
8331     { Bad_Opcode },
8332     { Bad_Opcode },
8333     { Bad_Opcode },
8334     { Bad_Opcode },
8335     { Bad_Opcode },
8336     { Bad_Opcode },
8337     { Bad_Opcode },
8338     /* e8 */
8339     { Bad_Opcode },
8340     { Bad_Opcode },
8341     { Bad_Opcode },
8342     { Bad_Opcode },
8343     { Bad_Opcode },
8344     { Bad_Opcode },
8345     { Bad_Opcode },
8346     { Bad_Opcode },
8347     /* f0 */
8348     { Bad_Opcode },
8349     { Bad_Opcode },
8350     { Bad_Opcode },
8351     { Bad_Opcode },
8352     { Bad_Opcode },
8353     { Bad_Opcode },
8354     { Bad_Opcode },
8355     { Bad_Opcode },
8356     /* f8 */
8357     { Bad_Opcode },
8358     { Bad_Opcode },
8359     { Bad_Opcode },
8360     { Bad_Opcode },
8361     { Bad_Opcode },
8362     { Bad_Opcode },
8363     { Bad_Opcode },
8364     { Bad_Opcode },
8365   },
8366 };
8367
8368 static const struct dis386 vex_table[][256] = {
8369   /* VEX_0F */
8370   {
8371     /* 00 */
8372     { Bad_Opcode },
8373     { Bad_Opcode },
8374     { Bad_Opcode },
8375     { Bad_Opcode },
8376     { Bad_Opcode },
8377     { Bad_Opcode },
8378     { Bad_Opcode },
8379     { Bad_Opcode },
8380     /* 08 */
8381     { Bad_Opcode },
8382     { Bad_Opcode },
8383     { Bad_Opcode },
8384     { Bad_Opcode },
8385     { Bad_Opcode },
8386     { Bad_Opcode },
8387     { Bad_Opcode },
8388     { Bad_Opcode },
8389     /* 10 */
8390     { PREFIX_TABLE (PREFIX_VEX_0F10) },
8391     { PREFIX_TABLE (PREFIX_VEX_0F11) },
8392     { PREFIX_TABLE (PREFIX_VEX_0F12) },
8393     { MOD_TABLE (MOD_VEX_0F13) },
8394     { "vunpcklpX",      { XM, Vex, EXx }, PREFIX_OPCODE },
8395     { "vunpckhpX",      { XM, Vex, EXx }, PREFIX_OPCODE },
8396     { PREFIX_TABLE (PREFIX_VEX_0F16) },
8397     { MOD_TABLE (MOD_VEX_0F17) },
8398     /* 18 */
8399     { Bad_Opcode },
8400     { Bad_Opcode },
8401     { Bad_Opcode },
8402     { Bad_Opcode },
8403     { Bad_Opcode },
8404     { Bad_Opcode },
8405     { Bad_Opcode },
8406     { Bad_Opcode },
8407     /* 20 */
8408     { Bad_Opcode },
8409     { Bad_Opcode },
8410     { Bad_Opcode },
8411     { Bad_Opcode },
8412     { Bad_Opcode },
8413     { Bad_Opcode },
8414     { Bad_Opcode },
8415     { Bad_Opcode },
8416     /* 28 */
8417     { "vmovapX",        { XM, EXx }, PREFIX_OPCODE },
8418     { "vmovapX",        { EXxS, XM }, PREFIX_OPCODE },
8419     { PREFIX_TABLE (PREFIX_VEX_0F2A) },
8420     { MOD_TABLE (MOD_VEX_0F2B) },
8421     { PREFIX_TABLE (PREFIX_VEX_0F2C) },
8422     { PREFIX_TABLE (PREFIX_VEX_0F2D) },
8423     { PREFIX_TABLE (PREFIX_VEX_0F2E) },
8424     { PREFIX_TABLE (PREFIX_VEX_0F2F) },
8425     /* 30 */
8426     { Bad_Opcode },
8427     { Bad_Opcode },
8428     { Bad_Opcode },
8429     { Bad_Opcode },
8430     { Bad_Opcode },
8431     { Bad_Opcode },
8432     { Bad_Opcode },
8433     { Bad_Opcode },
8434     /* 38 */
8435     { Bad_Opcode },
8436     { Bad_Opcode },
8437     { Bad_Opcode },
8438     { Bad_Opcode },
8439     { Bad_Opcode },
8440     { Bad_Opcode },
8441     { Bad_Opcode },
8442     { Bad_Opcode },
8443     /* 40 */
8444     { Bad_Opcode },
8445     { PREFIX_TABLE (PREFIX_VEX_0F41) },
8446     { PREFIX_TABLE (PREFIX_VEX_0F42) },
8447     { Bad_Opcode },
8448     { PREFIX_TABLE (PREFIX_VEX_0F44) },
8449     { PREFIX_TABLE (PREFIX_VEX_0F45) },
8450     { PREFIX_TABLE (PREFIX_VEX_0F46) },
8451     { PREFIX_TABLE (PREFIX_VEX_0F47) },
8452     /* 48 */
8453     { Bad_Opcode },
8454     { Bad_Opcode },
8455     { PREFIX_TABLE (PREFIX_VEX_0F4A) },
8456     { PREFIX_TABLE (PREFIX_VEX_0F4B) },
8457     { Bad_Opcode },
8458     { Bad_Opcode },
8459     { Bad_Opcode },
8460     { Bad_Opcode },
8461     /* 50 */
8462     { MOD_TABLE (MOD_VEX_0F50) },
8463     { PREFIX_TABLE (PREFIX_VEX_0F51) },
8464     { PREFIX_TABLE (PREFIX_VEX_0F52) },
8465     { PREFIX_TABLE (PREFIX_VEX_0F53) },
8466     { "vandpX",         { XM, Vex, EXx }, PREFIX_OPCODE },
8467     { "vandnpX",        { XM, Vex, EXx }, PREFIX_OPCODE },
8468     { "vorpX",          { XM, Vex, EXx }, PREFIX_OPCODE },
8469     { "vxorpX",         { XM, Vex, EXx }, PREFIX_OPCODE },
8470     /* 58 */
8471     { PREFIX_TABLE (PREFIX_VEX_0F58) },
8472     { PREFIX_TABLE (PREFIX_VEX_0F59) },
8473     { PREFIX_TABLE (PREFIX_VEX_0F5A) },
8474     { PREFIX_TABLE (PREFIX_VEX_0F5B) },
8475     { PREFIX_TABLE (PREFIX_VEX_0F5C) },
8476     { PREFIX_TABLE (PREFIX_VEX_0F5D) },
8477     { PREFIX_TABLE (PREFIX_VEX_0F5E) },
8478     { PREFIX_TABLE (PREFIX_VEX_0F5F) },
8479     /* 60 */
8480     { PREFIX_TABLE (PREFIX_VEX_0F60) },
8481     { PREFIX_TABLE (PREFIX_VEX_0F61) },
8482     { PREFIX_TABLE (PREFIX_VEX_0F62) },
8483     { PREFIX_TABLE (PREFIX_VEX_0F63) },
8484     { PREFIX_TABLE (PREFIX_VEX_0F64) },
8485     { PREFIX_TABLE (PREFIX_VEX_0F65) },
8486     { PREFIX_TABLE (PREFIX_VEX_0F66) },
8487     { PREFIX_TABLE (PREFIX_VEX_0F67) },
8488     /* 68 */
8489     { PREFIX_TABLE (PREFIX_VEX_0F68) },
8490     { PREFIX_TABLE (PREFIX_VEX_0F69) },
8491     { PREFIX_TABLE (PREFIX_VEX_0F6A) },
8492     { PREFIX_TABLE (PREFIX_VEX_0F6B) },
8493     { PREFIX_TABLE (PREFIX_VEX_0F6C) },
8494     { PREFIX_TABLE (PREFIX_VEX_0F6D) },
8495     { PREFIX_TABLE (PREFIX_VEX_0F6E) },
8496     { PREFIX_TABLE (PREFIX_VEX_0F6F) },
8497     /* 70 */
8498     { PREFIX_TABLE (PREFIX_VEX_0F70) },
8499     { REG_TABLE (REG_VEX_0F71) },
8500     { REG_TABLE (REG_VEX_0F72) },
8501     { REG_TABLE (REG_VEX_0F73) },
8502     { PREFIX_TABLE (PREFIX_VEX_0F74) },
8503     { PREFIX_TABLE (PREFIX_VEX_0F75) },
8504     { PREFIX_TABLE (PREFIX_VEX_0F76) },
8505     { PREFIX_TABLE (PREFIX_VEX_0F77) },
8506     /* 78 */
8507     { Bad_Opcode },
8508     { Bad_Opcode },
8509     { Bad_Opcode },
8510     { Bad_Opcode },
8511     { PREFIX_TABLE (PREFIX_VEX_0F7C) },
8512     { PREFIX_TABLE (PREFIX_VEX_0F7D) },
8513     { PREFIX_TABLE (PREFIX_VEX_0F7E) },
8514     { PREFIX_TABLE (PREFIX_VEX_0F7F) },
8515     /* 80 */
8516     { Bad_Opcode },
8517     { Bad_Opcode },
8518     { Bad_Opcode },
8519     { Bad_Opcode },
8520     { Bad_Opcode },
8521     { Bad_Opcode },
8522     { Bad_Opcode },
8523     { Bad_Opcode },
8524     /* 88 */
8525     { Bad_Opcode },
8526     { Bad_Opcode },
8527     { Bad_Opcode },
8528     { Bad_Opcode },
8529     { Bad_Opcode },
8530     { Bad_Opcode },
8531     { Bad_Opcode },
8532     { Bad_Opcode },
8533     /* 90 */
8534     { PREFIX_TABLE (PREFIX_VEX_0F90) },
8535     { PREFIX_TABLE (PREFIX_VEX_0F91) },
8536     { PREFIX_TABLE (PREFIX_VEX_0F92) },
8537     { PREFIX_TABLE (PREFIX_VEX_0F93) },
8538     { Bad_Opcode },
8539     { Bad_Opcode },
8540     { Bad_Opcode },
8541     { Bad_Opcode },
8542     /* 98 */
8543     { PREFIX_TABLE (PREFIX_VEX_0F98) },
8544     { PREFIX_TABLE (PREFIX_VEX_0F99) },
8545     { Bad_Opcode },
8546     { Bad_Opcode },
8547     { Bad_Opcode },
8548     { Bad_Opcode },
8549     { Bad_Opcode },
8550     { Bad_Opcode },
8551     /* a0 */
8552     { Bad_Opcode },
8553     { Bad_Opcode },
8554     { Bad_Opcode },
8555     { Bad_Opcode },
8556     { Bad_Opcode },
8557     { Bad_Opcode },
8558     { Bad_Opcode },
8559     { Bad_Opcode },
8560     /* a8 */
8561     { Bad_Opcode },
8562     { Bad_Opcode },
8563     { Bad_Opcode },
8564     { Bad_Opcode },
8565     { Bad_Opcode },
8566     { Bad_Opcode },
8567     { REG_TABLE (REG_VEX_0FAE) },
8568     { Bad_Opcode },
8569     /* b0 */
8570     { Bad_Opcode },
8571     { Bad_Opcode },
8572     { Bad_Opcode },
8573     { Bad_Opcode },
8574     { Bad_Opcode },
8575     { Bad_Opcode },
8576     { Bad_Opcode },
8577     { Bad_Opcode },
8578     /* b8 */
8579     { Bad_Opcode },
8580     { Bad_Opcode },
8581     { Bad_Opcode },
8582     { Bad_Opcode },
8583     { Bad_Opcode },
8584     { Bad_Opcode },
8585     { Bad_Opcode },
8586     { Bad_Opcode },
8587     /* c0 */
8588     { Bad_Opcode },
8589     { Bad_Opcode },
8590     { PREFIX_TABLE (PREFIX_VEX_0FC2) },
8591     { Bad_Opcode },
8592     { PREFIX_TABLE (PREFIX_VEX_0FC4) },
8593     { PREFIX_TABLE (PREFIX_VEX_0FC5) },
8594     { "vshufpX",        { XM, Vex, EXx, Ib }, PREFIX_OPCODE },
8595     { Bad_Opcode },
8596     /* c8 */
8597     { Bad_Opcode },
8598     { Bad_Opcode },
8599     { Bad_Opcode },
8600     { Bad_Opcode },
8601     { Bad_Opcode },
8602     { Bad_Opcode },
8603     { Bad_Opcode },
8604     { Bad_Opcode },
8605     /* d0 */
8606     { PREFIX_TABLE (PREFIX_VEX_0FD0) },
8607     { PREFIX_TABLE (PREFIX_VEX_0FD1) },
8608     { PREFIX_TABLE (PREFIX_VEX_0FD2) },
8609     { PREFIX_TABLE (PREFIX_VEX_0FD3) },
8610     { PREFIX_TABLE (PREFIX_VEX_0FD4) },
8611     { PREFIX_TABLE (PREFIX_VEX_0FD5) },
8612     { PREFIX_TABLE (PREFIX_VEX_0FD6) },
8613     { PREFIX_TABLE (PREFIX_VEX_0FD7) },
8614     /* d8 */
8615     { PREFIX_TABLE (PREFIX_VEX_0FD8) },
8616     { PREFIX_TABLE (PREFIX_VEX_0FD9) },
8617     { PREFIX_TABLE (PREFIX_VEX_0FDA) },
8618     { PREFIX_TABLE (PREFIX_VEX_0FDB) },
8619     { PREFIX_TABLE (PREFIX_VEX_0FDC) },
8620     { PREFIX_TABLE (PREFIX_VEX_0FDD) },
8621     { PREFIX_TABLE (PREFIX_VEX_0FDE) },
8622     { PREFIX_TABLE (PREFIX_VEX_0FDF) },
8623     /* e0 */
8624     { PREFIX_TABLE (PREFIX_VEX_0FE0) },
8625     { PREFIX_TABLE (PREFIX_VEX_0FE1) },
8626     { PREFIX_TABLE (PREFIX_VEX_0FE2) },
8627     { PREFIX_TABLE (PREFIX_VEX_0FE3) },
8628     { PREFIX_TABLE (PREFIX_VEX_0FE4) },
8629     { PREFIX_TABLE (PREFIX_VEX_0FE5) },
8630     { PREFIX_TABLE (PREFIX_VEX_0FE6) },
8631     { PREFIX_TABLE (PREFIX_VEX_0FE7) },
8632     /* e8 */
8633     { PREFIX_TABLE (PREFIX_VEX_0FE8) },
8634     { PREFIX_TABLE (PREFIX_VEX_0FE9) },
8635     { PREFIX_TABLE (PREFIX_VEX_0FEA) },
8636     { PREFIX_TABLE (PREFIX_VEX_0FEB) },
8637     { PREFIX_TABLE (PREFIX_VEX_0FEC) },
8638     { PREFIX_TABLE (PREFIX_VEX_0FED) },
8639     { PREFIX_TABLE (PREFIX_VEX_0FEE) },
8640     { PREFIX_TABLE (PREFIX_VEX_0FEF) },
8641     /* f0 */
8642     { PREFIX_TABLE (PREFIX_VEX_0FF0) },
8643     { PREFIX_TABLE (PREFIX_VEX_0FF1) },
8644     { PREFIX_TABLE (PREFIX_VEX_0FF2) },
8645     { PREFIX_TABLE (PREFIX_VEX_0FF3) },
8646     { PREFIX_TABLE (PREFIX_VEX_0FF4) },
8647     { PREFIX_TABLE (PREFIX_VEX_0FF5) },
8648     { PREFIX_TABLE (PREFIX_VEX_0FF6) },
8649     { PREFIX_TABLE (PREFIX_VEX_0FF7) },
8650     /* f8 */
8651     { PREFIX_TABLE (PREFIX_VEX_0FF8) },
8652     { PREFIX_TABLE (PREFIX_VEX_0FF9) },
8653     { PREFIX_TABLE (PREFIX_VEX_0FFA) },
8654     { PREFIX_TABLE (PREFIX_VEX_0FFB) },
8655     { PREFIX_TABLE (PREFIX_VEX_0FFC) },
8656     { PREFIX_TABLE (PREFIX_VEX_0FFD) },
8657     { PREFIX_TABLE (PREFIX_VEX_0FFE) },
8658     { Bad_Opcode },
8659   },
8660   /* VEX_0F38 */
8661   {
8662     /* 00 */
8663     { PREFIX_TABLE (PREFIX_VEX_0F3800) },
8664     { PREFIX_TABLE (PREFIX_VEX_0F3801) },
8665     { PREFIX_TABLE (PREFIX_VEX_0F3802) },
8666     { PREFIX_TABLE (PREFIX_VEX_0F3803) },
8667     { PREFIX_TABLE (PREFIX_VEX_0F3804) },
8668     { PREFIX_TABLE (PREFIX_VEX_0F3805) },
8669     { PREFIX_TABLE (PREFIX_VEX_0F3806) },
8670     { PREFIX_TABLE (PREFIX_VEX_0F3807) },
8671     /* 08 */
8672     { PREFIX_TABLE (PREFIX_VEX_0F3808) },
8673     { PREFIX_TABLE (PREFIX_VEX_0F3809) },
8674     { PREFIX_TABLE (PREFIX_VEX_0F380A) },
8675     { PREFIX_TABLE (PREFIX_VEX_0F380B) },
8676     { PREFIX_TABLE (PREFIX_VEX_0F380C) },
8677     { PREFIX_TABLE (PREFIX_VEX_0F380D) },
8678     { PREFIX_TABLE (PREFIX_VEX_0F380E) },
8679     { PREFIX_TABLE (PREFIX_VEX_0F380F) },
8680     /* 10 */
8681     { Bad_Opcode },
8682     { Bad_Opcode },
8683     { Bad_Opcode },
8684     { PREFIX_TABLE (PREFIX_VEX_0F3813) },
8685     { Bad_Opcode },
8686     { Bad_Opcode },
8687     { PREFIX_TABLE (PREFIX_VEX_0F3816) },
8688     { PREFIX_TABLE (PREFIX_VEX_0F3817) },
8689     /* 18 */
8690     { PREFIX_TABLE (PREFIX_VEX_0F3818) },
8691     { PREFIX_TABLE (PREFIX_VEX_0F3819) },
8692     { PREFIX_TABLE (PREFIX_VEX_0F381A) },
8693     { Bad_Opcode },
8694     { PREFIX_TABLE (PREFIX_VEX_0F381C) },
8695     { PREFIX_TABLE (PREFIX_VEX_0F381D) },
8696     { PREFIX_TABLE (PREFIX_VEX_0F381E) },
8697     { Bad_Opcode },
8698     /* 20 */
8699     { PREFIX_TABLE (PREFIX_VEX_0F3820) },
8700     { PREFIX_TABLE (PREFIX_VEX_0F3821) },
8701     { PREFIX_TABLE (PREFIX_VEX_0F3822) },
8702     { PREFIX_TABLE (PREFIX_VEX_0F3823) },
8703     { PREFIX_TABLE (PREFIX_VEX_0F3824) },
8704     { PREFIX_TABLE (PREFIX_VEX_0F3825) },
8705     { Bad_Opcode },
8706     { Bad_Opcode },
8707     /* 28 */
8708     { PREFIX_TABLE (PREFIX_VEX_0F3828) },
8709     { PREFIX_TABLE (PREFIX_VEX_0F3829) },
8710     { PREFIX_TABLE (PREFIX_VEX_0F382A) },
8711     { PREFIX_TABLE (PREFIX_VEX_0F382B) },
8712     { PREFIX_TABLE (PREFIX_VEX_0F382C) },
8713     { PREFIX_TABLE (PREFIX_VEX_0F382D) },
8714     { PREFIX_TABLE (PREFIX_VEX_0F382E) },
8715     { PREFIX_TABLE (PREFIX_VEX_0F382F) },
8716     /* 30 */
8717     { PREFIX_TABLE (PREFIX_VEX_0F3830) },
8718     { PREFIX_TABLE (PREFIX_VEX_0F3831) },
8719     { PREFIX_TABLE (PREFIX_VEX_0F3832) },
8720     { PREFIX_TABLE (PREFIX_VEX_0F3833) },
8721     { PREFIX_TABLE (PREFIX_VEX_0F3834) },
8722     { PREFIX_TABLE (PREFIX_VEX_0F3835) },
8723     { PREFIX_TABLE (PREFIX_VEX_0F3836) },
8724     { PREFIX_TABLE (PREFIX_VEX_0F3837) },
8725     /* 38 */
8726     { PREFIX_TABLE (PREFIX_VEX_0F3838) },
8727     { PREFIX_TABLE (PREFIX_VEX_0F3839) },
8728     { PREFIX_TABLE (PREFIX_VEX_0F383A) },
8729     { PREFIX_TABLE (PREFIX_VEX_0F383B) },
8730     { PREFIX_TABLE (PREFIX_VEX_0F383C) },
8731     { PREFIX_TABLE (PREFIX_VEX_0F383D) },
8732     { PREFIX_TABLE (PREFIX_VEX_0F383E) },
8733     { PREFIX_TABLE (PREFIX_VEX_0F383F) },
8734     /* 40 */
8735     { PREFIX_TABLE (PREFIX_VEX_0F3840) },
8736     { PREFIX_TABLE (PREFIX_VEX_0F3841) },
8737     { Bad_Opcode },
8738     { Bad_Opcode },
8739     { Bad_Opcode },
8740     { PREFIX_TABLE (PREFIX_VEX_0F3845) },
8741     { PREFIX_TABLE (PREFIX_VEX_0F3846) },
8742     { PREFIX_TABLE (PREFIX_VEX_0F3847) },
8743     /* 48 */
8744     { Bad_Opcode },
8745     { Bad_Opcode },
8746     { Bad_Opcode },
8747     { Bad_Opcode },
8748     { Bad_Opcode },
8749     { Bad_Opcode },
8750     { Bad_Opcode },
8751     { Bad_Opcode },
8752     /* 50 */
8753     { Bad_Opcode },
8754     { Bad_Opcode },
8755     { Bad_Opcode },
8756     { Bad_Opcode },
8757     { Bad_Opcode },
8758     { Bad_Opcode },
8759     { Bad_Opcode },
8760     { Bad_Opcode },
8761     /* 58 */
8762     { PREFIX_TABLE (PREFIX_VEX_0F3858) },
8763     { PREFIX_TABLE (PREFIX_VEX_0F3859) },
8764     { PREFIX_TABLE (PREFIX_VEX_0F385A) },
8765     { Bad_Opcode },
8766     { Bad_Opcode },
8767     { Bad_Opcode },
8768     { Bad_Opcode },
8769     { Bad_Opcode },
8770     /* 60 */
8771     { Bad_Opcode },
8772     { Bad_Opcode },
8773     { Bad_Opcode },
8774     { Bad_Opcode },
8775     { Bad_Opcode },
8776     { Bad_Opcode },
8777     { Bad_Opcode },
8778     { Bad_Opcode },
8779     /* 68 */
8780     { Bad_Opcode },
8781     { Bad_Opcode },
8782     { Bad_Opcode },
8783     { Bad_Opcode },
8784     { Bad_Opcode },
8785     { Bad_Opcode },
8786     { Bad_Opcode },
8787     { Bad_Opcode },
8788     /* 70 */
8789     { Bad_Opcode },
8790     { Bad_Opcode },
8791     { Bad_Opcode },
8792     { Bad_Opcode },
8793     { Bad_Opcode },
8794     { Bad_Opcode },
8795     { Bad_Opcode },
8796     { Bad_Opcode },
8797     /* 78 */
8798     { PREFIX_TABLE (PREFIX_VEX_0F3878) },
8799     { PREFIX_TABLE (PREFIX_VEX_0F3879) },
8800     { Bad_Opcode },
8801     { Bad_Opcode },
8802     { Bad_Opcode },
8803     { Bad_Opcode },
8804     { Bad_Opcode },
8805     { Bad_Opcode },
8806     /* 80 */
8807     { Bad_Opcode },
8808     { Bad_Opcode },
8809     { Bad_Opcode },
8810     { Bad_Opcode },
8811     { Bad_Opcode },
8812     { Bad_Opcode },
8813     { Bad_Opcode },
8814     { Bad_Opcode },
8815     /* 88 */
8816     { Bad_Opcode },
8817     { Bad_Opcode },
8818     { Bad_Opcode },
8819     { Bad_Opcode },
8820     { PREFIX_TABLE (PREFIX_VEX_0F388C) },
8821     { Bad_Opcode },
8822     { PREFIX_TABLE (PREFIX_VEX_0F388E) },
8823     { Bad_Opcode },
8824     /* 90 */
8825     { PREFIX_TABLE (PREFIX_VEX_0F3890) },
8826     { PREFIX_TABLE (PREFIX_VEX_0F3891) },
8827     { PREFIX_TABLE (PREFIX_VEX_0F3892) },
8828     { PREFIX_TABLE (PREFIX_VEX_0F3893) },
8829     { Bad_Opcode },
8830     { Bad_Opcode },
8831     { PREFIX_TABLE (PREFIX_VEX_0F3896) },
8832     { PREFIX_TABLE (PREFIX_VEX_0F3897) },
8833     /* 98 */
8834     { PREFIX_TABLE (PREFIX_VEX_0F3898) },
8835     { PREFIX_TABLE (PREFIX_VEX_0F3899) },
8836     { PREFIX_TABLE (PREFIX_VEX_0F389A) },
8837     { PREFIX_TABLE (PREFIX_VEX_0F389B) },
8838     { PREFIX_TABLE (PREFIX_VEX_0F389C) },
8839     { PREFIX_TABLE (PREFIX_VEX_0F389D) },
8840     { PREFIX_TABLE (PREFIX_VEX_0F389E) },
8841     { PREFIX_TABLE (PREFIX_VEX_0F389F) },
8842     /* a0 */
8843     { Bad_Opcode },
8844     { Bad_Opcode },
8845     { Bad_Opcode },
8846     { Bad_Opcode },
8847     { Bad_Opcode },
8848     { Bad_Opcode },
8849     { PREFIX_TABLE (PREFIX_VEX_0F38A6) },
8850     { PREFIX_TABLE (PREFIX_VEX_0F38A7) },
8851     /* a8 */
8852     { PREFIX_TABLE (PREFIX_VEX_0F38A8) },
8853     { PREFIX_TABLE (PREFIX_VEX_0F38A9) },
8854     { PREFIX_TABLE (PREFIX_VEX_0F38AA) },
8855     { PREFIX_TABLE (PREFIX_VEX_0F38AB) },
8856     { PREFIX_TABLE (PREFIX_VEX_0F38AC) },
8857     { PREFIX_TABLE (PREFIX_VEX_0F38AD) },
8858     { PREFIX_TABLE (PREFIX_VEX_0F38AE) },
8859     { PREFIX_TABLE (PREFIX_VEX_0F38AF) },
8860     /* b0 */
8861     { Bad_Opcode },
8862     { Bad_Opcode },
8863     { Bad_Opcode },
8864     { Bad_Opcode },
8865     { Bad_Opcode },
8866     { Bad_Opcode },
8867     { PREFIX_TABLE (PREFIX_VEX_0F38B6) },
8868     { PREFIX_TABLE (PREFIX_VEX_0F38B7) },
8869     /* b8 */
8870     { PREFIX_TABLE (PREFIX_VEX_0F38B8) },
8871     { PREFIX_TABLE (PREFIX_VEX_0F38B9) },
8872     { PREFIX_TABLE (PREFIX_VEX_0F38BA) },
8873     { PREFIX_TABLE (PREFIX_VEX_0F38BB) },
8874     { PREFIX_TABLE (PREFIX_VEX_0F38BC) },
8875     { PREFIX_TABLE (PREFIX_VEX_0F38BD) },
8876     { PREFIX_TABLE (PREFIX_VEX_0F38BE) },
8877     { PREFIX_TABLE (PREFIX_VEX_0F38BF) },
8878     /* c0 */
8879     { Bad_Opcode },
8880     { Bad_Opcode },
8881     { Bad_Opcode },
8882     { Bad_Opcode },
8883     { Bad_Opcode },
8884     { Bad_Opcode },
8885     { Bad_Opcode },
8886     { Bad_Opcode },
8887     /* c8 */
8888     { Bad_Opcode },
8889     { Bad_Opcode },
8890     { Bad_Opcode },
8891     { Bad_Opcode },
8892     { Bad_Opcode },
8893     { Bad_Opcode },
8894     { Bad_Opcode },
8895     { PREFIX_TABLE (PREFIX_VEX_0F38CF) },
8896     /* d0 */
8897     { Bad_Opcode },
8898     { Bad_Opcode },
8899     { Bad_Opcode },
8900     { Bad_Opcode },
8901     { Bad_Opcode },
8902     { Bad_Opcode },
8903     { Bad_Opcode },
8904     { Bad_Opcode },
8905     /* d8 */
8906     { Bad_Opcode },
8907     { Bad_Opcode },
8908     { Bad_Opcode },
8909     { PREFIX_TABLE (PREFIX_VEX_0F38DB) },
8910     { PREFIX_TABLE (PREFIX_VEX_0F38DC) },
8911     { PREFIX_TABLE (PREFIX_VEX_0F38DD) },
8912     { PREFIX_TABLE (PREFIX_VEX_0F38DE) },
8913     { PREFIX_TABLE (PREFIX_VEX_0F38DF) },
8914     /* e0 */
8915     { Bad_Opcode },
8916     { Bad_Opcode },
8917     { Bad_Opcode },
8918     { Bad_Opcode },
8919     { Bad_Opcode },
8920     { Bad_Opcode },
8921     { Bad_Opcode },
8922     { Bad_Opcode },
8923     /* e8 */
8924     { Bad_Opcode },
8925     { Bad_Opcode },
8926     { Bad_Opcode },
8927     { Bad_Opcode },
8928     { Bad_Opcode },
8929     { Bad_Opcode },
8930     { Bad_Opcode },
8931     { Bad_Opcode },
8932     /* f0 */
8933     { Bad_Opcode },
8934     { Bad_Opcode },
8935     { PREFIX_TABLE (PREFIX_VEX_0F38F2) },
8936     { REG_TABLE (REG_VEX_0F38F3) },
8937     { Bad_Opcode },
8938     { PREFIX_TABLE (PREFIX_VEX_0F38F5) },
8939     { PREFIX_TABLE (PREFIX_VEX_0F38F6) },
8940     { PREFIX_TABLE (PREFIX_VEX_0F38F7) },
8941     /* f8 */
8942     { Bad_Opcode },
8943     { Bad_Opcode },
8944     { Bad_Opcode },
8945     { Bad_Opcode },
8946     { Bad_Opcode },
8947     { Bad_Opcode },
8948     { Bad_Opcode },
8949     { Bad_Opcode },
8950   },
8951   /* VEX_0F3A */
8952   {
8953     /* 00 */
8954     { PREFIX_TABLE (PREFIX_VEX_0F3A00) },
8955     { PREFIX_TABLE (PREFIX_VEX_0F3A01) },
8956     { PREFIX_TABLE (PREFIX_VEX_0F3A02) },
8957     { Bad_Opcode },
8958     { PREFIX_TABLE (PREFIX_VEX_0F3A04) },
8959     { PREFIX_TABLE (PREFIX_VEX_0F3A05) },
8960     { PREFIX_TABLE (PREFIX_VEX_0F3A06) },
8961     { Bad_Opcode },
8962     /* 08 */
8963     { PREFIX_TABLE (PREFIX_VEX_0F3A08) },
8964     { PREFIX_TABLE (PREFIX_VEX_0F3A09) },
8965     { PREFIX_TABLE (PREFIX_VEX_0F3A0A) },
8966     { PREFIX_TABLE (PREFIX_VEX_0F3A0B) },
8967     { PREFIX_TABLE (PREFIX_VEX_0F3A0C) },
8968     { PREFIX_TABLE (PREFIX_VEX_0F3A0D) },
8969     { PREFIX_TABLE (PREFIX_VEX_0F3A0E) },
8970     { PREFIX_TABLE (PREFIX_VEX_0F3A0F) },
8971     /* 10 */
8972     { Bad_Opcode },
8973     { Bad_Opcode },
8974     { Bad_Opcode },
8975     { Bad_Opcode },
8976     { PREFIX_TABLE (PREFIX_VEX_0F3A14) },
8977     { PREFIX_TABLE (PREFIX_VEX_0F3A15) },
8978     { PREFIX_TABLE (PREFIX_VEX_0F3A16) },
8979     { PREFIX_TABLE (PREFIX_VEX_0F3A17) },
8980     /* 18 */
8981     { PREFIX_TABLE (PREFIX_VEX_0F3A18) },
8982     { PREFIX_TABLE (PREFIX_VEX_0F3A19) },
8983     { Bad_Opcode },
8984     { Bad_Opcode },
8985     { Bad_Opcode },
8986     { PREFIX_TABLE (PREFIX_VEX_0F3A1D) },
8987     { Bad_Opcode },
8988     { Bad_Opcode },
8989     /* 20 */
8990     { PREFIX_TABLE (PREFIX_VEX_0F3A20) },
8991     { PREFIX_TABLE (PREFIX_VEX_0F3A21) },
8992     { PREFIX_TABLE (PREFIX_VEX_0F3A22) },
8993     { Bad_Opcode },
8994     { Bad_Opcode },
8995     { Bad_Opcode },
8996     { Bad_Opcode },
8997     { Bad_Opcode },
8998     /* 28 */
8999     { Bad_Opcode },
9000     { Bad_Opcode },
9001     { Bad_Opcode },
9002     { Bad_Opcode },
9003     { Bad_Opcode },
9004     { Bad_Opcode },
9005     { Bad_Opcode },
9006     { Bad_Opcode },
9007     /* 30 */
9008     { PREFIX_TABLE (PREFIX_VEX_0F3A30) },
9009     { PREFIX_TABLE (PREFIX_VEX_0F3A31) },
9010     { PREFIX_TABLE (PREFIX_VEX_0F3A32) },
9011     { PREFIX_TABLE (PREFIX_VEX_0F3A33) },
9012     { Bad_Opcode },
9013     { Bad_Opcode },
9014     { Bad_Opcode },
9015     { Bad_Opcode },
9016     /* 38 */
9017     { PREFIX_TABLE (PREFIX_VEX_0F3A38) },
9018     { PREFIX_TABLE (PREFIX_VEX_0F3A39) },
9019     { Bad_Opcode },
9020     { Bad_Opcode },
9021     { Bad_Opcode },
9022     { Bad_Opcode },
9023     { Bad_Opcode },
9024     { Bad_Opcode },
9025     /* 40 */
9026     { PREFIX_TABLE (PREFIX_VEX_0F3A40) },
9027     { PREFIX_TABLE (PREFIX_VEX_0F3A41) },
9028     { PREFIX_TABLE (PREFIX_VEX_0F3A42) },
9029     { Bad_Opcode },
9030     { PREFIX_TABLE (PREFIX_VEX_0F3A44) },
9031     { Bad_Opcode },
9032     { PREFIX_TABLE (PREFIX_VEX_0F3A46) },
9033     { Bad_Opcode },
9034     /* 48 */
9035     { PREFIX_TABLE (PREFIX_VEX_0F3A48) },
9036     { PREFIX_TABLE (PREFIX_VEX_0F3A49) },
9037     { PREFIX_TABLE (PREFIX_VEX_0F3A4A) },
9038     { PREFIX_TABLE (PREFIX_VEX_0F3A4B) },
9039     { PREFIX_TABLE (PREFIX_VEX_0F3A4C) },
9040     { Bad_Opcode },
9041     { Bad_Opcode },
9042     { Bad_Opcode },
9043     /* 50 */
9044     { Bad_Opcode },
9045     { Bad_Opcode },
9046     { Bad_Opcode },
9047     { Bad_Opcode },
9048     { Bad_Opcode },
9049     { Bad_Opcode },
9050     { Bad_Opcode },
9051     { Bad_Opcode },
9052     /* 58 */
9053     { Bad_Opcode },
9054     { Bad_Opcode },
9055     { Bad_Opcode },
9056     { Bad_Opcode },
9057     { PREFIX_TABLE (PREFIX_VEX_0F3A5C) },
9058     { PREFIX_TABLE (PREFIX_VEX_0F3A5D) },
9059     { PREFIX_TABLE (PREFIX_VEX_0F3A5E) },
9060     { PREFIX_TABLE (PREFIX_VEX_0F3A5F) },
9061     /* 60 */
9062     { PREFIX_TABLE (PREFIX_VEX_0F3A60) },
9063     { PREFIX_TABLE (PREFIX_VEX_0F3A61) },
9064     { PREFIX_TABLE (PREFIX_VEX_0F3A62) },
9065     { PREFIX_TABLE (PREFIX_VEX_0F3A63) },
9066     { Bad_Opcode },
9067     { Bad_Opcode },
9068     { Bad_Opcode },
9069     { Bad_Opcode },
9070     /* 68 */
9071     { PREFIX_TABLE (PREFIX_VEX_0F3A68) },
9072     { PREFIX_TABLE (PREFIX_VEX_0F3A69) },
9073     { PREFIX_TABLE (PREFIX_VEX_0F3A6A) },
9074     { PREFIX_TABLE (PREFIX_VEX_0F3A6B) },
9075     { PREFIX_TABLE (PREFIX_VEX_0F3A6C) },
9076     { PREFIX_TABLE (PREFIX_VEX_0F3A6D) },
9077     { PREFIX_TABLE (PREFIX_VEX_0F3A6E) },
9078     { PREFIX_TABLE (PREFIX_VEX_0F3A6F) },
9079     /* 70 */
9080     { Bad_Opcode },
9081     { Bad_Opcode },
9082     { Bad_Opcode },
9083     { Bad_Opcode },
9084     { Bad_Opcode },
9085     { Bad_Opcode },
9086     { Bad_Opcode },
9087     { Bad_Opcode },
9088     /* 78 */
9089     { PREFIX_TABLE (PREFIX_VEX_0F3A78) },
9090     { PREFIX_TABLE (PREFIX_VEX_0F3A79) },
9091     { PREFIX_TABLE (PREFIX_VEX_0F3A7A) },
9092     { PREFIX_TABLE (PREFIX_VEX_0F3A7B) },
9093     { PREFIX_TABLE (PREFIX_VEX_0F3A7C) },
9094     { PREFIX_TABLE (PREFIX_VEX_0F3A7D) },
9095     { PREFIX_TABLE (PREFIX_VEX_0F3A7E) },
9096     { PREFIX_TABLE (PREFIX_VEX_0F3A7F) },
9097     /* 80 */
9098     { Bad_Opcode },
9099     { Bad_Opcode },
9100     { Bad_Opcode },
9101     { Bad_Opcode },
9102     { Bad_Opcode },
9103     { Bad_Opcode },
9104     { Bad_Opcode },
9105     { Bad_Opcode },
9106     /* 88 */
9107     { Bad_Opcode },
9108     { Bad_Opcode },
9109     { Bad_Opcode },
9110     { Bad_Opcode },
9111     { Bad_Opcode },
9112     { Bad_Opcode },
9113     { Bad_Opcode },
9114     { Bad_Opcode },
9115     /* 90 */
9116     { Bad_Opcode },
9117     { Bad_Opcode },
9118     { Bad_Opcode },
9119     { Bad_Opcode },
9120     { Bad_Opcode },
9121     { Bad_Opcode },
9122     { Bad_Opcode },
9123     { Bad_Opcode },
9124     /* 98 */
9125     { Bad_Opcode },
9126     { Bad_Opcode },
9127     { Bad_Opcode },
9128     { Bad_Opcode },
9129     { Bad_Opcode },
9130     { Bad_Opcode },
9131     { Bad_Opcode },
9132     { Bad_Opcode },
9133     /* a0 */
9134     { Bad_Opcode },
9135     { Bad_Opcode },
9136     { Bad_Opcode },
9137     { Bad_Opcode },
9138     { Bad_Opcode },
9139     { Bad_Opcode },
9140     { Bad_Opcode },
9141     { Bad_Opcode },
9142     /* a8 */
9143     { Bad_Opcode },
9144     { Bad_Opcode },
9145     { Bad_Opcode },
9146     { Bad_Opcode },
9147     { Bad_Opcode },
9148     { Bad_Opcode },
9149     { Bad_Opcode },
9150     { Bad_Opcode },
9151     /* b0 */
9152     { Bad_Opcode },
9153     { Bad_Opcode },
9154     { Bad_Opcode },
9155     { Bad_Opcode },
9156     { Bad_Opcode },
9157     { Bad_Opcode },
9158     { Bad_Opcode },
9159     { Bad_Opcode },
9160     /* b8 */
9161     { Bad_Opcode },
9162     { Bad_Opcode },
9163     { Bad_Opcode },
9164     { Bad_Opcode },
9165     { Bad_Opcode },
9166     { Bad_Opcode },
9167     { Bad_Opcode },
9168     { Bad_Opcode },
9169     /* c0 */
9170     { Bad_Opcode },
9171     { Bad_Opcode },
9172     { Bad_Opcode },
9173     { Bad_Opcode },
9174     { Bad_Opcode },
9175     { Bad_Opcode },
9176     { Bad_Opcode },
9177     { Bad_Opcode },
9178     /* c8 */
9179     { Bad_Opcode },
9180     { Bad_Opcode },
9181     { Bad_Opcode },
9182     { Bad_Opcode },
9183     { Bad_Opcode },
9184     { Bad_Opcode },
9185     { PREFIX_TABLE(PREFIX_VEX_0F3ACE) },
9186     { PREFIX_TABLE(PREFIX_VEX_0F3ACF) },
9187     /* d0 */
9188     { Bad_Opcode },
9189     { Bad_Opcode },
9190     { Bad_Opcode },
9191     { Bad_Opcode },
9192     { Bad_Opcode },
9193     { Bad_Opcode },
9194     { Bad_Opcode },
9195     { Bad_Opcode },
9196     /* d8 */
9197     { Bad_Opcode },
9198     { Bad_Opcode },
9199     { Bad_Opcode },
9200     { Bad_Opcode },
9201     { Bad_Opcode },
9202     { Bad_Opcode },
9203     { Bad_Opcode },
9204     { PREFIX_TABLE (PREFIX_VEX_0F3ADF) },
9205     /* e0 */
9206     { Bad_Opcode },
9207     { Bad_Opcode },
9208     { Bad_Opcode },
9209     { Bad_Opcode },
9210     { Bad_Opcode },
9211     { Bad_Opcode },
9212     { Bad_Opcode },
9213     { Bad_Opcode },
9214     /* e8 */
9215     { Bad_Opcode },
9216     { Bad_Opcode },
9217     { Bad_Opcode },
9218     { Bad_Opcode },
9219     { Bad_Opcode },
9220     { Bad_Opcode },
9221     { Bad_Opcode },
9222     { Bad_Opcode },
9223     /* f0 */
9224     { PREFIX_TABLE (PREFIX_VEX_0F3AF0) },
9225     { Bad_Opcode },
9226     { Bad_Opcode },
9227     { Bad_Opcode },
9228     { Bad_Opcode },
9229     { Bad_Opcode },
9230     { Bad_Opcode },
9231     { Bad_Opcode },
9232     /* f8 */
9233     { Bad_Opcode },
9234     { Bad_Opcode },
9235     { Bad_Opcode },
9236     { Bad_Opcode },
9237     { Bad_Opcode },
9238     { Bad_Opcode },
9239     { Bad_Opcode },
9240     { Bad_Opcode },
9241   },
9242 };
9243
9244 #include "i386-dis-evex.h"
9245
9246 static const struct dis386 vex_len_table[][2] = {
9247   /* VEX_LEN_0F12_P_0_M_0 / VEX_LEN_0F12_P_2_M_0 */
9248   {
9249     { "vmovlpX",        { XM, Vex128, EXq }, 0 },
9250   },
9251
9252   /* VEX_LEN_0F12_P_0_M_1 */
9253   {
9254     { "vmovhlps",       { XM, Vex128, EXq }, 0 },
9255   },
9256
9257   /* VEX_LEN_0F13_M_0 */
9258   {
9259     { "vmovlpX",        { EXq, XM }, PREFIX_OPCODE },
9260   },
9261
9262   /* VEX_LEN_0F16_P_0_M_0 / VEX_LEN_0F16_P_2_M_0 */
9263   {
9264     { "vmovhpX",        { XM, Vex128, EXq }, 0 },
9265   },
9266
9267   /* VEX_LEN_0F16_P_0_M_1 */
9268   {
9269     { "vmovlhps",       { XM, Vex128, EXq }, 0 },
9270   },
9271
9272   /* VEX_LEN_0F17_M_0 */
9273   {
9274     { "vmovhpX",        { EXq, XM }, PREFIX_OPCODE },
9275   },
9276
9277   /* VEX_LEN_0F41_P_0 */
9278   {
9279     { Bad_Opcode },
9280     { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) },
9281   },
9282   /* VEX_LEN_0F41_P_2 */
9283   {
9284     { Bad_Opcode },
9285     { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) },
9286   },
9287   /* VEX_LEN_0F42_P_0 */
9288   {
9289     { Bad_Opcode },
9290     { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) },
9291   },
9292   /* VEX_LEN_0F42_P_2 */
9293   {
9294     { Bad_Opcode },
9295     { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) },
9296   },
9297   /* VEX_LEN_0F44_P_0 */
9298   {
9299     { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) },
9300   },
9301   /* VEX_LEN_0F44_P_2 */
9302   {
9303     { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) },
9304   },
9305   /* VEX_LEN_0F45_P_0 */
9306   {
9307     { Bad_Opcode },
9308     { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) },
9309   },
9310   /* VEX_LEN_0F45_P_2 */
9311   {
9312     { Bad_Opcode },
9313     { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) },
9314   },
9315   /* VEX_LEN_0F46_P_0 */
9316   {
9317     { Bad_Opcode },
9318     { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) },
9319   },
9320   /* VEX_LEN_0F46_P_2 */
9321   {
9322     { Bad_Opcode },
9323     { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) },
9324   },
9325   /* VEX_LEN_0F47_P_0 */
9326   {
9327     { Bad_Opcode },
9328     { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) },
9329   },
9330   /* VEX_LEN_0F47_P_2 */
9331   {
9332     { Bad_Opcode },
9333     { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) },
9334   },
9335   /* VEX_LEN_0F4A_P_0 */
9336   {
9337     { Bad_Opcode },
9338     { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) },
9339   },
9340   /* VEX_LEN_0F4A_P_2 */
9341   {
9342     { Bad_Opcode },
9343     { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) },
9344   },
9345   /* VEX_LEN_0F4B_P_0 */
9346   {
9347     { Bad_Opcode },
9348     { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) },
9349   },
9350   /* VEX_LEN_0F4B_P_2 */
9351   {
9352     { Bad_Opcode },
9353     { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) },
9354   },
9355
9356   /* VEX_LEN_0F6E_P_2 */
9357   {
9358     { "vmovK",          { XMScalar, Edq }, 0 },
9359   },
9360
9361   /* VEX_LEN_0F77_P_1 */
9362   {
9363     { "vzeroupper",     { XX }, 0 },
9364     { "vzeroall",       { XX }, 0 },
9365   },
9366
9367   /* VEX_LEN_0F7E_P_1 */
9368   {
9369     { "vmovq",          { XMScalar, EXxmm_mq }, 0 },
9370   },
9371
9372   /* VEX_LEN_0F7E_P_2 */
9373   {
9374     { "vmovK",          { Edq, XMScalar }, 0 },
9375   },
9376
9377   /* VEX_LEN_0F90_P_0 */
9378   {
9379     { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) },
9380   },
9381
9382   /* VEX_LEN_0F90_P_2 */
9383   {
9384     { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) },
9385   },
9386
9387   /* VEX_LEN_0F91_P_0 */
9388   {
9389     { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) },
9390   },
9391
9392   /* VEX_LEN_0F91_P_2 */
9393   {
9394     { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) },
9395   },
9396
9397   /* VEX_LEN_0F92_P_0 */
9398   {
9399     { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) },
9400   },
9401
9402   /* VEX_LEN_0F92_P_2 */
9403   {
9404     { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) },
9405   },
9406
9407   /* VEX_LEN_0F92_P_3 */
9408   {
9409     { MOD_TABLE (MOD_VEX_0F92_P_3_LEN_0) },
9410   },
9411
9412   /* VEX_LEN_0F93_P_0 */
9413   {
9414     { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) },
9415   },
9416
9417   /* VEX_LEN_0F93_P_2 */
9418   {
9419     { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) },
9420   },
9421
9422   /* VEX_LEN_0F93_P_3 */
9423   {
9424     { MOD_TABLE (MOD_VEX_0F93_P_3_LEN_0) },
9425   },
9426
9427   /* VEX_LEN_0F98_P_0 */
9428   {
9429     { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) },
9430   },
9431
9432   /* VEX_LEN_0F98_P_2 */
9433   {
9434     { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) },
9435   },
9436
9437   /* VEX_LEN_0F99_P_0 */
9438   {
9439     { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) },
9440   },
9441
9442   /* VEX_LEN_0F99_P_2 */
9443   {
9444     { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0) },
9445   },
9446
9447   /* VEX_LEN_0FAE_R_2_M_0 */
9448   {
9449     { "vldmxcsr",       { Md }, 0 },
9450   },
9451
9452   /* VEX_LEN_0FAE_R_3_M_0 */
9453   {
9454     { "vstmxcsr",       { Md }, 0 },
9455   },
9456
9457   /* VEX_LEN_0FC4_P_2 */
9458   {
9459     { "vpinsrw",        { XM, Vex128, Edqw, Ib }, 0 },
9460   },
9461
9462   /* VEX_LEN_0FC5_P_2 */
9463   {
9464     { "vpextrw",        { Gdq, XS, Ib }, 0 },
9465   },
9466
9467   /* VEX_LEN_0FD6_P_2 */
9468   {
9469     { "vmovq",          { EXqVexScalarS, XMScalar }, 0 },
9470   },
9471
9472   /* VEX_LEN_0FF7_P_2 */
9473   {
9474     { "vmaskmovdqu",    { XM, XS }, 0 },
9475   },
9476
9477   /* VEX_LEN_0F3816_P_2 */
9478   {
9479     { Bad_Opcode },
9480     { VEX_W_TABLE (VEX_W_0F3816_P_2) },
9481   },
9482
9483   /* VEX_LEN_0F3819_P_2 */
9484   {
9485     { Bad_Opcode },
9486     { VEX_W_TABLE (VEX_W_0F3819_P_2) },
9487   },
9488
9489   /* VEX_LEN_0F381A_P_2_M_0 */
9490   {
9491     { Bad_Opcode },
9492     { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) },
9493   },
9494
9495   /* VEX_LEN_0F3836_P_2 */
9496   {
9497     { Bad_Opcode },
9498     { VEX_W_TABLE (VEX_W_0F3836_P_2) },
9499   },
9500
9501   /* VEX_LEN_0F3841_P_2 */
9502   {
9503     { "vphminposuw",    { XM, EXx }, 0 },
9504   },
9505
9506   /* VEX_LEN_0F385A_P_2_M_0 */
9507   {
9508     { Bad_Opcode },
9509     { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) },
9510   },
9511
9512   /* VEX_LEN_0F38DB_P_2 */
9513   {
9514     { "vaesimc",        { XM, EXx }, 0 },
9515   },
9516
9517   /* VEX_LEN_0F38F2_P_0 */
9518   {
9519     { "andnS",          { Gdq, VexGdq, Edq }, 0 },
9520   },
9521
9522   /* VEX_LEN_0F38F3_R_1_P_0 */
9523   {
9524     { "blsrS",          { VexGdq, Edq }, 0 },
9525   },
9526
9527   /* VEX_LEN_0F38F3_R_2_P_0 */
9528   {
9529     { "blsmskS",        { VexGdq, Edq }, 0 },
9530   },
9531
9532   /* VEX_LEN_0F38F3_R_3_P_0 */
9533   {
9534     { "blsiS",          { VexGdq, Edq }, 0 },
9535   },
9536
9537   /* VEX_LEN_0F38F5_P_0 */
9538   {
9539     { "bzhiS",          { Gdq, Edq, VexGdq }, 0 },
9540   },
9541
9542   /* VEX_LEN_0F38F5_P_1 */
9543   {
9544     { "pextS",          { Gdq, VexGdq, Edq }, 0 },
9545   },
9546
9547   /* VEX_LEN_0F38F5_P_3 */
9548   {
9549     { "pdepS",          { Gdq, VexGdq, Edq }, 0 },
9550   },
9551
9552   /* VEX_LEN_0F38F6_P_3 */
9553   {
9554     { "mulxS",          { Gdq, VexGdq, Edq }, 0 },
9555   },
9556
9557   /* VEX_LEN_0F38F7_P_0 */
9558   {
9559     { "bextrS",         { Gdq, Edq, VexGdq }, 0 },
9560   },
9561
9562   /* VEX_LEN_0F38F7_P_1 */
9563   {
9564     { "sarxS",          { Gdq, Edq, VexGdq }, 0 },
9565   },
9566
9567   /* VEX_LEN_0F38F7_P_2 */
9568   {
9569     { "shlxS",          { Gdq, Edq, VexGdq }, 0 },
9570   },
9571
9572   /* VEX_LEN_0F38F7_P_3 */
9573   {
9574     { "shrxS",          { Gdq, Edq, VexGdq }, 0 },
9575   },
9576
9577   /* VEX_LEN_0F3A00_P_2 */
9578   {
9579     { Bad_Opcode },
9580     { VEX_W_TABLE (VEX_W_0F3A00_P_2) },
9581   },
9582
9583   /* VEX_LEN_0F3A01_P_2 */
9584   {
9585     { Bad_Opcode },
9586     { VEX_W_TABLE (VEX_W_0F3A01_P_2) },
9587   },
9588
9589   /* VEX_LEN_0F3A06_P_2 */
9590   {
9591     { Bad_Opcode },
9592     { VEX_W_TABLE (VEX_W_0F3A06_P_2) },
9593   },
9594
9595   /* VEX_LEN_0F3A14_P_2 */
9596   {
9597     { "vpextrb",        { Edqb, XM, Ib }, 0 },
9598   },
9599
9600   /* VEX_LEN_0F3A15_P_2 */
9601   {
9602     { "vpextrw",        { Edqw, XM, Ib }, 0 },
9603   },
9604
9605   /* VEX_LEN_0F3A16_P_2  */
9606   {
9607     { "vpextrK",        { Edq, XM, Ib }, 0 },
9608   },
9609
9610   /* VEX_LEN_0F3A17_P_2 */
9611   {
9612     { "vextractps",     { Edqd, XM, Ib }, 0 },
9613   },
9614
9615   /* VEX_LEN_0F3A18_P_2 */
9616   {
9617     { Bad_Opcode },
9618     { VEX_W_TABLE (VEX_W_0F3A18_P_2) },
9619   },
9620
9621   /* VEX_LEN_0F3A19_P_2 */
9622   {
9623     { Bad_Opcode },
9624     { VEX_W_TABLE (VEX_W_0F3A19_P_2) },
9625   },
9626
9627   /* VEX_LEN_0F3A20_P_2 */
9628   {
9629     { "vpinsrb",        { XM, Vex128, Edqb, Ib }, 0 },
9630   },
9631
9632   /* VEX_LEN_0F3A21_P_2 */
9633   {
9634     { "vinsertps",      { XM, Vex128, EXd, Ib }, 0 },
9635   },
9636
9637   /* VEX_LEN_0F3A22_P_2 */
9638   {
9639     { "vpinsrK",        { XM, Vex128, Edq, Ib }, 0 },
9640   },
9641
9642   /* VEX_LEN_0F3A30_P_2 */
9643   {
9644     { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) },
9645   },
9646
9647   /* VEX_LEN_0F3A31_P_2 */
9648   {
9649     { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0) },
9650   },
9651
9652   /* VEX_LEN_0F3A32_P_2 */
9653   {
9654     { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) },
9655   },
9656
9657   /* VEX_LEN_0F3A33_P_2 */
9658   {
9659     { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0) },
9660   },
9661
9662   /* VEX_LEN_0F3A38_P_2 */
9663   {
9664     { Bad_Opcode },
9665     { VEX_W_TABLE (VEX_W_0F3A38_P_2) },
9666   },
9667
9668   /* VEX_LEN_0F3A39_P_2 */
9669   {
9670     { Bad_Opcode },
9671     { VEX_W_TABLE (VEX_W_0F3A39_P_2) },
9672   },
9673
9674   /* VEX_LEN_0F3A41_P_2 */
9675   {
9676     { "vdppd",          { XM, Vex128, EXx, Ib }, 0 },
9677   },
9678
9679   /* VEX_LEN_0F3A46_P_2 */
9680   {
9681     { Bad_Opcode },
9682     { VEX_W_TABLE (VEX_W_0F3A46_P_2) },
9683   },
9684
9685   /* VEX_LEN_0F3A60_P_2 */
9686   {
9687     { "vpcmpestrm",     { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 },
9688   },
9689
9690   /* VEX_LEN_0F3A61_P_2 */
9691   {
9692     { "vpcmpestri",     { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 },
9693   },
9694
9695   /* VEX_LEN_0F3A62_P_2 */
9696   {
9697     { "vpcmpistrm",     { XM, EXx, Ib }, 0 },
9698   },
9699
9700   /* VEX_LEN_0F3A63_P_2 */
9701   {
9702     { "vpcmpistri",     { XM, EXx, Ib }, 0 },
9703   },
9704
9705   /* VEX_LEN_0F3ADF_P_2 */
9706   {
9707     { "vaeskeygenassist", { XM, EXx, Ib }, 0 },
9708   },
9709
9710   /* VEX_LEN_0F3AF0_P_3 */
9711   {
9712     { "rorxS",          { Gdq, Edq, Ib }, 0 },
9713   },
9714
9715   /* VEX_LEN_0FXOP_08_85 */
9716   {
9717     { VEX_W_TABLE (VEX_W_0FXOP_08_85_L_0) },
9718   },
9719
9720   /* VEX_LEN_0FXOP_08_86 */
9721   {
9722     { VEX_W_TABLE (VEX_W_0FXOP_08_86_L_0) },
9723   },
9724
9725   /* VEX_LEN_0FXOP_08_87 */
9726   {
9727     { VEX_W_TABLE (VEX_W_0FXOP_08_87_L_0) },
9728   },
9729
9730   /* VEX_LEN_0FXOP_08_8E */
9731   {
9732     { VEX_W_TABLE (VEX_W_0FXOP_08_8E_L_0) },
9733   },
9734
9735   /* VEX_LEN_0FXOP_08_8F */
9736   {
9737     { VEX_W_TABLE (VEX_W_0FXOP_08_8F_L_0) },
9738   },
9739
9740   /* VEX_LEN_0FXOP_08_95 */
9741   {
9742     { VEX_W_TABLE (VEX_W_0FXOP_08_95_L_0) },
9743   },
9744
9745   /* VEX_LEN_0FXOP_08_96 */
9746   {
9747     { VEX_W_TABLE (VEX_W_0FXOP_08_96_L_0) },
9748   },
9749
9750   /* VEX_LEN_0FXOP_08_97 */
9751   {
9752     { VEX_W_TABLE (VEX_W_0FXOP_08_97_L_0) },
9753   },
9754
9755   /* VEX_LEN_0FXOP_08_9E */
9756   {
9757     { VEX_W_TABLE (VEX_W_0FXOP_08_9E_L_0) },
9758   },
9759
9760   /* VEX_LEN_0FXOP_08_9F */
9761   {
9762     { VEX_W_TABLE (VEX_W_0FXOP_08_9F_L_0) },
9763   },
9764
9765   /* VEX_LEN_0FXOP_08_A3 */
9766   {
9767     { "vpperm",         { XM, Vex, EXx, XMVexI4 }, 0 },
9768   },
9769
9770   /* VEX_LEN_0FXOP_08_A6 */
9771   {
9772     { VEX_W_TABLE (VEX_W_0FXOP_08_A6_L_0) },
9773   },
9774
9775   /* VEX_LEN_0FXOP_08_B6 */
9776   {
9777     { VEX_W_TABLE (VEX_W_0FXOP_08_B6_L_0) },
9778   },
9779
9780   /* VEX_LEN_0FXOP_08_C0 */
9781   {
9782     { VEX_W_TABLE (VEX_W_0FXOP_08_C0_L_0) },
9783   },
9784
9785   /* VEX_LEN_0FXOP_08_C1 */
9786   {
9787     { VEX_W_TABLE (VEX_W_0FXOP_08_C1_L_0) },
9788   },
9789
9790   /* VEX_LEN_0FXOP_08_C2 */
9791   {
9792     { VEX_W_TABLE (VEX_W_0FXOP_08_C2_L_0) },
9793   },
9794
9795   /* VEX_LEN_0FXOP_08_C3 */
9796   {
9797     { VEX_W_TABLE (VEX_W_0FXOP_08_C3_L_0) },
9798   },
9799
9800   /* VEX_LEN_0FXOP_08_CC */
9801   {
9802     { VEX_W_TABLE (VEX_W_0FXOP_08_CC_L_0) },
9803   },
9804
9805   /* VEX_LEN_0FXOP_08_CD */
9806   {
9807     { VEX_W_TABLE (VEX_W_0FXOP_08_CD_L_0) },
9808   },
9809
9810   /* VEX_LEN_0FXOP_08_CE */
9811   {
9812     { VEX_W_TABLE (VEX_W_0FXOP_08_CE_L_0) },
9813   },
9814
9815   /* VEX_LEN_0FXOP_08_CF */
9816   {
9817     { VEX_W_TABLE (VEX_W_0FXOP_08_CF_L_0) },
9818   },
9819
9820   /* VEX_LEN_0FXOP_08_EC */
9821   {
9822     { VEX_W_TABLE (VEX_W_0FXOP_08_EC_L_0) },
9823   },
9824
9825   /* VEX_LEN_0FXOP_08_ED */
9826   {
9827     { VEX_W_TABLE (VEX_W_0FXOP_08_ED_L_0) },
9828   },
9829
9830   /* VEX_LEN_0FXOP_08_EE */
9831   {
9832     { VEX_W_TABLE (VEX_W_0FXOP_08_EE_L_0) },
9833   },
9834
9835   /* VEX_LEN_0FXOP_08_EF */
9836   {
9837     { VEX_W_TABLE (VEX_W_0FXOP_08_EF_L_0) },
9838   },
9839
9840   /* VEX_LEN_0FXOP_09_01 */
9841   {
9842     { REG_TABLE (REG_0FXOP_09_01_L_0) },
9843   },
9844
9845   /* VEX_LEN_0FXOP_09_02 */
9846   {
9847     { REG_TABLE (REG_0FXOP_09_02_L_0) },
9848   },
9849
9850   /* VEX_LEN_0FXOP_09_12_M_1 */
9851   {
9852     { REG_TABLE (REG_0FXOP_09_12_M_1_L_0) },
9853   },
9854
9855   /* VEX_LEN_0FXOP_09_82_W_0 */
9856   {
9857     { "vfrczss",        { XM, EXd }, 0 },
9858   },
9859
9860   /* VEX_LEN_0FXOP_09_83_W_0 */
9861   {
9862     { "vfrczsd",        { XM, EXq }, 0 },
9863   },
9864
9865   /* VEX_LEN_0FXOP_09_90 */
9866   {
9867     { "vprotb",         { XM, EXx, VexW }, 0 },
9868   },
9869
9870   /* VEX_LEN_0FXOP_09_91 */
9871   {
9872     { "vprotw",         { XM, EXx, VexW }, 0 },
9873   },
9874
9875   /* VEX_LEN_0FXOP_09_92 */
9876   {
9877     { "vprotd",         { XM, EXx, VexW }, 0 },
9878   },
9879
9880   /* VEX_LEN_0FXOP_09_93 */
9881   {
9882     { "vprotq",         { XM, EXx, VexW }, 0 },
9883   },
9884
9885   /* VEX_LEN_0FXOP_09_94 */
9886   {
9887     { "vpshlb",         { XM, EXx, VexW }, 0 },
9888   },
9889
9890   /* VEX_LEN_0FXOP_09_95 */
9891   {
9892     { "vpshlw",         { XM, EXx, VexW }, 0 },
9893   },
9894
9895   /* VEX_LEN_0FXOP_09_96 */
9896   {
9897     { "vpshld",         { XM, EXx, VexW }, 0 },
9898   },
9899
9900   /* VEX_LEN_0FXOP_09_97 */
9901   {
9902     { "vpshlq",         { XM, EXx, VexW }, 0 },
9903   },
9904
9905   /* VEX_LEN_0FXOP_09_98 */
9906   {
9907     { "vpshab",         { XM, EXx, VexW }, 0 },
9908   },
9909
9910   /* VEX_LEN_0FXOP_09_99 */
9911   {
9912     { "vpshaw",         { XM, EXx, VexW }, 0 },
9913   },
9914
9915   /* VEX_LEN_0FXOP_09_9A */
9916   {
9917     { "vpshad",         { XM, EXx, VexW }, 0 },
9918   },
9919
9920   /* VEX_LEN_0FXOP_09_9B */
9921   {
9922     { "vpshaq",         { XM, EXx, VexW }, 0 },
9923   },
9924
9925   /* VEX_LEN_0FXOP_09_C1 */
9926   {
9927     { VEX_W_TABLE (VEX_W_0FXOP_09_C1_L_0) },
9928   },
9929
9930   /* VEX_LEN_0FXOP_09_C2 */
9931   {
9932     { VEX_W_TABLE (VEX_W_0FXOP_09_C2_L_0) },
9933   },
9934
9935   /* VEX_LEN_0FXOP_09_C3 */
9936   {
9937     { VEX_W_TABLE (VEX_W_0FXOP_09_C3_L_0) },
9938   },
9939
9940   /* VEX_LEN_0FXOP_09_C6 */
9941   {
9942     { VEX_W_TABLE (VEX_W_0FXOP_09_C6_L_0) },
9943   },
9944
9945   /* VEX_LEN_0FXOP_09_C7 */
9946   {
9947     { VEX_W_TABLE (VEX_W_0FXOP_09_C7_L_0) },
9948   },
9949
9950   /* VEX_LEN_0FXOP_09_CB */
9951   {
9952     { VEX_W_TABLE (VEX_W_0FXOP_09_CB_L_0) },
9953   },
9954
9955   /* VEX_LEN_0FXOP_09_D1 */
9956   {
9957     { VEX_W_TABLE (VEX_W_0FXOP_09_D1_L_0) },
9958   },
9959
9960   /* VEX_LEN_0FXOP_09_D2 */
9961   {
9962     { VEX_W_TABLE (VEX_W_0FXOP_09_D2_L_0) },
9963   },
9964
9965   /* VEX_LEN_0FXOP_09_D3 */
9966   {
9967     { VEX_W_TABLE (VEX_W_0FXOP_09_D3_L_0) },
9968   },
9969
9970   /* VEX_LEN_0FXOP_09_D6 */
9971   {
9972     { VEX_W_TABLE (VEX_W_0FXOP_09_D6_L_0) },
9973   },
9974
9975   /* VEX_LEN_0FXOP_09_D7 */
9976   {
9977     { VEX_W_TABLE (VEX_W_0FXOP_09_D7_L_0) },
9978   },
9979
9980   /* VEX_LEN_0FXOP_09_DB */
9981   {
9982     { VEX_W_TABLE (VEX_W_0FXOP_09_DB_L_0) },
9983   },
9984
9985   /* VEX_LEN_0FXOP_09_E1 */
9986   {
9987     { VEX_W_TABLE (VEX_W_0FXOP_09_E1_L_0) },
9988   },
9989
9990   /* VEX_LEN_0FXOP_09_E2 */
9991   {
9992     { VEX_W_TABLE (VEX_W_0FXOP_09_E2_L_0) },
9993   },
9994
9995   /* VEX_LEN_0FXOP_09_E3 */
9996   {
9997     { VEX_W_TABLE (VEX_W_0FXOP_09_E3_L_0) },
9998   },
9999
10000   /* VEX_LEN_0FXOP_0A_12 */
10001   {
10002     { REG_TABLE (REG_0FXOP_0A_12_L_0) },
10003   },
10004 };
10005
10006 #include "i386-dis-evex-len.h"
10007
10008 static const struct dis386 vex_w_table[][2] = {
10009   {
10010     /* VEX_W_0F41_P_0_LEN_1 */
10011     { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1) },
10012     { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1) },
10013   },
10014   {
10015     /* VEX_W_0F41_P_2_LEN_1 */
10016     { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1) },
10017     { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1) }
10018   },
10019   {
10020     /* VEX_W_0F42_P_0_LEN_1 */
10021     { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1) },
10022     { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1) },
10023   },
10024   {
10025     /* VEX_W_0F42_P_2_LEN_1 */
10026     { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1) },
10027     { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1) },
10028   },
10029   {
10030     /* VEX_W_0F44_P_0_LEN_0 */
10031     { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1) },
10032     { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1) },
10033   },
10034   {
10035     /* VEX_W_0F44_P_2_LEN_0 */
10036     { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1) },
10037     { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1) },
10038   },
10039   {
10040     /* VEX_W_0F45_P_0_LEN_1 */
10041     { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1) },
10042     { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1) },
10043   },
10044   {
10045     /* VEX_W_0F45_P_2_LEN_1 */
10046     { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1) },
10047     { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1) },
10048   },
10049   {
10050     /* VEX_W_0F46_P_0_LEN_1 */
10051     { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1) },
10052     { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1) },
10053   },
10054   {
10055     /* VEX_W_0F46_P_2_LEN_1 */
10056     { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1) },
10057     { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1) },
10058   },
10059   {
10060     /* VEX_W_0F47_P_0_LEN_1 */
10061     { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1) },
10062     { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1) },
10063   },
10064   {
10065     /* VEX_W_0F47_P_2_LEN_1 */
10066     { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1) },
10067     { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1) },
10068   },
10069   {
10070     /* VEX_W_0F4A_P_0_LEN_1 */
10071     { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1) },
10072     { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1) },
10073   },
10074   {
10075     /* VEX_W_0F4A_P_2_LEN_1 */
10076     { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1) },
10077     { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1) },
10078   },
10079   {
10080     /* VEX_W_0F4B_P_0_LEN_1 */
10081     { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1) },
10082     { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1) },
10083   },
10084   {
10085     /* VEX_W_0F4B_P_2_LEN_1 */
10086     { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1) },
10087   },
10088   {
10089     /* VEX_W_0F90_P_0_LEN_0 */
10090     { "kmovw",          { MaskG, MaskE }, 0 },
10091     { "kmovq",          { MaskG, MaskE }, 0 },
10092   },
10093   {
10094     /* VEX_W_0F90_P_2_LEN_0 */
10095     { "kmovb",          { MaskG, MaskBDE }, 0 },
10096     { "kmovd",          { MaskG, MaskBDE }, 0 },
10097   },
10098   {
10099     /* VEX_W_0F91_P_0_LEN_0 */
10100     { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0) },
10101     { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0) },
10102   },
10103   {
10104     /* VEX_W_0F91_P_2_LEN_0 */
10105     { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0) },
10106     { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0) },
10107   },
10108   {
10109     /* VEX_W_0F92_P_0_LEN_0 */
10110     { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0) },
10111   },
10112   {
10113     /* VEX_W_0F92_P_2_LEN_0 */
10114     { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0) },
10115   },
10116   {
10117     /* VEX_W_0F93_P_0_LEN_0 */
10118     { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0) },
10119   },
10120   {
10121     /* VEX_W_0F93_P_2_LEN_0 */
10122     { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0) },
10123   },
10124   {
10125     /* VEX_W_0F98_P_0_LEN_0 */
10126     { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0) },
10127     { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0) },
10128   },
10129   {
10130     /* VEX_W_0F98_P_2_LEN_0 */
10131     { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0) },
10132     { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0) },
10133   },
10134   {
10135     /* VEX_W_0F99_P_0_LEN_0 */
10136     { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0) },
10137     { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0) },
10138   },
10139   {
10140     /* VEX_W_0F99_P_2_LEN_0 */
10141     { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0) },
10142     { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0) },
10143   },
10144   {
10145     /* VEX_W_0F380C_P_2  */
10146     { "vpermilps",      { XM, Vex, EXx }, 0 },
10147   },
10148   {
10149     /* VEX_W_0F380D_P_2  */
10150     { "vpermilpd",      { XM, Vex, EXx }, 0 },
10151   },
10152   {
10153     /* VEX_W_0F380E_P_2  */
10154     { "vtestps",        { XM, EXx }, 0 },
10155   },
10156   {
10157     /* VEX_W_0F380F_P_2  */
10158     { "vtestpd",        { XM, EXx }, 0 },
10159   },
10160   {
10161     /* VEX_W_0F3813_P_2 */
10162     { "vcvtph2ps", { XM, EXxmmq }, 0 },
10163   },
10164   {
10165     /* VEX_W_0F3816_P_2  */
10166     { "vpermps",        { XM, Vex, EXx }, 0 },
10167   },
10168   {
10169     /* VEX_W_0F3818_P_2 */
10170     { "vbroadcastss",   { XM, EXxmm_md }, 0 },
10171   },
10172   {
10173     /* VEX_W_0F3819_P_2 */
10174     { "vbroadcastsd",   { XM, EXxmm_mq }, 0 },
10175   },
10176   {
10177     /* VEX_W_0F381A_P_2_M_0 */
10178     { "vbroadcastf128", { XM, Mxmm }, 0 },
10179   },
10180   {
10181     /* VEX_W_0F382C_P_2_M_0 */
10182     { "vmaskmovps",     { XM, Vex, Mx }, 0 },
10183   },
10184   {
10185     /* VEX_W_0F382D_P_2_M_0 */
10186     { "vmaskmovpd",     { XM, Vex, Mx }, 0 },
10187   },
10188   {
10189     /* VEX_W_0F382E_P_2_M_0 */
10190     { "vmaskmovps",     { Mx, Vex, XM }, 0 },
10191   },
10192   {
10193     /* VEX_W_0F382F_P_2_M_0 */
10194     { "vmaskmovpd",     { Mx, Vex, XM }, 0 },
10195   },
10196   {
10197     /* VEX_W_0F3836_P_2  */
10198     { "vpermd",         { XM, Vex, EXx }, 0 },
10199   },
10200   {
10201     /* VEX_W_0F3846_P_2 */
10202     { "vpsravd",        { XM, Vex, EXx }, 0 },
10203   },
10204   {
10205     /* VEX_W_0F3858_P_2 */
10206     { "vpbroadcastd", { XM, EXxmm_md }, 0 },
10207   },
10208   {
10209     /* VEX_W_0F3859_P_2 */
10210     { "vpbroadcastq",   { XM, EXxmm_mq }, 0 },
10211   },
10212   {
10213     /* VEX_W_0F385A_P_2_M_0 */
10214     { "vbroadcasti128", { XM, Mxmm }, 0 },
10215   },
10216   {
10217     /* VEX_W_0F3878_P_2 */
10218     { "vpbroadcastb",   { XM, EXxmm_mb }, 0 },
10219   },
10220   {
10221     /* VEX_W_0F3879_P_2 */
10222     { "vpbroadcastw",   { XM, EXxmm_mw }, 0 },
10223   },
10224   {
10225     /* VEX_W_0F38CF_P_2 */
10226     { "vgf2p8mulb", { XM, Vex, EXx }, 0 },
10227   },
10228   {
10229     /* VEX_W_0F3A00_P_2 */
10230     { Bad_Opcode },
10231     { "vpermq",         { XM, EXx, Ib }, 0 },
10232   },
10233   {
10234     /* VEX_W_0F3A01_P_2 */
10235     { Bad_Opcode },
10236     { "vpermpd",        { XM, EXx, Ib }, 0 },
10237   },
10238   {
10239     /* VEX_W_0F3A02_P_2 */
10240     { "vpblendd",       { XM, Vex, EXx, Ib }, 0 },
10241   },
10242   {
10243     /* VEX_W_0F3A04_P_2 */
10244     { "vpermilps",      { XM, EXx, Ib }, 0 },
10245   },
10246   {
10247     /* VEX_W_0F3A05_P_2 */
10248     { "vpermilpd",      { XM, EXx, Ib }, 0 },
10249   },
10250   {
10251     /* VEX_W_0F3A06_P_2 */
10252     { "vperm2f128",     { XM, Vex256, EXx, Ib }, 0 },
10253   },
10254   {
10255     /* VEX_W_0F3A18_P_2 */
10256     { "vinsertf128",    { XM, Vex256, EXxmm, Ib }, 0 },
10257   },
10258   {
10259     /* VEX_W_0F3A19_P_2 */
10260     { "vextractf128",   { EXxmm, XM, Ib }, 0 },
10261   },
10262   {
10263     /* VEX_W_0F3A1D_P_2 */
10264     { "vcvtps2ph", { EXxmmq, XM, EXxEVexS, Ib }, 0 },
10265   },
10266   {
10267     /* VEX_W_0F3A30_P_2_LEN_0 */
10268     { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0) },
10269     { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0) },
10270   },
10271   {
10272     /* VEX_W_0F3A31_P_2_LEN_0 */
10273     { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0) },
10274     { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0) },
10275   },
10276   {
10277     /* VEX_W_0F3A32_P_2_LEN_0 */
10278     { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0) },
10279     { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0) },
10280   },
10281   {
10282     /* VEX_W_0F3A33_P_2_LEN_0 */
10283     { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0) },
10284     { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0) },
10285   },
10286   {
10287     /* VEX_W_0F3A38_P_2 */
10288     { "vinserti128",    { XM, Vex256, EXxmm, Ib }, 0 },
10289   },
10290   {
10291     /* VEX_W_0F3A39_P_2 */
10292     { "vextracti128",   { EXxmm, XM, Ib }, 0 },
10293   },
10294   {
10295     /* VEX_W_0F3A46_P_2 */
10296     { "vperm2i128",     { XM, Vex256, EXx, Ib }, 0 },
10297   },
10298   {
10299     /* VEX_W_0F3A4A_P_2 */
10300     { "vblendvps",      { XM, Vex, EXx, XMVexI4 }, 0 },
10301   },
10302   {
10303     /* VEX_W_0F3A4B_P_2 */
10304     { "vblendvpd",      { XM, Vex, EXx, XMVexI4 }, 0 },
10305   },
10306   {
10307     /* VEX_W_0F3A4C_P_2 */
10308     { "vpblendvb",      { XM, Vex, EXx, XMVexI4 }, 0 },
10309   },
10310   {
10311     /* VEX_W_0F3ACE_P_2 */
10312     { Bad_Opcode },
10313     { "vgf2p8affineqb", { XM, Vex, EXx, Ib }, 0 },
10314   },
10315   {
10316     /* VEX_W_0F3ACF_P_2 */
10317     { Bad_Opcode },
10318     { "vgf2p8affineinvqb",  { XM, Vex, EXx, Ib }, 0 },
10319   },
10320   /* VEX_W_0FXOP_08_85_L_0 */
10321   {
10322     { "vpmacssww",      { XM, Vex, EXx, XMVexI4 }, 0 },
10323   },
10324   /* VEX_W_0FXOP_08_86_L_0 */
10325   {
10326     { "vpmacsswd",      { XM, Vex, EXx, XMVexI4 }, 0 },
10327   },
10328   /* VEX_W_0FXOP_08_87_L_0 */
10329   {
10330     { "vpmacssdql",     { XM, Vex, EXx, XMVexI4 }, 0 },
10331   },
10332   /* VEX_W_0FXOP_08_8E_L_0 */
10333   {
10334     { "vpmacssdd",      { XM, Vex, EXx, XMVexI4 }, 0 },
10335   },
10336   /* VEX_W_0FXOP_08_8F_L_0 */
10337   {
10338     { "vpmacssdqh",     { XM, Vex, EXx, XMVexI4 }, 0 },
10339   },
10340   /* VEX_W_0FXOP_08_95_L_0 */
10341   {
10342     { "vpmacsww",       { XM, Vex, EXx, XMVexI4 }, 0 },
10343   },
10344   /* VEX_W_0FXOP_08_96_L_0 */
10345   {
10346     { "vpmacswd",       { XM, Vex, EXx, XMVexI4 }, 0 },
10347   },
10348   /* VEX_W_0FXOP_08_97_L_0 */
10349   {
10350     { "vpmacsdql",      { XM, Vex, EXx, XMVexI4 }, 0 },
10351   },
10352   /* VEX_W_0FXOP_08_9E_L_0 */
10353   {
10354     { "vpmacsdd",       { XM, Vex, EXx, XMVexI4 }, 0 },
10355   },
10356   /* VEX_W_0FXOP_08_9F_L_0 */
10357   {
10358     { "vpmacsdqh",      { XM, Vex, EXx, XMVexI4 }, 0 },
10359   },
10360   /* VEX_W_0FXOP_08_A6_L_0 */
10361   {
10362     { "vpmadcsswd",     { XM, Vex, EXx, XMVexI4 }, 0 },
10363   },
10364   /* VEX_W_0FXOP_08_B6_L_0 */
10365   {
10366     { "vpmadcswd",      { XM, Vex, EXx, XMVexI4 }, 0 },
10367   },
10368   /* VEX_W_0FXOP_08_C0_L_0 */
10369   {
10370     { "vprotb",         { XM, EXx, Ib }, 0 },
10371   },
10372   /* VEX_W_0FXOP_08_C1_L_0 */
10373   {
10374     { "vprotw",         { XM, EXx, Ib }, 0 },
10375   },
10376   /* VEX_W_0FXOP_08_C2_L_0 */
10377   {
10378     { "vprotd",         { XM, EXx, Ib }, 0 },
10379   },
10380   /* VEX_W_0FXOP_08_C3_L_0 */
10381   {
10382     { "vprotq",         { XM, EXx, Ib }, 0 },
10383   },
10384   /* VEX_W_0FXOP_08_CC_L_0 */
10385   {
10386      { "vpcomb",        { XM, Vex128, EXx, VPCOM }, 0 },
10387   },
10388   /* VEX_W_0FXOP_08_CD_L_0 */
10389   {
10390      { "vpcomw",        { XM, Vex128, EXx, VPCOM }, 0 },
10391   },
10392   /* VEX_W_0FXOP_08_CE_L_0 */
10393   {
10394      { "vpcomd",        { XM, Vex128, EXx, VPCOM }, 0 },
10395   },
10396   /* VEX_W_0FXOP_08_CF_L_0 */
10397   {
10398      { "vpcomq",        { XM, Vex128, EXx, VPCOM }, 0 },
10399   },
10400   /* VEX_W_0FXOP_08_EC_L_0 */
10401   {
10402      { "vpcomub",       { XM, Vex128, EXx, VPCOM }, 0 },
10403   },
10404   /* VEX_W_0FXOP_08_ED_L_0 */
10405   {
10406      { "vpcomuw",       { XM, Vex128, EXx, VPCOM }, 0 },
10407   },
10408   /* VEX_W_0FXOP_08_EE_L_0 */
10409   {
10410      { "vpcomud",       { XM, Vex128, EXx, VPCOM }, 0 },
10411   },
10412   /* VEX_W_0FXOP_08_EF_L_0 */
10413   {
10414      { "vpcomuq",       { XM, Vex128, EXx, VPCOM }, 0 },
10415   },
10416   /* VEX_W_0FXOP_09_80 */
10417   {
10418     { "vfrczps",        { XM, EXx }, 0 },
10419   },
10420   /* VEX_W_0FXOP_09_81 */
10421   {
10422     { "vfrczpd",        { XM, EXx }, 0 },
10423   },
10424   /* VEX_W_0FXOP_09_82 */
10425   {
10426     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_82_W_0) },
10427   },
10428   /* VEX_W_0FXOP_09_83 */
10429   {
10430     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_83_W_0) },
10431   },
10432   /* VEX_W_0FXOP_09_C1_L_0 */
10433   {
10434     { "vphaddbw",       { XM, EXxmm }, 0 },
10435   },
10436   /* VEX_W_0FXOP_09_C2_L_0 */
10437   {
10438     { "vphaddbd",       { XM, EXxmm }, 0 },
10439   },
10440   /* VEX_W_0FXOP_09_C3_L_0 */
10441   {
10442     { "vphaddbq",       { XM, EXxmm }, 0 },
10443   },
10444   /* VEX_W_0FXOP_09_C6_L_0 */
10445   {
10446     { "vphaddwd",       { XM, EXxmm }, 0 },
10447   },
10448   /* VEX_W_0FXOP_09_C7_L_0 */
10449   {
10450     { "vphaddwq",       { XM, EXxmm }, 0 },
10451   },
10452   /* VEX_W_0FXOP_09_CB_L_0 */
10453   {
10454     { "vphadddq",       { XM, EXxmm }, 0 },
10455   },
10456   /* VEX_W_0FXOP_09_D1_L_0 */
10457   {
10458     { "vphaddubw",      { XM, EXxmm }, 0 },
10459   },
10460   /* VEX_W_0FXOP_09_D2_L_0 */
10461   {
10462     { "vphaddubd",      { XM, EXxmm }, 0 },
10463   },
10464   /* VEX_W_0FXOP_09_D3_L_0 */
10465   {
10466     { "vphaddubq",      { XM, EXxmm }, 0 },
10467   },
10468   /* VEX_W_0FXOP_09_D6_L_0 */
10469   {
10470     { "vphadduwd",      { XM, EXxmm }, 0 },
10471   },
10472   /* VEX_W_0FXOP_09_D7_L_0 */
10473   {
10474     { "vphadduwq",      { XM, EXxmm }, 0 },
10475   },
10476   /* VEX_W_0FXOP_09_DB_L_0 */
10477   {
10478     { "vphaddudq",      { XM, EXxmm }, 0 },
10479   },
10480   /* VEX_W_0FXOP_09_E1_L_0 */
10481   {
10482     { "vphsubbw",       { XM, EXxmm }, 0 },
10483   },
10484   /* VEX_W_0FXOP_09_E2_L_0 */
10485   {
10486     { "vphsubwd",       { XM, EXxmm }, 0 },
10487   },
10488   /* VEX_W_0FXOP_09_E3_L_0 */
10489   {
10490     { "vphsubdq",       { XM, EXxmm }, 0 },
10491   },
10492
10493 #include "i386-dis-evex-w.h"
10494 };
10495
10496 static const struct dis386 mod_table[][2] = {
10497   {
10498     /* MOD_8D */
10499     { "leaS",           { Gv, M }, 0 },
10500   },
10501   {
10502     /* MOD_C6_REG_7 */
10503     { Bad_Opcode },
10504     { RM_TABLE (RM_C6_REG_7) },
10505   },
10506   {
10507     /* MOD_C7_REG_7 */
10508     { Bad_Opcode },
10509     { RM_TABLE (RM_C7_REG_7) },
10510   },
10511   {
10512     /* MOD_FF_REG_3 */
10513     { "{l|}call^", { indirEp }, 0 },
10514   },
10515   {
10516     /* MOD_FF_REG_5 */
10517     { "{l|}jmp^", { indirEp }, 0 },
10518   },
10519   {
10520     /* MOD_0F01_REG_0 */
10521     { X86_64_TABLE (X86_64_0F01_REG_0) },
10522     { RM_TABLE (RM_0F01_REG_0) },
10523   },
10524   {
10525     /* MOD_0F01_REG_1 */
10526     { X86_64_TABLE (X86_64_0F01_REG_1) },
10527     { RM_TABLE (RM_0F01_REG_1) },
10528   },
10529   {
10530     /* MOD_0F01_REG_2 */
10531     { X86_64_TABLE (X86_64_0F01_REG_2) },
10532     { RM_TABLE (RM_0F01_REG_2) },
10533   },
10534   {
10535     /* MOD_0F01_REG_3 */
10536     { X86_64_TABLE (X86_64_0F01_REG_3) },
10537     { RM_TABLE (RM_0F01_REG_3) },
10538   },
10539   {
10540     /* MOD_0F01_REG_5 */
10541     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_0) },
10542     { RM_TABLE (RM_0F01_REG_5_MOD_3) },
10543   },
10544   {
10545     /* MOD_0F01_REG_7 */
10546     { "invlpg",         { Mb }, 0 },
10547     { RM_TABLE (RM_0F01_REG_7_MOD_3) },
10548   },
10549   {
10550     /* MOD_0F12_PREFIX_0 */
10551     { "movlpX",         { XM, EXq }, 0 },
10552     { "movhlps",        { XM, EXq }, 0 },
10553   },
10554   {
10555     /* MOD_0F12_PREFIX_2 */
10556     { "movlpX", { XM, EXq }, 0 },
10557   },
10558   {
10559     /* MOD_0F13 */
10560     { "movlpX",         { EXq, XM }, PREFIX_OPCODE },
10561   },
10562   {
10563     /* MOD_0F16_PREFIX_0 */
10564     { "movhpX",         { XM, EXq }, 0 },
10565     { "movlhps",        { XM, EXq }, 0 },
10566   },
10567   {
10568     /* MOD_0F16_PREFIX_2 */
10569     { "movhpX", { XM, EXq }, 0 },
10570   },
10571   {
10572     /* MOD_0F17 */
10573     { "movhpX",         { EXq, XM }, PREFIX_OPCODE },
10574   },
10575   {
10576     /* MOD_0F18_REG_0 */
10577     { "prefetchnta",    { Mb }, 0 },
10578   },
10579   {
10580     /* MOD_0F18_REG_1 */
10581     { "prefetcht0",     { Mb }, 0 },
10582   },
10583   {
10584     /* MOD_0F18_REG_2 */
10585     { "prefetcht1",     { Mb }, 0 },
10586   },
10587   {
10588     /* MOD_0F18_REG_3 */
10589     { "prefetcht2",     { Mb }, 0 },
10590   },
10591   {
10592     /* MOD_0F18_REG_4 */
10593     { "nop/reserved",   { Mb }, 0 },
10594   },
10595   {
10596     /* MOD_0F18_REG_5 */
10597     { "nop/reserved",   { Mb }, 0 },
10598   },
10599   {
10600     /* MOD_0F18_REG_6 */
10601     { "nop/reserved",   { Mb }, 0 },
10602   },
10603   {
10604     /* MOD_0F18_REG_7 */
10605     { "nop/reserved",   { Mb }, 0 },
10606   },
10607   {
10608     /* MOD_0F1A_PREFIX_0 */
10609     { "bndldx",         { Gbnd, Mv_bnd }, 0 },
10610     { "nopQ",           { Ev }, 0 },
10611   },
10612   {
10613     /* MOD_0F1B_PREFIX_0 */
10614     { "bndstx",         { Mv_bnd, Gbnd }, 0 },
10615     { "nopQ",           { Ev }, 0 },
10616   },
10617   {
10618     /* MOD_0F1B_PREFIX_1 */
10619     { "bndmk",          { Gbnd, Mv_bnd }, 0 },
10620     { "nopQ",           { Ev }, 0 },
10621   },
10622   {
10623     /* MOD_0F1C_PREFIX_0 */
10624     { REG_TABLE (REG_0F1C_P_0_MOD_0) },
10625     { "nopQ",           { Ev }, 0 },
10626   },
10627   {
10628     /* MOD_0F1E_PREFIX_1 */
10629     { "nopQ",           { Ev }, 0 },
10630     { REG_TABLE (REG_0F1E_P_1_MOD_3) },
10631   },
10632   {
10633     /* MOD_0F24 */
10634     { Bad_Opcode },
10635     { "movL",           { Rd, Td }, 0 },
10636   },
10637   {
10638     /* MOD_0F26 */
10639     { Bad_Opcode },
10640     { "movL",           { Td, Rd }, 0 },
10641   },
10642   {
10643     /* MOD_0F2B_PREFIX_0 */
10644     {"movntps",         { Mx, XM }, PREFIX_OPCODE },
10645   },
10646   {
10647     /* MOD_0F2B_PREFIX_1 */
10648     {"movntss",         { Md, XM }, PREFIX_OPCODE },
10649   },
10650   {
10651     /* MOD_0F2B_PREFIX_2 */
10652     {"movntpd",         { Mx, XM }, PREFIX_OPCODE },
10653   },
10654   {
10655     /* MOD_0F2B_PREFIX_3 */
10656     {"movntsd",         { Mq, XM }, PREFIX_OPCODE },
10657   },
10658   {
10659     /* MOD_0F50 */
10660     { Bad_Opcode },
10661     { "movmskpX",       { Gdq, XS }, PREFIX_OPCODE },
10662   },
10663   {
10664     /* MOD_0F71_REG_2 */
10665     { Bad_Opcode },
10666     { "psrlw",          { MS, Ib }, 0 },
10667   },
10668   {
10669     /* MOD_0F71_REG_4 */
10670     { Bad_Opcode },
10671     { "psraw",          { MS, Ib }, 0 },
10672   },
10673   {
10674     /* MOD_0F71_REG_6 */
10675     { Bad_Opcode },
10676     { "psllw",          { MS, Ib }, 0 },
10677   },
10678   {
10679     /* MOD_0F72_REG_2 */
10680     { Bad_Opcode },
10681     { "psrld",          { MS, Ib }, 0 },
10682   },
10683   {
10684     /* MOD_0F72_REG_4 */
10685     { Bad_Opcode },
10686     { "psrad",          { MS, Ib }, 0 },
10687   },
10688   {
10689     /* MOD_0F72_REG_6 */
10690     { Bad_Opcode },
10691     { "pslld",          { MS, Ib }, 0 },
10692   },
10693   {
10694     /* MOD_0F73_REG_2 */
10695     { Bad_Opcode },
10696     { "psrlq",          { MS, Ib }, 0 },
10697   },
10698   {
10699     /* MOD_0F73_REG_3 */
10700     { Bad_Opcode },
10701     { PREFIX_TABLE (PREFIX_0F73_REG_3) },
10702   },
10703   {
10704     /* MOD_0F73_REG_6 */
10705     { Bad_Opcode },
10706     { "psllq",          { MS, Ib }, 0 },
10707   },
10708   {
10709     /* MOD_0F73_REG_7 */
10710     { Bad_Opcode },
10711     { PREFIX_TABLE (PREFIX_0F73_REG_7) },
10712   },
10713   {
10714     /* MOD_0FAE_REG_0 */
10715     { "fxsave",         { FXSAVE }, 0 },
10716     { PREFIX_TABLE (PREFIX_0FAE_REG_0_MOD_3) },
10717   },
10718   {
10719     /* MOD_0FAE_REG_1 */
10720     { "fxrstor",        { FXSAVE }, 0 },
10721     { PREFIX_TABLE (PREFIX_0FAE_REG_1_MOD_3) },
10722   },
10723   {
10724     /* MOD_0FAE_REG_2 */
10725     { "ldmxcsr",        { Md }, 0 },
10726     { PREFIX_TABLE (PREFIX_0FAE_REG_2_MOD_3) },
10727   },
10728   {
10729     /* MOD_0FAE_REG_3 */
10730     { "stmxcsr",        { Md }, 0 },
10731     { PREFIX_TABLE (PREFIX_0FAE_REG_3_MOD_3) },
10732   },
10733   {
10734     /* MOD_0FAE_REG_4 */
10735     { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_0) },
10736     { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_3) },
10737   },
10738   {
10739     /* MOD_0FAE_REG_5 */
10740     { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_0) },
10741     { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_3) },
10742   },
10743   {
10744     /* MOD_0FAE_REG_6 */
10745     { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_0) },
10746     { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_3) },
10747   },
10748   {
10749     /* MOD_0FAE_REG_7 */
10750     { PREFIX_TABLE (PREFIX_0FAE_REG_7_MOD_0) },
10751     { RM_TABLE (RM_0FAE_REG_7_MOD_3) },
10752   },
10753   {
10754     /* MOD_0FB2 */
10755     { "lssS",           { Gv, Mp }, 0 },
10756   },
10757   {
10758     /* MOD_0FB4 */
10759     { "lfsS",           { Gv, Mp }, 0 },
10760   },
10761   {
10762     /* MOD_0FB5 */
10763     { "lgsS",           { Gv, Mp }, 0 },
10764   },
10765   {
10766     /* MOD_0FC3 */
10767     { PREFIX_TABLE (PREFIX_0FC3_MOD_0) },
10768   },
10769   {
10770     /* MOD_0FC7_REG_3 */
10771     { "xrstors",        { FXSAVE }, 0 },
10772   },
10773   {
10774     /* MOD_0FC7_REG_4 */
10775     { "xsavec",         { FXSAVE }, 0 },
10776   },
10777   {
10778     /* MOD_0FC7_REG_5 */
10779     { "xsaves",         { FXSAVE }, 0 },
10780   },
10781   {
10782     /* MOD_0FC7_REG_6 */
10783     { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_0) },
10784     { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_3) }
10785   },
10786   {
10787     /* MOD_0FC7_REG_7 */
10788     { "vmptrst",        { Mq }, 0 },
10789     { PREFIX_TABLE (PREFIX_0FC7_REG_7_MOD_3) }
10790   },
10791   {
10792     /* MOD_0FD7 */
10793     { Bad_Opcode },
10794     { "pmovmskb",       { Gdq, MS }, 0 },
10795   },
10796   {
10797     /* MOD_0FE7_PREFIX_2 */
10798     { "movntdq",        { Mx, XM }, 0 },
10799   },
10800   {
10801     /* MOD_0FF0_PREFIX_3 */
10802     { "lddqu",          { XM, M }, 0 },
10803   },
10804   {
10805     /* MOD_0F382A_PREFIX_2 */
10806     { "movntdqa",       { XM, Mx }, 0 },
10807   },
10808   {
10809     /* MOD_0F38F5_PREFIX_2 */
10810     { "wrussK",         { M, Gdq }, PREFIX_OPCODE },
10811   },
10812   {
10813     /* MOD_0F38F6_PREFIX_0 */
10814     { "wrssK",          { M, Gdq }, PREFIX_OPCODE },
10815   },
10816   {
10817     /* MOD_0F38F8_PREFIX_1 */
10818     { "enqcmds",        { Gva, M }, PREFIX_OPCODE },
10819   },
10820   {
10821     /* MOD_0F38F8_PREFIX_2 */
10822     { "movdir64b",      { Gva, M }, PREFIX_OPCODE },
10823   },
10824   {
10825     /* MOD_0F38F8_PREFIX_3 */
10826     { "enqcmd",         { Gva, M }, PREFIX_OPCODE },
10827   },
10828   {
10829     /* MOD_0F38F9_PREFIX_0 */
10830     { "movdiri",        { Ev, Gv }, PREFIX_OPCODE },
10831   },
10832   {
10833     /* MOD_62_32BIT */
10834     { "bound{S|}",      { Gv, Ma }, 0 },
10835     { EVEX_TABLE (EVEX_0F) },
10836   },
10837   {
10838     /* MOD_C4_32BIT */
10839     { "lesS",           { Gv, Mp }, 0 },
10840     { VEX_C4_TABLE (VEX_0F) },
10841   },
10842   {
10843     /* MOD_C5_32BIT */
10844     { "ldsS",           { Gv, Mp }, 0 },
10845     { VEX_C5_TABLE (VEX_0F) },
10846   },
10847   {
10848     /* MOD_VEX_0F12_PREFIX_0 */
10849     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
10850     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
10851   },
10852   {
10853     /* MOD_VEX_0F12_PREFIX_2 */
10854     { VEX_LEN_TABLE (VEX_LEN_0F12_P_2_M_0) },
10855   },
10856   {
10857     /* MOD_VEX_0F13 */
10858     { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
10859   },
10860   {
10861     /* MOD_VEX_0F16_PREFIX_0 */
10862     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
10863     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
10864   },
10865   {
10866     /* MOD_VEX_0F16_PREFIX_2 */
10867     { VEX_LEN_TABLE (VEX_LEN_0F16_P_2_M_0) },
10868   },
10869   {
10870     /* MOD_VEX_0F17 */
10871     { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
10872   },
10873   {
10874     /* MOD_VEX_0F2B */
10875     { "vmovntpX",       { Mx, XM }, PREFIX_OPCODE },
10876   },
10877   {
10878     /* MOD_VEX_W_0_0F41_P_0_LEN_1 */
10879     { Bad_Opcode },
10880     { "kandw",          { MaskG, MaskVex, MaskR }, 0 },
10881   },
10882   {
10883     /* MOD_VEX_W_1_0F41_P_0_LEN_1 */
10884     { Bad_Opcode },
10885     { "kandq",          { MaskG, MaskVex, MaskR }, 0 },
10886   },
10887   {
10888     /* MOD_VEX_W_0_0F41_P_2_LEN_1 */
10889     { Bad_Opcode },
10890     { "kandb",          { MaskG, MaskVex, MaskR }, 0 },
10891   },
10892   {
10893     /* MOD_VEX_W_1_0F41_P_2_LEN_1 */
10894     { Bad_Opcode },
10895     { "kandd",          { MaskG, MaskVex, MaskR }, 0 },
10896   },
10897   {
10898     /* MOD_VEX_W_0_0F42_P_0_LEN_1 */
10899     { Bad_Opcode },
10900     { "kandnw",         { MaskG, MaskVex, MaskR }, 0 },
10901   },
10902   {
10903     /* MOD_VEX_W_1_0F42_P_0_LEN_1 */
10904     { Bad_Opcode },
10905     { "kandnq",         { MaskG, MaskVex, MaskR }, 0 },
10906   },
10907   {
10908     /* MOD_VEX_W_0_0F42_P_2_LEN_1 */
10909     { Bad_Opcode },
10910     { "kandnb",         { MaskG, MaskVex, MaskR }, 0 },
10911   },
10912   {
10913     /* MOD_VEX_W_1_0F42_P_2_LEN_1 */
10914     { Bad_Opcode },
10915     { "kandnd",         { MaskG, MaskVex, MaskR }, 0 },
10916   },
10917   {
10918     /* MOD_VEX_W_0_0F44_P_0_LEN_0 */
10919     { Bad_Opcode },
10920     { "knotw",          { MaskG, MaskR }, 0 },
10921   },
10922   {
10923     /* MOD_VEX_W_1_0F44_P_0_LEN_0 */
10924     { Bad_Opcode },
10925     { "knotq",          { MaskG, MaskR }, 0 },
10926   },
10927   {
10928     /* MOD_VEX_W_0_0F44_P_2_LEN_0 */
10929     { Bad_Opcode },
10930     { "knotb",          { MaskG, MaskR }, 0 },
10931   },
10932   {
10933     /* MOD_VEX_W_1_0F44_P_2_LEN_0 */
10934     { Bad_Opcode },
10935     { "knotd",          { MaskG, MaskR }, 0 },
10936   },
10937   {
10938     /* MOD_VEX_W_0_0F45_P_0_LEN_1 */
10939     { Bad_Opcode },
10940     { "korw",       { MaskG, MaskVex, MaskR }, 0 },
10941   },
10942   {
10943     /* MOD_VEX_W_1_0F45_P_0_LEN_1 */
10944     { Bad_Opcode },
10945     { "korq",       { MaskG, MaskVex, MaskR }, 0 },
10946   },
10947   {
10948     /* MOD_VEX_W_0_0F45_P_2_LEN_1 */
10949     { Bad_Opcode },
10950     { "korb",       { MaskG, MaskVex, MaskR }, 0 },
10951   },
10952   {
10953     /* MOD_VEX_W_1_0F45_P_2_LEN_1 */
10954     { Bad_Opcode },
10955     { "kord",       { MaskG, MaskVex, MaskR }, 0 },
10956   },
10957  {
10958     /* MOD_VEX_W_0_0F46_P_0_LEN_1 */
10959     { Bad_Opcode },
10960     { "kxnorw",     { MaskG, MaskVex, MaskR }, 0 },
10961   },
10962   {
10963     /* MOD_VEX_W_1_0F46_P_0_LEN_1 */
10964     { Bad_Opcode },
10965     { "kxnorq",     { MaskG, MaskVex, MaskR }, 0 },
10966   },
10967   {
10968     /* MOD_VEX_W_0_0F46_P_2_LEN_1 */
10969     { Bad_Opcode },
10970     { "kxnorb",     { MaskG, MaskVex, MaskR }, 0 },
10971   },
10972   {
10973     /* MOD_VEX_W_1_0F46_P_2_LEN_1 */
10974     { Bad_Opcode },
10975     { "kxnord",     { MaskG, MaskVex, MaskR }, 0 },
10976   },
10977   {
10978     /* MOD_VEX_W_0_0F47_P_0_LEN_1 */
10979     { Bad_Opcode },
10980     { "kxorw",      { MaskG, MaskVex, MaskR }, 0 },
10981   },
10982   {
10983     /* MOD_VEX_W_1_0F47_P_0_LEN_1 */
10984     { Bad_Opcode },
10985     { "kxorq",      { MaskG, MaskVex, MaskR }, 0 },
10986   },
10987   {
10988     /* MOD_VEX_W_0_0F47_P_2_LEN_1 */
10989     { Bad_Opcode },
10990     { "kxorb",      { MaskG, MaskVex, MaskR }, 0 },
10991   },
10992   {
10993     /* MOD_VEX_W_1_0F47_P_2_LEN_1 */
10994     { Bad_Opcode },
10995     { "kxord",      { MaskG, MaskVex, MaskR }, 0 },
10996   },
10997   {
10998     /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */
10999     { Bad_Opcode },
11000     { "kaddw",          { MaskG, MaskVex, MaskR }, 0 },
11001   },
11002   {
11003     /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */
11004     { Bad_Opcode },
11005     { "kaddq",          { MaskG, MaskVex, MaskR }, 0 },
11006   },
11007   {
11008     /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */
11009     { Bad_Opcode },
11010     { "kaddb",          { MaskG, MaskVex, MaskR }, 0 },
11011   },
11012   {
11013     /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */
11014     { Bad_Opcode },
11015     { "kaddd",          { MaskG, MaskVex, MaskR }, 0 },
11016   },
11017   {
11018     /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */
11019     { Bad_Opcode },
11020     { "kunpckwd",   { MaskG, MaskVex, MaskR }, 0 },
11021   },
11022   {
11023     /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */
11024     { Bad_Opcode },
11025     { "kunpckdq",   { MaskG, MaskVex, MaskR }, 0 },
11026   },
11027   {
11028     /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */
11029     { Bad_Opcode },
11030     { "kunpckbw",   { MaskG, MaskVex, MaskR }, 0 },
11031   },
11032   {
11033     /* MOD_VEX_0F50 */
11034     { Bad_Opcode },
11035     { "vmovmskpX",      { Gdq, XS }, PREFIX_OPCODE },
11036   },
11037   {
11038     /* MOD_VEX_0F71_REG_2 */
11039     { Bad_Opcode },
11040     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) },
11041   },
11042   {
11043     /* MOD_VEX_0F71_REG_4 */
11044     { Bad_Opcode },
11045     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) },
11046   },
11047   {
11048     /* MOD_VEX_0F71_REG_6 */
11049     { Bad_Opcode },
11050     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) },
11051   },
11052   {
11053     /* MOD_VEX_0F72_REG_2 */
11054     { Bad_Opcode },
11055     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) },
11056   },
11057   {
11058     /* MOD_VEX_0F72_REG_4 */
11059     { Bad_Opcode },
11060     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) },
11061   },
11062   {
11063     /* MOD_VEX_0F72_REG_6 */
11064     { Bad_Opcode },
11065     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) },
11066   },
11067   {
11068     /* MOD_VEX_0F73_REG_2 */
11069     { Bad_Opcode },
11070     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) },
11071   },
11072   {
11073     /* MOD_VEX_0F73_REG_3 */
11074     { Bad_Opcode },
11075     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) },
11076   },
11077   {
11078     /* MOD_VEX_0F73_REG_6 */
11079     { Bad_Opcode },
11080     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) },
11081   },
11082   {
11083     /* MOD_VEX_0F73_REG_7 */
11084     { Bad_Opcode },
11085     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) },
11086   },
11087   {
11088     /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
11089     { "kmovw",          { Ew, MaskG }, 0 },
11090     { Bad_Opcode },
11091   },
11092   {
11093     /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
11094     { "kmovq",          { Eq, MaskG }, 0 },
11095     { Bad_Opcode },
11096   },
11097   {
11098     /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
11099     { "kmovb",          { Eb, MaskG }, 0 },
11100     { Bad_Opcode },
11101   },
11102   {
11103     /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
11104     { "kmovd",          { Ed, MaskG }, 0 },
11105     { Bad_Opcode },
11106   },
11107   {
11108     /* MOD_VEX_W_0_0F92_P_0_LEN_0 */
11109     { Bad_Opcode },
11110     { "kmovw",          { MaskG, Rdq }, 0 },
11111   },
11112   {
11113     /* MOD_VEX_W_0_0F92_P_2_LEN_0 */
11114     { Bad_Opcode },
11115     { "kmovb",          { MaskG, Rdq }, 0 },
11116   },
11117   {
11118     /* MOD_VEX_0F92_P_3_LEN_0 */
11119     { Bad_Opcode },
11120     { "kmovK",          { MaskG, Rdq }, 0 },
11121   },
11122   {
11123     /* MOD_VEX_W_0_0F93_P_0_LEN_0 */
11124     { Bad_Opcode },
11125     { "kmovw",          { Gdq, MaskR }, 0 },
11126   },
11127   {
11128     /* MOD_VEX_W_0_0F93_P_2_LEN_0 */
11129     { Bad_Opcode },
11130     { "kmovb",          { Gdq, MaskR }, 0 },
11131   },
11132   {
11133     /* MOD_VEX_0F93_P_3_LEN_0 */
11134     { Bad_Opcode },
11135     { "kmovK",          { Gdq, MaskR }, 0 },
11136   },
11137   {
11138     /* MOD_VEX_W_0_0F98_P_0_LEN_0 */
11139     { Bad_Opcode },
11140     { "kortestw", { MaskG, MaskR }, 0 },
11141   },
11142   {
11143     /* MOD_VEX_W_1_0F98_P_0_LEN_0 */
11144     { Bad_Opcode },
11145     { "kortestq", { MaskG, MaskR }, 0 },
11146   },
11147   {
11148     /* MOD_VEX_W_0_0F98_P_2_LEN_0 */
11149     { Bad_Opcode },
11150     { "kortestb", { MaskG, MaskR }, 0 },
11151   },
11152   {
11153     /* MOD_VEX_W_1_0F98_P_2_LEN_0 */
11154     { Bad_Opcode },
11155     { "kortestd", { MaskG, MaskR }, 0 },
11156   },
11157   {
11158     /* MOD_VEX_W_0_0F99_P_0_LEN_0 */
11159     { Bad_Opcode },
11160     { "ktestw", { MaskG, MaskR }, 0 },
11161   },
11162   {
11163     /* MOD_VEX_W_1_0F99_P_0_LEN_0 */
11164     { Bad_Opcode },
11165     { "ktestq", { MaskG, MaskR }, 0 },
11166   },
11167   {
11168     /* MOD_VEX_W_0_0F99_P_2_LEN_0 */
11169     { Bad_Opcode },
11170     { "ktestb", { MaskG, MaskR }, 0 },
11171   },
11172   {
11173     /* MOD_VEX_W_1_0F99_P_2_LEN_0 */
11174     { Bad_Opcode },
11175     { "ktestd", { MaskG, MaskR }, 0 },
11176   },
11177   {
11178     /* MOD_VEX_0FAE_REG_2 */
11179     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
11180   },
11181   {
11182     /* MOD_VEX_0FAE_REG_3 */
11183     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
11184   },
11185   {
11186     /* MOD_VEX_0FD7_PREFIX_2 */
11187     { Bad_Opcode },
11188     { "vpmovmskb",      { Gdq, XS }, 0 },
11189   },
11190   {
11191     /* MOD_VEX_0FE7_PREFIX_2 */
11192     { "vmovntdq",       { Mx, XM }, 0 },
11193   },
11194   {
11195     /* MOD_VEX_0FF0_PREFIX_3 */
11196     { "vlddqu",         { XM, M }, 0 },
11197   },
11198   {
11199     /* MOD_VEX_0F381A_PREFIX_2 */
11200     { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) },
11201   },
11202   {
11203     /* MOD_VEX_0F382A_PREFIX_2 */
11204     { "vmovntdqa",      { XM, Mx }, 0 },
11205   },
11206   {
11207     /* MOD_VEX_0F382C_PREFIX_2 */
11208     { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) },
11209   },
11210   {
11211     /* MOD_VEX_0F382D_PREFIX_2 */
11212     { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) },
11213   },
11214   {
11215     /* MOD_VEX_0F382E_PREFIX_2 */
11216     { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) },
11217   },
11218   {
11219     /* MOD_VEX_0F382F_PREFIX_2 */
11220     { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) },
11221   },
11222   {
11223     /* MOD_VEX_0F385A_PREFIX_2 */
11224     { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) },
11225   },
11226   {
11227     /* MOD_VEX_0F388C_PREFIX_2 */
11228     { "vpmaskmov%LW",   { XM, Vex, Mx }, 0 },
11229   },
11230   {
11231     /* MOD_VEX_0F388E_PREFIX_2 */
11232     { "vpmaskmov%LW",   { Mx, Vex, XM }, 0 },
11233   },
11234   {
11235     /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */
11236     { Bad_Opcode },
11237     { "kshiftrb",       { MaskG, MaskR, Ib }, 0 },
11238   },
11239   {
11240     /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */
11241     { Bad_Opcode },
11242     { "kshiftrw",       { MaskG, MaskR, Ib }, 0 },
11243   },
11244   {
11245     /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */
11246     { Bad_Opcode },
11247     { "kshiftrd",       { MaskG, MaskR, Ib }, 0 },
11248   },
11249   {
11250     /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */
11251     { Bad_Opcode },
11252     { "kshiftrq",       { MaskG, MaskR, Ib }, 0 },
11253   },
11254   {
11255     /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */
11256     { Bad_Opcode },
11257     { "kshiftlb",       { MaskG, MaskR, Ib }, 0 },
11258   },
11259   {
11260     /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */
11261     { Bad_Opcode },
11262     { "kshiftlw",       { MaskG, MaskR, Ib }, 0 },
11263   },
11264   {
11265     /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */
11266     { Bad_Opcode },
11267     { "kshiftld",       { MaskG, MaskR, Ib }, 0 },
11268   },
11269   {
11270     /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */
11271     { Bad_Opcode },
11272     { "kshiftlq",       { MaskG, MaskR, Ib }, 0 },
11273   },
11274   {
11275     /* MOD_VEX_0FXOP_09_12 */
11276     { Bad_Opcode },
11277     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_12_M_1) },
11278   },
11279
11280 #include "i386-dis-evex-mod.h"
11281 };
11282
11283 static const struct dis386 rm_table[][8] = {
11284   {
11285     /* RM_C6_REG_7 */
11286     { "xabort",         { Skip_MODRM, Ib }, 0 },
11287   },
11288   {
11289     /* RM_C7_REG_7 */
11290     { "xbeginT",        { Skip_MODRM, Jdqw }, 0 },
11291   },
11292   {
11293     /* RM_0F01_REG_0 */
11294     { "enclv",          { Skip_MODRM }, 0 },
11295     { "vmcall",         { Skip_MODRM }, 0 },
11296     { "vmlaunch",       { Skip_MODRM }, 0 },
11297     { "vmresume",       { Skip_MODRM }, 0 },
11298     { "vmxoff",         { Skip_MODRM }, 0 },
11299     { "pconfig",        { Skip_MODRM }, 0 },
11300   },
11301   {
11302     /* RM_0F01_REG_1 */
11303     { "monitor",        { { OP_Monitor, 0 } }, 0 },
11304     { "mwait",          { { OP_Mwait, 0 } }, 0 },
11305     { "clac",           { Skip_MODRM }, 0 },
11306     { "stac",           { Skip_MODRM }, 0 },
11307     { Bad_Opcode },
11308     { Bad_Opcode },
11309     { Bad_Opcode },
11310     { "encls",          { Skip_MODRM }, 0 },
11311   },
11312   {
11313     /* RM_0F01_REG_2 */
11314     { "xgetbv",         { Skip_MODRM }, 0 },
11315     { "xsetbv",         { Skip_MODRM }, 0 },
11316     { Bad_Opcode },
11317     { Bad_Opcode },
11318     { "vmfunc",         { Skip_MODRM }, 0 },
11319     { "xend",           { Skip_MODRM }, 0 },
11320     { "xtest",          { Skip_MODRM }, 0 },
11321     { "enclu",          { Skip_MODRM }, 0 },
11322   },
11323   {
11324     /* RM_0F01_REG_3 */
11325     { "vmrun",          { Skip_MODRM }, 0 },
11326     { PREFIX_TABLE (PREFIX_0F01_REG_3_RM_1) },
11327     { "vmload",         { Skip_MODRM }, 0 },
11328     { "vmsave",         { Skip_MODRM }, 0 },
11329     { "stgi",           { Skip_MODRM }, 0 },
11330     { "clgi",           { Skip_MODRM }, 0 },
11331     { "skinit",         { Skip_MODRM }, 0 },
11332     { "invlpga",        { Skip_MODRM }, 0 },
11333   },
11334   {
11335     /* RM_0F01_REG_5_MOD_3 */
11336     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_0) },
11337     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_1) },
11338     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_2) },
11339     { Bad_Opcode },
11340     { Bad_Opcode },
11341     { Bad_Opcode },
11342     { "rdpkru",         { Skip_MODRM }, 0 },
11343     { "wrpkru",         { Skip_MODRM }, 0 },
11344   },
11345   {
11346     /* RM_0F01_REG_7_MOD_3 */
11347     { "swapgs",         { Skip_MODRM }, 0  },
11348     { "rdtscp",         { Skip_MODRM }, 0  },
11349     { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_2) },
11350     { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_3) },
11351     { "clzero",         { Skip_MODRM }, 0  },
11352     { "rdpru",          { Skip_MODRM }, 0  },
11353   },
11354   {
11355     /* RM_0F1E_P_1_MOD_3_REG_7 */
11356     { "nopQ",           { Ev }, 0 },
11357     { "nopQ",           { Ev }, 0 },
11358     { "endbr64",        { Skip_MODRM },  PREFIX_OPCODE },
11359     { "endbr32",        { Skip_MODRM },  PREFIX_OPCODE },
11360     { "nopQ",           { Ev }, 0 },
11361     { "nopQ",           { Ev }, 0 },
11362     { "nopQ",           { Ev }, 0 },
11363     { "nopQ",           { Ev }, 0 },
11364   },
11365   {
11366     /* RM_0FAE_REG_6_MOD_3 */
11367     { "mfence",         { Skip_MODRM }, 0 },
11368   },
11369   {
11370     /* RM_0FAE_REG_7_MOD_3 */
11371     { "sfence",         { Skip_MODRM }, 0 },
11372
11373   },
11374 };
11375
11376 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
11377
11378 /* We use the high bit to indicate different name for the same
11379    prefix.  */
11380 #define REP_PREFIX      (0xf3 | 0x100)
11381 #define XACQUIRE_PREFIX (0xf2 | 0x200)
11382 #define XRELEASE_PREFIX (0xf3 | 0x400)
11383 #define BND_PREFIX      (0xf2 | 0x400)
11384 #define NOTRACK_PREFIX  (0x3e | 0x100)
11385
11386 /* Remember if the current op is a jump instruction.  */
11387 static bfd_boolean op_is_jump = FALSE;
11388
11389 static int
11390 ckprefix (void)
11391 {
11392   int newrex, i, length;
11393   rex = 0;
11394   prefixes = 0;
11395   used_prefixes = 0;
11396   rex_used = 0;
11397   last_lock_prefix = -1;
11398   last_repz_prefix = -1;
11399   last_repnz_prefix = -1;
11400   last_data_prefix = -1;
11401   last_addr_prefix = -1;
11402   last_rex_prefix = -1;
11403   last_seg_prefix = -1;
11404   fwait_prefix = -1;
11405   active_seg_prefix = 0;
11406   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
11407     all_prefixes[i] = 0;
11408   i = 0;
11409   length = 0;
11410   /* The maximum instruction length is 15bytes.  */
11411   while (length < MAX_CODE_LENGTH - 1)
11412     {
11413       FETCH_DATA (the_info, codep + 1);
11414       newrex = 0;
11415       switch (*codep)
11416         {
11417         /* REX prefixes family.  */
11418         case 0x40:
11419         case 0x41:
11420         case 0x42:
11421         case 0x43:
11422         case 0x44:
11423         case 0x45:
11424         case 0x46:
11425         case 0x47:
11426         case 0x48:
11427         case 0x49:
11428         case 0x4a:
11429         case 0x4b:
11430         case 0x4c:
11431         case 0x4d:
11432         case 0x4e:
11433         case 0x4f:
11434           if (address_mode == mode_64bit)
11435             newrex = *codep;
11436           else
11437             return 1;
11438           last_rex_prefix = i;
11439           break;
11440         case 0xf3:
11441           prefixes |= PREFIX_REPZ;
11442           last_repz_prefix = i;
11443           break;
11444         case 0xf2:
11445           prefixes |= PREFIX_REPNZ;
11446           last_repnz_prefix = i;
11447           break;
11448         case 0xf0:
11449           prefixes |= PREFIX_LOCK;
11450           last_lock_prefix = i;
11451           break;
11452         case 0x2e:
11453           prefixes |= PREFIX_CS;
11454           last_seg_prefix = i;
11455           active_seg_prefix = PREFIX_CS;
11456           break;
11457         case 0x36:
11458           prefixes |= PREFIX_SS;
11459           last_seg_prefix = i;
11460           active_seg_prefix = PREFIX_SS;
11461           break;
11462         case 0x3e:
11463           prefixes |= PREFIX_DS;
11464           last_seg_prefix = i;
11465           active_seg_prefix = PREFIX_DS;
11466           break;
11467         case 0x26:
11468           prefixes |= PREFIX_ES;
11469           last_seg_prefix = i;
11470           active_seg_prefix = PREFIX_ES;
11471           break;
11472         case 0x64:
11473           prefixes |= PREFIX_FS;
11474           last_seg_prefix = i;
11475           active_seg_prefix = PREFIX_FS;
11476           break;
11477         case 0x65:
11478           prefixes |= PREFIX_GS;
11479           last_seg_prefix = i;
11480           active_seg_prefix = PREFIX_GS;
11481           break;
11482         case 0x66:
11483           prefixes |= PREFIX_DATA;
11484           last_data_prefix = i;
11485           break;
11486         case 0x67:
11487           prefixes |= PREFIX_ADDR;
11488           last_addr_prefix = i;
11489           break;
11490         case FWAIT_OPCODE:
11491           /* fwait is really an instruction.  If there are prefixes
11492              before the fwait, they belong to the fwait, *not* to the
11493              following instruction.  */
11494           fwait_prefix = i;
11495           if (prefixes || rex)
11496             {
11497               prefixes |= PREFIX_FWAIT;
11498               codep++;
11499               /* This ensures that the previous REX prefixes are noticed
11500                  as unused prefixes, as in the return case below.  */
11501               rex_used = rex;
11502               return 1;
11503             }
11504           prefixes = PREFIX_FWAIT;
11505           break;
11506         default:
11507           return 1;
11508         }
11509       /* Rex is ignored when followed by another prefix.  */
11510       if (rex)
11511         {
11512           rex_used = rex;
11513           return 1;
11514         }
11515       if (*codep != FWAIT_OPCODE)
11516         all_prefixes[i++] = *codep;
11517       rex = newrex;
11518       codep++;
11519       length++;
11520     }
11521   return 0;
11522 }
11523
11524 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
11525    prefix byte.  */
11526
11527 static const char *
11528 prefix_name (int pref, int sizeflag)
11529 {
11530   static const char *rexes [16] =
11531     {
11532       "rex",            /* 0x40 */
11533       "rex.B",          /* 0x41 */
11534       "rex.X",          /* 0x42 */
11535       "rex.XB",         /* 0x43 */
11536       "rex.R",          /* 0x44 */
11537       "rex.RB",         /* 0x45 */
11538       "rex.RX",         /* 0x46 */
11539       "rex.RXB",        /* 0x47 */
11540       "rex.W",          /* 0x48 */
11541       "rex.WB",         /* 0x49 */
11542       "rex.WX",         /* 0x4a */
11543       "rex.WXB",        /* 0x4b */
11544       "rex.WR",         /* 0x4c */
11545       "rex.WRB",        /* 0x4d */
11546       "rex.WRX",        /* 0x4e */
11547       "rex.WRXB",       /* 0x4f */
11548     };
11549
11550   switch (pref)
11551     {
11552     /* REX prefixes family.  */
11553     case 0x40:
11554     case 0x41:
11555     case 0x42:
11556     case 0x43:
11557     case 0x44:
11558     case 0x45:
11559     case 0x46:
11560     case 0x47:
11561     case 0x48:
11562     case 0x49:
11563     case 0x4a:
11564     case 0x4b:
11565     case 0x4c:
11566     case 0x4d:
11567     case 0x4e:
11568     case 0x4f:
11569       return rexes [pref - 0x40];
11570     case 0xf3:
11571       return "repz";
11572     case 0xf2:
11573       return "repnz";
11574     case 0xf0:
11575       return "lock";
11576     case 0x2e:
11577       return "cs";
11578     case 0x36:
11579       return "ss";
11580     case 0x3e:
11581       return "ds";
11582     case 0x26:
11583       return "es";
11584     case 0x64:
11585       return "fs";
11586     case 0x65:
11587       return "gs";
11588     case 0x66:
11589       return (sizeflag & DFLAG) ? "data16" : "data32";
11590     case 0x67:
11591       if (address_mode == mode_64bit)
11592         return (sizeflag & AFLAG) ? "addr32" : "addr64";
11593       else
11594         return (sizeflag & AFLAG) ? "addr16" : "addr32";
11595     case FWAIT_OPCODE:
11596       return "fwait";
11597     case REP_PREFIX:
11598       return "rep";
11599     case XACQUIRE_PREFIX:
11600       return "xacquire";
11601     case XRELEASE_PREFIX:
11602       return "xrelease";
11603     case BND_PREFIX:
11604       return "bnd";
11605     case NOTRACK_PREFIX:
11606       return "notrack";
11607     default:
11608       return NULL;
11609     }
11610 }
11611
11612 static char op_out[MAX_OPERANDS][100];
11613 static int op_ad, op_index[MAX_OPERANDS];
11614 static int two_source_ops;
11615 static bfd_vma op_address[MAX_OPERANDS];
11616 static bfd_vma op_riprel[MAX_OPERANDS];
11617 static bfd_vma start_pc;
11618
11619 /*
11620  *   On the 386's of 1988, the maximum length of an instruction is 15 bytes.
11621  *   (see topic "Redundant prefixes" in the "Differences from 8086"
11622  *   section of the "Virtual 8086 Mode" chapter.)
11623  * 'pc' should be the address of this instruction, it will
11624  *   be used to print the target address if this is a relative jump or call
11625  * The function returns the length of this instruction in bytes.
11626  */
11627
11628 static char intel_syntax;
11629 static char intel_mnemonic = !SYSV386_COMPAT;
11630 static char open_char;
11631 static char close_char;
11632 static char separator_char;
11633 static char scale_char;
11634
11635 enum x86_64_isa
11636 {
11637   amd64 = 1,
11638   intel64
11639 };
11640
11641 static enum x86_64_isa isa64;
11642
11643 /* Here for backwards compatibility.  When gdb stops using
11644    print_insn_i386_att and print_insn_i386_intel these functions can
11645    disappear, and print_insn_i386 be merged into print_insn.  */
11646 int
11647 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
11648 {
11649   intel_syntax = 0;
11650
11651   return print_insn (pc, info);
11652 }
11653
11654 int
11655 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
11656 {
11657   intel_syntax = 1;
11658
11659   return print_insn (pc, info);
11660 }
11661
11662 int
11663 print_insn_i386 (bfd_vma pc, disassemble_info *info)
11664 {
11665   intel_syntax = -1;
11666
11667   return print_insn (pc, info);
11668 }
11669
11670 void
11671 print_i386_disassembler_options (FILE *stream)
11672 {
11673   fprintf (stream, _("\n\
11674 The following i386/x86-64 specific disassembler options are supported for use\n\
11675 with the -M switch (multiple options should be separated by commas):\n"));
11676
11677   fprintf (stream, _("  x86-64      Disassemble in 64bit mode\n"));
11678   fprintf (stream, _("  i386        Disassemble in 32bit mode\n"));
11679   fprintf (stream, _("  i8086       Disassemble in 16bit mode\n"));
11680   fprintf (stream, _("  att         Display instruction in AT&T syntax\n"));
11681   fprintf (stream, _("  intel       Display instruction in Intel syntax\n"));
11682   fprintf (stream, _("  att-mnemonic\n"
11683                      "              Display instruction in AT&T mnemonic\n"));
11684   fprintf (stream, _("  intel-mnemonic\n"
11685                      "              Display instruction in Intel mnemonic\n"));
11686   fprintf (stream, _("  addr64      Assume 64bit address size\n"));
11687   fprintf (stream, _("  addr32      Assume 32bit address size\n"));
11688   fprintf (stream, _("  addr16      Assume 16bit address size\n"));
11689   fprintf (stream, _("  data32      Assume 32bit data size\n"));
11690   fprintf (stream, _("  data16      Assume 16bit data size\n"));
11691   fprintf (stream, _("  suffix      Always display instruction suffix in AT&T syntax\n"));
11692   fprintf (stream, _("  amd64       Display instruction in AMD64 ISA\n"));
11693   fprintf (stream, _("  intel64     Display instruction in Intel64 ISA\n"));
11694 }
11695
11696 /* Bad opcode.  */
11697 static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 };
11698
11699 /* Get a pointer to struct dis386 with a valid name.  */
11700
11701 static const struct dis386 *
11702 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
11703 {
11704   int vindex, vex_table_index;
11705
11706   if (dp->name != NULL)
11707     return dp;
11708
11709   switch (dp->op[0].bytemode)
11710     {
11711     case USE_REG_TABLE:
11712       dp = &reg_table[dp->op[1].bytemode][modrm.reg];
11713       break;
11714
11715     case USE_MOD_TABLE:
11716       vindex = modrm.mod == 0x3 ? 1 : 0;
11717       dp = &mod_table[dp->op[1].bytemode][vindex];
11718       break;
11719
11720     case USE_RM_TABLE:
11721       dp = &rm_table[dp->op[1].bytemode][modrm.rm];
11722       break;
11723
11724     case USE_PREFIX_TABLE:
11725       if (need_vex)
11726         {
11727           /* The prefix in VEX is implicit.  */
11728           switch (vex.prefix)
11729             {
11730             case 0:
11731               vindex = 0;
11732               break;
11733             case REPE_PREFIX_OPCODE:
11734               vindex = 1;
11735               break;
11736             case DATA_PREFIX_OPCODE:
11737               vindex = 2;
11738               break;
11739             case REPNE_PREFIX_OPCODE:
11740               vindex = 3;
11741               break;
11742             default:
11743               abort ();
11744               break;
11745             }
11746         }
11747       else
11748         {
11749           int last_prefix = -1;
11750           int prefix = 0;
11751           vindex = 0;
11752           /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
11753              When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
11754              last one wins.  */
11755           if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
11756             {
11757               if (last_repz_prefix > last_repnz_prefix)
11758                 {
11759                   vindex = 1;
11760                   prefix = PREFIX_REPZ;
11761                   last_prefix = last_repz_prefix;
11762                 }
11763               else
11764                 {
11765                   vindex = 3;
11766                   prefix = PREFIX_REPNZ;
11767                   last_prefix = last_repnz_prefix;
11768                 }
11769
11770               /* Check if prefix should be ignored.  */
11771               if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement
11772                      & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT)
11773                    & prefix) != 0)
11774                 vindex = 0;
11775             }
11776
11777           if (vindex == 0 && (prefixes & PREFIX_DATA) != 0)
11778             {
11779               vindex = 2;
11780               prefix = PREFIX_DATA;
11781               last_prefix = last_data_prefix;
11782             }
11783
11784           if (vindex != 0)
11785             {
11786               used_prefixes |= prefix;
11787               all_prefixes[last_prefix] = 0;
11788             }
11789         }
11790       dp = &prefix_table[dp->op[1].bytemode][vindex];
11791       break;
11792
11793     case USE_X86_64_TABLE:
11794       vindex = address_mode == mode_64bit ? 1 : 0;
11795       dp = &x86_64_table[dp->op[1].bytemode][vindex];
11796       break;
11797
11798     case USE_3BYTE_TABLE:
11799       FETCH_DATA (info, codep + 2);
11800       vindex = *codep++;
11801       dp = &three_byte_table[dp->op[1].bytemode][vindex];
11802       end_codep = codep;
11803       modrm.mod = (*codep >> 6) & 3;
11804       modrm.reg = (*codep >> 3) & 7;
11805       modrm.rm = *codep & 7;
11806       break;
11807
11808     case USE_VEX_LEN_TABLE:
11809       if (!need_vex)
11810         abort ();
11811
11812       switch (vex.length)
11813         {
11814         case 128:
11815           vindex = 0;
11816           break;
11817         case 256:
11818           vindex = 1;
11819           break;
11820         default:
11821           abort ();
11822           break;
11823         }
11824
11825       dp = &vex_len_table[dp->op[1].bytemode][vindex];
11826       break;
11827
11828     case USE_EVEX_LEN_TABLE:
11829       if (!vex.evex)
11830         abort ();
11831
11832       switch (vex.length)
11833         {
11834         case 128:
11835           vindex = 0;
11836           break;
11837         case 256:
11838           vindex = 1;
11839           break;
11840         case 512:
11841           vindex = 2;
11842           break;
11843         default:
11844           abort ();
11845           break;
11846         }
11847
11848       dp = &evex_len_table[dp->op[1].bytemode][vindex];
11849       break;
11850
11851     case USE_XOP_8F_TABLE:
11852       FETCH_DATA (info, codep + 3);
11853       rex = ~(*codep >> 5) & 0x7;
11854
11855       /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm".  */
11856       switch ((*codep & 0x1f))
11857         {
11858         default:
11859           dp = &bad_opcode;
11860           return dp;
11861         case 0x8:
11862           vex_table_index = XOP_08;
11863           break;
11864         case 0x9:
11865           vex_table_index = XOP_09;
11866           break;
11867         case 0xa:
11868           vex_table_index = XOP_0A;
11869           break;
11870         }
11871       codep++;
11872       vex.w = *codep & 0x80;
11873       if (vex.w && address_mode == mode_64bit)
11874         rex |= REX_W;
11875
11876       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11877       if (address_mode != mode_64bit)
11878         {
11879           /* In 16/32-bit mode REX_B is silently ignored.  */
11880           rex &= ~REX_B;
11881         }
11882
11883       vex.length = (*codep & 0x4) ? 256 : 128;
11884       switch ((*codep & 0x3))
11885         {
11886         case 0:
11887           break;
11888         case 1:
11889           vex.prefix = DATA_PREFIX_OPCODE;
11890           break;
11891         case 2:
11892           vex.prefix = REPE_PREFIX_OPCODE;
11893           break;
11894         case 3:
11895           vex.prefix = REPNE_PREFIX_OPCODE;
11896           break;
11897         }
11898       need_vex = 1;
11899       need_vex_reg = 1;
11900       codep++;
11901       vindex = *codep++;
11902       dp = &xop_table[vex_table_index][vindex];
11903
11904       end_codep = codep;
11905       FETCH_DATA (info, codep + 1);
11906       modrm.mod = (*codep >> 6) & 3;
11907       modrm.reg = (*codep >> 3) & 7;
11908       modrm.rm = *codep & 7;
11909
11910       /* No XOP encoding so far allows for a non-zero embedded prefix. Avoid
11911          having to decode the bits for every otherwise valid encoding.  */
11912       if (vex.prefix)
11913         return &bad_opcode;
11914       break;
11915
11916     case USE_VEX_C4_TABLE:
11917       /* VEX prefix.  */
11918       FETCH_DATA (info, codep + 3);
11919       rex = ~(*codep >> 5) & 0x7;
11920       switch ((*codep & 0x1f))
11921         {
11922         default:
11923           dp = &bad_opcode;
11924           return dp;
11925         case 0x1:
11926           vex_table_index = VEX_0F;
11927           break;
11928         case 0x2:
11929           vex_table_index = VEX_0F38;
11930           break;
11931         case 0x3:
11932           vex_table_index = VEX_0F3A;
11933           break;
11934         }
11935       codep++;
11936       vex.w = *codep & 0x80;
11937       if (address_mode == mode_64bit)
11938         {
11939           if (vex.w)
11940             rex |= REX_W;
11941         }
11942       else
11943         {
11944           /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
11945              is ignored, other REX bits are 0 and the highest bit in
11946              VEX.vvvv is also ignored (but we mustn't clear it here).  */
11947           rex = 0;
11948         }
11949       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11950       vex.length = (*codep & 0x4) ? 256 : 128;
11951       switch ((*codep & 0x3))
11952         {
11953         case 0:
11954           break;
11955         case 1:
11956           vex.prefix = DATA_PREFIX_OPCODE;
11957           break;
11958         case 2:
11959           vex.prefix = REPE_PREFIX_OPCODE;
11960           break;
11961         case 3:
11962           vex.prefix = REPNE_PREFIX_OPCODE;
11963           break;
11964         }
11965       need_vex = 1;
11966       need_vex_reg = 1;
11967       codep++;
11968       vindex = *codep++;
11969       dp = &vex_table[vex_table_index][vindex];
11970       end_codep = codep;
11971       /* There is no MODRM byte for VEX0F 77.  */
11972       if (vex_table_index != VEX_0F || vindex != 0x77)
11973         {
11974           FETCH_DATA (info, codep + 1);
11975           modrm.mod = (*codep >> 6) & 3;
11976           modrm.reg = (*codep >> 3) & 7;
11977           modrm.rm = *codep & 7;
11978         }
11979       break;
11980
11981     case USE_VEX_C5_TABLE:
11982       /* VEX prefix.  */
11983       FETCH_DATA (info, codep + 2);
11984       rex = (*codep & 0x80) ? 0 : REX_R;
11985
11986       /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
11987          VEX.vvvv is 1.  */
11988       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11989       vex.length = (*codep & 0x4) ? 256 : 128;
11990       switch ((*codep & 0x3))
11991         {
11992         case 0:
11993           break;
11994         case 1:
11995           vex.prefix = DATA_PREFIX_OPCODE;
11996           break;
11997         case 2:
11998           vex.prefix = REPE_PREFIX_OPCODE;
11999           break;
12000         case 3:
12001           vex.prefix = REPNE_PREFIX_OPCODE;
12002           break;
12003         }
12004       need_vex = 1;
12005       need_vex_reg = 1;
12006       codep++;
12007       vindex = *codep++;
12008       dp = &vex_table[dp->op[1].bytemode][vindex];
12009       end_codep = codep;
12010       /* There is no MODRM byte for VEX 77.  */
12011       if (vindex != 0x77)
12012         {
12013           FETCH_DATA (info, codep + 1);
12014           modrm.mod = (*codep >> 6) & 3;
12015           modrm.reg = (*codep >> 3) & 7;
12016           modrm.rm = *codep & 7;
12017         }
12018       break;
12019
12020     case USE_VEX_W_TABLE:
12021       if (!need_vex)
12022         abort ();
12023
12024       dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
12025       break;
12026
12027     case USE_EVEX_TABLE:
12028       two_source_ops = 0;
12029       /* EVEX prefix.  */
12030       vex.evex = 1;
12031       FETCH_DATA (info, codep + 4);
12032       /* The first byte after 0x62.  */
12033       rex = ~(*codep >> 5) & 0x7;
12034       vex.r = *codep & 0x10;
12035       switch ((*codep & 0xf))
12036         {
12037         default:
12038           return &bad_opcode;
12039         case 0x1:
12040           vex_table_index = EVEX_0F;
12041           break;
12042         case 0x2:
12043           vex_table_index = EVEX_0F38;
12044           break;
12045         case 0x3:
12046           vex_table_index = EVEX_0F3A;
12047           break;
12048         }
12049
12050       /* The second byte after 0x62.  */
12051       codep++;
12052       vex.w = *codep & 0x80;
12053       if (vex.w && address_mode == mode_64bit)
12054         rex |= REX_W;
12055
12056       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12057
12058       /* The U bit.  */
12059       if (!(*codep & 0x4))
12060         return &bad_opcode;
12061
12062       switch ((*codep & 0x3))
12063         {
12064         case 0:
12065           break;
12066         case 1:
12067           vex.prefix = DATA_PREFIX_OPCODE;
12068           break;
12069         case 2:
12070           vex.prefix = REPE_PREFIX_OPCODE;
12071           break;
12072         case 3:
12073           vex.prefix = REPNE_PREFIX_OPCODE;
12074           break;
12075         }
12076
12077       /* The third byte after 0x62.  */
12078       codep++;
12079
12080       /* Remember the static rounding bits.  */
12081       vex.ll = (*codep >> 5) & 3;
12082       vex.b = (*codep & 0x10) != 0;
12083
12084       vex.v = *codep & 0x8;
12085       vex.mask_register_specifier = *codep & 0x7;
12086       vex.zeroing = *codep & 0x80;
12087
12088       if (address_mode != mode_64bit)
12089         {
12090           /* In 16/32-bit mode silently ignore following bits.  */
12091           rex &= ~REX_B;
12092           vex.r = 1;
12093           vex.v = 1;
12094         }
12095
12096       need_vex = 1;
12097       need_vex_reg = 1;
12098       codep++;
12099       vindex = *codep++;
12100       dp = &evex_table[vex_table_index][vindex];
12101       end_codep = codep;
12102       FETCH_DATA (info, codep + 1);
12103       modrm.mod = (*codep >> 6) & 3;
12104       modrm.reg = (*codep >> 3) & 7;
12105       modrm.rm = *codep & 7;
12106
12107       /* Set vector length.  */
12108       if (modrm.mod == 3 && vex.b)
12109         vex.length = 512;
12110       else
12111         {
12112           switch (vex.ll)
12113             {
12114             case 0x0:
12115               vex.length = 128;
12116               break;
12117             case 0x1:
12118               vex.length = 256;
12119               break;
12120             case 0x2:
12121               vex.length = 512;
12122               break;
12123             default:
12124               return &bad_opcode;
12125             }
12126         }
12127       break;
12128
12129     case 0:
12130       dp = &bad_opcode;
12131       break;
12132
12133     default:
12134       abort ();
12135     }
12136
12137   if (dp->name != NULL)
12138     return dp;
12139   else
12140     return get_valid_dis386 (dp, info);
12141 }
12142
12143 static void
12144 get_sib (disassemble_info *info, int sizeflag)
12145 {
12146   /* If modrm.mod == 3, operand must be register.  */
12147   if (need_modrm
12148       && ((sizeflag & AFLAG) || address_mode == mode_64bit)
12149       && modrm.mod != 3
12150       && modrm.rm == 4)
12151     {
12152       FETCH_DATA (info, codep + 2);
12153       sib.index = (codep [1] >> 3) & 7;
12154       sib.scale = (codep [1] >> 6) & 3;
12155       sib.base = codep [1] & 7;
12156     }
12157 }
12158
12159 static int
12160 print_insn (bfd_vma pc, disassemble_info *info)
12161 {
12162   const struct dis386 *dp;
12163   int i;
12164   char *op_txt[MAX_OPERANDS];
12165   int needcomma;
12166   int sizeflag, orig_sizeflag;
12167   const char *p;
12168   struct dis_private priv;
12169   int prefix_length;
12170
12171   priv.orig_sizeflag = AFLAG | DFLAG;
12172   if ((info->mach & bfd_mach_i386_i386) != 0)
12173     address_mode = mode_32bit;
12174   else if (info->mach == bfd_mach_i386_i8086)
12175     {
12176       address_mode = mode_16bit;
12177       priv.orig_sizeflag = 0;
12178     }
12179   else
12180     address_mode = mode_64bit;
12181
12182   if (intel_syntax == (char) -1)
12183     intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0;
12184
12185   for (p = info->disassembler_options; p != NULL; )
12186     {
12187       if (CONST_STRNEQ (p, "amd64"))
12188         isa64 = amd64;
12189       else if (CONST_STRNEQ (p, "intel64"))
12190         isa64 = intel64;
12191       else if (CONST_STRNEQ (p, "x86-64"))
12192         {
12193           address_mode = mode_64bit;
12194           priv.orig_sizeflag |= AFLAG | DFLAG;
12195         }
12196       else if (CONST_STRNEQ (p, "i386"))
12197         {
12198           address_mode = mode_32bit;
12199           priv.orig_sizeflag |= AFLAG | DFLAG;
12200         }
12201       else if (CONST_STRNEQ (p, "i8086"))
12202         {
12203           address_mode = mode_16bit;
12204           priv.orig_sizeflag &= ~(AFLAG | DFLAG);
12205         }
12206       else if (CONST_STRNEQ (p, "intel"))
12207         {
12208           intel_syntax = 1;
12209           if (CONST_STRNEQ (p + 5, "-mnemonic"))
12210             intel_mnemonic = 1;
12211         }
12212       else if (CONST_STRNEQ (p, "att"))
12213         {
12214           intel_syntax = 0;
12215           if (CONST_STRNEQ (p + 3, "-mnemonic"))
12216             intel_mnemonic = 0;
12217         }
12218       else if (CONST_STRNEQ (p, "addr"))
12219         {
12220           if (address_mode == mode_64bit)
12221             {
12222               if (p[4] == '3' && p[5] == '2')
12223                 priv.orig_sizeflag &= ~AFLAG;
12224               else if (p[4] == '6' && p[5] == '4')
12225                 priv.orig_sizeflag |= AFLAG;
12226             }
12227           else
12228             {
12229               if (p[4] == '1' && p[5] == '6')
12230                 priv.orig_sizeflag &= ~AFLAG;
12231               else if (p[4] == '3' && p[5] == '2')
12232                 priv.orig_sizeflag |= AFLAG;
12233             }
12234         }
12235       else if (CONST_STRNEQ (p, "data"))
12236         {
12237           if (p[4] == '1' && p[5] == '6')
12238             priv.orig_sizeflag &= ~DFLAG;
12239           else if (p[4] == '3' && p[5] == '2')
12240             priv.orig_sizeflag |= DFLAG;
12241         }
12242       else if (CONST_STRNEQ (p, "suffix"))
12243         priv.orig_sizeflag |= SUFFIX_ALWAYS;
12244
12245       p = strchr (p, ',');
12246       if (p != NULL)
12247         p++;
12248     }
12249
12250   if (address_mode == mode_64bit && sizeof (bfd_vma) < 8)
12251     {
12252       (*info->fprintf_func) (info->stream,
12253                              _("64-bit address is disabled"));
12254       return -1;
12255     }
12256
12257   if (intel_syntax)
12258     {
12259       names64 = intel_names64;
12260       names32 = intel_names32;
12261       names16 = intel_names16;
12262       names8 = intel_names8;
12263       names8rex = intel_names8rex;
12264       names_seg = intel_names_seg;
12265       names_mm = intel_names_mm;
12266       names_bnd = intel_names_bnd;
12267       names_xmm = intel_names_xmm;
12268       names_ymm = intel_names_ymm;
12269       names_zmm = intel_names_zmm;
12270       index64 = intel_index64;
12271       index32 = intel_index32;
12272       names_mask = intel_names_mask;
12273       index16 = intel_index16;
12274       open_char = '[';
12275       close_char = ']';
12276       separator_char = '+';
12277       scale_char = '*';
12278     }
12279   else
12280     {
12281       names64 = att_names64;
12282       names32 = att_names32;
12283       names16 = att_names16;
12284       names8 = att_names8;
12285       names8rex = att_names8rex;
12286       names_seg = att_names_seg;
12287       names_mm = att_names_mm;
12288       names_bnd = att_names_bnd;
12289       names_xmm = att_names_xmm;
12290       names_ymm = att_names_ymm;
12291       names_zmm = att_names_zmm;
12292       index64 = att_index64;
12293       index32 = att_index32;
12294       names_mask = att_names_mask;
12295       index16 = att_index16;
12296       open_char = '(';
12297       close_char =  ')';
12298       separator_char = ',';
12299       scale_char = ',';
12300     }
12301
12302   /* The output looks better if we put 7 bytes on a line, since that
12303      puts most long word instructions on a single line.  Use 8 bytes
12304      for Intel L1OM.  */
12305   if ((info->mach & bfd_mach_l1om) != 0)
12306     info->bytes_per_line = 8;
12307   else
12308     info->bytes_per_line = 7;
12309
12310   info->private_data = &priv;
12311   priv.max_fetched = priv.the_buffer;
12312   priv.insn_start = pc;
12313
12314   obuf[0] = 0;
12315   for (i = 0; i < MAX_OPERANDS; ++i)
12316     {
12317       op_out[i][0] = 0;
12318       op_index[i] = -1;
12319     }
12320
12321   the_info = info;
12322   start_pc = pc;
12323   start_codep = priv.the_buffer;
12324   codep = priv.the_buffer;
12325
12326   if (OPCODES_SIGSETJMP (priv.bailout) != 0)
12327     {
12328       const char *name;
12329
12330       /* Getting here means we tried for data but didn't get it.  That
12331          means we have an incomplete instruction of some sort.  Just
12332          print the first byte as a prefix or a .byte pseudo-op.  */
12333       if (codep > priv.the_buffer)
12334         {
12335           name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
12336           if (name != NULL)
12337             (*info->fprintf_func) (info->stream, "%s", name);
12338           else
12339             {
12340               /* Just print the first byte as a .byte instruction.  */
12341               (*info->fprintf_func) (info->stream, ".byte 0x%x",
12342                                      (unsigned int) priv.the_buffer[0]);
12343             }
12344
12345           return 1;
12346         }
12347
12348       return -1;
12349     }
12350
12351   obufp = obuf;
12352   sizeflag = priv.orig_sizeflag;
12353
12354   if (!ckprefix () || rex_used)
12355     {
12356       /* Too many prefixes or unused REX prefixes.  */
12357       for (i = 0;
12358            i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i];
12359            i++)
12360         (*info->fprintf_func) (info->stream, "%s%s",
12361                                i == 0 ? "" : " ",
12362                                prefix_name (all_prefixes[i], sizeflag));
12363       return i;
12364     }
12365
12366   insn_codep = codep;
12367
12368   FETCH_DATA (info, codep + 1);
12369   two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
12370
12371   if (((prefixes & PREFIX_FWAIT)
12372        && ((*codep < 0xd8) || (*codep > 0xdf))))
12373     {
12374       /* Handle prefixes before fwait.  */
12375       for (i = 0; i < fwait_prefix && all_prefixes[i];
12376            i++)
12377         (*info->fprintf_func) (info->stream, "%s ",
12378                                prefix_name (all_prefixes[i], sizeflag));
12379       (*info->fprintf_func) (info->stream, "fwait");
12380       return i + 1;
12381     }
12382
12383   if (*codep == 0x0f)
12384     {
12385       unsigned char threebyte;
12386
12387       codep++;
12388       FETCH_DATA (info, codep + 1);
12389       threebyte = *codep;
12390       dp = &dis386_twobyte[threebyte];
12391       need_modrm = twobyte_has_modrm[*codep];
12392       codep++;
12393     }
12394   else
12395     {
12396       dp = &dis386[*codep];
12397       need_modrm = onebyte_has_modrm[*codep];
12398       codep++;
12399     }
12400
12401   /* Save sizeflag for printing the extra prefixes later before updating
12402      it for mnemonic and operand processing.  The prefix names depend
12403      only on the address mode.  */
12404   orig_sizeflag = sizeflag;
12405   if (prefixes & PREFIX_ADDR)
12406     sizeflag ^= AFLAG;
12407   if ((prefixes & PREFIX_DATA))
12408     sizeflag ^= DFLAG;
12409
12410   end_codep = codep;
12411   if (need_modrm)
12412     {
12413       FETCH_DATA (info, codep + 1);
12414       modrm.mod = (*codep >> 6) & 3;
12415       modrm.reg = (*codep >> 3) & 7;
12416       modrm.rm = *codep & 7;
12417     }
12418
12419   need_vex = 0;
12420   need_vex_reg = 0;
12421   memset (&vex, 0, sizeof (vex));
12422
12423   if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
12424     {
12425       get_sib (info, sizeflag);
12426       dofloat (sizeflag);
12427     }
12428   else
12429     {
12430       dp = get_valid_dis386 (dp, info);
12431       if (dp != NULL && putop (dp->name, sizeflag) == 0)
12432         {
12433           get_sib (info, sizeflag);
12434           for (i = 0; i < MAX_OPERANDS; ++i)
12435             {
12436               obufp = op_out[i];
12437               op_ad = MAX_OPERANDS - 1 - i;
12438               if (dp->op[i].rtn)
12439                 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
12440               /* For EVEX instruction after the last operand masking
12441                  should be printed.  */
12442               if (i == 0 && vex.evex)
12443                 {
12444                   /* Don't print {%k0}.  */
12445                   if (vex.mask_register_specifier)
12446                     {
12447                       oappend ("{");
12448                       oappend (names_mask[vex.mask_register_specifier]);
12449                       oappend ("}");
12450                     }
12451                   if (vex.zeroing)
12452                     oappend ("{z}");
12453                 }
12454             }
12455         }
12456     }
12457
12458   /* Clear instruction information.  */
12459   if (the_info)
12460     {
12461       the_info->insn_info_valid = 0;
12462       the_info->branch_delay_insns = 0;
12463       the_info->data_size = 0;
12464       the_info->insn_type = dis_noninsn;
12465       the_info->target = 0;
12466       the_info->target2 = 0;
12467     }
12468
12469   /* Reset jump operation indicator.  */
12470   op_is_jump = FALSE;
12471
12472   {
12473     int jump_detection = 0;
12474
12475     /* Extract flags.  */
12476     for (i = 0; i < MAX_OPERANDS; ++i)
12477       {
12478         if ((dp->op[i].rtn == OP_J)
12479             || (dp->op[i].rtn == OP_indirE))
12480           jump_detection |= 1;
12481         else if ((dp->op[i].rtn == BND_Fixup)
12482                  || (!dp->op[i].rtn && !dp->op[i].bytemode))
12483           jump_detection |= 2;
12484         else if ((dp->op[i].bytemode == cond_jump_mode)
12485                  || (dp->op[i].bytemode == loop_jcxz_mode))
12486           jump_detection |= 4;
12487       }
12488
12489     /* Determine if this is a jump or branch.  */
12490     if ((jump_detection & 0x3) == 0x3)
12491       {
12492         op_is_jump = TRUE;
12493         if (jump_detection & 0x4)
12494           the_info->insn_type = dis_condbranch;
12495         else
12496           the_info->insn_type =
12497             (dp->name && !strncmp(dp->name, "call", 4))
12498             ? dis_jsr : dis_branch;
12499       }
12500   }
12501
12502   /* If VEX.vvvv and EVEX.vvvv are unused, they must be all 1s, which
12503      are all 0s in inverted form.  */
12504   if (need_vex && vex.register_specifier != 0)
12505     {
12506       (*info->fprintf_func) (info->stream, "(bad)");
12507       return end_codep - priv.the_buffer;
12508     }
12509
12510   /* Check if the REX prefix is used.  */
12511   if ((rex ^ rex_used) == 0 && !need_vex && last_rex_prefix >= 0)
12512     all_prefixes[last_rex_prefix] = 0;
12513
12514   /* Check if the SEG prefix is used.  */
12515   if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
12516                    | PREFIX_FS | PREFIX_GS)) != 0
12517       && (used_prefixes & active_seg_prefix) != 0)
12518     all_prefixes[last_seg_prefix] = 0;
12519
12520   /* Check if the ADDR prefix is used.  */
12521   if ((prefixes & PREFIX_ADDR) != 0
12522       && (used_prefixes & PREFIX_ADDR) != 0)
12523     all_prefixes[last_addr_prefix] = 0;
12524
12525   /* Check if the DATA prefix is used.  */
12526   if ((prefixes & PREFIX_DATA) != 0
12527       && (used_prefixes & PREFIX_DATA) != 0
12528       && !need_vex)
12529     all_prefixes[last_data_prefix] = 0;
12530
12531   /* Print the extra prefixes.  */
12532   prefix_length = 0;
12533   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
12534     if (all_prefixes[i])
12535       {
12536         const char *name;
12537         name = prefix_name (all_prefixes[i], orig_sizeflag);
12538         if (name == NULL)
12539           abort ();
12540         prefix_length += strlen (name) + 1;
12541         (*info->fprintf_func) (info->stream, "%s ", name);
12542       }
12543
12544   /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
12545      unused, opcode is invalid.  Since the PREFIX_DATA prefix may be
12546      used by putop and MMX/SSE operand and may be overriden by the
12547      PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
12548      separately.  */
12549   if (dp->prefix_requirement == PREFIX_OPCODE
12550       && (((need_vex
12551             ? vex.prefix == REPE_PREFIX_OPCODE
12552               || vex.prefix == REPNE_PREFIX_OPCODE
12553             : (prefixes
12554                & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
12555            && (used_prefixes
12556                & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
12557           || (((need_vex
12558                 ? vex.prefix == DATA_PREFIX_OPCODE
12559                 : ((prefixes
12560                     & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
12561                    == PREFIX_DATA))
12562                && (used_prefixes & PREFIX_DATA) == 0))
12563           || (vex.evex && !vex.w != !(used_prefixes & PREFIX_DATA))))
12564     {
12565       (*info->fprintf_func) (info->stream, "(bad)");
12566       return end_codep - priv.the_buffer;
12567     }
12568
12569   /* Check maximum code length.  */
12570   if ((codep - start_codep) > MAX_CODE_LENGTH)
12571     {
12572       (*info->fprintf_func) (info->stream, "(bad)");
12573       return MAX_CODE_LENGTH;
12574     }
12575
12576   obufp = mnemonicendp;
12577   for (i = strlen (obuf) + prefix_length; i < 6; i++)
12578     oappend (" ");
12579   oappend (" ");
12580   (*info->fprintf_func) (info->stream, "%s", obuf);
12581
12582   /* The enter and bound instructions are printed with operands in the same
12583      order as the intel book; everything else is printed in reverse order.  */
12584   if (intel_syntax || two_source_ops)
12585     {
12586       bfd_vma riprel;
12587
12588       for (i = 0; i < MAX_OPERANDS; ++i)
12589         op_txt[i] = op_out[i];
12590
12591       if (intel_syntax && dp && dp->op[2].rtn == OP_Rounding
12592           && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL)
12593         {
12594           op_txt[2] = op_out[3];
12595           op_txt[3] = op_out[2];
12596         }
12597
12598       for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
12599         {
12600           op_ad = op_index[i];
12601           op_index[i] = op_index[MAX_OPERANDS - 1 - i];
12602           op_index[MAX_OPERANDS - 1 - i] = op_ad;
12603           riprel = op_riprel[i];
12604           op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
12605           op_riprel[MAX_OPERANDS - 1 - i] = riprel;
12606         }
12607     }
12608   else
12609     {
12610       for (i = 0; i < MAX_OPERANDS; ++i)
12611         op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
12612     }
12613
12614   needcomma = 0;
12615   for (i = 0; i < MAX_OPERANDS; ++i)
12616     if (*op_txt[i])
12617       {
12618         if (needcomma)
12619           (*info->fprintf_func) (info->stream, ",");
12620         if (op_index[i] != -1 && !op_riprel[i])
12621           {
12622             bfd_vma target = (bfd_vma) op_address[op_index[i]];
12623
12624             if (the_info && op_is_jump)
12625               {
12626                 the_info->insn_info_valid = 1;
12627                 the_info->branch_delay_insns = 0;
12628                 the_info->data_size = 0;
12629                 the_info->target = target;
12630                 the_info->target2 = 0;
12631               }
12632             (*info->print_address_func) (target, info);
12633           }
12634         else
12635           (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
12636         needcomma = 1;
12637       }
12638
12639   for (i = 0; i < MAX_OPERANDS; i++)
12640     if (op_index[i] != -1 && op_riprel[i])
12641       {
12642         (*info->fprintf_func) (info->stream, "        # ");
12643         (*info->print_address_func) ((bfd_vma) (start_pc + (codep - start_codep)
12644                                                 + op_address[op_index[i]]), info);
12645         break;
12646       }
12647   return codep - priv.the_buffer;
12648 }
12649
12650 static const char *float_mem[] = {
12651   /* d8 */
12652   "fadd{s|}",
12653   "fmul{s|}",
12654   "fcom{s|}",
12655   "fcomp{s|}",
12656   "fsub{s|}",
12657   "fsubr{s|}",
12658   "fdiv{s|}",
12659   "fdivr{s|}",
12660   /* d9 */
12661   "fld{s|}",
12662   "(bad)",
12663   "fst{s|}",
12664   "fstp{s|}",
12665   "fldenv{C|C}",
12666   "fldcw",
12667   "fNstenv{C|C}",
12668   "fNstcw",
12669   /* da */
12670   "fiadd{l|}",
12671   "fimul{l|}",
12672   "ficom{l|}",
12673   "ficomp{l|}",
12674   "fisub{l|}",
12675   "fisubr{l|}",
12676   "fidiv{l|}",
12677   "fidivr{l|}",
12678   /* db */
12679   "fild{l|}",
12680   "fisttp{l|}",
12681   "fist{l|}",
12682   "fistp{l|}",
12683   "(bad)",
12684   "fld{t|}",
12685   "(bad)",
12686   "fstp{t|}",
12687   /* dc */
12688   "fadd{l|}",
12689   "fmul{l|}",
12690   "fcom{l|}",
12691   "fcomp{l|}",
12692   "fsub{l|}",
12693   "fsubr{l|}",
12694   "fdiv{l|}",
12695   "fdivr{l|}",
12696   /* dd */
12697   "fld{l|}",
12698   "fisttp{ll|}",
12699   "fst{l||}",
12700   "fstp{l|}",
12701   "frstor{C|C}",
12702   "(bad)",
12703   "fNsave{C|C}",
12704   "fNstsw",
12705   /* de */
12706   "fiadd{s|}",
12707   "fimul{s|}",
12708   "ficom{s|}",
12709   "ficomp{s|}",
12710   "fisub{s|}",
12711   "fisubr{s|}",
12712   "fidiv{s|}",
12713   "fidivr{s|}",
12714   /* df */
12715   "fild{s|}",
12716   "fisttp{s|}",
12717   "fist{s|}",
12718   "fistp{s|}",
12719   "fbld",
12720   "fild{ll|}",
12721   "fbstp",
12722   "fistp{ll|}",
12723 };
12724
12725 static const unsigned char float_mem_mode[] = {
12726   /* d8 */
12727   d_mode,
12728   d_mode,
12729   d_mode,
12730   d_mode,
12731   d_mode,
12732   d_mode,
12733   d_mode,
12734   d_mode,
12735   /* d9 */
12736   d_mode,
12737   0,
12738   d_mode,
12739   d_mode,
12740   0,
12741   w_mode,
12742   0,
12743   w_mode,
12744   /* da */
12745   d_mode,
12746   d_mode,
12747   d_mode,
12748   d_mode,
12749   d_mode,
12750   d_mode,
12751   d_mode,
12752   d_mode,
12753   /* db */
12754   d_mode,
12755   d_mode,
12756   d_mode,
12757   d_mode,
12758   0,
12759   t_mode,
12760   0,
12761   t_mode,
12762   /* dc */
12763   q_mode,
12764   q_mode,
12765   q_mode,
12766   q_mode,
12767   q_mode,
12768   q_mode,
12769   q_mode,
12770   q_mode,
12771   /* dd */
12772   q_mode,
12773   q_mode,
12774   q_mode,
12775   q_mode,
12776   0,
12777   0,
12778   0,
12779   w_mode,
12780   /* de */
12781   w_mode,
12782   w_mode,
12783   w_mode,
12784   w_mode,
12785   w_mode,
12786   w_mode,
12787   w_mode,
12788   w_mode,
12789   /* df */
12790   w_mode,
12791   w_mode,
12792   w_mode,
12793   w_mode,
12794   t_mode,
12795   q_mode,
12796   t_mode,
12797   q_mode
12798 };
12799
12800 #define ST { OP_ST, 0 }
12801 #define STi { OP_STi, 0 }
12802
12803 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
12804 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
12805 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
12806 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
12807 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
12808 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
12809 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
12810 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
12811 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
12812
12813 static const struct dis386 float_reg[][8] = {
12814   /* d8 */
12815   {
12816     { "fadd",   { ST, STi }, 0 },
12817     { "fmul",   { ST, STi }, 0 },
12818     { "fcom",   { STi }, 0 },
12819     { "fcomp",  { STi }, 0 },
12820     { "fsub",   { ST, STi }, 0 },
12821     { "fsubr",  { ST, STi }, 0 },
12822     { "fdiv",   { ST, STi }, 0 },
12823     { "fdivr",  { ST, STi }, 0 },
12824   },
12825   /* d9 */
12826   {
12827     { "fld",    { STi }, 0 },
12828     { "fxch",   { STi }, 0 },
12829     { FGRPd9_2 },
12830     { Bad_Opcode },
12831     { FGRPd9_4 },
12832     { FGRPd9_5 },
12833     { FGRPd9_6 },
12834     { FGRPd9_7 },
12835   },
12836   /* da */
12837   {
12838     { "fcmovb", { ST, STi }, 0 },
12839     { "fcmove", { ST, STi }, 0 },
12840     { "fcmovbe",{ ST, STi }, 0 },
12841     { "fcmovu", { ST, STi }, 0 },
12842     { Bad_Opcode },
12843     { FGRPda_5 },
12844     { Bad_Opcode },
12845     { Bad_Opcode },
12846   },
12847   /* db */
12848   {
12849     { "fcmovnb",{ ST, STi }, 0 },
12850     { "fcmovne",{ ST, STi }, 0 },
12851     { "fcmovnbe",{ ST, STi }, 0 },
12852     { "fcmovnu",{ ST, STi }, 0 },
12853     { FGRPdb_4 },
12854     { "fucomi", { ST, STi }, 0 },
12855     { "fcomi",  { ST, STi }, 0 },
12856     { Bad_Opcode },
12857   },
12858   /* dc */
12859   {
12860     { "fadd",   { STi, ST }, 0 },
12861     { "fmul",   { STi, ST }, 0 },
12862     { Bad_Opcode },
12863     { Bad_Opcode },
12864     { "fsub{!M|r}",     { STi, ST }, 0 },
12865     { "fsub{M|}",       { STi, ST }, 0 },
12866     { "fdiv{!M|r}",     { STi, ST }, 0 },
12867     { "fdiv{M|}",       { STi, ST }, 0 },
12868   },
12869   /* dd */
12870   {
12871     { "ffree",  { STi }, 0 },
12872     { Bad_Opcode },
12873     { "fst",    { STi }, 0 },
12874     { "fstp",   { STi }, 0 },
12875     { "fucom",  { STi }, 0 },
12876     { "fucomp", { STi }, 0 },
12877     { Bad_Opcode },
12878     { Bad_Opcode },
12879   },
12880   /* de */
12881   {
12882     { "faddp",  { STi, ST }, 0 },
12883     { "fmulp",  { STi, ST }, 0 },
12884     { Bad_Opcode },
12885     { FGRPde_3 },
12886     { "fsub{!M|r}p",    { STi, ST }, 0 },
12887     { "fsub{M|}p",      { STi, ST }, 0 },
12888     { "fdiv{!M|r}p",    { STi, ST }, 0 },
12889     { "fdiv{M|}p",      { STi, ST }, 0 },
12890   },
12891   /* df */
12892   {
12893     { "ffreep", { STi }, 0 },
12894     { Bad_Opcode },
12895     { Bad_Opcode },
12896     { Bad_Opcode },
12897     { FGRPdf_4 },
12898     { "fucomip", { ST, STi }, 0 },
12899     { "fcomip", { ST, STi }, 0 },
12900     { Bad_Opcode },
12901   },
12902 };
12903
12904 static char *fgrps[][8] = {
12905   /* Bad opcode 0 */
12906   {
12907     "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12908   },
12909
12910   /* d9_2  1 */
12911   {
12912     "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12913   },
12914
12915   /* d9_4  2 */
12916   {
12917     "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
12918   },
12919
12920   /* d9_5  3 */
12921   {
12922     "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
12923   },
12924
12925   /* d9_6  4 */
12926   {
12927     "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
12928   },
12929
12930   /* d9_7  5 */
12931   {
12932     "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
12933   },
12934
12935   /* da_5  6 */
12936   {
12937     "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12938   },
12939
12940   /* db_4  7 */
12941   {
12942     "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
12943     "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
12944   },
12945
12946   /* de_3  8 */
12947   {
12948     "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12949   },
12950
12951   /* df_4  9 */
12952   {
12953     "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12954   },
12955 };
12956
12957 static void
12958 swap_operand (void)
12959 {
12960   mnemonicendp[0] = '.';
12961   mnemonicendp[1] = 's';
12962   mnemonicendp += 2;
12963 }
12964
12965 static void
12966 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
12967                int sizeflag ATTRIBUTE_UNUSED)
12968 {
12969   /* Skip mod/rm byte.  */
12970   MODRM_CHECK;
12971   codep++;
12972 }
12973
12974 static void
12975 dofloat (int sizeflag)
12976 {
12977   const struct dis386 *dp;
12978   unsigned char floatop;
12979
12980   floatop = codep[-1];
12981
12982   if (modrm.mod != 3)
12983     {
12984       int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
12985
12986       putop (float_mem[fp_indx], sizeflag);
12987       obufp = op_out[0];
12988       op_ad = 2;
12989       OP_E (float_mem_mode[fp_indx], sizeflag);
12990       return;
12991     }
12992   /* Skip mod/rm byte.  */
12993   MODRM_CHECK;
12994   codep++;
12995
12996   dp = &float_reg[floatop - 0xd8][modrm.reg];
12997   if (dp->name == NULL)
12998     {
12999       putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
13000
13001       /* Instruction fnstsw is only one with strange arg.  */
13002       if (floatop == 0xdf && codep[-1] == 0xe0)
13003         strcpy (op_out[0], names16[0]);
13004     }
13005   else
13006     {
13007       putop (dp->name, sizeflag);
13008
13009       obufp = op_out[0];
13010       op_ad = 2;
13011       if (dp->op[0].rtn)
13012         (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
13013
13014       obufp = op_out[1];
13015       op_ad = 1;
13016       if (dp->op[1].rtn)
13017         (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
13018     }
13019 }
13020
13021 /* Like oappend (below), but S is a string starting with '%'.
13022    In Intel syntax, the '%' is elided.  */
13023 static void
13024 oappend_maybe_intel (const char *s)
13025 {
13026   oappend (s + intel_syntax);
13027 }
13028
13029 static void
13030 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13031 {
13032   oappend_maybe_intel ("%st");
13033 }
13034
13035 static void
13036 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13037 {
13038   sprintf (scratchbuf, "%%st(%d)", modrm.rm);
13039   oappend_maybe_intel (scratchbuf);
13040 }
13041
13042 /* Capital letters in template are macros.  */
13043 static int
13044 putop (const char *in_template, int sizeflag)
13045 {
13046   const char *p;
13047   int alt = 0;
13048   int cond = 1;
13049   unsigned int l = 0, len = 0;
13050   char last[4];
13051
13052   for (p = in_template; *p; p++)
13053     {
13054       if (len > l)
13055         {
13056           if (l >= sizeof (last) || !ISUPPER (*p))
13057             abort ();
13058           last[l++] = *p;
13059           continue;
13060         }
13061       switch (*p)
13062         {
13063         default:
13064           *obufp++ = *p;
13065           break;
13066         case '%':
13067           len++;
13068           break;
13069         case '!':
13070           cond = 0;
13071           break;
13072         case '{':
13073           if (intel_syntax)
13074             {
13075               while (*++p != '|')
13076                 if (*p == '}' || *p == '\0')
13077                   abort ();
13078               alt = 1;
13079             }
13080           break;
13081         case '|':
13082           while (*++p != '}')
13083             {
13084               if (*p == '\0')
13085                 abort ();
13086             }
13087           break;
13088         case '}':
13089           alt = 0;
13090           break;
13091         case 'A':
13092           if (intel_syntax)
13093             break;
13094           if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13095             *obufp++ = 'b';
13096           break;
13097         case 'B':
13098           if (l == 0)
13099             {
13100             case_B:
13101               if (intel_syntax)
13102                 break;
13103               if (sizeflag & SUFFIX_ALWAYS)
13104                 *obufp++ = 'b';
13105             }
13106           else if (l == 1 && last[0] == 'L')
13107             {
13108               if (address_mode == mode_64bit
13109                   && !(prefixes & PREFIX_ADDR))
13110                 {
13111                   *obufp++ = 'a';
13112                   *obufp++ = 'b';
13113                   *obufp++ = 's';
13114                 }
13115
13116               goto case_B;
13117             }
13118           else
13119             abort ();
13120           break;
13121         case 'C':
13122           if (intel_syntax && !alt)
13123             break;
13124           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
13125             {
13126               if (sizeflag & DFLAG)
13127                 *obufp++ = intel_syntax ? 'd' : 'l';
13128               else
13129                 *obufp++ = intel_syntax ? 'w' : 's';
13130               used_prefixes |= (prefixes & PREFIX_DATA);
13131             }
13132           break;
13133         case 'D':
13134           if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
13135             break;
13136           USED_REX (REX_W);
13137           if (modrm.mod == 3)
13138             {
13139               if (rex & REX_W)
13140                 *obufp++ = 'q';
13141               else
13142                 {
13143                   if (sizeflag & DFLAG)
13144                     *obufp++ = intel_syntax ? 'd' : 'l';
13145                   else
13146                     *obufp++ = 'w';
13147                   used_prefixes |= (prefixes & PREFIX_DATA);
13148                 }
13149             }
13150           else
13151             *obufp++ = 'w';
13152           break;
13153         case 'E':               /* For jcxz/jecxz */
13154           if (address_mode == mode_64bit)
13155             {
13156               if (sizeflag & AFLAG)
13157                 *obufp++ = 'r';
13158               else
13159                 *obufp++ = 'e';
13160             }
13161           else
13162             if (sizeflag & AFLAG)
13163               *obufp++ = 'e';
13164           used_prefixes |= (prefixes & PREFIX_ADDR);
13165           break;
13166         case 'F':
13167           if (intel_syntax)
13168             break;
13169           if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
13170             {
13171               if (sizeflag & AFLAG)
13172                 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
13173               else
13174                 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
13175               used_prefixes |= (prefixes & PREFIX_ADDR);
13176             }
13177           break;
13178         case 'G':
13179           if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
13180             break;
13181           if ((rex & REX_W) || (sizeflag & DFLAG))
13182             *obufp++ = 'l';
13183           else
13184             *obufp++ = 'w';
13185           if (!(rex & REX_W))
13186             used_prefixes |= (prefixes & PREFIX_DATA);
13187           break;
13188         case 'H':
13189           if (intel_syntax)
13190             break;
13191           if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
13192               || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
13193             {
13194               used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
13195               *obufp++ = ',';
13196               *obufp++ = 'p';
13197               if (prefixes & PREFIX_DS)
13198                 *obufp++ = 't';
13199               else
13200                 *obufp++ = 'n';
13201             }
13202           break;
13203         case 'K':
13204           USED_REX (REX_W);
13205           if (rex & REX_W)
13206             *obufp++ = 'q';
13207           else
13208             *obufp++ = 'd';
13209           break;
13210         case 'Z':
13211           if (l != 0)
13212             {
13213               if (l != 1 || last[0] != 'X')
13214                 abort ();
13215               if (!need_vex || !vex.evex)
13216                 abort ();
13217               if (intel_syntax
13218                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
13219                 break;
13220               switch (vex.length)
13221                 {
13222                 case 128:
13223                   *obufp++ = 'x';
13224                   break;
13225                 case 256:
13226                   *obufp++ = 'y';
13227                   break;
13228                 case 512:
13229                   *obufp++ = 'z';
13230                   break;
13231                 default:
13232                   abort ();
13233                 }
13234               break;
13235             }
13236           if (intel_syntax)
13237             break;
13238           if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
13239             {
13240               *obufp++ = 'q';
13241               break;
13242             }
13243           /* Fall through.  */
13244           goto case_L;
13245         case 'L':
13246           if (l != 0)
13247             abort ();
13248         case_L:
13249           if (intel_syntax)
13250             break;
13251           if (sizeflag & SUFFIX_ALWAYS)
13252             *obufp++ = 'l';
13253           break;
13254         case 'M':
13255           if (intel_mnemonic != cond)
13256             *obufp++ = 'r';
13257           break;
13258         case 'N':
13259           if ((prefixes & PREFIX_FWAIT) == 0)
13260             *obufp++ = 'n';
13261           else
13262             used_prefixes |= PREFIX_FWAIT;
13263           break;
13264         case 'O':
13265           USED_REX (REX_W);
13266           if (rex & REX_W)
13267             *obufp++ = 'o';
13268           else if (intel_syntax && (sizeflag & DFLAG))
13269             *obufp++ = 'q';
13270           else
13271             *obufp++ = 'd';
13272           if (!(rex & REX_W))
13273             used_prefixes |= (prefixes & PREFIX_DATA);
13274           break;
13275         case '&':
13276           if (!intel_syntax
13277               && address_mode == mode_64bit
13278               && isa64 == intel64)
13279             {
13280               *obufp++ = 'q';
13281               break;
13282             }
13283           /* Fall through.  */
13284         case 'T':
13285           if (!intel_syntax
13286               && address_mode == mode_64bit
13287               && ((sizeflag & DFLAG) || (rex & REX_W)))
13288             {
13289               *obufp++ = 'q';
13290               break;
13291             }
13292           /* Fall through.  */
13293           goto case_P;
13294         case 'P':
13295           if (l == 0)
13296             {
13297             case_P:
13298               if (intel_syntax)
13299                 {
13300                   if ((rex & REX_W) == 0
13301                       && (prefixes & PREFIX_DATA))
13302                     {
13303                       if ((sizeflag & DFLAG) == 0)
13304                         *obufp++ = 'w';
13305                       used_prefixes |= (prefixes & PREFIX_DATA);
13306                     }
13307                   break;
13308                 }
13309               if ((prefixes & PREFIX_DATA)
13310                   || (rex & REX_W)
13311                   || (sizeflag & SUFFIX_ALWAYS))
13312                 {
13313                   USED_REX (REX_W);
13314                   if (rex & REX_W)
13315                     *obufp++ = 'q';
13316                   else
13317                     {
13318                       if (sizeflag & DFLAG)
13319                         *obufp++ = 'l';
13320                       else
13321                         *obufp++ = 'w';
13322                       used_prefixes |= (prefixes & PREFIX_DATA);
13323                     }
13324                 }
13325             }
13326           else if (l == 1 && last[0] == 'L')
13327             {
13328               if ((prefixes & PREFIX_DATA)
13329                   || (rex & REX_W)
13330                   || (sizeflag & SUFFIX_ALWAYS))
13331                 {
13332                   USED_REX (REX_W);
13333                   if (rex & REX_W)
13334                     *obufp++ = 'q';
13335                   else
13336                     {
13337                       if (sizeflag & DFLAG)
13338                         *obufp++ = intel_syntax ? 'd' : 'l';
13339                       else
13340                         *obufp++ = 'w';
13341                       used_prefixes |= (prefixes & PREFIX_DATA);
13342                     }
13343                 }
13344             }
13345           else
13346             abort ();
13347           break;
13348         case 'U':
13349           if (intel_syntax)
13350             break;
13351           if (address_mode == mode_64bit
13352               && ((sizeflag & DFLAG) || (rex & REX_W)))
13353             {
13354               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13355                 *obufp++ = 'q';
13356               break;
13357             }
13358           /* Fall through.  */
13359           goto case_Q;
13360         case 'Q':
13361           if (l == 0)
13362             {
13363             case_Q:
13364               if (intel_syntax && !alt)
13365                 break;
13366               USED_REX (REX_W);
13367               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13368                 {
13369                   if (rex & REX_W)
13370                     *obufp++ = 'q';
13371                   else
13372                     {
13373                       if (sizeflag & DFLAG)
13374                         *obufp++ = intel_syntax ? 'd' : 'l';
13375                       else
13376                         *obufp++ = 'w';
13377                       used_prefixes |= (prefixes & PREFIX_DATA);
13378                     }
13379                 }
13380             }
13381           else if (l == 1 && last[0] == 'L')
13382             {
13383               if ((intel_syntax && need_modrm)
13384                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
13385                 break;
13386               if ((rex & REX_W))
13387                 {
13388                   USED_REX (REX_W);
13389                   *obufp++ = 'q';
13390                 }
13391               else if((address_mode == mode_64bit && need_modrm)
13392                       || (sizeflag & SUFFIX_ALWAYS))
13393                 *obufp++ = intel_syntax? 'd' : 'l';
13394             }
13395           else
13396             abort ();
13397           break;
13398         case 'R':
13399           USED_REX (REX_W);
13400           if (rex & REX_W)
13401             *obufp++ = 'q';
13402           else if (sizeflag & DFLAG)
13403             {
13404               if (intel_syntax)
13405                   *obufp++ = 'd';
13406               else
13407                   *obufp++ = 'l';
13408             }
13409           else
13410             *obufp++ = 'w';
13411           if (intel_syntax && !p[1]
13412               && ((rex & REX_W) || (sizeflag & DFLAG)))
13413             *obufp++ = 'e';
13414           if (!(rex & REX_W))
13415             used_prefixes |= (prefixes & PREFIX_DATA);
13416           break;
13417         case 'V':
13418           if (l == 0)
13419             {
13420               if (intel_syntax)
13421                 break;
13422               if (address_mode == mode_64bit
13423                   && ((sizeflag & DFLAG) || (rex & REX_W)))
13424                 {
13425                   if (sizeflag & SUFFIX_ALWAYS)
13426                     *obufp++ = 'q';
13427                   break;
13428                 }
13429             }
13430           else if (l == 1 && last[0] == 'L')
13431             {
13432               if (rex & REX_W)
13433                 {
13434                   *obufp++ = 'a';
13435                   *obufp++ = 'b';
13436                   *obufp++ = 's';
13437                 }
13438             }
13439           else
13440             abort ();
13441           /* Fall through.  */
13442           goto case_S;
13443         case 'S':
13444           if (l == 0)
13445             {
13446             case_S:
13447               if (intel_syntax)
13448                 break;
13449               if (sizeflag & SUFFIX_ALWAYS)
13450                 {
13451                   if (rex & REX_W)
13452                     *obufp++ = 'q';
13453                   else
13454                     {
13455                       if (sizeflag & DFLAG)
13456                         *obufp++ = 'l';
13457                       else
13458                         *obufp++ = 'w';
13459                       used_prefixes |= (prefixes & PREFIX_DATA);
13460                     }
13461                 }
13462             }
13463           else if (l == 1 && last[0] == 'L')
13464             {
13465               if (address_mode == mode_64bit
13466                   && !(prefixes & PREFIX_ADDR))
13467                 {
13468                   *obufp++ = 'a';
13469                   *obufp++ = 'b';
13470                   *obufp++ = 's';
13471                 }
13472
13473               goto case_S;
13474             }
13475           else
13476             abort ();
13477           break;
13478         case 'X':
13479           if (l != 0)
13480             abort ();
13481           if (need_vex
13482               ? vex.prefix == DATA_PREFIX_OPCODE
13483               : prefixes & PREFIX_DATA)
13484             {
13485               *obufp++ = 'd';
13486               used_prefixes |= PREFIX_DATA;
13487             }
13488           else
13489             *obufp++ = 's';
13490           break;
13491         case 'Y':
13492           if (l == 1 && last[0] == 'X')
13493             {
13494               if (!need_vex)
13495                 abort ();
13496               if (intel_syntax
13497                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
13498                 break;
13499               switch (vex.length)
13500                 {
13501                 case 128:
13502                   *obufp++ = 'x';
13503                   break;
13504                 case 256:
13505                   *obufp++ = 'y';
13506                   break;
13507                 case 512:
13508                   if (!vex.evex)
13509                 default:
13510                     abort ();
13511                 }
13512             }
13513           else
13514             abort ();
13515           break;
13516         case 'W':
13517           if (l == 0)
13518             {
13519               /* operand size flag for cwtl, cbtw */
13520               USED_REX (REX_W);
13521               if (rex & REX_W)
13522                 {
13523                   if (intel_syntax)
13524                     *obufp++ = 'd';
13525                   else
13526                     *obufp++ = 'l';
13527                 }
13528               else if (sizeflag & DFLAG)
13529                 *obufp++ = 'w';
13530               else
13531                 *obufp++ = 'b';
13532               if (!(rex & REX_W))
13533                 used_prefixes |= (prefixes & PREFIX_DATA);
13534             }
13535           else if (l == 1)
13536             {
13537               if (!need_vex)
13538                 abort ();
13539               if (last[0] == 'X')
13540                 *obufp++ = vex.w ? 'd': 's';
13541               else if (last[0] == 'L')
13542                 *obufp++ = vex.w ? 'q': 'd';
13543               else if (last[0] == 'B')
13544                 *obufp++ = vex.w ? 'w': 'b';
13545               else
13546                 abort ();
13547             }
13548           else
13549             abort ();
13550           break;
13551         case '^':
13552           if (intel_syntax)
13553             break;
13554           if (isa64 == intel64 && (rex & REX_W))
13555             {
13556               USED_REX (REX_W);
13557               *obufp++ = 'q';
13558               break;
13559             }
13560           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
13561             {
13562               if (sizeflag & DFLAG)
13563                 *obufp++ = 'l';
13564               else
13565                 *obufp++ = 'w';
13566               used_prefixes |= (prefixes & PREFIX_DATA);
13567             }
13568           break;
13569         case '@':
13570           if (intel_syntax)
13571             break;
13572           if (address_mode == mode_64bit
13573               && (isa64 == intel64
13574                   || ((sizeflag & DFLAG) || (rex & REX_W))))
13575               *obufp++ = 'q';
13576           else if ((prefixes & PREFIX_DATA))
13577             {
13578               if (!(sizeflag & DFLAG))
13579                 *obufp++ = 'w';
13580               used_prefixes |= (prefixes & PREFIX_DATA);
13581             }
13582           break;
13583         }
13584
13585       if (len == l)
13586         len = l = 0;
13587     }
13588   *obufp = 0;
13589   mnemonicendp = obufp;
13590   return 0;
13591 }
13592
13593 static void
13594 oappend (const char *s)
13595 {
13596   obufp = stpcpy (obufp, s);
13597 }
13598
13599 static void
13600 append_seg (void)
13601 {
13602   /* Only print the active segment register.  */
13603   if (!active_seg_prefix)
13604     return;
13605
13606   used_prefixes |= active_seg_prefix;
13607   switch (active_seg_prefix)
13608     {
13609     case PREFIX_CS:
13610       oappend_maybe_intel ("%cs:");
13611       break;
13612     case PREFIX_DS:
13613       oappend_maybe_intel ("%ds:");
13614       break;
13615     case PREFIX_SS:
13616       oappend_maybe_intel ("%ss:");
13617       break;
13618     case PREFIX_ES:
13619       oappend_maybe_intel ("%es:");
13620       break;
13621     case PREFIX_FS:
13622       oappend_maybe_intel ("%fs:");
13623       break;
13624     case PREFIX_GS:
13625       oappend_maybe_intel ("%gs:");
13626       break;
13627     default:
13628       break;
13629     }
13630 }
13631
13632 static void
13633 OP_indirE (int bytemode, int sizeflag)
13634 {
13635   if (!intel_syntax)
13636     oappend ("*");
13637   OP_E (bytemode, sizeflag);
13638 }
13639
13640 static void
13641 print_operand_value (char *buf, int hex, bfd_vma disp)
13642 {
13643   if (address_mode == mode_64bit)
13644     {
13645       if (hex)
13646         {
13647           char tmp[30];
13648           int i;
13649           buf[0] = '0';
13650           buf[1] = 'x';
13651           sprintf_vma (tmp, disp);
13652           for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
13653           strcpy (buf + 2, tmp + i);
13654         }
13655       else
13656         {
13657           bfd_signed_vma v = disp;
13658           char tmp[30];
13659           int i;
13660           if (v < 0)
13661             {
13662               *(buf++) = '-';
13663               v = -disp;
13664               /* Check for possible overflow on 0x8000000000000000.  */
13665               if (v < 0)
13666                 {
13667                   strcpy (buf, "9223372036854775808");
13668                   return;
13669                 }
13670             }
13671           if (!v)
13672             {
13673               strcpy (buf, "0");
13674               return;
13675             }
13676
13677           i = 0;
13678           tmp[29] = 0;
13679           while (v)
13680             {
13681               tmp[28 - i] = (v % 10) + '0';
13682               v /= 10;
13683               i++;
13684             }
13685           strcpy (buf, tmp + 29 - i);
13686         }
13687     }
13688   else
13689     {
13690       if (hex)
13691         sprintf (buf, "0x%x", (unsigned int) disp);
13692       else
13693         sprintf (buf, "%d", (int) disp);
13694     }
13695 }
13696
13697 /* Put DISP in BUF as signed hex number.  */
13698
13699 static void
13700 print_displacement (char *buf, bfd_vma disp)
13701 {
13702   bfd_signed_vma val = disp;
13703   char tmp[30];
13704   int i, j = 0;
13705
13706   if (val < 0)
13707     {
13708       buf[j++] = '-';
13709       val = -disp;
13710
13711       /* Check for possible overflow.  */
13712       if (val < 0)
13713         {
13714           switch (address_mode)
13715             {
13716             case mode_64bit:
13717               strcpy (buf + j, "0x8000000000000000");
13718               break;
13719             case mode_32bit:
13720               strcpy (buf + j, "0x80000000");
13721               break;
13722             case mode_16bit:
13723               strcpy (buf + j, "0x8000");
13724               break;
13725             }
13726           return;
13727         }
13728     }
13729
13730   buf[j++] = '0';
13731   buf[j++] = 'x';
13732
13733   sprintf_vma (tmp, (bfd_vma) val);
13734   for (i = 0; tmp[i] == '0'; i++)
13735     continue;
13736   if (tmp[i] == '\0')
13737     i--;
13738   strcpy (buf + j, tmp + i);
13739 }
13740
13741 static void
13742 intel_operand_size (int bytemode, int sizeflag)
13743 {
13744   if (vex.evex
13745       && vex.b
13746       && (bytemode == x_mode
13747           || bytemode == evex_half_bcst_xmmq_mode))
13748     {
13749       if (vex.w)
13750         oappend ("QWORD PTR ");
13751       else
13752         oappend ("DWORD PTR ");
13753       return;
13754     }
13755   switch (bytemode)
13756     {
13757     case b_mode:
13758     case b_swap_mode:
13759     case dqb_mode:
13760     case db_mode:
13761       oappend ("BYTE PTR ");
13762       break;
13763     case w_mode:
13764     case dw_mode:
13765     case dqw_mode:
13766       oappend ("WORD PTR ");
13767       break;
13768     case indir_v_mode:
13769       if (address_mode == mode_64bit && isa64 == intel64)
13770         {
13771           oappend ("QWORD PTR ");
13772           break;
13773         }
13774       /* Fall through.  */
13775     case stack_v_mode:
13776       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
13777         {
13778           oappend ("QWORD PTR ");
13779           break;
13780         }
13781       /* Fall through.  */
13782     case v_mode:
13783     case v_swap_mode:
13784     case dq_mode:
13785       USED_REX (REX_W);
13786       if (rex & REX_W)
13787         oappend ("QWORD PTR ");
13788       else
13789         {
13790           if ((sizeflag & DFLAG) || bytemode == dq_mode)
13791             oappend ("DWORD PTR ");
13792           else
13793             oappend ("WORD PTR ");
13794           used_prefixes |= (prefixes & PREFIX_DATA);
13795         }
13796       break;
13797     case z_mode:
13798       if ((rex & REX_W) || (sizeflag & DFLAG))
13799         *obufp++ = 'D';
13800       oappend ("WORD PTR ");
13801       if (!(rex & REX_W))
13802         used_prefixes |= (prefixes & PREFIX_DATA);
13803       break;
13804     case a_mode:
13805       if (sizeflag & DFLAG)
13806         oappend ("QWORD PTR ");
13807       else
13808         oappend ("DWORD PTR ");
13809       used_prefixes |= (prefixes & PREFIX_DATA);
13810       break;
13811     case movsxd_mode:
13812       if (!(sizeflag & DFLAG) && isa64 == intel64)
13813         oappend ("WORD PTR ");
13814       else
13815         oappend ("DWORD PTR ");
13816       used_prefixes |= (prefixes & PREFIX_DATA);
13817       break;
13818     case d_mode:
13819     case d_scalar_swap_mode:
13820     case d_swap_mode:
13821     case dqd_mode:
13822       oappend ("DWORD PTR ");
13823       break;
13824     case q_mode:
13825     case q_scalar_swap_mode:
13826     case q_swap_mode:
13827       oappend ("QWORD PTR ");
13828       break;
13829     case m_mode:
13830       if (address_mode == mode_64bit)
13831         oappend ("QWORD PTR ");
13832       else
13833         oappend ("DWORD PTR ");
13834       break;
13835     case f_mode:
13836       if (sizeflag & DFLAG)
13837         oappend ("FWORD PTR ");
13838       else
13839         oappend ("DWORD PTR ");
13840       used_prefixes |= (prefixes & PREFIX_DATA);
13841       break;
13842     case t_mode:
13843       oappend ("TBYTE PTR ");
13844       break;
13845     case x_mode:
13846     case x_swap_mode:
13847     case evex_x_gscat_mode:
13848     case evex_x_nobcst_mode:
13849     case b_scalar_mode:
13850     case w_scalar_mode:
13851       if (need_vex)
13852         {
13853           switch (vex.length)
13854             {
13855             case 128:
13856               oappend ("XMMWORD PTR ");
13857               break;
13858             case 256:
13859               oappend ("YMMWORD PTR ");
13860               break;
13861             case 512:
13862               oappend ("ZMMWORD PTR ");
13863               break;
13864             default:
13865               abort ();
13866             }
13867         }
13868       else
13869         oappend ("XMMWORD PTR ");
13870       break;
13871     case xmm_mode:
13872       oappend ("XMMWORD PTR ");
13873       break;
13874     case ymm_mode:
13875       oappend ("YMMWORD PTR ");
13876       break;
13877     case xmmq_mode:
13878     case evex_half_bcst_xmmq_mode:
13879       if (!need_vex)
13880         abort ();
13881
13882       switch (vex.length)
13883         {
13884         case 128:
13885           oappend ("QWORD PTR ");
13886           break;
13887         case 256:
13888           oappend ("XMMWORD PTR ");
13889           break;
13890         case 512:
13891           oappend ("YMMWORD PTR ");
13892           break;
13893         default:
13894           abort ();
13895         }
13896       break;
13897     case xmm_mb_mode:
13898       if (!need_vex)
13899         abort ();
13900
13901       switch (vex.length)
13902         {
13903         case 128:
13904         case 256:
13905         case 512:
13906           oappend ("BYTE PTR ");
13907           break;
13908         default:
13909           abort ();
13910         }
13911       break;
13912     case xmm_mw_mode:
13913       if (!need_vex)
13914         abort ();
13915
13916       switch (vex.length)
13917         {
13918         case 128:
13919         case 256:
13920         case 512:
13921           oappend ("WORD PTR ");
13922           break;
13923         default:
13924           abort ();
13925         }
13926       break;
13927     case xmm_md_mode:
13928       if (!need_vex)
13929         abort ();
13930
13931       switch (vex.length)
13932         {
13933         case 128:
13934         case 256:
13935         case 512:
13936           oappend ("DWORD PTR ");
13937           break;
13938         default:
13939           abort ();
13940         }
13941       break;
13942     case xmm_mq_mode:
13943       if (!need_vex)
13944         abort ();
13945
13946       switch (vex.length)
13947         {
13948         case 128:
13949         case 256:
13950         case 512:
13951           oappend ("QWORD PTR ");
13952           break;
13953         default:
13954           abort ();
13955         }
13956       break;
13957     case xmmdw_mode:
13958       if (!need_vex)
13959         abort ();
13960
13961       switch (vex.length)
13962         {
13963         case 128:
13964           oappend ("WORD PTR ");
13965           break;
13966         case 256:
13967           oappend ("DWORD PTR ");
13968           break;
13969         case 512:
13970           oappend ("QWORD PTR ");
13971           break;
13972         default:
13973           abort ();
13974         }
13975       break;
13976     case xmmqd_mode:
13977       if (!need_vex)
13978         abort ();
13979
13980       switch (vex.length)
13981         {
13982         case 128:
13983           oappend ("DWORD PTR ");
13984           break;
13985         case 256:
13986           oappend ("QWORD PTR ");
13987           break;
13988         case 512:
13989           oappend ("XMMWORD PTR ");
13990           break;
13991         default:
13992           abort ();
13993         }
13994       break;
13995     case ymmq_mode:
13996       if (!need_vex)
13997         abort ();
13998
13999       switch (vex.length)
14000         {
14001         case 128:
14002           oappend ("QWORD PTR ");
14003           break;
14004         case 256:
14005           oappend ("YMMWORD PTR ");
14006           break;
14007         case 512:
14008           oappend ("ZMMWORD PTR ");
14009           break;
14010         default:
14011           abort ();
14012         }
14013       break;
14014     case ymmxmm_mode:
14015       if (!need_vex)
14016         abort ();
14017
14018       switch (vex.length)
14019         {
14020         case 128:
14021         case 256:
14022           oappend ("XMMWORD PTR ");
14023           break;
14024         default:
14025           abort ();
14026         }
14027       break;
14028     case o_mode:
14029       oappend ("OWORD PTR ");
14030       break;
14031     case vex_scalar_w_dq_mode:
14032       if (!need_vex)
14033         abort ();
14034
14035       if (vex.w)
14036         oappend ("QWORD PTR ");
14037       else
14038         oappend ("DWORD PTR ");
14039       break;
14040     case vex_vsib_d_w_dq_mode:
14041     case vex_vsib_q_w_dq_mode:
14042       if (!need_vex)
14043         abort ();
14044
14045       if (!vex.evex)
14046         {
14047           if (vex.w)
14048             oappend ("QWORD PTR ");
14049           else
14050             oappend ("DWORD PTR ");
14051         }
14052       else
14053         {
14054           switch (vex.length)
14055             {
14056             case 128:
14057               oappend ("XMMWORD PTR ");
14058               break;
14059             case 256:
14060               oappend ("YMMWORD PTR ");
14061               break;
14062             case 512:
14063               oappend ("ZMMWORD PTR ");
14064               break;
14065             default:
14066               abort ();
14067             }
14068         }
14069       break;
14070     case vex_vsib_q_w_d_mode:
14071     case vex_vsib_d_w_d_mode:
14072       if (!need_vex || !vex.evex)
14073         abort ();
14074
14075       switch (vex.length)
14076         {
14077         case 128:
14078           oappend ("QWORD PTR ");
14079           break;
14080         case 256:
14081           oappend ("XMMWORD PTR ");
14082           break;
14083         case 512:
14084           oappend ("YMMWORD PTR ");
14085           break;
14086         default:
14087           abort ();
14088         }
14089
14090       break;
14091     case mask_bd_mode:
14092       if (!need_vex || vex.length != 128)
14093         abort ();
14094       if (vex.w)
14095         oappend ("DWORD PTR ");
14096       else
14097         oappend ("BYTE PTR ");
14098       break;
14099     case mask_mode:
14100       if (!need_vex)
14101         abort ();
14102       if (vex.w)
14103         oappend ("QWORD PTR ");
14104       else
14105         oappend ("WORD PTR ");
14106       break;
14107     case v_bnd_mode:
14108     case v_bndmk_mode:
14109     default:
14110       break;
14111     }
14112 }
14113
14114 static void
14115 OP_E_register (int bytemode, int sizeflag)
14116 {
14117   int reg = modrm.rm;
14118   const char **names;
14119
14120   USED_REX (REX_B);
14121   if ((rex & REX_B))
14122     reg += 8;
14123
14124   if ((sizeflag & SUFFIX_ALWAYS)
14125       && (bytemode == b_swap_mode
14126           || bytemode == bnd_swap_mode
14127           || bytemode == v_swap_mode))
14128     swap_operand ();
14129
14130   switch (bytemode)
14131     {
14132     case b_mode:
14133     case b_swap_mode:
14134       USED_REX (0);
14135       if (rex)
14136         names = names8rex;
14137       else
14138         names = names8;
14139       break;
14140     case w_mode:
14141       names = names16;
14142       break;
14143     case d_mode:
14144     case dw_mode:
14145     case db_mode:
14146       names = names32;
14147       break;
14148     case q_mode:
14149       names = names64;
14150       break;
14151     case m_mode:
14152     case v_bnd_mode:
14153       names = address_mode == mode_64bit ? names64 : names32;
14154       break;
14155     case bnd_mode:
14156     case bnd_swap_mode:
14157       if (reg > 0x3)
14158         {
14159           oappend ("(bad)");
14160           return;
14161         }
14162       names = names_bnd;
14163       break;
14164     case indir_v_mode:
14165       if (address_mode == mode_64bit && isa64 == intel64)
14166         {
14167           names = names64;
14168           break;
14169         }
14170       /* Fall through.  */
14171     case stack_v_mode:
14172       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
14173         {
14174           names = names64;
14175           break;
14176         }
14177       bytemode = v_mode;
14178       /* Fall through.  */
14179     case v_mode:
14180     case v_swap_mode:
14181     case dq_mode:
14182     case dqb_mode:
14183     case dqd_mode:
14184     case dqw_mode:
14185       USED_REX (REX_W);
14186       if (rex & REX_W)
14187         names = names64;
14188       else
14189         {
14190           if ((sizeflag & DFLAG)
14191               || (bytemode != v_mode
14192                   && bytemode != v_swap_mode))
14193             names = names32;
14194           else
14195             names = names16;
14196           used_prefixes |= (prefixes & PREFIX_DATA);
14197         }
14198       break;
14199     case movsxd_mode:
14200       if (!(sizeflag & DFLAG) && isa64 == intel64)
14201         names = names16;
14202       else
14203         names = names32;
14204       used_prefixes |= (prefixes & PREFIX_DATA);
14205       break;
14206     case va_mode:
14207       names = (address_mode == mode_64bit
14208                ? names64 : names32);
14209       if (!(prefixes & PREFIX_ADDR))
14210         names = (address_mode == mode_16bit
14211                      ? names16 : names);
14212       else
14213         {
14214           /* Remove "addr16/addr32".  */
14215           all_prefixes[last_addr_prefix] = 0;
14216           names = (address_mode != mode_32bit
14217                        ? names32 : names16);
14218           used_prefixes |= PREFIX_ADDR;
14219         }
14220       break;
14221     case mask_bd_mode:
14222     case mask_mode:
14223       if (reg > 0x7)
14224         {
14225           oappend ("(bad)");
14226           return;
14227         }
14228       names = names_mask;
14229       break;
14230     case 0:
14231       return;
14232     default:
14233       oappend (INTERNAL_DISASSEMBLER_ERROR);
14234       return;
14235     }
14236   oappend (names[reg]);
14237 }
14238
14239 static void
14240 OP_E_memory (int bytemode, int sizeflag)
14241 {
14242   bfd_vma disp = 0;
14243   int add = (rex & REX_B) ? 8 : 0;
14244   int riprel = 0;
14245   int shift;
14246
14247   if (vex.evex)
14248     {
14249       /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0.  */
14250       if (vex.b
14251           && bytemode != x_mode
14252           && bytemode != xmmq_mode
14253           && bytemode != evex_half_bcst_xmmq_mode)
14254         {
14255           BadOp ();
14256           return;
14257         }
14258       switch (bytemode)
14259         {
14260         case dqw_mode:
14261         case dw_mode:
14262           shift = 1;
14263           break;
14264         case dqb_mode:
14265         case db_mode:
14266           shift = 0;
14267           break;
14268         case dq_mode:
14269           if (address_mode != mode_64bit)
14270             {
14271               shift = 2;
14272               break;
14273             }
14274             /* fall through */
14275         case vex_scalar_w_dq_mode:
14276         case vex_vsib_d_w_dq_mode:
14277         case vex_vsib_d_w_d_mode:
14278         case vex_vsib_q_w_dq_mode:
14279         case vex_vsib_q_w_d_mode:
14280         case evex_x_gscat_mode:
14281           shift = vex.w ? 3 : 2;
14282           break;
14283         case x_mode:
14284         case evex_half_bcst_xmmq_mode:
14285         case xmmq_mode:
14286           if (vex.b)
14287             {
14288               shift = vex.w ? 3 : 2;
14289               break;
14290             }
14291           /* Fall through.  */
14292         case xmmqd_mode:
14293         case xmmdw_mode:
14294         case ymmq_mode:
14295         case evex_x_nobcst_mode:
14296         case x_swap_mode:
14297           switch (vex.length)
14298             {
14299             case 128:
14300               shift = 4;
14301               break;
14302             case 256:
14303               shift = 5;
14304               break;
14305             case 512:
14306               shift = 6;
14307               break;
14308             default:
14309               abort ();
14310             }
14311           break;
14312         case ymm_mode:
14313           shift = 5;
14314           break;
14315         case xmm_mode:
14316           shift = 4;
14317           break;
14318         case xmm_mq_mode:
14319         case q_mode:
14320         case q_swap_mode:
14321         case q_scalar_swap_mode:
14322           shift = 3;
14323           break;
14324         case dqd_mode:
14325         case xmm_md_mode:
14326         case d_mode:
14327         case d_swap_mode:
14328         case d_scalar_swap_mode:
14329           shift = 2;
14330           break;
14331         case w_scalar_mode:
14332         case xmm_mw_mode:
14333           shift = 1;
14334           break;
14335         case b_scalar_mode:
14336         case xmm_mb_mode:
14337           shift = 0;
14338           break;
14339         default:
14340           abort ();
14341         }
14342       /* Make necessary corrections to shift for modes that need it.
14343          For these modes we currently have shift 4, 5 or 6 depending on
14344          vex.length (it corresponds to xmmword, ymmword or zmmword
14345          operand).  We might want to make it 3, 4 or 5 (e.g. for
14346          xmmq_mode).  In case of broadcast enabled the corrections
14347          aren't needed, as element size is always 32 or 64 bits.  */
14348       if (!vex.b
14349           && (bytemode == xmmq_mode
14350               || bytemode == evex_half_bcst_xmmq_mode))
14351         shift -= 1;
14352       else if (bytemode == xmmqd_mode)
14353         shift -= 2;
14354       else if (bytemode == xmmdw_mode)
14355         shift -= 3;
14356       else if (bytemode == ymmq_mode && vex.length == 128)
14357         shift -= 1;
14358     }
14359   else
14360     shift = 0;
14361
14362   USED_REX (REX_B);
14363   if (intel_syntax)
14364     intel_operand_size (bytemode, sizeflag);
14365   append_seg ();
14366
14367   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
14368     {
14369       /* 32/64 bit address mode */
14370       int havedisp;
14371       int havesib;
14372       int havebase;
14373       int haveindex;
14374       int needindex;
14375       int needaddr32;
14376       int base, rbase;
14377       int vindex = 0;
14378       int scale = 0;
14379       int addr32flag = !((sizeflag & AFLAG)
14380                          || bytemode == v_bnd_mode
14381                          || bytemode == v_bndmk_mode
14382                          || bytemode == bnd_mode
14383                          || bytemode == bnd_swap_mode);
14384       const char **indexes64 = names64;
14385       const char **indexes32 = names32;
14386
14387       havesib = 0;
14388       havebase = 1;
14389       haveindex = 0;
14390       base = modrm.rm;
14391
14392       if (base == 4)
14393         {
14394           havesib = 1;
14395           vindex = sib.index;
14396           USED_REX (REX_X);
14397           if (rex & REX_X)
14398             vindex += 8;
14399           switch (bytemode)
14400             {
14401             case vex_vsib_d_w_dq_mode:
14402             case vex_vsib_d_w_d_mode:
14403             case vex_vsib_q_w_dq_mode:
14404             case vex_vsib_q_w_d_mode:
14405               if (!need_vex)
14406                 abort ();
14407               if (vex.evex)
14408                 {
14409                   if (!vex.v)
14410                     vindex += 16;
14411                 }
14412
14413               haveindex = 1;
14414               switch (vex.length)
14415                 {
14416                 case 128:
14417                   indexes64 = indexes32 = names_xmm;
14418                   break;
14419                 case 256:
14420                   if (!vex.w
14421                       || bytemode == vex_vsib_q_w_dq_mode
14422                       || bytemode == vex_vsib_q_w_d_mode)
14423                     indexes64 = indexes32 = names_ymm;
14424                   else
14425                     indexes64 = indexes32 = names_xmm;
14426                   break;
14427                 case 512:
14428                   if (!vex.w
14429                       || bytemode == vex_vsib_q_w_dq_mode
14430                       || bytemode == vex_vsib_q_w_d_mode)
14431                     indexes64 = indexes32 = names_zmm;
14432                   else
14433                     indexes64 = indexes32 = names_ymm;
14434                   break;
14435                 default:
14436                   abort ();
14437                 }
14438               break;
14439             default:
14440               haveindex = vindex != 4;
14441               break;
14442             }
14443           scale = sib.scale;
14444           base = sib.base;
14445           codep++;
14446         }
14447       rbase = base + add;
14448
14449       switch (modrm.mod)
14450         {
14451         case 0:
14452           if (base == 5)
14453             {
14454               havebase = 0;
14455               if (address_mode == mode_64bit && !havesib)
14456                 riprel = 1;
14457               disp = get32s ();
14458               if (riprel && bytemode == v_bndmk_mode)
14459                 {
14460                   oappend ("(bad)");
14461                   return;
14462                 }
14463             }
14464           break;
14465         case 1:
14466           FETCH_DATA (the_info, codep + 1);
14467           disp = *codep++;
14468           if ((disp & 0x80) != 0)
14469             disp -= 0x100;
14470           if (vex.evex && shift > 0)
14471             disp <<= shift;
14472           break;
14473         case 2:
14474           disp = get32s ();
14475           break;
14476         }
14477
14478       needindex = 0;
14479       needaddr32 = 0;
14480       if (havesib
14481           && !havebase
14482           && !haveindex
14483           && address_mode != mode_16bit)
14484         {
14485           if (address_mode == mode_64bit)
14486             {
14487               /* Display eiz instead of addr32.  */
14488               needindex = addr32flag;
14489               needaddr32 = 1;
14490             }
14491           else
14492             {
14493               /* In 32-bit mode, we need index register to tell [offset]
14494                  from [eiz*1 + offset].  */
14495               needindex = 1;
14496             }
14497         }
14498
14499       havedisp = (havebase
14500                   || needindex
14501                   || (havesib && (haveindex || scale != 0)));
14502
14503       if (!intel_syntax)
14504         if (modrm.mod != 0 || base == 5)
14505           {
14506             if (havedisp || riprel)
14507               print_displacement (scratchbuf, disp);
14508             else
14509               print_operand_value (scratchbuf, 1, disp);
14510             oappend (scratchbuf);
14511             if (riprel)
14512               {
14513                 set_op (disp, 1);
14514                 oappend (!addr32flag ? "(%rip)" : "(%eip)");
14515               }
14516           }
14517
14518       if ((havebase || haveindex || needindex || needaddr32 || riprel)
14519           && (address_mode != mode_64bit
14520               || ((bytemode != v_bnd_mode)
14521                   && (bytemode != v_bndmk_mode)
14522                   && (bytemode != bnd_mode)
14523                   && (bytemode != bnd_swap_mode))))
14524         used_prefixes |= PREFIX_ADDR;
14525
14526       if (havedisp || (intel_syntax && riprel))
14527         {
14528           *obufp++ = open_char;
14529           if (intel_syntax && riprel)
14530             {
14531               set_op (disp, 1);
14532               oappend (!addr32flag ? "rip" : "eip");
14533             }
14534           *obufp = '\0';
14535           if (havebase)
14536             oappend (address_mode == mode_64bit && !addr32flag
14537                      ? names64[rbase] : names32[rbase]);
14538           if (havesib)
14539             {
14540               /* ESP/RSP won't allow index.  If base isn't ESP/RSP,
14541                  print index to tell base + index from base.  */
14542               if (scale != 0
14543                   || needindex
14544                   || haveindex
14545                   || (havebase && base != ESP_REG_NUM))
14546                 {
14547                   if (!intel_syntax || havebase)
14548                     {
14549                       *obufp++ = separator_char;
14550                       *obufp = '\0';
14551                     }
14552                   if (haveindex)
14553                     oappend (address_mode == mode_64bit && !addr32flag
14554                              ? indexes64[vindex] : indexes32[vindex]);
14555                   else
14556                     oappend (address_mode == mode_64bit && !addr32flag
14557                              ? index64 : index32);
14558
14559                   *obufp++ = scale_char;
14560                   *obufp = '\0';
14561                   sprintf (scratchbuf, "%d", 1 << scale);
14562                   oappend (scratchbuf);
14563                 }
14564             }
14565           if (intel_syntax
14566               && (disp || modrm.mod != 0 || base == 5))
14567             {
14568               if (!havedisp || (bfd_signed_vma) disp >= 0)
14569                 {
14570                   *obufp++ = '+';
14571                   *obufp = '\0';
14572                 }
14573               else if (modrm.mod != 1 && disp != -disp)
14574                 {
14575                   *obufp++ = '-';
14576                   *obufp = '\0';
14577                   disp = - (bfd_signed_vma) disp;
14578                 }
14579
14580               if (havedisp)
14581                 print_displacement (scratchbuf, disp);
14582               else
14583                 print_operand_value (scratchbuf, 1, disp);
14584               oappend (scratchbuf);
14585             }
14586
14587           *obufp++ = close_char;
14588           *obufp = '\0';
14589         }
14590       else if (intel_syntax)
14591         {
14592           if (modrm.mod != 0 || base == 5)
14593             {
14594               if (!active_seg_prefix)
14595                 {
14596                   oappend (names_seg[ds_reg - es_reg]);
14597                   oappend (":");
14598                 }
14599               print_operand_value (scratchbuf, 1, disp);
14600               oappend (scratchbuf);
14601             }
14602         }
14603     }
14604   else if (bytemode == v_bnd_mode
14605            || bytemode == v_bndmk_mode
14606            || bytemode == bnd_mode
14607            || bytemode == bnd_swap_mode)
14608     {
14609       oappend ("(bad)");
14610       return;
14611     }
14612   else
14613     {
14614       /* 16 bit address mode */
14615       used_prefixes |= prefixes & PREFIX_ADDR;
14616       switch (modrm.mod)
14617         {
14618         case 0:
14619           if (modrm.rm == 6)
14620             {
14621               disp = get16 ();
14622               if ((disp & 0x8000) != 0)
14623                 disp -= 0x10000;
14624             }
14625           break;
14626         case 1:
14627           FETCH_DATA (the_info, codep + 1);
14628           disp = *codep++;
14629           if ((disp & 0x80) != 0)
14630             disp -= 0x100;
14631           if (vex.evex && shift > 0)
14632             disp <<= shift;
14633           break;
14634         case 2:
14635           disp = get16 ();
14636           if ((disp & 0x8000) != 0)
14637             disp -= 0x10000;
14638           break;
14639         }
14640
14641       if (!intel_syntax)
14642         if (modrm.mod != 0 || modrm.rm == 6)
14643           {
14644             print_displacement (scratchbuf, disp);
14645             oappend (scratchbuf);
14646           }
14647
14648       if (modrm.mod != 0 || modrm.rm != 6)
14649         {
14650           *obufp++ = open_char;
14651           *obufp = '\0';
14652           oappend (index16[modrm.rm]);
14653           if (intel_syntax
14654               && (disp || modrm.mod != 0 || modrm.rm == 6))
14655             {
14656               if ((bfd_signed_vma) disp >= 0)
14657                 {
14658                   *obufp++ = '+';
14659                   *obufp = '\0';
14660                 }
14661               else if (modrm.mod != 1)
14662                 {
14663                   *obufp++ = '-';
14664                   *obufp = '\0';
14665                   disp = - (bfd_signed_vma) disp;
14666                 }
14667
14668               print_displacement (scratchbuf, disp);
14669               oappend (scratchbuf);
14670             }
14671
14672           *obufp++ = close_char;
14673           *obufp = '\0';
14674         }
14675       else if (intel_syntax)
14676         {
14677           if (!active_seg_prefix)
14678             {
14679               oappend (names_seg[ds_reg - es_reg]);
14680               oappend (":");
14681             }
14682           print_operand_value (scratchbuf, 1, disp & 0xffff);
14683           oappend (scratchbuf);
14684         }
14685     }
14686   if (vex.evex && vex.b
14687       && (bytemode == x_mode
14688           || bytemode == xmmq_mode
14689           || bytemode == evex_half_bcst_xmmq_mode))
14690     {
14691       if (vex.w
14692           || bytemode == xmmq_mode
14693           || bytemode == evex_half_bcst_xmmq_mode)
14694         {
14695           switch (vex.length)
14696             {
14697             case 128:
14698               oappend ("{1to2}");
14699               break;
14700             case 256:
14701               oappend ("{1to4}");
14702               break;
14703             case 512:
14704               oappend ("{1to8}");
14705               break;
14706             default:
14707               abort ();
14708             }
14709         }
14710       else
14711         {
14712           switch (vex.length)
14713             {
14714             case 128:
14715               oappend ("{1to4}");
14716               break;
14717             case 256:
14718               oappend ("{1to8}");
14719               break;
14720             case 512:
14721               oappend ("{1to16}");
14722               break;
14723             default:
14724               abort ();
14725             }
14726         }
14727     }
14728 }
14729
14730 static void
14731 OP_E (int bytemode, int sizeflag)
14732 {
14733   /* Skip mod/rm byte.  */
14734   MODRM_CHECK;
14735   codep++;
14736
14737   if (modrm.mod == 3)
14738     OP_E_register (bytemode, sizeflag);
14739   else
14740     OP_E_memory (bytemode, sizeflag);
14741 }
14742
14743 static void
14744 OP_G (int bytemode, int sizeflag)
14745 {
14746   int add = 0;
14747   const char **names;
14748   USED_REX (REX_R);
14749   if (rex & REX_R)
14750     add += 8;
14751   switch (bytemode)
14752     {
14753     case b_mode:
14754       USED_REX (0);
14755       if (rex)
14756         oappend (names8rex[modrm.reg + add]);
14757       else
14758         oappend (names8[modrm.reg + add]);
14759       break;
14760     case w_mode:
14761       oappend (names16[modrm.reg + add]);
14762       break;
14763     case d_mode:
14764     case db_mode:
14765     case dw_mode:
14766       oappend (names32[modrm.reg + add]);
14767       break;
14768     case q_mode:
14769       oappend (names64[modrm.reg + add]);
14770       break;
14771     case bnd_mode:
14772       if (modrm.reg > 0x3)
14773         {
14774           oappend ("(bad)");
14775           return;
14776         }
14777       oappend (names_bnd[modrm.reg]);
14778       break;
14779     case v_mode:
14780     case dq_mode:
14781     case dqb_mode:
14782     case dqd_mode:
14783     case dqw_mode:
14784     case movsxd_mode:
14785       USED_REX (REX_W);
14786       if (rex & REX_W)
14787         oappend (names64[modrm.reg + add]);
14788       else
14789         {
14790           if ((sizeflag & DFLAG)
14791               || (bytemode != v_mode && bytemode != movsxd_mode))
14792             oappend (names32[modrm.reg + add]);
14793           else
14794             oappend (names16[modrm.reg + add]);
14795           used_prefixes |= (prefixes & PREFIX_DATA);
14796         }
14797       break;
14798     case va_mode:
14799       names = (address_mode == mode_64bit
14800                ? names64 : names32);
14801       if (!(prefixes & PREFIX_ADDR))
14802         {
14803           if (address_mode == mode_16bit)
14804             names = names16;
14805         }
14806       else
14807         {
14808           /* Remove "addr16/addr32".  */
14809           all_prefixes[last_addr_prefix] = 0;
14810           names = (address_mode != mode_32bit
14811                        ? names32 : names16);
14812           used_prefixes |= PREFIX_ADDR;
14813         }
14814       oappend (names[modrm.reg + add]);
14815       break;
14816     case m_mode:
14817       if (address_mode == mode_64bit)
14818         oappend (names64[modrm.reg + add]);
14819       else
14820         oappend (names32[modrm.reg + add]);
14821       break;
14822     case mask_bd_mode:
14823     case mask_mode:
14824       if ((modrm.reg + add) > 0x7)
14825         {
14826           oappend ("(bad)");
14827           return;
14828         }
14829       oappend (names_mask[modrm.reg + add]);
14830       break;
14831     default:
14832       oappend (INTERNAL_DISASSEMBLER_ERROR);
14833       break;
14834     }
14835 }
14836
14837 static bfd_vma
14838 get64 (void)
14839 {
14840   bfd_vma x;
14841 #ifdef BFD64
14842   unsigned int a;
14843   unsigned int b;
14844
14845   FETCH_DATA (the_info, codep + 8);
14846   a = *codep++ & 0xff;
14847   a |= (*codep++ & 0xff) << 8;
14848   a |= (*codep++ & 0xff) << 16;
14849   a |= (*codep++ & 0xffu) << 24;
14850   b = *codep++ & 0xff;
14851   b |= (*codep++ & 0xff) << 8;
14852   b |= (*codep++ & 0xff) << 16;
14853   b |= (*codep++ & 0xffu) << 24;
14854   x = a + ((bfd_vma) b << 32);
14855 #else
14856   abort ();
14857   x = 0;
14858 #endif
14859   return x;
14860 }
14861
14862 static bfd_signed_vma
14863 get32 (void)
14864 {
14865   bfd_signed_vma x = 0;
14866
14867   FETCH_DATA (the_info, codep + 4);
14868   x = *codep++ & (bfd_signed_vma) 0xff;
14869   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
14870   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
14871   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
14872   return x;
14873 }
14874
14875 static bfd_signed_vma
14876 get32s (void)
14877 {
14878   bfd_signed_vma x = 0;
14879
14880   FETCH_DATA (the_info, codep + 4);
14881   x = *codep++ & (bfd_signed_vma) 0xff;
14882   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
14883   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
14884   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
14885
14886   x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
14887
14888   return x;
14889 }
14890
14891 static int
14892 get16 (void)
14893 {
14894   int x = 0;
14895
14896   FETCH_DATA (the_info, codep + 2);
14897   x = *codep++ & 0xff;
14898   x |= (*codep++ & 0xff) << 8;
14899   return x;
14900 }
14901
14902 static void
14903 set_op (bfd_vma op, int riprel)
14904 {
14905   op_index[op_ad] = op_ad;
14906   if (address_mode == mode_64bit)
14907     {
14908       op_address[op_ad] = op;
14909       op_riprel[op_ad] = riprel;
14910     }
14911   else
14912     {
14913       /* Mask to get a 32-bit address.  */
14914       op_address[op_ad] = op & 0xffffffff;
14915       op_riprel[op_ad] = riprel & 0xffffffff;
14916     }
14917 }
14918
14919 static void
14920 OP_REG (int code, int sizeflag)
14921 {
14922   const char *s;
14923   int add;
14924
14925   switch (code)
14926     {
14927     case es_reg: case ss_reg: case cs_reg:
14928     case ds_reg: case fs_reg: case gs_reg:
14929       oappend (names_seg[code - es_reg]);
14930       return;
14931     }
14932
14933   USED_REX (REX_B);
14934   if (rex & REX_B)
14935     add = 8;
14936   else
14937     add = 0;
14938
14939   switch (code)
14940     {
14941     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
14942     case sp_reg: case bp_reg: case si_reg: case di_reg:
14943       s = names16[code - ax_reg + add];
14944       break;
14945     case al_reg: case ah_reg: case cl_reg: case ch_reg:
14946     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
14947       USED_REX (0);
14948       if (rex)
14949         s = names8rex[code - al_reg + add];
14950       else
14951         s = names8[code - al_reg];
14952       break;
14953     case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
14954     case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
14955       if (address_mode == mode_64bit
14956           && ((sizeflag & DFLAG) || (rex & REX_W)))
14957         {
14958           s = names64[code - rAX_reg + add];
14959           break;
14960         }
14961       code += eAX_reg - rAX_reg;
14962       /* Fall through.  */
14963     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
14964     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
14965       USED_REX (REX_W);
14966       if (rex & REX_W)
14967         s = names64[code - eAX_reg + add];
14968       else
14969         {
14970           if (sizeflag & DFLAG)
14971             s = names32[code - eAX_reg + add];
14972           else
14973             s = names16[code - eAX_reg + add];
14974           used_prefixes |= (prefixes & PREFIX_DATA);
14975         }
14976       break;
14977     default:
14978       s = INTERNAL_DISASSEMBLER_ERROR;
14979       break;
14980     }
14981   oappend (s);
14982 }
14983
14984 static void
14985 OP_IMREG (int code, int sizeflag)
14986 {
14987   const char *s;
14988
14989   switch (code)
14990     {
14991     case indir_dx_reg:
14992       if (intel_syntax)
14993         s = "dx";
14994       else
14995         s = "(%dx)";
14996       break;
14997     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
14998     case sp_reg: case bp_reg: case si_reg: case di_reg:
14999       s = names16[code - ax_reg];
15000       break;
15001     case es_reg: case ss_reg: case cs_reg:
15002     case ds_reg: case fs_reg: case gs_reg:
15003       s = names_seg[code - es_reg];
15004       break;
15005     case al_reg: case ah_reg: case cl_reg: case ch_reg:
15006     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
15007       USED_REX (0);
15008       if (rex)
15009         s = names8rex[code - al_reg];
15010       else
15011         s = names8[code - al_reg];
15012       break;
15013     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
15014     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
15015       USED_REX (REX_W);
15016       if (rex & REX_W)
15017         s = names64[code - eAX_reg];
15018       else
15019         {
15020           if (sizeflag & DFLAG)
15021             s = names32[code - eAX_reg];
15022           else
15023             s = names16[code - eAX_reg];
15024           used_prefixes |= (prefixes & PREFIX_DATA);
15025         }
15026       break;
15027     case z_mode_ax_reg:
15028       if ((rex & REX_W) || (sizeflag & DFLAG))
15029         s = *names32;
15030       else
15031         s = *names16;
15032       if (!(rex & REX_W))
15033         used_prefixes |= (prefixes & PREFIX_DATA);
15034       break;
15035     default:
15036       s = INTERNAL_DISASSEMBLER_ERROR;
15037       break;
15038     }
15039   oappend (s);
15040 }
15041
15042 static void
15043 OP_I (int bytemode, int sizeflag)
15044 {
15045   bfd_signed_vma op;
15046   bfd_signed_vma mask = -1;
15047
15048   switch (bytemode)
15049     {
15050     case b_mode:
15051       FETCH_DATA (the_info, codep + 1);
15052       op = *codep++;
15053       mask = 0xff;
15054       break;
15055     case v_mode:
15056       USED_REX (REX_W);
15057       if (rex & REX_W)
15058         op = get32s ();
15059       else
15060         {
15061           if (sizeflag & DFLAG)
15062             {
15063               op = get32 ();
15064               mask = 0xffffffff;
15065             }
15066           else
15067             {
15068               op = get16 ();
15069               mask = 0xfffff;
15070             }
15071           used_prefixes |= (prefixes & PREFIX_DATA);
15072         }
15073       break;
15074     case d_mode:
15075       mask = 0xffffffff;
15076       op = get32 ();
15077       break;
15078     case w_mode:
15079       mask = 0xfffff;
15080       op = get16 ();
15081       break;
15082     case const_1_mode:
15083       if (intel_syntax)
15084         oappend ("1");
15085       return;
15086     default:
15087       oappend (INTERNAL_DISASSEMBLER_ERROR);
15088       return;
15089     }
15090
15091   op &= mask;
15092   scratchbuf[0] = '$';
15093   print_operand_value (scratchbuf + 1, 1, op);
15094   oappend_maybe_intel (scratchbuf);
15095   scratchbuf[0] = '\0';
15096 }
15097
15098 static void
15099 OP_I64 (int bytemode, int sizeflag)
15100 {
15101   if (bytemode != v_mode || address_mode != mode_64bit || !(rex & REX_W))
15102     {
15103       OP_I (bytemode, sizeflag);
15104       return;
15105     }
15106
15107   USED_REX (REX_W);
15108
15109   scratchbuf[0] = '$';
15110   print_operand_value (scratchbuf + 1, 1, get64 ());
15111   oappend_maybe_intel (scratchbuf);
15112   scratchbuf[0] = '\0';
15113 }
15114
15115 static void
15116 OP_sI (int bytemode, int sizeflag)
15117 {
15118   bfd_signed_vma op;
15119
15120   switch (bytemode)
15121     {
15122     case b_mode:
15123     case b_T_mode:
15124       FETCH_DATA (the_info, codep + 1);
15125       op = *codep++;
15126       if ((op & 0x80) != 0)
15127         op -= 0x100;
15128       if (bytemode == b_T_mode)
15129         {
15130           if (address_mode != mode_64bit
15131               || !((sizeflag & DFLAG) || (rex & REX_W)))
15132             {
15133               /* The operand-size prefix is overridden by a REX prefix.  */
15134               if ((sizeflag & DFLAG) || (rex & REX_W))
15135                 op &= 0xffffffff;
15136               else
15137                 op &= 0xffff;
15138           }
15139         }
15140       else
15141         {
15142           if (!(rex & REX_W))
15143             {
15144               if (sizeflag & DFLAG)
15145                 op &= 0xffffffff;
15146               else
15147                 op &= 0xffff;
15148             }
15149         }
15150       break;
15151     case v_mode:
15152       /* The operand-size prefix is overridden by a REX prefix.  */
15153       if ((sizeflag & DFLAG) || (rex & REX_W))
15154         op = get32s ();
15155       else
15156         op = get16 ();
15157       break;
15158     default:
15159       oappend (INTERNAL_DISASSEMBLER_ERROR);
15160       return;
15161     }
15162
15163   scratchbuf[0] = '$';
15164   print_operand_value (scratchbuf + 1, 1, op);
15165   oappend_maybe_intel (scratchbuf);
15166 }
15167
15168 static void
15169 OP_J (int bytemode, int sizeflag)
15170 {
15171   bfd_vma disp;
15172   bfd_vma mask = -1;
15173   bfd_vma segment = 0;
15174
15175   switch (bytemode)
15176     {
15177     case b_mode:
15178       FETCH_DATA (the_info, codep + 1);
15179       disp = *codep++;
15180       if ((disp & 0x80) != 0)
15181         disp -= 0x100;
15182       break;
15183     case v_mode:
15184       if (isa64 != intel64)
15185     case dqw_mode:
15186         USED_REX (REX_W);
15187       if ((sizeflag & DFLAG)
15188           || (address_mode == mode_64bit
15189               && ((isa64 == intel64 && bytemode != dqw_mode)
15190                   || (rex & REX_W))))
15191         disp = get32s ();
15192       else
15193         {
15194           disp = get16 ();
15195           if ((disp & 0x8000) != 0)
15196             disp -= 0x10000;
15197           /* In 16bit mode, address is wrapped around at 64k within
15198              the same segment.  Otherwise, a data16 prefix on a jump
15199              instruction means that the pc is masked to 16 bits after
15200              the displacement is added!  */
15201           mask = 0xffff;
15202           if ((prefixes & PREFIX_DATA) == 0)
15203             segment = ((start_pc + (codep - start_codep))
15204                        & ~((bfd_vma) 0xffff));
15205         }
15206       if (address_mode != mode_64bit
15207           || (isa64 != intel64 && !(rex & REX_W)))
15208         used_prefixes |= (prefixes & PREFIX_DATA);
15209       break;
15210     default:
15211       oappend (INTERNAL_DISASSEMBLER_ERROR);
15212       return;
15213     }
15214   disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment;
15215   set_op (disp, 0);
15216   print_operand_value (scratchbuf, 1, disp);
15217   oappend (scratchbuf);
15218 }
15219
15220 static void
15221 OP_SEG (int bytemode, int sizeflag)
15222 {
15223   if (bytemode == w_mode)
15224     oappend (names_seg[modrm.reg]);
15225   else
15226     OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
15227 }
15228
15229 static void
15230 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
15231 {
15232   int seg, offset;
15233
15234   if (sizeflag & DFLAG)
15235     {
15236       offset = get32 ();
15237       seg = get16 ();
15238     }
15239   else
15240     {
15241       offset = get16 ();
15242       seg = get16 ();
15243     }
15244   used_prefixes |= (prefixes & PREFIX_DATA);
15245   if (intel_syntax)
15246     sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
15247   else
15248     sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
15249   oappend (scratchbuf);
15250 }
15251
15252 static void
15253 OP_OFF (int bytemode, int sizeflag)
15254 {
15255   bfd_vma off;
15256
15257   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
15258     intel_operand_size (bytemode, sizeflag);
15259   append_seg ();
15260
15261   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
15262     off = get32 ();
15263   else
15264     off = get16 ();
15265
15266   if (intel_syntax)
15267     {
15268       if (!active_seg_prefix)
15269         {
15270           oappend (names_seg[ds_reg - es_reg]);
15271           oappend (":");
15272         }
15273     }
15274   print_operand_value (scratchbuf, 1, off);
15275   oappend (scratchbuf);
15276 }
15277
15278 static void
15279 OP_OFF64 (int bytemode, int sizeflag)
15280 {
15281   bfd_vma off;
15282
15283   if (address_mode != mode_64bit
15284       || (prefixes & PREFIX_ADDR))
15285     {
15286       OP_OFF (bytemode, sizeflag);
15287       return;
15288     }
15289
15290   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
15291     intel_operand_size (bytemode, sizeflag);
15292   append_seg ();
15293
15294   off = get64 ();
15295
15296   if (intel_syntax)
15297     {
15298       if (!active_seg_prefix)
15299         {
15300           oappend (names_seg[ds_reg - es_reg]);
15301           oappend (":");
15302         }
15303     }
15304   print_operand_value (scratchbuf, 1, off);
15305   oappend (scratchbuf);
15306 }
15307
15308 static void
15309 ptr_reg (int code, int sizeflag)
15310 {
15311   const char *s;
15312
15313   *obufp++ = open_char;
15314   used_prefixes |= (prefixes & PREFIX_ADDR);
15315   if (address_mode == mode_64bit)
15316     {
15317       if (!(sizeflag & AFLAG))
15318         s = names32[code - eAX_reg];
15319       else
15320         s = names64[code - eAX_reg];
15321     }
15322   else if (sizeflag & AFLAG)
15323     s = names32[code - eAX_reg];
15324   else
15325     s = names16[code - eAX_reg];
15326   oappend (s);
15327   *obufp++ = close_char;
15328   *obufp = 0;
15329 }
15330
15331 static void
15332 OP_ESreg (int code, int sizeflag)
15333 {
15334   if (intel_syntax)
15335     {
15336       switch (codep[-1])
15337         {
15338         case 0x6d:      /* insw/insl */
15339           intel_operand_size (z_mode, sizeflag);
15340           break;
15341         case 0xa5:      /* movsw/movsl/movsq */
15342         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
15343         case 0xab:      /* stosw/stosl */
15344         case 0xaf:      /* scasw/scasl */
15345           intel_operand_size (v_mode, sizeflag);
15346           break;
15347         default:
15348           intel_operand_size (b_mode, sizeflag);
15349         }
15350     }
15351   oappend_maybe_intel ("%es:");
15352   ptr_reg (code, sizeflag);
15353 }
15354
15355 static void
15356 OP_DSreg (int code, int sizeflag)
15357 {
15358   if (intel_syntax)
15359     {
15360       switch (codep[-1])
15361         {
15362         case 0x6f:      /* outsw/outsl */
15363           intel_operand_size (z_mode, sizeflag);
15364           break;
15365         case 0xa5:      /* movsw/movsl/movsq */
15366         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
15367         case 0xad:      /* lodsw/lodsl/lodsq */
15368           intel_operand_size (v_mode, sizeflag);
15369           break;
15370         default:
15371           intel_operand_size (b_mode, sizeflag);
15372         }
15373     }
15374   /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
15375      default segment register DS is printed.  */
15376   if (!active_seg_prefix)
15377     active_seg_prefix = PREFIX_DS;
15378   append_seg ();
15379   ptr_reg (code, sizeflag);
15380 }
15381
15382 static void
15383 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15384 {
15385   int add;
15386   if (rex & REX_R)
15387     {
15388       USED_REX (REX_R);
15389       add = 8;
15390     }
15391   else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
15392     {
15393       all_prefixes[last_lock_prefix] = 0;
15394       used_prefixes |= PREFIX_LOCK;
15395       add = 8;
15396     }
15397   else
15398     add = 0;
15399   sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
15400   oappend_maybe_intel (scratchbuf);
15401 }
15402
15403 static void
15404 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15405 {
15406   int add;
15407   USED_REX (REX_R);
15408   if (rex & REX_R)
15409     add = 8;
15410   else
15411     add = 0;
15412   if (intel_syntax)
15413     sprintf (scratchbuf, "db%d", modrm.reg + add);
15414   else
15415     sprintf (scratchbuf, "%%db%d", modrm.reg + add);
15416   oappend (scratchbuf);
15417 }
15418
15419 static void
15420 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15421 {
15422   sprintf (scratchbuf, "%%tr%d", modrm.reg);
15423   oappend_maybe_intel (scratchbuf);
15424 }
15425
15426 static void
15427 OP_R (int bytemode, int sizeflag)
15428 {
15429   /* Skip mod/rm byte.  */
15430   MODRM_CHECK;
15431   codep++;
15432   OP_E_register (bytemode, sizeflag);
15433 }
15434
15435 static void
15436 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15437 {
15438   int reg = modrm.reg;
15439   const char **names;
15440
15441   used_prefixes |= (prefixes & PREFIX_DATA);
15442   if (prefixes & PREFIX_DATA)
15443     {
15444       names = names_xmm;
15445       USED_REX (REX_R);
15446       if (rex & REX_R)
15447         reg += 8;
15448     }
15449   else
15450     names = names_mm;
15451   oappend (names[reg]);
15452 }
15453
15454 static void
15455 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
15456 {
15457   int reg = modrm.reg;
15458   const char **names;
15459
15460   USED_REX (REX_R);
15461   if (rex & REX_R)
15462     reg += 8;
15463   if (vex.evex)
15464     {
15465       if (!vex.r)
15466         reg += 16;
15467     }
15468
15469   if (need_vex
15470       && bytemode != xmm_mode
15471       && bytemode != xmmq_mode
15472       && bytemode != evex_half_bcst_xmmq_mode
15473       && bytemode != ymm_mode
15474       && bytemode != scalar_mode)
15475     {
15476       switch (vex.length)
15477         {
15478         case 128:
15479           names = names_xmm;
15480           break;
15481         case 256:
15482           if (vex.w
15483               || (bytemode != vex_vsib_q_w_dq_mode
15484                   && bytemode != vex_vsib_q_w_d_mode))
15485             names = names_ymm;
15486           else
15487             names = names_xmm;
15488           break;
15489         case 512:
15490           names = names_zmm;
15491           break;
15492         default:
15493           abort ();
15494         }
15495     }
15496   else if (bytemode == xmmq_mode
15497            || bytemode == evex_half_bcst_xmmq_mode)
15498     {
15499       switch (vex.length)
15500         {
15501         case 128:
15502         case 256:
15503           names = names_xmm;
15504           break;
15505         case 512:
15506           names = names_ymm;
15507           break;
15508         default:
15509           abort ();
15510         }
15511     }
15512   else if (bytemode == ymm_mode)
15513     names = names_ymm;
15514   else
15515     names = names_xmm;
15516   oappend (names[reg]);
15517 }
15518
15519 static void
15520 OP_EM (int bytemode, int sizeflag)
15521 {
15522   int reg;
15523   const char **names;
15524
15525   if (modrm.mod != 3)
15526     {
15527       if (intel_syntax
15528           && (bytemode == v_mode || bytemode == v_swap_mode))
15529         {
15530           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
15531           used_prefixes |= (prefixes & PREFIX_DATA);
15532         }
15533       OP_E (bytemode, sizeflag);
15534       return;
15535     }
15536
15537   if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
15538     swap_operand ();
15539
15540   /* Skip mod/rm byte.  */
15541   MODRM_CHECK;
15542   codep++;
15543   used_prefixes |= (prefixes & PREFIX_DATA);
15544   reg = modrm.rm;
15545   if (prefixes & PREFIX_DATA)
15546     {
15547       names = names_xmm;
15548       USED_REX (REX_B);
15549       if (rex & REX_B)
15550         reg += 8;
15551     }
15552   else
15553     names = names_mm;
15554   oappend (names[reg]);
15555 }
15556
15557 /* cvt* are the only instructions in sse2 which have
15558    both SSE and MMX operands and also have 0x66 prefix
15559    in their opcode. 0x66 was originally used to differentiate
15560    between SSE and MMX instruction(operands). So we have to handle the
15561    cvt* separately using OP_EMC and OP_MXC */
15562 static void
15563 OP_EMC (int bytemode, int sizeflag)
15564 {
15565   if (modrm.mod != 3)
15566     {
15567       if (intel_syntax && bytemode == v_mode)
15568         {
15569           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
15570           used_prefixes |= (prefixes & PREFIX_DATA);
15571         }
15572       OP_E (bytemode, sizeflag);
15573       return;
15574     }
15575
15576   /* Skip mod/rm byte.  */
15577   MODRM_CHECK;
15578   codep++;
15579   used_prefixes |= (prefixes & PREFIX_DATA);
15580   oappend (names_mm[modrm.rm]);
15581 }
15582
15583 static void
15584 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15585 {
15586   used_prefixes |= (prefixes & PREFIX_DATA);
15587   oappend (names_mm[modrm.reg]);
15588 }
15589
15590 static void
15591 OP_EX (int bytemode, int sizeflag)
15592 {
15593   int reg;
15594   const char **names;
15595
15596   /* Skip mod/rm byte.  */
15597   MODRM_CHECK;
15598   codep++;
15599
15600   if (modrm.mod != 3)
15601     {
15602       OP_E_memory (bytemode, sizeflag);
15603       return;
15604     }
15605
15606   reg = modrm.rm;
15607   USED_REX (REX_B);
15608   if (rex & REX_B)
15609     reg += 8;
15610   if (vex.evex)
15611     {
15612       USED_REX (REX_X);
15613       if ((rex & REX_X))
15614         reg += 16;
15615     }
15616
15617   if ((sizeflag & SUFFIX_ALWAYS)
15618       && (bytemode == x_swap_mode
15619           || bytemode == d_swap_mode
15620           || bytemode == d_scalar_swap_mode
15621           || bytemode == q_swap_mode
15622           || bytemode == q_scalar_swap_mode))
15623     swap_operand ();
15624
15625   if (need_vex
15626       && bytemode != xmm_mode
15627       && bytemode != xmmdw_mode
15628       && bytemode != xmmqd_mode
15629       && bytemode != xmm_mb_mode
15630       && bytemode != xmm_mw_mode
15631       && bytemode != xmm_md_mode
15632       && bytemode != xmm_mq_mode
15633       && bytemode != xmmq_mode
15634       && bytemode != evex_half_bcst_xmmq_mode
15635       && bytemode != ymm_mode
15636       && bytemode != d_scalar_swap_mode
15637       && bytemode != q_scalar_swap_mode
15638       && bytemode != vex_scalar_w_dq_mode)
15639     {
15640       switch (vex.length)
15641         {
15642         case 128:
15643           names = names_xmm;
15644           break;
15645         case 256:
15646           names = names_ymm;
15647           break;
15648         case 512:
15649           names = names_zmm;
15650           break;
15651         default:
15652           abort ();
15653         }
15654     }
15655   else if (bytemode == xmmq_mode
15656            || bytemode == evex_half_bcst_xmmq_mode)
15657     {
15658       switch (vex.length)
15659         {
15660         case 128:
15661         case 256:
15662           names = names_xmm;
15663           break;
15664         case 512:
15665           names = names_ymm;
15666           break;
15667         default:
15668           abort ();
15669         }
15670     }
15671   else if (bytemode == ymm_mode)
15672     names = names_ymm;
15673   else
15674     names = names_xmm;
15675   oappend (names[reg]);
15676 }
15677
15678 static void
15679 OP_MS (int bytemode, int sizeflag)
15680 {
15681   if (modrm.mod == 3)
15682     OP_EM (bytemode, sizeflag);
15683   else
15684     BadOp ();
15685 }
15686
15687 static void
15688 OP_XS (int bytemode, int sizeflag)
15689 {
15690   if (modrm.mod == 3)
15691     OP_EX (bytemode, sizeflag);
15692   else
15693     BadOp ();
15694 }
15695
15696 static void
15697 OP_M (int bytemode, int sizeflag)
15698 {
15699   if (modrm.mod == 3)
15700     /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
15701     BadOp ();
15702   else
15703     OP_E (bytemode, sizeflag);
15704 }
15705
15706 static void
15707 OP_0f07 (int bytemode, int sizeflag)
15708 {
15709   if (modrm.mod != 3 || modrm.rm != 0)
15710     BadOp ();
15711   else
15712     OP_E (bytemode, sizeflag);
15713 }
15714
15715 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
15716    32bit mode and "xchg %rax,%rax" in 64bit mode.  */
15717
15718 static void
15719 NOP_Fixup1 (int bytemode, int sizeflag)
15720 {
15721   if ((prefixes & PREFIX_DATA) != 0
15722       || (rex != 0
15723           && rex != 0x48
15724           && address_mode == mode_64bit))
15725     OP_REG (bytemode, sizeflag);
15726   else
15727     strcpy (obuf, "nop");
15728 }
15729
15730 static void
15731 NOP_Fixup2 (int bytemode, int sizeflag)
15732 {
15733   if ((prefixes & PREFIX_DATA) != 0
15734       || (rex != 0
15735           && rex != 0x48
15736           && address_mode == mode_64bit))
15737     OP_IMREG (bytemode, sizeflag);
15738 }
15739
15740 static const char *const Suffix3DNow[] = {
15741 /* 00 */        NULL,           NULL,           NULL,           NULL,
15742 /* 04 */        NULL,           NULL,           NULL,           NULL,
15743 /* 08 */        NULL,           NULL,           NULL,           NULL,
15744 /* 0C */        "pi2fw",        "pi2fd",        NULL,           NULL,
15745 /* 10 */        NULL,           NULL,           NULL,           NULL,
15746 /* 14 */        NULL,           NULL,           NULL,           NULL,
15747 /* 18 */        NULL,           NULL,           NULL,           NULL,
15748 /* 1C */        "pf2iw",        "pf2id",        NULL,           NULL,
15749 /* 20 */        NULL,           NULL,           NULL,           NULL,
15750 /* 24 */        NULL,           NULL,           NULL,           NULL,
15751 /* 28 */        NULL,           NULL,           NULL,           NULL,
15752 /* 2C */        NULL,           NULL,           NULL,           NULL,
15753 /* 30 */        NULL,           NULL,           NULL,           NULL,
15754 /* 34 */        NULL,           NULL,           NULL,           NULL,
15755 /* 38 */        NULL,           NULL,           NULL,           NULL,
15756 /* 3C */        NULL,           NULL,           NULL,           NULL,
15757 /* 40 */        NULL,           NULL,           NULL,           NULL,
15758 /* 44 */        NULL,           NULL,           NULL,           NULL,
15759 /* 48 */        NULL,           NULL,           NULL,           NULL,
15760 /* 4C */        NULL,           NULL,           NULL,           NULL,
15761 /* 50 */        NULL,           NULL,           NULL,           NULL,
15762 /* 54 */        NULL,           NULL,           NULL,           NULL,
15763 /* 58 */        NULL,           NULL,           NULL,           NULL,
15764 /* 5C */        NULL,           NULL,           NULL,           NULL,
15765 /* 60 */        NULL,           NULL,           NULL,           NULL,
15766 /* 64 */        NULL,           NULL,           NULL,           NULL,
15767 /* 68 */        NULL,           NULL,           NULL,           NULL,
15768 /* 6C */        NULL,           NULL,           NULL,           NULL,
15769 /* 70 */        NULL,           NULL,           NULL,           NULL,
15770 /* 74 */        NULL,           NULL,           NULL,           NULL,
15771 /* 78 */        NULL,           NULL,           NULL,           NULL,
15772 /* 7C */        NULL,           NULL,           NULL,           NULL,
15773 /* 80 */        NULL,           NULL,           NULL,           NULL,
15774 /* 84 */        NULL,           NULL,           NULL,           NULL,
15775 /* 88 */        NULL,           NULL,           "pfnacc",       NULL,
15776 /* 8C */        NULL,           NULL,           "pfpnacc",      NULL,
15777 /* 90 */        "pfcmpge",      NULL,           NULL,           NULL,
15778 /* 94 */        "pfmin",        NULL,           "pfrcp",        "pfrsqrt",
15779 /* 98 */        NULL,           NULL,           "pfsub",        NULL,
15780 /* 9C */        NULL,           NULL,           "pfadd",        NULL,
15781 /* A0 */        "pfcmpgt",      NULL,           NULL,           NULL,
15782 /* A4 */        "pfmax",        NULL,           "pfrcpit1",     "pfrsqit1",
15783 /* A8 */        NULL,           NULL,           "pfsubr",       NULL,
15784 /* AC */        NULL,           NULL,           "pfacc",        NULL,
15785 /* B0 */        "pfcmpeq",      NULL,           NULL,           NULL,
15786 /* B4 */        "pfmul",        NULL,           "pfrcpit2",     "pmulhrw",
15787 /* B8 */        NULL,           NULL,           NULL,           "pswapd",
15788 /* BC */        NULL,           NULL,           NULL,           "pavgusb",
15789 /* C0 */        NULL,           NULL,           NULL,           NULL,
15790 /* C4 */        NULL,           NULL,           NULL,           NULL,
15791 /* C8 */        NULL,           NULL,           NULL,           NULL,
15792 /* CC */        NULL,           NULL,           NULL,           NULL,
15793 /* D0 */        NULL,           NULL,           NULL,           NULL,
15794 /* D4 */        NULL,           NULL,           NULL,           NULL,
15795 /* D8 */        NULL,           NULL,           NULL,           NULL,
15796 /* DC */        NULL,           NULL,           NULL,           NULL,
15797 /* E0 */        NULL,           NULL,           NULL,           NULL,
15798 /* E4 */        NULL,           NULL,           NULL,           NULL,
15799 /* E8 */        NULL,           NULL,           NULL,           NULL,
15800 /* EC */        NULL,           NULL,           NULL,           NULL,
15801 /* F0 */        NULL,           NULL,           NULL,           NULL,
15802 /* F4 */        NULL,           NULL,           NULL,           NULL,
15803 /* F8 */        NULL,           NULL,           NULL,           NULL,
15804 /* FC */        NULL,           NULL,           NULL,           NULL,
15805 };
15806
15807 static void
15808 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15809 {
15810   const char *mnemonic;
15811
15812   FETCH_DATA (the_info, codep + 1);
15813   /* AMD 3DNow! instructions are specified by an opcode suffix in the
15814      place where an 8-bit immediate would normally go.  ie. the last
15815      byte of the instruction.  */
15816   obufp = mnemonicendp;
15817   mnemonic = Suffix3DNow[*codep++ & 0xff];
15818   if (mnemonic)
15819     oappend (mnemonic);
15820   else
15821     {
15822       /* Since a variable sized modrm/sib chunk is between the start
15823          of the opcode (0x0f0f) and the opcode suffix, we need to do
15824          all the modrm processing first, and don't know until now that
15825          we have a bad opcode.  This necessitates some cleaning up.  */
15826       op_out[0][0] = '\0';
15827       op_out[1][0] = '\0';
15828       BadOp ();
15829     }
15830   mnemonicendp = obufp;
15831 }
15832
15833 static struct op simd_cmp_op[] =
15834 {
15835   { STRING_COMMA_LEN ("eq") },
15836   { STRING_COMMA_LEN ("lt") },
15837   { STRING_COMMA_LEN ("le") },
15838   { STRING_COMMA_LEN ("unord") },
15839   { STRING_COMMA_LEN ("neq") },
15840   { STRING_COMMA_LEN ("nlt") },
15841   { STRING_COMMA_LEN ("nle") },
15842   { STRING_COMMA_LEN ("ord") }
15843 };
15844
15845 static void
15846 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15847 {
15848   unsigned int cmp_type;
15849
15850   FETCH_DATA (the_info, codep + 1);
15851   cmp_type = *codep++ & 0xff;
15852   if (cmp_type < ARRAY_SIZE (simd_cmp_op))
15853     {
15854       char suffix [3];
15855       char *p = mnemonicendp - 2;
15856       suffix[0] = p[0];
15857       suffix[1] = p[1];
15858       suffix[2] = '\0';
15859       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
15860       mnemonicendp += simd_cmp_op[cmp_type].len;
15861     }
15862   else
15863     {
15864       /* We have a reserved extension byte.  Output it directly.  */
15865       scratchbuf[0] = '$';
15866       print_operand_value (scratchbuf + 1, 1, cmp_type);
15867       oappend_maybe_intel (scratchbuf);
15868       scratchbuf[0] = '\0';
15869     }
15870 }
15871
15872 static void
15873 OP_Mwait (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
15874 {
15875   /* mwait %eax,%ecx / mwaitx %eax,%ecx,%ebx  */
15876   if (!intel_syntax)
15877     {
15878       strcpy (op_out[0], names32[0]);
15879       strcpy (op_out[1], names32[1]);
15880       if (bytemode == eBX_reg)
15881         strcpy (op_out[2], names32[3]);
15882       two_source_ops = 1;
15883     }
15884   /* Skip mod/rm byte.  */
15885   MODRM_CHECK;
15886   codep++;
15887 }
15888
15889 static void
15890 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
15891             int sizeflag ATTRIBUTE_UNUSED)
15892 {
15893   /* monitor %{e,r,}ax,%ecx,%edx"  */
15894   if (!intel_syntax)
15895     {
15896       const char **names = (address_mode == mode_64bit
15897                             ? names64 : names32);
15898
15899       if (prefixes & PREFIX_ADDR)
15900         {
15901           /* Remove "addr16/addr32".  */
15902           all_prefixes[last_addr_prefix] = 0;
15903           names = (address_mode != mode_32bit
15904                    ? names32 : names16);
15905           used_prefixes |= PREFIX_ADDR;
15906         }
15907       else if (address_mode == mode_16bit)
15908         names = names16;
15909       strcpy (op_out[0], names[0]);
15910       strcpy (op_out[1], names32[1]);
15911       strcpy (op_out[2], names32[2]);
15912       two_source_ops = 1;
15913     }
15914   /* Skip mod/rm byte.  */
15915   MODRM_CHECK;
15916   codep++;
15917 }
15918
15919 static void
15920 BadOp (void)
15921 {
15922   /* Throw away prefixes and 1st. opcode byte.  */
15923   codep = insn_codep + 1;
15924   oappend ("(bad)");
15925 }
15926
15927 static void
15928 REP_Fixup (int bytemode, int sizeflag)
15929 {
15930   /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
15931      lods and stos.  */
15932   if (prefixes & PREFIX_REPZ)
15933     all_prefixes[last_repz_prefix] = REP_PREFIX;
15934
15935   switch (bytemode)
15936     {
15937     case al_reg:
15938     case eAX_reg:
15939     case indir_dx_reg:
15940       OP_IMREG (bytemode, sizeflag);
15941       break;
15942     case eDI_reg:
15943       OP_ESreg (bytemode, sizeflag);
15944       break;
15945     case eSI_reg:
15946       OP_DSreg (bytemode, sizeflag);
15947       break;
15948     default:
15949       abort ();
15950       break;
15951     }
15952 }
15953
15954 static void
15955 SEP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15956 {
15957   if ( isa64 != amd64 )
15958     return;
15959
15960   obufp = obuf;
15961   BadOp ();
15962   mnemonicendp = obufp;
15963   ++codep;
15964 }
15965
15966 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
15967    "bnd".  */
15968
15969 static void
15970 BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15971 {
15972   if (prefixes & PREFIX_REPNZ)
15973     all_prefixes[last_repnz_prefix] = BND_PREFIX;
15974 }
15975
15976 /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
15977    "notrack".  */
15978
15979 static void
15980 NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED,
15981                int sizeflag ATTRIBUTE_UNUSED)
15982 {
15983   if (active_seg_prefix == PREFIX_DS
15984       && (address_mode != mode_64bit || last_data_prefix < 0))
15985     {
15986       /* NOTRACK prefix is only valid on indirect branch instructions.
15987          NB: DATA prefix is unsupported for Intel64.  */
15988       active_seg_prefix = 0;
15989       all_prefixes[last_seg_prefix] = NOTRACK_PREFIX;
15990     }
15991 }
15992
15993 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
15994    "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
15995  */
15996
15997 static void
15998 HLE_Fixup1 (int bytemode, int sizeflag)
15999 {
16000   if (modrm.mod != 3
16001       && (prefixes & PREFIX_LOCK) != 0)
16002     {
16003       if (prefixes & PREFIX_REPZ)
16004         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16005       if (prefixes & PREFIX_REPNZ)
16006         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16007     }
16008
16009   OP_E (bytemode, sizeflag);
16010 }
16011
16012 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
16013    "xacquire"/"xrelease" for memory operand.  No check for LOCK prefix.
16014  */
16015
16016 static void
16017 HLE_Fixup2 (int bytemode, int sizeflag)
16018 {
16019   if (modrm.mod != 3)
16020     {
16021       if (prefixes & PREFIX_REPZ)
16022         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16023       if (prefixes & PREFIX_REPNZ)
16024         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16025     }
16026
16027   OP_E (bytemode, sizeflag);
16028 }
16029
16030 /* Similar to OP_E.  But the 0xf3 prefixes should be displayed as
16031    "xrelease" for memory operand.  No check for LOCK prefix.   */
16032
16033 static void
16034 HLE_Fixup3 (int bytemode, int sizeflag)
16035 {
16036   if (modrm.mod != 3
16037       && last_repz_prefix > last_repnz_prefix
16038       && (prefixes & PREFIX_REPZ) != 0)
16039     all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16040
16041   OP_E (bytemode, sizeflag);
16042 }
16043
16044 static void
16045 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
16046 {
16047   USED_REX (REX_W);
16048   if (rex & REX_W)
16049     {
16050       /* Change cmpxchg8b to cmpxchg16b.  */
16051       char *p = mnemonicendp - 2;
16052       mnemonicendp = stpcpy (p, "16b");
16053       bytemode = o_mode;
16054     }
16055   else if ((prefixes & PREFIX_LOCK) != 0)
16056     {
16057       if (prefixes & PREFIX_REPZ)
16058         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16059       if (prefixes & PREFIX_REPNZ)
16060         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16061     }
16062
16063   OP_M (bytemode, sizeflag);
16064 }
16065
16066 static void
16067 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
16068 {
16069   const char **names;
16070
16071   if (need_vex)
16072     {
16073       switch (vex.length)
16074         {
16075         case 128:
16076           names = names_xmm;
16077           break;
16078         case 256:
16079           names = names_ymm;
16080           break;
16081         default:
16082           abort ();
16083         }
16084     }
16085   else
16086     names = names_xmm;
16087   oappend (names[reg]);
16088 }
16089
16090 static void
16091 CRC32_Fixup (int bytemode, int sizeflag)
16092 {
16093   /* Add proper suffix to "crc32".  */
16094   char *p = mnemonicendp;
16095
16096   switch (bytemode)
16097     {
16098     case b_mode:
16099       if (intel_syntax)
16100         goto skip;
16101
16102       *p++ = 'b';
16103       break;
16104     case v_mode:
16105       if (intel_syntax)
16106         goto skip;
16107
16108       USED_REX (REX_W);
16109       if (rex & REX_W)
16110         *p++ = 'q';
16111       else
16112         {
16113           if (sizeflag & DFLAG)
16114             *p++ = 'l';
16115           else
16116             *p++ = 'w';
16117           used_prefixes |= (prefixes & PREFIX_DATA);
16118         }
16119       break;
16120     default:
16121       oappend (INTERNAL_DISASSEMBLER_ERROR);
16122       break;
16123     }
16124   mnemonicendp = p;
16125   *p = '\0';
16126
16127  skip:
16128   if (modrm.mod == 3)
16129     {
16130       int add;
16131
16132       /* Skip mod/rm byte.  */
16133       MODRM_CHECK;
16134       codep++;
16135
16136       USED_REX (REX_B);
16137       add = (rex & REX_B) ? 8 : 0;
16138       if (bytemode == b_mode)
16139         {
16140           USED_REX (0);
16141           if (rex)
16142             oappend (names8rex[modrm.rm + add]);
16143           else
16144             oappend (names8[modrm.rm + add]);
16145         }
16146       else
16147         {
16148           USED_REX (REX_W);
16149           if (rex & REX_W)
16150             oappend (names64[modrm.rm + add]);
16151           else if ((prefixes & PREFIX_DATA))
16152             oappend (names16[modrm.rm + add]);
16153           else
16154             oappend (names32[modrm.rm + add]);
16155         }
16156     }
16157   else
16158     OP_E (bytemode, sizeflag);
16159 }
16160
16161 static void
16162 FXSAVE_Fixup (int bytemode, int sizeflag)
16163 {
16164   /* Add proper suffix to "fxsave" and "fxrstor".  */
16165   USED_REX (REX_W);
16166   if (rex & REX_W)
16167     {
16168       char *p = mnemonicendp;
16169       *p++ = '6';
16170       *p++ = '4';
16171       *p = '\0';
16172       mnemonicendp = p;
16173     }
16174   OP_M (bytemode, sizeflag);
16175 }
16176
16177 static void
16178 PCMPESTR_Fixup (int bytemode, int sizeflag)
16179 {
16180   /* Add proper suffix to "{,v}pcmpestr{i,m}".  */
16181   if (!intel_syntax)
16182     {
16183       char *p = mnemonicendp;
16184
16185       USED_REX (REX_W);
16186       if (rex & REX_W)
16187         *p++ = 'q';
16188       else if (sizeflag & SUFFIX_ALWAYS)
16189         *p++ = 'l';
16190
16191       *p = '\0';
16192       mnemonicendp = p;
16193     }
16194
16195   OP_EX (bytemode, sizeflag);
16196 }
16197
16198 /* Display the destination register operand for instructions with
16199    VEX. */
16200
16201 static void
16202 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16203 {
16204   int reg;
16205   const char **names;
16206
16207   if (!need_vex)
16208     abort ();
16209
16210   if (!need_vex_reg)
16211     return;
16212
16213   reg = vex.register_specifier;
16214   vex.register_specifier = 0;
16215   if (address_mode != mode_64bit)
16216     reg &= 7;
16217   else if (vex.evex && !vex.v)
16218     reg += 16;
16219
16220   if (bytemode == vex_scalar_mode)
16221     {
16222       oappend (names_xmm[reg]);
16223       return;
16224     }
16225
16226   switch (vex.length)
16227     {
16228     case 128:
16229       switch (bytemode)
16230         {
16231         case vex_mode:
16232         case vex128_mode:
16233         case vex_vsib_q_w_dq_mode:
16234         case vex_vsib_q_w_d_mode:
16235           names = names_xmm;
16236           break;
16237         case dq_mode:
16238           if (rex & REX_W)
16239             names = names64;
16240           else
16241             names = names32;
16242           break;
16243         case mask_bd_mode:
16244         case mask_mode:
16245           if (reg > 0x7)
16246             {
16247               oappend ("(bad)");
16248               return;
16249             }
16250           names = names_mask;
16251           break;
16252         default:
16253           abort ();
16254           return;
16255         }
16256       break;
16257     case 256:
16258       switch (bytemode)
16259         {
16260         case vex_mode:
16261         case vex256_mode:
16262           names = names_ymm;
16263           break;
16264         case vex_vsib_q_w_dq_mode:
16265         case vex_vsib_q_w_d_mode:
16266           names = vex.w ? names_ymm : names_xmm;
16267           break;
16268         case mask_bd_mode:
16269         case mask_mode:
16270           if (reg > 0x7)
16271             {
16272               oappend ("(bad)");
16273               return;
16274             }
16275           names = names_mask;
16276           break;
16277         default:
16278           /* See PR binutils/20893 for a reproducer.  */
16279           oappend ("(bad)");
16280           return;
16281         }
16282       break;
16283     case 512:
16284       names = names_zmm;
16285       break;
16286     default:
16287       abort ();
16288       break;
16289     }
16290   oappend (names[reg]);
16291 }
16292
16293 static void
16294 OP_VexW (int bytemode, int sizeflag)
16295 {
16296   OP_VEX (bytemode, sizeflag);
16297
16298   if (vex.w)
16299     {
16300       /* Swap 2nd and 3rd operands.  */
16301       strcpy (scratchbuf, op_out[2]);
16302       strcpy (op_out[2], op_out[1]);
16303       strcpy (op_out[1], scratchbuf);
16304     }
16305 }
16306
16307 static void
16308 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16309 {
16310   int reg;
16311   const char **names = names_xmm;
16312
16313   FETCH_DATA (the_info, codep + 1);
16314   reg = *codep++;
16315
16316   if (bytemode != x_mode && bytemode != scalar_mode)
16317     abort ();
16318
16319   reg >>= 4;
16320   if (address_mode != mode_64bit)
16321     reg &= 7;
16322
16323   if (bytemode == x_mode && vex.length == 256)
16324     names = names_ymm;
16325
16326   oappend (names[reg]);
16327
16328   if (vex.w)
16329     {
16330       /* Swap 3rd and 4th operands.  */
16331       strcpy (scratchbuf, op_out[3]);
16332       strcpy (op_out[3], op_out[2]);
16333       strcpy (op_out[2], scratchbuf);
16334     }
16335 }
16336
16337 static void
16338 OP_VexI4 (int bytemode ATTRIBUTE_UNUSED,
16339           int sizeflag ATTRIBUTE_UNUSED)
16340 {
16341   scratchbuf[0] = '$';
16342   print_operand_value (scratchbuf + 1, 1, codep[-1] & 0xf);
16343   oappend_maybe_intel (scratchbuf);
16344 }
16345
16346 static void
16347 OP_EX_Vex (int bytemode, int sizeflag)
16348 {
16349   if (modrm.mod != 3)
16350     need_vex_reg = 0;
16351   OP_EX (bytemode, sizeflag);
16352 }
16353
16354 static void
16355 OP_XMM_Vex (int bytemode, int sizeflag)
16356 {
16357   if (modrm.mod != 3)
16358     need_vex_reg = 0;
16359   OP_XMM (bytemode, sizeflag);
16360 }
16361
16362 static struct op vex_cmp_op[] =
16363 {
16364   { STRING_COMMA_LEN ("eq") },
16365   { STRING_COMMA_LEN ("lt") },
16366   { STRING_COMMA_LEN ("le") },
16367   { STRING_COMMA_LEN ("unord") },
16368   { STRING_COMMA_LEN ("neq") },
16369   { STRING_COMMA_LEN ("nlt") },
16370   { STRING_COMMA_LEN ("nle") },
16371   { STRING_COMMA_LEN ("ord") },
16372   { STRING_COMMA_LEN ("eq_uq") },
16373   { STRING_COMMA_LEN ("nge") },
16374   { STRING_COMMA_LEN ("ngt") },
16375   { STRING_COMMA_LEN ("false") },
16376   { STRING_COMMA_LEN ("neq_oq") },
16377   { STRING_COMMA_LEN ("ge") },
16378   { STRING_COMMA_LEN ("gt") },
16379   { STRING_COMMA_LEN ("true") },
16380   { STRING_COMMA_LEN ("eq_os") },
16381   { STRING_COMMA_LEN ("lt_oq") },
16382   { STRING_COMMA_LEN ("le_oq") },
16383   { STRING_COMMA_LEN ("unord_s") },
16384   { STRING_COMMA_LEN ("neq_us") },
16385   { STRING_COMMA_LEN ("nlt_uq") },
16386   { STRING_COMMA_LEN ("nle_uq") },
16387   { STRING_COMMA_LEN ("ord_s") },
16388   { STRING_COMMA_LEN ("eq_us") },
16389   { STRING_COMMA_LEN ("nge_uq") },
16390   { STRING_COMMA_LEN ("ngt_uq") },
16391   { STRING_COMMA_LEN ("false_os") },
16392   { STRING_COMMA_LEN ("neq_os") },
16393   { STRING_COMMA_LEN ("ge_oq") },
16394   { STRING_COMMA_LEN ("gt_oq") },
16395   { STRING_COMMA_LEN ("true_us") },
16396 };
16397
16398 static void
16399 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16400 {
16401   unsigned int cmp_type;
16402
16403   FETCH_DATA (the_info, codep + 1);
16404   cmp_type = *codep++ & 0xff;
16405   if (cmp_type < ARRAY_SIZE (vex_cmp_op))
16406     {
16407       char suffix [3];
16408       char *p = mnemonicendp - 2;
16409       suffix[0] = p[0];
16410       suffix[1] = p[1];
16411       suffix[2] = '\0';
16412       sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
16413       mnemonicendp += vex_cmp_op[cmp_type].len;
16414     }
16415   else
16416     {
16417       /* We have a reserved extension byte.  Output it directly.  */
16418       scratchbuf[0] = '$';
16419       print_operand_value (scratchbuf + 1, 1, cmp_type);
16420       oappend_maybe_intel (scratchbuf);
16421       scratchbuf[0] = '\0';
16422     }
16423 }
16424
16425 static void
16426 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED,
16427              int sizeflag ATTRIBUTE_UNUSED)
16428 {
16429   unsigned int cmp_type;
16430
16431   if (!vex.evex)
16432     abort ();
16433
16434   FETCH_DATA (the_info, codep + 1);
16435   cmp_type = *codep++ & 0xff;
16436   /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
16437      If it's the case, print suffix, otherwise - print the immediate.  */
16438   if (cmp_type < ARRAY_SIZE (simd_cmp_op)
16439       && cmp_type != 3
16440       && cmp_type != 7)
16441     {
16442       char suffix [3];
16443       char *p = mnemonicendp - 2;
16444
16445       /* vpcmp* can have both one- and two-lettered suffix.  */
16446       if (p[0] == 'p')
16447         {
16448           p++;
16449           suffix[0] = p[0];
16450           suffix[1] = '\0';
16451         }
16452       else
16453         {
16454           suffix[0] = p[0];
16455           suffix[1] = p[1];
16456           suffix[2] = '\0';
16457         }
16458
16459       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
16460       mnemonicendp += simd_cmp_op[cmp_type].len;
16461     }
16462   else
16463     {
16464       /* We have a reserved extension byte.  Output it directly.  */
16465       scratchbuf[0] = '$';
16466       print_operand_value (scratchbuf + 1, 1, cmp_type);
16467       oappend_maybe_intel (scratchbuf);
16468       scratchbuf[0] = '\0';
16469     }
16470 }
16471
16472 static const struct op xop_cmp_op[] =
16473 {
16474   { STRING_COMMA_LEN ("lt") },
16475   { STRING_COMMA_LEN ("le") },
16476   { STRING_COMMA_LEN ("gt") },
16477   { STRING_COMMA_LEN ("ge") },
16478   { STRING_COMMA_LEN ("eq") },
16479   { STRING_COMMA_LEN ("neq") },
16480   { STRING_COMMA_LEN ("false") },
16481   { STRING_COMMA_LEN ("true") }
16482 };
16483
16484 static void
16485 VPCOM_Fixup (int bytemode ATTRIBUTE_UNUSED,
16486              int sizeflag ATTRIBUTE_UNUSED)
16487 {
16488   unsigned int cmp_type;
16489
16490   FETCH_DATA (the_info, codep + 1);
16491   cmp_type = *codep++ & 0xff;
16492   if (cmp_type < ARRAY_SIZE (xop_cmp_op))
16493     {
16494       char suffix[3];
16495       char *p = mnemonicendp - 2;
16496
16497       /* vpcom* can have both one- and two-lettered suffix.  */
16498       if (p[0] == 'm')
16499         {
16500           p++;
16501           suffix[0] = p[0];
16502           suffix[1] = '\0';
16503         }
16504       else
16505         {
16506           suffix[0] = p[0];
16507           suffix[1] = p[1];
16508           suffix[2] = '\0';
16509         }
16510
16511       sprintf (p, "%s%s", xop_cmp_op[cmp_type].name, suffix);
16512       mnemonicendp += xop_cmp_op[cmp_type].len;
16513     }
16514   else
16515     {
16516       /* We have a reserved extension byte.  Output it directly.  */
16517       scratchbuf[0] = '$';
16518       print_operand_value (scratchbuf + 1, 1, cmp_type);
16519       oappend_maybe_intel (scratchbuf);
16520       scratchbuf[0] = '\0';
16521     }
16522 }
16523
16524 static const struct op pclmul_op[] =
16525 {
16526   { STRING_COMMA_LEN ("lql") },
16527   { STRING_COMMA_LEN ("hql") },
16528   { STRING_COMMA_LEN ("lqh") },
16529   { STRING_COMMA_LEN ("hqh") }
16530 };
16531
16532 static void
16533 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
16534               int sizeflag ATTRIBUTE_UNUSED)
16535 {
16536   unsigned int pclmul_type;
16537
16538   FETCH_DATA (the_info, codep + 1);
16539   pclmul_type = *codep++ & 0xff;
16540   switch (pclmul_type)
16541     {
16542     case 0x10:
16543       pclmul_type = 2;
16544       break;
16545     case 0x11:
16546       pclmul_type = 3;
16547       break;
16548     default:
16549       break;
16550     }
16551   if (pclmul_type < ARRAY_SIZE (pclmul_op))
16552     {
16553       char suffix [4];
16554       char *p = mnemonicendp - 3;
16555       suffix[0] = p[0];
16556       suffix[1] = p[1];
16557       suffix[2] = p[2];
16558       suffix[3] = '\0';
16559       sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
16560       mnemonicendp += pclmul_op[pclmul_type].len;
16561     }
16562   else
16563     {
16564       /* We have a reserved extension byte.  Output it directly.  */
16565       scratchbuf[0] = '$';
16566       print_operand_value (scratchbuf + 1, 1, pclmul_type);
16567       oappend_maybe_intel (scratchbuf);
16568       scratchbuf[0] = '\0';
16569     }
16570 }
16571
16572 static void
16573 MOVBE_Fixup (int bytemode, int sizeflag)
16574 {
16575   /* Add proper suffix to "movbe".  */
16576   char *p = mnemonicendp;
16577
16578   switch (bytemode)
16579     {
16580     case v_mode:
16581       if (intel_syntax)
16582         goto skip;
16583
16584       USED_REX (REX_W);
16585       if (sizeflag & SUFFIX_ALWAYS)
16586         {
16587           if (rex & REX_W)
16588             *p++ = 'q';
16589           else
16590             {
16591               if (sizeflag & DFLAG)
16592                 *p++ = 'l';
16593               else
16594                 *p++ = 'w';
16595               used_prefixes |= (prefixes & PREFIX_DATA);
16596             }
16597         }
16598       break;
16599     default:
16600       oappend (INTERNAL_DISASSEMBLER_ERROR);
16601       break;
16602     }
16603   mnemonicendp = p;
16604   *p = '\0';
16605
16606  skip:
16607   OP_M (bytemode, sizeflag);
16608 }
16609
16610 static void
16611 MOVSXD_Fixup (int bytemode, int sizeflag)
16612 {
16613   /* Add proper suffix to "movsxd".  */
16614   char *p = mnemonicendp;
16615
16616   switch (bytemode)
16617     {
16618     case movsxd_mode:
16619       if (intel_syntax)
16620         {
16621           *p++ = 'x';
16622           *p++ = 'd';
16623           goto skip;
16624         }
16625
16626       USED_REX (REX_W);
16627       if (rex & REX_W)
16628         {
16629           *p++ = 'l';
16630           *p++ = 'q';
16631         }
16632       else
16633         {
16634           *p++ = 'x';
16635           *p++ = 'd';
16636         }
16637       break;
16638     default:
16639       oappend (INTERNAL_DISASSEMBLER_ERROR);
16640       break;
16641     }
16642
16643  skip:
16644   mnemonicendp = p;
16645   *p = '\0';
16646   OP_E (bytemode, sizeflag);
16647 }
16648
16649 static void
16650 OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16651 {
16652   if (!vex.evex
16653       || (bytemode != mask_mode && bytemode != mask_bd_mode))
16654     abort ();
16655
16656   USED_REX (REX_R);
16657   if ((rex & REX_R) != 0 || !vex.r)
16658     {
16659       BadOp ();
16660       return;
16661     }
16662
16663   oappend (names_mask [modrm.reg]);
16664 }
16665
16666 static void
16667 OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16668 {
16669   if (modrm.mod == 3 && vex.b)
16670     switch (bytemode)
16671       {
16672       case evex_rounding_64_mode:
16673         if (address_mode != mode_64bit)
16674           {
16675             oappend ("(bad)");
16676             break;
16677           }
16678         /* Fall through.  */
16679       case evex_rounding_mode:
16680         oappend (names_rounding[vex.ll]);
16681         break;
16682       case evex_sae_mode:
16683         oappend ("{sae}");
16684         break;
16685       default:
16686         abort ();
16687         break;
16688       }
16689 }