opcodes/i386-dis.c

   1 /* Print i386 instructions for GDB, the GNU debugger.
   2    Copyright (C) 1988-2020 Free Software Foundation, Inc.
   3
   4    This file is part of the GNU opcodes library.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    It is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program; if not, write to the Free Software
  18    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  19    MA 02110-1301, USA.  */
  20
  21
  22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
  23    July 1988
  24     modified by John Hassey (hassey@dg-rtp.dg.com)
  25     x86-64 support added by Jan Hubicka (jh@suse.cz)
  26     VIA PadLock support by Michal Ludvig (mludvig@suse.cz).  */
  27
  28 /* The main tables describing the instructions is essentially a copy
  29    of the "Opcode Map" chapter (Appendix A) of the Intel 80386
  30    Programmers Manual.  Usually, there is a capital letter, followed
  31    by a small letter.  The capital letter tell the addressing mode,
  32    and the small letter tells about the operand size.  Refer to
  33    the Intel manual for details.  */
  34
  35 #include "sysdep.h"
  36 #include "disassemble.h"
  37 #include "opintl.h"
  38 #include "opcode/i386.h"
  39 #include "libiberty.h"
  40 #include "safe-ctype.h"
  41
  42 #include <setjmp.h>
  43
  44 static int print_insn (bfd_vma, disassemble_info *);
  45 static void dofloat (int);
  46 static void OP_ST (int, int);
  47 static void OP_STi (int, int);
  48 static int putop (const char *, int);
  49 static void oappend (const char *);
  50 static void append_seg (void);
  51 static void OP_indirE (int, int);
  52 static void print_operand_value (char *, int, bfd_vma);
  53 static void OP_E_register (int, int);
  54 static void OP_E_memory (int, int);
  55 static void print_displacement (char *, bfd_vma);
  56 static void OP_E (int, int);
  57 static void OP_G (int, int);
  58 static bfd_vma get64 (void);
  59 static bfd_signed_vma get32 (void);
  60 static bfd_signed_vma get32s (void);
  61 static int get16 (void);
  62 static void set_op (bfd_vma, int);
  63 static void OP_Skip_MODRM (int, int);
  64 static void OP_REG (int, int);
  65 static void OP_IMREG (int, int);
  66 static void OP_I (int, int);
  67 static void OP_I64 (int, int);
  68 static void OP_sI (int, int);
  69 static void OP_J (int, int);
  70 static void OP_SEG (int, int);
  71 static void OP_DIR (int, int);
  72 static void OP_OFF (int, int);
  73 static void OP_OFF64 (int, int);
  74 static void ptr_reg (int, int);
  75 static void OP_ESreg (int, int);
  76 static void OP_DSreg (int, int);
  77 static void OP_C (int, int);
  78 static void OP_D (int, int);
  79 static void OP_T (int, int);
  80 static void OP_R (int, int);
  81 static void OP_MMX (int, int);
  82 static void OP_XMM (int, int);
  83 static void OP_EM (int, int);
  84 static void OP_EX (int, int);
  85 static void OP_EMC (int,int);
  86 static void OP_MXC (int,int);
  87 static void OP_MS (int, int);
  88 static void OP_XS (int, int);
  89 static void OP_M (int, int);
  90 static void OP_VEX (int, int);
  91 static void OP_VexW (int, int);
  92 static void OP_EX_Vex (int, int);
  93 static void OP_XMM_Vex (int, int);
  94 static void OP_Rounding (int, int);
  95 static void OP_REG_VexI4 (int, int);
  96 static void OP_VexI4 (int, int);
  97 static void PCLMUL_Fixup (int, int);
  98 static void VCMP_Fixup (int, int);
  99 static void VPCMP_Fixup (int, int);
 100 static void VPCOM_Fixup (int, int);
 101 static void OP_0f07 (int, int);
 102 static void OP_Monitor (int, int);
 103 static void OP_Mwait (int, int);
 104 static void NOP_Fixup1 (int, int);
 105 static void NOP_Fixup2 (int, int);
 106 static void OP_3DNowSuffix (int, int);
 107 static void CMP_Fixup (int, int);
 108 static void BadOp (void);
 109 static void REP_Fixup (int, int);
 110 static void SEP_Fixup (int, int);
 111 static void BND_Fixup (int, int);
 112 static void NOTRACK_Fixup (int, int);
 113 static void HLE_Fixup1 (int, int);
 114 static void HLE_Fixup2 (int, int);
 115 static void HLE_Fixup3 (int, int);
 116 static void CMPXCHG8B_Fixup (int, int);
 117 static void XMM_Fixup (int, int);
 118 static void CRC32_Fixup (int, int);
 119 static void FXSAVE_Fixup (int, int);
 120 static void PCMPESTR_Fixup (int, int);
 121 static void OP_LWPCB_E (int, int);
 122 static void OP_LWP_E (int, int);
 123
 124 static void MOVBE_Fixup (int, int);
 125 static void MOVSXD_Fixup (int, int);
 126
 127 static void OP_Mask (int, int);
 128
 129 struct dis_private {
 130   /* Points to first byte not fetched.  */
 131   bfd_byte *max_fetched;
 132   bfd_byte the_buffer[MAX_MNEM_SIZE];
 133   bfd_vma insn_start;
 134   int orig_sizeflag;
 135   OPCODES_SIGJMP_BUF bailout;
 136 };
 137
 138 enum address_mode
 139 {
 140   mode_16bit,
 141   mode_32bit,
 142   mode_64bit
 143 };
 144
 145 enum address_mode address_mode;
 146
 147 /* Flags for the prefixes for the current instruction.  See below.  */
 148 static int prefixes;
 149
 150 /* REX prefix the current instruction.  See below.  */
 151 static int rex;
 152 /* Bits of REX we've already used.  */
 153 static int rex_used;
 154 /* Mark parts used in the REX prefix.  When we are testing for
 155    empty prefix (for 8bit register REX extension), just mask it
 156    out.  Otherwise test for REX bit is excuse for existence of REX
 157    only in case value is nonzero.  */
 158 #define USED_REX(value)                                 \
 159   {                                                     \
 160     if (value)                                          \
 161       {                                                 \
 162         if ((rex & value))                              \
 163           rex_used |= (value) | REX_OPCODE;             \
 164       }                                                 \
 165     else                                                \
 166       rex_used |= REX_OPCODE;                           \
 167   }
 168
 169 /* Flags for prefixes which we somehow handled when printing the
 170    current instruction.  */
 171 static int used_prefixes;
 172
 173 /* Flags stored in PREFIXES.  */
 174 #define PREFIX_REPZ 1
 175 #define PREFIX_REPNZ 2
 176 #define PREFIX_LOCK 4
 177 #define PREFIX_CS 8
 178 #define PREFIX_SS 0x10
 179 #define PREFIX_DS 0x20
 180 #define PREFIX_ES 0x40
 181 #define PREFIX_FS 0x80
 182 #define PREFIX_GS 0x100
 183 #define PREFIX_DATA 0x200
 184 #define PREFIX_ADDR 0x400
 185 #define PREFIX_FWAIT 0x800
 186
 187 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
 188    to ADDR (exclusive) are valid.  Returns 1 for success, longjmps
 189    on error.  */
 190 #define FETCH_DATA(info, addr) \
 191   ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
 192    ? 1 : fetch_data ((info), (addr)))
 193
 194 static int
 195 fetch_data (struct disassemble_info *info, bfd_byte *addr)
 196 {
 197   int status;
 198   struct dis_private *priv = (struct dis_private *) info->private_data;
 199   bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
 200
 201   if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
 202     status = (*info->read_memory_func) (start,
 203                                         priv->max_fetched,
 204                                         addr - priv->max_fetched,
 205                                         info);
 206   else
 207     status = -1;
 208   if (status != 0)
 209     {
 210       /* If we did manage to read at least one byte, then
 211          print_insn_i386 will do something sensible.  Otherwise, print
 212          an error.  We do that here because this is where we know
 213          STATUS.  */
 214       if (priv->max_fetched == priv->the_buffer)
 215         (*info->memory_error_func) (status, start, info);
 216       OPCODES_SIGLONGJMP (priv->bailout, 1);
 217     }
 218   else
 219     priv->max_fetched = addr;
 220   return 1;
 221 }
 222
 223 /* Possible values for prefix requirement.  */
 224 #define PREFIX_IGNORED_SHIFT    16
 225 #define PREFIX_IGNORED_REPZ     (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
 226 #define PREFIX_IGNORED_REPNZ    (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
 227 #define PREFIX_IGNORED_DATA     (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
 228 #define PREFIX_IGNORED_ADDR     (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
 229 #define PREFIX_IGNORED_LOCK     (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
 230
 231 /* Opcode prefixes.  */
 232 #define PREFIX_OPCODE           (PREFIX_REPZ \
 233                                  | PREFIX_REPNZ \
 234                                  | PREFIX_DATA)
 235
 236 /* Prefixes ignored.  */
 237 #define PREFIX_IGNORED          (PREFIX_IGNORED_REPZ \
 238                                  | PREFIX_IGNORED_REPNZ \
 239                                  | PREFIX_IGNORED_DATA)
 240
 241 #define XX { NULL, 0 }
 242 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
 243
 244 #define Eb { OP_E, b_mode }
 245 #define Ebnd { OP_E, bnd_mode }
 246 #define EbS { OP_E, b_swap_mode }
 247 #define EbndS { OP_E, bnd_swap_mode }
 248 #define Ev { OP_E, v_mode }
 249 #define Eva { OP_E, va_mode }
 250 #define Ev_bnd { OP_E, v_bnd_mode }
 251 #define EvS { OP_E, v_swap_mode }
 252 #define Ed { OP_E, d_mode }
 253 #define Edq { OP_E, dq_mode }
 254 #define Edqw { OP_E, dqw_mode }
 255 #define Edqb { OP_E, dqb_mode }
 256 #define Edb { OP_E, db_mode }
 257 #define Edw { OP_E, dw_mode }
 258 #define Edqd { OP_E, dqd_mode }
 259 #define Eq { OP_E, q_mode }
 260 #define indirEv { OP_indirE, indir_v_mode }
 261 #define indirEp { OP_indirE, f_mode }
 262 #define stackEv { OP_E, stack_v_mode }
 263 #define Em { OP_E, m_mode }
 264 #define Ew { OP_E, w_mode }
 265 #define M { OP_M, 0 }           /* lea, lgdt, etc. */
 266 #define Ma { OP_M, a_mode }
 267 #define Mb { OP_M, b_mode }
 268 #define Md { OP_M, d_mode }
 269 #define Mo { OP_M, o_mode }
 270 #define Mp { OP_M, f_mode }             /* 32 or 48 bit memory operand for LDS, LES etc */
 271 #define Mq { OP_M, q_mode }
 272 #define Mv_bnd { OP_M, v_bndmk_mode }
 273 #define Mx { OP_M, x_mode }
 274 #define Mxmm { OP_M, xmm_mode }
 275 #define Gb { OP_G, b_mode }
 276 #define Gbnd { OP_G, bnd_mode }
 277 #define Gv { OP_G, v_mode }
 278 #define Gd { OP_G, d_mode }
 279 #define Gdq { OP_G, dq_mode }
 280 #define Gm { OP_G, m_mode }
 281 #define Gva { OP_G, va_mode }
 282 #define Gw { OP_G, w_mode }
 283 #define Rd { OP_R, d_mode }
 284 #define Rdq { OP_R, dq_mode }
 285 #define Rm { OP_R, m_mode }
 286 #define Ib { OP_I, b_mode }
 287 #define sIb { OP_sI, b_mode }   /* sign extened byte */
 288 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
 289 #define Iv { OP_I, v_mode }
 290 #define sIv { OP_sI, v_mode }
 291 #define Iv64 { OP_I64, v_mode }
 292 #define Id { OP_I, d_mode }
 293 #define Iw { OP_I, w_mode }
 294 #define I1 { OP_I, const_1_mode }
 295 #define Jb { OP_J, b_mode }
 296 #define Jv { OP_J, v_mode }
 297 #define Jdqw { OP_J, dqw_mode }
 298 #define Cm { OP_C, m_mode }
 299 #define Dm { OP_D, m_mode }
 300 #define Td { OP_T, d_mode }
 301 #define Skip_MODRM { OP_Skip_MODRM, 0 }
 302
 303 #define RMeAX { OP_REG, eAX_reg }
 304 #define RMeBX { OP_REG, eBX_reg }
 305 #define RMeCX { OP_REG, eCX_reg }
 306 #define RMeDX { OP_REG, eDX_reg }
 307 #define RMeSP { OP_REG, eSP_reg }
 308 #define RMeBP { OP_REG, eBP_reg }
 309 #define RMeSI { OP_REG, eSI_reg }
 310 #define RMeDI { OP_REG, eDI_reg }
 311 #define RMrAX { OP_REG, rAX_reg }
 312 #define RMrBX { OP_REG, rBX_reg }
 313 #define RMrCX { OP_REG, rCX_reg }
 314 #define RMrDX { OP_REG, rDX_reg }
 315 #define RMrSP { OP_REG, rSP_reg }
 316 #define RMrBP { OP_REG, rBP_reg }
 317 #define RMrSI { OP_REG, rSI_reg }
 318 #define RMrDI { OP_REG, rDI_reg }
 319 #define RMAL { OP_REG, al_reg }
 320 #define RMCL { OP_REG, cl_reg }
 321 #define RMDL { OP_REG, dl_reg }
 322 #define RMBL { OP_REG, bl_reg }
 323 #define RMAH { OP_REG, ah_reg }
 324 #define RMCH { OP_REG, ch_reg }
 325 #define RMDH { OP_REG, dh_reg }
 326 #define RMBH { OP_REG, bh_reg }
 327 #define RMAX { OP_REG, ax_reg }
 328 #define RMDX { OP_REG, dx_reg }
 329
 330 #define eAX { OP_IMREG, eAX_reg }
 331 #define eBX { OP_IMREG, eBX_reg }
 332 #define eCX { OP_IMREG, eCX_reg }
 333 #define eDX { OP_IMREG, eDX_reg }
 334 #define eSP { OP_IMREG, eSP_reg }
 335 #define eBP { OP_IMREG, eBP_reg }
 336 #define eSI { OP_IMREG, eSI_reg }
 337 #define eDI { OP_IMREG, eDI_reg }
 338 #define AL { OP_IMREG, al_reg }
 339 #define CL { OP_IMREG, cl_reg }
 340 #define DL { OP_IMREG, dl_reg }
 341 #define BL { OP_IMREG, bl_reg }
 342 #define AH { OP_IMREG, ah_reg }
 343 #define CH { OP_IMREG, ch_reg }
 344 #define DH { OP_IMREG, dh_reg }
 345 #define BH { OP_IMREG, bh_reg }
 346 #define AX { OP_IMREG, ax_reg }
 347 #define DX { OP_IMREG, dx_reg }
 348 #define zAX { OP_IMREG, z_mode_ax_reg }
 349 #define indirDX { OP_IMREG, indir_dx_reg }
 350
 351 #define Sw { OP_SEG, w_mode }
 352 #define Sv { OP_SEG, v_mode }
 353 #define Ap { OP_DIR, 0 }
 354 #define Ob { OP_OFF64, b_mode }
 355 #define Ov { OP_OFF64, v_mode }
 356 #define Xb { OP_DSreg, eSI_reg }
 357 #define Xv { OP_DSreg, eSI_reg }
 358 #define Xz { OP_DSreg, eSI_reg }
 359 #define Yb { OP_ESreg, eDI_reg }
 360 #define Yv { OP_ESreg, eDI_reg }
 361 #define DSBX { OP_DSreg, eBX_reg }
 362
 363 #define es { OP_REG, es_reg }
 364 #define ss { OP_REG, ss_reg }
 365 #define cs { OP_REG, cs_reg }
 366 #define ds { OP_REG, ds_reg }
 367 #define fs { OP_REG, fs_reg }
 368 #define gs { OP_REG, gs_reg }
 369
 370 #define MX { OP_MMX, 0 }
 371 #define XM { OP_XMM, 0 }
 372 #define XMScalar { OP_XMM, scalar_mode }
 373 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
 374 #define XMM { OP_XMM, xmm_mode }
 375 #define XMxmmq { OP_XMM, xmmq_mode }
 376 #define EM { OP_EM, v_mode }
 377 #define EMS { OP_EM, v_swap_mode }
 378 #define EMd { OP_EM, d_mode }
 379 #define EMx { OP_EM, x_mode }
 380 #define EXbScalar { OP_EX, b_scalar_mode }
 381 #define EXw { OP_EX, w_mode }
 382 #define EXwScalar { OP_EX, w_scalar_mode }
 383 #define EXd { OP_EX, d_mode }
 384 #define EXdS { OP_EX, d_swap_mode }
 385 #define EXq { OP_EX, q_mode }
 386 #define EXqS { OP_EX, q_swap_mode }
 387 #define EXx { OP_EX, x_mode }
 388 #define EXxS { OP_EX, x_swap_mode }
 389 #define EXxmm { OP_EX, xmm_mode }
 390 #define EXymm { OP_EX, ymm_mode }
 391 #define EXxmmq { OP_EX, xmmq_mode }
 392 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
 393 #define EXxmm_mb { OP_EX, xmm_mb_mode }
 394 #define EXxmm_mw { OP_EX, xmm_mw_mode }
 395 #define EXxmm_md { OP_EX, xmm_md_mode }
 396 #define EXxmm_mq { OP_EX, xmm_mq_mode }
 397 #define EXxmmdw { OP_EX, xmmdw_mode }
 398 #define EXxmmqd { OP_EX, xmmqd_mode }
 399 #define EXymmq { OP_EX, ymmq_mode }
 400 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
 401 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
 402 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
 403 #define MS { OP_MS, v_mode }
 404 #define XS { OP_XS, v_mode }
 405 #define EMCq { OP_EMC, q_mode }
 406 #define MXC { OP_MXC, 0 }
 407 #define OPSUF { OP_3DNowSuffix, 0 }
 408 #define SEP { SEP_Fixup, 0 }
 409 #define CMP { CMP_Fixup, 0 }
 410 #define XMM0 { XMM_Fixup, 0 }
 411 #define FXSAVE { FXSAVE_Fixup, 0 }
 412
 413 #define Vex { OP_VEX, vex_mode }
 414 #define VexW { OP_VexW, vex_mode }
 415 #define VexScalar { OP_VEX, vex_scalar_mode }
 416 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
 417 #define Vex128 { OP_VEX, vex128_mode }
 418 #define Vex256 { OP_VEX, vex256_mode }
 419 #define VexGdq { OP_VEX, dq_mode }
 420 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
 421 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
 422 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
 423 #define XMVexI4 { OP_REG_VexI4, x_mode }
 424 #define VexI4 { OP_VexI4, 0 }
 425 #define PCLMUL { PCLMUL_Fixup, 0 }
 426 #define VCMP { VCMP_Fixup, 0 }
 427 #define VPCMP { VPCMP_Fixup, 0 }
 428 #define VPCOM { VPCOM_Fixup, 0 }
 429
 430 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
 431 #define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode }
 432 #define EXxEVexS { OP_Rounding, evex_sae_mode }
 433
 434 #define XMask { OP_Mask, mask_mode }
 435 #define MaskG { OP_G, mask_mode }
 436 #define MaskE { OP_E, mask_mode }
 437 #define MaskBDE { OP_E, mask_bd_mode }
 438 #define MaskR { OP_R, mask_mode }
 439 #define MaskVex { OP_VEX, mask_mode }
 440
 441 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
 442 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
 443 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
 444 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
 445
 446 /* Used handle "rep" prefix for string instructions.  */
 447 #define Xbr { REP_Fixup, eSI_reg }
 448 #define Xvr { REP_Fixup, eSI_reg }
 449 #define Ybr { REP_Fixup, eDI_reg }
 450 #define Yvr { REP_Fixup, eDI_reg }
 451 #define Yzr { REP_Fixup, eDI_reg }
 452 #define indirDXr { REP_Fixup, indir_dx_reg }
 453 #define ALr { REP_Fixup, al_reg }
 454 #define eAXr { REP_Fixup, eAX_reg }
 455
 456 /* Used handle HLE prefix for lockable instructions.  */
 457 #define Ebh1 { HLE_Fixup1, b_mode }
 458 #define Evh1 { HLE_Fixup1, v_mode }
 459 #define Ebh2 { HLE_Fixup2, b_mode }
 460 #define Evh2 { HLE_Fixup2, v_mode }
 461 #define Ebh3 { HLE_Fixup3, b_mode }
 462 #define Evh3 { HLE_Fixup3, v_mode }
 463
 464 #define BND { BND_Fixup, 0 }
 465 #define NOTRACK { NOTRACK_Fixup, 0 }
 466
 467 #define cond_jump_flag { NULL, cond_jump_mode }
 468 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
 469
 470 /* bits in sizeflag */
 471 #define SUFFIX_ALWAYS 4
 472 #define AFLAG 2
 473 #define DFLAG 1
 474
 475 enum
 476 {
 477   /* byte operand */
 478   b_mode = 1,
 479   /* byte operand with operand swapped */
 480   b_swap_mode,
 481   /* byte operand, sign extend like 'T' suffix */
 482   b_T_mode,
 483   /* operand size depends on prefixes */
 484   v_mode,
 485   /* operand size depends on prefixes with operand swapped */
 486   v_swap_mode,
 487   /* operand size depends on address prefix */
 488   va_mode,
 489   /* word operand */
 490   w_mode,
 491   /* double word operand  */
 492   d_mode,
 493   /* double word operand with operand swapped */
 494   d_swap_mode,
 495   /* quad word operand */
 496   q_mode,
 497   /* quad word operand with operand swapped */
 498   q_swap_mode,
 499   /* ten-byte operand */
 500   t_mode,
 501   /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand.  In EVEX with
 502      broadcast enabled.  */
 503   x_mode,
 504   /* Similar to x_mode, but with different EVEX mem shifts.  */
 505   evex_x_gscat_mode,
 506   /* Similar to x_mode, but with disabled broadcast.  */
 507   evex_x_nobcst_mode,
 508   /* Similar to x_mode, but with operands swapped and disabled broadcast
 509      in EVEX.  */
 510   x_swap_mode,
 511   /* 16-byte XMM operand */
 512   xmm_mode,
 513   /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
 514      memory operand (depending on vector length).  Broadcast isn't
 515      allowed.  */
 516   xmmq_mode,
 517   /* Same as xmmq_mode, but broadcast is allowed.  */
 518   evex_half_bcst_xmmq_mode,
 519   /* XMM register or byte memory operand */
 520   xmm_mb_mode,
 521   /* XMM register or word memory operand */
 522   xmm_mw_mode,
 523   /* XMM register or double word memory operand */
 524   xmm_md_mode,
 525   /* XMM register or quad word memory operand */
 526   xmm_mq_mode,
 527   /* 16-byte XMM, word, double word or quad word operand.  */
 528   xmmdw_mode,
 529   /* 16-byte XMM, double word, quad word operand or xmm word operand.  */
 530   xmmqd_mode,
 531   /* 32-byte YMM operand */
 532   ymm_mode,
 533   /* quad word, ymmword or zmmword memory operand.  */
 534   ymmq_mode,
 535   /* 32-byte YMM or 16-byte word operand */
 536   ymmxmm_mode,
 537   /* d_mode in 32bit, q_mode in 64bit mode.  */
 538   m_mode,
 539   /* pair of v_mode operands */
 540   a_mode,
 541   cond_jump_mode,
 542   loop_jcxz_mode,
 543   movsxd_mode,
 544   v_bnd_mode,
 545   /* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode.  */
 546   v_bndmk_mode,
 547   /* operand size depends on REX prefixes.  */
 548   dq_mode,
 549   /* registers like dq_mode, memory like w_mode, displacements like
 550      v_mode without considering Intel64 ISA.  */
 551   dqw_mode,
 552   /* bounds operand */
 553   bnd_mode,
 554   /* bounds operand with operand swapped */
 555   bnd_swap_mode,
 556   /* 4- or 6-byte pointer operand */
 557   f_mode,
 558   const_1_mode,
 559   /* v_mode for indirect branch opcodes.  */
 560   indir_v_mode,
 561   /* v_mode for stack-related opcodes.  */
 562   stack_v_mode,
 563   /* non-quad operand size depends on prefixes */
 564   z_mode,
 565   /* 16-byte operand */
 566   o_mode,
 567   /* registers like dq_mode, memory like b_mode.  */
 568   dqb_mode,
 569   /* registers like d_mode, memory like b_mode.  */
 570   db_mode,
 571   /* registers like d_mode, memory like w_mode.  */
 572   dw_mode,
 573   /* registers like dq_mode, memory like d_mode.  */
 574   dqd_mode,
 575   /* normal vex mode */
 576   vex_mode,
 577   /* 128bit vex mode */
 578   vex128_mode,
 579   /* 256bit vex mode */
 580   vex256_mode,
 581
 582   /* Operand size depends on the VEX.W bit, with VSIB dword indices.  */
 583   vex_vsib_d_w_dq_mode,
 584   /* Similar to vex_vsib_d_w_dq_mode, with smaller memory.  */
 585   vex_vsib_d_w_d_mode,
 586   /* Operand size depends on the VEX.W bit, with VSIB qword indices.  */
 587   vex_vsib_q_w_dq_mode,
 588   /* Similar to vex_vsib_q_w_dq_mode, with smaller memory.  */
 589   vex_vsib_q_w_d_mode,
 590
 591   /* scalar, ignore vector length.  */
 592   scalar_mode,
 593   /* like b_mode, ignore vector length.  */
 594   b_scalar_mode,
 595   /* like w_mode, ignore vector length.  */
 596   w_scalar_mode,
 597   /* like d_swap_mode, ignore vector length.  */
 598   d_scalar_swap_mode,
 599   /* like q_swap_mode, ignore vector length.  */
 600   q_scalar_swap_mode,
 601   /* like vex_mode, ignore vector length.  */
 602   vex_scalar_mode,
 603   /* Operand size depends on the VEX.W bit, ignore vector length.  */
 604   vex_scalar_w_dq_mode,
 605
 606   /* Static rounding.  */
 607   evex_rounding_mode,
 608   /* Static rounding, 64-bit mode only.  */
 609   evex_rounding_64_mode,
 610   /* Supress all exceptions.  */
 611   evex_sae_mode,
 612
 613   /* Mask register operand.  */
 614   mask_mode,
 615   /* Mask register operand.  */
 616   mask_bd_mode,
 617
 618   es_reg,
 619   cs_reg,
 620   ss_reg,
 621   ds_reg,
 622   fs_reg,
 623   gs_reg,
 624
 625   eAX_reg,
 626   eCX_reg,
 627   eDX_reg,
 628   eBX_reg,
 629   eSP_reg,
 630   eBP_reg,
 631   eSI_reg,
 632   eDI_reg,
 633
 634   al_reg,
 635   cl_reg,
 636   dl_reg,
 637   bl_reg,
 638   ah_reg,
 639   ch_reg,
 640   dh_reg,
 641   bh_reg,
 642
 643   ax_reg,
 644   cx_reg,
 645   dx_reg,
 646   bx_reg,
 647   sp_reg,
 648   bp_reg,
 649   si_reg,
 650   di_reg,
 651
 652   rAX_reg,
 653   rCX_reg,
 654   rDX_reg,
 655   rBX_reg,
 656   rSP_reg,
 657   rBP_reg,
 658   rSI_reg,
 659   rDI_reg,
 660
 661   z_mode_ax_reg,
 662   indir_dx_reg
 663 };
 664
 665 enum
 666 {
 667   FLOATCODE = 1,
 668   USE_REG_TABLE,
 669   USE_MOD_TABLE,
 670   USE_RM_TABLE,
 671   USE_PREFIX_TABLE,
 672   USE_X86_64_TABLE,
 673   USE_3BYTE_TABLE,
 674   USE_XOP_8F_TABLE,
 675   USE_VEX_C4_TABLE,
 676   USE_VEX_C5_TABLE,
 677   USE_VEX_LEN_TABLE,
 678   USE_VEX_W_TABLE,
 679   USE_EVEX_TABLE,
 680   USE_EVEX_LEN_TABLE
 681 };
 682
 683 #define FLOAT                   NULL, { { NULL, FLOATCODE } }, 0
 684
 685 #define DIS386(T, I)            NULL, { { NULL, (T)}, { NULL,  (I) } }, 0
 686 #define DIS386_PREFIX(T, I, P)          NULL, { { NULL, (T)}, { NULL,  (I) } }, P
 687 #define REG_TABLE(I)            DIS386 (USE_REG_TABLE, (I))
 688 #define MOD_TABLE(I)            DIS386 (USE_MOD_TABLE, (I))
 689 #define RM_TABLE(I)             DIS386 (USE_RM_TABLE, (I))
 690 #define PREFIX_TABLE(I)         DIS386 (USE_PREFIX_TABLE, (I))
 691 #define X86_64_TABLE(I)         DIS386 (USE_X86_64_TABLE, (I))
 692 #define THREE_BYTE_TABLE(I)     DIS386 (USE_3BYTE_TABLE, (I))
 693 #define THREE_BYTE_TABLE_PREFIX(I, P)   DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
 694 #define XOP_8F_TABLE(I)         DIS386 (USE_XOP_8F_TABLE, (I))
 695 #define VEX_C4_TABLE(I)         DIS386 (USE_VEX_C4_TABLE, (I))
 696 #define VEX_C5_TABLE(I)         DIS386 (USE_VEX_C5_TABLE, (I))
 697 #define VEX_LEN_TABLE(I)        DIS386 (USE_VEX_LEN_TABLE, (I))
 698 #define VEX_W_TABLE(I)          DIS386 (USE_VEX_W_TABLE, (I))
 699 #define EVEX_TABLE(I)           DIS386 (USE_EVEX_TABLE, (I))
 700 #define EVEX_LEN_TABLE(I)       DIS386 (USE_EVEX_LEN_TABLE, (I))
 701
 702 enum
 703 {
 704   REG_80 = 0,
 705   REG_81,
 706   REG_83,
 707   REG_8F,
 708   REG_C0,
 709   REG_C1,
 710   REG_C6,
 711   REG_C7,
 712   REG_D0,
 713   REG_D1,
 714   REG_D2,
 715   REG_D3,
 716   REG_F6,
 717   REG_F7,
 718   REG_FE,
 719   REG_FF,
 720   REG_0F00,
 721   REG_0F01,
 722   REG_0F0D,
 723   REG_0F18,
 724   REG_0F1C_P_0_MOD_0,
 725   REG_0F1E_P_1_MOD_3,
 726   REG_0F71,
 727   REG_0F72,
 728   REG_0F73,
 729   REG_0FA6,
 730   REG_0FA7,
 731   REG_0FAE,
 732   REG_0FBA,
 733   REG_0FC7,
 734   REG_VEX_0F71,
 735   REG_VEX_0F72,
 736   REG_VEX_0F73,
 737   REG_VEX_0FAE,
 738   REG_VEX_0F38F3,
 739   REG_XOP_LWPCB,
 740   REG_XOP_LWP,
 741   REG_XOP_TBM_01,
 742   REG_XOP_TBM_02,
 743
 744   REG_EVEX_0F71,
 745   REG_EVEX_0F72,
 746   REG_EVEX_0F73,
 747   REG_EVEX_0F38C6,
 748   REG_EVEX_0F38C7
 749 };
 750
 751 enum
 752 {
 753   MOD_8D = 0,
 754   MOD_C6_REG_7,
 755   MOD_C7_REG_7,
 756   MOD_FF_REG_3,
 757   MOD_FF_REG_5,
 758   MOD_0F01_REG_0,
 759   MOD_0F01_REG_1,
 760   MOD_0F01_REG_2,
 761   MOD_0F01_REG_3,
 762   MOD_0F01_REG_5,
 763   MOD_0F01_REG_7,
 764   MOD_0F12_PREFIX_0,
 765   MOD_0F12_PREFIX_2,
 766   MOD_0F13,
 767   MOD_0F16_PREFIX_0,
 768   MOD_0F16_PREFIX_2,
 769   MOD_0F17,
 770   MOD_0F18_REG_0,
 771   MOD_0F18_REG_1,
 772   MOD_0F18_REG_2,
 773   MOD_0F18_REG_3,
 774   MOD_0F18_REG_4,
 775   MOD_0F18_REG_5,
 776   MOD_0F18_REG_6,
 777   MOD_0F18_REG_7,
 778   MOD_0F1A_PREFIX_0,
 779   MOD_0F1B_PREFIX_0,
 780   MOD_0F1B_PREFIX_1,
 781   MOD_0F1C_PREFIX_0,
 782   MOD_0F1E_PREFIX_1,
 783   MOD_0F24,
 784   MOD_0F26,
 785   MOD_0F2B_PREFIX_0,
 786   MOD_0F2B_PREFIX_1,
 787   MOD_0F2B_PREFIX_2,
 788   MOD_0F2B_PREFIX_3,
 789   MOD_0F50,
 790   MOD_0F71_REG_2,
 791   MOD_0F71_REG_4,
 792   MOD_0F71_REG_6,
 793   MOD_0F72_REG_2,
 794   MOD_0F72_REG_4,
 795   MOD_0F72_REG_6,
 796   MOD_0F73_REG_2,
 797   MOD_0F73_REG_3,
 798   MOD_0F73_REG_6,
 799   MOD_0F73_REG_7,
 800   MOD_0FAE_REG_0,
 801   MOD_0FAE_REG_1,
 802   MOD_0FAE_REG_2,
 803   MOD_0FAE_REG_3,
 804   MOD_0FAE_REG_4,
 805   MOD_0FAE_REG_5,
 806   MOD_0FAE_REG_6,
 807   MOD_0FAE_REG_7,
 808   MOD_0FB2,
 809   MOD_0FB4,
 810   MOD_0FB5,
 811   MOD_0FC3,
 812   MOD_0FC7_REG_3,
 813   MOD_0FC7_REG_4,
 814   MOD_0FC7_REG_5,
 815   MOD_0FC7_REG_6,
 816   MOD_0FC7_REG_7,
 817   MOD_0FD7,
 818   MOD_0FE7_PREFIX_2,
 819   MOD_0FF0_PREFIX_3,
 820   MOD_0F382A_PREFIX_2,
 821   MOD_0F38F5_PREFIX_2,
 822   MOD_0F38F6_PREFIX_0,
 823   MOD_0F38F8_PREFIX_1,
 824   MOD_0F38F8_PREFIX_2,
 825   MOD_0F38F8_PREFIX_3,
 826   MOD_0F38F9_PREFIX_0,
 827   MOD_62_32BIT,
 828   MOD_C4_32BIT,
 829   MOD_C5_32BIT,
 830   MOD_VEX_0F12_PREFIX_0,
 831   MOD_VEX_0F12_PREFIX_2,
 832   MOD_VEX_0F13,
 833   MOD_VEX_0F16_PREFIX_0,
 834   MOD_VEX_0F16_PREFIX_2,
 835   MOD_VEX_0F17,
 836   MOD_VEX_0F2B,
 837   MOD_VEX_W_0_0F41_P_0_LEN_1,
 838   MOD_VEX_W_1_0F41_P_0_LEN_1,
 839   MOD_VEX_W_0_0F41_P_2_LEN_1,
 840   MOD_VEX_W_1_0F41_P_2_LEN_1,
 841   MOD_VEX_W_0_0F42_P_0_LEN_1,
 842   MOD_VEX_W_1_0F42_P_0_LEN_1,
 843   MOD_VEX_W_0_0F42_P_2_LEN_1,
 844   MOD_VEX_W_1_0F42_P_2_LEN_1,
 845   MOD_VEX_W_0_0F44_P_0_LEN_1,
 846   MOD_VEX_W_1_0F44_P_0_LEN_1,
 847   MOD_VEX_W_0_0F44_P_2_LEN_1,
 848   MOD_VEX_W_1_0F44_P_2_LEN_1,
 849   MOD_VEX_W_0_0F45_P_0_LEN_1,
 850   MOD_VEX_W_1_0F45_P_0_LEN_1,
 851   MOD_VEX_W_0_0F45_P_2_LEN_1,
 852   MOD_VEX_W_1_0F45_P_2_LEN_1,
 853   MOD_VEX_W_0_0F46_P_0_LEN_1,
 854   MOD_VEX_W_1_0F46_P_0_LEN_1,
 855   MOD_VEX_W_0_0F46_P_2_LEN_1,
 856   MOD_VEX_W_1_0F46_P_2_LEN_1,
 857   MOD_VEX_W_0_0F47_P_0_LEN_1,
 858   MOD_VEX_W_1_0F47_P_0_LEN_1,
 859   MOD_VEX_W_0_0F47_P_2_LEN_1,
 860   MOD_VEX_W_1_0F47_P_2_LEN_1,
 861   MOD_VEX_W_0_0F4A_P_0_LEN_1,
 862   MOD_VEX_W_1_0F4A_P_0_LEN_1,
 863   MOD_VEX_W_0_0F4A_P_2_LEN_1,
 864   MOD_VEX_W_1_0F4A_P_2_LEN_1,
 865   MOD_VEX_W_0_0F4B_P_0_LEN_1,
 866   MOD_VEX_W_1_0F4B_P_0_LEN_1,
 867   MOD_VEX_W_0_0F4B_P_2_LEN_1,
 868   MOD_VEX_0F50,
 869   MOD_VEX_0F71_REG_2,
 870   MOD_VEX_0F71_REG_4,
 871   MOD_VEX_0F71_REG_6,
 872   MOD_VEX_0F72_REG_2,
 873   MOD_VEX_0F72_REG_4,
 874   MOD_VEX_0F72_REG_6,
 875   MOD_VEX_0F73_REG_2,
 876   MOD_VEX_0F73_REG_3,
 877   MOD_VEX_0F73_REG_6,
 878   MOD_VEX_0F73_REG_7,
 879   MOD_VEX_W_0_0F91_P_0_LEN_0,
 880   MOD_VEX_W_1_0F91_P_0_LEN_0,
 881   MOD_VEX_W_0_0F91_P_2_LEN_0,
 882   MOD_VEX_W_1_0F91_P_2_LEN_0,
 883   MOD_VEX_W_0_0F92_P_0_LEN_0,
 884   MOD_VEX_W_0_0F92_P_2_LEN_0,
 885   MOD_VEX_0F92_P_3_LEN_0,
 886   MOD_VEX_W_0_0F93_P_0_LEN_0,
 887   MOD_VEX_W_0_0F93_P_2_LEN_0,
 888   MOD_VEX_0F93_P_3_LEN_0,
 889   MOD_VEX_W_0_0F98_P_0_LEN_0,
 890   MOD_VEX_W_1_0F98_P_0_LEN_0,
 891   MOD_VEX_W_0_0F98_P_2_LEN_0,
 892   MOD_VEX_W_1_0F98_P_2_LEN_0,
 893   MOD_VEX_W_0_0F99_P_0_LEN_0,
 894   MOD_VEX_W_1_0F99_P_0_LEN_0,
 895   MOD_VEX_W_0_0F99_P_2_LEN_0,
 896   MOD_VEX_W_1_0F99_P_2_LEN_0,
 897   MOD_VEX_0FAE_REG_2,
 898   MOD_VEX_0FAE_REG_3,
 899   MOD_VEX_0FD7_PREFIX_2,
 900   MOD_VEX_0FE7_PREFIX_2,
 901   MOD_VEX_0FF0_PREFIX_3,
 902   MOD_VEX_0F381A_PREFIX_2,
 903   MOD_VEX_0F382A_PREFIX_2,
 904   MOD_VEX_0F382C_PREFIX_2,
 905   MOD_VEX_0F382D_PREFIX_2,
 906   MOD_VEX_0F382E_PREFIX_2,
 907   MOD_VEX_0F382F_PREFIX_2,
 908   MOD_VEX_0F385A_PREFIX_2,
 909   MOD_VEX_0F388C_PREFIX_2,
 910   MOD_VEX_0F388E_PREFIX_2,
 911   MOD_VEX_W_0_0F3A30_P_2_LEN_0,
 912   MOD_VEX_W_1_0F3A30_P_2_LEN_0,
 913   MOD_VEX_W_0_0F3A31_P_2_LEN_0,
 914   MOD_VEX_W_1_0F3A31_P_2_LEN_0,
 915   MOD_VEX_W_0_0F3A32_P_2_LEN_0,
 916   MOD_VEX_W_1_0F3A32_P_2_LEN_0,
 917   MOD_VEX_W_0_0F3A33_P_2_LEN_0,
 918   MOD_VEX_W_1_0F3A33_P_2_LEN_0,
 919
 920   MOD_EVEX_0F12_PREFIX_0,
 921   MOD_EVEX_0F12_PREFIX_2,
 922   MOD_EVEX_0F13,
 923   MOD_EVEX_0F16_PREFIX_0,
 924   MOD_EVEX_0F16_PREFIX_2,
 925   MOD_EVEX_0F17,
 926   MOD_EVEX_0F2B,
 927   MOD_EVEX_0F381A_P_2_W_0,
 928   MOD_EVEX_0F381A_P_2_W_1,
 929   MOD_EVEX_0F381B_P_2_W_0,
 930   MOD_EVEX_0F381B_P_2_W_1,
 931   MOD_EVEX_0F385A_P_2_W_0,
 932   MOD_EVEX_0F385A_P_2_W_1,
 933   MOD_EVEX_0F385B_P_2_W_0,
 934   MOD_EVEX_0F385B_P_2_W_1,
 935   MOD_EVEX_0F38C6_REG_1,
 936   MOD_EVEX_0F38C6_REG_2,
 937   MOD_EVEX_0F38C6_REG_5,
 938   MOD_EVEX_0F38C6_REG_6,
 939   MOD_EVEX_0F38C7_REG_1,
 940   MOD_EVEX_0F38C7_REG_2,
 941   MOD_EVEX_0F38C7_REG_5,
 942   MOD_EVEX_0F38C7_REG_6
 943 };
 944
 945 enum
 946 {
 947   RM_C6_REG_7 = 0,
 948   RM_C7_REG_7,
 949   RM_0F01_REG_0,
 950   RM_0F01_REG_1,
 951   RM_0F01_REG_2,
 952   RM_0F01_REG_3,
 953   RM_0F01_REG_5_MOD_3,
 954   RM_0F01_REG_7_MOD_3,
 955   RM_0F1E_P_1_MOD_3_REG_7,
 956   RM_0FAE_REG_6_MOD_3_P_0,
 957   RM_0FAE_REG_7_MOD_3,
 958 };
 959
 960 enum
 961 {
 962   PREFIX_90 = 0,
 963   PREFIX_0F01_REG_3_RM_1,
 964   PREFIX_0F01_REG_5_MOD_0,
 965   PREFIX_0F01_REG_5_MOD_3_RM_0,
 966   PREFIX_0F01_REG_5_MOD_3_RM_1,
 967   PREFIX_0F01_REG_5_MOD_3_RM_2,
 968   PREFIX_0F01_REG_7_MOD_3_RM_2,
 969   PREFIX_0F01_REG_7_MOD_3_RM_3,
 970   PREFIX_0F09,
 971   PREFIX_0F10,
 972   PREFIX_0F11,
 973   PREFIX_0F12,
 974   PREFIX_0F16,
 975   PREFIX_0F1A,
 976   PREFIX_0F1B,
 977   PREFIX_0F1C,
 978   PREFIX_0F1E,
 979   PREFIX_0F2A,
 980   PREFIX_0F2B,
 981   PREFIX_0F2C,
 982   PREFIX_0F2D,
 983   PREFIX_0F2E,
 984   PREFIX_0F2F,
 985   PREFIX_0F51,
 986   PREFIX_0F52,
 987   PREFIX_0F53,
 988   PREFIX_0F58,
 989   PREFIX_0F59,
 990   PREFIX_0F5A,
 991   PREFIX_0F5B,
 992   PREFIX_0F5C,
 993   PREFIX_0F5D,
 994   PREFIX_0F5E,
 995   PREFIX_0F5F,
 996   PREFIX_0F60,
 997   PREFIX_0F61,
 998   PREFIX_0F62,
 999   PREFIX_0F6C,
1000   PREFIX_0F6D,
1001   PREFIX_0F6F,
1002   PREFIX_0F70,
1003   PREFIX_0F73_REG_3,
1004   PREFIX_0F73_REG_7,
1005   PREFIX_0F78,
1006   PREFIX_0F79,
1007   PREFIX_0F7C,
1008   PREFIX_0F7D,
1009   PREFIX_0F7E,
1010   PREFIX_0F7F,
1011   PREFIX_0FAE_REG_0_MOD_3,
1012   PREFIX_0FAE_REG_1_MOD_3,
1013   PREFIX_0FAE_REG_2_MOD_3,
1014   PREFIX_0FAE_REG_3_MOD_3,
1015   PREFIX_0FAE_REG_4_MOD_0,
1016   PREFIX_0FAE_REG_4_MOD_3,
1017   PREFIX_0FAE_REG_5_MOD_0,
1018   PREFIX_0FAE_REG_5_MOD_3,
1019   PREFIX_0FAE_REG_6_MOD_0,
1020   PREFIX_0FAE_REG_6_MOD_3,
1021   PREFIX_0FAE_REG_7_MOD_0,
1022   PREFIX_0FB8,
1023   PREFIX_0FBC,
1024   PREFIX_0FBD,
1025   PREFIX_0FC2,
1026   PREFIX_0FC3_MOD_0,
1027   PREFIX_0FC7_REG_6_MOD_0,
1028   PREFIX_0FC7_REG_6_MOD_3,
1029   PREFIX_0FC7_REG_7_MOD_3,
1030   PREFIX_0FD0,
1031   PREFIX_0FD6,
1032   PREFIX_0FE6,
1033   PREFIX_0FE7,
1034   PREFIX_0FF0,
1035   PREFIX_0FF7,
1036   PREFIX_0F3810,
1037   PREFIX_0F3814,
1038   PREFIX_0F3815,
1039   PREFIX_0F3817,
1040   PREFIX_0F3820,
1041   PREFIX_0F3821,
1042   PREFIX_0F3822,
1043   PREFIX_0F3823,
1044   PREFIX_0F3824,
1045   PREFIX_0F3825,
1046   PREFIX_0F3828,
1047   PREFIX_0F3829,
1048   PREFIX_0F382A,
1049   PREFIX_0F382B,
1050   PREFIX_0F3830,
1051   PREFIX_0F3831,
1052   PREFIX_0F3832,
1053   PREFIX_0F3833,
1054   PREFIX_0F3834,
1055   PREFIX_0F3835,
1056   PREFIX_0F3837,
1057   PREFIX_0F3838,
1058   PREFIX_0F3839,
1059   PREFIX_0F383A,
1060   PREFIX_0F383B,
1061   PREFIX_0F383C,
1062   PREFIX_0F383D,
1063   PREFIX_0F383E,
1064   PREFIX_0F383F,
1065   PREFIX_0F3840,
1066   PREFIX_0F3841,
1067   PREFIX_0F3880,
1068   PREFIX_0F3881,
1069   PREFIX_0F3882,
1070   PREFIX_0F38C8,
1071   PREFIX_0F38C9,
1072   PREFIX_0F38CA,
1073   PREFIX_0F38CB,
1074   PREFIX_0F38CC,
1075   PREFIX_0F38CD,
1076   PREFIX_0F38CF,
1077   PREFIX_0F38DB,
1078   PREFIX_0F38DC,
1079   PREFIX_0F38DD,
1080   PREFIX_0F38DE,
1081   PREFIX_0F38DF,
1082   PREFIX_0F38F0,
1083   PREFIX_0F38F1,
1084   PREFIX_0F38F5,
1085   PREFIX_0F38F6,
1086   PREFIX_0F38F8,
1087   PREFIX_0F38F9,
1088   PREFIX_0F3A08,
1089   PREFIX_0F3A09,
1090   PREFIX_0F3A0A,
1091   PREFIX_0F3A0B,
1092   PREFIX_0F3A0C,
1093   PREFIX_0F3A0D,
1094   PREFIX_0F3A0E,
1095   PREFIX_0F3A14,
1096   PREFIX_0F3A15,
1097   PREFIX_0F3A16,
1098   PREFIX_0F3A17,
1099   PREFIX_0F3A20,
1100   PREFIX_0F3A21,
1101   PREFIX_0F3A22,
1102   PREFIX_0F3A40,
1103   PREFIX_0F3A41,
1104   PREFIX_0F3A42,
1105   PREFIX_0F3A44,
1106   PREFIX_0F3A60,
1107   PREFIX_0F3A61,
1108   PREFIX_0F3A62,
1109   PREFIX_0F3A63,
1110   PREFIX_0F3ACC,
1111   PREFIX_0F3ACE,
1112   PREFIX_0F3ACF,
1113   PREFIX_0F3ADF,
1114   PREFIX_VEX_0F10,
1115   PREFIX_VEX_0F11,
1116   PREFIX_VEX_0F12,
1117   PREFIX_VEX_0F16,
1118   PREFIX_VEX_0F2A,
1119   PREFIX_VEX_0F2C,
1120   PREFIX_VEX_0F2D,
1121   PREFIX_VEX_0F2E,
1122   PREFIX_VEX_0F2F,
1123   PREFIX_VEX_0F41,
1124   PREFIX_VEX_0F42,
1125   PREFIX_VEX_0F44,
1126   PREFIX_VEX_0F45,
1127   PREFIX_VEX_0F46,
1128   PREFIX_VEX_0F47,
1129   PREFIX_VEX_0F4A,
1130   PREFIX_VEX_0F4B,
1131   PREFIX_VEX_0F51,
1132   PREFIX_VEX_0F52,
1133   PREFIX_VEX_0F53,
1134   PREFIX_VEX_0F58,
1135   PREFIX_VEX_0F59,
1136   PREFIX_VEX_0F5A,
1137   PREFIX_VEX_0F5B,
1138   PREFIX_VEX_0F5C,
1139   PREFIX_VEX_0F5D,
1140   PREFIX_VEX_0F5E,
1141   PREFIX_VEX_0F5F,
1142   PREFIX_VEX_0F60,
1143   PREFIX_VEX_0F61,
1144   PREFIX_VEX_0F62,
1145   PREFIX_VEX_0F63,
1146   PREFIX_VEX_0F64,
1147   PREFIX_VEX_0F65,
1148   PREFIX_VEX_0F66,
1149   PREFIX_VEX_0F67,
1150   PREFIX_VEX_0F68,
1151   PREFIX_VEX_0F69,
1152   PREFIX_VEX_0F6A,
1153   PREFIX_VEX_0F6B,
1154   PREFIX_VEX_0F6C,
1155   PREFIX_VEX_0F6D,
1156   PREFIX_VEX_0F6E,
1157   PREFIX_VEX_0F6F,
1158   PREFIX_VEX_0F70,
1159   PREFIX_VEX_0F71_REG_2,
1160   PREFIX_VEX_0F71_REG_4,
1161   PREFIX_VEX_0F71_REG_6,
1162   PREFIX_VEX_0F72_REG_2,
1163   PREFIX_VEX_0F72_REG_4,
1164   PREFIX_VEX_0F72_REG_6,
1165   PREFIX_VEX_0F73_REG_2,
1166   PREFIX_VEX_0F73_REG_3,
1167   PREFIX_VEX_0F73_REG_6,
1168   PREFIX_VEX_0F73_REG_7,
1169   PREFIX_VEX_0F74,
1170   PREFIX_VEX_0F75,
1171   PREFIX_VEX_0F76,
1172   PREFIX_VEX_0F77,
1173   PREFIX_VEX_0F7C,
1174   PREFIX_VEX_0F7D,
1175   PREFIX_VEX_0F7E,
1176   PREFIX_VEX_0F7F,
1177   PREFIX_VEX_0F90,
1178   PREFIX_VEX_0F91,
1179   PREFIX_VEX_0F92,
1180   PREFIX_VEX_0F93,
1181   PREFIX_VEX_0F98,
1182   PREFIX_VEX_0F99,
1183   PREFIX_VEX_0FC2,
1184   PREFIX_VEX_0FC4,
1185   PREFIX_VEX_0FC5,
1186   PREFIX_VEX_0FD0,
1187   PREFIX_VEX_0FD1,
1188   PREFIX_VEX_0FD2,
1189   PREFIX_VEX_0FD3,
1190   PREFIX_VEX_0FD4,
1191   PREFIX_VEX_0FD5,
1192   PREFIX_VEX_0FD6,
1193   PREFIX_VEX_0FD7,
1194   PREFIX_VEX_0FD8,
1195   PREFIX_VEX_0FD9,
1196   PREFIX_VEX_0FDA,
1197   PREFIX_VEX_0FDB,
1198   PREFIX_VEX_0FDC,
1199   PREFIX_VEX_0FDD,
1200   PREFIX_VEX_0FDE,
1201   PREFIX_VEX_0FDF,
1202   PREFIX_VEX_0FE0,
1203   PREFIX_VEX_0FE1,
1204   PREFIX_VEX_0FE2,
1205   PREFIX_VEX_0FE3,
1206   PREFIX_VEX_0FE4,
1207   PREFIX_VEX_0FE5,
1208   PREFIX_VEX_0FE6,
1209   PREFIX_VEX_0FE7,
1210   PREFIX_VEX_0FE8,
1211   PREFIX_VEX_0FE9,
1212   PREFIX_VEX_0FEA,
1213   PREFIX_VEX_0FEB,
1214   PREFIX_VEX_0FEC,
1215   PREFIX_VEX_0FED,
1216   PREFIX_VEX_0FEE,
1217   PREFIX_VEX_0FEF,
1218   PREFIX_VEX_0FF0,
1219   PREFIX_VEX_0FF1,
1220   PREFIX_VEX_0FF2,
1221   PREFIX_VEX_0FF3,
1222   PREFIX_VEX_0FF4,
1223   PREFIX_VEX_0FF5,
1224   PREFIX_VEX_0FF6,
1225   PREFIX_VEX_0FF7,
1226   PREFIX_VEX_0FF8,
1227   PREFIX_VEX_0FF9,
1228   PREFIX_VEX_0FFA,
1229   PREFIX_VEX_0FFB,
1230   PREFIX_VEX_0FFC,
1231   PREFIX_VEX_0FFD,
1232   PREFIX_VEX_0FFE,
1233   PREFIX_VEX_0F3800,
1234   PREFIX_VEX_0F3801,
1235   PREFIX_VEX_0F3802,
1236   PREFIX_VEX_0F3803,
1237   PREFIX_VEX_0F3804,
1238   PREFIX_VEX_0F3805,
1239   PREFIX_VEX_0F3806,
1240   PREFIX_VEX_0F3807,
1241   PREFIX_VEX_0F3808,
1242   PREFIX_VEX_0F3809,
1243   PREFIX_VEX_0F380A,
1244   PREFIX_VEX_0F380B,
1245   PREFIX_VEX_0F380C,
1246   PREFIX_VEX_0F380D,
1247   PREFIX_VEX_0F380E,
1248   PREFIX_VEX_0F380F,
1249   PREFIX_VEX_0F3813,
1250   PREFIX_VEX_0F3816,
1251   PREFIX_VEX_0F3817,
1252   PREFIX_VEX_0F3818,
1253   PREFIX_VEX_0F3819,
1254   PREFIX_VEX_0F381A,
1255   PREFIX_VEX_0F381C,
1256   PREFIX_VEX_0F381D,
1257   PREFIX_VEX_0F381E,
1258   PREFIX_VEX_0F3820,
1259   PREFIX_VEX_0F3821,
1260   PREFIX_VEX_0F3822,
1261   PREFIX_VEX_0F3823,
1262   PREFIX_VEX_0F3824,
1263   PREFIX_VEX_0F3825,
1264   PREFIX_VEX_0F3828,
1265   PREFIX_VEX_0F3829,
1266   PREFIX_VEX_0F382A,
1267   PREFIX_VEX_0F382B,
1268   PREFIX_VEX_0F382C,
1269   PREFIX_VEX_0F382D,
1270   PREFIX_VEX_0F382E,
1271   PREFIX_VEX_0F382F,
1272   PREFIX_VEX_0F3830,
1273   PREFIX_VEX_0F3831,
1274   PREFIX_VEX_0F3832,
1275   PREFIX_VEX_0F3833,
1276   PREFIX_VEX_0F3834,
1277   PREFIX_VEX_0F3835,
1278   PREFIX_VEX_0F3836,
1279   PREFIX_VEX_0F3837,
1280   PREFIX_VEX_0F3838,
1281   PREFIX_VEX_0F3839,
1282   PREFIX_VEX_0F383A,
1283   PREFIX_VEX_0F383B,
1284   PREFIX_VEX_0F383C,
1285   PREFIX_VEX_0F383D,
1286   PREFIX_VEX_0F383E,
1287   PREFIX_VEX_0F383F,
1288   PREFIX_VEX_0F3840,
1289   PREFIX_VEX_0F3841,
1290   PREFIX_VEX_0F3845,
1291   PREFIX_VEX_0F3846,
1292   PREFIX_VEX_0F3847,
1293   PREFIX_VEX_0F3858,
1294   PREFIX_VEX_0F3859,
1295   PREFIX_VEX_0F385A,
1296   PREFIX_VEX_0F3878,
1297   PREFIX_VEX_0F3879,
1298   PREFIX_VEX_0F388C,
1299   PREFIX_VEX_0F388E,
1300   PREFIX_VEX_0F3890,
1301   PREFIX_VEX_0F3891,
1302   PREFIX_VEX_0F3892,
1303   PREFIX_VEX_0F3893,
1304   PREFIX_VEX_0F3896,
1305   PREFIX_VEX_0F3897,
1306   PREFIX_VEX_0F3898,
1307   PREFIX_VEX_0F3899,
1308   PREFIX_VEX_0F389A,
1309   PREFIX_VEX_0F389B,
1310   PREFIX_VEX_0F389C,
1311   PREFIX_VEX_0F389D,
1312   PREFIX_VEX_0F389E,
1313   PREFIX_VEX_0F389F,
1314   PREFIX_VEX_0F38A6,
1315   PREFIX_VEX_0F38A7,
1316   PREFIX_VEX_0F38A8,
1317   PREFIX_VEX_0F38A9,
1318   PREFIX_VEX_0F38AA,
1319   PREFIX_VEX_0F38AB,
1320   PREFIX_VEX_0F38AC,
1321   PREFIX_VEX_0F38AD,
1322   PREFIX_VEX_0F38AE,
1323   PREFIX_VEX_0F38AF,
1324   PREFIX_VEX_0F38B6,
1325   PREFIX_VEX_0F38B7,
1326   PREFIX_VEX_0F38B8,
1327   PREFIX_VEX_0F38B9,
1328   PREFIX_VEX_0F38BA,
1329   PREFIX_VEX_0F38BB,
1330   PREFIX_VEX_0F38BC,
1331   PREFIX_VEX_0F38BD,
1332   PREFIX_VEX_0F38BE,
1333   PREFIX_VEX_0F38BF,
1334   PREFIX_VEX_0F38CF,
1335   PREFIX_VEX_0F38DB,
1336   PREFIX_VEX_0F38DC,
1337   PREFIX_VEX_0F38DD,
1338   PREFIX_VEX_0F38DE,
1339   PREFIX_VEX_0F38DF,
1340   PREFIX_VEX_0F38F2,
1341   PREFIX_VEX_0F38F3_REG_1,
1342   PREFIX_VEX_0F38F3_REG_2,
1343   PREFIX_VEX_0F38F3_REG_3,
1344   PREFIX_VEX_0F38F5,
1345   PREFIX_VEX_0F38F6,
1346   PREFIX_VEX_0F38F7,
1347   PREFIX_VEX_0F3A00,
1348   PREFIX_VEX_0F3A01,
1349   PREFIX_VEX_0F3A02,
1350   PREFIX_VEX_0F3A04,
1351   PREFIX_VEX_0F3A05,
1352   PREFIX_VEX_0F3A06,
1353   PREFIX_VEX_0F3A08,
1354   PREFIX_VEX_0F3A09,
1355   PREFIX_VEX_0F3A0A,
1356   PREFIX_VEX_0F3A0B,
1357   PREFIX_VEX_0F3A0C,
1358   PREFIX_VEX_0F3A0D,
1359   PREFIX_VEX_0F3A0E,
1360   PREFIX_VEX_0F3A0F,
1361   PREFIX_VEX_0F3A14,
1362   PREFIX_VEX_0F3A15,
1363   PREFIX_VEX_0F3A16,
1364   PREFIX_VEX_0F3A17,
1365   PREFIX_VEX_0F3A18,
1366   PREFIX_VEX_0F3A19,
1367   PREFIX_VEX_0F3A1D,
1368   PREFIX_VEX_0F3A20,
1369   PREFIX_VEX_0F3A21,
1370   PREFIX_VEX_0F3A22,
1371   PREFIX_VEX_0F3A30,
1372   PREFIX_VEX_0F3A31,
1373   PREFIX_VEX_0F3A32,
1374   PREFIX_VEX_0F3A33,
1375   PREFIX_VEX_0F3A38,
1376   PREFIX_VEX_0F3A39,
1377   PREFIX_VEX_0F3A40,
1378   PREFIX_VEX_0F3A41,
1379   PREFIX_VEX_0F3A42,
1380   PREFIX_VEX_0F3A44,
1381   PREFIX_VEX_0F3A46,
1382   PREFIX_VEX_0F3A48,
1383   PREFIX_VEX_0F3A49,
1384   PREFIX_VEX_0F3A4A,
1385   PREFIX_VEX_0F3A4B,
1386   PREFIX_VEX_0F3A4C,
1387   PREFIX_VEX_0F3A5C,
1388   PREFIX_VEX_0F3A5D,
1389   PREFIX_VEX_0F3A5E,
1390   PREFIX_VEX_0F3A5F,
1391   PREFIX_VEX_0F3A60,
1392   PREFIX_VEX_0F3A61,
1393   PREFIX_VEX_0F3A62,
1394   PREFIX_VEX_0F3A63,
1395   PREFIX_VEX_0F3A68,
1396   PREFIX_VEX_0F3A69,
1397   PREFIX_VEX_0F3A6A,
1398   PREFIX_VEX_0F3A6B,
1399   PREFIX_VEX_0F3A6C,
1400   PREFIX_VEX_0F3A6D,
1401   PREFIX_VEX_0F3A6E,
1402   PREFIX_VEX_0F3A6F,
1403   PREFIX_VEX_0F3A78,
1404   PREFIX_VEX_0F3A79,
1405   PREFIX_VEX_0F3A7A,
1406   PREFIX_VEX_0F3A7B,
1407   PREFIX_VEX_0F3A7C,
1408   PREFIX_VEX_0F3A7D,
1409   PREFIX_VEX_0F3A7E,
1410   PREFIX_VEX_0F3A7F,
1411   PREFIX_VEX_0F3ACE,
1412   PREFIX_VEX_0F3ACF,
1413   PREFIX_VEX_0F3ADF,
1414   PREFIX_VEX_0F3AF0,
1415
1416   PREFIX_EVEX_0F10,
1417   PREFIX_EVEX_0F11,
1418   PREFIX_EVEX_0F12,
1419   PREFIX_EVEX_0F16,
1420   PREFIX_EVEX_0F2A,
1421   PREFIX_EVEX_0F2C,
1422   PREFIX_EVEX_0F2D,
1423   PREFIX_EVEX_0F2E,
1424   PREFIX_EVEX_0F2F,
1425   PREFIX_EVEX_0F51,
1426   PREFIX_EVEX_0F58,
1427   PREFIX_EVEX_0F59,
1428   PREFIX_EVEX_0F5A,
1429   PREFIX_EVEX_0F5B,
1430   PREFIX_EVEX_0F5C,
1431   PREFIX_EVEX_0F5D,
1432   PREFIX_EVEX_0F5E,
1433   PREFIX_EVEX_0F5F,
1434   PREFIX_EVEX_0F64,
1435   PREFIX_EVEX_0F65,
1436   PREFIX_EVEX_0F66,
1437   PREFIX_EVEX_0F6E,
1438   PREFIX_EVEX_0F6F,
1439   PREFIX_EVEX_0F70,
1440   PREFIX_EVEX_0F71_REG_2,
1441   PREFIX_EVEX_0F71_REG_4,
1442   PREFIX_EVEX_0F71_REG_6,
1443   PREFIX_EVEX_0F72_REG_0,
1444   PREFIX_EVEX_0F72_REG_1,
1445   PREFIX_EVEX_0F72_REG_2,
1446   PREFIX_EVEX_0F72_REG_4,
1447   PREFIX_EVEX_0F72_REG_6,
1448   PREFIX_EVEX_0F73_REG_2,
1449   PREFIX_EVEX_0F73_REG_3,
1450   PREFIX_EVEX_0F73_REG_6,
1451   PREFIX_EVEX_0F73_REG_7,
1452   PREFIX_EVEX_0F74,
1453   PREFIX_EVEX_0F75,
1454   PREFIX_EVEX_0F76,
1455   PREFIX_EVEX_0F78,
1456   PREFIX_EVEX_0F79,
1457   PREFIX_EVEX_0F7A,
1458   PREFIX_EVEX_0F7B,
1459   PREFIX_EVEX_0F7E,
1460   PREFIX_EVEX_0F7F,
1461   PREFIX_EVEX_0FC2,
1462   PREFIX_EVEX_0FC4,
1463   PREFIX_EVEX_0FC5,
1464   PREFIX_EVEX_0FD6,
1465   PREFIX_EVEX_0FDB,
1466   PREFIX_EVEX_0FDF,
1467   PREFIX_EVEX_0FE2,
1468   PREFIX_EVEX_0FE6,
1469   PREFIX_EVEX_0FE7,
1470   PREFIX_EVEX_0FEB,
1471   PREFIX_EVEX_0FEF,
1472   PREFIX_EVEX_0F380D,
1473   PREFIX_EVEX_0F3810,
1474   PREFIX_EVEX_0F3811,
1475   PREFIX_EVEX_0F3812,
1476   PREFIX_EVEX_0F3813,
1477   PREFIX_EVEX_0F3814,
1478   PREFIX_EVEX_0F3815,
1479   PREFIX_EVEX_0F3816,
1480   PREFIX_EVEX_0F3819,
1481   PREFIX_EVEX_0F381A,
1482   PREFIX_EVEX_0F381B,
1483   PREFIX_EVEX_0F381E,
1484   PREFIX_EVEX_0F381F,
1485   PREFIX_EVEX_0F3820,
1486   PREFIX_EVEX_0F3821,
1487   PREFIX_EVEX_0F3822,
1488   PREFIX_EVEX_0F3823,
1489   PREFIX_EVEX_0F3824,
1490   PREFIX_EVEX_0F3825,
1491   PREFIX_EVEX_0F3826,
1492   PREFIX_EVEX_0F3827,
1493   PREFIX_EVEX_0F3828,
1494   PREFIX_EVEX_0F3829,
1495   PREFIX_EVEX_0F382A,
1496   PREFIX_EVEX_0F382C,
1497   PREFIX_EVEX_0F382D,
1498   PREFIX_EVEX_0F3830,
1499   PREFIX_EVEX_0F3831,
1500   PREFIX_EVEX_0F3832,
1501   PREFIX_EVEX_0F3833,
1502   PREFIX_EVEX_0F3834,
1503   PREFIX_EVEX_0F3835,
1504   PREFIX_EVEX_0F3836,
1505   PREFIX_EVEX_0F3837,
1506   PREFIX_EVEX_0F3838,
1507   PREFIX_EVEX_0F3839,
1508   PREFIX_EVEX_0F383A,
1509   PREFIX_EVEX_0F383B,
1510   PREFIX_EVEX_0F383D,
1511   PREFIX_EVEX_0F383F,
1512   PREFIX_EVEX_0F3840,
1513   PREFIX_EVEX_0F3842,
1514   PREFIX_EVEX_0F3843,
1515   PREFIX_EVEX_0F3844,
1516   PREFIX_EVEX_0F3845,
1517   PREFIX_EVEX_0F3846,
1518   PREFIX_EVEX_0F3847,
1519   PREFIX_EVEX_0F384C,
1520   PREFIX_EVEX_0F384D,
1521   PREFIX_EVEX_0F384E,
1522   PREFIX_EVEX_0F384F,
1523   PREFIX_EVEX_0F3850,
1524   PREFIX_EVEX_0F3851,
1525   PREFIX_EVEX_0F3852,
1526   PREFIX_EVEX_0F3853,
1527   PREFIX_EVEX_0F3854,
1528   PREFIX_EVEX_0F3855,
1529   PREFIX_EVEX_0F3859,
1530   PREFIX_EVEX_0F385A,
1531   PREFIX_EVEX_0F385B,
1532   PREFIX_EVEX_0F3862,
1533   PREFIX_EVEX_0F3863,
1534   PREFIX_EVEX_0F3864,
1535   PREFIX_EVEX_0F3865,
1536   PREFIX_EVEX_0F3866,
1537   PREFIX_EVEX_0F3868,
1538   PREFIX_EVEX_0F3870,
1539   PREFIX_EVEX_0F3871,
1540   PREFIX_EVEX_0F3872,
1541   PREFIX_EVEX_0F3873,
1542   PREFIX_EVEX_0F3875,
1543   PREFIX_EVEX_0F3876,
1544   PREFIX_EVEX_0F3877,
1545   PREFIX_EVEX_0F387A,
1546   PREFIX_EVEX_0F387B,
1547   PREFIX_EVEX_0F387C,
1548   PREFIX_EVEX_0F387D,
1549   PREFIX_EVEX_0F387E,
1550   PREFIX_EVEX_0F387F,
1551   PREFIX_EVEX_0F3883,
1552   PREFIX_EVEX_0F3888,
1553   PREFIX_EVEX_0F3889,
1554   PREFIX_EVEX_0F388A,
1555   PREFIX_EVEX_0F388B,
1556   PREFIX_EVEX_0F388D,
1557   PREFIX_EVEX_0F388F,
1558   PREFIX_EVEX_0F3890,
1559   PREFIX_EVEX_0F3891,
1560   PREFIX_EVEX_0F3892,
1561   PREFIX_EVEX_0F3893,
1562   PREFIX_EVEX_0F389A,
1563   PREFIX_EVEX_0F389B,
1564   PREFIX_EVEX_0F38A0,
1565   PREFIX_EVEX_0F38A1,
1566   PREFIX_EVEX_0F38A2,
1567   PREFIX_EVEX_0F38A3,
1568   PREFIX_EVEX_0F38AA,
1569   PREFIX_EVEX_0F38AB,
1570   PREFIX_EVEX_0F38B4,
1571   PREFIX_EVEX_0F38B5,
1572   PREFIX_EVEX_0F38C4,
1573   PREFIX_EVEX_0F38C6_REG_1,
1574   PREFIX_EVEX_0F38C6_REG_2,
1575   PREFIX_EVEX_0F38C6_REG_5,
1576   PREFIX_EVEX_0F38C6_REG_6,
1577   PREFIX_EVEX_0F38C7_REG_1,
1578   PREFIX_EVEX_0F38C7_REG_2,
1579   PREFIX_EVEX_0F38C7_REG_5,
1580   PREFIX_EVEX_0F38C7_REG_6,
1581   PREFIX_EVEX_0F38C8,
1582   PREFIX_EVEX_0F38CA,
1583   PREFIX_EVEX_0F38CB,
1584   PREFIX_EVEX_0F38CC,
1585   PREFIX_EVEX_0F38CD,
1586
1587   PREFIX_EVEX_0F3A00,
1588   PREFIX_EVEX_0F3A01,
1589   PREFIX_EVEX_0F3A03,
1590   PREFIX_EVEX_0F3A05,
1591   PREFIX_EVEX_0F3A08,
1592   PREFIX_EVEX_0F3A09,
1593   PREFIX_EVEX_0F3A0A,
1594   PREFIX_EVEX_0F3A0B,
1595   PREFIX_EVEX_0F3A14,
1596   PREFIX_EVEX_0F3A15,
1597   PREFIX_EVEX_0F3A16,
1598   PREFIX_EVEX_0F3A17,
1599   PREFIX_EVEX_0F3A18,
1600   PREFIX_EVEX_0F3A19,
1601   PREFIX_EVEX_0F3A1A,
1602   PREFIX_EVEX_0F3A1B,
1603   PREFIX_EVEX_0F3A1E,
1604   PREFIX_EVEX_0F3A1F,
1605   PREFIX_EVEX_0F3A20,
1606   PREFIX_EVEX_0F3A21,
1607   PREFIX_EVEX_0F3A22,
1608   PREFIX_EVEX_0F3A23,
1609   PREFIX_EVEX_0F3A25,
1610   PREFIX_EVEX_0F3A26,
1611   PREFIX_EVEX_0F3A27,
1612   PREFIX_EVEX_0F3A38,
1613   PREFIX_EVEX_0F3A39,
1614   PREFIX_EVEX_0F3A3A,
1615   PREFIX_EVEX_0F3A3B,
1616   PREFIX_EVEX_0F3A3E,
1617   PREFIX_EVEX_0F3A3F,
1618   PREFIX_EVEX_0F3A42,
1619   PREFIX_EVEX_0F3A43,
1620   PREFIX_EVEX_0F3A50,
1621   PREFIX_EVEX_0F3A51,
1622   PREFIX_EVEX_0F3A54,
1623   PREFIX_EVEX_0F3A55,
1624   PREFIX_EVEX_0F3A56,
1625   PREFIX_EVEX_0F3A57,
1626   PREFIX_EVEX_0F3A66,
1627   PREFIX_EVEX_0F3A67,
1628   PREFIX_EVEX_0F3A70,
1629   PREFIX_EVEX_0F3A71,
1630   PREFIX_EVEX_0F3A72,
1631   PREFIX_EVEX_0F3A73,
1632 };
1633
1634 enum
1635 {
1636   X86_64_06 = 0,
1637   X86_64_07,
1638   X86_64_0E,
1639   X86_64_16,
1640   X86_64_17,
1641   X86_64_1E,
1642   X86_64_1F,
1643   X86_64_27,
1644   X86_64_2F,
1645   X86_64_37,
1646   X86_64_3F,
1647   X86_64_60,
1648   X86_64_61,
1649   X86_64_62,
1650   X86_64_63,
1651   X86_64_6D,
1652   X86_64_6F,
1653   X86_64_82,
1654   X86_64_9A,
1655   X86_64_C2,
1656   X86_64_C3,
1657   X86_64_C4,
1658   X86_64_C5,
1659   X86_64_CE,
1660   X86_64_D4,
1661   X86_64_D5,
1662   X86_64_E8,
1663   X86_64_E9,
1664   X86_64_EA,
1665   X86_64_0F01_REG_0,
1666   X86_64_0F01_REG_1,
1667   X86_64_0F01_REG_2,
1668   X86_64_0F01_REG_3
1669 };
1670
1671 enum
1672 {
1673   THREE_BYTE_0F38 = 0,
1674   THREE_BYTE_0F3A
1675 };
1676
1677 enum
1678 {
1679   XOP_08 = 0,
1680   XOP_09,
1681   XOP_0A
1682 };
1683
1684 enum
1685 {
1686   VEX_0F = 0,
1687   VEX_0F38,
1688   VEX_0F3A
1689 };
1690
1691 enum
1692 {
1693   EVEX_0F = 0,
1694   EVEX_0F38,
1695   EVEX_0F3A
1696 };
1697
1698 enum
1699 {
1700   VEX_LEN_0F12_P_0_M_0 = 0,
1701   VEX_LEN_0F12_P_0_M_1,
1702 #define VEX_LEN_0F12_P_2_M_0 VEX_LEN_0F12_P_0_M_0
1703   VEX_LEN_0F13_M_0,
1704   VEX_LEN_0F16_P_0_M_0,
1705   VEX_LEN_0F16_P_0_M_1,
1706 #define VEX_LEN_0F16_P_2_M_0 VEX_LEN_0F16_P_0_M_0
1707   VEX_LEN_0F17_M_0,
1708   VEX_LEN_0F41_P_0,
1709   VEX_LEN_0F41_P_2,
1710   VEX_LEN_0F42_P_0,
1711   VEX_LEN_0F42_P_2,
1712   VEX_LEN_0F44_P_0,
1713   VEX_LEN_0F44_P_2,
1714   VEX_LEN_0F45_P_0,
1715   VEX_LEN_0F45_P_2,
1716   VEX_LEN_0F46_P_0,
1717   VEX_LEN_0F46_P_2,
1718   VEX_LEN_0F47_P_0,
1719   VEX_LEN_0F47_P_2,
1720   VEX_LEN_0F4A_P_0,
1721   VEX_LEN_0F4A_P_2,
1722   VEX_LEN_0F4B_P_0,
1723   VEX_LEN_0F4B_P_2,
1724   VEX_LEN_0F6E_P_2,
1725   VEX_LEN_0F77_P_0,
1726   VEX_LEN_0F7E_P_1,
1727   VEX_LEN_0F7E_P_2,
1728   VEX_LEN_0F90_P_0,
1729   VEX_LEN_0F90_P_2,
1730   VEX_LEN_0F91_P_0,
1731   VEX_LEN_0F91_P_2,
1732   VEX_LEN_0F92_P_0,
1733   VEX_LEN_0F92_P_2,
1734   VEX_LEN_0F92_P_3,
1735   VEX_LEN_0F93_P_0,
1736   VEX_LEN_0F93_P_2,
1737   VEX_LEN_0F93_P_3,
1738   VEX_LEN_0F98_P_0,
1739   VEX_LEN_0F98_P_2,
1740   VEX_LEN_0F99_P_0,
1741   VEX_LEN_0F99_P_2,
1742   VEX_LEN_0FAE_R_2_M_0,
1743   VEX_LEN_0FAE_R_3_M_0,
1744   VEX_LEN_0FC4_P_2,
1745   VEX_LEN_0FC5_P_2,
1746   VEX_LEN_0FD6_P_2,
1747   VEX_LEN_0FF7_P_2,
1748   VEX_LEN_0F3816_P_2,
1749   VEX_LEN_0F3819_P_2,
1750   VEX_LEN_0F381A_P_2_M_0,
1751   VEX_LEN_0F3836_P_2,
1752   VEX_LEN_0F3841_P_2,
1753   VEX_LEN_0F385A_P_2_M_0,
1754   VEX_LEN_0F38DB_P_2,
1755   VEX_LEN_0F38F2_P_0,
1756   VEX_LEN_0F38F3_R_1_P_0,
1757   VEX_LEN_0F38F3_R_2_P_0,
1758   VEX_LEN_0F38F3_R_3_P_0,
1759   VEX_LEN_0F38F5_P_0,
1760   VEX_LEN_0F38F5_P_1,
1761   VEX_LEN_0F38F5_P_3,
1762   VEX_LEN_0F38F6_P_3,
1763   VEX_LEN_0F38F7_P_0,
1764   VEX_LEN_0F38F7_P_1,
1765   VEX_LEN_0F38F7_P_2,
1766   VEX_LEN_0F38F7_P_3,
1767   VEX_LEN_0F3A00_P_2,
1768   VEX_LEN_0F3A01_P_2,
1769   VEX_LEN_0F3A06_P_2,
1770   VEX_LEN_0F3A14_P_2,
1771   VEX_LEN_0F3A15_P_2,
1772   VEX_LEN_0F3A16_P_2,
1773   VEX_LEN_0F3A17_P_2,
1774   VEX_LEN_0F3A18_P_2,
1775   VEX_LEN_0F3A19_P_2,
1776   VEX_LEN_0F3A20_P_2,
1777   VEX_LEN_0F3A21_P_2,
1778   VEX_LEN_0F3A22_P_2,
1779   VEX_LEN_0F3A30_P_2,
1780   VEX_LEN_0F3A31_P_2,
1781   VEX_LEN_0F3A32_P_2,
1782   VEX_LEN_0F3A33_P_2,
1783   VEX_LEN_0F3A38_P_2,
1784   VEX_LEN_0F3A39_P_2,
1785   VEX_LEN_0F3A41_P_2,
1786   VEX_LEN_0F3A46_P_2,
1787   VEX_LEN_0F3A60_P_2,
1788   VEX_LEN_0F3A61_P_2,
1789   VEX_LEN_0F3A62_P_2,
1790   VEX_LEN_0F3A63_P_2,
1791   VEX_LEN_0F3A6A_P_2,
1792   VEX_LEN_0F3A6B_P_2,
1793   VEX_LEN_0F3A6E_P_2,
1794   VEX_LEN_0F3A6F_P_2,
1795   VEX_LEN_0F3A7A_P_2,
1796   VEX_LEN_0F3A7B_P_2,
1797   VEX_LEN_0F3A7E_P_2,
1798   VEX_LEN_0F3A7F_P_2,
1799   VEX_LEN_0F3ADF_P_2,
1800   VEX_LEN_0F3AF0_P_3,
1801   VEX_LEN_0FXOP_08_CC,
1802   VEX_LEN_0FXOP_08_CD,
1803   VEX_LEN_0FXOP_08_CE,
1804   VEX_LEN_0FXOP_08_CF,
1805   VEX_LEN_0FXOP_08_EC,
1806   VEX_LEN_0FXOP_08_ED,
1807   VEX_LEN_0FXOP_08_EE,
1808   VEX_LEN_0FXOP_08_EF,
1809   VEX_LEN_0FXOP_09_82_W_0,
1810   VEX_LEN_0FXOP_09_83_W_0,
1811 };
1812
1813 enum
1814 {
1815   EVEX_LEN_0F6E_P_2 = 0,
1816   EVEX_LEN_0F7E_P_1,
1817   EVEX_LEN_0F7E_P_2,
1818   EVEX_LEN_0FC4_P_2,
1819   EVEX_LEN_0FC5_P_2,
1820   EVEX_LEN_0FD6_P_2,
1821   EVEX_LEN_0F3816_P_2,
1822   EVEX_LEN_0F3819_P_2_W_0,
1823   EVEX_LEN_0F3819_P_2_W_1,
1824   EVEX_LEN_0F381A_P_2_W_0_M_0,
1825   EVEX_LEN_0F381A_P_2_W_1_M_0,
1826   EVEX_LEN_0F381B_P_2_W_0_M_0,
1827   EVEX_LEN_0F381B_P_2_W_1_M_0,
1828   EVEX_LEN_0F3836_P_2,
1829   EVEX_LEN_0F385A_P_2_W_0_M_0,
1830   EVEX_LEN_0F385A_P_2_W_1_M_0,
1831   EVEX_LEN_0F385B_P_2_W_0_M_0,
1832   EVEX_LEN_0F385B_P_2_W_1_M_0,
1833   EVEX_LEN_0F38C6_REG_1_PREFIX_2,
1834   EVEX_LEN_0F38C6_REG_2_PREFIX_2,
1835   EVEX_LEN_0F38C6_REG_5_PREFIX_2,
1836   EVEX_LEN_0F38C6_REG_6_PREFIX_2,
1837   EVEX_LEN_0F38C7_R_1_P_2_W_0,
1838   EVEX_LEN_0F38C7_R_1_P_2_W_1,
1839   EVEX_LEN_0F38C7_R_2_P_2_W_0,
1840   EVEX_LEN_0F38C7_R_2_P_2_W_1,
1841   EVEX_LEN_0F38C7_R_5_P_2_W_0,
1842   EVEX_LEN_0F38C7_R_5_P_2_W_1,
1843   EVEX_LEN_0F38C7_R_6_P_2_W_0,
1844   EVEX_LEN_0F38C7_R_6_P_2_W_1,
1845   EVEX_LEN_0F3A00_P_2_W_1,
1846   EVEX_LEN_0F3A01_P_2_W_1,
1847   EVEX_LEN_0F3A14_P_2,
1848   EVEX_LEN_0F3A15_P_2,
1849   EVEX_LEN_0F3A16_P_2,
1850   EVEX_LEN_0F3A17_P_2,
1851   EVEX_LEN_0F3A18_P_2_W_0,
1852   EVEX_LEN_0F3A18_P_2_W_1,
1853   EVEX_LEN_0F3A19_P_2_W_0,
1854   EVEX_LEN_0F3A19_P_2_W_1,
1855   EVEX_LEN_0F3A1A_P_2_W_0,
1856   EVEX_LEN_0F3A1A_P_2_W_1,
1857   EVEX_LEN_0F3A1B_P_2_W_0,
1858   EVEX_LEN_0F3A1B_P_2_W_1,
1859   EVEX_LEN_0F3A20_P_2,
1860   EVEX_LEN_0F3A21_P_2_W_0,
1861   EVEX_LEN_0F3A22_P_2,
1862   EVEX_LEN_0F3A23_P_2_W_0,
1863   EVEX_LEN_0F3A23_P_2_W_1,
1864   EVEX_LEN_0F3A38_P_2_W_0,
1865   EVEX_LEN_0F3A38_P_2_W_1,
1866   EVEX_LEN_0F3A39_P_2_W_0,
1867   EVEX_LEN_0F3A39_P_2_W_1,
1868   EVEX_LEN_0F3A3A_P_2_W_0,
1869   EVEX_LEN_0F3A3A_P_2_W_1,
1870   EVEX_LEN_0F3A3B_P_2_W_0,
1871   EVEX_LEN_0F3A3B_P_2_W_1,
1872   EVEX_LEN_0F3A43_P_2_W_0,
1873   EVEX_LEN_0F3A43_P_2_W_1
1874 };
1875
1876 enum
1877 {
1878   VEX_W_0F41_P_0_LEN_1 = 0,
1879   VEX_W_0F41_P_2_LEN_1,
1880   VEX_W_0F42_P_0_LEN_1,
1881   VEX_W_0F42_P_2_LEN_1,
1882   VEX_W_0F44_P_0_LEN_0,
1883   VEX_W_0F44_P_2_LEN_0,
1884   VEX_W_0F45_P_0_LEN_1,
1885   VEX_W_0F45_P_2_LEN_1,
1886   VEX_W_0F46_P_0_LEN_1,
1887   VEX_W_0F46_P_2_LEN_1,
1888   VEX_W_0F47_P_0_LEN_1,
1889   VEX_W_0F47_P_2_LEN_1,
1890   VEX_W_0F4A_P_0_LEN_1,
1891   VEX_W_0F4A_P_2_LEN_1,
1892   VEX_W_0F4B_P_0_LEN_1,
1893   VEX_W_0F4B_P_2_LEN_1,
1894   VEX_W_0F90_P_0_LEN_0,
1895   VEX_W_0F90_P_2_LEN_0,
1896   VEX_W_0F91_P_0_LEN_0,
1897   VEX_W_0F91_P_2_LEN_0,
1898   VEX_W_0F92_P_0_LEN_0,
1899   VEX_W_0F92_P_2_LEN_0,
1900   VEX_W_0F93_P_0_LEN_0,
1901   VEX_W_0F93_P_2_LEN_0,
1902   VEX_W_0F98_P_0_LEN_0,
1903   VEX_W_0F98_P_2_LEN_0,
1904   VEX_W_0F99_P_0_LEN_0,
1905   VEX_W_0F99_P_2_LEN_0,
1906   VEX_W_0F380C_P_2,
1907   VEX_W_0F380D_P_2,
1908   VEX_W_0F380E_P_2,
1909   VEX_W_0F380F_P_2,
1910   VEX_W_0F3813_P_2,
1911   VEX_W_0F3816_P_2,
1912   VEX_W_0F3818_P_2,
1913   VEX_W_0F3819_P_2,
1914   VEX_W_0F381A_P_2_M_0,
1915   VEX_W_0F382C_P_2_M_0,
1916   VEX_W_0F382D_P_2_M_0,
1917   VEX_W_0F382E_P_2_M_0,
1918   VEX_W_0F382F_P_2_M_0,
1919   VEX_W_0F3836_P_2,
1920   VEX_W_0F3846_P_2,
1921   VEX_W_0F3858_P_2,
1922   VEX_W_0F3859_P_2,
1923   VEX_W_0F385A_P_2_M_0,
1924   VEX_W_0F3878_P_2,
1925   VEX_W_0F3879_P_2,
1926   VEX_W_0F38CF_P_2,
1927   VEX_W_0F3A00_P_2,
1928   VEX_W_0F3A01_P_2,
1929   VEX_W_0F3A02_P_2,
1930   VEX_W_0F3A04_P_2,
1931   VEX_W_0F3A05_P_2,
1932   VEX_W_0F3A06_P_2,
1933   VEX_W_0F3A18_P_2,
1934   VEX_W_0F3A19_P_2,
1935   VEX_W_0F3A1D_P_2,
1936   VEX_W_0F3A30_P_2_LEN_0,
1937   VEX_W_0F3A31_P_2_LEN_0,
1938   VEX_W_0F3A32_P_2_LEN_0,
1939   VEX_W_0F3A33_P_2_LEN_0,
1940   VEX_W_0F3A38_P_2,
1941   VEX_W_0F3A39_P_2,
1942   VEX_W_0F3A46_P_2,
1943   VEX_W_0F3A4A_P_2,
1944   VEX_W_0F3A4B_P_2,
1945   VEX_W_0F3A4C_P_2,
1946   VEX_W_0F3ACE_P_2,
1947   VEX_W_0F3ACF_P_2,
1948
1949   VEX_W_0FXOP_09_80,
1950   VEX_W_0FXOP_09_81,
1951   VEX_W_0FXOP_09_82,
1952   VEX_W_0FXOP_09_83,
1953
1954   EVEX_W_0F10_P_1,
1955   EVEX_W_0F10_P_3,
1956   EVEX_W_0F11_P_1,
1957   EVEX_W_0F11_P_3,
1958   EVEX_W_0F12_P_0_M_1,
1959   EVEX_W_0F12_P_1,
1960   EVEX_W_0F12_P_3,
1961   EVEX_W_0F16_P_0_M_1,
1962   EVEX_W_0F16_P_1,
1963   EVEX_W_0F2A_P_3,
1964   EVEX_W_0F51_P_1,
1965   EVEX_W_0F51_P_3,
1966   EVEX_W_0F58_P_1,
1967   EVEX_W_0F58_P_3,
1968   EVEX_W_0F59_P_1,
1969   EVEX_W_0F59_P_3,
1970   EVEX_W_0F5A_P_0,
1971   EVEX_W_0F5A_P_1,
1972   EVEX_W_0F5A_P_2,
1973   EVEX_W_0F5A_P_3,
1974   EVEX_W_0F5B_P_0,
1975   EVEX_W_0F5B_P_1,
1976   EVEX_W_0F5B_P_2,
1977   EVEX_W_0F5C_P_1,
1978   EVEX_W_0F5C_P_3,
1979   EVEX_W_0F5D_P_1,
1980   EVEX_W_0F5D_P_3,
1981   EVEX_W_0F5E_P_1,
1982   EVEX_W_0F5E_P_3,
1983   EVEX_W_0F5F_P_1,
1984   EVEX_W_0F5F_P_3,
1985   EVEX_W_0F62,
1986   EVEX_W_0F66_P_2,
1987   EVEX_W_0F6A,
1988   EVEX_W_0F6B,
1989   EVEX_W_0F6C,
1990   EVEX_W_0F6D,
1991   EVEX_W_0F6F_P_1,
1992   EVEX_W_0F6F_P_2,
1993   EVEX_W_0F6F_P_3,
1994   EVEX_W_0F70_P_2,
1995   EVEX_W_0F72_R_2_P_2,
1996   EVEX_W_0F72_R_6_P_2,
1997   EVEX_W_0F73_R_2_P_2,
1998   EVEX_W_0F73_R_6_P_2,
1999   EVEX_W_0F76_P_2,
2000   EVEX_W_0F78_P_0,
2001   EVEX_W_0F78_P_2,
2002   EVEX_W_0F79_P_0,
2003   EVEX_W_0F79_P_2,
2004   EVEX_W_0F7A_P_1,
2005   EVEX_W_0F7A_P_2,
2006   EVEX_W_0F7A_P_3,
2007   EVEX_W_0F7B_P_2,
2008   EVEX_W_0F7B_P_3,
2009   EVEX_W_0F7E_P_1,
2010   EVEX_W_0F7F_P_1,
2011   EVEX_W_0F7F_P_2,
2012   EVEX_W_0F7F_P_3,
2013   EVEX_W_0FC2_P_1,
2014   EVEX_W_0FC2_P_3,
2015   EVEX_W_0FD2,
2016   EVEX_W_0FD3,
2017   EVEX_W_0FD4,
2018   EVEX_W_0FD6_P_2,
2019   EVEX_W_0FE6_P_1,
2020   EVEX_W_0FE6_P_2,
2021   EVEX_W_0FE6_P_3,
2022   EVEX_W_0FE7_P_2,
2023   EVEX_W_0FF2,
2024   EVEX_W_0FF3,
2025   EVEX_W_0FF4,
2026   EVEX_W_0FFA,
2027   EVEX_W_0FFB,
2028   EVEX_W_0FFE,
2029   EVEX_W_0F380D_P_2,
2030   EVEX_W_0F3810_P_1,
2031   EVEX_W_0F3810_P_2,
2032   EVEX_W_0F3811_P_1,
2033   EVEX_W_0F3811_P_2,
2034   EVEX_W_0F3812_P_1,
2035   EVEX_W_0F3812_P_2,
2036   EVEX_W_0F3813_P_1,
2037   EVEX_W_0F3813_P_2,
2038   EVEX_W_0F3814_P_1,
2039   EVEX_W_0F3815_P_1,
2040   EVEX_W_0F3819_P_2,
2041   EVEX_W_0F381A_P_2,
2042   EVEX_W_0F381B_P_2,
2043   EVEX_W_0F381E_P_2,
2044   EVEX_W_0F381F_P_2,
2045   EVEX_W_0F3820_P_1,
2046   EVEX_W_0F3821_P_1,
2047   EVEX_W_0F3822_P_1,
2048   EVEX_W_0F3823_P_1,
2049   EVEX_W_0F3824_P_1,
2050   EVEX_W_0F3825_P_1,
2051   EVEX_W_0F3825_P_2,
2052   EVEX_W_0F3828_P_2,
2053   EVEX_W_0F3829_P_2,
2054   EVEX_W_0F382A_P_1,
2055   EVEX_W_0F382A_P_2,
2056   EVEX_W_0F382B,
2057   EVEX_W_0F3830_P_1,
2058   EVEX_W_0F3831_P_1,
2059   EVEX_W_0F3832_P_1,
2060   EVEX_W_0F3833_P_1,
2061   EVEX_W_0F3834_P_1,
2062   EVEX_W_0F3835_P_1,
2063   EVEX_W_0F3835_P_2,
2064   EVEX_W_0F3837_P_2,
2065   EVEX_W_0F383A_P_1,
2066   EVEX_W_0F3852_P_1,
2067   EVEX_W_0F3859_P_2,
2068   EVEX_W_0F385A_P_2,
2069   EVEX_W_0F385B_P_2,
2070   EVEX_W_0F3862_P_2,
2071   EVEX_W_0F3863_P_2,
2072   EVEX_W_0F3870_P_2,
2073   EVEX_W_0F3872_P_1,
2074   EVEX_W_0F3872_P_2,
2075   EVEX_W_0F3872_P_3,
2076   EVEX_W_0F387A_P_2,
2077   EVEX_W_0F387B_P_2,
2078   EVEX_W_0F3883_P_2,
2079   EVEX_W_0F3891_P_2,
2080   EVEX_W_0F3893_P_2,
2081   EVEX_W_0F38A1_P_2,
2082   EVEX_W_0F38A3_P_2,
2083   EVEX_W_0F38C7_R_1_P_2,
2084   EVEX_W_0F38C7_R_2_P_2,
2085   EVEX_W_0F38C7_R_5_P_2,
2086   EVEX_W_0F38C7_R_6_P_2,
2087
2088   EVEX_W_0F3A00_P_2,
2089   EVEX_W_0F3A01_P_2,
2090   EVEX_W_0F3A05_P_2,
2091   EVEX_W_0F3A08_P_2,
2092   EVEX_W_0F3A09_P_2,
2093   EVEX_W_0F3A0A_P_2,
2094   EVEX_W_0F3A0B_P_2,
2095   EVEX_W_0F3A18_P_2,
2096   EVEX_W_0F3A19_P_2,
2097   EVEX_W_0F3A1A_P_2,
2098   EVEX_W_0F3A1B_P_2,
2099   EVEX_W_0F3A21_P_2,
2100   EVEX_W_0F3A23_P_2,
2101   EVEX_W_0F3A38_P_2,
2102   EVEX_W_0F3A39_P_2,
2103   EVEX_W_0F3A3A_P_2,
2104   EVEX_W_0F3A3B_P_2,
2105   EVEX_W_0F3A42_P_2,
2106   EVEX_W_0F3A43_P_2,
2107   EVEX_W_0F3A70_P_2,
2108   EVEX_W_0F3A72_P_2,
2109 };
2110
2111 typedef void (*op_rtn) (int bytemode, int sizeflag);
2112
2113 struct dis386 {
2114   const char *name;
2115   struct
2116     {
2117       op_rtn rtn;
2118       int bytemode;
2119     } op[MAX_OPERANDS];
2120   unsigned int prefix_requirement;
2121 };
2122
2123 /* Upper case letters in the instruction names here are macros.
2124    'A' => print 'b' if no register operands or suffix_always is true
2125    'B' => print 'b' if suffix_always is true
2126    'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2127           size prefix
2128    'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2129           suffix_always is true
2130    'E' => print 'e' if 32-bit form of jcxz
2131    'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2132    'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2133    'H' => print ",pt" or ",pn" branch hint
2134    'I' unused.
2135    'J' unused.
2136    'K' => print 'd' or 'q' if rex prefix is present.
2137    'L' => print 'l' if suffix_always is true
2138    'M' => print 'r' if intel_mnemonic is false.
2139    'N' => print 'n' if instruction has no wait "prefix"
2140    'O' => print 'd' or 'o' (or 'q' in Intel mode)
2141    'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2142           or suffix_always is true.  print 'q' if rex prefix is present.
2143    'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2144           is true
2145    'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2146    'S' => print 'w', 'l' or 'q' if suffix_always is true
2147    'T' => print 'q' in 64bit mode if instruction has no operand size
2148           prefix and behave as 'P' otherwise
2149    'U' => print 'q' in 64bit mode if instruction has no operand size
2150           prefix and behave as 'Q' otherwise
2151    'V' => print 'q' in 64bit mode if instruction has no operand size
2152           prefix and behave as 'S' otherwise
2153    'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2154    'X' => print 's', 'd' depending on data16 prefix (for XMM)
2155    'Y' unused.
2156    'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2157    '!' => change condition from true to false or from false to true.
2158    '%' => add 1 upper case letter to the macro.
2159    '^' => print 'w', 'l', or 'q' (Intel64 ISA only) depending on operand size
2160           prefix or suffix_always is true (lcall/ljmp).
2161    '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending
2162           on operand size prefix.
2163    '&' => print 'q' in 64bit mode for Intel64 ISA or if instruction
2164           has no operand size prefix for AMD64 ISA, behave as 'P'
2165           otherwise
2166
2167    2 upper case letter macros:
2168    "XY" => print 'x' or 'y' if suffix_always is true or no register
2169            operands and no broadcast.
2170    "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
2171            register operands and no broadcast.
2172    "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2173    "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory
2174            operand or no operand at all in 64bit mode, or if suffix_always
2175            is true.
2176    "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2177    "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2178    "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2179    "LW" => print 'd', 'q' depending on the VEX.W bit
2180    "BW" => print 'b' or 'w' depending on the EVEX.W bit
2181    "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
2182            an operand size prefix, or suffix_always is true.  print
2183            'q' if rex prefix is present.
2184
2185    Many of the above letters print nothing in Intel mode.  See "putop"
2186    for the details.
2187
2188    Braces '{' and '}', and vertical bars '|', indicate alternative
2189    mnemonic strings for AT&T and Intel.  */
2190
2191 static const struct dis386 dis386[] = {
2192   /* 00 */
2193   { "addB",             { Ebh1, Gb }, 0 },
2194   { "addS",             { Evh1, Gv }, 0 },
2195   { "addB",             { Gb, EbS }, 0 },
2196   { "addS",             { Gv, EvS }, 0 },
2197   { "addB",             { AL, Ib }, 0 },
2198   { "addS",             { eAX, Iv }, 0 },
2199   { X86_64_TABLE (X86_64_06) },
2200   { X86_64_TABLE (X86_64_07) },
2201   /* 08 */
2202   { "orB",              { Ebh1, Gb }, 0 },
2203   { "orS",              { Evh1, Gv }, 0 },
2204   { "orB",              { Gb, EbS }, 0 },
2205   { "orS",              { Gv, EvS }, 0 },
2206   { "orB",              { AL, Ib }, 0 },
2207   { "orS",              { eAX, Iv }, 0 },
2208   { X86_64_TABLE (X86_64_0E) },
2209   { Bad_Opcode },       /* 0x0f extended opcode escape */
2210   /* 10 */
2211   { "adcB",             { Ebh1, Gb }, 0 },
2212   { "adcS",             { Evh1, Gv }, 0 },
2213   { "adcB",             { Gb, EbS }, 0 },
2214   { "adcS",             { Gv, EvS }, 0 },
2215   { "adcB",             { AL, Ib }, 0 },
2216   { "adcS",             { eAX, Iv }, 0 },
2217   { X86_64_TABLE (X86_64_16) },
2218   { X86_64_TABLE (X86_64_17) },
2219   /* 18 */
2220   { "sbbB",             { Ebh1, Gb }, 0 },
2221   { "sbbS",             { Evh1, Gv }, 0 },
2222   { "sbbB",             { Gb, EbS }, 0 },
2223   { "sbbS",             { Gv, EvS }, 0 },
2224   { "sbbB",             { AL, Ib }, 0 },
2225   { "sbbS",             { eAX, Iv }, 0 },
2226   { X86_64_TABLE (X86_64_1E) },
2227   { X86_64_TABLE (X86_64_1F) },
2228   /* 20 */
2229   { "andB",             { Ebh1, Gb }, 0 },
2230   { "andS",             { Evh1, Gv }, 0 },
2231   { "andB",             { Gb, EbS }, 0 },
2232   { "andS",             { Gv, EvS }, 0 },
2233   { "andB",             { AL, Ib }, 0 },
2234   { "andS",             { eAX, Iv }, 0 },
2235   { Bad_Opcode },       /* SEG ES prefix */
2236   { X86_64_TABLE (X86_64_27) },
2237   /* 28 */
2238   { "subB",             { Ebh1, Gb }, 0 },
2239   { "subS",             { Evh1, Gv }, 0 },
2240   { "subB",             { Gb, EbS }, 0 },
2241   { "subS",             { Gv, EvS }, 0 },
2242   { "subB",             { AL, Ib }, 0 },
2243   { "subS",             { eAX, Iv }, 0 },
2244   { Bad_Opcode },       /* SEG CS prefix */
2245   { X86_64_TABLE (X86_64_2F) },
2246   /* 30 */
2247   { "xorB",             { Ebh1, Gb }, 0 },
2248   { "xorS",             { Evh1, Gv }, 0 },
2249   { "xorB",             { Gb, EbS }, 0 },
2250   { "xorS",             { Gv, EvS }, 0 },
2251   { "xorB",             { AL, Ib }, 0 },
2252   { "xorS",             { eAX, Iv }, 0 },
2253   { Bad_Opcode },       /* SEG SS prefix */
2254   { X86_64_TABLE (X86_64_37) },
2255   /* 38 */
2256   { "cmpB",             { Eb, Gb }, 0 },
2257   { "cmpS",             { Ev, Gv }, 0 },
2258   { "cmpB",             { Gb, EbS }, 0 },
2259   { "cmpS",             { Gv, EvS }, 0 },
2260   { "cmpB",             { AL, Ib }, 0 },
2261   { "cmpS",             { eAX, Iv }, 0 },
2262   { Bad_Opcode },       /* SEG DS prefix */
2263   { X86_64_TABLE (X86_64_3F) },
2264   /* 40 */
2265   { "inc{S|}",          { RMeAX }, 0 },
2266   { "inc{S|}",          { RMeCX }, 0 },
2267   { "inc{S|}",          { RMeDX }, 0 },
2268   { "inc{S|}",          { RMeBX }, 0 },
2269   { "inc{S|}",          { RMeSP }, 0 },
2270   { "inc{S|}",          { RMeBP }, 0 },
2271   { "inc{S|}",          { RMeSI }, 0 },
2272   { "inc{S|}",          { RMeDI }, 0 },
2273   /* 48 */
2274   { "dec{S|}",          { RMeAX }, 0 },
2275   { "dec{S|}",          { RMeCX }, 0 },
2276   { "dec{S|}",          { RMeDX }, 0 },
2277   { "dec{S|}",          { RMeBX }, 0 },
2278   { "dec{S|}",          { RMeSP }, 0 },
2279   { "dec{S|}",          { RMeBP }, 0 },
2280   { "dec{S|}",          { RMeSI }, 0 },
2281   { "dec{S|}",          { RMeDI }, 0 },
2282   /* 50 */
2283   { "pushV",            { RMrAX }, 0 },
2284   { "pushV",            { RMrCX }, 0 },
2285   { "pushV",            { RMrDX }, 0 },
2286   { "pushV",            { RMrBX }, 0 },
2287   { "pushV",            { RMrSP }, 0 },
2288   { "pushV",            { RMrBP }, 0 },
2289   { "pushV",            { RMrSI }, 0 },
2290   { "pushV",            { RMrDI }, 0 },
2291   /* 58 */
2292   { "popV",             { RMrAX }, 0 },
2293   { "popV",             { RMrCX }, 0 },
2294   { "popV",             { RMrDX }, 0 },
2295   { "popV",             { RMrBX }, 0 },
2296   { "popV",             { RMrSP }, 0 },
2297   { "popV",             { RMrBP }, 0 },
2298   { "popV",             { RMrSI }, 0 },
2299   { "popV",             { RMrDI }, 0 },
2300   /* 60 */
2301   { X86_64_TABLE (X86_64_60) },
2302   { X86_64_TABLE (X86_64_61) },
2303   { X86_64_TABLE (X86_64_62) },
2304   { X86_64_TABLE (X86_64_63) },
2305   { Bad_Opcode },       /* seg fs */
2306   { Bad_Opcode },       /* seg gs */
2307   { Bad_Opcode },       /* op size prefix */
2308   { Bad_Opcode },       /* adr size prefix */
2309   /* 68 */
2310   { "pushT",            { sIv }, 0 },
2311   { "imulS",            { Gv, Ev, Iv }, 0 },
2312   { "pushT",            { sIbT }, 0 },
2313   { "imulS",            { Gv, Ev, sIb }, 0 },
2314   { "ins{b|}",          { Ybr, indirDX }, 0 },
2315   { X86_64_TABLE (X86_64_6D) },
2316   { "outs{b|}",         { indirDXr, Xb }, 0 },
2317   { X86_64_TABLE (X86_64_6F) },
2318   /* 70 */
2319   { "joH",              { Jb, BND, cond_jump_flag }, 0 },
2320   { "jnoH",             { Jb, BND, cond_jump_flag }, 0 },
2321   { "jbH",              { Jb, BND, cond_jump_flag }, 0 },
2322   { "jaeH",             { Jb, BND, cond_jump_flag }, 0 },
2323   { "jeH",              { Jb, BND, cond_jump_flag }, 0 },
2324   { "jneH",             { Jb, BND, cond_jump_flag }, 0 },
2325   { "jbeH",             { Jb, BND, cond_jump_flag }, 0 },
2326   { "jaH",              { Jb, BND, cond_jump_flag }, 0 },
2327   /* 78 */
2328   { "jsH",              { Jb, BND, cond_jump_flag }, 0 },
2329   { "jnsH",             { Jb, BND, cond_jump_flag }, 0 },
2330   { "jpH",              { Jb, BND, cond_jump_flag }, 0 },
2331   { "jnpH",             { Jb, BND, cond_jump_flag }, 0 },
2332   { "jlH",              { Jb, BND, cond_jump_flag }, 0 },
2333   { "jgeH",             { Jb, BND, cond_jump_flag }, 0 },
2334   { "jleH",             { Jb, BND, cond_jump_flag }, 0 },
2335   { "jgH",              { Jb, BND, cond_jump_flag }, 0 },
2336   /* 80 */
2337   { REG_TABLE (REG_80) },
2338   { REG_TABLE (REG_81) },
2339   { X86_64_TABLE (X86_64_82) },
2340   { REG_TABLE (REG_83) },
2341   { "testB",            { Eb, Gb }, 0 },
2342   { "testS",            { Ev, Gv }, 0 },
2343   { "xchgB",            { Ebh2, Gb }, 0 },
2344   { "xchgS",            { Evh2, Gv }, 0 },
2345   /* 88 */
2346   { "movB",             { Ebh3, Gb }, 0 },
2347   { "movS",             { Evh3, Gv }, 0 },
2348   { "movB",             { Gb, EbS }, 0 },
2349   { "movS",             { Gv, EvS }, 0 },
2350   { "movD",             { Sv, Sw }, 0 },
2351   { MOD_TABLE (MOD_8D) },
2352   { "movD",             { Sw, Sv }, 0 },
2353   { REG_TABLE (REG_8F) },
2354   /* 90 */
2355   { PREFIX_TABLE (PREFIX_90) },
2356   { "xchgS",            { RMeCX, eAX }, 0 },
2357   { "xchgS",            { RMeDX, eAX }, 0 },
2358   { "xchgS",            { RMeBX, eAX }, 0 },
2359   { "xchgS",            { RMeSP, eAX }, 0 },
2360   { "xchgS",            { RMeBP, eAX }, 0 },
2361   { "xchgS",            { RMeSI, eAX }, 0 },
2362   { "xchgS",            { RMeDI, eAX }, 0 },
2363   /* 98 */
2364   { "cW{t|}R",          { XX }, 0 },
2365   { "cR{t|}O",          { XX }, 0 },
2366   { X86_64_TABLE (X86_64_9A) },
2367   { Bad_Opcode },       /* fwait */
2368   { "pushfT",           { XX }, 0 },
2369   { "popfT",            { XX }, 0 },
2370   { "sahf",             { XX }, 0 },
2371   { "lahf",             { XX }, 0 },
2372   /* a0 */
2373   { "mov%LB",           { AL, Ob }, 0 },
2374   { "mov%LS",           { eAX, Ov }, 0 },
2375   { "mov%LB",           { Ob, AL }, 0 },
2376   { "mov%LS",           { Ov, eAX }, 0 },
2377   { "movs{b|}",         { Ybr, Xb }, 0 },
2378   { "movs{R|}",         { Yvr, Xv }, 0 },
2379   { "cmps{b|}",         { Xb, Yb }, 0 },
2380   { "cmps{R|}",         { Xv, Yv }, 0 },
2381   /* a8 */
2382   { "testB",            { AL, Ib }, 0 },
2383   { "testS",            { eAX, Iv }, 0 },
2384   { "stosB",            { Ybr, AL }, 0 },
2385   { "stosS",            { Yvr, eAX }, 0 },
2386   { "lodsB",            { ALr, Xb }, 0 },
2387   { "lodsS",            { eAXr, Xv }, 0 },
2388   { "scasB",            { AL, Yb }, 0 },
2389   { "scasS",            { eAX, Yv }, 0 },
2390   /* b0 */
2391   { "movB",             { RMAL, Ib }, 0 },
2392   { "movB",             { RMCL, Ib }, 0 },
2393   { "movB",             { RMDL, Ib }, 0 },
2394   { "movB",             { RMBL, Ib }, 0 },
2395   { "movB",             { RMAH, Ib }, 0 },
2396   { "movB",             { RMCH, Ib }, 0 },
2397   { "movB",             { RMDH, Ib }, 0 },
2398   { "movB",             { RMBH, Ib }, 0 },
2399   /* b8 */
2400   { "mov%LV",           { RMeAX, Iv64 }, 0 },
2401   { "mov%LV",           { RMeCX, Iv64 }, 0 },
2402   { "mov%LV",           { RMeDX, Iv64 }, 0 },
2403   { "mov%LV",           { RMeBX, Iv64 }, 0 },
2404   { "mov%LV",           { RMeSP, Iv64 }, 0 },
2405   { "mov%LV",           { RMeBP, Iv64 }, 0 },
2406   { "mov%LV",           { RMeSI, Iv64 }, 0 },
2407   { "mov%LV",           { RMeDI, Iv64 }, 0 },
2408   /* c0 */
2409   { REG_TABLE (REG_C0) },
2410   { REG_TABLE (REG_C1) },
2411   { X86_64_TABLE (X86_64_C2) },
2412   { X86_64_TABLE (X86_64_C3) },
2413   { X86_64_TABLE (X86_64_C4) },
2414   { X86_64_TABLE (X86_64_C5) },
2415   { REG_TABLE (REG_C6) },
2416   { REG_TABLE (REG_C7) },
2417   /* c8 */
2418   { "enterT",           { Iw, Ib }, 0 },
2419   { "leaveT",           { XX }, 0 },
2420   { "{l|}ret{|f}P",     { Iw }, 0 },
2421   { "{l|}ret{|f}P",     { XX }, 0 },
2422   { "int3",             { XX }, 0 },
2423   { "int",              { Ib }, 0 },
2424   { X86_64_TABLE (X86_64_CE) },
2425   { "iret%LP",          { XX }, 0 },
2426   /* d0 */
2427   { REG_TABLE (REG_D0) },
2428   { REG_TABLE (REG_D1) },
2429   { REG_TABLE (REG_D2) },
2430   { REG_TABLE (REG_D3) },
2431   { X86_64_TABLE (X86_64_D4) },
2432   { X86_64_TABLE (X86_64_D5) },
2433   { Bad_Opcode },
2434   { "xlat",             { DSBX }, 0 },
2435   /* d8 */
2436   { FLOAT },
2437   { FLOAT },
2438   { FLOAT },
2439   { FLOAT },
2440   { FLOAT },
2441   { FLOAT },
2442   { FLOAT },
2443   { FLOAT },
2444   /* e0 */
2445   { "loopneFH",         { Jb, XX, loop_jcxz_flag }, 0 },
2446   { "loopeFH",          { Jb, XX, loop_jcxz_flag }, 0 },
2447   { "loopFH",           { Jb, XX, loop_jcxz_flag }, 0 },
2448   { "jEcxzH",           { Jb, XX, loop_jcxz_flag }, 0 },
2449   { "inB",              { AL, Ib }, 0 },
2450   { "inG",              { zAX, Ib }, 0 },
2451   { "outB",             { Ib, AL }, 0 },
2452   { "outG",             { Ib, zAX }, 0 },
2453   /* e8 */
2454   { X86_64_TABLE (X86_64_E8) },
2455   { X86_64_TABLE (X86_64_E9) },
2456   { X86_64_TABLE (X86_64_EA) },
2457   { "jmp",              { Jb, BND }, 0 },
2458   { "inB",              { AL, indirDX }, 0 },
2459   { "inG",              { zAX, indirDX }, 0 },
2460   { "outB",             { indirDX, AL }, 0 },
2461   { "outG",             { indirDX, zAX }, 0 },
2462   /* f0 */
2463   { Bad_Opcode },       /* lock prefix */
2464   { "icebp",            { XX }, 0 },
2465   { Bad_Opcode },       /* repne */
2466   { Bad_Opcode },       /* repz */
2467   { "hlt",              { XX }, 0 },
2468   { "cmc",              { XX }, 0 },
2469   { REG_TABLE (REG_F6) },
2470   { REG_TABLE (REG_F7) },
2471   /* f8 */
2472   { "clc",              { XX }, 0 },
2473   { "stc",              { XX }, 0 },
2474   { "cli",              { XX }, 0 },
2475   { "sti",              { XX }, 0 },
2476   { "cld",              { XX }, 0 },
2477   { "std",              { XX }, 0 },
2478   { REG_TABLE (REG_FE) },
2479   { REG_TABLE (REG_FF) },
2480 };
2481
2482 static const struct dis386 dis386_twobyte[] = {
2483   /* 00 */
2484   { REG_TABLE (REG_0F00 ) },
2485   { REG_TABLE (REG_0F01 ) },
2486   { "larS",             { Gv, Ew }, 0 },
2487   { "lslS",             { Gv, Ew }, 0 },
2488   { Bad_Opcode },
2489   { "syscall",          { XX }, 0 },
2490   { "clts",             { XX }, 0 },
2491   { "sysret%LQ",                { XX }, 0 },
2492   /* 08 */
2493   { "invd",             { XX }, 0 },
2494   { PREFIX_TABLE (PREFIX_0F09) },
2495   { Bad_Opcode },
2496   { "ud2",              { XX }, 0 },
2497   { Bad_Opcode },
2498   { REG_TABLE (REG_0F0D) },
2499   { "femms",            { XX }, 0 },
2500   { "",                 { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix.  */
2501   /* 10 */
2502   { PREFIX_TABLE (PREFIX_0F10) },
2503   { PREFIX_TABLE (PREFIX_0F11) },
2504   { PREFIX_TABLE (PREFIX_0F12) },
2505   { MOD_TABLE (MOD_0F13) },
2506   { "unpcklpX",         { XM, EXx }, PREFIX_OPCODE },
2507   { "unpckhpX",         { XM, EXx }, PREFIX_OPCODE },
2508   { PREFIX_TABLE (PREFIX_0F16) },
2509   { MOD_TABLE (MOD_0F17) },
2510   /* 18 */
2511   { REG_TABLE (REG_0F18) },
2512   { "nopQ",             { Ev }, 0 },
2513   { PREFIX_TABLE (PREFIX_0F1A) },
2514   { PREFIX_TABLE (PREFIX_0F1B) },
2515   { PREFIX_TABLE (PREFIX_0F1C) },
2516   { "nopQ",             { Ev }, 0 },
2517   { PREFIX_TABLE (PREFIX_0F1E) },
2518   { "nopQ",             { Ev }, 0 },
2519   /* 20 */
2520   { "movZ",             { Rm, Cm }, 0 },
2521   { "movZ",             { Rm, Dm }, 0 },
2522   { "movZ",             { Cm, Rm }, 0 },
2523   { "movZ",             { Dm, Rm }, 0 },
2524   { MOD_TABLE (MOD_0F24) },
2525   { Bad_Opcode },
2526   { MOD_TABLE (MOD_0F26) },
2527   { Bad_Opcode },
2528   /* 28 */
2529   { "movapX",           { XM, EXx }, PREFIX_OPCODE },
2530   { "movapX",           { EXxS, XM }, PREFIX_OPCODE },
2531   { PREFIX_TABLE (PREFIX_0F2A) },
2532   { PREFIX_TABLE (PREFIX_0F2B) },
2533   { PREFIX_TABLE (PREFIX_0F2C) },
2534   { PREFIX_TABLE (PREFIX_0F2D) },
2535   { PREFIX_TABLE (PREFIX_0F2E) },
2536   { PREFIX_TABLE (PREFIX_0F2F) },
2537   /* 30 */
2538   { "wrmsr",            { XX }, 0 },
2539   { "rdtsc",            { XX }, 0 },
2540   { "rdmsr",            { XX }, 0 },
2541   { "rdpmc",            { XX }, 0 },
2542   { "sysenter",         { SEP }, 0 },
2543   { "sysexit",          { SEP }, 0 },
2544   { Bad_Opcode },
2545   { "getsec",           { XX }, 0 },
2546   /* 38 */
2547   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) },
2548   { Bad_Opcode },
2549   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) },
2550   { Bad_Opcode },
2551   { Bad_Opcode },
2552   { Bad_Opcode },
2553   { Bad_Opcode },
2554   { Bad_Opcode },
2555   /* 40 */
2556   { "cmovoS",           { Gv, Ev }, 0 },
2557   { "cmovnoS",          { Gv, Ev }, 0 },
2558   { "cmovbS",           { Gv, Ev }, 0 },
2559   { "cmovaeS",          { Gv, Ev }, 0 },
2560   { "cmoveS",           { Gv, Ev }, 0 },
2561   { "cmovneS",          { Gv, Ev }, 0 },
2562   { "cmovbeS",          { Gv, Ev }, 0 },
2563   { "cmovaS",           { Gv, Ev }, 0 },
2564   /* 48 */
2565   { "cmovsS",           { Gv, Ev }, 0 },
2566   { "cmovnsS",          { Gv, Ev }, 0 },
2567   { "cmovpS",           { Gv, Ev }, 0 },
2568   { "cmovnpS",          { Gv, Ev }, 0 },
2569   { "cmovlS",           { Gv, Ev }, 0 },
2570   { "cmovgeS",          { Gv, Ev }, 0 },
2571   { "cmovleS",          { Gv, Ev }, 0 },
2572   { "cmovgS",           { Gv, Ev }, 0 },
2573   /* 50 */
2574   { MOD_TABLE (MOD_0F50) },
2575   { PREFIX_TABLE (PREFIX_0F51) },
2576   { PREFIX_TABLE (PREFIX_0F52) },
2577   { PREFIX_TABLE (PREFIX_0F53) },
2578   { "andpX",            { XM, EXx }, PREFIX_OPCODE },
2579   { "andnpX",           { XM, EXx }, PREFIX_OPCODE },
2580   { "orpX",             { XM, EXx }, PREFIX_OPCODE },
2581   { "xorpX",            { XM, EXx }, PREFIX_OPCODE },
2582   /* 58 */
2583   { PREFIX_TABLE (PREFIX_0F58) },
2584   { PREFIX_TABLE (PREFIX_0F59) },
2585   { PREFIX_TABLE (PREFIX_0F5A) },
2586   { PREFIX_TABLE (PREFIX_0F5B) },
2587   { PREFIX_TABLE (PREFIX_0F5C) },
2588   { PREFIX_TABLE (PREFIX_0F5D) },
2589   { PREFIX_TABLE (PREFIX_0F5E) },
2590   { PREFIX_TABLE (PREFIX_0F5F) },
2591   /* 60 */
2592   { PREFIX_TABLE (PREFIX_0F60) },
2593   { PREFIX_TABLE (PREFIX_0F61) },
2594   { PREFIX_TABLE (PREFIX_0F62) },
2595   { "packsswb",         { MX, EM }, PREFIX_OPCODE },
2596   { "pcmpgtb",          { MX, EM }, PREFIX_OPCODE },
2597   { "pcmpgtw",          { MX, EM }, PREFIX_OPCODE },
2598   { "pcmpgtd",          { MX, EM }, PREFIX_OPCODE },
2599   { "packuswb",         { MX, EM }, PREFIX_OPCODE },
2600   /* 68 */
2601   { "punpckhbw",        { MX, EM }, PREFIX_OPCODE },
2602   { "punpckhwd",        { MX, EM }, PREFIX_OPCODE },
2603   { "punpckhdq",        { MX, EM }, PREFIX_OPCODE },
2604   { "packssdw",         { MX, EM }, PREFIX_OPCODE },
2605   { PREFIX_TABLE (PREFIX_0F6C) },
2606   { PREFIX_TABLE (PREFIX_0F6D) },
2607   { "movK",             { MX, Edq }, PREFIX_OPCODE },
2608   { PREFIX_TABLE (PREFIX_0F6F) },
2609   /* 70 */
2610   { PREFIX_TABLE (PREFIX_0F70) },
2611   { REG_TABLE (REG_0F71) },
2612   { REG_TABLE (REG_0F72) },
2613   { REG_TABLE (REG_0F73) },
2614   { "pcmpeqb",          { MX, EM }, PREFIX_OPCODE },
2615   { "pcmpeqw",          { MX, EM }, PREFIX_OPCODE },
2616   { "pcmpeqd",          { MX, EM }, PREFIX_OPCODE },
2617   { "emms",             { XX }, PREFIX_OPCODE },
2618   /* 78 */
2619   { PREFIX_TABLE (PREFIX_0F78) },
2620   { PREFIX_TABLE (PREFIX_0F79) },
2621   { Bad_Opcode },
2622   { Bad_Opcode },
2623   { PREFIX_TABLE (PREFIX_0F7C) },
2624   { PREFIX_TABLE (PREFIX_0F7D) },
2625   { PREFIX_TABLE (PREFIX_0F7E) },
2626   { PREFIX_TABLE (PREFIX_0F7F) },
2627   /* 80 */
2628   { "joH",              { Jv, BND, cond_jump_flag }, 0 },
2629   { "jnoH",             { Jv, BND, cond_jump_flag }, 0 },
2630   { "jbH",              { Jv, BND, cond_jump_flag }, 0 },
2631   { "jaeH",             { Jv, BND, cond_jump_flag }, 0 },
2632   { "jeH",              { Jv, BND, cond_jump_flag }, 0 },
2633   { "jneH",             { Jv, BND, cond_jump_flag }, 0 },
2634   { "jbeH",             { Jv, BND, cond_jump_flag }, 0 },
2635   { "jaH",              { Jv, BND, cond_jump_flag }, 0 },
2636   /* 88 */
2637   { "jsH",              { Jv, BND, cond_jump_flag }, 0 },
2638   { "jnsH",             { Jv, BND, cond_jump_flag }, 0 },
2639   { "jpH",              { Jv, BND, cond_jump_flag }, 0 },
2640   { "jnpH",             { Jv, BND, cond_jump_flag }, 0 },
2641   { "jlH",              { Jv, BND, cond_jump_flag }, 0 },
2642   { "jgeH",             { Jv, BND, cond_jump_flag }, 0 },
2643   { "jleH",             { Jv, BND, cond_jump_flag }, 0 },
2644   { "jgH",              { Jv, BND, cond_jump_flag }, 0 },
2645   /* 90 */
2646   { "seto",             { Eb }, 0 },
2647   { "setno",            { Eb }, 0 },
2648   { "setb",             { Eb }, 0 },
2649   { "setae",            { Eb }, 0 },
2650   { "sete",             { Eb }, 0 },
2651   { "setne",            { Eb }, 0 },
2652   { "setbe",            { Eb }, 0 },
2653   { "seta",             { Eb }, 0 },
2654   /* 98 */
2655   { "sets",             { Eb }, 0 },
2656   { "setns",            { Eb }, 0 },
2657   { "setp",             { Eb }, 0 },
2658   { "setnp",            { Eb }, 0 },
2659   { "setl",             { Eb }, 0 },
2660   { "setge",            { Eb }, 0 },
2661   { "setle",            { Eb }, 0 },
2662   { "setg",             { Eb }, 0 },
2663   /* a0 */
2664   { "pushT",            { fs }, 0 },
2665   { "popT",             { fs }, 0 },
2666   { "cpuid",            { XX }, 0 },
2667   { "btS",              { Ev, Gv }, 0 },
2668   { "shldS",            { Ev, Gv, Ib }, 0 },
2669   { "shldS",            { Ev, Gv, CL }, 0 },
2670   { REG_TABLE (REG_0FA6) },
2671   { REG_TABLE (REG_0FA7) },
2672   /* a8 */
2673   { "pushT",            { gs }, 0 },
2674   { "popT",             { gs }, 0 },
2675   { "rsm",              { XX }, 0 },
2676   { "btsS",             { Evh1, Gv }, 0 },
2677   { "shrdS",            { Ev, Gv, Ib }, 0 },
2678   { "shrdS",            { Ev, Gv, CL }, 0 },
2679   { REG_TABLE (REG_0FAE) },
2680   { "imulS",            { Gv, Ev }, 0 },
2681   /* b0 */
2682   { "cmpxchgB",         { Ebh1, Gb }, 0 },
2683   { "cmpxchgS",         { Evh1, Gv }, 0 },
2684   { MOD_TABLE (MOD_0FB2) },
2685   { "btrS",             { Evh1, Gv }, 0 },
2686   { MOD_TABLE (MOD_0FB4) },
2687   { MOD_TABLE (MOD_0FB5) },
2688   { "movz{bR|x}",       { Gv, Eb }, 0 },
2689   { "movz{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movzww ! */
2690   /* b8 */
2691   { PREFIX_TABLE (PREFIX_0FB8) },
2692   { "ud1S",             { Gv, Ev }, 0 },
2693   { REG_TABLE (REG_0FBA) },
2694   { "btcS",             { Evh1, Gv }, 0 },
2695   { PREFIX_TABLE (PREFIX_0FBC) },
2696   { PREFIX_TABLE (PREFIX_0FBD) },
2697   { "movs{bR|x}",       { Gv, Eb }, 0 },
2698   { "movs{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movsww ! */
2699   /* c0 */
2700   { "xaddB",            { Ebh1, Gb }, 0 },
2701   { "xaddS",            { Evh1, Gv }, 0 },
2702   { PREFIX_TABLE (PREFIX_0FC2) },
2703   { MOD_TABLE (MOD_0FC3) },
2704   { "pinsrw",           { MX, Edqw, Ib }, PREFIX_OPCODE },
2705   { "pextrw",           { Gdq, MS, Ib }, PREFIX_OPCODE },
2706   { "shufpX",           { XM, EXx, Ib }, PREFIX_OPCODE },
2707   { REG_TABLE (REG_0FC7) },
2708   /* c8 */
2709   { "bswap",            { RMeAX }, 0 },
2710   { "bswap",            { RMeCX }, 0 },
2711   { "bswap",            { RMeDX }, 0 },
2712   { "bswap",            { RMeBX }, 0 },
2713   { "bswap",            { RMeSP }, 0 },
2714   { "bswap",            { RMeBP }, 0 },
2715   { "bswap",            { RMeSI }, 0 },
2716   { "bswap",            { RMeDI }, 0 },
2717   /* d0 */
2718   { PREFIX_TABLE (PREFIX_0FD0) },
2719   { "psrlw",            { MX, EM }, PREFIX_OPCODE },
2720   { "psrld",            { MX, EM }, PREFIX_OPCODE },
2721   { "psrlq",            { MX, EM }, PREFIX_OPCODE },
2722   { "paddq",            { MX, EM }, PREFIX_OPCODE },
2723   { "pmullw",           { MX, EM }, PREFIX_OPCODE },
2724   { PREFIX_TABLE (PREFIX_0FD6) },
2725   { MOD_TABLE (MOD_0FD7) },
2726   /* d8 */
2727   { "psubusb",          { MX, EM }, PREFIX_OPCODE },
2728   { "psubusw",          { MX, EM }, PREFIX_OPCODE },
2729   { "pminub",           { MX, EM }, PREFIX_OPCODE },
2730   { "pand",             { MX, EM }, PREFIX_OPCODE },
2731   { "paddusb",          { MX, EM }, PREFIX_OPCODE },
2732   { "paddusw",          { MX, EM }, PREFIX_OPCODE },
2733   { "pmaxub",           { MX, EM }, PREFIX_OPCODE },
2734   { "pandn",            { MX, EM }, PREFIX_OPCODE },
2735   /* e0 */
2736   { "pavgb",            { MX, EM }, PREFIX_OPCODE },
2737   { "psraw",            { MX, EM }, PREFIX_OPCODE },
2738   { "psrad",            { MX, EM }, PREFIX_OPCODE },
2739   { "pavgw",            { MX, EM }, PREFIX_OPCODE },
2740   { "pmulhuw",          { MX, EM }, PREFIX_OPCODE },
2741   { "pmulhw",           { MX, EM }, PREFIX_OPCODE },
2742   { PREFIX_TABLE (PREFIX_0FE6) },
2743   { PREFIX_TABLE (PREFIX_0FE7) },
2744   /* e8 */
2745   { "psubsb",           { MX, EM }, PREFIX_OPCODE },
2746   { "psubsw",           { MX, EM }, PREFIX_OPCODE },
2747   { "pminsw",           { MX, EM }, PREFIX_OPCODE },
2748   { "por",              { MX, EM }, PREFIX_OPCODE },
2749   { "paddsb",           { MX, EM }, PREFIX_OPCODE },
2750   { "paddsw",           { MX, EM }, PREFIX_OPCODE },
2751   { "pmaxsw",           { MX, EM }, PREFIX_OPCODE },
2752   { "pxor",             { MX, EM }, PREFIX_OPCODE },
2753   /* f0 */
2754   { PREFIX_TABLE (PREFIX_0FF0) },
2755   { "psllw",            { MX, EM }, PREFIX_OPCODE },
2756   { "pslld",            { MX, EM }, PREFIX_OPCODE },
2757   { "psllq",            { MX, EM }, PREFIX_OPCODE },
2758   { "pmuludq",          { MX, EM }, PREFIX_OPCODE },
2759   { "pmaddwd",          { MX, EM }, PREFIX_OPCODE },
2760   { "psadbw",           { MX, EM }, PREFIX_OPCODE },
2761   { PREFIX_TABLE (PREFIX_0FF7) },
2762   /* f8 */
2763   { "psubb",            { MX, EM }, PREFIX_OPCODE },
2764   { "psubw",            { MX, EM }, PREFIX_OPCODE },
2765   { "psubd",            { MX, EM }, PREFIX_OPCODE },
2766   { "psubq",            { MX, EM }, PREFIX_OPCODE },
2767   { "paddb",            { MX, EM }, PREFIX_OPCODE },
2768   { "paddw",            { MX, EM }, PREFIX_OPCODE },
2769   { "paddd",            { MX, EM }, PREFIX_OPCODE },
2770   { "ud0S",             { Gv, Ev }, 0 },
2771 };
2772
2773 static const unsigned char onebyte_has_modrm[256] = {
2774   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2775   /*       -------------------------------        */
2776   /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2777   /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2778   /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2779   /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2780   /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2781   /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2782   /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2783   /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2784   /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2785   /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2786   /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2787   /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2788   /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2789   /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2790   /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2791   /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1  /* f0 */
2792   /*       -------------------------------        */
2793   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2794 };
2795
2796 static const unsigned char twobyte_has_modrm[256] = {
2797   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2798   /*       -------------------------------        */
2799   /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2800   /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2801   /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2802   /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2803   /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2804   /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2805   /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2806   /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2807   /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2808   /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2809   /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2810   /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */
2811   /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2812   /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2813   /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2814   /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1  /* ff */
2815   /*       -------------------------------        */
2816   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2817 };
2818
2819 static char obuf[100];
2820 static char *obufp;
2821 static char *mnemonicendp;
2822 static char scratchbuf[100];
2823 static unsigned char *start_codep;
2824 static unsigned char *insn_codep;
2825 static unsigned char *codep;
2826 static unsigned char *end_codep;
2827 static int last_lock_prefix;
2828 static int last_repz_prefix;
2829 static int last_repnz_prefix;
2830 static int last_data_prefix;
2831 static int last_addr_prefix;
2832 static int last_rex_prefix;
2833 static int last_seg_prefix;
2834 static int fwait_prefix;
2835 /* The active segment register prefix.  */
2836 static int active_seg_prefix;
2837 #define MAX_CODE_LENGTH 15
2838 /* We can up to 14 prefixes since the maximum instruction length is
2839    15bytes.  */
2840 static int all_prefixes[MAX_CODE_LENGTH - 1];
2841 static disassemble_info *the_info;
2842 static struct
2843   {
2844     int mod;
2845     int reg;
2846     int rm;
2847   }
2848 modrm;
2849 static unsigned char need_modrm;
2850 static struct
2851   {
2852     int scale;
2853     int index;
2854     int base;
2855   }
2856 sib;
2857 static struct
2858   {
2859     int register_specifier;
2860     int length;
2861     int prefix;
2862     int w;
2863     int evex;
2864     int r;
2865     int v;
2866     int mask_register_specifier;
2867     int zeroing;
2868     int ll;
2869     int b;
2870   }
2871 vex;
2872 static unsigned char need_vex;
2873 static unsigned char need_vex_reg;
2874
2875 struct op
2876   {
2877     const char *name;
2878     unsigned int len;
2879   };
2880
2881 /* If we are accessing mod/rm/reg without need_modrm set, then the
2882    values are stale.  Hitting this abort likely indicates that you
2883    need to update onebyte_has_modrm or twobyte_has_modrm.  */
2884 #define MODRM_CHECK  if (!need_modrm) abort ()
2885
2886 static const char **names64;
2887 static const char **names32;
2888 static const char **names16;
2889 static const char **names8;
2890 static const char **names8rex;
2891 static const char **names_seg;
2892 static const char *index64;
2893 static const char *index32;
2894 static const char **index16;
2895 static const char **names_bnd;
2896
2897 static const char *intel_names64[] = {
2898   "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
2899   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
2900 };
2901 static const char *intel_names32[] = {
2902   "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
2903   "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
2904 };
2905 static const char *intel_names16[] = {
2906   "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
2907   "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
2908 };
2909 static const char *intel_names8[] = {
2910   "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
2911 };
2912 static const char *intel_names8rex[] = {
2913   "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
2914   "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
2915 };
2916 static const char *intel_names_seg[] = {
2917   "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
2918 };
2919 static const char *intel_index64 = "riz";
2920 static const char *intel_index32 = "eiz";
2921 static const char *intel_index16[] = {
2922   "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
2923 };
2924
2925 static const char *att_names64[] = {
2926   "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
2927   "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
2928 };
2929 static const char *att_names32[] = {
2930   "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
2931   "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
2932 };
2933 static const char *att_names16[] = {
2934   "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
2935   "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
2936 };
2937 static const char *att_names8[] = {
2938   "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
2939 };
2940 static const char *att_names8rex[] = {
2941   "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
2942   "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
2943 };
2944 static const char *att_names_seg[] = {
2945   "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
2946 };
2947 static const char *att_index64 = "%riz";
2948 static const char *att_index32 = "%eiz";
2949 static const char *att_index16[] = {
2950   "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
2951 };
2952
2953 static const char **names_mm;
2954 static const char *intel_names_mm[] = {
2955   "mm0", "mm1", "mm2", "mm3",
2956   "mm4", "mm5", "mm6", "mm7"
2957 };
2958 static const char *att_names_mm[] = {
2959   "%mm0", "%mm1", "%mm2", "%mm3",
2960   "%mm4", "%mm5", "%mm6", "%mm7"
2961 };
2962
2963 static const char *intel_names_bnd[] = {
2964   "bnd0", "bnd1", "bnd2", "bnd3"
2965 };
2966
2967 static const char *att_names_bnd[] = {
2968   "%bnd0", "%bnd1", "%bnd2", "%bnd3"
2969 };
2970
2971 static const char **names_xmm;
2972 static const char *intel_names_xmm[] = {
2973   "xmm0", "xmm1", "xmm2", "xmm3",
2974   "xmm4", "xmm5", "xmm6", "xmm7",
2975   "xmm8", "xmm9", "xmm10", "xmm11",
2976   "xmm12", "xmm13", "xmm14", "xmm15",
2977   "xmm16", "xmm17", "xmm18", "xmm19",
2978   "xmm20", "xmm21", "xmm22", "xmm23",
2979   "xmm24", "xmm25", "xmm26", "xmm27",
2980   "xmm28", "xmm29", "xmm30", "xmm31"
2981 };
2982 static const char *att_names_xmm[] = {
2983   "%xmm0", "%xmm1", "%xmm2", "%xmm3",
2984   "%xmm4", "%xmm5", "%xmm6", "%xmm7",
2985   "%xmm8", "%xmm9", "%xmm10", "%xmm11",
2986   "%xmm12", "%xmm13", "%xmm14", "%xmm15",
2987   "%xmm16", "%xmm17", "%xmm18", "%xmm19",
2988   "%xmm20", "%xmm21", "%xmm22", "%xmm23",
2989   "%xmm24", "%xmm25", "%xmm26", "%xmm27",
2990   "%xmm28", "%xmm29", "%xmm30", "%xmm31"
2991 };
2992
2993 static const char **names_ymm;
2994 static const char *intel_names_ymm[] = {
2995   "ymm0", "ymm1", "ymm2", "ymm3",
2996   "ymm4", "ymm5", "ymm6", "ymm7",
2997   "ymm8", "ymm9", "ymm10", "ymm11",
2998   "ymm12", "ymm13", "ymm14", "ymm15",
2999   "ymm16", "ymm17", "ymm18", "ymm19",
3000   "ymm20", "ymm21", "ymm22", "ymm23",
3001   "ymm24", "ymm25", "ymm26", "ymm27",
3002   "ymm28", "ymm29", "ymm30", "ymm31"
3003 };
3004 static const char *att_names_ymm[] = {
3005   "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3006   "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3007   "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3008   "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3009   "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3010   "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3011   "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3012   "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3013 };
3014
3015 static const char **names_zmm;
3016 static const char *intel_names_zmm[] = {
3017   "zmm0", "zmm1", "zmm2", "zmm3",
3018   "zmm4", "zmm5", "zmm6", "zmm7",
3019   "zmm8", "zmm9", "zmm10", "zmm11",
3020   "zmm12", "zmm13", "zmm14", "zmm15",
3021   "zmm16", "zmm17", "zmm18", "zmm19",
3022   "zmm20", "zmm21", "zmm22", "zmm23",
3023   "zmm24", "zmm25", "zmm26", "zmm27",
3024   "zmm28", "zmm29", "zmm30", "zmm31"
3025 };
3026 static const char *att_names_zmm[] = {
3027   "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3028   "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3029   "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3030   "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3031   "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3032   "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3033   "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3034   "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3035 };
3036
3037 static const char **names_mask;
3038 static const char *intel_names_mask[] = {
3039   "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3040 };
3041 static const char *att_names_mask[] = {
3042   "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3043 };
3044
3045 static const char *names_rounding[] =
3046 {
3047   "{rn-sae}",
3048   "{rd-sae}",
3049   "{ru-sae}",
3050   "{rz-sae}"
3051 };
3052
3053 static const struct dis386 reg_table[][8] = {
3054   /* REG_80 */
3055   {
3056     { "addA",   { Ebh1, Ib }, 0 },
3057     { "orA",    { Ebh1, Ib }, 0 },
3058     { "adcA",   { Ebh1, Ib }, 0 },
3059     { "sbbA",   { Ebh1, Ib }, 0 },
3060     { "andA",   { Ebh1, Ib }, 0 },
3061     { "subA",   { Ebh1, Ib }, 0 },
3062     { "xorA",   { Ebh1, Ib }, 0 },
3063     { "cmpA",   { Eb, Ib }, 0 },
3064   },
3065   /* REG_81 */
3066   {
3067     { "addQ",   { Evh1, Iv }, 0 },
3068     { "orQ",    { Evh1, Iv }, 0 },
3069     { "adcQ",   { Evh1, Iv }, 0 },
3070     { "sbbQ",   { Evh1, Iv }, 0 },
3071     { "andQ",   { Evh1, Iv }, 0 },
3072     { "subQ",   { Evh1, Iv }, 0 },
3073     { "xorQ",   { Evh1, Iv }, 0 },
3074     { "cmpQ",   { Ev, Iv }, 0 },
3075   },
3076   /* REG_83 */
3077   {
3078     { "addQ",   { Evh1, sIb }, 0 },
3079     { "orQ",    { Evh1, sIb }, 0 },
3080     { "adcQ",   { Evh1, sIb }, 0 },
3081     { "sbbQ",   { Evh1, sIb }, 0 },
3082     { "andQ",   { Evh1, sIb }, 0 },
3083     { "subQ",   { Evh1, sIb }, 0 },
3084     { "xorQ",   { Evh1, sIb }, 0 },
3085     { "cmpQ",   { Ev, sIb }, 0 },
3086   },
3087   /* REG_8F */
3088   {
3089     { "popU",   { stackEv }, 0 },
3090     { XOP_8F_TABLE (XOP_09) },
3091     { Bad_Opcode },
3092     { Bad_Opcode },
3093     { Bad_Opcode },
3094     { XOP_8F_TABLE (XOP_09) },
3095   },
3096   /* REG_C0 */
3097   {
3098     { "rolA",   { Eb, Ib }, 0 },
3099     { "rorA",   { Eb, Ib }, 0 },
3100     { "rclA",   { Eb, Ib }, 0 },
3101     { "rcrA",   { Eb, Ib }, 0 },
3102     { "shlA",   { Eb, Ib }, 0 },
3103     { "shrA",   { Eb, Ib }, 0 },
3104     { "shlA",   { Eb, Ib }, 0 },
3105     { "sarA",   { Eb, Ib }, 0 },
3106   },
3107   /* REG_C1 */
3108   {
3109     { "rolQ",   { Ev, Ib }, 0 },
3110     { "rorQ",   { Ev, Ib }, 0 },
3111     { "rclQ",   { Ev, Ib }, 0 },
3112     { "rcrQ",   { Ev, Ib }, 0 },
3113     { "shlQ",   { Ev, Ib }, 0 },
3114     { "shrQ",   { Ev, Ib }, 0 },
3115     { "shlQ",   { Ev, Ib }, 0 },
3116     { "sarQ",   { Ev, Ib }, 0 },
3117   },
3118   /* REG_C6 */
3119   {
3120     { "movA",   { Ebh3, Ib }, 0 },
3121     { Bad_Opcode },
3122     { Bad_Opcode },
3123     { Bad_Opcode },
3124     { Bad_Opcode },
3125     { Bad_Opcode },
3126     { Bad_Opcode },
3127     { MOD_TABLE (MOD_C6_REG_7) },
3128   },
3129   /* REG_C7 */
3130   {
3131     { "movQ",   { Evh3, Iv }, 0 },
3132     { Bad_Opcode },
3133     { Bad_Opcode },
3134     { Bad_Opcode },
3135     { Bad_Opcode },
3136     { Bad_Opcode },
3137     { Bad_Opcode },
3138     { MOD_TABLE (MOD_C7_REG_7) },
3139   },
3140   /* REG_D0 */
3141   {
3142     { "rolA",   { Eb, I1 }, 0 },
3143     { "rorA",   { Eb, I1 }, 0 },
3144     { "rclA",   { Eb, I1 }, 0 },
3145     { "rcrA",   { Eb, I1 }, 0 },
3146     { "shlA",   { Eb, I1 }, 0 },
3147     { "shrA",   { Eb, I1 }, 0 },
3148     { "shlA",   { Eb, I1 }, 0 },
3149     { "sarA",   { Eb, I1 }, 0 },
3150   },
3151   /* REG_D1 */
3152   {
3153     { "rolQ",   { Ev, I1 }, 0 },
3154     { "rorQ",   { Ev, I1 }, 0 },
3155     { "rclQ",   { Ev, I1 }, 0 },
3156     { "rcrQ",   { Ev, I1 }, 0 },
3157     { "shlQ",   { Ev, I1 }, 0 },
3158     { "shrQ",   { Ev, I1 }, 0 },
3159     { "shlQ",   { Ev, I1 }, 0 },
3160     { "sarQ",   { Ev, I1 }, 0 },
3161   },
3162   /* REG_D2 */
3163   {
3164     { "rolA",   { Eb, CL }, 0 },
3165     { "rorA",   { Eb, CL }, 0 },
3166     { "rclA",   { Eb, CL }, 0 },
3167     { "rcrA",   { Eb, CL }, 0 },
3168     { "shlA",   { Eb, CL }, 0 },
3169     { "shrA",   { Eb, CL }, 0 },
3170     { "shlA",   { Eb, CL }, 0 },
3171     { "sarA",   { Eb, CL }, 0 },
3172   },
3173   /* REG_D3 */
3174   {
3175     { "rolQ",   { Ev, CL }, 0 },
3176     { "rorQ",   { Ev, CL }, 0 },
3177     { "rclQ",   { Ev, CL }, 0 },
3178     { "rcrQ",   { Ev, CL }, 0 },
3179     { "shlQ",   { Ev, CL }, 0 },
3180     { "shrQ",   { Ev, CL }, 0 },
3181     { "shlQ",   { Ev, CL }, 0 },
3182     { "sarQ",   { Ev, CL }, 0 },
3183   },
3184   /* REG_F6 */
3185   {
3186     { "testA",  { Eb, Ib }, 0 },
3187     { "testA",  { Eb, Ib }, 0 },
3188     { "notA",   { Ebh1 }, 0 },
3189     { "negA",   { Ebh1 }, 0 },
3190     { "mulA",   { Eb }, 0 },    /* Don't print the implicit %al register,  */
3191     { "imulA",  { Eb }, 0 },    /* to distinguish these opcodes from other */
3192     { "divA",   { Eb }, 0 },    /* mul/imul opcodes.  Do the same for div  */
3193     { "idivA",  { Eb }, 0 },    /* and idiv for consistency.               */
3194   },
3195   /* REG_F7 */
3196   {
3197     { "testQ",  { Ev, Iv }, 0 },
3198     { "testQ",  { Ev, Iv }, 0 },
3199     { "notQ",   { Evh1 }, 0 },
3200     { "negQ",   { Evh1 }, 0 },
3201     { "mulQ",   { Ev }, 0 },    /* Don't print the implicit register.  */
3202     { "imulQ",  { Ev }, 0 },
3203     { "divQ",   { Ev }, 0 },
3204     { "idivQ",  { Ev }, 0 },
3205   },
3206   /* REG_FE */
3207   {
3208     { "incA",   { Ebh1 }, 0 },
3209     { "decA",   { Ebh1 }, 0 },
3210   },
3211   /* REG_FF */
3212   {
3213     { "incQ",   { Evh1 }, 0 },
3214     { "decQ",   { Evh1 }, 0 },
3215     { "call{&|}", { NOTRACK, indirEv, BND }, 0 },
3216     { MOD_TABLE (MOD_FF_REG_3) },
3217     { "jmp{&|}", { NOTRACK, indirEv, BND }, 0 },
3218     { MOD_TABLE (MOD_FF_REG_5) },
3219     { "pushU",  { stackEv }, 0 },
3220     { Bad_Opcode },
3221   },
3222   /* REG_0F00 */
3223   {
3224     { "sldtD",  { Sv }, 0 },
3225     { "strD",   { Sv }, 0 },
3226     { "lldt",   { Ew }, 0 },
3227     { "ltr",    { Ew }, 0 },
3228     { "verr",   { Ew }, 0 },
3229     { "verw",   { Ew }, 0 },
3230     { Bad_Opcode },
3231     { Bad_Opcode },
3232   },
3233   /* REG_0F01 */
3234   {
3235     { MOD_TABLE (MOD_0F01_REG_0) },
3236     { MOD_TABLE (MOD_0F01_REG_1) },
3237     { MOD_TABLE (MOD_0F01_REG_2) },
3238     { MOD_TABLE (MOD_0F01_REG_3) },
3239     { "smswD",  { Sv }, 0 },
3240     { MOD_TABLE (MOD_0F01_REG_5) },
3241     { "lmsw",   { Ew }, 0 },
3242     { MOD_TABLE (MOD_0F01_REG_7) },
3243   },
3244   /* REG_0F0D */
3245   {
3246     { "prefetch",       { Mb }, 0 },
3247     { "prefetchw",      { Mb }, 0 },
3248     { "prefetchwt1",    { Mb }, 0 },
3249     { "prefetch",       { Mb }, 0 },
3250     { "prefetch",       { Mb }, 0 },
3251     { "prefetch",       { Mb }, 0 },
3252     { "prefetch",       { Mb }, 0 },
3253     { "prefetch",       { Mb }, 0 },
3254   },
3255   /* REG_0F18 */
3256   {
3257     { MOD_TABLE (MOD_0F18_REG_0) },
3258     { MOD_TABLE (MOD_0F18_REG_1) },
3259     { MOD_TABLE (MOD_0F18_REG_2) },
3260     { MOD_TABLE (MOD_0F18_REG_3) },
3261     { MOD_TABLE (MOD_0F18_REG_4) },
3262     { MOD_TABLE (MOD_0F18_REG_5) },
3263     { MOD_TABLE (MOD_0F18_REG_6) },
3264     { MOD_TABLE (MOD_0F18_REG_7) },
3265   },
3266   /* REG_0F1C_P_0_MOD_0 */
3267   {
3268     { "cldemote",       { Mb }, 0 },
3269     { "nopQ",           { Ev }, 0 },
3270     { "nopQ",           { Ev }, 0 },
3271     { "nopQ",           { Ev }, 0 },
3272     { "nopQ",           { Ev }, 0 },
3273     { "nopQ",           { Ev }, 0 },
3274     { "nopQ",           { Ev }, 0 },
3275     { "nopQ",           { Ev }, 0 },
3276   },
3277   /* REG_0F1E_P_1_MOD_3 */
3278   {
3279     { "nopQ",           { Ev }, 0 },
3280     { "rdsspK",         { Rdq }, PREFIX_OPCODE },
3281     { "nopQ",           { Ev }, 0 },
3282     { "nopQ",           { Ev }, 0 },
3283     { "nopQ",           { Ev }, 0 },
3284     { "nopQ",           { Ev }, 0 },
3285     { "nopQ",           { Ev }, 0 },
3286     { RM_TABLE (RM_0F1E_P_1_MOD_3_REG_7) },
3287   },
3288   /* REG_0F71 */
3289   {
3290     { Bad_Opcode },
3291     { Bad_Opcode },
3292     { MOD_TABLE (MOD_0F71_REG_2) },
3293     { Bad_Opcode },
3294     { MOD_TABLE (MOD_0F71_REG_4) },
3295     { Bad_Opcode },
3296     { MOD_TABLE (MOD_0F71_REG_6) },
3297   },
3298   /* REG_0F72 */
3299   {
3300     { Bad_Opcode },
3301     { Bad_Opcode },
3302     { MOD_TABLE (MOD_0F72_REG_2) },
3303     { Bad_Opcode },
3304     { MOD_TABLE (MOD_0F72_REG_4) },
3305     { Bad_Opcode },
3306     { MOD_TABLE (MOD_0F72_REG_6) },
3307   },
3308   /* REG_0F73 */
3309   {
3310     { Bad_Opcode },
3311     { Bad_Opcode },
3312     { MOD_TABLE (MOD_0F73_REG_2) },
3313     { MOD_TABLE (MOD_0F73_REG_3) },
3314     { Bad_Opcode },
3315     { Bad_Opcode },
3316     { MOD_TABLE (MOD_0F73_REG_6) },
3317     { MOD_TABLE (MOD_0F73_REG_7) },
3318   },
3319   /* REG_0FA6 */
3320   {
3321     { "montmul",        { { OP_0f07, 0 } }, 0 },
3322     { "xsha1",          { { OP_0f07, 0 } }, 0 },
3323     { "xsha256",        { { OP_0f07, 0 } }, 0 },
3324   },
3325   /* REG_0FA7 */
3326   {
3327     { "xstore-rng",     { { OP_0f07, 0 } }, 0 },
3328     { "xcrypt-ecb",     { { OP_0f07, 0 } }, 0 },
3329     { "xcrypt-cbc",     { { OP_0f07, 0 } }, 0 },
3330     { "xcrypt-ctr",     { { OP_0f07, 0 } }, 0 },
3331     { "xcrypt-cfb",     { { OP_0f07, 0 } }, 0 },
3332     { "xcrypt-ofb",     { { OP_0f07, 0 } }, 0 },
3333   },
3334   /* REG_0FAE */
3335   {
3336     { MOD_TABLE (MOD_0FAE_REG_0) },
3337     { MOD_TABLE (MOD_0FAE_REG_1) },
3338     { MOD_TABLE (MOD_0FAE_REG_2) },
3339     { MOD_TABLE (MOD_0FAE_REG_3) },
3340     { MOD_TABLE (MOD_0FAE_REG_4) },
3341     { MOD_TABLE (MOD_0FAE_REG_5) },
3342     { MOD_TABLE (MOD_0FAE_REG_6) },
3343     { MOD_TABLE (MOD_0FAE_REG_7) },
3344   },
3345   /* REG_0FBA */
3346   {
3347     { Bad_Opcode },
3348     { Bad_Opcode },
3349     { Bad_Opcode },
3350     { Bad_Opcode },
3351     { "btQ",    { Ev, Ib }, 0 },
3352     { "btsQ",   { Evh1, Ib }, 0 },
3353     { "btrQ",   { Evh1, Ib }, 0 },
3354     { "btcQ",   { Evh1, Ib }, 0 },
3355   },
3356   /* REG_0FC7 */
3357   {
3358     { Bad_Opcode },
3359     { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 },
3360     { Bad_Opcode },
3361     { MOD_TABLE (MOD_0FC7_REG_3) },
3362     { MOD_TABLE (MOD_0FC7_REG_4) },
3363     { MOD_TABLE (MOD_0FC7_REG_5) },
3364     { MOD_TABLE (MOD_0FC7_REG_6) },
3365     { MOD_TABLE (MOD_0FC7_REG_7) },
3366   },
3367   /* REG_VEX_0F71 */
3368   {
3369     { Bad_Opcode },
3370     { Bad_Opcode },
3371     { MOD_TABLE (MOD_VEX_0F71_REG_2) },
3372     { Bad_Opcode },
3373     { MOD_TABLE (MOD_VEX_0F71_REG_4) },
3374     { Bad_Opcode },
3375     { MOD_TABLE (MOD_VEX_0F71_REG_6) },
3376   },
3377   /* REG_VEX_0F72 */
3378   {
3379     { Bad_Opcode },
3380     { Bad_Opcode },
3381     { MOD_TABLE (MOD_VEX_0F72_REG_2) },
3382     { Bad_Opcode },
3383     { MOD_TABLE (MOD_VEX_0F72_REG_4) },
3384     { Bad_Opcode },
3385     { MOD_TABLE (MOD_VEX_0F72_REG_6) },
3386   },
3387   /* REG_VEX_0F73 */
3388   {
3389     { Bad_Opcode },
3390     { Bad_Opcode },
3391     { MOD_TABLE (MOD_VEX_0F73_REG_2) },
3392     { MOD_TABLE (MOD_VEX_0F73_REG_3) },
3393     { Bad_Opcode },
3394     { Bad_Opcode },
3395     { MOD_TABLE (MOD_VEX_0F73_REG_6) },
3396     { MOD_TABLE (MOD_VEX_0F73_REG_7) },
3397   },
3398   /* REG_VEX_0FAE */
3399   {
3400     { Bad_Opcode },
3401     { Bad_Opcode },
3402     { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
3403     { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
3404   },
3405   /* REG_VEX_0F38F3 */
3406   {
3407     { Bad_Opcode },
3408     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) },
3409     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) },
3410     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) },
3411   },
3412   /* REG_XOP_LWPCB */
3413   {
3414     { "llwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3415     { "slwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3416   },
3417   /* REG_XOP_LWP */
3418   {
3419     { "lwpins", { { OP_LWP_E, 0 }, Ed, Id }, 0 },
3420     { "lwpval", { { OP_LWP_E, 0 }, Ed, Id }, 0 },
3421   },
3422   /* REG_XOP_TBM_01 */
3423   {
3424     { Bad_Opcode },
3425     { "blcfill",        { { OP_LWP_E, 0 }, Edq }, 0 },
3426     { "blsfill",        { { OP_LWP_E, 0 }, Edq }, 0 },
3427     { "blcs",   { { OP_LWP_E, 0 }, Edq }, 0 },
3428     { "tzmsk",  { { OP_LWP_E, 0 }, Edq }, 0 },
3429     { "blcic",  { { OP_LWP_E, 0 }, Edq }, 0 },
3430     { "blsic",  { { OP_LWP_E, 0 }, Edq }, 0 },
3431     { "t1mskc", { { OP_LWP_E, 0 }, Edq }, 0 },
3432   },
3433   /* REG_XOP_TBM_02 */
3434   {
3435     { Bad_Opcode },
3436     { "blcmsk", { { OP_LWP_E, 0 }, Edq }, 0 },
3437     { Bad_Opcode },
3438     { Bad_Opcode },
3439     { Bad_Opcode },
3440     { Bad_Opcode },
3441     { "blci",   { { OP_LWP_E, 0 }, Edq }, 0 },
3442   },
3443
3444 #include "i386-dis-evex-reg.h"
3445 };
3446
3447 static const struct dis386 prefix_table[][4] = {
3448   /* PREFIX_90 */
3449   {
3450     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3451     { "pause", { XX }, 0 },
3452     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3453     { NULL, { { NULL, 0 } }, PREFIX_IGNORED }
3454   },
3455
3456   /* PREFIX_0F01_REG_3_RM_1 */
3457   {
3458     { "vmmcall",        { Skip_MODRM }, 0 },
3459     { "vmgexit",        { Skip_MODRM }, 0 },
3460     { Bad_Opcode },
3461     { "vmgexit",        { Skip_MODRM }, 0 },
3462   },
3463
3464   /* PREFIX_0F01_REG_5_MOD_0 */
3465   {
3466     { Bad_Opcode },
3467     { "rstorssp",       { Mq }, PREFIX_OPCODE },
3468   },
3469
3470   /* PREFIX_0F01_REG_5_MOD_3_RM_0 */
3471   {
3472     { "serialize",      { Skip_MODRM }, PREFIX_OPCODE },
3473     { "setssbsy",       { Skip_MODRM }, PREFIX_OPCODE },
3474     { Bad_Opcode },
3475     { "xsusldtrk",      { Skip_MODRM }, PREFIX_OPCODE },
3476   },
3477
3478   /* PREFIX_0F01_REG_5_MOD_3_RM_1 */
3479   {
3480     { Bad_Opcode },
3481     { Bad_Opcode },
3482     { Bad_Opcode },
3483     { "xresldtrk",     { Skip_MODRM }, PREFIX_OPCODE },
3484   },
3485
3486   /* PREFIX_0F01_REG_5_MOD_3_RM_2 */
3487   {
3488     { Bad_Opcode },
3489     { "saveprevssp",    { Skip_MODRM }, PREFIX_OPCODE },
3490   },
3491
3492   /* PREFIX_0F01_REG_7_MOD_3_RM_2 */
3493   {
3494     { "monitorx",       { { OP_Monitor, 0 } }, 0  },
3495     { "mcommit",        { Skip_MODRM }, 0 },
3496   },
3497
3498   /* PREFIX_0F01_REG_7_MOD_3_RM_3 */
3499   {
3500     { "mwaitx",         { { OP_Mwait, eBX_reg } }, 0  },
3501   },
3502
3503   /* PREFIX_0F09 */
3504   {
3505     { "wbinvd",   { XX }, 0 },
3506     { "wbnoinvd", { XX }, 0 },
3507   },
3508
3509   /* PREFIX_0F10 */
3510   {
3511     { "movups", { XM, EXx }, PREFIX_OPCODE },
3512     { "movss",  { XM, EXd }, PREFIX_OPCODE },
3513     { "movupd", { XM, EXx }, PREFIX_OPCODE },
3514     { "movsd",  { XM, EXq }, PREFIX_OPCODE },
3515   },
3516
3517   /* PREFIX_0F11 */
3518   {
3519     { "movups", { EXxS, XM }, PREFIX_OPCODE },
3520     { "movss",  { EXdS, XM }, PREFIX_OPCODE },
3521     { "movupd", { EXxS, XM }, PREFIX_OPCODE },
3522     { "movsd",  { EXqS, XM }, PREFIX_OPCODE },
3523   },
3524
3525   /* PREFIX_0F12 */
3526   {
3527     { MOD_TABLE (MOD_0F12_PREFIX_0) },
3528     { "movsldup", { XM, EXx }, PREFIX_OPCODE },
3529     { MOD_TABLE (MOD_0F12_PREFIX_2) },
3530     { "movddup", { XM, EXq }, PREFIX_OPCODE },
3531   },
3532
3533   /* PREFIX_0F16 */
3534   {
3535     { MOD_TABLE (MOD_0F16_PREFIX_0) },
3536     { "movshdup", { XM, EXx }, PREFIX_OPCODE },
3537     { MOD_TABLE (MOD_0F16_PREFIX_2) },
3538   },
3539
3540   /* PREFIX_0F1A */
3541   {
3542     { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3543     { "bndcl",  { Gbnd, Ev_bnd }, 0 },
3544     { "bndmov", { Gbnd, Ebnd }, 0 },
3545     { "bndcu",  { Gbnd, Ev_bnd }, 0 },
3546   },
3547
3548   /* PREFIX_0F1B */
3549   {
3550     { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3551     { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3552     { "bndmov", { EbndS, Gbnd }, 0 },
3553     { "bndcn",  { Gbnd, Ev_bnd }, 0 },
3554   },
3555
3556   /* PREFIX_0F1C */
3557   {
3558     { MOD_TABLE (MOD_0F1C_PREFIX_0) },
3559     { "nopQ",   { Ev }, PREFIX_OPCODE },
3560     { "nopQ",   { Ev }, PREFIX_OPCODE },
3561     { "nopQ",   { Ev }, PREFIX_OPCODE },
3562   },
3563
3564   /* PREFIX_0F1E */
3565   {
3566     { "nopQ",   { Ev }, PREFIX_OPCODE },
3567     { MOD_TABLE (MOD_0F1E_PREFIX_1) },
3568     { "nopQ",   { Ev }, PREFIX_OPCODE },
3569     { "nopQ",   { Ev }, PREFIX_OPCODE },
3570   },
3571
3572   /* PREFIX_0F2A */
3573   {
3574     { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE },
3575     { "cvtsi2ss%LQ", { XM, Edq }, PREFIX_OPCODE },
3576     { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE },
3577     { "cvtsi2sd%LQ", { XM, Edq }, 0 },
3578   },
3579
3580   /* PREFIX_0F2B */
3581   {
3582     { MOD_TABLE (MOD_0F2B_PREFIX_0) },
3583     { MOD_TABLE (MOD_0F2B_PREFIX_1) },
3584     { MOD_TABLE (MOD_0F2B_PREFIX_2) },
3585     { MOD_TABLE (MOD_0F2B_PREFIX_3) },
3586   },
3587
3588   /* PREFIX_0F2C */
3589   {
3590     { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE },
3591     { "cvttss2si", { Gdq, EXd }, PREFIX_OPCODE },
3592     { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3593     { "cvttsd2si", { Gdq, EXq }, PREFIX_OPCODE },
3594   },
3595
3596   /* PREFIX_0F2D */
3597   {
3598     { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE },
3599     { "cvtss2si", { Gdq, EXd }, PREFIX_OPCODE },
3600     { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3601     { "cvtsd2si", { Gdq, EXq }, PREFIX_OPCODE },
3602   },
3603
3604   /* PREFIX_0F2E */
3605   {
3606     { "ucomiss",{ XM, EXd }, 0 },
3607     { Bad_Opcode },
3608     { "ucomisd",{ XM, EXq }, 0 },
3609   },
3610
3611   /* PREFIX_0F2F */
3612   {
3613     { "comiss", { XM, EXd }, 0 },
3614     { Bad_Opcode },
3615     { "comisd", { XM, EXq }, 0 },
3616   },
3617
3618   /* PREFIX_0F51 */
3619   {
3620     { "sqrtps", { XM, EXx }, PREFIX_OPCODE },
3621     { "sqrtss", { XM, EXd }, PREFIX_OPCODE },
3622     { "sqrtpd", { XM, EXx }, PREFIX_OPCODE },
3623     { "sqrtsd", { XM, EXq }, PREFIX_OPCODE },
3624   },
3625
3626   /* PREFIX_0F52 */
3627   {
3628     { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE },
3629     { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE },
3630   },
3631
3632   /* PREFIX_0F53 */
3633   {
3634     { "rcpps",  { XM, EXx }, PREFIX_OPCODE },
3635     { "rcpss",  { XM, EXd }, PREFIX_OPCODE },
3636   },
3637
3638   /* PREFIX_0F58 */
3639   {
3640     { "addps", { XM, EXx }, PREFIX_OPCODE },
3641     { "addss", { XM, EXd }, PREFIX_OPCODE },
3642     { "addpd", { XM, EXx }, PREFIX_OPCODE },
3643     { "addsd", { XM, EXq }, PREFIX_OPCODE },
3644   },
3645
3646   /* PREFIX_0F59 */
3647   {
3648     { "mulps",  { XM, EXx }, PREFIX_OPCODE },
3649     { "mulss",  { XM, EXd }, PREFIX_OPCODE },
3650     { "mulpd",  { XM, EXx }, PREFIX_OPCODE },
3651     { "mulsd",  { XM, EXq }, PREFIX_OPCODE },
3652   },
3653
3654   /* PREFIX_0F5A */
3655   {
3656     { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE },
3657     { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE },
3658     { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE },
3659     { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE },
3660   },
3661
3662   /* PREFIX_0F5B */
3663   {
3664     { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE },
3665     { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE },
3666     { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE },
3667   },
3668
3669   /* PREFIX_0F5C */
3670   {
3671     { "subps",  { XM, EXx }, PREFIX_OPCODE },
3672     { "subss",  { XM, EXd }, PREFIX_OPCODE },
3673     { "subpd",  { XM, EXx }, PREFIX_OPCODE },
3674     { "subsd",  { XM, EXq }, PREFIX_OPCODE },
3675   },
3676
3677   /* PREFIX_0F5D */
3678   {
3679     { "minps",  { XM, EXx }, PREFIX_OPCODE },
3680     { "minss",  { XM, EXd }, PREFIX_OPCODE },
3681     { "minpd",  { XM, EXx }, PREFIX_OPCODE },
3682     { "minsd",  { XM, EXq }, PREFIX_OPCODE },
3683   },
3684
3685   /* PREFIX_0F5E */
3686   {
3687     { "divps",  { XM, EXx }, PREFIX_OPCODE },
3688     { "divss",  { XM, EXd }, PREFIX_OPCODE },
3689     { "divpd",  { XM, EXx }, PREFIX_OPCODE },
3690     { "divsd",  { XM, EXq }, PREFIX_OPCODE },
3691   },
3692
3693   /* PREFIX_0F5F */
3694   {
3695     { "maxps",  { XM, EXx }, PREFIX_OPCODE },
3696     { "maxss",  { XM, EXd }, PREFIX_OPCODE },
3697     { "maxpd",  { XM, EXx }, PREFIX_OPCODE },
3698     { "maxsd",  { XM, EXq }, PREFIX_OPCODE },
3699   },
3700
3701   /* PREFIX_0F60 */
3702   {
3703     { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE },
3704     { Bad_Opcode },
3705     { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE },
3706   },
3707
3708   /* PREFIX_0F61 */
3709   {
3710     { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE },
3711     { Bad_Opcode },
3712     { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE },
3713   },
3714
3715   /* PREFIX_0F62 */
3716   {
3717     { "punpckldq",{ MX, EMd }, PREFIX_OPCODE },
3718     { Bad_Opcode },
3719     { "punpckldq",{ MX, EMx }, PREFIX_OPCODE },
3720   },
3721
3722   /* PREFIX_0F6C */
3723   {
3724     { Bad_Opcode },
3725     { Bad_Opcode },
3726     { "punpcklqdq", { XM, EXx }, PREFIX_OPCODE },
3727   },
3728
3729   /* PREFIX_0F6D */
3730   {
3731     { Bad_Opcode },
3732     { Bad_Opcode },
3733     { "punpckhqdq", { XM, EXx }, PREFIX_OPCODE },
3734   },
3735
3736   /* PREFIX_0F6F */
3737   {
3738     { "movq",   { MX, EM }, PREFIX_OPCODE },
3739     { "movdqu", { XM, EXx }, PREFIX_OPCODE },
3740     { "movdqa", { XM, EXx }, PREFIX_OPCODE },
3741   },
3742
3743   /* PREFIX_0F70 */
3744   {
3745     { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE },
3746     { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3747     { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE },
3748     { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3749   },
3750
3751   /* PREFIX_0F73_REG_3 */
3752   {
3753     { Bad_Opcode },
3754     { Bad_Opcode },
3755     { "psrldq", { XS, Ib }, 0 },
3756   },
3757
3758   /* PREFIX_0F73_REG_7 */
3759   {
3760     { Bad_Opcode },
3761     { Bad_Opcode },
3762     { "pslldq", { XS, Ib }, 0 },
3763   },
3764
3765   /* PREFIX_0F78 */
3766   {
3767     {"vmread",  { Em, Gm }, 0 },
3768     { Bad_Opcode },
3769     {"extrq",   { XS, Ib, Ib }, 0 },
3770     {"insertq", { XM, XS, Ib, Ib }, 0 },
3771   },
3772
3773   /* PREFIX_0F79 */
3774   {
3775     {"vmwrite", { Gm, Em }, 0 },
3776     { Bad_Opcode },
3777     {"extrq",   { XM, XS }, 0 },
3778     {"insertq", { XM, XS }, 0 },
3779   },
3780
3781   /* PREFIX_0F7C */
3782   {
3783     { Bad_Opcode },
3784     { Bad_Opcode },
3785     { "haddpd", { XM, EXx }, PREFIX_OPCODE },
3786     { "haddps", { XM, EXx }, PREFIX_OPCODE },
3787   },
3788
3789   /* PREFIX_0F7D */
3790   {
3791     { Bad_Opcode },
3792     { Bad_Opcode },
3793     { "hsubpd", { XM, EXx }, PREFIX_OPCODE },
3794     { "hsubps", { XM, EXx }, PREFIX_OPCODE },
3795   },
3796
3797   /* PREFIX_0F7E */
3798   {
3799     { "movK",   { Edq, MX }, PREFIX_OPCODE },
3800     { "movq",   { XM, EXq }, PREFIX_OPCODE },
3801     { "movK",   { Edq, XM }, PREFIX_OPCODE },
3802   },
3803
3804   /* PREFIX_0F7F */
3805   {
3806     { "movq",   { EMS, MX }, PREFIX_OPCODE },
3807     { "movdqu", { EXxS, XM }, PREFIX_OPCODE },
3808     { "movdqa", { EXxS, XM }, PREFIX_OPCODE },
3809   },
3810
3811   /* PREFIX_0FAE_REG_0_MOD_3 */
3812   {
3813     { Bad_Opcode },
3814     { "rdfsbase", { Ev }, 0 },
3815   },
3816
3817   /* PREFIX_0FAE_REG_1_MOD_3 */
3818   {
3819     { Bad_Opcode },
3820     { "rdgsbase", { Ev }, 0 },
3821   },
3822
3823   /* PREFIX_0FAE_REG_2_MOD_3 */
3824   {
3825     { Bad_Opcode },
3826     { "wrfsbase", { Ev }, 0 },
3827   },
3828
3829   /* PREFIX_0FAE_REG_3_MOD_3 */
3830   {
3831     { Bad_Opcode },
3832     { "wrgsbase", { Ev }, 0 },
3833   },
3834
3835   /* PREFIX_0FAE_REG_4_MOD_0 */
3836   {
3837     { "xsave",  { FXSAVE }, 0 },
3838     { "ptwrite%LQ", { Edq }, 0 },
3839   },
3840
3841   /* PREFIX_0FAE_REG_4_MOD_3 */
3842   {
3843     { Bad_Opcode },
3844     { "ptwrite%LQ", { Edq }, 0 },
3845   },
3846
3847   /* PREFIX_0FAE_REG_5_MOD_0 */
3848   {
3849     { "xrstor",         { FXSAVE }, PREFIX_OPCODE },
3850   },
3851
3852   /* PREFIX_0FAE_REG_5_MOD_3 */
3853   {
3854     { "lfence",         { Skip_MODRM }, 0 },
3855     { "incsspK",        { Rdq }, PREFIX_OPCODE },
3856   },
3857
3858   /* PREFIX_0FAE_REG_6_MOD_0 */
3859   {
3860     { "xsaveopt",       { FXSAVE }, PREFIX_OPCODE },
3861     { "clrssbsy",       { Mq }, PREFIX_OPCODE },
3862     { "clwb",   { Mb }, PREFIX_OPCODE },
3863   },
3864
3865   /* PREFIX_0FAE_REG_6_MOD_3 */
3866   {
3867     { RM_TABLE (RM_0FAE_REG_6_MOD_3_P_0) },
3868     { "umonitor",       { Eva }, PREFIX_OPCODE },
3869     { "tpause", { Edq }, PREFIX_OPCODE },
3870     { "umwait", { Edq }, PREFIX_OPCODE },
3871   },
3872
3873   /* PREFIX_0FAE_REG_7_MOD_0 */
3874   {
3875     { "clflush",        { Mb }, 0 },
3876     { Bad_Opcode },
3877     { "clflushopt",     { Mb }, 0 },
3878   },
3879
3880   /* PREFIX_0FB8 */
3881   {
3882     { Bad_Opcode },
3883     { "popcntS", { Gv, Ev }, 0 },
3884   },
3885
3886   /* PREFIX_0FBC */
3887   {
3888     { "bsfS",   { Gv, Ev }, 0 },
3889     { "tzcntS", { Gv, Ev }, 0 },
3890     { "bsfS",   { Gv, Ev }, 0 },
3891   },
3892
3893   /* PREFIX_0FBD */
3894   {
3895     { "bsrS",   { Gv, Ev }, 0 },
3896     { "lzcntS", { Gv, Ev }, 0 },
3897     { "bsrS",   { Gv, Ev }, 0 },
3898   },
3899
3900   /* PREFIX_0FC2 */
3901   {
3902     { "cmpps",  { XM, EXx, CMP }, PREFIX_OPCODE },
3903     { "cmpss",  { XM, EXd, CMP }, PREFIX_OPCODE },
3904     { "cmppd",  { XM, EXx, CMP }, PREFIX_OPCODE },
3905     { "cmpsd",  { XM, EXq, CMP }, PREFIX_OPCODE },
3906   },
3907
3908   /* PREFIX_0FC3_MOD_0 */
3909   {
3910     { "movntiS", { Edq, Gdq }, PREFIX_OPCODE },
3911   },
3912
3913   /* PREFIX_0FC7_REG_6_MOD_0 */
3914   {
3915     { "vmptrld",{ Mq }, 0 },
3916     { "vmxon",  { Mq }, 0 },
3917     { "vmclear",{ Mq }, 0 },
3918   },
3919
3920   /* PREFIX_0FC7_REG_6_MOD_3 */
3921   {
3922     { "rdrand", { Ev }, 0 },
3923     { Bad_Opcode },
3924     { "rdrand", { Ev }, 0 }
3925   },
3926
3927   /* PREFIX_0FC7_REG_7_MOD_3 */
3928   {
3929     { "rdseed", { Ev }, 0 },
3930     { "rdpid",  { Em }, 0 },
3931     { "rdseed", { Ev }, 0 },
3932   },
3933
3934   /* PREFIX_0FD0 */
3935   {
3936     { Bad_Opcode },
3937     { Bad_Opcode },
3938     { "addsubpd", { XM, EXx }, 0 },
3939     { "addsubps", { XM, EXx }, 0 },
3940   },
3941
3942   /* PREFIX_0FD6 */
3943   {
3944     { Bad_Opcode },
3945     { "movq2dq",{ XM, MS }, 0 },
3946     { "movq",   { EXqS, XM }, 0 },
3947     { "movdq2q",{ MX, XS }, 0 },
3948   },
3949
3950   /* PREFIX_0FE6 */
3951   {
3952     { Bad_Opcode },
3953     { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE },
3954     { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE },
3955     { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE },
3956   },
3957
3958   /* PREFIX_0FE7 */
3959   {
3960     { "movntq", { Mq, MX }, PREFIX_OPCODE },
3961     { Bad_Opcode },
3962     { MOD_TABLE (MOD_0FE7_PREFIX_2) },
3963   },
3964
3965   /* PREFIX_0FF0 */
3966   {
3967     { Bad_Opcode },
3968     { Bad_Opcode },
3969     { Bad_Opcode },
3970     { MOD_TABLE (MOD_0FF0_PREFIX_3) },
3971   },
3972
3973   /* PREFIX_0FF7 */
3974   {
3975     { "maskmovq", { MX, MS }, PREFIX_OPCODE },
3976     { Bad_Opcode },
3977     { "maskmovdqu", { XM, XS }, PREFIX_OPCODE },
3978   },
3979
3980   /* PREFIX_0F3810 */
3981   {
3982     { Bad_Opcode },
3983     { Bad_Opcode },
3984     { "pblendvb", { XM, EXx, XMM0 }, PREFIX_OPCODE },
3985   },
3986
3987   /* PREFIX_0F3814 */
3988   {
3989     { Bad_Opcode },
3990     { Bad_Opcode },
3991     { "blendvps", { XM, EXx, XMM0 }, PREFIX_OPCODE },
3992   },
3993
3994   /* PREFIX_0F3815 */
3995   {
3996     { Bad_Opcode },
3997     { Bad_Opcode },
3998     { "blendvpd", { XM, EXx, XMM0 }, PREFIX_OPCODE },
3999   },
4000
4001   /* PREFIX_0F3817 */
4002   {
4003     { Bad_Opcode },
4004     { Bad_Opcode },
4005     { "ptest",  { XM, EXx }, PREFIX_OPCODE },
4006   },
4007
4008   /* PREFIX_0F3820 */
4009   {
4010     { Bad_Opcode },
4011     { Bad_Opcode },
4012     { "pmovsxbw", { XM, EXq }, PREFIX_OPCODE },
4013   },
4014
4015   /* PREFIX_0F3821 */
4016   {
4017     { Bad_Opcode },
4018     { Bad_Opcode },
4019     { "pmovsxbd", { XM, EXd }, PREFIX_OPCODE },
4020   },
4021
4022   /* PREFIX_0F3822 */
4023   {
4024     { Bad_Opcode },
4025     { Bad_Opcode },
4026     { "pmovsxbq", { XM, EXw }, PREFIX_OPCODE },
4027   },
4028
4029   /* PREFIX_0F3823 */
4030   {
4031     { Bad_Opcode },
4032     { Bad_Opcode },
4033     { "pmovsxwd", { XM, EXq }, PREFIX_OPCODE },
4034   },
4035
4036   /* PREFIX_0F3824 */
4037   {
4038     { Bad_Opcode },
4039     { Bad_Opcode },
4040     { "pmovsxwq", { XM, EXd }, PREFIX_OPCODE },
4041   },
4042
4043   /* PREFIX_0F3825 */
4044   {
4045     { Bad_Opcode },
4046     { Bad_Opcode },
4047     { "pmovsxdq", { XM, EXq }, PREFIX_OPCODE },
4048   },
4049
4050   /* PREFIX_0F3828 */
4051   {
4052     { Bad_Opcode },
4053     { Bad_Opcode },
4054     { "pmuldq", { XM, EXx }, PREFIX_OPCODE },
4055   },
4056
4057   /* PREFIX_0F3829 */
4058   {
4059     { Bad_Opcode },
4060     { Bad_Opcode },
4061     { "pcmpeqq", { XM, EXx }, PREFIX_OPCODE },
4062   },
4063
4064   /* PREFIX_0F382A */
4065   {
4066     { Bad_Opcode },
4067     { Bad_Opcode },
4068     { MOD_TABLE (MOD_0F382A_PREFIX_2) },
4069   },
4070
4071   /* PREFIX_0F382B */
4072   {
4073     { Bad_Opcode },
4074     { Bad_Opcode },
4075     { "packusdw", { XM, EXx }, PREFIX_OPCODE },
4076   },
4077
4078   /* PREFIX_0F3830 */
4079   {
4080     { Bad_Opcode },
4081     { Bad_Opcode },
4082     { "pmovzxbw", { XM, EXq }, PREFIX_OPCODE },
4083   },
4084
4085   /* PREFIX_0F3831 */
4086   {
4087     { Bad_Opcode },
4088     { Bad_Opcode },
4089     { "pmovzxbd", { XM, EXd }, PREFIX_OPCODE },
4090   },
4091
4092   /* PREFIX_0F3832 */
4093   {
4094     { Bad_Opcode },
4095     { Bad_Opcode },
4096     { "pmovzxbq", { XM, EXw }, PREFIX_OPCODE },
4097   },
4098
4099   /* PREFIX_0F3833 */
4100   {
4101     { Bad_Opcode },
4102     { Bad_Opcode },
4103     { "pmovzxwd", { XM, EXq }, PREFIX_OPCODE },
4104   },
4105
4106   /* PREFIX_0F3834 */
4107   {
4108     { Bad_Opcode },
4109     { Bad_Opcode },
4110     { "pmovzxwq", { XM, EXd }, PREFIX_OPCODE },
4111   },
4112
4113   /* PREFIX_0F3835 */
4114   {
4115     { Bad_Opcode },
4116     { Bad_Opcode },
4117     { "pmovzxdq", { XM, EXq }, PREFIX_OPCODE },
4118   },
4119
4120   /* PREFIX_0F3837 */
4121   {
4122     { Bad_Opcode },
4123     { Bad_Opcode },
4124     { "pcmpgtq", { XM, EXx }, PREFIX_OPCODE },
4125   },
4126
4127   /* PREFIX_0F3838 */
4128   {
4129     { Bad_Opcode },
4130     { Bad_Opcode },
4131     { "pminsb", { XM, EXx }, PREFIX_OPCODE },
4132   },
4133
4134   /* PREFIX_0F3839 */
4135   {
4136     { Bad_Opcode },
4137     { Bad_Opcode },
4138     { "pminsd", { XM, EXx }, PREFIX_OPCODE },
4139   },
4140
4141   /* PREFIX_0F383A */
4142   {
4143     { Bad_Opcode },
4144     { Bad_Opcode },
4145     { "pminuw", { XM, EXx }, PREFIX_OPCODE },
4146   },
4147
4148   /* PREFIX_0F383B */
4149   {
4150     { Bad_Opcode },
4151     { Bad_Opcode },
4152     { "pminud", { XM, EXx }, PREFIX_OPCODE },
4153   },
4154
4155   /* PREFIX_0F383C */
4156   {
4157     { Bad_Opcode },
4158     { Bad_Opcode },
4159     { "pmaxsb", { XM, EXx }, PREFIX_OPCODE },
4160   },
4161
4162   /* PREFIX_0F383D */
4163   {
4164     { Bad_Opcode },
4165     { Bad_Opcode },
4166     { "pmaxsd", { XM, EXx }, PREFIX_OPCODE },
4167   },
4168
4169   /* PREFIX_0F383E */
4170   {
4171     { Bad_Opcode },
4172     { Bad_Opcode },
4173     { "pmaxuw", { XM, EXx }, PREFIX_OPCODE },
4174   },
4175
4176   /* PREFIX_0F383F */
4177   {
4178     { Bad_Opcode },
4179     { Bad_Opcode },
4180     { "pmaxud", { XM, EXx }, PREFIX_OPCODE },
4181   },
4182
4183   /* PREFIX_0F3840 */
4184   {
4185     { Bad_Opcode },
4186     { Bad_Opcode },
4187     { "pmulld", { XM, EXx }, PREFIX_OPCODE },
4188   },
4189
4190   /* PREFIX_0F3841 */
4191   {
4192     { Bad_Opcode },
4193     { Bad_Opcode },
4194     { "phminposuw", { XM, EXx }, PREFIX_OPCODE },
4195   },
4196
4197   /* PREFIX_0F3880 */
4198   {
4199     { Bad_Opcode },
4200     { Bad_Opcode },
4201     { "invept", { Gm, Mo }, PREFIX_OPCODE },
4202   },
4203
4204   /* PREFIX_0F3881 */
4205   {
4206     { Bad_Opcode },
4207     { Bad_Opcode },
4208     { "invvpid", { Gm, Mo }, PREFIX_OPCODE },
4209   },
4210
4211   /* PREFIX_0F3882 */
4212   {
4213     { Bad_Opcode },
4214     { Bad_Opcode },
4215     { "invpcid", { Gm, M }, PREFIX_OPCODE },
4216   },
4217
4218   /* PREFIX_0F38C8 */
4219   {
4220     { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE },
4221   },
4222
4223   /* PREFIX_0F38C9 */
4224   {
4225     { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE },
4226   },
4227
4228   /* PREFIX_0F38CA */
4229   {
4230     { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE },
4231   },
4232
4233   /* PREFIX_0F38CB */
4234   {
4235     { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE },
4236   },
4237
4238   /* PREFIX_0F38CC */
4239   {
4240     { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE },
4241   },
4242
4243   /* PREFIX_0F38CD */
4244   {
4245     { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE },
4246   },
4247
4248   /* PREFIX_0F38CF */
4249   {
4250     { Bad_Opcode },
4251     { Bad_Opcode },
4252     { "gf2p8mulb", { XM, EXxmm }, PREFIX_OPCODE },
4253   },
4254
4255   /* PREFIX_0F38DB */
4256   {
4257     { Bad_Opcode },
4258     { Bad_Opcode },
4259     { "aesimc", { XM, EXx }, PREFIX_OPCODE },
4260   },
4261
4262   /* PREFIX_0F38DC */
4263   {
4264     { Bad_Opcode },
4265     { Bad_Opcode },
4266     { "aesenc", { XM, EXx }, PREFIX_OPCODE },
4267   },
4268
4269   /* PREFIX_0F38DD */
4270   {
4271     { Bad_Opcode },
4272     { Bad_Opcode },
4273     { "aesenclast", { XM, EXx }, PREFIX_OPCODE },
4274   },
4275
4276   /* PREFIX_0F38DE */
4277   {
4278     { Bad_Opcode },
4279     { Bad_Opcode },
4280     { "aesdec", { XM, EXx }, PREFIX_OPCODE },
4281   },
4282
4283   /* PREFIX_0F38DF */
4284   {
4285     { Bad_Opcode },
4286     { Bad_Opcode },
4287     { "aesdeclast", { XM, EXx }, PREFIX_OPCODE },
4288   },
4289
4290   /* PREFIX_0F38F0 */
4291   {
4292     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4293     { Bad_Opcode },
4294     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4295     { "crc32",  { Gdq, { CRC32_Fixup, b_mode } }, PREFIX_OPCODE },
4296   },
4297
4298   /* PREFIX_0F38F1 */
4299   {
4300     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4301     { Bad_Opcode },
4302     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4303     { "crc32",  { Gdq, { CRC32_Fixup, v_mode } }, PREFIX_OPCODE },
4304   },
4305
4306   /* PREFIX_0F38F5 */
4307   {
4308     { Bad_Opcode },
4309     { Bad_Opcode },
4310     { MOD_TABLE (MOD_0F38F5_PREFIX_2) },
4311   },
4312
4313   /* PREFIX_0F38F6 */
4314   {
4315     { MOD_TABLE (MOD_0F38F6_PREFIX_0) },
4316     { "adoxS",  { Gdq, Edq}, PREFIX_OPCODE },
4317     { "adcxS",  { Gdq, Edq}, PREFIX_OPCODE },
4318     { Bad_Opcode },
4319   },
4320
4321   /* PREFIX_0F38F8 */
4322   {
4323     { Bad_Opcode },
4324     { MOD_TABLE (MOD_0F38F8_PREFIX_1) },
4325     { MOD_TABLE (MOD_0F38F8_PREFIX_2) },
4326     { MOD_TABLE (MOD_0F38F8_PREFIX_3) },
4327   },
4328
4329   /* PREFIX_0F38F9 */
4330   {
4331     { MOD_TABLE (MOD_0F38F9_PREFIX_0) },
4332   },
4333
4334   /* PREFIX_0F3A08 */
4335   {
4336     { Bad_Opcode },
4337     { Bad_Opcode },
4338     { "roundps", { XM, EXx, Ib }, PREFIX_OPCODE },
4339   },
4340
4341   /* PREFIX_0F3A09 */
4342   {
4343     { Bad_Opcode },
4344     { Bad_Opcode },
4345     { "roundpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4346   },
4347
4348   /* PREFIX_0F3A0A */
4349   {
4350     { Bad_Opcode },
4351     { Bad_Opcode },
4352     { "roundss", { XM, EXd, Ib }, PREFIX_OPCODE },
4353   },
4354
4355   /* PREFIX_0F3A0B */
4356   {
4357     { Bad_Opcode },
4358     { Bad_Opcode },
4359     { "roundsd", { XM, EXq, Ib }, PREFIX_OPCODE },
4360   },
4361
4362   /* PREFIX_0F3A0C */
4363   {
4364     { Bad_Opcode },
4365     { Bad_Opcode },
4366     { "blendps", { XM, EXx, Ib }, PREFIX_OPCODE },
4367   },
4368
4369   /* PREFIX_0F3A0D */
4370   {
4371     { Bad_Opcode },
4372     { Bad_Opcode },
4373     { "blendpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4374   },
4375
4376   /* PREFIX_0F3A0E */
4377   {
4378     { Bad_Opcode },
4379     { Bad_Opcode },
4380     { "pblendw", { XM, EXx, Ib }, PREFIX_OPCODE },
4381   },
4382
4383   /* PREFIX_0F3A14 */
4384   {
4385     { Bad_Opcode },
4386     { Bad_Opcode },
4387     { "pextrb", { Edqb, XM, Ib }, PREFIX_OPCODE },
4388   },
4389
4390   /* PREFIX_0F3A15 */
4391   {
4392     { Bad_Opcode },
4393     { Bad_Opcode },
4394     { "pextrw", { Edqw, XM, Ib }, PREFIX_OPCODE },
4395   },
4396
4397   /* PREFIX_0F3A16 */
4398   {
4399     { Bad_Opcode },
4400     { Bad_Opcode },
4401     { "pextrK", { Edq, XM, Ib }, PREFIX_OPCODE },
4402   },
4403
4404   /* PREFIX_0F3A17 */
4405   {
4406     { Bad_Opcode },
4407     { Bad_Opcode },
4408     { "extractps", { Edqd, XM, Ib }, PREFIX_OPCODE },
4409   },
4410
4411   /* PREFIX_0F3A20 */
4412   {
4413     { Bad_Opcode },
4414     { Bad_Opcode },
4415     { "pinsrb", { XM, Edqb, Ib }, PREFIX_OPCODE },
4416   },
4417
4418   /* PREFIX_0F3A21 */
4419   {
4420     { Bad_Opcode },
4421     { Bad_Opcode },
4422     { "insertps", { XM, EXd, Ib }, PREFIX_OPCODE },
4423   },
4424
4425   /* PREFIX_0F3A22 */
4426   {
4427     { Bad_Opcode },
4428     { Bad_Opcode },
4429     { "pinsrK", { XM, Edq, Ib }, PREFIX_OPCODE },
4430   },
4431
4432   /* PREFIX_0F3A40 */
4433   {
4434     { Bad_Opcode },
4435     { Bad_Opcode },
4436     { "dpps",   { XM, EXx, Ib }, PREFIX_OPCODE },
4437   },
4438
4439   /* PREFIX_0F3A41 */
4440   {
4441     { Bad_Opcode },
4442     { Bad_Opcode },
4443     { "dppd",   { XM, EXx, Ib }, PREFIX_OPCODE },
4444   },
4445
4446   /* PREFIX_0F3A42 */
4447   {
4448     { Bad_Opcode },
4449     { Bad_Opcode },
4450     { "mpsadbw", { XM, EXx, Ib }, PREFIX_OPCODE },
4451   },
4452
4453   /* PREFIX_0F3A44 */
4454   {
4455     { Bad_Opcode },
4456     { Bad_Opcode },
4457     { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_OPCODE },
4458   },
4459
4460   /* PREFIX_0F3A60 */
4461   {
4462     { Bad_Opcode },
4463     { Bad_Opcode },
4464     { "pcmpestrm", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE },
4465   },
4466
4467   /* PREFIX_0F3A61 */
4468   {
4469     { Bad_Opcode },
4470     { Bad_Opcode },
4471     { "pcmpestri", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE },
4472   },
4473
4474   /* PREFIX_0F3A62 */
4475   {
4476     { Bad_Opcode },
4477     { Bad_Opcode },
4478     { "pcmpistrm", { XM, EXx, Ib }, PREFIX_OPCODE },
4479   },
4480
4481   /* PREFIX_0F3A63 */
4482   {
4483     { Bad_Opcode },
4484     { Bad_Opcode },
4485     { "pcmpistri", { XM, EXx, Ib }, PREFIX_OPCODE },
4486   },
4487
4488   /* PREFIX_0F3ACC */
4489   {
4490     { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4491   },
4492
4493   /* PREFIX_0F3ACE */
4494   {
4495     { Bad_Opcode },
4496     { Bad_Opcode },
4497     { "gf2p8affineqb", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4498   },
4499
4500   /* PREFIX_0F3ACF */
4501   {
4502     { Bad_Opcode },
4503     { Bad_Opcode },
4504     { "gf2p8affineinvqb", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4505   },
4506
4507   /* PREFIX_0F3ADF */
4508   {
4509     { Bad_Opcode },
4510     { Bad_Opcode },
4511     { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_OPCODE },
4512   },
4513
4514   /* PREFIX_VEX_0F10 */
4515   {
4516     { "vmovups",        { XM, EXx }, 0 },
4517     { "vmovss",         { XMVexScalar, VexScalar, EXxmm_md }, 0 },
4518     { "vmovupd",        { XM, EXx }, 0 },
4519     { "vmovsd",         { XMVexScalar, VexScalar, EXxmm_mq }, 0 },
4520   },
4521
4522   /* PREFIX_VEX_0F11 */
4523   {
4524     { "vmovups",        { EXxS, XM }, 0 },
4525     { "vmovss",         { EXdVexScalarS, VexScalar, XMScalar }, 0 },
4526     { "vmovupd",        { EXxS, XM }, 0 },
4527     { "vmovsd",         { EXqVexScalarS, VexScalar, XMScalar }, 0 },
4528   },
4529
4530   /* PREFIX_VEX_0F12 */
4531   {
4532     { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
4533     { "vmovsldup",      { XM, EXx }, 0 },
4534     { MOD_TABLE (MOD_VEX_0F12_PREFIX_2) },
4535     { "vmovddup",       { XM, EXymmq }, 0 },
4536   },
4537
4538   /* PREFIX_VEX_0F16 */
4539   {
4540     { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
4541     { "vmovshdup",      { XM, EXx }, 0 },
4542     { MOD_TABLE (MOD_VEX_0F16_PREFIX_2) },
4543   },
4544
4545   /* PREFIX_VEX_0F2A */
4546   {
4547     { Bad_Opcode },
4548     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Edq }, 0 },
4549     { Bad_Opcode },
4550     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Edq }, 0 },
4551   },
4552
4553   /* PREFIX_VEX_0F2C */
4554   {
4555     { Bad_Opcode },
4556     { "vcvttss2si",     { Gdq, EXxmm_md }, 0 },
4557     { Bad_Opcode },
4558     { "vcvttsd2si",     { Gdq, EXxmm_mq }, 0 },
4559   },
4560
4561   /* PREFIX_VEX_0F2D */
4562   {
4563     { Bad_Opcode },
4564     { "vcvtss2si",      { Gdq, EXxmm_md }, 0 },
4565     { Bad_Opcode },
4566     { "vcvtsd2si",      { Gdq, EXxmm_mq }, 0 },
4567   },
4568
4569   /* PREFIX_VEX_0F2E */
4570   {
4571     { "vucomiss",       { XMScalar, EXxmm_md }, 0 },
4572     { Bad_Opcode },
4573     { "vucomisd",       { XMScalar, EXxmm_mq }, 0 },
4574   },
4575
4576   /* PREFIX_VEX_0F2F */
4577   {
4578     { "vcomiss",        { XMScalar, EXxmm_md }, 0 },
4579     { Bad_Opcode },
4580     { "vcomisd",        { XMScalar, EXxmm_mq }, 0 },
4581   },
4582
4583   /* PREFIX_VEX_0F41 */
4584   {
4585     { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) },
4586     { Bad_Opcode },
4587     { VEX_LEN_TABLE (VEX_LEN_0F41_P_2) },
4588   },
4589
4590   /* PREFIX_VEX_0F42 */
4591   {
4592     { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) },
4593     { Bad_Opcode },
4594     { VEX_LEN_TABLE (VEX_LEN_0F42_P_2) },
4595   },
4596
4597   /* PREFIX_VEX_0F44 */
4598   {
4599     { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) },
4600     { Bad_Opcode },
4601     { VEX_LEN_TABLE (VEX_LEN_0F44_P_2) },
4602   },
4603
4604   /* PREFIX_VEX_0F45 */
4605   {
4606     { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) },
4607     { Bad_Opcode },
4608     { VEX_LEN_TABLE (VEX_LEN_0F45_P_2) },
4609   },
4610
4611   /* PREFIX_VEX_0F46 */
4612   {
4613     { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) },
4614     { Bad_Opcode },
4615     { VEX_LEN_TABLE (VEX_LEN_0F46_P_2) },
4616   },
4617
4618   /* PREFIX_VEX_0F47 */
4619   {
4620     { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) },
4621     { Bad_Opcode },
4622     { VEX_LEN_TABLE (VEX_LEN_0F47_P_2) },
4623   },
4624
4625   /* PREFIX_VEX_0F4A */
4626   {
4627     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0) },
4628     { Bad_Opcode },
4629     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2) },
4630   },
4631
4632   /* PREFIX_VEX_0F4B */
4633   {
4634     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0) },
4635     { Bad_Opcode },
4636     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) },
4637   },
4638
4639   /* PREFIX_VEX_0F51 */
4640   {
4641     { "vsqrtps",        { XM, EXx }, 0 },
4642     { "vsqrtss",        { XMScalar, VexScalar, EXxmm_md }, 0 },
4643     { "vsqrtpd",        { XM, EXx }, 0 },
4644     { "vsqrtsd",        { XMScalar, VexScalar, EXxmm_mq }, 0 },
4645   },
4646
4647   /* PREFIX_VEX_0F52 */
4648   {
4649     { "vrsqrtps",       { XM, EXx }, 0 },
4650     { "vrsqrtss",       { XMScalar, VexScalar, EXxmm_md }, 0 },
4651   },
4652
4653   /* PREFIX_VEX_0F53 */
4654   {
4655     { "vrcpps",         { XM, EXx }, 0 },
4656     { "vrcpss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
4657   },
4658
4659   /* PREFIX_VEX_0F58 */
4660   {
4661     { "vaddps",         { XM, Vex, EXx }, 0 },
4662     { "vaddss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
4663     { "vaddpd",         { XM, Vex, EXx }, 0 },
4664     { "vaddsd",         { XMScalar, VexScalar, EXxmm_mq }, 0 },
4665   },
4666
4667   /* PREFIX_VEX_0F59 */
4668   {
4669     { "vmulps",         { XM, Vex, EXx }, 0 },
4670     { "vmulss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
4671     { "vmulpd",         { XM, Vex, EXx }, 0 },
4672     { "vmulsd",         { XMScalar, VexScalar, EXxmm_mq }, 0 },
4673   },
4674
4675   /* PREFIX_VEX_0F5A */
4676   {
4677     { "vcvtps2pd",      { XM, EXxmmq }, 0 },
4678     { "vcvtss2sd",      { XMScalar, VexScalar, EXxmm_md }, 0 },
4679     { "vcvtpd2ps%XY",{ XMM, EXx }, 0 },
4680     { "vcvtsd2ss",      { XMScalar, VexScalar, EXxmm_mq }, 0 },
4681   },
4682
4683   /* PREFIX_VEX_0F5B */
4684   {
4685     { "vcvtdq2ps",      { XM, EXx }, 0 },
4686     { "vcvttps2dq",     { XM, EXx }, 0 },
4687     { "vcvtps2dq",      { XM, EXx }, 0 },
4688   },
4689
4690   /* PREFIX_VEX_0F5C */
4691   {
4692     { "vsubps",         { XM, Vex, EXx }, 0 },
4693     { "vsubss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
4694     { "vsubpd",         { XM, Vex, EXx }, 0 },
4695     { "vsubsd",         { XMScalar, VexScalar, EXxmm_mq }, 0 },
4696   },
4697
4698   /* PREFIX_VEX_0F5D */
4699   {
4700     { "vminps",         { XM, Vex, EXx }, 0 },
4701     { "vminss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
4702     { "vminpd",         { XM, Vex, EXx }, 0 },
4703     { "vminsd",         { XMScalar, VexScalar, EXxmm_mq }, 0 },
4704   },
4705
4706   /* PREFIX_VEX_0F5E */
4707   {
4708     { "vdivps",         { XM, Vex, EXx }, 0 },
4709     { "vdivss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
4710     { "vdivpd",         { XM, Vex, EXx }, 0 },
4711     { "vdivsd",         { XMScalar, VexScalar, EXxmm_mq }, 0 },
4712   },
4713
4714   /* PREFIX_VEX_0F5F */
4715   {
4716     { "vmaxps",         { XM, Vex, EXx }, 0 },
4717     { "vmaxss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
4718     { "vmaxpd",         { XM, Vex, EXx }, 0 },
4719     { "vmaxsd",         { XMScalar, VexScalar, EXxmm_mq }, 0 },
4720   },
4721
4722   /* PREFIX_VEX_0F60 */
4723   {
4724     { Bad_Opcode },
4725     { Bad_Opcode },
4726     { "vpunpcklbw",     { XM, Vex, EXx }, 0 },
4727   },
4728
4729   /* PREFIX_VEX_0F61 */
4730   {
4731     { Bad_Opcode },
4732     { Bad_Opcode },
4733     { "vpunpcklwd",     { XM, Vex, EXx }, 0 },
4734   },
4735
4736   /* PREFIX_VEX_0F62 */
4737   {
4738     { Bad_Opcode },
4739     { Bad_Opcode },
4740     { "vpunpckldq",     { XM, Vex, EXx }, 0 },
4741   },
4742
4743   /* PREFIX_VEX_0F63 */
4744   {
4745     { Bad_Opcode },
4746     { Bad_Opcode },
4747     { "vpacksswb",      { XM, Vex, EXx }, 0 },
4748   },
4749
4750   /* PREFIX_VEX_0F64 */
4751   {
4752     { Bad_Opcode },
4753     { Bad_Opcode },
4754     { "vpcmpgtb",       { XM, Vex, EXx }, 0 },
4755   },
4756
4757   /* PREFIX_VEX_0F65 */
4758   {
4759     { Bad_Opcode },
4760     { Bad_Opcode },
4761     { "vpcmpgtw",       { XM, Vex, EXx }, 0 },
4762   },
4763
4764   /* PREFIX_VEX_0F66 */
4765   {
4766     { Bad_Opcode },
4767     { Bad_Opcode },
4768     { "vpcmpgtd",       { XM, Vex, EXx }, 0 },
4769   },
4770
4771   /* PREFIX_VEX_0F67 */
4772   {
4773     { Bad_Opcode },
4774     { Bad_Opcode },
4775     { "vpackuswb",      { XM, Vex, EXx }, 0 },
4776   },
4777
4778   /* PREFIX_VEX_0F68 */
4779   {
4780     { Bad_Opcode },
4781     { Bad_Opcode },
4782     { "vpunpckhbw",     { XM, Vex, EXx }, 0 },
4783   },
4784
4785   /* PREFIX_VEX_0F69 */
4786   {
4787     { Bad_Opcode },
4788     { Bad_Opcode },
4789     { "vpunpckhwd",     { XM, Vex, EXx }, 0 },
4790   },
4791
4792   /* PREFIX_VEX_0F6A */
4793   {
4794     { Bad_Opcode },
4795     { Bad_Opcode },
4796     { "vpunpckhdq",     { XM, Vex, EXx }, 0 },
4797   },
4798
4799   /* PREFIX_VEX_0F6B */
4800   {
4801     { Bad_Opcode },
4802     { Bad_Opcode },
4803     { "vpackssdw",      { XM, Vex, EXx }, 0 },
4804   },
4805
4806   /* PREFIX_VEX_0F6C */
4807   {
4808     { Bad_Opcode },
4809     { Bad_Opcode },
4810     { "vpunpcklqdq",    { XM, Vex, EXx }, 0 },
4811   },
4812
4813   /* PREFIX_VEX_0F6D */
4814   {
4815     { Bad_Opcode },
4816     { Bad_Opcode },
4817     { "vpunpckhqdq",    { XM, Vex, EXx }, 0 },
4818   },
4819
4820   /* PREFIX_VEX_0F6E */
4821   {
4822     { Bad_Opcode },
4823     { Bad_Opcode },
4824     { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) },
4825   },
4826
4827   /* PREFIX_VEX_0F6F */
4828   {
4829     { Bad_Opcode },
4830     { "vmovdqu",        { XM, EXx }, 0 },
4831     { "vmovdqa",        { XM, EXx }, 0 },
4832   },
4833
4834   /* PREFIX_VEX_0F70 */
4835   {
4836     { Bad_Opcode },
4837     { "vpshufhw",       { XM, EXx, Ib }, 0 },
4838     { "vpshufd",        { XM, EXx, Ib }, 0 },
4839     { "vpshuflw",       { XM, EXx, Ib }, 0 },
4840   },
4841
4842   /* PREFIX_VEX_0F71_REG_2 */
4843   {
4844     { Bad_Opcode },
4845     { Bad_Opcode },
4846     { "vpsrlw",         { Vex, XS, Ib }, 0 },
4847   },
4848
4849   /* PREFIX_VEX_0F71_REG_4 */
4850   {
4851     { Bad_Opcode },
4852     { Bad_Opcode },
4853     { "vpsraw",         { Vex, XS, Ib }, 0 },
4854   },
4855
4856   /* PREFIX_VEX_0F71_REG_6 */
4857   {
4858     { Bad_Opcode },
4859     { Bad_Opcode },
4860     { "vpsllw",         { Vex, XS, Ib }, 0 },
4861   },
4862
4863   /* PREFIX_VEX_0F72_REG_2 */
4864   {
4865     { Bad_Opcode },
4866     { Bad_Opcode },
4867     { "vpsrld",         { Vex, XS, Ib }, 0 },
4868   },
4869
4870   /* PREFIX_VEX_0F72_REG_4 */
4871   {
4872     { Bad_Opcode },
4873     { Bad_Opcode },
4874     { "vpsrad",         { Vex, XS, Ib }, 0 },
4875   },
4876
4877   /* PREFIX_VEX_0F72_REG_6 */
4878   {
4879     { Bad_Opcode },
4880     { Bad_Opcode },
4881     { "vpslld",         { Vex, XS, Ib }, 0 },
4882   },
4883
4884   /* PREFIX_VEX_0F73_REG_2 */
4885   {
4886     { Bad_Opcode },
4887     { Bad_Opcode },
4888     { "vpsrlq",         { Vex, XS, Ib }, 0 },
4889   },
4890
4891   /* PREFIX_VEX_0F73_REG_3 */
4892   {
4893     { Bad_Opcode },
4894     { Bad_Opcode },
4895     { "vpsrldq",        { Vex, XS, Ib }, 0 },
4896   },
4897
4898   /* PREFIX_VEX_0F73_REG_6 */
4899   {
4900     { Bad_Opcode },
4901     { Bad_Opcode },
4902     { "vpsllq",         { Vex, XS, Ib }, 0 },
4903   },
4904
4905   /* PREFIX_VEX_0F73_REG_7 */
4906   {
4907     { Bad_Opcode },
4908     { Bad_Opcode },
4909     { "vpslldq",        { Vex, XS, Ib }, 0 },
4910   },
4911
4912   /* PREFIX_VEX_0F74 */
4913   {
4914     { Bad_Opcode },
4915     { Bad_Opcode },
4916     { "vpcmpeqb",       { XM, Vex, EXx }, 0 },
4917   },
4918
4919   /* PREFIX_VEX_0F75 */
4920   {
4921     { Bad_Opcode },
4922     { Bad_Opcode },
4923     { "vpcmpeqw",       { XM, Vex, EXx }, 0 },
4924   },
4925
4926   /* PREFIX_VEX_0F76 */
4927   {
4928     { Bad_Opcode },
4929     { Bad_Opcode },
4930     { "vpcmpeqd",       { XM, Vex, EXx }, 0 },
4931   },
4932
4933   /* PREFIX_VEX_0F77 */
4934   {
4935     { VEX_LEN_TABLE (VEX_LEN_0F77_P_0) },
4936   },
4937
4938   /* PREFIX_VEX_0F7C */
4939   {
4940     { Bad_Opcode },
4941     { Bad_Opcode },
4942     { "vhaddpd",        { XM, Vex, EXx }, 0 },
4943     { "vhaddps",        { XM, Vex, EXx }, 0 },
4944   },
4945
4946   /* PREFIX_VEX_0F7D */
4947   {
4948     { Bad_Opcode },
4949     { Bad_Opcode },
4950     { "vhsubpd",        { XM, Vex, EXx }, 0 },
4951     { "vhsubps",        { XM, Vex, EXx }, 0 },
4952   },
4953
4954   /* PREFIX_VEX_0F7E */
4955   {
4956     { Bad_Opcode },
4957     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
4958     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
4959   },
4960
4961   /* PREFIX_VEX_0F7F */
4962   {
4963     { Bad_Opcode },
4964     { "vmovdqu",        { EXxS, XM }, 0 },
4965     { "vmovdqa",        { EXxS, XM }, 0 },
4966   },
4967
4968   /* PREFIX_VEX_0F90 */
4969   {
4970     { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) },
4971     { Bad_Opcode },
4972     { VEX_LEN_TABLE (VEX_LEN_0F90_P_2) },
4973   },
4974
4975   /* PREFIX_VEX_0F91 */
4976   {
4977     { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) },
4978     { Bad_Opcode },
4979     { VEX_LEN_TABLE (VEX_LEN_0F91_P_2) },
4980   },
4981
4982   /* PREFIX_VEX_0F92 */
4983   {
4984     { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) },
4985     { Bad_Opcode },
4986     { VEX_LEN_TABLE (VEX_LEN_0F92_P_2) },
4987     { VEX_LEN_TABLE (VEX_LEN_0F92_P_3) },
4988   },
4989
4990   /* PREFIX_VEX_0F93 */
4991   {
4992     { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) },
4993     { Bad_Opcode },
4994     { VEX_LEN_TABLE (VEX_LEN_0F93_P_2) },
4995     { VEX_LEN_TABLE (VEX_LEN_0F93_P_3) },
4996   },
4997
4998   /* PREFIX_VEX_0F98 */
4999   {
5000     { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) },
5001     { Bad_Opcode },
5002     { VEX_LEN_TABLE (VEX_LEN_0F98_P_2) },
5003   },
5004
5005   /* PREFIX_VEX_0F99 */
5006   {
5007     { VEX_LEN_TABLE (VEX_LEN_0F99_P_0) },
5008     { Bad_Opcode },
5009     { VEX_LEN_TABLE (VEX_LEN_0F99_P_2) },
5010   },
5011
5012   /* PREFIX_VEX_0FC2 */
5013   {
5014     { "vcmpps",         { XM, Vex, EXx, VCMP }, 0 },
5015     { "vcmpss",         { XMScalar, VexScalar, EXxmm_md, VCMP }, 0 },
5016     { "vcmppd",         { XM, Vex, EXx, VCMP }, 0 },
5017     { "vcmpsd",         { XMScalar, VexScalar, EXxmm_mq, VCMP }, 0 },
5018   },
5019
5020   /* PREFIX_VEX_0FC4 */
5021   {
5022     { Bad_Opcode },
5023     { Bad_Opcode },
5024     { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) },
5025   },
5026
5027   /* PREFIX_VEX_0FC5 */
5028   {
5029     { Bad_Opcode },
5030     { Bad_Opcode },
5031     { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) },
5032   },
5033
5034   /* PREFIX_VEX_0FD0 */
5035   {
5036     { Bad_Opcode },
5037     { Bad_Opcode },
5038     { "vaddsubpd",      { XM, Vex, EXx }, 0 },
5039     { "vaddsubps",      { XM, Vex, EXx }, 0 },
5040   },
5041
5042   /* PREFIX_VEX_0FD1 */
5043   {
5044     { Bad_Opcode },
5045     { Bad_Opcode },
5046     { "vpsrlw",         { XM, Vex, EXxmm }, 0 },
5047   },
5048
5049   /* PREFIX_VEX_0FD2 */
5050   {
5051     { Bad_Opcode },
5052     { Bad_Opcode },
5053     { "vpsrld",         { XM, Vex, EXxmm }, 0 },
5054   },
5055
5056   /* PREFIX_VEX_0FD3 */
5057   {
5058     { Bad_Opcode },
5059     { Bad_Opcode },
5060     { "vpsrlq",         { XM, Vex, EXxmm }, 0 },
5061   },
5062
5063   /* PREFIX_VEX_0FD4 */
5064   {
5065     { Bad_Opcode },
5066     { Bad_Opcode },
5067     { "vpaddq",         { XM, Vex, EXx }, 0 },
5068   },
5069
5070   /* PREFIX_VEX_0FD5 */
5071   {
5072     { Bad_Opcode },
5073     { Bad_Opcode },
5074     { "vpmullw",        { XM, Vex, EXx }, 0 },
5075   },
5076
5077   /* PREFIX_VEX_0FD6 */
5078   {
5079     { Bad_Opcode },
5080     { Bad_Opcode },
5081     { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) },
5082   },
5083
5084   /* PREFIX_VEX_0FD7 */
5085   {
5086     { Bad_Opcode },
5087     { Bad_Opcode },
5088     { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) },
5089   },
5090
5091   /* PREFIX_VEX_0FD8 */
5092   {
5093     { Bad_Opcode },
5094     { Bad_Opcode },
5095     { "vpsubusb",       { XM, Vex, EXx }, 0 },
5096   },
5097
5098   /* PREFIX_VEX_0FD9 */
5099   {
5100     { Bad_Opcode },
5101     { Bad_Opcode },
5102     { "vpsubusw",       { XM, Vex, EXx }, 0 },
5103   },
5104
5105   /* PREFIX_VEX_0FDA */
5106   {
5107     { Bad_Opcode },
5108     { Bad_Opcode },
5109     { "vpminub",        { XM, Vex, EXx }, 0 },
5110   },
5111
5112   /* PREFIX_VEX_0FDB */
5113   {
5114     { Bad_Opcode },
5115     { Bad_Opcode },
5116     { "vpand",          { XM, Vex, EXx }, 0 },
5117   },
5118
5119   /* PREFIX_VEX_0FDC */
5120   {
5121     { Bad_Opcode },
5122     { Bad_Opcode },
5123     { "vpaddusb",       { XM, Vex, EXx }, 0 },
5124   },
5125
5126   /* PREFIX_VEX_0FDD */
5127   {
5128     { Bad_Opcode },
5129     { Bad_Opcode },
5130     { "vpaddusw",       { XM, Vex, EXx }, 0 },
5131   },
5132
5133   /* PREFIX_VEX_0FDE */
5134   {
5135     { Bad_Opcode },
5136     { Bad_Opcode },
5137     { "vpmaxub",        { XM, Vex, EXx }, 0 },
5138   },
5139
5140   /* PREFIX_VEX_0FDF */
5141   {
5142     { Bad_Opcode },
5143     { Bad_Opcode },
5144     { "vpandn",         { XM, Vex, EXx }, 0 },
5145   },
5146
5147   /* PREFIX_VEX_0FE0 */
5148   {
5149     { Bad_Opcode },
5150     { Bad_Opcode },
5151     { "vpavgb",         { XM, Vex, EXx }, 0 },
5152   },
5153
5154   /* PREFIX_VEX_0FE1 */
5155   {
5156     { Bad_Opcode },
5157     { Bad_Opcode },
5158     { "vpsraw",         { XM, Vex, EXxmm }, 0 },
5159   },
5160
5161   /* PREFIX_VEX_0FE2 */
5162   {
5163     { Bad_Opcode },
5164     { Bad_Opcode },
5165     { "vpsrad",         { XM, Vex, EXxmm }, 0 },
5166   },
5167
5168   /* PREFIX_VEX_0FE3 */
5169   {
5170     { Bad_Opcode },
5171     { Bad_Opcode },
5172     { "vpavgw",         { XM, Vex, EXx }, 0 },
5173   },
5174
5175   /* PREFIX_VEX_0FE4 */
5176   {
5177     { Bad_Opcode },
5178     { Bad_Opcode },
5179     { "vpmulhuw",       { XM, Vex, EXx }, 0 },
5180   },
5181
5182   /* PREFIX_VEX_0FE5 */
5183   {
5184     { Bad_Opcode },
5185     { Bad_Opcode },
5186     { "vpmulhw",        { XM, Vex, EXx }, 0 },
5187   },
5188
5189   /* PREFIX_VEX_0FE6 */
5190   {
5191     { Bad_Opcode },
5192     { "vcvtdq2pd",      { XM, EXxmmq }, 0 },
5193     { "vcvttpd2dq%XY",  { XMM, EXx }, 0 },
5194     { "vcvtpd2dq%XY",   { XMM, EXx }, 0 },
5195   },
5196
5197   /* PREFIX_VEX_0FE7 */
5198   {
5199     { Bad_Opcode },
5200     { Bad_Opcode },
5201     { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) },
5202   },
5203
5204   /* PREFIX_VEX_0FE8 */
5205   {
5206     { Bad_Opcode },
5207     { Bad_Opcode },
5208     { "vpsubsb",        { XM, Vex, EXx }, 0 },
5209   },
5210
5211   /* PREFIX_VEX_0FE9 */
5212   {
5213     { Bad_Opcode },
5214     { Bad_Opcode },
5215     { "vpsubsw",        { XM, Vex, EXx }, 0 },
5216   },
5217
5218   /* PREFIX_VEX_0FEA */
5219   {
5220     { Bad_Opcode },
5221     { Bad_Opcode },
5222     { "vpminsw",        { XM, Vex, EXx }, 0 },
5223   },
5224
5225   /* PREFIX_VEX_0FEB */
5226   {
5227     { Bad_Opcode },
5228     { Bad_Opcode },
5229     { "vpor",           { XM, Vex, EXx }, 0 },
5230   },
5231
5232   /* PREFIX_VEX_0FEC */
5233   {
5234     { Bad_Opcode },
5235     { Bad_Opcode },
5236     { "vpaddsb",        { XM, Vex, EXx }, 0 },
5237   },
5238
5239   /* PREFIX_VEX_0FED */
5240   {
5241     { Bad_Opcode },
5242     { Bad_Opcode },
5243     { "vpaddsw",        { XM, Vex, EXx }, 0 },
5244   },
5245
5246   /* PREFIX_VEX_0FEE */
5247   {
5248     { Bad_Opcode },
5249     { Bad_Opcode },
5250     { "vpmaxsw",        { XM, Vex, EXx }, 0 },
5251   },
5252
5253   /* PREFIX_VEX_0FEF */
5254   {
5255     { Bad_Opcode },
5256     { Bad_Opcode },
5257     { "vpxor",          { XM, Vex, EXx }, 0 },
5258   },
5259
5260   /* PREFIX_VEX_0FF0 */
5261   {
5262     { Bad_Opcode },
5263     { Bad_Opcode },
5264     { Bad_Opcode },
5265     { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
5266   },
5267
5268   /* PREFIX_VEX_0FF1 */
5269   {
5270     { Bad_Opcode },
5271     { Bad_Opcode },
5272     { "vpsllw",         { XM, Vex, EXxmm }, 0 },
5273   },
5274
5275   /* PREFIX_VEX_0FF2 */
5276   {
5277     { Bad_Opcode },
5278     { Bad_Opcode },
5279     { "vpslld",         { XM, Vex, EXxmm }, 0 },
5280   },
5281
5282   /* PREFIX_VEX_0FF3 */
5283   {
5284     { Bad_Opcode },
5285     { Bad_Opcode },
5286     { "vpsllq",         { XM, Vex, EXxmm }, 0 },
5287   },
5288
5289   /* PREFIX_VEX_0FF4 */
5290   {
5291     { Bad_Opcode },
5292     { Bad_Opcode },
5293     { "vpmuludq",       { XM, Vex, EXx }, 0 },
5294   },
5295
5296   /* PREFIX_VEX_0FF5 */
5297   {
5298     { Bad_Opcode },
5299     { Bad_Opcode },
5300     { "vpmaddwd",       { XM, Vex, EXx }, 0 },
5301   },
5302
5303   /* PREFIX_VEX_0FF6 */
5304   {
5305     { Bad_Opcode },
5306     { Bad_Opcode },
5307     { "vpsadbw",        { XM, Vex, EXx }, 0 },
5308   },
5309
5310   /* PREFIX_VEX_0FF7 */
5311   {
5312     { Bad_Opcode },
5313     { Bad_Opcode },
5314     { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) },
5315   },
5316
5317   /* PREFIX_VEX_0FF8 */
5318   {
5319     { Bad_Opcode },
5320     { Bad_Opcode },
5321     { "vpsubb",         { XM, Vex, EXx }, 0 },
5322   },
5323
5324   /* PREFIX_VEX_0FF9 */
5325   {
5326     { Bad_Opcode },
5327     { Bad_Opcode },
5328     { "vpsubw",         { XM, Vex, EXx }, 0 },
5329   },
5330
5331   /* PREFIX_VEX_0FFA */
5332   {
5333     { Bad_Opcode },
5334     { Bad_Opcode },
5335     { "vpsubd",         { XM, Vex, EXx }, 0 },
5336   },
5337
5338   /* PREFIX_VEX_0FFB */
5339   {
5340     { Bad_Opcode },
5341     { Bad_Opcode },
5342     { "vpsubq",         { XM, Vex, EXx }, 0 },
5343   },
5344
5345   /* PREFIX_VEX_0FFC */
5346   {
5347     { Bad_Opcode },
5348     { Bad_Opcode },
5349     { "vpaddb",         { XM, Vex, EXx }, 0 },
5350   },
5351
5352   /* PREFIX_VEX_0FFD */
5353   {
5354     { Bad_Opcode },
5355     { Bad_Opcode },
5356     { "vpaddw",         { XM, Vex, EXx }, 0 },
5357   },
5358
5359   /* PREFIX_VEX_0FFE */
5360   {
5361     { Bad_Opcode },
5362     { Bad_Opcode },
5363     { "vpaddd",         { XM, Vex, EXx }, 0 },
5364   },
5365
5366   /* PREFIX_VEX_0F3800 */
5367   {
5368     { Bad_Opcode },
5369     { Bad_Opcode },
5370     { "vpshufb",        { XM, Vex, EXx }, 0 },
5371   },
5372
5373   /* PREFIX_VEX_0F3801 */
5374   {
5375     { Bad_Opcode },
5376     { Bad_Opcode },
5377     { "vphaddw",        { XM, Vex, EXx }, 0 },
5378   },
5379
5380   /* PREFIX_VEX_0F3802 */
5381   {
5382     { Bad_Opcode },
5383     { Bad_Opcode },
5384     { "vphaddd",        { XM, Vex, EXx }, 0 },
5385   },
5386
5387   /* PREFIX_VEX_0F3803 */
5388   {
5389     { Bad_Opcode },
5390     { Bad_Opcode },
5391     { "vphaddsw",       { XM, Vex, EXx }, 0 },
5392   },
5393
5394   /* PREFIX_VEX_0F3804 */
5395   {
5396     { Bad_Opcode },
5397     { Bad_Opcode },
5398     { "vpmaddubsw",     { XM, Vex, EXx }, 0 },
5399   },
5400
5401   /* PREFIX_VEX_0F3805 */
5402   {
5403     { Bad_Opcode },
5404     { Bad_Opcode },
5405     { "vphsubw",        { XM, Vex, EXx }, 0 },
5406   },
5407
5408   /* PREFIX_VEX_0F3806 */
5409   {
5410     { Bad_Opcode },
5411     { Bad_Opcode },
5412     { "vphsubd",        { XM, Vex, EXx }, 0 },
5413   },
5414
5415   /* PREFIX_VEX_0F3807 */
5416   {
5417     { Bad_Opcode },
5418     { Bad_Opcode },
5419     { "vphsubsw",       { XM, Vex, EXx }, 0 },
5420   },
5421
5422   /* PREFIX_VEX_0F3808 */
5423   {
5424     { Bad_Opcode },
5425     { Bad_Opcode },
5426     { "vpsignb",        { XM, Vex, EXx }, 0 },
5427   },
5428
5429   /* PREFIX_VEX_0F3809 */
5430   {
5431     { Bad_Opcode },
5432     { Bad_Opcode },
5433     { "vpsignw",        { XM, Vex, EXx }, 0 },
5434   },
5435
5436   /* PREFIX_VEX_0F380A */
5437   {
5438     { Bad_Opcode },
5439     { Bad_Opcode },
5440     { "vpsignd",        { XM, Vex, EXx }, 0 },
5441   },
5442
5443   /* PREFIX_VEX_0F380B */
5444   {
5445     { Bad_Opcode },
5446     { Bad_Opcode },
5447     { "vpmulhrsw",      { XM, Vex, EXx }, 0 },
5448   },
5449
5450   /* PREFIX_VEX_0F380C */
5451   {
5452     { Bad_Opcode },
5453     { Bad_Opcode },
5454     { VEX_W_TABLE (VEX_W_0F380C_P_2) },
5455   },
5456
5457   /* PREFIX_VEX_0F380D */
5458   {
5459     { Bad_Opcode },
5460     { Bad_Opcode },
5461     { VEX_W_TABLE (VEX_W_0F380D_P_2) },
5462   },
5463
5464   /* PREFIX_VEX_0F380E */
5465   {
5466     { Bad_Opcode },
5467     { Bad_Opcode },
5468     { VEX_W_TABLE (VEX_W_0F380E_P_2) },
5469   },
5470
5471   /* PREFIX_VEX_0F380F */
5472   {
5473     { Bad_Opcode },
5474     { Bad_Opcode },
5475     { VEX_W_TABLE (VEX_W_0F380F_P_2) },
5476   },
5477
5478   /* PREFIX_VEX_0F3813 */
5479   {
5480     { Bad_Opcode },
5481     { Bad_Opcode },
5482     { VEX_W_TABLE (VEX_W_0F3813_P_2) },
5483   },
5484
5485   /* PREFIX_VEX_0F3816 */
5486   {
5487     { Bad_Opcode },
5488     { Bad_Opcode },
5489     { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) },
5490   },
5491
5492   /* PREFIX_VEX_0F3817 */
5493   {
5494     { Bad_Opcode },
5495     { Bad_Opcode },
5496     { "vptest",         { XM, EXx }, 0 },
5497   },
5498
5499   /* PREFIX_VEX_0F3818 */
5500   {
5501     { Bad_Opcode },
5502     { Bad_Opcode },
5503     { VEX_W_TABLE (VEX_W_0F3818_P_2) },
5504   },
5505
5506   /* PREFIX_VEX_0F3819 */
5507   {
5508     { Bad_Opcode },
5509     { Bad_Opcode },
5510     { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) },
5511   },
5512
5513   /* PREFIX_VEX_0F381A */
5514   {
5515     { Bad_Opcode },
5516     { Bad_Opcode },
5517     { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) },
5518   },
5519
5520   /* PREFIX_VEX_0F381C */
5521   {
5522     { Bad_Opcode },
5523     { Bad_Opcode },
5524     { "vpabsb",         { XM, EXx }, 0 },
5525   },
5526
5527   /* PREFIX_VEX_0F381D */
5528   {
5529     { Bad_Opcode },
5530     { Bad_Opcode },
5531     { "vpabsw",         { XM, EXx }, 0 },
5532   },
5533
5534   /* PREFIX_VEX_0F381E */
5535   {
5536     { Bad_Opcode },
5537     { Bad_Opcode },
5538     { "vpabsd",         { XM, EXx }, 0 },
5539   },
5540
5541   /* PREFIX_VEX_0F3820 */
5542   {
5543     { Bad_Opcode },
5544     { Bad_Opcode },
5545     { "vpmovsxbw",      { XM, EXxmmq }, 0 },
5546   },
5547
5548   /* PREFIX_VEX_0F3821 */
5549   {
5550     { Bad_Opcode },
5551     { Bad_Opcode },
5552     { "vpmovsxbd",      { XM, EXxmmqd }, 0 },
5553   },
5554
5555   /* PREFIX_VEX_0F3822 */
5556   {
5557     { Bad_Opcode },
5558     { Bad_Opcode },
5559     { "vpmovsxbq",      { XM, EXxmmdw }, 0 },
5560   },
5561
5562   /* PREFIX_VEX_0F3823 */
5563   {
5564     { Bad_Opcode },
5565     { Bad_Opcode },
5566     { "vpmovsxwd",      { XM, EXxmmq }, 0 },
5567   },
5568
5569   /* PREFIX_VEX_0F3824 */
5570   {
5571     { Bad_Opcode },
5572     { Bad_Opcode },
5573     { "vpmovsxwq",      { XM, EXxmmqd }, 0 },
5574   },
5575
5576   /* PREFIX_VEX_0F3825 */
5577   {
5578     { Bad_Opcode },
5579     { Bad_Opcode },
5580     { "vpmovsxdq",      { XM, EXxmmq }, 0 },
5581   },
5582
5583   /* PREFIX_VEX_0F3828 */
5584   {
5585     { Bad_Opcode },
5586     { Bad_Opcode },
5587     { "vpmuldq",        { XM, Vex, EXx }, 0 },
5588   },
5589
5590   /* PREFIX_VEX_0F3829 */
5591   {
5592     { Bad_Opcode },
5593     { Bad_Opcode },
5594     { "vpcmpeqq",       { XM, Vex, EXx }, 0 },
5595   },
5596
5597   /* PREFIX_VEX_0F382A */
5598   {
5599     { Bad_Opcode },
5600     { Bad_Opcode },
5601     { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) },
5602   },
5603
5604   /* PREFIX_VEX_0F382B */
5605   {
5606     { Bad_Opcode },
5607     { Bad_Opcode },
5608     { "vpackusdw",      { XM, Vex, EXx }, 0 },
5609   },
5610
5611   /* PREFIX_VEX_0F382C */
5612   {
5613     { Bad_Opcode },
5614     { Bad_Opcode },
5615      { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) },
5616   },
5617
5618   /* PREFIX_VEX_0F382D */
5619   {
5620     { Bad_Opcode },
5621     { Bad_Opcode },
5622      { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) },
5623   },
5624
5625   /* PREFIX_VEX_0F382E */
5626   {
5627     { Bad_Opcode },
5628     { Bad_Opcode },
5629      { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) },
5630   },
5631
5632   /* PREFIX_VEX_0F382F */
5633   {
5634     { Bad_Opcode },
5635     { Bad_Opcode },
5636      { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) },
5637   },
5638
5639   /* PREFIX_VEX_0F3830 */
5640   {
5641     { Bad_Opcode },
5642     { Bad_Opcode },
5643     { "vpmovzxbw",      { XM, EXxmmq }, 0 },
5644   },
5645
5646   /* PREFIX_VEX_0F3831 */
5647   {
5648     { Bad_Opcode },
5649     { Bad_Opcode },
5650     { "vpmovzxbd",      { XM, EXxmmqd }, 0 },
5651   },
5652
5653   /* PREFIX_VEX_0F3832 */
5654   {
5655     { Bad_Opcode },
5656     { Bad_Opcode },
5657     { "vpmovzxbq",      { XM, EXxmmdw }, 0 },
5658   },
5659
5660   /* PREFIX_VEX_0F3833 */
5661   {
5662     { Bad_Opcode },
5663     { Bad_Opcode },
5664     { "vpmovzxwd",      { XM, EXxmmq }, 0 },
5665   },
5666
5667   /* PREFIX_VEX_0F3834 */
5668   {
5669     { Bad_Opcode },
5670     { Bad_Opcode },
5671     { "vpmovzxwq",      { XM, EXxmmqd }, 0 },
5672   },
5673
5674   /* PREFIX_VEX_0F3835 */
5675   {
5676     { Bad_Opcode },
5677     { Bad_Opcode },
5678     { "vpmovzxdq",      { XM, EXxmmq }, 0 },
5679   },
5680
5681   /* PREFIX_VEX_0F3836 */
5682   {
5683     { Bad_Opcode },
5684     { Bad_Opcode },
5685     { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) },
5686   },
5687
5688   /* PREFIX_VEX_0F3837 */
5689   {
5690     { Bad_Opcode },
5691     { Bad_Opcode },
5692     { "vpcmpgtq",       { XM, Vex, EXx }, 0 },
5693   },
5694
5695   /* PREFIX_VEX_0F3838 */
5696   {
5697     { Bad_Opcode },
5698     { Bad_Opcode },
5699     { "vpminsb",        { XM, Vex, EXx }, 0 },
5700   },
5701
5702   /* PREFIX_VEX_0F3839 */
5703   {
5704     { Bad_Opcode },
5705     { Bad_Opcode },
5706     { "vpminsd",        { XM, Vex, EXx }, 0 },
5707   },
5708
5709   /* PREFIX_VEX_0F383A */
5710   {
5711     { Bad_Opcode },
5712     { Bad_Opcode },
5713     { "vpminuw",        { XM, Vex, EXx }, 0 },
5714   },
5715
5716   /* PREFIX_VEX_0F383B */
5717   {
5718     { Bad_Opcode },
5719     { Bad_Opcode },
5720     { "vpminud",        { XM, Vex, EXx }, 0 },
5721   },
5722
5723   /* PREFIX_VEX_0F383C */
5724   {
5725     { Bad_Opcode },
5726     { Bad_Opcode },
5727     { "vpmaxsb",        { XM, Vex, EXx }, 0 },
5728   },
5729
5730   /* PREFIX_VEX_0F383D */
5731   {
5732     { Bad_Opcode },
5733     { Bad_Opcode },
5734     { "vpmaxsd",        { XM, Vex, EXx }, 0 },
5735   },
5736
5737   /* PREFIX_VEX_0F383E */
5738   {
5739     { Bad_Opcode },
5740     { Bad_Opcode },
5741     { "vpmaxuw",        { XM, Vex, EXx }, 0 },
5742   },
5743
5744   /* PREFIX_VEX_0F383F */
5745   {
5746     { Bad_Opcode },
5747     { Bad_Opcode },
5748     { "vpmaxud",        { XM, Vex, EXx }, 0 },
5749   },
5750
5751   /* PREFIX_VEX_0F3840 */
5752   {
5753     { Bad_Opcode },
5754     { Bad_Opcode },
5755     { "vpmulld",        { XM, Vex, EXx }, 0 },
5756   },
5757
5758   /* PREFIX_VEX_0F3841 */
5759   {
5760     { Bad_Opcode },
5761     { Bad_Opcode },
5762     { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) },
5763   },
5764
5765   /* PREFIX_VEX_0F3845 */
5766   {
5767     { Bad_Opcode },
5768     { Bad_Opcode },
5769     { "vpsrlv%LW", { XM, Vex, EXx }, 0 },
5770   },
5771
5772   /* PREFIX_VEX_0F3846 */
5773   {
5774     { Bad_Opcode },
5775     { Bad_Opcode },
5776     { VEX_W_TABLE (VEX_W_0F3846_P_2) },
5777   },
5778
5779   /* PREFIX_VEX_0F3847 */
5780   {
5781     { Bad_Opcode },
5782     { Bad_Opcode },
5783     { "vpsllv%LW", { XM, Vex, EXx }, 0 },
5784   },
5785
5786   /* PREFIX_VEX_0F3858 */
5787   {
5788     { Bad_Opcode },
5789     { Bad_Opcode },
5790     { VEX_W_TABLE (VEX_W_0F3858_P_2) },
5791   },
5792
5793   /* PREFIX_VEX_0F3859 */
5794   {
5795     { Bad_Opcode },
5796     { Bad_Opcode },
5797     { VEX_W_TABLE (VEX_W_0F3859_P_2) },
5798   },
5799
5800   /* PREFIX_VEX_0F385A */
5801   {
5802     { Bad_Opcode },
5803     { Bad_Opcode },
5804     { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) },
5805   },
5806
5807   /* PREFIX_VEX_0F3878 */
5808   {
5809     { Bad_Opcode },
5810     { Bad_Opcode },
5811     { VEX_W_TABLE (VEX_W_0F3878_P_2) },
5812   },
5813
5814   /* PREFIX_VEX_0F3879 */
5815   {
5816     { Bad_Opcode },
5817     { Bad_Opcode },
5818     { VEX_W_TABLE (VEX_W_0F3879_P_2) },
5819   },
5820
5821   /* PREFIX_VEX_0F388C */
5822   {
5823     { Bad_Opcode },
5824     { Bad_Opcode },
5825     { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) },
5826   },
5827
5828   /* PREFIX_VEX_0F388E */
5829   {
5830     { Bad_Opcode },
5831     { Bad_Opcode },
5832     { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) },
5833   },
5834
5835   /* PREFIX_VEX_0F3890 */
5836   {
5837     { Bad_Opcode },
5838     { Bad_Opcode },
5839     { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex }, 0 },
5840   },
5841
5842   /* PREFIX_VEX_0F3891 */
5843   {
5844     { Bad_Opcode },
5845     { Bad_Opcode },
5846     { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
5847   },
5848
5849   /* PREFIX_VEX_0F3892 */
5850   {
5851     { Bad_Opcode },
5852     { Bad_Opcode },
5853     { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex }, 0 },
5854   },
5855
5856   /* PREFIX_VEX_0F3893 */
5857   {
5858     { Bad_Opcode },
5859     { Bad_Opcode },
5860     { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
5861   },
5862
5863   /* PREFIX_VEX_0F3896 */
5864   {
5865     { Bad_Opcode },
5866     { Bad_Opcode },
5867     { "vfmaddsub132p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
5868   },
5869
5870   /* PREFIX_VEX_0F3897 */
5871   {
5872     { Bad_Opcode },
5873     { Bad_Opcode },
5874     { "vfmsubadd132p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
5875   },
5876
5877   /* PREFIX_VEX_0F3898 */
5878   {
5879     { Bad_Opcode },
5880     { Bad_Opcode },
5881     { "vfmadd132p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
5882   },
5883
5884   /* PREFIX_VEX_0F3899 */
5885   {
5886     { Bad_Opcode },
5887     { Bad_Opcode },
5888     { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
5889   },
5890
5891   /* PREFIX_VEX_0F389A */
5892   {
5893     { Bad_Opcode },
5894     { Bad_Opcode },
5895     { "vfmsub132p%XW", { XM, Vex, EXx }, 0 },
5896   },
5897
5898   /* PREFIX_VEX_0F389B */
5899   {
5900     { Bad_Opcode },
5901     { Bad_Opcode },
5902     { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
5903   },
5904
5905   /* PREFIX_VEX_0F389C */
5906   {
5907     { Bad_Opcode },
5908     { Bad_Opcode },
5909     { "vfnmadd132p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
5910   },
5911
5912   /* PREFIX_VEX_0F389D */
5913   {
5914     { Bad_Opcode },
5915     { Bad_Opcode },
5916     { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
5917   },
5918
5919   /* PREFIX_VEX_0F389E */
5920   {
5921     { Bad_Opcode },
5922     { Bad_Opcode },
5923     { "vfnmsub132p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
5924   },
5925
5926   /* PREFIX_VEX_0F389F */
5927   {
5928     { Bad_Opcode },
5929     { Bad_Opcode },
5930     { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
5931   },
5932
5933   /* PREFIX_VEX_0F38A6 */
5934   {
5935     { Bad_Opcode },
5936     { Bad_Opcode },
5937     { "vfmaddsub213p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
5938     { Bad_Opcode },
5939   },
5940
5941   /* PREFIX_VEX_0F38A7 */
5942   {
5943     { Bad_Opcode },
5944     { Bad_Opcode },
5945     { "vfmsubadd213p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
5946   },
5947
5948   /* PREFIX_VEX_0F38A8 */
5949   {
5950     { Bad_Opcode },
5951     { Bad_Opcode },
5952     { "vfmadd213p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
5953   },
5954
5955   /* PREFIX_VEX_0F38A9 */
5956   {
5957     { Bad_Opcode },
5958     { Bad_Opcode },
5959     { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
5960   },
5961
5962   /* PREFIX_VEX_0F38AA */
5963   {
5964     { Bad_Opcode },
5965     { Bad_Opcode },
5966     { "vfmsub213p%XW", { XM, Vex, EXx }, 0 },
5967   },
5968
5969   /* PREFIX_VEX_0F38AB */
5970   {
5971     { Bad_Opcode },
5972     { Bad_Opcode },
5973     { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
5974   },
5975
5976   /* PREFIX_VEX_0F38AC */
5977   {
5978     { Bad_Opcode },
5979     { Bad_Opcode },
5980     { "vfnmadd213p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
5981   },
5982
5983   /* PREFIX_VEX_0F38AD */
5984   {
5985     { Bad_Opcode },
5986     { Bad_Opcode },
5987     { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
5988   },
5989
5990   /* PREFIX_VEX_0F38AE */
5991   {
5992     { Bad_Opcode },
5993     { Bad_Opcode },
5994     { "vfnmsub213p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
5995   },
5996
5997   /* PREFIX_VEX_0F38AF */
5998   {
5999     { Bad_Opcode },
6000     { Bad_Opcode },
6001     { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
6002   },
6003
6004   /* PREFIX_VEX_0F38B6 */
6005   {
6006     { Bad_Opcode },
6007     { Bad_Opcode },
6008     { "vfmaddsub231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6009   },
6010
6011   /* PREFIX_VEX_0F38B7 */
6012   {
6013     { Bad_Opcode },
6014     { Bad_Opcode },
6015     { "vfmsubadd231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6016   },
6017
6018   /* PREFIX_VEX_0F38B8 */
6019   {
6020     { Bad_Opcode },
6021     { Bad_Opcode },
6022     { "vfmadd231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6023   },
6024
6025   /* PREFIX_VEX_0F38B9 */
6026   {
6027     { Bad_Opcode },
6028     { Bad_Opcode },
6029     { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
6030   },
6031
6032   /* PREFIX_VEX_0F38BA */
6033   {
6034     { Bad_Opcode },
6035     { Bad_Opcode },
6036     { "vfmsub231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6037   },
6038
6039   /* PREFIX_VEX_0F38BB */
6040   {
6041     { Bad_Opcode },
6042     { Bad_Opcode },
6043     { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
6044   },
6045
6046   /* PREFIX_VEX_0F38BC */
6047   {
6048     { Bad_Opcode },
6049     { Bad_Opcode },
6050     { "vfnmadd231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6051   },
6052
6053   /* PREFIX_VEX_0F38BD */
6054   {
6055     { Bad_Opcode },
6056     { Bad_Opcode },
6057     { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
6058   },
6059
6060   /* PREFIX_VEX_0F38BE */
6061   {
6062     { Bad_Opcode },
6063     { Bad_Opcode },
6064     { "vfnmsub231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6065   },
6066
6067   /* PREFIX_VEX_0F38BF */
6068   {
6069     { Bad_Opcode },
6070     { Bad_Opcode },
6071     { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
6072   },
6073
6074   /* PREFIX_VEX_0F38CF */
6075   {
6076     { Bad_Opcode },
6077     { Bad_Opcode },
6078     { VEX_W_TABLE (VEX_W_0F38CF_P_2) },
6079   },
6080
6081   /* PREFIX_VEX_0F38DB */
6082   {
6083     { Bad_Opcode },
6084     { Bad_Opcode },
6085     { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) },
6086   },
6087
6088   /* PREFIX_VEX_0F38DC */
6089   {
6090     { Bad_Opcode },
6091     { Bad_Opcode },
6092     { "vaesenc",        { XM, Vex, EXx }, 0 },
6093   },
6094
6095   /* PREFIX_VEX_0F38DD */
6096   {
6097     { Bad_Opcode },
6098     { Bad_Opcode },
6099     { "vaesenclast",    { XM, Vex, EXx }, 0 },
6100   },
6101
6102   /* PREFIX_VEX_0F38DE */
6103   {
6104     { Bad_Opcode },
6105     { Bad_Opcode },
6106     { "vaesdec",        { XM, Vex, EXx }, 0 },
6107   },
6108
6109   /* PREFIX_VEX_0F38DF */
6110   {
6111     { Bad_Opcode },
6112     { Bad_Opcode },
6113     { "vaesdeclast",    { XM, Vex, EXx }, 0 },
6114   },
6115
6116   /* PREFIX_VEX_0F38F2 */
6117   {
6118     { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) },
6119   },
6120
6121   /* PREFIX_VEX_0F38F3_REG_1 */
6122   {
6123     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) },
6124   },
6125
6126   /* PREFIX_VEX_0F38F3_REG_2 */
6127   {
6128     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) },
6129   },
6130
6131   /* PREFIX_VEX_0F38F3_REG_3 */
6132   {
6133     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) },
6134   },
6135
6136   /* PREFIX_VEX_0F38F5 */
6137   {
6138     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) },
6139     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) },
6140     { Bad_Opcode },
6141     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) },
6142   },
6143
6144   /* PREFIX_VEX_0F38F6 */
6145   {
6146     { Bad_Opcode },
6147     { Bad_Opcode },
6148     { Bad_Opcode },
6149     { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) },
6150   },
6151
6152   /* PREFIX_VEX_0F38F7 */
6153   {
6154     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) },
6155     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) },
6156     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) },
6157     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) },
6158   },
6159
6160   /* PREFIX_VEX_0F3A00 */
6161   {
6162     { Bad_Opcode },
6163     { Bad_Opcode },
6164     { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) },
6165   },
6166
6167   /* PREFIX_VEX_0F3A01 */
6168   {
6169     { Bad_Opcode },
6170     { Bad_Opcode },
6171     { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) },
6172   },
6173
6174   /* PREFIX_VEX_0F3A02 */
6175   {
6176     { Bad_Opcode },
6177     { Bad_Opcode },
6178     { VEX_W_TABLE (VEX_W_0F3A02_P_2) },
6179   },
6180
6181   /* PREFIX_VEX_0F3A04 */
6182   {
6183     { Bad_Opcode },
6184     { Bad_Opcode },
6185     { VEX_W_TABLE (VEX_W_0F3A04_P_2) },
6186   },
6187
6188   /* PREFIX_VEX_0F3A05 */
6189   {
6190     { Bad_Opcode },
6191     { Bad_Opcode },
6192     { VEX_W_TABLE (VEX_W_0F3A05_P_2) },
6193   },
6194
6195   /* PREFIX_VEX_0F3A06 */
6196   {
6197     { Bad_Opcode },
6198     { Bad_Opcode },
6199     { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) },
6200   },
6201
6202   /* PREFIX_VEX_0F3A08 */
6203   {
6204     { Bad_Opcode },
6205     { Bad_Opcode },
6206     { "vroundps",       { XM, EXx, Ib }, 0 },
6207   },
6208
6209   /* PREFIX_VEX_0F3A09 */
6210   {
6211     { Bad_Opcode },
6212     { Bad_Opcode },
6213     { "vroundpd",       { XM, EXx, Ib }, 0 },
6214   },
6215
6216   /* PREFIX_VEX_0F3A0A */
6217   {
6218     { Bad_Opcode },
6219     { Bad_Opcode },
6220     { "vroundss",       { XMScalar, VexScalar, EXxmm_md, Ib }, 0 },
6221   },
6222
6223   /* PREFIX_VEX_0F3A0B */
6224   {
6225     { Bad_Opcode },
6226     { Bad_Opcode },
6227     { "vroundsd",       { XMScalar, VexScalar, EXxmm_mq, Ib }, 0 },
6228   },
6229
6230   /* PREFIX_VEX_0F3A0C */
6231   {
6232     { Bad_Opcode },
6233     { Bad_Opcode },
6234     { "vblendps",       { XM, Vex, EXx, Ib }, 0 },
6235   },
6236
6237   /* PREFIX_VEX_0F3A0D */
6238   {
6239     { Bad_Opcode },
6240     { Bad_Opcode },
6241     { "vblendpd",       { XM, Vex, EXx, Ib }, 0 },
6242   },
6243
6244   /* PREFIX_VEX_0F3A0E */
6245   {
6246     { Bad_Opcode },
6247     { Bad_Opcode },
6248     { "vpblendw",       { XM, Vex, EXx, Ib }, 0 },
6249   },
6250
6251   /* PREFIX_VEX_0F3A0F */
6252   {
6253     { Bad_Opcode },
6254     { Bad_Opcode },
6255     { "vpalignr",       { XM, Vex, EXx, Ib }, 0 },
6256   },
6257
6258   /* PREFIX_VEX_0F3A14 */
6259   {
6260     { Bad_Opcode },
6261     { Bad_Opcode },
6262     { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) },
6263   },
6264
6265   /* PREFIX_VEX_0F3A15 */
6266   {
6267     { Bad_Opcode },
6268     { Bad_Opcode },
6269     { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) },
6270   },
6271
6272   /* PREFIX_VEX_0F3A16 */
6273   {
6274     { Bad_Opcode },
6275     { Bad_Opcode },
6276     { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) },
6277   },
6278
6279   /* PREFIX_VEX_0F3A17 */
6280   {
6281     { Bad_Opcode },
6282     { Bad_Opcode },
6283     { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) },
6284   },
6285
6286   /* PREFIX_VEX_0F3A18 */
6287   {
6288     { Bad_Opcode },
6289     { Bad_Opcode },
6290     { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) },
6291   },
6292
6293   /* PREFIX_VEX_0F3A19 */
6294   {
6295     { Bad_Opcode },
6296     { Bad_Opcode },
6297     { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) },
6298   },
6299
6300   /* PREFIX_VEX_0F3A1D */
6301   {
6302     { Bad_Opcode },
6303     { Bad_Opcode },
6304     { VEX_W_TABLE (VEX_W_0F3A1D_P_2) },
6305   },
6306
6307   /* PREFIX_VEX_0F3A20 */
6308   {
6309     { Bad_Opcode },
6310     { Bad_Opcode },
6311     { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) },
6312   },
6313
6314   /* PREFIX_VEX_0F3A21 */
6315   {
6316     { Bad_Opcode },
6317     { Bad_Opcode },
6318     { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) },
6319   },
6320
6321   /* PREFIX_VEX_0F3A22 */
6322   {
6323     { Bad_Opcode },
6324     { Bad_Opcode },
6325     { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) },
6326   },
6327
6328   /* PREFIX_VEX_0F3A30 */
6329   {
6330     { Bad_Opcode },
6331     { Bad_Opcode },
6332     { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2) },
6333   },
6334
6335   /* PREFIX_VEX_0F3A31 */
6336   {
6337     { Bad_Opcode },
6338     { Bad_Opcode },
6339     { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2) },
6340   },
6341
6342   /* PREFIX_VEX_0F3A32 */
6343   {
6344     { Bad_Opcode },
6345     { Bad_Opcode },
6346     { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2) },
6347   },
6348
6349   /* PREFIX_VEX_0F3A33 */
6350   {
6351     { Bad_Opcode },
6352     { Bad_Opcode },
6353     { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2) },
6354   },
6355
6356   /* PREFIX_VEX_0F3A38 */
6357   {
6358     { Bad_Opcode },
6359     { Bad_Opcode },
6360     { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) },
6361   },
6362
6363   /* PREFIX_VEX_0F3A39 */
6364   {
6365     { Bad_Opcode },
6366     { Bad_Opcode },
6367     { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) },
6368   },
6369
6370   /* PREFIX_VEX_0F3A40 */
6371   {
6372     { Bad_Opcode },
6373     { Bad_Opcode },
6374     { "vdpps",          { XM, Vex, EXx, Ib }, 0 },
6375   },
6376
6377   /* PREFIX_VEX_0F3A41 */
6378   {
6379     { Bad_Opcode },
6380     { Bad_Opcode },
6381     { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) },
6382   },
6383
6384   /* PREFIX_VEX_0F3A42 */
6385   {
6386     { Bad_Opcode },
6387     { Bad_Opcode },
6388     { "vmpsadbw",       { XM, Vex, EXx, Ib }, 0 },
6389   },
6390
6391   /* PREFIX_VEX_0F3A44 */
6392   {
6393     { Bad_Opcode },
6394     { Bad_Opcode },
6395     { "vpclmulqdq",     { XM, Vex, EXx, PCLMUL }, 0 },
6396   },
6397
6398   /* PREFIX_VEX_0F3A46 */
6399   {
6400     { Bad_Opcode },
6401     { Bad_Opcode },
6402     { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) },
6403   },
6404
6405   /* PREFIX_VEX_0F3A48 */
6406   {
6407     { Bad_Opcode },
6408     { Bad_Opcode },
6409     { "vpermil2ps",     { XM, Vex, EXx, XMVexI4, VexI4 }, 0 },
6410   },
6411
6412   /* PREFIX_VEX_0F3A49 */
6413   {
6414     { Bad_Opcode },
6415     { Bad_Opcode },
6416     { "vpermil2pd",     { XM, Vex, EXx, XMVexI4, VexI4 }, 0 },
6417   },
6418
6419   /* PREFIX_VEX_0F3A4A */
6420   {
6421     { Bad_Opcode },
6422     { Bad_Opcode },
6423     { VEX_W_TABLE (VEX_W_0F3A4A_P_2) },
6424   },
6425
6426   /* PREFIX_VEX_0F3A4B */
6427   {
6428     { Bad_Opcode },
6429     { Bad_Opcode },
6430     { VEX_W_TABLE (VEX_W_0F3A4B_P_2) },
6431   },
6432
6433   /* PREFIX_VEX_0F3A4C */
6434   {
6435     { Bad_Opcode },
6436     { Bad_Opcode },
6437     { VEX_W_TABLE (VEX_W_0F3A4C_P_2) },
6438   },
6439
6440   /* PREFIX_VEX_0F3A5C */
6441   {
6442     { Bad_Opcode },
6443     { Bad_Opcode },
6444     { "vfmaddsubps", { XM, Vex, EXx, XMVexI4 }, 0 },
6445   },
6446
6447   /* PREFIX_VEX_0F3A5D */
6448   {
6449     { Bad_Opcode },
6450     { Bad_Opcode },
6451     { "vfmaddsubpd", { XM, Vex, EXx, XMVexI4 }, 0 },
6452   },
6453
6454   /* PREFIX_VEX_0F3A5E */
6455   {
6456     { Bad_Opcode },
6457     { Bad_Opcode },
6458     { "vfmsubaddps", { XM, Vex, EXx, XMVexI4 }, 0 },
6459   },
6460
6461   /* PREFIX_VEX_0F3A5F */
6462   {
6463     { Bad_Opcode },
6464     { Bad_Opcode },
6465     { "vfmsubaddpd", { XM, Vex, EXx, XMVexI4 }, 0 },
6466   },
6467
6468   /* PREFIX_VEX_0F3A60 */
6469   {
6470     { Bad_Opcode },
6471     { Bad_Opcode },
6472     { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) },
6473     { Bad_Opcode },
6474   },
6475
6476   /* PREFIX_VEX_0F3A61 */
6477   {
6478     { Bad_Opcode },
6479     { Bad_Opcode },
6480     { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) },
6481   },
6482
6483   /* PREFIX_VEX_0F3A62 */
6484   {
6485     { Bad_Opcode },
6486     { Bad_Opcode },
6487     { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) },
6488   },
6489
6490   /* PREFIX_VEX_0F3A63 */
6491   {
6492     { Bad_Opcode },
6493     { Bad_Opcode },
6494     { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) },
6495   },
6496
6497   /* PREFIX_VEX_0F3A68 */
6498   {
6499     { Bad_Opcode },
6500     { Bad_Opcode },
6501     { "vfmaddps", { XM, Vex, EXx, XMVexI4 }, 0 },
6502   },
6503
6504   /* PREFIX_VEX_0F3A69 */
6505   {
6506     { Bad_Opcode },
6507     { Bad_Opcode },
6508     { "vfmaddpd", { XM, Vex, EXx, XMVexI4 }, 0 },
6509   },
6510
6511   /* PREFIX_VEX_0F3A6A */
6512   {
6513     { Bad_Opcode },
6514     { Bad_Opcode },
6515     { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) },
6516   },
6517
6518   /* PREFIX_VEX_0F3A6B */
6519   {
6520     { Bad_Opcode },
6521     { Bad_Opcode },
6522     { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) },
6523   },
6524
6525   /* PREFIX_VEX_0F3A6C */
6526   {
6527     { Bad_Opcode },
6528     { Bad_Opcode },
6529     { "vfmsubps", { XM, Vex, EXx, XMVexI4 }, 0 },
6530   },
6531
6532   /* PREFIX_VEX_0F3A6D */
6533   {
6534     { Bad_Opcode },
6535     { Bad_Opcode },
6536     { "vfmsubpd", { XM, Vex, EXx, XMVexI4 }, 0 },
6537   },
6538
6539   /* PREFIX_VEX_0F3A6E */
6540   {
6541     { Bad_Opcode },
6542     { Bad_Opcode },
6543     { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) },
6544   },
6545
6546   /* PREFIX_VEX_0F3A6F */
6547   {
6548     { Bad_Opcode },
6549     { Bad_Opcode },
6550     { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) },
6551   },
6552
6553   /* PREFIX_VEX_0F3A78 */
6554   {
6555     { Bad_Opcode },
6556     { Bad_Opcode },
6557     { "vfnmaddps", { XM, Vex, EXx, XMVexI4 }, 0 },
6558   },
6559
6560   /* PREFIX_VEX_0F3A79 */
6561   {
6562     { Bad_Opcode },
6563     { Bad_Opcode },
6564     { "vfnmaddpd", { XM, Vex, EXx, XMVexI4 }, 0 },
6565   },
6566
6567   /* PREFIX_VEX_0F3A7A */
6568   {
6569     { Bad_Opcode },
6570     { Bad_Opcode },
6571     { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) },
6572   },
6573
6574   /* PREFIX_VEX_0F3A7B */
6575   {
6576     { Bad_Opcode },
6577     { Bad_Opcode },
6578     { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) },
6579   },
6580
6581   /* PREFIX_VEX_0F3A7C */
6582   {
6583     { Bad_Opcode },
6584     { Bad_Opcode },
6585     { "vfnmsubps", { XM, Vex, EXx, XMVexI4 }, 0 },
6586     { Bad_Opcode },
6587   },
6588
6589   /* PREFIX_VEX_0F3A7D */
6590   {
6591     { Bad_Opcode },
6592     { Bad_Opcode },
6593     { "vfnmsubpd", { XM, Vex, EXx, XMVexI4 }, 0 },
6594   },
6595
6596   /* PREFIX_VEX_0F3A7E */
6597   {
6598     { Bad_Opcode },
6599     { Bad_Opcode },
6600     { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) },
6601   },
6602
6603   /* PREFIX_VEX_0F3A7F */
6604   {
6605     { Bad_Opcode },
6606     { Bad_Opcode },
6607     { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) },
6608   },
6609
6610   /* PREFIX_VEX_0F3ACE */
6611   {
6612     { Bad_Opcode },
6613     { Bad_Opcode },
6614     { VEX_W_TABLE (VEX_W_0F3ACE_P_2) },
6615   },
6616
6617   /* PREFIX_VEX_0F3ACF */
6618   {
6619     { Bad_Opcode },
6620     { Bad_Opcode },
6621     { VEX_W_TABLE (VEX_W_0F3ACF_P_2) },
6622   },
6623
6624   /* PREFIX_VEX_0F3ADF */
6625   {
6626     { Bad_Opcode },
6627     { Bad_Opcode },
6628     { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) },
6629   },
6630
6631   /* PREFIX_VEX_0F3AF0 */
6632   {
6633     { Bad_Opcode },
6634     { Bad_Opcode },
6635     { Bad_Opcode },
6636     { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) },
6637   },
6638
6639 #include "i386-dis-evex-prefix.h"
6640 };
6641
6642 static const struct dis386 x86_64_table[][2] = {
6643   /* X86_64_06 */
6644   {
6645     { "pushP", { es }, 0 },
6646   },
6647
6648   /* X86_64_07 */
6649   {
6650     { "popP", { es }, 0 },
6651   },
6652
6653   /* X86_64_0E */
6654   {
6655     { "pushP", { cs }, 0 },
6656   },
6657
6658   /* X86_64_16 */
6659   {
6660     { "pushP", { ss }, 0 },
6661   },
6662
6663   /* X86_64_17 */
6664   {
6665     { "popP", { ss }, 0 },
6666   },
6667
6668   /* X86_64_1E */
6669   {
6670     { "pushP", { ds }, 0 },
6671   },
6672
6673   /* X86_64_1F */
6674   {
6675     { "popP", { ds }, 0 },
6676   },
6677
6678   /* X86_64_27 */
6679   {
6680     { "daa", { XX }, 0 },
6681   },
6682
6683   /* X86_64_2F */
6684   {
6685     { "das", { XX }, 0 },
6686   },
6687
6688   /* X86_64_37 */
6689   {
6690     { "aaa", { XX }, 0 },
6691   },
6692
6693   /* X86_64_3F */
6694   {
6695     { "aas", { XX }, 0 },
6696   },
6697
6698   /* X86_64_60 */
6699   {
6700     { "pushaP", { XX }, 0 },
6701   },
6702
6703   /* X86_64_61 */
6704   {
6705     { "popaP", { XX }, 0 },
6706   },
6707
6708   /* X86_64_62 */
6709   {
6710     { MOD_TABLE (MOD_62_32BIT) },
6711     { EVEX_TABLE (EVEX_0F) },
6712   },
6713
6714   /* X86_64_63 */
6715   {
6716     { "arpl", { Ew, Gw }, 0 },
6717     { "movs", { { OP_G, movsxd_mode }, { MOVSXD_Fixup, movsxd_mode } }, 0 },
6718   },
6719
6720   /* X86_64_6D */
6721   {
6722     { "ins{R|}", { Yzr, indirDX }, 0 },
6723     { "ins{G|}", { Yzr, indirDX }, 0 },
6724   },
6725
6726   /* X86_64_6F */
6727   {
6728     { "outs{R|}", { indirDXr, Xz }, 0 },
6729     { "outs{G|}", { indirDXr, Xz }, 0 },
6730   },
6731
6732   /* X86_64_82 */
6733   {
6734     /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode.  */
6735     { REG_TABLE (REG_80) },
6736   },
6737
6738   /* X86_64_9A */
6739   {
6740     { "{l|}call{T|}", { Ap }, 0 },
6741   },
6742
6743   /* X86_64_C2 */
6744   {
6745     { "retP",           { Iw, BND }, 0 },
6746     { "ret@",           { Iw, BND }, 0 },
6747   },
6748
6749   /* X86_64_C3 */
6750   {
6751     { "retP",           { BND }, 0 },
6752     { "ret@",           { BND }, 0 },
6753   },
6754
6755   /* X86_64_C4 */
6756   {
6757     { MOD_TABLE (MOD_C4_32BIT) },
6758     { VEX_C4_TABLE (VEX_0F) },
6759   },
6760
6761   /* X86_64_C5 */
6762   {
6763     { MOD_TABLE (MOD_C5_32BIT) },
6764     { VEX_C5_TABLE (VEX_0F) },
6765   },
6766
6767   /* X86_64_CE */
6768   {
6769     { "into", { XX }, 0 },
6770   },
6771
6772   /* X86_64_D4 */
6773   {
6774     { "aam", { Ib }, 0 },
6775   },
6776
6777   /* X86_64_D5 */
6778   {
6779     { "aad", { Ib }, 0 },
6780   },
6781
6782   /* X86_64_E8 */
6783   {
6784     { "callP",          { Jv, BND }, 0 },
6785     { "call@",          { Jv, BND }, 0 }
6786   },
6787
6788   /* X86_64_E9 */
6789   {
6790     { "jmpP",           { Jv, BND }, 0 },
6791     { "jmp@",           { Jv, BND }, 0 }
6792   },
6793
6794   /* X86_64_EA */
6795   {
6796     { "{l|}jmp{T|}", { Ap }, 0 },
6797   },
6798
6799   /* X86_64_0F01_REG_0 */
6800   {
6801     { "sgdt{Q|Q}", { M }, 0 },
6802     { "sgdt", { M }, 0 },
6803   },
6804
6805   /* X86_64_0F01_REG_1 */
6806   {
6807     { "sidt{Q|Q}", { M }, 0 },
6808     { "sidt", { M }, 0 },
6809   },
6810
6811   /* X86_64_0F01_REG_2 */
6812   {
6813     { "lgdt{Q|Q}", { M }, 0 },
6814     { "lgdt", { M }, 0 },
6815   },
6816
6817   /* X86_64_0F01_REG_3 */
6818   {
6819     { "lidt{Q|Q}", { M }, 0 },
6820     { "lidt", { M }, 0 },
6821   },
6822 };
6823
6824 static const struct dis386 three_byte_table[][256] = {
6825
6826   /* THREE_BYTE_0F38 */
6827   {
6828     /* 00 */
6829     { "pshufb",         { MX, EM }, PREFIX_OPCODE },
6830     { "phaddw",         { MX, EM }, PREFIX_OPCODE },
6831     { "phaddd",         { MX, EM }, PREFIX_OPCODE },
6832     { "phaddsw",        { MX, EM }, PREFIX_OPCODE },
6833     { "pmaddubsw",      { MX, EM }, PREFIX_OPCODE },
6834     { "phsubw",         { MX, EM }, PREFIX_OPCODE },
6835     { "phsubd",         { MX, EM }, PREFIX_OPCODE },
6836     { "phsubsw",        { MX, EM }, PREFIX_OPCODE },
6837     /* 08 */
6838     { "psignb",         { MX, EM }, PREFIX_OPCODE },
6839     { "psignw",         { MX, EM }, PREFIX_OPCODE },
6840     { "psignd",         { MX, EM }, PREFIX_OPCODE },
6841     { "pmulhrsw",       { MX, EM }, PREFIX_OPCODE },
6842     { Bad_Opcode },
6843     { Bad_Opcode },
6844     { Bad_Opcode },
6845     { Bad_Opcode },
6846     /* 10 */
6847     { PREFIX_TABLE (PREFIX_0F3810) },
6848     { Bad_Opcode },
6849     { Bad_Opcode },
6850     { Bad_Opcode },
6851     { PREFIX_TABLE (PREFIX_0F3814) },
6852     { PREFIX_TABLE (PREFIX_0F3815) },
6853     { Bad_Opcode },
6854     { PREFIX_TABLE (PREFIX_0F3817) },
6855     /* 18 */
6856     { Bad_Opcode },
6857     { Bad_Opcode },
6858     { Bad_Opcode },
6859     { Bad_Opcode },
6860     { "pabsb",          { MX, EM }, PREFIX_OPCODE },
6861     { "pabsw",          { MX, EM }, PREFIX_OPCODE },
6862     { "pabsd",          { MX, EM }, PREFIX_OPCODE },
6863     { Bad_Opcode },
6864     /* 20 */
6865     { PREFIX_TABLE (PREFIX_0F3820) },
6866     { PREFIX_TABLE (PREFIX_0F3821) },
6867     { PREFIX_TABLE (PREFIX_0F3822) },
6868     { PREFIX_TABLE (PREFIX_0F3823) },
6869     { PREFIX_TABLE (PREFIX_0F3824) },
6870     { PREFIX_TABLE (PREFIX_0F3825) },
6871     { Bad_Opcode },
6872     { Bad_Opcode },
6873     /* 28 */
6874     { PREFIX_TABLE (PREFIX_0F3828) },
6875     { PREFIX_TABLE (PREFIX_0F3829) },
6876     { PREFIX_TABLE (PREFIX_0F382A) },
6877     { PREFIX_TABLE (PREFIX_0F382B) },
6878     { Bad_Opcode },
6879     { Bad_Opcode },
6880     { Bad_Opcode },
6881     { Bad_Opcode },
6882     /* 30 */
6883     { PREFIX_TABLE (PREFIX_0F3830) },
6884     { PREFIX_TABLE (PREFIX_0F3831) },
6885     { PREFIX_TABLE (PREFIX_0F3832) },
6886     { PREFIX_TABLE (PREFIX_0F3833) },
6887     { PREFIX_TABLE (PREFIX_0F3834) },
6888     { PREFIX_TABLE (PREFIX_0F3835) },
6889     { Bad_Opcode },
6890     { PREFIX_TABLE (PREFIX_0F3837) },
6891     /* 38 */
6892     { PREFIX_TABLE (PREFIX_0F3838) },
6893     { PREFIX_TABLE (PREFIX_0F3839) },
6894     { PREFIX_TABLE (PREFIX_0F383A) },
6895     { PREFIX_TABLE (PREFIX_0F383B) },
6896     { PREFIX_TABLE (PREFIX_0F383C) },
6897     { PREFIX_TABLE (PREFIX_0F383D) },
6898     { PREFIX_TABLE (PREFIX_0F383E) },
6899     { PREFIX_TABLE (PREFIX_0F383F) },
6900     /* 40 */
6901     { PREFIX_TABLE (PREFIX_0F3840) },
6902     { PREFIX_TABLE (PREFIX_0F3841) },
6903     { Bad_Opcode },
6904     { Bad_Opcode },
6905     { Bad_Opcode },
6906     { Bad_Opcode },
6907     { Bad_Opcode },
6908     { Bad_Opcode },
6909     /* 48 */
6910     { Bad_Opcode },
6911     { Bad_Opcode },
6912     { Bad_Opcode },
6913     { Bad_Opcode },
6914     { Bad_Opcode },
6915     { Bad_Opcode },
6916     { Bad_Opcode },
6917     { Bad_Opcode },
6918     /* 50 */
6919     { Bad_Opcode },
6920     { Bad_Opcode },
6921     { Bad_Opcode },
6922     { Bad_Opcode },
6923     { Bad_Opcode },
6924     { Bad_Opcode },
6925     { Bad_Opcode },
6926     { Bad_Opcode },
6927     /* 58 */
6928     { Bad_Opcode },
6929     { Bad_Opcode },
6930     { Bad_Opcode },
6931     { Bad_Opcode },
6932     { Bad_Opcode },
6933     { Bad_Opcode },
6934     { Bad_Opcode },
6935     { Bad_Opcode },
6936     /* 60 */
6937     { Bad_Opcode },
6938     { Bad_Opcode },
6939     { Bad_Opcode },
6940     { Bad_Opcode },
6941     { Bad_Opcode },
6942     { Bad_Opcode },
6943     { Bad_Opcode },
6944     { Bad_Opcode },
6945     /* 68 */
6946     { Bad_Opcode },
6947     { Bad_Opcode },
6948     { Bad_Opcode },
6949     { Bad_Opcode },
6950     { Bad_Opcode },
6951     { Bad_Opcode },
6952     { Bad_Opcode },
6953     { Bad_Opcode },
6954     /* 70 */
6955     { Bad_Opcode },
6956     { Bad_Opcode },
6957     { Bad_Opcode },
6958     { Bad_Opcode },
6959     { Bad_Opcode },
6960     { Bad_Opcode },
6961     { Bad_Opcode },
6962     { Bad_Opcode },
6963     /* 78 */
6964     { Bad_Opcode },
6965     { Bad_Opcode },
6966     { Bad_Opcode },
6967     { Bad_Opcode },
6968     { Bad_Opcode },
6969     { Bad_Opcode },
6970     { Bad_Opcode },
6971     { Bad_Opcode },
6972     /* 80 */
6973     { PREFIX_TABLE (PREFIX_0F3880) },
6974     { PREFIX_TABLE (PREFIX_0F3881) },
6975     { PREFIX_TABLE (PREFIX_0F3882) },
6976     { Bad_Opcode },
6977     { Bad_Opcode },
6978     { Bad_Opcode },
6979     { Bad_Opcode },
6980     { Bad_Opcode },
6981     /* 88 */
6982     { Bad_Opcode },
6983     { Bad_Opcode },
6984     { Bad_Opcode },
6985     { Bad_Opcode },
6986     { Bad_Opcode },
6987     { Bad_Opcode },
6988     { Bad_Opcode },
6989     { Bad_Opcode },
6990     /* 90 */
6991     { Bad_Opcode },
6992     { Bad_Opcode },
6993     { Bad_Opcode },
6994     { Bad_Opcode },
6995     { Bad_Opcode },
6996     { Bad_Opcode },
6997     { Bad_Opcode },
6998     { Bad_Opcode },
6999     /* 98 */
7000     { Bad_Opcode },
7001     { Bad_Opcode },
7002     { Bad_Opcode },
7003     { Bad_Opcode },
7004     { Bad_Opcode },
7005     { Bad_Opcode },
7006     { Bad_Opcode },
7007     { Bad_Opcode },
7008     /* a0 */
7009     { Bad_Opcode },
7010     { Bad_Opcode },
7011     { Bad_Opcode },
7012     { Bad_Opcode },
7013     { Bad_Opcode },
7014     { Bad_Opcode },
7015     { Bad_Opcode },
7016     { Bad_Opcode },
7017     /* a8 */
7018     { Bad_Opcode },
7019     { Bad_Opcode },
7020     { Bad_Opcode },
7021     { Bad_Opcode },
7022     { Bad_Opcode },
7023     { Bad_Opcode },
7024     { Bad_Opcode },
7025     { Bad_Opcode },
7026     /* b0 */
7027     { Bad_Opcode },
7028     { Bad_Opcode },
7029     { Bad_Opcode },
7030     { Bad_Opcode },
7031     { Bad_Opcode },
7032     { Bad_Opcode },
7033     { Bad_Opcode },
7034     { Bad_Opcode },
7035     /* b8 */
7036     { Bad_Opcode },
7037     { Bad_Opcode },
7038     { Bad_Opcode },
7039     { Bad_Opcode },
7040     { Bad_Opcode },
7041     { Bad_Opcode },
7042     { Bad_Opcode },
7043     { Bad_Opcode },
7044     /* c0 */
7045     { Bad_Opcode },
7046     { Bad_Opcode },
7047     { Bad_Opcode },
7048     { Bad_Opcode },
7049     { Bad_Opcode },
7050     { Bad_Opcode },
7051     { Bad_Opcode },
7052     { Bad_Opcode },
7053     /* c8 */
7054     { PREFIX_TABLE (PREFIX_0F38C8) },
7055     { PREFIX_TABLE (PREFIX_0F38C9) },
7056     { PREFIX_TABLE (PREFIX_0F38CA) },
7057     { PREFIX_TABLE (PREFIX_0F38CB) },
7058     { PREFIX_TABLE (PREFIX_0F38CC) },
7059     { PREFIX_TABLE (PREFIX_0F38CD) },
7060     { Bad_Opcode },
7061     { PREFIX_TABLE (PREFIX_0F38CF) },
7062     /* d0 */
7063     { Bad_Opcode },
7064     { Bad_Opcode },
7065     { Bad_Opcode },
7066     { Bad_Opcode },
7067     { Bad_Opcode },
7068     { Bad_Opcode },
7069     { Bad_Opcode },
7070     { Bad_Opcode },
7071     /* d8 */
7072     { Bad_Opcode },
7073     { Bad_Opcode },
7074     { Bad_Opcode },
7075     { PREFIX_TABLE (PREFIX_0F38DB) },
7076     { PREFIX_TABLE (PREFIX_0F38DC) },
7077     { PREFIX_TABLE (PREFIX_0F38DD) },
7078     { PREFIX_TABLE (PREFIX_0F38DE) },
7079     { PREFIX_TABLE (PREFIX_0F38DF) },
7080     /* e0 */
7081     { Bad_Opcode },
7082     { Bad_Opcode },
7083     { Bad_Opcode },
7084     { Bad_Opcode },
7085     { Bad_Opcode },
7086     { Bad_Opcode },
7087     { Bad_Opcode },
7088     { Bad_Opcode },
7089     /* e8 */
7090     { Bad_Opcode },
7091     { Bad_Opcode },
7092     { Bad_Opcode },
7093     { Bad_Opcode },
7094     { Bad_Opcode },
7095     { Bad_Opcode },
7096     { Bad_Opcode },
7097     { Bad_Opcode },
7098     /* f0 */
7099     { PREFIX_TABLE (PREFIX_0F38F0) },
7100     { PREFIX_TABLE (PREFIX_0F38F1) },
7101     { Bad_Opcode },
7102     { Bad_Opcode },
7103     { Bad_Opcode },
7104     { PREFIX_TABLE (PREFIX_0F38F5) },
7105     { PREFIX_TABLE (PREFIX_0F38F6) },
7106     { Bad_Opcode },
7107     /* f8 */
7108     { PREFIX_TABLE (PREFIX_0F38F8) },
7109     { PREFIX_TABLE (PREFIX_0F38F9) },
7110     { Bad_Opcode },
7111     { Bad_Opcode },
7112     { Bad_Opcode },
7113     { Bad_Opcode },
7114     { Bad_Opcode },
7115     { Bad_Opcode },
7116   },
7117   /* THREE_BYTE_0F3A */
7118   {
7119     /* 00 */
7120     { Bad_Opcode },
7121     { Bad_Opcode },
7122     { Bad_Opcode },
7123     { Bad_Opcode },
7124     { Bad_Opcode },
7125     { Bad_Opcode },
7126     { Bad_Opcode },
7127     { Bad_Opcode },
7128     /* 08 */
7129     { PREFIX_TABLE (PREFIX_0F3A08) },
7130     { PREFIX_TABLE (PREFIX_0F3A09) },
7131     { PREFIX_TABLE (PREFIX_0F3A0A) },
7132     { PREFIX_TABLE (PREFIX_0F3A0B) },
7133     { PREFIX_TABLE (PREFIX_0F3A0C) },
7134     { PREFIX_TABLE (PREFIX_0F3A0D) },
7135     { PREFIX_TABLE (PREFIX_0F3A0E) },
7136     { "palignr",        { MX, EM, Ib }, PREFIX_OPCODE },
7137     /* 10 */
7138     { Bad_Opcode },
7139     { Bad_Opcode },
7140     { Bad_Opcode },
7141     { Bad_Opcode },
7142     { PREFIX_TABLE (PREFIX_0F3A14) },
7143     { PREFIX_TABLE (PREFIX_0F3A15) },
7144     { PREFIX_TABLE (PREFIX_0F3A16) },
7145     { PREFIX_TABLE (PREFIX_0F3A17) },
7146     /* 18 */
7147     { Bad_Opcode },
7148     { Bad_Opcode },
7149     { Bad_Opcode },
7150     { Bad_Opcode },
7151     { Bad_Opcode },
7152     { Bad_Opcode },
7153     { Bad_Opcode },
7154     { Bad_Opcode },
7155     /* 20 */
7156     { PREFIX_TABLE (PREFIX_0F3A20) },
7157     { PREFIX_TABLE (PREFIX_0F3A21) },
7158     { PREFIX_TABLE (PREFIX_0F3A22) },
7159     { Bad_Opcode },
7160     { Bad_Opcode },
7161     { Bad_Opcode },
7162     { Bad_Opcode },
7163     { Bad_Opcode },
7164     /* 28 */
7165     { Bad_Opcode },
7166     { Bad_Opcode },
7167     { Bad_Opcode },
7168     { Bad_Opcode },
7169     { Bad_Opcode },
7170     { Bad_Opcode },
7171     { Bad_Opcode },
7172     { Bad_Opcode },
7173     /* 30 */
7174     { Bad_Opcode },
7175     { Bad_Opcode },
7176     { Bad_Opcode },
7177     { Bad_Opcode },
7178     { Bad_Opcode },
7179     { Bad_Opcode },
7180     { Bad_Opcode },
7181     { Bad_Opcode },
7182     /* 38 */
7183     { Bad_Opcode },
7184     { Bad_Opcode },
7185     { Bad_Opcode },
7186     { Bad_Opcode },
7187     { Bad_Opcode },
7188     { Bad_Opcode },
7189     { Bad_Opcode },
7190     { Bad_Opcode },
7191     /* 40 */
7192     { PREFIX_TABLE (PREFIX_0F3A40) },
7193     { PREFIX_TABLE (PREFIX_0F3A41) },
7194     { PREFIX_TABLE (PREFIX_0F3A42) },
7195     { Bad_Opcode },
7196     { PREFIX_TABLE (PREFIX_0F3A44) },
7197     { Bad_Opcode },
7198     { Bad_Opcode },
7199     { Bad_Opcode },
7200     /* 48 */
7201     { Bad_Opcode },
7202     { Bad_Opcode },
7203     { Bad_Opcode },
7204     { Bad_Opcode },
7205     { Bad_Opcode },
7206     { Bad_Opcode },
7207     { Bad_Opcode },
7208     { Bad_Opcode },
7209     /* 50 */
7210     { Bad_Opcode },
7211     { Bad_Opcode },
7212     { Bad_Opcode },
7213     { Bad_Opcode },
7214     { Bad_Opcode },
7215     { Bad_Opcode },
7216     { Bad_Opcode },
7217     { Bad_Opcode },
7218     /* 58 */
7219     { Bad_Opcode },
7220     { Bad_Opcode },
7221     { Bad_Opcode },
7222     { Bad_Opcode },
7223     { Bad_Opcode },
7224     { Bad_Opcode },
7225     { Bad_Opcode },
7226     { Bad_Opcode },
7227     /* 60 */
7228     { PREFIX_TABLE (PREFIX_0F3A60) },
7229     { PREFIX_TABLE (PREFIX_0F3A61) },
7230     { PREFIX_TABLE (PREFIX_0F3A62) },
7231     { PREFIX_TABLE (PREFIX_0F3A63) },
7232     { Bad_Opcode },
7233     { Bad_Opcode },
7234     { Bad_Opcode },
7235     { Bad_Opcode },
7236     /* 68 */
7237     { Bad_Opcode },
7238     { Bad_Opcode },
7239     { Bad_Opcode },
7240     { Bad_Opcode },
7241     { Bad_Opcode },
7242     { Bad_Opcode },
7243     { Bad_Opcode },
7244     { Bad_Opcode },
7245     /* 70 */
7246     { Bad_Opcode },
7247     { Bad_Opcode },
7248     { Bad_Opcode },
7249     { Bad_Opcode },
7250     { Bad_Opcode },
7251     { Bad_Opcode },
7252     { Bad_Opcode },
7253     { Bad_Opcode },
7254     /* 78 */
7255     { Bad_Opcode },
7256     { Bad_Opcode },
7257     { Bad_Opcode },
7258     { Bad_Opcode },
7259     { Bad_Opcode },
7260     { Bad_Opcode },
7261     { Bad_Opcode },
7262     { Bad_Opcode },
7263     /* 80 */
7264     { Bad_Opcode },
7265     { Bad_Opcode },
7266     { Bad_Opcode },
7267     { Bad_Opcode },
7268     { Bad_Opcode },
7269     { Bad_Opcode },
7270     { Bad_Opcode },
7271     { Bad_Opcode },
7272     /* 88 */
7273     { Bad_Opcode },
7274     { Bad_Opcode },
7275     { Bad_Opcode },
7276     { Bad_Opcode },
7277     { Bad_Opcode },
7278     { Bad_Opcode },
7279     { Bad_Opcode },
7280     { Bad_Opcode },
7281     /* 90 */
7282     { Bad_Opcode },
7283     { Bad_Opcode },
7284     { Bad_Opcode },
7285     { Bad_Opcode },
7286     { Bad_Opcode },
7287     { Bad_Opcode },
7288     { Bad_Opcode },
7289     { Bad_Opcode },
7290     /* 98 */
7291     { Bad_Opcode },
7292     { Bad_Opcode },
7293     { Bad_Opcode },
7294     { Bad_Opcode },
7295     { Bad_Opcode },
7296     { Bad_Opcode },
7297     { Bad_Opcode },
7298     { Bad_Opcode },
7299     /* a0 */
7300     { Bad_Opcode },
7301     { Bad_Opcode },
7302     { Bad_Opcode },
7303     { Bad_Opcode },
7304     { Bad_Opcode },
7305     { Bad_Opcode },
7306     { Bad_Opcode },
7307     { Bad_Opcode },
7308     /* a8 */
7309     { Bad_Opcode },
7310     { Bad_Opcode },
7311     { Bad_Opcode },
7312     { Bad_Opcode },
7313     { Bad_Opcode },
7314     { Bad_Opcode },
7315     { Bad_Opcode },
7316     { Bad_Opcode },
7317     /* b0 */
7318     { Bad_Opcode },
7319     { Bad_Opcode },
7320     { Bad_Opcode },
7321     { Bad_Opcode },
7322     { Bad_Opcode },
7323     { Bad_Opcode },
7324     { Bad_Opcode },
7325     { Bad_Opcode },
7326     /* b8 */
7327     { Bad_Opcode },
7328     { Bad_Opcode },
7329     { Bad_Opcode },
7330     { Bad_Opcode },
7331     { Bad_Opcode },
7332     { Bad_Opcode },
7333     { Bad_Opcode },
7334     { Bad_Opcode },
7335     /* c0 */
7336     { Bad_Opcode },
7337     { Bad_Opcode },
7338     { Bad_Opcode },
7339     { Bad_Opcode },
7340     { Bad_Opcode },
7341     { Bad_Opcode },
7342     { Bad_Opcode },
7343     { Bad_Opcode },
7344     /* c8 */
7345     { Bad_Opcode },
7346     { Bad_Opcode },
7347     { Bad_Opcode },
7348     { Bad_Opcode },
7349     { PREFIX_TABLE (PREFIX_0F3ACC) },
7350     { Bad_Opcode },
7351     { PREFIX_TABLE (PREFIX_0F3ACE) },
7352     { PREFIX_TABLE (PREFIX_0F3ACF) },
7353     /* d0 */
7354     { Bad_Opcode },
7355     { Bad_Opcode },
7356     { Bad_Opcode },
7357     { Bad_Opcode },
7358     { Bad_Opcode },
7359     { Bad_Opcode },
7360     { Bad_Opcode },
7361     { Bad_Opcode },
7362     /* d8 */
7363     { Bad_Opcode },
7364     { Bad_Opcode },
7365     { Bad_Opcode },
7366     { Bad_Opcode },
7367     { Bad_Opcode },
7368     { Bad_Opcode },
7369     { Bad_Opcode },
7370     { PREFIX_TABLE (PREFIX_0F3ADF) },
7371     /* e0 */
7372     { Bad_Opcode },
7373     { Bad_Opcode },
7374     { Bad_Opcode },
7375     { Bad_Opcode },
7376     { Bad_Opcode },
7377     { Bad_Opcode },
7378     { Bad_Opcode },
7379     { Bad_Opcode },
7380     /* e8 */
7381     { Bad_Opcode },
7382     { Bad_Opcode },
7383     { Bad_Opcode },
7384     { Bad_Opcode },
7385     { Bad_Opcode },
7386     { Bad_Opcode },
7387     { Bad_Opcode },
7388     { Bad_Opcode },
7389     /* f0 */
7390     { Bad_Opcode },
7391     { Bad_Opcode },
7392     { Bad_Opcode },
7393     { Bad_Opcode },
7394     { Bad_Opcode },
7395     { Bad_Opcode },
7396     { Bad_Opcode },
7397     { Bad_Opcode },
7398     /* f8 */
7399     { Bad_Opcode },
7400     { Bad_Opcode },
7401     { Bad_Opcode },
7402     { Bad_Opcode },
7403     { Bad_Opcode },
7404     { Bad_Opcode },
7405     { Bad_Opcode },
7406     { Bad_Opcode },
7407   },
7408 };
7409
7410 static const struct dis386 xop_table[][256] = {
7411   /* XOP_08 */
7412   {
7413     /* 00 */
7414     { Bad_Opcode },
7415     { Bad_Opcode },
7416     { Bad_Opcode },
7417     { Bad_Opcode },
7418     { Bad_Opcode },
7419     { Bad_Opcode },
7420     { Bad_Opcode },
7421     { Bad_Opcode },
7422     /* 08 */
7423     { Bad_Opcode },
7424     { Bad_Opcode },
7425     { Bad_Opcode },
7426     { Bad_Opcode },
7427     { Bad_Opcode },
7428     { Bad_Opcode },
7429     { Bad_Opcode },
7430     { Bad_Opcode },
7431     /* 10 */
7432     { Bad_Opcode },
7433     { Bad_Opcode },
7434     { Bad_Opcode },
7435     { Bad_Opcode },
7436     { Bad_Opcode },
7437     { Bad_Opcode },
7438     { Bad_Opcode },
7439     { Bad_Opcode },
7440     /* 18 */
7441     { Bad_Opcode },
7442     { Bad_Opcode },
7443     { Bad_Opcode },
7444     { Bad_Opcode },
7445     { Bad_Opcode },
7446     { Bad_Opcode },
7447     { Bad_Opcode },
7448     { Bad_Opcode },
7449     /* 20 */
7450     { Bad_Opcode },
7451     { Bad_Opcode },
7452     { Bad_Opcode },
7453     { Bad_Opcode },
7454     { Bad_Opcode },
7455     { Bad_Opcode },
7456     { Bad_Opcode },
7457     { Bad_Opcode },
7458     /* 28 */
7459     { Bad_Opcode },
7460     { Bad_Opcode },
7461     { Bad_Opcode },
7462     { Bad_Opcode },
7463     { Bad_Opcode },
7464     { Bad_Opcode },
7465     { Bad_Opcode },
7466     { Bad_Opcode },
7467     /* 30 */
7468     { Bad_Opcode },
7469     { Bad_Opcode },
7470     { Bad_Opcode },
7471     { Bad_Opcode },
7472     { Bad_Opcode },
7473     { Bad_Opcode },
7474     { Bad_Opcode },
7475     { Bad_Opcode },
7476     /* 38 */
7477     { Bad_Opcode },
7478     { Bad_Opcode },
7479     { Bad_Opcode },
7480     { Bad_Opcode },
7481     { Bad_Opcode },
7482     { Bad_Opcode },
7483     { Bad_Opcode },
7484     { Bad_Opcode },
7485     /* 40 */
7486     { Bad_Opcode },
7487     { Bad_Opcode },
7488     { Bad_Opcode },
7489     { Bad_Opcode },
7490     { Bad_Opcode },
7491     { Bad_Opcode },
7492     { Bad_Opcode },
7493     { Bad_Opcode },
7494     /* 48 */
7495     { Bad_Opcode },
7496     { Bad_Opcode },
7497     { Bad_Opcode },
7498     { Bad_Opcode },
7499     { Bad_Opcode },
7500     { Bad_Opcode },
7501     { Bad_Opcode },
7502     { Bad_Opcode },
7503     /* 50 */
7504     { Bad_Opcode },
7505     { Bad_Opcode },
7506     { Bad_Opcode },
7507     { Bad_Opcode },
7508     { Bad_Opcode },
7509     { Bad_Opcode },
7510     { Bad_Opcode },
7511     { Bad_Opcode },
7512     /* 58 */
7513     { Bad_Opcode },
7514     { Bad_Opcode },
7515     { Bad_Opcode },
7516     { Bad_Opcode },
7517     { Bad_Opcode },
7518     { Bad_Opcode },
7519     { Bad_Opcode },
7520     { Bad_Opcode },
7521     /* 60 */
7522     { Bad_Opcode },
7523     { Bad_Opcode },
7524     { Bad_Opcode },
7525     { Bad_Opcode },
7526     { Bad_Opcode },
7527     { Bad_Opcode },
7528     { Bad_Opcode },
7529     { Bad_Opcode },
7530     /* 68 */
7531     { Bad_Opcode },
7532     { Bad_Opcode },
7533     { Bad_Opcode },
7534     { Bad_Opcode },
7535     { Bad_Opcode },
7536     { Bad_Opcode },
7537     { Bad_Opcode },
7538     { Bad_Opcode },
7539     /* 70 */
7540     { Bad_Opcode },
7541     { Bad_Opcode },
7542     { Bad_Opcode },
7543     { Bad_Opcode },
7544     { Bad_Opcode },
7545     { Bad_Opcode },
7546     { Bad_Opcode },
7547     { Bad_Opcode },
7548     /* 78 */
7549     { Bad_Opcode },
7550     { Bad_Opcode },
7551     { Bad_Opcode },
7552     { Bad_Opcode },
7553     { Bad_Opcode },
7554     { Bad_Opcode },
7555     { Bad_Opcode },
7556     { Bad_Opcode },
7557     /* 80 */
7558     { Bad_Opcode },
7559     { Bad_Opcode },
7560     { Bad_Opcode },
7561     { Bad_Opcode },
7562     { Bad_Opcode },
7563     { "vpmacssww",      { XM, Vex, EXx, XMVexI4 }, 0 },
7564     { "vpmacsswd",      { XM, Vex, EXx, XMVexI4 }, 0 },
7565     { "vpmacssdql",     { XM, Vex, EXx, XMVexI4 }, 0 },
7566     /* 88 */
7567     { Bad_Opcode },
7568     { Bad_Opcode },
7569     { Bad_Opcode },
7570     { Bad_Opcode },
7571     { Bad_Opcode },
7572     { Bad_Opcode },
7573     { "vpmacssdd",      { XM, Vex, EXx, XMVexI4 }, 0 },
7574     { "vpmacssdqh",     { XM, Vex, EXx, XMVexI4 }, 0 },
7575     /* 90 */
7576     { Bad_Opcode },
7577     { Bad_Opcode },
7578     { Bad_Opcode },
7579     { Bad_Opcode },
7580     { Bad_Opcode },
7581     { "vpmacsww",       { XM, Vex, EXx, XMVexI4 }, 0 },
7582     { "vpmacswd",       { XM, Vex, EXx, XMVexI4 }, 0 },
7583     { "vpmacsdql",      { XM, Vex, EXx, XMVexI4 }, 0 },
7584     /* 98 */
7585     { Bad_Opcode },
7586     { Bad_Opcode },
7587     { Bad_Opcode },
7588     { Bad_Opcode },
7589     { Bad_Opcode },
7590     { Bad_Opcode },
7591     { "vpmacsdd",       { XM, Vex, EXx, XMVexI4 }, 0 },
7592     { "vpmacsdqh",      { XM, Vex, EXx, XMVexI4 }, 0 },
7593     /* a0 */
7594     { Bad_Opcode },
7595     { Bad_Opcode },
7596     { "vpcmov",         { XM, Vex, EXx, XMVexI4 }, 0 },
7597     { "vpperm",         { XM, Vex, EXx, XMVexI4 }, 0 },
7598     { Bad_Opcode },
7599     { Bad_Opcode },
7600     { "vpmadcsswd",     { XM, Vex, EXx, XMVexI4 }, 0 },
7601     { Bad_Opcode },
7602     /* a8 */
7603     { Bad_Opcode },
7604     { Bad_Opcode },
7605     { Bad_Opcode },
7606     { Bad_Opcode },
7607     { Bad_Opcode },
7608     { Bad_Opcode },
7609     { Bad_Opcode },
7610     { Bad_Opcode },
7611     /* b0 */
7612     { Bad_Opcode },
7613     { Bad_Opcode },
7614     { Bad_Opcode },
7615     { Bad_Opcode },
7616     { Bad_Opcode },
7617     { Bad_Opcode },
7618     { "vpmadcswd",      { XM, Vex, EXx, XMVexI4 }, 0 },
7619     { Bad_Opcode },
7620     /* b8 */
7621     { Bad_Opcode },
7622     { Bad_Opcode },
7623     { Bad_Opcode },
7624     { Bad_Opcode },
7625     { Bad_Opcode },
7626     { Bad_Opcode },
7627     { Bad_Opcode },
7628     { Bad_Opcode },
7629     /* c0 */
7630     { "vprotb",         { XM, EXx, Ib }, 0 },
7631     { "vprotw",         { XM, EXx, Ib }, 0 },
7632     { "vprotd",         { XM, EXx, Ib }, 0 },
7633     { "vprotq",         { XM, EXx, Ib }, 0 },
7634     { Bad_Opcode },
7635     { Bad_Opcode },
7636     { Bad_Opcode },
7637     { Bad_Opcode },
7638     /* c8 */
7639     { Bad_Opcode },
7640     { Bad_Opcode },
7641     { Bad_Opcode },
7642     { Bad_Opcode },
7643     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
7644     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
7645     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
7646     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
7647     /* d0 */
7648     { Bad_Opcode },
7649     { Bad_Opcode },
7650     { Bad_Opcode },
7651     { Bad_Opcode },
7652     { Bad_Opcode },
7653     { Bad_Opcode },
7654     { Bad_Opcode },
7655     { Bad_Opcode },
7656     /* d8 */
7657     { Bad_Opcode },
7658     { Bad_Opcode },
7659     { Bad_Opcode },
7660     { Bad_Opcode },
7661     { Bad_Opcode },
7662     { Bad_Opcode },
7663     { Bad_Opcode },
7664     { Bad_Opcode },
7665     /* e0 */
7666     { Bad_Opcode },
7667     { Bad_Opcode },
7668     { Bad_Opcode },
7669     { Bad_Opcode },
7670     { Bad_Opcode },
7671     { Bad_Opcode },
7672     { Bad_Opcode },
7673     { Bad_Opcode },
7674     /* e8 */
7675     { Bad_Opcode },
7676     { Bad_Opcode },
7677     { Bad_Opcode },
7678     { Bad_Opcode },
7679     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
7680     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
7681     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
7682     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
7683     /* f0 */
7684     { Bad_Opcode },
7685     { Bad_Opcode },
7686     { Bad_Opcode },
7687     { Bad_Opcode },
7688     { Bad_Opcode },
7689     { Bad_Opcode },
7690     { Bad_Opcode },
7691     { Bad_Opcode },
7692     /* f8 */
7693     { Bad_Opcode },
7694     { Bad_Opcode },
7695     { Bad_Opcode },
7696     { Bad_Opcode },
7697     { Bad_Opcode },
7698     { Bad_Opcode },
7699     { Bad_Opcode },
7700     { Bad_Opcode },
7701   },
7702   /* XOP_09 */
7703   {
7704     /* 00 */
7705     { Bad_Opcode },
7706     { REG_TABLE (REG_XOP_TBM_01) },
7707     { REG_TABLE (REG_XOP_TBM_02) },
7708     { Bad_Opcode },
7709     { Bad_Opcode },
7710     { Bad_Opcode },
7711     { Bad_Opcode },
7712     { Bad_Opcode },
7713     /* 08 */
7714     { Bad_Opcode },
7715     { Bad_Opcode },
7716     { Bad_Opcode },
7717     { Bad_Opcode },
7718     { Bad_Opcode },
7719     { Bad_Opcode },
7720     { Bad_Opcode },
7721     { Bad_Opcode },
7722     /* 10 */
7723     { Bad_Opcode },
7724     { Bad_Opcode },
7725     { REG_TABLE (REG_XOP_LWPCB) },
7726     { Bad_Opcode },
7727     { Bad_Opcode },
7728     { Bad_Opcode },
7729     { Bad_Opcode },
7730     { Bad_Opcode },
7731     /* 18 */
7732     { Bad_Opcode },
7733     { Bad_Opcode },
7734     { Bad_Opcode },
7735     { Bad_Opcode },
7736     { Bad_Opcode },
7737     { Bad_Opcode },
7738     { Bad_Opcode },
7739     { Bad_Opcode },
7740     /* 20 */
7741     { Bad_Opcode },
7742     { Bad_Opcode },
7743     { Bad_Opcode },
7744     { Bad_Opcode },
7745     { Bad_Opcode },
7746     { Bad_Opcode },
7747     { Bad_Opcode },
7748     { Bad_Opcode },
7749     /* 28 */
7750     { Bad_Opcode },
7751     { Bad_Opcode },
7752     { Bad_Opcode },
7753     { Bad_Opcode },
7754     { Bad_Opcode },
7755     { Bad_Opcode },
7756     { Bad_Opcode },
7757     { Bad_Opcode },
7758     /* 30 */
7759     { Bad_Opcode },
7760     { Bad_Opcode },
7761     { Bad_Opcode },
7762     { Bad_Opcode },
7763     { Bad_Opcode },
7764     { Bad_Opcode },
7765     { Bad_Opcode },
7766     { Bad_Opcode },
7767     /* 38 */
7768     { Bad_Opcode },
7769     { Bad_Opcode },
7770     { Bad_Opcode },
7771     { Bad_Opcode },
7772     { Bad_Opcode },
7773     { Bad_Opcode },
7774     { Bad_Opcode },
7775     { Bad_Opcode },
7776     /* 40 */
7777     { Bad_Opcode },
7778     { Bad_Opcode },
7779     { Bad_Opcode },
7780     { Bad_Opcode },
7781     { Bad_Opcode },
7782     { Bad_Opcode },
7783     { Bad_Opcode },
7784     { Bad_Opcode },
7785     /* 48 */
7786     { Bad_Opcode },
7787     { Bad_Opcode },
7788     { Bad_Opcode },
7789     { Bad_Opcode },
7790     { Bad_Opcode },
7791     { Bad_Opcode },
7792     { Bad_Opcode },
7793     { Bad_Opcode },
7794     /* 50 */
7795     { Bad_Opcode },
7796     { Bad_Opcode },
7797     { Bad_Opcode },
7798     { Bad_Opcode },
7799     { Bad_Opcode },
7800     { Bad_Opcode },
7801     { Bad_Opcode },
7802     { Bad_Opcode },
7803     /* 58 */
7804     { Bad_Opcode },
7805     { Bad_Opcode },
7806     { Bad_Opcode },
7807     { Bad_Opcode },
7808     { Bad_Opcode },
7809     { Bad_Opcode },
7810     { Bad_Opcode },
7811     { Bad_Opcode },
7812     /* 60 */
7813     { Bad_Opcode },
7814     { Bad_Opcode },
7815     { Bad_Opcode },
7816     { Bad_Opcode },
7817     { Bad_Opcode },
7818     { Bad_Opcode },
7819     { Bad_Opcode },
7820     { Bad_Opcode },
7821     /* 68 */
7822     { Bad_Opcode },
7823     { Bad_Opcode },
7824     { Bad_Opcode },
7825     { Bad_Opcode },
7826     { Bad_Opcode },
7827     { Bad_Opcode },
7828     { Bad_Opcode },
7829     { Bad_Opcode },
7830     /* 70 */
7831     { Bad_Opcode },
7832     { Bad_Opcode },
7833     { Bad_Opcode },
7834     { Bad_Opcode },
7835     { Bad_Opcode },
7836     { Bad_Opcode },
7837     { Bad_Opcode },
7838     { Bad_Opcode },
7839     /* 78 */
7840     { Bad_Opcode },
7841     { Bad_Opcode },
7842     { Bad_Opcode },
7843     { Bad_Opcode },
7844     { Bad_Opcode },
7845     { Bad_Opcode },
7846     { Bad_Opcode },
7847     { Bad_Opcode },
7848     /* 80 */
7849     { VEX_W_TABLE (VEX_W_0FXOP_09_80) },
7850     { VEX_W_TABLE (VEX_W_0FXOP_09_81) },
7851     { VEX_W_TABLE (VEX_W_0FXOP_09_82) },
7852     { VEX_W_TABLE (VEX_W_0FXOP_09_83) },
7853     { Bad_Opcode },
7854     { Bad_Opcode },
7855     { Bad_Opcode },
7856     { Bad_Opcode },
7857     /* 88 */
7858     { Bad_Opcode },
7859     { Bad_Opcode },
7860     { Bad_Opcode },
7861     { Bad_Opcode },
7862     { Bad_Opcode },
7863     { Bad_Opcode },
7864     { Bad_Opcode },
7865     { Bad_Opcode },
7866     /* 90 */
7867     { "vprotb",         { XM, EXx, VexW }, 0 },
7868     { "vprotw",         { XM, EXx, VexW }, 0 },
7869     { "vprotd",         { XM, EXx, VexW }, 0 },
7870     { "vprotq",         { XM, EXx, VexW }, 0 },
7871     { "vpshlb",         { XM, EXx, VexW }, 0 },
7872     { "vpshlw",         { XM, EXx, VexW }, 0 },
7873     { "vpshld",         { XM, EXx, VexW }, 0 },
7874     { "vpshlq",         { XM, EXx, VexW }, 0 },
7875     /* 98 */
7876     { "vpshab",         { XM, EXx, VexW }, 0 },
7877     { "vpshaw",         { XM, EXx, VexW }, 0 },
7878     { "vpshad",         { XM, EXx, VexW }, 0 },
7879     { "vpshaq",         { XM, EXx, VexW }, 0 },
7880     { Bad_Opcode },
7881     { Bad_Opcode },
7882     { Bad_Opcode },
7883     { Bad_Opcode },
7884     /* a0 */
7885     { Bad_Opcode },
7886     { Bad_Opcode },
7887     { Bad_Opcode },
7888     { Bad_Opcode },
7889     { Bad_Opcode },
7890     { Bad_Opcode },
7891     { Bad_Opcode },
7892     { Bad_Opcode },
7893     /* a8 */
7894     { Bad_Opcode },
7895     { Bad_Opcode },
7896     { Bad_Opcode },
7897     { Bad_Opcode },
7898     { Bad_Opcode },
7899     { Bad_Opcode },
7900     { Bad_Opcode },
7901     { Bad_Opcode },
7902     /* b0 */
7903     { Bad_Opcode },
7904     { Bad_Opcode },
7905     { Bad_Opcode },
7906     { Bad_Opcode },
7907     { Bad_Opcode },
7908     { Bad_Opcode },
7909     { Bad_Opcode },
7910     { Bad_Opcode },
7911     /* b8 */
7912     { Bad_Opcode },
7913     { Bad_Opcode },
7914     { Bad_Opcode },
7915     { Bad_Opcode },
7916     { Bad_Opcode },
7917     { Bad_Opcode },
7918     { Bad_Opcode },
7919     { Bad_Opcode },
7920     /* c0 */
7921     { Bad_Opcode },
7922     { "vphaddbw",       { XM, EXxmm }, 0 },
7923     { "vphaddbd",       { XM, EXxmm }, 0 },
7924     { "vphaddbq",       { XM, EXxmm }, 0 },
7925     { Bad_Opcode },
7926     { Bad_Opcode },
7927     { "vphaddwd",       { XM, EXxmm }, 0 },
7928     { "vphaddwq",       { XM, EXxmm }, 0 },
7929     /* c8 */
7930     { Bad_Opcode },
7931     { Bad_Opcode },
7932     { Bad_Opcode },
7933     { "vphadddq",       { XM, EXxmm }, 0 },
7934     { Bad_Opcode },
7935     { Bad_Opcode },
7936     { Bad_Opcode },
7937     { Bad_Opcode },
7938     /* d0 */
7939     { Bad_Opcode },
7940     { "vphaddubw",      { XM, EXxmm }, 0 },
7941     { "vphaddubd",      { XM, EXxmm }, 0 },
7942     { "vphaddubq",      { XM, EXxmm }, 0 },
7943     { Bad_Opcode },
7944     { Bad_Opcode },
7945     { "vphadduwd",      { XM, EXxmm }, 0 },
7946     { "vphadduwq",      { XM, EXxmm }, 0 },
7947     /* d8 */
7948     { Bad_Opcode },
7949     { Bad_Opcode },
7950     { Bad_Opcode },
7951     { "vphaddudq",      { XM, EXxmm }, 0 },
7952     { Bad_Opcode },
7953     { Bad_Opcode },
7954     { Bad_Opcode },
7955     { Bad_Opcode },
7956     /* e0 */
7957     { Bad_Opcode },
7958     { "vphsubbw",       { XM, EXxmm }, 0 },
7959     { "vphsubwd",       { XM, EXxmm }, 0 },
7960     { "vphsubdq",       { XM, EXxmm }, 0 },
7961     { Bad_Opcode },
7962     { Bad_Opcode },
7963     { Bad_Opcode },
7964     { Bad_Opcode },
7965     /* e8 */
7966     { Bad_Opcode },
7967     { Bad_Opcode },
7968     { Bad_Opcode },
7969     { Bad_Opcode },
7970     { Bad_Opcode },
7971     { Bad_Opcode },
7972     { Bad_Opcode },
7973     { Bad_Opcode },
7974     /* f0 */
7975     { Bad_Opcode },
7976     { Bad_Opcode },
7977     { Bad_Opcode },
7978     { Bad_Opcode },
7979     { Bad_Opcode },
7980     { Bad_Opcode },
7981     { Bad_Opcode },
7982     { Bad_Opcode },
7983     /* f8 */
7984     { Bad_Opcode },
7985     { Bad_Opcode },
7986     { Bad_Opcode },
7987     { Bad_Opcode },
7988     { Bad_Opcode },
7989     { Bad_Opcode },
7990     { Bad_Opcode },
7991     { Bad_Opcode },
7992   },
7993   /* XOP_0A */
7994   {
7995     /* 00 */
7996     { Bad_Opcode },
7997     { Bad_Opcode },
7998     { Bad_Opcode },
7999     { Bad_Opcode },
8000     { Bad_Opcode },
8001     { Bad_Opcode },
8002     { Bad_Opcode },
8003     { Bad_Opcode },
8004     /* 08 */
8005     { Bad_Opcode },
8006     { Bad_Opcode },
8007     { Bad_Opcode },
8008     { Bad_Opcode },
8009     { Bad_Opcode },
8010     { Bad_Opcode },
8011     { Bad_Opcode },
8012     { Bad_Opcode },
8013     /* 10 */
8014     { "bextrS", { Gdq, Edq, Id }, 0 },
8015     { Bad_Opcode },
8016     { REG_TABLE (REG_XOP_LWP) },
8017     { Bad_Opcode },
8018     { Bad_Opcode },
8019     { Bad_Opcode },
8020     { Bad_Opcode },
8021     { Bad_Opcode },
8022     /* 18 */
8023     { Bad_Opcode },
8024     { Bad_Opcode },
8025     { Bad_Opcode },
8026     { Bad_Opcode },
8027     { Bad_Opcode },
8028     { Bad_Opcode },
8029     { Bad_Opcode },
8030     { Bad_Opcode },
8031     /* 20 */
8032     { Bad_Opcode },
8033     { Bad_Opcode },
8034     { Bad_Opcode },
8035     { Bad_Opcode },
8036     { Bad_Opcode },
8037     { Bad_Opcode },
8038     { Bad_Opcode },
8039     { Bad_Opcode },
8040     /* 28 */
8041     { Bad_Opcode },
8042     { Bad_Opcode },
8043     { Bad_Opcode },
8044     { Bad_Opcode },
8045     { Bad_Opcode },
8046     { Bad_Opcode },
8047     { Bad_Opcode },
8048     { Bad_Opcode },
8049     /* 30 */
8050     { Bad_Opcode },
8051     { Bad_Opcode },
8052     { Bad_Opcode },
8053     { Bad_Opcode },
8054     { Bad_Opcode },
8055     { Bad_Opcode },
8056     { Bad_Opcode },
8057     { Bad_Opcode },
8058     /* 38 */
8059     { Bad_Opcode },
8060     { Bad_Opcode },
8061     { Bad_Opcode },
8062     { Bad_Opcode },
8063     { Bad_Opcode },
8064     { Bad_Opcode },
8065     { Bad_Opcode },
8066     { Bad_Opcode },
8067     /* 40 */
8068     { Bad_Opcode },
8069     { Bad_Opcode },
8070     { Bad_Opcode },
8071     { Bad_Opcode },
8072     { Bad_Opcode },
8073     { Bad_Opcode },
8074     { Bad_Opcode },
8075     { Bad_Opcode },
8076     /* 48 */
8077     { Bad_Opcode },
8078     { Bad_Opcode },
8079     { Bad_Opcode },
8080     { Bad_Opcode },
8081     { Bad_Opcode },
8082     { Bad_Opcode },
8083     { Bad_Opcode },
8084     { Bad_Opcode },
8085     /* 50 */
8086     { Bad_Opcode },
8087     { Bad_Opcode },
8088     { Bad_Opcode },
8089     { Bad_Opcode },
8090     { Bad_Opcode },
8091     { Bad_Opcode },
8092     { Bad_Opcode },
8093     { Bad_Opcode },
8094     /* 58 */
8095     { Bad_Opcode },
8096     { Bad_Opcode },
8097     { Bad_Opcode },
8098     { Bad_Opcode },
8099     { Bad_Opcode },
8100     { Bad_Opcode },
8101     { Bad_Opcode },
8102     { Bad_Opcode },
8103     /* 60 */
8104     { Bad_Opcode },
8105     { Bad_Opcode },
8106     { Bad_Opcode },
8107     { Bad_Opcode },
8108     { Bad_Opcode },
8109     { Bad_Opcode },
8110     { Bad_Opcode },
8111     { Bad_Opcode },
8112     /* 68 */
8113     { Bad_Opcode },
8114     { Bad_Opcode },
8115     { Bad_Opcode },
8116     { Bad_Opcode },
8117     { Bad_Opcode },
8118     { Bad_Opcode },
8119     { Bad_Opcode },
8120     { Bad_Opcode },
8121     /* 70 */
8122     { Bad_Opcode },
8123     { Bad_Opcode },
8124     { Bad_Opcode },
8125     { Bad_Opcode },
8126     { Bad_Opcode },
8127     { Bad_Opcode },
8128     { Bad_Opcode },
8129     { Bad_Opcode },
8130     /* 78 */
8131     { Bad_Opcode },
8132     { Bad_Opcode },
8133     { Bad_Opcode },
8134     { Bad_Opcode },
8135     { Bad_Opcode },
8136     { Bad_Opcode },
8137     { Bad_Opcode },
8138     { Bad_Opcode },
8139     /* 80 */
8140     { Bad_Opcode },
8141     { Bad_Opcode },
8142     { Bad_Opcode },
8143     { Bad_Opcode },
8144     { Bad_Opcode },
8145     { Bad_Opcode },
8146     { Bad_Opcode },
8147     { Bad_Opcode },
8148     /* 88 */
8149     { Bad_Opcode },
8150     { Bad_Opcode },
8151     { Bad_Opcode },
8152     { Bad_Opcode },
8153     { Bad_Opcode },
8154     { Bad_Opcode },
8155     { Bad_Opcode },
8156     { Bad_Opcode },
8157     /* 90 */
8158     { Bad_Opcode },
8159     { Bad_Opcode },
8160     { Bad_Opcode },
8161     { Bad_Opcode },
8162     { Bad_Opcode },
8163     { Bad_Opcode },
8164     { Bad_Opcode },
8165     { Bad_Opcode },
8166     /* 98 */
8167     { Bad_Opcode },
8168     { Bad_Opcode },
8169     { Bad_Opcode },
8170     { Bad_Opcode },
8171     { Bad_Opcode },
8172     { Bad_Opcode },
8173     { Bad_Opcode },
8174     { Bad_Opcode },
8175     /* a0 */
8176     { Bad_Opcode },
8177     { Bad_Opcode },
8178     { Bad_Opcode },
8179     { Bad_Opcode },
8180     { Bad_Opcode },
8181     { Bad_Opcode },
8182     { Bad_Opcode },
8183     { Bad_Opcode },
8184     /* a8 */
8185     { Bad_Opcode },
8186     { Bad_Opcode },
8187     { Bad_Opcode },
8188     { Bad_Opcode },
8189     { Bad_Opcode },
8190     { Bad_Opcode },
8191     { Bad_Opcode },
8192     { Bad_Opcode },
8193     /* b0 */
8194     { Bad_Opcode },
8195     { Bad_Opcode },
8196     { Bad_Opcode },
8197     { Bad_Opcode },
8198     { Bad_Opcode },
8199     { Bad_Opcode },
8200     { Bad_Opcode },
8201     { Bad_Opcode },
8202     /* b8 */
8203     { Bad_Opcode },
8204     { Bad_Opcode },
8205     { Bad_Opcode },
8206     { Bad_Opcode },
8207     { Bad_Opcode },
8208     { Bad_Opcode },
8209     { Bad_Opcode },
8210     { Bad_Opcode },
8211     /* c0 */
8212     { Bad_Opcode },
8213     { Bad_Opcode },
8214     { Bad_Opcode },
8215     { Bad_Opcode },
8216     { Bad_Opcode },
8217     { Bad_Opcode },
8218     { Bad_Opcode },
8219     { Bad_Opcode },
8220     /* c8 */
8221     { Bad_Opcode },
8222     { Bad_Opcode },
8223     { Bad_Opcode },
8224     { Bad_Opcode },
8225     { Bad_Opcode },
8226     { Bad_Opcode },
8227     { Bad_Opcode },
8228     { Bad_Opcode },
8229     /* d0 */
8230     { Bad_Opcode },
8231     { Bad_Opcode },
8232     { Bad_Opcode },
8233     { Bad_Opcode },
8234     { Bad_Opcode },
8235     { Bad_Opcode },
8236     { Bad_Opcode },
8237     { Bad_Opcode },
8238     /* d8 */
8239     { Bad_Opcode },
8240     { Bad_Opcode },
8241     { Bad_Opcode },
8242     { Bad_Opcode },
8243     { Bad_Opcode },
8244     { Bad_Opcode },
8245     { Bad_Opcode },
8246     { Bad_Opcode },
8247     /* e0 */
8248     { Bad_Opcode },
8249     { Bad_Opcode },
8250     { Bad_Opcode },
8251     { Bad_Opcode },
8252     { Bad_Opcode },
8253     { Bad_Opcode },
8254     { Bad_Opcode },
8255     { Bad_Opcode },
8256     /* e8 */
8257     { Bad_Opcode },
8258     { Bad_Opcode },
8259     { Bad_Opcode },
8260     { Bad_Opcode },
8261     { Bad_Opcode },
8262     { Bad_Opcode },
8263     { Bad_Opcode },
8264     { Bad_Opcode },
8265     /* f0 */
8266     { Bad_Opcode },
8267     { Bad_Opcode },
8268     { Bad_Opcode },
8269     { Bad_Opcode },
8270     { Bad_Opcode },
8271     { Bad_Opcode },
8272     { Bad_Opcode },
8273     { Bad_Opcode },
8274     /* f8 */
8275     { Bad_Opcode },
8276     { Bad_Opcode },
8277     { Bad_Opcode },
8278     { Bad_Opcode },
8279     { Bad_Opcode },
8280     { Bad_Opcode },
8281     { Bad_Opcode },
8282     { Bad_Opcode },
8283   },
8284 };
8285
8286 static const struct dis386 vex_table[][256] = {
8287   /* VEX_0F */
8288   {
8289     /* 00 */
8290     { Bad_Opcode },
8291     { Bad_Opcode },
8292     { Bad_Opcode },
8293     { Bad_Opcode },
8294     { Bad_Opcode },
8295     { Bad_Opcode },
8296     { Bad_Opcode },
8297     { Bad_Opcode },
8298     /* 08 */
8299     { Bad_Opcode },
8300     { Bad_Opcode },
8301     { Bad_Opcode },
8302     { Bad_Opcode },
8303     { Bad_Opcode },
8304     { Bad_Opcode },
8305     { Bad_Opcode },
8306     { Bad_Opcode },
8307     /* 10 */
8308     { PREFIX_TABLE (PREFIX_VEX_0F10) },
8309     { PREFIX_TABLE (PREFIX_VEX_0F11) },
8310     { PREFIX_TABLE (PREFIX_VEX_0F12) },
8311     { MOD_TABLE (MOD_VEX_0F13) },
8312     { "vunpcklpX",      { XM, Vex, EXx }, PREFIX_OPCODE },
8313     { "vunpckhpX",      { XM, Vex, EXx }, PREFIX_OPCODE },
8314     { PREFIX_TABLE (PREFIX_VEX_0F16) },
8315     { MOD_TABLE (MOD_VEX_0F17) },
8316     /* 18 */
8317     { Bad_Opcode },
8318     { Bad_Opcode },
8319     { Bad_Opcode },
8320     { Bad_Opcode },
8321     { Bad_Opcode },
8322     { Bad_Opcode },
8323     { Bad_Opcode },
8324     { Bad_Opcode },
8325     /* 20 */
8326     { Bad_Opcode },
8327     { Bad_Opcode },
8328     { Bad_Opcode },
8329     { Bad_Opcode },
8330     { Bad_Opcode },
8331     { Bad_Opcode },
8332     { Bad_Opcode },
8333     { Bad_Opcode },
8334     /* 28 */
8335     { "vmovapX",        { XM, EXx }, PREFIX_OPCODE },
8336     { "vmovapX",        { EXxS, XM }, PREFIX_OPCODE },
8337     { PREFIX_TABLE (PREFIX_VEX_0F2A) },
8338     { MOD_TABLE (MOD_VEX_0F2B) },
8339     { PREFIX_TABLE (PREFIX_VEX_0F2C) },
8340     { PREFIX_TABLE (PREFIX_VEX_0F2D) },
8341     { PREFIX_TABLE (PREFIX_VEX_0F2E) },
8342     { PREFIX_TABLE (PREFIX_VEX_0F2F) },
8343     /* 30 */
8344     { Bad_Opcode },
8345     { Bad_Opcode },
8346     { Bad_Opcode },
8347     { Bad_Opcode },
8348     { Bad_Opcode },
8349     { Bad_Opcode },
8350     { Bad_Opcode },
8351     { Bad_Opcode },
8352     /* 38 */
8353     { Bad_Opcode },
8354     { Bad_Opcode },
8355     { Bad_Opcode },
8356     { Bad_Opcode },
8357     { Bad_Opcode },
8358     { Bad_Opcode },
8359     { Bad_Opcode },
8360     { Bad_Opcode },
8361     /* 40 */
8362     { Bad_Opcode },
8363     { PREFIX_TABLE (PREFIX_VEX_0F41) },
8364     { PREFIX_TABLE (PREFIX_VEX_0F42) },
8365     { Bad_Opcode },
8366     { PREFIX_TABLE (PREFIX_VEX_0F44) },
8367     { PREFIX_TABLE (PREFIX_VEX_0F45) },
8368     { PREFIX_TABLE (PREFIX_VEX_0F46) },
8369     { PREFIX_TABLE (PREFIX_VEX_0F47) },
8370     /* 48 */
8371     { Bad_Opcode },
8372     { Bad_Opcode },
8373     { PREFIX_TABLE (PREFIX_VEX_0F4A) },
8374     { PREFIX_TABLE (PREFIX_VEX_0F4B) },
8375     { Bad_Opcode },
8376     { Bad_Opcode },
8377     { Bad_Opcode },
8378     { Bad_Opcode },
8379     /* 50 */
8380     { MOD_TABLE (MOD_VEX_0F50) },
8381     { PREFIX_TABLE (PREFIX_VEX_0F51) },
8382     { PREFIX_TABLE (PREFIX_VEX_0F52) },
8383     { PREFIX_TABLE (PREFIX_VEX_0F53) },
8384     { "vandpX",         { XM, Vex, EXx }, PREFIX_OPCODE },
8385     { "vandnpX",        { XM, Vex, EXx }, PREFIX_OPCODE },
8386     { "vorpX",          { XM, Vex, EXx }, PREFIX_OPCODE },
8387     { "vxorpX",         { XM, Vex, EXx }, PREFIX_OPCODE },
8388     /* 58 */
8389     { PREFIX_TABLE (PREFIX_VEX_0F58) },
8390     { PREFIX_TABLE (PREFIX_VEX_0F59) },
8391     { PREFIX_TABLE (PREFIX_VEX_0F5A) },
8392     { PREFIX_TABLE (PREFIX_VEX_0F5B) },
8393     { PREFIX_TABLE (PREFIX_VEX_0F5C) },
8394     { PREFIX_TABLE (PREFIX_VEX_0F5D) },
8395     { PREFIX_TABLE (PREFIX_VEX_0F5E) },
8396     { PREFIX_TABLE (PREFIX_VEX_0F5F) },
8397     /* 60 */
8398     { PREFIX_TABLE (PREFIX_VEX_0F60) },
8399     { PREFIX_TABLE (PREFIX_VEX_0F61) },
8400     { PREFIX_TABLE (PREFIX_VEX_0F62) },
8401     { PREFIX_TABLE (PREFIX_VEX_0F63) },
8402     { PREFIX_TABLE (PREFIX_VEX_0F64) },
8403     { PREFIX_TABLE (PREFIX_VEX_0F65) },
8404     { PREFIX_TABLE (PREFIX_VEX_0F66) },
8405     { PREFIX_TABLE (PREFIX_VEX_0F67) },
8406     /* 68 */
8407     { PREFIX_TABLE (PREFIX_VEX_0F68) },
8408     { PREFIX_TABLE (PREFIX_VEX_0F69) },
8409     { PREFIX_TABLE (PREFIX_VEX_0F6A) },
8410     { PREFIX_TABLE (PREFIX_VEX_0F6B) },
8411     { PREFIX_TABLE (PREFIX_VEX_0F6C) },
8412     { PREFIX_TABLE (PREFIX_VEX_0F6D) },
8413     { PREFIX_TABLE (PREFIX_VEX_0F6E) },
8414     { PREFIX_TABLE (PREFIX_VEX_0F6F) },
8415     /* 70 */
8416     { PREFIX_TABLE (PREFIX_VEX_0F70) },
8417     { REG_TABLE (REG_VEX_0F71) },
8418     { REG_TABLE (REG_VEX_0F72) },
8419     { REG_TABLE (REG_VEX_0F73) },
8420     { PREFIX_TABLE (PREFIX_VEX_0F74) },
8421     { PREFIX_TABLE (PREFIX_VEX_0F75) },
8422     { PREFIX_TABLE (PREFIX_VEX_0F76) },
8423     { PREFIX_TABLE (PREFIX_VEX_0F77) },
8424     /* 78 */
8425     { Bad_Opcode },
8426     { Bad_Opcode },
8427     { Bad_Opcode },
8428     { Bad_Opcode },
8429     { PREFIX_TABLE (PREFIX_VEX_0F7C) },
8430     { PREFIX_TABLE (PREFIX_VEX_0F7D) },
8431     { PREFIX_TABLE (PREFIX_VEX_0F7E) },
8432     { PREFIX_TABLE (PREFIX_VEX_0F7F) },
8433     /* 80 */
8434     { Bad_Opcode },
8435     { Bad_Opcode },
8436     { Bad_Opcode },
8437     { Bad_Opcode },
8438     { Bad_Opcode },
8439     { Bad_Opcode },
8440     { Bad_Opcode },
8441     { Bad_Opcode },
8442     /* 88 */
8443     { Bad_Opcode },
8444     { Bad_Opcode },
8445     { Bad_Opcode },
8446     { Bad_Opcode },
8447     { Bad_Opcode },
8448     { Bad_Opcode },
8449     { Bad_Opcode },
8450     { Bad_Opcode },
8451     /* 90 */
8452     { PREFIX_TABLE (PREFIX_VEX_0F90) },
8453     { PREFIX_TABLE (PREFIX_VEX_0F91) },
8454     { PREFIX_TABLE (PREFIX_VEX_0F92) },
8455     { PREFIX_TABLE (PREFIX_VEX_0F93) },
8456     { Bad_Opcode },
8457     { Bad_Opcode },
8458     { Bad_Opcode },
8459     { Bad_Opcode },
8460     /* 98 */
8461     { PREFIX_TABLE (PREFIX_VEX_0F98) },
8462     { PREFIX_TABLE (PREFIX_VEX_0F99) },
8463     { Bad_Opcode },
8464     { Bad_Opcode },
8465     { Bad_Opcode },
8466     { Bad_Opcode },
8467     { Bad_Opcode },
8468     { Bad_Opcode },
8469     /* a0 */
8470     { Bad_Opcode },
8471     { Bad_Opcode },
8472     { Bad_Opcode },
8473     { Bad_Opcode },
8474     { Bad_Opcode },
8475     { Bad_Opcode },
8476     { Bad_Opcode },
8477     { Bad_Opcode },
8478     /* a8 */
8479     { Bad_Opcode },
8480     { Bad_Opcode },
8481     { Bad_Opcode },
8482     { Bad_Opcode },
8483     { Bad_Opcode },
8484     { Bad_Opcode },
8485     { REG_TABLE (REG_VEX_0FAE) },
8486     { Bad_Opcode },
8487     /* b0 */
8488     { Bad_Opcode },
8489     { Bad_Opcode },
8490     { Bad_Opcode },
8491     { Bad_Opcode },
8492     { Bad_Opcode },
8493     { Bad_Opcode },
8494     { Bad_Opcode },
8495     { Bad_Opcode },
8496     /* b8 */
8497     { Bad_Opcode },
8498     { Bad_Opcode },
8499     { Bad_Opcode },
8500     { Bad_Opcode },
8501     { Bad_Opcode },
8502     { Bad_Opcode },
8503     { Bad_Opcode },
8504     { Bad_Opcode },
8505     /* c0 */
8506     { Bad_Opcode },
8507     { Bad_Opcode },
8508     { PREFIX_TABLE (PREFIX_VEX_0FC2) },
8509     { Bad_Opcode },
8510     { PREFIX_TABLE (PREFIX_VEX_0FC4) },
8511     { PREFIX_TABLE (PREFIX_VEX_0FC5) },
8512     { "vshufpX",        { XM, Vex, EXx, Ib }, PREFIX_OPCODE },
8513     { Bad_Opcode },
8514     /* c8 */
8515     { Bad_Opcode },
8516     { Bad_Opcode },
8517     { Bad_Opcode },
8518     { Bad_Opcode },
8519     { Bad_Opcode },
8520     { Bad_Opcode },
8521     { Bad_Opcode },
8522     { Bad_Opcode },
8523     /* d0 */
8524     { PREFIX_TABLE (PREFIX_VEX_0FD0) },
8525     { PREFIX_TABLE (PREFIX_VEX_0FD1) },
8526     { PREFIX_TABLE (PREFIX_VEX_0FD2) },
8527     { PREFIX_TABLE (PREFIX_VEX_0FD3) },
8528     { PREFIX_TABLE (PREFIX_VEX_0FD4) },
8529     { PREFIX_TABLE (PREFIX_VEX_0FD5) },
8530     { PREFIX_TABLE (PREFIX_VEX_0FD6) },
8531     { PREFIX_TABLE (PREFIX_VEX_0FD7) },
8532     /* d8 */
8533     { PREFIX_TABLE (PREFIX_VEX_0FD8) },
8534     { PREFIX_TABLE (PREFIX_VEX_0FD9) },
8535     { PREFIX_TABLE (PREFIX_VEX_0FDA) },
8536     { PREFIX_TABLE (PREFIX_VEX_0FDB) },
8537     { PREFIX_TABLE (PREFIX_VEX_0FDC) },
8538     { PREFIX_TABLE (PREFIX_VEX_0FDD) },
8539     { PREFIX_TABLE (PREFIX_VEX_0FDE) },
8540     { PREFIX_TABLE (PREFIX_VEX_0FDF) },
8541     /* e0 */
8542     { PREFIX_TABLE (PREFIX_VEX_0FE0) },
8543     { PREFIX_TABLE (PREFIX_VEX_0FE1) },
8544     { PREFIX_TABLE (PREFIX_VEX_0FE2) },
8545     { PREFIX_TABLE (PREFIX_VEX_0FE3) },
8546     { PREFIX_TABLE (PREFIX_VEX_0FE4) },
8547     { PREFIX_TABLE (PREFIX_VEX_0FE5) },
8548     { PREFIX_TABLE (PREFIX_VEX_0FE6) },
8549     { PREFIX_TABLE (PREFIX_VEX_0FE7) },
8550     /* e8 */
8551     { PREFIX_TABLE (PREFIX_VEX_0FE8) },
8552     { PREFIX_TABLE (PREFIX_VEX_0FE9) },
8553     { PREFIX_TABLE (PREFIX_VEX_0FEA) },
8554     { PREFIX_TABLE (PREFIX_VEX_0FEB) },
8555     { PREFIX_TABLE (PREFIX_VEX_0FEC) },
8556     { PREFIX_TABLE (PREFIX_VEX_0FED) },
8557     { PREFIX_TABLE (PREFIX_VEX_0FEE) },
8558     { PREFIX_TABLE (PREFIX_VEX_0FEF) },
8559     /* f0 */
8560     { PREFIX_TABLE (PREFIX_VEX_0FF0) },
8561     { PREFIX_TABLE (PREFIX_VEX_0FF1) },
8562     { PREFIX_TABLE (PREFIX_VEX_0FF2) },
8563     { PREFIX_TABLE (PREFIX_VEX_0FF3) },
8564     { PREFIX_TABLE (PREFIX_VEX_0FF4) },
8565     { PREFIX_TABLE (PREFIX_VEX_0FF5) },
8566     { PREFIX_TABLE (PREFIX_VEX_0FF6) },
8567     { PREFIX_TABLE (PREFIX_VEX_0FF7) },
8568     /* f8 */
8569     { PREFIX_TABLE (PREFIX_VEX_0FF8) },
8570     { PREFIX_TABLE (PREFIX_VEX_0FF9) },
8571     { PREFIX_TABLE (PREFIX_VEX_0FFA) },
8572     { PREFIX_TABLE (PREFIX_VEX_0FFB) },
8573     { PREFIX_TABLE (PREFIX_VEX_0FFC) },
8574     { PREFIX_TABLE (PREFIX_VEX_0FFD) },
8575     { PREFIX_TABLE (PREFIX_VEX_0FFE) },
8576     { Bad_Opcode },
8577   },
8578   /* VEX_0F38 */
8579   {
8580     /* 00 */
8581     { PREFIX_TABLE (PREFIX_VEX_0F3800) },
8582     { PREFIX_TABLE (PREFIX_VEX_0F3801) },
8583     { PREFIX_TABLE (PREFIX_VEX_0F3802) },
8584     { PREFIX_TABLE (PREFIX_VEX_0F3803) },
8585     { PREFIX_TABLE (PREFIX_VEX_0F3804) },
8586     { PREFIX_TABLE (PREFIX_VEX_0F3805) },
8587     { PREFIX_TABLE (PREFIX_VEX_0F3806) },
8588     { PREFIX_TABLE (PREFIX_VEX_0F3807) },
8589     /* 08 */
8590     { PREFIX_TABLE (PREFIX_VEX_0F3808) },
8591     { PREFIX_TABLE (PREFIX_VEX_0F3809) },
8592     { PREFIX_TABLE (PREFIX_VEX_0F380A) },
8593     { PREFIX_TABLE (PREFIX_VEX_0F380B) },
8594     { PREFIX_TABLE (PREFIX_VEX_0F380C) },
8595     { PREFIX_TABLE (PREFIX_VEX_0F380D) },
8596     { PREFIX_TABLE (PREFIX_VEX_0F380E) },
8597     { PREFIX_TABLE (PREFIX_VEX_0F380F) },
8598     /* 10 */
8599     { Bad_Opcode },
8600     { Bad_Opcode },
8601     { Bad_Opcode },
8602     { PREFIX_TABLE (PREFIX_VEX_0F3813) },
8603     { Bad_Opcode },
8604     { Bad_Opcode },
8605     { PREFIX_TABLE (PREFIX_VEX_0F3816) },
8606     { PREFIX_TABLE (PREFIX_VEX_0F3817) },
8607     /* 18 */
8608     { PREFIX_TABLE (PREFIX_VEX_0F3818) },
8609     { PREFIX_TABLE (PREFIX_VEX_0F3819) },
8610     { PREFIX_TABLE (PREFIX_VEX_0F381A) },
8611     { Bad_Opcode },
8612     { PREFIX_TABLE (PREFIX_VEX_0F381C) },
8613     { PREFIX_TABLE (PREFIX_VEX_0F381D) },
8614     { PREFIX_TABLE (PREFIX_VEX_0F381E) },
8615     { Bad_Opcode },
8616     /* 20 */
8617     { PREFIX_TABLE (PREFIX_VEX_0F3820) },
8618     { PREFIX_TABLE (PREFIX_VEX_0F3821) },
8619     { PREFIX_TABLE (PREFIX_VEX_0F3822) },
8620     { PREFIX_TABLE (PREFIX_VEX_0F3823) },
8621     { PREFIX_TABLE (PREFIX_VEX_0F3824) },
8622     { PREFIX_TABLE (PREFIX_VEX_0F3825) },
8623     { Bad_Opcode },
8624     { Bad_Opcode },
8625     /* 28 */
8626     { PREFIX_TABLE (PREFIX_VEX_0F3828) },
8627     { PREFIX_TABLE (PREFIX_VEX_0F3829) },
8628     { PREFIX_TABLE (PREFIX_VEX_0F382A) },
8629     { PREFIX_TABLE (PREFIX_VEX_0F382B) },
8630     { PREFIX_TABLE (PREFIX_VEX_0F382C) },
8631     { PREFIX_TABLE (PREFIX_VEX_0F382D) },
8632     { PREFIX_TABLE (PREFIX_VEX_0F382E) },
8633     { PREFIX_TABLE (PREFIX_VEX_0F382F) },
8634     /* 30 */
8635     { PREFIX_TABLE (PREFIX_VEX_0F3830) },
8636     { PREFIX_TABLE (PREFIX_VEX_0F3831) },
8637     { PREFIX_TABLE (PREFIX_VEX_0F3832) },
8638     { PREFIX_TABLE (PREFIX_VEX_0F3833) },
8639     { PREFIX_TABLE (PREFIX_VEX_0F3834) },
8640     { PREFIX_TABLE (PREFIX_VEX_0F3835) },
8641     { PREFIX_TABLE (PREFIX_VEX_0F3836) },
8642     { PREFIX_TABLE (PREFIX_VEX_0F3837) },
8643     /* 38 */
8644     { PREFIX_TABLE (PREFIX_VEX_0F3838) },
8645     { PREFIX_TABLE (PREFIX_VEX_0F3839) },
8646     { PREFIX_TABLE (PREFIX_VEX_0F383A) },
8647     { PREFIX_TABLE (PREFIX_VEX_0F383B) },
8648     { PREFIX_TABLE (PREFIX_VEX_0F383C) },
8649     { PREFIX_TABLE (PREFIX_VEX_0F383D) },
8650     { PREFIX_TABLE (PREFIX_VEX_0F383E) },
8651     { PREFIX_TABLE (PREFIX_VEX_0F383F) },
8652     /* 40 */
8653     { PREFIX_TABLE (PREFIX_VEX_0F3840) },
8654     { PREFIX_TABLE (PREFIX_VEX_0F3841) },
8655     { Bad_Opcode },
8656     { Bad_Opcode },
8657     { Bad_Opcode },
8658     { PREFIX_TABLE (PREFIX_VEX_0F3845) },
8659     { PREFIX_TABLE (PREFIX_VEX_0F3846) },
8660     { PREFIX_TABLE (PREFIX_VEX_0F3847) },
8661     /* 48 */
8662     { Bad_Opcode },
8663     { Bad_Opcode },
8664     { Bad_Opcode },
8665     { Bad_Opcode },
8666     { Bad_Opcode },
8667     { Bad_Opcode },
8668     { Bad_Opcode },
8669     { Bad_Opcode },
8670     /* 50 */
8671     { Bad_Opcode },
8672     { Bad_Opcode },
8673     { Bad_Opcode },
8674     { Bad_Opcode },
8675     { Bad_Opcode },
8676     { Bad_Opcode },
8677     { Bad_Opcode },
8678     { Bad_Opcode },
8679     /* 58 */
8680     { PREFIX_TABLE (PREFIX_VEX_0F3858) },
8681     { PREFIX_TABLE (PREFIX_VEX_0F3859) },
8682     { PREFIX_TABLE (PREFIX_VEX_0F385A) },
8683     { Bad_Opcode },
8684     { Bad_Opcode },
8685     { Bad_Opcode },
8686     { Bad_Opcode },
8687     { Bad_Opcode },
8688     /* 60 */
8689     { Bad_Opcode },
8690     { Bad_Opcode },
8691     { Bad_Opcode },
8692     { Bad_Opcode },
8693     { Bad_Opcode },
8694     { Bad_Opcode },
8695     { Bad_Opcode },
8696     { Bad_Opcode },
8697     /* 68 */
8698     { Bad_Opcode },
8699     { Bad_Opcode },
8700     { Bad_Opcode },
8701     { Bad_Opcode },
8702     { Bad_Opcode },
8703     { Bad_Opcode },
8704     { Bad_Opcode },
8705     { Bad_Opcode },
8706     /* 70 */
8707     { Bad_Opcode },
8708     { Bad_Opcode },
8709     { Bad_Opcode },
8710     { Bad_Opcode },
8711     { Bad_Opcode },
8712     { Bad_Opcode },
8713     { Bad_Opcode },
8714     { Bad_Opcode },
8715     /* 78 */
8716     { PREFIX_TABLE (PREFIX_VEX_0F3878) },
8717     { PREFIX_TABLE (PREFIX_VEX_0F3879) },
8718     { Bad_Opcode },
8719     { Bad_Opcode },
8720     { Bad_Opcode },
8721     { Bad_Opcode },
8722     { Bad_Opcode },
8723     { Bad_Opcode },
8724     /* 80 */
8725     { Bad_Opcode },
8726     { Bad_Opcode },
8727     { Bad_Opcode },
8728     { Bad_Opcode },
8729     { Bad_Opcode },
8730     { Bad_Opcode },
8731     { Bad_Opcode },
8732     { Bad_Opcode },
8733     /* 88 */
8734     { Bad_Opcode },
8735     { Bad_Opcode },
8736     { Bad_Opcode },
8737     { Bad_Opcode },
8738     { PREFIX_TABLE (PREFIX_VEX_0F388C) },
8739     { Bad_Opcode },
8740     { PREFIX_TABLE (PREFIX_VEX_0F388E) },
8741     { Bad_Opcode },
8742     /* 90 */
8743     { PREFIX_TABLE (PREFIX_VEX_0F3890) },
8744     { PREFIX_TABLE (PREFIX_VEX_0F3891) },
8745     { PREFIX_TABLE (PREFIX_VEX_0F3892) },
8746     { PREFIX_TABLE (PREFIX_VEX_0F3893) },
8747     { Bad_Opcode },
8748     { Bad_Opcode },
8749     { PREFIX_TABLE (PREFIX_VEX_0F3896) },
8750     { PREFIX_TABLE (PREFIX_VEX_0F3897) },
8751     /* 98 */
8752     { PREFIX_TABLE (PREFIX_VEX_0F3898) },
8753     { PREFIX_TABLE (PREFIX_VEX_0F3899) },
8754     { PREFIX_TABLE (PREFIX_VEX_0F389A) },
8755     { PREFIX_TABLE (PREFIX_VEX_0F389B) },
8756     { PREFIX_TABLE (PREFIX_VEX_0F389C) },
8757     { PREFIX_TABLE (PREFIX_VEX_0F389D) },
8758     { PREFIX_TABLE (PREFIX_VEX_0F389E) },
8759     { PREFIX_TABLE (PREFIX_VEX_0F389F) },
8760     /* a0 */
8761     { Bad_Opcode },
8762     { Bad_Opcode },
8763     { Bad_Opcode },
8764     { Bad_Opcode },
8765     { Bad_Opcode },
8766     { Bad_Opcode },
8767     { PREFIX_TABLE (PREFIX_VEX_0F38A6) },
8768     { PREFIX_TABLE (PREFIX_VEX_0F38A7) },
8769     /* a8 */
8770     { PREFIX_TABLE (PREFIX_VEX_0F38A8) },
8771     { PREFIX_TABLE (PREFIX_VEX_0F38A9) },
8772     { PREFIX_TABLE (PREFIX_VEX_0F38AA) },
8773     { PREFIX_TABLE (PREFIX_VEX_0F38AB) },
8774     { PREFIX_TABLE (PREFIX_VEX_0F38AC) },
8775     { PREFIX_TABLE (PREFIX_VEX_0F38AD) },
8776     { PREFIX_TABLE (PREFIX_VEX_0F38AE) },
8777     { PREFIX_TABLE (PREFIX_VEX_0F38AF) },
8778     /* b0 */
8779     { Bad_Opcode },
8780     { Bad_Opcode },
8781     { Bad_Opcode },
8782     { Bad_Opcode },
8783     { Bad_Opcode },
8784     { Bad_Opcode },
8785     { PREFIX_TABLE (PREFIX_VEX_0F38B6) },
8786     { PREFIX_TABLE (PREFIX_VEX_0F38B7) },
8787     /* b8 */
8788     { PREFIX_TABLE (PREFIX_VEX_0F38B8) },
8789     { PREFIX_TABLE (PREFIX_VEX_0F38B9) },
8790     { PREFIX_TABLE (PREFIX_VEX_0F38BA) },
8791     { PREFIX_TABLE (PREFIX_VEX_0F38BB) },
8792     { PREFIX_TABLE (PREFIX_VEX_0F38BC) },
8793     { PREFIX_TABLE (PREFIX_VEX_0F38BD) },
8794     { PREFIX_TABLE (PREFIX_VEX_0F38BE) },
8795     { PREFIX_TABLE (PREFIX_VEX_0F38BF) },
8796     /* c0 */
8797     { Bad_Opcode },
8798     { Bad_Opcode },
8799     { Bad_Opcode },
8800     { Bad_Opcode },
8801     { Bad_Opcode },
8802     { Bad_Opcode },
8803     { Bad_Opcode },
8804     { Bad_Opcode },
8805     /* c8 */
8806     { Bad_Opcode },
8807     { Bad_Opcode },
8808     { Bad_Opcode },
8809     { Bad_Opcode },
8810     { Bad_Opcode },
8811     { Bad_Opcode },
8812     { Bad_Opcode },
8813     { PREFIX_TABLE (PREFIX_VEX_0F38CF) },
8814     /* d0 */
8815     { Bad_Opcode },
8816     { Bad_Opcode },
8817     { Bad_Opcode },
8818     { Bad_Opcode },
8819     { Bad_Opcode },
8820     { Bad_Opcode },
8821     { Bad_Opcode },
8822     { Bad_Opcode },
8823     /* d8 */
8824     { Bad_Opcode },
8825     { Bad_Opcode },
8826     { Bad_Opcode },
8827     { PREFIX_TABLE (PREFIX_VEX_0F38DB) },
8828     { PREFIX_TABLE (PREFIX_VEX_0F38DC) },
8829     { PREFIX_TABLE (PREFIX_VEX_0F38DD) },
8830     { PREFIX_TABLE (PREFIX_VEX_0F38DE) },
8831     { PREFIX_TABLE (PREFIX_VEX_0F38DF) },
8832     /* e0 */
8833     { Bad_Opcode },
8834     { Bad_Opcode },
8835     { Bad_Opcode },
8836     { Bad_Opcode },
8837     { Bad_Opcode },
8838     { Bad_Opcode },
8839     { Bad_Opcode },
8840     { Bad_Opcode },
8841     /* e8 */
8842     { Bad_Opcode },
8843     { Bad_Opcode },
8844     { Bad_Opcode },
8845     { Bad_Opcode },
8846     { Bad_Opcode },
8847     { Bad_Opcode },
8848     { Bad_Opcode },
8849     { Bad_Opcode },
8850     /* f0 */
8851     { Bad_Opcode },
8852     { Bad_Opcode },
8853     { PREFIX_TABLE (PREFIX_VEX_0F38F2) },
8854     { REG_TABLE (REG_VEX_0F38F3) },
8855     { Bad_Opcode },
8856     { PREFIX_TABLE (PREFIX_VEX_0F38F5) },
8857     { PREFIX_TABLE (PREFIX_VEX_0F38F6) },
8858     { PREFIX_TABLE (PREFIX_VEX_0F38F7) },
8859     /* f8 */
8860     { Bad_Opcode },
8861     { Bad_Opcode },
8862     { Bad_Opcode },
8863     { Bad_Opcode },
8864     { Bad_Opcode },
8865     { Bad_Opcode },
8866     { Bad_Opcode },
8867     { Bad_Opcode },
8868   },
8869   /* VEX_0F3A */
8870   {
8871     /* 00 */
8872     { PREFIX_TABLE (PREFIX_VEX_0F3A00) },
8873     { PREFIX_TABLE (PREFIX_VEX_0F3A01) },
8874     { PREFIX_TABLE (PREFIX_VEX_0F3A02) },
8875     { Bad_Opcode },
8876     { PREFIX_TABLE (PREFIX_VEX_0F3A04) },
8877     { PREFIX_TABLE (PREFIX_VEX_0F3A05) },
8878     { PREFIX_TABLE (PREFIX_VEX_0F3A06) },
8879     { Bad_Opcode },
8880     /* 08 */
8881     { PREFIX_TABLE (PREFIX_VEX_0F3A08) },
8882     { PREFIX_TABLE (PREFIX_VEX_0F3A09) },
8883     { PREFIX_TABLE (PREFIX_VEX_0F3A0A) },
8884     { PREFIX_TABLE (PREFIX_VEX_0F3A0B) },
8885     { PREFIX_TABLE (PREFIX_VEX_0F3A0C) },
8886     { PREFIX_TABLE (PREFIX_VEX_0F3A0D) },
8887     { PREFIX_TABLE (PREFIX_VEX_0F3A0E) },
8888     { PREFIX_TABLE (PREFIX_VEX_0F3A0F) },
8889     /* 10 */
8890     { Bad_Opcode },
8891     { Bad_Opcode },
8892     { Bad_Opcode },
8893     { Bad_Opcode },
8894     { PREFIX_TABLE (PREFIX_VEX_0F3A14) },
8895     { PREFIX_TABLE (PREFIX_VEX_0F3A15) },
8896     { PREFIX_TABLE (PREFIX_VEX_0F3A16) },
8897     { PREFIX_TABLE (PREFIX_VEX_0F3A17) },
8898     /* 18 */
8899     { PREFIX_TABLE (PREFIX_VEX_0F3A18) },
8900     { PREFIX_TABLE (PREFIX_VEX_0F3A19) },
8901     { Bad_Opcode },
8902     { Bad_Opcode },
8903     { Bad_Opcode },
8904     { PREFIX_TABLE (PREFIX_VEX_0F3A1D) },
8905     { Bad_Opcode },
8906     { Bad_Opcode },
8907     /* 20 */
8908     { PREFIX_TABLE (PREFIX_VEX_0F3A20) },
8909     { PREFIX_TABLE (PREFIX_VEX_0F3A21) },
8910     { PREFIX_TABLE (PREFIX_VEX_0F3A22) },
8911     { Bad_Opcode },
8912     { Bad_Opcode },
8913     { Bad_Opcode },
8914     { Bad_Opcode },
8915     { Bad_Opcode },
8916     /* 28 */
8917     { Bad_Opcode },
8918     { Bad_Opcode },
8919     { Bad_Opcode },
8920     { Bad_Opcode },
8921     { Bad_Opcode },
8922     { Bad_Opcode },
8923     { Bad_Opcode },
8924     { Bad_Opcode },
8925     /* 30 */
8926     { PREFIX_TABLE (PREFIX_VEX_0F3A30) },
8927     { PREFIX_TABLE (PREFIX_VEX_0F3A31) },
8928     { PREFIX_TABLE (PREFIX_VEX_0F3A32) },
8929     { PREFIX_TABLE (PREFIX_VEX_0F3A33) },
8930     { Bad_Opcode },
8931     { Bad_Opcode },
8932     { Bad_Opcode },
8933     { Bad_Opcode },
8934     /* 38 */
8935     { PREFIX_TABLE (PREFIX_VEX_0F3A38) },
8936     { PREFIX_TABLE (PREFIX_VEX_0F3A39) },
8937     { Bad_Opcode },
8938     { Bad_Opcode },
8939     { Bad_Opcode },
8940     { Bad_Opcode },
8941     { Bad_Opcode },
8942     { Bad_Opcode },
8943     /* 40 */
8944     { PREFIX_TABLE (PREFIX_VEX_0F3A40) },
8945     { PREFIX_TABLE (PREFIX_VEX_0F3A41) },
8946     { PREFIX_TABLE (PREFIX_VEX_0F3A42) },
8947     { Bad_Opcode },
8948     { PREFIX_TABLE (PREFIX_VEX_0F3A44) },
8949     { Bad_Opcode },
8950     { PREFIX_TABLE (PREFIX_VEX_0F3A46) },
8951     { Bad_Opcode },
8952     /* 48 */
8953     { PREFIX_TABLE (PREFIX_VEX_0F3A48) },
8954     { PREFIX_TABLE (PREFIX_VEX_0F3A49) },
8955     { PREFIX_TABLE (PREFIX_VEX_0F3A4A) },
8956     { PREFIX_TABLE (PREFIX_VEX_0F3A4B) },
8957     { PREFIX_TABLE (PREFIX_VEX_0F3A4C) },
8958     { Bad_Opcode },
8959     { Bad_Opcode },
8960     { Bad_Opcode },
8961     /* 50 */
8962     { Bad_Opcode },
8963     { Bad_Opcode },
8964     { Bad_Opcode },
8965     { Bad_Opcode },
8966     { Bad_Opcode },
8967     { Bad_Opcode },
8968     { Bad_Opcode },
8969     { Bad_Opcode },
8970     /* 58 */
8971     { Bad_Opcode },
8972     { Bad_Opcode },
8973     { Bad_Opcode },
8974     { Bad_Opcode },
8975     { PREFIX_TABLE (PREFIX_VEX_0F3A5C) },
8976     { PREFIX_TABLE (PREFIX_VEX_0F3A5D) },
8977     { PREFIX_TABLE (PREFIX_VEX_0F3A5E) },
8978     { PREFIX_TABLE (PREFIX_VEX_0F3A5F) },
8979     /* 60 */
8980     { PREFIX_TABLE (PREFIX_VEX_0F3A60) },
8981     { PREFIX_TABLE (PREFIX_VEX_0F3A61) },
8982     { PREFIX_TABLE (PREFIX_VEX_0F3A62) },
8983     { PREFIX_TABLE (PREFIX_VEX_0F3A63) },
8984     { Bad_Opcode },
8985     { Bad_Opcode },
8986     { Bad_Opcode },
8987     { Bad_Opcode },
8988     /* 68 */
8989     { PREFIX_TABLE (PREFIX_VEX_0F3A68) },
8990     { PREFIX_TABLE (PREFIX_VEX_0F3A69) },
8991     { PREFIX_TABLE (PREFIX_VEX_0F3A6A) },
8992     { PREFIX_TABLE (PREFIX_VEX_0F3A6B) },
8993     { PREFIX_TABLE (PREFIX_VEX_0F3A6C) },
8994     { PREFIX_TABLE (PREFIX_VEX_0F3A6D) },
8995     { PREFIX_TABLE (PREFIX_VEX_0F3A6E) },
8996     { PREFIX_TABLE (PREFIX_VEX_0F3A6F) },
8997     /* 70 */
8998     { Bad_Opcode },
8999     { Bad_Opcode },
9000     { Bad_Opcode },
9001     { Bad_Opcode },
9002     { Bad_Opcode },
9003     { Bad_Opcode },
9004     { Bad_Opcode },
9005     { Bad_Opcode },
9006     /* 78 */
9007     { PREFIX_TABLE (PREFIX_VEX_0F3A78) },
9008     { PREFIX_TABLE (PREFIX_VEX_0F3A79) },
9009     { PREFIX_TABLE (PREFIX_VEX_0F3A7A) },
9010     { PREFIX_TABLE (PREFIX_VEX_0F3A7B) },
9011     { PREFIX_TABLE (PREFIX_VEX_0F3A7C) },
9012     { PREFIX_TABLE (PREFIX_VEX_0F3A7D) },
9013     { PREFIX_TABLE (PREFIX_VEX_0F3A7E) },
9014     { PREFIX_TABLE (PREFIX_VEX_0F3A7F) },
9015     /* 80 */
9016     { Bad_Opcode },
9017     { Bad_Opcode },
9018     { Bad_Opcode },
9019     { Bad_Opcode },
9020     { Bad_Opcode },
9021     { Bad_Opcode },
9022     { Bad_Opcode },
9023     { Bad_Opcode },
9024     /* 88 */
9025     { Bad_Opcode },
9026     { Bad_Opcode },
9027     { Bad_Opcode },
9028     { Bad_Opcode },
9029     { Bad_Opcode },
9030     { Bad_Opcode },
9031     { Bad_Opcode },
9032     { Bad_Opcode },
9033     /* 90 */
9034     { Bad_Opcode },
9035     { Bad_Opcode },
9036     { Bad_Opcode },
9037     { Bad_Opcode },
9038     { Bad_Opcode },
9039     { Bad_Opcode },
9040     { Bad_Opcode },
9041     { Bad_Opcode },
9042     /* 98 */
9043     { Bad_Opcode },
9044     { Bad_Opcode },
9045     { Bad_Opcode },
9046     { Bad_Opcode },
9047     { Bad_Opcode },
9048     { Bad_Opcode },
9049     { Bad_Opcode },
9050     { Bad_Opcode },
9051     /* a0 */
9052     { Bad_Opcode },
9053     { Bad_Opcode },
9054     { Bad_Opcode },
9055     { Bad_Opcode },
9056     { Bad_Opcode },
9057     { Bad_Opcode },
9058     { Bad_Opcode },
9059     { Bad_Opcode },
9060     /* a8 */
9061     { Bad_Opcode },
9062     { Bad_Opcode },
9063     { Bad_Opcode },
9064     { Bad_Opcode },
9065     { Bad_Opcode },
9066     { Bad_Opcode },
9067     { Bad_Opcode },
9068     { Bad_Opcode },
9069     /* b0 */
9070     { Bad_Opcode },
9071     { Bad_Opcode },
9072     { Bad_Opcode },
9073     { Bad_Opcode },
9074     { Bad_Opcode },
9075     { Bad_Opcode },
9076     { Bad_Opcode },
9077     { Bad_Opcode },
9078     /* b8 */
9079     { Bad_Opcode },
9080     { Bad_Opcode },
9081     { Bad_Opcode },
9082     { Bad_Opcode },
9083     { Bad_Opcode },
9084     { Bad_Opcode },
9085     { Bad_Opcode },
9086     { Bad_Opcode },
9087     /* c0 */
9088     { Bad_Opcode },
9089     { Bad_Opcode },
9090     { Bad_Opcode },
9091     { Bad_Opcode },
9092     { Bad_Opcode },
9093     { Bad_Opcode },
9094     { Bad_Opcode },
9095     { Bad_Opcode },
9096     /* c8 */
9097     { Bad_Opcode },
9098     { Bad_Opcode },
9099     { Bad_Opcode },
9100     { Bad_Opcode },
9101     { Bad_Opcode },
9102     { Bad_Opcode },
9103     { PREFIX_TABLE(PREFIX_VEX_0F3ACE) },
9104     { PREFIX_TABLE(PREFIX_VEX_0F3ACF) },
9105     /* d0 */
9106     { Bad_Opcode },
9107     { Bad_Opcode },
9108     { Bad_Opcode },
9109     { Bad_Opcode },
9110     { Bad_Opcode },
9111     { Bad_Opcode },
9112     { Bad_Opcode },
9113     { Bad_Opcode },
9114     /* d8 */
9115     { Bad_Opcode },
9116     { Bad_Opcode },
9117     { Bad_Opcode },
9118     { Bad_Opcode },
9119     { Bad_Opcode },
9120     { Bad_Opcode },
9121     { Bad_Opcode },
9122     { PREFIX_TABLE (PREFIX_VEX_0F3ADF) },
9123     /* e0 */
9124     { Bad_Opcode },
9125     { Bad_Opcode },
9126     { Bad_Opcode },
9127     { Bad_Opcode },
9128     { Bad_Opcode },
9129     { Bad_Opcode },
9130     { Bad_Opcode },
9131     { Bad_Opcode },
9132     /* e8 */
9133     { Bad_Opcode },
9134     { Bad_Opcode },
9135     { Bad_Opcode },
9136     { Bad_Opcode },
9137     { Bad_Opcode },
9138     { Bad_Opcode },
9139     { Bad_Opcode },
9140     { Bad_Opcode },
9141     /* f0 */
9142     { PREFIX_TABLE (PREFIX_VEX_0F3AF0) },
9143     { Bad_Opcode },
9144     { Bad_Opcode },
9145     { Bad_Opcode },
9146     { Bad_Opcode },
9147     { Bad_Opcode },
9148     { Bad_Opcode },
9149     { Bad_Opcode },
9150     /* f8 */
9151     { Bad_Opcode },
9152     { Bad_Opcode },
9153     { Bad_Opcode },
9154     { Bad_Opcode },
9155     { Bad_Opcode },
9156     { Bad_Opcode },
9157     { Bad_Opcode },
9158     { Bad_Opcode },
9159   },
9160 };
9161
9162 #include "i386-dis-evex.h"
9163
9164 static const struct dis386 vex_len_table[][2] = {
9165   /* VEX_LEN_0F12_P_0_M_0 / VEX_LEN_0F12_P_2_M_0 */
9166   {
9167     { "vmovlpX",        { XM, Vex128, EXq }, 0 },
9168   },
9169
9170   /* VEX_LEN_0F12_P_0_M_1 */
9171   {
9172     { "vmovhlps",       { XM, Vex128, EXq }, 0 },
9173   },
9174
9175   /* VEX_LEN_0F13_M_0 */
9176   {
9177     { "vmovlpX",        { EXq, XM }, PREFIX_OPCODE },
9178   },
9179
9180   /* VEX_LEN_0F16_P_0_M_0 / VEX_LEN_0F16_P_2_M_0 */
9181   {
9182     { "vmovhpX",        { XM, Vex128, EXq }, 0 },
9183   },
9184
9185   /* VEX_LEN_0F16_P_0_M_1 */
9186   {
9187     { "vmovlhps",       { XM, Vex128, EXq }, 0 },
9188   },
9189
9190   /* VEX_LEN_0F17_M_0 */
9191   {
9192     { "vmovhpX",        { EXq, XM }, PREFIX_OPCODE },
9193   },
9194
9195   /* VEX_LEN_0F41_P_0 */
9196   {
9197     { Bad_Opcode },
9198     { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) },
9199   },
9200   /* VEX_LEN_0F41_P_2 */
9201   {
9202     { Bad_Opcode },
9203     { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) },
9204   },
9205   /* VEX_LEN_0F42_P_0 */
9206   {
9207     { Bad_Opcode },
9208     { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) },
9209   },
9210   /* VEX_LEN_0F42_P_2 */
9211   {
9212     { Bad_Opcode },
9213     { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) },
9214   },
9215   /* VEX_LEN_0F44_P_0 */
9216   {
9217     { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) },
9218   },
9219   /* VEX_LEN_0F44_P_2 */
9220   {
9221     { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) },
9222   },
9223   /* VEX_LEN_0F45_P_0 */
9224   {
9225     { Bad_Opcode },
9226     { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) },
9227   },
9228   /* VEX_LEN_0F45_P_2 */
9229   {
9230     { Bad_Opcode },
9231     { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) },
9232   },
9233   /* VEX_LEN_0F46_P_0 */
9234   {
9235     { Bad_Opcode },
9236     { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) },
9237   },
9238   /* VEX_LEN_0F46_P_2 */
9239   {
9240     { Bad_Opcode },
9241     { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) },
9242   },
9243   /* VEX_LEN_0F47_P_0 */
9244   {
9245     { Bad_Opcode },
9246     { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) },
9247   },
9248   /* VEX_LEN_0F47_P_2 */
9249   {
9250     { Bad_Opcode },
9251     { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) },
9252   },
9253   /* VEX_LEN_0F4A_P_0 */
9254   {
9255     { Bad_Opcode },
9256     { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) },
9257   },
9258   /* VEX_LEN_0F4A_P_2 */
9259   {
9260     { Bad_Opcode },
9261     { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) },
9262   },
9263   /* VEX_LEN_0F4B_P_0 */
9264   {
9265     { Bad_Opcode },
9266     { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) },
9267   },
9268   /* VEX_LEN_0F4B_P_2 */
9269   {
9270     { Bad_Opcode },
9271     { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) },
9272   },
9273
9274   /* VEX_LEN_0F6E_P_2 */
9275   {
9276     { "vmovK",          { XMScalar, Edq }, 0 },
9277   },
9278
9279   /* VEX_LEN_0F77_P_1 */
9280   {
9281     { "vzeroupper",     { XX }, 0 },
9282     { "vzeroall",       { XX }, 0 },
9283   },
9284
9285   /* VEX_LEN_0F7E_P_1 */
9286   {
9287     { "vmovq",          { XMScalar, EXxmm_mq }, 0 },
9288   },
9289
9290   /* VEX_LEN_0F7E_P_2 */
9291   {
9292     { "vmovK",          { Edq, XMScalar }, 0 },
9293   },
9294
9295   /* VEX_LEN_0F90_P_0 */
9296   {
9297     { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) },
9298   },
9299
9300   /* VEX_LEN_0F90_P_2 */
9301   {
9302     { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) },
9303   },
9304
9305   /* VEX_LEN_0F91_P_0 */
9306   {
9307     { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) },
9308   },
9309
9310   /* VEX_LEN_0F91_P_2 */
9311   {
9312     { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) },
9313   },
9314
9315   /* VEX_LEN_0F92_P_0 */
9316   {
9317     { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) },
9318   },
9319
9320   /* VEX_LEN_0F92_P_2 */
9321   {
9322     { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) },
9323   },
9324
9325   /* VEX_LEN_0F92_P_3 */
9326   {
9327     { MOD_TABLE (MOD_VEX_0F92_P_3_LEN_0) },
9328   },
9329
9330   /* VEX_LEN_0F93_P_0 */
9331   {
9332     { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) },
9333   },
9334
9335   /* VEX_LEN_0F93_P_2 */
9336   {
9337     { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) },
9338   },
9339
9340   /* VEX_LEN_0F93_P_3 */
9341   {
9342     { MOD_TABLE (MOD_VEX_0F93_P_3_LEN_0) },
9343   },
9344
9345   /* VEX_LEN_0F98_P_0 */
9346   {
9347     { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) },
9348   },
9349
9350   /* VEX_LEN_0F98_P_2 */
9351   {
9352     { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) },
9353   },
9354
9355   /* VEX_LEN_0F99_P_0 */
9356   {
9357     { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) },
9358   },
9359
9360   /* VEX_LEN_0F99_P_2 */
9361   {
9362     { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0) },
9363   },
9364
9365   /* VEX_LEN_0FAE_R_2_M_0 */
9366   {
9367     { "vldmxcsr",       { Md }, 0 },
9368   },
9369
9370   /* VEX_LEN_0FAE_R_3_M_0 */
9371   {
9372     { "vstmxcsr",       { Md }, 0 },
9373   },
9374
9375   /* VEX_LEN_0FC4_P_2 */
9376   {
9377     { "vpinsrw",        { XM, Vex128, Edqw, Ib }, 0 },
9378   },
9379
9380   /* VEX_LEN_0FC5_P_2 */
9381   {
9382     { "vpextrw",        { Gdq, XS, Ib }, 0 },
9383   },
9384
9385   /* VEX_LEN_0FD6_P_2 */
9386   {
9387     { "vmovq",          { EXqVexScalarS, XMScalar }, 0 },
9388   },
9389
9390   /* VEX_LEN_0FF7_P_2 */
9391   {
9392     { "vmaskmovdqu",    { XM, XS }, 0 },
9393   },
9394
9395   /* VEX_LEN_0F3816_P_2 */
9396   {
9397     { Bad_Opcode },
9398     { VEX_W_TABLE (VEX_W_0F3816_P_2) },
9399   },
9400
9401   /* VEX_LEN_0F3819_P_2 */
9402   {
9403     { Bad_Opcode },
9404     { VEX_W_TABLE (VEX_W_0F3819_P_2) },
9405   },
9406
9407   /* VEX_LEN_0F381A_P_2_M_0 */
9408   {
9409     { Bad_Opcode },
9410     { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) },
9411   },
9412
9413   /* VEX_LEN_0F3836_P_2 */
9414   {
9415     { Bad_Opcode },
9416     { VEX_W_TABLE (VEX_W_0F3836_P_2) },
9417   },
9418
9419   /* VEX_LEN_0F3841_P_2 */
9420   {
9421     { "vphminposuw",    { XM, EXx }, 0 },
9422   },
9423
9424   /* VEX_LEN_0F385A_P_2_M_0 */
9425   {
9426     { Bad_Opcode },
9427     { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) },
9428   },
9429
9430   /* VEX_LEN_0F38DB_P_2 */
9431   {
9432     { "vaesimc",        { XM, EXx }, 0 },
9433   },
9434
9435   /* VEX_LEN_0F38F2_P_0 */
9436   {
9437     { "andnS",          { Gdq, VexGdq, Edq }, 0 },
9438   },
9439
9440   /* VEX_LEN_0F38F3_R_1_P_0 */
9441   {
9442     { "blsrS",          { VexGdq, Edq }, 0 },
9443   },
9444
9445   /* VEX_LEN_0F38F3_R_2_P_0 */
9446   {
9447     { "blsmskS",        { VexGdq, Edq }, 0 },
9448   },
9449
9450   /* VEX_LEN_0F38F3_R_3_P_0 */
9451   {
9452     { "blsiS",          { VexGdq, Edq }, 0 },
9453   },
9454
9455   /* VEX_LEN_0F38F5_P_0 */
9456   {
9457     { "bzhiS",          { Gdq, Edq, VexGdq }, 0 },
9458   },
9459
9460   /* VEX_LEN_0F38F5_P_1 */
9461   {
9462     { "pextS",          { Gdq, VexGdq, Edq }, 0 },
9463   },
9464
9465   /* VEX_LEN_0F38F5_P_3 */
9466   {
9467     { "pdepS",          { Gdq, VexGdq, Edq }, 0 },
9468   },
9469
9470   /* VEX_LEN_0F38F6_P_3 */
9471   {
9472     { "mulxS",          { Gdq, VexGdq, Edq }, 0 },
9473   },
9474
9475   /* VEX_LEN_0F38F7_P_0 */
9476   {
9477     { "bextrS",         { Gdq, Edq, VexGdq }, 0 },
9478   },
9479
9480   /* VEX_LEN_0F38F7_P_1 */
9481   {
9482     { "sarxS",          { Gdq, Edq, VexGdq }, 0 },
9483   },
9484
9485   /* VEX_LEN_0F38F7_P_2 */
9486   {
9487     { "shlxS",          { Gdq, Edq, VexGdq }, 0 },
9488   },
9489
9490   /* VEX_LEN_0F38F7_P_3 */
9491   {
9492     { "shrxS",          { Gdq, Edq, VexGdq }, 0 },
9493   },
9494
9495   /* VEX_LEN_0F3A00_P_2 */
9496   {
9497     { Bad_Opcode },
9498     { VEX_W_TABLE (VEX_W_0F3A00_P_2) },
9499   },
9500
9501   /* VEX_LEN_0F3A01_P_2 */
9502   {
9503     { Bad_Opcode },
9504     { VEX_W_TABLE (VEX_W_0F3A01_P_2) },
9505   },
9506
9507   /* VEX_LEN_0F3A06_P_2 */
9508   {
9509     { Bad_Opcode },
9510     { VEX_W_TABLE (VEX_W_0F3A06_P_2) },
9511   },
9512
9513   /* VEX_LEN_0F3A14_P_2 */
9514   {
9515     { "vpextrb",        { Edqb, XM, Ib }, 0 },
9516   },
9517
9518   /* VEX_LEN_0F3A15_P_2 */
9519   {
9520     { "vpextrw",        { Edqw, XM, Ib }, 0 },
9521   },
9522
9523   /* VEX_LEN_0F3A16_P_2  */
9524   {
9525     { "vpextrK",        { Edq, XM, Ib }, 0 },
9526   },
9527
9528   /* VEX_LEN_0F3A17_P_2 */
9529   {
9530     { "vextractps",     { Edqd, XM, Ib }, 0 },
9531   },
9532
9533   /* VEX_LEN_0F3A18_P_2 */
9534   {
9535     { Bad_Opcode },
9536     { VEX_W_TABLE (VEX_W_0F3A18_P_2) },
9537   },
9538
9539   /* VEX_LEN_0F3A19_P_2 */
9540   {
9541     { Bad_Opcode },
9542     { VEX_W_TABLE (VEX_W_0F3A19_P_2) },
9543   },
9544
9545   /* VEX_LEN_0F3A20_P_2 */
9546   {
9547     { "vpinsrb",        { XM, Vex128, Edqb, Ib }, 0 },
9548   },
9549
9550   /* VEX_LEN_0F3A21_P_2 */
9551   {
9552     { "vinsertps",      { XM, Vex128, EXd, Ib }, 0 },
9553   },
9554
9555   /* VEX_LEN_0F3A22_P_2 */
9556   {
9557     { "vpinsrK",        { XM, Vex128, Edq, Ib }, 0 },
9558   },
9559
9560   /* VEX_LEN_0F3A30_P_2 */
9561   {
9562     { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) },
9563   },
9564
9565   /* VEX_LEN_0F3A31_P_2 */
9566   {
9567     { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0) },
9568   },
9569
9570   /* VEX_LEN_0F3A32_P_2 */
9571   {
9572     { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) },
9573   },
9574
9575   /* VEX_LEN_0F3A33_P_2 */
9576   {
9577     { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0) },
9578   },
9579
9580   /* VEX_LEN_0F3A38_P_2 */
9581   {
9582     { Bad_Opcode },
9583     { VEX_W_TABLE (VEX_W_0F3A38_P_2) },
9584   },
9585
9586   /* VEX_LEN_0F3A39_P_2 */
9587   {
9588     { Bad_Opcode },
9589     { VEX_W_TABLE (VEX_W_0F3A39_P_2) },
9590   },
9591
9592   /* VEX_LEN_0F3A41_P_2 */
9593   {
9594     { "vdppd",          { XM, Vex128, EXx, Ib }, 0 },
9595   },
9596
9597   /* VEX_LEN_0F3A46_P_2 */
9598   {
9599     { Bad_Opcode },
9600     { VEX_W_TABLE (VEX_W_0F3A46_P_2) },
9601   },
9602
9603   /* VEX_LEN_0F3A60_P_2 */
9604   {
9605     { "vpcmpestrm",     { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 },
9606   },
9607
9608   /* VEX_LEN_0F3A61_P_2 */
9609   {
9610     { "vpcmpestri",     { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 },
9611   },
9612
9613   /* VEX_LEN_0F3A62_P_2 */
9614   {
9615     { "vpcmpistrm",     { XM, EXx, Ib }, 0 },
9616   },
9617
9618   /* VEX_LEN_0F3A63_P_2 */
9619   {
9620     { "vpcmpistri",     { XM, EXx, Ib }, 0 },
9621   },
9622
9623   /* VEX_LEN_0F3A6A_P_2 */
9624   {
9625     { "vfmaddss",       { XMScalar, VexScalar, EXxmm_md, XMVexI4 }, 0 },
9626   },
9627
9628   /* VEX_LEN_0F3A6B_P_2 */
9629   {
9630     { "vfmaddsd",       { XMScalar, VexScalar, EXxmm_mq, XMVexI4 }, 0 },
9631   },
9632
9633   /* VEX_LEN_0F3A6E_P_2 */
9634   {
9635     { "vfmsubss",       { XMScalar, VexScalar, EXxmm_md, XMVexI4 }, 0 },
9636   },
9637
9638   /* VEX_LEN_0F3A6F_P_2 */
9639   {
9640     { "vfmsubsd",       { XMScalar, VexScalar, EXxmm_mq, XMVexI4 }, 0 },
9641   },
9642
9643   /* VEX_LEN_0F3A7A_P_2 */
9644   {
9645     { "vfnmaddss",      { XMScalar, VexScalar, EXxmm_md, XMVexI4 }, 0 },
9646   },
9647
9648   /* VEX_LEN_0F3A7B_P_2 */
9649   {
9650     { "vfnmaddsd",      { XMScalar, VexScalar, EXxmm_mq, XMVexI4 }, 0 },
9651   },
9652
9653   /* VEX_LEN_0F3A7E_P_2 */
9654   {
9655     { "vfnmsubss",      { XMScalar, VexScalar, EXxmm_md, XMVexI4 }, 0 },
9656   },
9657
9658   /* VEX_LEN_0F3A7F_P_2 */
9659   {
9660     { "vfnmsubsd",      { XMScalar, VexScalar, EXxmm_mq, XMVexI4 }, 0 },
9661   },
9662
9663   /* VEX_LEN_0F3ADF_P_2 */
9664   {
9665     { "vaeskeygenassist", { XM, EXx, Ib }, 0 },
9666   },
9667
9668   /* VEX_LEN_0F3AF0_P_3 */
9669   {
9670     { "rorxS",          { Gdq, Edq, Ib }, 0 },
9671   },
9672
9673   /* VEX_LEN_0FXOP_08_CC */
9674   {
9675      { "vpcomb",        { XM, Vex128, EXx, VPCOM }, 0 },
9676   },
9677
9678   /* VEX_LEN_0FXOP_08_CD */
9679   {
9680      { "vpcomw",        { XM, Vex128, EXx, VPCOM }, 0 },
9681   },
9682
9683   /* VEX_LEN_0FXOP_08_CE */
9684   {
9685      { "vpcomd",        { XM, Vex128, EXx, VPCOM }, 0 },
9686   },
9687
9688   /* VEX_LEN_0FXOP_08_CF */
9689   {
9690      { "vpcomq",        { XM, Vex128, EXx, VPCOM }, 0 },
9691   },
9692
9693   /* VEX_LEN_0FXOP_08_EC */
9694   {
9695      { "vpcomub",       { XM, Vex128, EXx, VPCOM }, 0 },
9696   },
9697
9698   /* VEX_LEN_0FXOP_08_ED */
9699   {
9700      { "vpcomuw",       { XM, Vex128, EXx, VPCOM }, 0 },
9701   },
9702
9703   /* VEX_LEN_0FXOP_08_EE */
9704   {
9705      { "vpcomud",       { XM, Vex128, EXx, VPCOM }, 0 },
9706   },
9707
9708   /* VEX_LEN_0FXOP_08_EF */
9709   {
9710      { "vpcomuq",       { XM, Vex128, EXx, VPCOM }, 0 },
9711   },
9712
9713   /* VEX_LEN_0FXOP_09_82_W_0 */
9714   {
9715     { "vfrczss",        { XM, EXd }, 0 },
9716   },
9717
9718   /* VEX_LEN_0FXOP_09_83_W_0 */
9719   {
9720     { "vfrczsd",        { XM, EXq }, 0 },
9721   },
9722 };
9723
9724 #include "i386-dis-evex-len.h"
9725
9726 static const struct dis386 vex_w_table[][2] = {
9727   {
9728     /* VEX_W_0F41_P_0_LEN_1 */
9729     { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1) },
9730     { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1) },
9731   },
9732   {
9733     /* VEX_W_0F41_P_2_LEN_1 */
9734     { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1) },
9735     { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1) }
9736   },
9737   {
9738     /* VEX_W_0F42_P_0_LEN_1 */
9739     { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1) },
9740     { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1) },
9741   },
9742   {
9743     /* VEX_W_0F42_P_2_LEN_1 */
9744     { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1) },
9745     { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1) },
9746   },
9747   {
9748     /* VEX_W_0F44_P_0_LEN_0 */
9749     { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1) },
9750     { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1) },
9751   },
9752   {
9753     /* VEX_W_0F44_P_2_LEN_0 */
9754     { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1) },
9755     { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1) },
9756   },
9757   {
9758     /* VEX_W_0F45_P_0_LEN_1 */
9759     { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1) },
9760     { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1) },
9761   },
9762   {
9763     /* VEX_W_0F45_P_2_LEN_1 */
9764     { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1) },
9765     { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1) },
9766   },
9767   {
9768     /* VEX_W_0F46_P_0_LEN_1 */
9769     { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1) },
9770     { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1) },
9771   },
9772   {
9773     /* VEX_W_0F46_P_2_LEN_1 */
9774     { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1) },
9775     { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1) },
9776   },
9777   {
9778     /* VEX_W_0F47_P_0_LEN_1 */
9779     { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1) },
9780     { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1) },
9781   },
9782   {
9783     /* VEX_W_0F47_P_2_LEN_1 */
9784     { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1) },
9785     { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1) },
9786   },
9787   {
9788     /* VEX_W_0F4A_P_0_LEN_1 */
9789     { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1) },
9790     { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1) },
9791   },
9792   {
9793     /* VEX_W_0F4A_P_2_LEN_1 */
9794     { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1) },
9795     { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1) },
9796   },
9797   {
9798     /* VEX_W_0F4B_P_0_LEN_1 */
9799     { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1) },
9800     { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1) },
9801   },
9802   {
9803     /* VEX_W_0F4B_P_2_LEN_1 */
9804     { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1) },
9805   },
9806   {
9807     /* VEX_W_0F90_P_0_LEN_0 */
9808     { "kmovw",          { MaskG, MaskE }, 0 },
9809     { "kmovq",          { MaskG, MaskE }, 0 },
9810   },
9811   {
9812     /* VEX_W_0F90_P_2_LEN_0 */
9813     { "kmovb",          { MaskG, MaskBDE }, 0 },
9814     { "kmovd",          { MaskG, MaskBDE }, 0 },
9815   },
9816   {
9817     /* VEX_W_0F91_P_0_LEN_0 */
9818     { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0) },
9819     { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0) },
9820   },
9821   {
9822     /* VEX_W_0F91_P_2_LEN_0 */
9823     { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0) },
9824     { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0) },
9825   },
9826   {
9827     /* VEX_W_0F92_P_0_LEN_0 */
9828     { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0) },
9829   },
9830   {
9831     /* VEX_W_0F92_P_2_LEN_0 */
9832     { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0) },
9833   },
9834   {
9835     /* VEX_W_0F93_P_0_LEN_0 */
9836     { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0) },
9837   },
9838   {
9839     /* VEX_W_0F93_P_2_LEN_0 */
9840     { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0) },
9841   },
9842   {
9843     /* VEX_W_0F98_P_0_LEN_0 */
9844     { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0) },
9845     { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0) },
9846   },
9847   {
9848     /* VEX_W_0F98_P_2_LEN_0 */
9849     { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0) },
9850     { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0) },
9851   },
9852   {
9853     /* VEX_W_0F99_P_0_LEN_0 */
9854     { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0) },
9855     { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0) },
9856   },
9857   {
9858     /* VEX_W_0F99_P_2_LEN_0 */
9859     { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0) },
9860     { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0) },
9861   },
9862   {
9863     /* VEX_W_0F380C_P_2  */
9864     { "vpermilps",      { XM, Vex, EXx }, 0 },
9865   },
9866   {
9867     /* VEX_W_0F380D_P_2  */
9868     { "vpermilpd",      { XM, Vex, EXx }, 0 },
9869   },
9870   {
9871     /* VEX_W_0F380E_P_2  */
9872     { "vtestps",        { XM, EXx }, 0 },
9873   },
9874   {
9875     /* VEX_W_0F380F_P_2  */
9876     { "vtestpd",        { XM, EXx }, 0 },
9877   },
9878   {
9879     /* VEX_W_0F3813_P_2 */
9880     { "vcvtph2ps", { XM, EXxmmq }, 0 },
9881   },
9882   {
9883     /* VEX_W_0F3816_P_2  */
9884     { "vpermps",        { XM, Vex, EXx }, 0 },
9885   },
9886   {
9887     /* VEX_W_0F3818_P_2 */
9888     { "vbroadcastss",   { XM, EXxmm_md }, 0 },
9889   },
9890   {
9891     /* VEX_W_0F3819_P_2 */
9892     { "vbroadcastsd",   { XM, EXxmm_mq }, 0 },
9893   },
9894   {
9895     /* VEX_W_0F381A_P_2_M_0 */
9896     { "vbroadcastf128", { XM, Mxmm }, 0 },
9897   },
9898   {
9899     /* VEX_W_0F382C_P_2_M_0 */
9900     { "vmaskmovps",     { XM, Vex, Mx }, 0 },
9901   },
9902   {
9903     /* VEX_W_0F382D_P_2_M_0 */
9904     { "vmaskmovpd",     { XM, Vex, Mx }, 0 },
9905   },
9906   {
9907     /* VEX_W_0F382E_P_2_M_0 */
9908     { "vmaskmovps",     { Mx, Vex, XM }, 0 },
9909   },
9910   {
9911     /* VEX_W_0F382F_P_2_M_0 */
9912     { "vmaskmovpd",     { Mx, Vex, XM }, 0 },
9913   },
9914   {
9915     /* VEX_W_0F3836_P_2  */
9916     { "vpermd",         { XM, Vex, EXx }, 0 },
9917   },
9918   {
9919     /* VEX_W_0F3846_P_2 */
9920     { "vpsravd",        { XM, Vex, EXx }, 0 },
9921   },
9922   {
9923     /* VEX_W_0F3858_P_2 */
9924     { "vpbroadcastd", { XM, EXxmm_md }, 0 },
9925   },
9926   {
9927     /* VEX_W_0F3859_P_2 */
9928     { "vpbroadcastq",   { XM, EXxmm_mq }, 0 },
9929   },
9930   {
9931     /* VEX_W_0F385A_P_2_M_0 */
9932     { "vbroadcasti128", { XM, Mxmm }, 0 },
9933   },
9934   {
9935     /* VEX_W_0F3878_P_2 */
9936     { "vpbroadcastb",   { XM, EXxmm_mb }, 0 },
9937   },
9938   {
9939     /* VEX_W_0F3879_P_2 */
9940     { "vpbroadcastw",   { XM, EXxmm_mw }, 0 },
9941   },
9942   {
9943     /* VEX_W_0F38CF_P_2 */
9944     { "vgf2p8mulb", { XM, Vex, EXx }, 0 },
9945   },
9946   {
9947     /* VEX_W_0F3A00_P_2 */
9948     { Bad_Opcode },
9949     { "vpermq",         { XM, EXx, Ib }, 0 },
9950   },
9951   {
9952     /* VEX_W_0F3A01_P_2 */
9953     { Bad_Opcode },
9954     { "vpermpd",        { XM, EXx, Ib }, 0 },
9955   },
9956   {
9957     /* VEX_W_0F3A02_P_2 */
9958     { "vpblendd",       { XM, Vex, EXx, Ib }, 0 },
9959   },
9960   {
9961     /* VEX_W_0F3A04_P_2 */
9962     { "vpermilps",      { XM, EXx, Ib }, 0 },
9963   },
9964   {
9965     /* VEX_W_0F3A05_P_2 */
9966     { "vpermilpd",      { XM, EXx, Ib }, 0 },
9967   },
9968   {
9969     /* VEX_W_0F3A06_P_2 */
9970     { "vperm2f128",     { XM, Vex256, EXx, Ib }, 0 },
9971   },
9972   {
9973     /* VEX_W_0F3A18_P_2 */
9974     { "vinsertf128",    { XM, Vex256, EXxmm, Ib }, 0 },
9975   },
9976   {
9977     /* VEX_W_0F3A19_P_2 */
9978     { "vextractf128",   { EXxmm, XM, Ib }, 0 },
9979   },
9980   {
9981     /* VEX_W_0F3A1D_P_2 */
9982     { "vcvtps2ph", { EXxmmq, XM, EXxEVexS, Ib }, 0 },
9983   },
9984   {
9985     /* VEX_W_0F3A30_P_2_LEN_0 */
9986     { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0) },
9987     { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0) },
9988   },
9989   {
9990     /* VEX_W_0F3A31_P_2_LEN_0 */
9991     { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0) },
9992     { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0) },
9993   },
9994   {
9995     /* VEX_W_0F3A32_P_2_LEN_0 */
9996     { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0) },
9997     { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0) },
9998   },
9999   {
10000     /* VEX_W_0F3A33_P_2_LEN_0 */
10001     { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0) },
10002     { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0) },
10003   },
10004   {
10005     /* VEX_W_0F3A38_P_2 */
10006     { "vinserti128",    { XM, Vex256, EXxmm, Ib }, 0 },
10007   },
10008   {
10009     /* VEX_W_0F3A39_P_2 */
10010     { "vextracti128",   { EXxmm, XM, Ib }, 0 },
10011   },
10012   {
10013     /* VEX_W_0F3A46_P_2 */
10014     { "vperm2i128",     { XM, Vex256, EXx, Ib }, 0 },
10015   },
10016   {
10017     /* VEX_W_0F3A4A_P_2 */
10018     { "vblendvps",      { XM, Vex, EXx, XMVexI4 }, 0 },
10019   },
10020   {
10021     /* VEX_W_0F3A4B_P_2 */
10022     { "vblendvpd",      { XM, Vex, EXx, XMVexI4 }, 0 },
10023   },
10024   {
10025     /* VEX_W_0F3A4C_P_2 */
10026     { "vpblendvb",      { XM, Vex, EXx, XMVexI4 }, 0 },
10027   },
10028   {
10029     /* VEX_W_0F3ACE_P_2 */
10030     { Bad_Opcode },
10031     { "vgf2p8affineqb", { XM, Vex, EXx, Ib }, 0 },
10032   },
10033   {
10034     /* VEX_W_0F3ACF_P_2 */
10035     { Bad_Opcode },
10036     { "vgf2p8affineinvqb",  { XM, Vex, EXx, Ib }, 0 },
10037   },
10038   /* VEX_W_0FXOP_09_80 */
10039   {
10040     { "vfrczps",        { XM, EXx }, 0 },
10041   },
10042   /* VEX_W_0FXOP_09_81 */
10043   {
10044     { "vfrczpd",        { XM, EXx }, 0 },
10045   },
10046   /* VEX_W_0FXOP_09_82 */
10047   {
10048     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_82_W_0) },
10049   },
10050   /* VEX_W_0FXOP_09_83 */
10051   {
10052     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_83_W_0) },
10053   },
10054
10055 #include "i386-dis-evex-w.h"
10056 };
10057
10058 static const struct dis386 mod_table[][2] = {
10059   {
10060     /* MOD_8D */
10061     { "leaS",           { Gv, M }, 0 },
10062   },
10063   {
10064     /* MOD_C6_REG_7 */
10065     { Bad_Opcode },
10066     { RM_TABLE (RM_C6_REG_7) },
10067   },
10068   {
10069     /* MOD_C7_REG_7 */
10070     { Bad_Opcode },
10071     { RM_TABLE (RM_C7_REG_7) },
10072   },
10073   {
10074     /* MOD_FF_REG_3 */
10075     { "{l|}call^", { indirEp }, 0 },
10076   },
10077   {
10078     /* MOD_FF_REG_5 */
10079     { "{l|}jmp^", { indirEp }, 0 },
10080   },
10081   {
10082     /* MOD_0F01_REG_0 */
10083     { X86_64_TABLE (X86_64_0F01_REG_0) },
10084     { RM_TABLE (RM_0F01_REG_0) },
10085   },
10086   {
10087     /* MOD_0F01_REG_1 */
10088     { X86_64_TABLE (X86_64_0F01_REG_1) },
10089     { RM_TABLE (RM_0F01_REG_1) },
10090   },
10091   {
10092     /* MOD_0F01_REG_2 */
10093     { X86_64_TABLE (X86_64_0F01_REG_2) },
10094     { RM_TABLE (RM_0F01_REG_2) },
10095   },
10096   {
10097     /* MOD_0F01_REG_3 */
10098     { X86_64_TABLE (X86_64_0F01_REG_3) },
10099     { RM_TABLE (RM_0F01_REG_3) },
10100   },
10101   {
10102     /* MOD_0F01_REG_5 */
10103     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_0) },
10104     { RM_TABLE (RM_0F01_REG_5_MOD_3) },
10105   },
10106   {
10107     /* MOD_0F01_REG_7 */
10108     { "invlpg",         { Mb }, 0 },
10109     { RM_TABLE (RM_0F01_REG_7_MOD_3) },
10110   },
10111   {
10112     /* MOD_0F12_PREFIX_0 */
10113     { "movlpX",         { XM, EXq }, 0 },
10114     { "movhlps",        { XM, EXq }, 0 },
10115   },
10116   {
10117     /* MOD_0F12_PREFIX_2 */
10118     { "movlpX", { XM, EXq }, 0 },
10119   },
10120   {
10121     /* MOD_0F13 */
10122     { "movlpX",         { EXq, XM }, PREFIX_OPCODE },
10123   },
10124   {
10125     /* MOD_0F16_PREFIX_0 */
10126     { "movhpX",         { XM, EXq }, 0 },
10127     { "movlhps",        { XM, EXq }, 0 },
10128   },
10129   {
10130     /* MOD_0F16_PREFIX_2 */
10131     { "movhpX", { XM, EXq }, 0 },
10132   },
10133   {
10134     /* MOD_0F17 */
10135     { "movhpX",         { EXq, XM }, PREFIX_OPCODE },
10136   },
10137   {
10138     /* MOD_0F18_REG_0 */
10139     { "prefetchnta",    { Mb }, 0 },
10140   },
10141   {
10142     /* MOD_0F18_REG_1 */
10143     { "prefetcht0",     { Mb }, 0 },
10144   },
10145   {
10146     /* MOD_0F18_REG_2 */
10147     { "prefetcht1",     { Mb }, 0 },
10148   },
10149   {
10150     /* MOD_0F18_REG_3 */
10151     { "prefetcht2",     { Mb }, 0 },
10152   },
10153   {
10154     /* MOD_0F18_REG_4 */
10155     { "nop/reserved",   { Mb }, 0 },
10156   },
10157   {
10158     /* MOD_0F18_REG_5 */
10159     { "nop/reserved",   { Mb }, 0 },
10160   },
10161   {
10162     /* MOD_0F18_REG_6 */
10163     { "nop/reserved",   { Mb }, 0 },
10164   },
10165   {
10166     /* MOD_0F18_REG_7 */
10167     { "nop/reserved",   { Mb }, 0 },
10168   },
10169   {
10170     /* MOD_0F1A_PREFIX_0 */
10171     { "bndldx",         { Gbnd, Mv_bnd }, 0 },
10172     { "nopQ",           { Ev }, 0 },
10173   },
10174   {
10175     /* MOD_0F1B_PREFIX_0 */
10176     { "bndstx",         { Mv_bnd, Gbnd }, 0 },
10177     { "nopQ",           { Ev }, 0 },
10178   },
10179   {
10180     /* MOD_0F1B_PREFIX_1 */
10181     { "bndmk",          { Gbnd, Mv_bnd }, 0 },
10182     { "nopQ",           { Ev }, 0 },
10183   },
10184   {
10185     /* MOD_0F1C_PREFIX_0 */
10186     { REG_TABLE (REG_0F1C_P_0_MOD_0) },
10187     { "nopQ",           { Ev }, 0 },
10188   },
10189   {
10190     /* MOD_0F1E_PREFIX_1 */
10191     { "nopQ",           { Ev }, 0 },
10192     { REG_TABLE (REG_0F1E_P_1_MOD_3) },
10193   },
10194   {
10195     /* MOD_0F24 */
10196     { Bad_Opcode },
10197     { "movL",           { Rd, Td }, 0 },
10198   },
10199   {
10200     /* MOD_0F26 */
10201     { Bad_Opcode },
10202     { "movL",           { Td, Rd }, 0 },
10203   },
10204   {
10205     /* MOD_0F2B_PREFIX_0 */
10206     {"movntps",         { Mx, XM }, PREFIX_OPCODE },
10207   },
10208   {
10209     /* MOD_0F2B_PREFIX_1 */
10210     {"movntss",         { Md, XM }, PREFIX_OPCODE },
10211   },
10212   {
10213     /* MOD_0F2B_PREFIX_2 */
10214     {"movntpd",         { Mx, XM }, PREFIX_OPCODE },
10215   },
10216   {
10217     /* MOD_0F2B_PREFIX_3 */
10218     {"movntsd",         { Mq, XM }, PREFIX_OPCODE },
10219   },
10220   {
10221     /* MOD_0F50 */
10222     { Bad_Opcode },
10223     { "movmskpX",       { Gdq, XS }, PREFIX_OPCODE },
10224   },
10225   {
10226     /* MOD_0F71_REG_2 */
10227     { Bad_Opcode },
10228     { "psrlw",          { MS, Ib }, 0 },
10229   },
10230   {
10231     /* MOD_0F71_REG_4 */
10232     { Bad_Opcode },
10233     { "psraw",          { MS, Ib }, 0 },
10234   },
10235   {
10236     /* MOD_0F71_REG_6 */
10237     { Bad_Opcode },
10238     { "psllw",          { MS, Ib }, 0 },
10239   },
10240   {
10241     /* MOD_0F72_REG_2 */
10242     { Bad_Opcode },
10243     { "psrld",          { MS, Ib }, 0 },
10244   },
10245   {
10246     /* MOD_0F72_REG_4 */
10247     { Bad_Opcode },
10248     { "psrad",          { MS, Ib }, 0 },
10249   },
10250   {
10251     /* MOD_0F72_REG_6 */
10252     { Bad_Opcode },
10253     { "pslld",          { MS, Ib }, 0 },
10254   },
10255   {
10256     /* MOD_0F73_REG_2 */
10257     { Bad_Opcode },
10258     { "psrlq",          { MS, Ib }, 0 },
10259   },
10260   {
10261     /* MOD_0F73_REG_3 */
10262     { Bad_Opcode },
10263     { PREFIX_TABLE (PREFIX_0F73_REG_3) },
10264   },
10265   {
10266     /* MOD_0F73_REG_6 */
10267     { Bad_Opcode },
10268     { "psllq",          { MS, Ib }, 0 },
10269   },
10270   {
10271     /* MOD_0F73_REG_7 */
10272     { Bad_Opcode },
10273     { PREFIX_TABLE (PREFIX_0F73_REG_7) },
10274   },
10275   {
10276     /* MOD_0FAE_REG_0 */
10277     { "fxsave",         { FXSAVE }, 0 },
10278     { PREFIX_TABLE (PREFIX_0FAE_REG_0_MOD_3) },
10279   },
10280   {
10281     /* MOD_0FAE_REG_1 */
10282     { "fxrstor",        { FXSAVE }, 0 },
10283     { PREFIX_TABLE (PREFIX_0FAE_REG_1_MOD_3) },
10284   },
10285   {
10286     /* MOD_0FAE_REG_2 */
10287     { "ldmxcsr",        { Md }, 0 },
10288     { PREFIX_TABLE (PREFIX_0FAE_REG_2_MOD_3) },
10289   },
10290   {
10291     /* MOD_0FAE_REG_3 */
10292     { "stmxcsr",        { Md }, 0 },
10293     { PREFIX_TABLE (PREFIX_0FAE_REG_3_MOD_3) },
10294   },
10295   {
10296     /* MOD_0FAE_REG_4 */
10297     { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_0) },
10298     { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_3) },
10299   },
10300   {
10301     /* MOD_0FAE_REG_5 */
10302     { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_0) },
10303     { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_3) },
10304   },
10305   {
10306     /* MOD_0FAE_REG_6 */
10307     { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_0) },
10308     { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_3) },
10309   },
10310   {
10311     /* MOD_0FAE_REG_7 */
10312     { PREFIX_TABLE (PREFIX_0FAE_REG_7_MOD_0) },
10313     { RM_TABLE (RM_0FAE_REG_7_MOD_3) },
10314   },
10315   {
10316     /* MOD_0FB2 */
10317     { "lssS",           { Gv, Mp }, 0 },
10318   },
10319   {
10320     /* MOD_0FB4 */
10321     { "lfsS",           { Gv, Mp }, 0 },
10322   },
10323   {
10324     /* MOD_0FB5 */
10325     { "lgsS",           { Gv, Mp }, 0 },
10326   },
10327   {
10328     /* MOD_0FC3 */
10329     { PREFIX_TABLE (PREFIX_0FC3_MOD_0) },
10330   },
10331   {
10332     /* MOD_0FC7_REG_3 */
10333     { "xrstors",        { FXSAVE }, 0 },
10334   },
10335   {
10336     /* MOD_0FC7_REG_4 */
10337     { "xsavec",         { FXSAVE }, 0 },
10338   },
10339   {
10340     /* MOD_0FC7_REG_5 */
10341     { "xsaves",         { FXSAVE }, 0 },
10342   },
10343   {
10344     /* MOD_0FC7_REG_6 */
10345     { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_0) },
10346     { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_3) }
10347   },
10348   {
10349     /* MOD_0FC7_REG_7 */
10350     { "vmptrst",        { Mq }, 0 },
10351     { PREFIX_TABLE (PREFIX_0FC7_REG_7_MOD_3) }
10352   },
10353   {
10354     /* MOD_0FD7 */
10355     { Bad_Opcode },
10356     { "pmovmskb",       { Gdq, MS }, 0 },
10357   },
10358   {
10359     /* MOD_0FE7_PREFIX_2 */
10360     { "movntdq",        { Mx, XM }, 0 },
10361   },
10362   {
10363     /* MOD_0FF0_PREFIX_3 */
10364     { "lddqu",          { XM, M }, 0 },
10365   },
10366   {
10367     /* MOD_0F382A_PREFIX_2 */
10368     { "movntdqa",       { XM, Mx }, 0 },
10369   },
10370   {
10371     /* MOD_0F38F5_PREFIX_2 */
10372     { "wrussK",         { M, Gdq }, PREFIX_OPCODE },
10373   },
10374   {
10375     /* MOD_0F38F6_PREFIX_0 */
10376     { "wrssK",          { M, Gdq }, PREFIX_OPCODE },
10377   },
10378   {
10379     /* MOD_0F38F8_PREFIX_1 */
10380     { "enqcmds",        { Gva, M }, PREFIX_OPCODE },
10381   },
10382   {
10383     /* MOD_0F38F8_PREFIX_2 */
10384     { "movdir64b",      { Gva, M }, PREFIX_OPCODE },
10385   },
10386   {
10387     /* MOD_0F38F8_PREFIX_3 */
10388     { "enqcmd",         { Gva, M }, PREFIX_OPCODE },
10389   },
10390   {
10391     /* MOD_0F38F9_PREFIX_0 */
10392     { "movdiri",        { Ev, Gv }, PREFIX_OPCODE },
10393   },
10394   {
10395     /* MOD_62_32BIT */
10396     { "bound{S|}",      { Gv, Ma }, 0 },
10397     { EVEX_TABLE (EVEX_0F) },
10398   },
10399   {
10400     /* MOD_C4_32BIT */
10401     { "lesS",           { Gv, Mp }, 0 },
10402     { VEX_C4_TABLE (VEX_0F) },
10403   },
10404   {
10405     /* MOD_C5_32BIT */
10406     { "ldsS",           { Gv, Mp }, 0 },
10407     { VEX_C5_TABLE (VEX_0F) },
10408   },
10409   {
10410     /* MOD_VEX_0F12_PREFIX_0 */
10411     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
10412     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
10413   },
10414   {
10415     /* MOD_VEX_0F12_PREFIX_2 */
10416     { VEX_LEN_TABLE (VEX_LEN_0F12_P_2_M_0) },
10417   },
10418   {
10419     /* MOD_VEX_0F13 */
10420     { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
10421   },
10422   {
10423     /* MOD_VEX_0F16_PREFIX_0 */
10424     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
10425     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
10426   },
10427   {
10428     /* MOD_VEX_0F16_PREFIX_2 */
10429     { VEX_LEN_TABLE (VEX_LEN_0F16_P_2_M_0) },
10430   },
10431   {
10432     /* MOD_VEX_0F17 */
10433     { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
10434   },
10435   {
10436     /* MOD_VEX_0F2B */
10437     { "vmovntpX",       { Mx, XM }, PREFIX_OPCODE },
10438   },
10439   {
10440     /* MOD_VEX_W_0_0F41_P_0_LEN_1 */
10441     { Bad_Opcode },
10442     { "kandw",          { MaskG, MaskVex, MaskR }, 0 },
10443   },
10444   {
10445     /* MOD_VEX_W_1_0F41_P_0_LEN_1 */
10446     { Bad_Opcode },
10447     { "kandq",          { MaskG, MaskVex, MaskR }, 0 },
10448   },
10449   {
10450     /* MOD_VEX_W_0_0F41_P_2_LEN_1 */
10451     { Bad_Opcode },
10452     { "kandb",          { MaskG, MaskVex, MaskR }, 0 },
10453   },
10454   {
10455     /* MOD_VEX_W_1_0F41_P_2_LEN_1 */
10456     { Bad_Opcode },
10457     { "kandd",          { MaskG, MaskVex, MaskR }, 0 },
10458   },
10459   {
10460     /* MOD_VEX_W_0_0F42_P_0_LEN_1 */
10461     { Bad_Opcode },
10462     { "kandnw",         { MaskG, MaskVex, MaskR }, 0 },
10463   },
10464   {
10465     /* MOD_VEX_W_1_0F42_P_0_LEN_1 */
10466     { Bad_Opcode },
10467     { "kandnq",         { MaskG, MaskVex, MaskR }, 0 },
10468   },
10469   {
10470     /* MOD_VEX_W_0_0F42_P_2_LEN_1 */
10471     { Bad_Opcode },
10472     { "kandnb",         { MaskG, MaskVex, MaskR }, 0 },
10473   },
10474   {
10475     /* MOD_VEX_W_1_0F42_P_2_LEN_1 */
10476     { Bad_Opcode },
10477     { "kandnd",         { MaskG, MaskVex, MaskR }, 0 },
10478   },
10479   {
10480     /* MOD_VEX_W_0_0F44_P_0_LEN_0 */
10481     { Bad_Opcode },
10482     { "knotw",          { MaskG, MaskR }, 0 },
10483   },
10484   {
10485     /* MOD_VEX_W_1_0F44_P_0_LEN_0 */
10486     { Bad_Opcode },
10487     { "knotq",          { MaskG, MaskR }, 0 },
10488   },
10489   {
10490     /* MOD_VEX_W_0_0F44_P_2_LEN_0 */
10491     { Bad_Opcode },
10492     { "knotb",          { MaskG, MaskR }, 0 },
10493   },
10494   {
10495     /* MOD_VEX_W_1_0F44_P_2_LEN_0 */
10496     { Bad_Opcode },
10497     { "knotd",          { MaskG, MaskR }, 0 },
10498   },
10499   {
10500     /* MOD_VEX_W_0_0F45_P_0_LEN_1 */
10501     { Bad_Opcode },
10502     { "korw",       { MaskG, MaskVex, MaskR }, 0 },
10503   },
10504   {
10505     /* MOD_VEX_W_1_0F45_P_0_LEN_1 */
10506     { Bad_Opcode },
10507     { "korq",       { MaskG, MaskVex, MaskR }, 0 },
10508   },
10509   {
10510     /* MOD_VEX_W_0_0F45_P_2_LEN_1 */
10511     { Bad_Opcode },
10512     { "korb",       { MaskG, MaskVex, MaskR }, 0 },
10513   },
10514   {
10515     /* MOD_VEX_W_1_0F45_P_2_LEN_1 */
10516     { Bad_Opcode },
10517     { "kord",       { MaskG, MaskVex, MaskR }, 0 },
10518   },
10519  {
10520     /* MOD_VEX_W_0_0F46_P_0_LEN_1 */
10521     { Bad_Opcode },
10522     { "kxnorw",     { MaskG, MaskVex, MaskR }, 0 },
10523   },
10524   {
10525     /* MOD_VEX_W_1_0F46_P_0_LEN_1 */
10526     { Bad_Opcode },
10527     { "kxnorq",     { MaskG, MaskVex, MaskR }, 0 },
10528   },
10529   {
10530     /* MOD_VEX_W_0_0F46_P_2_LEN_1 */
10531     { Bad_Opcode },
10532     { "kxnorb",     { MaskG, MaskVex, MaskR }, 0 },
10533   },
10534   {
10535     /* MOD_VEX_W_1_0F46_P_2_LEN_1 */
10536     { Bad_Opcode },
10537     { "kxnord",     { MaskG, MaskVex, MaskR }, 0 },
10538   },
10539   {
10540     /* MOD_VEX_W_0_0F47_P_0_LEN_1 */
10541     { Bad_Opcode },
10542     { "kxorw",      { MaskG, MaskVex, MaskR }, 0 },
10543   },
10544   {
10545     /* MOD_VEX_W_1_0F47_P_0_LEN_1 */
10546     { Bad_Opcode },
10547     { "kxorq",      { MaskG, MaskVex, MaskR }, 0 },
10548   },
10549   {
10550     /* MOD_VEX_W_0_0F47_P_2_LEN_1 */
10551     { Bad_Opcode },
10552     { "kxorb",      { MaskG, MaskVex, MaskR }, 0 },
10553   },
10554   {
10555     /* MOD_VEX_W_1_0F47_P_2_LEN_1 */
10556     { Bad_Opcode },
10557     { "kxord",      { MaskG, MaskVex, MaskR }, 0 },
10558   },
10559   {
10560     /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */
10561     { Bad_Opcode },
10562     { "kaddw",          { MaskG, MaskVex, MaskR }, 0 },
10563   },
10564   {
10565     /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */
10566     { Bad_Opcode },
10567     { "kaddq",          { MaskG, MaskVex, MaskR }, 0 },
10568   },
10569   {
10570     /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */
10571     { Bad_Opcode },
10572     { "kaddb",          { MaskG, MaskVex, MaskR }, 0 },
10573   },
10574   {
10575     /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */
10576     { Bad_Opcode },
10577     { "kaddd",          { MaskG, MaskVex, MaskR }, 0 },
10578   },
10579   {
10580     /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */
10581     { Bad_Opcode },
10582     { "kunpckwd",   { MaskG, MaskVex, MaskR }, 0 },
10583   },
10584   {
10585     /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */
10586     { Bad_Opcode },
10587     { "kunpckdq",   { MaskG, MaskVex, MaskR }, 0 },
10588   },
10589   {
10590     /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */
10591     { Bad_Opcode },
10592     { "kunpckbw",   { MaskG, MaskVex, MaskR }, 0 },
10593   },
10594   {
10595     /* MOD_VEX_0F50 */
10596     { Bad_Opcode },
10597     { "vmovmskpX",      { Gdq, XS }, PREFIX_OPCODE },
10598   },
10599   {
10600     /* MOD_VEX_0F71_REG_2 */
10601     { Bad_Opcode },
10602     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) },
10603   },
10604   {
10605     /* MOD_VEX_0F71_REG_4 */
10606     { Bad_Opcode },
10607     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) },
10608   },
10609   {
10610     /* MOD_VEX_0F71_REG_6 */
10611     { Bad_Opcode },
10612     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) },
10613   },
10614   {
10615     /* MOD_VEX_0F72_REG_2 */
10616     { Bad_Opcode },
10617     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) },
10618   },
10619   {
10620     /* MOD_VEX_0F72_REG_4 */
10621     { Bad_Opcode },
10622     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) },
10623   },
10624   {
10625     /* MOD_VEX_0F72_REG_6 */
10626     { Bad_Opcode },
10627     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) },
10628   },
10629   {
10630     /* MOD_VEX_0F73_REG_2 */
10631     { Bad_Opcode },
10632     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) },
10633   },
10634   {
10635     /* MOD_VEX_0F73_REG_3 */
10636     { Bad_Opcode },
10637     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) },
10638   },
10639   {
10640     /* MOD_VEX_0F73_REG_6 */
10641     { Bad_Opcode },
10642     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) },
10643   },
10644   {
10645     /* MOD_VEX_0F73_REG_7 */
10646     { Bad_Opcode },
10647     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) },
10648   },
10649   {
10650     /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
10651     { "kmovw",          { Ew, MaskG }, 0 },
10652     { Bad_Opcode },
10653   },
10654   {
10655     /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
10656     { "kmovq",          { Eq, MaskG }, 0 },
10657     { Bad_Opcode },
10658   },
10659   {
10660     /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
10661     { "kmovb",          { Eb, MaskG }, 0 },
10662     { Bad_Opcode },
10663   },
10664   {
10665     /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
10666     { "kmovd",          { Ed, MaskG }, 0 },
10667     { Bad_Opcode },
10668   },
10669   {
10670     /* MOD_VEX_W_0_0F92_P_0_LEN_0 */
10671     { Bad_Opcode },
10672     { "kmovw",          { MaskG, Rdq }, 0 },
10673   },
10674   {
10675     /* MOD_VEX_W_0_0F92_P_2_LEN_0 */
10676     { Bad_Opcode },
10677     { "kmovb",          { MaskG, Rdq }, 0 },
10678   },
10679   {
10680     /* MOD_VEX_0F92_P_3_LEN_0 */
10681     { Bad_Opcode },
10682     { "kmovK",          { MaskG, Rdq }, 0 },
10683   },
10684   {
10685     /* MOD_VEX_W_0_0F93_P_0_LEN_0 */
10686     { Bad_Opcode },
10687     { "kmovw",          { Gdq, MaskR }, 0 },
10688   },
10689   {
10690     /* MOD_VEX_W_0_0F93_P_2_LEN_0 */
10691     { Bad_Opcode },
10692     { "kmovb",          { Gdq, MaskR }, 0 },
10693   },
10694   {
10695     /* MOD_VEX_0F93_P_3_LEN_0 */
10696     { Bad_Opcode },
10697     { "kmovK",          { Gdq, MaskR }, 0 },
10698   },
10699   {
10700     /* MOD_VEX_W_0_0F98_P_0_LEN_0 */
10701     { Bad_Opcode },
10702     { "kortestw", { MaskG, MaskR }, 0 },
10703   },
10704   {
10705     /* MOD_VEX_W_1_0F98_P_0_LEN_0 */
10706     { Bad_Opcode },
10707     { "kortestq", { MaskG, MaskR }, 0 },
10708   },
10709   {
10710     /* MOD_VEX_W_0_0F98_P_2_LEN_0 */
10711     { Bad_Opcode },
10712     { "kortestb", { MaskG, MaskR }, 0 },
10713   },
10714   {
10715     /* MOD_VEX_W_1_0F98_P_2_LEN_0 */
10716     { Bad_Opcode },
10717     { "kortestd", { MaskG, MaskR }, 0 },
10718   },
10719   {
10720     /* MOD_VEX_W_0_0F99_P_0_LEN_0 */
10721     { Bad_Opcode },
10722     { "ktestw", { MaskG, MaskR }, 0 },
10723   },
10724   {
10725     /* MOD_VEX_W_1_0F99_P_0_LEN_0 */
10726     { Bad_Opcode },
10727     { "ktestq", { MaskG, MaskR }, 0 },
10728   },
10729   {
10730     /* MOD_VEX_W_0_0F99_P_2_LEN_0 */
10731     { Bad_Opcode },
10732     { "ktestb", { MaskG, MaskR }, 0 },
10733   },
10734   {
10735     /* MOD_VEX_W_1_0F99_P_2_LEN_0 */
10736     { Bad_Opcode },
10737     { "ktestd", { MaskG, MaskR }, 0 },
10738   },
10739   {
10740     /* MOD_VEX_0FAE_REG_2 */
10741     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
10742   },
10743   {
10744     /* MOD_VEX_0FAE_REG_3 */
10745     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
10746   },
10747   {
10748     /* MOD_VEX_0FD7_PREFIX_2 */
10749     { Bad_Opcode },
10750     { "vpmovmskb",      { Gdq, XS }, 0 },
10751   },
10752   {
10753     /* MOD_VEX_0FE7_PREFIX_2 */
10754     { "vmovntdq",       { Mx, XM }, 0 },
10755   },
10756   {
10757     /* MOD_VEX_0FF0_PREFIX_3 */
10758     { "vlddqu",         { XM, M }, 0 },
10759   },
10760   {
10761     /* MOD_VEX_0F381A_PREFIX_2 */
10762     { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) },
10763   },
10764   {
10765     /* MOD_VEX_0F382A_PREFIX_2 */
10766     { "vmovntdqa",      { XM, Mx }, 0 },
10767   },
10768   {
10769     /* MOD_VEX_0F382C_PREFIX_2 */
10770     { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) },
10771   },
10772   {
10773     /* MOD_VEX_0F382D_PREFIX_2 */
10774     { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) },
10775   },
10776   {
10777     /* MOD_VEX_0F382E_PREFIX_2 */
10778     { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) },
10779   },
10780   {
10781     /* MOD_VEX_0F382F_PREFIX_2 */
10782     { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) },
10783   },
10784   {
10785     /* MOD_VEX_0F385A_PREFIX_2 */
10786     { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) },
10787   },
10788   {
10789     /* MOD_VEX_0F388C_PREFIX_2 */
10790     { "vpmaskmov%LW",   { XM, Vex, Mx }, 0 },
10791   },
10792   {
10793     /* MOD_VEX_0F388E_PREFIX_2 */
10794     { "vpmaskmov%LW",   { Mx, Vex, XM }, 0 },
10795   },
10796   {
10797     /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */
10798     { Bad_Opcode },
10799     { "kshiftrb",       { MaskG, MaskR, Ib }, 0 },
10800   },
10801   {
10802     /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */
10803     { Bad_Opcode },
10804     { "kshiftrw",       { MaskG, MaskR, Ib }, 0 },
10805   },
10806   {
10807     /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */
10808     { Bad_Opcode },
10809     { "kshiftrd",       { MaskG, MaskR, Ib }, 0 },
10810   },
10811   {
10812     /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */
10813     { Bad_Opcode },
10814     { "kshiftrq",       { MaskG, MaskR, Ib }, 0 },
10815   },
10816   {
10817     /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */
10818     { Bad_Opcode },
10819     { "kshiftlb",       { MaskG, MaskR, Ib }, 0 },
10820   },
10821   {
10822     /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */
10823     { Bad_Opcode },
10824     { "kshiftlw",       { MaskG, MaskR, Ib }, 0 },
10825   },
10826   {
10827     /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */
10828     { Bad_Opcode },
10829     { "kshiftld",       { MaskG, MaskR, Ib }, 0 },
10830   },
10831   {
10832     /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */
10833     { Bad_Opcode },
10834     { "kshiftlq",       { MaskG, MaskR, Ib }, 0 },
10835   },
10836
10837 #include "i386-dis-evex-mod.h"
10838 };
10839
10840 static const struct dis386 rm_table[][8] = {
10841   {
10842     /* RM_C6_REG_7 */
10843     { "xabort",         { Skip_MODRM, Ib }, 0 },
10844   },
10845   {
10846     /* RM_C7_REG_7 */
10847     { "xbeginT",        { Skip_MODRM, Jdqw }, 0 },
10848   },
10849   {
10850     /* RM_0F01_REG_0 */
10851     { "enclv",          { Skip_MODRM }, 0 },
10852     { "vmcall",         { Skip_MODRM }, 0 },
10853     { "vmlaunch",       { Skip_MODRM }, 0 },
10854     { "vmresume",       { Skip_MODRM }, 0 },
10855     { "vmxoff",         { Skip_MODRM }, 0 },
10856     { "pconfig",        { Skip_MODRM }, 0 },
10857   },
10858   {
10859     /* RM_0F01_REG_1 */
10860     { "monitor",        { { OP_Monitor, 0 } }, 0 },
10861     { "mwait",          { { OP_Mwait, 0 } }, 0 },
10862     { "clac",           { Skip_MODRM }, 0 },
10863     { "stac",           { Skip_MODRM }, 0 },
10864     { Bad_Opcode },
10865     { Bad_Opcode },
10866     { Bad_Opcode },
10867     { "encls",          { Skip_MODRM }, 0 },
10868   },
10869   {
10870     /* RM_0F01_REG_2 */
10871     { "xgetbv",         { Skip_MODRM }, 0 },
10872     { "xsetbv",         { Skip_MODRM }, 0 },
10873     { Bad_Opcode },
10874     { Bad_Opcode },
10875     { "vmfunc",         { Skip_MODRM }, 0 },
10876     { "xend",           { Skip_MODRM }, 0 },
10877     { "xtest",          { Skip_MODRM }, 0 },
10878     { "enclu",          { Skip_MODRM }, 0 },
10879   },
10880   {
10881     /* RM_0F01_REG_3 */
10882     { "vmrun",          { Skip_MODRM }, 0 },
10883     { PREFIX_TABLE (PREFIX_0F01_REG_3_RM_1) },
10884     { "vmload",         { Skip_MODRM }, 0 },
10885     { "vmsave",         { Skip_MODRM }, 0 },
10886     { "stgi",           { Skip_MODRM }, 0 },
10887     { "clgi",           { Skip_MODRM }, 0 },
10888     { "skinit",         { Skip_MODRM }, 0 },
10889     { "invlpga",        { Skip_MODRM }, 0 },
10890   },
10891   {
10892     /* RM_0F01_REG_5_MOD_3 */
10893     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_0) },
10894     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_1) },
10895     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_2) },
10896     { Bad_Opcode },
10897     { Bad_Opcode },
10898     { Bad_Opcode },
10899     { "rdpkru",         { Skip_MODRM }, 0 },
10900     { "wrpkru",         { Skip_MODRM }, 0 },
10901   },
10902   {
10903     /* RM_0F01_REG_7_MOD_3 */
10904     { "swapgs",         { Skip_MODRM }, 0  },
10905     { "rdtscp",         { Skip_MODRM }, 0  },
10906     { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_2) },
10907     { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_3) },
10908     { "clzero",         { Skip_MODRM }, 0  },
10909     { "rdpru",          { Skip_MODRM }, 0  },
10910   },
10911   {
10912     /* RM_0F1E_P_1_MOD_3_REG_7 */
10913     { "nopQ",           { Ev }, 0 },
10914     { "nopQ",           { Ev }, 0 },
10915     { "endbr64",        { Skip_MODRM },  PREFIX_OPCODE },
10916     { "endbr32",        { Skip_MODRM },  PREFIX_OPCODE },
10917     { "nopQ",           { Ev }, 0 },
10918     { "nopQ",           { Ev }, 0 },
10919     { "nopQ",           { Ev }, 0 },
10920     { "nopQ",           { Ev }, 0 },
10921   },
10922   {
10923     /* RM_0FAE_REG_6_MOD_3 */
10924     { "mfence",         { Skip_MODRM }, 0 },
10925   },
10926   {
10927     /* RM_0FAE_REG_7_MOD_3 */
10928     { "sfence",         { Skip_MODRM }, 0 },
10929
10930   },
10931 };
10932
10933 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
10934
10935 /* We use the high bit to indicate different name for the same
10936    prefix.  */
10937 #define REP_PREFIX      (0xf3 | 0x100)
10938 #define XACQUIRE_PREFIX (0xf2 | 0x200)
10939 #define XRELEASE_PREFIX (0xf3 | 0x400)
10940 #define BND_PREFIX      (0xf2 | 0x400)
10941 #define NOTRACK_PREFIX  (0x3e | 0x100)
10942
10943 /* Remember if the current op is a jump instruction.  */
10944 static bfd_boolean op_is_jump = FALSE;
10945
10946 static int
10947 ckprefix (void)
10948 {
10949   int newrex, i, length;
10950   rex = 0;
10951   prefixes = 0;
10952   used_prefixes = 0;
10953   rex_used = 0;
10954   last_lock_prefix = -1;
10955   last_repz_prefix = -1;
10956   last_repnz_prefix = -1;
10957   last_data_prefix = -1;
10958   last_addr_prefix = -1;
10959   last_rex_prefix = -1;
10960   last_seg_prefix = -1;
10961   fwait_prefix = -1;
10962   active_seg_prefix = 0;
10963   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
10964     all_prefixes[i] = 0;
10965   i = 0;
10966   length = 0;
10967   /* The maximum instruction length is 15bytes.  */
10968   while (length < MAX_CODE_LENGTH - 1)
10969     {
10970       FETCH_DATA (the_info, codep + 1);
10971       newrex = 0;
10972       switch (*codep)
10973         {
10974         /* REX prefixes family.  */
10975         case 0x40:
10976         case 0x41:
10977         case 0x42:
10978         case 0x43:
10979         case 0x44:
10980         case 0x45:
10981         case 0x46:
10982         case 0x47:
10983         case 0x48:
10984         case 0x49:
10985         case 0x4a:
10986         case 0x4b:
10987         case 0x4c:
10988         case 0x4d:
10989         case 0x4e:
10990         case 0x4f:
10991           if (address_mode == mode_64bit)
10992             newrex = *codep;
10993           else
10994             return 1;
10995           last_rex_prefix = i;
10996           break;
10997         case 0xf3:
10998           prefixes |= PREFIX_REPZ;
10999           last_repz_prefix = i;
11000           break;
11001         case 0xf2:
11002           prefixes |= PREFIX_REPNZ;
11003           last_repnz_prefix = i;
11004           break;
11005         case 0xf0:
11006           prefixes |= PREFIX_LOCK;
11007           last_lock_prefix = i;
11008           break;
11009         case 0x2e:
11010           prefixes |= PREFIX_CS;
11011           last_seg_prefix = i;
11012           active_seg_prefix = PREFIX_CS;
11013           break;
11014         case 0x36:
11015           prefixes |= PREFIX_SS;
11016           last_seg_prefix = i;
11017           active_seg_prefix = PREFIX_SS;
11018           break;
11019         case 0x3e:
11020           prefixes |= PREFIX_DS;
11021           last_seg_prefix = i;
11022           active_seg_prefix = PREFIX_DS;
11023           break;
11024         case 0x26:
11025           prefixes |= PREFIX_ES;
11026           last_seg_prefix = i;
11027           active_seg_prefix = PREFIX_ES;
11028           break;
11029         case 0x64:
11030           prefixes |= PREFIX_FS;
11031           last_seg_prefix = i;
11032           active_seg_prefix = PREFIX_FS;
11033           break;
11034         case 0x65:
11035           prefixes |= PREFIX_GS;
11036           last_seg_prefix = i;
11037           active_seg_prefix = PREFIX_GS;
11038           break;
11039         case 0x66:
11040           prefixes |= PREFIX_DATA;
11041           last_data_prefix = i;
11042           break;
11043         case 0x67:
11044           prefixes |= PREFIX_ADDR;
11045           last_addr_prefix = i;
11046           break;
11047         case FWAIT_OPCODE:
11048           /* fwait is really an instruction.  If there are prefixes
11049              before the fwait, they belong to the fwait, *not* to the
11050              following instruction.  */
11051           fwait_prefix = i;
11052           if (prefixes || rex)
11053             {
11054               prefixes |= PREFIX_FWAIT;
11055               codep++;
11056               /* This ensures that the previous REX prefixes are noticed
11057                  as unused prefixes, as in the return case below.  */
11058               rex_used = rex;
11059               return 1;
11060             }
11061           prefixes = PREFIX_FWAIT;
11062           break;
11063         default:
11064           return 1;
11065         }
11066       /* Rex is ignored when followed by another prefix.  */
11067       if (rex)
11068         {
11069           rex_used = rex;
11070           return 1;
11071         }
11072       if (*codep != FWAIT_OPCODE)
11073         all_prefixes[i++] = *codep;
11074       rex = newrex;
11075       codep++;
11076       length++;
11077     }
11078   return 0;
11079 }
11080
11081 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
11082    prefix byte.  */
11083
11084 static const char *
11085 prefix_name (int pref, int sizeflag)
11086 {
11087   static const char *rexes [16] =
11088     {
11089       "rex",            /* 0x40 */
11090       "rex.B",          /* 0x41 */
11091       "rex.X",          /* 0x42 */
11092       "rex.XB",         /* 0x43 */
11093       "rex.R",          /* 0x44 */
11094       "rex.RB",         /* 0x45 */
11095       "rex.RX",         /* 0x46 */
11096       "rex.RXB",        /* 0x47 */
11097       "rex.W",          /* 0x48 */
11098       "rex.WB",         /* 0x49 */
11099       "rex.WX",         /* 0x4a */
11100       "rex.WXB",        /* 0x4b */
11101       "rex.WR",         /* 0x4c */
11102       "rex.WRB",        /* 0x4d */
11103       "rex.WRX",        /* 0x4e */
11104       "rex.WRXB",       /* 0x4f */
11105     };
11106
11107   switch (pref)
11108     {
11109     /* REX prefixes family.  */
11110     case 0x40:
11111     case 0x41:
11112     case 0x42:
11113     case 0x43:
11114     case 0x44:
11115     case 0x45:
11116     case 0x46:
11117     case 0x47:
11118     case 0x48:
11119     case 0x49:
11120     case 0x4a:
11121     case 0x4b:
11122     case 0x4c:
11123     case 0x4d:
11124     case 0x4e:
11125     case 0x4f:
11126       return rexes [pref - 0x40];
11127     case 0xf3:
11128       return "repz";
11129     case 0xf2:
11130       return "repnz";
11131     case 0xf0:
11132       return "lock";
11133     case 0x2e:
11134       return "cs";
11135     case 0x36:
11136       return "ss";
11137     case 0x3e:
11138       return "ds";
11139     case 0x26:
11140       return "es";
11141     case 0x64:
11142       return "fs";
11143     case 0x65:
11144       return "gs";
11145     case 0x66:
11146       return (sizeflag & DFLAG) ? "data16" : "data32";
11147     case 0x67:
11148       if (address_mode == mode_64bit)
11149         return (sizeflag & AFLAG) ? "addr32" : "addr64";
11150       else
11151         return (sizeflag & AFLAG) ? "addr16" : "addr32";
11152     case FWAIT_OPCODE:
11153       return "fwait";
11154     case REP_PREFIX:
11155       return "rep";
11156     case XACQUIRE_PREFIX:
11157       return "xacquire";
11158     case XRELEASE_PREFIX:
11159       return "xrelease";
11160     case BND_PREFIX:
11161       return "bnd";
11162     case NOTRACK_PREFIX:
11163       return "notrack";
11164     default:
11165       return NULL;
11166     }
11167 }
11168
11169 static char op_out[MAX_OPERANDS][100];
11170 static int op_ad, op_index[MAX_OPERANDS];
11171 static int two_source_ops;
11172 static bfd_vma op_address[MAX_OPERANDS];
11173 static bfd_vma op_riprel[MAX_OPERANDS];
11174 static bfd_vma start_pc;
11175
11176 /*
11177  *   On the 386's of 1988, the maximum length of an instruction is 15 bytes.
11178  *   (see topic "Redundant prefixes" in the "Differences from 8086"
11179  *   section of the "Virtual 8086 Mode" chapter.)
11180  * 'pc' should be the address of this instruction, it will
11181  *   be used to print the target address if this is a relative jump or call
11182  * The function returns the length of this instruction in bytes.
11183  */
11184
11185 static char intel_syntax;
11186 static char intel_mnemonic = !SYSV386_COMPAT;
11187 static char open_char;
11188 static char close_char;
11189 static char separator_char;
11190 static char scale_char;
11191
11192 enum x86_64_isa
11193 {
11194   amd64 = 1,
11195   intel64
11196 };
11197
11198 static enum x86_64_isa isa64;
11199
11200 /* Here for backwards compatibility.  When gdb stops using
11201    print_insn_i386_att and print_insn_i386_intel these functions can
11202    disappear, and print_insn_i386 be merged into print_insn.  */
11203 int
11204 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
11205 {
11206   intel_syntax = 0;
11207
11208   return print_insn (pc, info);
11209 }
11210
11211 int
11212 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
11213 {
11214   intel_syntax = 1;
11215
11216   return print_insn (pc, info);
11217 }
11218
11219 int
11220 print_insn_i386 (bfd_vma pc, disassemble_info *info)
11221 {
11222   intel_syntax = -1;
11223
11224   return print_insn (pc, info);
11225 }
11226
11227 void
11228 print_i386_disassembler_options (FILE *stream)
11229 {
11230   fprintf (stream, _("\n\
11231 The following i386/x86-64 specific disassembler options are supported for use\n\
11232 with the -M switch (multiple options should be separated by commas):\n"));
11233
11234   fprintf (stream, _("  x86-64      Disassemble in 64bit mode\n"));
11235   fprintf (stream, _("  i386        Disassemble in 32bit mode\n"));
11236   fprintf (stream, _("  i8086       Disassemble in 16bit mode\n"));
11237   fprintf (stream, _("  att         Display instruction in AT&T syntax\n"));
11238   fprintf (stream, _("  intel       Display instruction in Intel syntax\n"));
11239   fprintf (stream, _("  att-mnemonic\n"
11240                      "              Display instruction in AT&T mnemonic\n"));
11241   fprintf (stream, _("  intel-mnemonic\n"
11242                      "              Display instruction in Intel mnemonic\n"));
11243   fprintf (stream, _("  addr64      Assume 64bit address size\n"));
11244   fprintf (stream, _("  addr32      Assume 32bit address size\n"));
11245   fprintf (stream, _("  addr16      Assume 16bit address size\n"));
11246   fprintf (stream, _("  data32      Assume 32bit data size\n"));
11247   fprintf (stream, _("  data16      Assume 16bit data size\n"));
11248   fprintf (stream, _("  suffix      Always display instruction suffix in AT&T syntax\n"));
11249   fprintf (stream, _("  amd64       Display instruction in AMD64 ISA\n"));
11250   fprintf (stream, _("  intel64     Display instruction in Intel64 ISA\n"));
11251 }
11252
11253 /* Bad opcode.  */
11254 static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 };
11255
11256 /* Get a pointer to struct dis386 with a valid name.  */
11257
11258 static const struct dis386 *
11259 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
11260 {
11261   int vindex, vex_table_index;
11262
11263   if (dp->name != NULL)
11264     return dp;
11265
11266   switch (dp->op[0].bytemode)
11267     {
11268     case USE_REG_TABLE:
11269       dp = &reg_table[dp->op[1].bytemode][modrm.reg];
11270       break;
11271
11272     case USE_MOD_TABLE:
11273       vindex = modrm.mod == 0x3 ? 1 : 0;
11274       dp = &mod_table[dp->op[1].bytemode][vindex];
11275       break;
11276
11277     case USE_RM_TABLE:
11278       dp = &rm_table[dp->op[1].bytemode][modrm.rm];
11279       break;
11280
11281     case USE_PREFIX_TABLE:
11282       if (need_vex)
11283         {
11284           /* The prefix in VEX is implicit.  */
11285           switch (vex.prefix)
11286             {
11287             case 0:
11288               vindex = 0;
11289               break;
11290             case REPE_PREFIX_OPCODE:
11291               vindex = 1;
11292               break;
11293             case DATA_PREFIX_OPCODE:
11294               vindex = 2;
11295               break;
11296             case REPNE_PREFIX_OPCODE:
11297               vindex = 3;
11298               break;
11299             default:
11300               abort ();
11301               break;
11302             }
11303         }
11304       else
11305         {
11306           int last_prefix = -1;
11307           int prefix = 0;
11308           vindex = 0;
11309           /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
11310              When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
11311              last one wins.  */
11312           if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
11313             {
11314               if (last_repz_prefix > last_repnz_prefix)
11315                 {
11316                   vindex = 1;
11317                   prefix = PREFIX_REPZ;
11318                   last_prefix = last_repz_prefix;
11319                 }
11320               else
11321                 {
11322                   vindex = 3;
11323                   prefix = PREFIX_REPNZ;
11324                   last_prefix = last_repnz_prefix;
11325                 }
11326
11327               /* Check if prefix should be ignored.  */
11328               if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement
11329                      & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT)
11330                    & prefix) != 0)
11331                 vindex = 0;
11332             }
11333
11334           if (vindex == 0 && (prefixes & PREFIX_DATA) != 0)
11335             {
11336               vindex = 2;
11337               prefix = PREFIX_DATA;
11338               last_prefix = last_data_prefix;
11339             }
11340
11341           if (vindex != 0)
11342             {
11343               used_prefixes |= prefix;
11344               all_prefixes[last_prefix] = 0;
11345             }
11346         }
11347       dp = &prefix_table[dp->op[1].bytemode][vindex];
11348       break;
11349
11350     case USE_X86_64_TABLE:
11351       vindex = address_mode == mode_64bit ? 1 : 0;
11352       dp = &x86_64_table[dp->op[1].bytemode][vindex];
11353       break;
11354
11355     case USE_3BYTE_TABLE:
11356       FETCH_DATA (info, codep + 2);
11357       vindex = *codep++;
11358       dp = &three_byte_table[dp->op[1].bytemode][vindex];
11359       end_codep = codep;
11360       modrm.mod = (*codep >> 6) & 3;
11361       modrm.reg = (*codep >> 3) & 7;
11362       modrm.rm = *codep & 7;
11363       break;
11364
11365     case USE_VEX_LEN_TABLE:
11366       if (!need_vex)
11367         abort ();
11368
11369       switch (vex.length)
11370         {
11371         case 128:
11372           vindex = 0;
11373           break;
11374         case 256:
11375           vindex = 1;
11376           break;
11377         default:
11378           abort ();
11379           break;
11380         }
11381
11382       dp = &vex_len_table[dp->op[1].bytemode][vindex];
11383       break;
11384
11385     case USE_EVEX_LEN_TABLE:
11386       if (!vex.evex)
11387         abort ();
11388
11389       switch (vex.length)
11390         {
11391         case 128:
11392           vindex = 0;
11393           break;
11394         case 256:
11395           vindex = 1;
11396           break;
11397         case 512:
11398           vindex = 2;
11399           break;
11400         default:
11401           abort ();
11402           break;
11403         }
11404
11405       dp = &evex_len_table[dp->op[1].bytemode][vindex];
11406       break;
11407
11408     case USE_XOP_8F_TABLE:
11409       FETCH_DATA (info, codep + 3);
11410       rex = ~(*codep >> 5) & 0x7;
11411
11412       /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm".  */
11413       switch ((*codep & 0x1f))
11414         {
11415         default:
11416           dp = &bad_opcode;
11417           return dp;
11418         case 0x8:
11419           vex_table_index = XOP_08;
11420           break;
11421         case 0x9:
11422           vex_table_index = XOP_09;
11423           break;
11424         case 0xa:
11425           vex_table_index = XOP_0A;
11426           break;
11427         }
11428       codep++;
11429       vex.w = *codep & 0x80;
11430       if (vex.w && address_mode == mode_64bit)
11431         rex |= REX_W;
11432
11433       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11434       if (address_mode != mode_64bit)
11435         {
11436           /* In 16/32-bit mode REX_B is silently ignored.  */
11437           rex &= ~REX_B;
11438         }
11439
11440       vex.length = (*codep & 0x4) ? 256 : 128;
11441       switch ((*codep & 0x3))
11442         {
11443         case 0:
11444           break;
11445         case 1:
11446           vex.prefix = DATA_PREFIX_OPCODE;
11447           break;
11448         case 2:
11449           vex.prefix = REPE_PREFIX_OPCODE;
11450           break;
11451         case 3:
11452           vex.prefix = REPNE_PREFIX_OPCODE;
11453           break;
11454         }
11455       need_vex = 1;
11456       need_vex_reg = 1;
11457       codep++;
11458       vindex = *codep++;
11459       dp = &xop_table[vex_table_index][vindex];
11460
11461       end_codep = codep;
11462       FETCH_DATA (info, codep + 1);
11463       modrm.mod = (*codep >> 6) & 3;
11464       modrm.reg = (*codep >> 3) & 7;
11465       modrm.rm = *codep & 7;
11466
11467       /* No XOP encoding so far allows for a non-zero embedded prefix. Avoid
11468          having to decode the bits for every otherwise valid encoding.  */
11469       if (vex.prefix)
11470         return &bad_opcode;
11471       break;
11472
11473     case USE_VEX_C4_TABLE:
11474       /* VEX prefix.  */
11475       FETCH_DATA (info, codep + 3);
11476       rex = ~(*codep >> 5) & 0x7;
11477       switch ((*codep & 0x1f))
11478         {
11479         default:
11480           dp = &bad_opcode;
11481           return dp;
11482         case 0x1:
11483           vex_table_index = VEX_0F;
11484           break;
11485         case 0x2:
11486           vex_table_index = VEX_0F38;
11487           break;
11488         case 0x3:
11489           vex_table_index = VEX_0F3A;
11490           break;
11491         }
11492       codep++;
11493       vex.w = *codep & 0x80;
11494       if (address_mode == mode_64bit)
11495         {
11496           if (vex.w)
11497             rex |= REX_W;
11498         }
11499       else
11500         {
11501           /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
11502              is ignored, other REX bits are 0 and the highest bit in
11503              VEX.vvvv is also ignored (but we mustn't clear it here).  */
11504           rex = 0;
11505         }
11506       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11507       vex.length = (*codep & 0x4) ? 256 : 128;
11508       switch ((*codep & 0x3))
11509         {
11510         case 0:
11511           break;
11512         case 1:
11513           vex.prefix = DATA_PREFIX_OPCODE;
11514           break;
11515         case 2:
11516           vex.prefix = REPE_PREFIX_OPCODE;
11517           break;
11518         case 3:
11519           vex.prefix = REPNE_PREFIX_OPCODE;
11520           break;
11521         }
11522       need_vex = 1;
11523       need_vex_reg = 1;
11524       codep++;
11525       vindex = *codep++;
11526       dp = &vex_table[vex_table_index][vindex];
11527       end_codep = codep;
11528       /* There is no MODRM byte for VEX0F 77.  */
11529       if (vex_table_index != VEX_0F || vindex != 0x77)
11530         {
11531           FETCH_DATA (info, codep + 1);
11532           modrm.mod = (*codep >> 6) & 3;
11533           modrm.reg = (*codep >> 3) & 7;
11534           modrm.rm = *codep & 7;
11535         }
11536       break;
11537
11538     case USE_VEX_C5_TABLE:
11539       /* VEX prefix.  */
11540       FETCH_DATA (info, codep + 2);
11541       rex = (*codep & 0x80) ? 0 : REX_R;
11542
11543       /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
11544          VEX.vvvv is 1.  */
11545       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11546       vex.length = (*codep & 0x4) ? 256 : 128;
11547       switch ((*codep & 0x3))
11548         {
11549         case 0:
11550           break;
11551         case 1:
11552           vex.prefix = DATA_PREFIX_OPCODE;
11553           break;
11554         case 2:
11555           vex.prefix = REPE_PREFIX_OPCODE;
11556           break;
11557         case 3:
11558           vex.prefix = REPNE_PREFIX_OPCODE;
11559           break;
11560         }
11561       need_vex = 1;
11562       need_vex_reg = 1;
11563       codep++;
11564       vindex = *codep++;
11565       dp = &vex_table[dp->op[1].bytemode][vindex];
11566       end_codep = codep;
11567       /* There is no MODRM byte for VEX 77.  */
11568       if (vindex != 0x77)
11569         {
11570           FETCH_DATA (info, codep + 1);
11571           modrm.mod = (*codep >> 6) & 3;
11572           modrm.reg = (*codep >> 3) & 7;
11573           modrm.rm = *codep & 7;
11574         }
11575       break;
11576
11577     case USE_VEX_W_TABLE:
11578       if (!need_vex)
11579         abort ();
11580
11581       dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
11582       break;
11583
11584     case USE_EVEX_TABLE:
11585       two_source_ops = 0;
11586       /* EVEX prefix.  */
11587       vex.evex = 1;
11588       FETCH_DATA (info, codep + 4);
11589       /* The first byte after 0x62.  */
11590       rex = ~(*codep >> 5) & 0x7;
11591       vex.r = *codep & 0x10;
11592       switch ((*codep & 0xf))
11593         {
11594         default:
11595           return &bad_opcode;
11596         case 0x1:
11597           vex_table_index = EVEX_0F;
11598           break;
11599         case 0x2:
11600           vex_table_index = EVEX_0F38;
11601           break;
11602         case 0x3:
11603           vex_table_index = EVEX_0F3A;
11604           break;
11605         }
11606
11607       /* The second byte after 0x62.  */
11608       codep++;
11609       vex.w = *codep & 0x80;
11610       if (vex.w && address_mode == mode_64bit)
11611         rex |= REX_W;
11612
11613       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11614
11615       /* The U bit.  */
11616       if (!(*codep & 0x4))
11617         return &bad_opcode;
11618
11619       switch ((*codep & 0x3))
11620         {
11621         case 0:
11622           break;
11623         case 1:
11624           vex.prefix = DATA_PREFIX_OPCODE;
11625           break;
11626         case 2:
11627           vex.prefix = REPE_PREFIX_OPCODE;
11628           break;
11629         case 3:
11630           vex.prefix = REPNE_PREFIX_OPCODE;
11631           break;
11632         }
11633
11634       /* The third byte after 0x62.  */
11635       codep++;
11636
11637       /* Remember the static rounding bits.  */
11638       vex.ll = (*codep >> 5) & 3;
11639       vex.b = (*codep & 0x10) != 0;
11640
11641       vex.v = *codep & 0x8;
11642       vex.mask_register_specifier = *codep & 0x7;
11643       vex.zeroing = *codep & 0x80;
11644
11645       if (address_mode != mode_64bit)
11646         {
11647           /* In 16/32-bit mode silently ignore following bits.  */
11648           rex &= ~REX_B;
11649           vex.r = 1;
11650           vex.v = 1;
11651         }
11652
11653       need_vex = 1;
11654       need_vex_reg = 1;
11655       codep++;
11656       vindex = *codep++;
11657       dp = &evex_table[vex_table_index][vindex];
11658       end_codep = codep;
11659       FETCH_DATA (info, codep + 1);
11660       modrm.mod = (*codep >> 6) & 3;
11661       modrm.reg = (*codep >> 3) & 7;
11662       modrm.rm = *codep & 7;
11663
11664       /* Set vector length.  */
11665       if (modrm.mod == 3 && vex.b)
11666         vex.length = 512;
11667       else
11668         {
11669           switch (vex.ll)
11670             {
11671             case 0x0:
11672               vex.length = 128;
11673               break;
11674             case 0x1:
11675               vex.length = 256;
11676               break;
11677             case 0x2:
11678               vex.length = 512;
11679               break;
11680             default:
11681               return &bad_opcode;
11682             }
11683         }
11684       break;
11685
11686     case 0:
11687       dp = &bad_opcode;
11688       break;
11689
11690     default:
11691       abort ();
11692     }
11693
11694   if (dp->name != NULL)
11695     return dp;
11696   else
11697     return get_valid_dis386 (dp, info);
11698 }
11699
11700 static void
11701 get_sib (disassemble_info *info, int sizeflag)
11702 {
11703   /* If modrm.mod == 3, operand must be register.  */
11704   if (need_modrm
11705       && ((sizeflag & AFLAG) || address_mode == mode_64bit)
11706       && modrm.mod != 3
11707       && modrm.rm == 4)
11708     {
11709       FETCH_DATA (info, codep + 2);
11710       sib.index = (codep [1] >> 3) & 7;
11711       sib.scale = (codep [1] >> 6) & 3;
11712       sib.base = codep [1] & 7;
11713     }
11714 }
11715
11716 static int
11717 print_insn (bfd_vma pc, disassemble_info *info)
11718 {
11719   const struct dis386 *dp;
11720   int i;
11721   char *op_txt[MAX_OPERANDS];
11722   int needcomma;
11723   int sizeflag, orig_sizeflag;
11724   const char *p;
11725   struct dis_private priv;
11726   int prefix_length;
11727
11728   priv.orig_sizeflag = AFLAG | DFLAG;
11729   if ((info->mach & bfd_mach_i386_i386) != 0)
11730     address_mode = mode_32bit;
11731   else if (info->mach == bfd_mach_i386_i8086)
11732     {
11733       address_mode = mode_16bit;
11734       priv.orig_sizeflag = 0;
11735     }
11736   else
11737     address_mode = mode_64bit;
11738
11739   if (intel_syntax == (char) -1)
11740     intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0;
11741
11742   for (p = info->disassembler_options; p != NULL; )
11743     {
11744       if (CONST_STRNEQ (p, "amd64"))
11745         isa64 = amd64;
11746       else if (CONST_STRNEQ (p, "intel64"))
11747         isa64 = intel64;
11748       else if (CONST_STRNEQ (p, "x86-64"))
11749         {
11750           address_mode = mode_64bit;
11751           priv.orig_sizeflag |= AFLAG | DFLAG;
11752         }
11753       else if (CONST_STRNEQ (p, "i386"))
11754         {
11755           address_mode = mode_32bit;
11756           priv.orig_sizeflag |= AFLAG | DFLAG;
11757         }
11758       else if (CONST_STRNEQ (p, "i8086"))
11759         {
11760           address_mode = mode_16bit;
11761           priv.orig_sizeflag &= ~(AFLAG | DFLAG);
11762         }
11763       else if (CONST_STRNEQ (p, "intel"))
11764         {
11765           intel_syntax = 1;
11766           if (CONST_STRNEQ (p + 5, "-mnemonic"))
11767             intel_mnemonic = 1;
11768         }
11769       else if (CONST_STRNEQ (p, "att"))
11770         {
11771           intel_syntax = 0;
11772           if (CONST_STRNEQ (p + 3, "-mnemonic"))
11773             intel_mnemonic = 0;
11774         }
11775       else if (CONST_STRNEQ (p, "addr"))
11776         {
11777           if (address_mode == mode_64bit)
11778             {
11779               if (p[4] == '3' && p[5] == '2')
11780                 priv.orig_sizeflag &= ~AFLAG;
11781               else if (p[4] == '6' && p[5] == '4')
11782                 priv.orig_sizeflag |= AFLAG;
11783             }
11784           else
11785             {
11786               if (p[4] == '1' && p[5] == '6')
11787                 priv.orig_sizeflag &= ~AFLAG;
11788               else if (p[4] == '3' && p[5] == '2')
11789                 priv.orig_sizeflag |= AFLAG;
11790             }
11791         }
11792       else if (CONST_STRNEQ (p, "data"))
11793         {
11794           if (p[4] == '1' && p[5] == '6')
11795             priv.orig_sizeflag &= ~DFLAG;
11796           else if (p[4] == '3' && p[5] == '2')
11797             priv.orig_sizeflag |= DFLAG;
11798         }
11799       else if (CONST_STRNEQ (p, "suffix"))
11800         priv.orig_sizeflag |= SUFFIX_ALWAYS;
11801
11802       p = strchr (p, ',');
11803       if (p != NULL)
11804         p++;
11805     }
11806
11807   if (address_mode == mode_64bit && sizeof (bfd_vma) < 8)
11808     {
11809       (*info->fprintf_func) (info->stream,
11810                              _("64-bit address is disabled"));
11811       return -1;
11812     }
11813
11814   if (intel_syntax)
11815     {
11816       names64 = intel_names64;
11817       names32 = intel_names32;
11818       names16 = intel_names16;
11819       names8 = intel_names8;
11820       names8rex = intel_names8rex;
11821       names_seg = intel_names_seg;
11822       names_mm = intel_names_mm;
11823       names_bnd = intel_names_bnd;
11824       names_xmm = intel_names_xmm;
11825       names_ymm = intel_names_ymm;
11826       names_zmm = intel_names_zmm;
11827       index64 = intel_index64;
11828       index32 = intel_index32;
11829       names_mask = intel_names_mask;
11830       index16 = intel_index16;
11831       open_char = '[';
11832       close_char = ']';
11833       separator_char = '+';
11834       scale_char = '*';
11835     }
11836   else
11837     {
11838       names64 = att_names64;
11839       names32 = att_names32;
11840       names16 = att_names16;
11841       names8 = att_names8;
11842       names8rex = att_names8rex;
11843       names_seg = att_names_seg;
11844       names_mm = att_names_mm;
11845       names_bnd = att_names_bnd;
11846       names_xmm = att_names_xmm;
11847       names_ymm = att_names_ymm;
11848       names_zmm = att_names_zmm;
11849       index64 = att_index64;
11850       index32 = att_index32;
11851       names_mask = att_names_mask;
11852       index16 = att_index16;
11853       open_char = '(';
11854       close_char =  ')';
11855       separator_char = ',';
11856       scale_char = ',';
11857     }
11858
11859   /* The output looks better if we put 7 bytes on a line, since that
11860      puts most long word instructions on a single line.  Use 8 bytes
11861      for Intel L1OM.  */
11862   if ((info->mach & bfd_mach_l1om) != 0)
11863     info->bytes_per_line = 8;
11864   else
11865     info->bytes_per_line = 7;
11866
11867   info->private_data = &priv;
11868   priv.max_fetched = priv.the_buffer;
11869   priv.insn_start = pc;
11870
11871   obuf[0] = 0;
11872   for (i = 0; i < MAX_OPERANDS; ++i)
11873     {
11874       op_out[i][0] = 0;
11875       op_index[i] = -1;
11876     }
11877
11878   the_info = info;
11879   start_pc = pc;
11880   start_codep = priv.the_buffer;
11881   codep = priv.the_buffer;
11882
11883   if (OPCODES_SIGSETJMP (priv.bailout) != 0)
11884     {
11885       const char *name;
11886
11887       /* Getting here means we tried for data but didn't get it.  That
11888          means we have an incomplete instruction of some sort.  Just
11889          print the first byte as a prefix or a .byte pseudo-op.  */
11890       if (codep > priv.the_buffer)
11891         {
11892           name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
11893           if (name != NULL)
11894             (*info->fprintf_func) (info->stream, "%s", name);
11895           else
11896             {
11897               /* Just print the first byte as a .byte instruction.  */
11898               (*info->fprintf_func) (info->stream, ".byte 0x%x",
11899                                      (unsigned int) priv.the_buffer[0]);
11900             }
11901
11902           return 1;
11903         }
11904
11905       return -1;
11906     }
11907
11908   obufp = obuf;
11909   sizeflag = priv.orig_sizeflag;
11910
11911   if (!ckprefix () || rex_used)
11912     {
11913       /* Too many prefixes or unused REX prefixes.  */
11914       for (i = 0;
11915            i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i];
11916            i++)
11917         (*info->fprintf_func) (info->stream, "%s%s",
11918                                i == 0 ? "" : " ",
11919                                prefix_name (all_prefixes[i], sizeflag));
11920       return i;
11921     }
11922
11923   insn_codep = codep;
11924
11925   FETCH_DATA (info, codep + 1);
11926   two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
11927
11928   if (((prefixes & PREFIX_FWAIT)
11929        && ((*codep < 0xd8) || (*codep > 0xdf))))
11930     {
11931       /* Handle prefixes before fwait.  */
11932       for (i = 0; i < fwait_prefix && all_prefixes[i];
11933            i++)
11934         (*info->fprintf_func) (info->stream, "%s ",
11935                                prefix_name (all_prefixes[i], sizeflag));
11936       (*info->fprintf_func) (info->stream, "fwait");
11937       return i + 1;
11938     }
11939
11940   if (*codep == 0x0f)
11941     {
11942       unsigned char threebyte;
11943
11944       codep++;
11945       FETCH_DATA (info, codep + 1);
11946       threebyte = *codep;
11947       dp = &dis386_twobyte[threebyte];
11948       need_modrm = twobyte_has_modrm[*codep];
11949       codep++;
11950     }
11951   else
11952     {
11953       dp = &dis386[*codep];
11954       need_modrm = onebyte_has_modrm[*codep];
11955       codep++;
11956     }
11957
11958   /* Save sizeflag for printing the extra prefixes later before updating
11959      it for mnemonic and operand processing.  The prefix names depend
11960      only on the address mode.  */
11961   orig_sizeflag = sizeflag;
11962   if (prefixes & PREFIX_ADDR)
11963     sizeflag ^= AFLAG;
11964   if ((prefixes & PREFIX_DATA))
11965     sizeflag ^= DFLAG;
11966
11967   end_codep = codep;
11968   if (need_modrm)
11969     {
11970       FETCH_DATA (info, codep + 1);
11971       modrm.mod = (*codep >> 6) & 3;
11972       modrm.reg = (*codep >> 3) & 7;
11973       modrm.rm = *codep & 7;
11974     }
11975
11976   need_vex = 0;
11977   need_vex_reg = 0;
11978   memset (&vex, 0, sizeof (vex));
11979
11980   if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
11981     {
11982       get_sib (info, sizeflag);
11983       dofloat (sizeflag);
11984     }
11985   else
11986     {
11987       dp = get_valid_dis386 (dp, info);
11988       if (dp != NULL && putop (dp->name, sizeflag) == 0)
11989         {
11990           get_sib (info, sizeflag);
11991           for (i = 0; i < MAX_OPERANDS; ++i)
11992             {
11993               obufp = op_out[i];
11994               op_ad = MAX_OPERANDS - 1 - i;
11995               if (dp->op[i].rtn)
11996                 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
11997               /* For EVEX instruction after the last operand masking
11998                  should be printed.  */
11999               if (i == 0 && vex.evex)
12000                 {
12001                   /* Don't print {%k0}.  */
12002                   if (vex.mask_register_specifier)
12003                     {
12004                       oappend ("{");
12005                       oappend (names_mask[vex.mask_register_specifier]);
12006                       oappend ("}");
12007                     }
12008                   if (vex.zeroing)
12009                     oappend ("{z}");
12010                 }
12011             }
12012         }
12013     }
12014
12015   /* Clear instruction information.  */
12016   if (the_info)
12017     {
12018       the_info->insn_info_valid = 0;
12019       the_info->branch_delay_insns = 0;
12020       the_info->data_size = 0;
12021       the_info->insn_type = dis_noninsn;
12022       the_info->target = 0;
12023       the_info->target2 = 0;
12024     }
12025
12026   /* Reset jump operation indicator.  */
12027   op_is_jump = FALSE;
12028
12029   {
12030     int jump_detection = 0;
12031
12032     /* Extract flags.  */
12033     for (i = 0; i < MAX_OPERANDS; ++i)
12034       {
12035         if ((dp->op[i].rtn == OP_J)
12036             || (dp->op[i].rtn == OP_indirE))
12037           jump_detection |= 1;
12038         else if ((dp->op[i].rtn == BND_Fixup)
12039                  || (!dp->op[i].rtn && !dp->op[i].bytemode))
12040           jump_detection |= 2;
12041         else if ((dp->op[i].bytemode == cond_jump_mode)
12042                  || (dp->op[i].bytemode == loop_jcxz_mode))
12043           jump_detection |= 4;
12044       }
12045
12046     /* Determine if this is a jump or branch.  */
12047     if ((jump_detection & 0x3) == 0x3)
12048       {
12049         op_is_jump = TRUE;
12050         if (jump_detection & 0x4)
12051           the_info->insn_type = dis_condbranch;
12052         else
12053           the_info->insn_type =
12054             (dp->name && !strncmp(dp->name, "call", 4))
12055             ? dis_jsr : dis_branch;
12056       }
12057   }
12058
12059   /* If VEX.vvvv and EVEX.vvvv are unused, they must be all 1s, which
12060      are all 0s in inverted form.  */
12061   if (need_vex && vex.register_specifier != 0)
12062     {
12063       (*info->fprintf_func) (info->stream, "(bad)");
12064       return end_codep - priv.the_buffer;
12065     }
12066
12067   /* Check if the REX prefix is used.  */
12068   if ((rex ^ rex_used) == 0 && !need_vex && last_rex_prefix >= 0)
12069     all_prefixes[last_rex_prefix] = 0;
12070
12071   /* Check if the SEG prefix is used.  */
12072   if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
12073                    | PREFIX_FS | PREFIX_GS)) != 0
12074       && (used_prefixes & active_seg_prefix) != 0)
12075     all_prefixes[last_seg_prefix] = 0;
12076
12077   /* Check if the ADDR prefix is used.  */
12078   if ((prefixes & PREFIX_ADDR) != 0
12079       && (used_prefixes & PREFIX_ADDR) != 0)
12080     all_prefixes[last_addr_prefix] = 0;
12081
12082   /* Check if the DATA prefix is used.  */
12083   if ((prefixes & PREFIX_DATA) != 0
12084       && (used_prefixes & PREFIX_DATA) != 0
12085       && !need_vex)
12086     all_prefixes[last_data_prefix] = 0;
12087
12088   /* Print the extra prefixes.  */
12089   prefix_length = 0;
12090   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
12091     if (all_prefixes[i])
12092       {
12093         const char *name;
12094         name = prefix_name (all_prefixes[i], orig_sizeflag);
12095         if (name == NULL)
12096           abort ();
12097         prefix_length += strlen (name) + 1;
12098         (*info->fprintf_func) (info->stream, "%s ", name);
12099       }
12100
12101   /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
12102      unused, opcode is invalid.  Since the PREFIX_DATA prefix may be
12103      used by putop and MMX/SSE operand and may be overriden by the
12104      PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
12105      separately.  */
12106   if (dp->prefix_requirement == PREFIX_OPCODE
12107       && (((need_vex
12108             ? vex.prefix == REPE_PREFIX_OPCODE
12109               || vex.prefix == REPNE_PREFIX_OPCODE
12110             : (prefixes
12111                & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
12112            && (used_prefixes
12113                & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
12114           || (((need_vex
12115                 ? vex.prefix == DATA_PREFIX_OPCODE
12116                 : ((prefixes
12117                     & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
12118                    == PREFIX_DATA))
12119                && (used_prefixes & PREFIX_DATA) == 0))
12120           || (vex.evex && !vex.w != !(used_prefixes & PREFIX_DATA))))
12121     {
12122       (*info->fprintf_func) (info->stream, "(bad)");
12123       return end_codep - priv.the_buffer;
12124     }
12125
12126   /* Check maximum code length.  */
12127   if ((codep - start_codep) > MAX_CODE_LENGTH)
12128     {
12129       (*info->fprintf_func) (info->stream, "(bad)");
12130       return MAX_CODE_LENGTH;
12131     }
12132
12133   obufp = mnemonicendp;
12134   for (i = strlen (obuf) + prefix_length; i < 6; i++)
12135     oappend (" ");
12136   oappend (" ");
12137   (*info->fprintf_func) (info->stream, "%s", obuf);
12138
12139   /* The enter and bound instructions are printed with operands in the same
12140      order as the intel book; everything else is printed in reverse order.  */
12141   if (intel_syntax || two_source_ops)
12142     {
12143       bfd_vma riprel;
12144
12145       for (i = 0; i < MAX_OPERANDS; ++i)
12146         op_txt[i] = op_out[i];
12147
12148       if (intel_syntax && dp && dp->op[2].rtn == OP_Rounding
12149           && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL)
12150         {
12151           op_txt[2] = op_out[3];
12152           op_txt[3] = op_out[2];
12153         }
12154
12155       for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
12156         {
12157           op_ad = op_index[i];
12158           op_index[i] = op_index[MAX_OPERANDS - 1 - i];
12159           op_index[MAX_OPERANDS - 1 - i] = op_ad;
12160           riprel = op_riprel[i];
12161           op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
12162           op_riprel[MAX_OPERANDS - 1 - i] = riprel;
12163         }
12164     }
12165   else
12166     {
12167       for (i = 0; i < MAX_OPERANDS; ++i)
12168         op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
12169     }
12170
12171   needcomma = 0;
12172   for (i = 0; i < MAX_OPERANDS; ++i)
12173     if (*op_txt[i])
12174       {
12175         if (needcomma)
12176           (*info->fprintf_func) (info->stream, ",");
12177         if (op_index[i] != -1 && !op_riprel[i])
12178           {
12179             bfd_vma target = (bfd_vma) op_address[op_index[i]];
12180
12181             if (the_info && op_is_jump)
12182               {
12183                 the_info->insn_info_valid = 1;
12184                 the_info->branch_delay_insns = 0;
12185                 the_info->data_size = 0;
12186                 the_info->target = target;
12187                 the_info->target2 = 0;
12188               }
12189             (*info->print_address_func) (target, info);
12190           }
12191         else
12192           (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
12193         needcomma = 1;
12194       }
12195
12196   for (i = 0; i < MAX_OPERANDS; i++)
12197     if (op_index[i] != -1 && op_riprel[i])
12198       {
12199         (*info->fprintf_func) (info->stream, "        # ");
12200         (*info->print_address_func) ((bfd_vma) (start_pc + (codep - start_codep)
12201                                                 + op_address[op_index[i]]), info);
12202         break;
12203       }
12204   return codep - priv.the_buffer;
12205 }
12206
12207 static const char *float_mem[] = {
12208   /* d8 */
12209   "fadd{s|}",
12210   "fmul{s|}",
12211   "fcom{s|}",
12212   "fcomp{s|}",
12213   "fsub{s|}",
12214   "fsubr{s|}",
12215   "fdiv{s|}",
12216   "fdivr{s|}",
12217   /* d9 */
12218   "fld{s|}",
12219   "(bad)",
12220   "fst{s|}",
12221   "fstp{s|}",
12222   "fldenv{C|C}",
12223   "fldcw",
12224   "fNstenv{C|C}",
12225   "fNstcw",
12226   /* da */
12227   "fiadd{l|}",
12228   "fimul{l|}",
12229   "ficom{l|}",
12230   "ficomp{l|}",
12231   "fisub{l|}",
12232   "fisubr{l|}",
12233   "fidiv{l|}",
12234   "fidivr{l|}",
12235   /* db */
12236   "fild{l|}",
12237   "fisttp{l|}",
12238   "fist{l|}",
12239   "fistp{l|}",
12240   "(bad)",
12241   "fld{t|}",
12242   "(bad)",
12243   "fstp{t|}",
12244   /* dc */
12245   "fadd{l|}",
12246   "fmul{l|}",
12247   "fcom{l|}",
12248   "fcomp{l|}",
12249   "fsub{l|}",
12250   "fsubr{l|}",
12251   "fdiv{l|}",
12252   "fdivr{l|}",
12253   /* dd */
12254   "fld{l|}",
12255   "fisttp{ll|}",
12256   "fst{l||}",
12257   "fstp{l|}",
12258   "frstor{C|C}",
12259   "(bad)",
12260   "fNsave{C|C}",
12261   "fNstsw",
12262   /* de */
12263   "fiadd{s|}",
12264   "fimul{s|}",
12265   "ficom{s|}",
12266   "ficomp{s|}",
12267   "fisub{s|}",
12268   "fisubr{s|}",
12269   "fidiv{s|}",
12270   "fidivr{s|}",
12271   /* df */
12272   "fild{s|}",
12273   "fisttp{s|}",
12274   "fist{s|}",
12275   "fistp{s|}",
12276   "fbld",
12277   "fild{ll|}",
12278   "fbstp",
12279   "fistp{ll|}",
12280 };
12281
12282 static const unsigned char float_mem_mode[] = {
12283   /* d8 */
12284   d_mode,
12285   d_mode,
12286   d_mode,
12287   d_mode,
12288   d_mode,
12289   d_mode,
12290   d_mode,
12291   d_mode,
12292   /* d9 */
12293   d_mode,
12294   0,
12295   d_mode,
12296   d_mode,
12297   0,
12298   w_mode,
12299   0,
12300   w_mode,
12301   /* da */
12302   d_mode,
12303   d_mode,
12304   d_mode,
12305   d_mode,
12306   d_mode,
12307   d_mode,
12308   d_mode,
12309   d_mode,
12310   /* db */
12311   d_mode,
12312   d_mode,
12313   d_mode,
12314   d_mode,
12315   0,
12316   t_mode,
12317   0,
12318   t_mode,
12319   /* dc */
12320   q_mode,
12321   q_mode,
12322   q_mode,
12323   q_mode,
12324   q_mode,
12325   q_mode,
12326   q_mode,
12327   q_mode,
12328   /* dd */
12329   q_mode,
12330   q_mode,
12331   q_mode,
12332   q_mode,
12333   0,
12334   0,
12335   0,
12336   w_mode,
12337   /* de */
12338   w_mode,
12339   w_mode,
12340   w_mode,
12341   w_mode,
12342   w_mode,
12343   w_mode,
12344   w_mode,
12345   w_mode,
12346   /* df */
12347   w_mode,
12348   w_mode,
12349   w_mode,
12350   w_mode,
12351   t_mode,
12352   q_mode,
12353   t_mode,
12354   q_mode
12355 };
12356
12357 #define ST { OP_ST, 0 }
12358 #define STi { OP_STi, 0 }
12359
12360 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
12361 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
12362 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
12363 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
12364 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
12365 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
12366 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
12367 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
12368 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
12369
12370 static const struct dis386 float_reg[][8] = {
12371   /* d8 */
12372   {
12373     { "fadd",   { ST, STi }, 0 },
12374     { "fmul",   { ST, STi }, 0 },
12375     { "fcom",   { STi }, 0 },
12376     { "fcomp",  { STi }, 0 },
12377     { "fsub",   { ST, STi }, 0 },
12378     { "fsubr",  { ST, STi }, 0 },
12379     { "fdiv",   { ST, STi }, 0 },
12380     { "fdivr",  { ST, STi }, 0 },
12381   },
12382   /* d9 */
12383   {
12384     { "fld",    { STi }, 0 },
12385     { "fxch",   { STi }, 0 },
12386     { FGRPd9_2 },
12387     { Bad_Opcode },
12388     { FGRPd9_4 },
12389     { FGRPd9_5 },
12390     { FGRPd9_6 },
12391     { FGRPd9_7 },
12392   },
12393   /* da */
12394   {
12395     { "fcmovb", { ST, STi }, 0 },
12396     { "fcmove", { ST, STi }, 0 },
12397     { "fcmovbe",{ ST, STi }, 0 },
12398     { "fcmovu", { ST, STi }, 0 },
12399     { Bad_Opcode },
12400     { FGRPda_5 },
12401     { Bad_Opcode },
12402     { Bad_Opcode },
12403   },
12404   /* db */
12405   {
12406     { "fcmovnb",{ ST, STi }, 0 },
12407     { "fcmovne",{ ST, STi }, 0 },
12408     { "fcmovnbe",{ ST, STi }, 0 },
12409     { "fcmovnu",{ ST, STi }, 0 },
12410     { FGRPdb_4 },
12411     { "fucomi", { ST, STi }, 0 },
12412     { "fcomi",  { ST, STi }, 0 },
12413     { Bad_Opcode },
12414   },
12415   /* dc */
12416   {
12417     { "fadd",   { STi, ST }, 0 },
12418     { "fmul",   { STi, ST }, 0 },
12419     { Bad_Opcode },
12420     { Bad_Opcode },
12421     { "fsub{!M|r}",     { STi, ST }, 0 },
12422     { "fsub{M|}",       { STi, ST }, 0 },
12423     { "fdiv{!M|r}",     { STi, ST }, 0 },
12424     { "fdiv{M|}",       { STi, ST }, 0 },
12425   },
12426   /* dd */
12427   {
12428     { "ffree",  { STi }, 0 },
12429     { Bad_Opcode },
12430     { "fst",    { STi }, 0 },
12431     { "fstp",   { STi }, 0 },
12432     { "fucom",  { STi }, 0 },
12433     { "fucomp", { STi }, 0 },
12434     { Bad_Opcode },
12435     { Bad_Opcode },
12436   },
12437   /* de */
12438   {
12439     { "faddp",  { STi, ST }, 0 },
12440     { "fmulp",  { STi, ST }, 0 },
12441     { Bad_Opcode },
12442     { FGRPde_3 },
12443     { "fsub{!M|r}p",    { STi, ST }, 0 },
12444     { "fsub{M|}p",      { STi, ST }, 0 },
12445     { "fdiv{!M|r}p",    { STi, ST }, 0 },
12446     { "fdiv{M|}p",      { STi, ST }, 0 },
12447   },
12448   /* df */
12449   {
12450     { "ffreep", { STi }, 0 },
12451     { Bad_Opcode },
12452     { Bad_Opcode },
12453     { Bad_Opcode },
12454     { FGRPdf_4 },
12455     { "fucomip", { ST, STi }, 0 },
12456     { "fcomip", { ST, STi }, 0 },
12457     { Bad_Opcode },
12458   },
12459 };
12460
12461 static char *fgrps[][8] = {
12462   /* Bad opcode 0 */
12463   {
12464     "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12465   },
12466
12467   /* d9_2  1 */
12468   {
12469     "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12470   },
12471
12472   /* d9_4  2 */
12473   {
12474     "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
12475   },
12476
12477   /* d9_5  3 */
12478   {
12479     "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
12480   },
12481
12482   /* d9_6  4 */
12483   {
12484     "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
12485   },
12486
12487   /* d9_7  5 */
12488   {
12489     "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
12490   },
12491
12492   /* da_5  6 */
12493   {
12494     "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12495   },
12496
12497   /* db_4  7 */
12498   {
12499     "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
12500     "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
12501   },
12502
12503   /* de_3  8 */
12504   {
12505     "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12506   },
12507
12508   /* df_4  9 */
12509   {
12510     "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12511   },
12512 };
12513
12514 static void
12515 swap_operand (void)
12516 {
12517   mnemonicendp[0] = '.';
12518   mnemonicendp[1] = 's';
12519   mnemonicendp += 2;
12520 }
12521
12522 static void
12523 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
12524                int sizeflag ATTRIBUTE_UNUSED)
12525 {
12526   /* Skip mod/rm byte.  */
12527   MODRM_CHECK;
12528   codep++;
12529 }
12530
12531 static void
12532 dofloat (int sizeflag)
12533 {
12534   const struct dis386 *dp;
12535   unsigned char floatop;
12536
12537   floatop = codep[-1];
12538
12539   if (modrm.mod != 3)
12540     {
12541       int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
12542
12543       putop (float_mem[fp_indx], sizeflag);
12544       obufp = op_out[0];
12545       op_ad = 2;
12546       OP_E (float_mem_mode[fp_indx], sizeflag);
12547       return;
12548     }
12549   /* Skip mod/rm byte.  */
12550   MODRM_CHECK;
12551   codep++;
12552
12553   dp = &float_reg[floatop - 0xd8][modrm.reg];
12554   if (dp->name == NULL)
12555     {
12556       putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
12557
12558       /* Instruction fnstsw is only one with strange arg.  */
12559       if (floatop == 0xdf && codep[-1] == 0xe0)
12560         strcpy (op_out[0], names16[0]);
12561     }
12562   else
12563     {
12564       putop (dp->name, sizeflag);
12565
12566       obufp = op_out[0];
12567       op_ad = 2;
12568       if (dp->op[0].rtn)
12569         (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
12570
12571       obufp = op_out[1];
12572       op_ad = 1;
12573       if (dp->op[1].rtn)
12574         (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
12575     }
12576 }
12577
12578 /* Like oappend (below), but S is a string starting with '%'.
12579    In Intel syntax, the '%' is elided.  */
12580 static void
12581 oappend_maybe_intel (const char *s)
12582 {
12583   oappend (s + intel_syntax);
12584 }
12585
12586 static void
12587 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12588 {
12589   oappend_maybe_intel ("%st");
12590 }
12591
12592 static void
12593 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12594 {
12595   sprintf (scratchbuf, "%%st(%d)", modrm.rm);
12596   oappend_maybe_intel (scratchbuf);
12597 }
12598
12599 /* Capital letters in template are macros.  */
12600 static int
12601 putop (const char *in_template, int sizeflag)
12602 {
12603   const char *p;
12604   int alt = 0;
12605   int cond = 1;
12606   unsigned int l = 0, len = 0;
12607   char last[4];
12608
12609   for (p = in_template; *p; p++)
12610     {
12611       if (len > l)
12612         {
12613           if (l >= sizeof (last) || !ISUPPER (*p))
12614             abort ();
12615           last[l++] = *p;
12616           continue;
12617         }
12618       switch (*p)
12619         {
12620         default:
12621           *obufp++ = *p;
12622           break;
12623         case '%':
12624           len++;
12625           break;
12626         case '!':
12627           cond = 0;
12628           break;
12629         case '{':
12630           if (intel_syntax)
12631             {
12632               while (*++p != '|')
12633                 if (*p == '}' || *p == '\0')
12634                   abort ();
12635               alt = 1;
12636             }
12637           break;
12638         case '|':
12639           while (*++p != '}')
12640             {
12641               if (*p == '\0')
12642                 abort ();
12643             }
12644           break;
12645         case '}':
12646           alt = 0;
12647           break;
12648         case 'A':
12649           if (intel_syntax)
12650             break;
12651           if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
12652             *obufp++ = 'b';
12653           break;
12654         case 'B':
12655           if (l == 0)
12656             {
12657             case_B:
12658               if (intel_syntax)
12659                 break;
12660               if (sizeflag & SUFFIX_ALWAYS)
12661                 *obufp++ = 'b';
12662             }
12663           else if (l == 1 && last[0] == 'L')
12664             {
12665               if (address_mode == mode_64bit
12666                   && !(prefixes & PREFIX_ADDR))
12667                 {
12668                   *obufp++ = 'a';
12669                   *obufp++ = 'b';
12670                   *obufp++ = 's';
12671                 }
12672
12673               goto case_B;
12674             }
12675           else
12676             abort ();
12677           break;
12678         case 'C':
12679           if (intel_syntax && !alt)
12680             break;
12681           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
12682             {
12683               if (sizeflag & DFLAG)
12684                 *obufp++ = intel_syntax ? 'd' : 'l';
12685               else
12686                 *obufp++ = intel_syntax ? 'w' : 's';
12687               used_prefixes |= (prefixes & PREFIX_DATA);
12688             }
12689           break;
12690         case 'D':
12691           if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
12692             break;
12693           USED_REX (REX_W);
12694           if (modrm.mod == 3)
12695             {
12696               if (rex & REX_W)
12697                 *obufp++ = 'q';
12698               else
12699                 {
12700                   if (sizeflag & DFLAG)
12701                     *obufp++ = intel_syntax ? 'd' : 'l';
12702                   else
12703                     *obufp++ = 'w';
12704                   used_prefixes |= (prefixes & PREFIX_DATA);
12705                 }
12706             }
12707           else
12708             *obufp++ = 'w';
12709           break;
12710         case 'E':               /* For jcxz/jecxz */
12711           if (address_mode == mode_64bit)
12712             {
12713               if (sizeflag & AFLAG)
12714                 *obufp++ = 'r';
12715               else
12716                 *obufp++ = 'e';
12717             }
12718           else
12719             if (sizeflag & AFLAG)
12720               *obufp++ = 'e';
12721           used_prefixes |= (prefixes & PREFIX_ADDR);
12722           break;
12723         case 'F':
12724           if (intel_syntax)
12725             break;
12726           if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
12727             {
12728               if (sizeflag & AFLAG)
12729                 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
12730               else
12731                 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
12732               used_prefixes |= (prefixes & PREFIX_ADDR);
12733             }
12734           break;
12735         case 'G':
12736           if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
12737             break;
12738           if ((rex & REX_W) || (sizeflag & DFLAG))
12739             *obufp++ = 'l';
12740           else
12741             *obufp++ = 'w';
12742           if (!(rex & REX_W))
12743             used_prefixes |= (prefixes & PREFIX_DATA);
12744           break;
12745         case 'H':
12746           if (intel_syntax)
12747             break;
12748           if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
12749               || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
12750             {
12751               used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
12752               *obufp++ = ',';
12753               *obufp++ = 'p';
12754               if (prefixes & PREFIX_DS)
12755                 *obufp++ = 't';
12756               else
12757                 *obufp++ = 'n';
12758             }
12759           break;
12760         case 'K':
12761           USED_REX (REX_W);
12762           if (rex & REX_W)
12763             *obufp++ = 'q';
12764           else
12765             *obufp++ = 'd';
12766           break;
12767         case 'Z':
12768           if (l != 0)
12769             {
12770               if (l != 1 || last[0] != 'X')
12771                 abort ();
12772               if (!need_vex || !vex.evex)
12773                 abort ();
12774               if (intel_syntax
12775                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
12776                 break;
12777               switch (vex.length)
12778                 {
12779                 case 128:
12780                   *obufp++ = 'x';
12781                   break;
12782                 case 256:
12783                   *obufp++ = 'y';
12784                   break;
12785                 case 512:
12786                   *obufp++ = 'z';
12787                   break;
12788                 default:
12789                   abort ();
12790                 }
12791               break;
12792             }
12793           if (intel_syntax)
12794             break;
12795           if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
12796             {
12797               *obufp++ = 'q';
12798               break;
12799             }
12800           /* Fall through.  */
12801           goto case_L;
12802         case 'L':
12803           if (l != 0)
12804             abort ();
12805         case_L:
12806           if (intel_syntax)
12807             break;
12808           if (sizeflag & SUFFIX_ALWAYS)
12809             *obufp++ = 'l';
12810           break;
12811         case 'M':
12812           if (intel_mnemonic != cond)
12813             *obufp++ = 'r';
12814           break;
12815         case 'N':
12816           if ((prefixes & PREFIX_FWAIT) == 0)
12817             *obufp++ = 'n';
12818           else
12819             used_prefixes |= PREFIX_FWAIT;
12820           break;
12821         case 'O':
12822           USED_REX (REX_W);
12823           if (rex & REX_W)
12824             *obufp++ = 'o';
12825           else if (intel_syntax && (sizeflag & DFLAG))
12826             *obufp++ = 'q';
12827           else
12828             *obufp++ = 'd';
12829           if (!(rex & REX_W))
12830             used_prefixes |= (prefixes & PREFIX_DATA);
12831           break;
12832         case '&':
12833           if (!intel_syntax
12834               && address_mode == mode_64bit
12835               && isa64 == intel64)
12836             {
12837               *obufp++ = 'q';
12838               break;
12839             }
12840           /* Fall through.  */
12841         case 'T':
12842           if (!intel_syntax
12843               && address_mode == mode_64bit
12844               && ((sizeflag & DFLAG) || (rex & REX_W)))
12845             {
12846               *obufp++ = 'q';
12847               break;
12848             }
12849           /* Fall through.  */
12850           goto case_P;
12851         case 'P':
12852           if (l == 0)
12853             {
12854             case_P:
12855               if (intel_syntax)
12856                 {
12857                   if ((rex & REX_W) == 0
12858                       && (prefixes & PREFIX_DATA))
12859                     {
12860                       if ((sizeflag & DFLAG) == 0)
12861                         *obufp++ = 'w';
12862                       used_prefixes |= (prefixes & PREFIX_DATA);
12863                     }
12864                   break;
12865                 }
12866               if ((prefixes & PREFIX_DATA)
12867                   || (rex & REX_W)
12868                   || (sizeflag & SUFFIX_ALWAYS))
12869                 {
12870                   USED_REX (REX_W);
12871                   if (rex & REX_W)
12872                     *obufp++ = 'q';
12873                   else
12874                     {
12875                       if (sizeflag & DFLAG)
12876                         *obufp++ = 'l';
12877                       else
12878                         *obufp++ = 'w';
12879                       used_prefixes |= (prefixes & PREFIX_DATA);
12880                     }
12881                 }
12882             }
12883           else if (l == 1 && last[0] == 'L')
12884             {
12885               if ((prefixes & PREFIX_DATA)
12886                   || (rex & REX_W)
12887                   || (sizeflag & SUFFIX_ALWAYS))
12888                 {
12889                   USED_REX (REX_W);
12890                   if (rex & REX_W)
12891                     *obufp++ = 'q';
12892                   else
12893                     {
12894                       if (sizeflag & DFLAG)
12895                         *obufp++ = intel_syntax ? 'd' : 'l';
12896                       else
12897                         *obufp++ = 'w';
12898                       used_prefixes |= (prefixes & PREFIX_DATA);
12899                     }
12900                 }
12901             }
12902           else
12903             abort ();
12904           break;
12905         case 'U':
12906           if (intel_syntax)
12907             break;
12908           if (address_mode == mode_64bit
12909               && ((sizeflag & DFLAG) || (rex & REX_W)))
12910             {
12911               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
12912                 *obufp++ = 'q';
12913               break;
12914             }
12915           /* Fall through.  */
12916           goto case_Q;
12917         case 'Q':
12918           if (l == 0)
12919             {
12920             case_Q:
12921               if (intel_syntax && !alt)
12922                 break;
12923               USED_REX (REX_W);
12924               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
12925                 {
12926                   if (rex & REX_W)
12927                     *obufp++ = 'q';
12928                   else
12929                     {
12930                       if (sizeflag & DFLAG)
12931                         *obufp++ = intel_syntax ? 'd' : 'l';
12932                       else
12933                         *obufp++ = 'w';
12934                       used_prefixes |= (prefixes & PREFIX_DATA);
12935                     }
12936                 }
12937             }
12938           else if (l == 1 && last[0] == 'L')
12939             {
12940               if ((intel_syntax && need_modrm)
12941                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
12942                 break;
12943               if ((rex & REX_W))
12944                 {
12945                   USED_REX (REX_W);
12946                   *obufp++ = 'q';
12947                 }
12948               else if((address_mode == mode_64bit && need_modrm)
12949                       || (sizeflag & SUFFIX_ALWAYS))
12950                 *obufp++ = intel_syntax? 'd' : 'l';
12951             }
12952           else
12953             abort ();
12954           break;
12955         case 'R':
12956           USED_REX (REX_W);
12957           if (rex & REX_W)
12958             *obufp++ = 'q';
12959           else if (sizeflag & DFLAG)
12960             {
12961               if (intel_syntax)
12962                   *obufp++ = 'd';
12963               else
12964                   *obufp++ = 'l';
12965             }
12966           else
12967             *obufp++ = 'w';
12968           if (intel_syntax && !p[1]
12969               && ((rex & REX_W) || (sizeflag & DFLAG)))
12970             *obufp++ = 'e';
12971           if (!(rex & REX_W))
12972             used_prefixes |= (prefixes & PREFIX_DATA);
12973           break;
12974         case 'V':
12975           if (l == 0)
12976             {
12977               if (intel_syntax)
12978                 break;
12979               if (address_mode == mode_64bit
12980                   && ((sizeflag & DFLAG) || (rex & REX_W)))
12981                 {
12982                   if (sizeflag & SUFFIX_ALWAYS)
12983                     *obufp++ = 'q';
12984                   break;
12985                 }
12986             }
12987           else if (l == 1 && last[0] == 'L')
12988             {
12989               if (rex & REX_W)
12990                 {
12991                   *obufp++ = 'a';
12992                   *obufp++ = 'b';
12993                   *obufp++ = 's';
12994                 }
12995             }
12996           else
12997             abort ();
12998           /* Fall through.  */
12999           goto case_S;
13000         case 'S':
13001           if (l == 0)
13002             {
13003             case_S:
13004               if (intel_syntax)
13005                 break;
13006               if (sizeflag & SUFFIX_ALWAYS)
13007                 {
13008                   if (rex & REX_W)
13009                     *obufp++ = 'q';
13010                   else
13011                     {
13012                       if (sizeflag & DFLAG)
13013                         *obufp++ = 'l';
13014                       else
13015                         *obufp++ = 'w';
13016                       used_prefixes |= (prefixes & PREFIX_DATA);
13017                     }
13018                 }
13019             }
13020           else if (l == 1 && last[0] == 'L')
13021             {
13022               if (address_mode == mode_64bit
13023                   && !(prefixes & PREFIX_ADDR))
13024                 {
13025                   *obufp++ = 'a';
13026                   *obufp++ = 'b';
13027                   *obufp++ = 's';
13028                 }
13029
13030               goto case_S;
13031             }
13032           else
13033             abort ();
13034           break;
13035         case 'X':
13036           if (l != 0)
13037             abort ();
13038           if (need_vex
13039               ? vex.prefix == DATA_PREFIX_OPCODE
13040               : prefixes & PREFIX_DATA)
13041             {
13042               *obufp++ = 'd';
13043               used_prefixes |= PREFIX_DATA;
13044             }
13045           else
13046             *obufp++ = 's';
13047           break;
13048         case 'Y':
13049           if (l == 1 && last[0] == 'X')
13050             {
13051               if (!need_vex)
13052                 abort ();
13053               if (intel_syntax
13054                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
13055                 break;
13056               switch (vex.length)
13057                 {
13058                 case 128:
13059                   *obufp++ = 'x';
13060                   break;
13061                 case 256:
13062                   *obufp++ = 'y';
13063                   break;
13064                 case 512:
13065                   if (!vex.evex)
13066                 default:
13067                     abort ();
13068                 }
13069             }
13070           else
13071             abort ();
13072           break;
13073         case 'W':
13074           if (l == 0)
13075             {
13076               /* operand size flag for cwtl, cbtw */
13077               USED_REX (REX_W);
13078               if (rex & REX_W)
13079                 {
13080                   if (intel_syntax)
13081                     *obufp++ = 'd';
13082                   else
13083                     *obufp++ = 'l';
13084                 }
13085               else if (sizeflag & DFLAG)
13086                 *obufp++ = 'w';
13087               else
13088                 *obufp++ = 'b';
13089               if (!(rex & REX_W))
13090                 used_prefixes |= (prefixes & PREFIX_DATA);
13091             }
13092           else if (l == 1)
13093             {
13094               if (!need_vex)
13095                 abort ();
13096               if (last[0] == 'X')
13097                 *obufp++ = vex.w ? 'd': 's';
13098               else if (last[0] == 'L')
13099                 *obufp++ = vex.w ? 'q': 'd';
13100               else if (last[0] == 'B')
13101                 *obufp++ = vex.w ? 'w': 'b';
13102               else
13103                 abort ();
13104             }
13105           else
13106             abort ();
13107           break;
13108         case '^':
13109           if (intel_syntax)
13110             break;
13111           if (isa64 == intel64 && (rex & REX_W))
13112             {
13113               USED_REX (REX_W);
13114               *obufp++ = 'q';
13115               break;
13116             }
13117           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
13118             {
13119               if (sizeflag & DFLAG)
13120                 *obufp++ = 'l';
13121               else
13122                 *obufp++ = 'w';
13123               used_prefixes |= (prefixes & PREFIX_DATA);
13124             }
13125           break;
13126         case '@':
13127           if (intel_syntax)
13128             break;
13129           if (address_mode == mode_64bit
13130               && (isa64 == intel64
13131                   || ((sizeflag & DFLAG) || (rex & REX_W))))
13132               *obufp++ = 'q';
13133           else if ((prefixes & PREFIX_DATA))
13134             {
13135               if (!(sizeflag & DFLAG))
13136                 *obufp++ = 'w';
13137               used_prefixes |= (prefixes & PREFIX_DATA);
13138             }
13139           break;
13140         }
13141
13142       if (len == l)
13143         len = l = 0;
13144     }
13145   *obufp = 0;
13146   mnemonicendp = obufp;
13147   return 0;
13148 }
13149
13150 static void
13151 oappend (const char *s)
13152 {
13153   obufp = stpcpy (obufp, s);
13154 }
13155
13156 static void
13157 append_seg (void)
13158 {
13159   /* Only print the active segment register.  */
13160   if (!active_seg_prefix)
13161     return;
13162
13163   used_prefixes |= active_seg_prefix;
13164   switch (active_seg_prefix)
13165     {
13166     case PREFIX_CS:
13167       oappend_maybe_intel ("%cs:");
13168       break;
13169     case PREFIX_DS:
13170       oappend_maybe_intel ("%ds:");
13171       break;
13172     case PREFIX_SS:
13173       oappend_maybe_intel ("%ss:");
13174       break;
13175     case PREFIX_ES:
13176       oappend_maybe_intel ("%es:");
13177       break;
13178     case PREFIX_FS:
13179       oappend_maybe_intel ("%fs:");
13180       break;
13181     case PREFIX_GS:
13182       oappend_maybe_intel ("%gs:");
13183       break;
13184     default:
13185       break;
13186     }
13187 }
13188
13189 static void
13190 OP_indirE (int bytemode, int sizeflag)
13191 {
13192   if (!intel_syntax)
13193     oappend ("*");
13194   OP_E (bytemode, sizeflag);
13195 }
13196
13197 static void
13198 print_operand_value (char *buf, int hex, bfd_vma disp)
13199 {
13200   if (address_mode == mode_64bit)
13201     {
13202       if (hex)
13203         {
13204           char tmp[30];
13205           int i;
13206           buf[0] = '0';
13207           buf[1] = 'x';
13208           sprintf_vma (tmp, disp);
13209           for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
13210           strcpy (buf + 2, tmp + i);
13211         }
13212       else
13213         {
13214           bfd_signed_vma v = disp;
13215           char tmp[30];
13216           int i;
13217           if (v < 0)
13218             {
13219               *(buf++) = '-';
13220               v = -disp;
13221               /* Check for possible overflow on 0x8000000000000000.  */
13222               if (v < 0)
13223                 {
13224                   strcpy (buf, "9223372036854775808");
13225                   return;
13226                 }
13227             }
13228           if (!v)
13229             {
13230               strcpy (buf, "0");
13231               return;
13232             }
13233
13234           i = 0;
13235           tmp[29] = 0;
13236           while (v)
13237             {
13238               tmp[28 - i] = (v % 10) + '0';
13239               v /= 10;
13240               i++;
13241             }
13242           strcpy (buf, tmp + 29 - i);
13243         }
13244     }
13245   else
13246     {
13247       if (hex)
13248         sprintf (buf, "0x%x", (unsigned int) disp);
13249       else
13250         sprintf (buf, "%d", (int) disp);
13251     }
13252 }
13253
13254 /* Put DISP in BUF as signed hex number.  */
13255
13256 static void
13257 print_displacement (char *buf, bfd_vma disp)
13258 {
13259   bfd_signed_vma val = disp;
13260   char tmp[30];
13261   int i, j = 0;
13262
13263   if (val < 0)
13264     {
13265       buf[j++] = '-';
13266       val = -disp;
13267
13268       /* Check for possible overflow.  */
13269       if (val < 0)
13270         {
13271           switch (address_mode)
13272             {
13273             case mode_64bit:
13274               strcpy (buf + j, "0x8000000000000000");
13275               break;
13276             case mode_32bit:
13277               strcpy (buf + j, "0x80000000");
13278               break;
13279             case mode_16bit:
13280               strcpy (buf + j, "0x8000");
13281               break;
13282             }
13283           return;
13284         }
13285     }
13286
13287   buf[j++] = '0';
13288   buf[j++] = 'x';
13289
13290   sprintf_vma (tmp, (bfd_vma) val);
13291   for (i = 0; tmp[i] == '0'; i++)
13292     continue;
13293   if (tmp[i] == '\0')
13294     i--;
13295   strcpy (buf + j, tmp + i);
13296 }
13297
13298 static void
13299 intel_operand_size (int bytemode, int sizeflag)
13300 {
13301   if (vex.evex
13302       && vex.b
13303       && (bytemode == x_mode
13304           || bytemode == evex_half_bcst_xmmq_mode))
13305     {
13306       if (vex.w)
13307         oappend ("QWORD PTR ");
13308       else
13309         oappend ("DWORD PTR ");
13310       return;
13311     }
13312   switch (bytemode)
13313     {
13314     case b_mode:
13315     case b_swap_mode:
13316     case dqb_mode:
13317     case db_mode:
13318       oappend ("BYTE PTR ");
13319       break;
13320     case w_mode:
13321     case dw_mode:
13322     case dqw_mode:
13323       oappend ("WORD PTR ");
13324       break;
13325     case indir_v_mode:
13326       if (address_mode == mode_64bit && isa64 == intel64)
13327         {
13328           oappend ("QWORD PTR ");
13329           break;
13330         }
13331       /* Fall through.  */
13332     case stack_v_mode:
13333       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
13334         {
13335           oappend ("QWORD PTR ");
13336           break;
13337         }
13338       /* Fall through.  */
13339     case v_mode:
13340     case v_swap_mode:
13341     case dq_mode:
13342       USED_REX (REX_W);
13343       if (rex & REX_W)
13344         oappend ("QWORD PTR ");
13345       else
13346         {
13347           if ((sizeflag & DFLAG) || bytemode == dq_mode)
13348             oappend ("DWORD PTR ");
13349           else
13350             oappend ("WORD PTR ");
13351           used_prefixes |= (prefixes & PREFIX_DATA);
13352         }
13353       break;
13354     case z_mode:
13355       if ((rex & REX_W) || (sizeflag & DFLAG))
13356         *obufp++ = 'D';
13357       oappend ("WORD PTR ");
13358       if (!(rex & REX_W))
13359         used_prefixes |= (prefixes & PREFIX_DATA);
13360       break;
13361     case a_mode:
13362       if (sizeflag & DFLAG)
13363         oappend ("QWORD PTR ");
13364       else
13365         oappend ("DWORD PTR ");
13366       used_prefixes |= (prefixes & PREFIX_DATA);
13367       break;
13368     case movsxd_mode:
13369       if (!(sizeflag & DFLAG) && isa64 == intel64)
13370         oappend ("WORD PTR ");
13371       else
13372         oappend ("DWORD PTR ");
13373       used_prefixes |= (prefixes & PREFIX_DATA);
13374       break;
13375     case d_mode:
13376     case d_scalar_swap_mode:
13377     case d_swap_mode:
13378     case dqd_mode:
13379       oappend ("DWORD PTR ");
13380       break;
13381     case q_mode:
13382     case q_scalar_swap_mode:
13383     case q_swap_mode:
13384       oappend ("QWORD PTR ");
13385       break;
13386     case m_mode:
13387       if (address_mode == mode_64bit)
13388         oappend ("QWORD PTR ");
13389       else
13390         oappend ("DWORD PTR ");
13391       break;
13392     case f_mode:
13393       if (sizeflag & DFLAG)
13394         oappend ("FWORD PTR ");
13395       else
13396         oappend ("DWORD PTR ");
13397       used_prefixes |= (prefixes & PREFIX_DATA);
13398       break;
13399     case t_mode:
13400       oappend ("TBYTE PTR ");
13401       break;
13402     case x_mode:
13403     case x_swap_mode:
13404     case evex_x_gscat_mode:
13405     case evex_x_nobcst_mode:
13406     case b_scalar_mode:
13407     case w_scalar_mode:
13408       if (need_vex)
13409         {
13410           switch (vex.length)
13411             {
13412             case 128:
13413               oappend ("XMMWORD PTR ");
13414               break;
13415             case 256:
13416               oappend ("YMMWORD PTR ");
13417               break;
13418             case 512:
13419               oappend ("ZMMWORD PTR ");
13420               break;
13421             default:
13422               abort ();
13423             }
13424         }
13425       else
13426         oappend ("XMMWORD PTR ");
13427       break;
13428     case xmm_mode:
13429       oappend ("XMMWORD PTR ");
13430       break;
13431     case ymm_mode:
13432       oappend ("YMMWORD PTR ");
13433       break;
13434     case xmmq_mode:
13435     case evex_half_bcst_xmmq_mode:
13436       if (!need_vex)
13437         abort ();
13438
13439       switch (vex.length)
13440         {
13441         case 128:
13442           oappend ("QWORD PTR ");
13443           break;
13444         case 256:
13445           oappend ("XMMWORD PTR ");
13446           break;
13447         case 512:
13448           oappend ("YMMWORD PTR ");
13449           break;
13450         default:
13451           abort ();
13452         }
13453       break;
13454     case xmm_mb_mode:
13455       if (!need_vex)
13456         abort ();
13457
13458       switch (vex.length)
13459         {
13460         case 128:
13461         case 256:
13462         case 512:
13463           oappend ("BYTE PTR ");
13464           break;
13465         default:
13466           abort ();
13467         }
13468       break;
13469     case xmm_mw_mode:
13470       if (!need_vex)
13471         abort ();
13472
13473       switch (vex.length)
13474         {
13475         case 128:
13476         case 256:
13477         case 512:
13478           oappend ("WORD PTR ");
13479           break;
13480         default:
13481           abort ();
13482         }
13483       break;
13484     case xmm_md_mode:
13485       if (!need_vex)
13486         abort ();
13487
13488       switch (vex.length)
13489         {
13490         case 128:
13491         case 256:
13492         case 512:
13493           oappend ("DWORD PTR ");
13494           break;
13495         default:
13496           abort ();
13497         }
13498       break;
13499     case xmm_mq_mode:
13500       if (!need_vex)
13501         abort ();
13502
13503       switch (vex.length)
13504         {
13505         case 128:
13506         case 256:
13507         case 512:
13508           oappend ("QWORD PTR ");
13509           break;
13510         default:
13511           abort ();
13512         }
13513       break;
13514     case xmmdw_mode:
13515       if (!need_vex)
13516         abort ();
13517
13518       switch (vex.length)
13519         {
13520         case 128:
13521           oappend ("WORD PTR ");
13522           break;
13523         case 256:
13524           oappend ("DWORD PTR ");
13525           break;
13526         case 512:
13527           oappend ("QWORD PTR ");
13528           break;
13529         default:
13530           abort ();
13531         }
13532       break;
13533     case xmmqd_mode:
13534       if (!need_vex)
13535         abort ();
13536
13537       switch (vex.length)
13538         {
13539         case 128:
13540           oappend ("DWORD PTR ");
13541           break;
13542         case 256:
13543           oappend ("QWORD PTR ");
13544           break;
13545         case 512:
13546           oappend ("XMMWORD PTR ");
13547           break;
13548         default:
13549           abort ();
13550         }
13551       break;
13552     case ymmq_mode:
13553       if (!need_vex)
13554         abort ();
13555
13556       switch (vex.length)
13557         {
13558         case 128:
13559           oappend ("QWORD PTR ");
13560           break;
13561         case 256:
13562           oappend ("YMMWORD PTR ");
13563           break;
13564         case 512:
13565           oappend ("ZMMWORD PTR ");
13566           break;
13567         default:
13568           abort ();
13569         }
13570       break;
13571     case ymmxmm_mode:
13572       if (!need_vex)
13573         abort ();
13574
13575       switch (vex.length)
13576         {
13577         case 128:
13578         case 256:
13579           oappend ("XMMWORD PTR ");
13580           break;
13581         default:
13582           abort ();
13583         }
13584       break;
13585     case o_mode:
13586       oappend ("OWORD PTR ");
13587       break;
13588     case vex_scalar_w_dq_mode:
13589       if (!need_vex)
13590         abort ();
13591
13592       if (vex.w)
13593         oappend ("QWORD PTR ");
13594       else
13595         oappend ("DWORD PTR ");
13596       break;
13597     case vex_vsib_d_w_dq_mode:
13598     case vex_vsib_q_w_dq_mode:
13599       if (!need_vex)
13600         abort ();
13601
13602       if (!vex.evex)
13603         {
13604           if (vex.w)
13605             oappend ("QWORD PTR ");
13606           else
13607             oappend ("DWORD PTR ");
13608         }
13609       else
13610         {
13611           switch (vex.length)
13612             {
13613             case 128:
13614               oappend ("XMMWORD PTR ");
13615               break;
13616             case 256:
13617               oappend ("YMMWORD PTR ");
13618               break;
13619             case 512:
13620               oappend ("ZMMWORD PTR ");
13621               break;
13622             default:
13623               abort ();
13624             }
13625         }
13626       break;
13627     case vex_vsib_q_w_d_mode:
13628     case vex_vsib_d_w_d_mode:
13629       if (!need_vex || !vex.evex)
13630         abort ();
13631
13632       switch (vex.length)
13633         {
13634         case 128:
13635           oappend ("QWORD PTR ");
13636           break;
13637         case 256:
13638           oappend ("XMMWORD PTR ");
13639           break;
13640         case 512:
13641           oappend ("YMMWORD PTR ");
13642           break;
13643         default:
13644           abort ();
13645         }
13646
13647       break;
13648     case mask_bd_mode:
13649       if (!need_vex || vex.length != 128)
13650         abort ();
13651       if (vex.w)
13652         oappend ("DWORD PTR ");
13653       else
13654         oappend ("BYTE PTR ");
13655       break;
13656     case mask_mode:
13657       if (!need_vex)
13658         abort ();
13659       if (vex.w)
13660         oappend ("QWORD PTR ");
13661       else
13662         oappend ("WORD PTR ");
13663       break;
13664     case v_bnd_mode:
13665     case v_bndmk_mode:
13666     default:
13667       break;
13668     }
13669 }
13670
13671 static void
13672 OP_E_register (int bytemode, int sizeflag)
13673 {
13674   int reg = modrm.rm;
13675   const char **names;
13676
13677   USED_REX (REX_B);
13678   if ((rex & REX_B))
13679     reg += 8;
13680
13681   if ((sizeflag & SUFFIX_ALWAYS)
13682       && (bytemode == b_swap_mode
13683           || bytemode == bnd_swap_mode
13684           || bytemode == v_swap_mode))
13685     swap_operand ();
13686
13687   switch (bytemode)
13688     {
13689     case b_mode:
13690     case b_swap_mode:
13691       USED_REX (0);
13692       if (rex)
13693         names = names8rex;
13694       else
13695         names = names8;
13696       break;
13697     case w_mode:
13698       names = names16;
13699       break;
13700     case d_mode:
13701     case dw_mode:
13702     case db_mode:
13703       names = names32;
13704       break;
13705     case q_mode:
13706       names = names64;
13707       break;
13708     case m_mode:
13709     case v_bnd_mode:
13710       names = address_mode == mode_64bit ? names64 : names32;
13711       break;
13712     case bnd_mode:
13713     case bnd_swap_mode:
13714       if (reg > 0x3)
13715         {
13716           oappend ("(bad)");
13717           return;
13718         }
13719       names = names_bnd;
13720       break;
13721     case indir_v_mode:
13722       if (address_mode == mode_64bit && isa64 == intel64)
13723         {
13724           names = names64;
13725           break;
13726         }
13727       /* Fall through.  */
13728     case stack_v_mode:
13729       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
13730         {
13731           names = names64;
13732           break;
13733         }
13734       bytemode = v_mode;
13735       /* Fall through.  */
13736     case v_mode:
13737     case v_swap_mode:
13738     case dq_mode:
13739     case dqb_mode:
13740     case dqd_mode:
13741     case dqw_mode:
13742       USED_REX (REX_W);
13743       if (rex & REX_W)
13744         names = names64;
13745       else
13746         {
13747           if ((sizeflag & DFLAG)
13748               || (bytemode != v_mode
13749                   && bytemode != v_swap_mode))
13750             names = names32;
13751           else
13752             names = names16;
13753           used_prefixes |= (prefixes & PREFIX_DATA);
13754         }
13755       break;
13756     case movsxd_mode:
13757       if (!(sizeflag & DFLAG) && isa64 == intel64)
13758         names = names16;
13759       else
13760         names = names32;
13761       used_prefixes |= (prefixes & PREFIX_DATA);
13762       break;
13763     case va_mode:
13764       names = (address_mode == mode_64bit
13765                ? names64 : names32);
13766       if (!(prefixes & PREFIX_ADDR))
13767         names = (address_mode == mode_16bit
13768                      ? names16 : names);
13769       else
13770         {
13771           /* Remove "addr16/addr32".  */
13772           all_prefixes[last_addr_prefix] = 0;
13773           names = (address_mode != mode_32bit
13774                        ? names32 : names16);
13775           used_prefixes |= PREFIX_ADDR;
13776         }
13777       break;
13778     case mask_bd_mode:
13779     case mask_mode:
13780       if (reg > 0x7)
13781         {
13782           oappend ("(bad)");
13783           return;
13784         }
13785       names = names_mask;
13786       break;
13787     case 0:
13788       return;
13789     default:
13790       oappend (INTERNAL_DISASSEMBLER_ERROR);
13791       return;
13792     }
13793   oappend (names[reg]);
13794 }
13795
13796 static void
13797 OP_E_memory (int bytemode, int sizeflag)
13798 {
13799   bfd_vma disp = 0;
13800   int add = (rex & REX_B) ? 8 : 0;
13801   int riprel = 0;
13802   int shift;
13803
13804   if (vex.evex)
13805     {
13806       /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0.  */
13807       if (vex.b
13808           && bytemode != x_mode
13809           && bytemode != xmmq_mode
13810           && bytemode != evex_half_bcst_xmmq_mode)
13811         {
13812           BadOp ();
13813           return;
13814         }
13815       switch (bytemode)
13816         {
13817         case dqw_mode:
13818         case dw_mode:
13819           shift = 1;
13820           break;
13821         case dqb_mode:
13822         case db_mode:
13823           shift = 0;
13824           break;
13825         case dq_mode:
13826           if (address_mode != mode_64bit)
13827             {
13828               shift = 2;
13829               break;
13830             }
13831             /* fall through */
13832         case vex_scalar_w_dq_mode:
13833         case vex_vsib_d_w_dq_mode:
13834         case vex_vsib_d_w_d_mode:
13835         case vex_vsib_q_w_dq_mode:
13836         case vex_vsib_q_w_d_mode:
13837         case evex_x_gscat_mode:
13838           shift = vex.w ? 3 : 2;
13839           break;
13840         case x_mode:
13841         case evex_half_bcst_xmmq_mode:
13842         case xmmq_mode:
13843           if (vex.b)
13844             {
13845               shift = vex.w ? 3 : 2;
13846               break;
13847             }
13848           /* Fall through.  */
13849         case xmmqd_mode:
13850         case xmmdw_mode:
13851         case ymmq_mode:
13852         case evex_x_nobcst_mode:
13853         case x_swap_mode:
13854           switch (vex.length)
13855             {
13856             case 128:
13857               shift = 4;
13858               break;
13859             case 256:
13860               shift = 5;
13861               break;
13862             case 512:
13863               shift = 6;
13864               break;
13865             default:
13866               abort ();
13867             }
13868           break;
13869         case ymm_mode:
13870           shift = 5;
13871           break;
13872         case xmm_mode:
13873           shift = 4;
13874           break;
13875         case xmm_mq_mode:
13876         case q_mode:
13877         case q_swap_mode:
13878         case q_scalar_swap_mode:
13879           shift = 3;
13880           break;
13881         case dqd_mode:
13882         case xmm_md_mode:
13883         case d_mode:
13884         case d_swap_mode:
13885         case d_scalar_swap_mode:
13886           shift = 2;
13887           break;
13888         case w_scalar_mode:
13889         case xmm_mw_mode:
13890           shift = 1;
13891           break;
13892         case b_scalar_mode:
13893         case xmm_mb_mode:
13894           shift = 0;
13895           break;
13896         default:
13897           abort ();
13898         }
13899       /* Make necessary corrections to shift for modes that need it.
13900          For these modes we currently have shift 4, 5 or 6 depending on
13901          vex.length (it corresponds to xmmword, ymmword or zmmword
13902          operand).  We might want to make it 3, 4 or 5 (e.g. for
13903          xmmq_mode).  In case of broadcast enabled the corrections
13904          aren't needed, as element size is always 32 or 64 bits.  */
13905       if (!vex.b
13906           && (bytemode == xmmq_mode
13907               || bytemode == evex_half_bcst_xmmq_mode))
13908         shift -= 1;
13909       else if (bytemode == xmmqd_mode)
13910         shift -= 2;
13911       else if (bytemode == xmmdw_mode)
13912         shift -= 3;
13913       else if (bytemode == ymmq_mode && vex.length == 128)
13914         shift -= 1;
13915     }
13916   else
13917     shift = 0;
13918
13919   USED_REX (REX_B);
13920   if (intel_syntax)
13921     intel_operand_size (bytemode, sizeflag);
13922   append_seg ();
13923
13924   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
13925     {
13926       /* 32/64 bit address mode */
13927       int havedisp;
13928       int havesib;
13929       int havebase;
13930       int haveindex;
13931       int needindex;
13932       int needaddr32;
13933       int base, rbase;
13934       int vindex = 0;
13935       int scale = 0;
13936       int addr32flag = !((sizeflag & AFLAG)
13937                          || bytemode == v_bnd_mode
13938                          || bytemode == v_bndmk_mode
13939                          || bytemode == bnd_mode
13940                          || bytemode == bnd_swap_mode);
13941       const char **indexes64 = names64;
13942       const char **indexes32 = names32;
13943
13944       havesib = 0;
13945       havebase = 1;
13946       haveindex = 0;
13947       base = modrm.rm;
13948
13949       if (base == 4)
13950         {
13951           havesib = 1;
13952           vindex = sib.index;
13953           USED_REX (REX_X);
13954           if (rex & REX_X)
13955             vindex += 8;
13956           switch (bytemode)
13957             {
13958             case vex_vsib_d_w_dq_mode:
13959             case vex_vsib_d_w_d_mode:
13960             case vex_vsib_q_w_dq_mode:
13961             case vex_vsib_q_w_d_mode:
13962               if (!need_vex)
13963                 abort ();
13964               if (vex.evex)
13965                 {
13966                   if (!vex.v)
13967                     vindex += 16;
13968                 }
13969
13970               haveindex = 1;
13971               switch (vex.length)
13972                 {
13973                 case 128:
13974                   indexes64 = indexes32 = names_xmm;
13975                   break;
13976                 case 256:
13977                   if (!vex.w
13978                       || bytemode == vex_vsib_q_w_dq_mode
13979                       || bytemode == vex_vsib_q_w_d_mode)
13980                     indexes64 = indexes32 = names_ymm;
13981                   else
13982                     indexes64 = indexes32 = names_xmm;
13983                   break;
13984                 case 512:
13985                   if (!vex.w
13986                       || bytemode == vex_vsib_q_w_dq_mode
13987                       || bytemode == vex_vsib_q_w_d_mode)
13988                     indexes64 = indexes32 = names_zmm;
13989                   else
13990                     indexes64 = indexes32 = names_ymm;
13991                   break;
13992                 default:
13993                   abort ();
13994                 }
13995               break;
13996             default:
13997               haveindex = vindex != 4;
13998               break;
13999             }
14000           scale = sib.scale;
14001           base = sib.base;
14002           codep++;
14003         }
14004       rbase = base + add;
14005
14006       switch (modrm.mod)
14007         {
14008         case 0:
14009           if (base == 5)
14010             {
14011               havebase = 0;
14012               if (address_mode == mode_64bit && !havesib)
14013                 riprel = 1;
14014               disp = get32s ();
14015               if (riprel && bytemode == v_bndmk_mode)
14016                 {
14017                   oappend ("(bad)");
14018                   return;
14019                 }
14020             }
14021           break;
14022         case 1:
14023           FETCH_DATA (the_info, codep + 1);
14024           disp = *codep++;
14025           if ((disp & 0x80) != 0)
14026             disp -= 0x100;
14027           if (vex.evex && shift > 0)
14028             disp <<= shift;
14029           break;
14030         case 2:
14031           disp = get32s ();
14032           break;
14033         }
14034
14035       needindex = 0;
14036       needaddr32 = 0;
14037       if (havesib
14038           && !havebase
14039           && !haveindex
14040           && address_mode != mode_16bit)
14041         {
14042           if (address_mode == mode_64bit)
14043             {
14044               /* Display eiz instead of addr32.  */
14045               needindex = addr32flag;
14046               needaddr32 = 1;
14047             }
14048           else
14049             {
14050               /* In 32-bit mode, we need index register to tell [offset]
14051                  from [eiz*1 + offset].  */
14052               needindex = 1;
14053             }
14054         }
14055
14056       havedisp = (havebase
14057                   || needindex
14058                   || (havesib && (haveindex || scale != 0)));
14059
14060       if (!intel_syntax)
14061         if (modrm.mod != 0 || base == 5)
14062           {
14063             if (havedisp || riprel)
14064               print_displacement (scratchbuf, disp);
14065             else
14066               print_operand_value (scratchbuf, 1, disp);
14067             oappend (scratchbuf);
14068             if (riprel)
14069               {
14070                 set_op (disp, 1);
14071                 oappend (!addr32flag ? "(%rip)" : "(%eip)");
14072               }
14073           }
14074
14075       if ((havebase || haveindex || needindex || needaddr32 || riprel)
14076           && (address_mode != mode_64bit
14077               || ((bytemode != v_bnd_mode)
14078                   && (bytemode != v_bndmk_mode)
14079                   && (bytemode != bnd_mode)
14080                   && (bytemode != bnd_swap_mode))))
14081         used_prefixes |= PREFIX_ADDR;
14082
14083       if (havedisp || (intel_syntax && riprel))
14084         {
14085           *obufp++ = open_char;
14086           if (intel_syntax && riprel)
14087             {
14088               set_op (disp, 1);
14089               oappend (!addr32flag ? "rip" : "eip");
14090             }
14091           *obufp = '\0';
14092           if (havebase)
14093             oappend (address_mode == mode_64bit && !addr32flag
14094                      ? names64[rbase] : names32[rbase]);
14095           if (havesib)
14096             {
14097               /* ESP/RSP won't allow index.  If base isn't ESP/RSP,
14098                  print index to tell base + index from base.  */
14099               if (scale != 0
14100                   || needindex
14101                   || haveindex
14102                   || (havebase && base != ESP_REG_NUM))
14103                 {
14104                   if (!intel_syntax || havebase)
14105                     {
14106                       *obufp++ = separator_char;
14107                       *obufp = '\0';
14108                     }
14109                   if (haveindex)
14110                     oappend (address_mode == mode_64bit && !addr32flag
14111                              ? indexes64[vindex] : indexes32[vindex]);
14112                   else
14113                     oappend (address_mode == mode_64bit && !addr32flag
14114                              ? index64 : index32);
14115
14116                   *obufp++ = scale_char;
14117                   *obufp = '\0';
14118                   sprintf (scratchbuf, "%d", 1 << scale);
14119                   oappend (scratchbuf);
14120                 }
14121             }
14122           if (intel_syntax
14123               && (disp || modrm.mod != 0 || base == 5))
14124             {
14125               if (!havedisp || (bfd_signed_vma) disp >= 0)
14126                 {
14127                   *obufp++ = '+';
14128                   *obufp = '\0';
14129                 }
14130               else if (modrm.mod != 1 && disp != -disp)
14131                 {
14132                   *obufp++ = '-';
14133                   *obufp = '\0';
14134                   disp = - (bfd_signed_vma) disp;
14135                 }
14136
14137               if (havedisp)
14138                 print_displacement (scratchbuf, disp);
14139               else
14140                 print_operand_value (scratchbuf, 1, disp);
14141               oappend (scratchbuf);
14142             }
14143
14144           *obufp++ = close_char;
14145           *obufp = '\0';
14146         }
14147       else if (intel_syntax)
14148         {
14149           if (modrm.mod != 0 || base == 5)
14150             {
14151               if (!active_seg_prefix)
14152                 {
14153                   oappend (names_seg[ds_reg - es_reg]);
14154                   oappend (":");
14155                 }
14156               print_operand_value (scratchbuf, 1, disp);
14157               oappend (scratchbuf);
14158             }
14159         }
14160     }
14161   else if (bytemode == v_bnd_mode
14162            || bytemode == v_bndmk_mode
14163            || bytemode == bnd_mode
14164            || bytemode == bnd_swap_mode)
14165     {
14166       oappend ("(bad)");
14167       return;
14168     }
14169   else
14170     {
14171       /* 16 bit address mode */
14172       used_prefixes |= prefixes & PREFIX_ADDR;
14173       switch (modrm.mod)
14174         {
14175         case 0:
14176           if (modrm.rm == 6)
14177             {
14178               disp = get16 ();
14179               if ((disp & 0x8000) != 0)
14180                 disp -= 0x10000;
14181             }
14182           break;
14183         case 1:
14184           FETCH_DATA (the_info, codep + 1);
14185           disp = *codep++;
14186           if ((disp & 0x80) != 0)
14187             disp -= 0x100;
14188           if (vex.evex && shift > 0)
14189             disp <<= shift;
14190           break;
14191         case 2:
14192           disp = get16 ();
14193           if ((disp & 0x8000) != 0)
14194             disp -= 0x10000;
14195           break;
14196         }
14197
14198       if (!intel_syntax)
14199         if (modrm.mod != 0 || modrm.rm == 6)
14200           {
14201             print_displacement (scratchbuf, disp);
14202             oappend (scratchbuf);
14203           }
14204
14205       if (modrm.mod != 0 || modrm.rm != 6)
14206         {
14207           *obufp++ = open_char;
14208           *obufp = '\0';
14209           oappend (index16[modrm.rm]);
14210           if (intel_syntax
14211               && (disp || modrm.mod != 0 || modrm.rm == 6))
14212             {
14213               if ((bfd_signed_vma) disp >= 0)
14214                 {
14215                   *obufp++ = '+';
14216                   *obufp = '\0';
14217                 }
14218               else if (modrm.mod != 1)
14219                 {
14220                   *obufp++ = '-';
14221                   *obufp = '\0';
14222                   disp = - (bfd_signed_vma) disp;
14223                 }
14224
14225               print_displacement (scratchbuf, disp);
14226               oappend (scratchbuf);
14227             }
14228
14229           *obufp++ = close_char;
14230           *obufp = '\0';
14231         }
14232       else if (intel_syntax)
14233         {
14234           if (!active_seg_prefix)
14235             {
14236               oappend (names_seg[ds_reg - es_reg]);
14237               oappend (":");
14238             }
14239           print_operand_value (scratchbuf, 1, disp & 0xffff);
14240           oappend (scratchbuf);
14241         }
14242     }
14243   if (vex.evex && vex.b
14244       && (bytemode == x_mode
14245           || bytemode == xmmq_mode
14246           || bytemode == evex_half_bcst_xmmq_mode))
14247     {
14248       if (vex.w
14249           || bytemode == xmmq_mode
14250           || bytemode == evex_half_bcst_xmmq_mode)
14251         {
14252           switch (vex.length)
14253             {
14254             case 128:
14255               oappend ("{1to2}");
14256               break;
14257             case 256:
14258               oappend ("{1to4}");
14259               break;
14260             case 512:
14261               oappend ("{1to8}");
14262               break;
14263             default:
14264               abort ();
14265             }
14266         }
14267       else
14268         {
14269           switch (vex.length)
14270             {
14271             case 128:
14272               oappend ("{1to4}");
14273               break;
14274             case 256:
14275               oappend ("{1to8}");
14276               break;
14277             case 512:
14278               oappend ("{1to16}");
14279               break;
14280             default:
14281               abort ();
14282             }
14283         }
14284     }
14285 }
14286
14287 static void
14288 OP_E (int bytemode, int sizeflag)
14289 {
14290   /* Skip mod/rm byte.  */
14291   MODRM_CHECK;
14292   codep++;
14293
14294   if (modrm.mod == 3)
14295     OP_E_register (bytemode, sizeflag);
14296   else
14297     OP_E_memory (bytemode, sizeflag);
14298 }
14299
14300 static void
14301 OP_G (int bytemode, int sizeflag)
14302 {
14303   int add = 0;
14304   const char **names;
14305   USED_REX (REX_R);
14306   if (rex & REX_R)
14307     add += 8;
14308   switch (bytemode)
14309     {
14310     case b_mode:
14311       USED_REX (0);
14312       if (rex)
14313         oappend (names8rex[modrm.reg + add]);
14314       else
14315         oappend (names8[modrm.reg + add]);
14316       break;
14317     case w_mode:
14318       oappend (names16[modrm.reg + add]);
14319       break;
14320     case d_mode:
14321     case db_mode:
14322     case dw_mode:
14323       oappend (names32[modrm.reg + add]);
14324       break;
14325     case q_mode:
14326       oappend (names64[modrm.reg + add]);
14327       break;
14328     case bnd_mode:
14329       if (modrm.reg > 0x3)
14330         {
14331           oappend ("(bad)");
14332           return;
14333         }
14334       oappend (names_bnd[modrm.reg]);
14335       break;
14336     case v_mode:
14337     case dq_mode:
14338     case dqb_mode:
14339     case dqd_mode:
14340     case dqw_mode:
14341     case movsxd_mode:
14342       USED_REX (REX_W);
14343       if (rex & REX_W)
14344         oappend (names64[modrm.reg + add]);
14345       else
14346         {
14347           if ((sizeflag & DFLAG)
14348               || (bytemode != v_mode && bytemode != movsxd_mode))
14349             oappend (names32[modrm.reg + add]);
14350           else
14351             oappend (names16[modrm.reg + add]);
14352           used_prefixes |= (prefixes & PREFIX_DATA);
14353         }
14354       break;
14355     case va_mode:
14356       names = (address_mode == mode_64bit
14357                ? names64 : names32);
14358       if (!(prefixes & PREFIX_ADDR))
14359         {
14360           if (address_mode == mode_16bit)
14361             names = names16;
14362         }
14363       else
14364         {
14365           /* Remove "addr16/addr32".  */
14366           all_prefixes[last_addr_prefix] = 0;
14367           names = (address_mode != mode_32bit
14368                        ? names32 : names16);
14369           used_prefixes |= PREFIX_ADDR;
14370         }
14371       oappend (names[modrm.reg + add]);
14372       break;
14373     case m_mode:
14374       if (address_mode == mode_64bit)
14375         oappend (names64[modrm.reg + add]);
14376       else
14377         oappend (names32[modrm.reg + add]);
14378       break;
14379     case mask_bd_mode:
14380     case mask_mode:
14381       if ((modrm.reg + add) > 0x7)
14382         {
14383           oappend ("(bad)");
14384           return;
14385         }
14386       oappend (names_mask[modrm.reg + add]);
14387       break;
14388     default:
14389       oappend (INTERNAL_DISASSEMBLER_ERROR);
14390       break;
14391     }
14392 }
14393
14394 static bfd_vma
14395 get64 (void)
14396 {
14397   bfd_vma x;
14398 #ifdef BFD64
14399   unsigned int a;
14400   unsigned int b;
14401
14402   FETCH_DATA (the_info, codep + 8);
14403   a = *codep++ & 0xff;
14404   a |= (*codep++ & 0xff) << 8;
14405   a |= (*codep++ & 0xff) << 16;
14406   a |= (*codep++ & 0xffu) << 24;
14407   b = *codep++ & 0xff;
14408   b |= (*codep++ & 0xff) << 8;
14409   b |= (*codep++ & 0xff) << 16;
14410   b |= (*codep++ & 0xffu) << 24;
14411   x = a + ((bfd_vma) b << 32);
14412 #else
14413   abort ();
14414   x = 0;
14415 #endif
14416   return x;
14417 }
14418
14419 static bfd_signed_vma
14420 get32 (void)
14421 {
14422   bfd_signed_vma x = 0;
14423
14424   FETCH_DATA (the_info, codep + 4);
14425   x = *codep++ & (bfd_signed_vma) 0xff;
14426   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
14427   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
14428   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
14429   return x;
14430 }
14431
14432 static bfd_signed_vma
14433 get32s (void)
14434 {
14435   bfd_signed_vma x = 0;
14436
14437   FETCH_DATA (the_info, codep + 4);
14438   x = *codep++ & (bfd_signed_vma) 0xff;
14439   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
14440   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
14441   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
14442
14443   x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
14444
14445   return x;
14446 }
14447
14448 static int
14449 get16 (void)
14450 {
14451   int x = 0;
14452
14453   FETCH_DATA (the_info, codep + 2);
14454   x = *codep++ & 0xff;
14455   x |= (*codep++ & 0xff) << 8;
14456   return x;
14457 }
14458
14459 static void
14460 set_op (bfd_vma op, int riprel)
14461 {
14462   op_index[op_ad] = op_ad;
14463   if (address_mode == mode_64bit)
14464     {
14465       op_address[op_ad] = op;
14466       op_riprel[op_ad] = riprel;
14467     }
14468   else
14469     {
14470       /* Mask to get a 32-bit address.  */
14471       op_address[op_ad] = op & 0xffffffff;
14472       op_riprel[op_ad] = riprel & 0xffffffff;
14473     }
14474 }
14475
14476 static void
14477 OP_REG (int code, int sizeflag)
14478 {
14479   const char *s;
14480   int add;
14481
14482   switch (code)
14483     {
14484     case es_reg: case ss_reg: case cs_reg:
14485     case ds_reg: case fs_reg: case gs_reg:
14486       oappend (names_seg[code - es_reg]);
14487       return;
14488     }
14489
14490   USED_REX (REX_B);
14491   if (rex & REX_B)
14492     add = 8;
14493   else
14494     add = 0;
14495
14496   switch (code)
14497     {
14498     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
14499     case sp_reg: case bp_reg: case si_reg: case di_reg:
14500       s = names16[code - ax_reg + add];
14501       break;
14502     case al_reg: case ah_reg: case cl_reg: case ch_reg:
14503     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
14504       USED_REX (0);
14505       if (rex)
14506         s = names8rex[code - al_reg + add];
14507       else
14508         s = names8[code - al_reg];
14509       break;
14510     case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
14511     case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
14512       if (address_mode == mode_64bit
14513           && ((sizeflag & DFLAG) || (rex & REX_W)))
14514         {
14515           s = names64[code - rAX_reg + add];
14516           break;
14517         }
14518       code += eAX_reg - rAX_reg;
14519       /* Fall through.  */
14520     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
14521     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
14522       USED_REX (REX_W);
14523       if (rex & REX_W)
14524         s = names64[code - eAX_reg + add];
14525       else
14526         {
14527           if (sizeflag & DFLAG)
14528             s = names32[code - eAX_reg + add];
14529           else
14530             s = names16[code - eAX_reg + add];
14531           used_prefixes |= (prefixes & PREFIX_DATA);
14532         }
14533       break;
14534     default:
14535       s = INTERNAL_DISASSEMBLER_ERROR;
14536       break;
14537     }
14538   oappend (s);
14539 }
14540
14541 static void
14542 OP_IMREG (int code, int sizeflag)
14543 {
14544   const char *s;
14545
14546   switch (code)
14547     {
14548     case indir_dx_reg:
14549       if (intel_syntax)
14550         s = "dx";
14551       else
14552         s = "(%dx)";
14553       break;
14554     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
14555     case sp_reg: case bp_reg: case si_reg: case di_reg:
14556       s = names16[code - ax_reg];
14557       break;
14558     case es_reg: case ss_reg: case cs_reg:
14559     case ds_reg: case fs_reg: case gs_reg:
14560       s = names_seg[code - es_reg];
14561       break;
14562     case al_reg: case ah_reg: case cl_reg: case ch_reg:
14563     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
14564       USED_REX (0);
14565       if (rex)
14566         s = names8rex[code - al_reg];
14567       else
14568         s = names8[code - al_reg];
14569       break;
14570     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
14571     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
14572       USED_REX (REX_W);
14573       if (rex & REX_W)
14574         s = names64[code - eAX_reg];
14575       else
14576         {
14577           if (sizeflag & DFLAG)
14578             s = names32[code - eAX_reg];
14579           else
14580             s = names16[code - eAX_reg];
14581           used_prefixes |= (prefixes & PREFIX_DATA);
14582         }
14583       break;
14584     case z_mode_ax_reg:
14585       if ((rex & REX_W) || (sizeflag & DFLAG))
14586         s = *names32;
14587       else
14588         s = *names16;
14589       if (!(rex & REX_W))
14590         used_prefixes |= (prefixes & PREFIX_DATA);
14591       break;
14592     default:
14593       s = INTERNAL_DISASSEMBLER_ERROR;
14594       break;
14595     }
14596   oappend (s);
14597 }
14598
14599 static void
14600 OP_I (int bytemode, int sizeflag)
14601 {
14602   bfd_signed_vma op;
14603   bfd_signed_vma mask = -1;
14604
14605   switch (bytemode)
14606     {
14607     case b_mode:
14608       FETCH_DATA (the_info, codep + 1);
14609       op = *codep++;
14610       mask = 0xff;
14611       break;
14612     case v_mode:
14613       USED_REX (REX_W);
14614       if (rex & REX_W)
14615         op = get32s ();
14616       else
14617         {
14618           if (sizeflag & DFLAG)
14619             {
14620               op = get32 ();
14621               mask = 0xffffffff;
14622             }
14623           else
14624             {
14625               op = get16 ();
14626               mask = 0xfffff;
14627             }
14628           used_prefixes |= (prefixes & PREFIX_DATA);
14629         }
14630       break;
14631     case d_mode:
14632       mask = 0xffffffff;
14633       op = get32 ();
14634       break;
14635     case w_mode:
14636       mask = 0xfffff;
14637       op = get16 ();
14638       break;
14639     case const_1_mode:
14640       if (intel_syntax)
14641         oappend ("1");
14642       return;
14643     default:
14644       oappend (INTERNAL_DISASSEMBLER_ERROR);
14645       return;
14646     }
14647
14648   op &= mask;
14649   scratchbuf[0] = '$';
14650   print_operand_value (scratchbuf + 1, 1, op);
14651   oappend_maybe_intel (scratchbuf);
14652   scratchbuf[0] = '\0';
14653 }
14654
14655 static void
14656 OP_I64 (int bytemode, int sizeflag)
14657 {
14658   if (bytemode != v_mode || address_mode != mode_64bit || !(rex & REX_W))
14659     {
14660       OP_I (bytemode, sizeflag);
14661       return;
14662     }
14663
14664   USED_REX (REX_W);
14665
14666   scratchbuf[0] = '$';
14667   print_operand_value (scratchbuf + 1, 1, get64 ());
14668   oappend_maybe_intel (scratchbuf);
14669   scratchbuf[0] = '\0';
14670 }
14671
14672 static void
14673 OP_sI (int bytemode, int sizeflag)
14674 {
14675   bfd_signed_vma op;
14676
14677   switch (bytemode)
14678     {
14679     case b_mode:
14680     case b_T_mode:
14681       FETCH_DATA (the_info, codep + 1);
14682       op = *codep++;
14683       if ((op & 0x80) != 0)
14684         op -= 0x100;
14685       if (bytemode == b_T_mode)
14686         {
14687           if (address_mode != mode_64bit
14688               || !((sizeflag & DFLAG) || (rex & REX_W)))
14689             {
14690               /* The operand-size prefix is overridden by a REX prefix.  */
14691               if ((sizeflag & DFLAG) || (rex & REX_W))
14692                 op &= 0xffffffff;
14693               else
14694                 op &= 0xffff;
14695           }
14696         }
14697       else
14698         {
14699           if (!(rex & REX_W))
14700             {
14701               if (sizeflag & DFLAG)
14702                 op &= 0xffffffff;
14703               else
14704                 op &= 0xffff;
14705             }
14706         }
14707       break;
14708     case v_mode:
14709       /* The operand-size prefix is overridden by a REX prefix.  */
14710       if ((sizeflag & DFLAG) || (rex & REX_W))
14711         op = get32s ();
14712       else
14713         op = get16 ();
14714       break;
14715     default:
14716       oappend (INTERNAL_DISASSEMBLER_ERROR);
14717       return;
14718     }
14719
14720   scratchbuf[0] = '$';
14721   print_operand_value (scratchbuf + 1, 1, op);
14722   oappend_maybe_intel (scratchbuf);
14723 }
14724
14725 static void
14726 OP_J (int bytemode, int sizeflag)
14727 {
14728   bfd_vma disp;
14729   bfd_vma mask = -1;
14730   bfd_vma segment = 0;
14731
14732   switch (bytemode)
14733     {
14734     case b_mode:
14735       FETCH_DATA (the_info, codep + 1);
14736       disp = *codep++;
14737       if ((disp & 0x80) != 0)
14738         disp -= 0x100;
14739       break;
14740     case v_mode:
14741       if (isa64 != intel64)
14742     case dqw_mode:
14743         USED_REX (REX_W);
14744       if ((sizeflag & DFLAG)
14745           || (address_mode == mode_64bit
14746               && ((isa64 == intel64 && bytemode != dqw_mode)
14747                   || (rex & REX_W))))
14748         disp = get32s ();
14749       else
14750         {
14751           disp = get16 ();
14752           if ((disp & 0x8000) != 0)
14753             disp -= 0x10000;
14754           /* In 16bit mode, address is wrapped around at 64k within
14755              the same segment.  Otherwise, a data16 prefix on a jump
14756              instruction means that the pc is masked to 16 bits after
14757              the displacement is added!  */
14758           mask = 0xffff;
14759           if ((prefixes & PREFIX_DATA) == 0)
14760             segment = ((start_pc + (codep - start_codep))
14761                        & ~((bfd_vma) 0xffff));
14762         }
14763       if (address_mode != mode_64bit
14764           || (isa64 != intel64 && !(rex & REX_W)))
14765         used_prefixes |= (prefixes & PREFIX_DATA);
14766       break;
14767     default:
14768       oappend (INTERNAL_DISASSEMBLER_ERROR);
14769       return;
14770     }
14771   disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment;
14772   set_op (disp, 0);
14773   print_operand_value (scratchbuf, 1, disp);
14774   oappend (scratchbuf);
14775 }
14776
14777 static void
14778 OP_SEG (int bytemode, int sizeflag)
14779 {
14780   if (bytemode == w_mode)
14781     oappend (names_seg[modrm.reg]);
14782   else
14783     OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
14784 }
14785
14786 static void
14787 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
14788 {
14789   int seg, offset;
14790
14791   if (sizeflag & DFLAG)
14792     {
14793       offset = get32 ();
14794       seg = get16 ();
14795     }
14796   else
14797     {
14798       offset = get16 ();
14799       seg = get16 ();
14800     }
14801   used_prefixes |= (prefixes & PREFIX_DATA);
14802   if (intel_syntax)
14803     sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
14804   else
14805     sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
14806   oappend (scratchbuf);
14807 }
14808
14809 static void
14810 OP_OFF (int bytemode, int sizeflag)
14811 {
14812   bfd_vma off;
14813
14814   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
14815     intel_operand_size (bytemode, sizeflag);
14816   append_seg ();
14817
14818   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
14819     off = get32 ();
14820   else
14821     off = get16 ();
14822
14823   if (intel_syntax)
14824     {
14825       if (!active_seg_prefix)
14826         {
14827           oappend (names_seg[ds_reg - es_reg]);
14828           oappend (":");
14829         }
14830     }
14831   print_operand_value (scratchbuf, 1, off);
14832   oappend (scratchbuf);
14833 }
14834
14835 static void
14836 OP_OFF64 (int bytemode, int sizeflag)
14837 {
14838   bfd_vma off;
14839
14840   if (address_mode != mode_64bit
14841       || (prefixes & PREFIX_ADDR))
14842     {
14843       OP_OFF (bytemode, sizeflag);
14844       return;
14845     }
14846
14847   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
14848     intel_operand_size (bytemode, sizeflag);
14849   append_seg ();
14850
14851   off = get64 ();
14852
14853   if (intel_syntax)
14854     {
14855       if (!active_seg_prefix)
14856         {
14857           oappend (names_seg[ds_reg - es_reg]);
14858           oappend (":");
14859         }
14860     }
14861   print_operand_value (scratchbuf, 1, off);
14862   oappend (scratchbuf);
14863 }
14864
14865 static void
14866 ptr_reg (int code, int sizeflag)
14867 {
14868   const char *s;
14869
14870   *obufp++ = open_char;
14871   used_prefixes |= (prefixes & PREFIX_ADDR);
14872   if (address_mode == mode_64bit)
14873     {
14874       if (!(sizeflag & AFLAG))
14875         s = names32[code - eAX_reg];
14876       else
14877         s = names64[code - eAX_reg];
14878     }
14879   else if (sizeflag & AFLAG)
14880     s = names32[code - eAX_reg];
14881   else
14882     s = names16[code - eAX_reg];
14883   oappend (s);
14884   *obufp++ = close_char;
14885   *obufp = 0;
14886 }
14887
14888 static void
14889 OP_ESreg (int code, int sizeflag)
14890 {
14891   if (intel_syntax)
14892     {
14893       switch (codep[-1])
14894         {
14895         case 0x6d:      /* insw/insl */
14896           intel_operand_size (z_mode, sizeflag);
14897           break;
14898         case 0xa5:      /* movsw/movsl/movsq */
14899         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
14900         case 0xab:      /* stosw/stosl */
14901         case 0xaf:      /* scasw/scasl */
14902           intel_operand_size (v_mode, sizeflag);
14903           break;
14904         default:
14905           intel_operand_size (b_mode, sizeflag);
14906         }
14907     }
14908   oappend_maybe_intel ("%es:");
14909   ptr_reg (code, sizeflag);
14910 }
14911
14912 static void
14913 OP_DSreg (int code, int sizeflag)
14914 {
14915   if (intel_syntax)
14916     {
14917       switch (codep[-1])
14918         {
14919         case 0x6f:      /* outsw/outsl */
14920           intel_operand_size (z_mode, sizeflag);
14921           break;
14922         case 0xa5:      /* movsw/movsl/movsq */
14923         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
14924         case 0xad:      /* lodsw/lodsl/lodsq */
14925           intel_operand_size (v_mode, sizeflag);
14926           break;
14927         default:
14928           intel_operand_size (b_mode, sizeflag);
14929         }
14930     }
14931   /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
14932      default segment register DS is printed.  */
14933   if (!active_seg_prefix)
14934     active_seg_prefix = PREFIX_DS;
14935   append_seg ();
14936   ptr_reg (code, sizeflag);
14937 }
14938
14939 static void
14940 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14941 {
14942   int add;
14943   if (rex & REX_R)
14944     {
14945       USED_REX (REX_R);
14946       add = 8;
14947     }
14948   else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
14949     {
14950       all_prefixes[last_lock_prefix] = 0;
14951       used_prefixes |= PREFIX_LOCK;
14952       add = 8;
14953     }
14954   else
14955     add = 0;
14956   sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
14957   oappend_maybe_intel (scratchbuf);
14958 }
14959
14960 static void
14961 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14962 {
14963   int add;
14964   USED_REX (REX_R);
14965   if (rex & REX_R)
14966     add = 8;
14967   else
14968     add = 0;
14969   if (intel_syntax)
14970     sprintf (scratchbuf, "db%d", modrm.reg + add);
14971   else
14972     sprintf (scratchbuf, "%%db%d", modrm.reg + add);
14973   oappend (scratchbuf);
14974 }
14975
14976 static void
14977 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14978 {
14979   sprintf (scratchbuf, "%%tr%d", modrm.reg);
14980   oappend_maybe_intel (scratchbuf);
14981 }
14982
14983 static void
14984 OP_R (int bytemode, int sizeflag)
14985 {
14986   /* Skip mod/rm byte.  */
14987   MODRM_CHECK;
14988   codep++;
14989   OP_E_register (bytemode, sizeflag);
14990 }
14991
14992 static void
14993 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14994 {
14995   int reg = modrm.reg;
14996   const char **names;
14997
14998   used_prefixes |= (prefixes & PREFIX_DATA);
14999   if (prefixes & PREFIX_DATA)
15000     {
15001       names = names_xmm;
15002       USED_REX (REX_R);
15003       if (rex & REX_R)
15004         reg += 8;
15005     }
15006   else
15007     names = names_mm;
15008   oappend (names[reg]);
15009 }
15010
15011 static void
15012 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
15013 {
15014   int reg = modrm.reg;
15015   const char **names;
15016
15017   USED_REX (REX_R);
15018   if (rex & REX_R)
15019     reg += 8;
15020   if (vex.evex)
15021     {
15022       if (!vex.r)
15023         reg += 16;
15024     }
15025
15026   if (need_vex
15027       && bytemode != xmm_mode
15028       && bytemode != xmmq_mode
15029       && bytemode != evex_half_bcst_xmmq_mode
15030       && bytemode != ymm_mode
15031       && bytemode != scalar_mode)
15032     {
15033       switch (vex.length)
15034         {
15035         case 128:
15036           names = names_xmm;
15037           break;
15038         case 256:
15039           if (vex.w
15040               || (bytemode != vex_vsib_q_w_dq_mode
15041                   && bytemode != vex_vsib_q_w_d_mode))
15042             names = names_ymm;
15043           else
15044             names = names_xmm;
15045           break;
15046         case 512:
15047           names = names_zmm;
15048           break;
15049         default:
15050           abort ();
15051         }
15052     }
15053   else if (bytemode == xmmq_mode
15054            || bytemode == evex_half_bcst_xmmq_mode)
15055     {
15056       switch (vex.length)
15057         {
15058         case 128:
15059         case 256:
15060           names = names_xmm;
15061           break;
15062         case 512:
15063           names = names_ymm;
15064           break;
15065         default:
15066           abort ();
15067         }
15068     }
15069   else if (bytemode == ymm_mode)
15070     names = names_ymm;
15071   else
15072     names = names_xmm;
15073   oappend (names[reg]);
15074 }
15075
15076 static void
15077 OP_EM (int bytemode, int sizeflag)
15078 {
15079   int reg;
15080   const char **names;
15081
15082   if (modrm.mod != 3)
15083     {
15084       if (intel_syntax
15085           && (bytemode == v_mode || bytemode == v_swap_mode))
15086         {
15087           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
15088           used_prefixes |= (prefixes & PREFIX_DATA);
15089         }
15090       OP_E (bytemode, sizeflag);
15091       return;
15092     }
15093
15094   if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
15095     swap_operand ();
15096
15097   /* Skip mod/rm byte.  */
15098   MODRM_CHECK;
15099   codep++;
15100   used_prefixes |= (prefixes & PREFIX_DATA);
15101   reg = modrm.rm;
15102   if (prefixes & PREFIX_DATA)
15103     {
15104       names = names_xmm;
15105       USED_REX (REX_B);
15106       if (rex & REX_B)
15107         reg += 8;
15108     }
15109   else
15110     names = names_mm;
15111   oappend (names[reg]);
15112 }
15113
15114 /* cvt* are the only instructions in sse2 which have
15115    both SSE and MMX operands and also have 0x66 prefix
15116    in their opcode. 0x66 was originally used to differentiate
15117    between SSE and MMX instruction(operands). So we have to handle the
15118    cvt* separately using OP_EMC and OP_MXC */
15119 static void
15120 OP_EMC (int bytemode, int sizeflag)
15121 {
15122   if (modrm.mod != 3)
15123     {
15124       if (intel_syntax && bytemode == v_mode)
15125         {
15126           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
15127           used_prefixes |= (prefixes & PREFIX_DATA);
15128         }
15129       OP_E (bytemode, sizeflag);
15130       return;
15131     }
15132
15133   /* Skip mod/rm byte.  */
15134   MODRM_CHECK;
15135   codep++;
15136   used_prefixes |= (prefixes & PREFIX_DATA);
15137   oappend (names_mm[modrm.rm]);
15138 }
15139
15140 static void
15141 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15142 {
15143   used_prefixes |= (prefixes & PREFIX_DATA);
15144   oappend (names_mm[modrm.reg]);
15145 }
15146
15147 static void
15148 OP_EX (int bytemode, int sizeflag)
15149 {
15150   int reg;
15151   const char **names;
15152
15153   /* Skip mod/rm byte.  */
15154   MODRM_CHECK;
15155   codep++;
15156
15157   if (modrm.mod != 3)
15158     {
15159       OP_E_memory (bytemode, sizeflag);
15160       return;
15161     }
15162
15163   reg = modrm.rm;
15164   USED_REX (REX_B);
15165   if (rex & REX_B)
15166     reg += 8;
15167   if (vex.evex)
15168     {
15169       USED_REX (REX_X);
15170       if ((rex & REX_X))
15171         reg += 16;
15172     }
15173
15174   if ((sizeflag & SUFFIX_ALWAYS)
15175       && (bytemode == x_swap_mode
15176           || bytemode == d_swap_mode
15177           || bytemode == d_scalar_swap_mode
15178           || bytemode == q_swap_mode
15179           || bytemode == q_scalar_swap_mode))
15180     swap_operand ();
15181
15182   if (need_vex
15183       && bytemode != xmm_mode
15184       && bytemode != xmmdw_mode
15185       && bytemode != xmmqd_mode
15186       && bytemode != xmm_mb_mode
15187       && bytemode != xmm_mw_mode
15188       && bytemode != xmm_md_mode
15189       && bytemode != xmm_mq_mode
15190       && bytemode != xmmq_mode
15191       && bytemode != evex_half_bcst_xmmq_mode
15192       && bytemode != ymm_mode
15193       && bytemode != d_scalar_swap_mode
15194       && bytemode != q_scalar_swap_mode
15195       && bytemode != vex_scalar_w_dq_mode)
15196     {
15197       switch (vex.length)
15198         {
15199         case 128:
15200           names = names_xmm;
15201           break;
15202         case 256:
15203           names = names_ymm;
15204           break;
15205         case 512:
15206           names = names_zmm;
15207           break;
15208         default:
15209           abort ();
15210         }
15211     }
15212   else if (bytemode == xmmq_mode
15213            || bytemode == evex_half_bcst_xmmq_mode)
15214     {
15215       switch (vex.length)
15216         {
15217         case 128:
15218         case 256:
15219           names = names_xmm;
15220           break;
15221         case 512:
15222           names = names_ymm;
15223           break;
15224         default:
15225           abort ();
15226         }
15227     }
15228   else if (bytemode == ymm_mode)
15229     names = names_ymm;
15230   else
15231     names = names_xmm;
15232   oappend (names[reg]);
15233 }
15234
15235 static void
15236 OP_MS (int bytemode, int sizeflag)
15237 {
15238   if (modrm.mod == 3)
15239     OP_EM (bytemode, sizeflag);
15240   else
15241     BadOp ();
15242 }
15243
15244 static void
15245 OP_XS (int bytemode, int sizeflag)
15246 {
15247   if (modrm.mod == 3)
15248     OP_EX (bytemode, sizeflag);
15249   else
15250     BadOp ();
15251 }
15252
15253 static void
15254 OP_M (int bytemode, int sizeflag)
15255 {
15256   if (modrm.mod == 3)
15257     /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
15258     BadOp ();
15259   else
15260     OP_E (bytemode, sizeflag);
15261 }
15262
15263 static void
15264 OP_0f07 (int bytemode, int sizeflag)
15265 {
15266   if (modrm.mod != 3 || modrm.rm != 0)
15267     BadOp ();
15268   else
15269     OP_E (bytemode, sizeflag);
15270 }
15271
15272 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
15273    32bit mode and "xchg %rax,%rax" in 64bit mode.  */
15274
15275 static void
15276 NOP_Fixup1 (int bytemode, int sizeflag)
15277 {
15278   if ((prefixes & PREFIX_DATA) != 0
15279       || (rex != 0
15280           && rex != 0x48
15281           && address_mode == mode_64bit))
15282     OP_REG (bytemode, sizeflag);
15283   else
15284     strcpy (obuf, "nop");
15285 }
15286
15287 static void
15288 NOP_Fixup2 (int bytemode, int sizeflag)
15289 {
15290   if ((prefixes & PREFIX_DATA) != 0
15291       || (rex != 0
15292           && rex != 0x48
15293           && address_mode == mode_64bit))
15294     OP_IMREG (bytemode, sizeflag);
15295 }
15296
15297 static const char *const Suffix3DNow[] = {
15298 /* 00 */        NULL,           NULL,           NULL,           NULL,
15299 /* 04 */        NULL,           NULL,           NULL,           NULL,
15300 /* 08 */        NULL,           NULL,           NULL,           NULL,
15301 /* 0C */        "pi2fw",        "pi2fd",        NULL,           NULL,
15302 /* 10 */        NULL,           NULL,           NULL,           NULL,
15303 /* 14 */        NULL,           NULL,           NULL,           NULL,
15304 /* 18 */        NULL,           NULL,           NULL,           NULL,
15305 /* 1C */        "pf2iw",        "pf2id",        NULL,           NULL,
15306 /* 20 */        NULL,           NULL,           NULL,           NULL,
15307 /* 24 */        NULL,           NULL,           NULL,           NULL,
15308 /* 28 */        NULL,           NULL,           NULL,           NULL,
15309 /* 2C */        NULL,           NULL,           NULL,           NULL,
15310 /* 30 */        NULL,           NULL,           NULL,           NULL,
15311 /* 34 */        NULL,           NULL,           NULL,           NULL,
15312 /* 38 */        NULL,           NULL,           NULL,           NULL,
15313 /* 3C */        NULL,           NULL,           NULL,           NULL,
15314 /* 40 */        NULL,           NULL,           NULL,           NULL,
15315 /* 44 */        NULL,           NULL,           NULL,           NULL,
15316 /* 48 */        NULL,           NULL,           NULL,           NULL,
15317 /* 4C */        NULL,           NULL,           NULL,           NULL,
15318 /* 50 */        NULL,           NULL,           NULL,           NULL,
15319 /* 54 */        NULL,           NULL,           NULL,           NULL,
15320 /* 58 */        NULL,           NULL,           NULL,           NULL,
15321 /* 5C */        NULL,           NULL,           NULL,           NULL,
15322 /* 60 */        NULL,           NULL,           NULL,           NULL,
15323 /* 64 */        NULL,           NULL,           NULL,           NULL,
15324 /* 68 */        NULL,           NULL,           NULL,           NULL,
15325 /* 6C */        NULL,           NULL,           NULL,           NULL,
15326 /* 70 */        NULL,           NULL,           NULL,           NULL,
15327 /* 74 */        NULL,           NULL,           NULL,           NULL,
15328 /* 78 */        NULL,           NULL,           NULL,           NULL,
15329 /* 7C */        NULL,           NULL,           NULL,           NULL,
15330 /* 80 */        NULL,           NULL,           NULL,           NULL,
15331 /* 84 */        NULL,           NULL,           NULL,           NULL,
15332 /* 88 */        NULL,           NULL,           "pfnacc",       NULL,
15333 /* 8C */        NULL,           NULL,           "pfpnacc",      NULL,
15334 /* 90 */        "pfcmpge",      NULL,           NULL,           NULL,
15335 /* 94 */        "pfmin",        NULL,           "pfrcp",        "pfrsqrt",
15336 /* 98 */        NULL,           NULL,           "pfsub",        NULL,
15337 /* 9C */        NULL,           NULL,           "pfadd",        NULL,
15338 /* A0 */        "pfcmpgt",      NULL,           NULL,           NULL,
15339 /* A4 */        "pfmax",        NULL,           "pfrcpit1",     "pfrsqit1",
15340 /* A8 */        NULL,           NULL,           "pfsubr",       NULL,
15341 /* AC */        NULL,           NULL,           "pfacc",        NULL,
15342 /* B0 */        "pfcmpeq",      NULL,           NULL,           NULL,
15343 /* B4 */        "pfmul",        NULL,           "pfrcpit2",     "pmulhrw",
15344 /* B8 */        NULL,           NULL,           NULL,           "pswapd",
15345 /* BC */        NULL,           NULL,           NULL,           "pavgusb",
15346 /* C0 */        NULL,           NULL,           NULL,           NULL,
15347 /* C4 */        NULL,           NULL,           NULL,           NULL,
15348 /* C8 */        NULL,           NULL,           NULL,           NULL,
15349 /* CC */        NULL,           NULL,           NULL,           NULL,
15350 /* D0 */        NULL,           NULL,           NULL,           NULL,
15351 /* D4 */        NULL,           NULL,           NULL,           NULL,
15352 /* D8 */        NULL,           NULL,           NULL,           NULL,
15353 /* DC */        NULL,           NULL,           NULL,           NULL,
15354 /* E0 */        NULL,           NULL,           NULL,           NULL,
15355 /* E4 */        NULL,           NULL,           NULL,           NULL,
15356 /* E8 */        NULL,           NULL,           NULL,           NULL,
15357 /* EC */        NULL,           NULL,           NULL,           NULL,
15358 /* F0 */        NULL,           NULL,           NULL,           NULL,
15359 /* F4 */        NULL,           NULL,           NULL,           NULL,
15360 /* F8 */        NULL,           NULL,           NULL,           NULL,
15361 /* FC */        NULL,           NULL,           NULL,           NULL,
15362 };
15363
15364 static void
15365 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15366 {
15367   const char *mnemonic;
15368
15369   FETCH_DATA (the_info, codep + 1);
15370   /* AMD 3DNow! instructions are specified by an opcode suffix in the
15371      place where an 8-bit immediate would normally go.  ie. the last
15372      byte of the instruction.  */
15373   obufp = mnemonicendp;
15374   mnemonic = Suffix3DNow[*codep++ & 0xff];
15375   if (mnemonic)
15376     oappend (mnemonic);
15377   else
15378     {
15379       /* Since a variable sized modrm/sib chunk is between the start
15380          of the opcode (0x0f0f) and the opcode suffix, we need to do
15381          all the modrm processing first, and don't know until now that
15382          we have a bad opcode.  This necessitates some cleaning up.  */
15383       op_out[0][0] = '\0';
15384       op_out[1][0] = '\0';
15385       BadOp ();
15386     }
15387   mnemonicendp = obufp;
15388 }
15389
15390 static struct op simd_cmp_op[] =
15391 {
15392   { STRING_COMMA_LEN ("eq") },
15393   { STRING_COMMA_LEN ("lt") },
15394   { STRING_COMMA_LEN ("le") },
15395   { STRING_COMMA_LEN ("unord") },
15396   { STRING_COMMA_LEN ("neq") },
15397   { STRING_COMMA_LEN ("nlt") },
15398   { STRING_COMMA_LEN ("nle") },
15399   { STRING_COMMA_LEN ("ord") }
15400 };
15401
15402 static void
15403 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15404 {
15405   unsigned int cmp_type;
15406
15407   FETCH_DATA (the_info, codep + 1);
15408   cmp_type = *codep++ & 0xff;
15409   if (cmp_type < ARRAY_SIZE (simd_cmp_op))
15410     {
15411       char suffix [3];
15412       char *p = mnemonicendp - 2;
15413       suffix[0] = p[0];
15414       suffix[1] = p[1];
15415       suffix[2] = '\0';
15416       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
15417       mnemonicendp += simd_cmp_op[cmp_type].len;
15418     }
15419   else
15420     {
15421       /* We have a reserved extension byte.  Output it directly.  */
15422       scratchbuf[0] = '$';
15423       print_operand_value (scratchbuf + 1, 1, cmp_type);
15424       oappend_maybe_intel (scratchbuf);
15425       scratchbuf[0] = '\0';
15426     }
15427 }
15428
15429 static void
15430 OP_Mwait (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
15431 {
15432   /* mwait %eax,%ecx / mwaitx %eax,%ecx,%ebx  */
15433   if (!intel_syntax)
15434     {
15435       strcpy (op_out[0], names32[0]);
15436       strcpy (op_out[1], names32[1]);
15437       if (bytemode == eBX_reg)
15438         strcpy (op_out[2], names32[3]);
15439       two_source_ops = 1;
15440     }
15441   /* Skip mod/rm byte.  */
15442   MODRM_CHECK;
15443   codep++;
15444 }
15445
15446 static void
15447 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
15448             int sizeflag ATTRIBUTE_UNUSED)
15449 {
15450   /* monitor %{e,r,}ax,%ecx,%edx"  */
15451   if (!intel_syntax)
15452     {
15453       const char **names = (address_mode == mode_64bit
15454                             ? names64 : names32);
15455
15456       if (prefixes & PREFIX_ADDR)
15457         {
15458           /* Remove "addr16/addr32".  */
15459           all_prefixes[last_addr_prefix] = 0;
15460           names = (address_mode != mode_32bit
15461                    ? names32 : names16);
15462           used_prefixes |= PREFIX_ADDR;
15463         }
15464       else if (address_mode == mode_16bit)
15465         names = names16;
15466       strcpy (op_out[0], names[0]);
15467       strcpy (op_out[1], names32[1]);
15468       strcpy (op_out[2], names32[2]);
15469       two_source_ops = 1;
15470     }
15471   /* Skip mod/rm byte.  */
15472   MODRM_CHECK;
15473   codep++;
15474 }
15475
15476 static void
15477 BadOp (void)
15478 {
15479   /* Throw away prefixes and 1st. opcode byte.  */
15480   codep = insn_codep + 1;
15481   oappend ("(bad)");
15482 }
15483
15484 static void
15485 REP_Fixup (int bytemode, int sizeflag)
15486 {
15487   /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
15488      lods and stos.  */
15489   if (prefixes & PREFIX_REPZ)
15490     all_prefixes[last_repz_prefix] = REP_PREFIX;
15491
15492   switch (bytemode)
15493     {
15494     case al_reg:
15495     case eAX_reg:
15496     case indir_dx_reg:
15497       OP_IMREG (bytemode, sizeflag);
15498       break;
15499     case eDI_reg:
15500       OP_ESreg (bytemode, sizeflag);
15501       break;
15502     case eSI_reg:
15503       OP_DSreg (bytemode, sizeflag);
15504       break;
15505     default:
15506       abort ();
15507       break;
15508     }
15509 }
15510
15511 static void
15512 SEP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15513 {
15514   if ( isa64 != amd64 )
15515     return;
15516
15517   obufp = obuf;
15518   BadOp ();
15519   mnemonicendp = obufp;
15520   ++codep;
15521 }
15522
15523 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
15524    "bnd".  */
15525
15526 static void
15527 BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15528 {
15529   if (prefixes & PREFIX_REPNZ)
15530     all_prefixes[last_repnz_prefix] = BND_PREFIX;
15531 }
15532
15533 /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
15534    "notrack".  */
15535
15536 static void
15537 NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED,
15538                int sizeflag ATTRIBUTE_UNUSED)
15539 {
15540   if (active_seg_prefix == PREFIX_DS
15541       && (address_mode != mode_64bit || last_data_prefix < 0))
15542     {
15543       /* NOTRACK prefix is only valid on indirect branch instructions.
15544          NB: DATA prefix is unsupported for Intel64.  */
15545       active_seg_prefix = 0;
15546       all_prefixes[last_seg_prefix] = NOTRACK_PREFIX;
15547     }
15548 }
15549
15550 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
15551    "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
15552  */
15553
15554 static void
15555 HLE_Fixup1 (int bytemode, int sizeflag)
15556 {
15557   if (modrm.mod != 3
15558       && (prefixes & PREFIX_LOCK) != 0)
15559     {
15560       if (prefixes & PREFIX_REPZ)
15561         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15562       if (prefixes & PREFIX_REPNZ)
15563         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15564     }
15565
15566   OP_E (bytemode, sizeflag);
15567 }
15568
15569 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
15570    "xacquire"/"xrelease" for memory operand.  No check for LOCK prefix.
15571  */
15572
15573 static void
15574 HLE_Fixup2 (int bytemode, int sizeflag)
15575 {
15576   if (modrm.mod != 3)
15577     {
15578       if (prefixes & PREFIX_REPZ)
15579         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15580       if (prefixes & PREFIX_REPNZ)
15581         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15582     }
15583
15584   OP_E (bytemode, sizeflag);
15585 }
15586
15587 /* Similar to OP_E.  But the 0xf3 prefixes should be displayed as
15588    "xrelease" for memory operand.  No check for LOCK prefix.   */
15589
15590 static void
15591 HLE_Fixup3 (int bytemode, int sizeflag)
15592 {
15593   if (modrm.mod != 3
15594       && last_repz_prefix > last_repnz_prefix
15595       && (prefixes & PREFIX_REPZ) != 0)
15596     all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15597
15598   OP_E (bytemode, sizeflag);
15599 }
15600
15601 static void
15602 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
15603 {
15604   USED_REX (REX_W);
15605   if (rex & REX_W)
15606     {
15607       /* Change cmpxchg8b to cmpxchg16b.  */
15608       char *p = mnemonicendp - 2;
15609       mnemonicendp = stpcpy (p, "16b");
15610       bytemode = o_mode;
15611     }
15612   else if ((prefixes & PREFIX_LOCK) != 0)
15613     {
15614       if (prefixes & PREFIX_REPZ)
15615         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15616       if (prefixes & PREFIX_REPNZ)
15617         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15618     }
15619
15620   OP_M (bytemode, sizeflag);
15621 }
15622
15623 static void
15624 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
15625 {
15626   const char **names;
15627
15628   if (need_vex)
15629     {
15630       switch (vex.length)
15631         {
15632         case 128:
15633           names = names_xmm;
15634           break;
15635         case 256:
15636           names = names_ymm;
15637           break;
15638         default:
15639           abort ();
15640         }
15641     }
15642   else
15643     names = names_xmm;
15644   oappend (names[reg]);
15645 }
15646
15647 static void
15648 CRC32_Fixup (int bytemode, int sizeflag)
15649 {
15650   /* Add proper suffix to "crc32".  */
15651   char *p = mnemonicendp;
15652
15653   switch (bytemode)
15654     {
15655     case b_mode:
15656       if (intel_syntax)
15657         goto skip;
15658
15659       *p++ = 'b';
15660       break;
15661     case v_mode:
15662       if (intel_syntax)
15663         goto skip;
15664
15665       USED_REX (REX_W);
15666       if (rex & REX_W)
15667         *p++ = 'q';
15668       else
15669         {
15670           if (sizeflag & DFLAG)
15671             *p++ = 'l';
15672           else
15673             *p++ = 'w';
15674           used_prefixes |= (prefixes & PREFIX_DATA);
15675         }
15676       break;
15677     default:
15678       oappend (INTERNAL_DISASSEMBLER_ERROR);
15679       break;
15680     }
15681   mnemonicendp = p;
15682   *p = '\0';
15683
15684  skip:
15685   if (modrm.mod == 3)
15686     {
15687       int add;
15688
15689       /* Skip mod/rm byte.  */
15690       MODRM_CHECK;
15691       codep++;
15692
15693       USED_REX (REX_B);
15694       add = (rex & REX_B) ? 8 : 0;
15695       if (bytemode == b_mode)
15696         {
15697           USED_REX (0);
15698           if (rex)
15699             oappend (names8rex[modrm.rm + add]);
15700           else
15701             oappend (names8[modrm.rm + add]);
15702         }
15703       else
15704         {
15705           USED_REX (REX_W);
15706           if (rex & REX_W)
15707             oappend (names64[modrm.rm + add]);
15708           else if ((prefixes & PREFIX_DATA))
15709             oappend (names16[modrm.rm + add]);
15710           else
15711             oappend (names32[modrm.rm + add]);
15712         }
15713     }
15714   else
15715     OP_E (bytemode, sizeflag);
15716 }
15717
15718 static void
15719 FXSAVE_Fixup (int bytemode, int sizeflag)
15720 {
15721   /* Add proper suffix to "fxsave" and "fxrstor".  */
15722   USED_REX (REX_W);
15723   if (rex & REX_W)
15724     {
15725       char *p = mnemonicendp;
15726       *p++ = '6';
15727       *p++ = '4';
15728       *p = '\0';
15729       mnemonicendp = p;
15730     }
15731   OP_M (bytemode, sizeflag);
15732 }
15733
15734 static void
15735 PCMPESTR_Fixup (int bytemode, int sizeflag)
15736 {
15737   /* Add proper suffix to "{,v}pcmpestr{i,m}".  */
15738   if (!intel_syntax)
15739     {
15740       char *p = mnemonicendp;
15741
15742       USED_REX (REX_W);
15743       if (rex & REX_W)
15744         *p++ = 'q';
15745       else if (sizeflag & SUFFIX_ALWAYS)
15746         *p++ = 'l';
15747
15748       *p = '\0';
15749       mnemonicendp = p;
15750     }
15751
15752   OP_EX (bytemode, sizeflag);
15753 }
15754
15755 /* Display the destination register operand for instructions with
15756    VEX. */
15757
15758 static void
15759 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
15760 {
15761   int reg;
15762   const char **names;
15763
15764   if (!need_vex)
15765     abort ();
15766
15767   if (!need_vex_reg)
15768     return;
15769
15770   reg = vex.register_specifier;
15771   vex.register_specifier = 0;
15772   if (address_mode != mode_64bit)
15773     reg &= 7;
15774   else if (vex.evex && !vex.v)
15775     reg += 16;
15776
15777   if (bytemode == vex_scalar_mode)
15778     {
15779       oappend (names_xmm[reg]);
15780       return;
15781     }
15782
15783   switch (vex.length)
15784     {
15785     case 128:
15786       switch (bytemode)
15787         {
15788         case vex_mode:
15789         case vex128_mode:
15790         case vex_vsib_q_w_dq_mode:
15791         case vex_vsib_q_w_d_mode:
15792           names = names_xmm;
15793           break;
15794         case dq_mode:
15795           if (rex & REX_W)
15796             names = names64;
15797           else
15798             names = names32;
15799           break;
15800         case mask_bd_mode:
15801         case mask_mode:
15802           if (reg > 0x7)
15803             {
15804               oappend ("(bad)");
15805               return;
15806             }
15807           names = names_mask;
15808           break;
15809         default:
15810           abort ();
15811           return;
15812         }
15813       break;
15814     case 256:
15815       switch (bytemode)
15816         {
15817         case vex_mode:
15818         case vex256_mode:
15819           names = names_ymm;
15820           break;
15821         case vex_vsib_q_w_dq_mode:
15822         case vex_vsib_q_w_d_mode:
15823           names = vex.w ? names_ymm : names_xmm;
15824           break;
15825         case mask_bd_mode:
15826         case mask_mode:
15827           if (reg > 0x7)
15828             {
15829               oappend ("(bad)");
15830               return;
15831             }
15832           names = names_mask;
15833           break;
15834         default:
15835           /* See PR binutils/20893 for a reproducer.  */
15836           oappend ("(bad)");
15837           return;
15838         }
15839       break;
15840     case 512:
15841       names = names_zmm;
15842       break;
15843     default:
15844       abort ();
15845       break;
15846     }
15847   oappend (names[reg]);
15848 }
15849
15850 static void
15851 OP_VexW (int bytemode, int sizeflag)
15852 {
15853   OP_VEX (bytemode, sizeflag);
15854
15855   if (vex.w)
15856     {
15857       /* Swap 2nd and 3rd operands.  */
15858       strcpy (scratchbuf, op_out[2]);
15859       strcpy (op_out[2], op_out[1]);
15860       strcpy (op_out[1], scratchbuf);
15861     }
15862 }
15863
15864 static void
15865 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
15866 {
15867   int reg;
15868   const char **names;
15869
15870   FETCH_DATA (the_info, codep + 1);
15871   reg = *codep++;
15872
15873   if (bytemode != x_mode)
15874     abort ();
15875
15876   reg >>= 4;
15877   if (address_mode != mode_64bit)
15878     reg &= 7;
15879
15880   switch (vex.length)
15881     {
15882     case 128:
15883       names = names_xmm;
15884       break;
15885     case 256:
15886       names = names_ymm;
15887       break;
15888     default:
15889       abort ();
15890     }
15891   oappend (names[reg]);
15892
15893   if (vex.w)
15894     {
15895       /* Swap 3rd and 4th operands.  */
15896       strcpy (scratchbuf, op_out[3]);
15897       strcpy (op_out[3], op_out[2]);
15898       strcpy (op_out[2], scratchbuf);
15899     }
15900 }
15901
15902 static void
15903 OP_VexI4 (int bytemode ATTRIBUTE_UNUSED,
15904           int sizeflag ATTRIBUTE_UNUSED)
15905 {
15906   scratchbuf[0] = '$';
15907   print_operand_value (scratchbuf + 1, 1, codep[-1] & 0xf);
15908   oappend_maybe_intel (scratchbuf);
15909 }
15910
15911 static void
15912 OP_EX_Vex (int bytemode, int sizeflag)
15913 {
15914   if (modrm.mod != 3)
15915     need_vex_reg = 0;
15916   OP_EX (bytemode, sizeflag);
15917 }
15918
15919 static void
15920 OP_XMM_Vex (int bytemode, int sizeflag)
15921 {
15922   if (modrm.mod != 3)
15923     need_vex_reg = 0;
15924   OP_XMM (bytemode, sizeflag);
15925 }
15926
15927 static struct op vex_cmp_op[] =
15928 {
15929   { STRING_COMMA_LEN ("eq") },
15930   { STRING_COMMA_LEN ("lt") },
15931   { STRING_COMMA_LEN ("le") },
15932   { STRING_COMMA_LEN ("unord") },
15933   { STRING_COMMA_LEN ("neq") },
15934   { STRING_COMMA_LEN ("nlt") },
15935   { STRING_COMMA_LEN ("nle") },
15936   { STRING_COMMA_LEN ("ord") },
15937   { STRING_COMMA_LEN ("eq_uq") },
15938   { STRING_COMMA_LEN ("nge") },
15939   { STRING_COMMA_LEN ("ngt") },
15940   { STRING_COMMA_LEN ("false") },
15941   { STRING_COMMA_LEN ("neq_oq") },
15942   { STRING_COMMA_LEN ("ge") },
15943   { STRING_COMMA_LEN ("gt") },
15944   { STRING_COMMA_LEN ("true") },
15945   { STRING_COMMA_LEN ("eq_os") },
15946   { STRING_COMMA_LEN ("lt_oq") },
15947   { STRING_COMMA_LEN ("le_oq") },
15948   { STRING_COMMA_LEN ("unord_s") },
15949   { STRING_COMMA_LEN ("neq_us") },
15950   { STRING_COMMA_LEN ("nlt_uq") },
15951   { STRING_COMMA_LEN ("nle_uq") },
15952   { STRING_COMMA_LEN ("ord_s") },
15953   { STRING_COMMA_LEN ("eq_us") },
15954   { STRING_COMMA_LEN ("nge_uq") },
15955   { STRING_COMMA_LEN ("ngt_uq") },
15956   { STRING_COMMA_LEN ("false_os") },
15957   { STRING_COMMA_LEN ("neq_os") },
15958   { STRING_COMMA_LEN ("ge_oq") },
15959   { STRING_COMMA_LEN ("gt_oq") },
15960   { STRING_COMMA_LEN ("true_us") },
15961 };
15962
15963 static void
15964 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15965 {
15966   unsigned int cmp_type;
15967
15968   FETCH_DATA (the_info, codep + 1);
15969   cmp_type = *codep++ & 0xff;
15970   if (cmp_type < ARRAY_SIZE (vex_cmp_op))
15971     {
15972       char suffix [3];
15973       char *p = mnemonicendp - 2;
15974       suffix[0] = p[0];
15975       suffix[1] = p[1];
15976       suffix[2] = '\0';
15977       sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
15978       mnemonicendp += vex_cmp_op[cmp_type].len;
15979     }
15980   else
15981     {
15982       /* We have a reserved extension byte.  Output it directly.  */
15983       scratchbuf[0] = '$';
15984       print_operand_value (scratchbuf + 1, 1, cmp_type);
15985       oappend_maybe_intel (scratchbuf);
15986       scratchbuf[0] = '\0';
15987     }
15988 }
15989
15990 static void
15991 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED,
15992              int sizeflag ATTRIBUTE_UNUSED)
15993 {
15994   unsigned int cmp_type;
15995
15996   if (!vex.evex)
15997     abort ();
15998
15999   FETCH_DATA (the_info, codep + 1);
16000   cmp_type = *codep++ & 0xff;
16001   /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
16002      If it's the case, print suffix, otherwise - print the immediate.  */
16003   if (cmp_type < ARRAY_SIZE (simd_cmp_op)
16004       && cmp_type != 3
16005       && cmp_type != 7)
16006     {
16007       char suffix [3];
16008       char *p = mnemonicendp - 2;
16009
16010       /* vpcmp* can have both one- and two-lettered suffix.  */
16011       if (p[0] == 'p')
16012         {
16013           p++;
16014           suffix[0] = p[0];
16015           suffix[1] = '\0';
16016         }
16017       else
16018         {
16019           suffix[0] = p[0];
16020           suffix[1] = p[1];
16021           suffix[2] = '\0';
16022         }
16023
16024       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
16025       mnemonicendp += simd_cmp_op[cmp_type].len;
16026     }
16027   else
16028     {
16029       /* We have a reserved extension byte.  Output it directly.  */
16030       scratchbuf[0] = '$';
16031       print_operand_value (scratchbuf + 1, 1, cmp_type);
16032       oappend_maybe_intel (scratchbuf);
16033       scratchbuf[0] = '\0';
16034     }
16035 }
16036
16037 static const struct op xop_cmp_op[] =
16038 {
16039   { STRING_COMMA_LEN ("lt") },
16040   { STRING_COMMA_LEN ("le") },
16041   { STRING_COMMA_LEN ("gt") },
16042   { STRING_COMMA_LEN ("ge") },
16043   { STRING_COMMA_LEN ("eq") },
16044   { STRING_COMMA_LEN ("neq") },
16045   { STRING_COMMA_LEN ("false") },
16046   { STRING_COMMA_LEN ("true") }
16047 };
16048
16049 static void
16050 VPCOM_Fixup (int bytemode ATTRIBUTE_UNUSED,
16051              int sizeflag ATTRIBUTE_UNUSED)
16052 {
16053   unsigned int cmp_type;
16054
16055   FETCH_DATA (the_info, codep + 1);
16056   cmp_type = *codep++ & 0xff;
16057   if (cmp_type < ARRAY_SIZE (xop_cmp_op))
16058     {
16059       char suffix[3];
16060       char *p = mnemonicendp - 2;
16061
16062       /* vpcom* can have both one- and two-lettered suffix.  */
16063       if (p[0] == 'm')
16064         {
16065           p++;
16066           suffix[0] = p[0];
16067           suffix[1] = '\0';
16068         }
16069       else
16070         {
16071           suffix[0] = p[0];
16072           suffix[1] = p[1];
16073           suffix[2] = '\0';
16074         }
16075
16076       sprintf (p, "%s%s", xop_cmp_op[cmp_type].name, suffix);
16077       mnemonicendp += xop_cmp_op[cmp_type].len;
16078     }
16079   else
16080     {
16081       /* We have a reserved extension byte.  Output it directly.  */
16082       scratchbuf[0] = '$';
16083       print_operand_value (scratchbuf + 1, 1, cmp_type);
16084       oappend_maybe_intel (scratchbuf);
16085       scratchbuf[0] = '\0';
16086     }
16087 }
16088
16089 static const struct op pclmul_op[] =
16090 {
16091   { STRING_COMMA_LEN ("lql") },
16092   { STRING_COMMA_LEN ("hql") },
16093   { STRING_COMMA_LEN ("lqh") },
16094   { STRING_COMMA_LEN ("hqh") }
16095 };
16096
16097 static void
16098 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
16099               int sizeflag ATTRIBUTE_UNUSED)
16100 {
16101   unsigned int pclmul_type;
16102
16103   FETCH_DATA (the_info, codep + 1);
16104   pclmul_type = *codep++ & 0xff;
16105   switch (pclmul_type)
16106     {
16107     case 0x10:
16108       pclmul_type = 2;
16109       break;
16110     case 0x11:
16111       pclmul_type = 3;
16112       break;
16113     default:
16114       break;
16115     }
16116   if (pclmul_type < ARRAY_SIZE (pclmul_op))
16117     {
16118       char suffix [4];
16119       char *p = mnemonicendp - 3;
16120       suffix[0] = p[0];
16121       suffix[1] = p[1];
16122       suffix[2] = p[2];
16123       suffix[3] = '\0';
16124       sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
16125       mnemonicendp += pclmul_op[pclmul_type].len;
16126     }
16127   else
16128     {
16129       /* We have a reserved extension byte.  Output it directly.  */
16130       scratchbuf[0] = '$';
16131       print_operand_value (scratchbuf + 1, 1, pclmul_type);
16132       oappend_maybe_intel (scratchbuf);
16133       scratchbuf[0] = '\0';
16134     }
16135 }
16136
16137 static void
16138 MOVBE_Fixup (int bytemode, int sizeflag)
16139 {
16140   /* Add proper suffix to "movbe".  */
16141   char *p = mnemonicendp;
16142
16143   switch (bytemode)
16144     {
16145     case v_mode:
16146       if (intel_syntax)
16147         goto skip;
16148
16149       USED_REX (REX_W);
16150       if (sizeflag & SUFFIX_ALWAYS)
16151         {
16152           if (rex & REX_W)
16153             *p++ = 'q';
16154           else
16155             {
16156               if (sizeflag & DFLAG)
16157                 *p++ = 'l';
16158               else
16159                 *p++ = 'w';
16160               used_prefixes |= (prefixes & PREFIX_DATA);
16161             }
16162         }
16163       break;
16164     default:
16165       oappend (INTERNAL_DISASSEMBLER_ERROR);
16166       break;
16167     }
16168   mnemonicendp = p;
16169   *p = '\0';
16170
16171  skip:
16172   OP_M (bytemode, sizeflag);
16173 }
16174
16175 static void
16176 MOVSXD_Fixup (int bytemode, int sizeflag)
16177 {
16178   /* Add proper suffix to "movsxd".  */
16179   char *p = mnemonicendp;
16180
16181   switch (bytemode)
16182     {
16183     case movsxd_mode:
16184       if (intel_syntax)
16185         {
16186           *p++ = 'x';
16187           *p++ = 'd';
16188           goto skip;
16189         }
16190
16191       USED_REX (REX_W);
16192       if (rex & REX_W)
16193         {
16194           *p++ = 'l';
16195           *p++ = 'q';
16196         }
16197       else
16198         {
16199           *p++ = 'x';
16200           *p++ = 'd';
16201         }
16202       break;
16203     default:
16204       oappend (INTERNAL_DISASSEMBLER_ERROR);
16205       break;
16206     }
16207
16208  skip:
16209   mnemonicendp = p;
16210   *p = '\0';
16211   OP_E (bytemode, sizeflag);
16212 }
16213
16214 static void
16215 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16216 {
16217   int reg;
16218   const char **names;
16219
16220   /* Skip mod/rm byte.  */
16221   MODRM_CHECK;
16222   codep++;
16223
16224   if (rex & REX_W)
16225     names = names64;
16226   else
16227     names = names32;
16228
16229   reg = modrm.rm;
16230   USED_REX (REX_B);
16231   if (rex & REX_B)
16232     reg += 8;
16233
16234   oappend (names[reg]);
16235 }
16236
16237 static void
16238 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16239 {
16240   const char **names;
16241   unsigned int reg = vex.register_specifier;
16242   vex.register_specifier = 0;
16243
16244   if (rex & REX_W)
16245     names = names64;
16246   else
16247     names = names32;
16248
16249   if (address_mode != mode_64bit)
16250     reg &= 7;
16251   oappend (names[reg]);
16252 }
16253
16254 static void
16255 OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16256 {
16257   if (!vex.evex
16258       || (bytemode != mask_mode && bytemode != mask_bd_mode))
16259     abort ();
16260
16261   USED_REX (REX_R);
16262   if ((rex & REX_R) != 0 || !vex.r)
16263     {
16264       BadOp ();
16265       return;
16266     }
16267
16268   oappend (names_mask [modrm.reg]);
16269 }
16270
16271 static void
16272 OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16273 {
16274   if (modrm.mod == 3 && vex.b)
16275     switch (bytemode)
16276       {
16277       case evex_rounding_64_mode:
16278         if (address_mode != mode_64bit)
16279           {
16280             oappend ("(bad)");
16281             break;
16282           }
16283         /* Fall through.  */
16284       case evex_rounding_mode:
16285         oappend (names_rounding[vex.ll]);
16286         break;
16287       case evex_sae_mode:
16288         oappend ("{sae}");
16289         break;
16290       default:
16291         abort ();
16292         break;
16293       }
16294 }