opcodes/i386-dis.c

   1 /* Print i386 instructions for GDB, the GNU debugger.
   2    Copyright (C) 1988-2020 Free Software Foundation, Inc.
   3
   4    This file is part of the GNU opcodes library.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    It is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program; if not, write to the Free Software
  18    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  19    MA 02110-1301, USA.  */
  20
  21
  22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
  23    July 1988
  24     modified by John Hassey (hassey@dg-rtp.dg.com)
  25     x86-64 support added by Jan Hubicka (jh@suse.cz)
  26     VIA PadLock support by Michal Ludvig (mludvig@suse.cz).  */
  27
  28 /* The main tables describing the instructions is essentially a copy
  29    of the "Opcode Map" chapter (Appendix A) of the Intel 80386
  30    Programmers Manual.  Usually, there is a capital letter, followed
  31    by a small letter.  The capital letter tell the addressing mode,
  32    and the small letter tells about the operand size.  Refer to
  33    the Intel manual for details.  */
  34
  35 #include "sysdep.h"
  36 #include "disassemble.h"
  37 #include "opintl.h"
  38 #include "opcode/i386.h"
  39 #include "libiberty.h"
  40 #include "safe-ctype.h"
  41
  42 #include <setjmp.h>
  43
  44 static int print_insn (bfd_vma, disassemble_info *);
  45 static void dofloat (int);
  46 static void OP_ST (int, int);
  47 static void OP_STi (int, int);
  48 static int putop (const char *, int);
  49 static void oappend (const char *);
  50 static void append_seg (void);
  51 static void OP_indirE (int, int);
  52 static void print_operand_value (char *, int, bfd_vma);
  53 static void OP_E_register (int, int);
  54 static void OP_E_memory (int, int);
  55 static void print_displacement (char *, bfd_vma);
  56 static void OP_E (int, int);
  57 static void OP_G (int, int);
  58 static bfd_vma get64 (void);
  59 static bfd_signed_vma get32 (void);
  60 static bfd_signed_vma get32s (void);
  61 static int get16 (void);
  62 static void set_op (bfd_vma, int);
  63 static void OP_Skip_MODRM (int, int);
  64 static void OP_REG (int, int);
  65 static void OP_IMREG (int, int);
  66 static void OP_I (int, int);
  67 static void OP_I64 (int, int);
  68 static void OP_sI (int, int);
  69 static void OP_J (int, int);
  70 static void OP_SEG (int, int);
  71 static void OP_DIR (int, int);
  72 static void OP_OFF (int, int);
  73 static void OP_OFF64 (int, int);
  74 static void ptr_reg (int, int);
  75 static void OP_ESreg (int, int);
  76 static void OP_DSreg (int, int);
  77 static void OP_C (int, int);
  78 static void OP_D (int, int);
  79 static void OP_T (int, int);
  80 static void OP_R (int, int);
  81 static void OP_MMX (int, int);
  82 static void OP_XMM (int, int);
  83 static void OP_EM (int, int);
  84 static void OP_EX (int, int);
  85 static void OP_EMC (int,int);
  86 static void OP_MXC (int,int);
  87 static void OP_MS (int, int);
  88 static void OP_XS (int, int);
  89 static void OP_M (int, int);
  90 static void OP_VEX (int, int);
  91 static void OP_EX_Vex (int, int);
  92 static void OP_EX_VexW (int, int);
  93 static void OP_EX_VexImmW (int, int);
  94 static void OP_XMM_Vex (int, int);
  95 static void OP_XMM_VexW (int, int);
  96 static void OP_Rounding (int, int);
  97 static void OP_REG_VexI4 (int, int);
  98 static void PCLMUL_Fixup (int, int);
  99 static void VCMP_Fixup (int, int);
 100 static void VPCMP_Fixup (int, int);
 101 static void VPCOM_Fixup (int, int);
 102 static void OP_0f07 (int, int);
 103 static void OP_Monitor (int, int);
 104 static void OP_Mwait (int, int);
 105 static void NOP_Fixup1 (int, int);
 106 static void NOP_Fixup2 (int, int);
 107 static void OP_3DNowSuffix (int, int);
 108 static void CMP_Fixup (int, int);
 109 static void BadOp (void);
 110 static void REP_Fixup (int, int);
 111 static void SEP_Fixup (int, int);
 112 static void BND_Fixup (int, int);
 113 static void NOTRACK_Fixup (int, int);
 114 static void HLE_Fixup1 (int, int);
 115 static void HLE_Fixup2 (int, int);
 116 static void HLE_Fixup3 (int, int);
 117 static void CMPXCHG8B_Fixup (int, int);
 118 static void XMM_Fixup (int, int);
 119 static void CRC32_Fixup (int, int);
 120 static void FXSAVE_Fixup (int, int);
 121 static void PCMPESTR_Fixup (int, int);
 122 static void OP_LWPCB_E (int, int);
 123 static void OP_LWP_E (int, int);
 124 static void OP_Vex_2src_1 (int, int);
 125 static void OP_Vex_2src_2 (int, int);
 126
 127 static void MOVBE_Fixup (int, int);
 128 static void MOVSXD_Fixup (int, int);
 129
 130 static void OP_Mask (int, int);
 131
 132 struct dis_private {
 133   /* Points to first byte not fetched.  */
 134   bfd_byte *max_fetched;
 135   bfd_byte the_buffer[MAX_MNEM_SIZE];
 136   bfd_vma insn_start;
 137   int orig_sizeflag;
 138   OPCODES_SIGJMP_BUF bailout;
 139 };
 140
 141 enum address_mode
 142 {
 143   mode_16bit,
 144   mode_32bit,
 145   mode_64bit
 146 };
 147
 148 enum address_mode address_mode;
 149
 150 /* Flags for the prefixes for the current instruction.  See below.  */
 151 static int prefixes;
 152
 153 /* REX prefix the current instruction.  See below.  */
 154 static int rex;
 155 /* Bits of REX we've already used.  */
 156 static int rex_used;
 157 /* Mark parts used in the REX prefix.  When we are testing for
 158    empty prefix (for 8bit register REX extension), just mask it
 159    out.  Otherwise test for REX bit is excuse for existence of REX
 160    only in case value is nonzero.  */
 161 #define USED_REX(value)                                 \
 162   {                                                     \
 163     if (value)                                          \
 164       {                                                 \
 165         if ((rex & value))                              \
 166           rex_used |= (value) | REX_OPCODE;             \
 167       }                                                 \
 168     else                                                \
 169       rex_used |= REX_OPCODE;                           \
 170   }
 171
 172 /* Flags for prefixes which we somehow handled when printing the
 173    current instruction.  */
 174 static int used_prefixes;
 175
 176 /* Flags stored in PREFIXES.  */
 177 #define PREFIX_REPZ 1
 178 #define PREFIX_REPNZ 2
 179 #define PREFIX_LOCK 4
 180 #define PREFIX_CS 8
 181 #define PREFIX_SS 0x10
 182 #define PREFIX_DS 0x20
 183 #define PREFIX_ES 0x40
 184 #define PREFIX_FS 0x80
 185 #define PREFIX_GS 0x100
 186 #define PREFIX_DATA 0x200
 187 #define PREFIX_ADDR 0x400
 188 #define PREFIX_FWAIT 0x800
 189
 190 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
 191    to ADDR (exclusive) are valid.  Returns 1 for success, longjmps
 192    on error.  */
 193 #define FETCH_DATA(info, addr) \
 194   ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
 195    ? 1 : fetch_data ((info), (addr)))
 196
 197 static int
 198 fetch_data (struct disassemble_info *info, bfd_byte *addr)
 199 {
 200   int status;
 201   struct dis_private *priv = (struct dis_private *) info->private_data;
 202   bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
 203
 204   if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
 205     status = (*info->read_memory_func) (start,
 206                                         priv->max_fetched,
 207                                         addr - priv->max_fetched,
 208                                         info);
 209   else
 210     status = -1;
 211   if (status != 0)
 212     {
 213       /* If we did manage to read at least one byte, then
 214          print_insn_i386 will do something sensible.  Otherwise, print
 215          an error.  We do that here because this is where we know
 216          STATUS.  */
 217       if (priv->max_fetched == priv->the_buffer)
 218         (*info->memory_error_func) (status, start, info);
 219       OPCODES_SIGLONGJMP (priv->bailout, 1);
 220     }
 221   else
 222     priv->max_fetched = addr;
 223   return 1;
 224 }
 225
 226 /* Possible values for prefix requirement.  */
 227 #define PREFIX_IGNORED_SHIFT    16
 228 #define PREFIX_IGNORED_REPZ     (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
 229 #define PREFIX_IGNORED_REPNZ    (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
 230 #define PREFIX_IGNORED_DATA     (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
 231 #define PREFIX_IGNORED_ADDR     (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
 232 #define PREFIX_IGNORED_LOCK     (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
 233
 234 /* Opcode prefixes.  */
 235 #define PREFIX_OPCODE           (PREFIX_REPZ \
 236                                  | PREFIX_REPNZ \
 237                                  | PREFIX_DATA)
 238
 239 /* Prefixes ignored.  */
 240 #define PREFIX_IGNORED          (PREFIX_IGNORED_REPZ \
 241                                  | PREFIX_IGNORED_REPNZ \
 242                                  | PREFIX_IGNORED_DATA)
 243
 244 #define XX { NULL, 0 }
 245 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
 246
 247 #define Eb { OP_E, b_mode }
 248 #define Ebnd { OP_E, bnd_mode }
 249 #define EbS { OP_E, b_swap_mode }
 250 #define EbndS { OP_E, bnd_swap_mode }
 251 #define Ev { OP_E, v_mode }
 252 #define Eva { OP_E, va_mode }
 253 #define Ev_bnd { OP_E, v_bnd_mode }
 254 #define EvS { OP_E, v_swap_mode }
 255 #define Ed { OP_E, d_mode }
 256 #define Edq { OP_E, dq_mode }
 257 #define Edqw { OP_E, dqw_mode }
 258 #define Edqb { OP_E, dqb_mode }
 259 #define Edb { OP_E, db_mode }
 260 #define Edw { OP_E, dw_mode }
 261 #define Edqd { OP_E, dqd_mode }
 262 #define Eq { OP_E, q_mode }
 263 #define indirEv { OP_indirE, indir_v_mode }
 264 #define indirEp { OP_indirE, f_mode }
 265 #define stackEv { OP_E, stack_v_mode }
 266 #define Em { OP_E, m_mode }
 267 #define Ew { OP_E, w_mode }
 268 #define M { OP_M, 0 }           /* lea, lgdt, etc. */
 269 #define Ma { OP_M, a_mode }
 270 #define Mb { OP_M, b_mode }
 271 #define Md { OP_M, d_mode }
 272 #define Mo { OP_M, o_mode }
 273 #define Mp { OP_M, f_mode }             /* 32 or 48 bit memory operand for LDS, LES etc */
 274 #define Mq { OP_M, q_mode }
 275 #define Mv_bnd { OP_M, v_bndmk_mode }
 276 #define Mx { OP_M, x_mode }
 277 #define Mxmm { OP_M, xmm_mode }
 278 #define Gb { OP_G, b_mode }
 279 #define Gbnd { OP_G, bnd_mode }
 280 #define Gv { OP_G, v_mode }
 281 #define Gd { OP_G, d_mode }
 282 #define Gdq { OP_G, dq_mode }
 283 #define Gm { OP_G, m_mode }
 284 #define Gva { OP_G, va_mode }
 285 #define Gw { OP_G, w_mode }
 286 #define Rd { OP_R, d_mode }
 287 #define Rdq { OP_R, dq_mode }
 288 #define Rm { OP_R, m_mode }
 289 #define Ib { OP_I, b_mode }
 290 #define sIb { OP_sI, b_mode }   /* sign extened byte */
 291 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
 292 #define Iv { OP_I, v_mode }
 293 #define sIv { OP_sI, v_mode }
 294 #define Iv64 { OP_I64, v_mode }
 295 #define Id { OP_I, d_mode }
 296 #define Iw { OP_I, w_mode }
 297 #define I1 { OP_I, const_1_mode }
 298 #define Jb { OP_J, b_mode }
 299 #define Jv { OP_J, v_mode }
 300 #define Jdqw { OP_J, dqw_mode }
 301 #define Cm { OP_C, m_mode }
 302 #define Dm { OP_D, m_mode }
 303 #define Td { OP_T, d_mode }
 304 #define Skip_MODRM { OP_Skip_MODRM, 0 }
 305
 306 #define RMeAX { OP_REG, eAX_reg }
 307 #define RMeBX { OP_REG, eBX_reg }
 308 #define RMeCX { OP_REG, eCX_reg }
 309 #define RMeDX { OP_REG, eDX_reg }
 310 #define RMeSP { OP_REG, eSP_reg }
 311 #define RMeBP { OP_REG, eBP_reg }
 312 #define RMeSI { OP_REG, eSI_reg }
 313 #define RMeDI { OP_REG, eDI_reg }
 314 #define RMrAX { OP_REG, rAX_reg }
 315 #define RMrBX { OP_REG, rBX_reg }
 316 #define RMrCX { OP_REG, rCX_reg }
 317 #define RMrDX { OP_REG, rDX_reg }
 318 #define RMrSP { OP_REG, rSP_reg }
 319 #define RMrBP { OP_REG, rBP_reg }
 320 #define RMrSI { OP_REG, rSI_reg }
 321 #define RMrDI { OP_REG, rDI_reg }
 322 #define RMAL { OP_REG, al_reg }
 323 #define RMCL { OP_REG, cl_reg }
 324 #define RMDL { OP_REG, dl_reg }
 325 #define RMBL { OP_REG, bl_reg }
 326 #define RMAH { OP_REG, ah_reg }
 327 #define RMCH { OP_REG, ch_reg }
 328 #define RMDH { OP_REG, dh_reg }
 329 #define RMBH { OP_REG, bh_reg }
 330 #define RMAX { OP_REG, ax_reg }
 331 #define RMDX { OP_REG, dx_reg }
 332
 333 #define eAX { OP_IMREG, eAX_reg }
 334 #define eBX { OP_IMREG, eBX_reg }
 335 #define eCX { OP_IMREG, eCX_reg }
 336 #define eDX { OP_IMREG, eDX_reg }
 337 #define eSP { OP_IMREG, eSP_reg }
 338 #define eBP { OP_IMREG, eBP_reg }
 339 #define eSI { OP_IMREG, eSI_reg }
 340 #define eDI { OP_IMREG, eDI_reg }
 341 #define AL { OP_IMREG, al_reg }
 342 #define CL { OP_IMREG, cl_reg }
 343 #define DL { OP_IMREG, dl_reg }
 344 #define BL { OP_IMREG, bl_reg }
 345 #define AH { OP_IMREG, ah_reg }
 346 #define CH { OP_IMREG, ch_reg }
 347 #define DH { OP_IMREG, dh_reg }
 348 #define BH { OP_IMREG, bh_reg }
 349 #define AX { OP_IMREG, ax_reg }
 350 #define DX { OP_IMREG, dx_reg }
 351 #define zAX { OP_IMREG, z_mode_ax_reg }
 352 #define indirDX { OP_IMREG, indir_dx_reg }
 353
 354 #define Sw { OP_SEG, w_mode }
 355 #define Sv { OP_SEG, v_mode }
 356 #define Ap { OP_DIR, 0 }
 357 #define Ob { OP_OFF64, b_mode }
 358 #define Ov { OP_OFF64, v_mode }
 359 #define Xb { OP_DSreg, eSI_reg }
 360 #define Xv { OP_DSreg, eSI_reg }
 361 #define Xz { OP_DSreg, eSI_reg }
 362 #define Yb { OP_ESreg, eDI_reg }
 363 #define Yv { OP_ESreg, eDI_reg }
 364 #define DSBX { OP_DSreg, eBX_reg }
 365
 366 #define es { OP_REG, es_reg }
 367 #define ss { OP_REG, ss_reg }
 368 #define cs { OP_REG, cs_reg }
 369 #define ds { OP_REG, ds_reg }
 370 #define fs { OP_REG, fs_reg }
 371 #define gs { OP_REG, gs_reg }
 372
 373 #define MX { OP_MMX, 0 }
 374 #define XM { OP_XMM, 0 }
 375 #define XMScalar { OP_XMM, scalar_mode }
 376 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
 377 #define XMM { OP_XMM, xmm_mode }
 378 #define XMxmmq { OP_XMM, xmmq_mode }
 379 #define EM { OP_EM, v_mode }
 380 #define EMS { OP_EM, v_swap_mode }
 381 #define EMd { OP_EM, d_mode }
 382 #define EMx { OP_EM, x_mode }
 383 #define EXbScalar { OP_EX, b_scalar_mode }
 384 #define EXw { OP_EX, w_mode }
 385 #define EXwScalar { OP_EX, w_scalar_mode }
 386 #define EXd { OP_EX, d_mode }
 387 #define EXdS { OP_EX, d_swap_mode }
 388 #define EXq { OP_EX, q_mode }
 389 #define EXqS { OP_EX, q_swap_mode }
 390 #define EXx { OP_EX, x_mode }
 391 #define EXxS { OP_EX, x_swap_mode }
 392 #define EXxmm { OP_EX, xmm_mode }
 393 #define EXymm { OP_EX, ymm_mode }
 394 #define EXxmmq { OP_EX, xmmq_mode }
 395 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
 396 #define EXxmm_mb { OP_EX, xmm_mb_mode }
 397 #define EXxmm_mw { OP_EX, xmm_mw_mode }
 398 #define EXxmm_md { OP_EX, xmm_md_mode }
 399 #define EXxmm_mq { OP_EX, xmm_mq_mode }
 400 #define EXxmmdw { OP_EX, xmmdw_mode }
 401 #define EXxmmqd { OP_EX, xmmqd_mode }
 402 #define EXymmq { OP_EX, ymmq_mode }
 403 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
 404 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
 405 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
 406 #define MS { OP_MS, v_mode }
 407 #define XS { OP_XS, v_mode }
 408 #define EMCq { OP_EMC, q_mode }
 409 #define MXC { OP_MXC, 0 }
 410 #define OPSUF { OP_3DNowSuffix, 0 }
 411 #define SEP { SEP_Fixup, 0 }
 412 #define CMP { CMP_Fixup, 0 }
 413 #define XMM0 { XMM_Fixup, 0 }
 414 #define FXSAVE { FXSAVE_Fixup, 0 }
 415 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
 416 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
 417
 418 #define Vex { OP_VEX, vex_mode }
 419 #define VexScalar { OP_VEX, vex_scalar_mode }
 420 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
 421 #define Vex128 { OP_VEX, vex128_mode }
 422 #define Vex256 { OP_VEX, vex256_mode }
 423 #define VexGdq { OP_VEX, dq_mode }
 424 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
 425 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
 426 #define EXVexW { OP_EX_VexW, x_mode }
 427 #define EXdVexW { OP_EX_VexW, d_mode }
 428 #define EXqVexW { OP_EX_VexW, q_mode }
 429 #define EXVexImmW { OP_EX_VexImmW, x_mode }
 430 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
 431 #define XMVexW { OP_XMM_VexW, 0 }
 432 #define XMVexI4 { OP_REG_VexI4, x_mode }
 433 #define PCLMUL { PCLMUL_Fixup, 0 }
 434 #define VCMP { VCMP_Fixup, 0 }
 435 #define VPCMP { VPCMP_Fixup, 0 }
 436 #define VPCOM { VPCOM_Fixup, 0 }
 437
 438 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
 439 #define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode }
 440 #define EXxEVexS { OP_Rounding, evex_sae_mode }
 441
 442 #define XMask { OP_Mask, mask_mode }
 443 #define MaskG { OP_G, mask_mode }
 444 #define MaskE { OP_E, mask_mode }
 445 #define MaskBDE { OP_E, mask_bd_mode }
 446 #define MaskR { OP_R, mask_mode }
 447 #define MaskVex { OP_VEX, mask_mode }
 448
 449 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
 450 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
 451 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
 452 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
 453
 454 /* Used handle "rep" prefix for string instructions.  */
 455 #define Xbr { REP_Fixup, eSI_reg }
 456 #define Xvr { REP_Fixup, eSI_reg }
 457 #define Ybr { REP_Fixup, eDI_reg }
 458 #define Yvr { REP_Fixup, eDI_reg }
 459 #define Yzr { REP_Fixup, eDI_reg }
 460 #define indirDXr { REP_Fixup, indir_dx_reg }
 461 #define ALr { REP_Fixup, al_reg }
 462 #define eAXr { REP_Fixup, eAX_reg }
 463
 464 /* Used handle HLE prefix for lockable instructions.  */
 465 #define Ebh1 { HLE_Fixup1, b_mode }
 466 #define Evh1 { HLE_Fixup1, v_mode }
 467 #define Ebh2 { HLE_Fixup2, b_mode }
 468 #define Evh2 { HLE_Fixup2, v_mode }
 469 #define Ebh3 { HLE_Fixup3, b_mode }
 470 #define Evh3 { HLE_Fixup3, v_mode }
 471
 472 #define BND { BND_Fixup, 0 }
 473 #define NOTRACK { NOTRACK_Fixup, 0 }
 474
 475 #define cond_jump_flag { NULL, cond_jump_mode }
 476 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
 477
 478 /* bits in sizeflag */
 479 #define SUFFIX_ALWAYS 4
 480 #define AFLAG 2
 481 #define DFLAG 1
 482
 483 enum
 484 {
 485   /* byte operand */
 486   b_mode = 1,
 487   /* byte operand with operand swapped */
 488   b_swap_mode,
 489   /* byte operand, sign extend like 'T' suffix */
 490   b_T_mode,
 491   /* operand size depends on prefixes */
 492   v_mode,
 493   /* operand size depends on prefixes with operand swapped */
 494   v_swap_mode,
 495   /* operand size depends on address prefix */
 496   va_mode,
 497   /* word operand */
 498   w_mode,
 499   /* double word operand  */
 500   d_mode,
 501   /* double word operand with operand swapped */
 502   d_swap_mode,
 503   /* quad word operand */
 504   q_mode,
 505   /* quad word operand with operand swapped */
 506   q_swap_mode,
 507   /* ten-byte operand */
 508   t_mode,
 509   /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand.  In EVEX with
 510      broadcast enabled.  */
 511   x_mode,
 512   /* Similar to x_mode, but with different EVEX mem shifts.  */
 513   evex_x_gscat_mode,
 514   /* Similar to x_mode, but with disabled broadcast.  */
 515   evex_x_nobcst_mode,
 516   /* Similar to x_mode, but with operands swapped and disabled broadcast
 517      in EVEX.  */
 518   x_swap_mode,
 519   /* 16-byte XMM operand */
 520   xmm_mode,
 521   /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
 522      memory operand (depending on vector length).  Broadcast isn't
 523      allowed.  */
 524   xmmq_mode,
 525   /* Same as xmmq_mode, but broadcast is allowed.  */
 526   evex_half_bcst_xmmq_mode,
 527   /* XMM register or byte memory operand */
 528   xmm_mb_mode,
 529   /* XMM register or word memory operand */
 530   xmm_mw_mode,
 531   /* XMM register or double word memory operand */
 532   xmm_md_mode,
 533   /* XMM register or quad word memory operand */
 534   xmm_mq_mode,
 535   /* 16-byte XMM, word, double word or quad word operand.  */
 536   xmmdw_mode,
 537   /* 16-byte XMM, double word, quad word operand or xmm word operand.  */
 538   xmmqd_mode,
 539   /* 32-byte YMM operand */
 540   ymm_mode,
 541   /* quad word, ymmword or zmmword memory operand.  */
 542   ymmq_mode,
 543   /* 32-byte YMM or 16-byte word operand */
 544   ymmxmm_mode,
 545   /* d_mode in 32bit, q_mode in 64bit mode.  */
 546   m_mode,
 547   /* pair of v_mode operands */
 548   a_mode,
 549   cond_jump_mode,
 550   loop_jcxz_mode,
 551   movsxd_mode,
 552   v_bnd_mode,
 553   /* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode.  */
 554   v_bndmk_mode,
 555   /* operand size depends on REX prefixes.  */
 556   dq_mode,
 557   /* registers like dq_mode, memory like w_mode, displacements like
 558      v_mode without considering Intel64 ISA.  */
 559   dqw_mode,
 560   /* bounds operand */
 561   bnd_mode,
 562   /* bounds operand with operand swapped */
 563   bnd_swap_mode,
 564   /* 4- or 6-byte pointer operand */
 565   f_mode,
 566   const_1_mode,
 567   /* v_mode for indirect branch opcodes.  */
 568   indir_v_mode,
 569   /* v_mode for stack-related opcodes.  */
 570   stack_v_mode,
 571   /* non-quad operand size depends on prefixes */
 572   z_mode,
 573   /* 16-byte operand */
 574   o_mode,
 575   /* registers like dq_mode, memory like b_mode.  */
 576   dqb_mode,
 577   /* registers like d_mode, memory like b_mode.  */
 578   db_mode,
 579   /* registers like d_mode, memory like w_mode.  */
 580   dw_mode,
 581   /* registers like dq_mode, memory like d_mode.  */
 582   dqd_mode,
 583   /* normal vex mode */
 584   vex_mode,
 585   /* 128bit vex mode */
 586   vex128_mode,
 587   /* 256bit vex mode */
 588   vex256_mode,
 589
 590   /* Operand size depends on the VEX.W bit, with VSIB dword indices.  */
 591   vex_vsib_d_w_dq_mode,
 592   /* Similar to vex_vsib_d_w_dq_mode, with smaller memory.  */
 593   vex_vsib_d_w_d_mode,
 594   /* Operand size depends on the VEX.W bit, with VSIB qword indices.  */
 595   vex_vsib_q_w_dq_mode,
 596   /* Similar to vex_vsib_q_w_dq_mode, with smaller memory.  */
 597   vex_vsib_q_w_d_mode,
 598
 599   /* scalar, ignore vector length.  */
 600   scalar_mode,
 601   /* like b_mode, ignore vector length.  */
 602   b_scalar_mode,
 603   /* like w_mode, ignore vector length.  */
 604   w_scalar_mode,
 605   /* like d_swap_mode, ignore vector length.  */
 606   d_scalar_swap_mode,
 607   /* like q_swap_mode, ignore vector length.  */
 608   q_scalar_swap_mode,
 609   /* like vex_mode, ignore vector length.  */
 610   vex_scalar_mode,
 611   /* Operand size depends on the VEX.W bit, ignore vector length.  */
 612   vex_scalar_w_dq_mode,
 613
 614   /* Static rounding.  */
 615   evex_rounding_mode,
 616   /* Static rounding, 64-bit mode only.  */
 617   evex_rounding_64_mode,
 618   /* Supress all exceptions.  */
 619   evex_sae_mode,
 620
 621   /* Mask register operand.  */
 622   mask_mode,
 623   /* Mask register operand.  */
 624   mask_bd_mode,
 625
 626   es_reg,
 627   cs_reg,
 628   ss_reg,
 629   ds_reg,
 630   fs_reg,
 631   gs_reg,
 632
 633   eAX_reg,
 634   eCX_reg,
 635   eDX_reg,
 636   eBX_reg,
 637   eSP_reg,
 638   eBP_reg,
 639   eSI_reg,
 640   eDI_reg,
 641
 642   al_reg,
 643   cl_reg,
 644   dl_reg,
 645   bl_reg,
 646   ah_reg,
 647   ch_reg,
 648   dh_reg,
 649   bh_reg,
 650
 651   ax_reg,
 652   cx_reg,
 653   dx_reg,
 654   bx_reg,
 655   sp_reg,
 656   bp_reg,
 657   si_reg,
 658   di_reg,
 659
 660   rAX_reg,
 661   rCX_reg,
 662   rDX_reg,
 663   rBX_reg,
 664   rSP_reg,
 665   rBP_reg,
 666   rSI_reg,
 667   rDI_reg,
 668
 669   z_mode_ax_reg,
 670   indir_dx_reg
 671 };
 672
 673 enum
 674 {
 675   FLOATCODE = 1,
 676   USE_REG_TABLE,
 677   USE_MOD_TABLE,
 678   USE_RM_TABLE,
 679   USE_PREFIX_TABLE,
 680   USE_X86_64_TABLE,
 681   USE_3BYTE_TABLE,
 682   USE_XOP_8F_TABLE,
 683   USE_VEX_C4_TABLE,
 684   USE_VEX_C5_TABLE,
 685   USE_VEX_LEN_TABLE,
 686   USE_VEX_W_TABLE,
 687   USE_EVEX_TABLE,
 688   USE_EVEX_LEN_TABLE
 689 };
 690
 691 #define FLOAT                   NULL, { { NULL, FLOATCODE } }, 0
 692
 693 #define DIS386(T, I)            NULL, { { NULL, (T)}, { NULL,  (I) } }, 0
 694 #define DIS386_PREFIX(T, I, P)          NULL, { { NULL, (T)}, { NULL,  (I) } }, P
 695 #define REG_TABLE(I)            DIS386 (USE_REG_TABLE, (I))
 696 #define MOD_TABLE(I)            DIS386 (USE_MOD_TABLE, (I))
 697 #define RM_TABLE(I)             DIS386 (USE_RM_TABLE, (I))
 698 #define PREFIX_TABLE(I)         DIS386 (USE_PREFIX_TABLE, (I))
 699 #define X86_64_TABLE(I)         DIS386 (USE_X86_64_TABLE, (I))
 700 #define THREE_BYTE_TABLE(I)     DIS386 (USE_3BYTE_TABLE, (I))
 701 #define THREE_BYTE_TABLE_PREFIX(I, P)   DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
 702 #define XOP_8F_TABLE(I)         DIS386 (USE_XOP_8F_TABLE, (I))
 703 #define VEX_C4_TABLE(I)         DIS386 (USE_VEX_C4_TABLE, (I))
 704 #define VEX_C5_TABLE(I)         DIS386 (USE_VEX_C5_TABLE, (I))
 705 #define VEX_LEN_TABLE(I)        DIS386 (USE_VEX_LEN_TABLE, (I))
 706 #define VEX_W_TABLE(I)          DIS386 (USE_VEX_W_TABLE, (I))
 707 #define EVEX_TABLE(I)           DIS386 (USE_EVEX_TABLE, (I))
 708 #define EVEX_LEN_TABLE(I)       DIS386 (USE_EVEX_LEN_TABLE, (I))
 709
 710 enum
 711 {
 712   REG_80 = 0,
 713   REG_81,
 714   REG_83,
 715   REG_8F,
 716   REG_C0,
 717   REG_C1,
 718   REG_C6,
 719   REG_C7,
 720   REG_D0,
 721   REG_D1,
 722   REG_D2,
 723   REG_D3,
 724   REG_F6,
 725   REG_F7,
 726   REG_FE,
 727   REG_FF,
 728   REG_0F00,
 729   REG_0F01,
 730   REG_0F0D,
 731   REG_0F18,
 732   REG_0F1C_P_0_MOD_0,
 733   REG_0F1E_P_1_MOD_3,
 734   REG_0F71,
 735   REG_0F72,
 736   REG_0F73,
 737   REG_0FA6,
 738   REG_0FA7,
 739   REG_0FAE,
 740   REG_0FBA,
 741   REG_0FC7,
 742   REG_VEX_0F71,
 743   REG_VEX_0F72,
 744   REG_VEX_0F73,
 745   REG_VEX_0FAE,
 746   REG_VEX_0F38F3,
 747   REG_XOP_LWPCB,
 748   REG_XOP_LWP,
 749   REG_XOP_TBM_01,
 750   REG_XOP_TBM_02,
 751
 752   REG_EVEX_0F71,
 753   REG_EVEX_0F72,
 754   REG_EVEX_0F73,
 755   REG_EVEX_0F38C6,
 756   REG_EVEX_0F38C7
 757 };
 758
 759 enum
 760 {
 761   MOD_8D = 0,
 762   MOD_C6_REG_7,
 763   MOD_C7_REG_7,
 764   MOD_FF_REG_3,
 765   MOD_FF_REG_5,
 766   MOD_0F01_REG_0,
 767   MOD_0F01_REG_1,
 768   MOD_0F01_REG_2,
 769   MOD_0F01_REG_3,
 770   MOD_0F01_REG_5,
 771   MOD_0F01_REG_7,
 772   MOD_0F12_PREFIX_0,
 773   MOD_0F12_PREFIX_2,
 774   MOD_0F13,
 775   MOD_0F16_PREFIX_0,
 776   MOD_0F16_PREFIX_2,
 777   MOD_0F17,
 778   MOD_0F18_REG_0,
 779   MOD_0F18_REG_1,
 780   MOD_0F18_REG_2,
 781   MOD_0F18_REG_3,
 782   MOD_0F18_REG_4,
 783   MOD_0F18_REG_5,
 784   MOD_0F18_REG_6,
 785   MOD_0F18_REG_7,
 786   MOD_0F1A_PREFIX_0,
 787   MOD_0F1B_PREFIX_0,
 788   MOD_0F1B_PREFIX_1,
 789   MOD_0F1C_PREFIX_0,
 790   MOD_0F1E_PREFIX_1,
 791   MOD_0F24,
 792   MOD_0F26,
 793   MOD_0F2B_PREFIX_0,
 794   MOD_0F2B_PREFIX_1,
 795   MOD_0F2B_PREFIX_2,
 796   MOD_0F2B_PREFIX_3,
 797   MOD_0F50,
 798   MOD_0F71_REG_2,
 799   MOD_0F71_REG_4,
 800   MOD_0F71_REG_6,
 801   MOD_0F72_REG_2,
 802   MOD_0F72_REG_4,
 803   MOD_0F72_REG_6,
 804   MOD_0F73_REG_2,
 805   MOD_0F73_REG_3,
 806   MOD_0F73_REG_6,
 807   MOD_0F73_REG_7,
 808   MOD_0FAE_REG_0,
 809   MOD_0FAE_REG_1,
 810   MOD_0FAE_REG_2,
 811   MOD_0FAE_REG_3,
 812   MOD_0FAE_REG_4,
 813   MOD_0FAE_REG_5,
 814   MOD_0FAE_REG_6,
 815   MOD_0FAE_REG_7,
 816   MOD_0FB2,
 817   MOD_0FB4,
 818   MOD_0FB5,
 819   MOD_0FC3,
 820   MOD_0FC7_REG_3,
 821   MOD_0FC7_REG_4,
 822   MOD_0FC7_REG_5,
 823   MOD_0FC7_REG_6,
 824   MOD_0FC7_REG_7,
 825   MOD_0FD7,
 826   MOD_0FE7_PREFIX_2,
 827   MOD_0FF0_PREFIX_3,
 828   MOD_0F382A_PREFIX_2,
 829   MOD_0F38F5_PREFIX_2,
 830   MOD_0F38F6_PREFIX_0,
 831   MOD_0F38F8_PREFIX_1,
 832   MOD_0F38F8_PREFIX_2,
 833   MOD_0F38F8_PREFIX_3,
 834   MOD_0F38F9_PREFIX_0,
 835   MOD_62_32BIT,
 836   MOD_C4_32BIT,
 837   MOD_C5_32BIT,
 838   MOD_VEX_0F12_PREFIX_0,
 839   MOD_VEX_0F12_PREFIX_2,
 840   MOD_VEX_0F13,
 841   MOD_VEX_0F16_PREFIX_0,
 842   MOD_VEX_0F16_PREFIX_2,
 843   MOD_VEX_0F17,
 844   MOD_VEX_0F2B,
 845   MOD_VEX_W_0_0F41_P_0_LEN_1,
 846   MOD_VEX_W_1_0F41_P_0_LEN_1,
 847   MOD_VEX_W_0_0F41_P_2_LEN_1,
 848   MOD_VEX_W_1_0F41_P_2_LEN_1,
 849   MOD_VEX_W_0_0F42_P_0_LEN_1,
 850   MOD_VEX_W_1_0F42_P_0_LEN_1,
 851   MOD_VEX_W_0_0F42_P_2_LEN_1,
 852   MOD_VEX_W_1_0F42_P_2_LEN_1,
 853   MOD_VEX_W_0_0F44_P_0_LEN_1,
 854   MOD_VEX_W_1_0F44_P_0_LEN_1,
 855   MOD_VEX_W_0_0F44_P_2_LEN_1,
 856   MOD_VEX_W_1_0F44_P_2_LEN_1,
 857   MOD_VEX_W_0_0F45_P_0_LEN_1,
 858   MOD_VEX_W_1_0F45_P_0_LEN_1,
 859   MOD_VEX_W_0_0F45_P_2_LEN_1,
 860   MOD_VEX_W_1_0F45_P_2_LEN_1,
 861   MOD_VEX_W_0_0F46_P_0_LEN_1,
 862   MOD_VEX_W_1_0F46_P_0_LEN_1,
 863   MOD_VEX_W_0_0F46_P_2_LEN_1,
 864   MOD_VEX_W_1_0F46_P_2_LEN_1,
 865   MOD_VEX_W_0_0F47_P_0_LEN_1,
 866   MOD_VEX_W_1_0F47_P_0_LEN_1,
 867   MOD_VEX_W_0_0F47_P_2_LEN_1,
 868   MOD_VEX_W_1_0F47_P_2_LEN_1,
 869   MOD_VEX_W_0_0F4A_P_0_LEN_1,
 870   MOD_VEX_W_1_0F4A_P_0_LEN_1,
 871   MOD_VEX_W_0_0F4A_P_2_LEN_1,
 872   MOD_VEX_W_1_0F4A_P_2_LEN_1,
 873   MOD_VEX_W_0_0F4B_P_0_LEN_1,
 874   MOD_VEX_W_1_0F4B_P_0_LEN_1,
 875   MOD_VEX_W_0_0F4B_P_2_LEN_1,
 876   MOD_VEX_0F50,
 877   MOD_VEX_0F71_REG_2,
 878   MOD_VEX_0F71_REG_4,
 879   MOD_VEX_0F71_REG_6,
 880   MOD_VEX_0F72_REG_2,
 881   MOD_VEX_0F72_REG_4,
 882   MOD_VEX_0F72_REG_6,
 883   MOD_VEX_0F73_REG_2,
 884   MOD_VEX_0F73_REG_3,
 885   MOD_VEX_0F73_REG_6,
 886   MOD_VEX_0F73_REG_7,
 887   MOD_VEX_W_0_0F91_P_0_LEN_0,
 888   MOD_VEX_W_1_0F91_P_0_LEN_0,
 889   MOD_VEX_W_0_0F91_P_2_LEN_0,
 890   MOD_VEX_W_1_0F91_P_2_LEN_0,
 891   MOD_VEX_W_0_0F92_P_0_LEN_0,
 892   MOD_VEX_W_0_0F92_P_2_LEN_0,
 893   MOD_VEX_0F92_P_3_LEN_0,
 894   MOD_VEX_W_0_0F93_P_0_LEN_0,
 895   MOD_VEX_W_0_0F93_P_2_LEN_0,
 896   MOD_VEX_0F93_P_3_LEN_0,
 897   MOD_VEX_W_0_0F98_P_0_LEN_0,
 898   MOD_VEX_W_1_0F98_P_0_LEN_0,
 899   MOD_VEX_W_0_0F98_P_2_LEN_0,
 900   MOD_VEX_W_1_0F98_P_2_LEN_0,
 901   MOD_VEX_W_0_0F99_P_0_LEN_0,
 902   MOD_VEX_W_1_0F99_P_0_LEN_0,
 903   MOD_VEX_W_0_0F99_P_2_LEN_0,
 904   MOD_VEX_W_1_0F99_P_2_LEN_0,
 905   MOD_VEX_0FAE_REG_2,
 906   MOD_VEX_0FAE_REG_3,
 907   MOD_VEX_0FD7_PREFIX_2,
 908   MOD_VEX_0FE7_PREFIX_2,
 909   MOD_VEX_0FF0_PREFIX_3,
 910   MOD_VEX_0F381A_PREFIX_2,
 911   MOD_VEX_0F382A_PREFIX_2,
 912   MOD_VEX_0F382C_PREFIX_2,
 913   MOD_VEX_0F382D_PREFIX_2,
 914   MOD_VEX_0F382E_PREFIX_2,
 915   MOD_VEX_0F382F_PREFIX_2,
 916   MOD_VEX_0F385A_PREFIX_2,
 917   MOD_VEX_0F388C_PREFIX_2,
 918   MOD_VEX_0F388E_PREFIX_2,
 919   MOD_VEX_W_0_0F3A30_P_2_LEN_0,
 920   MOD_VEX_W_1_0F3A30_P_2_LEN_0,
 921   MOD_VEX_W_0_0F3A31_P_2_LEN_0,
 922   MOD_VEX_W_1_0F3A31_P_2_LEN_0,
 923   MOD_VEX_W_0_0F3A32_P_2_LEN_0,
 924   MOD_VEX_W_1_0F3A32_P_2_LEN_0,
 925   MOD_VEX_W_0_0F3A33_P_2_LEN_0,
 926   MOD_VEX_W_1_0F3A33_P_2_LEN_0,
 927
 928   MOD_EVEX_0F12_PREFIX_0,
 929   MOD_EVEX_0F12_PREFIX_2,
 930   MOD_EVEX_0F13,
 931   MOD_EVEX_0F16_PREFIX_0,
 932   MOD_EVEX_0F16_PREFIX_2,
 933   MOD_EVEX_0F17,
 934   MOD_EVEX_0F2B,
 935   MOD_EVEX_0F38C6_REG_1,
 936   MOD_EVEX_0F38C6_REG_2,
 937   MOD_EVEX_0F38C6_REG_5,
 938   MOD_EVEX_0F38C6_REG_6,
 939   MOD_EVEX_0F38C7_REG_1,
 940   MOD_EVEX_0F38C7_REG_2,
 941   MOD_EVEX_0F38C7_REG_5,
 942   MOD_EVEX_0F38C7_REG_6
 943 };
 944
 945 enum
 946 {
 947   RM_C6_REG_7 = 0,
 948   RM_C7_REG_7,
 949   RM_0F01_REG_0,
 950   RM_0F01_REG_1,
 951   RM_0F01_REG_2,
 952   RM_0F01_REG_3,
 953   RM_0F01_REG_5_MOD_3,
 954   RM_0F01_REG_7_MOD_3,
 955   RM_0F1E_P_1_MOD_3_REG_7,
 956   RM_0FAE_REG_6_MOD_3_P_0,
 957   RM_0FAE_REG_7_MOD_3,
 958 };
 959
 960 enum
 961 {
 962   PREFIX_90 = 0,
 963   PREFIX_0F01_REG_3_RM_1,
 964   PREFIX_0F01_REG_5_MOD_0,
 965   PREFIX_0F01_REG_5_MOD_3_RM_0,
 966   PREFIX_0F01_REG_5_MOD_3_RM_1,
 967   PREFIX_0F01_REG_5_MOD_3_RM_2,
 968   PREFIX_0F01_REG_7_MOD_3_RM_2,
 969   PREFIX_0F01_REG_7_MOD_3_RM_3,
 970   PREFIX_0F09,
 971   PREFIX_0F10,
 972   PREFIX_0F11,
 973   PREFIX_0F12,
 974   PREFIX_0F16,
 975   PREFIX_0F1A,
 976   PREFIX_0F1B,
 977   PREFIX_0F1C,
 978   PREFIX_0F1E,
 979   PREFIX_0F2A,
 980   PREFIX_0F2B,
 981   PREFIX_0F2C,
 982   PREFIX_0F2D,
 983   PREFIX_0F2E,
 984   PREFIX_0F2F,
 985   PREFIX_0F51,
 986   PREFIX_0F52,
 987   PREFIX_0F53,
 988   PREFIX_0F58,
 989   PREFIX_0F59,
 990   PREFIX_0F5A,
 991   PREFIX_0F5B,
 992   PREFIX_0F5C,
 993   PREFIX_0F5D,
 994   PREFIX_0F5E,
 995   PREFIX_0F5F,
 996   PREFIX_0F60,
 997   PREFIX_0F61,
 998   PREFIX_0F62,
 999   PREFIX_0F6C,
1000   PREFIX_0F6D,
1001   PREFIX_0F6F,
1002   PREFIX_0F70,
1003   PREFIX_0F73_REG_3,
1004   PREFIX_0F73_REG_7,
1005   PREFIX_0F78,
1006   PREFIX_0F79,
1007   PREFIX_0F7C,
1008   PREFIX_0F7D,
1009   PREFIX_0F7E,
1010   PREFIX_0F7F,
1011   PREFIX_0FAE_REG_0_MOD_3,
1012   PREFIX_0FAE_REG_1_MOD_3,
1013   PREFIX_0FAE_REG_2_MOD_3,
1014   PREFIX_0FAE_REG_3_MOD_3,
1015   PREFIX_0FAE_REG_4_MOD_0,
1016   PREFIX_0FAE_REG_4_MOD_3,
1017   PREFIX_0FAE_REG_5_MOD_0,
1018   PREFIX_0FAE_REG_5_MOD_3,
1019   PREFIX_0FAE_REG_6_MOD_0,
1020   PREFIX_0FAE_REG_6_MOD_3,
1021   PREFIX_0FAE_REG_7_MOD_0,
1022   PREFIX_0FB8,
1023   PREFIX_0FBC,
1024   PREFIX_0FBD,
1025   PREFIX_0FC2,
1026   PREFIX_0FC3_MOD_0,
1027   PREFIX_0FC7_REG_6_MOD_0,
1028   PREFIX_0FC7_REG_6_MOD_3,
1029   PREFIX_0FC7_REG_7_MOD_3,
1030   PREFIX_0FD0,
1031   PREFIX_0FD6,
1032   PREFIX_0FE6,
1033   PREFIX_0FE7,
1034   PREFIX_0FF0,
1035   PREFIX_0FF7,
1036   PREFIX_0F3810,
1037   PREFIX_0F3814,
1038   PREFIX_0F3815,
1039   PREFIX_0F3817,
1040   PREFIX_0F3820,
1041   PREFIX_0F3821,
1042   PREFIX_0F3822,
1043   PREFIX_0F3823,
1044   PREFIX_0F3824,
1045   PREFIX_0F3825,
1046   PREFIX_0F3828,
1047   PREFIX_0F3829,
1048   PREFIX_0F382A,
1049   PREFIX_0F382B,
1050   PREFIX_0F3830,
1051   PREFIX_0F3831,
1052   PREFIX_0F3832,
1053   PREFIX_0F3833,
1054   PREFIX_0F3834,
1055   PREFIX_0F3835,
1056   PREFIX_0F3837,
1057   PREFIX_0F3838,
1058   PREFIX_0F3839,
1059   PREFIX_0F383A,
1060   PREFIX_0F383B,
1061   PREFIX_0F383C,
1062   PREFIX_0F383D,
1063   PREFIX_0F383E,
1064   PREFIX_0F383F,
1065   PREFIX_0F3840,
1066   PREFIX_0F3841,
1067   PREFIX_0F3880,
1068   PREFIX_0F3881,
1069   PREFIX_0F3882,
1070   PREFIX_0F38C8,
1071   PREFIX_0F38C9,
1072   PREFIX_0F38CA,
1073   PREFIX_0F38CB,
1074   PREFIX_0F38CC,
1075   PREFIX_0F38CD,
1076   PREFIX_0F38CF,
1077   PREFIX_0F38DB,
1078   PREFIX_0F38DC,
1079   PREFIX_0F38DD,
1080   PREFIX_0F38DE,
1081   PREFIX_0F38DF,
1082   PREFIX_0F38F0,
1083   PREFIX_0F38F1,
1084   PREFIX_0F38F5,
1085   PREFIX_0F38F6,
1086   PREFIX_0F38F8,
1087   PREFIX_0F38F9,
1088   PREFIX_0F3A08,
1089   PREFIX_0F3A09,
1090   PREFIX_0F3A0A,
1091   PREFIX_0F3A0B,
1092   PREFIX_0F3A0C,
1093   PREFIX_0F3A0D,
1094   PREFIX_0F3A0E,
1095   PREFIX_0F3A14,
1096   PREFIX_0F3A15,
1097   PREFIX_0F3A16,
1098   PREFIX_0F3A17,
1099   PREFIX_0F3A20,
1100   PREFIX_0F3A21,
1101   PREFIX_0F3A22,
1102   PREFIX_0F3A40,
1103   PREFIX_0F3A41,
1104   PREFIX_0F3A42,
1105   PREFIX_0F3A44,
1106   PREFIX_0F3A60,
1107   PREFIX_0F3A61,
1108   PREFIX_0F3A62,
1109   PREFIX_0F3A63,
1110   PREFIX_0F3ACC,
1111   PREFIX_0F3ACE,
1112   PREFIX_0F3ACF,
1113   PREFIX_0F3ADF,
1114   PREFIX_VEX_0F10,
1115   PREFIX_VEX_0F11,
1116   PREFIX_VEX_0F12,
1117   PREFIX_VEX_0F16,
1118   PREFIX_VEX_0F2A,
1119   PREFIX_VEX_0F2C,
1120   PREFIX_VEX_0F2D,
1121   PREFIX_VEX_0F2E,
1122   PREFIX_VEX_0F2F,
1123   PREFIX_VEX_0F41,
1124   PREFIX_VEX_0F42,
1125   PREFIX_VEX_0F44,
1126   PREFIX_VEX_0F45,
1127   PREFIX_VEX_0F46,
1128   PREFIX_VEX_0F47,
1129   PREFIX_VEX_0F4A,
1130   PREFIX_VEX_0F4B,
1131   PREFIX_VEX_0F51,
1132   PREFIX_VEX_0F52,
1133   PREFIX_VEX_0F53,
1134   PREFIX_VEX_0F58,
1135   PREFIX_VEX_0F59,
1136   PREFIX_VEX_0F5A,
1137   PREFIX_VEX_0F5B,
1138   PREFIX_VEX_0F5C,
1139   PREFIX_VEX_0F5D,
1140   PREFIX_VEX_0F5E,
1141   PREFIX_VEX_0F5F,
1142   PREFIX_VEX_0F60,
1143   PREFIX_VEX_0F61,
1144   PREFIX_VEX_0F62,
1145   PREFIX_VEX_0F63,
1146   PREFIX_VEX_0F64,
1147   PREFIX_VEX_0F65,
1148   PREFIX_VEX_0F66,
1149   PREFIX_VEX_0F67,
1150   PREFIX_VEX_0F68,
1151   PREFIX_VEX_0F69,
1152   PREFIX_VEX_0F6A,
1153   PREFIX_VEX_0F6B,
1154   PREFIX_VEX_0F6C,
1155   PREFIX_VEX_0F6D,
1156   PREFIX_VEX_0F6E,
1157   PREFIX_VEX_0F6F,
1158   PREFIX_VEX_0F70,
1159   PREFIX_VEX_0F71_REG_2,
1160   PREFIX_VEX_0F71_REG_4,
1161   PREFIX_VEX_0F71_REG_6,
1162   PREFIX_VEX_0F72_REG_2,
1163   PREFIX_VEX_0F72_REG_4,
1164   PREFIX_VEX_0F72_REG_6,
1165   PREFIX_VEX_0F73_REG_2,
1166   PREFIX_VEX_0F73_REG_3,
1167   PREFIX_VEX_0F73_REG_6,
1168   PREFIX_VEX_0F73_REG_7,
1169   PREFIX_VEX_0F74,
1170   PREFIX_VEX_0F75,
1171   PREFIX_VEX_0F76,
1172   PREFIX_VEX_0F77,
1173   PREFIX_VEX_0F7C,
1174   PREFIX_VEX_0F7D,
1175   PREFIX_VEX_0F7E,
1176   PREFIX_VEX_0F7F,
1177   PREFIX_VEX_0F90,
1178   PREFIX_VEX_0F91,
1179   PREFIX_VEX_0F92,
1180   PREFIX_VEX_0F93,
1181   PREFIX_VEX_0F98,
1182   PREFIX_VEX_0F99,
1183   PREFIX_VEX_0FC2,
1184   PREFIX_VEX_0FC4,
1185   PREFIX_VEX_0FC5,
1186   PREFIX_VEX_0FD0,
1187   PREFIX_VEX_0FD1,
1188   PREFIX_VEX_0FD2,
1189   PREFIX_VEX_0FD3,
1190   PREFIX_VEX_0FD4,
1191   PREFIX_VEX_0FD5,
1192   PREFIX_VEX_0FD6,
1193   PREFIX_VEX_0FD7,
1194   PREFIX_VEX_0FD8,
1195   PREFIX_VEX_0FD9,
1196   PREFIX_VEX_0FDA,
1197   PREFIX_VEX_0FDB,
1198   PREFIX_VEX_0FDC,
1199   PREFIX_VEX_0FDD,
1200   PREFIX_VEX_0FDE,
1201   PREFIX_VEX_0FDF,
1202   PREFIX_VEX_0FE0,
1203   PREFIX_VEX_0FE1,
1204   PREFIX_VEX_0FE2,
1205   PREFIX_VEX_0FE3,
1206   PREFIX_VEX_0FE4,
1207   PREFIX_VEX_0FE5,
1208   PREFIX_VEX_0FE6,
1209   PREFIX_VEX_0FE7,
1210   PREFIX_VEX_0FE8,
1211   PREFIX_VEX_0FE9,
1212   PREFIX_VEX_0FEA,
1213   PREFIX_VEX_0FEB,
1214   PREFIX_VEX_0FEC,
1215   PREFIX_VEX_0FED,
1216   PREFIX_VEX_0FEE,
1217   PREFIX_VEX_0FEF,
1218   PREFIX_VEX_0FF0,
1219   PREFIX_VEX_0FF1,
1220   PREFIX_VEX_0FF2,
1221   PREFIX_VEX_0FF3,
1222   PREFIX_VEX_0FF4,
1223   PREFIX_VEX_0FF5,
1224   PREFIX_VEX_0FF6,
1225   PREFIX_VEX_0FF7,
1226   PREFIX_VEX_0FF8,
1227   PREFIX_VEX_0FF9,
1228   PREFIX_VEX_0FFA,
1229   PREFIX_VEX_0FFB,
1230   PREFIX_VEX_0FFC,
1231   PREFIX_VEX_0FFD,
1232   PREFIX_VEX_0FFE,
1233   PREFIX_VEX_0F3800,
1234   PREFIX_VEX_0F3801,
1235   PREFIX_VEX_0F3802,
1236   PREFIX_VEX_0F3803,
1237   PREFIX_VEX_0F3804,
1238   PREFIX_VEX_0F3805,
1239   PREFIX_VEX_0F3806,
1240   PREFIX_VEX_0F3807,
1241   PREFIX_VEX_0F3808,
1242   PREFIX_VEX_0F3809,
1243   PREFIX_VEX_0F380A,
1244   PREFIX_VEX_0F380B,
1245   PREFIX_VEX_0F380C,
1246   PREFIX_VEX_0F380D,
1247   PREFIX_VEX_0F380E,
1248   PREFIX_VEX_0F380F,
1249   PREFIX_VEX_0F3813,
1250   PREFIX_VEX_0F3816,
1251   PREFIX_VEX_0F3817,
1252   PREFIX_VEX_0F3818,
1253   PREFIX_VEX_0F3819,
1254   PREFIX_VEX_0F381A,
1255   PREFIX_VEX_0F381C,
1256   PREFIX_VEX_0F381D,
1257   PREFIX_VEX_0F381E,
1258   PREFIX_VEX_0F3820,
1259   PREFIX_VEX_0F3821,
1260   PREFIX_VEX_0F3822,
1261   PREFIX_VEX_0F3823,
1262   PREFIX_VEX_0F3824,
1263   PREFIX_VEX_0F3825,
1264   PREFIX_VEX_0F3828,
1265   PREFIX_VEX_0F3829,
1266   PREFIX_VEX_0F382A,
1267   PREFIX_VEX_0F382B,
1268   PREFIX_VEX_0F382C,
1269   PREFIX_VEX_0F382D,
1270   PREFIX_VEX_0F382E,
1271   PREFIX_VEX_0F382F,
1272   PREFIX_VEX_0F3830,
1273   PREFIX_VEX_0F3831,
1274   PREFIX_VEX_0F3832,
1275   PREFIX_VEX_0F3833,
1276   PREFIX_VEX_0F3834,
1277   PREFIX_VEX_0F3835,
1278   PREFIX_VEX_0F3836,
1279   PREFIX_VEX_0F3837,
1280   PREFIX_VEX_0F3838,
1281   PREFIX_VEX_0F3839,
1282   PREFIX_VEX_0F383A,
1283   PREFIX_VEX_0F383B,
1284   PREFIX_VEX_0F383C,
1285   PREFIX_VEX_0F383D,
1286   PREFIX_VEX_0F383E,
1287   PREFIX_VEX_0F383F,
1288   PREFIX_VEX_0F3840,
1289   PREFIX_VEX_0F3841,
1290   PREFIX_VEX_0F3845,
1291   PREFIX_VEX_0F3846,
1292   PREFIX_VEX_0F3847,
1293   PREFIX_VEX_0F3858,
1294   PREFIX_VEX_0F3859,
1295   PREFIX_VEX_0F385A,
1296   PREFIX_VEX_0F3878,
1297   PREFIX_VEX_0F3879,
1298   PREFIX_VEX_0F388C,
1299   PREFIX_VEX_0F388E,
1300   PREFIX_VEX_0F3890,
1301   PREFIX_VEX_0F3891,
1302   PREFIX_VEX_0F3892,
1303   PREFIX_VEX_0F3893,
1304   PREFIX_VEX_0F3896,
1305   PREFIX_VEX_0F3897,
1306   PREFIX_VEX_0F3898,
1307   PREFIX_VEX_0F3899,
1308   PREFIX_VEX_0F389A,
1309   PREFIX_VEX_0F389B,
1310   PREFIX_VEX_0F389C,
1311   PREFIX_VEX_0F389D,
1312   PREFIX_VEX_0F389E,
1313   PREFIX_VEX_0F389F,
1314   PREFIX_VEX_0F38A6,
1315   PREFIX_VEX_0F38A7,
1316   PREFIX_VEX_0F38A8,
1317   PREFIX_VEX_0F38A9,
1318   PREFIX_VEX_0F38AA,
1319   PREFIX_VEX_0F38AB,
1320   PREFIX_VEX_0F38AC,
1321   PREFIX_VEX_0F38AD,
1322   PREFIX_VEX_0F38AE,
1323   PREFIX_VEX_0F38AF,
1324   PREFIX_VEX_0F38B6,
1325   PREFIX_VEX_0F38B7,
1326   PREFIX_VEX_0F38B8,
1327   PREFIX_VEX_0F38B9,
1328   PREFIX_VEX_0F38BA,
1329   PREFIX_VEX_0F38BB,
1330   PREFIX_VEX_0F38BC,
1331   PREFIX_VEX_0F38BD,
1332   PREFIX_VEX_0F38BE,
1333   PREFIX_VEX_0F38BF,
1334   PREFIX_VEX_0F38CF,
1335   PREFIX_VEX_0F38DB,
1336   PREFIX_VEX_0F38DC,
1337   PREFIX_VEX_0F38DD,
1338   PREFIX_VEX_0F38DE,
1339   PREFIX_VEX_0F38DF,
1340   PREFIX_VEX_0F38F2,
1341   PREFIX_VEX_0F38F3_REG_1,
1342   PREFIX_VEX_0F38F3_REG_2,
1343   PREFIX_VEX_0F38F3_REG_3,
1344   PREFIX_VEX_0F38F5,
1345   PREFIX_VEX_0F38F6,
1346   PREFIX_VEX_0F38F7,
1347   PREFIX_VEX_0F3A00,
1348   PREFIX_VEX_0F3A01,
1349   PREFIX_VEX_0F3A02,
1350   PREFIX_VEX_0F3A04,
1351   PREFIX_VEX_0F3A05,
1352   PREFIX_VEX_0F3A06,
1353   PREFIX_VEX_0F3A08,
1354   PREFIX_VEX_0F3A09,
1355   PREFIX_VEX_0F3A0A,
1356   PREFIX_VEX_0F3A0B,
1357   PREFIX_VEX_0F3A0C,
1358   PREFIX_VEX_0F3A0D,
1359   PREFIX_VEX_0F3A0E,
1360   PREFIX_VEX_0F3A0F,
1361   PREFIX_VEX_0F3A14,
1362   PREFIX_VEX_0F3A15,
1363   PREFIX_VEX_0F3A16,
1364   PREFIX_VEX_0F3A17,
1365   PREFIX_VEX_0F3A18,
1366   PREFIX_VEX_0F3A19,
1367   PREFIX_VEX_0F3A1D,
1368   PREFIX_VEX_0F3A20,
1369   PREFIX_VEX_0F3A21,
1370   PREFIX_VEX_0F3A22,
1371   PREFIX_VEX_0F3A30,
1372   PREFIX_VEX_0F3A31,
1373   PREFIX_VEX_0F3A32,
1374   PREFIX_VEX_0F3A33,
1375   PREFIX_VEX_0F3A38,
1376   PREFIX_VEX_0F3A39,
1377   PREFIX_VEX_0F3A40,
1378   PREFIX_VEX_0F3A41,
1379   PREFIX_VEX_0F3A42,
1380   PREFIX_VEX_0F3A44,
1381   PREFIX_VEX_0F3A46,
1382   PREFIX_VEX_0F3A48,
1383   PREFIX_VEX_0F3A49,
1384   PREFIX_VEX_0F3A4A,
1385   PREFIX_VEX_0F3A4B,
1386   PREFIX_VEX_0F3A4C,
1387   PREFIX_VEX_0F3A5C,
1388   PREFIX_VEX_0F3A5D,
1389   PREFIX_VEX_0F3A5E,
1390   PREFIX_VEX_0F3A5F,
1391   PREFIX_VEX_0F3A60,
1392   PREFIX_VEX_0F3A61,
1393   PREFIX_VEX_0F3A62,
1394   PREFIX_VEX_0F3A63,
1395   PREFIX_VEX_0F3A68,
1396   PREFIX_VEX_0F3A69,
1397   PREFIX_VEX_0F3A6A,
1398   PREFIX_VEX_0F3A6B,
1399   PREFIX_VEX_0F3A6C,
1400   PREFIX_VEX_0F3A6D,
1401   PREFIX_VEX_0F3A6E,
1402   PREFIX_VEX_0F3A6F,
1403   PREFIX_VEX_0F3A78,
1404   PREFIX_VEX_0F3A79,
1405   PREFIX_VEX_0F3A7A,
1406   PREFIX_VEX_0F3A7B,
1407   PREFIX_VEX_0F3A7C,
1408   PREFIX_VEX_0F3A7D,
1409   PREFIX_VEX_0F3A7E,
1410   PREFIX_VEX_0F3A7F,
1411   PREFIX_VEX_0F3ACE,
1412   PREFIX_VEX_0F3ACF,
1413   PREFIX_VEX_0F3ADF,
1414   PREFIX_VEX_0F3AF0,
1415
1416   PREFIX_EVEX_0F10,
1417   PREFIX_EVEX_0F11,
1418   PREFIX_EVEX_0F12,
1419   PREFIX_EVEX_0F16,
1420   PREFIX_EVEX_0F2A,
1421   PREFIX_EVEX_0F2C,
1422   PREFIX_EVEX_0F2D,
1423   PREFIX_EVEX_0F2E,
1424   PREFIX_EVEX_0F2F,
1425   PREFIX_EVEX_0F51,
1426   PREFIX_EVEX_0F58,
1427   PREFIX_EVEX_0F59,
1428   PREFIX_EVEX_0F5A,
1429   PREFIX_EVEX_0F5B,
1430   PREFIX_EVEX_0F5C,
1431   PREFIX_EVEX_0F5D,
1432   PREFIX_EVEX_0F5E,
1433   PREFIX_EVEX_0F5F,
1434   PREFIX_EVEX_0F62,
1435   PREFIX_EVEX_0F64,
1436   PREFIX_EVEX_0F65,
1437   PREFIX_EVEX_0F66,
1438   PREFIX_EVEX_0F6A,
1439   PREFIX_EVEX_0F6B,
1440   PREFIX_EVEX_0F6C,
1441   PREFIX_EVEX_0F6D,
1442   PREFIX_EVEX_0F6E,
1443   PREFIX_EVEX_0F6F,
1444   PREFIX_EVEX_0F70,
1445   PREFIX_EVEX_0F71_REG_2,
1446   PREFIX_EVEX_0F71_REG_4,
1447   PREFIX_EVEX_0F71_REG_6,
1448   PREFIX_EVEX_0F72_REG_0,
1449   PREFIX_EVEX_0F72_REG_1,
1450   PREFIX_EVEX_0F72_REG_2,
1451   PREFIX_EVEX_0F72_REG_4,
1452   PREFIX_EVEX_0F72_REG_6,
1453   PREFIX_EVEX_0F73_REG_2,
1454   PREFIX_EVEX_0F73_REG_3,
1455   PREFIX_EVEX_0F73_REG_6,
1456   PREFIX_EVEX_0F73_REG_7,
1457   PREFIX_EVEX_0F74,
1458   PREFIX_EVEX_0F75,
1459   PREFIX_EVEX_0F76,
1460   PREFIX_EVEX_0F78,
1461   PREFIX_EVEX_0F79,
1462   PREFIX_EVEX_0F7A,
1463   PREFIX_EVEX_0F7B,
1464   PREFIX_EVEX_0F7E,
1465   PREFIX_EVEX_0F7F,
1466   PREFIX_EVEX_0FC2,
1467   PREFIX_EVEX_0FC4,
1468   PREFIX_EVEX_0FC5,
1469   PREFIX_EVEX_0FD2,
1470   PREFIX_EVEX_0FD3,
1471   PREFIX_EVEX_0FD4,
1472   PREFIX_EVEX_0FD6,
1473   PREFIX_EVEX_0FDB,
1474   PREFIX_EVEX_0FDF,
1475   PREFIX_EVEX_0FE2,
1476   PREFIX_EVEX_0FE6,
1477   PREFIX_EVEX_0FE7,
1478   PREFIX_EVEX_0FEB,
1479   PREFIX_EVEX_0FEF,
1480   PREFIX_EVEX_0FF2,
1481   PREFIX_EVEX_0FF3,
1482   PREFIX_EVEX_0FF4,
1483   PREFIX_EVEX_0FFA,
1484   PREFIX_EVEX_0FFB,
1485   PREFIX_EVEX_0FFE,
1486   PREFIX_EVEX_0F380D,
1487   PREFIX_EVEX_0F3810,
1488   PREFIX_EVEX_0F3811,
1489   PREFIX_EVEX_0F3812,
1490   PREFIX_EVEX_0F3813,
1491   PREFIX_EVEX_0F3814,
1492   PREFIX_EVEX_0F3815,
1493   PREFIX_EVEX_0F3816,
1494   PREFIX_EVEX_0F3819,
1495   PREFIX_EVEX_0F381A,
1496   PREFIX_EVEX_0F381B,
1497   PREFIX_EVEX_0F381E,
1498   PREFIX_EVEX_0F381F,
1499   PREFIX_EVEX_0F3820,
1500   PREFIX_EVEX_0F3821,
1501   PREFIX_EVEX_0F3822,
1502   PREFIX_EVEX_0F3823,
1503   PREFIX_EVEX_0F3824,
1504   PREFIX_EVEX_0F3825,
1505   PREFIX_EVEX_0F3826,
1506   PREFIX_EVEX_0F3827,
1507   PREFIX_EVEX_0F3828,
1508   PREFIX_EVEX_0F3829,
1509   PREFIX_EVEX_0F382A,
1510   PREFIX_EVEX_0F382B,
1511   PREFIX_EVEX_0F382C,
1512   PREFIX_EVEX_0F382D,
1513   PREFIX_EVEX_0F3830,
1514   PREFIX_EVEX_0F3831,
1515   PREFIX_EVEX_0F3832,
1516   PREFIX_EVEX_0F3833,
1517   PREFIX_EVEX_0F3834,
1518   PREFIX_EVEX_0F3835,
1519   PREFIX_EVEX_0F3836,
1520   PREFIX_EVEX_0F3837,
1521   PREFIX_EVEX_0F3838,
1522   PREFIX_EVEX_0F3839,
1523   PREFIX_EVEX_0F383A,
1524   PREFIX_EVEX_0F383B,
1525   PREFIX_EVEX_0F383D,
1526   PREFIX_EVEX_0F383F,
1527   PREFIX_EVEX_0F3840,
1528   PREFIX_EVEX_0F3842,
1529   PREFIX_EVEX_0F3843,
1530   PREFIX_EVEX_0F3844,
1531   PREFIX_EVEX_0F3845,
1532   PREFIX_EVEX_0F3846,
1533   PREFIX_EVEX_0F3847,
1534   PREFIX_EVEX_0F384C,
1535   PREFIX_EVEX_0F384D,
1536   PREFIX_EVEX_0F384E,
1537   PREFIX_EVEX_0F384F,
1538   PREFIX_EVEX_0F3850,
1539   PREFIX_EVEX_0F3851,
1540   PREFIX_EVEX_0F3852,
1541   PREFIX_EVEX_0F3853,
1542   PREFIX_EVEX_0F3854,
1543   PREFIX_EVEX_0F3855,
1544   PREFIX_EVEX_0F3859,
1545   PREFIX_EVEX_0F385A,
1546   PREFIX_EVEX_0F385B,
1547   PREFIX_EVEX_0F3862,
1548   PREFIX_EVEX_0F3863,
1549   PREFIX_EVEX_0F3864,
1550   PREFIX_EVEX_0F3865,
1551   PREFIX_EVEX_0F3866,
1552   PREFIX_EVEX_0F3868,
1553   PREFIX_EVEX_0F3870,
1554   PREFIX_EVEX_0F3871,
1555   PREFIX_EVEX_0F3872,
1556   PREFIX_EVEX_0F3873,
1557   PREFIX_EVEX_0F3875,
1558   PREFIX_EVEX_0F3876,
1559   PREFIX_EVEX_0F3877,
1560   PREFIX_EVEX_0F387A,
1561   PREFIX_EVEX_0F387B,
1562   PREFIX_EVEX_0F387C,
1563   PREFIX_EVEX_0F387D,
1564   PREFIX_EVEX_0F387E,
1565   PREFIX_EVEX_0F387F,
1566   PREFIX_EVEX_0F3883,
1567   PREFIX_EVEX_0F3888,
1568   PREFIX_EVEX_0F3889,
1569   PREFIX_EVEX_0F388A,
1570   PREFIX_EVEX_0F388B,
1571   PREFIX_EVEX_0F388D,
1572   PREFIX_EVEX_0F388F,
1573   PREFIX_EVEX_0F3890,
1574   PREFIX_EVEX_0F3891,
1575   PREFIX_EVEX_0F3892,
1576   PREFIX_EVEX_0F3893,
1577   PREFIX_EVEX_0F389A,
1578   PREFIX_EVEX_0F389B,
1579   PREFIX_EVEX_0F38A0,
1580   PREFIX_EVEX_0F38A1,
1581   PREFIX_EVEX_0F38A2,
1582   PREFIX_EVEX_0F38A3,
1583   PREFIX_EVEX_0F38AA,
1584   PREFIX_EVEX_0F38AB,
1585   PREFIX_EVEX_0F38B4,
1586   PREFIX_EVEX_0F38B5,
1587   PREFIX_EVEX_0F38C4,
1588   PREFIX_EVEX_0F38C6_REG_1,
1589   PREFIX_EVEX_0F38C6_REG_2,
1590   PREFIX_EVEX_0F38C6_REG_5,
1591   PREFIX_EVEX_0F38C6_REG_6,
1592   PREFIX_EVEX_0F38C7_REG_1,
1593   PREFIX_EVEX_0F38C7_REG_2,
1594   PREFIX_EVEX_0F38C7_REG_5,
1595   PREFIX_EVEX_0F38C7_REG_6,
1596   PREFIX_EVEX_0F38C8,
1597   PREFIX_EVEX_0F38CA,
1598   PREFIX_EVEX_0F38CB,
1599   PREFIX_EVEX_0F38CC,
1600   PREFIX_EVEX_0F38CD,
1601
1602   PREFIX_EVEX_0F3A00,
1603   PREFIX_EVEX_0F3A01,
1604   PREFIX_EVEX_0F3A03,
1605   PREFIX_EVEX_0F3A05,
1606   PREFIX_EVEX_0F3A08,
1607   PREFIX_EVEX_0F3A09,
1608   PREFIX_EVEX_0F3A0A,
1609   PREFIX_EVEX_0F3A0B,
1610   PREFIX_EVEX_0F3A14,
1611   PREFIX_EVEX_0F3A15,
1612   PREFIX_EVEX_0F3A16,
1613   PREFIX_EVEX_0F3A17,
1614   PREFIX_EVEX_0F3A18,
1615   PREFIX_EVEX_0F3A19,
1616   PREFIX_EVEX_0F3A1A,
1617   PREFIX_EVEX_0F3A1B,
1618   PREFIX_EVEX_0F3A1E,
1619   PREFIX_EVEX_0F3A1F,
1620   PREFIX_EVEX_0F3A20,
1621   PREFIX_EVEX_0F3A21,
1622   PREFIX_EVEX_0F3A22,
1623   PREFIX_EVEX_0F3A23,
1624   PREFIX_EVEX_0F3A25,
1625   PREFIX_EVEX_0F3A26,
1626   PREFIX_EVEX_0F3A27,
1627   PREFIX_EVEX_0F3A38,
1628   PREFIX_EVEX_0F3A39,
1629   PREFIX_EVEX_0F3A3A,
1630   PREFIX_EVEX_0F3A3B,
1631   PREFIX_EVEX_0F3A3E,
1632   PREFIX_EVEX_0F3A3F,
1633   PREFIX_EVEX_0F3A42,
1634   PREFIX_EVEX_0F3A43,
1635   PREFIX_EVEX_0F3A50,
1636   PREFIX_EVEX_0F3A51,
1637   PREFIX_EVEX_0F3A54,
1638   PREFIX_EVEX_0F3A55,
1639   PREFIX_EVEX_0F3A56,
1640   PREFIX_EVEX_0F3A57,
1641   PREFIX_EVEX_0F3A66,
1642   PREFIX_EVEX_0F3A67,
1643   PREFIX_EVEX_0F3A70,
1644   PREFIX_EVEX_0F3A71,
1645   PREFIX_EVEX_0F3A72,
1646   PREFIX_EVEX_0F3A73,
1647 };
1648
1649 enum
1650 {
1651   X86_64_06 = 0,
1652   X86_64_07,
1653   X86_64_0E,
1654   X86_64_16,
1655   X86_64_17,
1656   X86_64_1E,
1657   X86_64_1F,
1658   X86_64_27,
1659   X86_64_2F,
1660   X86_64_37,
1661   X86_64_3F,
1662   X86_64_60,
1663   X86_64_61,
1664   X86_64_62,
1665   X86_64_63,
1666   X86_64_6D,
1667   X86_64_6F,
1668   X86_64_82,
1669   X86_64_9A,
1670   X86_64_C2,
1671   X86_64_C3,
1672   X86_64_C4,
1673   X86_64_C5,
1674   X86_64_CE,
1675   X86_64_D4,
1676   X86_64_D5,
1677   X86_64_E8,
1678   X86_64_E9,
1679   X86_64_EA,
1680   X86_64_0F01_REG_0,
1681   X86_64_0F01_REG_1,
1682   X86_64_0F01_REG_2,
1683   X86_64_0F01_REG_3
1684 };
1685
1686 enum
1687 {
1688   THREE_BYTE_0F38 = 0,
1689   THREE_BYTE_0F3A
1690 };
1691
1692 enum
1693 {
1694   XOP_08 = 0,
1695   XOP_09,
1696   XOP_0A
1697 };
1698
1699 enum
1700 {
1701   VEX_0F = 0,
1702   VEX_0F38,
1703   VEX_0F3A
1704 };
1705
1706 enum
1707 {
1708   EVEX_0F = 0,
1709   EVEX_0F38,
1710   EVEX_0F3A
1711 };
1712
1713 enum
1714 {
1715   VEX_LEN_0F12_P_0_M_0 = 0,
1716   VEX_LEN_0F12_P_0_M_1,
1717 #define VEX_LEN_0F12_P_2_M_0 VEX_LEN_0F12_P_0_M_0
1718   VEX_LEN_0F13_M_0,
1719   VEX_LEN_0F16_P_0_M_0,
1720   VEX_LEN_0F16_P_0_M_1,
1721 #define VEX_LEN_0F16_P_2_M_0 VEX_LEN_0F16_P_0_M_0
1722   VEX_LEN_0F17_M_0,
1723   VEX_LEN_0F41_P_0,
1724   VEX_LEN_0F41_P_2,
1725   VEX_LEN_0F42_P_0,
1726   VEX_LEN_0F42_P_2,
1727   VEX_LEN_0F44_P_0,
1728   VEX_LEN_0F44_P_2,
1729   VEX_LEN_0F45_P_0,
1730   VEX_LEN_0F45_P_2,
1731   VEX_LEN_0F46_P_0,
1732   VEX_LEN_0F46_P_2,
1733   VEX_LEN_0F47_P_0,
1734   VEX_LEN_0F47_P_2,
1735   VEX_LEN_0F4A_P_0,
1736   VEX_LEN_0F4A_P_2,
1737   VEX_LEN_0F4B_P_0,
1738   VEX_LEN_0F4B_P_2,
1739   VEX_LEN_0F6E_P_2,
1740   VEX_LEN_0F77_P_0,
1741   VEX_LEN_0F7E_P_1,
1742   VEX_LEN_0F7E_P_2,
1743   VEX_LEN_0F90_P_0,
1744   VEX_LEN_0F90_P_2,
1745   VEX_LEN_0F91_P_0,
1746   VEX_LEN_0F91_P_2,
1747   VEX_LEN_0F92_P_0,
1748   VEX_LEN_0F92_P_2,
1749   VEX_LEN_0F92_P_3,
1750   VEX_LEN_0F93_P_0,
1751   VEX_LEN_0F93_P_2,
1752   VEX_LEN_0F93_P_3,
1753   VEX_LEN_0F98_P_0,
1754   VEX_LEN_0F98_P_2,
1755   VEX_LEN_0F99_P_0,
1756   VEX_LEN_0F99_P_2,
1757   VEX_LEN_0FAE_R_2_M_0,
1758   VEX_LEN_0FAE_R_3_M_0,
1759   VEX_LEN_0FC4_P_2,
1760   VEX_LEN_0FC5_P_2,
1761   VEX_LEN_0FD6_P_2,
1762   VEX_LEN_0FF7_P_2,
1763   VEX_LEN_0F3816_P_2,
1764   VEX_LEN_0F3819_P_2,
1765   VEX_LEN_0F381A_P_2_M_0,
1766   VEX_LEN_0F3836_P_2,
1767   VEX_LEN_0F3841_P_2,
1768   VEX_LEN_0F385A_P_2_M_0,
1769   VEX_LEN_0F38DB_P_2,
1770   VEX_LEN_0F38F2_P_0,
1771   VEX_LEN_0F38F3_R_1_P_0,
1772   VEX_LEN_0F38F3_R_2_P_0,
1773   VEX_LEN_0F38F3_R_3_P_0,
1774   VEX_LEN_0F38F5_P_0,
1775   VEX_LEN_0F38F5_P_1,
1776   VEX_LEN_0F38F5_P_3,
1777   VEX_LEN_0F38F6_P_3,
1778   VEX_LEN_0F38F7_P_0,
1779   VEX_LEN_0F38F7_P_1,
1780   VEX_LEN_0F38F7_P_2,
1781   VEX_LEN_0F38F7_P_3,
1782   VEX_LEN_0F3A00_P_2,
1783   VEX_LEN_0F3A01_P_2,
1784   VEX_LEN_0F3A06_P_2,
1785   VEX_LEN_0F3A14_P_2,
1786   VEX_LEN_0F3A15_P_2,
1787   VEX_LEN_0F3A16_P_2,
1788   VEX_LEN_0F3A17_P_2,
1789   VEX_LEN_0F3A18_P_2,
1790   VEX_LEN_0F3A19_P_2,
1791   VEX_LEN_0F3A20_P_2,
1792   VEX_LEN_0F3A21_P_2,
1793   VEX_LEN_0F3A22_P_2,
1794   VEX_LEN_0F3A30_P_2,
1795   VEX_LEN_0F3A31_P_2,
1796   VEX_LEN_0F3A32_P_2,
1797   VEX_LEN_0F3A33_P_2,
1798   VEX_LEN_0F3A38_P_2,
1799   VEX_LEN_0F3A39_P_2,
1800   VEX_LEN_0F3A41_P_2,
1801   VEX_LEN_0F3A46_P_2,
1802   VEX_LEN_0F3A60_P_2,
1803   VEX_LEN_0F3A61_P_2,
1804   VEX_LEN_0F3A62_P_2,
1805   VEX_LEN_0F3A63_P_2,
1806   VEX_LEN_0F3A6A_P_2,
1807   VEX_LEN_0F3A6B_P_2,
1808   VEX_LEN_0F3A6E_P_2,
1809   VEX_LEN_0F3A6F_P_2,
1810   VEX_LEN_0F3A7A_P_2,
1811   VEX_LEN_0F3A7B_P_2,
1812   VEX_LEN_0F3A7E_P_2,
1813   VEX_LEN_0F3A7F_P_2,
1814   VEX_LEN_0F3ADF_P_2,
1815   VEX_LEN_0F3AF0_P_3,
1816   VEX_LEN_0FXOP_08_CC,
1817   VEX_LEN_0FXOP_08_CD,
1818   VEX_LEN_0FXOP_08_CE,
1819   VEX_LEN_0FXOP_08_CF,
1820   VEX_LEN_0FXOP_08_EC,
1821   VEX_LEN_0FXOP_08_ED,
1822   VEX_LEN_0FXOP_08_EE,
1823   VEX_LEN_0FXOP_08_EF,
1824   VEX_LEN_0FXOP_09_80,
1825   VEX_LEN_0FXOP_09_81
1826 };
1827
1828 enum
1829 {
1830   EVEX_LEN_0F6E_P_2 = 0,
1831   EVEX_LEN_0F7E_P_1,
1832   EVEX_LEN_0F7E_P_2,
1833   EVEX_LEN_0FC4_P_2,
1834   EVEX_LEN_0FC5_P_2,
1835   EVEX_LEN_0FD6_P_2,
1836   EVEX_LEN_0F3819_P_2_W_0,
1837   EVEX_LEN_0F3819_P_2_W_1,
1838   EVEX_LEN_0F381A_P_2_W_0,
1839   EVEX_LEN_0F381A_P_2_W_1,
1840   EVEX_LEN_0F381B_P_2_W_0,
1841   EVEX_LEN_0F381B_P_2_W_1,
1842   EVEX_LEN_0F385A_P_2_W_0,
1843   EVEX_LEN_0F385A_P_2_W_1,
1844   EVEX_LEN_0F385B_P_2_W_0,
1845   EVEX_LEN_0F385B_P_2_W_1,
1846   EVEX_LEN_0F38C6_REG_1_PREFIX_2,
1847   EVEX_LEN_0F38C6_REG_2_PREFIX_2,
1848   EVEX_LEN_0F38C6_REG_5_PREFIX_2,
1849   EVEX_LEN_0F38C6_REG_6_PREFIX_2,
1850   EVEX_LEN_0F38C7_R_1_P_2_W_0,
1851   EVEX_LEN_0F38C7_R_1_P_2_W_1,
1852   EVEX_LEN_0F38C7_R_2_P_2_W_0,
1853   EVEX_LEN_0F38C7_R_2_P_2_W_1,
1854   EVEX_LEN_0F38C7_R_5_P_2_W_0,
1855   EVEX_LEN_0F38C7_R_5_P_2_W_1,
1856   EVEX_LEN_0F38C7_R_6_P_2_W_0,
1857   EVEX_LEN_0F38C7_R_6_P_2_W_1,
1858   EVEX_LEN_0F3A14_P_2,
1859   EVEX_LEN_0F3A15_P_2,
1860   EVEX_LEN_0F3A16_P_2,
1861   EVEX_LEN_0F3A17_P_2,
1862   EVEX_LEN_0F3A18_P_2_W_0,
1863   EVEX_LEN_0F3A18_P_2_W_1,
1864   EVEX_LEN_0F3A19_P_2_W_0,
1865   EVEX_LEN_0F3A19_P_2_W_1,
1866   EVEX_LEN_0F3A1A_P_2_W_0,
1867   EVEX_LEN_0F3A1A_P_2_W_1,
1868   EVEX_LEN_0F3A1B_P_2_W_0,
1869   EVEX_LEN_0F3A1B_P_2_W_1,
1870   EVEX_LEN_0F3A20_P_2,
1871   EVEX_LEN_0F3A21_P_2_W_0,
1872   EVEX_LEN_0F3A22_P_2,
1873   EVEX_LEN_0F3A23_P_2_W_0,
1874   EVEX_LEN_0F3A23_P_2_W_1,
1875   EVEX_LEN_0F3A38_P_2_W_0,
1876   EVEX_LEN_0F3A38_P_2_W_1,
1877   EVEX_LEN_0F3A39_P_2_W_0,
1878   EVEX_LEN_0F3A39_P_2_W_1,
1879   EVEX_LEN_0F3A3A_P_2_W_0,
1880   EVEX_LEN_0F3A3A_P_2_W_1,
1881   EVEX_LEN_0F3A3B_P_2_W_0,
1882   EVEX_LEN_0F3A3B_P_2_W_1,
1883   EVEX_LEN_0F3A43_P_2_W_0,
1884   EVEX_LEN_0F3A43_P_2_W_1
1885 };
1886
1887 enum
1888 {
1889   VEX_W_0F41_P_0_LEN_1 = 0,
1890   VEX_W_0F41_P_2_LEN_1,
1891   VEX_W_0F42_P_0_LEN_1,
1892   VEX_W_0F42_P_2_LEN_1,
1893   VEX_W_0F44_P_0_LEN_0,
1894   VEX_W_0F44_P_2_LEN_0,
1895   VEX_W_0F45_P_0_LEN_1,
1896   VEX_W_0F45_P_2_LEN_1,
1897   VEX_W_0F46_P_0_LEN_1,
1898   VEX_W_0F46_P_2_LEN_1,
1899   VEX_W_0F47_P_0_LEN_1,
1900   VEX_W_0F47_P_2_LEN_1,
1901   VEX_W_0F4A_P_0_LEN_1,
1902   VEX_W_0F4A_P_2_LEN_1,
1903   VEX_W_0F4B_P_0_LEN_1,
1904   VEX_W_0F4B_P_2_LEN_1,
1905   VEX_W_0F90_P_0_LEN_0,
1906   VEX_W_0F90_P_2_LEN_0,
1907   VEX_W_0F91_P_0_LEN_0,
1908   VEX_W_0F91_P_2_LEN_0,
1909   VEX_W_0F92_P_0_LEN_0,
1910   VEX_W_0F92_P_2_LEN_0,
1911   VEX_W_0F93_P_0_LEN_0,
1912   VEX_W_0F93_P_2_LEN_0,
1913   VEX_W_0F98_P_0_LEN_0,
1914   VEX_W_0F98_P_2_LEN_0,
1915   VEX_W_0F99_P_0_LEN_0,
1916   VEX_W_0F99_P_2_LEN_0,
1917   VEX_W_0F380C_P_2,
1918   VEX_W_0F380D_P_2,
1919   VEX_W_0F380E_P_2,
1920   VEX_W_0F380F_P_2,
1921   VEX_W_0F3813_P_2,
1922   VEX_W_0F3816_P_2,
1923   VEX_W_0F3818_P_2,
1924   VEX_W_0F3819_P_2,
1925   VEX_W_0F381A_P_2_M_0,
1926   VEX_W_0F382C_P_2_M_0,
1927   VEX_W_0F382D_P_2_M_0,
1928   VEX_W_0F382E_P_2_M_0,
1929   VEX_W_0F382F_P_2_M_0,
1930   VEX_W_0F3836_P_2,
1931   VEX_W_0F3846_P_2,
1932   VEX_W_0F3858_P_2,
1933   VEX_W_0F3859_P_2,
1934   VEX_W_0F385A_P_2_M_0,
1935   VEX_W_0F3878_P_2,
1936   VEX_W_0F3879_P_2,
1937   VEX_W_0F38CF_P_2,
1938   VEX_W_0F3A00_P_2,
1939   VEX_W_0F3A01_P_2,
1940   VEX_W_0F3A02_P_2,
1941   VEX_W_0F3A04_P_2,
1942   VEX_W_0F3A05_P_2,
1943   VEX_W_0F3A06_P_2,
1944   VEX_W_0F3A18_P_2,
1945   VEX_W_0F3A19_P_2,
1946   VEX_W_0F3A1D_P_2,
1947   VEX_W_0F3A30_P_2_LEN_0,
1948   VEX_W_0F3A31_P_2_LEN_0,
1949   VEX_W_0F3A32_P_2_LEN_0,
1950   VEX_W_0F3A33_P_2_LEN_0,
1951   VEX_W_0F3A38_P_2,
1952   VEX_W_0F3A39_P_2,
1953   VEX_W_0F3A46_P_2,
1954   VEX_W_0F3A48_P_2,
1955   VEX_W_0F3A49_P_2,
1956   VEX_W_0F3A4A_P_2,
1957   VEX_W_0F3A4B_P_2,
1958   VEX_W_0F3A4C_P_2,
1959   VEX_W_0F3ACE_P_2,
1960   VEX_W_0F3ACF_P_2,
1961
1962   EVEX_W_0F10_P_1,
1963   EVEX_W_0F10_P_3,
1964   EVEX_W_0F11_P_1,
1965   EVEX_W_0F11_P_3,
1966   EVEX_W_0F12_P_0_M_1,
1967   EVEX_W_0F12_P_1,
1968   EVEX_W_0F12_P_3,
1969   EVEX_W_0F16_P_0_M_1,
1970   EVEX_W_0F16_P_1,
1971   EVEX_W_0F2A_P_3,
1972   EVEX_W_0F51_P_1,
1973   EVEX_W_0F51_P_3,
1974   EVEX_W_0F58_P_1,
1975   EVEX_W_0F58_P_3,
1976   EVEX_W_0F59_P_1,
1977   EVEX_W_0F59_P_3,
1978   EVEX_W_0F5A_P_0,
1979   EVEX_W_0F5A_P_1,
1980   EVEX_W_0F5A_P_2,
1981   EVEX_W_0F5A_P_3,
1982   EVEX_W_0F5B_P_0,
1983   EVEX_W_0F5B_P_1,
1984   EVEX_W_0F5B_P_2,
1985   EVEX_W_0F5C_P_1,
1986   EVEX_W_0F5C_P_3,
1987   EVEX_W_0F5D_P_1,
1988   EVEX_W_0F5D_P_3,
1989   EVEX_W_0F5E_P_1,
1990   EVEX_W_0F5E_P_3,
1991   EVEX_W_0F5F_P_1,
1992   EVEX_W_0F5F_P_3,
1993   EVEX_W_0F62_P_2,
1994   EVEX_W_0F66_P_2,
1995   EVEX_W_0F6A_P_2,
1996   EVEX_W_0F6B_P_2,
1997   EVEX_W_0F6C_P_2,
1998   EVEX_W_0F6D_P_2,
1999   EVEX_W_0F6F_P_1,
2000   EVEX_W_0F6F_P_2,
2001   EVEX_W_0F6F_P_3,
2002   EVEX_W_0F70_P_2,
2003   EVEX_W_0F72_R_2_P_2,
2004   EVEX_W_0F72_R_6_P_2,
2005   EVEX_W_0F73_R_2_P_2,
2006   EVEX_W_0F73_R_6_P_2,
2007   EVEX_W_0F76_P_2,
2008   EVEX_W_0F78_P_0,
2009   EVEX_W_0F78_P_2,
2010   EVEX_W_0F79_P_0,
2011   EVEX_W_0F79_P_2,
2012   EVEX_W_0F7A_P_1,
2013   EVEX_W_0F7A_P_2,
2014   EVEX_W_0F7A_P_3,
2015   EVEX_W_0F7B_P_2,
2016   EVEX_W_0F7B_P_3,
2017   EVEX_W_0F7E_P_1,
2018   EVEX_W_0F7F_P_1,
2019   EVEX_W_0F7F_P_2,
2020   EVEX_W_0F7F_P_3,
2021   EVEX_W_0FC2_P_1,
2022   EVEX_W_0FC2_P_3,
2023   EVEX_W_0FD2_P_2,
2024   EVEX_W_0FD3_P_2,
2025   EVEX_W_0FD4_P_2,
2026   EVEX_W_0FD6_P_2,
2027   EVEX_W_0FE6_P_1,
2028   EVEX_W_0FE6_P_2,
2029   EVEX_W_0FE6_P_3,
2030   EVEX_W_0FE7_P_2,
2031   EVEX_W_0FF2_P_2,
2032   EVEX_W_0FF3_P_2,
2033   EVEX_W_0FF4_P_2,
2034   EVEX_W_0FFA_P_2,
2035   EVEX_W_0FFB_P_2,
2036   EVEX_W_0FFE_P_2,
2037   EVEX_W_0F380D_P_2,
2038   EVEX_W_0F3810_P_1,
2039   EVEX_W_0F3810_P_2,
2040   EVEX_W_0F3811_P_1,
2041   EVEX_W_0F3811_P_2,
2042   EVEX_W_0F3812_P_1,
2043   EVEX_W_0F3812_P_2,
2044   EVEX_W_0F3813_P_1,
2045   EVEX_W_0F3813_P_2,
2046   EVEX_W_0F3814_P_1,
2047   EVEX_W_0F3815_P_1,
2048   EVEX_W_0F3819_P_2,
2049   EVEX_W_0F381A_P_2,
2050   EVEX_W_0F381B_P_2,
2051   EVEX_W_0F381E_P_2,
2052   EVEX_W_0F381F_P_2,
2053   EVEX_W_0F3820_P_1,
2054   EVEX_W_0F3821_P_1,
2055   EVEX_W_0F3822_P_1,
2056   EVEX_W_0F3823_P_1,
2057   EVEX_W_0F3824_P_1,
2058   EVEX_W_0F3825_P_1,
2059   EVEX_W_0F3825_P_2,
2060   EVEX_W_0F3826_P_1,
2061   EVEX_W_0F3826_P_2,
2062   EVEX_W_0F3828_P_1,
2063   EVEX_W_0F3828_P_2,
2064   EVEX_W_0F3829_P_1,
2065   EVEX_W_0F3829_P_2,
2066   EVEX_W_0F382A_P_1,
2067   EVEX_W_0F382A_P_2,
2068   EVEX_W_0F382B_P_2,
2069   EVEX_W_0F3830_P_1,
2070   EVEX_W_0F3831_P_1,
2071   EVEX_W_0F3832_P_1,
2072   EVEX_W_0F3833_P_1,
2073   EVEX_W_0F3834_P_1,
2074   EVEX_W_0F3835_P_1,
2075   EVEX_W_0F3835_P_2,
2076   EVEX_W_0F3837_P_2,
2077   EVEX_W_0F3838_P_1,
2078   EVEX_W_0F3839_P_1,
2079   EVEX_W_0F383A_P_1,
2080   EVEX_W_0F3840_P_2,
2081   EVEX_W_0F3852_P_1,
2082   EVEX_W_0F3854_P_2,
2083   EVEX_W_0F3855_P_2,
2084   EVEX_W_0F3859_P_2,
2085   EVEX_W_0F385A_P_2,
2086   EVEX_W_0F385B_P_2,
2087   EVEX_W_0F3862_P_2,
2088   EVEX_W_0F3863_P_2,
2089   EVEX_W_0F3866_P_2,
2090   EVEX_W_0F3868_P_3,
2091   EVEX_W_0F3870_P_2,
2092   EVEX_W_0F3871_P_2,
2093   EVEX_W_0F3872_P_1,
2094   EVEX_W_0F3872_P_2,
2095   EVEX_W_0F3872_P_3,
2096   EVEX_W_0F3873_P_2,
2097   EVEX_W_0F3875_P_2,
2098   EVEX_W_0F387A_P_2,
2099   EVEX_W_0F387B_P_2,
2100   EVEX_W_0F387D_P_2,
2101   EVEX_W_0F3883_P_2,
2102   EVEX_W_0F388D_P_2,
2103   EVEX_W_0F3891_P_2,
2104   EVEX_W_0F3893_P_2,
2105   EVEX_W_0F38A1_P_2,
2106   EVEX_W_0F38A3_P_2,
2107   EVEX_W_0F38C7_R_1_P_2,
2108   EVEX_W_0F38C7_R_2_P_2,
2109   EVEX_W_0F38C7_R_5_P_2,
2110   EVEX_W_0F38C7_R_6_P_2,
2111
2112   EVEX_W_0F3A00_P_2,
2113   EVEX_W_0F3A01_P_2,
2114   EVEX_W_0F3A05_P_2,
2115   EVEX_W_0F3A08_P_2,
2116   EVEX_W_0F3A09_P_2,
2117   EVEX_W_0F3A0A_P_2,
2118   EVEX_W_0F3A0B_P_2,
2119   EVEX_W_0F3A18_P_2,
2120   EVEX_W_0F3A19_P_2,
2121   EVEX_W_0F3A1A_P_2,
2122   EVEX_W_0F3A1B_P_2,
2123   EVEX_W_0F3A21_P_2,
2124   EVEX_W_0F3A23_P_2,
2125   EVEX_W_0F3A38_P_2,
2126   EVEX_W_0F3A39_P_2,
2127   EVEX_W_0F3A3A_P_2,
2128   EVEX_W_0F3A3B_P_2,
2129   EVEX_W_0F3A3E_P_2,
2130   EVEX_W_0F3A3F_P_2,
2131   EVEX_W_0F3A42_P_2,
2132   EVEX_W_0F3A43_P_2,
2133   EVEX_W_0F3A50_P_2,
2134   EVEX_W_0F3A51_P_2,
2135   EVEX_W_0F3A56_P_2,
2136   EVEX_W_0F3A57_P_2,
2137   EVEX_W_0F3A66_P_2,
2138   EVEX_W_0F3A67_P_2,
2139   EVEX_W_0F3A70_P_2,
2140   EVEX_W_0F3A71_P_2,
2141   EVEX_W_0F3A72_P_2,
2142   EVEX_W_0F3A73_P_2,
2143 };
2144
2145 typedef void (*op_rtn) (int bytemode, int sizeflag);
2146
2147 struct dis386 {
2148   const char *name;
2149   struct
2150     {
2151       op_rtn rtn;
2152       int bytemode;
2153     } op[MAX_OPERANDS];
2154   unsigned int prefix_requirement;
2155 };
2156
2157 /* Upper case letters in the instruction names here are macros.
2158    'A' => print 'b' if no register operands or suffix_always is true
2159    'B' => print 'b' if suffix_always is true
2160    'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2161           size prefix
2162    'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2163           suffix_always is true
2164    'E' => print 'e' if 32-bit form of jcxz
2165    'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2166    'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2167    'H' => print ",pt" or ",pn" branch hint
2168    'I' unused.
2169    'J' unused.
2170    'K' => print 'd' or 'q' if rex prefix is present.
2171    'L' => print 'l' if suffix_always is true
2172    'M' => print 'r' if intel_mnemonic is false.
2173    'N' => print 'n' if instruction has no wait "prefix"
2174    'O' => print 'd' or 'o' (or 'q' in Intel mode)
2175    'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2176           or suffix_always is true.  print 'q' if rex prefix is present.
2177    'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2178           is true
2179    'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2180    'S' => print 'w', 'l' or 'q' if suffix_always is true
2181    'T' => print 'q' in 64bit mode if instruction has no operand size
2182           prefix and behave as 'P' otherwise
2183    'U' => print 'q' in 64bit mode if instruction has no operand size
2184           prefix and behave as 'Q' otherwise
2185    'V' => print 'q' in 64bit mode if instruction has no operand size
2186           prefix and behave as 'S' otherwise
2187    'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2188    'X' => print 's', 'd' depending on data16 prefix (for XMM)
2189    'Y' unused.
2190    'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2191    '!' => change condition from true to false or from false to true.
2192    '%' => add 1 upper case letter to the macro.
2193    '^' => print 'w', 'l', or 'q' (Intel64 ISA only) depending on operand size
2194           prefix or suffix_always is true (lcall/ljmp).
2195    '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending
2196           on operand size prefix.
2197    '&' => print 'q' in 64bit mode for Intel64 ISA or if instruction
2198           has no operand size prefix for AMD64 ISA, behave as 'P'
2199           otherwise
2200
2201    2 upper case letter macros:
2202    "XY" => print 'x' or 'y' if suffix_always is true or no register
2203            operands and no broadcast.
2204    "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
2205            register operands and no broadcast.
2206    "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2207    "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory
2208            operand or no operand at all in 64bit mode, or if suffix_always
2209            is true.
2210    "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2211    "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2212    "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2213    "LW" => print 'd', 'q' depending on the VEX.W bit
2214    "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
2215            an operand size prefix, or suffix_always is true.  print
2216            'q' if rex prefix is present.
2217
2218    Many of the above letters print nothing in Intel mode.  See "putop"
2219    for the details.
2220
2221    Braces '{' and '}', and vertical bars '|', indicate alternative
2222    mnemonic strings for AT&T and Intel.  */
2223
2224 static const struct dis386 dis386[] = {
2225   /* 00 */
2226   { "addB",             { Ebh1, Gb }, 0 },
2227   { "addS",             { Evh1, Gv }, 0 },
2228   { "addB",             { Gb, EbS }, 0 },
2229   { "addS",             { Gv, EvS }, 0 },
2230   { "addB",             { AL, Ib }, 0 },
2231   { "addS",             { eAX, Iv }, 0 },
2232   { X86_64_TABLE (X86_64_06) },
2233   { X86_64_TABLE (X86_64_07) },
2234   /* 08 */
2235   { "orB",              { Ebh1, Gb }, 0 },
2236   { "orS",              { Evh1, Gv }, 0 },
2237   { "orB",              { Gb, EbS }, 0 },
2238   { "orS",              { Gv, EvS }, 0 },
2239   { "orB",              { AL, Ib }, 0 },
2240   { "orS",              { eAX, Iv }, 0 },
2241   { X86_64_TABLE (X86_64_0E) },
2242   { Bad_Opcode },       /* 0x0f extended opcode escape */
2243   /* 10 */
2244   { "adcB",             { Ebh1, Gb }, 0 },
2245   { "adcS",             { Evh1, Gv }, 0 },
2246   { "adcB",             { Gb, EbS }, 0 },
2247   { "adcS",             { Gv, EvS }, 0 },
2248   { "adcB",             { AL, Ib }, 0 },
2249   { "adcS",             { eAX, Iv }, 0 },
2250   { X86_64_TABLE (X86_64_16) },
2251   { X86_64_TABLE (X86_64_17) },
2252   /* 18 */
2253   { "sbbB",             { Ebh1, Gb }, 0 },
2254   { "sbbS",             { Evh1, Gv }, 0 },
2255   { "sbbB",             { Gb, EbS }, 0 },
2256   { "sbbS",             { Gv, EvS }, 0 },
2257   { "sbbB",             { AL, Ib }, 0 },
2258   { "sbbS",             { eAX, Iv }, 0 },
2259   { X86_64_TABLE (X86_64_1E) },
2260   { X86_64_TABLE (X86_64_1F) },
2261   /* 20 */
2262   { "andB",             { Ebh1, Gb }, 0 },
2263   { "andS",             { Evh1, Gv }, 0 },
2264   { "andB",             { Gb, EbS }, 0 },
2265   { "andS",             { Gv, EvS }, 0 },
2266   { "andB",             { AL, Ib }, 0 },
2267   { "andS",             { eAX, Iv }, 0 },
2268   { Bad_Opcode },       /* SEG ES prefix */
2269   { X86_64_TABLE (X86_64_27) },
2270   /* 28 */
2271   { "subB",             { Ebh1, Gb }, 0 },
2272   { "subS",             { Evh1, Gv }, 0 },
2273   { "subB",             { Gb, EbS }, 0 },
2274   { "subS",             { Gv, EvS }, 0 },
2275   { "subB",             { AL, Ib }, 0 },
2276   { "subS",             { eAX, Iv }, 0 },
2277   { Bad_Opcode },       /* SEG CS prefix */
2278   { X86_64_TABLE (X86_64_2F) },
2279   /* 30 */
2280   { "xorB",             { Ebh1, Gb }, 0 },
2281   { "xorS",             { Evh1, Gv }, 0 },
2282   { "xorB",             { Gb, EbS }, 0 },
2283   { "xorS",             { Gv, EvS }, 0 },
2284   { "xorB",             { AL, Ib }, 0 },
2285   { "xorS",             { eAX, Iv }, 0 },
2286   { Bad_Opcode },       /* SEG SS prefix */
2287   { X86_64_TABLE (X86_64_37) },
2288   /* 38 */
2289   { "cmpB",             { Eb, Gb }, 0 },
2290   { "cmpS",             { Ev, Gv }, 0 },
2291   { "cmpB",             { Gb, EbS }, 0 },
2292   { "cmpS",             { Gv, EvS }, 0 },
2293   { "cmpB",             { AL, Ib }, 0 },
2294   { "cmpS",             { eAX, Iv }, 0 },
2295   { Bad_Opcode },       /* SEG DS prefix */
2296   { X86_64_TABLE (X86_64_3F) },
2297   /* 40 */
2298   { "inc{S|}",          { RMeAX }, 0 },
2299   { "inc{S|}",          { RMeCX }, 0 },
2300   { "inc{S|}",          { RMeDX }, 0 },
2301   { "inc{S|}",          { RMeBX }, 0 },
2302   { "inc{S|}",          { RMeSP }, 0 },
2303   { "inc{S|}",          { RMeBP }, 0 },
2304   { "inc{S|}",          { RMeSI }, 0 },
2305   { "inc{S|}",          { RMeDI }, 0 },
2306   /* 48 */
2307   { "dec{S|}",          { RMeAX }, 0 },
2308   { "dec{S|}",          { RMeCX }, 0 },
2309   { "dec{S|}",          { RMeDX }, 0 },
2310   { "dec{S|}",          { RMeBX }, 0 },
2311   { "dec{S|}",          { RMeSP }, 0 },
2312   { "dec{S|}",          { RMeBP }, 0 },
2313   { "dec{S|}",          { RMeSI }, 0 },
2314   { "dec{S|}",          { RMeDI }, 0 },
2315   /* 50 */
2316   { "pushV",            { RMrAX }, 0 },
2317   { "pushV",            { RMrCX }, 0 },
2318   { "pushV",            { RMrDX }, 0 },
2319   { "pushV",            { RMrBX }, 0 },
2320   { "pushV",            { RMrSP }, 0 },
2321   { "pushV",            { RMrBP }, 0 },
2322   { "pushV",            { RMrSI }, 0 },
2323   { "pushV",            { RMrDI }, 0 },
2324   /* 58 */
2325   { "popV",             { RMrAX }, 0 },
2326   { "popV",             { RMrCX }, 0 },
2327   { "popV",             { RMrDX }, 0 },
2328   { "popV",             { RMrBX }, 0 },
2329   { "popV",             { RMrSP }, 0 },
2330   { "popV",             { RMrBP }, 0 },
2331   { "popV",             { RMrSI }, 0 },
2332   { "popV",             { RMrDI }, 0 },
2333   /* 60 */
2334   { X86_64_TABLE (X86_64_60) },
2335   { X86_64_TABLE (X86_64_61) },
2336   { X86_64_TABLE (X86_64_62) },
2337   { X86_64_TABLE (X86_64_63) },
2338   { Bad_Opcode },       /* seg fs */
2339   { Bad_Opcode },       /* seg gs */
2340   { Bad_Opcode },       /* op size prefix */
2341   { Bad_Opcode },       /* adr size prefix */
2342   /* 68 */
2343   { "pushT",            { sIv }, 0 },
2344   { "imulS",            { Gv, Ev, Iv }, 0 },
2345   { "pushT",            { sIbT }, 0 },
2346   { "imulS",            { Gv, Ev, sIb }, 0 },
2347   { "ins{b|}",          { Ybr, indirDX }, 0 },
2348   { X86_64_TABLE (X86_64_6D) },
2349   { "outs{b|}",         { indirDXr, Xb }, 0 },
2350   { X86_64_TABLE (X86_64_6F) },
2351   /* 70 */
2352   { "joH",              { Jb, BND, cond_jump_flag }, 0 },
2353   { "jnoH",             { Jb, BND, cond_jump_flag }, 0 },
2354   { "jbH",              { Jb, BND, cond_jump_flag }, 0 },
2355   { "jaeH",             { Jb, BND, cond_jump_flag }, 0 },
2356   { "jeH",              { Jb, BND, cond_jump_flag }, 0 },
2357   { "jneH",             { Jb, BND, cond_jump_flag }, 0 },
2358   { "jbeH",             { Jb, BND, cond_jump_flag }, 0 },
2359   { "jaH",              { Jb, BND, cond_jump_flag }, 0 },
2360   /* 78 */
2361   { "jsH",              { Jb, BND, cond_jump_flag }, 0 },
2362   { "jnsH",             { Jb, BND, cond_jump_flag }, 0 },
2363   { "jpH",              { Jb, BND, cond_jump_flag }, 0 },
2364   { "jnpH",             { Jb, BND, cond_jump_flag }, 0 },
2365   { "jlH",              { Jb, BND, cond_jump_flag }, 0 },
2366   { "jgeH",             { Jb, BND, cond_jump_flag }, 0 },
2367   { "jleH",             { Jb, BND, cond_jump_flag }, 0 },
2368   { "jgH",              { Jb, BND, cond_jump_flag }, 0 },
2369   /* 80 */
2370   { REG_TABLE (REG_80) },
2371   { REG_TABLE (REG_81) },
2372   { X86_64_TABLE (X86_64_82) },
2373   { REG_TABLE (REG_83) },
2374   { "testB",            { Eb, Gb }, 0 },
2375   { "testS",            { Ev, Gv }, 0 },
2376   { "xchgB",            { Ebh2, Gb }, 0 },
2377   { "xchgS",            { Evh2, Gv }, 0 },
2378   /* 88 */
2379   { "movB",             { Ebh3, Gb }, 0 },
2380   { "movS",             { Evh3, Gv }, 0 },
2381   { "movB",             { Gb, EbS }, 0 },
2382   { "movS",             { Gv, EvS }, 0 },
2383   { "movD",             { Sv, Sw }, 0 },
2384   { MOD_TABLE (MOD_8D) },
2385   { "movD",             { Sw, Sv }, 0 },
2386   { REG_TABLE (REG_8F) },
2387   /* 90 */
2388   { PREFIX_TABLE (PREFIX_90) },
2389   { "xchgS",            { RMeCX, eAX }, 0 },
2390   { "xchgS",            { RMeDX, eAX }, 0 },
2391   { "xchgS",            { RMeBX, eAX }, 0 },
2392   { "xchgS",            { RMeSP, eAX }, 0 },
2393   { "xchgS",            { RMeBP, eAX }, 0 },
2394   { "xchgS",            { RMeSI, eAX }, 0 },
2395   { "xchgS",            { RMeDI, eAX }, 0 },
2396   /* 98 */
2397   { "cW{t|}R",          { XX }, 0 },
2398   { "cR{t|}O",          { XX }, 0 },
2399   { X86_64_TABLE (X86_64_9A) },
2400   { Bad_Opcode },       /* fwait */
2401   { "pushfT",           { XX }, 0 },
2402   { "popfT",            { XX }, 0 },
2403   { "sahf",             { XX }, 0 },
2404   { "lahf",             { XX }, 0 },
2405   /* a0 */
2406   { "mov%LB",           { AL, Ob }, 0 },
2407   { "mov%LS",           { eAX, Ov }, 0 },
2408   { "mov%LB",           { Ob, AL }, 0 },
2409   { "mov%LS",           { Ov, eAX }, 0 },
2410   { "movs{b|}",         { Ybr, Xb }, 0 },
2411   { "movs{R|}",         { Yvr, Xv }, 0 },
2412   { "cmps{b|}",         { Xb, Yb }, 0 },
2413   { "cmps{R|}",         { Xv, Yv }, 0 },
2414   /* a8 */
2415   { "testB",            { AL, Ib }, 0 },
2416   { "testS",            { eAX, Iv }, 0 },
2417   { "stosB",            { Ybr, AL }, 0 },
2418   { "stosS",            { Yvr, eAX }, 0 },
2419   { "lodsB",            { ALr, Xb }, 0 },
2420   { "lodsS",            { eAXr, Xv }, 0 },
2421   { "scasB",            { AL, Yb }, 0 },
2422   { "scasS",            { eAX, Yv }, 0 },
2423   /* b0 */
2424   { "movB",             { RMAL, Ib }, 0 },
2425   { "movB",             { RMCL, Ib }, 0 },
2426   { "movB",             { RMDL, Ib }, 0 },
2427   { "movB",             { RMBL, Ib }, 0 },
2428   { "movB",             { RMAH, Ib }, 0 },
2429   { "movB",             { RMCH, Ib }, 0 },
2430   { "movB",             { RMDH, Ib }, 0 },
2431   { "movB",             { RMBH, Ib }, 0 },
2432   /* b8 */
2433   { "mov%LV",           { RMeAX, Iv64 }, 0 },
2434   { "mov%LV",           { RMeCX, Iv64 }, 0 },
2435   { "mov%LV",           { RMeDX, Iv64 }, 0 },
2436   { "mov%LV",           { RMeBX, Iv64 }, 0 },
2437   { "mov%LV",           { RMeSP, Iv64 }, 0 },
2438   { "mov%LV",           { RMeBP, Iv64 }, 0 },
2439   { "mov%LV",           { RMeSI, Iv64 }, 0 },
2440   { "mov%LV",           { RMeDI, Iv64 }, 0 },
2441   /* c0 */
2442   { REG_TABLE (REG_C0) },
2443   { REG_TABLE (REG_C1) },
2444   { X86_64_TABLE (X86_64_C2) },
2445   { X86_64_TABLE (X86_64_C3) },
2446   { X86_64_TABLE (X86_64_C4) },
2447   { X86_64_TABLE (X86_64_C5) },
2448   { REG_TABLE (REG_C6) },
2449   { REG_TABLE (REG_C7) },
2450   /* c8 */
2451   { "enterT",           { Iw, Ib }, 0 },
2452   { "leaveT",           { XX }, 0 },
2453   { "{l|}ret{|f}P",     { Iw }, 0 },
2454   { "{l|}ret{|f}P",     { XX }, 0 },
2455   { "int3",             { XX }, 0 },
2456   { "int",              { Ib }, 0 },
2457   { X86_64_TABLE (X86_64_CE) },
2458   { "iret%LP",          { XX }, 0 },
2459   /* d0 */
2460   { REG_TABLE (REG_D0) },
2461   { REG_TABLE (REG_D1) },
2462   { REG_TABLE (REG_D2) },
2463   { REG_TABLE (REG_D3) },
2464   { X86_64_TABLE (X86_64_D4) },
2465   { X86_64_TABLE (X86_64_D5) },
2466   { Bad_Opcode },
2467   { "xlat",             { DSBX }, 0 },
2468   /* d8 */
2469   { FLOAT },
2470   { FLOAT },
2471   { FLOAT },
2472   { FLOAT },
2473   { FLOAT },
2474   { FLOAT },
2475   { FLOAT },
2476   { FLOAT },
2477   /* e0 */
2478   { "loopneFH",         { Jb, XX, loop_jcxz_flag }, 0 },
2479   { "loopeFH",          { Jb, XX, loop_jcxz_flag }, 0 },
2480   { "loopFH",           { Jb, XX, loop_jcxz_flag }, 0 },
2481   { "jEcxzH",           { Jb, XX, loop_jcxz_flag }, 0 },
2482   { "inB",              { AL, Ib }, 0 },
2483   { "inG",              { zAX, Ib }, 0 },
2484   { "outB",             { Ib, AL }, 0 },
2485   { "outG",             { Ib, zAX }, 0 },
2486   /* e8 */
2487   { X86_64_TABLE (X86_64_E8) },
2488   { X86_64_TABLE (X86_64_E9) },
2489   { X86_64_TABLE (X86_64_EA) },
2490   { "jmp",              { Jb, BND }, 0 },
2491   { "inB",              { AL, indirDX }, 0 },
2492   { "inG",              { zAX, indirDX }, 0 },
2493   { "outB",             { indirDX, AL }, 0 },
2494   { "outG",             { indirDX, zAX }, 0 },
2495   /* f0 */
2496   { Bad_Opcode },       /* lock prefix */
2497   { "icebp",            { XX }, 0 },
2498   { Bad_Opcode },       /* repne */
2499   { Bad_Opcode },       /* repz */
2500   { "hlt",              { XX }, 0 },
2501   { "cmc",              { XX }, 0 },
2502   { REG_TABLE (REG_F6) },
2503   { REG_TABLE (REG_F7) },
2504   /* f8 */
2505   { "clc",              { XX }, 0 },
2506   { "stc",              { XX }, 0 },
2507   { "cli",              { XX }, 0 },
2508   { "sti",              { XX }, 0 },
2509   { "cld",              { XX }, 0 },
2510   { "std",              { XX }, 0 },
2511   { REG_TABLE (REG_FE) },
2512   { REG_TABLE (REG_FF) },
2513 };
2514
2515 static const struct dis386 dis386_twobyte[] = {
2516   /* 00 */
2517   { REG_TABLE (REG_0F00 ) },
2518   { REG_TABLE (REG_0F01 ) },
2519   { "larS",             { Gv, Ew }, 0 },
2520   { "lslS",             { Gv, Ew }, 0 },
2521   { Bad_Opcode },
2522   { "syscall",          { XX }, 0 },
2523   { "clts",             { XX }, 0 },
2524   { "sysret%LQ",                { XX }, 0 },
2525   /* 08 */
2526   { "invd",             { XX }, 0 },
2527   { PREFIX_TABLE (PREFIX_0F09) },
2528   { Bad_Opcode },
2529   { "ud2",              { XX }, 0 },
2530   { Bad_Opcode },
2531   { REG_TABLE (REG_0F0D) },
2532   { "femms",            { XX }, 0 },
2533   { "",                 { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix.  */
2534   /* 10 */
2535   { PREFIX_TABLE (PREFIX_0F10) },
2536   { PREFIX_TABLE (PREFIX_0F11) },
2537   { PREFIX_TABLE (PREFIX_0F12) },
2538   { MOD_TABLE (MOD_0F13) },
2539   { "unpcklpX",         { XM, EXx }, PREFIX_OPCODE },
2540   { "unpckhpX",         { XM, EXx }, PREFIX_OPCODE },
2541   { PREFIX_TABLE (PREFIX_0F16) },
2542   { MOD_TABLE (MOD_0F17) },
2543   /* 18 */
2544   { REG_TABLE (REG_0F18) },
2545   { "nopQ",             { Ev }, 0 },
2546   { PREFIX_TABLE (PREFIX_0F1A) },
2547   { PREFIX_TABLE (PREFIX_0F1B) },
2548   { PREFIX_TABLE (PREFIX_0F1C) },
2549   { "nopQ",             { Ev }, 0 },
2550   { PREFIX_TABLE (PREFIX_0F1E) },
2551   { "nopQ",             { Ev }, 0 },
2552   /* 20 */
2553   { "movZ",             { Rm, Cm }, 0 },
2554   { "movZ",             { Rm, Dm }, 0 },
2555   { "movZ",             { Cm, Rm }, 0 },
2556   { "movZ",             { Dm, Rm }, 0 },
2557   { MOD_TABLE (MOD_0F24) },
2558   { Bad_Opcode },
2559   { MOD_TABLE (MOD_0F26) },
2560   { Bad_Opcode },
2561   /* 28 */
2562   { "movapX",           { XM, EXx }, PREFIX_OPCODE },
2563   { "movapX",           { EXxS, XM }, PREFIX_OPCODE },
2564   { PREFIX_TABLE (PREFIX_0F2A) },
2565   { PREFIX_TABLE (PREFIX_0F2B) },
2566   { PREFIX_TABLE (PREFIX_0F2C) },
2567   { PREFIX_TABLE (PREFIX_0F2D) },
2568   { PREFIX_TABLE (PREFIX_0F2E) },
2569   { PREFIX_TABLE (PREFIX_0F2F) },
2570   /* 30 */
2571   { "wrmsr",            { XX }, 0 },
2572   { "rdtsc",            { XX }, 0 },
2573   { "rdmsr",            { XX }, 0 },
2574   { "rdpmc",            { XX }, 0 },
2575   { "sysenter",         { SEP }, 0 },
2576   { "sysexit",          { SEP }, 0 },
2577   { Bad_Opcode },
2578   { "getsec",           { XX }, 0 },
2579   /* 38 */
2580   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) },
2581   { Bad_Opcode },
2582   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) },
2583   { Bad_Opcode },
2584   { Bad_Opcode },
2585   { Bad_Opcode },
2586   { Bad_Opcode },
2587   { Bad_Opcode },
2588   /* 40 */
2589   { "cmovoS",           { Gv, Ev }, 0 },
2590   { "cmovnoS",          { Gv, Ev }, 0 },
2591   { "cmovbS",           { Gv, Ev }, 0 },
2592   { "cmovaeS",          { Gv, Ev }, 0 },
2593   { "cmoveS",           { Gv, Ev }, 0 },
2594   { "cmovneS",          { Gv, Ev }, 0 },
2595   { "cmovbeS",          { Gv, Ev }, 0 },
2596   { "cmovaS",           { Gv, Ev }, 0 },
2597   /* 48 */
2598   { "cmovsS",           { Gv, Ev }, 0 },
2599   { "cmovnsS",          { Gv, Ev }, 0 },
2600   { "cmovpS",           { Gv, Ev }, 0 },
2601   { "cmovnpS",          { Gv, Ev }, 0 },
2602   { "cmovlS",           { Gv, Ev }, 0 },
2603   { "cmovgeS",          { Gv, Ev }, 0 },
2604   { "cmovleS",          { Gv, Ev }, 0 },
2605   { "cmovgS",           { Gv, Ev }, 0 },
2606   /* 50 */
2607   { MOD_TABLE (MOD_0F50) },
2608   { PREFIX_TABLE (PREFIX_0F51) },
2609   { PREFIX_TABLE (PREFIX_0F52) },
2610   { PREFIX_TABLE (PREFIX_0F53) },
2611   { "andpX",            { XM, EXx }, PREFIX_OPCODE },
2612   { "andnpX",           { XM, EXx }, PREFIX_OPCODE },
2613   { "orpX",             { XM, EXx }, PREFIX_OPCODE },
2614   { "xorpX",            { XM, EXx }, PREFIX_OPCODE },
2615   /* 58 */
2616   { PREFIX_TABLE (PREFIX_0F58) },
2617   { PREFIX_TABLE (PREFIX_0F59) },
2618   { PREFIX_TABLE (PREFIX_0F5A) },
2619   { PREFIX_TABLE (PREFIX_0F5B) },
2620   { PREFIX_TABLE (PREFIX_0F5C) },
2621   { PREFIX_TABLE (PREFIX_0F5D) },
2622   { PREFIX_TABLE (PREFIX_0F5E) },
2623   { PREFIX_TABLE (PREFIX_0F5F) },
2624   /* 60 */
2625   { PREFIX_TABLE (PREFIX_0F60) },
2626   { PREFIX_TABLE (PREFIX_0F61) },
2627   { PREFIX_TABLE (PREFIX_0F62) },
2628   { "packsswb",         { MX, EM }, PREFIX_OPCODE },
2629   { "pcmpgtb",          { MX, EM }, PREFIX_OPCODE },
2630   { "pcmpgtw",          { MX, EM }, PREFIX_OPCODE },
2631   { "pcmpgtd",          { MX, EM }, PREFIX_OPCODE },
2632   { "packuswb",         { MX, EM }, PREFIX_OPCODE },
2633   /* 68 */
2634   { "punpckhbw",        { MX, EM }, PREFIX_OPCODE },
2635   { "punpckhwd",        { MX, EM }, PREFIX_OPCODE },
2636   { "punpckhdq",        { MX, EM }, PREFIX_OPCODE },
2637   { "packssdw",         { MX, EM }, PREFIX_OPCODE },
2638   { PREFIX_TABLE (PREFIX_0F6C) },
2639   { PREFIX_TABLE (PREFIX_0F6D) },
2640   { "movK",             { MX, Edq }, PREFIX_OPCODE },
2641   { PREFIX_TABLE (PREFIX_0F6F) },
2642   /* 70 */
2643   { PREFIX_TABLE (PREFIX_0F70) },
2644   { REG_TABLE (REG_0F71) },
2645   { REG_TABLE (REG_0F72) },
2646   { REG_TABLE (REG_0F73) },
2647   { "pcmpeqb",          { MX, EM }, PREFIX_OPCODE },
2648   { "pcmpeqw",          { MX, EM }, PREFIX_OPCODE },
2649   { "pcmpeqd",          { MX, EM }, PREFIX_OPCODE },
2650   { "emms",             { XX }, PREFIX_OPCODE },
2651   /* 78 */
2652   { PREFIX_TABLE (PREFIX_0F78) },
2653   { PREFIX_TABLE (PREFIX_0F79) },
2654   { Bad_Opcode },
2655   { Bad_Opcode },
2656   { PREFIX_TABLE (PREFIX_0F7C) },
2657   { PREFIX_TABLE (PREFIX_0F7D) },
2658   { PREFIX_TABLE (PREFIX_0F7E) },
2659   { PREFIX_TABLE (PREFIX_0F7F) },
2660   /* 80 */
2661   { "joH",              { Jv, BND, cond_jump_flag }, 0 },
2662   { "jnoH",             { Jv, BND, cond_jump_flag }, 0 },
2663   { "jbH",              { Jv, BND, cond_jump_flag }, 0 },
2664   { "jaeH",             { Jv, BND, cond_jump_flag }, 0 },
2665   { "jeH",              { Jv, BND, cond_jump_flag }, 0 },
2666   { "jneH",             { Jv, BND, cond_jump_flag }, 0 },
2667   { "jbeH",             { Jv, BND, cond_jump_flag }, 0 },
2668   { "jaH",              { Jv, BND, cond_jump_flag }, 0 },
2669   /* 88 */
2670   { "jsH",              { Jv, BND, cond_jump_flag }, 0 },
2671   { "jnsH",             { Jv, BND, cond_jump_flag }, 0 },
2672   { "jpH",              { Jv, BND, cond_jump_flag }, 0 },
2673   { "jnpH",             { Jv, BND, cond_jump_flag }, 0 },
2674   { "jlH",              { Jv, BND, cond_jump_flag }, 0 },
2675   { "jgeH",             { Jv, BND, cond_jump_flag }, 0 },
2676   { "jleH",             { Jv, BND, cond_jump_flag }, 0 },
2677   { "jgH",              { Jv, BND, cond_jump_flag }, 0 },
2678   /* 90 */
2679   { "seto",             { Eb }, 0 },
2680   { "setno",            { Eb }, 0 },
2681   { "setb",             { Eb }, 0 },
2682   { "setae",            { Eb }, 0 },
2683   { "sete",             { Eb }, 0 },
2684   { "setne",            { Eb }, 0 },
2685   { "setbe",            { Eb }, 0 },
2686   { "seta",             { Eb }, 0 },
2687   /* 98 */
2688   { "sets",             { Eb }, 0 },
2689   { "setns",            { Eb }, 0 },
2690   { "setp",             { Eb }, 0 },
2691   { "setnp",            { Eb }, 0 },
2692   { "setl",             { Eb }, 0 },
2693   { "setge",            { Eb }, 0 },
2694   { "setle",            { Eb }, 0 },
2695   { "setg",             { Eb }, 0 },
2696   /* a0 */
2697   { "pushT",            { fs }, 0 },
2698   { "popT",             { fs }, 0 },
2699   { "cpuid",            { XX }, 0 },
2700   { "btS",              { Ev, Gv }, 0 },
2701   { "shldS",            { Ev, Gv, Ib }, 0 },
2702   { "shldS",            { Ev, Gv, CL }, 0 },
2703   { REG_TABLE (REG_0FA6) },
2704   { REG_TABLE (REG_0FA7) },
2705   /* a8 */
2706   { "pushT",            { gs }, 0 },
2707   { "popT",             { gs }, 0 },
2708   { "rsm",              { XX }, 0 },
2709   { "btsS",             { Evh1, Gv }, 0 },
2710   { "shrdS",            { Ev, Gv, Ib }, 0 },
2711   { "shrdS",            { Ev, Gv, CL }, 0 },
2712   { REG_TABLE (REG_0FAE) },
2713   { "imulS",            { Gv, Ev }, 0 },
2714   /* b0 */
2715   { "cmpxchgB",         { Ebh1, Gb }, 0 },
2716   { "cmpxchgS",         { Evh1, Gv }, 0 },
2717   { MOD_TABLE (MOD_0FB2) },
2718   { "btrS",             { Evh1, Gv }, 0 },
2719   { MOD_TABLE (MOD_0FB4) },
2720   { MOD_TABLE (MOD_0FB5) },
2721   { "movz{bR|x}",       { Gv, Eb }, 0 },
2722   { "movz{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movzww ! */
2723   /* b8 */
2724   { PREFIX_TABLE (PREFIX_0FB8) },
2725   { "ud1S",             { Gv, Ev }, 0 },
2726   { REG_TABLE (REG_0FBA) },
2727   { "btcS",             { Evh1, Gv }, 0 },
2728   { PREFIX_TABLE (PREFIX_0FBC) },
2729   { PREFIX_TABLE (PREFIX_0FBD) },
2730   { "movs{bR|x}",       { Gv, Eb }, 0 },
2731   { "movs{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movsww ! */
2732   /* c0 */
2733   { "xaddB",            { Ebh1, Gb }, 0 },
2734   { "xaddS",            { Evh1, Gv }, 0 },
2735   { PREFIX_TABLE (PREFIX_0FC2) },
2736   { MOD_TABLE (MOD_0FC3) },
2737   { "pinsrw",           { MX, Edqw, Ib }, PREFIX_OPCODE },
2738   { "pextrw",           { Gdq, MS, Ib }, PREFIX_OPCODE },
2739   { "shufpX",           { XM, EXx, Ib }, PREFIX_OPCODE },
2740   { REG_TABLE (REG_0FC7) },
2741   /* c8 */
2742   { "bswap",            { RMeAX }, 0 },
2743   { "bswap",            { RMeCX }, 0 },
2744   { "bswap",            { RMeDX }, 0 },
2745   { "bswap",            { RMeBX }, 0 },
2746   { "bswap",            { RMeSP }, 0 },
2747   { "bswap",            { RMeBP }, 0 },
2748   { "bswap",            { RMeSI }, 0 },
2749   { "bswap",            { RMeDI }, 0 },
2750   /* d0 */
2751   { PREFIX_TABLE (PREFIX_0FD0) },
2752   { "psrlw",            { MX, EM }, PREFIX_OPCODE },
2753   { "psrld",            { MX, EM }, PREFIX_OPCODE },
2754   { "psrlq",            { MX, EM }, PREFIX_OPCODE },
2755   { "paddq",            { MX, EM }, PREFIX_OPCODE },
2756   { "pmullw",           { MX, EM }, PREFIX_OPCODE },
2757   { PREFIX_TABLE (PREFIX_0FD6) },
2758   { MOD_TABLE (MOD_0FD7) },
2759   /* d8 */
2760   { "psubusb",          { MX, EM }, PREFIX_OPCODE },
2761   { "psubusw",          { MX, EM }, PREFIX_OPCODE },
2762   { "pminub",           { MX, EM }, PREFIX_OPCODE },
2763   { "pand",             { MX, EM }, PREFIX_OPCODE },
2764   { "paddusb",          { MX, EM }, PREFIX_OPCODE },
2765   { "paddusw",          { MX, EM }, PREFIX_OPCODE },
2766   { "pmaxub",           { MX, EM }, PREFIX_OPCODE },
2767   { "pandn",            { MX, EM }, PREFIX_OPCODE },
2768   /* e0 */
2769   { "pavgb",            { MX, EM }, PREFIX_OPCODE },
2770   { "psraw",            { MX, EM }, PREFIX_OPCODE },
2771   { "psrad",            { MX, EM }, PREFIX_OPCODE },
2772   { "pavgw",            { MX, EM }, PREFIX_OPCODE },
2773   { "pmulhuw",          { MX, EM }, PREFIX_OPCODE },
2774   { "pmulhw",           { MX, EM }, PREFIX_OPCODE },
2775   { PREFIX_TABLE (PREFIX_0FE6) },
2776   { PREFIX_TABLE (PREFIX_0FE7) },
2777   /* e8 */
2778   { "psubsb",           { MX, EM }, PREFIX_OPCODE },
2779   { "psubsw",           { MX, EM }, PREFIX_OPCODE },
2780   { "pminsw",           { MX, EM }, PREFIX_OPCODE },
2781   { "por",              { MX, EM }, PREFIX_OPCODE },
2782   { "paddsb",           { MX, EM }, PREFIX_OPCODE },
2783   { "paddsw",           { MX, EM }, PREFIX_OPCODE },
2784   { "pmaxsw",           { MX, EM }, PREFIX_OPCODE },
2785   { "pxor",             { MX, EM }, PREFIX_OPCODE },
2786   /* f0 */
2787   { PREFIX_TABLE (PREFIX_0FF0) },
2788   { "psllw",            { MX, EM }, PREFIX_OPCODE },
2789   { "pslld",            { MX, EM }, PREFIX_OPCODE },
2790   { "psllq",            { MX, EM }, PREFIX_OPCODE },
2791   { "pmuludq",          { MX, EM }, PREFIX_OPCODE },
2792   { "pmaddwd",          { MX, EM }, PREFIX_OPCODE },
2793   { "psadbw",           { MX, EM }, PREFIX_OPCODE },
2794   { PREFIX_TABLE (PREFIX_0FF7) },
2795   /* f8 */
2796   { "psubb",            { MX, EM }, PREFIX_OPCODE },
2797   { "psubw",            { MX, EM }, PREFIX_OPCODE },
2798   { "psubd",            { MX, EM }, PREFIX_OPCODE },
2799   { "psubq",            { MX, EM }, PREFIX_OPCODE },
2800   { "paddb",            { MX, EM }, PREFIX_OPCODE },
2801   { "paddw",            { MX, EM }, PREFIX_OPCODE },
2802   { "paddd",            { MX, EM }, PREFIX_OPCODE },
2803   { "ud0S",             { Gv, Ev }, 0 },
2804 };
2805
2806 static const unsigned char onebyte_has_modrm[256] = {
2807   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2808   /*       -------------------------------        */
2809   /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2810   /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2811   /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2812   /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2813   /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2814   /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2815   /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2816   /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2817   /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2818   /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2819   /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2820   /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2821   /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2822   /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2823   /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2824   /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1  /* f0 */
2825   /*       -------------------------------        */
2826   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2827 };
2828
2829 static const unsigned char twobyte_has_modrm[256] = {
2830   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2831   /*       -------------------------------        */
2832   /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2833   /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2834   /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2835   /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2836   /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2837   /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2838   /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2839   /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2840   /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2841   /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2842   /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2843   /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */
2844   /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2845   /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2846   /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2847   /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1  /* ff */
2848   /*       -------------------------------        */
2849   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2850 };
2851
2852 static char obuf[100];
2853 static char *obufp;
2854 static char *mnemonicendp;
2855 static char scratchbuf[100];
2856 static unsigned char *start_codep;
2857 static unsigned char *insn_codep;
2858 static unsigned char *codep;
2859 static unsigned char *end_codep;
2860 static int last_lock_prefix;
2861 static int last_repz_prefix;
2862 static int last_repnz_prefix;
2863 static int last_data_prefix;
2864 static int last_addr_prefix;
2865 static int last_rex_prefix;
2866 static int last_seg_prefix;
2867 static int fwait_prefix;
2868 /* The active segment register prefix.  */
2869 static int active_seg_prefix;
2870 #define MAX_CODE_LENGTH 15
2871 /* We can up to 14 prefixes since the maximum instruction length is
2872    15bytes.  */
2873 static int all_prefixes[MAX_CODE_LENGTH - 1];
2874 static disassemble_info *the_info;
2875 static struct
2876   {
2877     int mod;
2878     int reg;
2879     int rm;
2880   }
2881 modrm;
2882 static unsigned char need_modrm;
2883 static struct
2884   {
2885     int scale;
2886     int index;
2887     int base;
2888   }
2889 sib;
2890 static struct
2891   {
2892     int register_specifier;
2893     int length;
2894     int prefix;
2895     int w;
2896     int evex;
2897     int r;
2898     int v;
2899     int mask_register_specifier;
2900     int zeroing;
2901     int ll;
2902     int b;
2903   }
2904 vex;
2905 static unsigned char need_vex;
2906 static unsigned char need_vex_reg;
2907 static unsigned char vex_w_done;
2908
2909 struct op
2910   {
2911     const char *name;
2912     unsigned int len;
2913   };
2914
2915 /* If we are accessing mod/rm/reg without need_modrm set, then the
2916    values are stale.  Hitting this abort likely indicates that you
2917    need to update onebyte_has_modrm or twobyte_has_modrm.  */
2918 #define MODRM_CHECK  if (!need_modrm) abort ()
2919
2920 static const char **names64;
2921 static const char **names32;
2922 static const char **names16;
2923 static const char **names8;
2924 static const char **names8rex;
2925 static const char **names_seg;
2926 static const char *index64;
2927 static const char *index32;
2928 static const char **index16;
2929 static const char **names_bnd;
2930
2931 static const char *intel_names64[] = {
2932   "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
2933   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
2934 };
2935 static const char *intel_names32[] = {
2936   "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
2937   "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
2938 };
2939 static const char *intel_names16[] = {
2940   "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
2941   "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
2942 };
2943 static const char *intel_names8[] = {
2944   "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
2945 };
2946 static const char *intel_names8rex[] = {
2947   "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
2948   "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
2949 };
2950 static const char *intel_names_seg[] = {
2951   "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
2952 };
2953 static const char *intel_index64 = "riz";
2954 static const char *intel_index32 = "eiz";
2955 static const char *intel_index16[] = {
2956   "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
2957 };
2958
2959 static const char *att_names64[] = {
2960   "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
2961   "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
2962 };
2963 static const char *att_names32[] = {
2964   "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
2965   "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
2966 };
2967 static const char *att_names16[] = {
2968   "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
2969   "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
2970 };
2971 static const char *att_names8[] = {
2972   "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
2973 };
2974 static const char *att_names8rex[] = {
2975   "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
2976   "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
2977 };
2978 static const char *att_names_seg[] = {
2979   "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
2980 };
2981 static const char *att_index64 = "%riz";
2982 static const char *att_index32 = "%eiz";
2983 static const char *att_index16[] = {
2984   "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
2985 };
2986
2987 static const char **names_mm;
2988 static const char *intel_names_mm[] = {
2989   "mm0", "mm1", "mm2", "mm3",
2990   "mm4", "mm5", "mm6", "mm7"
2991 };
2992 static const char *att_names_mm[] = {
2993   "%mm0", "%mm1", "%mm2", "%mm3",
2994   "%mm4", "%mm5", "%mm6", "%mm7"
2995 };
2996
2997 static const char *intel_names_bnd[] = {
2998   "bnd0", "bnd1", "bnd2", "bnd3"
2999 };
3000
3001 static const char *att_names_bnd[] = {
3002   "%bnd0", "%bnd1", "%bnd2", "%bnd3"
3003 };
3004
3005 static const char **names_xmm;
3006 static const char *intel_names_xmm[] = {
3007   "xmm0", "xmm1", "xmm2", "xmm3",
3008   "xmm4", "xmm5", "xmm6", "xmm7",
3009   "xmm8", "xmm9", "xmm10", "xmm11",
3010   "xmm12", "xmm13", "xmm14", "xmm15",
3011   "xmm16", "xmm17", "xmm18", "xmm19",
3012   "xmm20", "xmm21", "xmm22", "xmm23",
3013   "xmm24", "xmm25", "xmm26", "xmm27",
3014   "xmm28", "xmm29", "xmm30", "xmm31"
3015 };
3016 static const char *att_names_xmm[] = {
3017   "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3018   "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3019   "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3020   "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3021   "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3022   "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3023   "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3024   "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3025 };
3026
3027 static const char **names_ymm;
3028 static const char *intel_names_ymm[] = {
3029   "ymm0", "ymm1", "ymm2", "ymm3",
3030   "ymm4", "ymm5", "ymm6", "ymm7",
3031   "ymm8", "ymm9", "ymm10", "ymm11",
3032   "ymm12", "ymm13", "ymm14", "ymm15",
3033   "ymm16", "ymm17", "ymm18", "ymm19",
3034   "ymm20", "ymm21", "ymm22", "ymm23",
3035   "ymm24", "ymm25", "ymm26", "ymm27",
3036   "ymm28", "ymm29", "ymm30", "ymm31"
3037 };
3038 static const char *att_names_ymm[] = {
3039   "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3040   "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3041   "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3042   "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3043   "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3044   "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3045   "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3046   "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3047 };
3048
3049 static const char **names_zmm;
3050 static const char *intel_names_zmm[] = {
3051   "zmm0", "zmm1", "zmm2", "zmm3",
3052   "zmm4", "zmm5", "zmm6", "zmm7",
3053   "zmm8", "zmm9", "zmm10", "zmm11",
3054   "zmm12", "zmm13", "zmm14", "zmm15",
3055   "zmm16", "zmm17", "zmm18", "zmm19",
3056   "zmm20", "zmm21", "zmm22", "zmm23",
3057   "zmm24", "zmm25", "zmm26", "zmm27",
3058   "zmm28", "zmm29", "zmm30", "zmm31"
3059 };
3060 static const char *att_names_zmm[] = {
3061   "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3062   "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3063   "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3064   "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3065   "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3066   "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3067   "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3068   "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3069 };
3070
3071 static const char **names_mask;
3072 static const char *intel_names_mask[] = {
3073   "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3074 };
3075 static const char *att_names_mask[] = {
3076   "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3077 };
3078
3079 static const char *names_rounding[] =
3080 {
3081   "{rn-sae}",
3082   "{rd-sae}",
3083   "{ru-sae}",
3084   "{rz-sae}"
3085 };
3086
3087 static const struct dis386 reg_table[][8] = {
3088   /* REG_80 */
3089   {
3090     { "addA",   { Ebh1, Ib }, 0 },
3091     { "orA",    { Ebh1, Ib }, 0 },
3092     { "adcA",   { Ebh1, Ib }, 0 },
3093     { "sbbA",   { Ebh1, Ib }, 0 },
3094     { "andA",   { Ebh1, Ib }, 0 },
3095     { "subA",   { Ebh1, Ib }, 0 },
3096     { "xorA",   { Ebh1, Ib }, 0 },
3097     { "cmpA",   { Eb, Ib }, 0 },
3098   },
3099   /* REG_81 */
3100   {
3101     { "addQ",   { Evh1, Iv }, 0 },
3102     { "orQ",    { Evh1, Iv }, 0 },
3103     { "adcQ",   { Evh1, Iv }, 0 },
3104     { "sbbQ",   { Evh1, Iv }, 0 },
3105     { "andQ",   { Evh1, Iv }, 0 },
3106     { "subQ",   { Evh1, Iv }, 0 },
3107     { "xorQ",   { Evh1, Iv }, 0 },
3108     { "cmpQ",   { Ev, Iv }, 0 },
3109   },
3110   /* REG_83 */
3111   {
3112     { "addQ",   { Evh1, sIb }, 0 },
3113     { "orQ",    { Evh1, sIb }, 0 },
3114     { "adcQ",   { Evh1, sIb }, 0 },
3115     { "sbbQ",   { Evh1, sIb }, 0 },
3116     { "andQ",   { Evh1, sIb }, 0 },
3117     { "subQ",   { Evh1, sIb }, 0 },
3118     { "xorQ",   { Evh1, sIb }, 0 },
3119     { "cmpQ",   { Ev, sIb }, 0 },
3120   },
3121   /* REG_8F */
3122   {
3123     { "popU",   { stackEv }, 0 },
3124     { XOP_8F_TABLE (XOP_09) },
3125     { Bad_Opcode },
3126     { Bad_Opcode },
3127     { Bad_Opcode },
3128     { XOP_8F_TABLE (XOP_09) },
3129   },
3130   /* REG_C0 */
3131   {
3132     { "rolA",   { Eb, Ib }, 0 },
3133     { "rorA",   { Eb, Ib }, 0 },
3134     { "rclA",   { Eb, Ib }, 0 },
3135     { "rcrA",   { Eb, Ib }, 0 },
3136     { "shlA",   { Eb, Ib }, 0 },
3137     { "shrA",   { Eb, Ib }, 0 },
3138     { "shlA",   { Eb, Ib }, 0 },
3139     { "sarA",   { Eb, Ib }, 0 },
3140   },
3141   /* REG_C1 */
3142   {
3143     { "rolQ",   { Ev, Ib }, 0 },
3144     { "rorQ",   { Ev, Ib }, 0 },
3145     { "rclQ",   { Ev, Ib }, 0 },
3146     { "rcrQ",   { Ev, Ib }, 0 },
3147     { "shlQ",   { Ev, Ib }, 0 },
3148     { "shrQ",   { Ev, Ib }, 0 },
3149     { "shlQ",   { Ev, Ib }, 0 },
3150     { "sarQ",   { Ev, Ib }, 0 },
3151   },
3152   /* REG_C6 */
3153   {
3154     { "movA",   { Ebh3, Ib }, 0 },
3155     { Bad_Opcode },
3156     { Bad_Opcode },
3157     { Bad_Opcode },
3158     { Bad_Opcode },
3159     { Bad_Opcode },
3160     { Bad_Opcode },
3161     { MOD_TABLE (MOD_C6_REG_7) },
3162   },
3163   /* REG_C7 */
3164   {
3165     { "movQ",   { Evh3, Iv }, 0 },
3166     { Bad_Opcode },
3167     { Bad_Opcode },
3168     { Bad_Opcode },
3169     { Bad_Opcode },
3170     { Bad_Opcode },
3171     { Bad_Opcode },
3172     { MOD_TABLE (MOD_C7_REG_7) },
3173   },
3174   /* REG_D0 */
3175   {
3176     { "rolA",   { Eb, I1 }, 0 },
3177     { "rorA",   { Eb, I1 }, 0 },
3178     { "rclA",   { Eb, I1 }, 0 },
3179     { "rcrA",   { Eb, I1 }, 0 },
3180     { "shlA",   { Eb, I1 }, 0 },
3181     { "shrA",   { Eb, I1 }, 0 },
3182     { "shlA",   { Eb, I1 }, 0 },
3183     { "sarA",   { Eb, I1 }, 0 },
3184   },
3185   /* REG_D1 */
3186   {
3187     { "rolQ",   { Ev, I1 }, 0 },
3188     { "rorQ",   { Ev, I1 }, 0 },
3189     { "rclQ",   { Ev, I1 }, 0 },
3190     { "rcrQ",   { Ev, I1 }, 0 },
3191     { "shlQ",   { Ev, I1 }, 0 },
3192     { "shrQ",   { Ev, I1 }, 0 },
3193     { "shlQ",   { Ev, I1 }, 0 },
3194     { "sarQ",   { Ev, I1 }, 0 },
3195   },
3196   /* REG_D2 */
3197   {
3198     { "rolA",   { Eb, CL }, 0 },
3199     { "rorA",   { Eb, CL }, 0 },
3200     { "rclA",   { Eb, CL }, 0 },
3201     { "rcrA",   { Eb, CL }, 0 },
3202     { "shlA",   { Eb, CL }, 0 },
3203     { "shrA",   { Eb, CL }, 0 },
3204     { "shlA",   { Eb, CL }, 0 },
3205     { "sarA",   { Eb, CL }, 0 },
3206   },
3207   /* REG_D3 */
3208   {
3209     { "rolQ",   { Ev, CL }, 0 },
3210     { "rorQ",   { Ev, CL }, 0 },
3211     { "rclQ",   { Ev, CL }, 0 },
3212     { "rcrQ",   { Ev, CL }, 0 },
3213     { "shlQ",   { Ev, CL }, 0 },
3214     { "shrQ",   { Ev, CL }, 0 },
3215     { "shlQ",   { Ev, CL }, 0 },
3216     { "sarQ",   { Ev, CL }, 0 },
3217   },
3218   /* REG_F6 */
3219   {
3220     { "testA",  { Eb, Ib }, 0 },
3221     { "testA",  { Eb, Ib }, 0 },
3222     { "notA",   { Ebh1 }, 0 },
3223     { "negA",   { Ebh1 }, 0 },
3224     { "mulA",   { Eb }, 0 },    /* Don't print the implicit %al register,  */
3225     { "imulA",  { Eb }, 0 },    /* to distinguish these opcodes from other */
3226     { "divA",   { Eb }, 0 },    /* mul/imul opcodes.  Do the same for div  */
3227     { "idivA",  { Eb }, 0 },    /* and idiv for consistency.               */
3228   },
3229   /* REG_F7 */
3230   {
3231     { "testQ",  { Ev, Iv }, 0 },
3232     { "testQ",  { Ev, Iv }, 0 },
3233     { "notQ",   { Evh1 }, 0 },
3234     { "negQ",   { Evh1 }, 0 },
3235     { "mulQ",   { Ev }, 0 },    /* Don't print the implicit register.  */
3236     { "imulQ",  { Ev }, 0 },
3237     { "divQ",   { Ev }, 0 },
3238     { "idivQ",  { Ev }, 0 },
3239   },
3240   /* REG_FE */
3241   {
3242     { "incA",   { Ebh1 }, 0 },
3243     { "decA",   { Ebh1 }, 0 },
3244   },
3245   /* REG_FF */
3246   {
3247     { "incQ",   { Evh1 }, 0 },
3248     { "decQ",   { Evh1 }, 0 },
3249     { "call{&|}", { NOTRACK, indirEv, BND }, 0 },
3250     { MOD_TABLE (MOD_FF_REG_3) },
3251     { "jmp{&|}", { NOTRACK, indirEv, BND }, 0 },
3252     { MOD_TABLE (MOD_FF_REG_5) },
3253     { "pushU",  { stackEv }, 0 },
3254     { Bad_Opcode },
3255   },
3256   /* REG_0F00 */
3257   {
3258     { "sldtD",  { Sv }, 0 },
3259     { "strD",   { Sv }, 0 },
3260     { "lldt",   { Ew }, 0 },
3261     { "ltr",    { Ew }, 0 },
3262     { "verr",   { Ew }, 0 },
3263     { "verw",   { Ew }, 0 },
3264     { Bad_Opcode },
3265     { Bad_Opcode },
3266   },
3267   /* REG_0F01 */
3268   {
3269     { MOD_TABLE (MOD_0F01_REG_0) },
3270     { MOD_TABLE (MOD_0F01_REG_1) },
3271     { MOD_TABLE (MOD_0F01_REG_2) },
3272     { MOD_TABLE (MOD_0F01_REG_3) },
3273     { "smswD",  { Sv }, 0 },
3274     { MOD_TABLE (MOD_0F01_REG_5) },
3275     { "lmsw",   { Ew }, 0 },
3276     { MOD_TABLE (MOD_0F01_REG_7) },
3277   },
3278   /* REG_0F0D */
3279   {
3280     { "prefetch",       { Mb }, 0 },
3281     { "prefetchw",      { Mb }, 0 },
3282     { "prefetchwt1",    { Mb }, 0 },
3283     { "prefetch",       { Mb }, 0 },
3284     { "prefetch",       { Mb }, 0 },
3285     { "prefetch",       { Mb }, 0 },
3286     { "prefetch",       { Mb }, 0 },
3287     { "prefetch",       { Mb }, 0 },
3288   },
3289   /* REG_0F18 */
3290   {
3291     { MOD_TABLE (MOD_0F18_REG_0) },
3292     { MOD_TABLE (MOD_0F18_REG_1) },
3293     { MOD_TABLE (MOD_0F18_REG_2) },
3294     { MOD_TABLE (MOD_0F18_REG_3) },
3295     { MOD_TABLE (MOD_0F18_REG_4) },
3296     { MOD_TABLE (MOD_0F18_REG_5) },
3297     { MOD_TABLE (MOD_0F18_REG_6) },
3298     { MOD_TABLE (MOD_0F18_REG_7) },
3299   },
3300   /* REG_0F1C_P_0_MOD_0 */
3301   {
3302     { "cldemote",       { Mb }, 0 },
3303     { "nopQ",           { Ev }, 0 },
3304     { "nopQ",           { Ev }, 0 },
3305     { "nopQ",           { Ev }, 0 },
3306     { "nopQ",           { Ev }, 0 },
3307     { "nopQ",           { Ev }, 0 },
3308     { "nopQ",           { Ev }, 0 },
3309     { "nopQ",           { Ev }, 0 },
3310   },
3311   /* REG_0F1E_P_1_MOD_3 */
3312   {
3313     { "nopQ",           { Ev }, 0 },
3314     { "rdsspK",         { Rdq }, PREFIX_OPCODE },
3315     { "nopQ",           { Ev }, 0 },
3316     { "nopQ",           { Ev }, 0 },
3317     { "nopQ",           { Ev }, 0 },
3318     { "nopQ",           { Ev }, 0 },
3319     { "nopQ",           { Ev }, 0 },
3320     { RM_TABLE (RM_0F1E_P_1_MOD_3_REG_7) },
3321   },
3322   /* REG_0F71 */
3323   {
3324     { Bad_Opcode },
3325     { Bad_Opcode },
3326     { MOD_TABLE (MOD_0F71_REG_2) },
3327     { Bad_Opcode },
3328     { MOD_TABLE (MOD_0F71_REG_4) },
3329     { Bad_Opcode },
3330     { MOD_TABLE (MOD_0F71_REG_6) },
3331   },
3332   /* REG_0F72 */
3333   {
3334     { Bad_Opcode },
3335     { Bad_Opcode },
3336     { MOD_TABLE (MOD_0F72_REG_2) },
3337     { Bad_Opcode },
3338     { MOD_TABLE (MOD_0F72_REG_4) },
3339     { Bad_Opcode },
3340     { MOD_TABLE (MOD_0F72_REG_6) },
3341   },
3342   /* REG_0F73 */
3343   {
3344     { Bad_Opcode },
3345     { Bad_Opcode },
3346     { MOD_TABLE (MOD_0F73_REG_2) },
3347     { MOD_TABLE (MOD_0F73_REG_3) },
3348     { Bad_Opcode },
3349     { Bad_Opcode },
3350     { MOD_TABLE (MOD_0F73_REG_6) },
3351     { MOD_TABLE (MOD_0F73_REG_7) },
3352   },
3353   /* REG_0FA6 */
3354   {
3355     { "montmul",        { { OP_0f07, 0 } }, 0 },
3356     { "xsha1",          { { OP_0f07, 0 } }, 0 },
3357     { "xsha256",        { { OP_0f07, 0 } }, 0 },
3358   },
3359   /* REG_0FA7 */
3360   {
3361     { "xstore-rng",     { { OP_0f07, 0 } }, 0 },
3362     { "xcrypt-ecb",     { { OP_0f07, 0 } }, 0 },
3363     { "xcrypt-cbc",     { { OP_0f07, 0 } }, 0 },
3364     { "xcrypt-ctr",     { { OP_0f07, 0 } }, 0 },
3365     { "xcrypt-cfb",     { { OP_0f07, 0 } }, 0 },
3366     { "xcrypt-ofb",     { { OP_0f07, 0 } }, 0 },
3367   },
3368   /* REG_0FAE */
3369   {
3370     { MOD_TABLE (MOD_0FAE_REG_0) },
3371     { MOD_TABLE (MOD_0FAE_REG_1) },
3372     { MOD_TABLE (MOD_0FAE_REG_2) },
3373     { MOD_TABLE (MOD_0FAE_REG_3) },
3374     { MOD_TABLE (MOD_0FAE_REG_4) },
3375     { MOD_TABLE (MOD_0FAE_REG_5) },
3376     { MOD_TABLE (MOD_0FAE_REG_6) },
3377     { MOD_TABLE (MOD_0FAE_REG_7) },
3378   },
3379   /* REG_0FBA */
3380   {
3381     { Bad_Opcode },
3382     { Bad_Opcode },
3383     { Bad_Opcode },
3384     { Bad_Opcode },
3385     { "btQ",    { Ev, Ib }, 0 },
3386     { "btsQ",   { Evh1, Ib }, 0 },
3387     { "btrQ",   { Evh1, Ib }, 0 },
3388     { "btcQ",   { Evh1, Ib }, 0 },
3389   },
3390   /* REG_0FC7 */
3391   {
3392     { Bad_Opcode },
3393     { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 },
3394     { Bad_Opcode },
3395     { MOD_TABLE (MOD_0FC7_REG_3) },
3396     { MOD_TABLE (MOD_0FC7_REG_4) },
3397     { MOD_TABLE (MOD_0FC7_REG_5) },
3398     { MOD_TABLE (MOD_0FC7_REG_6) },
3399     { MOD_TABLE (MOD_0FC7_REG_7) },
3400   },
3401   /* REG_VEX_0F71 */
3402   {
3403     { Bad_Opcode },
3404     { Bad_Opcode },
3405     { MOD_TABLE (MOD_VEX_0F71_REG_2) },
3406     { Bad_Opcode },
3407     { MOD_TABLE (MOD_VEX_0F71_REG_4) },
3408     { Bad_Opcode },
3409     { MOD_TABLE (MOD_VEX_0F71_REG_6) },
3410   },
3411   /* REG_VEX_0F72 */
3412   {
3413     { Bad_Opcode },
3414     { Bad_Opcode },
3415     { MOD_TABLE (MOD_VEX_0F72_REG_2) },
3416     { Bad_Opcode },
3417     { MOD_TABLE (MOD_VEX_0F72_REG_4) },
3418     { Bad_Opcode },
3419     { MOD_TABLE (MOD_VEX_0F72_REG_6) },
3420   },
3421   /* REG_VEX_0F73 */
3422   {
3423     { Bad_Opcode },
3424     { Bad_Opcode },
3425     { MOD_TABLE (MOD_VEX_0F73_REG_2) },
3426     { MOD_TABLE (MOD_VEX_0F73_REG_3) },
3427     { Bad_Opcode },
3428     { Bad_Opcode },
3429     { MOD_TABLE (MOD_VEX_0F73_REG_6) },
3430     { MOD_TABLE (MOD_VEX_0F73_REG_7) },
3431   },
3432   /* REG_VEX_0FAE */
3433   {
3434     { Bad_Opcode },
3435     { Bad_Opcode },
3436     { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
3437     { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
3438   },
3439   /* REG_VEX_0F38F3 */
3440   {
3441     { Bad_Opcode },
3442     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) },
3443     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) },
3444     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) },
3445   },
3446   /* REG_XOP_LWPCB */
3447   {
3448     { "llwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3449     { "slwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3450   },
3451   /* REG_XOP_LWP */
3452   {
3453     { "lwpins", { { OP_LWP_E, 0 }, Ed, Id }, 0 },
3454     { "lwpval", { { OP_LWP_E, 0 }, Ed, Id }, 0 },
3455   },
3456   /* REG_XOP_TBM_01 */
3457   {
3458     { Bad_Opcode },
3459     { "blcfill",        { { OP_LWP_E, 0 }, Edq }, 0 },
3460     { "blsfill",        { { OP_LWP_E, 0 }, Edq }, 0 },
3461     { "blcs",   { { OP_LWP_E, 0 }, Edq }, 0 },
3462     { "tzmsk",  { { OP_LWP_E, 0 }, Edq }, 0 },
3463     { "blcic",  { { OP_LWP_E, 0 }, Edq }, 0 },
3464     { "blsic",  { { OP_LWP_E, 0 }, Edq }, 0 },
3465     { "t1mskc", { { OP_LWP_E, 0 }, Edq }, 0 },
3466   },
3467   /* REG_XOP_TBM_02 */
3468   {
3469     { Bad_Opcode },
3470     { "blcmsk", { { OP_LWP_E, 0 }, Edq }, 0 },
3471     { Bad_Opcode },
3472     { Bad_Opcode },
3473     { Bad_Opcode },
3474     { Bad_Opcode },
3475     { "blci",   { { OP_LWP_E, 0 }, Edq }, 0 },
3476   },
3477
3478 #include "i386-dis-evex-reg.h"
3479 };
3480
3481 static const struct dis386 prefix_table[][4] = {
3482   /* PREFIX_90 */
3483   {
3484     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3485     { "pause", { XX }, 0 },
3486     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3487     { NULL, { { NULL, 0 } }, PREFIX_IGNORED }
3488   },
3489
3490   /* PREFIX_0F01_REG_3_RM_1 */
3491   {
3492     { "vmmcall",        { Skip_MODRM }, 0 },
3493     { "vmgexit",        { Skip_MODRM }, 0 },
3494     { Bad_Opcode },
3495     { "vmgexit",        { Skip_MODRM }, 0 },
3496   },
3497
3498   /* PREFIX_0F01_REG_5_MOD_0 */
3499   {
3500     { Bad_Opcode },
3501     { "rstorssp",       { Mq }, PREFIX_OPCODE },
3502   },
3503
3504   /* PREFIX_0F01_REG_5_MOD_3_RM_0 */
3505   {
3506     { "serialize",      { Skip_MODRM }, PREFIX_OPCODE },
3507     { "setssbsy",       { Skip_MODRM }, PREFIX_OPCODE },
3508     { Bad_Opcode },
3509     { "xsusldtrk",      { Skip_MODRM }, PREFIX_OPCODE },
3510   },
3511
3512   /* PREFIX_0F01_REG_5_MOD_3_RM_1 */
3513   {
3514     { Bad_Opcode },
3515     { Bad_Opcode },
3516     { Bad_Opcode },
3517     { "xresldtrk",     { Skip_MODRM }, PREFIX_OPCODE },
3518   },
3519
3520   /* PREFIX_0F01_REG_5_MOD_3_RM_2 */
3521   {
3522     { Bad_Opcode },
3523     { "saveprevssp",    { Skip_MODRM }, PREFIX_OPCODE },
3524   },
3525
3526   /* PREFIX_0F01_REG_7_MOD_3_RM_2 */
3527   {
3528     { "monitorx",       { { OP_Monitor, 0 } }, 0  },
3529     { "mcommit",        { Skip_MODRM }, 0 },
3530   },
3531
3532   /* PREFIX_0F01_REG_7_MOD_3_RM_3 */
3533   {
3534     { "mwaitx",         { { OP_Mwait, eBX_reg } }, 0  },
3535   },
3536
3537   /* PREFIX_0F09 */
3538   {
3539     { "wbinvd",   { XX }, 0 },
3540     { "wbnoinvd", { XX }, 0 },
3541   },
3542
3543   /* PREFIX_0F10 */
3544   {
3545     { "movups", { XM, EXx }, PREFIX_OPCODE },
3546     { "movss",  { XM, EXd }, PREFIX_OPCODE },
3547     { "movupd", { XM, EXx }, PREFIX_OPCODE },
3548     { "movsd",  { XM, EXq }, PREFIX_OPCODE },
3549   },
3550
3551   /* PREFIX_0F11 */
3552   {
3553     { "movups", { EXxS, XM }, PREFIX_OPCODE },
3554     { "movss",  { EXdS, XM }, PREFIX_OPCODE },
3555     { "movupd", { EXxS, XM }, PREFIX_OPCODE },
3556     { "movsd",  { EXqS, XM }, PREFIX_OPCODE },
3557   },
3558
3559   /* PREFIX_0F12 */
3560   {
3561     { MOD_TABLE (MOD_0F12_PREFIX_0) },
3562     { "movsldup", { XM, EXx }, PREFIX_OPCODE },
3563     { MOD_TABLE (MOD_0F12_PREFIX_2) },
3564     { "movddup", { XM, EXq }, PREFIX_OPCODE },
3565   },
3566
3567   /* PREFIX_0F16 */
3568   {
3569     { MOD_TABLE (MOD_0F16_PREFIX_0) },
3570     { "movshdup", { XM, EXx }, PREFIX_OPCODE },
3571     { MOD_TABLE (MOD_0F16_PREFIX_2) },
3572   },
3573
3574   /* PREFIX_0F1A */
3575   {
3576     { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3577     { "bndcl",  { Gbnd, Ev_bnd }, 0 },
3578     { "bndmov", { Gbnd, Ebnd }, 0 },
3579     { "bndcu",  { Gbnd, Ev_bnd }, 0 },
3580   },
3581
3582   /* PREFIX_0F1B */
3583   {
3584     { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3585     { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3586     { "bndmov", { EbndS, Gbnd }, 0 },
3587     { "bndcn",  { Gbnd, Ev_bnd }, 0 },
3588   },
3589
3590   /* PREFIX_0F1C */
3591   {
3592     { MOD_TABLE (MOD_0F1C_PREFIX_0) },
3593     { "nopQ",   { Ev }, PREFIX_OPCODE },
3594     { "nopQ",   { Ev }, PREFIX_OPCODE },
3595     { "nopQ",   { Ev }, PREFIX_OPCODE },
3596   },
3597
3598   /* PREFIX_0F1E */
3599   {
3600     { "nopQ",   { Ev }, PREFIX_OPCODE },
3601     { MOD_TABLE (MOD_0F1E_PREFIX_1) },
3602     { "nopQ",   { Ev }, PREFIX_OPCODE },
3603     { "nopQ",   { Ev }, PREFIX_OPCODE },
3604   },
3605
3606   /* PREFIX_0F2A */
3607   {
3608     { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE },
3609     { "cvtsi2ss%LQ", { XM, Edq }, PREFIX_OPCODE },
3610     { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE },
3611     { "cvtsi2sd%LQ", { XM, Edq }, 0 },
3612   },
3613
3614   /* PREFIX_0F2B */
3615   {
3616     { MOD_TABLE (MOD_0F2B_PREFIX_0) },
3617     { MOD_TABLE (MOD_0F2B_PREFIX_1) },
3618     { MOD_TABLE (MOD_0F2B_PREFIX_2) },
3619     { MOD_TABLE (MOD_0F2B_PREFIX_3) },
3620   },
3621
3622   /* PREFIX_0F2C */
3623   {
3624     { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE },
3625     { "cvttss2si", { Gdq, EXd }, PREFIX_OPCODE },
3626     { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3627     { "cvttsd2si", { Gdq, EXq }, PREFIX_OPCODE },
3628   },
3629
3630   /* PREFIX_0F2D */
3631   {
3632     { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE },
3633     { "cvtss2si", { Gdq, EXd }, PREFIX_OPCODE },
3634     { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3635     { "cvtsd2si", { Gdq, EXq }, PREFIX_OPCODE },
3636   },
3637
3638   /* PREFIX_0F2E */
3639   {
3640     { "ucomiss",{ XM, EXd }, 0 },
3641     { Bad_Opcode },
3642     { "ucomisd",{ XM, EXq }, 0 },
3643   },
3644
3645   /* PREFIX_0F2F */
3646   {
3647     { "comiss", { XM, EXd }, 0 },
3648     { Bad_Opcode },
3649     { "comisd", { XM, EXq }, 0 },
3650   },
3651
3652   /* PREFIX_0F51 */
3653   {
3654     { "sqrtps", { XM, EXx }, PREFIX_OPCODE },
3655     { "sqrtss", { XM, EXd }, PREFIX_OPCODE },
3656     { "sqrtpd", { XM, EXx }, PREFIX_OPCODE },
3657     { "sqrtsd", { XM, EXq }, PREFIX_OPCODE },
3658   },
3659
3660   /* PREFIX_0F52 */
3661   {
3662     { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE },
3663     { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE },
3664   },
3665
3666   /* PREFIX_0F53 */
3667   {
3668     { "rcpps",  { XM, EXx }, PREFIX_OPCODE },
3669     { "rcpss",  { XM, EXd }, PREFIX_OPCODE },
3670   },
3671
3672   /* PREFIX_0F58 */
3673   {
3674     { "addps", { XM, EXx }, PREFIX_OPCODE },
3675     { "addss", { XM, EXd }, PREFIX_OPCODE },
3676     { "addpd", { XM, EXx }, PREFIX_OPCODE },
3677     { "addsd", { XM, EXq }, PREFIX_OPCODE },
3678   },
3679
3680   /* PREFIX_0F59 */
3681   {
3682     { "mulps",  { XM, EXx }, PREFIX_OPCODE },
3683     { "mulss",  { XM, EXd }, PREFIX_OPCODE },
3684     { "mulpd",  { XM, EXx }, PREFIX_OPCODE },
3685     { "mulsd",  { XM, EXq }, PREFIX_OPCODE },
3686   },
3687
3688   /* PREFIX_0F5A */
3689   {
3690     { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE },
3691     { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE },
3692     { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE },
3693     { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE },
3694   },
3695
3696   /* PREFIX_0F5B */
3697   {
3698     { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE },
3699     { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE },
3700     { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE },
3701   },
3702
3703   /* PREFIX_0F5C */
3704   {
3705     { "subps",  { XM, EXx }, PREFIX_OPCODE },
3706     { "subss",  { XM, EXd }, PREFIX_OPCODE },
3707     { "subpd",  { XM, EXx }, PREFIX_OPCODE },
3708     { "subsd",  { XM, EXq }, PREFIX_OPCODE },
3709   },
3710
3711   /* PREFIX_0F5D */
3712   {
3713     { "minps",  { XM, EXx }, PREFIX_OPCODE },
3714     { "minss",  { XM, EXd }, PREFIX_OPCODE },
3715     { "minpd",  { XM, EXx }, PREFIX_OPCODE },
3716     { "minsd",  { XM, EXq }, PREFIX_OPCODE },
3717   },
3718
3719   /* PREFIX_0F5E */
3720   {
3721     { "divps",  { XM, EXx }, PREFIX_OPCODE },
3722     { "divss",  { XM, EXd }, PREFIX_OPCODE },
3723     { "divpd",  { XM, EXx }, PREFIX_OPCODE },
3724     { "divsd",  { XM, EXq }, PREFIX_OPCODE },
3725   },
3726
3727   /* PREFIX_0F5F */
3728   {
3729     { "maxps",  { XM, EXx }, PREFIX_OPCODE },
3730     { "maxss",  { XM, EXd }, PREFIX_OPCODE },
3731     { "maxpd",  { XM, EXx }, PREFIX_OPCODE },
3732     { "maxsd",  { XM, EXq }, PREFIX_OPCODE },
3733   },
3734
3735   /* PREFIX_0F60 */
3736   {
3737     { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE },
3738     { Bad_Opcode },
3739     { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE },
3740   },
3741
3742   /* PREFIX_0F61 */
3743   {
3744     { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE },
3745     { Bad_Opcode },
3746     { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE },
3747   },
3748
3749   /* PREFIX_0F62 */
3750   {
3751     { "punpckldq",{ MX, EMd }, PREFIX_OPCODE },
3752     { Bad_Opcode },
3753     { "punpckldq",{ MX, EMx }, PREFIX_OPCODE },
3754   },
3755
3756   /* PREFIX_0F6C */
3757   {
3758     { Bad_Opcode },
3759     { Bad_Opcode },
3760     { "punpcklqdq", { XM, EXx }, PREFIX_OPCODE },
3761   },
3762
3763   /* PREFIX_0F6D */
3764   {
3765     { Bad_Opcode },
3766     { Bad_Opcode },
3767     { "punpckhqdq", { XM, EXx }, PREFIX_OPCODE },
3768   },
3769
3770   /* PREFIX_0F6F */
3771   {
3772     { "movq",   { MX, EM }, PREFIX_OPCODE },
3773     { "movdqu", { XM, EXx }, PREFIX_OPCODE },
3774     { "movdqa", { XM, EXx }, PREFIX_OPCODE },
3775   },
3776
3777   /* PREFIX_0F70 */
3778   {
3779     { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE },
3780     { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3781     { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE },
3782     { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3783   },
3784
3785   /* PREFIX_0F73_REG_3 */
3786   {
3787     { Bad_Opcode },
3788     { Bad_Opcode },
3789     { "psrldq", { XS, Ib }, 0 },
3790   },
3791
3792   /* PREFIX_0F73_REG_7 */
3793   {
3794     { Bad_Opcode },
3795     { Bad_Opcode },
3796     { "pslldq", { XS, Ib }, 0 },
3797   },
3798
3799   /* PREFIX_0F78 */
3800   {
3801     {"vmread",  { Em, Gm }, 0 },
3802     { Bad_Opcode },
3803     {"extrq",   { XS, Ib, Ib }, 0 },
3804     {"insertq", { XM, XS, Ib, Ib }, 0 },
3805   },
3806
3807   /* PREFIX_0F79 */
3808   {
3809     {"vmwrite", { Gm, Em }, 0 },
3810     { Bad_Opcode },
3811     {"extrq",   { XM, XS }, 0 },
3812     {"insertq", { XM, XS }, 0 },
3813   },
3814
3815   /* PREFIX_0F7C */
3816   {
3817     { Bad_Opcode },
3818     { Bad_Opcode },
3819     { "haddpd", { XM, EXx }, PREFIX_OPCODE },
3820     { "haddps", { XM, EXx }, PREFIX_OPCODE },
3821   },
3822
3823   /* PREFIX_0F7D */
3824   {
3825     { Bad_Opcode },
3826     { Bad_Opcode },
3827     { "hsubpd", { XM, EXx }, PREFIX_OPCODE },
3828     { "hsubps", { XM, EXx }, PREFIX_OPCODE },
3829   },
3830
3831   /* PREFIX_0F7E */
3832   {
3833     { "movK",   { Edq, MX }, PREFIX_OPCODE },
3834     { "movq",   { XM, EXq }, PREFIX_OPCODE },
3835     { "movK",   { Edq, XM }, PREFIX_OPCODE },
3836   },
3837
3838   /* PREFIX_0F7F */
3839   {
3840     { "movq",   { EMS, MX }, PREFIX_OPCODE },
3841     { "movdqu", { EXxS, XM }, PREFIX_OPCODE },
3842     { "movdqa", { EXxS, XM }, PREFIX_OPCODE },
3843   },
3844
3845   /* PREFIX_0FAE_REG_0_MOD_3 */
3846   {
3847     { Bad_Opcode },
3848     { "rdfsbase", { Ev }, 0 },
3849   },
3850
3851   /* PREFIX_0FAE_REG_1_MOD_3 */
3852   {
3853     { Bad_Opcode },
3854     { "rdgsbase", { Ev }, 0 },
3855   },
3856
3857   /* PREFIX_0FAE_REG_2_MOD_3 */
3858   {
3859     { Bad_Opcode },
3860     { "wrfsbase", { Ev }, 0 },
3861   },
3862
3863   /* PREFIX_0FAE_REG_3_MOD_3 */
3864   {
3865     { Bad_Opcode },
3866     { "wrgsbase", { Ev }, 0 },
3867   },
3868
3869   /* PREFIX_0FAE_REG_4_MOD_0 */
3870   {
3871     { "xsave",  { FXSAVE }, 0 },
3872     { "ptwrite%LQ", { Edq }, 0 },
3873   },
3874
3875   /* PREFIX_0FAE_REG_4_MOD_3 */
3876   {
3877     { Bad_Opcode },
3878     { "ptwrite%LQ", { Edq }, 0 },
3879   },
3880
3881   /* PREFIX_0FAE_REG_5_MOD_0 */
3882   {
3883     { "xrstor",         { FXSAVE }, PREFIX_OPCODE },
3884   },
3885
3886   /* PREFIX_0FAE_REG_5_MOD_3 */
3887   {
3888     { "lfence",         { Skip_MODRM }, 0 },
3889     { "incsspK",        { Rdq }, PREFIX_OPCODE },
3890   },
3891
3892   /* PREFIX_0FAE_REG_6_MOD_0 */
3893   {
3894     { "xsaveopt",       { FXSAVE }, PREFIX_OPCODE },
3895     { "clrssbsy",       { Mq }, PREFIX_OPCODE },
3896     { "clwb",   { Mb }, PREFIX_OPCODE },
3897   },
3898
3899   /* PREFIX_0FAE_REG_6_MOD_3 */
3900   {
3901     { RM_TABLE (RM_0FAE_REG_6_MOD_3_P_0) },
3902     { "umonitor",       { Eva }, PREFIX_OPCODE },
3903     { "tpause", { Edq }, PREFIX_OPCODE },
3904     { "umwait", { Edq }, PREFIX_OPCODE },
3905   },
3906
3907   /* PREFIX_0FAE_REG_7_MOD_0 */
3908   {
3909     { "clflush",        { Mb }, 0 },
3910     { Bad_Opcode },
3911     { "clflushopt",     { Mb }, 0 },
3912   },
3913
3914   /* PREFIX_0FB8 */
3915   {
3916     { Bad_Opcode },
3917     { "popcntS", { Gv, Ev }, 0 },
3918   },
3919
3920   /* PREFIX_0FBC */
3921   {
3922     { "bsfS",   { Gv, Ev }, 0 },
3923     { "tzcntS", { Gv, Ev }, 0 },
3924     { "bsfS",   { Gv, Ev }, 0 },
3925   },
3926
3927   /* PREFIX_0FBD */
3928   {
3929     { "bsrS",   { Gv, Ev }, 0 },
3930     { "lzcntS", { Gv, Ev }, 0 },
3931     { "bsrS",   { Gv, Ev }, 0 },
3932   },
3933
3934   /* PREFIX_0FC2 */
3935   {
3936     { "cmpps",  { XM, EXx, CMP }, PREFIX_OPCODE },
3937     { "cmpss",  { XM, EXd, CMP }, PREFIX_OPCODE },
3938     { "cmppd",  { XM, EXx, CMP }, PREFIX_OPCODE },
3939     { "cmpsd",  { XM, EXq, CMP }, PREFIX_OPCODE },
3940   },
3941
3942   /* PREFIX_0FC3_MOD_0 */
3943   {
3944     { "movntiS", { Edq, Gdq }, PREFIX_OPCODE },
3945   },
3946
3947   /* PREFIX_0FC7_REG_6_MOD_0 */
3948   {
3949     { "vmptrld",{ Mq }, 0 },
3950     { "vmxon",  { Mq }, 0 },
3951     { "vmclear",{ Mq }, 0 },
3952   },
3953
3954   /* PREFIX_0FC7_REG_6_MOD_3 */
3955   {
3956     { "rdrand", { Ev }, 0 },
3957     { Bad_Opcode },
3958     { "rdrand", { Ev }, 0 }
3959   },
3960
3961   /* PREFIX_0FC7_REG_7_MOD_3 */
3962   {
3963     { "rdseed", { Ev }, 0 },
3964     { "rdpid",  { Em }, 0 },
3965     { "rdseed", { Ev }, 0 },
3966   },
3967
3968   /* PREFIX_0FD0 */
3969   {
3970     { Bad_Opcode },
3971     { Bad_Opcode },
3972     { "addsubpd", { XM, EXx }, 0 },
3973     { "addsubps", { XM, EXx }, 0 },
3974   },
3975
3976   /* PREFIX_0FD6 */
3977   {
3978     { Bad_Opcode },
3979     { "movq2dq",{ XM, MS }, 0 },
3980     { "movq",   { EXqS, XM }, 0 },
3981     { "movdq2q",{ MX, XS }, 0 },
3982   },
3983
3984   /* PREFIX_0FE6 */
3985   {
3986     { Bad_Opcode },
3987     { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE },
3988     { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE },
3989     { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE },
3990   },
3991
3992   /* PREFIX_0FE7 */
3993   {
3994     { "movntq", { Mq, MX }, PREFIX_OPCODE },
3995     { Bad_Opcode },
3996     { MOD_TABLE (MOD_0FE7_PREFIX_2) },
3997   },
3998
3999   /* PREFIX_0FF0 */
4000   {
4001     { Bad_Opcode },
4002     { Bad_Opcode },
4003     { Bad_Opcode },
4004     { MOD_TABLE (MOD_0FF0_PREFIX_3) },
4005   },
4006
4007   /* PREFIX_0FF7 */
4008   {
4009     { "maskmovq", { MX, MS }, PREFIX_OPCODE },
4010     { Bad_Opcode },
4011     { "maskmovdqu", { XM, XS }, PREFIX_OPCODE },
4012   },
4013
4014   /* PREFIX_0F3810 */
4015   {
4016     { Bad_Opcode },
4017     { Bad_Opcode },
4018     { "pblendvb", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4019   },
4020
4021   /* PREFIX_0F3814 */
4022   {
4023     { Bad_Opcode },
4024     { Bad_Opcode },
4025     { "blendvps", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4026   },
4027
4028   /* PREFIX_0F3815 */
4029   {
4030     { Bad_Opcode },
4031     { Bad_Opcode },
4032     { "blendvpd", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4033   },
4034
4035   /* PREFIX_0F3817 */
4036   {
4037     { Bad_Opcode },
4038     { Bad_Opcode },
4039     { "ptest",  { XM, EXx }, PREFIX_OPCODE },
4040   },
4041
4042   /* PREFIX_0F3820 */
4043   {
4044     { Bad_Opcode },
4045     { Bad_Opcode },
4046     { "pmovsxbw", { XM, EXq }, PREFIX_OPCODE },
4047   },
4048
4049   /* PREFIX_0F3821 */
4050   {
4051     { Bad_Opcode },
4052     { Bad_Opcode },
4053     { "pmovsxbd", { XM, EXd }, PREFIX_OPCODE },
4054   },
4055
4056   /* PREFIX_0F3822 */
4057   {
4058     { Bad_Opcode },
4059     { Bad_Opcode },
4060     { "pmovsxbq", { XM, EXw }, PREFIX_OPCODE },
4061   },
4062
4063   /* PREFIX_0F3823 */
4064   {
4065     { Bad_Opcode },
4066     { Bad_Opcode },
4067     { "pmovsxwd", { XM, EXq }, PREFIX_OPCODE },
4068   },
4069
4070   /* PREFIX_0F3824 */
4071   {
4072     { Bad_Opcode },
4073     { Bad_Opcode },
4074     { "pmovsxwq", { XM, EXd }, PREFIX_OPCODE },
4075   },
4076
4077   /* PREFIX_0F3825 */
4078   {
4079     { Bad_Opcode },
4080     { Bad_Opcode },
4081     { "pmovsxdq", { XM, EXq }, PREFIX_OPCODE },
4082   },
4083
4084   /* PREFIX_0F3828 */
4085   {
4086     { Bad_Opcode },
4087     { Bad_Opcode },
4088     { "pmuldq", { XM, EXx }, PREFIX_OPCODE },
4089   },
4090
4091   /* PREFIX_0F3829 */
4092   {
4093     { Bad_Opcode },
4094     { Bad_Opcode },
4095     { "pcmpeqq", { XM, EXx }, PREFIX_OPCODE },
4096   },
4097
4098   /* PREFIX_0F382A */
4099   {
4100     { Bad_Opcode },
4101     { Bad_Opcode },
4102     { MOD_TABLE (MOD_0F382A_PREFIX_2) },
4103   },
4104
4105   /* PREFIX_0F382B */
4106   {
4107     { Bad_Opcode },
4108     { Bad_Opcode },
4109     { "packusdw", { XM, EXx }, PREFIX_OPCODE },
4110   },
4111
4112   /* PREFIX_0F3830 */
4113   {
4114     { Bad_Opcode },
4115     { Bad_Opcode },
4116     { "pmovzxbw", { XM, EXq }, PREFIX_OPCODE },
4117   },
4118
4119   /* PREFIX_0F3831 */
4120   {
4121     { Bad_Opcode },
4122     { Bad_Opcode },
4123     { "pmovzxbd", { XM, EXd }, PREFIX_OPCODE },
4124   },
4125
4126   /* PREFIX_0F3832 */
4127   {
4128     { Bad_Opcode },
4129     { Bad_Opcode },
4130     { "pmovzxbq", { XM, EXw }, PREFIX_OPCODE },
4131   },
4132
4133   /* PREFIX_0F3833 */
4134   {
4135     { Bad_Opcode },
4136     { Bad_Opcode },
4137     { "pmovzxwd", { XM, EXq }, PREFIX_OPCODE },
4138   },
4139
4140   /* PREFIX_0F3834 */
4141   {
4142     { Bad_Opcode },
4143     { Bad_Opcode },
4144     { "pmovzxwq", { XM, EXd }, PREFIX_OPCODE },
4145   },
4146
4147   /* PREFIX_0F3835 */
4148   {
4149     { Bad_Opcode },
4150     { Bad_Opcode },
4151     { "pmovzxdq", { XM, EXq }, PREFIX_OPCODE },
4152   },
4153
4154   /* PREFIX_0F3837 */
4155   {
4156     { Bad_Opcode },
4157     { Bad_Opcode },
4158     { "pcmpgtq", { XM, EXx }, PREFIX_OPCODE },
4159   },
4160
4161   /* PREFIX_0F3838 */
4162   {
4163     { Bad_Opcode },
4164     { Bad_Opcode },
4165     { "pminsb", { XM, EXx }, PREFIX_OPCODE },
4166   },
4167
4168   /* PREFIX_0F3839 */
4169   {
4170     { Bad_Opcode },
4171     { Bad_Opcode },
4172     { "pminsd", { XM, EXx }, PREFIX_OPCODE },
4173   },
4174
4175   /* PREFIX_0F383A */
4176   {
4177     { Bad_Opcode },
4178     { Bad_Opcode },
4179     { "pminuw", { XM, EXx }, PREFIX_OPCODE },
4180   },
4181
4182   /* PREFIX_0F383B */
4183   {
4184     { Bad_Opcode },
4185     { Bad_Opcode },
4186     { "pminud", { XM, EXx }, PREFIX_OPCODE },
4187   },
4188
4189   /* PREFIX_0F383C */
4190   {
4191     { Bad_Opcode },
4192     { Bad_Opcode },
4193     { "pmaxsb", { XM, EXx }, PREFIX_OPCODE },
4194   },
4195
4196   /* PREFIX_0F383D */
4197   {
4198     { Bad_Opcode },
4199     { Bad_Opcode },
4200     { "pmaxsd", { XM, EXx }, PREFIX_OPCODE },
4201   },
4202
4203   /* PREFIX_0F383E */
4204   {
4205     { Bad_Opcode },
4206     { Bad_Opcode },
4207     { "pmaxuw", { XM, EXx }, PREFIX_OPCODE },
4208   },
4209
4210   /* PREFIX_0F383F */
4211   {
4212     { Bad_Opcode },
4213     { Bad_Opcode },
4214     { "pmaxud", { XM, EXx }, PREFIX_OPCODE },
4215   },
4216
4217   /* PREFIX_0F3840 */
4218   {
4219     { Bad_Opcode },
4220     { Bad_Opcode },
4221     { "pmulld", { XM, EXx }, PREFIX_OPCODE },
4222   },
4223
4224   /* PREFIX_0F3841 */
4225   {
4226     { Bad_Opcode },
4227     { Bad_Opcode },
4228     { "phminposuw", { XM, EXx }, PREFIX_OPCODE },
4229   },
4230
4231   /* PREFIX_0F3880 */
4232   {
4233     { Bad_Opcode },
4234     { Bad_Opcode },
4235     { "invept", { Gm, Mo }, PREFIX_OPCODE },
4236   },
4237
4238   /* PREFIX_0F3881 */
4239   {
4240     { Bad_Opcode },
4241     { Bad_Opcode },
4242     { "invvpid", { Gm, Mo }, PREFIX_OPCODE },
4243   },
4244
4245   /* PREFIX_0F3882 */
4246   {
4247     { Bad_Opcode },
4248     { Bad_Opcode },
4249     { "invpcid", { Gm, M }, PREFIX_OPCODE },
4250   },
4251
4252   /* PREFIX_0F38C8 */
4253   {
4254     { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE },
4255   },
4256
4257   /* PREFIX_0F38C9 */
4258   {
4259     { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE },
4260   },
4261
4262   /* PREFIX_0F38CA */
4263   {
4264     { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE },
4265   },
4266
4267   /* PREFIX_0F38CB */
4268   {
4269     { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE },
4270   },
4271
4272   /* PREFIX_0F38CC */
4273   {
4274     { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE },
4275   },
4276
4277   /* PREFIX_0F38CD */
4278   {
4279     { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE },
4280   },
4281
4282   /* PREFIX_0F38CF */
4283   {
4284     { Bad_Opcode },
4285     { Bad_Opcode },
4286     { "gf2p8mulb", { XM, EXxmm }, PREFIX_OPCODE },
4287   },
4288
4289   /* PREFIX_0F38DB */
4290   {
4291     { Bad_Opcode },
4292     { Bad_Opcode },
4293     { "aesimc", { XM, EXx }, PREFIX_OPCODE },
4294   },
4295
4296   /* PREFIX_0F38DC */
4297   {
4298     { Bad_Opcode },
4299     { Bad_Opcode },
4300     { "aesenc", { XM, EXx }, PREFIX_OPCODE },
4301   },
4302
4303   /* PREFIX_0F38DD */
4304   {
4305     { Bad_Opcode },
4306     { Bad_Opcode },
4307     { "aesenclast", { XM, EXx }, PREFIX_OPCODE },
4308   },
4309
4310   /* PREFIX_0F38DE */
4311   {
4312     { Bad_Opcode },
4313     { Bad_Opcode },
4314     { "aesdec", { XM, EXx }, PREFIX_OPCODE },
4315   },
4316
4317   /* PREFIX_0F38DF */
4318   {
4319     { Bad_Opcode },
4320     { Bad_Opcode },
4321     { "aesdeclast", { XM, EXx }, PREFIX_OPCODE },
4322   },
4323
4324   /* PREFIX_0F38F0 */
4325   {
4326     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4327     { Bad_Opcode },
4328     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4329     { "crc32",  { Gdq, { CRC32_Fixup, b_mode } }, PREFIX_OPCODE },
4330   },
4331
4332   /* PREFIX_0F38F1 */
4333   {
4334     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4335     { Bad_Opcode },
4336     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4337     { "crc32",  { Gdq, { CRC32_Fixup, v_mode } }, PREFIX_OPCODE },
4338   },
4339
4340   /* PREFIX_0F38F5 */
4341   {
4342     { Bad_Opcode },
4343     { Bad_Opcode },
4344     { MOD_TABLE (MOD_0F38F5_PREFIX_2) },
4345   },
4346
4347   /* PREFIX_0F38F6 */
4348   {
4349     { MOD_TABLE (MOD_0F38F6_PREFIX_0) },
4350     { "adoxS",  { Gdq, Edq}, PREFIX_OPCODE },
4351     { "adcxS",  { Gdq, Edq}, PREFIX_OPCODE },
4352     { Bad_Opcode },
4353   },
4354
4355   /* PREFIX_0F38F8 */
4356   {
4357     { Bad_Opcode },
4358     { MOD_TABLE (MOD_0F38F8_PREFIX_1) },
4359     { MOD_TABLE (MOD_0F38F8_PREFIX_2) },
4360     { MOD_TABLE (MOD_0F38F8_PREFIX_3) },
4361   },
4362
4363   /* PREFIX_0F38F9 */
4364   {
4365     { MOD_TABLE (MOD_0F38F9_PREFIX_0) },
4366   },
4367
4368   /* PREFIX_0F3A08 */
4369   {
4370     { Bad_Opcode },
4371     { Bad_Opcode },
4372     { "roundps", { XM, EXx, Ib }, PREFIX_OPCODE },
4373   },
4374
4375   /* PREFIX_0F3A09 */
4376   {
4377     { Bad_Opcode },
4378     { Bad_Opcode },
4379     { "roundpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4380   },
4381
4382   /* PREFIX_0F3A0A */
4383   {
4384     { Bad_Opcode },
4385     { Bad_Opcode },
4386     { "roundss", { XM, EXd, Ib }, PREFIX_OPCODE },
4387   },
4388
4389   /* PREFIX_0F3A0B */
4390   {
4391     { Bad_Opcode },
4392     { Bad_Opcode },
4393     { "roundsd", { XM, EXq, Ib }, PREFIX_OPCODE },
4394   },
4395
4396   /* PREFIX_0F3A0C */
4397   {
4398     { Bad_Opcode },
4399     { Bad_Opcode },
4400     { "blendps", { XM, EXx, Ib }, PREFIX_OPCODE },
4401   },
4402
4403   /* PREFIX_0F3A0D */
4404   {
4405     { Bad_Opcode },
4406     { Bad_Opcode },
4407     { "blendpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4408   },
4409
4410   /* PREFIX_0F3A0E */
4411   {
4412     { Bad_Opcode },
4413     { Bad_Opcode },
4414     { "pblendw", { XM, EXx, Ib }, PREFIX_OPCODE },
4415   },
4416
4417   /* PREFIX_0F3A14 */
4418   {
4419     { Bad_Opcode },
4420     { Bad_Opcode },
4421     { "pextrb", { Edqb, XM, Ib }, PREFIX_OPCODE },
4422   },
4423
4424   /* PREFIX_0F3A15 */
4425   {
4426     { Bad_Opcode },
4427     { Bad_Opcode },
4428     { "pextrw", { Edqw, XM, Ib }, PREFIX_OPCODE },
4429   },
4430
4431   /* PREFIX_0F3A16 */
4432   {
4433     { Bad_Opcode },
4434     { Bad_Opcode },
4435     { "pextrK", { Edq, XM, Ib }, PREFIX_OPCODE },
4436   },
4437
4438   /* PREFIX_0F3A17 */
4439   {
4440     { Bad_Opcode },
4441     { Bad_Opcode },
4442     { "extractps", { Edqd, XM, Ib }, PREFIX_OPCODE },
4443   },
4444
4445   /* PREFIX_0F3A20 */
4446   {
4447     { Bad_Opcode },
4448     { Bad_Opcode },
4449     { "pinsrb", { XM, Edqb, Ib }, PREFIX_OPCODE },
4450   },
4451
4452   /* PREFIX_0F3A21 */
4453   {
4454     { Bad_Opcode },
4455     { Bad_Opcode },
4456     { "insertps", { XM, EXd, Ib }, PREFIX_OPCODE },
4457   },
4458
4459   /* PREFIX_0F3A22 */
4460   {
4461     { Bad_Opcode },
4462     { Bad_Opcode },
4463     { "pinsrK", { XM, Edq, Ib }, PREFIX_OPCODE },
4464   },
4465
4466   /* PREFIX_0F3A40 */
4467   {
4468     { Bad_Opcode },
4469     { Bad_Opcode },
4470     { "dpps",   { XM, EXx, Ib }, PREFIX_OPCODE },
4471   },
4472
4473   /* PREFIX_0F3A41 */
4474   {
4475     { Bad_Opcode },
4476     { Bad_Opcode },
4477     { "dppd",   { XM, EXx, Ib }, PREFIX_OPCODE },
4478   },
4479
4480   /* PREFIX_0F3A42 */
4481   {
4482     { Bad_Opcode },
4483     { Bad_Opcode },
4484     { "mpsadbw", { XM, EXx, Ib }, PREFIX_OPCODE },
4485   },
4486
4487   /* PREFIX_0F3A44 */
4488   {
4489     { Bad_Opcode },
4490     { Bad_Opcode },
4491     { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_OPCODE },
4492   },
4493
4494   /* PREFIX_0F3A60 */
4495   {
4496     { Bad_Opcode },
4497     { Bad_Opcode },
4498     { "pcmpestrm", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE },
4499   },
4500
4501   /* PREFIX_0F3A61 */
4502   {
4503     { Bad_Opcode },
4504     { Bad_Opcode },
4505     { "pcmpestri", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE },
4506   },
4507
4508   /* PREFIX_0F3A62 */
4509   {
4510     { Bad_Opcode },
4511     { Bad_Opcode },
4512     { "pcmpistrm", { XM, EXx, Ib }, PREFIX_OPCODE },
4513   },
4514
4515   /* PREFIX_0F3A63 */
4516   {
4517     { Bad_Opcode },
4518     { Bad_Opcode },
4519     { "pcmpistri", { XM, EXx, Ib }, PREFIX_OPCODE },
4520   },
4521
4522   /* PREFIX_0F3ACC */
4523   {
4524     { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4525   },
4526
4527   /* PREFIX_0F3ACE */
4528   {
4529     { Bad_Opcode },
4530     { Bad_Opcode },
4531     { "gf2p8affineqb", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4532   },
4533
4534   /* PREFIX_0F3ACF */
4535   {
4536     { Bad_Opcode },
4537     { Bad_Opcode },
4538     { "gf2p8affineinvqb", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4539   },
4540
4541   /* PREFIX_0F3ADF */
4542   {
4543     { Bad_Opcode },
4544     { Bad_Opcode },
4545     { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_OPCODE },
4546   },
4547
4548   /* PREFIX_VEX_0F10 */
4549   {
4550     { "vmovups",        { XM, EXx }, 0 },
4551     { "vmovss",         { XMVexScalar, VexScalar, EXxmm_md }, 0 },
4552     { "vmovupd",        { XM, EXx }, 0 },
4553     { "vmovsd",         { XMVexScalar, VexScalar, EXxmm_mq }, 0 },
4554   },
4555
4556   /* PREFIX_VEX_0F11 */
4557   {
4558     { "vmovups",        { EXxS, XM }, 0 },
4559     { "vmovss",         { EXdVexScalarS, VexScalar, XMScalar }, 0 },
4560     { "vmovupd",        { EXxS, XM }, 0 },
4561     { "vmovsd",         { EXqVexScalarS, VexScalar, XMScalar }, 0 },
4562   },
4563
4564   /* PREFIX_VEX_0F12 */
4565   {
4566     { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
4567     { "vmovsldup",      { XM, EXx }, 0 },
4568     { MOD_TABLE (MOD_VEX_0F12_PREFIX_2) },
4569     { "vmovddup",       { XM, EXymmq }, 0 },
4570   },
4571
4572   /* PREFIX_VEX_0F16 */
4573   {
4574     { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
4575     { "vmovshdup",      { XM, EXx }, 0 },
4576     { MOD_TABLE (MOD_VEX_0F16_PREFIX_2) },
4577   },
4578
4579   /* PREFIX_VEX_0F2A */
4580   {
4581     { Bad_Opcode },
4582     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Edq }, 0 },
4583     { Bad_Opcode },
4584     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Edq }, 0 },
4585   },
4586
4587   /* PREFIX_VEX_0F2C */
4588   {
4589     { Bad_Opcode },
4590     { "vcvttss2si",     { Gdq, EXxmm_md }, 0 },
4591     { Bad_Opcode },
4592     { "vcvttsd2si",     { Gdq, EXxmm_mq }, 0 },
4593   },
4594
4595   /* PREFIX_VEX_0F2D */
4596   {
4597     { Bad_Opcode },
4598     { "vcvtss2si",      { Gdq, EXxmm_md }, 0 },
4599     { Bad_Opcode },
4600     { "vcvtsd2si",      { Gdq, EXxmm_mq }, 0 },
4601   },
4602
4603   /* PREFIX_VEX_0F2E */
4604   {
4605     { "vucomiss",       { XMScalar, EXxmm_md }, 0 },
4606     { Bad_Opcode },
4607     { "vucomisd",       { XMScalar, EXxmm_mq }, 0 },
4608   },
4609
4610   /* PREFIX_VEX_0F2F */
4611   {
4612     { "vcomiss",        { XMScalar, EXxmm_md }, 0 },
4613     { Bad_Opcode },
4614     { "vcomisd",        { XMScalar, EXxmm_mq }, 0 },
4615   },
4616
4617   /* PREFIX_VEX_0F41 */
4618   {
4619     { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) },
4620     { Bad_Opcode },
4621     { VEX_LEN_TABLE (VEX_LEN_0F41_P_2) },
4622   },
4623
4624   /* PREFIX_VEX_0F42 */
4625   {
4626     { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) },
4627     { Bad_Opcode },
4628     { VEX_LEN_TABLE (VEX_LEN_0F42_P_2) },
4629   },
4630
4631   /* PREFIX_VEX_0F44 */
4632   {
4633     { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) },
4634     { Bad_Opcode },
4635     { VEX_LEN_TABLE (VEX_LEN_0F44_P_2) },
4636   },
4637
4638   /* PREFIX_VEX_0F45 */
4639   {
4640     { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) },
4641     { Bad_Opcode },
4642     { VEX_LEN_TABLE (VEX_LEN_0F45_P_2) },
4643   },
4644
4645   /* PREFIX_VEX_0F46 */
4646   {
4647     { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) },
4648     { Bad_Opcode },
4649     { VEX_LEN_TABLE (VEX_LEN_0F46_P_2) },
4650   },
4651
4652   /* PREFIX_VEX_0F47 */
4653   {
4654     { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) },
4655     { Bad_Opcode },
4656     { VEX_LEN_TABLE (VEX_LEN_0F47_P_2) },
4657   },
4658
4659   /* PREFIX_VEX_0F4A */
4660   {
4661     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0) },
4662     { Bad_Opcode },
4663     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2) },
4664   },
4665
4666   /* PREFIX_VEX_0F4B */
4667   {
4668     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0) },
4669     { Bad_Opcode },
4670     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) },
4671   },
4672
4673   /* PREFIX_VEX_0F51 */
4674   {
4675     { "vsqrtps",        { XM, EXx }, 0 },
4676     { "vsqrtss",        { XMScalar, VexScalar, EXxmm_md }, 0 },
4677     { "vsqrtpd",        { XM, EXx }, 0 },
4678     { "vsqrtsd",        { XMScalar, VexScalar, EXxmm_mq }, 0 },
4679   },
4680
4681   /* PREFIX_VEX_0F52 */
4682   {
4683     { "vrsqrtps",       { XM, EXx }, 0 },
4684     { "vrsqrtss",       { XMScalar, VexScalar, EXxmm_md }, 0 },
4685   },
4686
4687   /* PREFIX_VEX_0F53 */
4688   {
4689     { "vrcpps",         { XM, EXx }, 0 },
4690     { "vrcpss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
4691   },
4692
4693   /* PREFIX_VEX_0F58 */
4694   {
4695     { "vaddps",         { XM, Vex, EXx }, 0 },
4696     { "vaddss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
4697     { "vaddpd",         { XM, Vex, EXx }, 0 },
4698     { "vaddsd",         { XMScalar, VexScalar, EXxmm_mq }, 0 },
4699   },
4700
4701   /* PREFIX_VEX_0F59 */
4702   {
4703     { "vmulps",         { XM, Vex, EXx }, 0 },
4704     { "vmulss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
4705     { "vmulpd",         { XM, Vex, EXx }, 0 },
4706     { "vmulsd",         { XMScalar, VexScalar, EXxmm_mq }, 0 },
4707   },
4708
4709   /* PREFIX_VEX_0F5A */
4710   {
4711     { "vcvtps2pd",      { XM, EXxmmq }, 0 },
4712     { "vcvtss2sd",      { XMScalar, VexScalar, EXxmm_md }, 0 },
4713     { "vcvtpd2ps%XY",{ XMM, EXx }, 0 },
4714     { "vcvtsd2ss",      { XMScalar, VexScalar, EXxmm_mq }, 0 },
4715   },
4716
4717   /* PREFIX_VEX_0F5B */
4718   {
4719     { "vcvtdq2ps",      { XM, EXx }, 0 },
4720     { "vcvttps2dq",     { XM, EXx }, 0 },
4721     { "vcvtps2dq",      { XM, EXx }, 0 },
4722   },
4723
4724   /* PREFIX_VEX_0F5C */
4725   {
4726     { "vsubps",         { XM, Vex, EXx }, 0 },
4727     { "vsubss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
4728     { "vsubpd",         { XM, Vex, EXx }, 0 },
4729     { "vsubsd",         { XMScalar, VexScalar, EXxmm_mq }, 0 },
4730   },
4731
4732   /* PREFIX_VEX_0F5D */
4733   {
4734     { "vminps",         { XM, Vex, EXx }, 0 },
4735     { "vminss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
4736     { "vminpd",         { XM, Vex, EXx }, 0 },
4737     { "vminsd",         { XMScalar, VexScalar, EXxmm_mq }, 0 },
4738   },
4739
4740   /* PREFIX_VEX_0F5E */
4741   {
4742     { "vdivps",         { XM, Vex, EXx }, 0 },
4743     { "vdivss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
4744     { "vdivpd",         { XM, Vex, EXx }, 0 },
4745     { "vdivsd",         { XMScalar, VexScalar, EXxmm_mq }, 0 },
4746   },
4747
4748   /* PREFIX_VEX_0F5F */
4749   {
4750     { "vmaxps",         { XM, Vex, EXx }, 0 },
4751     { "vmaxss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
4752     { "vmaxpd",         { XM, Vex, EXx }, 0 },
4753     { "vmaxsd",         { XMScalar, VexScalar, EXxmm_mq }, 0 },
4754   },
4755
4756   /* PREFIX_VEX_0F60 */
4757   {
4758     { Bad_Opcode },
4759     { Bad_Opcode },
4760     { "vpunpcklbw",     { XM, Vex, EXx }, 0 },
4761   },
4762
4763   /* PREFIX_VEX_0F61 */
4764   {
4765     { Bad_Opcode },
4766     { Bad_Opcode },
4767     { "vpunpcklwd",     { XM, Vex, EXx }, 0 },
4768   },
4769
4770   /* PREFIX_VEX_0F62 */
4771   {
4772     { Bad_Opcode },
4773     { Bad_Opcode },
4774     { "vpunpckldq",     { XM, Vex, EXx }, 0 },
4775   },
4776
4777   /* PREFIX_VEX_0F63 */
4778   {
4779     { Bad_Opcode },
4780     { Bad_Opcode },
4781     { "vpacksswb",      { XM, Vex, EXx }, 0 },
4782   },
4783
4784   /* PREFIX_VEX_0F64 */
4785   {
4786     { Bad_Opcode },
4787     { Bad_Opcode },
4788     { "vpcmpgtb",       { XM, Vex, EXx }, 0 },
4789   },
4790
4791   /* PREFIX_VEX_0F65 */
4792   {
4793     { Bad_Opcode },
4794     { Bad_Opcode },
4795     { "vpcmpgtw",       { XM, Vex, EXx }, 0 },
4796   },
4797
4798   /* PREFIX_VEX_0F66 */
4799   {
4800     { Bad_Opcode },
4801     { Bad_Opcode },
4802     { "vpcmpgtd",       { XM, Vex, EXx }, 0 },
4803   },
4804
4805   /* PREFIX_VEX_0F67 */
4806   {
4807     { Bad_Opcode },
4808     { Bad_Opcode },
4809     { "vpackuswb",      { XM, Vex, EXx }, 0 },
4810   },
4811
4812   /* PREFIX_VEX_0F68 */
4813   {
4814     { Bad_Opcode },
4815     { Bad_Opcode },
4816     { "vpunpckhbw",     { XM, Vex, EXx }, 0 },
4817   },
4818
4819   /* PREFIX_VEX_0F69 */
4820   {
4821     { Bad_Opcode },
4822     { Bad_Opcode },
4823     { "vpunpckhwd",     { XM, Vex, EXx }, 0 },
4824   },
4825
4826   /* PREFIX_VEX_0F6A */
4827   {
4828     { Bad_Opcode },
4829     { Bad_Opcode },
4830     { "vpunpckhdq",     { XM, Vex, EXx }, 0 },
4831   },
4832
4833   /* PREFIX_VEX_0F6B */
4834   {
4835     { Bad_Opcode },
4836     { Bad_Opcode },
4837     { "vpackssdw",      { XM, Vex, EXx }, 0 },
4838   },
4839
4840   /* PREFIX_VEX_0F6C */
4841   {
4842     { Bad_Opcode },
4843     { Bad_Opcode },
4844     { "vpunpcklqdq",    { XM, Vex, EXx }, 0 },
4845   },
4846
4847   /* PREFIX_VEX_0F6D */
4848   {
4849     { Bad_Opcode },
4850     { Bad_Opcode },
4851     { "vpunpckhqdq",    { XM, Vex, EXx }, 0 },
4852   },
4853
4854   /* PREFIX_VEX_0F6E */
4855   {
4856     { Bad_Opcode },
4857     { Bad_Opcode },
4858     { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) },
4859   },
4860
4861   /* PREFIX_VEX_0F6F */
4862   {
4863     { Bad_Opcode },
4864     { "vmovdqu",        { XM, EXx }, 0 },
4865     { "vmovdqa",        { XM, EXx }, 0 },
4866   },
4867
4868   /* PREFIX_VEX_0F70 */
4869   {
4870     { Bad_Opcode },
4871     { "vpshufhw",       { XM, EXx, Ib }, 0 },
4872     { "vpshufd",        { XM, EXx, Ib }, 0 },
4873     { "vpshuflw",       { XM, EXx, Ib }, 0 },
4874   },
4875
4876   /* PREFIX_VEX_0F71_REG_2 */
4877   {
4878     { Bad_Opcode },
4879     { Bad_Opcode },
4880     { "vpsrlw",         { Vex, XS, Ib }, 0 },
4881   },
4882
4883   /* PREFIX_VEX_0F71_REG_4 */
4884   {
4885     { Bad_Opcode },
4886     { Bad_Opcode },
4887     { "vpsraw",         { Vex, XS, Ib }, 0 },
4888   },
4889
4890   /* PREFIX_VEX_0F71_REG_6 */
4891   {
4892     { Bad_Opcode },
4893     { Bad_Opcode },
4894     { "vpsllw",         { Vex, XS, Ib }, 0 },
4895   },
4896
4897   /* PREFIX_VEX_0F72_REG_2 */
4898   {
4899     { Bad_Opcode },
4900     { Bad_Opcode },
4901     { "vpsrld",         { Vex, XS, Ib }, 0 },
4902   },
4903
4904   /* PREFIX_VEX_0F72_REG_4 */
4905   {
4906     { Bad_Opcode },
4907     { Bad_Opcode },
4908     { "vpsrad",         { Vex, XS, Ib }, 0 },
4909   },
4910
4911   /* PREFIX_VEX_0F72_REG_6 */
4912   {
4913     { Bad_Opcode },
4914     { Bad_Opcode },
4915     { "vpslld",         { Vex, XS, Ib }, 0 },
4916   },
4917
4918   /* PREFIX_VEX_0F73_REG_2 */
4919   {
4920     { Bad_Opcode },
4921     { Bad_Opcode },
4922     { "vpsrlq",         { Vex, XS, Ib }, 0 },
4923   },
4924
4925   /* PREFIX_VEX_0F73_REG_3 */
4926   {
4927     { Bad_Opcode },
4928     { Bad_Opcode },
4929     { "vpsrldq",        { Vex, XS, Ib }, 0 },
4930   },
4931
4932   /* PREFIX_VEX_0F73_REG_6 */
4933   {
4934     { Bad_Opcode },
4935     { Bad_Opcode },
4936     { "vpsllq",         { Vex, XS, Ib }, 0 },
4937   },
4938
4939   /* PREFIX_VEX_0F73_REG_7 */
4940   {
4941     { Bad_Opcode },
4942     { Bad_Opcode },
4943     { "vpslldq",        { Vex, XS, Ib }, 0 },
4944   },
4945
4946   /* PREFIX_VEX_0F74 */
4947   {
4948     { Bad_Opcode },
4949     { Bad_Opcode },
4950     { "vpcmpeqb",       { XM, Vex, EXx }, 0 },
4951   },
4952
4953   /* PREFIX_VEX_0F75 */
4954   {
4955     { Bad_Opcode },
4956     { Bad_Opcode },
4957     { "vpcmpeqw",       { XM, Vex, EXx }, 0 },
4958   },
4959
4960   /* PREFIX_VEX_0F76 */
4961   {
4962     { Bad_Opcode },
4963     { Bad_Opcode },
4964     { "vpcmpeqd",       { XM, Vex, EXx }, 0 },
4965   },
4966
4967   /* PREFIX_VEX_0F77 */
4968   {
4969     { VEX_LEN_TABLE (VEX_LEN_0F77_P_0) },
4970   },
4971
4972   /* PREFIX_VEX_0F7C */
4973   {
4974     { Bad_Opcode },
4975     { Bad_Opcode },
4976     { "vhaddpd",        { XM, Vex, EXx }, 0 },
4977     { "vhaddps",        { XM, Vex, EXx }, 0 },
4978   },
4979
4980   /* PREFIX_VEX_0F7D */
4981   {
4982     { Bad_Opcode },
4983     { Bad_Opcode },
4984     { "vhsubpd",        { XM, Vex, EXx }, 0 },
4985     { "vhsubps",        { XM, Vex, EXx }, 0 },
4986   },
4987
4988   /* PREFIX_VEX_0F7E */
4989   {
4990     { Bad_Opcode },
4991     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
4992     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
4993   },
4994
4995   /* PREFIX_VEX_0F7F */
4996   {
4997     { Bad_Opcode },
4998     { "vmovdqu",        { EXxS, XM }, 0 },
4999     { "vmovdqa",        { EXxS, XM }, 0 },
5000   },
5001
5002   /* PREFIX_VEX_0F90 */
5003   {
5004     { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) },
5005     { Bad_Opcode },
5006     { VEX_LEN_TABLE (VEX_LEN_0F90_P_2) },
5007   },
5008
5009   /* PREFIX_VEX_0F91 */
5010   {
5011     { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) },
5012     { Bad_Opcode },
5013     { VEX_LEN_TABLE (VEX_LEN_0F91_P_2) },
5014   },
5015
5016   /* PREFIX_VEX_0F92 */
5017   {
5018     { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) },
5019     { Bad_Opcode },
5020     { VEX_LEN_TABLE (VEX_LEN_0F92_P_2) },
5021     { VEX_LEN_TABLE (VEX_LEN_0F92_P_3) },
5022   },
5023
5024   /* PREFIX_VEX_0F93 */
5025   {
5026     { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) },
5027     { Bad_Opcode },
5028     { VEX_LEN_TABLE (VEX_LEN_0F93_P_2) },
5029     { VEX_LEN_TABLE (VEX_LEN_0F93_P_3) },
5030   },
5031
5032   /* PREFIX_VEX_0F98 */
5033   {
5034     { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) },
5035     { Bad_Opcode },
5036     { VEX_LEN_TABLE (VEX_LEN_0F98_P_2) },
5037   },
5038
5039   /* PREFIX_VEX_0F99 */
5040   {
5041     { VEX_LEN_TABLE (VEX_LEN_0F99_P_0) },
5042     { Bad_Opcode },
5043     { VEX_LEN_TABLE (VEX_LEN_0F99_P_2) },
5044   },
5045
5046   /* PREFIX_VEX_0FC2 */
5047   {
5048     { "vcmpps",         { XM, Vex, EXx, VCMP }, 0 },
5049     { "vcmpss",         { XMScalar, VexScalar, EXxmm_md, VCMP }, 0 },
5050     { "vcmppd",         { XM, Vex, EXx, VCMP }, 0 },
5051     { "vcmpsd",         { XMScalar, VexScalar, EXxmm_mq, VCMP }, 0 },
5052   },
5053
5054   /* PREFIX_VEX_0FC4 */
5055   {
5056     { Bad_Opcode },
5057     { Bad_Opcode },
5058     { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) },
5059   },
5060
5061   /* PREFIX_VEX_0FC5 */
5062   {
5063     { Bad_Opcode },
5064     { Bad_Opcode },
5065     { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) },
5066   },
5067
5068   /* PREFIX_VEX_0FD0 */
5069   {
5070     { Bad_Opcode },
5071     { Bad_Opcode },
5072     { "vaddsubpd",      { XM, Vex, EXx }, 0 },
5073     { "vaddsubps",      { XM, Vex, EXx }, 0 },
5074   },
5075
5076   /* PREFIX_VEX_0FD1 */
5077   {
5078     { Bad_Opcode },
5079     { Bad_Opcode },
5080     { "vpsrlw",         { XM, Vex, EXxmm }, 0 },
5081   },
5082
5083   /* PREFIX_VEX_0FD2 */
5084   {
5085     { Bad_Opcode },
5086     { Bad_Opcode },
5087     { "vpsrld",         { XM, Vex, EXxmm }, 0 },
5088   },
5089
5090   /* PREFIX_VEX_0FD3 */
5091   {
5092     { Bad_Opcode },
5093     { Bad_Opcode },
5094     { "vpsrlq",         { XM, Vex, EXxmm }, 0 },
5095   },
5096
5097   /* PREFIX_VEX_0FD4 */
5098   {
5099     { Bad_Opcode },
5100     { Bad_Opcode },
5101     { "vpaddq",         { XM, Vex, EXx }, 0 },
5102   },
5103
5104   /* PREFIX_VEX_0FD5 */
5105   {
5106     { Bad_Opcode },
5107     { Bad_Opcode },
5108     { "vpmullw",        { XM, Vex, EXx }, 0 },
5109   },
5110
5111   /* PREFIX_VEX_0FD6 */
5112   {
5113     { Bad_Opcode },
5114     { Bad_Opcode },
5115     { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) },
5116   },
5117
5118   /* PREFIX_VEX_0FD7 */
5119   {
5120     { Bad_Opcode },
5121     { Bad_Opcode },
5122     { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) },
5123   },
5124
5125   /* PREFIX_VEX_0FD8 */
5126   {
5127     { Bad_Opcode },
5128     { Bad_Opcode },
5129     { "vpsubusb",       { XM, Vex, EXx }, 0 },
5130   },
5131
5132   /* PREFIX_VEX_0FD9 */
5133   {
5134     { Bad_Opcode },
5135     { Bad_Opcode },
5136     { "vpsubusw",       { XM, Vex, EXx }, 0 },
5137   },
5138
5139   /* PREFIX_VEX_0FDA */
5140   {
5141     { Bad_Opcode },
5142     { Bad_Opcode },
5143     { "vpminub",        { XM, Vex, EXx }, 0 },
5144   },
5145
5146   /* PREFIX_VEX_0FDB */
5147   {
5148     { Bad_Opcode },
5149     { Bad_Opcode },
5150     { "vpand",          { XM, Vex, EXx }, 0 },
5151   },
5152
5153   /* PREFIX_VEX_0FDC */
5154   {
5155     { Bad_Opcode },
5156     { Bad_Opcode },
5157     { "vpaddusb",       { XM, Vex, EXx }, 0 },
5158   },
5159
5160   /* PREFIX_VEX_0FDD */
5161   {
5162     { Bad_Opcode },
5163     { Bad_Opcode },
5164     { "vpaddusw",       { XM, Vex, EXx }, 0 },
5165   },
5166
5167   /* PREFIX_VEX_0FDE */
5168   {
5169     { Bad_Opcode },
5170     { Bad_Opcode },
5171     { "vpmaxub",        { XM, Vex, EXx }, 0 },
5172   },
5173
5174   /* PREFIX_VEX_0FDF */
5175   {
5176     { Bad_Opcode },
5177     { Bad_Opcode },
5178     { "vpandn",         { XM, Vex, EXx }, 0 },
5179   },
5180
5181   /* PREFIX_VEX_0FE0 */
5182   {
5183     { Bad_Opcode },
5184     { Bad_Opcode },
5185     { "vpavgb",         { XM, Vex, EXx }, 0 },
5186   },
5187
5188   /* PREFIX_VEX_0FE1 */
5189   {
5190     { Bad_Opcode },
5191     { Bad_Opcode },
5192     { "vpsraw",         { XM, Vex, EXxmm }, 0 },
5193   },
5194
5195   /* PREFIX_VEX_0FE2 */
5196   {
5197     { Bad_Opcode },
5198     { Bad_Opcode },
5199     { "vpsrad",         { XM, Vex, EXxmm }, 0 },
5200   },
5201
5202   /* PREFIX_VEX_0FE3 */
5203   {
5204     { Bad_Opcode },
5205     { Bad_Opcode },
5206     { "vpavgw",         { XM, Vex, EXx }, 0 },
5207   },
5208
5209   /* PREFIX_VEX_0FE4 */
5210   {
5211     { Bad_Opcode },
5212     { Bad_Opcode },
5213     { "vpmulhuw",       { XM, Vex, EXx }, 0 },
5214   },
5215
5216   /* PREFIX_VEX_0FE5 */
5217   {
5218     { Bad_Opcode },
5219     { Bad_Opcode },
5220     { "vpmulhw",        { XM, Vex, EXx }, 0 },
5221   },
5222
5223   /* PREFIX_VEX_0FE6 */
5224   {
5225     { Bad_Opcode },
5226     { "vcvtdq2pd",      { XM, EXxmmq }, 0 },
5227     { "vcvttpd2dq%XY",  { XMM, EXx }, 0 },
5228     { "vcvtpd2dq%XY",   { XMM, EXx }, 0 },
5229   },
5230
5231   /* PREFIX_VEX_0FE7 */
5232   {
5233     { Bad_Opcode },
5234     { Bad_Opcode },
5235     { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) },
5236   },
5237
5238   /* PREFIX_VEX_0FE8 */
5239   {
5240     { Bad_Opcode },
5241     { Bad_Opcode },
5242     { "vpsubsb",        { XM, Vex, EXx }, 0 },
5243   },
5244
5245   /* PREFIX_VEX_0FE9 */
5246   {
5247     { Bad_Opcode },
5248     { Bad_Opcode },
5249     { "vpsubsw",        { XM, Vex, EXx }, 0 },
5250   },
5251
5252   /* PREFIX_VEX_0FEA */
5253   {
5254     { Bad_Opcode },
5255     { Bad_Opcode },
5256     { "vpminsw",        { XM, Vex, EXx }, 0 },
5257   },
5258
5259   /* PREFIX_VEX_0FEB */
5260   {
5261     { Bad_Opcode },
5262     { Bad_Opcode },
5263     { "vpor",           { XM, Vex, EXx }, 0 },
5264   },
5265
5266   /* PREFIX_VEX_0FEC */
5267   {
5268     { Bad_Opcode },
5269     { Bad_Opcode },
5270     { "vpaddsb",        { XM, Vex, EXx }, 0 },
5271   },
5272
5273   /* PREFIX_VEX_0FED */
5274   {
5275     { Bad_Opcode },
5276     { Bad_Opcode },
5277     { "vpaddsw",        { XM, Vex, EXx }, 0 },
5278   },
5279
5280   /* PREFIX_VEX_0FEE */
5281   {
5282     { Bad_Opcode },
5283     { Bad_Opcode },
5284     { "vpmaxsw",        { XM, Vex, EXx }, 0 },
5285   },
5286
5287   /* PREFIX_VEX_0FEF */
5288   {
5289     { Bad_Opcode },
5290     { Bad_Opcode },
5291     { "vpxor",          { XM, Vex, EXx }, 0 },
5292   },
5293
5294   /* PREFIX_VEX_0FF0 */
5295   {
5296     { Bad_Opcode },
5297     { Bad_Opcode },
5298     { Bad_Opcode },
5299     { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
5300   },
5301
5302   /* PREFIX_VEX_0FF1 */
5303   {
5304     { Bad_Opcode },
5305     { Bad_Opcode },
5306     { "vpsllw",         { XM, Vex, EXxmm }, 0 },
5307   },
5308
5309   /* PREFIX_VEX_0FF2 */
5310   {
5311     { Bad_Opcode },
5312     { Bad_Opcode },
5313     { "vpslld",         { XM, Vex, EXxmm }, 0 },
5314   },
5315
5316   /* PREFIX_VEX_0FF3 */
5317   {
5318     { Bad_Opcode },
5319     { Bad_Opcode },
5320     { "vpsllq",         { XM, Vex, EXxmm }, 0 },
5321   },
5322
5323   /* PREFIX_VEX_0FF4 */
5324   {
5325     { Bad_Opcode },
5326     { Bad_Opcode },
5327     { "vpmuludq",       { XM, Vex, EXx }, 0 },
5328   },
5329
5330   /* PREFIX_VEX_0FF5 */
5331   {
5332     { Bad_Opcode },
5333     { Bad_Opcode },
5334     { "vpmaddwd",       { XM, Vex, EXx }, 0 },
5335   },
5336
5337   /* PREFIX_VEX_0FF6 */
5338   {
5339     { Bad_Opcode },
5340     { Bad_Opcode },
5341     { "vpsadbw",        { XM, Vex, EXx }, 0 },
5342   },
5343
5344   /* PREFIX_VEX_0FF7 */
5345   {
5346     { Bad_Opcode },
5347     { Bad_Opcode },
5348     { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) },
5349   },
5350
5351   /* PREFIX_VEX_0FF8 */
5352   {
5353     { Bad_Opcode },
5354     { Bad_Opcode },
5355     { "vpsubb",         { XM, Vex, EXx }, 0 },
5356   },
5357
5358   /* PREFIX_VEX_0FF9 */
5359   {
5360     { Bad_Opcode },
5361     { Bad_Opcode },
5362     { "vpsubw",         { XM, Vex, EXx }, 0 },
5363   },
5364
5365   /* PREFIX_VEX_0FFA */
5366   {
5367     { Bad_Opcode },
5368     { Bad_Opcode },
5369     { "vpsubd",         { XM, Vex, EXx }, 0 },
5370   },
5371
5372   /* PREFIX_VEX_0FFB */
5373   {
5374     { Bad_Opcode },
5375     { Bad_Opcode },
5376     { "vpsubq",         { XM, Vex, EXx }, 0 },
5377   },
5378
5379   /* PREFIX_VEX_0FFC */
5380   {
5381     { Bad_Opcode },
5382     { Bad_Opcode },
5383     { "vpaddb",         { XM, Vex, EXx }, 0 },
5384   },
5385
5386   /* PREFIX_VEX_0FFD */
5387   {
5388     { Bad_Opcode },
5389     { Bad_Opcode },
5390     { "vpaddw",         { XM, Vex, EXx }, 0 },
5391   },
5392
5393   /* PREFIX_VEX_0FFE */
5394   {
5395     { Bad_Opcode },
5396     { Bad_Opcode },
5397     { "vpaddd",         { XM, Vex, EXx }, 0 },
5398   },
5399
5400   /* PREFIX_VEX_0F3800 */
5401   {
5402     { Bad_Opcode },
5403     { Bad_Opcode },
5404     { "vpshufb",        { XM, Vex, EXx }, 0 },
5405   },
5406
5407   /* PREFIX_VEX_0F3801 */
5408   {
5409     { Bad_Opcode },
5410     { Bad_Opcode },
5411     { "vphaddw",        { XM, Vex, EXx }, 0 },
5412   },
5413
5414   /* PREFIX_VEX_0F3802 */
5415   {
5416     { Bad_Opcode },
5417     { Bad_Opcode },
5418     { "vphaddd",        { XM, Vex, EXx }, 0 },
5419   },
5420
5421   /* PREFIX_VEX_0F3803 */
5422   {
5423     { Bad_Opcode },
5424     { Bad_Opcode },
5425     { "vphaddsw",       { XM, Vex, EXx }, 0 },
5426   },
5427
5428   /* PREFIX_VEX_0F3804 */
5429   {
5430     { Bad_Opcode },
5431     { Bad_Opcode },
5432     { "vpmaddubsw",     { XM, Vex, EXx }, 0 },
5433   },
5434
5435   /* PREFIX_VEX_0F3805 */
5436   {
5437     { Bad_Opcode },
5438     { Bad_Opcode },
5439     { "vphsubw",        { XM, Vex, EXx }, 0 },
5440   },
5441
5442   /* PREFIX_VEX_0F3806 */
5443   {
5444     { Bad_Opcode },
5445     { Bad_Opcode },
5446     { "vphsubd",        { XM, Vex, EXx }, 0 },
5447   },
5448
5449   /* PREFIX_VEX_0F3807 */
5450   {
5451     { Bad_Opcode },
5452     { Bad_Opcode },
5453     { "vphsubsw",       { XM, Vex, EXx }, 0 },
5454   },
5455
5456   /* PREFIX_VEX_0F3808 */
5457   {
5458     { Bad_Opcode },
5459     { Bad_Opcode },
5460     { "vpsignb",        { XM, Vex, EXx }, 0 },
5461   },
5462
5463   /* PREFIX_VEX_0F3809 */
5464   {
5465     { Bad_Opcode },
5466     { Bad_Opcode },
5467     { "vpsignw",        { XM, Vex, EXx }, 0 },
5468   },
5469
5470   /* PREFIX_VEX_0F380A */
5471   {
5472     { Bad_Opcode },
5473     { Bad_Opcode },
5474     { "vpsignd",        { XM, Vex, EXx }, 0 },
5475   },
5476
5477   /* PREFIX_VEX_0F380B */
5478   {
5479     { Bad_Opcode },
5480     { Bad_Opcode },
5481     { "vpmulhrsw",      { XM, Vex, EXx }, 0 },
5482   },
5483
5484   /* PREFIX_VEX_0F380C */
5485   {
5486     { Bad_Opcode },
5487     { Bad_Opcode },
5488     { VEX_W_TABLE (VEX_W_0F380C_P_2) },
5489   },
5490
5491   /* PREFIX_VEX_0F380D */
5492   {
5493     { Bad_Opcode },
5494     { Bad_Opcode },
5495     { VEX_W_TABLE (VEX_W_0F380D_P_2) },
5496   },
5497
5498   /* PREFIX_VEX_0F380E */
5499   {
5500     { Bad_Opcode },
5501     { Bad_Opcode },
5502     { VEX_W_TABLE (VEX_W_0F380E_P_2) },
5503   },
5504
5505   /* PREFIX_VEX_0F380F */
5506   {
5507     { Bad_Opcode },
5508     { Bad_Opcode },
5509     { VEX_W_TABLE (VEX_W_0F380F_P_2) },
5510   },
5511
5512   /* PREFIX_VEX_0F3813 */
5513   {
5514     { Bad_Opcode },
5515     { Bad_Opcode },
5516     { VEX_W_TABLE (VEX_W_0F3813_P_2) },
5517   },
5518
5519   /* PREFIX_VEX_0F3816 */
5520   {
5521     { Bad_Opcode },
5522     { Bad_Opcode },
5523     { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) },
5524   },
5525
5526   /* PREFIX_VEX_0F3817 */
5527   {
5528     { Bad_Opcode },
5529     { Bad_Opcode },
5530     { "vptest",         { XM, EXx }, 0 },
5531   },
5532
5533   /* PREFIX_VEX_0F3818 */
5534   {
5535     { Bad_Opcode },
5536     { Bad_Opcode },
5537     { VEX_W_TABLE (VEX_W_0F3818_P_2) },
5538   },
5539
5540   /* PREFIX_VEX_0F3819 */
5541   {
5542     { Bad_Opcode },
5543     { Bad_Opcode },
5544     { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) },
5545   },
5546
5547   /* PREFIX_VEX_0F381A */
5548   {
5549     { Bad_Opcode },
5550     { Bad_Opcode },
5551     { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) },
5552   },
5553
5554   /* PREFIX_VEX_0F381C */
5555   {
5556     { Bad_Opcode },
5557     { Bad_Opcode },
5558     { "vpabsb",         { XM, EXx }, 0 },
5559   },
5560
5561   /* PREFIX_VEX_0F381D */
5562   {
5563     { Bad_Opcode },
5564     { Bad_Opcode },
5565     { "vpabsw",         { XM, EXx }, 0 },
5566   },
5567
5568   /* PREFIX_VEX_0F381E */
5569   {
5570     { Bad_Opcode },
5571     { Bad_Opcode },
5572     { "vpabsd",         { XM, EXx }, 0 },
5573   },
5574
5575   /* PREFIX_VEX_0F3820 */
5576   {
5577     { Bad_Opcode },
5578     { Bad_Opcode },
5579     { "vpmovsxbw",      { XM, EXxmmq }, 0 },
5580   },
5581
5582   /* PREFIX_VEX_0F3821 */
5583   {
5584     { Bad_Opcode },
5585     { Bad_Opcode },
5586     { "vpmovsxbd",      { XM, EXxmmqd }, 0 },
5587   },
5588
5589   /* PREFIX_VEX_0F3822 */
5590   {
5591     { Bad_Opcode },
5592     { Bad_Opcode },
5593     { "vpmovsxbq",      { XM, EXxmmdw }, 0 },
5594   },
5595
5596   /* PREFIX_VEX_0F3823 */
5597   {
5598     { Bad_Opcode },
5599     { Bad_Opcode },
5600     { "vpmovsxwd",      { XM, EXxmmq }, 0 },
5601   },
5602
5603   /* PREFIX_VEX_0F3824 */
5604   {
5605     { Bad_Opcode },
5606     { Bad_Opcode },
5607     { "vpmovsxwq",      { XM, EXxmmqd }, 0 },
5608   },
5609
5610   /* PREFIX_VEX_0F3825 */
5611   {
5612     { Bad_Opcode },
5613     { Bad_Opcode },
5614     { "vpmovsxdq",      { XM, EXxmmq }, 0 },
5615   },
5616
5617   /* PREFIX_VEX_0F3828 */
5618   {
5619     { Bad_Opcode },
5620     { Bad_Opcode },
5621     { "vpmuldq",        { XM, Vex, EXx }, 0 },
5622   },
5623
5624   /* PREFIX_VEX_0F3829 */
5625   {
5626     { Bad_Opcode },
5627     { Bad_Opcode },
5628     { "vpcmpeqq",       { XM, Vex, EXx }, 0 },
5629   },
5630
5631   /* PREFIX_VEX_0F382A */
5632   {
5633     { Bad_Opcode },
5634     { Bad_Opcode },
5635     { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) },
5636   },
5637
5638   /* PREFIX_VEX_0F382B */
5639   {
5640     { Bad_Opcode },
5641     { Bad_Opcode },
5642     { "vpackusdw",      { XM, Vex, EXx }, 0 },
5643   },
5644
5645   /* PREFIX_VEX_0F382C */
5646   {
5647     { Bad_Opcode },
5648     { Bad_Opcode },
5649      { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) },
5650   },
5651
5652   /* PREFIX_VEX_0F382D */
5653   {
5654     { Bad_Opcode },
5655     { Bad_Opcode },
5656      { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) },
5657   },
5658
5659   /* PREFIX_VEX_0F382E */
5660   {
5661     { Bad_Opcode },
5662     { Bad_Opcode },
5663      { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) },
5664   },
5665
5666   /* PREFIX_VEX_0F382F */
5667   {
5668     { Bad_Opcode },
5669     { Bad_Opcode },
5670      { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) },
5671   },
5672
5673   /* PREFIX_VEX_0F3830 */
5674   {
5675     { Bad_Opcode },
5676     { Bad_Opcode },
5677     { "vpmovzxbw",      { XM, EXxmmq }, 0 },
5678   },
5679
5680   /* PREFIX_VEX_0F3831 */
5681   {
5682     { Bad_Opcode },
5683     { Bad_Opcode },
5684     { "vpmovzxbd",      { XM, EXxmmqd }, 0 },
5685   },
5686
5687   /* PREFIX_VEX_0F3832 */
5688   {
5689     { Bad_Opcode },
5690     { Bad_Opcode },
5691     { "vpmovzxbq",      { XM, EXxmmdw }, 0 },
5692   },
5693
5694   /* PREFIX_VEX_0F3833 */
5695   {
5696     { Bad_Opcode },
5697     { Bad_Opcode },
5698     { "vpmovzxwd",      { XM, EXxmmq }, 0 },
5699   },
5700
5701   /* PREFIX_VEX_0F3834 */
5702   {
5703     { Bad_Opcode },
5704     { Bad_Opcode },
5705     { "vpmovzxwq",      { XM, EXxmmqd }, 0 },
5706   },
5707
5708   /* PREFIX_VEX_0F3835 */
5709   {
5710     { Bad_Opcode },
5711     { Bad_Opcode },
5712     { "vpmovzxdq",      { XM, EXxmmq }, 0 },
5713   },
5714
5715   /* PREFIX_VEX_0F3836 */
5716   {
5717     { Bad_Opcode },
5718     { Bad_Opcode },
5719     { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) },
5720   },
5721
5722   /* PREFIX_VEX_0F3837 */
5723   {
5724     { Bad_Opcode },
5725     { Bad_Opcode },
5726     { "vpcmpgtq",       { XM, Vex, EXx }, 0 },
5727   },
5728
5729   /* PREFIX_VEX_0F3838 */
5730   {
5731     { Bad_Opcode },
5732     { Bad_Opcode },
5733     { "vpminsb",        { XM, Vex, EXx }, 0 },
5734   },
5735
5736   /* PREFIX_VEX_0F3839 */
5737   {
5738     { Bad_Opcode },
5739     { Bad_Opcode },
5740     { "vpminsd",        { XM, Vex, EXx }, 0 },
5741   },
5742
5743   /* PREFIX_VEX_0F383A */
5744   {
5745     { Bad_Opcode },
5746     { Bad_Opcode },
5747     { "vpminuw",        { XM, Vex, EXx }, 0 },
5748   },
5749
5750   /* PREFIX_VEX_0F383B */
5751   {
5752     { Bad_Opcode },
5753     { Bad_Opcode },
5754     { "vpminud",        { XM, Vex, EXx }, 0 },
5755   },
5756
5757   /* PREFIX_VEX_0F383C */
5758   {
5759     { Bad_Opcode },
5760     { Bad_Opcode },
5761     { "vpmaxsb",        { XM, Vex, EXx }, 0 },
5762   },
5763
5764   /* PREFIX_VEX_0F383D */
5765   {
5766     { Bad_Opcode },
5767     { Bad_Opcode },
5768     { "vpmaxsd",        { XM, Vex, EXx }, 0 },
5769   },
5770
5771   /* PREFIX_VEX_0F383E */
5772   {
5773     { Bad_Opcode },
5774     { Bad_Opcode },
5775     { "vpmaxuw",        { XM, Vex, EXx }, 0 },
5776   },
5777
5778   /* PREFIX_VEX_0F383F */
5779   {
5780     { Bad_Opcode },
5781     { Bad_Opcode },
5782     { "vpmaxud",        { XM, Vex, EXx }, 0 },
5783   },
5784
5785   /* PREFIX_VEX_0F3840 */
5786   {
5787     { Bad_Opcode },
5788     { Bad_Opcode },
5789     { "vpmulld",        { XM, Vex, EXx }, 0 },
5790   },
5791
5792   /* PREFIX_VEX_0F3841 */
5793   {
5794     { Bad_Opcode },
5795     { Bad_Opcode },
5796     { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) },
5797   },
5798
5799   /* PREFIX_VEX_0F3845 */
5800   {
5801     { Bad_Opcode },
5802     { Bad_Opcode },
5803     { "vpsrlv%LW", { XM, Vex, EXx }, 0 },
5804   },
5805
5806   /* PREFIX_VEX_0F3846 */
5807   {
5808     { Bad_Opcode },
5809     { Bad_Opcode },
5810     { VEX_W_TABLE (VEX_W_0F3846_P_2) },
5811   },
5812
5813   /* PREFIX_VEX_0F3847 */
5814   {
5815     { Bad_Opcode },
5816     { Bad_Opcode },
5817     { "vpsllv%LW", { XM, Vex, EXx }, 0 },
5818   },
5819
5820   /* PREFIX_VEX_0F3858 */
5821   {
5822     { Bad_Opcode },
5823     { Bad_Opcode },
5824     { VEX_W_TABLE (VEX_W_0F3858_P_2) },
5825   },
5826
5827   /* PREFIX_VEX_0F3859 */
5828   {
5829     { Bad_Opcode },
5830     { Bad_Opcode },
5831     { VEX_W_TABLE (VEX_W_0F3859_P_2) },
5832   },
5833
5834   /* PREFIX_VEX_0F385A */
5835   {
5836     { Bad_Opcode },
5837     { Bad_Opcode },
5838     { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) },
5839   },
5840
5841   /* PREFIX_VEX_0F3878 */
5842   {
5843     { Bad_Opcode },
5844     { Bad_Opcode },
5845     { VEX_W_TABLE (VEX_W_0F3878_P_2) },
5846   },
5847
5848   /* PREFIX_VEX_0F3879 */
5849   {
5850     { Bad_Opcode },
5851     { Bad_Opcode },
5852     { VEX_W_TABLE (VEX_W_0F3879_P_2) },
5853   },
5854
5855   /* PREFIX_VEX_0F388C */
5856   {
5857     { Bad_Opcode },
5858     { Bad_Opcode },
5859     { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) },
5860   },
5861
5862   /* PREFIX_VEX_0F388E */
5863   {
5864     { Bad_Opcode },
5865     { Bad_Opcode },
5866     { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) },
5867   },
5868
5869   /* PREFIX_VEX_0F3890 */
5870   {
5871     { Bad_Opcode },
5872     { Bad_Opcode },
5873     { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex }, 0 },
5874   },
5875
5876   /* PREFIX_VEX_0F3891 */
5877   {
5878     { Bad_Opcode },
5879     { Bad_Opcode },
5880     { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
5881   },
5882
5883   /* PREFIX_VEX_0F3892 */
5884   {
5885     { Bad_Opcode },
5886     { Bad_Opcode },
5887     { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex }, 0 },
5888   },
5889
5890   /* PREFIX_VEX_0F3893 */
5891   {
5892     { Bad_Opcode },
5893     { Bad_Opcode },
5894     { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
5895   },
5896
5897   /* PREFIX_VEX_0F3896 */
5898   {
5899     { Bad_Opcode },
5900     { Bad_Opcode },
5901     { "vfmaddsub132p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
5902   },
5903
5904   /* PREFIX_VEX_0F3897 */
5905   {
5906     { Bad_Opcode },
5907     { Bad_Opcode },
5908     { "vfmsubadd132p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
5909   },
5910
5911   /* PREFIX_VEX_0F3898 */
5912   {
5913     { Bad_Opcode },
5914     { Bad_Opcode },
5915     { "vfmadd132p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
5916   },
5917
5918   /* PREFIX_VEX_0F3899 */
5919   {
5920     { Bad_Opcode },
5921     { Bad_Opcode },
5922     { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
5923   },
5924
5925   /* PREFIX_VEX_0F389A */
5926   {
5927     { Bad_Opcode },
5928     { Bad_Opcode },
5929     { "vfmsub132p%XW", { XM, Vex, EXx }, 0 },
5930   },
5931
5932   /* PREFIX_VEX_0F389B */
5933   {
5934     { Bad_Opcode },
5935     { Bad_Opcode },
5936     { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
5937   },
5938
5939   /* PREFIX_VEX_0F389C */
5940   {
5941     { Bad_Opcode },
5942     { Bad_Opcode },
5943     { "vfnmadd132p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
5944   },
5945
5946   /* PREFIX_VEX_0F389D */
5947   {
5948     { Bad_Opcode },
5949     { Bad_Opcode },
5950     { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
5951   },
5952
5953   /* PREFIX_VEX_0F389E */
5954   {
5955     { Bad_Opcode },
5956     { Bad_Opcode },
5957     { "vfnmsub132p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
5958   },
5959
5960   /* PREFIX_VEX_0F389F */
5961   {
5962     { Bad_Opcode },
5963     { Bad_Opcode },
5964     { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
5965   },
5966
5967   /* PREFIX_VEX_0F38A6 */
5968   {
5969     { Bad_Opcode },
5970     { Bad_Opcode },
5971     { "vfmaddsub213p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
5972     { Bad_Opcode },
5973   },
5974
5975   /* PREFIX_VEX_0F38A7 */
5976   {
5977     { Bad_Opcode },
5978     { Bad_Opcode },
5979     { "vfmsubadd213p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
5980   },
5981
5982   /* PREFIX_VEX_0F38A8 */
5983   {
5984     { Bad_Opcode },
5985     { Bad_Opcode },
5986     { "vfmadd213p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
5987   },
5988
5989   /* PREFIX_VEX_0F38A9 */
5990   {
5991     { Bad_Opcode },
5992     { Bad_Opcode },
5993     { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
5994   },
5995
5996   /* PREFIX_VEX_0F38AA */
5997   {
5998     { Bad_Opcode },
5999     { Bad_Opcode },
6000     { "vfmsub213p%XW", { XM, Vex, EXx }, 0 },
6001   },
6002
6003   /* PREFIX_VEX_0F38AB */
6004   {
6005     { Bad_Opcode },
6006     { Bad_Opcode },
6007     { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6008   },
6009
6010   /* PREFIX_VEX_0F38AC */
6011   {
6012     { Bad_Opcode },
6013     { Bad_Opcode },
6014     { "vfnmadd213p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6015   },
6016
6017   /* PREFIX_VEX_0F38AD */
6018   {
6019     { Bad_Opcode },
6020     { Bad_Opcode },
6021     { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
6022   },
6023
6024   /* PREFIX_VEX_0F38AE */
6025   {
6026     { Bad_Opcode },
6027     { Bad_Opcode },
6028     { "vfnmsub213p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6029   },
6030
6031   /* PREFIX_VEX_0F38AF */
6032   {
6033     { Bad_Opcode },
6034     { Bad_Opcode },
6035     { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
6036   },
6037
6038   /* PREFIX_VEX_0F38B6 */
6039   {
6040     { Bad_Opcode },
6041     { Bad_Opcode },
6042     { "vfmaddsub231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6043   },
6044
6045   /* PREFIX_VEX_0F38B7 */
6046   {
6047     { Bad_Opcode },
6048     { Bad_Opcode },
6049     { "vfmsubadd231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6050   },
6051
6052   /* PREFIX_VEX_0F38B8 */
6053   {
6054     { Bad_Opcode },
6055     { Bad_Opcode },
6056     { "vfmadd231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6057   },
6058
6059   /* PREFIX_VEX_0F38B9 */
6060   {
6061     { Bad_Opcode },
6062     { Bad_Opcode },
6063     { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
6064   },
6065
6066   /* PREFIX_VEX_0F38BA */
6067   {
6068     { Bad_Opcode },
6069     { Bad_Opcode },
6070     { "vfmsub231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6071   },
6072
6073   /* PREFIX_VEX_0F38BB */
6074   {
6075     { Bad_Opcode },
6076     { Bad_Opcode },
6077     { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
6078   },
6079
6080   /* PREFIX_VEX_0F38BC */
6081   {
6082     { Bad_Opcode },
6083     { Bad_Opcode },
6084     { "vfnmadd231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6085   },
6086
6087   /* PREFIX_VEX_0F38BD */
6088   {
6089     { Bad_Opcode },
6090     { Bad_Opcode },
6091     { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
6092   },
6093
6094   /* PREFIX_VEX_0F38BE */
6095   {
6096     { Bad_Opcode },
6097     { Bad_Opcode },
6098     { "vfnmsub231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6099   },
6100
6101   /* PREFIX_VEX_0F38BF */
6102   {
6103     { Bad_Opcode },
6104     { Bad_Opcode },
6105     { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
6106   },
6107
6108   /* PREFIX_VEX_0F38CF */
6109   {
6110     { Bad_Opcode },
6111     { Bad_Opcode },
6112     { VEX_W_TABLE (VEX_W_0F38CF_P_2) },
6113   },
6114
6115   /* PREFIX_VEX_0F38DB */
6116   {
6117     { Bad_Opcode },
6118     { Bad_Opcode },
6119     { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) },
6120   },
6121
6122   /* PREFIX_VEX_0F38DC */
6123   {
6124     { Bad_Opcode },
6125     { Bad_Opcode },
6126     { "vaesenc",        { XM, Vex, EXx }, 0 },
6127   },
6128
6129   /* PREFIX_VEX_0F38DD */
6130   {
6131     { Bad_Opcode },
6132     { Bad_Opcode },
6133     { "vaesenclast",    { XM, Vex, EXx }, 0 },
6134   },
6135
6136   /* PREFIX_VEX_0F38DE */
6137   {
6138     { Bad_Opcode },
6139     { Bad_Opcode },
6140     { "vaesdec",        { XM, Vex, EXx }, 0 },
6141   },
6142
6143   /* PREFIX_VEX_0F38DF */
6144   {
6145     { Bad_Opcode },
6146     { Bad_Opcode },
6147     { "vaesdeclast",    { XM, Vex, EXx }, 0 },
6148   },
6149
6150   /* PREFIX_VEX_0F38F2 */
6151   {
6152     { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) },
6153   },
6154
6155   /* PREFIX_VEX_0F38F3_REG_1 */
6156   {
6157     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) },
6158   },
6159
6160   /* PREFIX_VEX_0F38F3_REG_2 */
6161   {
6162     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) },
6163   },
6164
6165   /* PREFIX_VEX_0F38F3_REG_3 */
6166   {
6167     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) },
6168   },
6169
6170   /* PREFIX_VEX_0F38F5 */
6171   {
6172     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) },
6173     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) },
6174     { Bad_Opcode },
6175     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) },
6176   },
6177
6178   /* PREFIX_VEX_0F38F6 */
6179   {
6180     { Bad_Opcode },
6181     { Bad_Opcode },
6182     { Bad_Opcode },
6183     { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) },
6184   },
6185
6186   /* PREFIX_VEX_0F38F7 */
6187   {
6188     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) },
6189     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) },
6190     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) },
6191     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) },
6192   },
6193
6194   /* PREFIX_VEX_0F3A00 */
6195   {
6196     { Bad_Opcode },
6197     { Bad_Opcode },
6198     { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) },
6199   },
6200
6201   /* PREFIX_VEX_0F3A01 */
6202   {
6203     { Bad_Opcode },
6204     { Bad_Opcode },
6205     { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) },
6206   },
6207
6208   /* PREFIX_VEX_0F3A02 */
6209   {
6210     { Bad_Opcode },
6211     { Bad_Opcode },
6212     { VEX_W_TABLE (VEX_W_0F3A02_P_2) },
6213   },
6214
6215   /* PREFIX_VEX_0F3A04 */
6216   {
6217     { Bad_Opcode },
6218     { Bad_Opcode },
6219     { VEX_W_TABLE (VEX_W_0F3A04_P_2) },
6220   },
6221
6222   /* PREFIX_VEX_0F3A05 */
6223   {
6224     { Bad_Opcode },
6225     { Bad_Opcode },
6226     { VEX_W_TABLE (VEX_W_0F3A05_P_2) },
6227   },
6228
6229   /* PREFIX_VEX_0F3A06 */
6230   {
6231     { Bad_Opcode },
6232     { Bad_Opcode },
6233     { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) },
6234   },
6235
6236   /* PREFIX_VEX_0F3A08 */
6237   {
6238     { Bad_Opcode },
6239     { Bad_Opcode },
6240     { "vroundps",       { XM, EXx, Ib }, 0 },
6241   },
6242
6243   /* PREFIX_VEX_0F3A09 */
6244   {
6245     { Bad_Opcode },
6246     { Bad_Opcode },
6247     { "vroundpd",       { XM, EXx, Ib }, 0 },
6248   },
6249
6250   /* PREFIX_VEX_0F3A0A */
6251   {
6252     { Bad_Opcode },
6253     { Bad_Opcode },
6254     { "vroundss",       { XMScalar, VexScalar, EXxmm_md, Ib }, 0 },
6255   },
6256
6257   /* PREFIX_VEX_0F3A0B */
6258   {
6259     { Bad_Opcode },
6260     { Bad_Opcode },
6261     { "vroundsd",       { XMScalar, VexScalar, EXxmm_mq, Ib }, 0 },
6262   },
6263
6264   /* PREFIX_VEX_0F3A0C */
6265   {
6266     { Bad_Opcode },
6267     { Bad_Opcode },
6268     { "vblendps",       { XM, Vex, EXx, Ib }, 0 },
6269   },
6270
6271   /* PREFIX_VEX_0F3A0D */
6272   {
6273     { Bad_Opcode },
6274     { Bad_Opcode },
6275     { "vblendpd",       { XM, Vex, EXx, Ib }, 0 },
6276   },
6277
6278   /* PREFIX_VEX_0F3A0E */
6279   {
6280     { Bad_Opcode },
6281     { Bad_Opcode },
6282     { "vpblendw",       { XM, Vex, EXx, Ib }, 0 },
6283   },
6284
6285   /* PREFIX_VEX_0F3A0F */
6286   {
6287     { Bad_Opcode },
6288     { Bad_Opcode },
6289     { "vpalignr",       { XM, Vex, EXx, Ib }, 0 },
6290   },
6291
6292   /* PREFIX_VEX_0F3A14 */
6293   {
6294     { Bad_Opcode },
6295     { Bad_Opcode },
6296     { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) },
6297   },
6298
6299   /* PREFIX_VEX_0F3A15 */
6300   {
6301     { Bad_Opcode },
6302     { Bad_Opcode },
6303     { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) },
6304   },
6305
6306   /* PREFIX_VEX_0F3A16 */
6307   {
6308     { Bad_Opcode },
6309     { Bad_Opcode },
6310     { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) },
6311   },
6312
6313   /* PREFIX_VEX_0F3A17 */
6314   {
6315     { Bad_Opcode },
6316     { Bad_Opcode },
6317     { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) },
6318   },
6319
6320   /* PREFIX_VEX_0F3A18 */
6321   {
6322     { Bad_Opcode },
6323     { Bad_Opcode },
6324     { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) },
6325   },
6326
6327   /* PREFIX_VEX_0F3A19 */
6328   {
6329     { Bad_Opcode },
6330     { Bad_Opcode },
6331     { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) },
6332   },
6333
6334   /* PREFIX_VEX_0F3A1D */
6335   {
6336     { Bad_Opcode },
6337     { Bad_Opcode },
6338     { VEX_W_TABLE (VEX_W_0F3A1D_P_2) },
6339   },
6340
6341   /* PREFIX_VEX_0F3A20 */
6342   {
6343     { Bad_Opcode },
6344     { Bad_Opcode },
6345     { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) },
6346   },
6347
6348   /* PREFIX_VEX_0F3A21 */
6349   {
6350     { Bad_Opcode },
6351     { Bad_Opcode },
6352     { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) },
6353   },
6354
6355   /* PREFIX_VEX_0F3A22 */
6356   {
6357     { Bad_Opcode },
6358     { Bad_Opcode },
6359     { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) },
6360   },
6361
6362   /* PREFIX_VEX_0F3A30 */
6363   {
6364     { Bad_Opcode },
6365     { Bad_Opcode },
6366     { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2) },
6367   },
6368
6369   /* PREFIX_VEX_0F3A31 */
6370   {
6371     { Bad_Opcode },
6372     { Bad_Opcode },
6373     { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2) },
6374   },
6375
6376   /* PREFIX_VEX_0F3A32 */
6377   {
6378     { Bad_Opcode },
6379     { Bad_Opcode },
6380     { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2) },
6381   },
6382
6383   /* PREFIX_VEX_0F3A33 */
6384   {
6385     { Bad_Opcode },
6386     { Bad_Opcode },
6387     { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2) },
6388   },
6389
6390   /* PREFIX_VEX_0F3A38 */
6391   {
6392     { Bad_Opcode },
6393     { Bad_Opcode },
6394     { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) },
6395   },
6396
6397   /* PREFIX_VEX_0F3A39 */
6398   {
6399     { Bad_Opcode },
6400     { Bad_Opcode },
6401     { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) },
6402   },
6403
6404   /* PREFIX_VEX_0F3A40 */
6405   {
6406     { Bad_Opcode },
6407     { Bad_Opcode },
6408     { "vdpps",          { XM, Vex, EXx, Ib }, 0 },
6409   },
6410
6411   /* PREFIX_VEX_0F3A41 */
6412   {
6413     { Bad_Opcode },
6414     { Bad_Opcode },
6415     { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) },
6416   },
6417
6418   /* PREFIX_VEX_0F3A42 */
6419   {
6420     { Bad_Opcode },
6421     { Bad_Opcode },
6422     { "vmpsadbw",       { XM, Vex, EXx, Ib }, 0 },
6423   },
6424
6425   /* PREFIX_VEX_0F3A44 */
6426   {
6427     { Bad_Opcode },
6428     { Bad_Opcode },
6429     { "vpclmulqdq",     { XM, Vex, EXx, PCLMUL }, 0 },
6430   },
6431
6432   /* PREFIX_VEX_0F3A46 */
6433   {
6434     { Bad_Opcode },
6435     { Bad_Opcode },
6436     { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) },
6437   },
6438
6439   /* PREFIX_VEX_0F3A48 */
6440   {
6441     { Bad_Opcode },
6442     { Bad_Opcode },
6443     { VEX_W_TABLE (VEX_W_0F3A48_P_2) },
6444   },
6445
6446   /* PREFIX_VEX_0F3A49 */
6447   {
6448     { Bad_Opcode },
6449     { Bad_Opcode },
6450     { VEX_W_TABLE (VEX_W_0F3A49_P_2) },
6451   },
6452
6453   /* PREFIX_VEX_0F3A4A */
6454   {
6455     { Bad_Opcode },
6456     { Bad_Opcode },
6457     { VEX_W_TABLE (VEX_W_0F3A4A_P_2) },
6458   },
6459
6460   /* PREFIX_VEX_0F3A4B */
6461   {
6462     { Bad_Opcode },
6463     { Bad_Opcode },
6464     { VEX_W_TABLE (VEX_W_0F3A4B_P_2) },
6465   },
6466
6467   /* PREFIX_VEX_0F3A4C */
6468   {
6469     { Bad_Opcode },
6470     { Bad_Opcode },
6471     { VEX_W_TABLE (VEX_W_0F3A4C_P_2) },
6472   },
6473
6474   /* PREFIX_VEX_0F3A5C */
6475   {
6476     { Bad_Opcode },
6477     { Bad_Opcode },
6478     { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6479   },
6480
6481   /* PREFIX_VEX_0F3A5D */
6482   {
6483     { Bad_Opcode },
6484     { Bad_Opcode },
6485     { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6486   },
6487
6488   /* PREFIX_VEX_0F3A5E */
6489   {
6490     { Bad_Opcode },
6491     { Bad_Opcode },
6492     { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6493   },
6494
6495   /* PREFIX_VEX_0F3A5F */
6496   {
6497     { Bad_Opcode },
6498     { Bad_Opcode },
6499     { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6500   },
6501
6502   /* PREFIX_VEX_0F3A60 */
6503   {
6504     { Bad_Opcode },
6505     { Bad_Opcode },
6506     { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) },
6507     { Bad_Opcode },
6508   },
6509
6510   /* PREFIX_VEX_0F3A61 */
6511   {
6512     { Bad_Opcode },
6513     { Bad_Opcode },
6514     { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) },
6515   },
6516
6517   /* PREFIX_VEX_0F3A62 */
6518   {
6519     { Bad_Opcode },
6520     { Bad_Opcode },
6521     { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) },
6522   },
6523
6524   /* PREFIX_VEX_0F3A63 */
6525   {
6526     { Bad_Opcode },
6527     { Bad_Opcode },
6528     { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) },
6529   },
6530
6531   /* PREFIX_VEX_0F3A68 */
6532   {
6533     { Bad_Opcode },
6534     { Bad_Opcode },
6535     { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6536   },
6537
6538   /* PREFIX_VEX_0F3A69 */
6539   {
6540     { Bad_Opcode },
6541     { Bad_Opcode },
6542     { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6543   },
6544
6545   /* PREFIX_VEX_0F3A6A */
6546   {
6547     { Bad_Opcode },
6548     { Bad_Opcode },
6549     { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) },
6550   },
6551
6552   /* PREFIX_VEX_0F3A6B */
6553   {
6554     { Bad_Opcode },
6555     { Bad_Opcode },
6556     { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) },
6557   },
6558
6559   /* PREFIX_VEX_0F3A6C */
6560   {
6561     { Bad_Opcode },
6562     { Bad_Opcode },
6563     { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6564   },
6565
6566   /* PREFIX_VEX_0F3A6D */
6567   {
6568     { Bad_Opcode },
6569     { Bad_Opcode },
6570     { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6571   },
6572
6573   /* PREFIX_VEX_0F3A6E */
6574   {
6575     { Bad_Opcode },
6576     { Bad_Opcode },
6577     { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) },
6578   },
6579
6580   /* PREFIX_VEX_0F3A6F */
6581   {
6582     { Bad_Opcode },
6583     { Bad_Opcode },
6584     { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) },
6585   },
6586
6587   /* PREFIX_VEX_0F3A78 */
6588   {
6589     { Bad_Opcode },
6590     { Bad_Opcode },
6591     { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6592   },
6593
6594   /* PREFIX_VEX_0F3A79 */
6595   {
6596     { Bad_Opcode },
6597     { Bad_Opcode },
6598     { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6599   },
6600
6601   /* PREFIX_VEX_0F3A7A */
6602   {
6603     { Bad_Opcode },
6604     { Bad_Opcode },
6605     { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) },
6606   },
6607
6608   /* PREFIX_VEX_0F3A7B */
6609   {
6610     { Bad_Opcode },
6611     { Bad_Opcode },
6612     { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) },
6613   },
6614
6615   /* PREFIX_VEX_0F3A7C */
6616   {
6617     { Bad_Opcode },
6618     { Bad_Opcode },
6619     { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6620     { Bad_Opcode },
6621   },
6622
6623   /* PREFIX_VEX_0F3A7D */
6624   {
6625     { Bad_Opcode },
6626     { Bad_Opcode },
6627     { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6628   },
6629
6630   /* PREFIX_VEX_0F3A7E */
6631   {
6632     { Bad_Opcode },
6633     { Bad_Opcode },
6634     { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) },
6635   },
6636
6637   /* PREFIX_VEX_0F3A7F */
6638   {
6639     { Bad_Opcode },
6640     { Bad_Opcode },
6641     { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) },
6642   },
6643
6644   /* PREFIX_VEX_0F3ACE */
6645   {
6646     { Bad_Opcode },
6647     { Bad_Opcode },
6648     { VEX_W_TABLE (VEX_W_0F3ACE_P_2) },
6649   },
6650
6651   /* PREFIX_VEX_0F3ACF */
6652   {
6653     { Bad_Opcode },
6654     { Bad_Opcode },
6655     { VEX_W_TABLE (VEX_W_0F3ACF_P_2) },
6656   },
6657
6658   /* PREFIX_VEX_0F3ADF */
6659   {
6660     { Bad_Opcode },
6661     { Bad_Opcode },
6662     { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) },
6663   },
6664
6665   /* PREFIX_VEX_0F3AF0 */
6666   {
6667     { Bad_Opcode },
6668     { Bad_Opcode },
6669     { Bad_Opcode },
6670     { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) },
6671   },
6672
6673 #include "i386-dis-evex-prefix.h"
6674 };
6675
6676 static const struct dis386 x86_64_table[][2] = {
6677   /* X86_64_06 */
6678   {
6679     { "pushP", { es }, 0 },
6680   },
6681
6682   /* X86_64_07 */
6683   {
6684     { "popP", { es }, 0 },
6685   },
6686
6687   /* X86_64_0E */
6688   {
6689     { "pushP", { cs }, 0 },
6690   },
6691
6692   /* X86_64_16 */
6693   {
6694     { "pushP", { ss }, 0 },
6695   },
6696
6697   /* X86_64_17 */
6698   {
6699     { "popP", { ss }, 0 },
6700   },
6701
6702   /* X86_64_1E */
6703   {
6704     { "pushP", { ds }, 0 },
6705   },
6706
6707   /* X86_64_1F */
6708   {
6709     { "popP", { ds }, 0 },
6710   },
6711
6712   /* X86_64_27 */
6713   {
6714     { "daa", { XX }, 0 },
6715   },
6716
6717   /* X86_64_2F */
6718   {
6719     { "das", { XX }, 0 },
6720   },
6721
6722   /* X86_64_37 */
6723   {
6724     { "aaa", { XX }, 0 },
6725   },
6726
6727   /* X86_64_3F */
6728   {
6729     { "aas", { XX }, 0 },
6730   },
6731
6732   /* X86_64_60 */
6733   {
6734     { "pushaP", { XX }, 0 },
6735   },
6736
6737   /* X86_64_61 */
6738   {
6739     { "popaP", { XX }, 0 },
6740   },
6741
6742   /* X86_64_62 */
6743   {
6744     { MOD_TABLE (MOD_62_32BIT) },
6745     { EVEX_TABLE (EVEX_0F) },
6746   },
6747
6748   /* X86_64_63 */
6749   {
6750     { "arpl", { Ew, Gw }, 0 },
6751     { "movs", { { OP_G, movsxd_mode }, { MOVSXD_Fixup, movsxd_mode } }, 0 },
6752   },
6753
6754   /* X86_64_6D */
6755   {
6756     { "ins{R|}", { Yzr, indirDX }, 0 },
6757     { "ins{G|}", { Yzr, indirDX }, 0 },
6758   },
6759
6760   /* X86_64_6F */
6761   {
6762     { "outs{R|}", { indirDXr, Xz }, 0 },
6763     { "outs{G|}", { indirDXr, Xz }, 0 },
6764   },
6765
6766   /* X86_64_82 */
6767   {
6768     /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode.  */
6769     { REG_TABLE (REG_80) },
6770   },
6771
6772   /* X86_64_9A */
6773   {
6774     { "{l|}call{T|}", { Ap }, 0 },
6775   },
6776
6777   /* X86_64_C2 */
6778   {
6779     { "retP",           { Iw, BND }, 0 },
6780     { "ret@",           { Iw, BND }, 0 },
6781   },
6782
6783   /* X86_64_C3 */
6784   {
6785     { "retP",           { BND }, 0 },
6786     { "ret@",           { BND }, 0 },
6787   },
6788
6789   /* X86_64_C4 */
6790   {
6791     { MOD_TABLE (MOD_C4_32BIT) },
6792     { VEX_C4_TABLE (VEX_0F) },
6793   },
6794
6795   /* X86_64_C5 */
6796   {
6797     { MOD_TABLE (MOD_C5_32BIT) },
6798     { VEX_C5_TABLE (VEX_0F) },
6799   },
6800
6801   /* X86_64_CE */
6802   {
6803     { "into", { XX }, 0 },
6804   },
6805
6806   /* X86_64_D4 */
6807   {
6808     { "aam", { Ib }, 0 },
6809   },
6810
6811   /* X86_64_D5 */
6812   {
6813     { "aad", { Ib }, 0 },
6814   },
6815
6816   /* X86_64_E8 */
6817   {
6818     { "callP",          { Jv, BND }, 0 },
6819     { "call@",          { Jv, BND }, 0 }
6820   },
6821
6822   /* X86_64_E9 */
6823   {
6824     { "jmpP",           { Jv, BND }, 0 },
6825     { "jmp@",           { Jv, BND }, 0 }
6826   },
6827
6828   /* X86_64_EA */
6829   {
6830     { "{l|}jmp{T|}", { Ap }, 0 },
6831   },
6832
6833   /* X86_64_0F01_REG_0 */
6834   {
6835     { "sgdt{Q|Q}", { M }, 0 },
6836     { "sgdt", { M }, 0 },
6837   },
6838
6839   /* X86_64_0F01_REG_1 */
6840   {
6841     { "sidt{Q|Q}", { M }, 0 },
6842     { "sidt", { M }, 0 },
6843   },
6844
6845   /* X86_64_0F01_REG_2 */
6846   {
6847     { "lgdt{Q|Q}", { M }, 0 },
6848     { "lgdt", { M }, 0 },
6849   },
6850
6851   /* X86_64_0F01_REG_3 */
6852   {
6853     { "lidt{Q|Q}", { M }, 0 },
6854     { "lidt", { M }, 0 },
6855   },
6856 };
6857
6858 static const struct dis386 three_byte_table[][256] = {
6859
6860   /* THREE_BYTE_0F38 */
6861   {
6862     /* 00 */
6863     { "pshufb",         { MX, EM }, PREFIX_OPCODE },
6864     { "phaddw",         { MX, EM }, PREFIX_OPCODE },
6865     { "phaddd",         { MX, EM }, PREFIX_OPCODE },
6866     { "phaddsw",        { MX, EM }, PREFIX_OPCODE },
6867     { "pmaddubsw",      { MX, EM }, PREFIX_OPCODE },
6868     { "phsubw",         { MX, EM }, PREFIX_OPCODE },
6869     { "phsubd",         { MX, EM }, PREFIX_OPCODE },
6870     { "phsubsw",        { MX, EM }, PREFIX_OPCODE },
6871     /* 08 */
6872     { "psignb",         { MX, EM }, PREFIX_OPCODE },
6873     { "psignw",         { MX, EM }, PREFIX_OPCODE },
6874     { "psignd",         { MX, EM }, PREFIX_OPCODE },
6875     { "pmulhrsw",       { MX, EM }, PREFIX_OPCODE },
6876     { Bad_Opcode },
6877     { Bad_Opcode },
6878     { Bad_Opcode },
6879     { Bad_Opcode },
6880     /* 10 */
6881     { PREFIX_TABLE (PREFIX_0F3810) },
6882     { Bad_Opcode },
6883     { Bad_Opcode },
6884     { Bad_Opcode },
6885     { PREFIX_TABLE (PREFIX_0F3814) },
6886     { PREFIX_TABLE (PREFIX_0F3815) },
6887     { Bad_Opcode },
6888     { PREFIX_TABLE (PREFIX_0F3817) },
6889     /* 18 */
6890     { Bad_Opcode },
6891     { Bad_Opcode },
6892     { Bad_Opcode },
6893     { Bad_Opcode },
6894     { "pabsb",          { MX, EM }, PREFIX_OPCODE },
6895     { "pabsw",          { MX, EM }, PREFIX_OPCODE },
6896     { "pabsd",          { MX, EM }, PREFIX_OPCODE },
6897     { Bad_Opcode },
6898     /* 20 */
6899     { PREFIX_TABLE (PREFIX_0F3820) },
6900     { PREFIX_TABLE (PREFIX_0F3821) },
6901     { PREFIX_TABLE (PREFIX_0F3822) },
6902     { PREFIX_TABLE (PREFIX_0F3823) },
6903     { PREFIX_TABLE (PREFIX_0F3824) },
6904     { PREFIX_TABLE (PREFIX_0F3825) },
6905     { Bad_Opcode },
6906     { Bad_Opcode },
6907     /* 28 */
6908     { PREFIX_TABLE (PREFIX_0F3828) },
6909     { PREFIX_TABLE (PREFIX_0F3829) },
6910     { PREFIX_TABLE (PREFIX_0F382A) },
6911     { PREFIX_TABLE (PREFIX_0F382B) },
6912     { Bad_Opcode },
6913     { Bad_Opcode },
6914     { Bad_Opcode },
6915     { Bad_Opcode },
6916     /* 30 */
6917     { PREFIX_TABLE (PREFIX_0F3830) },
6918     { PREFIX_TABLE (PREFIX_0F3831) },
6919     { PREFIX_TABLE (PREFIX_0F3832) },
6920     { PREFIX_TABLE (PREFIX_0F3833) },
6921     { PREFIX_TABLE (PREFIX_0F3834) },
6922     { PREFIX_TABLE (PREFIX_0F3835) },
6923     { Bad_Opcode },
6924     { PREFIX_TABLE (PREFIX_0F3837) },
6925     /* 38 */
6926     { PREFIX_TABLE (PREFIX_0F3838) },
6927     { PREFIX_TABLE (PREFIX_0F3839) },
6928     { PREFIX_TABLE (PREFIX_0F383A) },
6929     { PREFIX_TABLE (PREFIX_0F383B) },
6930     { PREFIX_TABLE (PREFIX_0F383C) },
6931     { PREFIX_TABLE (PREFIX_0F383D) },
6932     { PREFIX_TABLE (PREFIX_0F383E) },
6933     { PREFIX_TABLE (PREFIX_0F383F) },
6934     /* 40 */
6935     { PREFIX_TABLE (PREFIX_0F3840) },
6936     { PREFIX_TABLE (PREFIX_0F3841) },
6937     { Bad_Opcode },
6938     { Bad_Opcode },
6939     { Bad_Opcode },
6940     { Bad_Opcode },
6941     { Bad_Opcode },
6942     { Bad_Opcode },
6943     /* 48 */
6944     { Bad_Opcode },
6945     { Bad_Opcode },
6946     { Bad_Opcode },
6947     { Bad_Opcode },
6948     { Bad_Opcode },
6949     { Bad_Opcode },
6950     { Bad_Opcode },
6951     { Bad_Opcode },
6952     /* 50 */
6953     { Bad_Opcode },
6954     { Bad_Opcode },
6955     { Bad_Opcode },
6956     { Bad_Opcode },
6957     { Bad_Opcode },
6958     { Bad_Opcode },
6959     { Bad_Opcode },
6960     { Bad_Opcode },
6961     /* 58 */
6962     { Bad_Opcode },
6963     { Bad_Opcode },
6964     { Bad_Opcode },
6965     { Bad_Opcode },
6966     { Bad_Opcode },
6967     { Bad_Opcode },
6968     { Bad_Opcode },
6969     { Bad_Opcode },
6970     /* 60 */
6971     { Bad_Opcode },
6972     { Bad_Opcode },
6973     { Bad_Opcode },
6974     { Bad_Opcode },
6975     { Bad_Opcode },
6976     { Bad_Opcode },
6977     { Bad_Opcode },
6978     { Bad_Opcode },
6979     /* 68 */
6980     { Bad_Opcode },
6981     { Bad_Opcode },
6982     { Bad_Opcode },
6983     { Bad_Opcode },
6984     { Bad_Opcode },
6985     { Bad_Opcode },
6986     { Bad_Opcode },
6987     { Bad_Opcode },
6988     /* 70 */
6989     { Bad_Opcode },
6990     { Bad_Opcode },
6991     { Bad_Opcode },
6992     { Bad_Opcode },
6993     { Bad_Opcode },
6994     { Bad_Opcode },
6995     { Bad_Opcode },
6996     { Bad_Opcode },
6997     /* 78 */
6998     { Bad_Opcode },
6999     { Bad_Opcode },
7000     { Bad_Opcode },
7001     { Bad_Opcode },
7002     { Bad_Opcode },
7003     { Bad_Opcode },
7004     { Bad_Opcode },
7005     { Bad_Opcode },
7006     /* 80 */
7007     { PREFIX_TABLE (PREFIX_0F3880) },
7008     { PREFIX_TABLE (PREFIX_0F3881) },
7009     { PREFIX_TABLE (PREFIX_0F3882) },
7010     { Bad_Opcode },
7011     { Bad_Opcode },
7012     { Bad_Opcode },
7013     { Bad_Opcode },
7014     { Bad_Opcode },
7015     /* 88 */
7016     { Bad_Opcode },
7017     { Bad_Opcode },
7018     { Bad_Opcode },
7019     { Bad_Opcode },
7020     { Bad_Opcode },
7021     { Bad_Opcode },
7022     { Bad_Opcode },
7023     { Bad_Opcode },
7024     /* 90 */
7025     { Bad_Opcode },
7026     { Bad_Opcode },
7027     { Bad_Opcode },
7028     { Bad_Opcode },
7029     { Bad_Opcode },
7030     { Bad_Opcode },
7031     { Bad_Opcode },
7032     { Bad_Opcode },
7033     /* 98 */
7034     { Bad_Opcode },
7035     { Bad_Opcode },
7036     { Bad_Opcode },
7037     { Bad_Opcode },
7038     { Bad_Opcode },
7039     { Bad_Opcode },
7040     { Bad_Opcode },
7041     { Bad_Opcode },
7042     /* a0 */
7043     { Bad_Opcode },
7044     { Bad_Opcode },
7045     { Bad_Opcode },
7046     { Bad_Opcode },
7047     { Bad_Opcode },
7048     { Bad_Opcode },
7049     { Bad_Opcode },
7050     { Bad_Opcode },
7051     /* a8 */
7052     { Bad_Opcode },
7053     { Bad_Opcode },
7054     { Bad_Opcode },
7055     { Bad_Opcode },
7056     { Bad_Opcode },
7057     { Bad_Opcode },
7058     { Bad_Opcode },
7059     { Bad_Opcode },
7060     /* b0 */
7061     { Bad_Opcode },
7062     { Bad_Opcode },
7063     { Bad_Opcode },
7064     { Bad_Opcode },
7065     { Bad_Opcode },
7066     { Bad_Opcode },
7067     { Bad_Opcode },
7068     { Bad_Opcode },
7069     /* b8 */
7070     { Bad_Opcode },
7071     { Bad_Opcode },
7072     { Bad_Opcode },
7073     { Bad_Opcode },
7074     { Bad_Opcode },
7075     { Bad_Opcode },
7076     { Bad_Opcode },
7077     { Bad_Opcode },
7078     /* c0 */
7079     { Bad_Opcode },
7080     { Bad_Opcode },
7081     { Bad_Opcode },
7082     { Bad_Opcode },
7083     { Bad_Opcode },
7084     { Bad_Opcode },
7085     { Bad_Opcode },
7086     { Bad_Opcode },
7087     /* c8 */
7088     { PREFIX_TABLE (PREFIX_0F38C8) },
7089     { PREFIX_TABLE (PREFIX_0F38C9) },
7090     { PREFIX_TABLE (PREFIX_0F38CA) },
7091     { PREFIX_TABLE (PREFIX_0F38CB) },
7092     { PREFIX_TABLE (PREFIX_0F38CC) },
7093     { PREFIX_TABLE (PREFIX_0F38CD) },
7094     { Bad_Opcode },
7095     { PREFIX_TABLE (PREFIX_0F38CF) },
7096     /* d0 */
7097     { Bad_Opcode },
7098     { Bad_Opcode },
7099     { Bad_Opcode },
7100     { Bad_Opcode },
7101     { Bad_Opcode },
7102     { Bad_Opcode },
7103     { Bad_Opcode },
7104     { Bad_Opcode },
7105     /* d8 */
7106     { Bad_Opcode },
7107     { Bad_Opcode },
7108     { Bad_Opcode },
7109     { PREFIX_TABLE (PREFIX_0F38DB) },
7110     { PREFIX_TABLE (PREFIX_0F38DC) },
7111     { PREFIX_TABLE (PREFIX_0F38DD) },
7112     { PREFIX_TABLE (PREFIX_0F38DE) },
7113     { PREFIX_TABLE (PREFIX_0F38DF) },
7114     /* e0 */
7115     { Bad_Opcode },
7116     { Bad_Opcode },
7117     { Bad_Opcode },
7118     { Bad_Opcode },
7119     { Bad_Opcode },
7120     { Bad_Opcode },
7121     { Bad_Opcode },
7122     { Bad_Opcode },
7123     /* e8 */
7124     { Bad_Opcode },
7125     { Bad_Opcode },
7126     { Bad_Opcode },
7127     { Bad_Opcode },
7128     { Bad_Opcode },
7129     { Bad_Opcode },
7130     { Bad_Opcode },
7131     { Bad_Opcode },
7132     /* f0 */
7133     { PREFIX_TABLE (PREFIX_0F38F0) },
7134     { PREFIX_TABLE (PREFIX_0F38F1) },
7135     { Bad_Opcode },
7136     { Bad_Opcode },
7137     { Bad_Opcode },
7138     { PREFIX_TABLE (PREFIX_0F38F5) },
7139     { PREFIX_TABLE (PREFIX_0F38F6) },
7140     { Bad_Opcode },
7141     /* f8 */
7142     { PREFIX_TABLE (PREFIX_0F38F8) },
7143     { PREFIX_TABLE (PREFIX_0F38F9) },
7144     { Bad_Opcode },
7145     { Bad_Opcode },
7146     { Bad_Opcode },
7147     { Bad_Opcode },
7148     { Bad_Opcode },
7149     { Bad_Opcode },
7150   },
7151   /* THREE_BYTE_0F3A */
7152   {
7153     /* 00 */
7154     { Bad_Opcode },
7155     { Bad_Opcode },
7156     { Bad_Opcode },
7157     { Bad_Opcode },
7158     { Bad_Opcode },
7159     { Bad_Opcode },
7160     { Bad_Opcode },
7161     { Bad_Opcode },
7162     /* 08 */
7163     { PREFIX_TABLE (PREFIX_0F3A08) },
7164     { PREFIX_TABLE (PREFIX_0F3A09) },
7165     { PREFIX_TABLE (PREFIX_0F3A0A) },
7166     { PREFIX_TABLE (PREFIX_0F3A0B) },
7167     { PREFIX_TABLE (PREFIX_0F3A0C) },
7168     { PREFIX_TABLE (PREFIX_0F3A0D) },
7169     { PREFIX_TABLE (PREFIX_0F3A0E) },
7170     { "palignr",        { MX, EM, Ib }, PREFIX_OPCODE },
7171     /* 10 */
7172     { Bad_Opcode },
7173     { Bad_Opcode },
7174     { Bad_Opcode },
7175     { Bad_Opcode },
7176     { PREFIX_TABLE (PREFIX_0F3A14) },
7177     { PREFIX_TABLE (PREFIX_0F3A15) },
7178     { PREFIX_TABLE (PREFIX_0F3A16) },
7179     { PREFIX_TABLE (PREFIX_0F3A17) },
7180     /* 18 */
7181     { Bad_Opcode },
7182     { Bad_Opcode },
7183     { Bad_Opcode },
7184     { Bad_Opcode },
7185     { Bad_Opcode },
7186     { Bad_Opcode },
7187     { Bad_Opcode },
7188     { Bad_Opcode },
7189     /* 20 */
7190     { PREFIX_TABLE (PREFIX_0F3A20) },
7191     { PREFIX_TABLE (PREFIX_0F3A21) },
7192     { PREFIX_TABLE (PREFIX_0F3A22) },
7193     { Bad_Opcode },
7194     { Bad_Opcode },
7195     { Bad_Opcode },
7196     { Bad_Opcode },
7197     { Bad_Opcode },
7198     /* 28 */
7199     { Bad_Opcode },
7200     { Bad_Opcode },
7201     { Bad_Opcode },
7202     { Bad_Opcode },
7203     { Bad_Opcode },
7204     { Bad_Opcode },
7205     { Bad_Opcode },
7206     { Bad_Opcode },
7207     /* 30 */
7208     { Bad_Opcode },
7209     { Bad_Opcode },
7210     { Bad_Opcode },
7211     { Bad_Opcode },
7212     { Bad_Opcode },
7213     { Bad_Opcode },
7214     { Bad_Opcode },
7215     { Bad_Opcode },
7216     /* 38 */
7217     { Bad_Opcode },
7218     { Bad_Opcode },
7219     { Bad_Opcode },
7220     { Bad_Opcode },
7221     { Bad_Opcode },
7222     { Bad_Opcode },
7223     { Bad_Opcode },
7224     { Bad_Opcode },
7225     /* 40 */
7226     { PREFIX_TABLE (PREFIX_0F3A40) },
7227     { PREFIX_TABLE (PREFIX_0F3A41) },
7228     { PREFIX_TABLE (PREFIX_0F3A42) },
7229     { Bad_Opcode },
7230     { PREFIX_TABLE (PREFIX_0F3A44) },
7231     { Bad_Opcode },
7232     { Bad_Opcode },
7233     { Bad_Opcode },
7234     /* 48 */
7235     { Bad_Opcode },
7236     { Bad_Opcode },
7237     { Bad_Opcode },
7238     { Bad_Opcode },
7239     { Bad_Opcode },
7240     { Bad_Opcode },
7241     { Bad_Opcode },
7242     { Bad_Opcode },
7243     /* 50 */
7244     { Bad_Opcode },
7245     { Bad_Opcode },
7246     { Bad_Opcode },
7247     { Bad_Opcode },
7248     { Bad_Opcode },
7249     { Bad_Opcode },
7250     { Bad_Opcode },
7251     { Bad_Opcode },
7252     /* 58 */
7253     { Bad_Opcode },
7254     { Bad_Opcode },
7255     { Bad_Opcode },
7256     { Bad_Opcode },
7257     { Bad_Opcode },
7258     { Bad_Opcode },
7259     { Bad_Opcode },
7260     { Bad_Opcode },
7261     /* 60 */
7262     { PREFIX_TABLE (PREFIX_0F3A60) },
7263     { PREFIX_TABLE (PREFIX_0F3A61) },
7264     { PREFIX_TABLE (PREFIX_0F3A62) },
7265     { PREFIX_TABLE (PREFIX_0F3A63) },
7266     { Bad_Opcode },
7267     { Bad_Opcode },
7268     { Bad_Opcode },
7269     { Bad_Opcode },
7270     /* 68 */
7271     { Bad_Opcode },
7272     { Bad_Opcode },
7273     { Bad_Opcode },
7274     { Bad_Opcode },
7275     { Bad_Opcode },
7276     { Bad_Opcode },
7277     { Bad_Opcode },
7278     { Bad_Opcode },
7279     /* 70 */
7280     { Bad_Opcode },
7281     { Bad_Opcode },
7282     { Bad_Opcode },
7283     { Bad_Opcode },
7284     { Bad_Opcode },
7285     { Bad_Opcode },
7286     { Bad_Opcode },
7287     { Bad_Opcode },
7288     /* 78 */
7289     { Bad_Opcode },
7290     { Bad_Opcode },
7291     { Bad_Opcode },
7292     { Bad_Opcode },
7293     { Bad_Opcode },
7294     { Bad_Opcode },
7295     { Bad_Opcode },
7296     { Bad_Opcode },
7297     /* 80 */
7298     { Bad_Opcode },
7299     { Bad_Opcode },
7300     { Bad_Opcode },
7301     { Bad_Opcode },
7302     { Bad_Opcode },
7303     { Bad_Opcode },
7304     { Bad_Opcode },
7305     { Bad_Opcode },
7306     /* 88 */
7307     { Bad_Opcode },
7308     { Bad_Opcode },
7309     { Bad_Opcode },
7310     { Bad_Opcode },
7311     { Bad_Opcode },
7312     { Bad_Opcode },
7313     { Bad_Opcode },
7314     { Bad_Opcode },
7315     /* 90 */
7316     { Bad_Opcode },
7317     { Bad_Opcode },
7318     { Bad_Opcode },
7319     { Bad_Opcode },
7320     { Bad_Opcode },
7321     { Bad_Opcode },
7322     { Bad_Opcode },
7323     { Bad_Opcode },
7324     /* 98 */
7325     { Bad_Opcode },
7326     { Bad_Opcode },
7327     { Bad_Opcode },
7328     { Bad_Opcode },
7329     { Bad_Opcode },
7330     { Bad_Opcode },
7331     { Bad_Opcode },
7332     { Bad_Opcode },
7333     /* a0 */
7334     { Bad_Opcode },
7335     { Bad_Opcode },
7336     { Bad_Opcode },
7337     { Bad_Opcode },
7338     { Bad_Opcode },
7339     { Bad_Opcode },
7340     { Bad_Opcode },
7341     { Bad_Opcode },
7342     /* a8 */
7343     { Bad_Opcode },
7344     { Bad_Opcode },
7345     { Bad_Opcode },
7346     { Bad_Opcode },
7347     { Bad_Opcode },
7348     { Bad_Opcode },
7349     { Bad_Opcode },
7350     { Bad_Opcode },
7351     /* b0 */
7352     { Bad_Opcode },
7353     { Bad_Opcode },
7354     { Bad_Opcode },
7355     { Bad_Opcode },
7356     { Bad_Opcode },
7357     { Bad_Opcode },
7358     { Bad_Opcode },
7359     { Bad_Opcode },
7360     /* b8 */
7361     { Bad_Opcode },
7362     { Bad_Opcode },
7363     { Bad_Opcode },
7364     { Bad_Opcode },
7365     { Bad_Opcode },
7366     { Bad_Opcode },
7367     { Bad_Opcode },
7368     { Bad_Opcode },
7369     /* c0 */
7370     { Bad_Opcode },
7371     { Bad_Opcode },
7372     { Bad_Opcode },
7373     { Bad_Opcode },
7374     { Bad_Opcode },
7375     { Bad_Opcode },
7376     { Bad_Opcode },
7377     { Bad_Opcode },
7378     /* c8 */
7379     { Bad_Opcode },
7380     { Bad_Opcode },
7381     { Bad_Opcode },
7382     { Bad_Opcode },
7383     { PREFIX_TABLE (PREFIX_0F3ACC) },
7384     { Bad_Opcode },
7385     { PREFIX_TABLE (PREFIX_0F3ACE) },
7386     { PREFIX_TABLE (PREFIX_0F3ACF) },
7387     /* d0 */
7388     { Bad_Opcode },
7389     { Bad_Opcode },
7390     { Bad_Opcode },
7391     { Bad_Opcode },
7392     { Bad_Opcode },
7393     { Bad_Opcode },
7394     { Bad_Opcode },
7395     { Bad_Opcode },
7396     /* d8 */
7397     { Bad_Opcode },
7398     { Bad_Opcode },
7399     { Bad_Opcode },
7400     { Bad_Opcode },
7401     { Bad_Opcode },
7402     { Bad_Opcode },
7403     { Bad_Opcode },
7404     { PREFIX_TABLE (PREFIX_0F3ADF) },
7405     /* e0 */
7406     { Bad_Opcode },
7407     { Bad_Opcode },
7408     { Bad_Opcode },
7409     { Bad_Opcode },
7410     { Bad_Opcode },
7411     { Bad_Opcode },
7412     { Bad_Opcode },
7413     { Bad_Opcode },
7414     /* e8 */
7415     { Bad_Opcode },
7416     { Bad_Opcode },
7417     { Bad_Opcode },
7418     { Bad_Opcode },
7419     { Bad_Opcode },
7420     { Bad_Opcode },
7421     { Bad_Opcode },
7422     { Bad_Opcode },
7423     /* f0 */
7424     { Bad_Opcode },
7425     { Bad_Opcode },
7426     { Bad_Opcode },
7427     { Bad_Opcode },
7428     { Bad_Opcode },
7429     { Bad_Opcode },
7430     { Bad_Opcode },
7431     { Bad_Opcode },
7432     /* f8 */
7433     { Bad_Opcode },
7434     { Bad_Opcode },
7435     { Bad_Opcode },
7436     { Bad_Opcode },
7437     { Bad_Opcode },
7438     { Bad_Opcode },
7439     { Bad_Opcode },
7440     { Bad_Opcode },
7441   },
7442 };
7443
7444 static const struct dis386 xop_table[][256] = {
7445   /* XOP_08 */
7446   {
7447     /* 00 */
7448     { Bad_Opcode },
7449     { Bad_Opcode },
7450     { Bad_Opcode },
7451     { Bad_Opcode },
7452     { Bad_Opcode },
7453     { Bad_Opcode },
7454     { Bad_Opcode },
7455     { Bad_Opcode },
7456     /* 08 */
7457     { Bad_Opcode },
7458     { Bad_Opcode },
7459     { Bad_Opcode },
7460     { Bad_Opcode },
7461     { Bad_Opcode },
7462     { Bad_Opcode },
7463     { Bad_Opcode },
7464     { Bad_Opcode },
7465     /* 10 */
7466     { Bad_Opcode },
7467     { Bad_Opcode },
7468     { Bad_Opcode },
7469     { Bad_Opcode },
7470     { Bad_Opcode },
7471     { Bad_Opcode },
7472     { Bad_Opcode },
7473     { Bad_Opcode },
7474     /* 18 */
7475     { Bad_Opcode },
7476     { Bad_Opcode },
7477     { Bad_Opcode },
7478     { Bad_Opcode },
7479     { Bad_Opcode },
7480     { Bad_Opcode },
7481     { Bad_Opcode },
7482     { Bad_Opcode },
7483     /* 20 */
7484     { Bad_Opcode },
7485     { Bad_Opcode },
7486     { Bad_Opcode },
7487     { Bad_Opcode },
7488     { Bad_Opcode },
7489     { Bad_Opcode },
7490     { Bad_Opcode },
7491     { Bad_Opcode },
7492     /* 28 */
7493     { Bad_Opcode },
7494     { Bad_Opcode },
7495     { Bad_Opcode },
7496     { Bad_Opcode },
7497     { Bad_Opcode },
7498     { Bad_Opcode },
7499     { Bad_Opcode },
7500     { Bad_Opcode },
7501     /* 30 */
7502     { Bad_Opcode },
7503     { Bad_Opcode },
7504     { Bad_Opcode },
7505     { Bad_Opcode },
7506     { Bad_Opcode },
7507     { Bad_Opcode },
7508     { Bad_Opcode },
7509     { Bad_Opcode },
7510     /* 38 */
7511     { Bad_Opcode },
7512     { Bad_Opcode },
7513     { Bad_Opcode },
7514     { Bad_Opcode },
7515     { Bad_Opcode },
7516     { Bad_Opcode },
7517     { Bad_Opcode },
7518     { Bad_Opcode },
7519     /* 40 */
7520     { Bad_Opcode },
7521     { Bad_Opcode },
7522     { Bad_Opcode },
7523     { Bad_Opcode },
7524     { Bad_Opcode },
7525     { Bad_Opcode },
7526     { Bad_Opcode },
7527     { Bad_Opcode },
7528     /* 48 */
7529     { Bad_Opcode },
7530     { Bad_Opcode },
7531     { Bad_Opcode },
7532     { Bad_Opcode },
7533     { Bad_Opcode },
7534     { Bad_Opcode },
7535     { Bad_Opcode },
7536     { Bad_Opcode },
7537     /* 50 */
7538     { Bad_Opcode },
7539     { Bad_Opcode },
7540     { Bad_Opcode },
7541     { Bad_Opcode },
7542     { Bad_Opcode },
7543     { Bad_Opcode },
7544     { Bad_Opcode },
7545     { Bad_Opcode },
7546     /* 58 */
7547     { Bad_Opcode },
7548     { Bad_Opcode },
7549     { Bad_Opcode },
7550     { Bad_Opcode },
7551     { Bad_Opcode },
7552     { Bad_Opcode },
7553     { Bad_Opcode },
7554     { Bad_Opcode },
7555     /* 60 */
7556     { Bad_Opcode },
7557     { Bad_Opcode },
7558     { Bad_Opcode },
7559     { Bad_Opcode },
7560     { Bad_Opcode },
7561     { Bad_Opcode },
7562     { Bad_Opcode },
7563     { Bad_Opcode },
7564     /* 68 */
7565     { Bad_Opcode },
7566     { Bad_Opcode },
7567     { Bad_Opcode },
7568     { Bad_Opcode },
7569     { Bad_Opcode },
7570     { Bad_Opcode },
7571     { Bad_Opcode },
7572     { Bad_Opcode },
7573     /* 70 */
7574     { Bad_Opcode },
7575     { Bad_Opcode },
7576     { Bad_Opcode },
7577     { Bad_Opcode },
7578     { Bad_Opcode },
7579     { Bad_Opcode },
7580     { Bad_Opcode },
7581     { Bad_Opcode },
7582     /* 78 */
7583     { Bad_Opcode },
7584     { Bad_Opcode },
7585     { Bad_Opcode },
7586     { Bad_Opcode },
7587     { Bad_Opcode },
7588     { Bad_Opcode },
7589     { Bad_Opcode },
7590     { Bad_Opcode },
7591     /* 80 */
7592     { Bad_Opcode },
7593     { Bad_Opcode },
7594     { Bad_Opcode },
7595     { Bad_Opcode },
7596     { Bad_Opcode },
7597     { "vpmacssww",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7598     { "vpmacsswd",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7599     { "vpmacssdql",     { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7600     /* 88 */
7601     { Bad_Opcode },
7602     { Bad_Opcode },
7603     { Bad_Opcode },
7604     { Bad_Opcode },
7605     { Bad_Opcode },
7606     { Bad_Opcode },
7607     { "vpmacssdd",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7608     { "vpmacssdqh",     { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7609     /* 90 */
7610     { Bad_Opcode },
7611     { Bad_Opcode },
7612     { Bad_Opcode },
7613     { Bad_Opcode },
7614     { Bad_Opcode },
7615     { "vpmacsww",       { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7616     { "vpmacswd",       { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7617     { "vpmacsdql",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7618     /* 98 */
7619     { Bad_Opcode },
7620     { Bad_Opcode },
7621     { Bad_Opcode },
7622     { Bad_Opcode },
7623     { Bad_Opcode },
7624     { Bad_Opcode },
7625     { "vpmacsdd",       { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7626     { "vpmacsdqh",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7627     /* a0 */
7628     { Bad_Opcode },
7629     { Bad_Opcode },
7630     { "vpcmov",         { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7631     { "vpperm",         { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7632     { Bad_Opcode },
7633     { Bad_Opcode },
7634     { "vpmadcsswd",     { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7635     { Bad_Opcode },
7636     /* a8 */
7637     { Bad_Opcode },
7638     { Bad_Opcode },
7639     { Bad_Opcode },
7640     { Bad_Opcode },
7641     { Bad_Opcode },
7642     { Bad_Opcode },
7643     { Bad_Opcode },
7644     { Bad_Opcode },
7645     /* b0 */
7646     { Bad_Opcode },
7647     { Bad_Opcode },
7648     { Bad_Opcode },
7649     { Bad_Opcode },
7650     { Bad_Opcode },
7651     { Bad_Opcode },
7652     { "vpmadcswd",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7653     { Bad_Opcode },
7654     /* b8 */
7655     { Bad_Opcode },
7656     { Bad_Opcode },
7657     { Bad_Opcode },
7658     { Bad_Opcode },
7659     { Bad_Opcode },
7660     { Bad_Opcode },
7661     { Bad_Opcode },
7662     { Bad_Opcode },
7663     /* c0 */
7664     { "vprotb",         { XM, Vex_2src_1, Ib }, 0 },
7665     { "vprotw",         { XM, Vex_2src_1, Ib }, 0 },
7666     { "vprotd",         { XM, Vex_2src_1, Ib }, 0 },
7667     { "vprotq",         { XM, Vex_2src_1, Ib }, 0 },
7668     { Bad_Opcode },
7669     { Bad_Opcode },
7670     { Bad_Opcode },
7671     { Bad_Opcode },
7672     /* c8 */
7673     { Bad_Opcode },
7674     { Bad_Opcode },
7675     { Bad_Opcode },
7676     { Bad_Opcode },
7677     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
7678     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
7679     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
7680     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
7681     /* d0 */
7682     { Bad_Opcode },
7683     { Bad_Opcode },
7684     { Bad_Opcode },
7685     { Bad_Opcode },
7686     { Bad_Opcode },
7687     { Bad_Opcode },
7688     { Bad_Opcode },
7689     { Bad_Opcode },
7690     /* d8 */
7691     { Bad_Opcode },
7692     { Bad_Opcode },
7693     { Bad_Opcode },
7694     { Bad_Opcode },
7695     { Bad_Opcode },
7696     { Bad_Opcode },
7697     { Bad_Opcode },
7698     { Bad_Opcode },
7699     /* e0 */
7700     { Bad_Opcode },
7701     { Bad_Opcode },
7702     { Bad_Opcode },
7703     { Bad_Opcode },
7704     { Bad_Opcode },
7705     { Bad_Opcode },
7706     { Bad_Opcode },
7707     { Bad_Opcode },
7708     /* e8 */
7709     { Bad_Opcode },
7710     { Bad_Opcode },
7711     { Bad_Opcode },
7712     { Bad_Opcode },
7713     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
7714     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
7715     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
7716     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
7717     /* f0 */
7718     { Bad_Opcode },
7719     { Bad_Opcode },
7720     { Bad_Opcode },
7721     { Bad_Opcode },
7722     { Bad_Opcode },
7723     { Bad_Opcode },
7724     { Bad_Opcode },
7725     { Bad_Opcode },
7726     /* f8 */
7727     { Bad_Opcode },
7728     { Bad_Opcode },
7729     { Bad_Opcode },
7730     { Bad_Opcode },
7731     { Bad_Opcode },
7732     { Bad_Opcode },
7733     { Bad_Opcode },
7734     { Bad_Opcode },
7735   },
7736   /* XOP_09 */
7737   {
7738     /* 00 */
7739     { Bad_Opcode },
7740     { REG_TABLE (REG_XOP_TBM_01) },
7741     { REG_TABLE (REG_XOP_TBM_02) },
7742     { Bad_Opcode },
7743     { Bad_Opcode },
7744     { Bad_Opcode },
7745     { Bad_Opcode },
7746     { Bad_Opcode },
7747     /* 08 */
7748     { Bad_Opcode },
7749     { Bad_Opcode },
7750     { Bad_Opcode },
7751     { Bad_Opcode },
7752     { Bad_Opcode },
7753     { Bad_Opcode },
7754     { Bad_Opcode },
7755     { Bad_Opcode },
7756     /* 10 */
7757     { Bad_Opcode },
7758     { Bad_Opcode },
7759     { REG_TABLE (REG_XOP_LWPCB) },
7760     { Bad_Opcode },
7761     { Bad_Opcode },
7762     { Bad_Opcode },
7763     { Bad_Opcode },
7764     { Bad_Opcode },
7765     /* 18 */
7766     { Bad_Opcode },
7767     { Bad_Opcode },
7768     { Bad_Opcode },
7769     { Bad_Opcode },
7770     { Bad_Opcode },
7771     { Bad_Opcode },
7772     { Bad_Opcode },
7773     { Bad_Opcode },
7774     /* 20 */
7775     { Bad_Opcode },
7776     { Bad_Opcode },
7777     { Bad_Opcode },
7778     { Bad_Opcode },
7779     { Bad_Opcode },
7780     { Bad_Opcode },
7781     { Bad_Opcode },
7782     { Bad_Opcode },
7783     /* 28 */
7784     { Bad_Opcode },
7785     { Bad_Opcode },
7786     { Bad_Opcode },
7787     { Bad_Opcode },
7788     { Bad_Opcode },
7789     { Bad_Opcode },
7790     { Bad_Opcode },
7791     { Bad_Opcode },
7792     /* 30 */
7793     { Bad_Opcode },
7794     { Bad_Opcode },
7795     { Bad_Opcode },
7796     { Bad_Opcode },
7797     { Bad_Opcode },
7798     { Bad_Opcode },
7799     { Bad_Opcode },
7800     { Bad_Opcode },
7801     /* 38 */
7802     { Bad_Opcode },
7803     { Bad_Opcode },
7804     { Bad_Opcode },
7805     { Bad_Opcode },
7806     { Bad_Opcode },
7807     { Bad_Opcode },
7808     { Bad_Opcode },
7809     { Bad_Opcode },
7810     /* 40 */
7811     { Bad_Opcode },
7812     { Bad_Opcode },
7813     { Bad_Opcode },
7814     { Bad_Opcode },
7815     { Bad_Opcode },
7816     { Bad_Opcode },
7817     { Bad_Opcode },
7818     { Bad_Opcode },
7819     /* 48 */
7820     { Bad_Opcode },
7821     { Bad_Opcode },
7822     { Bad_Opcode },
7823     { Bad_Opcode },
7824     { Bad_Opcode },
7825     { Bad_Opcode },
7826     { Bad_Opcode },
7827     { Bad_Opcode },
7828     /* 50 */
7829     { Bad_Opcode },
7830     { Bad_Opcode },
7831     { Bad_Opcode },
7832     { Bad_Opcode },
7833     { Bad_Opcode },
7834     { Bad_Opcode },
7835     { Bad_Opcode },
7836     { Bad_Opcode },
7837     /* 58 */
7838     { Bad_Opcode },
7839     { Bad_Opcode },
7840     { Bad_Opcode },
7841     { Bad_Opcode },
7842     { Bad_Opcode },
7843     { Bad_Opcode },
7844     { Bad_Opcode },
7845     { Bad_Opcode },
7846     /* 60 */
7847     { Bad_Opcode },
7848     { Bad_Opcode },
7849     { Bad_Opcode },
7850     { Bad_Opcode },
7851     { Bad_Opcode },
7852     { Bad_Opcode },
7853     { Bad_Opcode },
7854     { Bad_Opcode },
7855     /* 68 */
7856     { Bad_Opcode },
7857     { Bad_Opcode },
7858     { Bad_Opcode },
7859     { Bad_Opcode },
7860     { Bad_Opcode },
7861     { Bad_Opcode },
7862     { Bad_Opcode },
7863     { Bad_Opcode },
7864     /* 70 */
7865     { Bad_Opcode },
7866     { Bad_Opcode },
7867     { Bad_Opcode },
7868     { Bad_Opcode },
7869     { Bad_Opcode },
7870     { Bad_Opcode },
7871     { Bad_Opcode },
7872     { Bad_Opcode },
7873     /* 78 */
7874     { Bad_Opcode },
7875     { Bad_Opcode },
7876     { Bad_Opcode },
7877     { Bad_Opcode },
7878     { Bad_Opcode },
7879     { Bad_Opcode },
7880     { Bad_Opcode },
7881     { Bad_Opcode },
7882     /* 80 */
7883     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) },
7884     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) },
7885     { "vfrczss",        { XM, EXd }, 0 },
7886     { "vfrczsd",        { XM, EXq }, 0 },
7887     { Bad_Opcode },
7888     { Bad_Opcode },
7889     { Bad_Opcode },
7890     { Bad_Opcode },
7891     /* 88 */
7892     { Bad_Opcode },
7893     { Bad_Opcode },
7894     { Bad_Opcode },
7895     { Bad_Opcode },
7896     { Bad_Opcode },
7897     { Bad_Opcode },
7898     { Bad_Opcode },
7899     { Bad_Opcode },
7900     /* 90 */
7901     { "vprotb",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7902     { "vprotw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7903     { "vprotd",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7904     { "vprotq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7905     { "vpshlb",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7906     { "vpshlw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7907     { "vpshld",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7908     { "vpshlq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7909     /* 98 */
7910     { "vpshab",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7911     { "vpshaw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7912     { "vpshad",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7913     { "vpshaq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7914     { Bad_Opcode },
7915     { Bad_Opcode },
7916     { Bad_Opcode },
7917     { Bad_Opcode },
7918     /* a0 */
7919     { Bad_Opcode },
7920     { Bad_Opcode },
7921     { Bad_Opcode },
7922     { Bad_Opcode },
7923     { Bad_Opcode },
7924     { Bad_Opcode },
7925     { Bad_Opcode },
7926     { Bad_Opcode },
7927     /* a8 */
7928     { Bad_Opcode },
7929     { Bad_Opcode },
7930     { Bad_Opcode },
7931     { Bad_Opcode },
7932     { Bad_Opcode },
7933     { Bad_Opcode },
7934     { Bad_Opcode },
7935     { Bad_Opcode },
7936     /* b0 */
7937     { Bad_Opcode },
7938     { Bad_Opcode },
7939     { Bad_Opcode },
7940     { Bad_Opcode },
7941     { Bad_Opcode },
7942     { Bad_Opcode },
7943     { Bad_Opcode },
7944     { Bad_Opcode },
7945     /* b8 */
7946     { Bad_Opcode },
7947     { Bad_Opcode },
7948     { Bad_Opcode },
7949     { Bad_Opcode },
7950     { Bad_Opcode },
7951     { Bad_Opcode },
7952     { Bad_Opcode },
7953     { Bad_Opcode },
7954     /* c0 */
7955     { Bad_Opcode },
7956     { "vphaddbw",       { XM, EXxmm }, 0 },
7957     { "vphaddbd",       { XM, EXxmm }, 0 },
7958     { "vphaddbq",       { XM, EXxmm }, 0 },
7959     { Bad_Opcode },
7960     { Bad_Opcode },
7961     { "vphaddwd",       { XM, EXxmm }, 0 },
7962     { "vphaddwq",       { XM, EXxmm }, 0 },
7963     /* c8 */
7964     { Bad_Opcode },
7965     { Bad_Opcode },
7966     { Bad_Opcode },
7967     { "vphadddq",       { XM, EXxmm }, 0 },
7968     { Bad_Opcode },
7969     { Bad_Opcode },
7970     { Bad_Opcode },
7971     { Bad_Opcode },
7972     /* d0 */
7973     { Bad_Opcode },
7974     { "vphaddubw",      { XM, EXxmm }, 0 },
7975     { "vphaddubd",      { XM, EXxmm }, 0 },
7976     { "vphaddubq",      { XM, EXxmm }, 0 },
7977     { Bad_Opcode },
7978     { Bad_Opcode },
7979     { "vphadduwd",      { XM, EXxmm }, 0 },
7980     { "vphadduwq",      { XM, EXxmm }, 0 },
7981     /* d8 */
7982     { Bad_Opcode },
7983     { Bad_Opcode },
7984     { Bad_Opcode },
7985     { "vphaddudq",      { XM, EXxmm }, 0 },
7986     { Bad_Opcode },
7987     { Bad_Opcode },
7988     { Bad_Opcode },
7989     { Bad_Opcode },
7990     /* e0 */
7991     { Bad_Opcode },
7992     { "vphsubbw",       { XM, EXxmm }, 0 },
7993     { "vphsubwd",       { XM, EXxmm }, 0 },
7994     { "vphsubdq",       { XM, EXxmm }, 0 },
7995     { Bad_Opcode },
7996     { Bad_Opcode },
7997     { Bad_Opcode },
7998     { Bad_Opcode },
7999     /* e8 */
8000     { Bad_Opcode },
8001     { Bad_Opcode },
8002     { Bad_Opcode },
8003     { Bad_Opcode },
8004     { Bad_Opcode },
8005     { Bad_Opcode },
8006     { Bad_Opcode },
8007     { Bad_Opcode },
8008     /* f0 */
8009     { Bad_Opcode },
8010     { Bad_Opcode },
8011     { Bad_Opcode },
8012     { Bad_Opcode },
8013     { Bad_Opcode },
8014     { Bad_Opcode },
8015     { Bad_Opcode },
8016     { Bad_Opcode },
8017     /* f8 */
8018     { Bad_Opcode },
8019     { Bad_Opcode },
8020     { Bad_Opcode },
8021     { Bad_Opcode },
8022     { Bad_Opcode },
8023     { Bad_Opcode },
8024     { Bad_Opcode },
8025     { Bad_Opcode },
8026   },
8027   /* XOP_0A */
8028   {
8029     /* 00 */
8030     { Bad_Opcode },
8031     { Bad_Opcode },
8032     { Bad_Opcode },
8033     { Bad_Opcode },
8034     { Bad_Opcode },
8035     { Bad_Opcode },
8036     { Bad_Opcode },
8037     { Bad_Opcode },
8038     /* 08 */
8039     { Bad_Opcode },
8040     { Bad_Opcode },
8041     { Bad_Opcode },
8042     { Bad_Opcode },
8043     { Bad_Opcode },
8044     { Bad_Opcode },
8045     { Bad_Opcode },
8046     { Bad_Opcode },
8047     /* 10 */
8048     { "bextrS", { Gdq, Edq, Id }, 0 },
8049     { Bad_Opcode },
8050     { REG_TABLE (REG_XOP_LWP) },
8051     { Bad_Opcode },
8052     { Bad_Opcode },
8053     { Bad_Opcode },
8054     { Bad_Opcode },
8055     { Bad_Opcode },
8056     /* 18 */
8057     { Bad_Opcode },
8058     { Bad_Opcode },
8059     { Bad_Opcode },
8060     { Bad_Opcode },
8061     { Bad_Opcode },
8062     { Bad_Opcode },
8063     { Bad_Opcode },
8064     { Bad_Opcode },
8065     /* 20 */
8066     { Bad_Opcode },
8067     { Bad_Opcode },
8068     { Bad_Opcode },
8069     { Bad_Opcode },
8070     { Bad_Opcode },
8071     { Bad_Opcode },
8072     { Bad_Opcode },
8073     { Bad_Opcode },
8074     /* 28 */
8075     { Bad_Opcode },
8076     { Bad_Opcode },
8077     { Bad_Opcode },
8078     { Bad_Opcode },
8079     { Bad_Opcode },
8080     { Bad_Opcode },
8081     { Bad_Opcode },
8082     { Bad_Opcode },
8083     /* 30 */
8084     { Bad_Opcode },
8085     { Bad_Opcode },
8086     { Bad_Opcode },
8087     { Bad_Opcode },
8088     { Bad_Opcode },
8089     { Bad_Opcode },
8090     { Bad_Opcode },
8091     { Bad_Opcode },
8092     /* 38 */
8093     { Bad_Opcode },
8094     { Bad_Opcode },
8095     { Bad_Opcode },
8096     { Bad_Opcode },
8097     { Bad_Opcode },
8098     { Bad_Opcode },
8099     { Bad_Opcode },
8100     { Bad_Opcode },
8101     /* 40 */
8102     { Bad_Opcode },
8103     { Bad_Opcode },
8104     { Bad_Opcode },
8105     { Bad_Opcode },
8106     { Bad_Opcode },
8107     { Bad_Opcode },
8108     { Bad_Opcode },
8109     { Bad_Opcode },
8110     /* 48 */
8111     { Bad_Opcode },
8112     { Bad_Opcode },
8113     { Bad_Opcode },
8114     { Bad_Opcode },
8115     { Bad_Opcode },
8116     { Bad_Opcode },
8117     { Bad_Opcode },
8118     { Bad_Opcode },
8119     /* 50 */
8120     { Bad_Opcode },
8121     { Bad_Opcode },
8122     { Bad_Opcode },
8123     { Bad_Opcode },
8124     { Bad_Opcode },
8125     { Bad_Opcode },
8126     { Bad_Opcode },
8127     { Bad_Opcode },
8128     /* 58 */
8129     { Bad_Opcode },
8130     { Bad_Opcode },
8131     { Bad_Opcode },
8132     { Bad_Opcode },
8133     { Bad_Opcode },
8134     { Bad_Opcode },
8135     { Bad_Opcode },
8136     { Bad_Opcode },
8137     /* 60 */
8138     { Bad_Opcode },
8139     { Bad_Opcode },
8140     { Bad_Opcode },
8141     { Bad_Opcode },
8142     { Bad_Opcode },
8143     { Bad_Opcode },
8144     { Bad_Opcode },
8145     { Bad_Opcode },
8146     /* 68 */
8147     { Bad_Opcode },
8148     { Bad_Opcode },
8149     { Bad_Opcode },
8150     { Bad_Opcode },
8151     { Bad_Opcode },
8152     { Bad_Opcode },
8153     { Bad_Opcode },
8154     { Bad_Opcode },
8155     /* 70 */
8156     { Bad_Opcode },
8157     { Bad_Opcode },
8158     { Bad_Opcode },
8159     { Bad_Opcode },
8160     { Bad_Opcode },
8161     { Bad_Opcode },
8162     { Bad_Opcode },
8163     { Bad_Opcode },
8164     /* 78 */
8165     { Bad_Opcode },
8166     { Bad_Opcode },
8167     { Bad_Opcode },
8168     { Bad_Opcode },
8169     { Bad_Opcode },
8170     { Bad_Opcode },
8171     { Bad_Opcode },
8172     { Bad_Opcode },
8173     /* 80 */
8174     { Bad_Opcode },
8175     { Bad_Opcode },
8176     { Bad_Opcode },
8177     { Bad_Opcode },
8178     { Bad_Opcode },
8179     { Bad_Opcode },
8180     { Bad_Opcode },
8181     { Bad_Opcode },
8182     /* 88 */
8183     { Bad_Opcode },
8184     { Bad_Opcode },
8185     { Bad_Opcode },
8186     { Bad_Opcode },
8187     { Bad_Opcode },
8188     { Bad_Opcode },
8189     { Bad_Opcode },
8190     { Bad_Opcode },
8191     /* 90 */
8192     { Bad_Opcode },
8193     { Bad_Opcode },
8194     { Bad_Opcode },
8195     { Bad_Opcode },
8196     { Bad_Opcode },
8197     { Bad_Opcode },
8198     { Bad_Opcode },
8199     { Bad_Opcode },
8200     /* 98 */
8201     { Bad_Opcode },
8202     { Bad_Opcode },
8203     { Bad_Opcode },
8204     { Bad_Opcode },
8205     { Bad_Opcode },
8206     { Bad_Opcode },
8207     { Bad_Opcode },
8208     { Bad_Opcode },
8209     /* a0 */
8210     { Bad_Opcode },
8211     { Bad_Opcode },
8212     { Bad_Opcode },
8213     { Bad_Opcode },
8214     { Bad_Opcode },
8215     { Bad_Opcode },
8216     { Bad_Opcode },
8217     { Bad_Opcode },
8218     /* a8 */
8219     { Bad_Opcode },
8220     { Bad_Opcode },
8221     { Bad_Opcode },
8222     { Bad_Opcode },
8223     { Bad_Opcode },
8224     { Bad_Opcode },
8225     { Bad_Opcode },
8226     { Bad_Opcode },
8227     /* b0 */
8228     { Bad_Opcode },
8229     { Bad_Opcode },
8230     { Bad_Opcode },
8231     { Bad_Opcode },
8232     { Bad_Opcode },
8233     { Bad_Opcode },
8234     { Bad_Opcode },
8235     { Bad_Opcode },
8236     /* b8 */
8237     { Bad_Opcode },
8238     { Bad_Opcode },
8239     { Bad_Opcode },
8240     { Bad_Opcode },
8241     { Bad_Opcode },
8242     { Bad_Opcode },
8243     { Bad_Opcode },
8244     { Bad_Opcode },
8245     /* c0 */
8246     { Bad_Opcode },
8247     { Bad_Opcode },
8248     { Bad_Opcode },
8249     { Bad_Opcode },
8250     { Bad_Opcode },
8251     { Bad_Opcode },
8252     { Bad_Opcode },
8253     { Bad_Opcode },
8254     /* c8 */
8255     { Bad_Opcode },
8256     { Bad_Opcode },
8257     { Bad_Opcode },
8258     { Bad_Opcode },
8259     { Bad_Opcode },
8260     { Bad_Opcode },
8261     { Bad_Opcode },
8262     { Bad_Opcode },
8263     /* d0 */
8264     { Bad_Opcode },
8265     { Bad_Opcode },
8266     { Bad_Opcode },
8267     { Bad_Opcode },
8268     { Bad_Opcode },
8269     { Bad_Opcode },
8270     { Bad_Opcode },
8271     { Bad_Opcode },
8272     /* d8 */
8273     { Bad_Opcode },
8274     { Bad_Opcode },
8275     { Bad_Opcode },
8276     { Bad_Opcode },
8277     { Bad_Opcode },
8278     { Bad_Opcode },
8279     { Bad_Opcode },
8280     { Bad_Opcode },
8281     /* e0 */
8282     { Bad_Opcode },
8283     { Bad_Opcode },
8284     { Bad_Opcode },
8285     { Bad_Opcode },
8286     { Bad_Opcode },
8287     { Bad_Opcode },
8288     { Bad_Opcode },
8289     { Bad_Opcode },
8290     /* e8 */
8291     { Bad_Opcode },
8292     { Bad_Opcode },
8293     { Bad_Opcode },
8294     { Bad_Opcode },
8295     { Bad_Opcode },
8296     { Bad_Opcode },
8297     { Bad_Opcode },
8298     { Bad_Opcode },
8299     /* f0 */
8300     { Bad_Opcode },
8301     { Bad_Opcode },
8302     { Bad_Opcode },
8303     { Bad_Opcode },
8304     { Bad_Opcode },
8305     { Bad_Opcode },
8306     { Bad_Opcode },
8307     { Bad_Opcode },
8308     /* f8 */
8309     { Bad_Opcode },
8310     { Bad_Opcode },
8311     { Bad_Opcode },
8312     { Bad_Opcode },
8313     { Bad_Opcode },
8314     { Bad_Opcode },
8315     { Bad_Opcode },
8316     { Bad_Opcode },
8317   },
8318 };
8319
8320 static const struct dis386 vex_table[][256] = {
8321   /* VEX_0F */
8322   {
8323     /* 00 */
8324     { Bad_Opcode },
8325     { Bad_Opcode },
8326     { Bad_Opcode },
8327     { Bad_Opcode },
8328     { Bad_Opcode },
8329     { Bad_Opcode },
8330     { Bad_Opcode },
8331     { Bad_Opcode },
8332     /* 08 */
8333     { Bad_Opcode },
8334     { Bad_Opcode },
8335     { Bad_Opcode },
8336     { Bad_Opcode },
8337     { Bad_Opcode },
8338     { Bad_Opcode },
8339     { Bad_Opcode },
8340     { Bad_Opcode },
8341     /* 10 */
8342     { PREFIX_TABLE (PREFIX_VEX_0F10) },
8343     { PREFIX_TABLE (PREFIX_VEX_0F11) },
8344     { PREFIX_TABLE (PREFIX_VEX_0F12) },
8345     { MOD_TABLE (MOD_VEX_0F13) },
8346     { "vunpcklpX",      { XM, Vex, EXx }, PREFIX_OPCODE },
8347     { "vunpckhpX",      { XM, Vex, EXx }, PREFIX_OPCODE },
8348     { PREFIX_TABLE (PREFIX_VEX_0F16) },
8349     { MOD_TABLE (MOD_VEX_0F17) },
8350     /* 18 */
8351     { Bad_Opcode },
8352     { Bad_Opcode },
8353     { Bad_Opcode },
8354     { Bad_Opcode },
8355     { Bad_Opcode },
8356     { Bad_Opcode },
8357     { Bad_Opcode },
8358     { Bad_Opcode },
8359     /* 20 */
8360     { Bad_Opcode },
8361     { Bad_Opcode },
8362     { Bad_Opcode },
8363     { Bad_Opcode },
8364     { Bad_Opcode },
8365     { Bad_Opcode },
8366     { Bad_Opcode },
8367     { Bad_Opcode },
8368     /* 28 */
8369     { "vmovapX",        { XM, EXx }, PREFIX_OPCODE },
8370     { "vmovapX",        { EXxS, XM }, PREFIX_OPCODE },
8371     { PREFIX_TABLE (PREFIX_VEX_0F2A) },
8372     { MOD_TABLE (MOD_VEX_0F2B) },
8373     { PREFIX_TABLE (PREFIX_VEX_0F2C) },
8374     { PREFIX_TABLE (PREFIX_VEX_0F2D) },
8375     { PREFIX_TABLE (PREFIX_VEX_0F2E) },
8376     { PREFIX_TABLE (PREFIX_VEX_0F2F) },
8377     /* 30 */
8378     { Bad_Opcode },
8379     { Bad_Opcode },
8380     { Bad_Opcode },
8381     { Bad_Opcode },
8382     { Bad_Opcode },
8383     { Bad_Opcode },
8384     { Bad_Opcode },
8385     { Bad_Opcode },
8386     /* 38 */
8387     { Bad_Opcode },
8388     { Bad_Opcode },
8389     { Bad_Opcode },
8390     { Bad_Opcode },
8391     { Bad_Opcode },
8392     { Bad_Opcode },
8393     { Bad_Opcode },
8394     { Bad_Opcode },
8395     /* 40 */
8396     { Bad_Opcode },
8397     { PREFIX_TABLE (PREFIX_VEX_0F41) },
8398     { PREFIX_TABLE (PREFIX_VEX_0F42) },
8399     { Bad_Opcode },
8400     { PREFIX_TABLE (PREFIX_VEX_0F44) },
8401     { PREFIX_TABLE (PREFIX_VEX_0F45) },
8402     { PREFIX_TABLE (PREFIX_VEX_0F46) },
8403     { PREFIX_TABLE (PREFIX_VEX_0F47) },
8404     /* 48 */
8405     { Bad_Opcode },
8406     { Bad_Opcode },
8407     { PREFIX_TABLE (PREFIX_VEX_0F4A) },
8408     { PREFIX_TABLE (PREFIX_VEX_0F4B) },
8409     { Bad_Opcode },
8410     { Bad_Opcode },
8411     { Bad_Opcode },
8412     { Bad_Opcode },
8413     /* 50 */
8414     { MOD_TABLE (MOD_VEX_0F50) },
8415     { PREFIX_TABLE (PREFIX_VEX_0F51) },
8416     { PREFIX_TABLE (PREFIX_VEX_0F52) },
8417     { PREFIX_TABLE (PREFIX_VEX_0F53) },
8418     { "vandpX",         { XM, Vex, EXx }, PREFIX_OPCODE },
8419     { "vandnpX",        { XM, Vex, EXx }, PREFIX_OPCODE },
8420     { "vorpX",          { XM, Vex, EXx }, PREFIX_OPCODE },
8421     { "vxorpX",         { XM, Vex, EXx }, PREFIX_OPCODE },
8422     /* 58 */
8423     { PREFIX_TABLE (PREFIX_VEX_0F58) },
8424     { PREFIX_TABLE (PREFIX_VEX_0F59) },
8425     { PREFIX_TABLE (PREFIX_VEX_0F5A) },
8426     { PREFIX_TABLE (PREFIX_VEX_0F5B) },
8427     { PREFIX_TABLE (PREFIX_VEX_0F5C) },
8428     { PREFIX_TABLE (PREFIX_VEX_0F5D) },
8429     { PREFIX_TABLE (PREFIX_VEX_0F5E) },
8430     { PREFIX_TABLE (PREFIX_VEX_0F5F) },
8431     /* 60 */
8432     { PREFIX_TABLE (PREFIX_VEX_0F60) },
8433     { PREFIX_TABLE (PREFIX_VEX_0F61) },
8434     { PREFIX_TABLE (PREFIX_VEX_0F62) },
8435     { PREFIX_TABLE (PREFIX_VEX_0F63) },
8436     { PREFIX_TABLE (PREFIX_VEX_0F64) },
8437     { PREFIX_TABLE (PREFIX_VEX_0F65) },
8438     { PREFIX_TABLE (PREFIX_VEX_0F66) },
8439     { PREFIX_TABLE (PREFIX_VEX_0F67) },
8440     /* 68 */
8441     { PREFIX_TABLE (PREFIX_VEX_0F68) },
8442     { PREFIX_TABLE (PREFIX_VEX_0F69) },
8443     { PREFIX_TABLE (PREFIX_VEX_0F6A) },
8444     { PREFIX_TABLE (PREFIX_VEX_0F6B) },
8445     { PREFIX_TABLE (PREFIX_VEX_0F6C) },
8446     { PREFIX_TABLE (PREFIX_VEX_0F6D) },
8447     { PREFIX_TABLE (PREFIX_VEX_0F6E) },
8448     { PREFIX_TABLE (PREFIX_VEX_0F6F) },
8449     /* 70 */
8450     { PREFIX_TABLE (PREFIX_VEX_0F70) },
8451     { REG_TABLE (REG_VEX_0F71) },
8452     { REG_TABLE (REG_VEX_0F72) },
8453     { REG_TABLE (REG_VEX_0F73) },
8454     { PREFIX_TABLE (PREFIX_VEX_0F74) },
8455     { PREFIX_TABLE (PREFIX_VEX_0F75) },
8456     { PREFIX_TABLE (PREFIX_VEX_0F76) },
8457     { PREFIX_TABLE (PREFIX_VEX_0F77) },
8458     /* 78 */
8459     { Bad_Opcode },
8460     { Bad_Opcode },
8461     { Bad_Opcode },
8462     { Bad_Opcode },
8463     { PREFIX_TABLE (PREFIX_VEX_0F7C) },
8464     { PREFIX_TABLE (PREFIX_VEX_0F7D) },
8465     { PREFIX_TABLE (PREFIX_VEX_0F7E) },
8466     { PREFIX_TABLE (PREFIX_VEX_0F7F) },
8467     /* 80 */
8468     { Bad_Opcode },
8469     { Bad_Opcode },
8470     { Bad_Opcode },
8471     { Bad_Opcode },
8472     { Bad_Opcode },
8473     { Bad_Opcode },
8474     { Bad_Opcode },
8475     { Bad_Opcode },
8476     /* 88 */
8477     { Bad_Opcode },
8478     { Bad_Opcode },
8479     { Bad_Opcode },
8480     { Bad_Opcode },
8481     { Bad_Opcode },
8482     { Bad_Opcode },
8483     { Bad_Opcode },
8484     { Bad_Opcode },
8485     /* 90 */
8486     { PREFIX_TABLE (PREFIX_VEX_0F90) },
8487     { PREFIX_TABLE (PREFIX_VEX_0F91) },
8488     { PREFIX_TABLE (PREFIX_VEX_0F92) },
8489     { PREFIX_TABLE (PREFIX_VEX_0F93) },
8490     { Bad_Opcode },
8491     { Bad_Opcode },
8492     { Bad_Opcode },
8493     { Bad_Opcode },
8494     /* 98 */
8495     { PREFIX_TABLE (PREFIX_VEX_0F98) },
8496     { PREFIX_TABLE (PREFIX_VEX_0F99) },
8497     { Bad_Opcode },
8498     { Bad_Opcode },
8499     { Bad_Opcode },
8500     { Bad_Opcode },
8501     { Bad_Opcode },
8502     { Bad_Opcode },
8503     /* a0 */
8504     { Bad_Opcode },
8505     { Bad_Opcode },
8506     { Bad_Opcode },
8507     { Bad_Opcode },
8508     { Bad_Opcode },
8509     { Bad_Opcode },
8510     { Bad_Opcode },
8511     { Bad_Opcode },
8512     /* a8 */
8513     { Bad_Opcode },
8514     { Bad_Opcode },
8515     { Bad_Opcode },
8516     { Bad_Opcode },
8517     { Bad_Opcode },
8518     { Bad_Opcode },
8519     { REG_TABLE (REG_VEX_0FAE) },
8520     { Bad_Opcode },
8521     /* b0 */
8522     { Bad_Opcode },
8523     { Bad_Opcode },
8524     { Bad_Opcode },
8525     { Bad_Opcode },
8526     { Bad_Opcode },
8527     { Bad_Opcode },
8528     { Bad_Opcode },
8529     { Bad_Opcode },
8530     /* b8 */
8531     { Bad_Opcode },
8532     { Bad_Opcode },
8533     { Bad_Opcode },
8534     { Bad_Opcode },
8535     { Bad_Opcode },
8536     { Bad_Opcode },
8537     { Bad_Opcode },
8538     { Bad_Opcode },
8539     /* c0 */
8540     { Bad_Opcode },
8541     { Bad_Opcode },
8542     { PREFIX_TABLE (PREFIX_VEX_0FC2) },
8543     { Bad_Opcode },
8544     { PREFIX_TABLE (PREFIX_VEX_0FC4) },
8545     { PREFIX_TABLE (PREFIX_VEX_0FC5) },
8546     { "vshufpX",        { XM, Vex, EXx, Ib }, PREFIX_OPCODE },
8547     { Bad_Opcode },
8548     /* c8 */
8549     { Bad_Opcode },
8550     { Bad_Opcode },
8551     { Bad_Opcode },
8552     { Bad_Opcode },
8553     { Bad_Opcode },
8554     { Bad_Opcode },
8555     { Bad_Opcode },
8556     { Bad_Opcode },
8557     /* d0 */
8558     { PREFIX_TABLE (PREFIX_VEX_0FD0) },
8559     { PREFIX_TABLE (PREFIX_VEX_0FD1) },
8560     { PREFIX_TABLE (PREFIX_VEX_0FD2) },
8561     { PREFIX_TABLE (PREFIX_VEX_0FD3) },
8562     { PREFIX_TABLE (PREFIX_VEX_0FD4) },
8563     { PREFIX_TABLE (PREFIX_VEX_0FD5) },
8564     { PREFIX_TABLE (PREFIX_VEX_0FD6) },
8565     { PREFIX_TABLE (PREFIX_VEX_0FD7) },
8566     /* d8 */
8567     { PREFIX_TABLE (PREFIX_VEX_0FD8) },
8568     { PREFIX_TABLE (PREFIX_VEX_0FD9) },
8569     { PREFIX_TABLE (PREFIX_VEX_0FDA) },
8570     { PREFIX_TABLE (PREFIX_VEX_0FDB) },
8571     { PREFIX_TABLE (PREFIX_VEX_0FDC) },
8572     { PREFIX_TABLE (PREFIX_VEX_0FDD) },
8573     { PREFIX_TABLE (PREFIX_VEX_0FDE) },
8574     { PREFIX_TABLE (PREFIX_VEX_0FDF) },
8575     /* e0 */
8576     { PREFIX_TABLE (PREFIX_VEX_0FE0) },
8577     { PREFIX_TABLE (PREFIX_VEX_0FE1) },
8578     { PREFIX_TABLE (PREFIX_VEX_0FE2) },
8579     { PREFIX_TABLE (PREFIX_VEX_0FE3) },
8580     { PREFIX_TABLE (PREFIX_VEX_0FE4) },
8581     { PREFIX_TABLE (PREFIX_VEX_0FE5) },
8582     { PREFIX_TABLE (PREFIX_VEX_0FE6) },
8583     { PREFIX_TABLE (PREFIX_VEX_0FE7) },
8584     /* e8 */
8585     { PREFIX_TABLE (PREFIX_VEX_0FE8) },
8586     { PREFIX_TABLE (PREFIX_VEX_0FE9) },
8587     { PREFIX_TABLE (PREFIX_VEX_0FEA) },
8588     { PREFIX_TABLE (PREFIX_VEX_0FEB) },
8589     { PREFIX_TABLE (PREFIX_VEX_0FEC) },
8590     { PREFIX_TABLE (PREFIX_VEX_0FED) },
8591     { PREFIX_TABLE (PREFIX_VEX_0FEE) },
8592     { PREFIX_TABLE (PREFIX_VEX_0FEF) },
8593     /* f0 */
8594     { PREFIX_TABLE (PREFIX_VEX_0FF0) },
8595     { PREFIX_TABLE (PREFIX_VEX_0FF1) },
8596     { PREFIX_TABLE (PREFIX_VEX_0FF2) },
8597     { PREFIX_TABLE (PREFIX_VEX_0FF3) },
8598     { PREFIX_TABLE (PREFIX_VEX_0FF4) },
8599     { PREFIX_TABLE (PREFIX_VEX_0FF5) },
8600     { PREFIX_TABLE (PREFIX_VEX_0FF6) },
8601     { PREFIX_TABLE (PREFIX_VEX_0FF7) },
8602     /* f8 */
8603     { PREFIX_TABLE (PREFIX_VEX_0FF8) },
8604     { PREFIX_TABLE (PREFIX_VEX_0FF9) },
8605     { PREFIX_TABLE (PREFIX_VEX_0FFA) },
8606     { PREFIX_TABLE (PREFIX_VEX_0FFB) },
8607     { PREFIX_TABLE (PREFIX_VEX_0FFC) },
8608     { PREFIX_TABLE (PREFIX_VEX_0FFD) },
8609     { PREFIX_TABLE (PREFIX_VEX_0FFE) },
8610     { Bad_Opcode },
8611   },
8612   /* VEX_0F38 */
8613   {
8614     /* 00 */
8615     { PREFIX_TABLE (PREFIX_VEX_0F3800) },
8616     { PREFIX_TABLE (PREFIX_VEX_0F3801) },
8617     { PREFIX_TABLE (PREFIX_VEX_0F3802) },
8618     { PREFIX_TABLE (PREFIX_VEX_0F3803) },
8619     { PREFIX_TABLE (PREFIX_VEX_0F3804) },
8620     { PREFIX_TABLE (PREFIX_VEX_0F3805) },
8621     { PREFIX_TABLE (PREFIX_VEX_0F3806) },
8622     { PREFIX_TABLE (PREFIX_VEX_0F3807) },
8623     /* 08 */
8624     { PREFIX_TABLE (PREFIX_VEX_0F3808) },
8625     { PREFIX_TABLE (PREFIX_VEX_0F3809) },
8626     { PREFIX_TABLE (PREFIX_VEX_0F380A) },
8627     { PREFIX_TABLE (PREFIX_VEX_0F380B) },
8628     { PREFIX_TABLE (PREFIX_VEX_0F380C) },
8629     { PREFIX_TABLE (PREFIX_VEX_0F380D) },
8630     { PREFIX_TABLE (PREFIX_VEX_0F380E) },
8631     { PREFIX_TABLE (PREFIX_VEX_0F380F) },
8632     /* 10 */
8633     { Bad_Opcode },
8634     { Bad_Opcode },
8635     { Bad_Opcode },
8636     { PREFIX_TABLE (PREFIX_VEX_0F3813) },
8637     { Bad_Opcode },
8638     { Bad_Opcode },
8639     { PREFIX_TABLE (PREFIX_VEX_0F3816) },
8640     { PREFIX_TABLE (PREFIX_VEX_0F3817) },
8641     /* 18 */
8642     { PREFIX_TABLE (PREFIX_VEX_0F3818) },
8643     { PREFIX_TABLE (PREFIX_VEX_0F3819) },
8644     { PREFIX_TABLE (PREFIX_VEX_0F381A) },
8645     { Bad_Opcode },
8646     { PREFIX_TABLE (PREFIX_VEX_0F381C) },
8647     { PREFIX_TABLE (PREFIX_VEX_0F381D) },
8648     { PREFIX_TABLE (PREFIX_VEX_0F381E) },
8649     { Bad_Opcode },
8650     /* 20 */
8651     { PREFIX_TABLE (PREFIX_VEX_0F3820) },
8652     { PREFIX_TABLE (PREFIX_VEX_0F3821) },
8653     { PREFIX_TABLE (PREFIX_VEX_0F3822) },
8654     { PREFIX_TABLE (PREFIX_VEX_0F3823) },
8655     { PREFIX_TABLE (PREFIX_VEX_0F3824) },
8656     { PREFIX_TABLE (PREFIX_VEX_0F3825) },
8657     { Bad_Opcode },
8658     { Bad_Opcode },
8659     /* 28 */
8660     { PREFIX_TABLE (PREFIX_VEX_0F3828) },
8661     { PREFIX_TABLE (PREFIX_VEX_0F3829) },
8662     { PREFIX_TABLE (PREFIX_VEX_0F382A) },
8663     { PREFIX_TABLE (PREFIX_VEX_0F382B) },
8664     { PREFIX_TABLE (PREFIX_VEX_0F382C) },
8665     { PREFIX_TABLE (PREFIX_VEX_0F382D) },
8666     { PREFIX_TABLE (PREFIX_VEX_0F382E) },
8667     { PREFIX_TABLE (PREFIX_VEX_0F382F) },
8668     /* 30 */
8669     { PREFIX_TABLE (PREFIX_VEX_0F3830) },
8670     { PREFIX_TABLE (PREFIX_VEX_0F3831) },
8671     { PREFIX_TABLE (PREFIX_VEX_0F3832) },
8672     { PREFIX_TABLE (PREFIX_VEX_0F3833) },
8673     { PREFIX_TABLE (PREFIX_VEX_0F3834) },
8674     { PREFIX_TABLE (PREFIX_VEX_0F3835) },
8675     { PREFIX_TABLE (PREFIX_VEX_0F3836) },
8676     { PREFIX_TABLE (PREFIX_VEX_0F3837) },
8677     /* 38 */
8678     { PREFIX_TABLE (PREFIX_VEX_0F3838) },
8679     { PREFIX_TABLE (PREFIX_VEX_0F3839) },
8680     { PREFIX_TABLE (PREFIX_VEX_0F383A) },
8681     { PREFIX_TABLE (PREFIX_VEX_0F383B) },
8682     { PREFIX_TABLE (PREFIX_VEX_0F383C) },
8683     { PREFIX_TABLE (PREFIX_VEX_0F383D) },
8684     { PREFIX_TABLE (PREFIX_VEX_0F383E) },
8685     { PREFIX_TABLE (PREFIX_VEX_0F383F) },
8686     /* 40 */
8687     { PREFIX_TABLE (PREFIX_VEX_0F3840) },
8688     { PREFIX_TABLE (PREFIX_VEX_0F3841) },
8689     { Bad_Opcode },
8690     { Bad_Opcode },
8691     { Bad_Opcode },
8692     { PREFIX_TABLE (PREFIX_VEX_0F3845) },
8693     { PREFIX_TABLE (PREFIX_VEX_0F3846) },
8694     { PREFIX_TABLE (PREFIX_VEX_0F3847) },
8695     /* 48 */
8696     { Bad_Opcode },
8697     { Bad_Opcode },
8698     { Bad_Opcode },
8699     { Bad_Opcode },
8700     { Bad_Opcode },
8701     { Bad_Opcode },
8702     { Bad_Opcode },
8703     { Bad_Opcode },
8704     /* 50 */
8705     { Bad_Opcode },
8706     { Bad_Opcode },
8707     { Bad_Opcode },
8708     { Bad_Opcode },
8709     { Bad_Opcode },
8710     { Bad_Opcode },
8711     { Bad_Opcode },
8712     { Bad_Opcode },
8713     /* 58 */
8714     { PREFIX_TABLE (PREFIX_VEX_0F3858) },
8715     { PREFIX_TABLE (PREFIX_VEX_0F3859) },
8716     { PREFIX_TABLE (PREFIX_VEX_0F385A) },
8717     { Bad_Opcode },
8718     { Bad_Opcode },
8719     { Bad_Opcode },
8720     { Bad_Opcode },
8721     { Bad_Opcode },
8722     /* 60 */
8723     { Bad_Opcode },
8724     { Bad_Opcode },
8725     { Bad_Opcode },
8726     { Bad_Opcode },
8727     { Bad_Opcode },
8728     { Bad_Opcode },
8729     { Bad_Opcode },
8730     { Bad_Opcode },
8731     /* 68 */
8732     { Bad_Opcode },
8733     { Bad_Opcode },
8734     { Bad_Opcode },
8735     { Bad_Opcode },
8736     { Bad_Opcode },
8737     { Bad_Opcode },
8738     { Bad_Opcode },
8739     { Bad_Opcode },
8740     /* 70 */
8741     { Bad_Opcode },
8742     { Bad_Opcode },
8743     { Bad_Opcode },
8744     { Bad_Opcode },
8745     { Bad_Opcode },
8746     { Bad_Opcode },
8747     { Bad_Opcode },
8748     { Bad_Opcode },
8749     /* 78 */
8750     { PREFIX_TABLE (PREFIX_VEX_0F3878) },
8751     { PREFIX_TABLE (PREFIX_VEX_0F3879) },
8752     { Bad_Opcode },
8753     { Bad_Opcode },
8754     { Bad_Opcode },
8755     { Bad_Opcode },
8756     { Bad_Opcode },
8757     { Bad_Opcode },
8758     /* 80 */
8759     { Bad_Opcode },
8760     { Bad_Opcode },
8761     { Bad_Opcode },
8762     { Bad_Opcode },
8763     { Bad_Opcode },
8764     { Bad_Opcode },
8765     { Bad_Opcode },
8766     { Bad_Opcode },
8767     /* 88 */
8768     { Bad_Opcode },
8769     { Bad_Opcode },
8770     { Bad_Opcode },
8771     { Bad_Opcode },
8772     { PREFIX_TABLE (PREFIX_VEX_0F388C) },
8773     { Bad_Opcode },
8774     { PREFIX_TABLE (PREFIX_VEX_0F388E) },
8775     { Bad_Opcode },
8776     /* 90 */
8777     { PREFIX_TABLE (PREFIX_VEX_0F3890) },
8778     { PREFIX_TABLE (PREFIX_VEX_0F3891) },
8779     { PREFIX_TABLE (PREFIX_VEX_0F3892) },
8780     { PREFIX_TABLE (PREFIX_VEX_0F3893) },
8781     { Bad_Opcode },
8782     { Bad_Opcode },
8783     { PREFIX_TABLE (PREFIX_VEX_0F3896) },
8784     { PREFIX_TABLE (PREFIX_VEX_0F3897) },
8785     /* 98 */
8786     { PREFIX_TABLE (PREFIX_VEX_0F3898) },
8787     { PREFIX_TABLE (PREFIX_VEX_0F3899) },
8788     { PREFIX_TABLE (PREFIX_VEX_0F389A) },
8789     { PREFIX_TABLE (PREFIX_VEX_0F389B) },
8790     { PREFIX_TABLE (PREFIX_VEX_0F389C) },
8791     { PREFIX_TABLE (PREFIX_VEX_0F389D) },
8792     { PREFIX_TABLE (PREFIX_VEX_0F389E) },
8793     { PREFIX_TABLE (PREFIX_VEX_0F389F) },
8794     /* a0 */
8795     { Bad_Opcode },
8796     { Bad_Opcode },
8797     { Bad_Opcode },
8798     { Bad_Opcode },
8799     { Bad_Opcode },
8800     { Bad_Opcode },
8801     { PREFIX_TABLE (PREFIX_VEX_0F38A6) },
8802     { PREFIX_TABLE (PREFIX_VEX_0F38A7) },
8803     /* a8 */
8804     { PREFIX_TABLE (PREFIX_VEX_0F38A8) },
8805     { PREFIX_TABLE (PREFIX_VEX_0F38A9) },
8806     { PREFIX_TABLE (PREFIX_VEX_0F38AA) },
8807     { PREFIX_TABLE (PREFIX_VEX_0F38AB) },
8808     { PREFIX_TABLE (PREFIX_VEX_0F38AC) },
8809     { PREFIX_TABLE (PREFIX_VEX_0F38AD) },
8810     { PREFIX_TABLE (PREFIX_VEX_0F38AE) },
8811     { PREFIX_TABLE (PREFIX_VEX_0F38AF) },
8812     /* b0 */
8813     { Bad_Opcode },
8814     { Bad_Opcode },
8815     { Bad_Opcode },
8816     { Bad_Opcode },
8817     { Bad_Opcode },
8818     { Bad_Opcode },
8819     { PREFIX_TABLE (PREFIX_VEX_0F38B6) },
8820     { PREFIX_TABLE (PREFIX_VEX_0F38B7) },
8821     /* b8 */
8822     { PREFIX_TABLE (PREFIX_VEX_0F38B8) },
8823     { PREFIX_TABLE (PREFIX_VEX_0F38B9) },
8824     { PREFIX_TABLE (PREFIX_VEX_0F38BA) },
8825     { PREFIX_TABLE (PREFIX_VEX_0F38BB) },
8826     { PREFIX_TABLE (PREFIX_VEX_0F38BC) },
8827     { PREFIX_TABLE (PREFIX_VEX_0F38BD) },
8828     { PREFIX_TABLE (PREFIX_VEX_0F38BE) },
8829     { PREFIX_TABLE (PREFIX_VEX_0F38BF) },
8830     /* c0 */
8831     { Bad_Opcode },
8832     { Bad_Opcode },
8833     { Bad_Opcode },
8834     { Bad_Opcode },
8835     { Bad_Opcode },
8836     { Bad_Opcode },
8837     { Bad_Opcode },
8838     { Bad_Opcode },
8839     /* c8 */
8840     { Bad_Opcode },
8841     { Bad_Opcode },
8842     { Bad_Opcode },
8843     { Bad_Opcode },
8844     { Bad_Opcode },
8845     { Bad_Opcode },
8846     { Bad_Opcode },
8847     { PREFIX_TABLE (PREFIX_VEX_0F38CF) },
8848     /* d0 */
8849     { Bad_Opcode },
8850     { Bad_Opcode },
8851     { Bad_Opcode },
8852     { Bad_Opcode },
8853     { Bad_Opcode },
8854     { Bad_Opcode },
8855     { Bad_Opcode },
8856     { Bad_Opcode },
8857     /* d8 */
8858     { Bad_Opcode },
8859     { Bad_Opcode },
8860     { Bad_Opcode },
8861     { PREFIX_TABLE (PREFIX_VEX_0F38DB) },
8862     { PREFIX_TABLE (PREFIX_VEX_0F38DC) },
8863     { PREFIX_TABLE (PREFIX_VEX_0F38DD) },
8864     { PREFIX_TABLE (PREFIX_VEX_0F38DE) },
8865     { PREFIX_TABLE (PREFIX_VEX_0F38DF) },
8866     /* e0 */
8867     { Bad_Opcode },
8868     { Bad_Opcode },
8869     { Bad_Opcode },
8870     { Bad_Opcode },
8871     { Bad_Opcode },
8872     { Bad_Opcode },
8873     { Bad_Opcode },
8874     { Bad_Opcode },
8875     /* e8 */
8876     { Bad_Opcode },
8877     { Bad_Opcode },
8878     { Bad_Opcode },
8879     { Bad_Opcode },
8880     { Bad_Opcode },
8881     { Bad_Opcode },
8882     { Bad_Opcode },
8883     { Bad_Opcode },
8884     /* f0 */
8885     { Bad_Opcode },
8886     { Bad_Opcode },
8887     { PREFIX_TABLE (PREFIX_VEX_0F38F2) },
8888     { REG_TABLE (REG_VEX_0F38F3) },
8889     { Bad_Opcode },
8890     { PREFIX_TABLE (PREFIX_VEX_0F38F5) },
8891     { PREFIX_TABLE (PREFIX_VEX_0F38F6) },
8892     { PREFIX_TABLE (PREFIX_VEX_0F38F7) },
8893     /* f8 */
8894     { Bad_Opcode },
8895     { Bad_Opcode },
8896     { Bad_Opcode },
8897     { Bad_Opcode },
8898     { Bad_Opcode },
8899     { Bad_Opcode },
8900     { Bad_Opcode },
8901     { Bad_Opcode },
8902   },
8903   /* VEX_0F3A */
8904   {
8905     /* 00 */
8906     { PREFIX_TABLE (PREFIX_VEX_0F3A00) },
8907     { PREFIX_TABLE (PREFIX_VEX_0F3A01) },
8908     { PREFIX_TABLE (PREFIX_VEX_0F3A02) },
8909     { Bad_Opcode },
8910     { PREFIX_TABLE (PREFIX_VEX_0F3A04) },
8911     { PREFIX_TABLE (PREFIX_VEX_0F3A05) },
8912     { PREFIX_TABLE (PREFIX_VEX_0F3A06) },
8913     { Bad_Opcode },
8914     /* 08 */
8915     { PREFIX_TABLE (PREFIX_VEX_0F3A08) },
8916     { PREFIX_TABLE (PREFIX_VEX_0F3A09) },
8917     { PREFIX_TABLE (PREFIX_VEX_0F3A0A) },
8918     { PREFIX_TABLE (PREFIX_VEX_0F3A0B) },
8919     { PREFIX_TABLE (PREFIX_VEX_0F3A0C) },
8920     { PREFIX_TABLE (PREFIX_VEX_0F3A0D) },
8921     { PREFIX_TABLE (PREFIX_VEX_0F3A0E) },
8922     { PREFIX_TABLE (PREFIX_VEX_0F3A0F) },
8923     /* 10 */
8924     { Bad_Opcode },
8925     { Bad_Opcode },
8926     { Bad_Opcode },
8927     { Bad_Opcode },
8928     { PREFIX_TABLE (PREFIX_VEX_0F3A14) },
8929     { PREFIX_TABLE (PREFIX_VEX_0F3A15) },
8930     { PREFIX_TABLE (PREFIX_VEX_0F3A16) },
8931     { PREFIX_TABLE (PREFIX_VEX_0F3A17) },
8932     /* 18 */
8933     { PREFIX_TABLE (PREFIX_VEX_0F3A18) },
8934     { PREFIX_TABLE (PREFIX_VEX_0F3A19) },
8935     { Bad_Opcode },
8936     { Bad_Opcode },
8937     { Bad_Opcode },
8938     { PREFIX_TABLE (PREFIX_VEX_0F3A1D) },
8939     { Bad_Opcode },
8940     { Bad_Opcode },
8941     /* 20 */
8942     { PREFIX_TABLE (PREFIX_VEX_0F3A20) },
8943     { PREFIX_TABLE (PREFIX_VEX_0F3A21) },
8944     { PREFIX_TABLE (PREFIX_VEX_0F3A22) },
8945     { Bad_Opcode },
8946     { Bad_Opcode },
8947     { Bad_Opcode },
8948     { Bad_Opcode },
8949     { Bad_Opcode },
8950     /* 28 */
8951     { Bad_Opcode },
8952     { Bad_Opcode },
8953     { Bad_Opcode },
8954     { Bad_Opcode },
8955     { Bad_Opcode },
8956     { Bad_Opcode },
8957     { Bad_Opcode },
8958     { Bad_Opcode },
8959     /* 30 */
8960     { PREFIX_TABLE (PREFIX_VEX_0F3A30) },
8961     { PREFIX_TABLE (PREFIX_VEX_0F3A31) },
8962     { PREFIX_TABLE (PREFIX_VEX_0F3A32) },
8963     { PREFIX_TABLE (PREFIX_VEX_0F3A33) },
8964     { Bad_Opcode },
8965     { Bad_Opcode },
8966     { Bad_Opcode },
8967     { Bad_Opcode },
8968     /* 38 */
8969     { PREFIX_TABLE (PREFIX_VEX_0F3A38) },
8970     { PREFIX_TABLE (PREFIX_VEX_0F3A39) },
8971     { Bad_Opcode },
8972     { Bad_Opcode },
8973     { Bad_Opcode },
8974     { Bad_Opcode },
8975     { Bad_Opcode },
8976     { Bad_Opcode },
8977     /* 40 */
8978     { PREFIX_TABLE (PREFIX_VEX_0F3A40) },
8979     { PREFIX_TABLE (PREFIX_VEX_0F3A41) },
8980     { PREFIX_TABLE (PREFIX_VEX_0F3A42) },
8981     { Bad_Opcode },
8982     { PREFIX_TABLE (PREFIX_VEX_0F3A44) },
8983     { Bad_Opcode },
8984     { PREFIX_TABLE (PREFIX_VEX_0F3A46) },
8985     { Bad_Opcode },
8986     /* 48 */
8987     { PREFIX_TABLE (PREFIX_VEX_0F3A48) },
8988     { PREFIX_TABLE (PREFIX_VEX_0F3A49) },
8989     { PREFIX_TABLE (PREFIX_VEX_0F3A4A) },
8990     { PREFIX_TABLE (PREFIX_VEX_0F3A4B) },
8991     { PREFIX_TABLE (PREFIX_VEX_0F3A4C) },
8992     { Bad_Opcode },
8993     { Bad_Opcode },
8994     { Bad_Opcode },
8995     /* 50 */
8996     { Bad_Opcode },
8997     { Bad_Opcode },
8998     { Bad_Opcode },
8999     { Bad_Opcode },
9000     { Bad_Opcode },
9001     { Bad_Opcode },
9002     { Bad_Opcode },
9003     { Bad_Opcode },
9004     /* 58 */
9005     { Bad_Opcode },
9006     { Bad_Opcode },
9007     { Bad_Opcode },
9008     { Bad_Opcode },
9009     { PREFIX_TABLE (PREFIX_VEX_0F3A5C) },
9010     { PREFIX_TABLE (PREFIX_VEX_0F3A5D) },
9011     { PREFIX_TABLE (PREFIX_VEX_0F3A5E) },
9012     { PREFIX_TABLE (PREFIX_VEX_0F3A5F) },
9013     /* 60 */
9014     { PREFIX_TABLE (PREFIX_VEX_0F3A60) },
9015     { PREFIX_TABLE (PREFIX_VEX_0F3A61) },
9016     { PREFIX_TABLE (PREFIX_VEX_0F3A62) },
9017     { PREFIX_TABLE (PREFIX_VEX_0F3A63) },
9018     { Bad_Opcode },
9019     { Bad_Opcode },
9020     { Bad_Opcode },
9021     { Bad_Opcode },
9022     /* 68 */
9023     { PREFIX_TABLE (PREFIX_VEX_0F3A68) },
9024     { PREFIX_TABLE (PREFIX_VEX_0F3A69) },
9025     { PREFIX_TABLE (PREFIX_VEX_0F3A6A) },
9026     { PREFIX_TABLE (PREFIX_VEX_0F3A6B) },
9027     { PREFIX_TABLE (PREFIX_VEX_0F3A6C) },
9028     { PREFIX_TABLE (PREFIX_VEX_0F3A6D) },
9029     { PREFIX_TABLE (PREFIX_VEX_0F3A6E) },
9030     { PREFIX_TABLE (PREFIX_VEX_0F3A6F) },
9031     /* 70 */
9032     { Bad_Opcode },
9033     { Bad_Opcode },
9034     { Bad_Opcode },
9035     { Bad_Opcode },
9036     { Bad_Opcode },
9037     { Bad_Opcode },
9038     { Bad_Opcode },
9039     { Bad_Opcode },
9040     /* 78 */
9041     { PREFIX_TABLE (PREFIX_VEX_0F3A78) },
9042     { PREFIX_TABLE (PREFIX_VEX_0F3A79) },
9043     { PREFIX_TABLE (PREFIX_VEX_0F3A7A) },
9044     { PREFIX_TABLE (PREFIX_VEX_0F3A7B) },
9045     { PREFIX_TABLE (PREFIX_VEX_0F3A7C) },
9046     { PREFIX_TABLE (PREFIX_VEX_0F3A7D) },
9047     { PREFIX_TABLE (PREFIX_VEX_0F3A7E) },
9048     { PREFIX_TABLE (PREFIX_VEX_0F3A7F) },
9049     /* 80 */
9050     { Bad_Opcode },
9051     { Bad_Opcode },
9052     { Bad_Opcode },
9053     { Bad_Opcode },
9054     { Bad_Opcode },
9055     { Bad_Opcode },
9056     { Bad_Opcode },
9057     { Bad_Opcode },
9058     /* 88 */
9059     { Bad_Opcode },
9060     { Bad_Opcode },
9061     { Bad_Opcode },
9062     { Bad_Opcode },
9063     { Bad_Opcode },
9064     { Bad_Opcode },
9065     { Bad_Opcode },
9066     { Bad_Opcode },
9067     /* 90 */
9068     { Bad_Opcode },
9069     { Bad_Opcode },
9070     { Bad_Opcode },
9071     { Bad_Opcode },
9072     { Bad_Opcode },
9073     { Bad_Opcode },
9074     { Bad_Opcode },
9075     { Bad_Opcode },
9076     /* 98 */
9077     { Bad_Opcode },
9078     { Bad_Opcode },
9079     { Bad_Opcode },
9080     { Bad_Opcode },
9081     { Bad_Opcode },
9082     { Bad_Opcode },
9083     { Bad_Opcode },
9084     { Bad_Opcode },
9085     /* a0 */
9086     { Bad_Opcode },
9087     { Bad_Opcode },
9088     { Bad_Opcode },
9089     { Bad_Opcode },
9090     { Bad_Opcode },
9091     { Bad_Opcode },
9092     { Bad_Opcode },
9093     { Bad_Opcode },
9094     /* a8 */
9095     { Bad_Opcode },
9096     { Bad_Opcode },
9097     { Bad_Opcode },
9098     { Bad_Opcode },
9099     { Bad_Opcode },
9100     { Bad_Opcode },
9101     { Bad_Opcode },
9102     { Bad_Opcode },
9103     /* b0 */
9104     { Bad_Opcode },
9105     { Bad_Opcode },
9106     { Bad_Opcode },
9107     { Bad_Opcode },
9108     { Bad_Opcode },
9109     { Bad_Opcode },
9110     { Bad_Opcode },
9111     { Bad_Opcode },
9112     /* b8 */
9113     { Bad_Opcode },
9114     { Bad_Opcode },
9115     { Bad_Opcode },
9116     { Bad_Opcode },
9117     { Bad_Opcode },
9118     { Bad_Opcode },
9119     { Bad_Opcode },
9120     { Bad_Opcode },
9121     /* c0 */
9122     { Bad_Opcode },
9123     { Bad_Opcode },
9124     { Bad_Opcode },
9125     { Bad_Opcode },
9126     { Bad_Opcode },
9127     { Bad_Opcode },
9128     { Bad_Opcode },
9129     { Bad_Opcode },
9130     /* c8 */
9131     { Bad_Opcode },
9132     { Bad_Opcode },
9133     { Bad_Opcode },
9134     { Bad_Opcode },
9135     { Bad_Opcode },
9136     { Bad_Opcode },
9137     { PREFIX_TABLE(PREFIX_VEX_0F3ACE) },
9138     { PREFIX_TABLE(PREFIX_VEX_0F3ACF) },
9139     /* d0 */
9140     { Bad_Opcode },
9141     { Bad_Opcode },
9142     { Bad_Opcode },
9143     { Bad_Opcode },
9144     { Bad_Opcode },
9145     { Bad_Opcode },
9146     { Bad_Opcode },
9147     { Bad_Opcode },
9148     /* d8 */
9149     { Bad_Opcode },
9150     { Bad_Opcode },
9151     { Bad_Opcode },
9152     { Bad_Opcode },
9153     { Bad_Opcode },
9154     { Bad_Opcode },
9155     { Bad_Opcode },
9156     { PREFIX_TABLE (PREFIX_VEX_0F3ADF) },
9157     /* e0 */
9158     { Bad_Opcode },
9159     { Bad_Opcode },
9160     { Bad_Opcode },
9161     { Bad_Opcode },
9162     { Bad_Opcode },
9163     { Bad_Opcode },
9164     { Bad_Opcode },
9165     { Bad_Opcode },
9166     /* e8 */
9167     { Bad_Opcode },
9168     { Bad_Opcode },
9169     { Bad_Opcode },
9170     { Bad_Opcode },
9171     { Bad_Opcode },
9172     { Bad_Opcode },
9173     { Bad_Opcode },
9174     { Bad_Opcode },
9175     /* f0 */
9176     { PREFIX_TABLE (PREFIX_VEX_0F3AF0) },
9177     { Bad_Opcode },
9178     { Bad_Opcode },
9179     { Bad_Opcode },
9180     { Bad_Opcode },
9181     { Bad_Opcode },
9182     { Bad_Opcode },
9183     { Bad_Opcode },
9184     /* f8 */
9185     { Bad_Opcode },
9186     { Bad_Opcode },
9187     { Bad_Opcode },
9188     { Bad_Opcode },
9189     { Bad_Opcode },
9190     { Bad_Opcode },
9191     { Bad_Opcode },
9192     { Bad_Opcode },
9193   },
9194 };
9195
9196 #include "i386-dis-evex.h"
9197
9198 static const struct dis386 vex_len_table[][2] = {
9199   /* VEX_LEN_0F12_P_0_M_0 / VEX_LEN_0F12_P_2_M_0 */
9200   {
9201     { "vmovlpX",        { XM, Vex128, EXq }, 0 },
9202   },
9203
9204   /* VEX_LEN_0F12_P_0_M_1 */
9205   {
9206     { "vmovhlps",       { XM, Vex128, EXq }, 0 },
9207   },
9208
9209   /* VEX_LEN_0F13_M_0 */
9210   {
9211     { "vmovlpX",        { EXq, XM }, PREFIX_OPCODE },
9212   },
9213
9214   /* VEX_LEN_0F16_P_0_M_0 / VEX_LEN_0F16_P_2_M_0 */
9215   {
9216     { "vmovhpX",        { XM, Vex128, EXq }, 0 },
9217   },
9218
9219   /* VEX_LEN_0F16_P_0_M_1 */
9220   {
9221     { "vmovlhps",       { XM, Vex128, EXq }, 0 },
9222   },
9223
9224   /* VEX_LEN_0F17_M_0 */
9225   {
9226     { "vmovhpX",        { EXq, XM }, PREFIX_OPCODE },
9227   },
9228
9229   /* VEX_LEN_0F41_P_0 */
9230   {
9231     { Bad_Opcode },
9232     { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) },
9233   },
9234   /* VEX_LEN_0F41_P_2 */
9235   {
9236     { Bad_Opcode },
9237     { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) },
9238   },
9239   /* VEX_LEN_0F42_P_0 */
9240   {
9241     { Bad_Opcode },
9242     { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) },
9243   },
9244   /* VEX_LEN_0F42_P_2 */
9245   {
9246     { Bad_Opcode },
9247     { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) },
9248   },
9249   /* VEX_LEN_0F44_P_0 */
9250   {
9251     { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) },
9252   },
9253   /* VEX_LEN_0F44_P_2 */
9254   {
9255     { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) },
9256   },
9257   /* VEX_LEN_0F45_P_0 */
9258   {
9259     { Bad_Opcode },
9260     { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) },
9261   },
9262   /* VEX_LEN_0F45_P_2 */
9263   {
9264     { Bad_Opcode },
9265     { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) },
9266   },
9267   /* VEX_LEN_0F46_P_0 */
9268   {
9269     { Bad_Opcode },
9270     { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) },
9271   },
9272   /* VEX_LEN_0F46_P_2 */
9273   {
9274     { Bad_Opcode },
9275     { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) },
9276   },
9277   /* VEX_LEN_0F47_P_0 */
9278   {
9279     { Bad_Opcode },
9280     { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) },
9281   },
9282   /* VEX_LEN_0F47_P_2 */
9283   {
9284     { Bad_Opcode },
9285     { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) },
9286   },
9287   /* VEX_LEN_0F4A_P_0 */
9288   {
9289     { Bad_Opcode },
9290     { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) },
9291   },
9292   /* VEX_LEN_0F4A_P_2 */
9293   {
9294     { Bad_Opcode },
9295     { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) },
9296   },
9297   /* VEX_LEN_0F4B_P_0 */
9298   {
9299     { Bad_Opcode },
9300     { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) },
9301   },
9302   /* VEX_LEN_0F4B_P_2 */
9303   {
9304     { Bad_Opcode },
9305     { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) },
9306   },
9307
9308   /* VEX_LEN_0F6E_P_2 */
9309   {
9310     { "vmovK",          { XMScalar, Edq }, 0 },
9311   },
9312
9313   /* VEX_LEN_0F77_P_1 */
9314   {
9315     { "vzeroupper",     { XX }, 0 },
9316     { "vzeroall",       { XX }, 0 },
9317   },
9318
9319   /* VEX_LEN_0F7E_P_1 */
9320   {
9321     { "vmovq",          { XMScalar, EXxmm_mq }, 0 },
9322   },
9323
9324   /* VEX_LEN_0F7E_P_2 */
9325   {
9326     { "vmovK",          { Edq, XMScalar }, 0 },
9327   },
9328
9329   /* VEX_LEN_0F90_P_0 */
9330   {
9331     { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) },
9332   },
9333
9334   /* VEX_LEN_0F90_P_2 */
9335   {
9336     { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) },
9337   },
9338
9339   /* VEX_LEN_0F91_P_0 */
9340   {
9341     { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) },
9342   },
9343
9344   /* VEX_LEN_0F91_P_2 */
9345   {
9346     { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) },
9347   },
9348
9349   /* VEX_LEN_0F92_P_0 */
9350   {
9351     { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) },
9352   },
9353
9354   /* VEX_LEN_0F92_P_2 */
9355   {
9356     { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) },
9357   },
9358
9359   /* VEX_LEN_0F92_P_3 */
9360   {
9361     { MOD_TABLE (MOD_VEX_0F92_P_3_LEN_0) },
9362   },
9363
9364   /* VEX_LEN_0F93_P_0 */
9365   {
9366     { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) },
9367   },
9368
9369   /* VEX_LEN_0F93_P_2 */
9370   {
9371     { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) },
9372   },
9373
9374   /* VEX_LEN_0F93_P_3 */
9375   {
9376     { MOD_TABLE (MOD_VEX_0F93_P_3_LEN_0) },
9377   },
9378
9379   /* VEX_LEN_0F98_P_0 */
9380   {
9381     { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) },
9382   },
9383
9384   /* VEX_LEN_0F98_P_2 */
9385   {
9386     { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) },
9387   },
9388
9389   /* VEX_LEN_0F99_P_0 */
9390   {
9391     { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) },
9392   },
9393
9394   /* VEX_LEN_0F99_P_2 */
9395   {
9396     { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0) },
9397   },
9398
9399   /* VEX_LEN_0FAE_R_2_M_0 */
9400   {
9401     { "vldmxcsr",       { Md }, 0 },
9402   },
9403
9404   /* VEX_LEN_0FAE_R_3_M_0 */
9405   {
9406     { "vstmxcsr",       { Md }, 0 },
9407   },
9408
9409   /* VEX_LEN_0FC4_P_2 */
9410   {
9411     { "vpinsrw",        { XM, Vex128, Edqw, Ib }, 0 },
9412   },
9413
9414   /* VEX_LEN_0FC5_P_2 */
9415   {
9416     { "vpextrw",        { Gdq, XS, Ib }, 0 },
9417   },
9418
9419   /* VEX_LEN_0FD6_P_2 */
9420   {
9421     { "vmovq",          { EXqVexScalarS, XMScalar }, 0 },
9422   },
9423
9424   /* VEX_LEN_0FF7_P_2 */
9425   {
9426     { "vmaskmovdqu",    { XM, XS }, 0 },
9427   },
9428
9429   /* VEX_LEN_0F3816_P_2 */
9430   {
9431     { Bad_Opcode },
9432     { VEX_W_TABLE (VEX_W_0F3816_P_2) },
9433   },
9434
9435   /* VEX_LEN_0F3819_P_2 */
9436   {
9437     { Bad_Opcode },
9438     { VEX_W_TABLE (VEX_W_0F3819_P_2) },
9439   },
9440
9441   /* VEX_LEN_0F381A_P_2_M_0 */
9442   {
9443     { Bad_Opcode },
9444     { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) },
9445   },
9446
9447   /* VEX_LEN_0F3836_P_2 */
9448   {
9449     { Bad_Opcode },
9450     { VEX_W_TABLE (VEX_W_0F3836_P_2) },
9451   },
9452
9453   /* VEX_LEN_0F3841_P_2 */
9454   {
9455     { "vphminposuw",    { XM, EXx }, 0 },
9456   },
9457
9458   /* VEX_LEN_0F385A_P_2_M_0 */
9459   {
9460     { Bad_Opcode },
9461     { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) },
9462   },
9463
9464   /* VEX_LEN_0F38DB_P_2 */
9465   {
9466     { "vaesimc",        { XM, EXx }, 0 },
9467   },
9468
9469   /* VEX_LEN_0F38F2_P_0 */
9470   {
9471     { "andnS",          { Gdq, VexGdq, Edq }, 0 },
9472   },
9473
9474   /* VEX_LEN_0F38F3_R_1_P_0 */
9475   {
9476     { "blsrS",          { VexGdq, Edq }, 0 },
9477   },
9478
9479   /* VEX_LEN_0F38F3_R_2_P_0 */
9480   {
9481     { "blsmskS",        { VexGdq, Edq }, 0 },
9482   },
9483
9484   /* VEX_LEN_0F38F3_R_3_P_0 */
9485   {
9486     { "blsiS",          { VexGdq, Edq }, 0 },
9487   },
9488
9489   /* VEX_LEN_0F38F5_P_0 */
9490   {
9491     { "bzhiS",          { Gdq, Edq, VexGdq }, 0 },
9492   },
9493
9494   /* VEX_LEN_0F38F5_P_1 */
9495   {
9496     { "pextS",          { Gdq, VexGdq, Edq }, 0 },
9497   },
9498
9499   /* VEX_LEN_0F38F5_P_3 */
9500   {
9501     { "pdepS",          { Gdq, VexGdq, Edq }, 0 },
9502   },
9503
9504   /* VEX_LEN_0F38F6_P_3 */
9505   {
9506     { "mulxS",          { Gdq, VexGdq, Edq }, 0 },
9507   },
9508
9509   /* VEX_LEN_0F38F7_P_0 */
9510   {
9511     { "bextrS",         { Gdq, Edq, VexGdq }, 0 },
9512   },
9513
9514   /* VEX_LEN_0F38F7_P_1 */
9515   {
9516     { "sarxS",          { Gdq, Edq, VexGdq }, 0 },
9517   },
9518
9519   /* VEX_LEN_0F38F7_P_2 */
9520   {
9521     { "shlxS",          { Gdq, Edq, VexGdq }, 0 },
9522   },
9523
9524   /* VEX_LEN_0F38F7_P_3 */
9525   {
9526     { "shrxS",          { Gdq, Edq, VexGdq }, 0 },
9527   },
9528
9529   /* VEX_LEN_0F3A00_P_2 */
9530   {
9531     { Bad_Opcode },
9532     { VEX_W_TABLE (VEX_W_0F3A00_P_2) },
9533   },
9534
9535   /* VEX_LEN_0F3A01_P_2 */
9536   {
9537     { Bad_Opcode },
9538     { VEX_W_TABLE (VEX_W_0F3A01_P_2) },
9539   },
9540
9541   /* VEX_LEN_0F3A06_P_2 */
9542   {
9543     { Bad_Opcode },
9544     { VEX_W_TABLE (VEX_W_0F3A06_P_2) },
9545   },
9546
9547   /* VEX_LEN_0F3A14_P_2 */
9548   {
9549     { "vpextrb",        { Edqb, XM, Ib }, 0 },
9550   },
9551
9552   /* VEX_LEN_0F3A15_P_2 */
9553   {
9554     { "vpextrw",        { Edqw, XM, Ib }, 0 },
9555   },
9556
9557   /* VEX_LEN_0F3A16_P_2  */
9558   {
9559     { "vpextrK",        { Edq, XM, Ib }, 0 },
9560   },
9561
9562   /* VEX_LEN_0F3A17_P_2 */
9563   {
9564     { "vextractps",     { Edqd, XM, Ib }, 0 },
9565   },
9566
9567   /* VEX_LEN_0F3A18_P_2 */
9568   {
9569     { Bad_Opcode },
9570     { VEX_W_TABLE (VEX_W_0F3A18_P_2) },
9571   },
9572
9573   /* VEX_LEN_0F3A19_P_2 */
9574   {
9575     { Bad_Opcode },
9576     { VEX_W_TABLE (VEX_W_0F3A19_P_2) },
9577   },
9578
9579   /* VEX_LEN_0F3A20_P_2 */
9580   {
9581     { "vpinsrb",        { XM, Vex128, Edqb, Ib }, 0 },
9582   },
9583
9584   /* VEX_LEN_0F3A21_P_2 */
9585   {
9586     { "vinsertps",      { XM, Vex128, EXd, Ib }, 0 },
9587   },
9588
9589   /* VEX_LEN_0F3A22_P_2 */
9590   {
9591     { "vpinsrK",        { XM, Vex128, Edq, Ib }, 0 },
9592   },
9593
9594   /* VEX_LEN_0F3A30_P_2 */
9595   {
9596     { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) },
9597   },
9598
9599   /* VEX_LEN_0F3A31_P_2 */
9600   {
9601     { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0) },
9602   },
9603
9604   /* VEX_LEN_0F3A32_P_2 */
9605   {
9606     { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) },
9607   },
9608
9609   /* VEX_LEN_0F3A33_P_2 */
9610   {
9611     { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0) },
9612   },
9613
9614   /* VEX_LEN_0F3A38_P_2 */
9615   {
9616     { Bad_Opcode },
9617     { VEX_W_TABLE (VEX_W_0F3A38_P_2) },
9618   },
9619
9620   /* VEX_LEN_0F3A39_P_2 */
9621   {
9622     { Bad_Opcode },
9623     { VEX_W_TABLE (VEX_W_0F3A39_P_2) },
9624   },
9625
9626   /* VEX_LEN_0F3A41_P_2 */
9627   {
9628     { "vdppd",          { XM, Vex128, EXx, Ib }, 0 },
9629   },
9630
9631   /* VEX_LEN_0F3A46_P_2 */
9632   {
9633     { Bad_Opcode },
9634     { VEX_W_TABLE (VEX_W_0F3A46_P_2) },
9635   },
9636
9637   /* VEX_LEN_0F3A60_P_2 */
9638   {
9639     { "vpcmpestrm",     { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 },
9640   },
9641
9642   /* VEX_LEN_0F3A61_P_2 */
9643   {
9644     { "vpcmpestri",     { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 },
9645   },
9646
9647   /* VEX_LEN_0F3A62_P_2 */
9648   {
9649     { "vpcmpistrm",     { XM, EXx, Ib }, 0 },
9650   },
9651
9652   /* VEX_LEN_0F3A63_P_2 */
9653   {
9654     { "vpcmpistri",     { XM, EXx, Ib }, 0 },
9655   },
9656
9657   /* VEX_LEN_0F3A6A_P_2 */
9658   {
9659     { "vfmaddss",       { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
9660   },
9661
9662   /* VEX_LEN_0F3A6B_P_2 */
9663   {
9664     { "vfmaddsd",       { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
9665   },
9666
9667   /* VEX_LEN_0F3A6E_P_2 */
9668   {
9669     { "vfmsubss",       { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
9670   },
9671
9672   /* VEX_LEN_0F3A6F_P_2 */
9673   {
9674     { "vfmsubsd",       { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
9675   },
9676
9677   /* VEX_LEN_0F3A7A_P_2 */
9678   {
9679     { "vfnmaddss",      { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
9680   },
9681
9682   /* VEX_LEN_0F3A7B_P_2 */
9683   {
9684     { "vfnmaddsd",      { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
9685   },
9686
9687   /* VEX_LEN_0F3A7E_P_2 */
9688   {
9689     { "vfnmsubss",      { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
9690   },
9691
9692   /* VEX_LEN_0F3A7F_P_2 */
9693   {
9694     { "vfnmsubsd",      { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
9695   },
9696
9697   /* VEX_LEN_0F3ADF_P_2 */
9698   {
9699     { "vaeskeygenassist", { XM, EXx, Ib }, 0 },
9700   },
9701
9702   /* VEX_LEN_0F3AF0_P_3 */
9703   {
9704     { "rorxS",          { Gdq, Edq, Ib }, 0 },
9705   },
9706
9707   /* VEX_LEN_0FXOP_08_CC */
9708   {
9709      { "vpcomb",        { XM, Vex128, EXx, VPCOM }, 0 },
9710   },
9711
9712   /* VEX_LEN_0FXOP_08_CD */
9713   {
9714      { "vpcomw",        { XM, Vex128, EXx, VPCOM }, 0 },
9715   },
9716
9717   /* VEX_LEN_0FXOP_08_CE */
9718   {
9719      { "vpcomd",        { XM, Vex128, EXx, VPCOM }, 0 },
9720   },
9721
9722   /* VEX_LEN_0FXOP_08_CF */
9723   {
9724      { "vpcomq",        { XM, Vex128, EXx, VPCOM }, 0 },
9725   },
9726
9727   /* VEX_LEN_0FXOP_08_EC */
9728   {
9729      { "vpcomub",       { XM, Vex128, EXx, VPCOM }, 0 },
9730   },
9731
9732   /* VEX_LEN_0FXOP_08_ED */
9733   {
9734      { "vpcomuw",       { XM, Vex128, EXx, VPCOM }, 0 },
9735   },
9736
9737   /* VEX_LEN_0FXOP_08_EE */
9738   {
9739      { "vpcomud",       { XM, Vex128, EXx, VPCOM }, 0 },
9740   },
9741
9742   /* VEX_LEN_0FXOP_08_EF */
9743   {
9744      { "vpcomuq",       { XM, Vex128, EXx, VPCOM }, 0 },
9745   },
9746
9747   /* VEX_LEN_0FXOP_09_80 */
9748   {
9749     { "vfrczps",        { XM, EXxmm }, 0 },
9750     { "vfrczps",        { XM, EXymmq }, 0 },
9751   },
9752
9753   /* VEX_LEN_0FXOP_09_81 */
9754   {
9755     { "vfrczpd",        { XM, EXxmm }, 0 },
9756     { "vfrczpd",        { XM, EXymmq }, 0 },
9757   },
9758 };
9759
9760 #include "i386-dis-evex-len.h"
9761
9762 static const struct dis386 vex_w_table[][2] = {
9763   {
9764     /* VEX_W_0F41_P_0_LEN_1 */
9765     { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1) },
9766     { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1) },
9767   },
9768   {
9769     /* VEX_W_0F41_P_2_LEN_1 */
9770     { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1) },
9771     { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1) }
9772   },
9773   {
9774     /* VEX_W_0F42_P_0_LEN_1 */
9775     { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1) },
9776     { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1) },
9777   },
9778   {
9779     /* VEX_W_0F42_P_2_LEN_1 */
9780     { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1) },
9781     { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1) },
9782   },
9783   {
9784     /* VEX_W_0F44_P_0_LEN_0 */
9785     { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1) },
9786     { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1) },
9787   },
9788   {
9789     /* VEX_W_0F44_P_2_LEN_0 */
9790     { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1) },
9791     { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1) },
9792   },
9793   {
9794     /* VEX_W_0F45_P_0_LEN_1 */
9795     { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1) },
9796     { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1) },
9797   },
9798   {
9799     /* VEX_W_0F45_P_2_LEN_1 */
9800     { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1) },
9801     { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1) },
9802   },
9803   {
9804     /* VEX_W_0F46_P_0_LEN_1 */
9805     { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1) },
9806     { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1) },
9807   },
9808   {
9809     /* VEX_W_0F46_P_2_LEN_1 */
9810     { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1) },
9811     { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1) },
9812   },
9813   {
9814     /* VEX_W_0F47_P_0_LEN_1 */
9815     { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1) },
9816     { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1) },
9817   },
9818   {
9819     /* VEX_W_0F47_P_2_LEN_1 */
9820     { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1) },
9821     { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1) },
9822   },
9823   {
9824     /* VEX_W_0F4A_P_0_LEN_1 */
9825     { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1) },
9826     { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1) },
9827   },
9828   {
9829     /* VEX_W_0F4A_P_2_LEN_1 */
9830     { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1) },
9831     { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1) },
9832   },
9833   {
9834     /* VEX_W_0F4B_P_0_LEN_1 */
9835     { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1) },
9836     { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1) },
9837   },
9838   {
9839     /* VEX_W_0F4B_P_2_LEN_1 */
9840     { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1) },
9841   },
9842   {
9843     /* VEX_W_0F90_P_0_LEN_0 */
9844     { "kmovw",          { MaskG, MaskE }, 0 },
9845     { "kmovq",          { MaskG, MaskE }, 0 },
9846   },
9847   {
9848     /* VEX_W_0F90_P_2_LEN_0 */
9849     { "kmovb",          { MaskG, MaskBDE }, 0 },
9850     { "kmovd",          { MaskG, MaskBDE }, 0 },
9851   },
9852   {
9853     /* VEX_W_0F91_P_0_LEN_0 */
9854     { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0) },
9855     { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0) },
9856   },
9857   {
9858     /* VEX_W_0F91_P_2_LEN_0 */
9859     { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0) },
9860     { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0) },
9861   },
9862   {
9863     /* VEX_W_0F92_P_0_LEN_0 */
9864     { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0) },
9865   },
9866   {
9867     /* VEX_W_0F92_P_2_LEN_0 */
9868     { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0) },
9869   },
9870   {
9871     /* VEX_W_0F93_P_0_LEN_0 */
9872     { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0) },
9873   },
9874   {
9875     /* VEX_W_0F93_P_2_LEN_0 */
9876     { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0) },
9877   },
9878   {
9879     /* VEX_W_0F98_P_0_LEN_0 */
9880     { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0) },
9881     { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0) },
9882   },
9883   {
9884     /* VEX_W_0F98_P_2_LEN_0 */
9885     { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0) },
9886     { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0) },
9887   },
9888   {
9889     /* VEX_W_0F99_P_0_LEN_0 */
9890     { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0) },
9891     { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0) },
9892   },
9893   {
9894     /* VEX_W_0F99_P_2_LEN_0 */
9895     { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0) },
9896     { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0) },
9897   },
9898   {
9899     /* VEX_W_0F380C_P_2  */
9900     { "vpermilps",      { XM, Vex, EXx }, 0 },
9901   },
9902   {
9903     /* VEX_W_0F380D_P_2  */
9904     { "vpermilpd",      { XM, Vex, EXx }, 0 },
9905   },
9906   {
9907     /* VEX_W_0F380E_P_2  */
9908     { "vtestps",        { XM, EXx }, 0 },
9909   },
9910   {
9911     /* VEX_W_0F380F_P_2  */
9912     { "vtestpd",        { XM, EXx }, 0 },
9913   },
9914   {
9915     /* VEX_W_0F3813_P_2 */
9916     { "vcvtph2ps", { XM, EXxmmq }, 0 },
9917   },
9918   {
9919     /* VEX_W_0F3816_P_2  */
9920     { "vpermps",        { XM, Vex, EXx }, 0 },
9921   },
9922   {
9923     /* VEX_W_0F3818_P_2 */
9924     { "vbroadcastss",   { XM, EXxmm_md }, 0 },
9925   },
9926   {
9927     /* VEX_W_0F3819_P_2 */
9928     { "vbroadcastsd",   { XM, EXxmm_mq }, 0 },
9929   },
9930   {
9931     /* VEX_W_0F381A_P_2_M_0 */
9932     { "vbroadcastf128", { XM, Mxmm }, 0 },
9933   },
9934   {
9935     /* VEX_W_0F382C_P_2_M_0 */
9936     { "vmaskmovps",     { XM, Vex, Mx }, 0 },
9937   },
9938   {
9939     /* VEX_W_0F382D_P_2_M_0 */
9940     { "vmaskmovpd",     { XM, Vex, Mx }, 0 },
9941   },
9942   {
9943     /* VEX_W_0F382E_P_2_M_0 */
9944     { "vmaskmovps",     { Mx, Vex, XM }, 0 },
9945   },
9946   {
9947     /* VEX_W_0F382F_P_2_M_0 */
9948     { "vmaskmovpd",     { Mx, Vex, XM }, 0 },
9949   },
9950   {
9951     /* VEX_W_0F3836_P_2  */
9952     { "vpermd",         { XM, Vex, EXx }, 0 },
9953   },
9954   {
9955     /* VEX_W_0F3846_P_2 */
9956     { "vpsravd",        { XM, Vex, EXx }, 0 },
9957   },
9958   {
9959     /* VEX_W_0F3858_P_2 */
9960     { "vpbroadcastd", { XM, EXxmm_md }, 0 },
9961   },
9962   {
9963     /* VEX_W_0F3859_P_2 */
9964     { "vpbroadcastq",   { XM, EXxmm_mq }, 0 },
9965   },
9966   {
9967     /* VEX_W_0F385A_P_2_M_0 */
9968     { "vbroadcasti128", { XM, Mxmm }, 0 },
9969   },
9970   {
9971     /* VEX_W_0F3878_P_2 */
9972     { "vpbroadcastb",   { XM, EXxmm_mb }, 0 },
9973   },
9974   {
9975     /* VEX_W_0F3879_P_2 */
9976     { "vpbroadcastw",   { XM, EXxmm_mw }, 0 },
9977   },
9978   {
9979     /* VEX_W_0F38CF_P_2 */
9980     { "vgf2p8mulb", { XM, Vex, EXx }, 0 },
9981   },
9982   {
9983     /* VEX_W_0F3A00_P_2 */
9984     { Bad_Opcode },
9985     { "vpermq",         { XM, EXx, Ib }, 0 },
9986   },
9987   {
9988     /* VEX_W_0F3A01_P_2 */
9989     { Bad_Opcode },
9990     { "vpermpd",        { XM, EXx, Ib }, 0 },
9991   },
9992   {
9993     /* VEX_W_0F3A02_P_2 */
9994     { "vpblendd",       { XM, Vex, EXx, Ib }, 0 },
9995   },
9996   {
9997     /* VEX_W_0F3A04_P_2 */
9998     { "vpermilps",      { XM, EXx, Ib }, 0 },
9999   },
10000   {
10001     /* VEX_W_0F3A05_P_2 */
10002     { "vpermilpd",      { XM, EXx, Ib }, 0 },
10003   },
10004   {
10005     /* VEX_W_0F3A06_P_2 */
10006     { "vperm2f128",     { XM, Vex256, EXx, Ib }, 0 },
10007   },
10008   {
10009     /* VEX_W_0F3A18_P_2 */
10010     { "vinsertf128",    { XM, Vex256, EXxmm, Ib }, 0 },
10011   },
10012   {
10013     /* VEX_W_0F3A19_P_2 */
10014     { "vextractf128",   { EXxmm, XM, Ib }, 0 },
10015   },
10016   {
10017     /* VEX_W_0F3A1D_P_2 */
10018     { "vcvtps2ph", { EXxmmq, XM, EXxEVexS, Ib }, 0 },
10019   },
10020   {
10021     /* VEX_W_0F3A30_P_2_LEN_0 */
10022     { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0) },
10023     { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0) },
10024   },
10025   {
10026     /* VEX_W_0F3A31_P_2_LEN_0 */
10027     { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0) },
10028     { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0) },
10029   },
10030   {
10031     /* VEX_W_0F3A32_P_2_LEN_0 */
10032     { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0) },
10033     { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0) },
10034   },
10035   {
10036     /* VEX_W_0F3A33_P_2_LEN_0 */
10037     { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0) },
10038     { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0) },
10039   },
10040   {
10041     /* VEX_W_0F3A38_P_2 */
10042     { "vinserti128",    { XM, Vex256, EXxmm, Ib }, 0 },
10043   },
10044   {
10045     /* VEX_W_0F3A39_P_2 */
10046     { "vextracti128",   { EXxmm, XM, Ib }, 0 },
10047   },
10048   {
10049     /* VEX_W_0F3A46_P_2 */
10050     { "vperm2i128",     { XM, Vex256, EXx, Ib }, 0 },
10051   },
10052   {
10053     /* VEX_W_0F3A48_P_2 */
10054     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
10055     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
10056   },
10057   {
10058     /* VEX_W_0F3A49_P_2 */
10059     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
10060     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
10061   },
10062   {
10063     /* VEX_W_0F3A4A_P_2 */
10064     { "vblendvps",      { XM, Vex, EXx, XMVexI4 }, 0 },
10065   },
10066   {
10067     /* VEX_W_0F3A4B_P_2 */
10068     { "vblendvpd",      { XM, Vex, EXx, XMVexI4 }, 0 },
10069   },
10070   {
10071     /* VEX_W_0F3A4C_P_2 */
10072     { "vpblendvb",      { XM, Vex, EXx, XMVexI4 }, 0 },
10073   },
10074   {
10075     /* VEX_W_0F3ACE_P_2 */
10076     { Bad_Opcode },
10077     { "vgf2p8affineqb", { XM, Vex, EXx, Ib }, 0 },
10078   },
10079   {
10080     /* VEX_W_0F3ACF_P_2 */
10081     { Bad_Opcode },
10082     { "vgf2p8affineinvqb",  { XM, Vex, EXx, Ib }, 0 },
10083   },
10084
10085 #include "i386-dis-evex-w.h"
10086 };
10087
10088 static const struct dis386 mod_table[][2] = {
10089   {
10090     /* MOD_8D */
10091     { "leaS",           { Gv, M }, 0 },
10092   },
10093   {
10094     /* MOD_C6_REG_7 */
10095     { Bad_Opcode },
10096     { RM_TABLE (RM_C6_REG_7) },
10097   },
10098   {
10099     /* MOD_C7_REG_7 */
10100     { Bad_Opcode },
10101     { RM_TABLE (RM_C7_REG_7) },
10102   },
10103   {
10104     /* MOD_FF_REG_3 */
10105     { "{l|}call^", { indirEp }, 0 },
10106   },
10107   {
10108     /* MOD_FF_REG_5 */
10109     { "{l|}jmp^", { indirEp }, 0 },
10110   },
10111   {
10112     /* MOD_0F01_REG_0 */
10113     { X86_64_TABLE (X86_64_0F01_REG_0) },
10114     { RM_TABLE (RM_0F01_REG_0) },
10115   },
10116   {
10117     /* MOD_0F01_REG_1 */
10118     { X86_64_TABLE (X86_64_0F01_REG_1) },
10119     { RM_TABLE (RM_0F01_REG_1) },
10120   },
10121   {
10122     /* MOD_0F01_REG_2 */
10123     { X86_64_TABLE (X86_64_0F01_REG_2) },
10124     { RM_TABLE (RM_0F01_REG_2) },
10125   },
10126   {
10127     /* MOD_0F01_REG_3 */
10128     { X86_64_TABLE (X86_64_0F01_REG_3) },
10129     { RM_TABLE (RM_0F01_REG_3) },
10130   },
10131   {
10132     /* MOD_0F01_REG_5 */
10133     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_0) },
10134     { RM_TABLE (RM_0F01_REG_5_MOD_3) },
10135   },
10136   {
10137     /* MOD_0F01_REG_7 */
10138     { "invlpg",         { Mb }, 0 },
10139     { RM_TABLE (RM_0F01_REG_7_MOD_3) },
10140   },
10141   {
10142     /* MOD_0F12_PREFIX_0 */
10143     { "movlpX",         { XM, EXq }, 0 },
10144     { "movhlps",        { XM, EXq }, 0 },
10145   },
10146   {
10147     /* MOD_0F12_PREFIX_2 */
10148     { "movlpX", { XM, EXq }, 0 },
10149   },
10150   {
10151     /* MOD_0F13 */
10152     { "movlpX",         { EXq, XM }, PREFIX_OPCODE },
10153   },
10154   {
10155     /* MOD_0F16_PREFIX_0 */
10156     { "movhpX",         { XM, EXq }, 0 },
10157     { "movlhps",        { XM, EXq }, 0 },
10158   },
10159   {
10160     /* MOD_0F16_PREFIX_2 */
10161     { "movhpX", { XM, EXq }, 0 },
10162   },
10163   {
10164     /* MOD_0F17 */
10165     { "movhpX",         { EXq, XM }, PREFIX_OPCODE },
10166   },
10167   {
10168     /* MOD_0F18_REG_0 */
10169     { "prefetchnta",    { Mb }, 0 },
10170   },
10171   {
10172     /* MOD_0F18_REG_1 */
10173     { "prefetcht0",     { Mb }, 0 },
10174   },
10175   {
10176     /* MOD_0F18_REG_2 */
10177     { "prefetcht1",     { Mb }, 0 },
10178   },
10179   {
10180     /* MOD_0F18_REG_3 */
10181     { "prefetcht2",     { Mb }, 0 },
10182   },
10183   {
10184     /* MOD_0F18_REG_4 */
10185     { "nop/reserved",   { Mb }, 0 },
10186   },
10187   {
10188     /* MOD_0F18_REG_5 */
10189     { "nop/reserved",   { Mb }, 0 },
10190   },
10191   {
10192     /* MOD_0F18_REG_6 */
10193     { "nop/reserved",   { Mb }, 0 },
10194   },
10195   {
10196     /* MOD_0F18_REG_7 */
10197     { "nop/reserved",   { Mb }, 0 },
10198   },
10199   {
10200     /* MOD_0F1A_PREFIX_0 */
10201     { "bndldx",         { Gbnd, Mv_bnd }, 0 },
10202     { "nopQ",           { Ev }, 0 },
10203   },
10204   {
10205     /* MOD_0F1B_PREFIX_0 */
10206     { "bndstx",         { Mv_bnd, Gbnd }, 0 },
10207     { "nopQ",           { Ev }, 0 },
10208   },
10209   {
10210     /* MOD_0F1B_PREFIX_1 */
10211     { "bndmk",          { Gbnd, Mv_bnd }, 0 },
10212     { "nopQ",           { Ev }, 0 },
10213   },
10214   {
10215     /* MOD_0F1C_PREFIX_0 */
10216     { REG_TABLE (REG_0F1C_P_0_MOD_0) },
10217     { "nopQ",           { Ev }, 0 },
10218   },
10219   {
10220     /* MOD_0F1E_PREFIX_1 */
10221     { "nopQ",           { Ev }, 0 },
10222     { REG_TABLE (REG_0F1E_P_1_MOD_3) },
10223   },
10224   {
10225     /* MOD_0F24 */
10226     { Bad_Opcode },
10227     { "movL",           { Rd, Td }, 0 },
10228   },
10229   {
10230     /* MOD_0F26 */
10231     { Bad_Opcode },
10232     { "movL",           { Td, Rd }, 0 },
10233   },
10234   {
10235     /* MOD_0F2B_PREFIX_0 */
10236     {"movntps",         { Mx, XM }, PREFIX_OPCODE },
10237   },
10238   {
10239     /* MOD_0F2B_PREFIX_1 */
10240     {"movntss",         { Md, XM }, PREFIX_OPCODE },
10241   },
10242   {
10243     /* MOD_0F2B_PREFIX_2 */
10244     {"movntpd",         { Mx, XM }, PREFIX_OPCODE },
10245   },
10246   {
10247     /* MOD_0F2B_PREFIX_3 */
10248     {"movntsd",         { Mq, XM }, PREFIX_OPCODE },
10249   },
10250   {
10251     /* MOD_0F50 */
10252     { Bad_Opcode },
10253     { "movmskpX",       { Gdq, XS }, PREFIX_OPCODE },
10254   },
10255   {
10256     /* MOD_0F71_REG_2 */
10257     { Bad_Opcode },
10258     { "psrlw",          { MS, Ib }, 0 },
10259   },
10260   {
10261     /* MOD_0F71_REG_4 */
10262     { Bad_Opcode },
10263     { "psraw",          { MS, Ib }, 0 },
10264   },
10265   {
10266     /* MOD_0F71_REG_6 */
10267     { Bad_Opcode },
10268     { "psllw",          { MS, Ib }, 0 },
10269   },
10270   {
10271     /* MOD_0F72_REG_2 */
10272     { Bad_Opcode },
10273     { "psrld",          { MS, Ib }, 0 },
10274   },
10275   {
10276     /* MOD_0F72_REG_4 */
10277     { Bad_Opcode },
10278     { "psrad",          { MS, Ib }, 0 },
10279   },
10280   {
10281     /* MOD_0F72_REG_6 */
10282     { Bad_Opcode },
10283     { "pslld",          { MS, Ib }, 0 },
10284   },
10285   {
10286     /* MOD_0F73_REG_2 */
10287     { Bad_Opcode },
10288     { "psrlq",          { MS, Ib }, 0 },
10289   },
10290   {
10291     /* MOD_0F73_REG_3 */
10292     { Bad_Opcode },
10293     { PREFIX_TABLE (PREFIX_0F73_REG_3) },
10294   },
10295   {
10296     /* MOD_0F73_REG_6 */
10297     { Bad_Opcode },
10298     { "psllq",          { MS, Ib }, 0 },
10299   },
10300   {
10301     /* MOD_0F73_REG_7 */
10302     { Bad_Opcode },
10303     { PREFIX_TABLE (PREFIX_0F73_REG_7) },
10304   },
10305   {
10306     /* MOD_0FAE_REG_0 */
10307     { "fxsave",         { FXSAVE }, 0 },
10308     { PREFIX_TABLE (PREFIX_0FAE_REG_0_MOD_3) },
10309   },
10310   {
10311     /* MOD_0FAE_REG_1 */
10312     { "fxrstor",        { FXSAVE }, 0 },
10313     { PREFIX_TABLE (PREFIX_0FAE_REG_1_MOD_3) },
10314   },
10315   {
10316     /* MOD_0FAE_REG_2 */
10317     { "ldmxcsr",        { Md }, 0 },
10318     { PREFIX_TABLE (PREFIX_0FAE_REG_2_MOD_3) },
10319   },
10320   {
10321     /* MOD_0FAE_REG_3 */
10322     { "stmxcsr",        { Md }, 0 },
10323     { PREFIX_TABLE (PREFIX_0FAE_REG_3_MOD_3) },
10324   },
10325   {
10326     /* MOD_0FAE_REG_4 */
10327     { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_0) },
10328     { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_3) },
10329   },
10330   {
10331     /* MOD_0FAE_REG_5 */
10332     { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_0) },
10333     { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_3) },
10334   },
10335   {
10336     /* MOD_0FAE_REG_6 */
10337     { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_0) },
10338     { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_3) },
10339   },
10340   {
10341     /* MOD_0FAE_REG_7 */
10342     { PREFIX_TABLE (PREFIX_0FAE_REG_7_MOD_0) },
10343     { RM_TABLE (RM_0FAE_REG_7_MOD_3) },
10344   },
10345   {
10346     /* MOD_0FB2 */
10347     { "lssS",           { Gv, Mp }, 0 },
10348   },
10349   {
10350     /* MOD_0FB4 */
10351     { "lfsS",           { Gv, Mp }, 0 },
10352   },
10353   {
10354     /* MOD_0FB5 */
10355     { "lgsS",           { Gv, Mp }, 0 },
10356   },
10357   {
10358     /* MOD_0FC3 */
10359     { PREFIX_TABLE (PREFIX_0FC3_MOD_0) },
10360   },
10361   {
10362     /* MOD_0FC7_REG_3 */
10363     { "xrstors",        { FXSAVE }, 0 },
10364   },
10365   {
10366     /* MOD_0FC7_REG_4 */
10367     { "xsavec",         { FXSAVE }, 0 },
10368   },
10369   {
10370     /* MOD_0FC7_REG_5 */
10371     { "xsaves",         { FXSAVE }, 0 },
10372   },
10373   {
10374     /* MOD_0FC7_REG_6 */
10375     { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_0) },
10376     { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_3) }
10377   },
10378   {
10379     /* MOD_0FC7_REG_7 */
10380     { "vmptrst",        { Mq }, 0 },
10381     { PREFIX_TABLE (PREFIX_0FC7_REG_7_MOD_3) }
10382   },
10383   {
10384     /* MOD_0FD7 */
10385     { Bad_Opcode },
10386     { "pmovmskb",       { Gdq, MS }, 0 },
10387   },
10388   {
10389     /* MOD_0FE7_PREFIX_2 */
10390     { "movntdq",        { Mx, XM }, 0 },
10391   },
10392   {
10393     /* MOD_0FF0_PREFIX_3 */
10394     { "lddqu",          { XM, M }, 0 },
10395   },
10396   {
10397     /* MOD_0F382A_PREFIX_2 */
10398     { "movntdqa",       { XM, Mx }, 0 },
10399   },
10400   {
10401     /* MOD_0F38F5_PREFIX_2 */
10402     { "wrussK",         { M, Gdq }, PREFIX_OPCODE },
10403   },
10404   {
10405     /* MOD_0F38F6_PREFIX_0 */
10406     { "wrssK",          { M, Gdq }, PREFIX_OPCODE },
10407   },
10408   {
10409     /* MOD_0F38F8_PREFIX_1 */
10410     { "enqcmds",        { Gva, M }, PREFIX_OPCODE },
10411   },
10412   {
10413     /* MOD_0F38F8_PREFIX_2 */
10414     { "movdir64b",      { Gva, M }, PREFIX_OPCODE },
10415   },
10416   {
10417     /* MOD_0F38F8_PREFIX_3 */
10418     { "enqcmd",         { Gva, M }, PREFIX_OPCODE },
10419   },
10420   {
10421     /* MOD_0F38F9_PREFIX_0 */
10422     { "movdiri",        { Ev, Gv }, PREFIX_OPCODE },
10423   },
10424   {
10425     /* MOD_62_32BIT */
10426     { "bound{S|}",      { Gv, Ma }, 0 },
10427     { EVEX_TABLE (EVEX_0F) },
10428   },
10429   {
10430     /* MOD_C4_32BIT */
10431     { "lesS",           { Gv, Mp }, 0 },
10432     { VEX_C4_TABLE (VEX_0F) },
10433   },
10434   {
10435     /* MOD_C5_32BIT */
10436     { "ldsS",           { Gv, Mp }, 0 },
10437     { VEX_C5_TABLE (VEX_0F) },
10438   },
10439   {
10440     /* MOD_VEX_0F12_PREFIX_0 */
10441     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
10442     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
10443   },
10444   {
10445     /* MOD_VEX_0F12_PREFIX_2 */
10446     { VEX_LEN_TABLE (VEX_LEN_0F12_P_2_M_0) },
10447   },
10448   {
10449     /* MOD_VEX_0F13 */
10450     { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
10451   },
10452   {
10453     /* MOD_VEX_0F16_PREFIX_0 */
10454     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
10455     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
10456   },
10457   {
10458     /* MOD_VEX_0F16_PREFIX_2 */
10459     { VEX_LEN_TABLE (VEX_LEN_0F16_P_2_M_0) },
10460   },
10461   {
10462     /* MOD_VEX_0F17 */
10463     { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
10464   },
10465   {
10466     /* MOD_VEX_0F2B */
10467     { "vmovntpX",       { Mx, XM }, PREFIX_OPCODE },
10468   },
10469   {
10470     /* MOD_VEX_W_0_0F41_P_0_LEN_1 */
10471     { Bad_Opcode },
10472     { "kandw",          { MaskG, MaskVex, MaskR }, 0 },
10473   },
10474   {
10475     /* MOD_VEX_W_1_0F41_P_0_LEN_1 */
10476     { Bad_Opcode },
10477     { "kandq",          { MaskG, MaskVex, MaskR }, 0 },
10478   },
10479   {
10480     /* MOD_VEX_W_0_0F41_P_2_LEN_1 */
10481     { Bad_Opcode },
10482     { "kandb",          { MaskG, MaskVex, MaskR }, 0 },
10483   },
10484   {
10485     /* MOD_VEX_W_1_0F41_P_2_LEN_1 */
10486     { Bad_Opcode },
10487     { "kandd",          { MaskG, MaskVex, MaskR }, 0 },
10488   },
10489   {
10490     /* MOD_VEX_W_0_0F42_P_0_LEN_1 */
10491     { Bad_Opcode },
10492     { "kandnw",         { MaskG, MaskVex, MaskR }, 0 },
10493   },
10494   {
10495     /* MOD_VEX_W_1_0F42_P_0_LEN_1 */
10496     { Bad_Opcode },
10497     { "kandnq",         { MaskG, MaskVex, MaskR }, 0 },
10498   },
10499   {
10500     /* MOD_VEX_W_0_0F42_P_2_LEN_1 */
10501     { Bad_Opcode },
10502     { "kandnb",         { MaskG, MaskVex, MaskR }, 0 },
10503   },
10504   {
10505     /* MOD_VEX_W_1_0F42_P_2_LEN_1 */
10506     { Bad_Opcode },
10507     { "kandnd",         { MaskG, MaskVex, MaskR }, 0 },
10508   },
10509   {
10510     /* MOD_VEX_W_0_0F44_P_0_LEN_0 */
10511     { Bad_Opcode },
10512     { "knotw",          { MaskG, MaskR }, 0 },
10513   },
10514   {
10515     /* MOD_VEX_W_1_0F44_P_0_LEN_0 */
10516     { Bad_Opcode },
10517     { "knotq",          { MaskG, MaskR }, 0 },
10518   },
10519   {
10520     /* MOD_VEX_W_0_0F44_P_2_LEN_0 */
10521     { Bad_Opcode },
10522     { "knotb",          { MaskG, MaskR }, 0 },
10523   },
10524   {
10525     /* MOD_VEX_W_1_0F44_P_2_LEN_0 */
10526     { Bad_Opcode },
10527     { "knotd",          { MaskG, MaskR }, 0 },
10528   },
10529   {
10530     /* MOD_VEX_W_0_0F45_P_0_LEN_1 */
10531     { Bad_Opcode },
10532     { "korw",       { MaskG, MaskVex, MaskR }, 0 },
10533   },
10534   {
10535     /* MOD_VEX_W_1_0F45_P_0_LEN_1 */
10536     { Bad_Opcode },
10537     { "korq",       { MaskG, MaskVex, MaskR }, 0 },
10538   },
10539   {
10540     /* MOD_VEX_W_0_0F45_P_2_LEN_1 */
10541     { Bad_Opcode },
10542     { "korb",       { MaskG, MaskVex, MaskR }, 0 },
10543   },
10544   {
10545     /* MOD_VEX_W_1_0F45_P_2_LEN_1 */
10546     { Bad_Opcode },
10547     { "kord",       { MaskG, MaskVex, MaskR }, 0 },
10548   },
10549  {
10550     /* MOD_VEX_W_0_0F46_P_0_LEN_1 */
10551     { Bad_Opcode },
10552     { "kxnorw",     { MaskG, MaskVex, MaskR }, 0 },
10553   },
10554   {
10555     /* MOD_VEX_W_1_0F46_P_0_LEN_1 */
10556     { Bad_Opcode },
10557     { "kxnorq",     { MaskG, MaskVex, MaskR }, 0 },
10558   },
10559   {
10560     /* MOD_VEX_W_0_0F46_P_2_LEN_1 */
10561     { Bad_Opcode },
10562     { "kxnorb",     { MaskG, MaskVex, MaskR }, 0 },
10563   },
10564   {
10565     /* MOD_VEX_W_1_0F46_P_2_LEN_1 */
10566     { Bad_Opcode },
10567     { "kxnord",     { MaskG, MaskVex, MaskR }, 0 },
10568   },
10569   {
10570     /* MOD_VEX_W_0_0F47_P_0_LEN_1 */
10571     { Bad_Opcode },
10572     { "kxorw",      { MaskG, MaskVex, MaskR }, 0 },
10573   },
10574   {
10575     /* MOD_VEX_W_1_0F47_P_0_LEN_1 */
10576     { Bad_Opcode },
10577     { "kxorq",      { MaskG, MaskVex, MaskR }, 0 },
10578   },
10579   {
10580     /* MOD_VEX_W_0_0F47_P_2_LEN_1 */
10581     { Bad_Opcode },
10582     { "kxorb",      { MaskG, MaskVex, MaskR }, 0 },
10583   },
10584   {
10585     /* MOD_VEX_W_1_0F47_P_2_LEN_1 */
10586     { Bad_Opcode },
10587     { "kxord",      { MaskG, MaskVex, MaskR }, 0 },
10588   },
10589   {
10590     /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */
10591     { Bad_Opcode },
10592     { "kaddw",          { MaskG, MaskVex, MaskR }, 0 },
10593   },
10594   {
10595     /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */
10596     { Bad_Opcode },
10597     { "kaddq",          { MaskG, MaskVex, MaskR }, 0 },
10598   },
10599   {
10600     /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */
10601     { Bad_Opcode },
10602     { "kaddb",          { MaskG, MaskVex, MaskR }, 0 },
10603   },
10604   {
10605     /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */
10606     { Bad_Opcode },
10607     { "kaddd",          { MaskG, MaskVex, MaskR }, 0 },
10608   },
10609   {
10610     /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */
10611     { Bad_Opcode },
10612     { "kunpckwd",   { MaskG, MaskVex, MaskR }, 0 },
10613   },
10614   {
10615     /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */
10616     { Bad_Opcode },
10617     { "kunpckdq",   { MaskG, MaskVex, MaskR }, 0 },
10618   },
10619   {
10620     /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */
10621     { Bad_Opcode },
10622     { "kunpckbw",   { MaskG, MaskVex, MaskR }, 0 },
10623   },
10624   {
10625     /* MOD_VEX_0F50 */
10626     { Bad_Opcode },
10627     { "vmovmskpX",      { Gdq, XS }, PREFIX_OPCODE },
10628   },
10629   {
10630     /* MOD_VEX_0F71_REG_2 */
10631     { Bad_Opcode },
10632     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) },
10633   },
10634   {
10635     /* MOD_VEX_0F71_REG_4 */
10636     { Bad_Opcode },
10637     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) },
10638   },
10639   {
10640     /* MOD_VEX_0F71_REG_6 */
10641     { Bad_Opcode },
10642     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) },
10643   },
10644   {
10645     /* MOD_VEX_0F72_REG_2 */
10646     { Bad_Opcode },
10647     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) },
10648   },
10649   {
10650     /* MOD_VEX_0F72_REG_4 */
10651     { Bad_Opcode },
10652     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) },
10653   },
10654   {
10655     /* MOD_VEX_0F72_REG_6 */
10656     { Bad_Opcode },
10657     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) },
10658   },
10659   {
10660     /* MOD_VEX_0F73_REG_2 */
10661     { Bad_Opcode },
10662     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) },
10663   },
10664   {
10665     /* MOD_VEX_0F73_REG_3 */
10666     { Bad_Opcode },
10667     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) },
10668   },
10669   {
10670     /* MOD_VEX_0F73_REG_6 */
10671     { Bad_Opcode },
10672     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) },
10673   },
10674   {
10675     /* MOD_VEX_0F73_REG_7 */
10676     { Bad_Opcode },
10677     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) },
10678   },
10679   {
10680     /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
10681     { "kmovw",          { Ew, MaskG }, 0 },
10682     { Bad_Opcode },
10683   },
10684   {
10685     /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
10686     { "kmovq",          { Eq, MaskG }, 0 },
10687     { Bad_Opcode },
10688   },
10689   {
10690     /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
10691     { "kmovb",          { Eb, MaskG }, 0 },
10692     { Bad_Opcode },
10693   },
10694   {
10695     /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
10696     { "kmovd",          { Ed, MaskG }, 0 },
10697     { Bad_Opcode },
10698   },
10699   {
10700     /* MOD_VEX_W_0_0F92_P_0_LEN_0 */
10701     { Bad_Opcode },
10702     { "kmovw",          { MaskG, Rdq }, 0 },
10703   },
10704   {
10705     /* MOD_VEX_W_0_0F92_P_2_LEN_0 */
10706     { Bad_Opcode },
10707     { "kmovb",          { MaskG, Rdq }, 0 },
10708   },
10709   {
10710     /* MOD_VEX_0F92_P_3_LEN_0 */
10711     { Bad_Opcode },
10712     { "kmovK",          { MaskG, Rdq }, 0 },
10713   },
10714   {
10715     /* MOD_VEX_W_0_0F93_P_0_LEN_0 */
10716     { Bad_Opcode },
10717     { "kmovw",          { Gdq, MaskR }, 0 },
10718   },
10719   {
10720     /* MOD_VEX_W_0_0F93_P_2_LEN_0 */
10721     { Bad_Opcode },
10722     { "kmovb",          { Gdq, MaskR }, 0 },
10723   },
10724   {
10725     /* MOD_VEX_0F93_P_3_LEN_0 */
10726     { Bad_Opcode },
10727     { "kmovK",          { Gdq, MaskR }, 0 },
10728   },
10729   {
10730     /* MOD_VEX_W_0_0F98_P_0_LEN_0 */
10731     { Bad_Opcode },
10732     { "kortestw", { MaskG, MaskR }, 0 },
10733   },
10734   {
10735     /* MOD_VEX_W_1_0F98_P_0_LEN_0 */
10736     { Bad_Opcode },
10737     { "kortestq", { MaskG, MaskR }, 0 },
10738   },
10739   {
10740     /* MOD_VEX_W_0_0F98_P_2_LEN_0 */
10741     { Bad_Opcode },
10742     { "kortestb", { MaskG, MaskR }, 0 },
10743   },
10744   {
10745     /* MOD_VEX_W_1_0F98_P_2_LEN_0 */
10746     { Bad_Opcode },
10747     { "kortestd", { MaskG, MaskR }, 0 },
10748   },
10749   {
10750     /* MOD_VEX_W_0_0F99_P_0_LEN_0 */
10751     { Bad_Opcode },
10752     { "ktestw", { MaskG, MaskR }, 0 },
10753   },
10754   {
10755     /* MOD_VEX_W_1_0F99_P_0_LEN_0 */
10756     { Bad_Opcode },
10757     { "ktestq", { MaskG, MaskR }, 0 },
10758   },
10759   {
10760     /* MOD_VEX_W_0_0F99_P_2_LEN_0 */
10761     { Bad_Opcode },
10762     { "ktestb", { MaskG, MaskR }, 0 },
10763   },
10764   {
10765     /* MOD_VEX_W_1_0F99_P_2_LEN_0 */
10766     { Bad_Opcode },
10767     { "ktestd", { MaskG, MaskR }, 0 },
10768   },
10769   {
10770     /* MOD_VEX_0FAE_REG_2 */
10771     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
10772   },
10773   {
10774     /* MOD_VEX_0FAE_REG_3 */
10775     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
10776   },
10777   {
10778     /* MOD_VEX_0FD7_PREFIX_2 */
10779     { Bad_Opcode },
10780     { "vpmovmskb",      { Gdq, XS }, 0 },
10781   },
10782   {
10783     /* MOD_VEX_0FE7_PREFIX_2 */
10784     { "vmovntdq",       { Mx, XM }, 0 },
10785   },
10786   {
10787     /* MOD_VEX_0FF0_PREFIX_3 */
10788     { "vlddqu",         { XM, M }, 0 },
10789   },
10790   {
10791     /* MOD_VEX_0F381A_PREFIX_2 */
10792     { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) },
10793   },
10794   {
10795     /* MOD_VEX_0F382A_PREFIX_2 */
10796     { "vmovntdqa",      { XM, Mx }, 0 },
10797   },
10798   {
10799     /* MOD_VEX_0F382C_PREFIX_2 */
10800     { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) },
10801   },
10802   {
10803     /* MOD_VEX_0F382D_PREFIX_2 */
10804     { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) },
10805   },
10806   {
10807     /* MOD_VEX_0F382E_PREFIX_2 */
10808     { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) },
10809   },
10810   {
10811     /* MOD_VEX_0F382F_PREFIX_2 */
10812     { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) },
10813   },
10814   {
10815     /* MOD_VEX_0F385A_PREFIX_2 */
10816     { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) },
10817   },
10818   {
10819     /* MOD_VEX_0F388C_PREFIX_2 */
10820     { "vpmaskmov%LW",   { XM, Vex, Mx }, 0 },
10821   },
10822   {
10823     /* MOD_VEX_0F388E_PREFIX_2 */
10824     { "vpmaskmov%LW",   { Mx, Vex, XM }, 0 },
10825   },
10826   {
10827     /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */
10828     { Bad_Opcode },
10829     { "kshiftrb",       { MaskG, MaskR, Ib }, 0 },
10830   },
10831   {
10832     /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */
10833     { Bad_Opcode },
10834     { "kshiftrw",       { MaskG, MaskR, Ib }, 0 },
10835   },
10836   {
10837     /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */
10838     { Bad_Opcode },
10839     { "kshiftrd",       { MaskG, MaskR, Ib }, 0 },
10840   },
10841   {
10842     /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */
10843     { Bad_Opcode },
10844     { "kshiftrq",       { MaskG, MaskR, Ib }, 0 },
10845   },
10846   {
10847     /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */
10848     { Bad_Opcode },
10849     { "kshiftlb",       { MaskG, MaskR, Ib }, 0 },
10850   },
10851   {
10852     /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */
10853     { Bad_Opcode },
10854     { "kshiftlw",       { MaskG, MaskR, Ib }, 0 },
10855   },
10856   {
10857     /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */
10858     { Bad_Opcode },
10859     { "kshiftld",       { MaskG, MaskR, Ib }, 0 },
10860   },
10861   {
10862     /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */
10863     { Bad_Opcode },
10864     { "kshiftlq",       { MaskG, MaskR, Ib }, 0 },
10865   },
10866
10867 #include "i386-dis-evex-mod.h"
10868 };
10869
10870 static const struct dis386 rm_table[][8] = {
10871   {
10872     /* RM_C6_REG_7 */
10873     { "xabort",         { Skip_MODRM, Ib }, 0 },
10874   },
10875   {
10876     /* RM_C7_REG_7 */
10877     { "xbeginT",        { Skip_MODRM, Jdqw }, 0 },
10878   },
10879   {
10880     /* RM_0F01_REG_0 */
10881     { "enclv",          { Skip_MODRM }, 0 },
10882     { "vmcall",         { Skip_MODRM }, 0 },
10883     { "vmlaunch",       { Skip_MODRM }, 0 },
10884     { "vmresume",       { Skip_MODRM }, 0 },
10885     { "vmxoff",         { Skip_MODRM }, 0 },
10886     { "pconfig",        { Skip_MODRM }, 0 },
10887   },
10888   {
10889     /* RM_0F01_REG_1 */
10890     { "monitor",        { { OP_Monitor, 0 } }, 0 },
10891     { "mwait",          { { OP_Mwait, 0 } }, 0 },
10892     { "clac",           { Skip_MODRM }, 0 },
10893     { "stac",           { Skip_MODRM }, 0 },
10894     { Bad_Opcode },
10895     { Bad_Opcode },
10896     { Bad_Opcode },
10897     { "encls",          { Skip_MODRM }, 0 },
10898   },
10899   {
10900     /* RM_0F01_REG_2 */
10901     { "xgetbv",         { Skip_MODRM }, 0 },
10902     { "xsetbv",         { Skip_MODRM }, 0 },
10903     { Bad_Opcode },
10904     { Bad_Opcode },
10905     { "vmfunc",         { Skip_MODRM }, 0 },
10906     { "xend",           { Skip_MODRM }, 0 },
10907     { "xtest",          { Skip_MODRM }, 0 },
10908     { "enclu",          { Skip_MODRM }, 0 },
10909   },
10910   {
10911     /* RM_0F01_REG_3 */
10912     { "vmrun",          { Skip_MODRM }, 0 },
10913     { PREFIX_TABLE (PREFIX_0F01_REG_3_RM_1) },
10914     { "vmload",         { Skip_MODRM }, 0 },
10915     { "vmsave",         { Skip_MODRM }, 0 },
10916     { "stgi",           { Skip_MODRM }, 0 },
10917     { "clgi",           { Skip_MODRM }, 0 },
10918     { "skinit",         { Skip_MODRM }, 0 },
10919     { "invlpga",        { Skip_MODRM }, 0 },
10920   },
10921   {
10922     /* RM_0F01_REG_5_MOD_3 */
10923     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_0) },
10924     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_1) },
10925     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_2) },
10926     { Bad_Opcode },
10927     { Bad_Opcode },
10928     { Bad_Opcode },
10929     { "rdpkru",         { Skip_MODRM }, 0 },
10930     { "wrpkru",         { Skip_MODRM }, 0 },
10931   },
10932   {
10933     /* RM_0F01_REG_7_MOD_3 */
10934     { "swapgs",         { Skip_MODRM }, 0  },
10935     { "rdtscp",         { Skip_MODRM }, 0  },
10936     { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_2) },
10937     { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_3) },
10938     { "clzero",         { Skip_MODRM }, 0  },
10939     { "rdpru",          { Skip_MODRM }, 0  },
10940   },
10941   {
10942     /* RM_0F1E_P_1_MOD_3_REG_7 */
10943     { "nopQ",           { Ev }, 0 },
10944     { "nopQ",           { Ev }, 0 },
10945     { "endbr64",        { Skip_MODRM },  PREFIX_OPCODE },
10946     { "endbr32",        { Skip_MODRM },  PREFIX_OPCODE },
10947     { "nopQ",           { Ev }, 0 },
10948     { "nopQ",           { Ev }, 0 },
10949     { "nopQ",           { Ev }, 0 },
10950     { "nopQ",           { Ev }, 0 },
10951   },
10952   {
10953     /* RM_0FAE_REG_6_MOD_3 */
10954     { "mfence",         { Skip_MODRM }, 0 },
10955   },
10956   {
10957     /* RM_0FAE_REG_7_MOD_3 */
10958     { "sfence",         { Skip_MODRM }, 0 },
10959
10960   },
10961 };
10962
10963 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
10964
10965 /* We use the high bit to indicate different name for the same
10966    prefix.  */
10967 #define REP_PREFIX      (0xf3 | 0x100)
10968 #define XACQUIRE_PREFIX (0xf2 | 0x200)
10969 #define XRELEASE_PREFIX (0xf3 | 0x400)
10970 #define BND_PREFIX      (0xf2 | 0x400)
10971 #define NOTRACK_PREFIX  (0x3e | 0x100)
10972
10973 /* Remember if the current op is a jump instruction.  */
10974 static bfd_boolean op_is_jump = FALSE;
10975
10976 static int
10977 ckprefix (void)
10978 {
10979   int newrex, i, length;
10980   rex = 0;
10981   prefixes = 0;
10982   used_prefixes = 0;
10983   rex_used = 0;
10984   last_lock_prefix = -1;
10985   last_repz_prefix = -1;
10986   last_repnz_prefix = -1;
10987   last_data_prefix = -1;
10988   last_addr_prefix = -1;
10989   last_rex_prefix = -1;
10990   last_seg_prefix = -1;
10991   fwait_prefix = -1;
10992   active_seg_prefix = 0;
10993   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
10994     all_prefixes[i] = 0;
10995   i = 0;
10996   length = 0;
10997   /* The maximum instruction length is 15bytes.  */
10998   while (length < MAX_CODE_LENGTH - 1)
10999     {
11000       FETCH_DATA (the_info, codep + 1);
11001       newrex = 0;
11002       switch (*codep)
11003         {
11004         /* REX prefixes family.  */
11005         case 0x40:
11006         case 0x41:
11007         case 0x42:
11008         case 0x43:
11009         case 0x44:
11010         case 0x45:
11011         case 0x46:
11012         case 0x47:
11013         case 0x48:
11014         case 0x49:
11015         case 0x4a:
11016         case 0x4b:
11017         case 0x4c:
11018         case 0x4d:
11019         case 0x4e:
11020         case 0x4f:
11021           if (address_mode == mode_64bit)
11022             newrex = *codep;
11023           else
11024             return 1;
11025           last_rex_prefix = i;
11026           break;
11027         case 0xf3:
11028           prefixes |= PREFIX_REPZ;
11029           last_repz_prefix = i;
11030           break;
11031         case 0xf2:
11032           prefixes |= PREFIX_REPNZ;
11033           last_repnz_prefix = i;
11034           break;
11035         case 0xf0:
11036           prefixes |= PREFIX_LOCK;
11037           last_lock_prefix = i;
11038           break;
11039         case 0x2e:
11040           prefixes |= PREFIX_CS;
11041           last_seg_prefix = i;
11042           active_seg_prefix = PREFIX_CS;
11043           break;
11044         case 0x36:
11045           prefixes |= PREFIX_SS;
11046           last_seg_prefix = i;
11047           active_seg_prefix = PREFIX_SS;
11048           break;
11049         case 0x3e:
11050           prefixes |= PREFIX_DS;
11051           last_seg_prefix = i;
11052           active_seg_prefix = PREFIX_DS;
11053           break;
11054         case 0x26:
11055           prefixes |= PREFIX_ES;
11056           last_seg_prefix = i;
11057           active_seg_prefix = PREFIX_ES;
11058           break;
11059         case 0x64:
11060           prefixes |= PREFIX_FS;
11061           last_seg_prefix = i;
11062           active_seg_prefix = PREFIX_FS;
11063           break;
11064         case 0x65:
11065           prefixes |= PREFIX_GS;
11066           last_seg_prefix = i;
11067           active_seg_prefix = PREFIX_GS;
11068           break;
11069         case 0x66:
11070           prefixes |= PREFIX_DATA;
11071           last_data_prefix = i;
11072           break;
11073         case 0x67:
11074           prefixes |= PREFIX_ADDR;
11075           last_addr_prefix = i;
11076           break;
11077         case FWAIT_OPCODE:
11078           /* fwait is really an instruction.  If there are prefixes
11079              before the fwait, they belong to the fwait, *not* to the
11080              following instruction.  */
11081           fwait_prefix = i;
11082           if (prefixes || rex)
11083             {
11084               prefixes |= PREFIX_FWAIT;
11085               codep++;
11086               /* This ensures that the previous REX prefixes are noticed
11087                  as unused prefixes, as in the return case below.  */
11088               rex_used = rex;
11089               return 1;
11090             }
11091           prefixes = PREFIX_FWAIT;
11092           break;
11093         default:
11094           return 1;
11095         }
11096       /* Rex is ignored when followed by another prefix.  */
11097       if (rex)
11098         {
11099           rex_used = rex;
11100           return 1;
11101         }
11102       if (*codep != FWAIT_OPCODE)
11103         all_prefixes[i++] = *codep;
11104       rex = newrex;
11105       codep++;
11106       length++;
11107     }
11108   return 0;
11109 }
11110
11111 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
11112    prefix byte.  */
11113
11114 static const char *
11115 prefix_name (int pref, int sizeflag)
11116 {
11117   static const char *rexes [16] =
11118     {
11119       "rex",            /* 0x40 */
11120       "rex.B",          /* 0x41 */
11121       "rex.X",          /* 0x42 */
11122       "rex.XB",         /* 0x43 */
11123       "rex.R",          /* 0x44 */
11124       "rex.RB",         /* 0x45 */
11125       "rex.RX",         /* 0x46 */
11126       "rex.RXB",        /* 0x47 */
11127       "rex.W",          /* 0x48 */
11128       "rex.WB",         /* 0x49 */
11129       "rex.WX",         /* 0x4a */
11130       "rex.WXB",        /* 0x4b */
11131       "rex.WR",         /* 0x4c */
11132       "rex.WRB",        /* 0x4d */
11133       "rex.WRX",        /* 0x4e */
11134       "rex.WRXB",       /* 0x4f */
11135     };
11136
11137   switch (pref)
11138     {
11139     /* REX prefixes family.  */
11140     case 0x40:
11141     case 0x41:
11142     case 0x42:
11143     case 0x43:
11144     case 0x44:
11145     case 0x45:
11146     case 0x46:
11147     case 0x47:
11148     case 0x48:
11149     case 0x49:
11150     case 0x4a:
11151     case 0x4b:
11152     case 0x4c:
11153     case 0x4d:
11154     case 0x4e:
11155     case 0x4f:
11156       return rexes [pref - 0x40];
11157     case 0xf3:
11158       return "repz";
11159     case 0xf2:
11160       return "repnz";
11161     case 0xf0:
11162       return "lock";
11163     case 0x2e:
11164       return "cs";
11165     case 0x36:
11166       return "ss";
11167     case 0x3e:
11168       return "ds";
11169     case 0x26:
11170       return "es";
11171     case 0x64:
11172       return "fs";
11173     case 0x65:
11174       return "gs";
11175     case 0x66:
11176       return (sizeflag & DFLAG) ? "data16" : "data32";
11177     case 0x67:
11178       if (address_mode == mode_64bit)
11179         return (sizeflag & AFLAG) ? "addr32" : "addr64";
11180       else
11181         return (sizeflag & AFLAG) ? "addr16" : "addr32";
11182     case FWAIT_OPCODE:
11183       return "fwait";
11184     case REP_PREFIX:
11185       return "rep";
11186     case XACQUIRE_PREFIX:
11187       return "xacquire";
11188     case XRELEASE_PREFIX:
11189       return "xrelease";
11190     case BND_PREFIX:
11191       return "bnd";
11192     case NOTRACK_PREFIX:
11193       return "notrack";
11194     default:
11195       return NULL;
11196     }
11197 }
11198
11199 static char op_out[MAX_OPERANDS][100];
11200 static int op_ad, op_index[MAX_OPERANDS];
11201 static int two_source_ops;
11202 static bfd_vma op_address[MAX_OPERANDS];
11203 static bfd_vma op_riprel[MAX_OPERANDS];
11204 static bfd_vma start_pc;
11205
11206 /*
11207  *   On the 386's of 1988, the maximum length of an instruction is 15 bytes.
11208  *   (see topic "Redundant prefixes" in the "Differences from 8086"
11209  *   section of the "Virtual 8086 Mode" chapter.)
11210  * 'pc' should be the address of this instruction, it will
11211  *   be used to print the target address if this is a relative jump or call
11212  * The function returns the length of this instruction in bytes.
11213  */
11214
11215 static char intel_syntax;
11216 static char intel_mnemonic = !SYSV386_COMPAT;
11217 static char open_char;
11218 static char close_char;
11219 static char separator_char;
11220 static char scale_char;
11221
11222 enum x86_64_isa
11223 {
11224   amd64 = 1,
11225   intel64
11226 };
11227
11228 static enum x86_64_isa isa64;
11229
11230 /* Here for backwards compatibility.  When gdb stops using
11231    print_insn_i386_att and print_insn_i386_intel these functions can
11232    disappear, and print_insn_i386 be merged into print_insn.  */
11233 int
11234 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
11235 {
11236   intel_syntax = 0;
11237
11238   return print_insn (pc, info);
11239 }
11240
11241 int
11242 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
11243 {
11244   intel_syntax = 1;
11245
11246   return print_insn (pc, info);
11247 }
11248
11249 int
11250 print_insn_i386 (bfd_vma pc, disassemble_info *info)
11251 {
11252   intel_syntax = -1;
11253
11254   return print_insn (pc, info);
11255 }
11256
11257 void
11258 print_i386_disassembler_options (FILE *stream)
11259 {
11260   fprintf (stream, _("\n\
11261 The following i386/x86-64 specific disassembler options are supported for use\n\
11262 with the -M switch (multiple options should be separated by commas):\n"));
11263
11264   fprintf (stream, _("  x86-64      Disassemble in 64bit mode\n"));
11265   fprintf (stream, _("  i386        Disassemble in 32bit mode\n"));
11266   fprintf (stream, _("  i8086       Disassemble in 16bit mode\n"));
11267   fprintf (stream, _("  att         Display instruction in AT&T syntax\n"));
11268   fprintf (stream, _("  intel       Display instruction in Intel syntax\n"));
11269   fprintf (stream, _("  att-mnemonic\n"
11270                      "              Display instruction in AT&T mnemonic\n"));
11271   fprintf (stream, _("  intel-mnemonic\n"
11272                      "              Display instruction in Intel mnemonic\n"));
11273   fprintf (stream, _("  addr64      Assume 64bit address size\n"));
11274   fprintf (stream, _("  addr32      Assume 32bit address size\n"));
11275   fprintf (stream, _("  addr16      Assume 16bit address size\n"));
11276   fprintf (stream, _("  data32      Assume 32bit data size\n"));
11277   fprintf (stream, _("  data16      Assume 16bit data size\n"));
11278   fprintf (stream, _("  suffix      Always display instruction suffix in AT&T syntax\n"));
11279   fprintf (stream, _("  amd64       Display instruction in AMD64 ISA\n"));
11280   fprintf (stream, _("  intel64     Display instruction in Intel64 ISA\n"));
11281 }
11282
11283 /* Bad opcode.  */
11284 static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 };
11285
11286 /* Get a pointer to struct dis386 with a valid name.  */
11287
11288 static const struct dis386 *
11289 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
11290 {
11291   int vindex, vex_table_index;
11292
11293   if (dp->name != NULL)
11294     return dp;
11295
11296   switch (dp->op[0].bytemode)
11297     {
11298     case USE_REG_TABLE:
11299       dp = &reg_table[dp->op[1].bytemode][modrm.reg];
11300       break;
11301
11302     case USE_MOD_TABLE:
11303       vindex = modrm.mod == 0x3 ? 1 : 0;
11304       dp = &mod_table[dp->op[1].bytemode][vindex];
11305       break;
11306
11307     case USE_RM_TABLE:
11308       dp = &rm_table[dp->op[1].bytemode][modrm.rm];
11309       break;
11310
11311     case USE_PREFIX_TABLE:
11312       if (need_vex)
11313         {
11314           /* The prefix in VEX is implicit.  */
11315           switch (vex.prefix)
11316             {
11317             case 0:
11318               vindex = 0;
11319               break;
11320             case REPE_PREFIX_OPCODE:
11321               vindex = 1;
11322               break;
11323             case DATA_PREFIX_OPCODE:
11324               vindex = 2;
11325               break;
11326             case REPNE_PREFIX_OPCODE:
11327               vindex = 3;
11328               break;
11329             default:
11330               abort ();
11331               break;
11332             }
11333         }
11334       else
11335         {
11336           int last_prefix = -1;
11337           int prefix = 0;
11338           vindex = 0;
11339           /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
11340              When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
11341              last one wins.  */
11342           if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
11343             {
11344               if (last_repz_prefix > last_repnz_prefix)
11345                 {
11346                   vindex = 1;
11347                   prefix = PREFIX_REPZ;
11348                   last_prefix = last_repz_prefix;
11349                 }
11350               else
11351                 {
11352                   vindex = 3;
11353                   prefix = PREFIX_REPNZ;
11354                   last_prefix = last_repnz_prefix;
11355                 }
11356
11357               /* Check if prefix should be ignored.  */
11358               if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement
11359                      & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT)
11360                    & prefix) != 0)
11361                 vindex = 0;
11362             }
11363
11364           if (vindex == 0 && (prefixes & PREFIX_DATA) != 0)
11365             {
11366               vindex = 2;
11367               prefix = PREFIX_DATA;
11368               last_prefix = last_data_prefix;
11369             }
11370
11371           if (vindex != 0)
11372             {
11373               used_prefixes |= prefix;
11374               all_prefixes[last_prefix] = 0;
11375             }
11376         }
11377       dp = &prefix_table[dp->op[1].bytemode][vindex];
11378       break;
11379
11380     case USE_X86_64_TABLE:
11381       vindex = address_mode == mode_64bit ? 1 : 0;
11382       dp = &x86_64_table[dp->op[1].bytemode][vindex];
11383       break;
11384
11385     case USE_3BYTE_TABLE:
11386       FETCH_DATA (info, codep + 2);
11387       vindex = *codep++;
11388       dp = &three_byte_table[dp->op[1].bytemode][vindex];
11389       end_codep = codep;
11390       modrm.mod = (*codep >> 6) & 3;
11391       modrm.reg = (*codep >> 3) & 7;
11392       modrm.rm = *codep & 7;
11393       break;
11394
11395     case USE_VEX_LEN_TABLE:
11396       if (!need_vex)
11397         abort ();
11398
11399       switch (vex.length)
11400         {
11401         case 128:
11402           vindex = 0;
11403           break;
11404         case 256:
11405           vindex = 1;
11406           break;
11407         default:
11408           abort ();
11409           break;
11410         }
11411
11412       dp = &vex_len_table[dp->op[1].bytemode][vindex];
11413       break;
11414
11415     case USE_EVEX_LEN_TABLE:
11416       if (!vex.evex)
11417         abort ();
11418
11419       switch (vex.length)
11420         {
11421         case 128:
11422           vindex = 0;
11423           break;
11424         case 256:
11425           vindex = 1;
11426           break;
11427         case 512:
11428           vindex = 2;
11429           break;
11430         default:
11431           abort ();
11432           break;
11433         }
11434
11435       dp = &evex_len_table[dp->op[1].bytemode][vindex];
11436       break;
11437
11438     case USE_XOP_8F_TABLE:
11439       FETCH_DATA (info, codep + 3);
11440       rex = ~(*codep >> 5) & 0x7;
11441
11442       /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm".  */
11443       switch ((*codep & 0x1f))
11444         {
11445         default:
11446           dp = &bad_opcode;
11447           return dp;
11448         case 0x8:
11449           vex_table_index = XOP_08;
11450           break;
11451         case 0x9:
11452           vex_table_index = XOP_09;
11453           break;
11454         case 0xa:
11455           vex_table_index = XOP_0A;
11456           break;
11457         }
11458       codep++;
11459       vex.w = *codep & 0x80;
11460       if (vex.w && address_mode == mode_64bit)
11461         rex |= REX_W;
11462
11463       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11464       if (address_mode != mode_64bit)
11465         {
11466           /* In 16/32-bit mode REX_B is silently ignored.  */
11467           rex &= ~REX_B;
11468         }
11469
11470       vex.length = (*codep & 0x4) ? 256 : 128;
11471       switch ((*codep & 0x3))
11472         {
11473         case 0:
11474           break;
11475         case 1:
11476           vex.prefix = DATA_PREFIX_OPCODE;
11477           break;
11478         case 2:
11479           vex.prefix = REPE_PREFIX_OPCODE;
11480           break;
11481         case 3:
11482           vex.prefix = REPNE_PREFIX_OPCODE;
11483           break;
11484         }
11485       need_vex = 1;
11486       need_vex_reg = 1;
11487       codep++;
11488       vindex = *codep++;
11489       dp = &xop_table[vex_table_index][vindex];
11490
11491       end_codep = codep;
11492       FETCH_DATA (info, codep + 1);
11493       modrm.mod = (*codep >> 6) & 3;
11494       modrm.reg = (*codep >> 3) & 7;
11495       modrm.rm = *codep & 7;
11496       break;
11497
11498     case USE_VEX_C4_TABLE:
11499       /* VEX prefix.  */
11500       FETCH_DATA (info, codep + 3);
11501       rex = ~(*codep >> 5) & 0x7;
11502       switch ((*codep & 0x1f))
11503         {
11504         default:
11505           dp = &bad_opcode;
11506           return dp;
11507         case 0x1:
11508           vex_table_index = VEX_0F;
11509           break;
11510         case 0x2:
11511           vex_table_index = VEX_0F38;
11512           break;
11513         case 0x3:
11514           vex_table_index = VEX_0F3A;
11515           break;
11516         }
11517       codep++;
11518       vex.w = *codep & 0x80;
11519       if (address_mode == mode_64bit)
11520         {
11521           if (vex.w)
11522             rex |= REX_W;
11523         }
11524       else
11525         {
11526           /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
11527              is ignored, other REX bits are 0 and the highest bit in
11528              VEX.vvvv is also ignored (but we mustn't clear it here).  */
11529           rex = 0;
11530         }
11531       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11532       vex.length = (*codep & 0x4) ? 256 : 128;
11533       switch ((*codep & 0x3))
11534         {
11535         case 0:
11536           break;
11537         case 1:
11538           vex.prefix = DATA_PREFIX_OPCODE;
11539           break;
11540         case 2:
11541           vex.prefix = REPE_PREFIX_OPCODE;
11542           break;
11543         case 3:
11544           vex.prefix = REPNE_PREFIX_OPCODE;
11545           break;
11546         }
11547       need_vex = 1;
11548       need_vex_reg = 1;
11549       codep++;
11550       vindex = *codep++;
11551       dp = &vex_table[vex_table_index][vindex];
11552       end_codep = codep;
11553       /* There is no MODRM byte for VEX0F 77.  */
11554       if (vex_table_index != VEX_0F || vindex != 0x77)
11555         {
11556           FETCH_DATA (info, codep + 1);
11557           modrm.mod = (*codep >> 6) & 3;
11558           modrm.reg = (*codep >> 3) & 7;
11559           modrm.rm = *codep & 7;
11560         }
11561       break;
11562
11563     case USE_VEX_C5_TABLE:
11564       /* VEX prefix.  */
11565       FETCH_DATA (info, codep + 2);
11566       rex = (*codep & 0x80) ? 0 : REX_R;
11567
11568       /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
11569          VEX.vvvv is 1.  */
11570       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11571       vex.length = (*codep & 0x4) ? 256 : 128;
11572       switch ((*codep & 0x3))
11573         {
11574         case 0:
11575           break;
11576         case 1:
11577           vex.prefix = DATA_PREFIX_OPCODE;
11578           break;
11579         case 2:
11580           vex.prefix = REPE_PREFIX_OPCODE;
11581           break;
11582         case 3:
11583           vex.prefix = REPNE_PREFIX_OPCODE;
11584           break;
11585         }
11586       need_vex = 1;
11587       need_vex_reg = 1;
11588       codep++;
11589       vindex = *codep++;
11590       dp = &vex_table[dp->op[1].bytemode][vindex];
11591       end_codep = codep;
11592       /* There is no MODRM byte for VEX 77.  */
11593       if (vindex != 0x77)
11594         {
11595           FETCH_DATA (info, codep + 1);
11596           modrm.mod = (*codep >> 6) & 3;
11597           modrm.reg = (*codep >> 3) & 7;
11598           modrm.rm = *codep & 7;
11599         }
11600       break;
11601
11602     case USE_VEX_W_TABLE:
11603       if (!need_vex)
11604         abort ();
11605
11606       dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
11607       break;
11608
11609     case USE_EVEX_TABLE:
11610       two_source_ops = 0;
11611       /* EVEX prefix.  */
11612       vex.evex = 1;
11613       FETCH_DATA (info, codep + 4);
11614       /* The first byte after 0x62.  */
11615       rex = ~(*codep >> 5) & 0x7;
11616       vex.r = *codep & 0x10;
11617       switch ((*codep & 0xf))
11618         {
11619         default:
11620           return &bad_opcode;
11621         case 0x1:
11622           vex_table_index = EVEX_0F;
11623           break;
11624         case 0x2:
11625           vex_table_index = EVEX_0F38;
11626           break;
11627         case 0x3:
11628           vex_table_index = EVEX_0F3A;
11629           break;
11630         }
11631
11632       /* The second byte after 0x62.  */
11633       codep++;
11634       vex.w = *codep & 0x80;
11635       if (vex.w && address_mode == mode_64bit)
11636         rex |= REX_W;
11637
11638       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11639
11640       /* The U bit.  */
11641       if (!(*codep & 0x4))
11642         return &bad_opcode;
11643
11644       switch ((*codep & 0x3))
11645         {
11646         case 0:
11647           break;
11648         case 1:
11649           vex.prefix = DATA_PREFIX_OPCODE;
11650           break;
11651         case 2:
11652           vex.prefix = REPE_PREFIX_OPCODE;
11653           break;
11654         case 3:
11655           vex.prefix = REPNE_PREFIX_OPCODE;
11656           break;
11657         }
11658
11659       /* The third byte after 0x62.  */
11660       codep++;
11661
11662       /* Remember the static rounding bits.  */
11663       vex.ll = (*codep >> 5) & 3;
11664       vex.b = (*codep & 0x10) != 0;
11665
11666       vex.v = *codep & 0x8;
11667       vex.mask_register_specifier = *codep & 0x7;
11668       vex.zeroing = *codep & 0x80;
11669
11670       if (address_mode != mode_64bit)
11671         {
11672           /* In 16/32-bit mode silently ignore following bits.  */
11673           rex &= ~REX_B;
11674           vex.r = 1;
11675           vex.v = 1;
11676         }
11677
11678       need_vex = 1;
11679       need_vex_reg = 1;
11680       codep++;
11681       vindex = *codep++;
11682       dp = &evex_table[vex_table_index][vindex];
11683       end_codep = codep;
11684       FETCH_DATA (info, codep + 1);
11685       modrm.mod = (*codep >> 6) & 3;
11686       modrm.reg = (*codep >> 3) & 7;
11687       modrm.rm = *codep & 7;
11688
11689       /* Set vector length.  */
11690       if (modrm.mod == 3 && vex.b)
11691         vex.length = 512;
11692       else
11693         {
11694           switch (vex.ll)
11695             {
11696             case 0x0:
11697               vex.length = 128;
11698               break;
11699             case 0x1:
11700               vex.length = 256;
11701               break;
11702             case 0x2:
11703               vex.length = 512;
11704               break;
11705             default:
11706               return &bad_opcode;
11707             }
11708         }
11709       break;
11710
11711     case 0:
11712       dp = &bad_opcode;
11713       break;
11714
11715     default:
11716       abort ();
11717     }
11718
11719   if (dp->name != NULL)
11720     return dp;
11721   else
11722     return get_valid_dis386 (dp, info);
11723 }
11724
11725 static void
11726 get_sib (disassemble_info *info, int sizeflag)
11727 {
11728   /* If modrm.mod == 3, operand must be register.  */
11729   if (need_modrm
11730       && ((sizeflag & AFLAG) || address_mode == mode_64bit)
11731       && modrm.mod != 3
11732       && modrm.rm == 4)
11733     {
11734       FETCH_DATA (info, codep + 2);
11735       sib.index = (codep [1] >> 3) & 7;
11736       sib.scale = (codep [1] >> 6) & 3;
11737       sib.base = codep [1] & 7;
11738     }
11739 }
11740
11741 static int
11742 print_insn (bfd_vma pc, disassemble_info *info)
11743 {
11744   const struct dis386 *dp;
11745   int i;
11746   char *op_txt[MAX_OPERANDS];
11747   int needcomma;
11748   int sizeflag, orig_sizeflag;
11749   const char *p;
11750   struct dis_private priv;
11751   int prefix_length;
11752
11753   priv.orig_sizeflag = AFLAG | DFLAG;
11754   if ((info->mach & bfd_mach_i386_i386) != 0)
11755     address_mode = mode_32bit;
11756   else if (info->mach == bfd_mach_i386_i8086)
11757     {
11758       address_mode = mode_16bit;
11759       priv.orig_sizeflag = 0;
11760     }
11761   else
11762     address_mode = mode_64bit;
11763
11764   if (intel_syntax == (char) -1)
11765     intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0;
11766
11767   for (p = info->disassembler_options; p != NULL; )
11768     {
11769       if (CONST_STRNEQ (p, "amd64"))
11770         isa64 = amd64;
11771       else if (CONST_STRNEQ (p, "intel64"))
11772         isa64 = intel64;
11773       else if (CONST_STRNEQ (p, "x86-64"))
11774         {
11775           address_mode = mode_64bit;
11776           priv.orig_sizeflag |= AFLAG | DFLAG;
11777         }
11778       else if (CONST_STRNEQ (p, "i386"))
11779         {
11780           address_mode = mode_32bit;
11781           priv.orig_sizeflag |= AFLAG | DFLAG;
11782         }
11783       else if (CONST_STRNEQ (p, "i8086"))
11784         {
11785           address_mode = mode_16bit;
11786           priv.orig_sizeflag &= ~(AFLAG | DFLAG);
11787         }
11788       else if (CONST_STRNEQ (p, "intel"))
11789         {
11790           intel_syntax = 1;
11791           if (CONST_STRNEQ (p + 5, "-mnemonic"))
11792             intel_mnemonic = 1;
11793         }
11794       else if (CONST_STRNEQ (p, "att"))
11795         {
11796           intel_syntax = 0;
11797           if (CONST_STRNEQ (p + 3, "-mnemonic"))
11798             intel_mnemonic = 0;
11799         }
11800       else if (CONST_STRNEQ (p, "addr"))
11801         {
11802           if (address_mode == mode_64bit)
11803             {
11804               if (p[4] == '3' && p[5] == '2')
11805                 priv.orig_sizeflag &= ~AFLAG;
11806               else if (p[4] == '6' && p[5] == '4')
11807                 priv.orig_sizeflag |= AFLAG;
11808             }
11809           else
11810             {
11811               if (p[4] == '1' && p[5] == '6')
11812                 priv.orig_sizeflag &= ~AFLAG;
11813               else if (p[4] == '3' && p[5] == '2')
11814                 priv.orig_sizeflag |= AFLAG;
11815             }
11816         }
11817       else if (CONST_STRNEQ (p, "data"))
11818         {
11819           if (p[4] == '1' && p[5] == '6')
11820             priv.orig_sizeflag &= ~DFLAG;
11821           else if (p[4] == '3' && p[5] == '2')
11822             priv.orig_sizeflag |= DFLAG;
11823         }
11824       else if (CONST_STRNEQ (p, "suffix"))
11825         priv.orig_sizeflag |= SUFFIX_ALWAYS;
11826
11827       p = strchr (p, ',');
11828       if (p != NULL)
11829         p++;
11830     }
11831
11832   if (address_mode == mode_64bit && sizeof (bfd_vma) < 8)
11833     {
11834       (*info->fprintf_func) (info->stream,
11835                              _("64-bit address is disabled"));
11836       return -1;
11837     }
11838
11839   if (intel_syntax)
11840     {
11841       names64 = intel_names64;
11842       names32 = intel_names32;
11843       names16 = intel_names16;
11844       names8 = intel_names8;
11845       names8rex = intel_names8rex;
11846       names_seg = intel_names_seg;
11847       names_mm = intel_names_mm;
11848       names_bnd = intel_names_bnd;
11849       names_xmm = intel_names_xmm;
11850       names_ymm = intel_names_ymm;
11851       names_zmm = intel_names_zmm;
11852       index64 = intel_index64;
11853       index32 = intel_index32;
11854       names_mask = intel_names_mask;
11855       index16 = intel_index16;
11856       open_char = '[';
11857       close_char = ']';
11858       separator_char = '+';
11859       scale_char = '*';
11860     }
11861   else
11862     {
11863       names64 = att_names64;
11864       names32 = att_names32;
11865       names16 = att_names16;
11866       names8 = att_names8;
11867       names8rex = att_names8rex;
11868       names_seg = att_names_seg;
11869       names_mm = att_names_mm;
11870       names_bnd = att_names_bnd;
11871       names_xmm = att_names_xmm;
11872       names_ymm = att_names_ymm;
11873       names_zmm = att_names_zmm;
11874       index64 = att_index64;
11875       index32 = att_index32;
11876       names_mask = att_names_mask;
11877       index16 = att_index16;
11878       open_char = '(';
11879       close_char =  ')';
11880       separator_char = ',';
11881       scale_char = ',';
11882     }
11883
11884   /* The output looks better if we put 7 bytes on a line, since that
11885      puts most long word instructions on a single line.  Use 8 bytes
11886      for Intel L1OM.  */
11887   if ((info->mach & bfd_mach_l1om) != 0)
11888     info->bytes_per_line = 8;
11889   else
11890     info->bytes_per_line = 7;
11891
11892   info->private_data = &priv;
11893   priv.max_fetched = priv.the_buffer;
11894   priv.insn_start = pc;
11895
11896   obuf[0] = 0;
11897   for (i = 0; i < MAX_OPERANDS; ++i)
11898     {
11899       op_out[i][0] = 0;
11900       op_index[i] = -1;
11901     }
11902
11903   the_info = info;
11904   start_pc = pc;
11905   start_codep = priv.the_buffer;
11906   codep = priv.the_buffer;
11907
11908   if (OPCODES_SIGSETJMP (priv.bailout) != 0)
11909     {
11910       const char *name;
11911
11912       /* Getting here means we tried for data but didn't get it.  That
11913          means we have an incomplete instruction of some sort.  Just
11914          print the first byte as a prefix or a .byte pseudo-op.  */
11915       if (codep > priv.the_buffer)
11916         {
11917           name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
11918           if (name != NULL)
11919             (*info->fprintf_func) (info->stream, "%s", name);
11920           else
11921             {
11922               /* Just print the first byte as a .byte instruction.  */
11923               (*info->fprintf_func) (info->stream, ".byte 0x%x",
11924                                      (unsigned int) priv.the_buffer[0]);
11925             }
11926
11927           return 1;
11928         }
11929
11930       return -1;
11931     }
11932
11933   obufp = obuf;
11934   sizeflag = priv.orig_sizeflag;
11935
11936   if (!ckprefix () || rex_used)
11937     {
11938       /* Too many prefixes or unused REX prefixes.  */
11939       for (i = 0;
11940            i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i];
11941            i++)
11942         (*info->fprintf_func) (info->stream, "%s%s",
11943                                i == 0 ? "" : " ",
11944                                prefix_name (all_prefixes[i], sizeflag));
11945       return i;
11946     }
11947
11948   insn_codep = codep;
11949
11950   FETCH_DATA (info, codep + 1);
11951   two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
11952
11953   if (((prefixes & PREFIX_FWAIT)
11954        && ((*codep < 0xd8) || (*codep > 0xdf))))
11955     {
11956       /* Handle prefixes before fwait.  */
11957       for (i = 0; i < fwait_prefix && all_prefixes[i];
11958            i++)
11959         (*info->fprintf_func) (info->stream, "%s ",
11960                                prefix_name (all_prefixes[i], sizeflag));
11961       (*info->fprintf_func) (info->stream, "fwait");
11962       return i + 1;
11963     }
11964
11965   if (*codep == 0x0f)
11966     {
11967       unsigned char threebyte;
11968
11969       codep++;
11970       FETCH_DATA (info, codep + 1);
11971       threebyte = *codep;
11972       dp = &dis386_twobyte[threebyte];
11973       need_modrm = twobyte_has_modrm[*codep];
11974       codep++;
11975     }
11976   else
11977     {
11978       dp = &dis386[*codep];
11979       need_modrm = onebyte_has_modrm[*codep];
11980       codep++;
11981     }
11982
11983   /* Save sizeflag for printing the extra prefixes later before updating
11984      it for mnemonic and operand processing.  The prefix names depend
11985      only on the address mode.  */
11986   orig_sizeflag = sizeflag;
11987   if (prefixes & PREFIX_ADDR)
11988     sizeflag ^= AFLAG;
11989   if ((prefixes & PREFIX_DATA))
11990     sizeflag ^= DFLAG;
11991
11992   end_codep = codep;
11993   if (need_modrm)
11994     {
11995       FETCH_DATA (info, codep + 1);
11996       modrm.mod = (*codep >> 6) & 3;
11997       modrm.reg = (*codep >> 3) & 7;
11998       modrm.rm = *codep & 7;
11999     }
12000
12001   need_vex = 0;
12002   need_vex_reg = 0;
12003   vex_w_done = 0;
12004   memset (&vex, 0, sizeof (vex));
12005
12006   if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
12007     {
12008       get_sib (info, sizeflag);
12009       dofloat (sizeflag);
12010     }
12011   else
12012     {
12013       dp = get_valid_dis386 (dp, info);
12014       if (dp != NULL && putop (dp->name, sizeflag) == 0)
12015         {
12016           get_sib (info, sizeflag);
12017           for (i = 0; i < MAX_OPERANDS; ++i)
12018             {
12019               obufp = op_out[i];
12020               op_ad = MAX_OPERANDS - 1 - i;
12021               if (dp->op[i].rtn)
12022                 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
12023               /* For EVEX instruction after the last operand masking
12024                  should be printed.  */
12025               if (i == 0 && vex.evex)
12026                 {
12027                   /* Don't print {%k0}.  */
12028                   if (vex.mask_register_specifier)
12029                     {
12030                       oappend ("{");
12031                       oappend (names_mask[vex.mask_register_specifier]);
12032                       oappend ("}");
12033                     }
12034                   if (vex.zeroing)
12035                     oappend ("{z}");
12036                 }
12037             }
12038         }
12039     }
12040
12041   /* Clear instruction information.  */
12042   if (the_info)
12043     {
12044       the_info->insn_info_valid = 0;
12045       the_info->branch_delay_insns = 0;
12046       the_info->data_size = 0;
12047       the_info->insn_type = dis_noninsn;
12048       the_info->target = 0;
12049       the_info->target2 = 0;
12050     }
12051
12052   /* Reset jump operation indicator.  */
12053   op_is_jump = FALSE;
12054
12055   {
12056     int jump_detection = 0;
12057
12058     /* Extract flags.  */
12059     for (i = 0; i < MAX_OPERANDS; ++i)
12060       {
12061         if ((dp->op[i].rtn == OP_J)
12062             || (dp->op[i].rtn == OP_indirE))
12063           jump_detection |= 1;
12064         else if ((dp->op[i].rtn == BND_Fixup)
12065                  || (!dp->op[i].rtn && !dp->op[i].bytemode))
12066           jump_detection |= 2;
12067         else if ((dp->op[i].bytemode == cond_jump_mode)
12068                  || (dp->op[i].bytemode == loop_jcxz_mode))
12069           jump_detection |= 4;
12070       }
12071
12072     /* Determine if this is a jump or branch.  */
12073     if ((jump_detection & 0x3) == 0x3)
12074       {
12075         op_is_jump = TRUE;
12076         if (jump_detection & 0x4)
12077           the_info->insn_type = dis_condbranch;
12078         else
12079           the_info->insn_type =
12080             (dp->name && !strncmp(dp->name, "call", 4))
12081             ? dis_jsr : dis_branch;
12082       }
12083   }
12084
12085   /* If VEX.vvvv and EVEX.vvvv are unused, they must be all 1s, which
12086      are all 0s in inverted form.  */
12087   if (need_vex && vex.register_specifier != 0)
12088     {
12089       (*info->fprintf_func) (info->stream, "(bad)");
12090       return end_codep - priv.the_buffer;
12091     }
12092
12093   /* Check if the REX prefix is used.  */
12094   if ((rex ^ rex_used) == 0 && !need_vex && last_rex_prefix >= 0)
12095     all_prefixes[last_rex_prefix] = 0;
12096
12097   /* Check if the SEG prefix is used.  */
12098   if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
12099                    | PREFIX_FS | PREFIX_GS)) != 0
12100       && (used_prefixes & active_seg_prefix) != 0)
12101     all_prefixes[last_seg_prefix] = 0;
12102
12103   /* Check if the ADDR prefix is used.  */
12104   if ((prefixes & PREFIX_ADDR) != 0
12105       && (used_prefixes & PREFIX_ADDR) != 0)
12106     all_prefixes[last_addr_prefix] = 0;
12107
12108   /* Check if the DATA prefix is used.  */
12109   if ((prefixes & PREFIX_DATA) != 0
12110       && (used_prefixes & PREFIX_DATA) != 0
12111       && !need_vex)
12112     all_prefixes[last_data_prefix] = 0;
12113
12114   /* Print the extra prefixes.  */
12115   prefix_length = 0;
12116   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
12117     if (all_prefixes[i])
12118       {
12119         const char *name;
12120         name = prefix_name (all_prefixes[i], orig_sizeflag);
12121         if (name == NULL)
12122           abort ();
12123         prefix_length += strlen (name) + 1;
12124         (*info->fprintf_func) (info->stream, "%s ", name);
12125       }
12126
12127   /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
12128      unused, opcode is invalid.  Since the PREFIX_DATA prefix may be
12129      used by putop and MMX/SSE operand and may be overriden by the
12130      PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
12131      separately.  */
12132   if (dp->prefix_requirement == PREFIX_OPCODE
12133       && (((need_vex
12134             ? vex.prefix == REPE_PREFIX_OPCODE
12135               || vex.prefix == REPNE_PREFIX_OPCODE
12136             : (prefixes
12137                & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
12138            && (used_prefixes
12139                & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
12140           || (((need_vex
12141                 ? vex.prefix == DATA_PREFIX_OPCODE
12142                 : ((prefixes
12143                     & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
12144                    == PREFIX_DATA))
12145                && (used_prefixes & PREFIX_DATA) == 0))
12146           || (vex.evex && !vex.w != !(used_prefixes & PREFIX_DATA))))
12147     {
12148       (*info->fprintf_func) (info->stream, "(bad)");
12149       return end_codep - priv.the_buffer;
12150     }
12151
12152   /* Check maximum code length.  */
12153   if ((codep - start_codep) > MAX_CODE_LENGTH)
12154     {
12155       (*info->fprintf_func) (info->stream, "(bad)");
12156       return MAX_CODE_LENGTH;
12157     }
12158
12159   obufp = mnemonicendp;
12160   for (i = strlen (obuf) + prefix_length; i < 6; i++)
12161     oappend (" ");
12162   oappend (" ");
12163   (*info->fprintf_func) (info->stream, "%s", obuf);
12164
12165   /* The enter and bound instructions are printed with operands in the same
12166      order as the intel book; everything else is printed in reverse order.  */
12167   if (intel_syntax || two_source_ops)
12168     {
12169       bfd_vma riprel;
12170
12171       for (i = 0; i < MAX_OPERANDS; ++i)
12172         op_txt[i] = op_out[i];
12173
12174       if (intel_syntax && dp && dp->op[2].rtn == OP_Rounding
12175           && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL)
12176         {
12177           op_txt[2] = op_out[3];
12178           op_txt[3] = op_out[2];
12179         }
12180
12181       for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
12182         {
12183           op_ad = op_index[i];
12184           op_index[i] = op_index[MAX_OPERANDS - 1 - i];
12185           op_index[MAX_OPERANDS - 1 - i] = op_ad;
12186           riprel = op_riprel[i];
12187           op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
12188           op_riprel[MAX_OPERANDS - 1 - i] = riprel;
12189         }
12190     }
12191   else
12192     {
12193       for (i = 0; i < MAX_OPERANDS; ++i)
12194         op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
12195     }
12196
12197   needcomma = 0;
12198   for (i = 0; i < MAX_OPERANDS; ++i)
12199     if (*op_txt[i])
12200       {
12201         if (needcomma)
12202           (*info->fprintf_func) (info->stream, ",");
12203         if (op_index[i] != -1 && !op_riprel[i])
12204           {
12205             bfd_vma target = (bfd_vma) op_address[op_index[i]];
12206
12207             if (the_info && op_is_jump)
12208               {
12209                 the_info->insn_info_valid = 1;
12210                 the_info->branch_delay_insns = 0;
12211                 the_info->data_size = 0;
12212                 the_info->target = target;
12213                 the_info->target2 = 0;
12214               }
12215             (*info->print_address_func) (target, info);
12216           }
12217         else
12218           (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
12219         needcomma = 1;
12220       }
12221
12222   for (i = 0; i < MAX_OPERANDS; i++)
12223     if (op_index[i] != -1 && op_riprel[i])
12224       {
12225         (*info->fprintf_func) (info->stream, "        # ");
12226         (*info->print_address_func) ((bfd_vma) (start_pc + (codep - start_codep)
12227                                                 + op_address[op_index[i]]), info);
12228         break;
12229       }
12230   return codep - priv.the_buffer;
12231 }
12232
12233 static const char *float_mem[] = {
12234   /* d8 */
12235   "fadd{s|}",
12236   "fmul{s|}",
12237   "fcom{s|}",
12238   "fcomp{s|}",
12239   "fsub{s|}",
12240   "fsubr{s|}",
12241   "fdiv{s|}",
12242   "fdivr{s|}",
12243   /* d9 */
12244   "fld{s|}",
12245   "(bad)",
12246   "fst{s|}",
12247   "fstp{s|}",
12248   "fldenv{C|C}",
12249   "fldcw",
12250   "fNstenv{C|C}",
12251   "fNstcw",
12252   /* da */
12253   "fiadd{l|}",
12254   "fimul{l|}",
12255   "ficom{l|}",
12256   "ficomp{l|}",
12257   "fisub{l|}",
12258   "fisubr{l|}",
12259   "fidiv{l|}",
12260   "fidivr{l|}",
12261   /* db */
12262   "fild{l|}",
12263   "fisttp{l|}",
12264   "fist{l|}",
12265   "fistp{l|}",
12266   "(bad)",
12267   "fld{t|}",
12268   "(bad)",
12269   "fstp{t|}",
12270   /* dc */
12271   "fadd{l|}",
12272   "fmul{l|}",
12273   "fcom{l|}",
12274   "fcomp{l|}",
12275   "fsub{l|}",
12276   "fsubr{l|}",
12277   "fdiv{l|}",
12278   "fdivr{l|}",
12279   /* dd */
12280   "fld{l|}",
12281   "fisttp{ll|}",
12282   "fst{l||}",
12283   "fstp{l|}",
12284   "frstor{C|C}",
12285   "(bad)",
12286   "fNsave{C|C}",
12287   "fNstsw",
12288   /* de */
12289   "fiadd{s|}",
12290   "fimul{s|}",
12291   "ficom{s|}",
12292   "ficomp{s|}",
12293   "fisub{s|}",
12294   "fisubr{s|}",
12295   "fidiv{s|}",
12296   "fidivr{s|}",
12297   /* df */
12298   "fild{s|}",
12299   "fisttp{s|}",
12300   "fist{s|}",
12301   "fistp{s|}",
12302   "fbld",
12303   "fild{ll|}",
12304   "fbstp",
12305   "fistp{ll|}",
12306 };
12307
12308 static const unsigned char float_mem_mode[] = {
12309   /* d8 */
12310   d_mode,
12311   d_mode,
12312   d_mode,
12313   d_mode,
12314   d_mode,
12315   d_mode,
12316   d_mode,
12317   d_mode,
12318   /* d9 */
12319   d_mode,
12320   0,
12321   d_mode,
12322   d_mode,
12323   0,
12324   w_mode,
12325   0,
12326   w_mode,
12327   /* da */
12328   d_mode,
12329   d_mode,
12330   d_mode,
12331   d_mode,
12332   d_mode,
12333   d_mode,
12334   d_mode,
12335   d_mode,
12336   /* db */
12337   d_mode,
12338   d_mode,
12339   d_mode,
12340   d_mode,
12341   0,
12342   t_mode,
12343   0,
12344   t_mode,
12345   /* dc */
12346   q_mode,
12347   q_mode,
12348   q_mode,
12349   q_mode,
12350   q_mode,
12351   q_mode,
12352   q_mode,
12353   q_mode,
12354   /* dd */
12355   q_mode,
12356   q_mode,
12357   q_mode,
12358   q_mode,
12359   0,
12360   0,
12361   0,
12362   w_mode,
12363   /* de */
12364   w_mode,
12365   w_mode,
12366   w_mode,
12367   w_mode,
12368   w_mode,
12369   w_mode,
12370   w_mode,
12371   w_mode,
12372   /* df */
12373   w_mode,
12374   w_mode,
12375   w_mode,
12376   w_mode,
12377   t_mode,
12378   q_mode,
12379   t_mode,
12380   q_mode
12381 };
12382
12383 #define ST { OP_ST, 0 }
12384 #define STi { OP_STi, 0 }
12385
12386 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
12387 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
12388 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
12389 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
12390 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
12391 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
12392 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
12393 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
12394 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
12395
12396 static const struct dis386 float_reg[][8] = {
12397   /* d8 */
12398   {
12399     { "fadd",   { ST, STi }, 0 },
12400     { "fmul",   { ST, STi }, 0 },
12401     { "fcom",   { STi }, 0 },
12402     { "fcomp",  { STi }, 0 },
12403     { "fsub",   { ST, STi }, 0 },
12404     { "fsubr",  { ST, STi }, 0 },
12405     { "fdiv",   { ST, STi }, 0 },
12406     { "fdivr",  { ST, STi }, 0 },
12407   },
12408   /* d9 */
12409   {
12410     { "fld",    { STi }, 0 },
12411     { "fxch",   { STi }, 0 },
12412     { FGRPd9_2 },
12413     { Bad_Opcode },
12414     { FGRPd9_4 },
12415     { FGRPd9_5 },
12416     { FGRPd9_6 },
12417     { FGRPd9_7 },
12418   },
12419   /* da */
12420   {
12421     { "fcmovb", { ST, STi }, 0 },
12422     { "fcmove", { ST, STi }, 0 },
12423     { "fcmovbe",{ ST, STi }, 0 },
12424     { "fcmovu", { ST, STi }, 0 },
12425     { Bad_Opcode },
12426     { FGRPda_5 },
12427     { Bad_Opcode },
12428     { Bad_Opcode },
12429   },
12430   /* db */
12431   {
12432     { "fcmovnb",{ ST, STi }, 0 },
12433     { "fcmovne",{ ST, STi }, 0 },
12434     { "fcmovnbe",{ ST, STi }, 0 },
12435     { "fcmovnu",{ ST, STi }, 0 },
12436     { FGRPdb_4 },
12437     { "fucomi", { ST, STi }, 0 },
12438     { "fcomi",  { ST, STi }, 0 },
12439     { Bad_Opcode },
12440   },
12441   /* dc */
12442   {
12443     { "fadd",   { STi, ST }, 0 },
12444     { "fmul",   { STi, ST }, 0 },
12445     { Bad_Opcode },
12446     { Bad_Opcode },
12447     { "fsub{!M|r}",     { STi, ST }, 0 },
12448     { "fsub{M|}",       { STi, ST }, 0 },
12449     { "fdiv{!M|r}",     { STi, ST }, 0 },
12450     { "fdiv{M|}",       { STi, ST }, 0 },
12451   },
12452   /* dd */
12453   {
12454     { "ffree",  { STi }, 0 },
12455     { Bad_Opcode },
12456     { "fst",    { STi }, 0 },
12457     { "fstp",   { STi }, 0 },
12458     { "fucom",  { STi }, 0 },
12459     { "fucomp", { STi }, 0 },
12460     { Bad_Opcode },
12461     { Bad_Opcode },
12462   },
12463   /* de */
12464   {
12465     { "faddp",  { STi, ST }, 0 },
12466     { "fmulp",  { STi, ST }, 0 },
12467     { Bad_Opcode },
12468     { FGRPde_3 },
12469     { "fsub{!M|r}p",    { STi, ST }, 0 },
12470     { "fsub{M|}p",      { STi, ST }, 0 },
12471     { "fdiv{!M|r}p",    { STi, ST }, 0 },
12472     { "fdiv{M|}p",      { STi, ST }, 0 },
12473   },
12474   /* df */
12475   {
12476     { "ffreep", { STi }, 0 },
12477     { Bad_Opcode },
12478     { Bad_Opcode },
12479     { Bad_Opcode },
12480     { FGRPdf_4 },
12481     { "fucomip", { ST, STi }, 0 },
12482     { "fcomip", { ST, STi }, 0 },
12483     { Bad_Opcode },
12484   },
12485 };
12486
12487 static char *fgrps[][8] = {
12488   /* Bad opcode 0 */
12489   {
12490     "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12491   },
12492
12493   /* d9_2  1 */
12494   {
12495     "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12496   },
12497
12498   /* d9_4  2 */
12499   {
12500     "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
12501   },
12502
12503   /* d9_5  3 */
12504   {
12505     "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
12506   },
12507
12508   /* d9_6  4 */
12509   {
12510     "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
12511   },
12512
12513   /* d9_7  5 */
12514   {
12515     "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
12516   },
12517
12518   /* da_5  6 */
12519   {
12520     "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12521   },
12522
12523   /* db_4  7 */
12524   {
12525     "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
12526     "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
12527   },
12528
12529   /* de_3  8 */
12530   {
12531     "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12532   },
12533
12534   /* df_4  9 */
12535   {
12536     "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12537   },
12538 };
12539
12540 static void
12541 swap_operand (void)
12542 {
12543   mnemonicendp[0] = '.';
12544   mnemonicendp[1] = 's';
12545   mnemonicendp += 2;
12546 }
12547
12548 static void
12549 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
12550                int sizeflag ATTRIBUTE_UNUSED)
12551 {
12552   /* Skip mod/rm byte.  */
12553   MODRM_CHECK;
12554   codep++;
12555 }
12556
12557 static void
12558 dofloat (int sizeflag)
12559 {
12560   const struct dis386 *dp;
12561   unsigned char floatop;
12562
12563   floatop = codep[-1];
12564
12565   if (modrm.mod != 3)
12566     {
12567       int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
12568
12569       putop (float_mem[fp_indx], sizeflag);
12570       obufp = op_out[0];
12571       op_ad = 2;
12572       OP_E (float_mem_mode[fp_indx], sizeflag);
12573       return;
12574     }
12575   /* Skip mod/rm byte.  */
12576   MODRM_CHECK;
12577   codep++;
12578
12579   dp = &float_reg[floatop - 0xd8][modrm.reg];
12580   if (dp->name == NULL)
12581     {
12582       putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
12583
12584       /* Instruction fnstsw is only one with strange arg.  */
12585       if (floatop == 0xdf && codep[-1] == 0xe0)
12586         strcpy (op_out[0], names16[0]);
12587     }
12588   else
12589     {
12590       putop (dp->name, sizeflag);
12591
12592       obufp = op_out[0];
12593       op_ad = 2;
12594       if (dp->op[0].rtn)
12595         (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
12596
12597       obufp = op_out[1];
12598       op_ad = 1;
12599       if (dp->op[1].rtn)
12600         (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
12601     }
12602 }
12603
12604 /* Like oappend (below), but S is a string starting with '%'.
12605    In Intel syntax, the '%' is elided.  */
12606 static void
12607 oappend_maybe_intel (const char *s)
12608 {
12609   oappend (s + intel_syntax);
12610 }
12611
12612 static void
12613 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12614 {
12615   oappend_maybe_intel ("%st");
12616 }
12617
12618 static void
12619 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12620 {
12621   sprintf (scratchbuf, "%%st(%d)", modrm.rm);
12622   oappend_maybe_intel (scratchbuf);
12623 }
12624
12625 /* Capital letters in template are macros.  */
12626 static int
12627 putop (const char *in_template, int sizeflag)
12628 {
12629   const char *p;
12630   int alt = 0;
12631   int cond = 1;
12632   unsigned int l = 0, len = 1;
12633   char last[4];
12634
12635 #define SAVE_LAST(c)                    \
12636   if (l < len && l < sizeof (last))     \
12637     last[l++] = c;                      \
12638   else                                  \
12639     abort ();
12640
12641   for (p = in_template; *p; p++)
12642     {
12643       switch (*p)
12644         {
12645         default:
12646           *obufp++ = *p;
12647           break;
12648         case '%':
12649           len++;
12650           break;
12651         case '!':
12652           cond = 0;
12653           break;
12654         case '{':
12655           if (intel_syntax)
12656             {
12657               while (*++p != '|')
12658                 if (*p == '}' || *p == '\0')
12659                   abort ();
12660               alt = 1;
12661             }
12662           break;
12663         case '|':
12664           while (*++p != '}')
12665             {
12666               if (*p == '\0')
12667                 abort ();
12668             }
12669           break;
12670         case '}':
12671           alt = 0;
12672           break;
12673         case 'A':
12674           if (intel_syntax)
12675             break;
12676           if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
12677             *obufp++ = 'b';
12678           break;
12679         case 'B':
12680           if (l == 0 && len == 1)
12681             {
12682             case_B:
12683               if (intel_syntax)
12684                 break;
12685               if (sizeflag & SUFFIX_ALWAYS)
12686                 *obufp++ = 'b';
12687             }
12688           else
12689             {
12690               if (l != 1
12691                   || len != 2
12692                   || last[0] != 'L')
12693                 {
12694                   SAVE_LAST (*p);
12695                   break;
12696                 }
12697
12698               if (address_mode == mode_64bit
12699                   && !(prefixes & PREFIX_ADDR))
12700                 {
12701                   *obufp++ = 'a';
12702                   *obufp++ = 'b';
12703                   *obufp++ = 's';
12704                 }
12705
12706               goto case_B;
12707             }
12708           break;
12709         case 'C':
12710           if (intel_syntax && !alt)
12711             break;
12712           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
12713             {
12714               if (sizeflag & DFLAG)
12715                 *obufp++ = intel_syntax ? 'd' : 'l';
12716               else
12717                 *obufp++ = intel_syntax ? 'w' : 's';
12718               used_prefixes |= (prefixes & PREFIX_DATA);
12719             }
12720           break;
12721         case 'D':
12722           if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
12723             break;
12724           USED_REX (REX_W);
12725           if (modrm.mod == 3)
12726             {
12727               if (rex & REX_W)
12728                 *obufp++ = 'q';
12729               else
12730                 {
12731                   if (sizeflag & DFLAG)
12732                     *obufp++ = intel_syntax ? 'd' : 'l';
12733                   else
12734                     *obufp++ = 'w';
12735                   used_prefixes |= (prefixes & PREFIX_DATA);
12736                 }
12737             }
12738           else
12739             *obufp++ = 'w';
12740           break;
12741         case 'E':               /* For jcxz/jecxz */
12742           if (address_mode == mode_64bit)
12743             {
12744               if (sizeflag & AFLAG)
12745                 *obufp++ = 'r';
12746               else
12747                 *obufp++ = 'e';
12748             }
12749           else
12750             if (sizeflag & AFLAG)
12751               *obufp++ = 'e';
12752           used_prefixes |= (prefixes & PREFIX_ADDR);
12753           break;
12754         case 'F':
12755           if (intel_syntax)
12756             break;
12757           if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
12758             {
12759               if (sizeflag & AFLAG)
12760                 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
12761               else
12762                 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
12763               used_prefixes |= (prefixes & PREFIX_ADDR);
12764             }
12765           break;
12766         case 'G':
12767           if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
12768             break;
12769           if ((rex & REX_W) || (sizeflag & DFLAG))
12770             *obufp++ = 'l';
12771           else
12772             *obufp++ = 'w';
12773           if (!(rex & REX_W))
12774             used_prefixes |= (prefixes & PREFIX_DATA);
12775           break;
12776         case 'H':
12777           if (intel_syntax)
12778             break;
12779           if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
12780               || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
12781             {
12782               used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
12783               *obufp++ = ',';
12784               *obufp++ = 'p';
12785               if (prefixes & PREFIX_DS)
12786                 *obufp++ = 't';
12787               else
12788                 *obufp++ = 'n';
12789             }
12790           break;
12791         case 'K':
12792           USED_REX (REX_W);
12793           if (rex & REX_W)
12794             *obufp++ = 'q';
12795           else
12796             *obufp++ = 'd';
12797           break;
12798         case 'Z':
12799           if (l != 0 || len != 1)
12800             {
12801               if (l != 1 || len != 2 || last[0] != 'X')
12802                 {
12803                   SAVE_LAST (*p);
12804                   break;
12805                 }
12806               if (!need_vex || !vex.evex)
12807                 abort ();
12808               if (intel_syntax
12809                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
12810                 break;
12811               switch (vex.length)
12812                 {
12813                 case 128:
12814                   *obufp++ = 'x';
12815                   break;
12816                 case 256:
12817                   *obufp++ = 'y';
12818                   break;
12819                 case 512:
12820                   *obufp++ = 'z';
12821                   break;
12822                 default:
12823                   abort ();
12824                 }
12825               break;
12826             }
12827           if (intel_syntax)
12828             break;
12829           if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
12830             {
12831               *obufp++ = 'q';
12832               break;
12833             }
12834           /* Fall through.  */
12835           goto case_L;
12836         case 'L':
12837           if (l != 0 || len != 1)
12838             {
12839               SAVE_LAST (*p);
12840               break;
12841             }
12842         case_L:
12843           if (intel_syntax)
12844             break;
12845           if (sizeflag & SUFFIX_ALWAYS)
12846             *obufp++ = 'l';
12847           break;
12848         case 'M':
12849           if (intel_mnemonic != cond)
12850             *obufp++ = 'r';
12851           break;
12852         case 'N':
12853           if ((prefixes & PREFIX_FWAIT) == 0)
12854             *obufp++ = 'n';
12855           else
12856             used_prefixes |= PREFIX_FWAIT;
12857           break;
12858         case 'O':
12859           USED_REX (REX_W);
12860           if (rex & REX_W)
12861             *obufp++ = 'o';
12862           else if (intel_syntax && (sizeflag & DFLAG))
12863             *obufp++ = 'q';
12864           else
12865             *obufp++ = 'd';
12866           if (!(rex & REX_W))
12867             used_prefixes |= (prefixes & PREFIX_DATA);
12868           break;
12869         case '&':
12870           if (!intel_syntax
12871               && address_mode == mode_64bit
12872               && isa64 == intel64)
12873             {
12874               *obufp++ = 'q';
12875               break;
12876             }
12877           /* Fall through.  */
12878         case 'T':
12879           if (!intel_syntax
12880               && address_mode == mode_64bit
12881               && ((sizeflag & DFLAG) || (rex & REX_W)))
12882             {
12883               *obufp++ = 'q';
12884               break;
12885             }
12886           /* Fall through.  */
12887           goto case_P;
12888         case 'P':
12889           if (l == 0 && len == 1)
12890             {
12891             case_P:
12892               if (intel_syntax)
12893                 {
12894                   if ((rex & REX_W) == 0
12895                       && (prefixes & PREFIX_DATA))
12896                     {
12897                       if ((sizeflag & DFLAG) == 0)
12898                         *obufp++ = 'w';
12899                       used_prefixes |= (prefixes & PREFIX_DATA);
12900                     }
12901                   break;
12902                 }
12903               if ((prefixes & PREFIX_DATA)
12904                   || (rex & REX_W)
12905                   || (sizeflag & SUFFIX_ALWAYS))
12906                 {
12907                   USED_REX (REX_W);
12908                   if (rex & REX_W)
12909                     *obufp++ = 'q';
12910                   else
12911                     {
12912                       if (sizeflag & DFLAG)
12913                         *obufp++ = 'l';
12914                       else
12915                         *obufp++ = 'w';
12916                       used_prefixes |= (prefixes & PREFIX_DATA);
12917                     }
12918                 }
12919             }
12920           else
12921             {
12922               if (l != 1 || len != 2 || last[0] != 'L')
12923                 {
12924                   SAVE_LAST (*p);
12925                   break;
12926                 }
12927
12928               if ((prefixes & PREFIX_DATA)
12929                   || (rex & REX_W)
12930                   || (sizeflag & SUFFIX_ALWAYS))
12931                 {
12932                   USED_REX (REX_W);
12933                   if (rex & REX_W)
12934                     *obufp++ = 'q';
12935                   else
12936                     {
12937                       if (sizeflag & DFLAG)
12938                         *obufp++ = intel_syntax ? 'd' : 'l';
12939                       else
12940                         *obufp++ = 'w';
12941                       used_prefixes |= (prefixes & PREFIX_DATA);
12942                     }
12943                 }
12944             }
12945           break;
12946         case 'U':
12947           if (intel_syntax)
12948             break;
12949           if (address_mode == mode_64bit
12950               && ((sizeflag & DFLAG) || (rex & REX_W)))
12951             {
12952               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
12953                 *obufp++ = 'q';
12954               break;
12955             }
12956           /* Fall through.  */
12957           goto case_Q;
12958         case 'Q':
12959           if (l == 0 && len == 1)
12960             {
12961             case_Q:
12962               if (intel_syntax && !alt)
12963                 break;
12964               USED_REX (REX_W);
12965               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
12966                 {
12967                   if (rex & REX_W)
12968                     *obufp++ = 'q';
12969                   else
12970                     {
12971                       if (sizeflag & DFLAG)
12972                         *obufp++ = intel_syntax ? 'd' : 'l';
12973                       else
12974                         *obufp++ = 'w';
12975                       used_prefixes |= (prefixes & PREFIX_DATA);
12976                     }
12977                 }
12978             }
12979           else
12980             {
12981               if (l != 1 || len != 2 || last[0] != 'L')
12982                 {
12983                   SAVE_LAST (*p);
12984                   break;
12985                 }
12986               if ((intel_syntax && need_modrm)
12987                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
12988                 break;
12989               if ((rex & REX_W))
12990                 {
12991                   USED_REX (REX_W);
12992                   *obufp++ = 'q';
12993                 }
12994               else if((address_mode == mode_64bit && need_modrm)
12995                       || (sizeflag & SUFFIX_ALWAYS))
12996                 *obufp++ = intel_syntax? 'd' : 'l';
12997             }
12998           break;
12999         case 'R':
13000           USED_REX (REX_W);
13001           if (rex & REX_W)
13002             *obufp++ = 'q';
13003           else if (sizeflag & DFLAG)
13004             {
13005               if (intel_syntax)
13006                   *obufp++ = 'd';
13007               else
13008                   *obufp++ = 'l';
13009             }
13010           else
13011             *obufp++ = 'w';
13012           if (intel_syntax && !p[1]
13013               && ((rex & REX_W) || (sizeflag & DFLAG)))
13014             *obufp++ = 'e';
13015           if (!(rex & REX_W))
13016             used_prefixes |= (prefixes & PREFIX_DATA);
13017           break;
13018         case 'V':
13019           if (l == 0 && len == 1)
13020             {
13021               if (intel_syntax)
13022                 break;
13023               if (address_mode == mode_64bit
13024                   && ((sizeflag & DFLAG) || (rex & REX_W)))
13025                 {
13026                   if (sizeflag & SUFFIX_ALWAYS)
13027                     *obufp++ = 'q';
13028                   break;
13029                 }
13030             }
13031           else
13032             {
13033               if (l != 1
13034                   || len != 2
13035                   || last[0] != 'L')
13036                 {
13037                   SAVE_LAST (*p);
13038                   break;
13039                 }
13040
13041               if (rex & REX_W)
13042                 {
13043                   *obufp++ = 'a';
13044                   *obufp++ = 'b';
13045                   *obufp++ = 's';
13046                 }
13047             }
13048           /* Fall through.  */
13049           goto case_S;
13050         case 'S':
13051           if (l == 0 && len == 1)
13052             {
13053             case_S:
13054               if (intel_syntax)
13055                 break;
13056               if (sizeflag & SUFFIX_ALWAYS)
13057                 {
13058                   if (rex & REX_W)
13059                     *obufp++ = 'q';
13060                   else
13061                     {
13062                       if (sizeflag & DFLAG)
13063                         *obufp++ = 'l';
13064                       else
13065                         *obufp++ = 'w';
13066                       used_prefixes |= (prefixes & PREFIX_DATA);
13067                     }
13068                 }
13069             }
13070           else
13071             {
13072               if (l != 1
13073                   || len != 2
13074                   || last[0] != 'L')
13075                 {
13076                   SAVE_LAST (*p);
13077                   break;
13078                 }
13079
13080               if (address_mode == mode_64bit
13081                   && !(prefixes & PREFIX_ADDR))
13082                 {
13083                   *obufp++ = 'a';
13084                   *obufp++ = 'b';
13085                   *obufp++ = 's';
13086                 }
13087
13088               goto case_S;
13089             }
13090           break;
13091         case 'X':
13092           if (l != 0 || len != 1)
13093             {
13094               SAVE_LAST (*p);
13095               break;
13096             }
13097           if (need_vex
13098               ? vex.prefix == DATA_PREFIX_OPCODE
13099               : prefixes & PREFIX_DATA)
13100             {
13101               *obufp++ = 'd';
13102               used_prefixes |= PREFIX_DATA;
13103             }
13104           else
13105             *obufp++ = 's';
13106           break;
13107         case 'Y':
13108           if (l == 0 && len == 1)
13109             abort ();
13110           else
13111             {
13112               if (l != 1 || len != 2 || last[0] != 'X')
13113                 {
13114                   SAVE_LAST (*p);
13115                   break;
13116                 }
13117               if (!need_vex)
13118                 abort ();
13119               if (intel_syntax
13120                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
13121                 break;
13122               switch (vex.length)
13123                 {
13124                 case 128:
13125                   *obufp++ = 'x';
13126                   break;
13127                 case 256:
13128                   *obufp++ = 'y';
13129                   break;
13130                 case 512:
13131                   if (!vex.evex)
13132                 default:
13133                     abort ();
13134                 }
13135             }
13136           break;
13137         case 'W':
13138           if (l == 0 && len == 1)
13139             {
13140               /* operand size flag for cwtl, cbtw */
13141               USED_REX (REX_W);
13142               if (rex & REX_W)
13143                 {
13144                   if (intel_syntax)
13145                     *obufp++ = 'd';
13146                   else
13147                     *obufp++ = 'l';
13148                 }
13149               else if (sizeflag & DFLAG)
13150                 *obufp++ = 'w';
13151               else
13152                 *obufp++ = 'b';
13153               if (!(rex & REX_W))
13154                 used_prefixes |= (prefixes & PREFIX_DATA);
13155             }
13156           else
13157             {
13158               if (l != 1
13159                   || len != 2
13160                   || (last[0] != 'X'
13161                       && last[0] != 'L'))
13162                 {
13163                   SAVE_LAST (*p);
13164                   break;
13165                 }
13166               if (!need_vex)
13167                 abort ();
13168               if (last[0] == 'X')
13169                 *obufp++ = vex.w ? 'd': 's';
13170               else
13171                 *obufp++ = vex.w ? 'q': 'd';
13172             }
13173           break;
13174         case '^':
13175           if (intel_syntax)
13176             break;
13177           if (isa64 == intel64 && (rex & REX_W))
13178             {
13179               USED_REX (REX_W);
13180               *obufp++ = 'q';
13181               break;
13182             }
13183           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
13184             {
13185               if (sizeflag & DFLAG)
13186                 *obufp++ = 'l';
13187               else
13188                 *obufp++ = 'w';
13189               used_prefixes |= (prefixes & PREFIX_DATA);
13190             }
13191           break;
13192         case '@':
13193           if (intel_syntax)
13194             break;
13195           if (address_mode == mode_64bit
13196               && (isa64 == intel64
13197                   || ((sizeflag & DFLAG) || (rex & REX_W))))
13198               *obufp++ = 'q';
13199           else if ((prefixes & PREFIX_DATA))
13200             {
13201               if (!(sizeflag & DFLAG))
13202                 *obufp++ = 'w';
13203               used_prefixes |= (prefixes & PREFIX_DATA);
13204             }
13205           break;
13206         }
13207     }
13208   *obufp = 0;
13209   mnemonicendp = obufp;
13210   return 0;
13211 }
13212
13213 static void
13214 oappend (const char *s)
13215 {
13216   obufp = stpcpy (obufp, s);
13217 }
13218
13219 static void
13220 append_seg (void)
13221 {
13222   /* Only print the active segment register.  */
13223   if (!active_seg_prefix)
13224     return;
13225
13226   used_prefixes |= active_seg_prefix;
13227   switch (active_seg_prefix)
13228     {
13229     case PREFIX_CS:
13230       oappend_maybe_intel ("%cs:");
13231       break;
13232     case PREFIX_DS:
13233       oappend_maybe_intel ("%ds:");
13234       break;
13235     case PREFIX_SS:
13236       oappend_maybe_intel ("%ss:");
13237       break;
13238     case PREFIX_ES:
13239       oappend_maybe_intel ("%es:");
13240       break;
13241     case PREFIX_FS:
13242       oappend_maybe_intel ("%fs:");
13243       break;
13244     case PREFIX_GS:
13245       oappend_maybe_intel ("%gs:");
13246       break;
13247     default:
13248       break;
13249     }
13250 }
13251
13252 static void
13253 OP_indirE (int bytemode, int sizeflag)
13254 {
13255   if (!intel_syntax)
13256     oappend ("*");
13257   OP_E (bytemode, sizeflag);
13258 }
13259
13260 static void
13261 print_operand_value (char *buf, int hex, bfd_vma disp)
13262 {
13263   if (address_mode == mode_64bit)
13264     {
13265       if (hex)
13266         {
13267           char tmp[30];
13268           int i;
13269           buf[0] = '0';
13270           buf[1] = 'x';
13271           sprintf_vma (tmp, disp);
13272           for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
13273           strcpy (buf + 2, tmp + i);
13274         }
13275       else
13276         {
13277           bfd_signed_vma v = disp;
13278           char tmp[30];
13279           int i;
13280           if (v < 0)
13281             {
13282               *(buf++) = '-';
13283               v = -disp;
13284               /* Check for possible overflow on 0x8000000000000000.  */
13285               if (v < 0)
13286                 {
13287                   strcpy (buf, "9223372036854775808");
13288                   return;
13289                 }
13290             }
13291           if (!v)
13292             {
13293               strcpy (buf, "0");
13294               return;
13295             }
13296
13297           i = 0;
13298           tmp[29] = 0;
13299           while (v)
13300             {
13301               tmp[28 - i] = (v % 10) + '0';
13302               v /= 10;
13303               i++;
13304             }
13305           strcpy (buf, tmp + 29 - i);
13306         }
13307     }
13308   else
13309     {
13310       if (hex)
13311         sprintf (buf, "0x%x", (unsigned int) disp);
13312       else
13313         sprintf (buf, "%d", (int) disp);
13314     }
13315 }
13316
13317 /* Put DISP in BUF as signed hex number.  */
13318
13319 static void
13320 print_displacement (char *buf, bfd_vma disp)
13321 {
13322   bfd_signed_vma val = disp;
13323   char tmp[30];
13324   int i, j = 0;
13325
13326   if (val < 0)
13327     {
13328       buf[j++] = '-';
13329       val = -disp;
13330
13331       /* Check for possible overflow.  */
13332       if (val < 0)
13333         {
13334           switch (address_mode)
13335             {
13336             case mode_64bit:
13337               strcpy (buf + j, "0x8000000000000000");
13338               break;
13339             case mode_32bit:
13340               strcpy (buf + j, "0x80000000");
13341               break;
13342             case mode_16bit:
13343               strcpy (buf + j, "0x8000");
13344               break;
13345             }
13346           return;
13347         }
13348     }
13349
13350   buf[j++] = '0';
13351   buf[j++] = 'x';
13352
13353   sprintf_vma (tmp, (bfd_vma) val);
13354   for (i = 0; tmp[i] == '0'; i++)
13355     continue;
13356   if (tmp[i] == '\0')
13357     i--;
13358   strcpy (buf + j, tmp + i);
13359 }
13360
13361 static void
13362 intel_operand_size (int bytemode, int sizeflag)
13363 {
13364   if (vex.evex
13365       && vex.b
13366       && (bytemode == x_mode
13367           || bytemode == evex_half_bcst_xmmq_mode))
13368     {
13369       if (vex.w)
13370         oappend ("QWORD PTR ");
13371       else
13372         oappend ("DWORD PTR ");
13373       return;
13374     }
13375   switch (bytemode)
13376     {
13377     case b_mode:
13378     case b_swap_mode:
13379     case dqb_mode:
13380     case db_mode:
13381       oappend ("BYTE PTR ");
13382       break;
13383     case w_mode:
13384     case dw_mode:
13385     case dqw_mode:
13386       oappend ("WORD PTR ");
13387       break;
13388     case indir_v_mode:
13389       if (address_mode == mode_64bit && isa64 == intel64)
13390         {
13391           oappend ("QWORD PTR ");
13392           break;
13393         }
13394       /* Fall through.  */
13395     case stack_v_mode:
13396       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
13397         {
13398           oappend ("QWORD PTR ");
13399           break;
13400         }
13401       /* Fall through.  */
13402     case v_mode:
13403     case v_swap_mode:
13404     case dq_mode:
13405       USED_REX (REX_W);
13406       if (rex & REX_W)
13407         oappend ("QWORD PTR ");
13408       else
13409         {
13410           if ((sizeflag & DFLAG) || bytemode == dq_mode)
13411             oappend ("DWORD PTR ");
13412           else
13413             oappend ("WORD PTR ");
13414           used_prefixes |= (prefixes & PREFIX_DATA);
13415         }
13416       break;
13417     case z_mode:
13418       if ((rex & REX_W) || (sizeflag & DFLAG))
13419         *obufp++ = 'D';
13420       oappend ("WORD PTR ");
13421       if (!(rex & REX_W))
13422         used_prefixes |= (prefixes & PREFIX_DATA);
13423       break;
13424     case a_mode:
13425       if (sizeflag & DFLAG)
13426         oappend ("QWORD PTR ");
13427       else
13428         oappend ("DWORD PTR ");
13429       used_prefixes |= (prefixes & PREFIX_DATA);
13430       break;
13431     case movsxd_mode:
13432       if (!(sizeflag & DFLAG) && isa64 == intel64)
13433         oappend ("WORD PTR ");
13434       else
13435         oappend ("DWORD PTR ");
13436       used_prefixes |= (prefixes & PREFIX_DATA);
13437       break;
13438     case d_mode:
13439     case d_scalar_swap_mode:
13440     case d_swap_mode:
13441     case dqd_mode:
13442       oappend ("DWORD PTR ");
13443       break;
13444     case q_mode:
13445     case q_scalar_swap_mode:
13446     case q_swap_mode:
13447       oappend ("QWORD PTR ");
13448       break;
13449     case m_mode:
13450       if (address_mode == mode_64bit)
13451         oappend ("QWORD PTR ");
13452       else
13453         oappend ("DWORD PTR ");
13454       break;
13455     case f_mode:
13456       if (sizeflag & DFLAG)
13457         oappend ("FWORD PTR ");
13458       else
13459         oappend ("DWORD PTR ");
13460       used_prefixes |= (prefixes & PREFIX_DATA);
13461       break;
13462     case t_mode:
13463       oappend ("TBYTE PTR ");
13464       break;
13465     case x_mode:
13466     case x_swap_mode:
13467     case evex_x_gscat_mode:
13468     case evex_x_nobcst_mode:
13469     case b_scalar_mode:
13470     case w_scalar_mode:
13471       if (need_vex)
13472         {
13473           switch (vex.length)
13474             {
13475             case 128:
13476               oappend ("XMMWORD PTR ");
13477               break;
13478             case 256:
13479               oappend ("YMMWORD PTR ");
13480               break;
13481             case 512:
13482               oappend ("ZMMWORD PTR ");
13483               break;
13484             default:
13485               abort ();
13486             }
13487         }
13488       else
13489         oappend ("XMMWORD PTR ");
13490       break;
13491     case xmm_mode:
13492       oappend ("XMMWORD PTR ");
13493       break;
13494     case ymm_mode:
13495       oappend ("YMMWORD PTR ");
13496       break;
13497     case xmmq_mode:
13498     case evex_half_bcst_xmmq_mode:
13499       if (!need_vex)
13500         abort ();
13501
13502       switch (vex.length)
13503         {
13504         case 128:
13505           oappend ("QWORD PTR ");
13506           break;
13507         case 256:
13508           oappend ("XMMWORD PTR ");
13509           break;
13510         case 512:
13511           oappend ("YMMWORD PTR ");
13512           break;
13513         default:
13514           abort ();
13515         }
13516       break;
13517     case xmm_mb_mode:
13518       if (!need_vex)
13519         abort ();
13520
13521       switch (vex.length)
13522         {
13523         case 128:
13524         case 256:
13525         case 512:
13526           oappend ("BYTE PTR ");
13527           break;
13528         default:
13529           abort ();
13530         }
13531       break;
13532     case xmm_mw_mode:
13533       if (!need_vex)
13534         abort ();
13535
13536       switch (vex.length)
13537         {
13538         case 128:
13539         case 256:
13540         case 512:
13541           oappend ("WORD PTR ");
13542           break;
13543         default:
13544           abort ();
13545         }
13546       break;
13547     case xmm_md_mode:
13548       if (!need_vex)
13549         abort ();
13550
13551       switch (vex.length)
13552         {
13553         case 128:
13554         case 256:
13555         case 512:
13556           oappend ("DWORD PTR ");
13557           break;
13558         default:
13559           abort ();
13560         }
13561       break;
13562     case xmm_mq_mode:
13563       if (!need_vex)
13564         abort ();
13565
13566       switch (vex.length)
13567         {
13568         case 128:
13569         case 256:
13570         case 512:
13571           oappend ("QWORD PTR ");
13572           break;
13573         default:
13574           abort ();
13575         }
13576       break;
13577     case xmmdw_mode:
13578       if (!need_vex)
13579         abort ();
13580
13581       switch (vex.length)
13582         {
13583         case 128:
13584           oappend ("WORD PTR ");
13585           break;
13586         case 256:
13587           oappend ("DWORD PTR ");
13588           break;
13589         case 512:
13590           oappend ("QWORD PTR ");
13591           break;
13592         default:
13593           abort ();
13594         }
13595       break;
13596     case xmmqd_mode:
13597       if (!need_vex)
13598         abort ();
13599
13600       switch (vex.length)
13601         {
13602         case 128:
13603           oappend ("DWORD PTR ");
13604           break;
13605         case 256:
13606           oappend ("QWORD PTR ");
13607           break;
13608         case 512:
13609           oappend ("XMMWORD PTR ");
13610           break;
13611         default:
13612           abort ();
13613         }
13614       break;
13615     case ymmq_mode:
13616       if (!need_vex)
13617         abort ();
13618
13619       switch (vex.length)
13620         {
13621         case 128:
13622           oappend ("QWORD PTR ");
13623           break;
13624         case 256:
13625           oappend ("YMMWORD PTR ");
13626           break;
13627         case 512:
13628           oappend ("ZMMWORD PTR ");
13629           break;
13630         default:
13631           abort ();
13632         }
13633       break;
13634     case ymmxmm_mode:
13635       if (!need_vex)
13636         abort ();
13637
13638       switch (vex.length)
13639         {
13640         case 128:
13641         case 256:
13642           oappend ("XMMWORD PTR ");
13643           break;
13644         default:
13645           abort ();
13646         }
13647       break;
13648     case o_mode:
13649       oappend ("OWORD PTR ");
13650       break;
13651     case vex_scalar_w_dq_mode:
13652       if (!need_vex)
13653         abort ();
13654
13655       if (vex.w)
13656         oappend ("QWORD PTR ");
13657       else
13658         oappend ("DWORD PTR ");
13659       break;
13660     case vex_vsib_d_w_dq_mode:
13661     case vex_vsib_q_w_dq_mode:
13662       if (!need_vex)
13663         abort ();
13664
13665       if (!vex.evex)
13666         {
13667           if (vex.w)
13668             oappend ("QWORD PTR ");
13669           else
13670             oappend ("DWORD PTR ");
13671         }
13672       else
13673         {
13674           switch (vex.length)
13675             {
13676             case 128:
13677               oappend ("XMMWORD PTR ");
13678               break;
13679             case 256:
13680               oappend ("YMMWORD PTR ");
13681               break;
13682             case 512:
13683               oappend ("ZMMWORD PTR ");
13684               break;
13685             default:
13686               abort ();
13687             }
13688         }
13689       break;
13690     case vex_vsib_q_w_d_mode:
13691     case vex_vsib_d_w_d_mode:
13692       if (!need_vex || !vex.evex)
13693         abort ();
13694
13695       switch (vex.length)
13696         {
13697         case 128:
13698           oappend ("QWORD PTR ");
13699           break;
13700         case 256:
13701           oappend ("XMMWORD PTR ");
13702           break;
13703         case 512:
13704           oappend ("YMMWORD PTR ");
13705           break;
13706         default:
13707           abort ();
13708         }
13709
13710       break;
13711     case mask_bd_mode:
13712       if (!need_vex || vex.length != 128)
13713         abort ();
13714       if (vex.w)
13715         oappend ("DWORD PTR ");
13716       else
13717         oappend ("BYTE PTR ");
13718       break;
13719     case mask_mode:
13720       if (!need_vex)
13721         abort ();
13722       if (vex.w)
13723         oappend ("QWORD PTR ");
13724       else
13725         oappend ("WORD PTR ");
13726       break;
13727     case v_bnd_mode:
13728     case v_bndmk_mode:
13729     default:
13730       break;
13731     }
13732 }
13733
13734 static void
13735 OP_E_register (int bytemode, int sizeflag)
13736 {
13737   int reg = modrm.rm;
13738   const char **names;
13739
13740   USED_REX (REX_B);
13741   if ((rex & REX_B))
13742     reg += 8;
13743
13744   if ((sizeflag & SUFFIX_ALWAYS)
13745       && (bytemode == b_swap_mode
13746           || bytemode == bnd_swap_mode
13747           || bytemode == v_swap_mode))
13748     swap_operand ();
13749
13750   switch (bytemode)
13751     {
13752     case b_mode:
13753     case b_swap_mode:
13754       USED_REX (0);
13755       if (rex)
13756         names = names8rex;
13757       else
13758         names = names8;
13759       break;
13760     case w_mode:
13761       names = names16;
13762       break;
13763     case d_mode:
13764     case dw_mode:
13765     case db_mode:
13766       names = names32;
13767       break;
13768     case q_mode:
13769       names = names64;
13770       break;
13771     case m_mode:
13772     case v_bnd_mode:
13773       names = address_mode == mode_64bit ? names64 : names32;
13774       break;
13775     case bnd_mode:
13776     case bnd_swap_mode:
13777       if (reg > 0x3)
13778         {
13779           oappend ("(bad)");
13780           return;
13781         }
13782       names = names_bnd;
13783       break;
13784     case indir_v_mode:
13785       if (address_mode == mode_64bit && isa64 == intel64)
13786         {
13787           names = names64;
13788           break;
13789         }
13790       /* Fall through.  */
13791     case stack_v_mode:
13792       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
13793         {
13794           names = names64;
13795           break;
13796         }
13797       bytemode = v_mode;
13798       /* Fall through.  */
13799     case v_mode:
13800     case v_swap_mode:
13801     case dq_mode:
13802     case dqb_mode:
13803     case dqd_mode:
13804     case dqw_mode:
13805       USED_REX (REX_W);
13806       if (rex & REX_W)
13807         names = names64;
13808       else
13809         {
13810           if ((sizeflag & DFLAG)
13811               || (bytemode != v_mode
13812                   && bytemode != v_swap_mode))
13813             names = names32;
13814           else
13815             names = names16;
13816           used_prefixes |= (prefixes & PREFIX_DATA);
13817         }
13818       break;
13819     case movsxd_mode:
13820       if (!(sizeflag & DFLAG) && isa64 == intel64)
13821         names = names16;
13822       else
13823         names = names32;
13824       used_prefixes |= (prefixes & PREFIX_DATA);
13825       break;
13826     case va_mode:
13827       names = (address_mode == mode_64bit
13828                ? names64 : names32);
13829       if (!(prefixes & PREFIX_ADDR))
13830         names = (address_mode == mode_16bit
13831                      ? names16 : names);
13832       else
13833         {
13834           /* Remove "addr16/addr32".  */
13835           all_prefixes[last_addr_prefix] = 0;
13836           names = (address_mode != mode_32bit
13837                        ? names32 : names16);
13838           used_prefixes |= PREFIX_ADDR;
13839         }
13840       break;
13841     case mask_bd_mode:
13842     case mask_mode:
13843       if (reg > 0x7)
13844         {
13845           oappend ("(bad)");
13846           return;
13847         }
13848       names = names_mask;
13849       break;
13850     case 0:
13851       return;
13852     default:
13853       oappend (INTERNAL_DISASSEMBLER_ERROR);
13854       return;
13855     }
13856   oappend (names[reg]);
13857 }
13858
13859 static void
13860 OP_E_memory (int bytemode, int sizeflag)
13861 {
13862   bfd_vma disp = 0;
13863   int add = (rex & REX_B) ? 8 : 0;
13864   int riprel = 0;
13865   int shift;
13866
13867   if (vex.evex)
13868     {
13869       /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0.  */
13870       if (vex.b
13871           && bytemode != x_mode
13872           && bytemode != xmmq_mode
13873           && bytemode != evex_half_bcst_xmmq_mode)
13874         {
13875           BadOp ();
13876           return;
13877         }
13878       switch (bytemode)
13879         {
13880         case dqw_mode:
13881         case dw_mode:
13882           shift = 1;
13883           break;
13884         case dqb_mode:
13885         case db_mode:
13886           shift = 0;
13887           break;
13888         case dq_mode:
13889           if (address_mode != mode_64bit)
13890             {
13891               shift = 2;
13892               break;
13893             }
13894             /* fall through */
13895         case vex_scalar_w_dq_mode:
13896         case vex_vsib_d_w_dq_mode:
13897         case vex_vsib_d_w_d_mode:
13898         case vex_vsib_q_w_dq_mode:
13899         case vex_vsib_q_w_d_mode:
13900         case evex_x_gscat_mode:
13901           shift = vex.w ? 3 : 2;
13902           break;
13903         case x_mode:
13904         case evex_half_bcst_xmmq_mode:
13905         case xmmq_mode:
13906           if (vex.b)
13907             {
13908               shift = vex.w ? 3 : 2;
13909               break;
13910             }
13911           /* Fall through.  */
13912         case xmmqd_mode:
13913         case xmmdw_mode:
13914         case ymmq_mode:
13915         case evex_x_nobcst_mode:
13916         case x_swap_mode:
13917           switch (vex.length)
13918             {
13919             case 128:
13920               shift = 4;
13921               break;
13922             case 256:
13923               shift = 5;
13924               break;
13925             case 512:
13926               shift = 6;
13927               break;
13928             default:
13929               abort ();
13930             }
13931           break;
13932         case ymm_mode:
13933           shift = 5;
13934           break;
13935         case xmm_mode:
13936           shift = 4;
13937           break;
13938         case xmm_mq_mode:
13939         case q_mode:
13940         case q_swap_mode:
13941         case q_scalar_swap_mode:
13942           shift = 3;
13943           break;
13944         case dqd_mode:
13945         case xmm_md_mode:
13946         case d_mode:
13947         case d_swap_mode:
13948         case d_scalar_swap_mode:
13949           shift = 2;
13950           break;
13951         case w_scalar_mode:
13952         case xmm_mw_mode:
13953           shift = 1;
13954           break;
13955         case b_scalar_mode:
13956         case xmm_mb_mode:
13957           shift = 0;
13958           break;
13959         default:
13960           abort ();
13961         }
13962       /* Make necessary corrections to shift for modes that need it.
13963          For these modes we currently have shift 4, 5 or 6 depending on
13964          vex.length (it corresponds to xmmword, ymmword or zmmword
13965          operand).  We might want to make it 3, 4 or 5 (e.g. for
13966          xmmq_mode).  In case of broadcast enabled the corrections
13967          aren't needed, as element size is always 32 or 64 bits.  */
13968       if (!vex.b
13969           && (bytemode == xmmq_mode
13970               || bytemode == evex_half_bcst_xmmq_mode))
13971         shift -= 1;
13972       else if (bytemode == xmmqd_mode)
13973         shift -= 2;
13974       else if (bytemode == xmmdw_mode)
13975         shift -= 3;
13976       else if (bytemode == ymmq_mode && vex.length == 128)
13977         shift -= 1;
13978     }
13979   else
13980     shift = 0;
13981
13982   USED_REX (REX_B);
13983   if (intel_syntax)
13984     intel_operand_size (bytemode, sizeflag);
13985   append_seg ();
13986
13987   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
13988     {
13989       /* 32/64 bit address mode */
13990       int havedisp;
13991       int havesib;
13992       int havebase;
13993       int haveindex;
13994       int needindex;
13995       int needaddr32;
13996       int base, rbase;
13997       int vindex = 0;
13998       int scale = 0;
13999       int addr32flag = !((sizeflag & AFLAG)
14000                          || bytemode == v_bnd_mode
14001                          || bytemode == v_bndmk_mode
14002                          || bytemode == bnd_mode
14003                          || bytemode == bnd_swap_mode);
14004       const char **indexes64 = names64;
14005       const char **indexes32 = names32;
14006
14007       havesib = 0;
14008       havebase = 1;
14009       haveindex = 0;
14010       base = modrm.rm;
14011
14012       if (base == 4)
14013         {
14014           havesib = 1;
14015           vindex = sib.index;
14016           USED_REX (REX_X);
14017           if (rex & REX_X)
14018             vindex += 8;
14019           switch (bytemode)
14020             {
14021             case vex_vsib_d_w_dq_mode:
14022             case vex_vsib_d_w_d_mode:
14023             case vex_vsib_q_w_dq_mode:
14024             case vex_vsib_q_w_d_mode:
14025               if (!need_vex)
14026                 abort ();
14027               if (vex.evex)
14028                 {
14029                   if (!vex.v)
14030                     vindex += 16;
14031                 }
14032
14033               haveindex = 1;
14034               switch (vex.length)
14035                 {
14036                 case 128:
14037                   indexes64 = indexes32 = names_xmm;
14038                   break;
14039                 case 256:
14040                   if (!vex.w
14041                       || bytemode == vex_vsib_q_w_dq_mode
14042                       || bytemode == vex_vsib_q_w_d_mode)
14043                     indexes64 = indexes32 = names_ymm;
14044                   else
14045                     indexes64 = indexes32 = names_xmm;
14046                   break;
14047                 case 512:
14048                   if (!vex.w
14049                       || bytemode == vex_vsib_q_w_dq_mode
14050                       || bytemode == vex_vsib_q_w_d_mode)
14051                     indexes64 = indexes32 = names_zmm;
14052                   else
14053                     indexes64 = indexes32 = names_ymm;
14054                   break;
14055                 default:
14056                   abort ();
14057                 }
14058               break;
14059             default:
14060               haveindex = vindex != 4;
14061               break;
14062             }
14063           scale = sib.scale;
14064           base = sib.base;
14065           codep++;
14066         }
14067       rbase = base + add;
14068
14069       switch (modrm.mod)
14070         {
14071         case 0:
14072           if (base == 5)
14073             {
14074               havebase = 0;
14075               if (address_mode == mode_64bit && !havesib)
14076                 riprel = 1;
14077               disp = get32s ();
14078               if (riprel && bytemode == v_bndmk_mode)
14079                 {
14080                   oappend ("(bad)");
14081                   return;
14082                 }
14083             }
14084           break;
14085         case 1:
14086           FETCH_DATA (the_info, codep + 1);
14087           disp = *codep++;
14088           if ((disp & 0x80) != 0)
14089             disp -= 0x100;
14090           if (vex.evex && shift > 0)
14091             disp <<= shift;
14092           break;
14093         case 2:
14094           disp = get32s ();
14095           break;
14096         }
14097
14098       needindex = 0;
14099       needaddr32 = 0;
14100       if (havesib
14101           && !havebase
14102           && !haveindex
14103           && address_mode != mode_16bit)
14104         {
14105           if (address_mode == mode_64bit)
14106             {
14107               /* Display eiz instead of addr32.  */
14108               needindex = addr32flag;
14109               needaddr32 = 1;
14110             }
14111           else
14112             {
14113               /* In 32-bit mode, we need index register to tell [offset]
14114                  from [eiz*1 + offset].  */
14115               needindex = 1;
14116             }
14117         }
14118
14119       havedisp = (havebase
14120                   || needindex
14121                   || (havesib && (haveindex || scale != 0)));
14122
14123       if (!intel_syntax)
14124         if (modrm.mod != 0 || base == 5)
14125           {
14126             if (havedisp || riprel)
14127               print_displacement (scratchbuf, disp);
14128             else
14129               print_operand_value (scratchbuf, 1, disp);
14130             oappend (scratchbuf);
14131             if (riprel)
14132               {
14133                 set_op (disp, 1);
14134                 oappend (!addr32flag ? "(%rip)" : "(%eip)");
14135               }
14136           }
14137
14138       if ((havebase || haveindex || needindex || needaddr32 || riprel)
14139           && (address_mode != mode_64bit
14140               || ((bytemode != v_bnd_mode)
14141                   && (bytemode != v_bndmk_mode)
14142                   && (bytemode != bnd_mode)
14143                   && (bytemode != bnd_swap_mode))))
14144         used_prefixes |= PREFIX_ADDR;
14145
14146       if (havedisp || (intel_syntax && riprel))
14147         {
14148           *obufp++ = open_char;
14149           if (intel_syntax && riprel)
14150             {
14151               set_op (disp, 1);
14152               oappend (!addr32flag ? "rip" : "eip");
14153             }
14154           *obufp = '\0';
14155           if (havebase)
14156             oappend (address_mode == mode_64bit && !addr32flag
14157                      ? names64[rbase] : names32[rbase]);
14158           if (havesib)
14159             {
14160               /* ESP/RSP won't allow index.  If base isn't ESP/RSP,
14161                  print index to tell base + index from base.  */
14162               if (scale != 0
14163                   || needindex
14164                   || haveindex
14165                   || (havebase && base != ESP_REG_NUM))
14166                 {
14167                   if (!intel_syntax || havebase)
14168                     {
14169                       *obufp++ = separator_char;
14170                       *obufp = '\0';
14171                     }
14172                   if (haveindex)
14173                     oappend (address_mode == mode_64bit && !addr32flag
14174                              ? indexes64[vindex] : indexes32[vindex]);
14175                   else
14176                     oappend (address_mode == mode_64bit && !addr32flag
14177                              ? index64 : index32);
14178
14179                   *obufp++ = scale_char;
14180                   *obufp = '\0';
14181                   sprintf (scratchbuf, "%d", 1 << scale);
14182                   oappend (scratchbuf);
14183                 }
14184             }
14185           if (intel_syntax
14186               && (disp || modrm.mod != 0 || base == 5))
14187             {
14188               if (!havedisp || (bfd_signed_vma) disp >= 0)
14189                 {
14190                   *obufp++ = '+';
14191                   *obufp = '\0';
14192                 }
14193               else if (modrm.mod != 1 && disp != -disp)
14194                 {
14195                   *obufp++ = '-';
14196                   *obufp = '\0';
14197                   disp = - (bfd_signed_vma) disp;
14198                 }
14199
14200               if (havedisp)
14201                 print_displacement (scratchbuf, disp);
14202               else
14203                 print_operand_value (scratchbuf, 1, disp);
14204               oappend (scratchbuf);
14205             }
14206
14207           *obufp++ = close_char;
14208           *obufp = '\0';
14209         }
14210       else if (intel_syntax)
14211         {
14212           if (modrm.mod != 0 || base == 5)
14213             {
14214               if (!active_seg_prefix)
14215                 {
14216                   oappend (names_seg[ds_reg - es_reg]);
14217                   oappend (":");
14218                 }
14219               print_operand_value (scratchbuf, 1, disp);
14220               oappend (scratchbuf);
14221             }
14222         }
14223     }
14224   else if (bytemode == v_bnd_mode
14225            || bytemode == v_bndmk_mode
14226            || bytemode == bnd_mode
14227            || bytemode == bnd_swap_mode)
14228     {
14229       oappend ("(bad)");
14230       return;
14231     }
14232   else
14233     {
14234       /* 16 bit address mode */
14235       used_prefixes |= prefixes & PREFIX_ADDR;
14236       switch (modrm.mod)
14237         {
14238         case 0:
14239           if (modrm.rm == 6)
14240             {
14241               disp = get16 ();
14242               if ((disp & 0x8000) != 0)
14243                 disp -= 0x10000;
14244             }
14245           break;
14246         case 1:
14247           FETCH_DATA (the_info, codep + 1);
14248           disp = *codep++;
14249           if ((disp & 0x80) != 0)
14250             disp -= 0x100;
14251           if (vex.evex && shift > 0)
14252             disp <<= shift;
14253           break;
14254         case 2:
14255           disp = get16 ();
14256           if ((disp & 0x8000) != 0)
14257             disp -= 0x10000;
14258           break;
14259         }
14260
14261       if (!intel_syntax)
14262         if (modrm.mod != 0 || modrm.rm == 6)
14263           {
14264             print_displacement (scratchbuf, disp);
14265             oappend (scratchbuf);
14266           }
14267
14268       if (modrm.mod != 0 || modrm.rm != 6)
14269         {
14270           *obufp++ = open_char;
14271           *obufp = '\0';
14272           oappend (index16[modrm.rm]);
14273           if (intel_syntax
14274               && (disp || modrm.mod != 0 || modrm.rm == 6))
14275             {
14276               if ((bfd_signed_vma) disp >= 0)
14277                 {
14278                   *obufp++ = '+';
14279                   *obufp = '\0';
14280                 }
14281               else if (modrm.mod != 1)
14282                 {
14283                   *obufp++ = '-';
14284                   *obufp = '\0';
14285                   disp = - (bfd_signed_vma) disp;
14286                 }
14287
14288               print_displacement (scratchbuf, disp);
14289               oappend (scratchbuf);
14290             }
14291
14292           *obufp++ = close_char;
14293           *obufp = '\0';
14294         }
14295       else if (intel_syntax)
14296         {
14297           if (!active_seg_prefix)
14298             {
14299               oappend (names_seg[ds_reg - es_reg]);
14300               oappend (":");
14301             }
14302           print_operand_value (scratchbuf, 1, disp & 0xffff);
14303           oappend (scratchbuf);
14304         }
14305     }
14306   if (vex.evex && vex.b
14307       && (bytemode == x_mode
14308           || bytemode == xmmq_mode
14309           || bytemode == evex_half_bcst_xmmq_mode))
14310     {
14311       if (vex.w
14312           || bytemode == xmmq_mode
14313           || bytemode == evex_half_bcst_xmmq_mode)
14314         {
14315           switch (vex.length)
14316             {
14317             case 128:
14318               oappend ("{1to2}");
14319               break;
14320             case 256:
14321               oappend ("{1to4}");
14322               break;
14323             case 512:
14324               oappend ("{1to8}");
14325               break;
14326             default:
14327               abort ();
14328             }
14329         }
14330       else
14331         {
14332           switch (vex.length)
14333             {
14334             case 128:
14335               oappend ("{1to4}");
14336               break;
14337             case 256:
14338               oappend ("{1to8}");
14339               break;
14340             case 512:
14341               oappend ("{1to16}");
14342               break;
14343             default:
14344               abort ();
14345             }
14346         }
14347     }
14348 }
14349
14350 static void
14351 OP_E (int bytemode, int sizeflag)
14352 {
14353   /* Skip mod/rm byte.  */
14354   MODRM_CHECK;
14355   codep++;
14356
14357   if (modrm.mod == 3)
14358     OP_E_register (bytemode, sizeflag);
14359   else
14360     OP_E_memory (bytemode, sizeflag);
14361 }
14362
14363 static void
14364 OP_G (int bytemode, int sizeflag)
14365 {
14366   int add = 0;
14367   const char **names;
14368   USED_REX (REX_R);
14369   if (rex & REX_R)
14370     add += 8;
14371   switch (bytemode)
14372     {
14373     case b_mode:
14374       USED_REX (0);
14375       if (rex)
14376         oappend (names8rex[modrm.reg + add]);
14377       else
14378         oappend (names8[modrm.reg + add]);
14379       break;
14380     case w_mode:
14381       oappend (names16[modrm.reg + add]);
14382       break;
14383     case d_mode:
14384     case db_mode:
14385     case dw_mode:
14386       oappend (names32[modrm.reg + add]);
14387       break;
14388     case q_mode:
14389       oappend (names64[modrm.reg + add]);
14390       break;
14391     case bnd_mode:
14392       if (modrm.reg > 0x3)
14393         {
14394           oappend ("(bad)");
14395           return;
14396         }
14397       oappend (names_bnd[modrm.reg]);
14398       break;
14399     case v_mode:
14400     case dq_mode:
14401     case dqb_mode:
14402     case dqd_mode:
14403     case dqw_mode:
14404     case movsxd_mode:
14405       USED_REX (REX_W);
14406       if (rex & REX_W)
14407         oappend (names64[modrm.reg + add]);
14408       else
14409         {
14410           if ((sizeflag & DFLAG)
14411               || (bytemode != v_mode && bytemode != movsxd_mode))
14412             oappend (names32[modrm.reg + add]);
14413           else
14414             oappend (names16[modrm.reg + add]);
14415           used_prefixes |= (prefixes & PREFIX_DATA);
14416         }
14417       break;
14418     case va_mode:
14419       names = (address_mode == mode_64bit
14420                ? names64 : names32);
14421       if (!(prefixes & PREFIX_ADDR))
14422         {
14423           if (address_mode == mode_16bit)
14424             names = names16;
14425         }
14426       else
14427         {
14428           /* Remove "addr16/addr32".  */
14429           all_prefixes[last_addr_prefix] = 0;
14430           names = (address_mode != mode_32bit
14431                        ? names32 : names16);
14432           used_prefixes |= PREFIX_ADDR;
14433         }
14434       oappend (names[modrm.reg + add]);
14435       break;
14436     case m_mode:
14437       if (address_mode == mode_64bit)
14438         oappend (names64[modrm.reg + add]);
14439       else
14440         oappend (names32[modrm.reg + add]);
14441       break;
14442     case mask_bd_mode:
14443     case mask_mode:
14444       if ((modrm.reg + add) > 0x7)
14445         {
14446           oappend ("(bad)");
14447           return;
14448         }
14449       oappend (names_mask[modrm.reg + add]);
14450       break;
14451     default:
14452       oappend (INTERNAL_DISASSEMBLER_ERROR);
14453       break;
14454     }
14455 }
14456
14457 static bfd_vma
14458 get64 (void)
14459 {
14460   bfd_vma x;
14461 #ifdef BFD64
14462   unsigned int a;
14463   unsigned int b;
14464
14465   FETCH_DATA (the_info, codep + 8);
14466   a = *codep++ & 0xff;
14467   a |= (*codep++ & 0xff) << 8;
14468   a |= (*codep++ & 0xff) << 16;
14469   a |= (*codep++ & 0xffu) << 24;
14470   b = *codep++ & 0xff;
14471   b |= (*codep++ & 0xff) << 8;
14472   b |= (*codep++ & 0xff) << 16;
14473   b |= (*codep++ & 0xffu) << 24;
14474   x = a + ((bfd_vma) b << 32);
14475 #else
14476   abort ();
14477   x = 0;
14478 #endif
14479   return x;
14480 }
14481
14482 static bfd_signed_vma
14483 get32 (void)
14484 {
14485   bfd_signed_vma x = 0;
14486
14487   FETCH_DATA (the_info, codep + 4);
14488   x = *codep++ & (bfd_signed_vma) 0xff;
14489   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
14490   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
14491   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
14492   return x;
14493 }
14494
14495 static bfd_signed_vma
14496 get32s (void)
14497 {
14498   bfd_signed_vma x = 0;
14499
14500   FETCH_DATA (the_info, codep + 4);
14501   x = *codep++ & (bfd_signed_vma) 0xff;
14502   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
14503   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
14504   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
14505
14506   x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
14507
14508   return x;
14509 }
14510
14511 static int
14512 get16 (void)
14513 {
14514   int x = 0;
14515
14516   FETCH_DATA (the_info, codep + 2);
14517   x = *codep++ & 0xff;
14518   x |= (*codep++ & 0xff) << 8;
14519   return x;
14520 }
14521
14522 static void
14523 set_op (bfd_vma op, int riprel)
14524 {
14525   op_index[op_ad] = op_ad;
14526   if (address_mode == mode_64bit)
14527     {
14528       op_address[op_ad] = op;
14529       op_riprel[op_ad] = riprel;
14530     }
14531   else
14532     {
14533       /* Mask to get a 32-bit address.  */
14534       op_address[op_ad] = op & 0xffffffff;
14535       op_riprel[op_ad] = riprel & 0xffffffff;
14536     }
14537 }
14538
14539 static void
14540 OP_REG (int code, int sizeflag)
14541 {
14542   const char *s;
14543   int add;
14544
14545   switch (code)
14546     {
14547     case es_reg: case ss_reg: case cs_reg:
14548     case ds_reg: case fs_reg: case gs_reg:
14549       oappend (names_seg[code - es_reg]);
14550       return;
14551     }
14552
14553   USED_REX (REX_B);
14554   if (rex & REX_B)
14555     add = 8;
14556   else
14557     add = 0;
14558
14559   switch (code)
14560     {
14561     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
14562     case sp_reg: case bp_reg: case si_reg: case di_reg:
14563       s = names16[code - ax_reg + add];
14564       break;
14565     case al_reg: case ah_reg: case cl_reg: case ch_reg:
14566     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
14567       USED_REX (0);
14568       if (rex)
14569         s = names8rex[code - al_reg + add];
14570       else
14571         s = names8[code - al_reg];
14572       break;
14573     case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
14574     case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
14575       if (address_mode == mode_64bit
14576           && ((sizeflag & DFLAG) || (rex & REX_W)))
14577         {
14578           s = names64[code - rAX_reg + add];
14579           break;
14580         }
14581       code += eAX_reg - rAX_reg;
14582       /* Fall through.  */
14583     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
14584     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
14585       USED_REX (REX_W);
14586       if (rex & REX_W)
14587         s = names64[code - eAX_reg + add];
14588       else
14589         {
14590           if (sizeflag & DFLAG)
14591             s = names32[code - eAX_reg + add];
14592           else
14593             s = names16[code - eAX_reg + add];
14594           used_prefixes |= (prefixes & PREFIX_DATA);
14595         }
14596       break;
14597     default:
14598       s = INTERNAL_DISASSEMBLER_ERROR;
14599       break;
14600     }
14601   oappend (s);
14602 }
14603
14604 static void
14605 OP_IMREG (int code, int sizeflag)
14606 {
14607   const char *s;
14608
14609   switch (code)
14610     {
14611     case indir_dx_reg:
14612       if (intel_syntax)
14613         s = "dx";
14614       else
14615         s = "(%dx)";
14616       break;
14617     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
14618     case sp_reg: case bp_reg: case si_reg: case di_reg:
14619       s = names16[code - ax_reg];
14620       break;
14621     case es_reg: case ss_reg: case cs_reg:
14622     case ds_reg: case fs_reg: case gs_reg:
14623       s = names_seg[code - es_reg];
14624       break;
14625     case al_reg: case ah_reg: case cl_reg: case ch_reg:
14626     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
14627       USED_REX (0);
14628       if (rex)
14629         s = names8rex[code - al_reg];
14630       else
14631         s = names8[code - al_reg];
14632       break;
14633     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
14634     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
14635       USED_REX (REX_W);
14636       if (rex & REX_W)
14637         s = names64[code - eAX_reg];
14638       else
14639         {
14640           if (sizeflag & DFLAG)
14641             s = names32[code - eAX_reg];
14642           else
14643             s = names16[code - eAX_reg];
14644           used_prefixes |= (prefixes & PREFIX_DATA);
14645         }
14646       break;
14647     case z_mode_ax_reg:
14648       if ((rex & REX_W) || (sizeflag & DFLAG))
14649         s = *names32;
14650       else
14651         s = *names16;
14652       if (!(rex & REX_W))
14653         used_prefixes |= (prefixes & PREFIX_DATA);
14654       break;
14655     default:
14656       s = INTERNAL_DISASSEMBLER_ERROR;
14657       break;
14658     }
14659   oappend (s);
14660 }
14661
14662 static void
14663 OP_I (int bytemode, int sizeflag)
14664 {
14665   bfd_signed_vma op;
14666   bfd_signed_vma mask = -1;
14667
14668   switch (bytemode)
14669     {
14670     case b_mode:
14671       FETCH_DATA (the_info, codep + 1);
14672       op = *codep++;
14673       mask = 0xff;
14674       break;
14675     case v_mode:
14676       USED_REX (REX_W);
14677       if (rex & REX_W)
14678         op = get32s ();
14679       else
14680         {
14681           if (sizeflag & DFLAG)
14682             {
14683               op = get32 ();
14684               mask = 0xffffffff;
14685             }
14686           else
14687             {
14688               op = get16 ();
14689               mask = 0xfffff;
14690             }
14691           used_prefixes |= (prefixes & PREFIX_DATA);
14692         }
14693       break;
14694     case d_mode:
14695       mask = 0xffffffff;
14696       op = get32 ();
14697       break;
14698     case w_mode:
14699       mask = 0xfffff;
14700       op = get16 ();
14701       break;
14702     case const_1_mode:
14703       if (intel_syntax)
14704         oappend ("1");
14705       return;
14706     default:
14707       oappend (INTERNAL_DISASSEMBLER_ERROR);
14708       return;
14709     }
14710
14711   op &= mask;
14712   scratchbuf[0] = '$';
14713   print_operand_value (scratchbuf + 1, 1, op);
14714   oappend_maybe_intel (scratchbuf);
14715   scratchbuf[0] = '\0';
14716 }
14717
14718 static void
14719 OP_I64 (int bytemode, int sizeflag)
14720 {
14721   if (bytemode != v_mode || address_mode != mode_64bit || !(rex & REX_W))
14722     {
14723       OP_I (bytemode, sizeflag);
14724       return;
14725     }
14726
14727   USED_REX (REX_W);
14728
14729   scratchbuf[0] = '$';
14730   print_operand_value (scratchbuf + 1, 1, get64 ());
14731   oappend_maybe_intel (scratchbuf);
14732   scratchbuf[0] = '\0';
14733 }
14734
14735 static void
14736 OP_sI (int bytemode, int sizeflag)
14737 {
14738   bfd_signed_vma op;
14739
14740   switch (bytemode)
14741     {
14742     case b_mode:
14743     case b_T_mode:
14744       FETCH_DATA (the_info, codep + 1);
14745       op = *codep++;
14746       if ((op & 0x80) != 0)
14747         op -= 0x100;
14748       if (bytemode == b_T_mode)
14749         {
14750           if (address_mode != mode_64bit
14751               || !((sizeflag & DFLAG) || (rex & REX_W)))
14752             {
14753               /* The operand-size prefix is overridden by a REX prefix.  */
14754               if ((sizeflag & DFLAG) || (rex & REX_W))
14755                 op &= 0xffffffff;
14756               else
14757                 op &= 0xffff;
14758           }
14759         }
14760       else
14761         {
14762           if (!(rex & REX_W))
14763             {
14764               if (sizeflag & DFLAG)
14765                 op &= 0xffffffff;
14766               else
14767                 op &= 0xffff;
14768             }
14769         }
14770       break;
14771     case v_mode:
14772       /* The operand-size prefix is overridden by a REX prefix.  */
14773       if ((sizeflag & DFLAG) || (rex & REX_W))
14774         op = get32s ();
14775       else
14776         op = get16 ();
14777       break;
14778     default:
14779       oappend (INTERNAL_DISASSEMBLER_ERROR);
14780       return;
14781     }
14782
14783   scratchbuf[0] = '$';
14784   print_operand_value (scratchbuf + 1, 1, op);
14785   oappend_maybe_intel (scratchbuf);
14786 }
14787
14788 static void
14789 OP_J (int bytemode, int sizeflag)
14790 {
14791   bfd_vma disp;
14792   bfd_vma mask = -1;
14793   bfd_vma segment = 0;
14794
14795   switch (bytemode)
14796     {
14797     case b_mode:
14798       FETCH_DATA (the_info, codep + 1);
14799       disp = *codep++;
14800       if ((disp & 0x80) != 0)
14801         disp -= 0x100;
14802       break;
14803     case v_mode:
14804       if (isa64 != intel64)
14805     case dqw_mode:
14806         USED_REX (REX_W);
14807       if ((sizeflag & DFLAG)
14808           || (address_mode == mode_64bit
14809               && ((isa64 == intel64 && bytemode != dqw_mode)
14810                   || (rex & REX_W))))
14811         disp = get32s ();
14812       else
14813         {
14814           disp = get16 ();
14815           if ((disp & 0x8000) != 0)
14816             disp -= 0x10000;
14817           /* In 16bit mode, address is wrapped around at 64k within
14818              the same segment.  Otherwise, a data16 prefix on a jump
14819              instruction means that the pc is masked to 16 bits after
14820              the displacement is added!  */
14821           mask = 0xffff;
14822           if ((prefixes & PREFIX_DATA) == 0)
14823             segment = ((start_pc + (codep - start_codep))
14824                        & ~((bfd_vma) 0xffff));
14825         }
14826       if (address_mode != mode_64bit
14827           || (isa64 != intel64 && !(rex & REX_W)))
14828         used_prefixes |= (prefixes & PREFIX_DATA);
14829       break;
14830     default:
14831       oappend (INTERNAL_DISASSEMBLER_ERROR);
14832       return;
14833     }
14834   disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment;
14835   set_op (disp, 0);
14836   print_operand_value (scratchbuf, 1, disp);
14837   oappend (scratchbuf);
14838 }
14839
14840 static void
14841 OP_SEG (int bytemode, int sizeflag)
14842 {
14843   if (bytemode == w_mode)
14844     oappend (names_seg[modrm.reg]);
14845   else
14846     OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
14847 }
14848
14849 static void
14850 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
14851 {
14852   int seg, offset;
14853
14854   if (sizeflag & DFLAG)
14855     {
14856       offset = get32 ();
14857       seg = get16 ();
14858     }
14859   else
14860     {
14861       offset = get16 ();
14862       seg = get16 ();
14863     }
14864   used_prefixes |= (prefixes & PREFIX_DATA);
14865   if (intel_syntax)
14866     sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
14867   else
14868     sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
14869   oappend (scratchbuf);
14870 }
14871
14872 static void
14873 OP_OFF (int bytemode, int sizeflag)
14874 {
14875   bfd_vma off;
14876
14877   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
14878     intel_operand_size (bytemode, sizeflag);
14879   append_seg ();
14880
14881   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
14882     off = get32 ();
14883   else
14884     off = get16 ();
14885
14886   if (intel_syntax)
14887     {
14888       if (!active_seg_prefix)
14889         {
14890           oappend (names_seg[ds_reg - es_reg]);
14891           oappend (":");
14892         }
14893     }
14894   print_operand_value (scratchbuf, 1, off);
14895   oappend (scratchbuf);
14896 }
14897
14898 static void
14899 OP_OFF64 (int bytemode, int sizeflag)
14900 {
14901   bfd_vma off;
14902
14903   if (address_mode != mode_64bit
14904       || (prefixes & PREFIX_ADDR))
14905     {
14906       OP_OFF (bytemode, sizeflag);
14907       return;
14908     }
14909
14910   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
14911     intel_operand_size (bytemode, sizeflag);
14912   append_seg ();
14913
14914   off = get64 ();
14915
14916   if (intel_syntax)
14917     {
14918       if (!active_seg_prefix)
14919         {
14920           oappend (names_seg[ds_reg - es_reg]);
14921           oappend (":");
14922         }
14923     }
14924   print_operand_value (scratchbuf, 1, off);
14925   oappend (scratchbuf);
14926 }
14927
14928 static void
14929 ptr_reg (int code, int sizeflag)
14930 {
14931   const char *s;
14932
14933   *obufp++ = open_char;
14934   used_prefixes |= (prefixes & PREFIX_ADDR);
14935   if (address_mode == mode_64bit)
14936     {
14937       if (!(sizeflag & AFLAG))
14938         s = names32[code - eAX_reg];
14939       else
14940         s = names64[code - eAX_reg];
14941     }
14942   else if (sizeflag & AFLAG)
14943     s = names32[code - eAX_reg];
14944   else
14945     s = names16[code - eAX_reg];
14946   oappend (s);
14947   *obufp++ = close_char;
14948   *obufp = 0;
14949 }
14950
14951 static void
14952 OP_ESreg (int code, int sizeflag)
14953 {
14954   if (intel_syntax)
14955     {
14956       switch (codep[-1])
14957         {
14958         case 0x6d:      /* insw/insl */
14959           intel_operand_size (z_mode, sizeflag);
14960           break;
14961         case 0xa5:      /* movsw/movsl/movsq */
14962         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
14963         case 0xab:      /* stosw/stosl */
14964         case 0xaf:      /* scasw/scasl */
14965           intel_operand_size (v_mode, sizeflag);
14966           break;
14967         default:
14968           intel_operand_size (b_mode, sizeflag);
14969         }
14970     }
14971   oappend_maybe_intel ("%es:");
14972   ptr_reg (code, sizeflag);
14973 }
14974
14975 static void
14976 OP_DSreg (int code, int sizeflag)
14977 {
14978   if (intel_syntax)
14979     {
14980       switch (codep[-1])
14981         {
14982         case 0x6f:      /* outsw/outsl */
14983           intel_operand_size (z_mode, sizeflag);
14984           break;
14985         case 0xa5:      /* movsw/movsl/movsq */
14986         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
14987         case 0xad:      /* lodsw/lodsl/lodsq */
14988           intel_operand_size (v_mode, sizeflag);
14989           break;
14990         default:
14991           intel_operand_size (b_mode, sizeflag);
14992         }
14993     }
14994   /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
14995      default segment register DS is printed.  */
14996   if (!active_seg_prefix)
14997     active_seg_prefix = PREFIX_DS;
14998   append_seg ();
14999   ptr_reg (code, sizeflag);
15000 }
15001
15002 static void
15003 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15004 {
15005   int add;
15006   if (rex & REX_R)
15007     {
15008       USED_REX (REX_R);
15009       add = 8;
15010     }
15011   else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
15012     {
15013       all_prefixes[last_lock_prefix] = 0;
15014       used_prefixes |= PREFIX_LOCK;
15015       add = 8;
15016     }
15017   else
15018     add = 0;
15019   sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
15020   oappend_maybe_intel (scratchbuf);
15021 }
15022
15023 static void
15024 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15025 {
15026   int add;
15027   USED_REX (REX_R);
15028   if (rex & REX_R)
15029     add = 8;
15030   else
15031     add = 0;
15032   if (intel_syntax)
15033     sprintf (scratchbuf, "db%d", modrm.reg + add);
15034   else
15035     sprintf (scratchbuf, "%%db%d", modrm.reg + add);
15036   oappend (scratchbuf);
15037 }
15038
15039 static void
15040 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15041 {
15042   sprintf (scratchbuf, "%%tr%d", modrm.reg);
15043   oappend_maybe_intel (scratchbuf);
15044 }
15045
15046 static void
15047 OP_R (int bytemode, int sizeflag)
15048 {
15049   /* Skip mod/rm byte.  */
15050   MODRM_CHECK;
15051   codep++;
15052   OP_E_register (bytemode, sizeflag);
15053 }
15054
15055 static void
15056 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15057 {
15058   int reg = modrm.reg;
15059   const char **names;
15060
15061   used_prefixes |= (prefixes & PREFIX_DATA);
15062   if (prefixes & PREFIX_DATA)
15063     {
15064       names = names_xmm;
15065       USED_REX (REX_R);
15066       if (rex & REX_R)
15067         reg += 8;
15068     }
15069   else
15070     names = names_mm;
15071   oappend (names[reg]);
15072 }
15073
15074 static void
15075 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
15076 {
15077   int reg = modrm.reg;
15078   const char **names;
15079
15080   USED_REX (REX_R);
15081   if (rex & REX_R)
15082     reg += 8;
15083   if (vex.evex)
15084     {
15085       if (!vex.r)
15086         reg += 16;
15087     }
15088
15089   if (need_vex
15090       && bytemode != xmm_mode
15091       && bytemode != xmmq_mode
15092       && bytemode != evex_half_bcst_xmmq_mode
15093       && bytemode != ymm_mode
15094       && bytemode != scalar_mode)
15095     {
15096       switch (vex.length)
15097         {
15098         case 128:
15099           names = names_xmm;
15100           break;
15101         case 256:
15102           if (vex.w
15103               || (bytemode != vex_vsib_q_w_dq_mode
15104                   && bytemode != vex_vsib_q_w_d_mode))
15105             names = names_ymm;
15106           else
15107             names = names_xmm;
15108           break;
15109         case 512:
15110           names = names_zmm;
15111           break;
15112         default:
15113           abort ();
15114         }
15115     }
15116   else if (bytemode == xmmq_mode
15117            || bytemode == evex_half_bcst_xmmq_mode)
15118     {
15119       switch (vex.length)
15120         {
15121         case 128:
15122         case 256:
15123           names = names_xmm;
15124           break;
15125         case 512:
15126           names = names_ymm;
15127           break;
15128         default:
15129           abort ();
15130         }
15131     }
15132   else if (bytemode == ymm_mode)
15133     names = names_ymm;
15134   else
15135     names = names_xmm;
15136   oappend (names[reg]);
15137 }
15138
15139 static void
15140 OP_EM (int bytemode, int sizeflag)
15141 {
15142   int reg;
15143   const char **names;
15144
15145   if (modrm.mod != 3)
15146     {
15147       if (intel_syntax
15148           && (bytemode == v_mode || bytemode == v_swap_mode))
15149         {
15150           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
15151           used_prefixes |= (prefixes & PREFIX_DATA);
15152         }
15153       OP_E (bytemode, sizeflag);
15154       return;
15155     }
15156
15157   if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
15158     swap_operand ();
15159
15160   /* Skip mod/rm byte.  */
15161   MODRM_CHECK;
15162   codep++;
15163   used_prefixes |= (prefixes & PREFIX_DATA);
15164   reg = modrm.rm;
15165   if (prefixes & PREFIX_DATA)
15166     {
15167       names = names_xmm;
15168       USED_REX (REX_B);
15169       if (rex & REX_B)
15170         reg += 8;
15171     }
15172   else
15173     names = names_mm;
15174   oappend (names[reg]);
15175 }
15176
15177 /* cvt* are the only instructions in sse2 which have
15178    both SSE and MMX operands and also have 0x66 prefix
15179    in their opcode. 0x66 was originally used to differentiate
15180    between SSE and MMX instruction(operands). So we have to handle the
15181    cvt* separately using OP_EMC and OP_MXC */
15182 static void
15183 OP_EMC (int bytemode, int sizeflag)
15184 {
15185   if (modrm.mod != 3)
15186     {
15187       if (intel_syntax && bytemode == v_mode)
15188         {
15189           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
15190           used_prefixes |= (prefixes & PREFIX_DATA);
15191         }
15192       OP_E (bytemode, sizeflag);
15193       return;
15194     }
15195
15196   /* Skip mod/rm byte.  */
15197   MODRM_CHECK;
15198   codep++;
15199   used_prefixes |= (prefixes & PREFIX_DATA);
15200   oappend (names_mm[modrm.rm]);
15201 }
15202
15203 static void
15204 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15205 {
15206   used_prefixes |= (prefixes & PREFIX_DATA);
15207   oappend (names_mm[modrm.reg]);
15208 }
15209
15210 static void
15211 OP_EX (int bytemode, int sizeflag)
15212 {
15213   int reg;
15214   const char **names;
15215
15216   /* Skip mod/rm byte.  */
15217   MODRM_CHECK;
15218   codep++;
15219
15220   if (modrm.mod != 3)
15221     {
15222       OP_E_memory (bytemode, sizeflag);
15223       return;
15224     }
15225
15226   reg = modrm.rm;
15227   USED_REX (REX_B);
15228   if (rex & REX_B)
15229     reg += 8;
15230   if (vex.evex)
15231     {
15232       USED_REX (REX_X);
15233       if ((rex & REX_X))
15234         reg += 16;
15235     }
15236
15237   if ((sizeflag & SUFFIX_ALWAYS)
15238       && (bytemode == x_swap_mode
15239           || bytemode == d_swap_mode
15240           || bytemode == d_scalar_swap_mode
15241           || bytemode == q_swap_mode
15242           || bytemode == q_scalar_swap_mode))
15243     swap_operand ();
15244
15245   if (need_vex
15246       && bytemode != xmm_mode
15247       && bytemode != xmmdw_mode
15248       && bytemode != xmmqd_mode
15249       && bytemode != xmm_mb_mode
15250       && bytemode != xmm_mw_mode
15251       && bytemode != xmm_md_mode
15252       && bytemode != xmm_mq_mode
15253       && bytemode != xmmq_mode
15254       && bytemode != evex_half_bcst_xmmq_mode
15255       && bytemode != ymm_mode
15256       && bytemode != d_scalar_swap_mode
15257       && bytemode != q_scalar_swap_mode
15258       && bytemode != vex_scalar_w_dq_mode)
15259     {
15260       switch (vex.length)
15261         {
15262         case 128:
15263           names = names_xmm;
15264           break;
15265         case 256:
15266           names = names_ymm;
15267           break;
15268         case 512:
15269           names = names_zmm;
15270           break;
15271         default:
15272           abort ();
15273         }
15274     }
15275   else if (bytemode == xmmq_mode
15276            || bytemode == evex_half_bcst_xmmq_mode)
15277     {
15278       switch (vex.length)
15279         {
15280         case 128:
15281         case 256:
15282           names = names_xmm;
15283           break;
15284         case 512:
15285           names = names_ymm;
15286           break;
15287         default:
15288           abort ();
15289         }
15290     }
15291   else if (bytemode == ymm_mode)
15292     names = names_ymm;
15293   else
15294     names = names_xmm;
15295   oappend (names[reg]);
15296 }
15297
15298 static void
15299 OP_MS (int bytemode, int sizeflag)
15300 {
15301   if (modrm.mod == 3)
15302     OP_EM (bytemode, sizeflag);
15303   else
15304     BadOp ();
15305 }
15306
15307 static void
15308 OP_XS (int bytemode, int sizeflag)
15309 {
15310   if (modrm.mod == 3)
15311     OP_EX (bytemode, sizeflag);
15312   else
15313     BadOp ();
15314 }
15315
15316 static void
15317 OP_M (int bytemode, int sizeflag)
15318 {
15319   if (modrm.mod == 3)
15320     /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
15321     BadOp ();
15322   else
15323     OP_E (bytemode, sizeflag);
15324 }
15325
15326 static void
15327 OP_0f07 (int bytemode, int sizeflag)
15328 {
15329   if (modrm.mod != 3 || modrm.rm != 0)
15330     BadOp ();
15331   else
15332     OP_E (bytemode, sizeflag);
15333 }
15334
15335 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
15336    32bit mode and "xchg %rax,%rax" in 64bit mode.  */
15337
15338 static void
15339 NOP_Fixup1 (int bytemode, int sizeflag)
15340 {
15341   if ((prefixes & PREFIX_DATA) != 0
15342       || (rex != 0
15343           && rex != 0x48
15344           && address_mode == mode_64bit))
15345     OP_REG (bytemode, sizeflag);
15346   else
15347     strcpy (obuf, "nop");
15348 }
15349
15350 static void
15351 NOP_Fixup2 (int bytemode, int sizeflag)
15352 {
15353   if ((prefixes & PREFIX_DATA) != 0
15354       || (rex != 0
15355           && rex != 0x48
15356           && address_mode == mode_64bit))
15357     OP_IMREG (bytemode, sizeflag);
15358 }
15359
15360 static const char *const Suffix3DNow[] = {
15361 /* 00 */        NULL,           NULL,           NULL,           NULL,
15362 /* 04 */        NULL,           NULL,           NULL,           NULL,
15363 /* 08 */        NULL,           NULL,           NULL,           NULL,
15364 /* 0C */        "pi2fw",        "pi2fd",        NULL,           NULL,
15365 /* 10 */        NULL,           NULL,           NULL,           NULL,
15366 /* 14 */        NULL,           NULL,           NULL,           NULL,
15367 /* 18 */        NULL,           NULL,           NULL,           NULL,
15368 /* 1C */        "pf2iw",        "pf2id",        NULL,           NULL,
15369 /* 20 */        NULL,           NULL,           NULL,           NULL,
15370 /* 24 */        NULL,           NULL,           NULL,           NULL,
15371 /* 28 */        NULL,           NULL,           NULL,           NULL,
15372 /* 2C */        NULL,           NULL,           NULL,           NULL,
15373 /* 30 */        NULL,           NULL,           NULL,           NULL,
15374 /* 34 */        NULL,           NULL,           NULL,           NULL,
15375 /* 38 */        NULL,           NULL,           NULL,           NULL,
15376 /* 3C */        NULL,           NULL,           NULL,           NULL,
15377 /* 40 */        NULL,           NULL,           NULL,           NULL,
15378 /* 44 */        NULL,           NULL,           NULL,           NULL,
15379 /* 48 */        NULL,           NULL,           NULL,           NULL,
15380 /* 4C */        NULL,           NULL,           NULL,           NULL,
15381 /* 50 */        NULL,           NULL,           NULL,           NULL,
15382 /* 54 */        NULL,           NULL,           NULL,           NULL,
15383 /* 58 */        NULL,           NULL,           NULL,           NULL,
15384 /* 5C */        NULL,           NULL,           NULL,           NULL,
15385 /* 60 */        NULL,           NULL,           NULL,           NULL,
15386 /* 64 */        NULL,           NULL,           NULL,           NULL,
15387 /* 68 */        NULL,           NULL,           NULL,           NULL,
15388 /* 6C */        NULL,           NULL,           NULL,           NULL,
15389 /* 70 */        NULL,           NULL,           NULL,           NULL,
15390 /* 74 */        NULL,           NULL,           NULL,           NULL,
15391 /* 78 */        NULL,           NULL,           NULL,           NULL,
15392 /* 7C */        NULL,           NULL,           NULL,           NULL,
15393 /* 80 */        NULL,           NULL,           NULL,           NULL,
15394 /* 84 */        NULL,           NULL,           NULL,           NULL,
15395 /* 88 */        NULL,           NULL,           "pfnacc",       NULL,
15396 /* 8C */        NULL,           NULL,           "pfpnacc",      NULL,
15397 /* 90 */        "pfcmpge",      NULL,           NULL,           NULL,
15398 /* 94 */        "pfmin",        NULL,           "pfrcp",        "pfrsqrt",
15399 /* 98 */        NULL,           NULL,           "pfsub",        NULL,
15400 /* 9C */        NULL,           NULL,           "pfadd",        NULL,
15401 /* A0 */        "pfcmpgt",      NULL,           NULL,           NULL,
15402 /* A4 */        "pfmax",        NULL,           "pfrcpit1",     "pfrsqit1",
15403 /* A8 */        NULL,           NULL,           "pfsubr",       NULL,
15404 /* AC */        NULL,           NULL,           "pfacc",        NULL,
15405 /* B0 */        "pfcmpeq",      NULL,           NULL,           NULL,
15406 /* B4 */        "pfmul",        NULL,           "pfrcpit2",     "pmulhrw",
15407 /* B8 */        NULL,           NULL,           NULL,           "pswapd",
15408 /* BC */        NULL,           NULL,           NULL,           "pavgusb",
15409 /* C0 */        NULL,           NULL,           NULL,           NULL,
15410 /* C4 */        NULL,           NULL,           NULL,           NULL,
15411 /* C8 */        NULL,           NULL,           NULL,           NULL,
15412 /* CC */        NULL,           NULL,           NULL,           NULL,
15413 /* D0 */        NULL,           NULL,           NULL,           NULL,
15414 /* D4 */        NULL,           NULL,           NULL,           NULL,
15415 /* D8 */        NULL,           NULL,           NULL,           NULL,
15416 /* DC */        NULL,           NULL,           NULL,           NULL,
15417 /* E0 */        NULL,           NULL,           NULL,           NULL,
15418 /* E4 */        NULL,           NULL,           NULL,           NULL,
15419 /* E8 */        NULL,           NULL,           NULL,           NULL,
15420 /* EC */        NULL,           NULL,           NULL,           NULL,
15421 /* F0 */        NULL,           NULL,           NULL,           NULL,
15422 /* F4 */        NULL,           NULL,           NULL,           NULL,
15423 /* F8 */        NULL,           NULL,           NULL,           NULL,
15424 /* FC */        NULL,           NULL,           NULL,           NULL,
15425 };
15426
15427 static void
15428 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15429 {
15430   const char *mnemonic;
15431
15432   FETCH_DATA (the_info, codep + 1);
15433   /* AMD 3DNow! instructions are specified by an opcode suffix in the
15434      place where an 8-bit immediate would normally go.  ie. the last
15435      byte of the instruction.  */
15436   obufp = mnemonicendp;
15437   mnemonic = Suffix3DNow[*codep++ & 0xff];
15438   if (mnemonic)
15439     oappend (mnemonic);
15440   else
15441     {
15442       /* Since a variable sized modrm/sib chunk is between the start
15443          of the opcode (0x0f0f) and the opcode suffix, we need to do
15444          all the modrm processing first, and don't know until now that
15445          we have a bad opcode.  This necessitates some cleaning up.  */
15446       op_out[0][0] = '\0';
15447       op_out[1][0] = '\0';
15448       BadOp ();
15449     }
15450   mnemonicendp = obufp;
15451 }
15452
15453 static struct op simd_cmp_op[] =
15454 {
15455   { STRING_COMMA_LEN ("eq") },
15456   { STRING_COMMA_LEN ("lt") },
15457   { STRING_COMMA_LEN ("le") },
15458   { STRING_COMMA_LEN ("unord") },
15459   { STRING_COMMA_LEN ("neq") },
15460   { STRING_COMMA_LEN ("nlt") },
15461   { STRING_COMMA_LEN ("nle") },
15462   { STRING_COMMA_LEN ("ord") }
15463 };
15464
15465 static void
15466 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15467 {
15468   unsigned int cmp_type;
15469
15470   FETCH_DATA (the_info, codep + 1);
15471   cmp_type = *codep++ & 0xff;
15472   if (cmp_type < ARRAY_SIZE (simd_cmp_op))
15473     {
15474       char suffix [3];
15475       char *p = mnemonicendp - 2;
15476       suffix[0] = p[0];
15477       suffix[1] = p[1];
15478       suffix[2] = '\0';
15479       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
15480       mnemonicendp += simd_cmp_op[cmp_type].len;
15481     }
15482   else
15483     {
15484       /* We have a reserved extension byte.  Output it directly.  */
15485       scratchbuf[0] = '$';
15486       print_operand_value (scratchbuf + 1, 1, cmp_type);
15487       oappend_maybe_intel (scratchbuf);
15488       scratchbuf[0] = '\0';
15489     }
15490 }
15491
15492 static void
15493 OP_Mwait (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
15494 {
15495   /* mwait %eax,%ecx / mwaitx %eax,%ecx,%ebx  */
15496   if (!intel_syntax)
15497     {
15498       strcpy (op_out[0], names32[0]);
15499       strcpy (op_out[1], names32[1]);
15500       if (bytemode == eBX_reg)
15501         strcpy (op_out[2], names32[3]);
15502       two_source_ops = 1;
15503     }
15504   /* Skip mod/rm byte.  */
15505   MODRM_CHECK;
15506   codep++;
15507 }
15508
15509 static void
15510 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
15511             int sizeflag ATTRIBUTE_UNUSED)
15512 {
15513   /* monitor %{e,r,}ax,%ecx,%edx"  */
15514   if (!intel_syntax)
15515     {
15516       const char **names = (address_mode == mode_64bit
15517                             ? names64 : names32);
15518
15519       if (prefixes & PREFIX_ADDR)
15520         {
15521           /* Remove "addr16/addr32".  */
15522           all_prefixes[last_addr_prefix] = 0;
15523           names = (address_mode != mode_32bit
15524                    ? names32 : names16);
15525           used_prefixes |= PREFIX_ADDR;
15526         }
15527       else if (address_mode == mode_16bit)
15528         names = names16;
15529       strcpy (op_out[0], names[0]);
15530       strcpy (op_out[1], names32[1]);
15531       strcpy (op_out[2], names32[2]);
15532       two_source_ops = 1;
15533     }
15534   /* Skip mod/rm byte.  */
15535   MODRM_CHECK;
15536   codep++;
15537 }
15538
15539 static void
15540 BadOp (void)
15541 {
15542   /* Throw away prefixes and 1st. opcode byte.  */
15543   codep = insn_codep + 1;
15544   oappend ("(bad)");
15545 }
15546
15547 static void
15548 REP_Fixup (int bytemode, int sizeflag)
15549 {
15550   /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
15551      lods and stos.  */
15552   if (prefixes & PREFIX_REPZ)
15553     all_prefixes[last_repz_prefix] = REP_PREFIX;
15554
15555   switch (bytemode)
15556     {
15557     case al_reg:
15558     case eAX_reg:
15559     case indir_dx_reg:
15560       OP_IMREG (bytemode, sizeflag);
15561       break;
15562     case eDI_reg:
15563       OP_ESreg (bytemode, sizeflag);
15564       break;
15565     case eSI_reg:
15566       OP_DSreg (bytemode, sizeflag);
15567       break;
15568     default:
15569       abort ();
15570       break;
15571     }
15572 }
15573
15574 static void
15575 SEP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15576 {
15577   if ( isa64 != amd64 )
15578     return;
15579
15580   obufp = obuf;
15581   BadOp ();
15582   mnemonicendp = obufp;
15583   ++codep;
15584 }
15585
15586 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
15587    "bnd".  */
15588
15589 static void
15590 BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15591 {
15592   if (prefixes & PREFIX_REPNZ)
15593     all_prefixes[last_repnz_prefix] = BND_PREFIX;
15594 }
15595
15596 /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
15597    "notrack".  */
15598
15599 static void
15600 NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED,
15601                int sizeflag ATTRIBUTE_UNUSED)
15602 {
15603   if (active_seg_prefix == PREFIX_DS
15604       && (address_mode != mode_64bit || last_data_prefix < 0))
15605     {
15606       /* NOTRACK prefix is only valid on indirect branch instructions.
15607          NB: DATA prefix is unsupported for Intel64.  */
15608       active_seg_prefix = 0;
15609       all_prefixes[last_seg_prefix] = NOTRACK_PREFIX;
15610     }
15611 }
15612
15613 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
15614    "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
15615  */
15616
15617 static void
15618 HLE_Fixup1 (int bytemode, int sizeflag)
15619 {
15620   if (modrm.mod != 3
15621       && (prefixes & PREFIX_LOCK) != 0)
15622     {
15623       if (prefixes & PREFIX_REPZ)
15624         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15625       if (prefixes & PREFIX_REPNZ)
15626         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15627     }
15628
15629   OP_E (bytemode, sizeflag);
15630 }
15631
15632 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
15633    "xacquire"/"xrelease" for memory operand.  No check for LOCK prefix.
15634  */
15635
15636 static void
15637 HLE_Fixup2 (int bytemode, int sizeflag)
15638 {
15639   if (modrm.mod != 3)
15640     {
15641       if (prefixes & PREFIX_REPZ)
15642         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15643       if (prefixes & PREFIX_REPNZ)
15644         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15645     }
15646
15647   OP_E (bytemode, sizeflag);
15648 }
15649
15650 /* Similar to OP_E.  But the 0xf3 prefixes should be displayed as
15651    "xrelease" for memory operand.  No check for LOCK prefix.   */
15652
15653 static void
15654 HLE_Fixup3 (int bytemode, int sizeflag)
15655 {
15656   if (modrm.mod != 3
15657       && last_repz_prefix > last_repnz_prefix
15658       && (prefixes & PREFIX_REPZ) != 0)
15659     all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15660
15661   OP_E (bytemode, sizeflag);
15662 }
15663
15664 static void
15665 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
15666 {
15667   USED_REX (REX_W);
15668   if (rex & REX_W)
15669     {
15670       /* Change cmpxchg8b to cmpxchg16b.  */
15671       char *p = mnemonicendp - 2;
15672       mnemonicendp = stpcpy (p, "16b");
15673       bytemode = o_mode;
15674     }
15675   else if ((prefixes & PREFIX_LOCK) != 0)
15676     {
15677       if (prefixes & PREFIX_REPZ)
15678         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15679       if (prefixes & PREFIX_REPNZ)
15680         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15681     }
15682
15683   OP_M (bytemode, sizeflag);
15684 }
15685
15686 static void
15687 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
15688 {
15689   const char **names;
15690
15691   if (need_vex)
15692     {
15693       switch (vex.length)
15694         {
15695         case 128:
15696           names = names_xmm;
15697           break;
15698         case 256:
15699           names = names_ymm;
15700           break;
15701         default:
15702           abort ();
15703         }
15704     }
15705   else
15706     names = names_xmm;
15707   oappend (names[reg]);
15708 }
15709
15710 static void
15711 CRC32_Fixup (int bytemode, int sizeflag)
15712 {
15713   /* Add proper suffix to "crc32".  */
15714   char *p = mnemonicendp;
15715
15716   switch (bytemode)
15717     {
15718     case b_mode:
15719       if (intel_syntax)
15720         goto skip;
15721
15722       *p++ = 'b';
15723       break;
15724     case v_mode:
15725       if (intel_syntax)
15726         goto skip;
15727
15728       USED_REX (REX_W);
15729       if (rex & REX_W)
15730         *p++ = 'q';
15731       else
15732         {
15733           if (sizeflag & DFLAG)
15734             *p++ = 'l';
15735           else
15736             *p++ = 'w';
15737           used_prefixes |= (prefixes & PREFIX_DATA);
15738         }
15739       break;
15740     default:
15741       oappend (INTERNAL_DISASSEMBLER_ERROR);
15742       break;
15743     }
15744   mnemonicendp = p;
15745   *p = '\0';
15746
15747  skip:
15748   if (modrm.mod == 3)
15749     {
15750       int add;
15751
15752       /* Skip mod/rm byte.  */
15753       MODRM_CHECK;
15754       codep++;
15755
15756       USED_REX (REX_B);
15757       add = (rex & REX_B) ? 8 : 0;
15758       if (bytemode == b_mode)
15759         {
15760           USED_REX (0);
15761           if (rex)
15762             oappend (names8rex[modrm.rm + add]);
15763           else
15764             oappend (names8[modrm.rm + add]);
15765         }
15766       else
15767         {
15768           USED_REX (REX_W);
15769           if (rex & REX_W)
15770             oappend (names64[modrm.rm + add]);
15771           else if ((prefixes & PREFIX_DATA))
15772             oappend (names16[modrm.rm + add]);
15773           else
15774             oappend (names32[modrm.rm + add]);
15775         }
15776     }
15777   else
15778     OP_E (bytemode, sizeflag);
15779 }
15780
15781 static void
15782 FXSAVE_Fixup (int bytemode, int sizeflag)
15783 {
15784   /* Add proper suffix to "fxsave" and "fxrstor".  */
15785   USED_REX (REX_W);
15786   if (rex & REX_W)
15787     {
15788       char *p = mnemonicendp;
15789       *p++ = '6';
15790       *p++ = '4';
15791       *p = '\0';
15792       mnemonicendp = p;
15793     }
15794   OP_M (bytemode, sizeflag);
15795 }
15796
15797 static void
15798 PCMPESTR_Fixup (int bytemode, int sizeflag)
15799 {
15800   /* Add proper suffix to "{,v}pcmpestr{i,m}".  */
15801   if (!intel_syntax)
15802     {
15803       char *p = mnemonicendp;
15804
15805       USED_REX (REX_W);
15806       if (rex & REX_W)
15807         *p++ = 'q';
15808       else if (sizeflag & SUFFIX_ALWAYS)
15809         *p++ = 'l';
15810
15811       *p = '\0';
15812       mnemonicendp = p;
15813     }
15814
15815   OP_EX (bytemode, sizeflag);
15816 }
15817
15818 /* Display the destination register operand for instructions with
15819    VEX. */
15820
15821 static void
15822 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
15823 {
15824   int reg;
15825   const char **names;
15826
15827   if (!need_vex)
15828     abort ();
15829
15830   if (!need_vex_reg)
15831     return;
15832
15833   reg = vex.register_specifier;
15834   vex.register_specifier = 0;
15835   if (address_mode != mode_64bit)
15836     reg &= 7;
15837   else if (vex.evex && !vex.v)
15838     reg += 16;
15839
15840   if (bytemode == vex_scalar_mode)
15841     {
15842       oappend (names_xmm[reg]);
15843       return;
15844     }
15845
15846   switch (vex.length)
15847     {
15848     case 128:
15849       switch (bytemode)
15850         {
15851         case vex_mode:
15852         case vex128_mode:
15853         case vex_vsib_q_w_dq_mode:
15854         case vex_vsib_q_w_d_mode:
15855           names = names_xmm;
15856           break;
15857         case dq_mode:
15858           if (rex & REX_W)
15859             names = names64;
15860           else
15861             names = names32;
15862           break;
15863         case mask_bd_mode:
15864         case mask_mode:
15865           if (reg > 0x7)
15866             {
15867               oappend ("(bad)");
15868               return;
15869             }
15870           names = names_mask;
15871           break;
15872         default:
15873           abort ();
15874           return;
15875         }
15876       break;
15877     case 256:
15878       switch (bytemode)
15879         {
15880         case vex_mode:
15881         case vex256_mode:
15882           names = names_ymm;
15883           break;
15884         case vex_vsib_q_w_dq_mode:
15885         case vex_vsib_q_w_d_mode:
15886           names = vex.w ? names_ymm : names_xmm;
15887           break;
15888         case mask_bd_mode:
15889         case mask_mode:
15890           if (reg > 0x7)
15891             {
15892               oappend ("(bad)");
15893               return;
15894             }
15895           names = names_mask;
15896           break;
15897         default:
15898           /* See PR binutils/20893 for a reproducer.  */
15899           oappend ("(bad)");
15900           return;
15901         }
15902       break;
15903     case 512:
15904       names = names_zmm;
15905       break;
15906     default:
15907       abort ();
15908       break;
15909     }
15910   oappend (names[reg]);
15911 }
15912
15913 /* Get the VEX immediate byte without moving codep.  */
15914
15915 static unsigned char
15916 get_vex_imm8 (int sizeflag, int opnum)
15917 {
15918   int bytes_before_imm = 0;
15919
15920   if (modrm.mod != 3)
15921     {
15922       /* There are SIB/displacement bytes.  */
15923       if ((sizeflag & AFLAG) || address_mode == mode_64bit)
15924         {
15925           /* 32/64 bit address mode */
15926           int base = modrm.rm;
15927
15928           /* Check SIB byte.  */
15929           if (base == 4)
15930             {
15931               FETCH_DATA (the_info, codep + 1);
15932               base = *codep & 7;
15933               /* When decoding the third source, don't increase
15934                  bytes_before_imm as this has already been incremented
15935                  by one in OP_E_memory while decoding the second
15936                  source operand.  */
15937               if (opnum == 0)
15938                 bytes_before_imm++;
15939             }
15940
15941           /* Don't increase bytes_before_imm when decoding the third source,
15942              it has already been incremented by OP_E_memory while decoding
15943              the second source operand.  */
15944           if (opnum == 0)
15945             {
15946               switch (modrm.mod)
15947                 {
15948                   case 0:
15949                     /* When modrm.rm == 5 or modrm.rm == 4 and base in
15950                        SIB == 5, there is a 4 byte displacement.  */
15951                     if (base != 5)
15952                       /* No displacement. */
15953                       break;
15954                     /* Fall through.  */
15955                   case 2:
15956                     /* 4 byte displacement.  */
15957                     bytes_before_imm += 4;
15958                     break;
15959                   case 1:
15960                     /* 1 byte displacement.  */
15961                     bytes_before_imm++;
15962                     break;
15963                 }
15964             }
15965         }
15966       else
15967         {
15968           /* 16 bit address mode */
15969           /* Don't increase bytes_before_imm when decoding the third source,
15970              it has already been incremented by OP_E_memory while decoding
15971              the second source operand.  */
15972           if (opnum == 0)
15973             {
15974               switch (modrm.mod)
15975                 {
15976                 case 0:
15977                   /* When modrm.rm == 6, there is a 2 byte displacement.  */
15978                   if (modrm.rm != 6)
15979                     /* No displacement. */
15980                     break;
15981                   /* Fall through.  */
15982                 case 2:
15983                   /* 2 byte displacement.  */
15984                   bytes_before_imm += 2;
15985                   break;
15986                 case 1:
15987                   /* 1 byte displacement: when decoding the third source,
15988                      don't increase bytes_before_imm as this has already
15989                      been incremented by one in OP_E_memory while decoding
15990                      the second source operand.  */
15991                   if (opnum == 0)
15992                     bytes_before_imm++;
15993
15994                   break;
15995                 }
15996             }
15997         }
15998     }
15999
16000   FETCH_DATA (the_info, codep + bytes_before_imm + 1);
16001   return codep [bytes_before_imm];
16002 }
16003
16004 static void
16005 OP_EX_VexReg (int bytemode, int sizeflag, int reg)
16006 {
16007   const char **names;
16008
16009   if (reg == -1 && modrm.mod != 3)
16010     {
16011       OP_E_memory (bytemode, sizeflag);
16012       return;
16013     }
16014   else
16015     {
16016       if (reg == -1)
16017         {
16018           reg = modrm.rm;
16019           USED_REX (REX_B);
16020           if (rex & REX_B)
16021             reg += 8;
16022         }
16023       if (address_mode != mode_64bit)
16024         reg &= 7;
16025     }
16026
16027   switch (vex.length)
16028     {
16029     case 128:
16030       names = names_xmm;
16031       break;
16032     case 256:
16033       names = names_ymm;
16034       break;
16035     default:
16036       abort ();
16037     }
16038   oappend (names[reg]);
16039 }
16040
16041 static void
16042 OP_EX_VexImmW (int bytemode, int sizeflag)
16043 {
16044   int reg = -1;
16045   static unsigned char vex_imm8;
16046
16047   if (vex_w_done == 0)
16048     {
16049       vex_w_done = 1;
16050
16051       /* Skip mod/rm byte.  */
16052       MODRM_CHECK;
16053       codep++;
16054
16055       vex_imm8 = get_vex_imm8 (sizeflag, 0);
16056
16057       if (vex.w)
16058           reg = vex_imm8 >> 4;
16059
16060       OP_EX_VexReg (bytemode, sizeflag, reg);
16061     }
16062   else if (vex_w_done == 1)
16063     {
16064       vex_w_done = 2;
16065
16066       if (!vex.w)
16067           reg = vex_imm8 >> 4;
16068
16069       OP_EX_VexReg (bytemode, sizeflag, reg);
16070     }
16071   else
16072     {
16073       /* Output the imm8 directly.  */
16074       scratchbuf[0] = '$';
16075       print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf);
16076       oappend_maybe_intel (scratchbuf);
16077       scratchbuf[0] = '\0';
16078       codep++;
16079     }
16080 }
16081
16082 static void
16083 OP_Vex_2src (int bytemode, int sizeflag)
16084 {
16085   if (modrm.mod == 3)
16086     {
16087       int reg = modrm.rm;
16088       USED_REX (REX_B);
16089       if (rex & REX_B)
16090         reg += 8;
16091       oappend (names_xmm[reg]);
16092     }
16093   else
16094     {
16095       if (intel_syntax
16096           && (bytemode == v_mode || bytemode == v_swap_mode))
16097         {
16098           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16099           used_prefixes |= (prefixes & PREFIX_DATA);
16100         }
16101       OP_E (bytemode, sizeflag);
16102     }
16103 }
16104
16105 static void
16106 OP_Vex_2src_1 (int bytemode, int sizeflag)
16107 {
16108   if (modrm.mod == 3)
16109     {
16110       /* Skip mod/rm byte.   */
16111       MODRM_CHECK;
16112       codep++;
16113     }
16114
16115   if (vex.w)
16116     {
16117       unsigned int reg = vex.register_specifier;
16118       vex.register_specifier = 0;
16119
16120       if (address_mode != mode_64bit)
16121         reg &= 7;
16122       oappend (names_xmm[reg]);
16123     }
16124   else
16125     OP_Vex_2src (bytemode, sizeflag);
16126 }
16127
16128 static void
16129 OP_Vex_2src_2 (int bytemode, int sizeflag)
16130 {
16131   if (vex.w)
16132     OP_Vex_2src (bytemode, sizeflag);
16133   else
16134     {
16135       unsigned int reg = vex.register_specifier;
16136       vex.register_specifier = 0;
16137
16138       if (address_mode != mode_64bit)
16139         reg &= 7;
16140       oappend (names_xmm[reg]);
16141     }
16142 }
16143
16144 static void
16145 OP_EX_VexW (int bytemode, int sizeflag)
16146 {
16147   int reg = -1;
16148
16149   if (!vex_w_done)
16150     {
16151       /* Skip mod/rm byte.  */
16152       MODRM_CHECK;
16153       codep++;
16154
16155       if (vex.w)
16156         reg = get_vex_imm8 (sizeflag, 0) >> 4;
16157     }
16158   else
16159     {
16160       if (!vex.w)
16161         reg = get_vex_imm8 (sizeflag, 1) >> 4;
16162     }
16163
16164   OP_EX_VexReg (bytemode, sizeflag, reg);
16165
16166   if (vex_w_done)
16167     codep++;
16168   vex_w_done = 1;
16169 }
16170
16171 static void
16172 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16173 {
16174   int reg;
16175   const char **names;
16176
16177   FETCH_DATA (the_info, codep + 1);
16178   reg = *codep++;
16179
16180   if (bytemode != x_mode)
16181     abort ();
16182
16183   reg >>= 4;
16184   if (address_mode != mode_64bit)
16185     reg &= 7;
16186
16187   switch (vex.length)
16188     {
16189     case 128:
16190       names = names_xmm;
16191       break;
16192     case 256:
16193       names = names_ymm;
16194       break;
16195     default:
16196       abort ();
16197     }
16198   oappend (names[reg]);
16199 }
16200
16201 static void
16202 OP_XMM_VexW (int bytemode, int sizeflag)
16203 {
16204   /* Turn off the REX.W bit since it is used for swapping operands
16205      now.  */
16206   rex &= ~REX_W;
16207   OP_XMM (bytemode, sizeflag);
16208 }
16209
16210 static void
16211 OP_EX_Vex (int bytemode, int sizeflag)
16212 {
16213   if (modrm.mod != 3)
16214     need_vex_reg = 0;
16215   OP_EX (bytemode, sizeflag);
16216 }
16217
16218 static void
16219 OP_XMM_Vex (int bytemode, int sizeflag)
16220 {
16221   if (modrm.mod != 3)
16222     need_vex_reg = 0;
16223   OP_XMM (bytemode, sizeflag);
16224 }
16225
16226 static struct op vex_cmp_op[] =
16227 {
16228   { STRING_COMMA_LEN ("eq") },
16229   { STRING_COMMA_LEN ("lt") },
16230   { STRING_COMMA_LEN ("le") },
16231   { STRING_COMMA_LEN ("unord") },
16232   { STRING_COMMA_LEN ("neq") },
16233   { STRING_COMMA_LEN ("nlt") },
16234   { STRING_COMMA_LEN ("nle") },
16235   { STRING_COMMA_LEN ("ord") },
16236   { STRING_COMMA_LEN ("eq_uq") },
16237   { STRING_COMMA_LEN ("nge") },
16238   { STRING_COMMA_LEN ("ngt") },
16239   { STRING_COMMA_LEN ("false") },
16240   { STRING_COMMA_LEN ("neq_oq") },
16241   { STRING_COMMA_LEN ("ge") },
16242   { STRING_COMMA_LEN ("gt") },
16243   { STRING_COMMA_LEN ("true") },
16244   { STRING_COMMA_LEN ("eq_os") },
16245   { STRING_COMMA_LEN ("lt_oq") },
16246   { STRING_COMMA_LEN ("le_oq") },
16247   { STRING_COMMA_LEN ("unord_s") },
16248   { STRING_COMMA_LEN ("neq_us") },
16249   { STRING_COMMA_LEN ("nlt_uq") },
16250   { STRING_COMMA_LEN ("nle_uq") },
16251   { STRING_COMMA_LEN ("ord_s") },
16252   { STRING_COMMA_LEN ("eq_us") },
16253   { STRING_COMMA_LEN ("nge_uq") },
16254   { STRING_COMMA_LEN ("ngt_uq") },
16255   { STRING_COMMA_LEN ("false_os") },
16256   { STRING_COMMA_LEN ("neq_os") },
16257   { STRING_COMMA_LEN ("ge_oq") },
16258   { STRING_COMMA_LEN ("gt_oq") },
16259   { STRING_COMMA_LEN ("true_us") },
16260 };
16261
16262 static void
16263 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16264 {
16265   unsigned int cmp_type;
16266
16267   FETCH_DATA (the_info, codep + 1);
16268   cmp_type = *codep++ & 0xff;
16269   if (cmp_type < ARRAY_SIZE (vex_cmp_op))
16270     {
16271       char suffix [3];
16272       char *p = mnemonicendp - 2;
16273       suffix[0] = p[0];
16274       suffix[1] = p[1];
16275       suffix[2] = '\0';
16276       sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
16277       mnemonicendp += vex_cmp_op[cmp_type].len;
16278     }
16279   else
16280     {
16281       /* We have a reserved extension byte.  Output it directly.  */
16282       scratchbuf[0] = '$';
16283       print_operand_value (scratchbuf + 1, 1, cmp_type);
16284       oappend_maybe_intel (scratchbuf);
16285       scratchbuf[0] = '\0';
16286     }
16287 }
16288
16289 static void
16290 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED,
16291              int sizeflag ATTRIBUTE_UNUSED)
16292 {
16293   unsigned int cmp_type;
16294
16295   if (!vex.evex)
16296     abort ();
16297
16298   FETCH_DATA (the_info, codep + 1);
16299   cmp_type = *codep++ & 0xff;
16300   /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
16301      If it's the case, print suffix, otherwise - print the immediate.  */
16302   if (cmp_type < ARRAY_SIZE (simd_cmp_op)
16303       && cmp_type != 3
16304       && cmp_type != 7)
16305     {
16306       char suffix [3];
16307       char *p = mnemonicendp - 2;
16308
16309       /* vpcmp* can have both one- and two-lettered suffix.  */
16310       if (p[0] == 'p')
16311         {
16312           p++;
16313           suffix[0] = p[0];
16314           suffix[1] = '\0';
16315         }
16316       else
16317         {
16318           suffix[0] = p[0];
16319           suffix[1] = p[1];
16320           suffix[2] = '\0';
16321         }
16322
16323       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
16324       mnemonicendp += simd_cmp_op[cmp_type].len;
16325     }
16326   else
16327     {
16328       /* We have a reserved extension byte.  Output it directly.  */
16329       scratchbuf[0] = '$';
16330       print_operand_value (scratchbuf + 1, 1, cmp_type);
16331       oappend_maybe_intel (scratchbuf);
16332       scratchbuf[0] = '\0';
16333     }
16334 }
16335
16336 static const struct op xop_cmp_op[] =
16337 {
16338   { STRING_COMMA_LEN ("lt") },
16339   { STRING_COMMA_LEN ("le") },
16340   { STRING_COMMA_LEN ("gt") },
16341   { STRING_COMMA_LEN ("ge") },
16342   { STRING_COMMA_LEN ("eq") },
16343   { STRING_COMMA_LEN ("neq") },
16344   { STRING_COMMA_LEN ("false") },
16345   { STRING_COMMA_LEN ("true") }
16346 };
16347
16348 static void
16349 VPCOM_Fixup (int bytemode ATTRIBUTE_UNUSED,
16350              int sizeflag ATTRIBUTE_UNUSED)
16351 {
16352   unsigned int cmp_type;
16353
16354   FETCH_DATA (the_info, codep + 1);
16355   cmp_type = *codep++ & 0xff;
16356   if (cmp_type < ARRAY_SIZE (xop_cmp_op))
16357     {
16358       char suffix[3];
16359       char *p = mnemonicendp - 2;
16360
16361       /* vpcom* can have both one- and two-lettered suffix.  */
16362       if (p[0] == 'm')
16363         {
16364           p++;
16365           suffix[0] = p[0];
16366           suffix[1] = '\0';
16367         }
16368       else
16369         {
16370           suffix[0] = p[0];
16371           suffix[1] = p[1];
16372           suffix[2] = '\0';
16373         }
16374
16375       sprintf (p, "%s%s", xop_cmp_op[cmp_type].name, suffix);
16376       mnemonicendp += xop_cmp_op[cmp_type].len;
16377     }
16378   else
16379     {
16380       /* We have a reserved extension byte.  Output it directly.  */
16381       scratchbuf[0] = '$';
16382       print_operand_value (scratchbuf + 1, 1, cmp_type);
16383       oappend_maybe_intel (scratchbuf);
16384       scratchbuf[0] = '\0';
16385     }
16386 }
16387
16388 static const struct op pclmul_op[] =
16389 {
16390   { STRING_COMMA_LEN ("lql") },
16391   { STRING_COMMA_LEN ("hql") },
16392   { STRING_COMMA_LEN ("lqh") },
16393   { STRING_COMMA_LEN ("hqh") }
16394 };
16395
16396 static void
16397 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
16398               int sizeflag ATTRIBUTE_UNUSED)
16399 {
16400   unsigned int pclmul_type;
16401
16402   FETCH_DATA (the_info, codep + 1);
16403   pclmul_type = *codep++ & 0xff;
16404   switch (pclmul_type)
16405     {
16406     case 0x10:
16407       pclmul_type = 2;
16408       break;
16409     case 0x11:
16410       pclmul_type = 3;
16411       break;
16412     default:
16413       break;
16414     }
16415   if (pclmul_type < ARRAY_SIZE (pclmul_op))
16416     {
16417       char suffix [4];
16418       char *p = mnemonicendp - 3;
16419       suffix[0] = p[0];
16420       suffix[1] = p[1];
16421       suffix[2] = p[2];
16422       suffix[3] = '\0';
16423       sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
16424       mnemonicendp += pclmul_op[pclmul_type].len;
16425     }
16426   else
16427     {
16428       /* We have a reserved extension byte.  Output it directly.  */
16429       scratchbuf[0] = '$';
16430       print_operand_value (scratchbuf + 1, 1, pclmul_type);
16431       oappend_maybe_intel (scratchbuf);
16432       scratchbuf[0] = '\0';
16433     }
16434 }
16435
16436 static void
16437 MOVBE_Fixup (int bytemode, int sizeflag)
16438 {
16439   /* Add proper suffix to "movbe".  */
16440   char *p = mnemonicendp;
16441
16442   switch (bytemode)
16443     {
16444     case v_mode:
16445       if (intel_syntax)
16446         goto skip;
16447
16448       USED_REX (REX_W);
16449       if (sizeflag & SUFFIX_ALWAYS)
16450         {
16451           if (rex & REX_W)
16452             *p++ = 'q';
16453           else
16454             {
16455               if (sizeflag & DFLAG)
16456                 *p++ = 'l';
16457               else
16458                 *p++ = 'w';
16459               used_prefixes |= (prefixes & PREFIX_DATA);
16460             }
16461         }
16462       break;
16463     default:
16464       oappend (INTERNAL_DISASSEMBLER_ERROR);
16465       break;
16466     }
16467   mnemonicendp = p;
16468   *p = '\0';
16469
16470  skip:
16471   OP_M (bytemode, sizeflag);
16472 }
16473
16474 static void
16475 MOVSXD_Fixup (int bytemode, int sizeflag)
16476 {
16477   /* Add proper suffix to "movsxd".  */
16478   char *p = mnemonicendp;
16479
16480   switch (bytemode)
16481     {
16482     case movsxd_mode:
16483       if (intel_syntax)
16484         {
16485           *p++ = 'x';
16486           *p++ = 'd';
16487           goto skip;
16488         }
16489
16490       USED_REX (REX_W);
16491       if (rex & REX_W)
16492         {
16493           *p++ = 'l';
16494           *p++ = 'q';
16495         }
16496       else
16497         {
16498           *p++ = 'x';
16499           *p++ = 'd';
16500         }
16501       break;
16502     default:
16503       oappend (INTERNAL_DISASSEMBLER_ERROR);
16504       break;
16505     }
16506
16507  skip:
16508   mnemonicendp = p;
16509   *p = '\0';
16510   OP_E (bytemode, sizeflag);
16511 }
16512
16513 static void
16514 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16515 {
16516   int reg;
16517   const char **names;
16518
16519   /* Skip mod/rm byte.  */
16520   MODRM_CHECK;
16521   codep++;
16522
16523   if (rex & REX_W)
16524     names = names64;
16525   else
16526     names = names32;
16527
16528   reg = modrm.rm;
16529   USED_REX (REX_B);
16530   if (rex & REX_B)
16531     reg += 8;
16532
16533   oappend (names[reg]);
16534 }
16535
16536 static void
16537 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16538 {
16539   const char **names;
16540   unsigned int reg = vex.register_specifier;
16541   vex.register_specifier = 0;
16542
16543   if (rex & REX_W)
16544     names = names64;
16545   else
16546     names = names32;
16547
16548   if (address_mode != mode_64bit)
16549     reg &= 7;
16550   oappend (names[reg]);
16551 }
16552
16553 static void
16554 OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16555 {
16556   if (!vex.evex
16557       || (bytemode != mask_mode && bytemode != mask_bd_mode))
16558     abort ();
16559
16560   USED_REX (REX_R);
16561   if ((rex & REX_R) != 0 || !vex.r)
16562     {
16563       BadOp ();
16564       return;
16565     }
16566
16567   oappend (names_mask [modrm.reg]);
16568 }
16569
16570 static void
16571 OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16572 {
16573   if (modrm.mod == 3 && vex.b)
16574     switch (bytemode)
16575       {
16576       case evex_rounding_64_mode:
16577         if (address_mode != mode_64bit)
16578           {
16579             oappend ("(bad)");
16580             break;
16581           }
16582         /* Fall through.  */
16583       case evex_rounding_mode:
16584         oappend (names_rounding[vex.ll]);
16585         break;
16586       case evex_sae_mode:
16587         oappend ("{sae}");
16588         break;
16589       default:
16590         abort ();
16591         break;
16592       }
16593 }