opcodes/i386-dis.c

   1 /* Print i386 instructions for GDB, the GNU debugger.
   2    Copyright (C) 1988-2020 Free Software Foundation, Inc.
   3
   4    This file is part of the GNU opcodes library.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    It is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program; if not, write to the Free Software
  18    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  19    MA 02110-1301, USA.  */
  20
  21
  22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
  23    July 1988
  24     modified by John Hassey (hassey@dg-rtp.dg.com)
  25     x86-64 support added by Jan Hubicka (jh@suse.cz)
  26     VIA PadLock support by Michal Ludvig (mludvig@suse.cz).  */
  27
  28 /* The main tables describing the instructions is essentially a copy
  29    of the "Opcode Map" chapter (Appendix A) of the Intel 80386
  30    Programmers Manual.  Usually, there is a capital letter, followed
  31    by a small letter.  The capital letter tell the addressing mode,
  32    and the small letter tells about the operand size.  Refer to
  33    the Intel manual for details.  */
  34
  35 #include "sysdep.h"
  36 #include "disassemble.h"
  37 #include "opintl.h"
  38 #include "opcode/i386.h"
  39 #include "libiberty.h"
  40 #include "safe-ctype.h"
  41
  42 #include <setjmp.h>
  43
  44 static int print_insn (bfd_vma, disassemble_info *);
  45 static void dofloat (int);
  46 static void OP_ST (int, int);
  47 static void OP_STi (int, int);
  48 static int putop (const char *, int);
  49 static void oappend (const char *);
  50 static void append_seg (void);
  51 static void OP_indirE (int, int);
  52 static void print_operand_value (char *, int, bfd_vma);
  53 static void OP_E_register (int, int);
  54 static void OP_E_memory (int, int);
  55 static void print_displacement (char *, bfd_vma);
  56 static void OP_E (int, int);
  57 static void OP_G (int, int);
  58 static bfd_vma get64 (void);
  59 static bfd_signed_vma get32 (void);
  60 static bfd_signed_vma get32s (void);
  61 static int get16 (void);
  62 static void set_op (bfd_vma, int);
  63 static void OP_Skip_MODRM (int, int);
  64 static void OP_REG (int, int);
  65 static void OP_IMREG (int, int);
  66 static void OP_I (int, int);
  67 static void OP_I64 (int, int);
  68 static void OP_sI (int, int);
  69 static void OP_J (int, int);
  70 static void OP_SEG (int, int);
  71 static void OP_DIR (int, int);
  72 static void OP_OFF (int, int);
  73 static void OP_OFF64 (int, int);
  74 static void ptr_reg (int, int);
  75 static void OP_ESreg (int, int);
  76 static void OP_DSreg (int, int);
  77 static void OP_C (int, int);
  78 static void OP_D (int, int);
  79 static void OP_T (int, int);
  80 static void OP_R (int, int);
  81 static void OP_MMX (int, int);
  82 static void OP_XMM (int, int);
  83 static void OP_EM (int, int);
  84 static void OP_EX (int, int);
  85 static void OP_EMC (int,int);
  86 static void OP_MXC (int,int);
  87 static void OP_MS (int, int);
  88 static void OP_XS (int, int);
  89 static void OP_M (int, int);
  90 static void OP_VEX (int, int);
  91 static void OP_EX_Vex (int, int);
  92 static void OP_EX_VexW (int, int);
  93 static void OP_EX_VexImmW (int, int);
  94 static void OP_XMM_Vex (int, int);
  95 static void OP_XMM_VexW (int, int);
  96 static void OP_Rounding (int, int);
  97 static void OP_REG_VexI4 (int, int);
  98 static void PCLMUL_Fixup (int, int);
  99 static void VCMP_Fixup (int, int);
 100 static void VPCMP_Fixup (int, int);
 101 static void VPCOM_Fixup (int, int);
 102 static void OP_0f07 (int, int);
 103 static void OP_Monitor (int, int);
 104 static void OP_Mwait (int, int);
 105 static void NOP_Fixup1 (int, int);
 106 static void NOP_Fixup2 (int, int);
 107 static void OP_3DNowSuffix (int, int);
 108 static void CMP_Fixup (int, int);
 109 static void BadOp (void);
 110 static void REP_Fixup (int, int);
 111 static void SEP_Fixup (int, int);
 112 static void BND_Fixup (int, int);
 113 static void NOTRACK_Fixup (int, int);
 114 static void HLE_Fixup1 (int, int);
 115 static void HLE_Fixup2 (int, int);
 116 static void HLE_Fixup3 (int, int);
 117 static void CMPXCHG8B_Fixup (int, int);
 118 static void XMM_Fixup (int, int);
 119 static void CRC32_Fixup (int, int);
 120 static void FXSAVE_Fixup (int, int);
 121 static void PCMPESTR_Fixup (int, int);
 122 static void OP_LWPCB_E (int, int);
 123 static void OP_LWP_E (int, int);
 124 static void OP_Vex_2src_1 (int, int);
 125 static void OP_Vex_2src_2 (int, int);
 126
 127 static void MOVBE_Fixup (int, int);
 128 static void MOVSXD_Fixup (int, int);
 129
 130 static void OP_Mask (int, int);
 131
 132 struct dis_private {
 133   /* Points to first byte not fetched.  */
 134   bfd_byte *max_fetched;
 135   bfd_byte the_buffer[MAX_MNEM_SIZE];
 136   bfd_vma insn_start;
 137   int orig_sizeflag;
 138   OPCODES_SIGJMP_BUF bailout;
 139 };
 140
 141 enum address_mode
 142 {
 143   mode_16bit,
 144   mode_32bit,
 145   mode_64bit
 146 };
 147
 148 enum address_mode address_mode;
 149
 150 /* Flags for the prefixes for the current instruction.  See below.  */
 151 static int prefixes;
 152
 153 /* REX prefix the current instruction.  See below.  */
 154 static int rex;
 155 /* Bits of REX we've already used.  */
 156 static int rex_used;
 157 /* Mark parts used in the REX prefix.  When we are testing for
 158    empty prefix (for 8bit register REX extension), just mask it
 159    out.  Otherwise test for REX bit is excuse for existence of REX
 160    only in case value is nonzero.  */
 161 #define USED_REX(value)                                 \
 162   {                                                     \
 163     if (value)                                          \
 164       {                                                 \
 165         if ((rex & value))                              \
 166           rex_used |= (value) | REX_OPCODE;             \
 167       }                                                 \
 168     else                                                \
 169       rex_used |= REX_OPCODE;                           \
 170   }
 171
 172 /* Flags for prefixes which we somehow handled when printing the
 173    current instruction.  */
 174 static int used_prefixes;
 175
 176 /* Flags stored in PREFIXES.  */
 177 #define PREFIX_REPZ 1
 178 #define PREFIX_REPNZ 2
 179 #define PREFIX_LOCK 4
 180 #define PREFIX_CS 8
 181 #define PREFIX_SS 0x10
 182 #define PREFIX_DS 0x20
 183 #define PREFIX_ES 0x40
 184 #define PREFIX_FS 0x80
 185 #define PREFIX_GS 0x100
 186 #define PREFIX_DATA 0x200
 187 #define PREFIX_ADDR 0x400
 188 #define PREFIX_FWAIT 0x800
 189
 190 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
 191    to ADDR (exclusive) are valid.  Returns 1 for success, longjmps
 192    on error.  */
 193 #define FETCH_DATA(info, addr) \
 194   ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
 195    ? 1 : fetch_data ((info), (addr)))
 196
 197 static int
 198 fetch_data (struct disassemble_info *info, bfd_byte *addr)
 199 {
 200   int status;
 201   struct dis_private *priv = (struct dis_private *) info->private_data;
 202   bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
 203
 204   if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
 205     status = (*info->read_memory_func) (start,
 206                                         priv->max_fetched,
 207                                         addr - priv->max_fetched,
 208                                         info);
 209   else
 210     status = -1;
 211   if (status != 0)
 212     {
 213       /* If we did manage to read at least one byte, then
 214          print_insn_i386 will do something sensible.  Otherwise, print
 215          an error.  We do that here because this is where we know
 216          STATUS.  */
 217       if (priv->max_fetched == priv->the_buffer)
 218         (*info->memory_error_func) (status, start, info);
 219       OPCODES_SIGLONGJMP (priv->bailout, 1);
 220     }
 221   else
 222     priv->max_fetched = addr;
 223   return 1;
 224 }
 225
 226 /* Possible values for prefix requirement.  */
 227 #define PREFIX_IGNORED_SHIFT    16
 228 #define PREFIX_IGNORED_REPZ     (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
 229 #define PREFIX_IGNORED_REPNZ    (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
 230 #define PREFIX_IGNORED_DATA     (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
 231 #define PREFIX_IGNORED_ADDR     (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
 232 #define PREFIX_IGNORED_LOCK     (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
 233
 234 /* Opcode prefixes.  */
 235 #define PREFIX_OPCODE           (PREFIX_REPZ \
 236                                  | PREFIX_REPNZ \
 237                                  | PREFIX_DATA)
 238
 239 /* Prefixes ignored.  */
 240 #define PREFIX_IGNORED          (PREFIX_IGNORED_REPZ \
 241                                  | PREFIX_IGNORED_REPNZ \
 242                                  | PREFIX_IGNORED_DATA)
 243
 244 #define XX { NULL, 0 }
 245 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
 246
 247 #define Eb { OP_E, b_mode }
 248 #define Ebnd { OP_E, bnd_mode }
 249 #define EbS { OP_E, b_swap_mode }
 250 #define EbndS { OP_E, bnd_swap_mode }
 251 #define Ev { OP_E, v_mode }
 252 #define Eva { OP_E, va_mode }
 253 #define Ev_bnd { OP_E, v_bnd_mode }
 254 #define EvS { OP_E, v_swap_mode }
 255 #define Ed { OP_E, d_mode }
 256 #define Edq { OP_E, dq_mode }
 257 #define Edqw { OP_E, dqw_mode }
 258 #define Edqb { OP_E, dqb_mode }
 259 #define Edb { OP_E, db_mode }
 260 #define Edw { OP_E, dw_mode }
 261 #define Edqd { OP_E, dqd_mode }
 262 #define Eq { OP_E, q_mode }
 263 #define indirEv { OP_indirE, indir_v_mode }
 264 #define indirEp { OP_indirE, f_mode }
 265 #define stackEv { OP_E, stack_v_mode }
 266 #define Em { OP_E, m_mode }
 267 #define Ew { OP_E, w_mode }
 268 #define M { OP_M, 0 }           /* lea, lgdt, etc. */
 269 #define Ma { OP_M, a_mode }
 270 #define Mb { OP_M, b_mode }
 271 #define Md { OP_M, d_mode }
 272 #define Mo { OP_M, o_mode }
 273 #define Mp { OP_M, f_mode }             /* 32 or 48 bit memory operand for LDS, LES etc */
 274 #define Mq { OP_M, q_mode }
 275 #define Mv_bnd { OP_M, v_bndmk_mode }
 276 #define Mx { OP_M, x_mode }
 277 #define Mxmm { OP_M, xmm_mode }
 278 #define Gb { OP_G, b_mode }
 279 #define Gbnd { OP_G, bnd_mode }
 280 #define Gv { OP_G, v_mode }
 281 #define Gd { OP_G, d_mode }
 282 #define Gdq { OP_G, dq_mode }
 283 #define Gm { OP_G, m_mode }
 284 #define Gva { OP_G, va_mode }
 285 #define Gw { OP_G, w_mode }
 286 #define Rd { OP_R, d_mode }
 287 #define Rdq { OP_R, dq_mode }
 288 #define Rm { OP_R, m_mode }
 289 #define Ib { OP_I, b_mode }
 290 #define sIb { OP_sI, b_mode }   /* sign extened byte */
 291 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
 292 #define Iv { OP_I, v_mode }
 293 #define sIv { OP_sI, v_mode }
 294 #define Iv64 { OP_I64, v_mode }
 295 #define Id { OP_I, d_mode }
 296 #define Iw { OP_I, w_mode }
 297 #define I1 { OP_I, const_1_mode }
 298 #define Jb { OP_J, b_mode }
 299 #define Jv { OP_J, v_mode }
 300 #define Jdqw { OP_J, dqw_mode }
 301 #define Cm { OP_C, m_mode }
 302 #define Dm { OP_D, m_mode }
 303 #define Td { OP_T, d_mode }
 304 #define Skip_MODRM { OP_Skip_MODRM, 0 }
 305
 306 #define RMeAX { OP_REG, eAX_reg }
 307 #define RMeBX { OP_REG, eBX_reg }
 308 #define RMeCX { OP_REG, eCX_reg }
 309 #define RMeDX { OP_REG, eDX_reg }
 310 #define RMeSP { OP_REG, eSP_reg }
 311 #define RMeBP { OP_REG, eBP_reg }
 312 #define RMeSI { OP_REG, eSI_reg }
 313 #define RMeDI { OP_REG, eDI_reg }
 314 #define RMrAX { OP_REG, rAX_reg }
 315 #define RMrBX { OP_REG, rBX_reg }
 316 #define RMrCX { OP_REG, rCX_reg }
 317 #define RMrDX { OP_REG, rDX_reg }
 318 #define RMrSP { OP_REG, rSP_reg }
 319 #define RMrBP { OP_REG, rBP_reg }
 320 #define RMrSI { OP_REG, rSI_reg }
 321 #define RMrDI { OP_REG, rDI_reg }
 322 #define RMAL { OP_REG, al_reg }
 323 #define RMCL { OP_REG, cl_reg }
 324 #define RMDL { OP_REG, dl_reg }
 325 #define RMBL { OP_REG, bl_reg }
 326 #define RMAH { OP_REG, ah_reg }
 327 #define RMCH { OP_REG, ch_reg }
 328 #define RMDH { OP_REG, dh_reg }
 329 #define RMBH { OP_REG, bh_reg }
 330 #define RMAX { OP_REG, ax_reg }
 331 #define RMDX { OP_REG, dx_reg }
 332
 333 #define eAX { OP_IMREG, eAX_reg }
 334 #define eBX { OP_IMREG, eBX_reg }
 335 #define eCX { OP_IMREG, eCX_reg }
 336 #define eDX { OP_IMREG, eDX_reg }
 337 #define eSP { OP_IMREG, eSP_reg }
 338 #define eBP { OP_IMREG, eBP_reg }
 339 #define eSI { OP_IMREG, eSI_reg }
 340 #define eDI { OP_IMREG, eDI_reg }
 341 #define AL { OP_IMREG, al_reg }
 342 #define CL { OP_IMREG, cl_reg }
 343 #define DL { OP_IMREG, dl_reg }
 344 #define BL { OP_IMREG, bl_reg }
 345 #define AH { OP_IMREG, ah_reg }
 346 #define CH { OP_IMREG, ch_reg }
 347 #define DH { OP_IMREG, dh_reg }
 348 #define BH { OP_IMREG, bh_reg }
 349 #define AX { OP_IMREG, ax_reg }
 350 #define DX { OP_IMREG, dx_reg }
 351 #define zAX { OP_IMREG, z_mode_ax_reg }
 352 #define indirDX { OP_IMREG, indir_dx_reg }
 353
 354 #define Sw { OP_SEG, w_mode }
 355 #define Sv { OP_SEG, v_mode }
 356 #define Ap { OP_DIR, 0 }
 357 #define Ob { OP_OFF64, b_mode }
 358 #define Ov { OP_OFF64, v_mode }
 359 #define Xb { OP_DSreg, eSI_reg }
 360 #define Xv { OP_DSreg, eSI_reg }
 361 #define Xz { OP_DSreg, eSI_reg }
 362 #define Yb { OP_ESreg, eDI_reg }
 363 #define Yv { OP_ESreg, eDI_reg }
 364 #define DSBX { OP_DSreg, eBX_reg }
 365
 366 #define es { OP_REG, es_reg }
 367 #define ss { OP_REG, ss_reg }
 368 #define cs { OP_REG, cs_reg }
 369 #define ds { OP_REG, ds_reg }
 370 #define fs { OP_REG, fs_reg }
 371 #define gs { OP_REG, gs_reg }
 372
 373 #define MX { OP_MMX, 0 }
 374 #define XM { OP_XMM, 0 }
 375 #define XMScalar { OP_XMM, scalar_mode }
 376 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
 377 #define XMM { OP_XMM, xmm_mode }
 378 #define XMxmmq { OP_XMM, xmmq_mode }
 379 #define EM { OP_EM, v_mode }
 380 #define EMS { OP_EM, v_swap_mode }
 381 #define EMd { OP_EM, d_mode }
 382 #define EMx { OP_EM, x_mode }
 383 #define EXbScalar { OP_EX, b_scalar_mode }
 384 #define EXw { OP_EX, w_mode }
 385 #define EXwScalar { OP_EX, w_scalar_mode }
 386 #define EXd { OP_EX, d_mode }
 387 #define EXdS { OP_EX, d_swap_mode }
 388 #define EXq { OP_EX, q_mode }
 389 #define EXqS { OP_EX, q_swap_mode }
 390 #define EXx { OP_EX, x_mode }
 391 #define EXxS { OP_EX, x_swap_mode }
 392 #define EXxmm { OP_EX, xmm_mode }
 393 #define EXymm { OP_EX, ymm_mode }
 394 #define EXxmmq { OP_EX, xmmq_mode }
 395 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
 396 #define EXxmm_mb { OP_EX, xmm_mb_mode }
 397 #define EXxmm_mw { OP_EX, xmm_mw_mode }
 398 #define EXxmm_md { OP_EX, xmm_md_mode }
 399 #define EXxmm_mq { OP_EX, xmm_mq_mode }
 400 #define EXxmmdw { OP_EX, xmmdw_mode }
 401 #define EXxmmqd { OP_EX, xmmqd_mode }
 402 #define EXymmq { OP_EX, ymmq_mode }
 403 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
 404 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
 405 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
 406 #define MS { OP_MS, v_mode }
 407 #define XS { OP_XS, v_mode }
 408 #define EMCq { OP_EMC, q_mode }
 409 #define MXC { OP_MXC, 0 }
 410 #define OPSUF { OP_3DNowSuffix, 0 }
 411 #define SEP { SEP_Fixup, 0 }
 412 #define CMP { CMP_Fixup, 0 }
 413 #define XMM0 { XMM_Fixup, 0 }
 414 #define FXSAVE { FXSAVE_Fixup, 0 }
 415 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
 416 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
 417
 418 #define Vex { OP_VEX, vex_mode }
 419 #define VexScalar { OP_VEX, vex_scalar_mode }
 420 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
 421 #define Vex128 { OP_VEX, vex128_mode }
 422 #define Vex256 { OP_VEX, vex256_mode }
 423 #define VexGdq { OP_VEX, dq_mode }
 424 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
 425 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
 426 #define EXVexW { OP_EX_VexW, x_mode }
 427 #define EXdVexW { OP_EX_VexW, d_mode }
 428 #define EXqVexW { OP_EX_VexW, q_mode }
 429 #define EXVexImmW { OP_EX_VexImmW, x_mode }
 430 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
 431 #define XMVexW { OP_XMM_VexW, 0 }
 432 #define XMVexI4 { OP_REG_VexI4, x_mode }
 433 #define PCLMUL { PCLMUL_Fixup, 0 }
 434 #define VCMP { VCMP_Fixup, 0 }
 435 #define VPCMP { VPCMP_Fixup, 0 }
 436 #define VPCOM { VPCOM_Fixup, 0 }
 437
 438 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
 439 #define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode }
 440 #define EXxEVexS { OP_Rounding, evex_sae_mode }
 441
 442 #define XMask { OP_Mask, mask_mode }
 443 #define MaskG { OP_G, mask_mode }
 444 #define MaskE { OP_E, mask_mode }
 445 #define MaskBDE { OP_E, mask_bd_mode }
 446 #define MaskR { OP_R, mask_mode }
 447 #define MaskVex { OP_VEX, mask_mode }
 448
 449 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
 450 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
 451 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
 452 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
 453
 454 /* Used handle "rep" prefix for string instructions.  */
 455 #define Xbr { REP_Fixup, eSI_reg }
 456 #define Xvr { REP_Fixup, eSI_reg }
 457 #define Ybr { REP_Fixup, eDI_reg }
 458 #define Yvr { REP_Fixup, eDI_reg }
 459 #define Yzr { REP_Fixup, eDI_reg }
 460 #define indirDXr { REP_Fixup, indir_dx_reg }
 461 #define ALr { REP_Fixup, al_reg }
 462 #define eAXr { REP_Fixup, eAX_reg }
 463
 464 /* Used handle HLE prefix for lockable instructions.  */
 465 #define Ebh1 { HLE_Fixup1, b_mode }
 466 #define Evh1 { HLE_Fixup1, v_mode }
 467 #define Ebh2 { HLE_Fixup2, b_mode }
 468 #define Evh2 { HLE_Fixup2, v_mode }
 469 #define Ebh3 { HLE_Fixup3, b_mode }
 470 #define Evh3 { HLE_Fixup3, v_mode }
 471
 472 #define BND { BND_Fixup, 0 }
 473 #define NOTRACK { NOTRACK_Fixup, 0 }
 474
 475 #define cond_jump_flag { NULL, cond_jump_mode }
 476 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
 477
 478 /* bits in sizeflag */
 479 #define SUFFIX_ALWAYS 4
 480 #define AFLAG 2
 481 #define DFLAG 1
 482
 483 enum
 484 {
 485   /* byte operand */
 486   b_mode = 1,
 487   /* byte operand with operand swapped */
 488   b_swap_mode,
 489   /* byte operand, sign extend like 'T' suffix */
 490   b_T_mode,
 491   /* operand size depends on prefixes */
 492   v_mode,
 493   /* operand size depends on prefixes with operand swapped */
 494   v_swap_mode,
 495   /* operand size depends on address prefix */
 496   va_mode,
 497   /* word operand */
 498   w_mode,
 499   /* double word operand  */
 500   d_mode,
 501   /* double word operand with operand swapped */
 502   d_swap_mode,
 503   /* quad word operand */
 504   q_mode,
 505   /* quad word operand with operand swapped */
 506   q_swap_mode,
 507   /* ten-byte operand */
 508   t_mode,
 509   /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand.  In EVEX with
 510      broadcast enabled.  */
 511   x_mode,
 512   /* Similar to x_mode, but with different EVEX mem shifts.  */
 513   evex_x_gscat_mode,
 514   /* Similar to x_mode, but with disabled broadcast.  */
 515   evex_x_nobcst_mode,
 516   /* Similar to x_mode, but with operands swapped and disabled broadcast
 517      in EVEX.  */
 518   x_swap_mode,
 519   /* 16-byte XMM operand */
 520   xmm_mode,
 521   /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
 522      memory operand (depending on vector length).  Broadcast isn't
 523      allowed.  */
 524   xmmq_mode,
 525   /* Same as xmmq_mode, but broadcast is allowed.  */
 526   evex_half_bcst_xmmq_mode,
 527   /* XMM register or byte memory operand */
 528   xmm_mb_mode,
 529   /* XMM register or word memory operand */
 530   xmm_mw_mode,
 531   /* XMM register or double word memory operand */
 532   xmm_md_mode,
 533   /* XMM register or quad word memory operand */
 534   xmm_mq_mode,
 535   /* 16-byte XMM, word, double word or quad word operand.  */
 536   xmmdw_mode,
 537   /* 16-byte XMM, double word, quad word operand or xmm word operand.  */
 538   xmmqd_mode,
 539   /* 32-byte YMM operand */
 540   ymm_mode,
 541   /* quad word, ymmword or zmmword memory operand.  */
 542   ymmq_mode,
 543   /* 32-byte YMM or 16-byte word operand */
 544   ymmxmm_mode,
 545   /* d_mode in 32bit, q_mode in 64bit mode.  */
 546   m_mode,
 547   /* pair of v_mode operands */
 548   a_mode,
 549   cond_jump_mode,
 550   loop_jcxz_mode,
 551   movsxd_mode,
 552   v_bnd_mode,
 553   /* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode.  */
 554   v_bndmk_mode,
 555   /* operand size depends on REX prefixes.  */
 556   dq_mode,
 557   /* registers like dq_mode, memory like w_mode, displacements like
 558      v_mode without considering Intel64 ISA.  */
 559   dqw_mode,
 560   /* bounds operand */
 561   bnd_mode,
 562   /* bounds operand with operand swapped */
 563   bnd_swap_mode,
 564   /* 4- or 6-byte pointer operand */
 565   f_mode,
 566   const_1_mode,
 567   /* v_mode for indirect branch opcodes.  */
 568   indir_v_mode,
 569   /* v_mode for stack-related opcodes.  */
 570   stack_v_mode,
 571   /* non-quad operand size depends on prefixes */
 572   z_mode,
 573   /* 16-byte operand */
 574   o_mode,
 575   /* registers like dq_mode, memory like b_mode.  */
 576   dqb_mode,
 577   /* registers like d_mode, memory like b_mode.  */
 578   db_mode,
 579   /* registers like d_mode, memory like w_mode.  */
 580   dw_mode,
 581   /* registers like dq_mode, memory like d_mode.  */
 582   dqd_mode,
 583   /* normal vex mode */
 584   vex_mode,
 585   /* 128bit vex mode */
 586   vex128_mode,
 587   /* 256bit vex mode */
 588   vex256_mode,
 589
 590   /* Operand size depends on the VEX.W bit, with VSIB dword indices.  */
 591   vex_vsib_d_w_dq_mode,
 592   /* Similar to vex_vsib_d_w_dq_mode, with smaller memory.  */
 593   vex_vsib_d_w_d_mode,
 594   /* Operand size depends on the VEX.W bit, with VSIB qword indices.  */
 595   vex_vsib_q_w_dq_mode,
 596   /* Similar to vex_vsib_q_w_dq_mode, with smaller memory.  */
 597   vex_vsib_q_w_d_mode,
 598
 599   /* scalar, ignore vector length.  */
 600   scalar_mode,
 601   /* like b_mode, ignore vector length.  */
 602   b_scalar_mode,
 603   /* like w_mode, ignore vector length.  */
 604   w_scalar_mode,
 605   /* like d_swap_mode, ignore vector length.  */
 606   d_scalar_swap_mode,
 607   /* like q_swap_mode, ignore vector length.  */
 608   q_scalar_swap_mode,
 609   /* like vex_mode, ignore vector length.  */
 610   vex_scalar_mode,
 611   /* Operand size depends on the VEX.W bit, ignore vector length.  */
 612   vex_scalar_w_dq_mode,
 613
 614   /* Static rounding.  */
 615   evex_rounding_mode,
 616   /* Static rounding, 64-bit mode only.  */
 617   evex_rounding_64_mode,
 618   /* Supress all exceptions.  */
 619   evex_sae_mode,
 620
 621   /* Mask register operand.  */
 622   mask_mode,
 623   /* Mask register operand.  */
 624   mask_bd_mode,
 625
 626   es_reg,
 627   cs_reg,
 628   ss_reg,
 629   ds_reg,
 630   fs_reg,
 631   gs_reg,
 632
 633   eAX_reg,
 634   eCX_reg,
 635   eDX_reg,
 636   eBX_reg,
 637   eSP_reg,
 638   eBP_reg,
 639   eSI_reg,
 640   eDI_reg,
 641
 642   al_reg,
 643   cl_reg,
 644   dl_reg,
 645   bl_reg,
 646   ah_reg,
 647   ch_reg,
 648   dh_reg,
 649   bh_reg,
 650
 651   ax_reg,
 652   cx_reg,
 653   dx_reg,
 654   bx_reg,
 655   sp_reg,
 656   bp_reg,
 657   si_reg,
 658   di_reg,
 659
 660   rAX_reg,
 661   rCX_reg,
 662   rDX_reg,
 663   rBX_reg,
 664   rSP_reg,
 665   rBP_reg,
 666   rSI_reg,
 667   rDI_reg,
 668
 669   z_mode_ax_reg,
 670   indir_dx_reg
 671 };
 672
 673 enum
 674 {
 675   FLOATCODE = 1,
 676   USE_REG_TABLE,
 677   USE_MOD_TABLE,
 678   USE_RM_TABLE,
 679   USE_PREFIX_TABLE,
 680   USE_X86_64_TABLE,
 681   USE_3BYTE_TABLE,
 682   USE_XOP_8F_TABLE,
 683   USE_VEX_C4_TABLE,
 684   USE_VEX_C5_TABLE,
 685   USE_VEX_LEN_TABLE,
 686   USE_VEX_W_TABLE,
 687   USE_EVEX_TABLE,
 688   USE_EVEX_LEN_TABLE
 689 };
 690
 691 #define FLOAT                   NULL, { { NULL, FLOATCODE } }, 0
 692
 693 #define DIS386(T, I)            NULL, { { NULL, (T)}, { NULL,  (I) } }, 0
 694 #define DIS386_PREFIX(T, I, P)          NULL, { { NULL, (T)}, { NULL,  (I) } }, P
 695 #define REG_TABLE(I)            DIS386 (USE_REG_TABLE, (I))
 696 #define MOD_TABLE(I)            DIS386 (USE_MOD_TABLE, (I))
 697 #define RM_TABLE(I)             DIS386 (USE_RM_TABLE, (I))
 698 #define PREFIX_TABLE(I)         DIS386 (USE_PREFIX_TABLE, (I))
 699 #define X86_64_TABLE(I)         DIS386 (USE_X86_64_TABLE, (I))
 700 #define THREE_BYTE_TABLE(I)     DIS386 (USE_3BYTE_TABLE, (I))
 701 #define THREE_BYTE_TABLE_PREFIX(I, P)   DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
 702 #define XOP_8F_TABLE(I)         DIS386 (USE_XOP_8F_TABLE, (I))
 703 #define VEX_C4_TABLE(I)         DIS386 (USE_VEX_C4_TABLE, (I))
 704 #define VEX_C5_TABLE(I)         DIS386 (USE_VEX_C5_TABLE, (I))
 705 #define VEX_LEN_TABLE(I)        DIS386 (USE_VEX_LEN_TABLE, (I))
 706 #define VEX_W_TABLE(I)          DIS386 (USE_VEX_W_TABLE, (I))
 707 #define EVEX_TABLE(I)           DIS386 (USE_EVEX_TABLE, (I))
 708 #define EVEX_LEN_TABLE(I)       DIS386 (USE_EVEX_LEN_TABLE, (I))
 709
 710 enum
 711 {
 712   REG_80 = 0,
 713   REG_81,
 714   REG_83,
 715   REG_8F,
 716   REG_C0,
 717   REG_C1,
 718   REG_C6,
 719   REG_C7,
 720   REG_D0,
 721   REG_D1,
 722   REG_D2,
 723   REG_D3,
 724   REG_F6,
 725   REG_F7,
 726   REG_FE,
 727   REG_FF,
 728   REG_0F00,
 729   REG_0F01,
 730   REG_0F0D,
 731   REG_0F18,
 732   REG_0F1C_P_0_MOD_0,
 733   REG_0F1E_P_1_MOD_3,
 734   REG_0F71,
 735   REG_0F72,
 736   REG_0F73,
 737   REG_0FA6,
 738   REG_0FA7,
 739   REG_0FAE,
 740   REG_0FBA,
 741   REG_0FC7,
 742   REG_VEX_0F71,
 743   REG_VEX_0F72,
 744   REG_VEX_0F73,
 745   REG_VEX_0FAE,
 746   REG_VEX_0F38F3,
 747   REG_XOP_LWPCB,
 748   REG_XOP_LWP,
 749   REG_XOP_TBM_01,
 750   REG_XOP_TBM_02,
 751
 752   REG_EVEX_0F71,
 753   REG_EVEX_0F72,
 754   REG_EVEX_0F73,
 755   REG_EVEX_0F38C6,
 756   REG_EVEX_0F38C7
 757 };
 758
 759 enum
 760 {
 761   MOD_8D = 0,
 762   MOD_C6_REG_7,
 763   MOD_C7_REG_7,
 764   MOD_FF_REG_3,
 765   MOD_FF_REG_5,
 766   MOD_0F01_REG_0,
 767   MOD_0F01_REG_1,
 768   MOD_0F01_REG_2,
 769   MOD_0F01_REG_3,
 770   MOD_0F01_REG_5,
 771   MOD_0F01_REG_7,
 772   MOD_0F12_PREFIX_0,
 773   MOD_0F12_PREFIX_2,
 774   MOD_0F13,
 775   MOD_0F16_PREFIX_0,
 776   MOD_0F16_PREFIX_2,
 777   MOD_0F17,
 778   MOD_0F18_REG_0,
 779   MOD_0F18_REG_1,
 780   MOD_0F18_REG_2,
 781   MOD_0F18_REG_3,
 782   MOD_0F18_REG_4,
 783   MOD_0F18_REG_5,
 784   MOD_0F18_REG_6,
 785   MOD_0F18_REG_7,
 786   MOD_0F1A_PREFIX_0,
 787   MOD_0F1B_PREFIX_0,
 788   MOD_0F1B_PREFIX_1,
 789   MOD_0F1C_PREFIX_0,
 790   MOD_0F1E_PREFIX_1,
 791   MOD_0F24,
 792   MOD_0F26,
 793   MOD_0F2B_PREFIX_0,
 794   MOD_0F2B_PREFIX_1,
 795   MOD_0F2B_PREFIX_2,
 796   MOD_0F2B_PREFIX_3,
 797   MOD_0F50,
 798   MOD_0F71_REG_2,
 799   MOD_0F71_REG_4,
 800   MOD_0F71_REG_6,
 801   MOD_0F72_REG_2,
 802   MOD_0F72_REG_4,
 803   MOD_0F72_REG_6,
 804   MOD_0F73_REG_2,
 805   MOD_0F73_REG_3,
 806   MOD_0F73_REG_6,
 807   MOD_0F73_REG_7,
 808   MOD_0FAE_REG_0,
 809   MOD_0FAE_REG_1,
 810   MOD_0FAE_REG_2,
 811   MOD_0FAE_REG_3,
 812   MOD_0FAE_REG_4,
 813   MOD_0FAE_REG_5,
 814   MOD_0FAE_REG_6,
 815   MOD_0FAE_REG_7,
 816   MOD_0FB2,
 817   MOD_0FB4,
 818   MOD_0FB5,
 819   MOD_0FC3,
 820   MOD_0FC7_REG_3,
 821   MOD_0FC7_REG_4,
 822   MOD_0FC7_REG_5,
 823   MOD_0FC7_REG_6,
 824   MOD_0FC7_REG_7,
 825   MOD_0FD7,
 826   MOD_0FE7_PREFIX_2,
 827   MOD_0FF0_PREFIX_3,
 828   MOD_0F382A_PREFIX_2,
 829   MOD_0F38F5_PREFIX_2,
 830   MOD_0F38F6_PREFIX_0,
 831   MOD_0F38F8_PREFIX_1,
 832   MOD_0F38F8_PREFIX_2,
 833   MOD_0F38F8_PREFIX_3,
 834   MOD_0F38F9_PREFIX_0,
 835   MOD_62_32BIT,
 836   MOD_C4_32BIT,
 837   MOD_C5_32BIT,
 838   MOD_VEX_0F12_PREFIX_0,
 839   MOD_VEX_0F12_PREFIX_2,
 840   MOD_VEX_0F13,
 841   MOD_VEX_0F16_PREFIX_0,
 842   MOD_VEX_0F16_PREFIX_2,
 843   MOD_VEX_0F17,
 844   MOD_VEX_0F2B,
 845   MOD_VEX_W_0_0F41_P_0_LEN_1,
 846   MOD_VEX_W_1_0F41_P_0_LEN_1,
 847   MOD_VEX_W_0_0F41_P_2_LEN_1,
 848   MOD_VEX_W_1_0F41_P_2_LEN_1,
 849   MOD_VEX_W_0_0F42_P_0_LEN_1,
 850   MOD_VEX_W_1_0F42_P_0_LEN_1,
 851   MOD_VEX_W_0_0F42_P_2_LEN_1,
 852   MOD_VEX_W_1_0F42_P_2_LEN_1,
 853   MOD_VEX_W_0_0F44_P_0_LEN_1,
 854   MOD_VEX_W_1_0F44_P_0_LEN_1,
 855   MOD_VEX_W_0_0F44_P_2_LEN_1,
 856   MOD_VEX_W_1_0F44_P_2_LEN_1,
 857   MOD_VEX_W_0_0F45_P_0_LEN_1,
 858   MOD_VEX_W_1_0F45_P_0_LEN_1,
 859   MOD_VEX_W_0_0F45_P_2_LEN_1,
 860   MOD_VEX_W_1_0F45_P_2_LEN_1,
 861   MOD_VEX_W_0_0F46_P_0_LEN_1,
 862   MOD_VEX_W_1_0F46_P_0_LEN_1,
 863   MOD_VEX_W_0_0F46_P_2_LEN_1,
 864   MOD_VEX_W_1_0F46_P_2_LEN_1,
 865   MOD_VEX_W_0_0F47_P_0_LEN_1,
 866   MOD_VEX_W_1_0F47_P_0_LEN_1,
 867   MOD_VEX_W_0_0F47_P_2_LEN_1,
 868   MOD_VEX_W_1_0F47_P_2_LEN_1,
 869   MOD_VEX_W_0_0F4A_P_0_LEN_1,
 870   MOD_VEX_W_1_0F4A_P_0_LEN_1,
 871   MOD_VEX_W_0_0F4A_P_2_LEN_1,
 872   MOD_VEX_W_1_0F4A_P_2_LEN_1,
 873   MOD_VEX_W_0_0F4B_P_0_LEN_1,
 874   MOD_VEX_W_1_0F4B_P_0_LEN_1,
 875   MOD_VEX_W_0_0F4B_P_2_LEN_1,
 876   MOD_VEX_0F50,
 877   MOD_VEX_0F71_REG_2,
 878   MOD_VEX_0F71_REG_4,
 879   MOD_VEX_0F71_REG_6,
 880   MOD_VEX_0F72_REG_2,
 881   MOD_VEX_0F72_REG_4,
 882   MOD_VEX_0F72_REG_6,
 883   MOD_VEX_0F73_REG_2,
 884   MOD_VEX_0F73_REG_3,
 885   MOD_VEX_0F73_REG_6,
 886   MOD_VEX_0F73_REG_7,
 887   MOD_VEX_W_0_0F91_P_0_LEN_0,
 888   MOD_VEX_W_1_0F91_P_0_LEN_0,
 889   MOD_VEX_W_0_0F91_P_2_LEN_0,
 890   MOD_VEX_W_1_0F91_P_2_LEN_0,
 891   MOD_VEX_W_0_0F92_P_0_LEN_0,
 892   MOD_VEX_W_0_0F92_P_2_LEN_0,
 893   MOD_VEX_0F92_P_3_LEN_0,
 894   MOD_VEX_W_0_0F93_P_0_LEN_0,
 895   MOD_VEX_W_0_0F93_P_2_LEN_0,
 896   MOD_VEX_0F93_P_3_LEN_0,
 897   MOD_VEX_W_0_0F98_P_0_LEN_0,
 898   MOD_VEX_W_1_0F98_P_0_LEN_0,
 899   MOD_VEX_W_0_0F98_P_2_LEN_0,
 900   MOD_VEX_W_1_0F98_P_2_LEN_0,
 901   MOD_VEX_W_0_0F99_P_0_LEN_0,
 902   MOD_VEX_W_1_0F99_P_0_LEN_0,
 903   MOD_VEX_W_0_0F99_P_2_LEN_0,
 904   MOD_VEX_W_1_0F99_P_2_LEN_0,
 905   MOD_VEX_0FAE_REG_2,
 906   MOD_VEX_0FAE_REG_3,
 907   MOD_VEX_0FD7_PREFIX_2,
 908   MOD_VEX_0FE7_PREFIX_2,
 909   MOD_VEX_0FF0_PREFIX_3,
 910   MOD_VEX_0F381A_PREFIX_2,
 911   MOD_VEX_0F382A_PREFIX_2,
 912   MOD_VEX_0F382C_PREFIX_2,
 913   MOD_VEX_0F382D_PREFIX_2,
 914   MOD_VEX_0F382E_PREFIX_2,
 915   MOD_VEX_0F382F_PREFIX_2,
 916   MOD_VEX_0F385A_PREFIX_2,
 917   MOD_VEX_0F388C_PREFIX_2,
 918   MOD_VEX_0F388E_PREFIX_2,
 919   MOD_VEX_W_0_0F3A30_P_2_LEN_0,
 920   MOD_VEX_W_1_0F3A30_P_2_LEN_0,
 921   MOD_VEX_W_0_0F3A31_P_2_LEN_0,
 922   MOD_VEX_W_1_0F3A31_P_2_LEN_0,
 923   MOD_VEX_W_0_0F3A32_P_2_LEN_0,
 924   MOD_VEX_W_1_0F3A32_P_2_LEN_0,
 925   MOD_VEX_W_0_0F3A33_P_2_LEN_0,
 926   MOD_VEX_W_1_0F3A33_P_2_LEN_0,
 927
 928   MOD_EVEX_0F12_PREFIX_0,
 929   MOD_EVEX_0F12_PREFIX_2,
 930   MOD_EVEX_0F13,
 931   MOD_EVEX_0F16_PREFIX_0,
 932   MOD_EVEX_0F16_PREFIX_2,
 933   MOD_EVEX_0F17,
 934   MOD_EVEX_0F2B,
 935   MOD_EVEX_0F38C6_REG_1,
 936   MOD_EVEX_0F38C6_REG_2,
 937   MOD_EVEX_0F38C6_REG_5,
 938   MOD_EVEX_0F38C6_REG_6,
 939   MOD_EVEX_0F38C7_REG_1,
 940   MOD_EVEX_0F38C7_REG_2,
 941   MOD_EVEX_0F38C7_REG_5,
 942   MOD_EVEX_0F38C7_REG_6
 943 };
 944
 945 enum
 946 {
 947   RM_C6_REG_7 = 0,
 948   RM_C7_REG_7,
 949   RM_0F01_REG_0,
 950   RM_0F01_REG_1,
 951   RM_0F01_REG_2,
 952   RM_0F01_REG_3,
 953   RM_0F01_REG_5_MOD_3,
 954   RM_0F01_REG_7_MOD_3,
 955   RM_0F1E_P_1_MOD_3_REG_7,
 956   RM_0FAE_REG_6_MOD_3_P_0,
 957   RM_0FAE_REG_7_MOD_3,
 958 };
 959
 960 enum
 961 {
 962   PREFIX_90 = 0,
 963   PREFIX_0F01_REG_3_RM_1,
 964   PREFIX_0F01_REG_5_MOD_0,
 965   PREFIX_0F01_REG_5_MOD_3_RM_0,
 966   PREFIX_0F01_REG_5_MOD_3_RM_1,
 967   PREFIX_0F01_REG_5_MOD_3_RM_2,
 968   PREFIX_0F01_REG_7_MOD_3_RM_2,
 969   PREFIX_0F01_REG_7_MOD_3_RM_3,
 970   PREFIX_0F09,
 971   PREFIX_0F10,
 972   PREFIX_0F11,
 973   PREFIX_0F12,
 974   PREFIX_0F16,
 975   PREFIX_0F1A,
 976   PREFIX_0F1B,
 977   PREFIX_0F1C,
 978   PREFIX_0F1E,
 979   PREFIX_0F2A,
 980   PREFIX_0F2B,
 981   PREFIX_0F2C,
 982   PREFIX_0F2D,
 983   PREFIX_0F2E,
 984   PREFIX_0F2F,
 985   PREFIX_0F51,
 986   PREFIX_0F52,
 987   PREFIX_0F53,
 988   PREFIX_0F58,
 989   PREFIX_0F59,
 990   PREFIX_0F5A,
 991   PREFIX_0F5B,
 992   PREFIX_0F5C,
 993   PREFIX_0F5D,
 994   PREFIX_0F5E,
 995   PREFIX_0F5F,
 996   PREFIX_0F60,
 997   PREFIX_0F61,
 998   PREFIX_0F62,
 999   PREFIX_0F6C,
1000   PREFIX_0F6D,
1001   PREFIX_0F6F,
1002   PREFIX_0F70,
1003   PREFIX_0F73_REG_3,
1004   PREFIX_0F73_REG_7,
1005   PREFIX_0F78,
1006   PREFIX_0F79,
1007   PREFIX_0F7C,
1008   PREFIX_0F7D,
1009   PREFIX_0F7E,
1010   PREFIX_0F7F,
1011   PREFIX_0FAE_REG_0_MOD_3,
1012   PREFIX_0FAE_REG_1_MOD_3,
1013   PREFIX_0FAE_REG_2_MOD_3,
1014   PREFIX_0FAE_REG_3_MOD_3,
1015   PREFIX_0FAE_REG_4_MOD_0,
1016   PREFIX_0FAE_REG_4_MOD_3,
1017   PREFIX_0FAE_REG_5_MOD_0,
1018   PREFIX_0FAE_REG_5_MOD_3,
1019   PREFIX_0FAE_REG_6_MOD_0,
1020   PREFIX_0FAE_REG_6_MOD_3,
1021   PREFIX_0FAE_REG_7_MOD_0,
1022   PREFIX_0FB8,
1023   PREFIX_0FBC,
1024   PREFIX_0FBD,
1025   PREFIX_0FC2,
1026   PREFIX_0FC3_MOD_0,
1027   PREFIX_0FC7_REG_6_MOD_0,
1028   PREFIX_0FC7_REG_6_MOD_3,
1029   PREFIX_0FC7_REG_7_MOD_3,
1030   PREFIX_0FD0,
1031   PREFIX_0FD6,
1032   PREFIX_0FE6,
1033   PREFIX_0FE7,
1034   PREFIX_0FF0,
1035   PREFIX_0FF7,
1036   PREFIX_0F3810,
1037   PREFIX_0F3814,
1038   PREFIX_0F3815,
1039   PREFIX_0F3817,
1040   PREFIX_0F3820,
1041   PREFIX_0F3821,
1042   PREFIX_0F3822,
1043   PREFIX_0F3823,
1044   PREFIX_0F3824,
1045   PREFIX_0F3825,
1046   PREFIX_0F3828,
1047   PREFIX_0F3829,
1048   PREFIX_0F382A,
1049   PREFIX_0F382B,
1050   PREFIX_0F3830,
1051   PREFIX_0F3831,
1052   PREFIX_0F3832,
1053   PREFIX_0F3833,
1054   PREFIX_0F3834,
1055   PREFIX_0F3835,
1056   PREFIX_0F3837,
1057   PREFIX_0F3838,
1058   PREFIX_0F3839,
1059   PREFIX_0F383A,
1060   PREFIX_0F383B,
1061   PREFIX_0F383C,
1062   PREFIX_0F383D,
1063   PREFIX_0F383E,
1064   PREFIX_0F383F,
1065   PREFIX_0F3840,
1066   PREFIX_0F3841,
1067   PREFIX_0F3880,
1068   PREFIX_0F3881,
1069   PREFIX_0F3882,
1070   PREFIX_0F38C8,
1071   PREFIX_0F38C9,
1072   PREFIX_0F38CA,
1073   PREFIX_0F38CB,
1074   PREFIX_0F38CC,
1075   PREFIX_0F38CD,
1076   PREFIX_0F38CF,
1077   PREFIX_0F38DB,
1078   PREFIX_0F38DC,
1079   PREFIX_0F38DD,
1080   PREFIX_0F38DE,
1081   PREFIX_0F38DF,
1082   PREFIX_0F38F0,
1083   PREFIX_0F38F1,
1084   PREFIX_0F38F5,
1085   PREFIX_0F38F6,
1086   PREFIX_0F38F8,
1087   PREFIX_0F38F9,
1088   PREFIX_0F3A08,
1089   PREFIX_0F3A09,
1090   PREFIX_0F3A0A,
1091   PREFIX_0F3A0B,
1092   PREFIX_0F3A0C,
1093   PREFIX_0F3A0D,
1094   PREFIX_0F3A0E,
1095   PREFIX_0F3A14,
1096   PREFIX_0F3A15,
1097   PREFIX_0F3A16,
1098   PREFIX_0F3A17,
1099   PREFIX_0F3A20,
1100   PREFIX_0F3A21,
1101   PREFIX_0F3A22,
1102   PREFIX_0F3A40,
1103   PREFIX_0F3A41,
1104   PREFIX_0F3A42,
1105   PREFIX_0F3A44,
1106   PREFIX_0F3A60,
1107   PREFIX_0F3A61,
1108   PREFIX_0F3A62,
1109   PREFIX_0F3A63,
1110   PREFIX_0F3ACC,
1111   PREFIX_0F3ACE,
1112   PREFIX_0F3ACF,
1113   PREFIX_0F3ADF,
1114   PREFIX_VEX_0F10,
1115   PREFIX_VEX_0F11,
1116   PREFIX_VEX_0F12,
1117   PREFIX_VEX_0F16,
1118   PREFIX_VEX_0F2A,
1119   PREFIX_VEX_0F2C,
1120   PREFIX_VEX_0F2D,
1121   PREFIX_VEX_0F2E,
1122   PREFIX_VEX_0F2F,
1123   PREFIX_VEX_0F41,
1124   PREFIX_VEX_0F42,
1125   PREFIX_VEX_0F44,
1126   PREFIX_VEX_0F45,
1127   PREFIX_VEX_0F46,
1128   PREFIX_VEX_0F47,
1129   PREFIX_VEX_0F4A,
1130   PREFIX_VEX_0F4B,
1131   PREFIX_VEX_0F51,
1132   PREFIX_VEX_0F52,
1133   PREFIX_VEX_0F53,
1134   PREFIX_VEX_0F58,
1135   PREFIX_VEX_0F59,
1136   PREFIX_VEX_0F5A,
1137   PREFIX_VEX_0F5B,
1138   PREFIX_VEX_0F5C,
1139   PREFIX_VEX_0F5D,
1140   PREFIX_VEX_0F5E,
1141   PREFIX_VEX_0F5F,
1142   PREFIX_VEX_0F60,
1143   PREFIX_VEX_0F61,
1144   PREFIX_VEX_0F62,
1145   PREFIX_VEX_0F63,
1146   PREFIX_VEX_0F64,
1147   PREFIX_VEX_0F65,
1148   PREFIX_VEX_0F66,
1149   PREFIX_VEX_0F67,
1150   PREFIX_VEX_0F68,
1151   PREFIX_VEX_0F69,
1152   PREFIX_VEX_0F6A,
1153   PREFIX_VEX_0F6B,
1154   PREFIX_VEX_0F6C,
1155   PREFIX_VEX_0F6D,
1156   PREFIX_VEX_0F6E,
1157   PREFIX_VEX_0F6F,
1158   PREFIX_VEX_0F70,
1159   PREFIX_VEX_0F71_REG_2,
1160   PREFIX_VEX_0F71_REG_4,
1161   PREFIX_VEX_0F71_REG_6,
1162   PREFIX_VEX_0F72_REG_2,
1163   PREFIX_VEX_0F72_REG_4,
1164   PREFIX_VEX_0F72_REG_6,
1165   PREFIX_VEX_0F73_REG_2,
1166   PREFIX_VEX_0F73_REG_3,
1167   PREFIX_VEX_0F73_REG_6,
1168   PREFIX_VEX_0F73_REG_7,
1169   PREFIX_VEX_0F74,
1170   PREFIX_VEX_0F75,
1171   PREFIX_VEX_0F76,
1172   PREFIX_VEX_0F77,
1173   PREFIX_VEX_0F7C,
1174   PREFIX_VEX_0F7D,
1175   PREFIX_VEX_0F7E,
1176   PREFIX_VEX_0F7F,
1177   PREFIX_VEX_0F90,
1178   PREFIX_VEX_0F91,
1179   PREFIX_VEX_0F92,
1180   PREFIX_VEX_0F93,
1181   PREFIX_VEX_0F98,
1182   PREFIX_VEX_0F99,
1183   PREFIX_VEX_0FC2,
1184   PREFIX_VEX_0FC4,
1185   PREFIX_VEX_0FC5,
1186   PREFIX_VEX_0FD0,
1187   PREFIX_VEX_0FD1,
1188   PREFIX_VEX_0FD2,
1189   PREFIX_VEX_0FD3,
1190   PREFIX_VEX_0FD4,
1191   PREFIX_VEX_0FD5,
1192   PREFIX_VEX_0FD6,
1193   PREFIX_VEX_0FD7,
1194   PREFIX_VEX_0FD8,
1195   PREFIX_VEX_0FD9,
1196   PREFIX_VEX_0FDA,
1197   PREFIX_VEX_0FDB,
1198   PREFIX_VEX_0FDC,
1199   PREFIX_VEX_0FDD,
1200   PREFIX_VEX_0FDE,
1201   PREFIX_VEX_0FDF,
1202   PREFIX_VEX_0FE0,
1203   PREFIX_VEX_0FE1,
1204   PREFIX_VEX_0FE2,
1205   PREFIX_VEX_0FE3,
1206   PREFIX_VEX_0FE4,
1207   PREFIX_VEX_0FE5,
1208   PREFIX_VEX_0FE6,
1209   PREFIX_VEX_0FE7,
1210   PREFIX_VEX_0FE8,
1211   PREFIX_VEX_0FE9,
1212   PREFIX_VEX_0FEA,
1213   PREFIX_VEX_0FEB,
1214   PREFIX_VEX_0FEC,
1215   PREFIX_VEX_0FED,
1216   PREFIX_VEX_0FEE,
1217   PREFIX_VEX_0FEF,
1218   PREFIX_VEX_0FF0,
1219   PREFIX_VEX_0FF1,
1220   PREFIX_VEX_0FF2,
1221   PREFIX_VEX_0FF3,
1222   PREFIX_VEX_0FF4,
1223   PREFIX_VEX_0FF5,
1224   PREFIX_VEX_0FF6,
1225   PREFIX_VEX_0FF7,
1226   PREFIX_VEX_0FF8,
1227   PREFIX_VEX_0FF9,
1228   PREFIX_VEX_0FFA,
1229   PREFIX_VEX_0FFB,
1230   PREFIX_VEX_0FFC,
1231   PREFIX_VEX_0FFD,
1232   PREFIX_VEX_0FFE,
1233   PREFIX_VEX_0F3800,
1234   PREFIX_VEX_0F3801,
1235   PREFIX_VEX_0F3802,
1236   PREFIX_VEX_0F3803,
1237   PREFIX_VEX_0F3804,
1238   PREFIX_VEX_0F3805,
1239   PREFIX_VEX_0F3806,
1240   PREFIX_VEX_0F3807,
1241   PREFIX_VEX_0F3808,
1242   PREFIX_VEX_0F3809,
1243   PREFIX_VEX_0F380A,
1244   PREFIX_VEX_0F380B,
1245   PREFIX_VEX_0F380C,
1246   PREFIX_VEX_0F380D,
1247   PREFIX_VEX_0F380E,
1248   PREFIX_VEX_0F380F,
1249   PREFIX_VEX_0F3813,
1250   PREFIX_VEX_0F3816,
1251   PREFIX_VEX_0F3817,
1252   PREFIX_VEX_0F3818,
1253   PREFIX_VEX_0F3819,
1254   PREFIX_VEX_0F381A,
1255   PREFIX_VEX_0F381C,
1256   PREFIX_VEX_0F381D,
1257   PREFIX_VEX_0F381E,
1258   PREFIX_VEX_0F3820,
1259   PREFIX_VEX_0F3821,
1260   PREFIX_VEX_0F3822,
1261   PREFIX_VEX_0F3823,
1262   PREFIX_VEX_0F3824,
1263   PREFIX_VEX_0F3825,
1264   PREFIX_VEX_0F3828,
1265   PREFIX_VEX_0F3829,
1266   PREFIX_VEX_0F382A,
1267   PREFIX_VEX_0F382B,
1268   PREFIX_VEX_0F382C,
1269   PREFIX_VEX_0F382D,
1270   PREFIX_VEX_0F382E,
1271   PREFIX_VEX_0F382F,
1272   PREFIX_VEX_0F3830,
1273   PREFIX_VEX_0F3831,
1274   PREFIX_VEX_0F3832,
1275   PREFIX_VEX_0F3833,
1276   PREFIX_VEX_0F3834,
1277   PREFIX_VEX_0F3835,
1278   PREFIX_VEX_0F3836,
1279   PREFIX_VEX_0F3837,
1280   PREFIX_VEX_0F3838,
1281   PREFIX_VEX_0F3839,
1282   PREFIX_VEX_0F383A,
1283   PREFIX_VEX_0F383B,
1284   PREFIX_VEX_0F383C,
1285   PREFIX_VEX_0F383D,
1286   PREFIX_VEX_0F383E,
1287   PREFIX_VEX_0F383F,
1288   PREFIX_VEX_0F3840,
1289   PREFIX_VEX_0F3841,
1290   PREFIX_VEX_0F3845,
1291   PREFIX_VEX_0F3846,
1292   PREFIX_VEX_0F3847,
1293   PREFIX_VEX_0F3858,
1294   PREFIX_VEX_0F3859,
1295   PREFIX_VEX_0F385A,
1296   PREFIX_VEX_0F3878,
1297   PREFIX_VEX_0F3879,
1298   PREFIX_VEX_0F388C,
1299   PREFIX_VEX_0F388E,
1300   PREFIX_VEX_0F3890,
1301   PREFIX_VEX_0F3891,
1302   PREFIX_VEX_0F3892,
1303   PREFIX_VEX_0F3893,
1304   PREFIX_VEX_0F3896,
1305   PREFIX_VEX_0F3897,
1306   PREFIX_VEX_0F3898,
1307   PREFIX_VEX_0F3899,
1308   PREFIX_VEX_0F389A,
1309   PREFIX_VEX_0F389B,
1310   PREFIX_VEX_0F389C,
1311   PREFIX_VEX_0F389D,
1312   PREFIX_VEX_0F389E,
1313   PREFIX_VEX_0F389F,
1314   PREFIX_VEX_0F38A6,
1315   PREFIX_VEX_0F38A7,
1316   PREFIX_VEX_0F38A8,
1317   PREFIX_VEX_0F38A9,
1318   PREFIX_VEX_0F38AA,
1319   PREFIX_VEX_0F38AB,
1320   PREFIX_VEX_0F38AC,
1321   PREFIX_VEX_0F38AD,
1322   PREFIX_VEX_0F38AE,
1323   PREFIX_VEX_0F38AF,
1324   PREFIX_VEX_0F38B6,
1325   PREFIX_VEX_0F38B7,
1326   PREFIX_VEX_0F38B8,
1327   PREFIX_VEX_0F38B9,
1328   PREFIX_VEX_0F38BA,
1329   PREFIX_VEX_0F38BB,
1330   PREFIX_VEX_0F38BC,
1331   PREFIX_VEX_0F38BD,
1332   PREFIX_VEX_0F38BE,
1333   PREFIX_VEX_0F38BF,
1334   PREFIX_VEX_0F38CF,
1335   PREFIX_VEX_0F38DB,
1336   PREFIX_VEX_0F38DC,
1337   PREFIX_VEX_0F38DD,
1338   PREFIX_VEX_0F38DE,
1339   PREFIX_VEX_0F38DF,
1340   PREFIX_VEX_0F38F2,
1341   PREFIX_VEX_0F38F3_REG_1,
1342   PREFIX_VEX_0F38F3_REG_2,
1343   PREFIX_VEX_0F38F3_REG_3,
1344   PREFIX_VEX_0F38F5,
1345   PREFIX_VEX_0F38F6,
1346   PREFIX_VEX_0F38F7,
1347   PREFIX_VEX_0F3A00,
1348   PREFIX_VEX_0F3A01,
1349   PREFIX_VEX_0F3A02,
1350   PREFIX_VEX_0F3A04,
1351   PREFIX_VEX_0F3A05,
1352   PREFIX_VEX_0F3A06,
1353   PREFIX_VEX_0F3A08,
1354   PREFIX_VEX_0F3A09,
1355   PREFIX_VEX_0F3A0A,
1356   PREFIX_VEX_0F3A0B,
1357   PREFIX_VEX_0F3A0C,
1358   PREFIX_VEX_0F3A0D,
1359   PREFIX_VEX_0F3A0E,
1360   PREFIX_VEX_0F3A0F,
1361   PREFIX_VEX_0F3A14,
1362   PREFIX_VEX_0F3A15,
1363   PREFIX_VEX_0F3A16,
1364   PREFIX_VEX_0F3A17,
1365   PREFIX_VEX_0F3A18,
1366   PREFIX_VEX_0F3A19,
1367   PREFIX_VEX_0F3A1D,
1368   PREFIX_VEX_0F3A20,
1369   PREFIX_VEX_0F3A21,
1370   PREFIX_VEX_0F3A22,
1371   PREFIX_VEX_0F3A30,
1372   PREFIX_VEX_0F3A31,
1373   PREFIX_VEX_0F3A32,
1374   PREFIX_VEX_0F3A33,
1375   PREFIX_VEX_0F3A38,
1376   PREFIX_VEX_0F3A39,
1377   PREFIX_VEX_0F3A40,
1378   PREFIX_VEX_0F3A41,
1379   PREFIX_VEX_0F3A42,
1380   PREFIX_VEX_0F3A44,
1381   PREFIX_VEX_0F3A46,
1382   PREFIX_VEX_0F3A48,
1383   PREFIX_VEX_0F3A49,
1384   PREFIX_VEX_0F3A4A,
1385   PREFIX_VEX_0F3A4B,
1386   PREFIX_VEX_0F3A4C,
1387   PREFIX_VEX_0F3A5C,
1388   PREFIX_VEX_0F3A5D,
1389   PREFIX_VEX_0F3A5E,
1390   PREFIX_VEX_0F3A5F,
1391   PREFIX_VEX_0F3A60,
1392   PREFIX_VEX_0F3A61,
1393   PREFIX_VEX_0F3A62,
1394   PREFIX_VEX_0F3A63,
1395   PREFIX_VEX_0F3A68,
1396   PREFIX_VEX_0F3A69,
1397   PREFIX_VEX_0F3A6A,
1398   PREFIX_VEX_0F3A6B,
1399   PREFIX_VEX_0F3A6C,
1400   PREFIX_VEX_0F3A6D,
1401   PREFIX_VEX_0F3A6E,
1402   PREFIX_VEX_0F3A6F,
1403   PREFIX_VEX_0F3A78,
1404   PREFIX_VEX_0F3A79,
1405   PREFIX_VEX_0F3A7A,
1406   PREFIX_VEX_0F3A7B,
1407   PREFIX_VEX_0F3A7C,
1408   PREFIX_VEX_0F3A7D,
1409   PREFIX_VEX_0F3A7E,
1410   PREFIX_VEX_0F3A7F,
1411   PREFIX_VEX_0F3ACE,
1412   PREFIX_VEX_0F3ACF,
1413   PREFIX_VEX_0F3ADF,
1414   PREFIX_VEX_0F3AF0,
1415
1416   PREFIX_EVEX_0F10,
1417   PREFIX_EVEX_0F11,
1418   PREFIX_EVEX_0F12,
1419   PREFIX_EVEX_0F16,
1420   PREFIX_EVEX_0F2A,
1421   PREFIX_EVEX_0F2C,
1422   PREFIX_EVEX_0F2D,
1423   PREFIX_EVEX_0F2E,
1424   PREFIX_EVEX_0F2F,
1425   PREFIX_EVEX_0F51,
1426   PREFIX_EVEX_0F58,
1427   PREFIX_EVEX_0F59,
1428   PREFIX_EVEX_0F5A,
1429   PREFIX_EVEX_0F5B,
1430   PREFIX_EVEX_0F5C,
1431   PREFIX_EVEX_0F5D,
1432   PREFIX_EVEX_0F5E,
1433   PREFIX_EVEX_0F5F,
1434   PREFIX_EVEX_0F60,
1435   PREFIX_EVEX_0F61,
1436   PREFIX_EVEX_0F62,
1437   PREFIX_EVEX_0F63,
1438   PREFIX_EVEX_0F64,
1439   PREFIX_EVEX_0F65,
1440   PREFIX_EVEX_0F66,
1441   PREFIX_EVEX_0F67,
1442   PREFIX_EVEX_0F68,
1443   PREFIX_EVEX_0F69,
1444   PREFIX_EVEX_0F6A,
1445   PREFIX_EVEX_0F6B,
1446   PREFIX_EVEX_0F6C,
1447   PREFIX_EVEX_0F6D,
1448   PREFIX_EVEX_0F6E,
1449   PREFIX_EVEX_0F6F,
1450   PREFIX_EVEX_0F70,
1451   PREFIX_EVEX_0F71_REG_2,
1452   PREFIX_EVEX_0F71_REG_4,
1453   PREFIX_EVEX_0F71_REG_6,
1454   PREFIX_EVEX_0F72_REG_0,
1455   PREFIX_EVEX_0F72_REG_1,
1456   PREFIX_EVEX_0F72_REG_2,
1457   PREFIX_EVEX_0F72_REG_4,
1458   PREFIX_EVEX_0F72_REG_6,
1459   PREFIX_EVEX_0F73_REG_2,
1460   PREFIX_EVEX_0F73_REG_3,
1461   PREFIX_EVEX_0F73_REG_6,
1462   PREFIX_EVEX_0F73_REG_7,
1463   PREFIX_EVEX_0F74,
1464   PREFIX_EVEX_0F75,
1465   PREFIX_EVEX_0F76,
1466   PREFIX_EVEX_0F78,
1467   PREFIX_EVEX_0F79,
1468   PREFIX_EVEX_0F7A,
1469   PREFIX_EVEX_0F7B,
1470   PREFIX_EVEX_0F7E,
1471   PREFIX_EVEX_0F7F,
1472   PREFIX_EVEX_0FC2,
1473   PREFIX_EVEX_0FC4,
1474   PREFIX_EVEX_0FC5,
1475   PREFIX_EVEX_0FD1,
1476   PREFIX_EVEX_0FD2,
1477   PREFIX_EVEX_0FD3,
1478   PREFIX_EVEX_0FD4,
1479   PREFIX_EVEX_0FD5,
1480   PREFIX_EVEX_0FD6,
1481   PREFIX_EVEX_0FD8,
1482   PREFIX_EVEX_0FD9,
1483   PREFIX_EVEX_0FDA,
1484   PREFIX_EVEX_0FDB,
1485   PREFIX_EVEX_0FDC,
1486   PREFIX_EVEX_0FDD,
1487   PREFIX_EVEX_0FDE,
1488   PREFIX_EVEX_0FDF,
1489   PREFIX_EVEX_0FE0,
1490   PREFIX_EVEX_0FE1,
1491   PREFIX_EVEX_0FE2,
1492   PREFIX_EVEX_0FE3,
1493   PREFIX_EVEX_0FE4,
1494   PREFIX_EVEX_0FE5,
1495   PREFIX_EVEX_0FE6,
1496   PREFIX_EVEX_0FE7,
1497   PREFIX_EVEX_0FE8,
1498   PREFIX_EVEX_0FE9,
1499   PREFIX_EVEX_0FEA,
1500   PREFIX_EVEX_0FEB,
1501   PREFIX_EVEX_0FEC,
1502   PREFIX_EVEX_0FED,
1503   PREFIX_EVEX_0FEE,
1504   PREFIX_EVEX_0FEF,
1505   PREFIX_EVEX_0FF1,
1506   PREFIX_EVEX_0FF2,
1507   PREFIX_EVEX_0FF3,
1508   PREFIX_EVEX_0FF4,
1509   PREFIX_EVEX_0FF5,
1510   PREFIX_EVEX_0FF6,
1511   PREFIX_EVEX_0FF8,
1512   PREFIX_EVEX_0FF9,
1513   PREFIX_EVEX_0FFA,
1514   PREFIX_EVEX_0FFB,
1515   PREFIX_EVEX_0FFC,
1516   PREFIX_EVEX_0FFD,
1517   PREFIX_EVEX_0FFE,
1518   PREFIX_EVEX_0F3800,
1519   PREFIX_EVEX_0F3804,
1520   PREFIX_EVEX_0F380B,
1521   PREFIX_EVEX_0F380C,
1522   PREFIX_EVEX_0F380D,
1523   PREFIX_EVEX_0F3810,
1524   PREFIX_EVEX_0F3811,
1525   PREFIX_EVEX_0F3812,
1526   PREFIX_EVEX_0F3813,
1527   PREFIX_EVEX_0F3814,
1528   PREFIX_EVEX_0F3815,
1529   PREFIX_EVEX_0F3816,
1530   PREFIX_EVEX_0F3818,
1531   PREFIX_EVEX_0F3819,
1532   PREFIX_EVEX_0F381A,
1533   PREFIX_EVEX_0F381B,
1534   PREFIX_EVEX_0F381C,
1535   PREFIX_EVEX_0F381D,
1536   PREFIX_EVEX_0F381E,
1537   PREFIX_EVEX_0F381F,
1538   PREFIX_EVEX_0F3820,
1539   PREFIX_EVEX_0F3821,
1540   PREFIX_EVEX_0F3822,
1541   PREFIX_EVEX_0F3823,
1542   PREFIX_EVEX_0F3824,
1543   PREFIX_EVEX_0F3825,
1544   PREFIX_EVEX_0F3826,
1545   PREFIX_EVEX_0F3827,
1546   PREFIX_EVEX_0F3828,
1547   PREFIX_EVEX_0F3829,
1548   PREFIX_EVEX_0F382A,
1549   PREFIX_EVEX_0F382B,
1550   PREFIX_EVEX_0F382C,
1551   PREFIX_EVEX_0F382D,
1552   PREFIX_EVEX_0F3830,
1553   PREFIX_EVEX_0F3831,
1554   PREFIX_EVEX_0F3832,
1555   PREFIX_EVEX_0F3833,
1556   PREFIX_EVEX_0F3834,
1557   PREFIX_EVEX_0F3835,
1558   PREFIX_EVEX_0F3836,
1559   PREFIX_EVEX_0F3837,
1560   PREFIX_EVEX_0F3838,
1561   PREFIX_EVEX_0F3839,
1562   PREFIX_EVEX_0F383A,
1563   PREFIX_EVEX_0F383B,
1564   PREFIX_EVEX_0F383C,
1565   PREFIX_EVEX_0F383D,
1566   PREFIX_EVEX_0F383E,
1567   PREFIX_EVEX_0F383F,
1568   PREFIX_EVEX_0F3840,
1569   PREFIX_EVEX_0F3842,
1570   PREFIX_EVEX_0F3843,
1571   PREFIX_EVEX_0F3844,
1572   PREFIX_EVEX_0F3845,
1573   PREFIX_EVEX_0F3846,
1574   PREFIX_EVEX_0F3847,
1575   PREFIX_EVEX_0F384C,
1576   PREFIX_EVEX_0F384D,
1577   PREFIX_EVEX_0F384E,
1578   PREFIX_EVEX_0F384F,
1579   PREFIX_EVEX_0F3850,
1580   PREFIX_EVEX_0F3851,
1581   PREFIX_EVEX_0F3852,
1582   PREFIX_EVEX_0F3853,
1583   PREFIX_EVEX_0F3854,
1584   PREFIX_EVEX_0F3855,
1585   PREFIX_EVEX_0F3858,
1586   PREFIX_EVEX_0F3859,
1587   PREFIX_EVEX_0F385A,
1588   PREFIX_EVEX_0F385B,
1589   PREFIX_EVEX_0F3862,
1590   PREFIX_EVEX_0F3863,
1591   PREFIX_EVEX_0F3864,
1592   PREFIX_EVEX_0F3865,
1593   PREFIX_EVEX_0F3866,
1594   PREFIX_EVEX_0F3868,
1595   PREFIX_EVEX_0F3870,
1596   PREFIX_EVEX_0F3871,
1597   PREFIX_EVEX_0F3872,
1598   PREFIX_EVEX_0F3873,
1599   PREFIX_EVEX_0F3875,
1600   PREFIX_EVEX_0F3876,
1601   PREFIX_EVEX_0F3877,
1602   PREFIX_EVEX_0F3878,
1603   PREFIX_EVEX_0F3879,
1604   PREFIX_EVEX_0F387A,
1605   PREFIX_EVEX_0F387B,
1606   PREFIX_EVEX_0F387C,
1607   PREFIX_EVEX_0F387D,
1608   PREFIX_EVEX_0F387E,
1609   PREFIX_EVEX_0F387F,
1610   PREFIX_EVEX_0F3883,
1611   PREFIX_EVEX_0F3888,
1612   PREFIX_EVEX_0F3889,
1613   PREFIX_EVEX_0F388A,
1614   PREFIX_EVEX_0F388B,
1615   PREFIX_EVEX_0F388D,
1616   PREFIX_EVEX_0F388F,
1617   PREFIX_EVEX_0F3890,
1618   PREFIX_EVEX_0F3891,
1619   PREFIX_EVEX_0F3892,
1620   PREFIX_EVEX_0F3893,
1621   PREFIX_EVEX_0F3896,
1622   PREFIX_EVEX_0F3897,
1623   PREFIX_EVEX_0F3898,
1624   PREFIX_EVEX_0F3899,
1625   PREFIX_EVEX_0F389A,
1626   PREFIX_EVEX_0F389B,
1627   PREFIX_EVEX_0F389C,
1628   PREFIX_EVEX_0F389D,
1629   PREFIX_EVEX_0F389E,
1630   PREFIX_EVEX_0F389F,
1631   PREFIX_EVEX_0F38A0,
1632   PREFIX_EVEX_0F38A1,
1633   PREFIX_EVEX_0F38A2,
1634   PREFIX_EVEX_0F38A3,
1635   PREFIX_EVEX_0F38A6,
1636   PREFIX_EVEX_0F38A7,
1637   PREFIX_EVEX_0F38A8,
1638   PREFIX_EVEX_0F38A9,
1639   PREFIX_EVEX_0F38AA,
1640   PREFIX_EVEX_0F38AB,
1641   PREFIX_EVEX_0F38AC,
1642   PREFIX_EVEX_0F38AD,
1643   PREFIX_EVEX_0F38AE,
1644   PREFIX_EVEX_0F38AF,
1645   PREFIX_EVEX_0F38B4,
1646   PREFIX_EVEX_0F38B5,
1647   PREFIX_EVEX_0F38B6,
1648   PREFIX_EVEX_0F38B7,
1649   PREFIX_EVEX_0F38B8,
1650   PREFIX_EVEX_0F38B9,
1651   PREFIX_EVEX_0F38BA,
1652   PREFIX_EVEX_0F38BB,
1653   PREFIX_EVEX_0F38BC,
1654   PREFIX_EVEX_0F38BD,
1655   PREFIX_EVEX_0F38BE,
1656   PREFIX_EVEX_0F38BF,
1657   PREFIX_EVEX_0F38C4,
1658   PREFIX_EVEX_0F38C6_REG_1,
1659   PREFIX_EVEX_0F38C6_REG_2,
1660   PREFIX_EVEX_0F38C6_REG_5,
1661   PREFIX_EVEX_0F38C6_REG_6,
1662   PREFIX_EVEX_0F38C7_REG_1,
1663   PREFIX_EVEX_0F38C7_REG_2,
1664   PREFIX_EVEX_0F38C7_REG_5,
1665   PREFIX_EVEX_0F38C7_REG_6,
1666   PREFIX_EVEX_0F38C8,
1667   PREFIX_EVEX_0F38CA,
1668   PREFIX_EVEX_0F38CB,
1669   PREFIX_EVEX_0F38CC,
1670   PREFIX_EVEX_0F38CD,
1671   PREFIX_EVEX_0F38CF,
1672   PREFIX_EVEX_0F38DC,
1673   PREFIX_EVEX_0F38DD,
1674   PREFIX_EVEX_0F38DE,
1675   PREFIX_EVEX_0F38DF,
1676
1677   PREFIX_EVEX_0F3A00,
1678   PREFIX_EVEX_0F3A01,
1679   PREFIX_EVEX_0F3A03,
1680   PREFIX_EVEX_0F3A04,
1681   PREFIX_EVEX_0F3A05,
1682   PREFIX_EVEX_0F3A08,
1683   PREFIX_EVEX_0F3A09,
1684   PREFIX_EVEX_0F3A0A,
1685   PREFIX_EVEX_0F3A0B,
1686   PREFIX_EVEX_0F3A0F,
1687   PREFIX_EVEX_0F3A14,
1688   PREFIX_EVEX_0F3A15,
1689   PREFIX_EVEX_0F3A16,
1690   PREFIX_EVEX_0F3A17,
1691   PREFIX_EVEX_0F3A18,
1692   PREFIX_EVEX_0F3A19,
1693   PREFIX_EVEX_0F3A1A,
1694   PREFIX_EVEX_0F3A1B,
1695   PREFIX_EVEX_0F3A1D,
1696   PREFIX_EVEX_0F3A1E,
1697   PREFIX_EVEX_0F3A1F,
1698   PREFIX_EVEX_0F3A20,
1699   PREFIX_EVEX_0F3A21,
1700   PREFIX_EVEX_0F3A22,
1701   PREFIX_EVEX_0F3A23,
1702   PREFIX_EVEX_0F3A25,
1703   PREFIX_EVEX_0F3A26,
1704   PREFIX_EVEX_0F3A27,
1705   PREFIX_EVEX_0F3A38,
1706   PREFIX_EVEX_0F3A39,
1707   PREFIX_EVEX_0F3A3A,
1708   PREFIX_EVEX_0F3A3B,
1709   PREFIX_EVEX_0F3A3E,
1710   PREFIX_EVEX_0F3A3F,
1711   PREFIX_EVEX_0F3A42,
1712   PREFIX_EVEX_0F3A43,
1713   PREFIX_EVEX_0F3A44,
1714   PREFIX_EVEX_0F3A50,
1715   PREFIX_EVEX_0F3A51,
1716   PREFIX_EVEX_0F3A54,
1717   PREFIX_EVEX_0F3A55,
1718   PREFIX_EVEX_0F3A56,
1719   PREFIX_EVEX_0F3A57,
1720   PREFIX_EVEX_0F3A66,
1721   PREFIX_EVEX_0F3A67,
1722   PREFIX_EVEX_0F3A70,
1723   PREFIX_EVEX_0F3A71,
1724   PREFIX_EVEX_0F3A72,
1725   PREFIX_EVEX_0F3A73,
1726   PREFIX_EVEX_0F3ACE,
1727   PREFIX_EVEX_0F3ACF
1728 };
1729
1730 enum
1731 {
1732   X86_64_06 = 0,
1733   X86_64_07,
1734   X86_64_0E,
1735   X86_64_16,
1736   X86_64_17,
1737   X86_64_1E,
1738   X86_64_1F,
1739   X86_64_27,
1740   X86_64_2F,
1741   X86_64_37,
1742   X86_64_3F,
1743   X86_64_60,
1744   X86_64_61,
1745   X86_64_62,
1746   X86_64_63,
1747   X86_64_6D,
1748   X86_64_6F,
1749   X86_64_82,
1750   X86_64_9A,
1751   X86_64_C2,
1752   X86_64_C3,
1753   X86_64_C4,
1754   X86_64_C5,
1755   X86_64_CE,
1756   X86_64_D4,
1757   X86_64_D5,
1758   X86_64_E8,
1759   X86_64_E9,
1760   X86_64_EA,
1761   X86_64_0F01_REG_0,
1762   X86_64_0F01_REG_1,
1763   X86_64_0F01_REG_2,
1764   X86_64_0F01_REG_3
1765 };
1766
1767 enum
1768 {
1769   THREE_BYTE_0F38 = 0,
1770   THREE_BYTE_0F3A
1771 };
1772
1773 enum
1774 {
1775   XOP_08 = 0,
1776   XOP_09,
1777   XOP_0A
1778 };
1779
1780 enum
1781 {
1782   VEX_0F = 0,
1783   VEX_0F38,
1784   VEX_0F3A
1785 };
1786
1787 enum
1788 {
1789   EVEX_0F = 0,
1790   EVEX_0F38,
1791   EVEX_0F3A
1792 };
1793
1794 enum
1795 {
1796   VEX_LEN_0F12_P_0_M_0 = 0,
1797   VEX_LEN_0F12_P_0_M_1,
1798 #define VEX_LEN_0F12_P_2_M_0 VEX_LEN_0F12_P_0_M_0
1799   VEX_LEN_0F13_M_0,
1800   VEX_LEN_0F16_P_0_M_0,
1801   VEX_LEN_0F16_P_0_M_1,
1802 #define VEX_LEN_0F16_P_2_M_0 VEX_LEN_0F16_P_0_M_0
1803   VEX_LEN_0F17_M_0,
1804   VEX_LEN_0F41_P_0,
1805   VEX_LEN_0F41_P_2,
1806   VEX_LEN_0F42_P_0,
1807   VEX_LEN_0F42_P_2,
1808   VEX_LEN_0F44_P_0,
1809   VEX_LEN_0F44_P_2,
1810   VEX_LEN_0F45_P_0,
1811   VEX_LEN_0F45_P_2,
1812   VEX_LEN_0F46_P_0,
1813   VEX_LEN_0F46_P_2,
1814   VEX_LEN_0F47_P_0,
1815   VEX_LEN_0F47_P_2,
1816   VEX_LEN_0F4A_P_0,
1817   VEX_LEN_0F4A_P_2,
1818   VEX_LEN_0F4B_P_0,
1819   VEX_LEN_0F4B_P_2,
1820   VEX_LEN_0F6E_P_2,
1821   VEX_LEN_0F77_P_0,
1822   VEX_LEN_0F7E_P_1,
1823   VEX_LEN_0F7E_P_2,
1824   VEX_LEN_0F90_P_0,
1825   VEX_LEN_0F90_P_2,
1826   VEX_LEN_0F91_P_0,
1827   VEX_LEN_0F91_P_2,
1828   VEX_LEN_0F92_P_0,
1829   VEX_LEN_0F92_P_2,
1830   VEX_LEN_0F92_P_3,
1831   VEX_LEN_0F93_P_0,
1832   VEX_LEN_0F93_P_2,
1833   VEX_LEN_0F93_P_3,
1834   VEX_LEN_0F98_P_0,
1835   VEX_LEN_0F98_P_2,
1836   VEX_LEN_0F99_P_0,
1837   VEX_LEN_0F99_P_2,
1838   VEX_LEN_0FAE_R_2_M_0,
1839   VEX_LEN_0FAE_R_3_M_0,
1840   VEX_LEN_0FC4_P_2,
1841   VEX_LEN_0FC5_P_2,
1842   VEX_LEN_0FD6_P_2,
1843   VEX_LEN_0FF7_P_2,
1844   VEX_LEN_0F3816_P_2,
1845   VEX_LEN_0F3819_P_2,
1846   VEX_LEN_0F381A_P_2_M_0,
1847   VEX_LEN_0F3836_P_2,
1848   VEX_LEN_0F3841_P_2,
1849   VEX_LEN_0F385A_P_2_M_0,
1850   VEX_LEN_0F38DB_P_2,
1851   VEX_LEN_0F38F2_P_0,
1852   VEX_LEN_0F38F3_R_1_P_0,
1853   VEX_LEN_0F38F3_R_2_P_0,
1854   VEX_LEN_0F38F3_R_3_P_0,
1855   VEX_LEN_0F38F5_P_0,
1856   VEX_LEN_0F38F5_P_1,
1857   VEX_LEN_0F38F5_P_3,
1858   VEX_LEN_0F38F6_P_3,
1859   VEX_LEN_0F38F7_P_0,
1860   VEX_LEN_0F38F7_P_1,
1861   VEX_LEN_0F38F7_P_2,
1862   VEX_LEN_0F38F7_P_3,
1863   VEX_LEN_0F3A00_P_2,
1864   VEX_LEN_0F3A01_P_2,
1865   VEX_LEN_0F3A06_P_2,
1866   VEX_LEN_0F3A14_P_2,
1867   VEX_LEN_0F3A15_P_2,
1868   VEX_LEN_0F3A16_P_2,
1869   VEX_LEN_0F3A17_P_2,
1870   VEX_LEN_0F3A18_P_2,
1871   VEX_LEN_0F3A19_P_2,
1872   VEX_LEN_0F3A20_P_2,
1873   VEX_LEN_0F3A21_P_2,
1874   VEX_LEN_0F3A22_P_2,
1875   VEX_LEN_0F3A30_P_2,
1876   VEX_LEN_0F3A31_P_2,
1877   VEX_LEN_0F3A32_P_2,
1878   VEX_LEN_0F3A33_P_2,
1879   VEX_LEN_0F3A38_P_2,
1880   VEX_LEN_0F3A39_P_2,
1881   VEX_LEN_0F3A41_P_2,
1882   VEX_LEN_0F3A46_P_2,
1883   VEX_LEN_0F3A60_P_2,
1884   VEX_LEN_0F3A61_P_2,
1885   VEX_LEN_0F3A62_P_2,
1886   VEX_LEN_0F3A63_P_2,
1887   VEX_LEN_0F3A6A_P_2,
1888   VEX_LEN_0F3A6B_P_2,
1889   VEX_LEN_0F3A6E_P_2,
1890   VEX_LEN_0F3A6F_P_2,
1891   VEX_LEN_0F3A7A_P_2,
1892   VEX_LEN_0F3A7B_P_2,
1893   VEX_LEN_0F3A7E_P_2,
1894   VEX_LEN_0F3A7F_P_2,
1895   VEX_LEN_0F3ADF_P_2,
1896   VEX_LEN_0F3AF0_P_3,
1897   VEX_LEN_0FXOP_08_CC,
1898   VEX_LEN_0FXOP_08_CD,
1899   VEX_LEN_0FXOP_08_CE,
1900   VEX_LEN_0FXOP_08_CF,
1901   VEX_LEN_0FXOP_08_EC,
1902   VEX_LEN_0FXOP_08_ED,
1903   VEX_LEN_0FXOP_08_EE,
1904   VEX_LEN_0FXOP_08_EF,
1905   VEX_LEN_0FXOP_09_80,
1906   VEX_LEN_0FXOP_09_81
1907 };
1908
1909 enum
1910 {
1911   EVEX_LEN_0F6E_P_2 = 0,
1912   EVEX_LEN_0F7E_P_1,
1913   EVEX_LEN_0F7E_P_2,
1914   EVEX_LEN_0FD6_P_2,
1915   EVEX_LEN_0F3819_P_2_W_0,
1916   EVEX_LEN_0F3819_P_2_W_1,
1917   EVEX_LEN_0F381A_P_2_W_0,
1918   EVEX_LEN_0F381A_P_2_W_1,
1919   EVEX_LEN_0F381B_P_2_W_0,
1920   EVEX_LEN_0F381B_P_2_W_1,
1921   EVEX_LEN_0F385A_P_2_W_0,
1922   EVEX_LEN_0F385A_P_2_W_1,
1923   EVEX_LEN_0F385B_P_2_W_0,
1924   EVEX_LEN_0F385B_P_2_W_1,
1925   EVEX_LEN_0F38C6_REG_1_PREFIX_2,
1926   EVEX_LEN_0F38C6_REG_2_PREFIX_2,
1927   EVEX_LEN_0F38C6_REG_5_PREFIX_2,
1928   EVEX_LEN_0F38C6_REG_6_PREFIX_2,
1929   EVEX_LEN_0F38C7_R_1_P_2_W_0,
1930   EVEX_LEN_0F38C7_R_1_P_2_W_1,
1931   EVEX_LEN_0F38C7_R_2_P_2_W_0,
1932   EVEX_LEN_0F38C7_R_2_P_2_W_1,
1933   EVEX_LEN_0F38C7_R_5_P_2_W_0,
1934   EVEX_LEN_0F38C7_R_5_P_2_W_1,
1935   EVEX_LEN_0F38C7_R_6_P_2_W_0,
1936   EVEX_LEN_0F38C7_R_6_P_2_W_1,
1937   EVEX_LEN_0F3A18_P_2_W_0,
1938   EVEX_LEN_0F3A18_P_2_W_1,
1939   EVEX_LEN_0F3A19_P_2_W_0,
1940   EVEX_LEN_0F3A19_P_2_W_1,
1941   EVEX_LEN_0F3A1A_P_2_W_0,
1942   EVEX_LEN_0F3A1A_P_2_W_1,
1943   EVEX_LEN_0F3A1B_P_2_W_0,
1944   EVEX_LEN_0F3A1B_P_2_W_1,
1945   EVEX_LEN_0F3A23_P_2_W_0,
1946   EVEX_LEN_0F3A23_P_2_W_1,
1947   EVEX_LEN_0F3A38_P_2_W_0,
1948   EVEX_LEN_0F3A38_P_2_W_1,
1949   EVEX_LEN_0F3A39_P_2_W_0,
1950   EVEX_LEN_0F3A39_P_2_W_1,
1951   EVEX_LEN_0F3A3A_P_2_W_0,
1952   EVEX_LEN_0F3A3A_P_2_W_1,
1953   EVEX_LEN_0F3A3B_P_2_W_0,
1954   EVEX_LEN_0F3A3B_P_2_W_1,
1955   EVEX_LEN_0F3A43_P_2_W_0,
1956   EVEX_LEN_0F3A43_P_2_W_1
1957 };
1958
1959 enum
1960 {
1961   VEX_W_0F41_P_0_LEN_1 = 0,
1962   VEX_W_0F41_P_2_LEN_1,
1963   VEX_W_0F42_P_0_LEN_1,
1964   VEX_W_0F42_P_2_LEN_1,
1965   VEX_W_0F44_P_0_LEN_0,
1966   VEX_W_0F44_P_2_LEN_0,
1967   VEX_W_0F45_P_0_LEN_1,
1968   VEX_W_0F45_P_2_LEN_1,
1969   VEX_W_0F46_P_0_LEN_1,
1970   VEX_W_0F46_P_2_LEN_1,
1971   VEX_W_0F47_P_0_LEN_1,
1972   VEX_W_0F47_P_2_LEN_1,
1973   VEX_W_0F4A_P_0_LEN_1,
1974   VEX_W_0F4A_P_2_LEN_1,
1975   VEX_W_0F4B_P_0_LEN_1,
1976   VEX_W_0F4B_P_2_LEN_1,
1977   VEX_W_0F90_P_0_LEN_0,
1978   VEX_W_0F90_P_2_LEN_0,
1979   VEX_W_0F91_P_0_LEN_0,
1980   VEX_W_0F91_P_2_LEN_0,
1981   VEX_W_0F92_P_0_LEN_0,
1982   VEX_W_0F92_P_2_LEN_0,
1983   VEX_W_0F93_P_0_LEN_0,
1984   VEX_W_0F93_P_2_LEN_0,
1985   VEX_W_0F98_P_0_LEN_0,
1986   VEX_W_0F98_P_2_LEN_0,
1987   VEX_W_0F99_P_0_LEN_0,
1988   VEX_W_0F99_P_2_LEN_0,
1989   VEX_W_0F380C_P_2,
1990   VEX_W_0F380D_P_2,
1991   VEX_W_0F380E_P_2,
1992   VEX_W_0F380F_P_2,
1993   VEX_W_0F3816_P_2,
1994   VEX_W_0F3818_P_2,
1995   VEX_W_0F3819_P_2,
1996   VEX_W_0F381A_P_2_M_0,
1997   VEX_W_0F382C_P_2_M_0,
1998   VEX_W_0F382D_P_2_M_0,
1999   VEX_W_0F382E_P_2_M_0,
2000   VEX_W_0F382F_P_2_M_0,
2001   VEX_W_0F3836_P_2,
2002   VEX_W_0F3846_P_2,
2003   VEX_W_0F3858_P_2,
2004   VEX_W_0F3859_P_2,
2005   VEX_W_0F385A_P_2_M_0,
2006   VEX_W_0F3878_P_2,
2007   VEX_W_0F3879_P_2,
2008   VEX_W_0F38CF_P_2,
2009   VEX_W_0F3A00_P_2,
2010   VEX_W_0F3A01_P_2,
2011   VEX_W_0F3A02_P_2,
2012   VEX_W_0F3A04_P_2,
2013   VEX_W_0F3A05_P_2,
2014   VEX_W_0F3A06_P_2,
2015   VEX_W_0F3A18_P_2,
2016   VEX_W_0F3A19_P_2,
2017   VEX_W_0F3A30_P_2_LEN_0,
2018   VEX_W_0F3A31_P_2_LEN_0,
2019   VEX_W_0F3A32_P_2_LEN_0,
2020   VEX_W_0F3A33_P_2_LEN_0,
2021   VEX_W_0F3A38_P_2,
2022   VEX_W_0F3A39_P_2,
2023   VEX_W_0F3A46_P_2,
2024   VEX_W_0F3A48_P_2,
2025   VEX_W_0F3A49_P_2,
2026   VEX_W_0F3A4A_P_2,
2027   VEX_W_0F3A4B_P_2,
2028   VEX_W_0F3A4C_P_2,
2029   VEX_W_0F3ACE_P_2,
2030   VEX_W_0F3ACF_P_2,
2031
2032   EVEX_W_0F10_P_1,
2033   EVEX_W_0F10_P_3,
2034   EVEX_W_0F11_P_1,
2035   EVEX_W_0F11_P_3,
2036   EVEX_W_0F12_P_0_M_1,
2037   EVEX_W_0F12_P_1,
2038   EVEX_W_0F12_P_3,
2039   EVEX_W_0F16_P_0_M_1,
2040   EVEX_W_0F16_P_1,
2041   EVEX_W_0F2A_P_3,
2042   EVEX_W_0F51_P_1,
2043   EVEX_W_0F51_P_3,
2044   EVEX_W_0F58_P_1,
2045   EVEX_W_0F58_P_3,
2046   EVEX_W_0F59_P_1,
2047   EVEX_W_0F59_P_3,
2048   EVEX_W_0F5A_P_0,
2049   EVEX_W_0F5A_P_1,
2050   EVEX_W_0F5A_P_2,
2051   EVEX_W_0F5A_P_3,
2052   EVEX_W_0F5B_P_0,
2053   EVEX_W_0F5B_P_1,
2054   EVEX_W_0F5B_P_2,
2055   EVEX_W_0F5C_P_1,
2056   EVEX_W_0F5C_P_3,
2057   EVEX_W_0F5D_P_1,
2058   EVEX_W_0F5D_P_3,
2059   EVEX_W_0F5E_P_1,
2060   EVEX_W_0F5E_P_3,
2061   EVEX_W_0F5F_P_1,
2062   EVEX_W_0F5F_P_3,
2063   EVEX_W_0F62_P_2,
2064   EVEX_W_0F66_P_2,
2065   EVEX_W_0F6A_P_2,
2066   EVEX_W_0F6B_P_2,
2067   EVEX_W_0F6C_P_2,
2068   EVEX_W_0F6D_P_2,
2069   EVEX_W_0F6F_P_1,
2070   EVEX_W_0F6F_P_2,
2071   EVEX_W_0F6F_P_3,
2072   EVEX_W_0F70_P_2,
2073   EVEX_W_0F72_R_2_P_2,
2074   EVEX_W_0F72_R_6_P_2,
2075   EVEX_W_0F73_R_2_P_2,
2076   EVEX_W_0F73_R_6_P_2,
2077   EVEX_W_0F76_P_2,
2078   EVEX_W_0F78_P_0,
2079   EVEX_W_0F78_P_2,
2080   EVEX_W_0F79_P_0,
2081   EVEX_W_0F79_P_2,
2082   EVEX_W_0F7A_P_1,
2083   EVEX_W_0F7A_P_2,
2084   EVEX_W_0F7A_P_3,
2085   EVEX_W_0F7B_P_2,
2086   EVEX_W_0F7B_P_3,
2087   EVEX_W_0F7E_P_1,
2088   EVEX_W_0F7F_P_1,
2089   EVEX_W_0F7F_P_2,
2090   EVEX_W_0F7F_P_3,
2091   EVEX_W_0FC2_P_1,
2092   EVEX_W_0FC2_P_3,
2093   EVEX_W_0FD2_P_2,
2094   EVEX_W_0FD3_P_2,
2095   EVEX_W_0FD4_P_2,
2096   EVEX_W_0FD6_P_2,
2097   EVEX_W_0FE6_P_1,
2098   EVEX_W_0FE6_P_2,
2099   EVEX_W_0FE6_P_3,
2100   EVEX_W_0FE7_P_2,
2101   EVEX_W_0FF2_P_2,
2102   EVEX_W_0FF3_P_2,
2103   EVEX_W_0FF4_P_2,
2104   EVEX_W_0FFA_P_2,
2105   EVEX_W_0FFB_P_2,
2106   EVEX_W_0FFE_P_2,
2107   EVEX_W_0F380C_P_2,
2108   EVEX_W_0F380D_P_2,
2109   EVEX_W_0F3810_P_1,
2110   EVEX_W_0F3810_P_2,
2111   EVEX_W_0F3811_P_1,
2112   EVEX_W_0F3811_P_2,
2113   EVEX_W_0F3812_P_1,
2114   EVEX_W_0F3812_P_2,
2115   EVEX_W_0F3813_P_1,
2116   EVEX_W_0F3813_P_2,
2117   EVEX_W_0F3814_P_1,
2118   EVEX_W_0F3815_P_1,
2119   EVEX_W_0F3818_P_2,
2120   EVEX_W_0F3819_P_2,
2121   EVEX_W_0F381A_P_2,
2122   EVEX_W_0F381B_P_2,
2123   EVEX_W_0F381E_P_2,
2124   EVEX_W_0F381F_P_2,
2125   EVEX_W_0F3820_P_1,
2126   EVEX_W_0F3821_P_1,
2127   EVEX_W_0F3822_P_1,
2128   EVEX_W_0F3823_P_1,
2129   EVEX_W_0F3824_P_1,
2130   EVEX_W_0F3825_P_1,
2131   EVEX_W_0F3825_P_2,
2132   EVEX_W_0F3826_P_1,
2133   EVEX_W_0F3826_P_2,
2134   EVEX_W_0F3828_P_1,
2135   EVEX_W_0F3828_P_2,
2136   EVEX_W_0F3829_P_1,
2137   EVEX_W_0F3829_P_2,
2138   EVEX_W_0F382A_P_1,
2139   EVEX_W_0F382A_P_2,
2140   EVEX_W_0F382B_P_2,
2141   EVEX_W_0F3830_P_1,
2142   EVEX_W_0F3831_P_1,
2143   EVEX_W_0F3832_P_1,
2144   EVEX_W_0F3833_P_1,
2145   EVEX_W_0F3834_P_1,
2146   EVEX_W_0F3835_P_1,
2147   EVEX_W_0F3835_P_2,
2148   EVEX_W_0F3837_P_2,
2149   EVEX_W_0F3838_P_1,
2150   EVEX_W_0F3839_P_1,
2151   EVEX_W_0F383A_P_1,
2152   EVEX_W_0F3840_P_2,
2153   EVEX_W_0F3852_P_1,
2154   EVEX_W_0F3854_P_2,
2155   EVEX_W_0F3855_P_2,
2156   EVEX_W_0F3858_P_2,
2157   EVEX_W_0F3859_P_2,
2158   EVEX_W_0F385A_P_2,
2159   EVEX_W_0F385B_P_2,
2160   EVEX_W_0F3862_P_2,
2161   EVEX_W_0F3863_P_2,
2162   EVEX_W_0F3866_P_2,
2163   EVEX_W_0F3868_P_3,
2164   EVEX_W_0F3870_P_2,
2165   EVEX_W_0F3871_P_2,
2166   EVEX_W_0F3872_P_1,
2167   EVEX_W_0F3872_P_2,
2168   EVEX_W_0F3872_P_3,
2169   EVEX_W_0F3873_P_2,
2170   EVEX_W_0F3875_P_2,
2171   EVEX_W_0F3878_P_2,
2172   EVEX_W_0F3879_P_2,
2173   EVEX_W_0F387A_P_2,
2174   EVEX_W_0F387B_P_2,
2175   EVEX_W_0F387D_P_2,
2176   EVEX_W_0F3883_P_2,
2177   EVEX_W_0F388D_P_2,
2178   EVEX_W_0F3891_P_2,
2179   EVEX_W_0F3893_P_2,
2180   EVEX_W_0F38A1_P_2,
2181   EVEX_W_0F38A3_P_2,
2182   EVEX_W_0F38C7_R_1_P_2,
2183   EVEX_W_0F38C7_R_2_P_2,
2184   EVEX_W_0F38C7_R_5_P_2,
2185   EVEX_W_0F38C7_R_6_P_2,
2186
2187   EVEX_W_0F3A00_P_2,
2188   EVEX_W_0F3A01_P_2,
2189   EVEX_W_0F3A04_P_2,
2190   EVEX_W_0F3A05_P_2,
2191   EVEX_W_0F3A08_P_2,
2192   EVEX_W_0F3A09_P_2,
2193   EVEX_W_0F3A0A_P_2,
2194   EVEX_W_0F3A0B_P_2,
2195   EVEX_W_0F3A18_P_2,
2196   EVEX_W_0F3A19_P_2,
2197   EVEX_W_0F3A1A_P_2,
2198   EVEX_W_0F3A1B_P_2,
2199   EVEX_W_0F3A1D_P_2,
2200   EVEX_W_0F3A21_P_2,
2201   EVEX_W_0F3A23_P_2,
2202   EVEX_W_0F3A38_P_2,
2203   EVEX_W_0F3A39_P_2,
2204   EVEX_W_0F3A3A_P_2,
2205   EVEX_W_0F3A3B_P_2,
2206   EVEX_W_0F3A3E_P_2,
2207   EVEX_W_0F3A3F_P_2,
2208   EVEX_W_0F3A42_P_2,
2209   EVEX_W_0F3A43_P_2,
2210   EVEX_W_0F3A50_P_2,
2211   EVEX_W_0F3A51_P_2,
2212   EVEX_W_0F3A56_P_2,
2213   EVEX_W_0F3A57_P_2,
2214   EVEX_W_0F3A66_P_2,
2215   EVEX_W_0F3A67_P_2,
2216   EVEX_W_0F3A70_P_2,
2217   EVEX_W_0F3A71_P_2,
2218   EVEX_W_0F3A72_P_2,
2219   EVEX_W_0F3A73_P_2,
2220   EVEX_W_0F3ACE_P_2,
2221   EVEX_W_0F3ACF_P_2
2222 };
2223
2224 typedef void (*op_rtn) (int bytemode, int sizeflag);
2225
2226 struct dis386 {
2227   const char *name;
2228   struct
2229     {
2230       op_rtn rtn;
2231       int bytemode;
2232     } op[MAX_OPERANDS];
2233   unsigned int prefix_requirement;
2234 };
2235
2236 /* Upper case letters in the instruction names here are macros.
2237    'A' => print 'b' if no register operands or suffix_always is true
2238    'B' => print 'b' if suffix_always is true
2239    'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2240           size prefix
2241    'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2242           suffix_always is true
2243    'E' => print 'e' if 32-bit form of jcxz
2244    'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2245    'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2246    'H' => print ",pt" or ",pn" branch hint
2247    'I' unused.
2248    'J' unused.
2249    'K' => print 'd' or 'q' if rex prefix is present.
2250    'L' => print 'l' if suffix_always is true
2251    'M' => print 'r' if intel_mnemonic is false.
2252    'N' => print 'n' if instruction has no wait "prefix"
2253    'O' => print 'd' or 'o' (or 'q' in Intel mode)
2254    'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2255           or suffix_always is true.  print 'q' if rex prefix is present.
2256    'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2257           is true
2258    'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2259    'S' => print 'w', 'l' or 'q' if suffix_always is true
2260    'T' => print 'q' in 64bit mode if instruction has no operand size
2261           prefix and behave as 'P' otherwise
2262    'U' => print 'q' in 64bit mode if instruction has no operand size
2263           prefix and behave as 'Q' otherwise
2264    'V' => print 'q' in 64bit mode if instruction has no operand size
2265           prefix and behave as 'S' otherwise
2266    'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2267    'X' => print 's', 'd' depending on data16 prefix (for XMM)
2268    'Y' unused.
2269    'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2270    '!' => change condition from true to false or from false to true.
2271    '%' => add 1 upper case letter to the macro.
2272    '^' => print 'w', 'l', or 'q' (Intel64 ISA only) depending on operand size
2273           prefix or suffix_always is true (lcall/ljmp).
2274    '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending
2275           on operand size prefix.
2276    '&' => print 'q' in 64bit mode for Intel64 ISA or if instruction
2277           has no operand size prefix for AMD64 ISA, behave as 'P'
2278           otherwise
2279
2280    2 upper case letter macros:
2281    "XY" => print 'x' or 'y' if suffix_always is true or no register
2282            operands and no broadcast.
2283    "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
2284            register operands and no broadcast.
2285    "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2286    "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory
2287            operand or no operand at all in 64bit mode, or if suffix_always
2288            is true.
2289    "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2290    "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2291    "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2292    "LW" => print 'd', 'q' depending on the VEX.W bit
2293    "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
2294            an operand size prefix, or suffix_always is true.  print
2295            'q' if rex prefix is present.
2296
2297    Many of the above letters print nothing in Intel mode.  See "putop"
2298    for the details.
2299
2300    Braces '{' and '}', and vertical bars '|', indicate alternative
2301    mnemonic strings for AT&T and Intel.  */
2302
2303 static const struct dis386 dis386[] = {
2304   /* 00 */
2305   { "addB",             { Ebh1, Gb }, 0 },
2306   { "addS",             { Evh1, Gv }, 0 },
2307   { "addB",             { Gb, EbS }, 0 },
2308   { "addS",             { Gv, EvS }, 0 },
2309   { "addB",             { AL, Ib }, 0 },
2310   { "addS",             { eAX, Iv }, 0 },
2311   { X86_64_TABLE (X86_64_06) },
2312   { X86_64_TABLE (X86_64_07) },
2313   /* 08 */
2314   { "orB",              { Ebh1, Gb }, 0 },
2315   { "orS",              { Evh1, Gv }, 0 },
2316   { "orB",              { Gb, EbS }, 0 },
2317   { "orS",              { Gv, EvS }, 0 },
2318   { "orB",              { AL, Ib }, 0 },
2319   { "orS",              { eAX, Iv }, 0 },
2320   { X86_64_TABLE (X86_64_0E) },
2321   { Bad_Opcode },       /* 0x0f extended opcode escape */
2322   /* 10 */
2323   { "adcB",             { Ebh1, Gb }, 0 },
2324   { "adcS",             { Evh1, Gv }, 0 },
2325   { "adcB",             { Gb, EbS }, 0 },
2326   { "adcS",             { Gv, EvS }, 0 },
2327   { "adcB",             { AL, Ib }, 0 },
2328   { "adcS",             { eAX, Iv }, 0 },
2329   { X86_64_TABLE (X86_64_16) },
2330   { X86_64_TABLE (X86_64_17) },
2331   /* 18 */
2332   { "sbbB",             { Ebh1, Gb }, 0 },
2333   { "sbbS",             { Evh1, Gv }, 0 },
2334   { "sbbB",             { Gb, EbS }, 0 },
2335   { "sbbS",             { Gv, EvS }, 0 },
2336   { "sbbB",             { AL, Ib }, 0 },
2337   { "sbbS",             { eAX, Iv }, 0 },
2338   { X86_64_TABLE (X86_64_1E) },
2339   { X86_64_TABLE (X86_64_1F) },
2340   /* 20 */
2341   { "andB",             { Ebh1, Gb }, 0 },
2342   { "andS",             { Evh1, Gv }, 0 },
2343   { "andB",             { Gb, EbS }, 0 },
2344   { "andS",             { Gv, EvS }, 0 },
2345   { "andB",             { AL, Ib }, 0 },
2346   { "andS",             { eAX, Iv }, 0 },
2347   { Bad_Opcode },       /* SEG ES prefix */
2348   { X86_64_TABLE (X86_64_27) },
2349   /* 28 */
2350   { "subB",             { Ebh1, Gb }, 0 },
2351   { "subS",             { Evh1, Gv }, 0 },
2352   { "subB",             { Gb, EbS }, 0 },
2353   { "subS",             { Gv, EvS }, 0 },
2354   { "subB",             { AL, Ib }, 0 },
2355   { "subS",             { eAX, Iv }, 0 },
2356   { Bad_Opcode },       /* SEG CS prefix */
2357   { X86_64_TABLE (X86_64_2F) },
2358   /* 30 */
2359   { "xorB",             { Ebh1, Gb }, 0 },
2360   { "xorS",             { Evh1, Gv }, 0 },
2361   { "xorB",             { Gb, EbS }, 0 },
2362   { "xorS",             { Gv, EvS }, 0 },
2363   { "xorB",             { AL, Ib }, 0 },
2364   { "xorS",             { eAX, Iv }, 0 },
2365   { Bad_Opcode },       /* SEG SS prefix */
2366   { X86_64_TABLE (X86_64_37) },
2367   /* 38 */
2368   { "cmpB",             { Eb, Gb }, 0 },
2369   { "cmpS",             { Ev, Gv }, 0 },
2370   { "cmpB",             { Gb, EbS }, 0 },
2371   { "cmpS",             { Gv, EvS }, 0 },
2372   { "cmpB",             { AL, Ib }, 0 },
2373   { "cmpS",             { eAX, Iv }, 0 },
2374   { Bad_Opcode },       /* SEG DS prefix */
2375   { X86_64_TABLE (X86_64_3F) },
2376   /* 40 */
2377   { "inc{S|}",          { RMeAX }, 0 },
2378   { "inc{S|}",          { RMeCX }, 0 },
2379   { "inc{S|}",          { RMeDX }, 0 },
2380   { "inc{S|}",          { RMeBX }, 0 },
2381   { "inc{S|}",          { RMeSP }, 0 },
2382   { "inc{S|}",          { RMeBP }, 0 },
2383   { "inc{S|}",          { RMeSI }, 0 },
2384   { "inc{S|}",          { RMeDI }, 0 },
2385   /* 48 */
2386   { "dec{S|}",          { RMeAX }, 0 },
2387   { "dec{S|}",          { RMeCX }, 0 },
2388   { "dec{S|}",          { RMeDX }, 0 },
2389   { "dec{S|}",          { RMeBX }, 0 },
2390   { "dec{S|}",          { RMeSP }, 0 },
2391   { "dec{S|}",          { RMeBP }, 0 },
2392   { "dec{S|}",          { RMeSI }, 0 },
2393   { "dec{S|}",          { RMeDI }, 0 },
2394   /* 50 */
2395   { "pushV",            { RMrAX }, 0 },
2396   { "pushV",            { RMrCX }, 0 },
2397   { "pushV",            { RMrDX }, 0 },
2398   { "pushV",            { RMrBX }, 0 },
2399   { "pushV",            { RMrSP }, 0 },
2400   { "pushV",            { RMrBP }, 0 },
2401   { "pushV",            { RMrSI }, 0 },
2402   { "pushV",            { RMrDI }, 0 },
2403   /* 58 */
2404   { "popV",             { RMrAX }, 0 },
2405   { "popV",             { RMrCX }, 0 },
2406   { "popV",             { RMrDX }, 0 },
2407   { "popV",             { RMrBX }, 0 },
2408   { "popV",             { RMrSP }, 0 },
2409   { "popV",             { RMrBP }, 0 },
2410   { "popV",             { RMrSI }, 0 },
2411   { "popV",             { RMrDI }, 0 },
2412   /* 60 */
2413   { X86_64_TABLE (X86_64_60) },
2414   { X86_64_TABLE (X86_64_61) },
2415   { X86_64_TABLE (X86_64_62) },
2416   { X86_64_TABLE (X86_64_63) },
2417   { Bad_Opcode },       /* seg fs */
2418   { Bad_Opcode },       /* seg gs */
2419   { Bad_Opcode },       /* op size prefix */
2420   { Bad_Opcode },       /* adr size prefix */
2421   /* 68 */
2422   { "pushT",            { sIv }, 0 },
2423   { "imulS",            { Gv, Ev, Iv }, 0 },
2424   { "pushT",            { sIbT }, 0 },
2425   { "imulS",            { Gv, Ev, sIb }, 0 },
2426   { "ins{b|}",          { Ybr, indirDX }, 0 },
2427   { X86_64_TABLE (X86_64_6D) },
2428   { "outs{b|}",         { indirDXr, Xb }, 0 },
2429   { X86_64_TABLE (X86_64_6F) },
2430   /* 70 */
2431   { "joH",              { Jb, BND, cond_jump_flag }, 0 },
2432   { "jnoH",             { Jb, BND, cond_jump_flag }, 0 },
2433   { "jbH",              { Jb, BND, cond_jump_flag }, 0 },
2434   { "jaeH",             { Jb, BND, cond_jump_flag }, 0 },
2435   { "jeH",              { Jb, BND, cond_jump_flag }, 0 },
2436   { "jneH",             { Jb, BND, cond_jump_flag }, 0 },
2437   { "jbeH",             { Jb, BND, cond_jump_flag }, 0 },
2438   { "jaH",              { Jb, BND, cond_jump_flag }, 0 },
2439   /* 78 */
2440   { "jsH",              { Jb, BND, cond_jump_flag }, 0 },
2441   { "jnsH",             { Jb, BND, cond_jump_flag }, 0 },
2442   { "jpH",              { Jb, BND, cond_jump_flag }, 0 },
2443   { "jnpH",             { Jb, BND, cond_jump_flag }, 0 },
2444   { "jlH",              { Jb, BND, cond_jump_flag }, 0 },
2445   { "jgeH",             { Jb, BND, cond_jump_flag }, 0 },
2446   { "jleH",             { Jb, BND, cond_jump_flag }, 0 },
2447   { "jgH",              { Jb, BND, cond_jump_flag }, 0 },
2448   /* 80 */
2449   { REG_TABLE (REG_80) },
2450   { REG_TABLE (REG_81) },
2451   { X86_64_TABLE (X86_64_82) },
2452   { REG_TABLE (REG_83) },
2453   { "testB",            { Eb, Gb }, 0 },
2454   { "testS",            { Ev, Gv }, 0 },
2455   { "xchgB",            { Ebh2, Gb }, 0 },
2456   { "xchgS",            { Evh2, Gv }, 0 },
2457   /* 88 */
2458   { "movB",             { Ebh3, Gb }, 0 },
2459   { "movS",             { Evh3, Gv }, 0 },
2460   { "movB",             { Gb, EbS }, 0 },
2461   { "movS",             { Gv, EvS }, 0 },
2462   { "movD",             { Sv, Sw }, 0 },
2463   { MOD_TABLE (MOD_8D) },
2464   { "movD",             { Sw, Sv }, 0 },
2465   { REG_TABLE (REG_8F) },
2466   /* 90 */
2467   { PREFIX_TABLE (PREFIX_90) },
2468   { "xchgS",            { RMeCX, eAX }, 0 },
2469   { "xchgS",            { RMeDX, eAX }, 0 },
2470   { "xchgS",            { RMeBX, eAX }, 0 },
2471   { "xchgS",            { RMeSP, eAX }, 0 },
2472   { "xchgS",            { RMeBP, eAX }, 0 },
2473   { "xchgS",            { RMeSI, eAX }, 0 },
2474   { "xchgS",            { RMeDI, eAX }, 0 },
2475   /* 98 */
2476   { "cW{t|}R",          { XX }, 0 },
2477   { "cR{t|}O",          { XX }, 0 },
2478   { X86_64_TABLE (X86_64_9A) },
2479   { Bad_Opcode },       /* fwait */
2480   { "pushfT",           { XX }, 0 },
2481   { "popfT",            { XX }, 0 },
2482   { "sahf",             { XX }, 0 },
2483   { "lahf",             { XX }, 0 },
2484   /* a0 */
2485   { "mov%LB",           { AL, Ob }, 0 },
2486   { "mov%LS",           { eAX, Ov }, 0 },
2487   { "mov%LB",           { Ob, AL }, 0 },
2488   { "mov%LS",           { Ov, eAX }, 0 },
2489   { "movs{b|}",         { Ybr, Xb }, 0 },
2490   { "movs{R|}",         { Yvr, Xv }, 0 },
2491   { "cmps{b|}",         { Xb, Yb }, 0 },
2492   { "cmps{R|}",         { Xv, Yv }, 0 },
2493   /* a8 */
2494   { "testB",            { AL, Ib }, 0 },
2495   { "testS",            { eAX, Iv }, 0 },
2496   { "stosB",            { Ybr, AL }, 0 },
2497   { "stosS",            { Yvr, eAX }, 0 },
2498   { "lodsB",            { ALr, Xb }, 0 },
2499   { "lodsS",            { eAXr, Xv }, 0 },
2500   { "scasB",            { AL, Yb }, 0 },
2501   { "scasS",            { eAX, Yv }, 0 },
2502   /* b0 */
2503   { "movB",             { RMAL, Ib }, 0 },
2504   { "movB",             { RMCL, Ib }, 0 },
2505   { "movB",             { RMDL, Ib }, 0 },
2506   { "movB",             { RMBL, Ib }, 0 },
2507   { "movB",             { RMAH, Ib }, 0 },
2508   { "movB",             { RMCH, Ib }, 0 },
2509   { "movB",             { RMDH, Ib }, 0 },
2510   { "movB",             { RMBH, Ib }, 0 },
2511   /* b8 */
2512   { "mov%LV",           { RMeAX, Iv64 }, 0 },
2513   { "mov%LV",           { RMeCX, Iv64 }, 0 },
2514   { "mov%LV",           { RMeDX, Iv64 }, 0 },
2515   { "mov%LV",           { RMeBX, Iv64 }, 0 },
2516   { "mov%LV",           { RMeSP, Iv64 }, 0 },
2517   { "mov%LV",           { RMeBP, Iv64 }, 0 },
2518   { "mov%LV",           { RMeSI, Iv64 }, 0 },
2519   { "mov%LV",           { RMeDI, Iv64 }, 0 },
2520   /* c0 */
2521   { REG_TABLE (REG_C0) },
2522   { REG_TABLE (REG_C1) },
2523   { X86_64_TABLE (X86_64_C2) },
2524   { X86_64_TABLE (X86_64_C3) },
2525   { X86_64_TABLE (X86_64_C4) },
2526   { X86_64_TABLE (X86_64_C5) },
2527   { REG_TABLE (REG_C6) },
2528   { REG_TABLE (REG_C7) },
2529   /* c8 */
2530   { "enterT",           { Iw, Ib }, 0 },
2531   { "leaveT",           { XX }, 0 },
2532   { "{l|}ret{|f}P",     { Iw }, 0 },
2533   { "{l|}ret{|f}P",     { XX }, 0 },
2534   { "int3",             { XX }, 0 },
2535   { "int",              { Ib }, 0 },
2536   { X86_64_TABLE (X86_64_CE) },
2537   { "iret%LP",          { XX }, 0 },
2538   /* d0 */
2539   { REG_TABLE (REG_D0) },
2540   { REG_TABLE (REG_D1) },
2541   { REG_TABLE (REG_D2) },
2542   { REG_TABLE (REG_D3) },
2543   { X86_64_TABLE (X86_64_D4) },
2544   { X86_64_TABLE (X86_64_D5) },
2545   { Bad_Opcode },
2546   { "xlat",             { DSBX }, 0 },
2547   /* d8 */
2548   { FLOAT },
2549   { FLOAT },
2550   { FLOAT },
2551   { FLOAT },
2552   { FLOAT },
2553   { FLOAT },
2554   { FLOAT },
2555   { FLOAT },
2556   /* e0 */
2557   { "loopneFH",         { Jb, XX, loop_jcxz_flag }, 0 },
2558   { "loopeFH",          { Jb, XX, loop_jcxz_flag }, 0 },
2559   { "loopFH",           { Jb, XX, loop_jcxz_flag }, 0 },
2560   { "jEcxzH",           { Jb, XX, loop_jcxz_flag }, 0 },
2561   { "inB",              { AL, Ib }, 0 },
2562   { "inG",              { zAX, Ib }, 0 },
2563   { "outB",             { Ib, AL }, 0 },
2564   { "outG",             { Ib, zAX }, 0 },
2565   /* e8 */
2566   { X86_64_TABLE (X86_64_E8) },
2567   { X86_64_TABLE (X86_64_E9) },
2568   { X86_64_TABLE (X86_64_EA) },
2569   { "jmp",              { Jb, BND }, 0 },
2570   { "inB",              { AL, indirDX }, 0 },
2571   { "inG",              { zAX, indirDX }, 0 },
2572   { "outB",             { indirDX, AL }, 0 },
2573   { "outG",             { indirDX, zAX }, 0 },
2574   /* f0 */
2575   { Bad_Opcode },       /* lock prefix */
2576   { "icebp",            { XX }, 0 },
2577   { Bad_Opcode },       /* repne */
2578   { Bad_Opcode },       /* repz */
2579   { "hlt",              { XX }, 0 },
2580   { "cmc",              { XX }, 0 },
2581   { REG_TABLE (REG_F6) },
2582   { REG_TABLE (REG_F7) },
2583   /* f8 */
2584   { "clc",              { XX }, 0 },
2585   { "stc",              { XX }, 0 },
2586   { "cli",              { XX }, 0 },
2587   { "sti",              { XX }, 0 },
2588   { "cld",              { XX }, 0 },
2589   { "std",              { XX }, 0 },
2590   { REG_TABLE (REG_FE) },
2591   { REG_TABLE (REG_FF) },
2592 };
2593
2594 static const struct dis386 dis386_twobyte[] = {
2595   /* 00 */
2596   { REG_TABLE (REG_0F00 ) },
2597   { REG_TABLE (REG_0F01 ) },
2598   { "larS",             { Gv, Ew }, 0 },
2599   { "lslS",             { Gv, Ew }, 0 },
2600   { Bad_Opcode },
2601   { "syscall",          { XX }, 0 },
2602   { "clts",             { XX }, 0 },
2603   { "sysret%LQ",                { XX }, 0 },
2604   /* 08 */
2605   { "invd",             { XX }, 0 },
2606   { PREFIX_TABLE (PREFIX_0F09) },
2607   { Bad_Opcode },
2608   { "ud2",              { XX }, 0 },
2609   { Bad_Opcode },
2610   { REG_TABLE (REG_0F0D) },
2611   { "femms",            { XX }, 0 },
2612   { "",                 { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix.  */
2613   /* 10 */
2614   { PREFIX_TABLE (PREFIX_0F10) },
2615   { PREFIX_TABLE (PREFIX_0F11) },
2616   { PREFIX_TABLE (PREFIX_0F12) },
2617   { MOD_TABLE (MOD_0F13) },
2618   { "unpcklpX",         { XM, EXx }, PREFIX_OPCODE },
2619   { "unpckhpX",         { XM, EXx }, PREFIX_OPCODE },
2620   { PREFIX_TABLE (PREFIX_0F16) },
2621   { MOD_TABLE (MOD_0F17) },
2622   /* 18 */
2623   { REG_TABLE (REG_0F18) },
2624   { "nopQ",             { Ev }, 0 },
2625   { PREFIX_TABLE (PREFIX_0F1A) },
2626   { PREFIX_TABLE (PREFIX_0F1B) },
2627   { PREFIX_TABLE (PREFIX_0F1C) },
2628   { "nopQ",             { Ev }, 0 },
2629   { PREFIX_TABLE (PREFIX_0F1E) },
2630   { "nopQ",             { Ev }, 0 },
2631   /* 20 */
2632   { "movZ",             { Rm, Cm }, 0 },
2633   { "movZ",             { Rm, Dm }, 0 },
2634   { "movZ",             { Cm, Rm }, 0 },
2635   { "movZ",             { Dm, Rm }, 0 },
2636   { MOD_TABLE (MOD_0F24) },
2637   { Bad_Opcode },
2638   { MOD_TABLE (MOD_0F26) },
2639   { Bad_Opcode },
2640   /* 28 */
2641   { "movapX",           { XM, EXx }, PREFIX_OPCODE },
2642   { "movapX",           { EXxS, XM }, PREFIX_OPCODE },
2643   { PREFIX_TABLE (PREFIX_0F2A) },
2644   { PREFIX_TABLE (PREFIX_0F2B) },
2645   { PREFIX_TABLE (PREFIX_0F2C) },
2646   { PREFIX_TABLE (PREFIX_0F2D) },
2647   { PREFIX_TABLE (PREFIX_0F2E) },
2648   { PREFIX_TABLE (PREFIX_0F2F) },
2649   /* 30 */
2650   { "wrmsr",            { XX }, 0 },
2651   { "rdtsc",            { XX }, 0 },
2652   { "rdmsr",            { XX }, 0 },
2653   { "rdpmc",            { XX }, 0 },
2654   { "sysenter",         { SEP }, 0 },
2655   { "sysexit",          { SEP }, 0 },
2656   { Bad_Opcode },
2657   { "getsec",           { XX }, 0 },
2658   /* 38 */
2659   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) },
2660   { Bad_Opcode },
2661   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) },
2662   { Bad_Opcode },
2663   { Bad_Opcode },
2664   { Bad_Opcode },
2665   { Bad_Opcode },
2666   { Bad_Opcode },
2667   /* 40 */
2668   { "cmovoS",           { Gv, Ev }, 0 },
2669   { "cmovnoS",          { Gv, Ev }, 0 },
2670   { "cmovbS",           { Gv, Ev }, 0 },
2671   { "cmovaeS",          { Gv, Ev }, 0 },
2672   { "cmoveS",           { Gv, Ev }, 0 },
2673   { "cmovneS",          { Gv, Ev }, 0 },
2674   { "cmovbeS",          { Gv, Ev }, 0 },
2675   { "cmovaS",           { Gv, Ev }, 0 },
2676   /* 48 */
2677   { "cmovsS",           { Gv, Ev }, 0 },
2678   { "cmovnsS",          { Gv, Ev }, 0 },
2679   { "cmovpS",           { Gv, Ev }, 0 },
2680   { "cmovnpS",          { Gv, Ev }, 0 },
2681   { "cmovlS",           { Gv, Ev }, 0 },
2682   { "cmovgeS",          { Gv, Ev }, 0 },
2683   { "cmovleS",          { Gv, Ev }, 0 },
2684   { "cmovgS",           { Gv, Ev }, 0 },
2685   /* 50 */
2686   { MOD_TABLE (MOD_0F50) },
2687   { PREFIX_TABLE (PREFIX_0F51) },
2688   { PREFIX_TABLE (PREFIX_0F52) },
2689   { PREFIX_TABLE (PREFIX_0F53) },
2690   { "andpX",            { XM, EXx }, PREFIX_OPCODE },
2691   { "andnpX",           { XM, EXx }, PREFIX_OPCODE },
2692   { "orpX",             { XM, EXx }, PREFIX_OPCODE },
2693   { "xorpX",            { XM, EXx }, PREFIX_OPCODE },
2694   /* 58 */
2695   { PREFIX_TABLE (PREFIX_0F58) },
2696   { PREFIX_TABLE (PREFIX_0F59) },
2697   { PREFIX_TABLE (PREFIX_0F5A) },
2698   { PREFIX_TABLE (PREFIX_0F5B) },
2699   { PREFIX_TABLE (PREFIX_0F5C) },
2700   { PREFIX_TABLE (PREFIX_0F5D) },
2701   { PREFIX_TABLE (PREFIX_0F5E) },
2702   { PREFIX_TABLE (PREFIX_0F5F) },
2703   /* 60 */
2704   { PREFIX_TABLE (PREFIX_0F60) },
2705   { PREFIX_TABLE (PREFIX_0F61) },
2706   { PREFIX_TABLE (PREFIX_0F62) },
2707   { "packsswb",         { MX, EM }, PREFIX_OPCODE },
2708   { "pcmpgtb",          { MX, EM }, PREFIX_OPCODE },
2709   { "pcmpgtw",          { MX, EM }, PREFIX_OPCODE },
2710   { "pcmpgtd",          { MX, EM }, PREFIX_OPCODE },
2711   { "packuswb",         { MX, EM }, PREFIX_OPCODE },
2712   /* 68 */
2713   { "punpckhbw",        { MX, EM }, PREFIX_OPCODE },
2714   { "punpckhwd",        { MX, EM }, PREFIX_OPCODE },
2715   { "punpckhdq",        { MX, EM }, PREFIX_OPCODE },
2716   { "packssdw",         { MX, EM }, PREFIX_OPCODE },
2717   { PREFIX_TABLE (PREFIX_0F6C) },
2718   { PREFIX_TABLE (PREFIX_0F6D) },
2719   { "movK",             { MX, Edq }, PREFIX_OPCODE },
2720   { PREFIX_TABLE (PREFIX_0F6F) },
2721   /* 70 */
2722   { PREFIX_TABLE (PREFIX_0F70) },
2723   { REG_TABLE (REG_0F71) },
2724   { REG_TABLE (REG_0F72) },
2725   { REG_TABLE (REG_0F73) },
2726   { "pcmpeqb",          { MX, EM }, PREFIX_OPCODE },
2727   { "pcmpeqw",          { MX, EM }, PREFIX_OPCODE },
2728   { "pcmpeqd",          { MX, EM }, PREFIX_OPCODE },
2729   { "emms",             { XX }, PREFIX_OPCODE },
2730   /* 78 */
2731   { PREFIX_TABLE (PREFIX_0F78) },
2732   { PREFIX_TABLE (PREFIX_0F79) },
2733   { Bad_Opcode },
2734   { Bad_Opcode },
2735   { PREFIX_TABLE (PREFIX_0F7C) },
2736   { PREFIX_TABLE (PREFIX_0F7D) },
2737   { PREFIX_TABLE (PREFIX_0F7E) },
2738   { PREFIX_TABLE (PREFIX_0F7F) },
2739   /* 80 */
2740   { "joH",              { Jv, BND, cond_jump_flag }, 0 },
2741   { "jnoH",             { Jv, BND, cond_jump_flag }, 0 },
2742   { "jbH",              { Jv, BND, cond_jump_flag }, 0 },
2743   { "jaeH",             { Jv, BND, cond_jump_flag }, 0 },
2744   { "jeH",              { Jv, BND, cond_jump_flag }, 0 },
2745   { "jneH",             { Jv, BND, cond_jump_flag }, 0 },
2746   { "jbeH",             { Jv, BND, cond_jump_flag }, 0 },
2747   { "jaH",              { Jv, BND, cond_jump_flag }, 0 },
2748   /* 88 */
2749   { "jsH",              { Jv, BND, cond_jump_flag }, 0 },
2750   { "jnsH",             { Jv, BND, cond_jump_flag }, 0 },
2751   { "jpH",              { Jv, BND, cond_jump_flag }, 0 },
2752   { "jnpH",             { Jv, BND, cond_jump_flag }, 0 },
2753   { "jlH",              { Jv, BND, cond_jump_flag }, 0 },
2754   { "jgeH",             { Jv, BND, cond_jump_flag }, 0 },
2755   { "jleH",             { Jv, BND, cond_jump_flag }, 0 },
2756   { "jgH",              { Jv, BND, cond_jump_flag }, 0 },
2757   /* 90 */
2758   { "seto",             { Eb }, 0 },
2759   { "setno",            { Eb }, 0 },
2760   { "setb",             { Eb }, 0 },
2761   { "setae",            { Eb }, 0 },
2762   { "sete",             { Eb }, 0 },
2763   { "setne",            { Eb }, 0 },
2764   { "setbe",            { Eb }, 0 },
2765   { "seta",             { Eb }, 0 },
2766   /* 98 */
2767   { "sets",             { Eb }, 0 },
2768   { "setns",            { Eb }, 0 },
2769   { "setp",             { Eb }, 0 },
2770   { "setnp",            { Eb }, 0 },
2771   { "setl",             { Eb }, 0 },
2772   { "setge",            { Eb }, 0 },
2773   { "setle",            { Eb }, 0 },
2774   { "setg",             { Eb }, 0 },
2775   /* a0 */
2776   { "pushT",            { fs }, 0 },
2777   { "popT",             { fs }, 0 },
2778   { "cpuid",            { XX }, 0 },
2779   { "btS",              { Ev, Gv }, 0 },
2780   { "shldS",            { Ev, Gv, Ib }, 0 },
2781   { "shldS",            { Ev, Gv, CL }, 0 },
2782   { REG_TABLE (REG_0FA6) },
2783   { REG_TABLE (REG_0FA7) },
2784   /* a8 */
2785   { "pushT",            { gs }, 0 },
2786   { "popT",             { gs }, 0 },
2787   { "rsm",              { XX }, 0 },
2788   { "btsS",             { Evh1, Gv }, 0 },
2789   { "shrdS",            { Ev, Gv, Ib }, 0 },
2790   { "shrdS",            { Ev, Gv, CL }, 0 },
2791   { REG_TABLE (REG_0FAE) },
2792   { "imulS",            { Gv, Ev }, 0 },
2793   /* b0 */
2794   { "cmpxchgB",         { Ebh1, Gb }, 0 },
2795   { "cmpxchgS",         { Evh1, Gv }, 0 },
2796   { MOD_TABLE (MOD_0FB2) },
2797   { "btrS",             { Evh1, Gv }, 0 },
2798   { MOD_TABLE (MOD_0FB4) },
2799   { MOD_TABLE (MOD_0FB5) },
2800   { "movz{bR|x}",       { Gv, Eb }, 0 },
2801   { "movz{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movzww ! */
2802   /* b8 */
2803   { PREFIX_TABLE (PREFIX_0FB8) },
2804   { "ud1S",             { Gv, Ev }, 0 },
2805   { REG_TABLE (REG_0FBA) },
2806   { "btcS",             { Evh1, Gv }, 0 },
2807   { PREFIX_TABLE (PREFIX_0FBC) },
2808   { PREFIX_TABLE (PREFIX_0FBD) },
2809   { "movs{bR|x}",       { Gv, Eb }, 0 },
2810   { "movs{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movsww ! */
2811   /* c0 */
2812   { "xaddB",            { Ebh1, Gb }, 0 },
2813   { "xaddS",            { Evh1, Gv }, 0 },
2814   { PREFIX_TABLE (PREFIX_0FC2) },
2815   { MOD_TABLE (MOD_0FC3) },
2816   { "pinsrw",           { MX, Edqw, Ib }, PREFIX_OPCODE },
2817   { "pextrw",           { Gdq, MS, Ib }, PREFIX_OPCODE },
2818   { "shufpX",           { XM, EXx, Ib }, PREFIX_OPCODE },
2819   { REG_TABLE (REG_0FC7) },
2820   /* c8 */
2821   { "bswap",            { RMeAX }, 0 },
2822   { "bswap",            { RMeCX }, 0 },
2823   { "bswap",            { RMeDX }, 0 },
2824   { "bswap",            { RMeBX }, 0 },
2825   { "bswap",            { RMeSP }, 0 },
2826   { "bswap",            { RMeBP }, 0 },
2827   { "bswap",            { RMeSI }, 0 },
2828   { "bswap",            { RMeDI }, 0 },
2829   /* d0 */
2830   { PREFIX_TABLE (PREFIX_0FD0) },
2831   { "psrlw",            { MX, EM }, PREFIX_OPCODE },
2832   { "psrld",            { MX, EM }, PREFIX_OPCODE },
2833   { "psrlq",            { MX, EM }, PREFIX_OPCODE },
2834   { "paddq",            { MX, EM }, PREFIX_OPCODE },
2835   { "pmullw",           { MX, EM }, PREFIX_OPCODE },
2836   { PREFIX_TABLE (PREFIX_0FD6) },
2837   { MOD_TABLE (MOD_0FD7) },
2838   /* d8 */
2839   { "psubusb",          { MX, EM }, PREFIX_OPCODE },
2840   { "psubusw",          { MX, EM }, PREFIX_OPCODE },
2841   { "pminub",           { MX, EM }, PREFIX_OPCODE },
2842   { "pand",             { MX, EM }, PREFIX_OPCODE },
2843   { "paddusb",          { MX, EM }, PREFIX_OPCODE },
2844   { "paddusw",          { MX, EM }, PREFIX_OPCODE },
2845   { "pmaxub",           { MX, EM }, PREFIX_OPCODE },
2846   { "pandn",            { MX, EM }, PREFIX_OPCODE },
2847   /* e0 */
2848   { "pavgb",            { MX, EM }, PREFIX_OPCODE },
2849   { "psraw",            { MX, EM }, PREFIX_OPCODE },
2850   { "psrad",            { MX, EM }, PREFIX_OPCODE },
2851   { "pavgw",            { MX, EM }, PREFIX_OPCODE },
2852   { "pmulhuw",          { MX, EM }, PREFIX_OPCODE },
2853   { "pmulhw",           { MX, EM }, PREFIX_OPCODE },
2854   { PREFIX_TABLE (PREFIX_0FE6) },
2855   { PREFIX_TABLE (PREFIX_0FE7) },
2856   /* e8 */
2857   { "psubsb",           { MX, EM }, PREFIX_OPCODE },
2858   { "psubsw",           { MX, EM }, PREFIX_OPCODE },
2859   { "pminsw",           { MX, EM }, PREFIX_OPCODE },
2860   { "por",              { MX, EM }, PREFIX_OPCODE },
2861   { "paddsb",           { MX, EM }, PREFIX_OPCODE },
2862   { "paddsw",           { MX, EM }, PREFIX_OPCODE },
2863   { "pmaxsw",           { MX, EM }, PREFIX_OPCODE },
2864   { "pxor",             { MX, EM }, PREFIX_OPCODE },
2865   /* f0 */
2866   { PREFIX_TABLE (PREFIX_0FF0) },
2867   { "psllw",            { MX, EM }, PREFIX_OPCODE },
2868   { "pslld",            { MX, EM }, PREFIX_OPCODE },
2869   { "psllq",            { MX, EM }, PREFIX_OPCODE },
2870   { "pmuludq",          { MX, EM }, PREFIX_OPCODE },
2871   { "pmaddwd",          { MX, EM }, PREFIX_OPCODE },
2872   { "psadbw",           { MX, EM }, PREFIX_OPCODE },
2873   { PREFIX_TABLE (PREFIX_0FF7) },
2874   /* f8 */
2875   { "psubb",            { MX, EM }, PREFIX_OPCODE },
2876   { "psubw",            { MX, EM }, PREFIX_OPCODE },
2877   { "psubd",            { MX, EM }, PREFIX_OPCODE },
2878   { "psubq",            { MX, EM }, PREFIX_OPCODE },
2879   { "paddb",            { MX, EM }, PREFIX_OPCODE },
2880   { "paddw",            { MX, EM }, PREFIX_OPCODE },
2881   { "paddd",            { MX, EM }, PREFIX_OPCODE },
2882   { "ud0S",             { Gv, Ev }, 0 },
2883 };
2884
2885 static const unsigned char onebyte_has_modrm[256] = {
2886   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2887   /*       -------------------------------        */
2888   /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2889   /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2890   /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2891   /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2892   /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2893   /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2894   /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2895   /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2896   /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2897   /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2898   /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2899   /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2900   /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2901   /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2902   /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2903   /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1  /* f0 */
2904   /*       -------------------------------        */
2905   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2906 };
2907
2908 static const unsigned char twobyte_has_modrm[256] = {
2909   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2910   /*       -------------------------------        */
2911   /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2912   /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2913   /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2914   /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2915   /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2916   /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2917   /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2918   /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2919   /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2920   /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2921   /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2922   /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */
2923   /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2924   /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2925   /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2926   /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1  /* ff */
2927   /*       -------------------------------        */
2928   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2929 };
2930
2931 static char obuf[100];
2932 static char *obufp;
2933 static char *mnemonicendp;
2934 static char scratchbuf[100];
2935 static unsigned char *start_codep;
2936 static unsigned char *insn_codep;
2937 static unsigned char *codep;
2938 static unsigned char *end_codep;
2939 static int last_lock_prefix;
2940 static int last_repz_prefix;
2941 static int last_repnz_prefix;
2942 static int last_data_prefix;
2943 static int last_addr_prefix;
2944 static int last_rex_prefix;
2945 static int last_seg_prefix;
2946 static int fwait_prefix;
2947 /* The active segment register prefix.  */
2948 static int active_seg_prefix;
2949 #define MAX_CODE_LENGTH 15
2950 /* We can up to 14 prefixes since the maximum instruction length is
2951    15bytes.  */
2952 static int all_prefixes[MAX_CODE_LENGTH - 1];
2953 static disassemble_info *the_info;
2954 static struct
2955   {
2956     int mod;
2957     int reg;
2958     int rm;
2959   }
2960 modrm;
2961 static unsigned char need_modrm;
2962 static struct
2963   {
2964     int scale;
2965     int index;
2966     int base;
2967   }
2968 sib;
2969 static struct
2970   {
2971     int register_specifier;
2972     int length;
2973     int prefix;
2974     int w;
2975     int evex;
2976     int r;
2977     int v;
2978     int mask_register_specifier;
2979     int zeroing;
2980     int ll;
2981     int b;
2982   }
2983 vex;
2984 static unsigned char need_vex;
2985 static unsigned char need_vex_reg;
2986 static unsigned char vex_w_done;
2987
2988 struct op
2989   {
2990     const char *name;
2991     unsigned int len;
2992   };
2993
2994 /* If we are accessing mod/rm/reg without need_modrm set, then the
2995    values are stale.  Hitting this abort likely indicates that you
2996    need to update onebyte_has_modrm or twobyte_has_modrm.  */
2997 #define MODRM_CHECK  if (!need_modrm) abort ()
2998
2999 static const char **names64;
3000 static const char **names32;
3001 static const char **names16;
3002 static const char **names8;
3003 static const char **names8rex;
3004 static const char **names_seg;
3005 static const char *index64;
3006 static const char *index32;
3007 static const char **index16;
3008 static const char **names_bnd;
3009
3010 static const char *intel_names64[] = {
3011   "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
3012   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3013 };
3014 static const char *intel_names32[] = {
3015   "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
3016   "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
3017 };
3018 static const char *intel_names16[] = {
3019   "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
3020   "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
3021 };
3022 static const char *intel_names8[] = {
3023   "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
3024 };
3025 static const char *intel_names8rex[] = {
3026   "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
3027   "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
3028 };
3029 static const char *intel_names_seg[] = {
3030   "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
3031 };
3032 static const char *intel_index64 = "riz";
3033 static const char *intel_index32 = "eiz";
3034 static const char *intel_index16[] = {
3035   "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
3036 };
3037
3038 static const char *att_names64[] = {
3039   "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
3040   "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
3041 };
3042 static const char *att_names32[] = {
3043   "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
3044   "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
3045 };
3046 static const char *att_names16[] = {
3047   "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
3048   "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
3049 };
3050 static const char *att_names8[] = {
3051   "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
3052 };
3053 static const char *att_names8rex[] = {
3054   "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
3055   "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
3056 };
3057 static const char *att_names_seg[] = {
3058   "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
3059 };
3060 static const char *att_index64 = "%riz";
3061 static const char *att_index32 = "%eiz";
3062 static const char *att_index16[] = {
3063   "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
3064 };
3065
3066 static const char **names_mm;
3067 static const char *intel_names_mm[] = {
3068   "mm0", "mm1", "mm2", "mm3",
3069   "mm4", "mm5", "mm6", "mm7"
3070 };
3071 static const char *att_names_mm[] = {
3072   "%mm0", "%mm1", "%mm2", "%mm3",
3073   "%mm4", "%mm5", "%mm6", "%mm7"
3074 };
3075
3076 static const char *intel_names_bnd[] = {
3077   "bnd0", "bnd1", "bnd2", "bnd3"
3078 };
3079
3080 static const char *att_names_bnd[] = {
3081   "%bnd0", "%bnd1", "%bnd2", "%bnd3"
3082 };
3083
3084 static const char **names_xmm;
3085 static const char *intel_names_xmm[] = {
3086   "xmm0", "xmm1", "xmm2", "xmm3",
3087   "xmm4", "xmm5", "xmm6", "xmm7",
3088   "xmm8", "xmm9", "xmm10", "xmm11",
3089   "xmm12", "xmm13", "xmm14", "xmm15",
3090   "xmm16", "xmm17", "xmm18", "xmm19",
3091   "xmm20", "xmm21", "xmm22", "xmm23",
3092   "xmm24", "xmm25", "xmm26", "xmm27",
3093   "xmm28", "xmm29", "xmm30", "xmm31"
3094 };
3095 static const char *att_names_xmm[] = {
3096   "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3097   "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3098   "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3099   "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3100   "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3101   "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3102   "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3103   "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3104 };
3105
3106 static const char **names_ymm;
3107 static const char *intel_names_ymm[] = {
3108   "ymm0", "ymm1", "ymm2", "ymm3",
3109   "ymm4", "ymm5", "ymm6", "ymm7",
3110   "ymm8", "ymm9", "ymm10", "ymm11",
3111   "ymm12", "ymm13", "ymm14", "ymm15",
3112   "ymm16", "ymm17", "ymm18", "ymm19",
3113   "ymm20", "ymm21", "ymm22", "ymm23",
3114   "ymm24", "ymm25", "ymm26", "ymm27",
3115   "ymm28", "ymm29", "ymm30", "ymm31"
3116 };
3117 static const char *att_names_ymm[] = {
3118   "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3119   "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3120   "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3121   "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3122   "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3123   "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3124   "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3125   "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3126 };
3127
3128 static const char **names_zmm;
3129 static const char *intel_names_zmm[] = {
3130   "zmm0", "zmm1", "zmm2", "zmm3",
3131   "zmm4", "zmm5", "zmm6", "zmm7",
3132   "zmm8", "zmm9", "zmm10", "zmm11",
3133   "zmm12", "zmm13", "zmm14", "zmm15",
3134   "zmm16", "zmm17", "zmm18", "zmm19",
3135   "zmm20", "zmm21", "zmm22", "zmm23",
3136   "zmm24", "zmm25", "zmm26", "zmm27",
3137   "zmm28", "zmm29", "zmm30", "zmm31"
3138 };
3139 static const char *att_names_zmm[] = {
3140   "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3141   "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3142   "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3143   "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3144   "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3145   "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3146   "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3147   "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3148 };
3149
3150 static const char **names_mask;
3151 static const char *intel_names_mask[] = {
3152   "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3153 };
3154 static const char *att_names_mask[] = {
3155   "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3156 };
3157
3158 static const char *names_rounding[] =
3159 {
3160   "{rn-sae}",
3161   "{rd-sae}",
3162   "{ru-sae}",
3163   "{rz-sae}"
3164 };
3165
3166 static const struct dis386 reg_table[][8] = {
3167   /* REG_80 */
3168   {
3169     { "addA",   { Ebh1, Ib }, 0 },
3170     { "orA",    { Ebh1, Ib }, 0 },
3171     { "adcA",   { Ebh1, Ib }, 0 },
3172     { "sbbA",   { Ebh1, Ib }, 0 },
3173     { "andA",   { Ebh1, Ib }, 0 },
3174     { "subA",   { Ebh1, Ib }, 0 },
3175     { "xorA",   { Ebh1, Ib }, 0 },
3176     { "cmpA",   { Eb, Ib }, 0 },
3177   },
3178   /* REG_81 */
3179   {
3180     { "addQ",   { Evh1, Iv }, 0 },
3181     { "orQ",    { Evh1, Iv }, 0 },
3182     { "adcQ",   { Evh1, Iv }, 0 },
3183     { "sbbQ",   { Evh1, Iv }, 0 },
3184     { "andQ",   { Evh1, Iv }, 0 },
3185     { "subQ",   { Evh1, Iv }, 0 },
3186     { "xorQ",   { Evh1, Iv }, 0 },
3187     { "cmpQ",   { Ev, Iv }, 0 },
3188   },
3189   /* REG_83 */
3190   {
3191     { "addQ",   { Evh1, sIb }, 0 },
3192     { "orQ",    { Evh1, sIb }, 0 },
3193     { "adcQ",   { Evh1, sIb }, 0 },
3194     { "sbbQ",   { Evh1, sIb }, 0 },
3195     { "andQ",   { Evh1, sIb }, 0 },
3196     { "subQ",   { Evh1, sIb }, 0 },
3197     { "xorQ",   { Evh1, sIb }, 0 },
3198     { "cmpQ",   { Ev, sIb }, 0 },
3199   },
3200   /* REG_8F */
3201   {
3202     { "popU",   { stackEv }, 0 },
3203     { XOP_8F_TABLE (XOP_09) },
3204     { Bad_Opcode },
3205     { Bad_Opcode },
3206     { Bad_Opcode },
3207     { XOP_8F_TABLE (XOP_09) },
3208   },
3209   /* REG_C0 */
3210   {
3211     { "rolA",   { Eb, Ib }, 0 },
3212     { "rorA",   { Eb, Ib }, 0 },
3213     { "rclA",   { Eb, Ib }, 0 },
3214     { "rcrA",   { Eb, Ib }, 0 },
3215     { "shlA",   { Eb, Ib }, 0 },
3216     { "shrA",   { Eb, Ib }, 0 },
3217     { "shlA",   { Eb, Ib }, 0 },
3218     { "sarA",   { Eb, Ib }, 0 },
3219   },
3220   /* REG_C1 */
3221   {
3222     { "rolQ",   { Ev, Ib }, 0 },
3223     { "rorQ",   { Ev, Ib }, 0 },
3224     { "rclQ",   { Ev, Ib }, 0 },
3225     { "rcrQ",   { Ev, Ib }, 0 },
3226     { "shlQ",   { Ev, Ib }, 0 },
3227     { "shrQ",   { Ev, Ib }, 0 },
3228     { "shlQ",   { Ev, Ib }, 0 },
3229     { "sarQ",   { Ev, Ib }, 0 },
3230   },
3231   /* REG_C6 */
3232   {
3233     { "movA",   { Ebh3, Ib }, 0 },
3234     { Bad_Opcode },
3235     { Bad_Opcode },
3236     { Bad_Opcode },
3237     { Bad_Opcode },
3238     { Bad_Opcode },
3239     { Bad_Opcode },
3240     { MOD_TABLE (MOD_C6_REG_7) },
3241   },
3242   /* REG_C7 */
3243   {
3244     { "movQ",   { Evh3, Iv }, 0 },
3245     { Bad_Opcode },
3246     { Bad_Opcode },
3247     { Bad_Opcode },
3248     { Bad_Opcode },
3249     { Bad_Opcode },
3250     { Bad_Opcode },
3251     { MOD_TABLE (MOD_C7_REG_7) },
3252   },
3253   /* REG_D0 */
3254   {
3255     { "rolA",   { Eb, I1 }, 0 },
3256     { "rorA",   { Eb, I1 }, 0 },
3257     { "rclA",   { Eb, I1 }, 0 },
3258     { "rcrA",   { Eb, I1 }, 0 },
3259     { "shlA",   { Eb, I1 }, 0 },
3260     { "shrA",   { Eb, I1 }, 0 },
3261     { "shlA",   { Eb, I1 }, 0 },
3262     { "sarA",   { Eb, I1 }, 0 },
3263   },
3264   /* REG_D1 */
3265   {
3266     { "rolQ",   { Ev, I1 }, 0 },
3267     { "rorQ",   { Ev, I1 }, 0 },
3268     { "rclQ",   { Ev, I1 }, 0 },
3269     { "rcrQ",   { Ev, I1 }, 0 },
3270     { "shlQ",   { Ev, I1 }, 0 },
3271     { "shrQ",   { Ev, I1 }, 0 },
3272     { "shlQ",   { Ev, I1 }, 0 },
3273     { "sarQ",   { Ev, I1 }, 0 },
3274   },
3275   /* REG_D2 */
3276   {
3277     { "rolA",   { Eb, CL }, 0 },
3278     { "rorA",   { Eb, CL }, 0 },
3279     { "rclA",   { Eb, CL }, 0 },
3280     { "rcrA",   { Eb, CL }, 0 },
3281     { "shlA",   { Eb, CL }, 0 },
3282     { "shrA",   { Eb, CL }, 0 },
3283     { "shlA",   { Eb, CL }, 0 },
3284     { "sarA",   { Eb, CL }, 0 },
3285   },
3286   /* REG_D3 */
3287   {
3288     { "rolQ",   { Ev, CL }, 0 },
3289     { "rorQ",   { Ev, CL }, 0 },
3290     { "rclQ",   { Ev, CL }, 0 },
3291     { "rcrQ",   { Ev, CL }, 0 },
3292     { "shlQ",   { Ev, CL }, 0 },
3293     { "shrQ",   { Ev, CL }, 0 },
3294     { "shlQ",   { Ev, CL }, 0 },
3295     { "sarQ",   { Ev, CL }, 0 },
3296   },
3297   /* REG_F6 */
3298   {
3299     { "testA",  { Eb, Ib }, 0 },
3300     { "testA",  { Eb, Ib }, 0 },
3301     { "notA",   { Ebh1 }, 0 },
3302     { "negA",   { Ebh1 }, 0 },
3303     { "mulA",   { Eb }, 0 },    /* Don't print the implicit %al register,  */
3304     { "imulA",  { Eb }, 0 },    /* to distinguish these opcodes from other */
3305     { "divA",   { Eb }, 0 },    /* mul/imul opcodes.  Do the same for div  */
3306     { "idivA",  { Eb }, 0 },    /* and idiv for consistency.               */
3307   },
3308   /* REG_F7 */
3309   {
3310     { "testQ",  { Ev, Iv }, 0 },
3311     { "testQ",  { Ev, Iv }, 0 },
3312     { "notQ",   { Evh1 }, 0 },
3313     { "negQ",   { Evh1 }, 0 },
3314     { "mulQ",   { Ev }, 0 },    /* Don't print the implicit register.  */
3315     { "imulQ",  { Ev }, 0 },
3316     { "divQ",   { Ev }, 0 },
3317     { "idivQ",  { Ev }, 0 },
3318   },
3319   /* REG_FE */
3320   {
3321     { "incA",   { Ebh1 }, 0 },
3322     { "decA",   { Ebh1 }, 0 },
3323   },
3324   /* REG_FF */
3325   {
3326     { "incQ",   { Evh1 }, 0 },
3327     { "decQ",   { Evh1 }, 0 },
3328     { "call{&|}", { NOTRACK, indirEv, BND }, 0 },
3329     { MOD_TABLE (MOD_FF_REG_3) },
3330     { "jmp{&|}", { NOTRACK, indirEv, BND }, 0 },
3331     { MOD_TABLE (MOD_FF_REG_5) },
3332     { "pushU",  { stackEv }, 0 },
3333     { Bad_Opcode },
3334   },
3335   /* REG_0F00 */
3336   {
3337     { "sldtD",  { Sv }, 0 },
3338     { "strD",   { Sv }, 0 },
3339     { "lldt",   { Ew }, 0 },
3340     { "ltr",    { Ew }, 0 },
3341     { "verr",   { Ew }, 0 },
3342     { "verw",   { Ew }, 0 },
3343     { Bad_Opcode },
3344     { Bad_Opcode },
3345   },
3346   /* REG_0F01 */
3347   {
3348     { MOD_TABLE (MOD_0F01_REG_0) },
3349     { MOD_TABLE (MOD_0F01_REG_1) },
3350     { MOD_TABLE (MOD_0F01_REG_2) },
3351     { MOD_TABLE (MOD_0F01_REG_3) },
3352     { "smswD",  { Sv }, 0 },
3353     { MOD_TABLE (MOD_0F01_REG_5) },
3354     { "lmsw",   { Ew }, 0 },
3355     { MOD_TABLE (MOD_0F01_REG_7) },
3356   },
3357   /* REG_0F0D */
3358   {
3359     { "prefetch",       { Mb }, 0 },
3360     { "prefetchw",      { Mb }, 0 },
3361     { "prefetchwt1",    { Mb }, 0 },
3362     { "prefetch",       { Mb }, 0 },
3363     { "prefetch",       { Mb }, 0 },
3364     { "prefetch",       { Mb }, 0 },
3365     { "prefetch",       { Mb }, 0 },
3366     { "prefetch",       { Mb }, 0 },
3367   },
3368   /* REG_0F18 */
3369   {
3370     { MOD_TABLE (MOD_0F18_REG_0) },
3371     { MOD_TABLE (MOD_0F18_REG_1) },
3372     { MOD_TABLE (MOD_0F18_REG_2) },
3373     { MOD_TABLE (MOD_0F18_REG_3) },
3374     { MOD_TABLE (MOD_0F18_REG_4) },
3375     { MOD_TABLE (MOD_0F18_REG_5) },
3376     { MOD_TABLE (MOD_0F18_REG_6) },
3377     { MOD_TABLE (MOD_0F18_REG_7) },
3378   },
3379   /* REG_0F1C_P_0_MOD_0 */
3380   {
3381     { "cldemote",       { Mb }, 0 },
3382     { "nopQ",           { Ev }, 0 },
3383     { "nopQ",           { Ev }, 0 },
3384     { "nopQ",           { Ev }, 0 },
3385     { "nopQ",           { Ev }, 0 },
3386     { "nopQ",           { Ev }, 0 },
3387     { "nopQ",           { Ev }, 0 },
3388     { "nopQ",           { Ev }, 0 },
3389   },
3390   /* REG_0F1E_P_1_MOD_3 */
3391   {
3392     { "nopQ",           { Ev }, 0 },
3393     { "rdsspK",         { Rdq }, PREFIX_OPCODE },
3394     { "nopQ",           { Ev }, 0 },
3395     { "nopQ",           { Ev }, 0 },
3396     { "nopQ",           { Ev }, 0 },
3397     { "nopQ",           { Ev }, 0 },
3398     { "nopQ",           { Ev }, 0 },
3399     { RM_TABLE (RM_0F1E_P_1_MOD_3_REG_7) },
3400   },
3401   /* REG_0F71 */
3402   {
3403     { Bad_Opcode },
3404     { Bad_Opcode },
3405     { MOD_TABLE (MOD_0F71_REG_2) },
3406     { Bad_Opcode },
3407     { MOD_TABLE (MOD_0F71_REG_4) },
3408     { Bad_Opcode },
3409     { MOD_TABLE (MOD_0F71_REG_6) },
3410   },
3411   /* REG_0F72 */
3412   {
3413     { Bad_Opcode },
3414     { Bad_Opcode },
3415     { MOD_TABLE (MOD_0F72_REG_2) },
3416     { Bad_Opcode },
3417     { MOD_TABLE (MOD_0F72_REG_4) },
3418     { Bad_Opcode },
3419     { MOD_TABLE (MOD_0F72_REG_6) },
3420   },
3421   /* REG_0F73 */
3422   {
3423     { Bad_Opcode },
3424     { Bad_Opcode },
3425     { MOD_TABLE (MOD_0F73_REG_2) },
3426     { MOD_TABLE (MOD_0F73_REG_3) },
3427     { Bad_Opcode },
3428     { Bad_Opcode },
3429     { MOD_TABLE (MOD_0F73_REG_6) },
3430     { MOD_TABLE (MOD_0F73_REG_7) },
3431   },
3432   /* REG_0FA6 */
3433   {
3434     { "montmul",        { { OP_0f07, 0 } }, 0 },
3435     { "xsha1",          { { OP_0f07, 0 } }, 0 },
3436     { "xsha256",        { { OP_0f07, 0 } }, 0 },
3437   },
3438   /* REG_0FA7 */
3439   {
3440     { "xstore-rng",     { { OP_0f07, 0 } }, 0 },
3441     { "xcrypt-ecb",     { { OP_0f07, 0 } }, 0 },
3442     { "xcrypt-cbc",     { { OP_0f07, 0 } }, 0 },
3443     { "xcrypt-ctr",     { { OP_0f07, 0 } }, 0 },
3444     { "xcrypt-cfb",     { { OP_0f07, 0 } }, 0 },
3445     { "xcrypt-ofb",     { { OP_0f07, 0 } }, 0 },
3446   },
3447   /* REG_0FAE */
3448   {
3449     { MOD_TABLE (MOD_0FAE_REG_0) },
3450     { MOD_TABLE (MOD_0FAE_REG_1) },
3451     { MOD_TABLE (MOD_0FAE_REG_2) },
3452     { MOD_TABLE (MOD_0FAE_REG_3) },
3453     { MOD_TABLE (MOD_0FAE_REG_4) },
3454     { MOD_TABLE (MOD_0FAE_REG_5) },
3455     { MOD_TABLE (MOD_0FAE_REG_6) },
3456     { MOD_TABLE (MOD_0FAE_REG_7) },
3457   },
3458   /* REG_0FBA */
3459   {
3460     { Bad_Opcode },
3461     { Bad_Opcode },
3462     { Bad_Opcode },
3463     { Bad_Opcode },
3464     { "btQ",    { Ev, Ib }, 0 },
3465     { "btsQ",   { Evh1, Ib }, 0 },
3466     { "btrQ",   { Evh1, Ib }, 0 },
3467     { "btcQ",   { Evh1, Ib }, 0 },
3468   },
3469   /* REG_0FC7 */
3470   {
3471     { Bad_Opcode },
3472     { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 },
3473     { Bad_Opcode },
3474     { MOD_TABLE (MOD_0FC7_REG_3) },
3475     { MOD_TABLE (MOD_0FC7_REG_4) },
3476     { MOD_TABLE (MOD_0FC7_REG_5) },
3477     { MOD_TABLE (MOD_0FC7_REG_6) },
3478     { MOD_TABLE (MOD_0FC7_REG_7) },
3479   },
3480   /* REG_VEX_0F71 */
3481   {
3482     { Bad_Opcode },
3483     { Bad_Opcode },
3484     { MOD_TABLE (MOD_VEX_0F71_REG_2) },
3485     { Bad_Opcode },
3486     { MOD_TABLE (MOD_VEX_0F71_REG_4) },
3487     { Bad_Opcode },
3488     { MOD_TABLE (MOD_VEX_0F71_REG_6) },
3489   },
3490   /* REG_VEX_0F72 */
3491   {
3492     { Bad_Opcode },
3493     { Bad_Opcode },
3494     { MOD_TABLE (MOD_VEX_0F72_REG_2) },
3495     { Bad_Opcode },
3496     { MOD_TABLE (MOD_VEX_0F72_REG_4) },
3497     { Bad_Opcode },
3498     { MOD_TABLE (MOD_VEX_0F72_REG_6) },
3499   },
3500   /* REG_VEX_0F73 */
3501   {
3502     { Bad_Opcode },
3503     { Bad_Opcode },
3504     { MOD_TABLE (MOD_VEX_0F73_REG_2) },
3505     { MOD_TABLE (MOD_VEX_0F73_REG_3) },
3506     { Bad_Opcode },
3507     { Bad_Opcode },
3508     { MOD_TABLE (MOD_VEX_0F73_REG_6) },
3509     { MOD_TABLE (MOD_VEX_0F73_REG_7) },
3510   },
3511   /* REG_VEX_0FAE */
3512   {
3513     { Bad_Opcode },
3514     { Bad_Opcode },
3515     { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
3516     { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
3517   },
3518   /* REG_VEX_0F38F3 */
3519   {
3520     { Bad_Opcode },
3521     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) },
3522     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) },
3523     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) },
3524   },
3525   /* REG_XOP_LWPCB */
3526   {
3527     { "llwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3528     { "slwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3529   },
3530   /* REG_XOP_LWP */
3531   {
3532     { "lwpins", { { OP_LWP_E, 0 }, Ed, Id }, 0 },
3533     { "lwpval", { { OP_LWP_E, 0 }, Ed, Id }, 0 },
3534   },
3535   /* REG_XOP_TBM_01 */
3536   {
3537     { Bad_Opcode },
3538     { "blcfill",        { { OP_LWP_E, 0 }, Edq }, 0 },
3539     { "blsfill",        { { OP_LWP_E, 0 }, Edq }, 0 },
3540     { "blcs",   { { OP_LWP_E, 0 }, Edq }, 0 },
3541     { "tzmsk",  { { OP_LWP_E, 0 }, Edq }, 0 },
3542     { "blcic",  { { OP_LWP_E, 0 }, Edq }, 0 },
3543     { "blsic",  { { OP_LWP_E, 0 }, Edq }, 0 },
3544     { "t1mskc", { { OP_LWP_E, 0 }, Edq }, 0 },
3545   },
3546   /* REG_XOP_TBM_02 */
3547   {
3548     { Bad_Opcode },
3549     { "blcmsk", { { OP_LWP_E, 0 }, Edq }, 0 },
3550     { Bad_Opcode },
3551     { Bad_Opcode },
3552     { Bad_Opcode },
3553     { Bad_Opcode },
3554     { "blci",   { { OP_LWP_E, 0 }, Edq }, 0 },
3555   },
3556
3557 #include "i386-dis-evex-reg.h"
3558 };
3559
3560 static const struct dis386 prefix_table[][4] = {
3561   /* PREFIX_90 */
3562   {
3563     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3564     { "pause", { XX }, 0 },
3565     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3566     { NULL, { { NULL, 0 } }, PREFIX_IGNORED }
3567   },
3568
3569   /* PREFIX_0F01_REG_3_RM_1 */
3570   {
3571     { "vmmcall",        { Skip_MODRM }, 0 },
3572     { "vmgexit",        { Skip_MODRM }, 0 },
3573     { Bad_Opcode },
3574     { "vmgexit",        { Skip_MODRM }, 0 },
3575   },
3576
3577   /* PREFIX_0F01_REG_5_MOD_0 */
3578   {
3579     { Bad_Opcode },
3580     { "rstorssp",       { Mq }, PREFIX_OPCODE },
3581   },
3582
3583   /* PREFIX_0F01_REG_5_MOD_3_RM_0 */
3584   {
3585     { "serialize",      { Skip_MODRM }, PREFIX_OPCODE },
3586     { "setssbsy",       { Skip_MODRM }, PREFIX_OPCODE },
3587     { Bad_Opcode },
3588     { "xsusldtrk",      { Skip_MODRM }, PREFIX_OPCODE },
3589   },
3590
3591   /* PREFIX_0F01_REG_5_MOD_3_RM_1 */
3592   {
3593     { Bad_Opcode },
3594     { Bad_Opcode },
3595     { Bad_Opcode },
3596     { "xresldtrk",     { Skip_MODRM }, PREFIX_OPCODE },
3597   },
3598
3599   /* PREFIX_0F01_REG_5_MOD_3_RM_2 */
3600   {
3601     { Bad_Opcode },
3602     { "saveprevssp",    { Skip_MODRM }, PREFIX_OPCODE },
3603   },
3604
3605   /* PREFIX_0F01_REG_7_MOD_3_RM_2 */
3606   {
3607     { "monitorx",       { { OP_Monitor, 0 } }, 0  },
3608     { "mcommit",        { Skip_MODRM }, 0 },
3609   },
3610
3611   /* PREFIX_0F01_REG_7_MOD_3_RM_3 */
3612   {
3613     { "mwaitx",         { { OP_Mwait, eBX_reg } }, 0  },
3614   },
3615
3616   /* PREFIX_0F09 */
3617   {
3618     { "wbinvd",   { XX }, 0 },
3619     { "wbnoinvd", { XX }, 0 },
3620   },
3621
3622   /* PREFIX_0F10 */
3623   {
3624     { "movups", { XM, EXx }, PREFIX_OPCODE },
3625     { "movss",  { XM, EXd }, PREFIX_OPCODE },
3626     { "movupd", { XM, EXx }, PREFIX_OPCODE },
3627     { "movsd",  { XM, EXq }, PREFIX_OPCODE },
3628   },
3629
3630   /* PREFIX_0F11 */
3631   {
3632     { "movups", { EXxS, XM }, PREFIX_OPCODE },
3633     { "movss",  { EXdS, XM }, PREFIX_OPCODE },
3634     { "movupd", { EXxS, XM }, PREFIX_OPCODE },
3635     { "movsd",  { EXqS, XM }, PREFIX_OPCODE },
3636   },
3637
3638   /* PREFIX_0F12 */
3639   {
3640     { MOD_TABLE (MOD_0F12_PREFIX_0) },
3641     { "movsldup", { XM, EXx }, PREFIX_OPCODE },
3642     { MOD_TABLE (MOD_0F12_PREFIX_2) },
3643     { "movddup", { XM, EXq }, PREFIX_OPCODE },
3644   },
3645
3646   /* PREFIX_0F16 */
3647   {
3648     { MOD_TABLE (MOD_0F16_PREFIX_0) },
3649     { "movshdup", { XM, EXx }, PREFIX_OPCODE },
3650     { MOD_TABLE (MOD_0F16_PREFIX_2) },
3651   },
3652
3653   /* PREFIX_0F1A */
3654   {
3655     { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3656     { "bndcl",  { Gbnd, Ev_bnd }, 0 },
3657     { "bndmov", { Gbnd, Ebnd }, 0 },
3658     { "bndcu",  { Gbnd, Ev_bnd }, 0 },
3659   },
3660
3661   /* PREFIX_0F1B */
3662   {
3663     { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3664     { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3665     { "bndmov", { EbndS, Gbnd }, 0 },
3666     { "bndcn",  { Gbnd, Ev_bnd }, 0 },
3667   },
3668
3669   /* PREFIX_0F1C */
3670   {
3671     { MOD_TABLE (MOD_0F1C_PREFIX_0) },
3672     { "nopQ",   { Ev }, PREFIX_OPCODE },
3673     { "nopQ",   { Ev }, PREFIX_OPCODE },
3674     { "nopQ",   { Ev }, PREFIX_OPCODE },
3675   },
3676
3677   /* PREFIX_0F1E */
3678   {
3679     { "nopQ",   { Ev }, PREFIX_OPCODE },
3680     { MOD_TABLE (MOD_0F1E_PREFIX_1) },
3681     { "nopQ",   { Ev }, PREFIX_OPCODE },
3682     { "nopQ",   { Ev }, PREFIX_OPCODE },
3683   },
3684
3685   /* PREFIX_0F2A */
3686   {
3687     { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE },
3688     { "cvtsi2ss%LQ", { XM, Edq }, PREFIX_OPCODE },
3689     { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE },
3690     { "cvtsi2sd%LQ", { XM, Edq }, 0 },
3691   },
3692
3693   /* PREFIX_0F2B */
3694   {
3695     { MOD_TABLE (MOD_0F2B_PREFIX_0) },
3696     { MOD_TABLE (MOD_0F2B_PREFIX_1) },
3697     { MOD_TABLE (MOD_0F2B_PREFIX_2) },
3698     { MOD_TABLE (MOD_0F2B_PREFIX_3) },
3699   },
3700
3701   /* PREFIX_0F2C */
3702   {
3703     { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE },
3704     { "cvttss2si", { Gdq, EXd }, PREFIX_OPCODE },
3705     { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3706     { "cvttsd2si", { Gdq, EXq }, PREFIX_OPCODE },
3707   },
3708
3709   /* PREFIX_0F2D */
3710   {
3711     { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE },
3712     { "cvtss2si", { Gdq, EXd }, PREFIX_OPCODE },
3713     { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3714     { "cvtsd2si", { Gdq, EXq }, PREFIX_OPCODE },
3715   },
3716
3717   /* PREFIX_0F2E */
3718   {
3719     { "ucomiss",{ XM, EXd }, 0 },
3720     { Bad_Opcode },
3721     { "ucomisd",{ XM, EXq }, 0 },
3722   },
3723
3724   /* PREFIX_0F2F */
3725   {
3726     { "comiss", { XM, EXd }, 0 },
3727     { Bad_Opcode },
3728     { "comisd", { XM, EXq }, 0 },
3729   },
3730
3731   /* PREFIX_0F51 */
3732   {
3733     { "sqrtps", { XM, EXx }, PREFIX_OPCODE },
3734     { "sqrtss", { XM, EXd }, PREFIX_OPCODE },
3735     { "sqrtpd", { XM, EXx }, PREFIX_OPCODE },
3736     { "sqrtsd", { XM, EXq }, PREFIX_OPCODE },
3737   },
3738
3739   /* PREFIX_0F52 */
3740   {
3741     { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE },
3742     { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE },
3743   },
3744
3745   /* PREFIX_0F53 */
3746   {
3747     { "rcpps",  { XM, EXx }, PREFIX_OPCODE },
3748     { "rcpss",  { XM, EXd }, PREFIX_OPCODE },
3749   },
3750
3751   /* PREFIX_0F58 */
3752   {
3753     { "addps", { XM, EXx }, PREFIX_OPCODE },
3754     { "addss", { XM, EXd }, PREFIX_OPCODE },
3755     { "addpd", { XM, EXx }, PREFIX_OPCODE },
3756     { "addsd", { XM, EXq }, PREFIX_OPCODE },
3757   },
3758
3759   /* PREFIX_0F59 */
3760   {
3761     { "mulps",  { XM, EXx }, PREFIX_OPCODE },
3762     { "mulss",  { XM, EXd }, PREFIX_OPCODE },
3763     { "mulpd",  { XM, EXx }, PREFIX_OPCODE },
3764     { "mulsd",  { XM, EXq }, PREFIX_OPCODE },
3765   },
3766
3767   /* PREFIX_0F5A */
3768   {
3769     { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE },
3770     { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE },
3771     { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE },
3772     { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE },
3773   },
3774
3775   /* PREFIX_0F5B */
3776   {
3777     { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE },
3778     { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE },
3779     { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE },
3780   },
3781
3782   /* PREFIX_0F5C */
3783   {
3784     { "subps",  { XM, EXx }, PREFIX_OPCODE },
3785     { "subss",  { XM, EXd }, PREFIX_OPCODE },
3786     { "subpd",  { XM, EXx }, PREFIX_OPCODE },
3787     { "subsd",  { XM, EXq }, PREFIX_OPCODE },
3788   },
3789
3790   /* PREFIX_0F5D */
3791   {
3792     { "minps",  { XM, EXx }, PREFIX_OPCODE },
3793     { "minss",  { XM, EXd }, PREFIX_OPCODE },
3794     { "minpd",  { XM, EXx }, PREFIX_OPCODE },
3795     { "minsd",  { XM, EXq }, PREFIX_OPCODE },
3796   },
3797
3798   /* PREFIX_0F5E */
3799   {
3800     { "divps",  { XM, EXx }, PREFIX_OPCODE },
3801     { "divss",  { XM, EXd }, PREFIX_OPCODE },
3802     { "divpd",  { XM, EXx }, PREFIX_OPCODE },
3803     { "divsd",  { XM, EXq }, PREFIX_OPCODE },
3804   },
3805
3806   /* PREFIX_0F5F */
3807   {
3808     { "maxps",  { XM, EXx }, PREFIX_OPCODE },
3809     { "maxss",  { XM, EXd }, PREFIX_OPCODE },
3810     { "maxpd",  { XM, EXx }, PREFIX_OPCODE },
3811     { "maxsd",  { XM, EXq }, PREFIX_OPCODE },
3812   },
3813
3814   /* PREFIX_0F60 */
3815   {
3816     { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE },
3817     { Bad_Opcode },
3818     { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE },
3819   },
3820
3821   /* PREFIX_0F61 */
3822   {
3823     { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE },
3824     { Bad_Opcode },
3825     { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE },
3826   },
3827
3828   /* PREFIX_0F62 */
3829   {
3830     { "punpckldq",{ MX, EMd }, PREFIX_OPCODE },
3831     { Bad_Opcode },
3832     { "punpckldq",{ MX, EMx }, PREFIX_OPCODE },
3833   },
3834
3835   /* PREFIX_0F6C */
3836   {
3837     { Bad_Opcode },
3838     { Bad_Opcode },
3839     { "punpcklqdq", { XM, EXx }, PREFIX_OPCODE },
3840   },
3841
3842   /* PREFIX_0F6D */
3843   {
3844     { Bad_Opcode },
3845     { Bad_Opcode },
3846     { "punpckhqdq", { XM, EXx }, PREFIX_OPCODE },
3847   },
3848
3849   /* PREFIX_0F6F */
3850   {
3851     { "movq",   { MX, EM }, PREFIX_OPCODE },
3852     { "movdqu", { XM, EXx }, PREFIX_OPCODE },
3853     { "movdqa", { XM, EXx }, PREFIX_OPCODE },
3854   },
3855
3856   /* PREFIX_0F70 */
3857   {
3858     { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE },
3859     { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3860     { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE },
3861     { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3862   },
3863
3864   /* PREFIX_0F73_REG_3 */
3865   {
3866     { Bad_Opcode },
3867     { Bad_Opcode },
3868     { "psrldq", { XS, Ib }, 0 },
3869   },
3870
3871   /* PREFIX_0F73_REG_7 */
3872   {
3873     { Bad_Opcode },
3874     { Bad_Opcode },
3875     { "pslldq", { XS, Ib }, 0 },
3876   },
3877
3878   /* PREFIX_0F78 */
3879   {
3880     {"vmread",  { Em, Gm }, 0 },
3881     { Bad_Opcode },
3882     {"extrq",   { XS, Ib, Ib }, 0 },
3883     {"insertq", { XM, XS, Ib, Ib }, 0 },
3884   },
3885
3886   /* PREFIX_0F79 */
3887   {
3888     {"vmwrite", { Gm, Em }, 0 },
3889     { Bad_Opcode },
3890     {"extrq",   { XM, XS }, 0 },
3891     {"insertq", { XM, XS }, 0 },
3892   },
3893
3894   /* PREFIX_0F7C */
3895   {
3896     { Bad_Opcode },
3897     { Bad_Opcode },
3898     { "haddpd", { XM, EXx }, PREFIX_OPCODE },
3899     { "haddps", { XM, EXx }, PREFIX_OPCODE },
3900   },
3901
3902   /* PREFIX_0F7D */
3903   {
3904     { Bad_Opcode },
3905     { Bad_Opcode },
3906     { "hsubpd", { XM, EXx }, PREFIX_OPCODE },
3907     { "hsubps", { XM, EXx }, PREFIX_OPCODE },
3908   },
3909
3910   /* PREFIX_0F7E */
3911   {
3912     { "movK",   { Edq, MX }, PREFIX_OPCODE },
3913     { "movq",   { XM, EXq }, PREFIX_OPCODE },
3914     { "movK",   { Edq, XM }, PREFIX_OPCODE },
3915   },
3916
3917   /* PREFIX_0F7F */
3918   {
3919     { "movq",   { EMS, MX }, PREFIX_OPCODE },
3920     { "movdqu", { EXxS, XM }, PREFIX_OPCODE },
3921     { "movdqa", { EXxS, XM }, PREFIX_OPCODE },
3922   },
3923
3924   /* PREFIX_0FAE_REG_0_MOD_3 */
3925   {
3926     { Bad_Opcode },
3927     { "rdfsbase", { Ev }, 0 },
3928   },
3929
3930   /* PREFIX_0FAE_REG_1_MOD_3 */
3931   {
3932     { Bad_Opcode },
3933     { "rdgsbase", { Ev }, 0 },
3934   },
3935
3936   /* PREFIX_0FAE_REG_2_MOD_3 */
3937   {
3938     { Bad_Opcode },
3939     { "wrfsbase", { Ev }, 0 },
3940   },
3941
3942   /* PREFIX_0FAE_REG_3_MOD_3 */
3943   {
3944     { Bad_Opcode },
3945     { "wrgsbase", { Ev }, 0 },
3946   },
3947
3948   /* PREFIX_0FAE_REG_4_MOD_0 */
3949   {
3950     { "xsave",  { FXSAVE }, 0 },
3951     { "ptwrite%LQ", { Edq }, 0 },
3952   },
3953
3954   /* PREFIX_0FAE_REG_4_MOD_3 */
3955   {
3956     { Bad_Opcode },
3957     { "ptwrite%LQ", { Edq }, 0 },
3958   },
3959
3960   /* PREFIX_0FAE_REG_5_MOD_0 */
3961   {
3962     { "xrstor",         { FXSAVE }, PREFIX_OPCODE },
3963   },
3964
3965   /* PREFIX_0FAE_REG_5_MOD_3 */
3966   {
3967     { "lfence",         { Skip_MODRM }, 0 },
3968     { "incsspK",        { Rdq }, PREFIX_OPCODE },
3969   },
3970
3971   /* PREFIX_0FAE_REG_6_MOD_0 */
3972   {
3973     { "xsaveopt",       { FXSAVE }, PREFIX_OPCODE },
3974     { "clrssbsy",       { Mq }, PREFIX_OPCODE },
3975     { "clwb",   { Mb }, PREFIX_OPCODE },
3976   },
3977
3978   /* PREFIX_0FAE_REG_6_MOD_3 */
3979   {
3980     { RM_TABLE (RM_0FAE_REG_6_MOD_3_P_0) },
3981     { "umonitor",       { Eva }, PREFIX_OPCODE },
3982     { "tpause", { Edq }, PREFIX_OPCODE },
3983     { "umwait", { Edq }, PREFIX_OPCODE },
3984   },
3985
3986   /* PREFIX_0FAE_REG_7_MOD_0 */
3987   {
3988     { "clflush",        { Mb }, 0 },
3989     { Bad_Opcode },
3990     { "clflushopt",     { Mb }, 0 },
3991   },
3992
3993   /* PREFIX_0FB8 */
3994   {
3995     { Bad_Opcode },
3996     { "popcntS", { Gv, Ev }, 0 },
3997   },
3998
3999   /* PREFIX_0FBC */
4000   {
4001     { "bsfS",   { Gv, Ev }, 0 },
4002     { "tzcntS", { Gv, Ev }, 0 },
4003     { "bsfS",   { Gv, Ev }, 0 },
4004   },
4005
4006   /* PREFIX_0FBD */
4007   {
4008     { "bsrS",   { Gv, Ev }, 0 },
4009     { "lzcntS", { Gv, Ev }, 0 },
4010     { "bsrS",   { Gv, Ev }, 0 },
4011   },
4012
4013   /* PREFIX_0FC2 */
4014   {
4015     { "cmpps",  { XM, EXx, CMP }, PREFIX_OPCODE },
4016     { "cmpss",  { XM, EXd, CMP }, PREFIX_OPCODE },
4017     { "cmppd",  { XM, EXx, CMP }, PREFIX_OPCODE },
4018     { "cmpsd",  { XM, EXq, CMP }, PREFIX_OPCODE },
4019   },
4020
4021   /* PREFIX_0FC3_MOD_0 */
4022   {
4023     { "movntiS", { Edq, Gdq }, PREFIX_OPCODE },
4024   },
4025
4026   /* PREFIX_0FC7_REG_6_MOD_0 */
4027   {
4028     { "vmptrld",{ Mq }, 0 },
4029     { "vmxon",  { Mq }, 0 },
4030     { "vmclear",{ Mq }, 0 },
4031   },
4032
4033   /* PREFIX_0FC7_REG_6_MOD_3 */
4034   {
4035     { "rdrand", { Ev }, 0 },
4036     { Bad_Opcode },
4037     { "rdrand", { Ev }, 0 }
4038   },
4039
4040   /* PREFIX_0FC7_REG_7_MOD_3 */
4041   {
4042     { "rdseed", { Ev }, 0 },
4043     { "rdpid",  { Em }, 0 },
4044     { "rdseed", { Ev }, 0 },
4045   },
4046
4047   /* PREFIX_0FD0 */
4048   {
4049     { Bad_Opcode },
4050     { Bad_Opcode },
4051     { "addsubpd", { XM, EXx }, 0 },
4052     { "addsubps", { XM, EXx }, 0 },
4053   },
4054
4055   /* PREFIX_0FD6 */
4056   {
4057     { Bad_Opcode },
4058     { "movq2dq",{ XM, MS }, 0 },
4059     { "movq",   { EXqS, XM }, 0 },
4060     { "movdq2q",{ MX, XS }, 0 },
4061   },
4062
4063   /* PREFIX_0FE6 */
4064   {
4065     { Bad_Opcode },
4066     { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE },
4067     { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE },
4068     { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE },
4069   },
4070
4071   /* PREFIX_0FE7 */
4072   {
4073     { "movntq", { Mq, MX }, PREFIX_OPCODE },
4074     { Bad_Opcode },
4075     { MOD_TABLE (MOD_0FE7_PREFIX_2) },
4076   },
4077
4078   /* PREFIX_0FF0 */
4079   {
4080     { Bad_Opcode },
4081     { Bad_Opcode },
4082     { Bad_Opcode },
4083     { MOD_TABLE (MOD_0FF0_PREFIX_3) },
4084   },
4085
4086   /* PREFIX_0FF7 */
4087   {
4088     { "maskmovq", { MX, MS }, PREFIX_OPCODE },
4089     { Bad_Opcode },
4090     { "maskmovdqu", { XM, XS }, PREFIX_OPCODE },
4091   },
4092
4093   /* PREFIX_0F3810 */
4094   {
4095     { Bad_Opcode },
4096     { Bad_Opcode },
4097     { "pblendvb", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4098   },
4099
4100   /* PREFIX_0F3814 */
4101   {
4102     { Bad_Opcode },
4103     { Bad_Opcode },
4104     { "blendvps", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4105   },
4106
4107   /* PREFIX_0F3815 */
4108   {
4109     { Bad_Opcode },
4110     { Bad_Opcode },
4111     { "blendvpd", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4112   },
4113
4114   /* PREFIX_0F3817 */
4115   {
4116     { Bad_Opcode },
4117     { Bad_Opcode },
4118     { "ptest",  { XM, EXx }, PREFIX_OPCODE },
4119   },
4120
4121   /* PREFIX_0F3820 */
4122   {
4123     { Bad_Opcode },
4124     { Bad_Opcode },
4125     { "pmovsxbw", { XM, EXq }, PREFIX_OPCODE },
4126   },
4127
4128   /* PREFIX_0F3821 */
4129   {
4130     { Bad_Opcode },
4131     { Bad_Opcode },
4132     { "pmovsxbd", { XM, EXd }, PREFIX_OPCODE },
4133   },
4134
4135   /* PREFIX_0F3822 */
4136   {
4137     { Bad_Opcode },
4138     { Bad_Opcode },
4139     { "pmovsxbq", { XM, EXw }, PREFIX_OPCODE },
4140   },
4141
4142   /* PREFIX_0F3823 */
4143   {
4144     { Bad_Opcode },
4145     { Bad_Opcode },
4146     { "pmovsxwd", { XM, EXq }, PREFIX_OPCODE },
4147   },
4148
4149   /* PREFIX_0F3824 */
4150   {
4151     { Bad_Opcode },
4152     { Bad_Opcode },
4153     { "pmovsxwq", { XM, EXd }, PREFIX_OPCODE },
4154   },
4155
4156   /* PREFIX_0F3825 */
4157   {
4158     { Bad_Opcode },
4159     { Bad_Opcode },
4160     { "pmovsxdq", { XM, EXq }, PREFIX_OPCODE },
4161   },
4162
4163   /* PREFIX_0F3828 */
4164   {
4165     { Bad_Opcode },
4166     { Bad_Opcode },
4167     { "pmuldq", { XM, EXx }, PREFIX_OPCODE },
4168   },
4169
4170   /* PREFIX_0F3829 */
4171   {
4172     { Bad_Opcode },
4173     { Bad_Opcode },
4174     { "pcmpeqq", { XM, EXx }, PREFIX_OPCODE },
4175   },
4176
4177   /* PREFIX_0F382A */
4178   {
4179     { Bad_Opcode },
4180     { Bad_Opcode },
4181     { MOD_TABLE (MOD_0F382A_PREFIX_2) },
4182   },
4183
4184   /* PREFIX_0F382B */
4185   {
4186     { Bad_Opcode },
4187     { Bad_Opcode },
4188     { "packusdw", { XM, EXx }, PREFIX_OPCODE },
4189   },
4190
4191   /* PREFIX_0F3830 */
4192   {
4193     { Bad_Opcode },
4194     { Bad_Opcode },
4195     { "pmovzxbw", { XM, EXq }, PREFIX_OPCODE },
4196   },
4197
4198   /* PREFIX_0F3831 */
4199   {
4200     { Bad_Opcode },
4201     { Bad_Opcode },
4202     { "pmovzxbd", { XM, EXd }, PREFIX_OPCODE },
4203   },
4204
4205   /* PREFIX_0F3832 */
4206   {
4207     { Bad_Opcode },
4208     { Bad_Opcode },
4209     { "pmovzxbq", { XM, EXw }, PREFIX_OPCODE },
4210   },
4211
4212   /* PREFIX_0F3833 */
4213   {
4214     { Bad_Opcode },
4215     { Bad_Opcode },
4216     { "pmovzxwd", { XM, EXq }, PREFIX_OPCODE },
4217   },
4218
4219   /* PREFIX_0F3834 */
4220   {
4221     { Bad_Opcode },
4222     { Bad_Opcode },
4223     { "pmovzxwq", { XM, EXd }, PREFIX_OPCODE },
4224   },
4225
4226   /* PREFIX_0F3835 */
4227   {
4228     { Bad_Opcode },
4229     { Bad_Opcode },
4230     { "pmovzxdq", { XM, EXq }, PREFIX_OPCODE },
4231   },
4232
4233   /* PREFIX_0F3837 */
4234   {
4235     { Bad_Opcode },
4236     { Bad_Opcode },
4237     { "pcmpgtq", { XM, EXx }, PREFIX_OPCODE },
4238   },
4239
4240   /* PREFIX_0F3838 */
4241   {
4242     { Bad_Opcode },
4243     { Bad_Opcode },
4244     { "pminsb", { XM, EXx }, PREFIX_OPCODE },
4245   },
4246
4247   /* PREFIX_0F3839 */
4248   {
4249     { Bad_Opcode },
4250     { Bad_Opcode },
4251     { "pminsd", { XM, EXx }, PREFIX_OPCODE },
4252   },
4253
4254   /* PREFIX_0F383A */
4255   {
4256     { Bad_Opcode },
4257     { Bad_Opcode },
4258     { "pminuw", { XM, EXx }, PREFIX_OPCODE },
4259   },
4260
4261   /* PREFIX_0F383B */
4262   {
4263     { Bad_Opcode },
4264     { Bad_Opcode },
4265     { "pminud", { XM, EXx }, PREFIX_OPCODE },
4266   },
4267
4268   /* PREFIX_0F383C */
4269   {
4270     { Bad_Opcode },
4271     { Bad_Opcode },
4272     { "pmaxsb", { XM, EXx }, PREFIX_OPCODE },
4273   },
4274
4275   /* PREFIX_0F383D */
4276   {
4277     { Bad_Opcode },
4278     { Bad_Opcode },
4279     { "pmaxsd", { XM, EXx }, PREFIX_OPCODE },
4280   },
4281
4282   /* PREFIX_0F383E */
4283   {
4284     { Bad_Opcode },
4285     { Bad_Opcode },
4286     { "pmaxuw", { XM, EXx }, PREFIX_OPCODE },
4287   },
4288
4289   /* PREFIX_0F383F */
4290   {
4291     { Bad_Opcode },
4292     { Bad_Opcode },
4293     { "pmaxud", { XM, EXx }, PREFIX_OPCODE },
4294   },
4295
4296   /* PREFIX_0F3840 */
4297   {
4298     { Bad_Opcode },
4299     { Bad_Opcode },
4300     { "pmulld", { XM, EXx }, PREFIX_OPCODE },
4301   },
4302
4303   /* PREFIX_0F3841 */
4304   {
4305     { Bad_Opcode },
4306     { Bad_Opcode },
4307     { "phminposuw", { XM, EXx }, PREFIX_OPCODE },
4308   },
4309
4310   /* PREFIX_0F3880 */
4311   {
4312     { Bad_Opcode },
4313     { Bad_Opcode },
4314     { "invept", { Gm, Mo }, PREFIX_OPCODE },
4315   },
4316
4317   /* PREFIX_0F3881 */
4318   {
4319     { Bad_Opcode },
4320     { Bad_Opcode },
4321     { "invvpid", { Gm, Mo }, PREFIX_OPCODE },
4322   },
4323
4324   /* PREFIX_0F3882 */
4325   {
4326     { Bad_Opcode },
4327     { Bad_Opcode },
4328     { "invpcid", { Gm, M }, PREFIX_OPCODE },
4329   },
4330
4331   /* PREFIX_0F38C8 */
4332   {
4333     { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE },
4334   },
4335
4336   /* PREFIX_0F38C9 */
4337   {
4338     { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE },
4339   },
4340
4341   /* PREFIX_0F38CA */
4342   {
4343     { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE },
4344   },
4345
4346   /* PREFIX_0F38CB */
4347   {
4348     { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE },
4349   },
4350
4351   /* PREFIX_0F38CC */
4352   {
4353     { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE },
4354   },
4355
4356   /* PREFIX_0F38CD */
4357   {
4358     { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE },
4359   },
4360
4361   /* PREFIX_0F38CF */
4362   {
4363     { Bad_Opcode },
4364     { Bad_Opcode },
4365     { "gf2p8mulb", { XM, EXxmm }, PREFIX_OPCODE },
4366   },
4367
4368   /* PREFIX_0F38DB */
4369   {
4370     { Bad_Opcode },
4371     { Bad_Opcode },
4372     { "aesimc", { XM, EXx }, PREFIX_OPCODE },
4373   },
4374
4375   /* PREFIX_0F38DC */
4376   {
4377     { Bad_Opcode },
4378     { Bad_Opcode },
4379     { "aesenc", { XM, EXx }, PREFIX_OPCODE },
4380   },
4381
4382   /* PREFIX_0F38DD */
4383   {
4384     { Bad_Opcode },
4385     { Bad_Opcode },
4386     { "aesenclast", { XM, EXx }, PREFIX_OPCODE },
4387   },
4388
4389   /* PREFIX_0F38DE */
4390   {
4391     { Bad_Opcode },
4392     { Bad_Opcode },
4393     { "aesdec", { XM, EXx }, PREFIX_OPCODE },
4394   },
4395
4396   /* PREFIX_0F38DF */
4397   {
4398     { Bad_Opcode },
4399     { Bad_Opcode },
4400     { "aesdeclast", { XM, EXx }, PREFIX_OPCODE },
4401   },
4402
4403   /* PREFIX_0F38F0 */
4404   {
4405     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4406     { Bad_Opcode },
4407     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4408     { "crc32",  { Gdq, { CRC32_Fixup, b_mode } }, PREFIX_OPCODE },
4409   },
4410
4411   /* PREFIX_0F38F1 */
4412   {
4413     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4414     { Bad_Opcode },
4415     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4416     { "crc32",  { Gdq, { CRC32_Fixup, v_mode } }, PREFIX_OPCODE },
4417   },
4418
4419   /* PREFIX_0F38F5 */
4420   {
4421     { Bad_Opcode },
4422     { Bad_Opcode },
4423     { MOD_TABLE (MOD_0F38F5_PREFIX_2) },
4424   },
4425
4426   /* PREFIX_0F38F6 */
4427   {
4428     { MOD_TABLE (MOD_0F38F6_PREFIX_0) },
4429     { "adoxS",  { Gdq, Edq}, PREFIX_OPCODE },
4430     { "adcxS",  { Gdq, Edq}, PREFIX_OPCODE },
4431     { Bad_Opcode },
4432   },
4433
4434   /* PREFIX_0F38F8 */
4435   {
4436     { Bad_Opcode },
4437     { MOD_TABLE (MOD_0F38F8_PREFIX_1) },
4438     { MOD_TABLE (MOD_0F38F8_PREFIX_2) },
4439     { MOD_TABLE (MOD_0F38F8_PREFIX_3) },
4440   },
4441
4442   /* PREFIX_0F38F9 */
4443   {
4444     { MOD_TABLE (MOD_0F38F9_PREFIX_0) },
4445   },
4446
4447   /* PREFIX_0F3A08 */
4448   {
4449     { Bad_Opcode },
4450     { Bad_Opcode },
4451     { "roundps", { XM, EXx, Ib }, PREFIX_OPCODE },
4452   },
4453
4454   /* PREFIX_0F3A09 */
4455   {
4456     { Bad_Opcode },
4457     { Bad_Opcode },
4458     { "roundpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4459   },
4460
4461   /* PREFIX_0F3A0A */
4462   {
4463     { Bad_Opcode },
4464     { Bad_Opcode },
4465     { "roundss", { XM, EXd, Ib }, PREFIX_OPCODE },
4466   },
4467
4468   /* PREFIX_0F3A0B */
4469   {
4470     { Bad_Opcode },
4471     { Bad_Opcode },
4472     { "roundsd", { XM, EXq, Ib }, PREFIX_OPCODE },
4473   },
4474
4475   /* PREFIX_0F3A0C */
4476   {
4477     { Bad_Opcode },
4478     { Bad_Opcode },
4479     { "blendps", { XM, EXx, Ib }, PREFIX_OPCODE },
4480   },
4481
4482   /* PREFIX_0F3A0D */
4483   {
4484     { Bad_Opcode },
4485     { Bad_Opcode },
4486     { "blendpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4487   },
4488
4489   /* PREFIX_0F3A0E */
4490   {
4491     { Bad_Opcode },
4492     { Bad_Opcode },
4493     { "pblendw", { XM, EXx, Ib }, PREFIX_OPCODE },
4494   },
4495
4496   /* PREFIX_0F3A14 */
4497   {
4498     { Bad_Opcode },
4499     { Bad_Opcode },
4500     { "pextrb", { Edqb, XM, Ib }, PREFIX_OPCODE },
4501   },
4502
4503   /* PREFIX_0F3A15 */
4504   {
4505     { Bad_Opcode },
4506     { Bad_Opcode },
4507     { "pextrw", { Edqw, XM, Ib }, PREFIX_OPCODE },
4508   },
4509
4510   /* PREFIX_0F3A16 */
4511   {
4512     { Bad_Opcode },
4513     { Bad_Opcode },
4514     { "pextrK", { Edq, XM, Ib }, PREFIX_OPCODE },
4515   },
4516
4517   /* PREFIX_0F3A17 */
4518   {
4519     { Bad_Opcode },
4520     { Bad_Opcode },
4521     { "extractps", { Edqd, XM, Ib }, PREFIX_OPCODE },
4522   },
4523
4524   /* PREFIX_0F3A20 */
4525   {
4526     { Bad_Opcode },
4527     { Bad_Opcode },
4528     { "pinsrb", { XM, Edqb, Ib }, PREFIX_OPCODE },
4529   },
4530
4531   /* PREFIX_0F3A21 */
4532   {
4533     { Bad_Opcode },
4534     { Bad_Opcode },
4535     { "insertps", { XM, EXd, Ib }, PREFIX_OPCODE },
4536   },
4537
4538   /* PREFIX_0F3A22 */
4539   {
4540     { Bad_Opcode },
4541     { Bad_Opcode },
4542     { "pinsrK", { XM, Edq, Ib }, PREFIX_OPCODE },
4543   },
4544
4545   /* PREFIX_0F3A40 */
4546   {
4547     { Bad_Opcode },
4548     { Bad_Opcode },
4549     { "dpps",   { XM, EXx, Ib }, PREFIX_OPCODE },
4550   },
4551
4552   /* PREFIX_0F3A41 */
4553   {
4554     { Bad_Opcode },
4555     { Bad_Opcode },
4556     { "dppd",   { XM, EXx, Ib }, PREFIX_OPCODE },
4557   },
4558
4559   /* PREFIX_0F3A42 */
4560   {
4561     { Bad_Opcode },
4562     { Bad_Opcode },
4563     { "mpsadbw", { XM, EXx, Ib }, PREFIX_OPCODE },
4564   },
4565
4566   /* PREFIX_0F3A44 */
4567   {
4568     { Bad_Opcode },
4569     { Bad_Opcode },
4570     { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_OPCODE },
4571   },
4572
4573   /* PREFIX_0F3A60 */
4574   {
4575     { Bad_Opcode },
4576     { Bad_Opcode },
4577     { "pcmpestrm", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE },
4578   },
4579
4580   /* PREFIX_0F3A61 */
4581   {
4582     { Bad_Opcode },
4583     { Bad_Opcode },
4584     { "pcmpestri", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE },
4585   },
4586
4587   /* PREFIX_0F3A62 */
4588   {
4589     { Bad_Opcode },
4590     { Bad_Opcode },
4591     { "pcmpistrm", { XM, EXx, Ib }, PREFIX_OPCODE },
4592   },
4593
4594   /* PREFIX_0F3A63 */
4595   {
4596     { Bad_Opcode },
4597     { Bad_Opcode },
4598     { "pcmpistri", { XM, EXx, Ib }, PREFIX_OPCODE },
4599   },
4600
4601   /* PREFIX_0F3ACC */
4602   {
4603     { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4604   },
4605
4606   /* PREFIX_0F3ACE */
4607   {
4608     { Bad_Opcode },
4609     { Bad_Opcode },
4610     { "gf2p8affineqb", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4611   },
4612
4613   /* PREFIX_0F3ACF */
4614   {
4615     { Bad_Opcode },
4616     { Bad_Opcode },
4617     { "gf2p8affineinvqb", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4618   },
4619
4620   /* PREFIX_0F3ADF */
4621   {
4622     { Bad_Opcode },
4623     { Bad_Opcode },
4624     { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_OPCODE },
4625   },
4626
4627   /* PREFIX_VEX_0F10 */
4628   {
4629     { "vmovups",        { XM, EXx }, 0 },
4630     { "vmovss",         { XMVexScalar, VexScalar, EXxmm_md }, 0 },
4631     { "vmovupd",        { XM, EXx }, 0 },
4632     { "vmovsd",         { XMVexScalar, VexScalar, EXxmm_mq }, 0 },
4633   },
4634
4635   /* PREFIX_VEX_0F11 */
4636   {
4637     { "vmovups",        { EXxS, XM }, 0 },
4638     { "vmovss",         { EXdVexScalarS, VexScalar, XMScalar }, 0 },
4639     { "vmovupd",        { EXxS, XM }, 0 },
4640     { "vmovsd",         { EXqVexScalarS, VexScalar, XMScalar }, 0 },
4641   },
4642
4643   /* PREFIX_VEX_0F12 */
4644   {
4645     { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
4646     { "vmovsldup",      { XM, EXx }, 0 },
4647     { MOD_TABLE (MOD_VEX_0F12_PREFIX_2) },
4648     { "vmovddup",       { XM, EXymmq }, 0 },
4649   },
4650
4651   /* PREFIX_VEX_0F16 */
4652   {
4653     { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
4654     { "vmovshdup",      { XM, EXx }, 0 },
4655     { MOD_TABLE (MOD_VEX_0F16_PREFIX_2) },
4656   },
4657
4658   /* PREFIX_VEX_0F2A */
4659   {
4660     { Bad_Opcode },
4661     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Edq }, 0 },
4662     { Bad_Opcode },
4663     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Edq }, 0 },
4664   },
4665
4666   /* PREFIX_VEX_0F2C */
4667   {
4668     { Bad_Opcode },
4669     { "vcvttss2si",     { Gdq, EXxmm_md }, 0 },
4670     { Bad_Opcode },
4671     { "vcvttsd2si",     { Gdq, EXxmm_mq }, 0 },
4672   },
4673
4674   /* PREFIX_VEX_0F2D */
4675   {
4676     { Bad_Opcode },
4677     { "vcvtss2si",      { Gdq, EXxmm_md }, 0 },
4678     { Bad_Opcode },
4679     { "vcvtsd2si",      { Gdq, EXxmm_mq }, 0 },
4680   },
4681
4682   /* PREFIX_VEX_0F2E */
4683   {
4684     { "vucomiss",       { XMScalar, EXxmm_md }, 0 },
4685     { Bad_Opcode },
4686     { "vucomisd",       { XMScalar, EXxmm_mq }, 0 },
4687   },
4688
4689   /* PREFIX_VEX_0F2F */
4690   {
4691     { "vcomiss",        { XMScalar, EXxmm_md }, 0 },
4692     { Bad_Opcode },
4693     { "vcomisd",        { XMScalar, EXxmm_mq }, 0 },
4694   },
4695
4696   /* PREFIX_VEX_0F41 */
4697   {
4698     { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) },
4699     { Bad_Opcode },
4700     { VEX_LEN_TABLE (VEX_LEN_0F41_P_2) },
4701   },
4702
4703   /* PREFIX_VEX_0F42 */
4704   {
4705     { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) },
4706     { Bad_Opcode },
4707     { VEX_LEN_TABLE (VEX_LEN_0F42_P_2) },
4708   },
4709
4710   /* PREFIX_VEX_0F44 */
4711   {
4712     { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) },
4713     { Bad_Opcode },
4714     { VEX_LEN_TABLE (VEX_LEN_0F44_P_2) },
4715   },
4716
4717   /* PREFIX_VEX_0F45 */
4718   {
4719     { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) },
4720     { Bad_Opcode },
4721     { VEX_LEN_TABLE (VEX_LEN_0F45_P_2) },
4722   },
4723
4724   /* PREFIX_VEX_0F46 */
4725   {
4726     { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) },
4727     { Bad_Opcode },
4728     { VEX_LEN_TABLE (VEX_LEN_0F46_P_2) },
4729   },
4730
4731   /* PREFIX_VEX_0F47 */
4732   {
4733     { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) },
4734     { Bad_Opcode },
4735     { VEX_LEN_TABLE (VEX_LEN_0F47_P_2) },
4736   },
4737
4738   /* PREFIX_VEX_0F4A */
4739   {
4740     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0) },
4741     { Bad_Opcode },
4742     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2) },
4743   },
4744
4745   /* PREFIX_VEX_0F4B */
4746   {
4747     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0) },
4748     { Bad_Opcode },
4749     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) },
4750   },
4751
4752   /* PREFIX_VEX_0F51 */
4753   {
4754     { "vsqrtps",        { XM, EXx }, 0 },
4755     { "vsqrtss",        { XMScalar, VexScalar, EXxmm_md }, 0 },
4756     { "vsqrtpd",        { XM, EXx }, 0 },
4757     { "vsqrtsd",        { XMScalar, VexScalar, EXxmm_mq }, 0 },
4758   },
4759
4760   /* PREFIX_VEX_0F52 */
4761   {
4762     { "vrsqrtps",       { XM, EXx }, 0 },
4763     { "vrsqrtss",       { XMScalar, VexScalar, EXxmm_md }, 0 },
4764   },
4765
4766   /* PREFIX_VEX_0F53 */
4767   {
4768     { "vrcpps",         { XM, EXx }, 0 },
4769     { "vrcpss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
4770   },
4771
4772   /* PREFIX_VEX_0F58 */
4773   {
4774     { "vaddps",         { XM, Vex, EXx }, 0 },
4775     { "vaddss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
4776     { "vaddpd",         { XM, Vex, EXx }, 0 },
4777     { "vaddsd",         { XMScalar, VexScalar, EXxmm_mq }, 0 },
4778   },
4779
4780   /* PREFIX_VEX_0F59 */
4781   {
4782     { "vmulps",         { XM, Vex, EXx }, 0 },
4783     { "vmulss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
4784     { "vmulpd",         { XM, Vex, EXx }, 0 },
4785     { "vmulsd",         { XMScalar, VexScalar, EXxmm_mq }, 0 },
4786   },
4787
4788   /* PREFIX_VEX_0F5A */
4789   {
4790     { "vcvtps2pd",      { XM, EXxmmq }, 0 },
4791     { "vcvtss2sd",      { XMScalar, VexScalar, EXxmm_md }, 0 },
4792     { "vcvtpd2ps%XY",{ XMM, EXx }, 0 },
4793     { "vcvtsd2ss",      { XMScalar, VexScalar, EXxmm_mq }, 0 },
4794   },
4795
4796   /* PREFIX_VEX_0F5B */
4797   {
4798     { "vcvtdq2ps",      { XM, EXx }, 0 },
4799     { "vcvttps2dq",     { XM, EXx }, 0 },
4800     { "vcvtps2dq",      { XM, EXx }, 0 },
4801   },
4802
4803   /* PREFIX_VEX_0F5C */
4804   {
4805     { "vsubps",         { XM, Vex, EXx }, 0 },
4806     { "vsubss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
4807     { "vsubpd",         { XM, Vex, EXx }, 0 },
4808     { "vsubsd",         { XMScalar, VexScalar, EXxmm_mq }, 0 },
4809   },
4810
4811   /* PREFIX_VEX_0F5D */
4812   {
4813     { "vminps",         { XM, Vex, EXx }, 0 },
4814     { "vminss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
4815     { "vminpd",         { XM, Vex, EXx }, 0 },
4816     { "vminsd",         { XMScalar, VexScalar, EXxmm_mq }, 0 },
4817   },
4818
4819   /* PREFIX_VEX_0F5E */
4820   {
4821     { "vdivps",         { XM, Vex, EXx }, 0 },
4822     { "vdivss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
4823     { "vdivpd",         { XM, Vex, EXx }, 0 },
4824     { "vdivsd",         { XMScalar, VexScalar, EXxmm_mq }, 0 },
4825   },
4826
4827   /* PREFIX_VEX_0F5F */
4828   {
4829     { "vmaxps",         { XM, Vex, EXx }, 0 },
4830     { "vmaxss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
4831     { "vmaxpd",         { XM, Vex, EXx }, 0 },
4832     { "vmaxsd",         { XMScalar, VexScalar, EXxmm_mq }, 0 },
4833   },
4834
4835   /* PREFIX_VEX_0F60 */
4836   {
4837     { Bad_Opcode },
4838     { Bad_Opcode },
4839     { "vpunpcklbw",     { XM, Vex, EXx }, 0 },
4840   },
4841
4842   /* PREFIX_VEX_0F61 */
4843   {
4844     { Bad_Opcode },
4845     { Bad_Opcode },
4846     { "vpunpcklwd",     { XM, Vex, EXx }, 0 },
4847   },
4848
4849   /* PREFIX_VEX_0F62 */
4850   {
4851     { Bad_Opcode },
4852     { Bad_Opcode },
4853     { "vpunpckldq",     { XM, Vex, EXx }, 0 },
4854   },
4855
4856   /* PREFIX_VEX_0F63 */
4857   {
4858     { Bad_Opcode },
4859     { Bad_Opcode },
4860     { "vpacksswb",      { XM, Vex, EXx }, 0 },
4861   },
4862
4863   /* PREFIX_VEX_0F64 */
4864   {
4865     { Bad_Opcode },
4866     { Bad_Opcode },
4867     { "vpcmpgtb",       { XM, Vex, EXx }, 0 },
4868   },
4869
4870   /* PREFIX_VEX_0F65 */
4871   {
4872     { Bad_Opcode },
4873     { Bad_Opcode },
4874     { "vpcmpgtw",       { XM, Vex, EXx }, 0 },
4875   },
4876
4877   /* PREFIX_VEX_0F66 */
4878   {
4879     { Bad_Opcode },
4880     { Bad_Opcode },
4881     { "vpcmpgtd",       { XM, Vex, EXx }, 0 },
4882   },
4883
4884   /* PREFIX_VEX_0F67 */
4885   {
4886     { Bad_Opcode },
4887     { Bad_Opcode },
4888     { "vpackuswb",      { XM, Vex, EXx }, 0 },
4889   },
4890
4891   /* PREFIX_VEX_0F68 */
4892   {
4893     { Bad_Opcode },
4894     { Bad_Opcode },
4895     { "vpunpckhbw",     { XM, Vex, EXx }, 0 },
4896   },
4897
4898   /* PREFIX_VEX_0F69 */
4899   {
4900     { Bad_Opcode },
4901     { Bad_Opcode },
4902     { "vpunpckhwd",     { XM, Vex, EXx }, 0 },
4903   },
4904
4905   /* PREFIX_VEX_0F6A */
4906   {
4907     { Bad_Opcode },
4908     { Bad_Opcode },
4909     { "vpunpckhdq",     { XM, Vex, EXx }, 0 },
4910   },
4911
4912   /* PREFIX_VEX_0F6B */
4913   {
4914     { Bad_Opcode },
4915     { Bad_Opcode },
4916     { "vpackssdw",      { XM, Vex, EXx }, 0 },
4917   },
4918
4919   /* PREFIX_VEX_0F6C */
4920   {
4921     { Bad_Opcode },
4922     { Bad_Opcode },
4923     { "vpunpcklqdq",    { XM, Vex, EXx }, 0 },
4924   },
4925
4926   /* PREFIX_VEX_0F6D */
4927   {
4928     { Bad_Opcode },
4929     { Bad_Opcode },
4930     { "vpunpckhqdq",    { XM, Vex, EXx }, 0 },
4931   },
4932
4933   /* PREFIX_VEX_0F6E */
4934   {
4935     { Bad_Opcode },
4936     { Bad_Opcode },
4937     { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) },
4938   },
4939
4940   /* PREFIX_VEX_0F6F */
4941   {
4942     { Bad_Opcode },
4943     { "vmovdqu",        { XM, EXx }, 0 },
4944     { "vmovdqa",        { XM, EXx }, 0 },
4945   },
4946
4947   /* PREFIX_VEX_0F70 */
4948   {
4949     { Bad_Opcode },
4950     { "vpshufhw",       { XM, EXx, Ib }, 0 },
4951     { "vpshufd",        { XM, EXx, Ib }, 0 },
4952     { "vpshuflw",       { XM, EXx, Ib }, 0 },
4953   },
4954
4955   /* PREFIX_VEX_0F71_REG_2 */
4956   {
4957     { Bad_Opcode },
4958     { Bad_Opcode },
4959     { "vpsrlw",         { Vex, XS, Ib }, 0 },
4960   },
4961
4962   /* PREFIX_VEX_0F71_REG_4 */
4963   {
4964     { Bad_Opcode },
4965     { Bad_Opcode },
4966     { "vpsraw",         { Vex, XS, Ib }, 0 },
4967   },
4968
4969   /* PREFIX_VEX_0F71_REG_6 */
4970   {
4971     { Bad_Opcode },
4972     { Bad_Opcode },
4973     { "vpsllw",         { Vex, XS, Ib }, 0 },
4974   },
4975
4976   /* PREFIX_VEX_0F72_REG_2 */
4977   {
4978     { Bad_Opcode },
4979     { Bad_Opcode },
4980     { "vpsrld",         { Vex, XS, Ib }, 0 },
4981   },
4982
4983   /* PREFIX_VEX_0F72_REG_4 */
4984   {
4985     { Bad_Opcode },
4986     { Bad_Opcode },
4987     { "vpsrad",         { Vex, XS, Ib }, 0 },
4988   },
4989
4990   /* PREFIX_VEX_0F72_REG_6 */
4991   {
4992     { Bad_Opcode },
4993     { Bad_Opcode },
4994     { "vpslld",         { Vex, XS, Ib }, 0 },
4995   },
4996
4997   /* PREFIX_VEX_0F73_REG_2 */
4998   {
4999     { Bad_Opcode },
5000     { Bad_Opcode },
5001     { "vpsrlq",         { Vex, XS, Ib }, 0 },
5002   },
5003
5004   /* PREFIX_VEX_0F73_REG_3 */
5005   {
5006     { Bad_Opcode },
5007     { Bad_Opcode },
5008     { "vpsrldq",        { Vex, XS, Ib }, 0 },
5009   },
5010
5011   /* PREFIX_VEX_0F73_REG_6 */
5012   {
5013     { Bad_Opcode },
5014     { Bad_Opcode },
5015     { "vpsllq",         { Vex, XS, Ib }, 0 },
5016   },
5017
5018   /* PREFIX_VEX_0F73_REG_7 */
5019   {
5020     { Bad_Opcode },
5021     { Bad_Opcode },
5022     { "vpslldq",        { Vex, XS, Ib }, 0 },
5023   },
5024
5025   /* PREFIX_VEX_0F74 */
5026   {
5027     { Bad_Opcode },
5028     { Bad_Opcode },
5029     { "vpcmpeqb",       { XM, Vex, EXx }, 0 },
5030   },
5031
5032   /* PREFIX_VEX_0F75 */
5033   {
5034     { Bad_Opcode },
5035     { Bad_Opcode },
5036     { "vpcmpeqw",       { XM, Vex, EXx }, 0 },
5037   },
5038
5039   /* PREFIX_VEX_0F76 */
5040   {
5041     { Bad_Opcode },
5042     { Bad_Opcode },
5043     { "vpcmpeqd",       { XM, Vex, EXx }, 0 },
5044   },
5045
5046   /* PREFIX_VEX_0F77 */
5047   {
5048     { VEX_LEN_TABLE (VEX_LEN_0F77_P_0) },
5049   },
5050
5051   /* PREFIX_VEX_0F7C */
5052   {
5053     { Bad_Opcode },
5054     { Bad_Opcode },
5055     { "vhaddpd",        { XM, Vex, EXx }, 0 },
5056     { "vhaddps",        { XM, Vex, EXx }, 0 },
5057   },
5058
5059   /* PREFIX_VEX_0F7D */
5060   {
5061     { Bad_Opcode },
5062     { Bad_Opcode },
5063     { "vhsubpd",        { XM, Vex, EXx }, 0 },
5064     { "vhsubps",        { XM, Vex, EXx }, 0 },
5065   },
5066
5067   /* PREFIX_VEX_0F7E */
5068   {
5069     { Bad_Opcode },
5070     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
5071     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
5072   },
5073
5074   /* PREFIX_VEX_0F7F */
5075   {
5076     { Bad_Opcode },
5077     { "vmovdqu",        { EXxS, XM }, 0 },
5078     { "vmovdqa",        { EXxS, XM }, 0 },
5079   },
5080
5081   /* PREFIX_VEX_0F90 */
5082   {
5083     { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) },
5084     { Bad_Opcode },
5085     { VEX_LEN_TABLE (VEX_LEN_0F90_P_2) },
5086   },
5087
5088   /* PREFIX_VEX_0F91 */
5089   {
5090     { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) },
5091     { Bad_Opcode },
5092     { VEX_LEN_TABLE (VEX_LEN_0F91_P_2) },
5093   },
5094
5095   /* PREFIX_VEX_0F92 */
5096   {
5097     { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) },
5098     { Bad_Opcode },
5099     { VEX_LEN_TABLE (VEX_LEN_0F92_P_2) },
5100     { VEX_LEN_TABLE (VEX_LEN_0F92_P_3) },
5101   },
5102
5103   /* PREFIX_VEX_0F93 */
5104   {
5105     { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) },
5106     { Bad_Opcode },
5107     { VEX_LEN_TABLE (VEX_LEN_0F93_P_2) },
5108     { VEX_LEN_TABLE (VEX_LEN_0F93_P_3) },
5109   },
5110
5111   /* PREFIX_VEX_0F98 */
5112   {
5113     { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) },
5114     { Bad_Opcode },
5115     { VEX_LEN_TABLE (VEX_LEN_0F98_P_2) },
5116   },
5117
5118   /* PREFIX_VEX_0F99 */
5119   {
5120     { VEX_LEN_TABLE (VEX_LEN_0F99_P_0) },
5121     { Bad_Opcode },
5122     { VEX_LEN_TABLE (VEX_LEN_0F99_P_2) },
5123   },
5124
5125   /* PREFIX_VEX_0FC2 */
5126   {
5127     { "vcmpps",         { XM, Vex, EXx, VCMP }, 0 },
5128     { "vcmpss",         { XMScalar, VexScalar, EXxmm_md, VCMP }, 0 },
5129     { "vcmppd",         { XM, Vex, EXx, VCMP }, 0 },
5130     { "vcmpsd",         { XMScalar, VexScalar, EXxmm_mq, VCMP }, 0 },
5131   },
5132
5133   /* PREFIX_VEX_0FC4 */
5134   {
5135     { Bad_Opcode },
5136     { Bad_Opcode },
5137     { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) },
5138   },
5139
5140   /* PREFIX_VEX_0FC5 */
5141   {
5142     { Bad_Opcode },
5143     { Bad_Opcode },
5144     { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) },
5145   },
5146
5147   /* PREFIX_VEX_0FD0 */
5148   {
5149     { Bad_Opcode },
5150     { Bad_Opcode },
5151     { "vaddsubpd",      { XM, Vex, EXx }, 0 },
5152     { "vaddsubps",      { XM, Vex, EXx }, 0 },
5153   },
5154
5155   /* PREFIX_VEX_0FD1 */
5156   {
5157     { Bad_Opcode },
5158     { Bad_Opcode },
5159     { "vpsrlw",         { XM, Vex, EXxmm }, 0 },
5160   },
5161
5162   /* PREFIX_VEX_0FD2 */
5163   {
5164     { Bad_Opcode },
5165     { Bad_Opcode },
5166     { "vpsrld",         { XM, Vex, EXxmm }, 0 },
5167   },
5168
5169   /* PREFIX_VEX_0FD3 */
5170   {
5171     { Bad_Opcode },
5172     { Bad_Opcode },
5173     { "vpsrlq",         { XM, Vex, EXxmm }, 0 },
5174   },
5175
5176   /* PREFIX_VEX_0FD4 */
5177   {
5178     { Bad_Opcode },
5179     { Bad_Opcode },
5180     { "vpaddq",         { XM, Vex, EXx }, 0 },
5181   },
5182
5183   /* PREFIX_VEX_0FD5 */
5184   {
5185     { Bad_Opcode },
5186     { Bad_Opcode },
5187     { "vpmullw",        { XM, Vex, EXx }, 0 },
5188   },
5189
5190   /* PREFIX_VEX_0FD6 */
5191   {
5192     { Bad_Opcode },
5193     { Bad_Opcode },
5194     { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) },
5195   },
5196
5197   /* PREFIX_VEX_0FD7 */
5198   {
5199     { Bad_Opcode },
5200     { Bad_Opcode },
5201     { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) },
5202   },
5203
5204   /* PREFIX_VEX_0FD8 */
5205   {
5206     { Bad_Opcode },
5207     { Bad_Opcode },
5208     { "vpsubusb",       { XM, Vex, EXx }, 0 },
5209   },
5210
5211   /* PREFIX_VEX_0FD9 */
5212   {
5213     { Bad_Opcode },
5214     { Bad_Opcode },
5215     { "vpsubusw",       { XM, Vex, EXx }, 0 },
5216   },
5217
5218   /* PREFIX_VEX_0FDA */
5219   {
5220     { Bad_Opcode },
5221     { Bad_Opcode },
5222     { "vpminub",        { XM, Vex, EXx }, 0 },
5223   },
5224
5225   /* PREFIX_VEX_0FDB */
5226   {
5227     { Bad_Opcode },
5228     { Bad_Opcode },
5229     { "vpand",          { XM, Vex, EXx }, 0 },
5230   },
5231
5232   /* PREFIX_VEX_0FDC */
5233   {
5234     { Bad_Opcode },
5235     { Bad_Opcode },
5236     { "vpaddusb",       { XM, Vex, EXx }, 0 },
5237   },
5238
5239   /* PREFIX_VEX_0FDD */
5240   {
5241     { Bad_Opcode },
5242     { Bad_Opcode },
5243     { "vpaddusw",       { XM, Vex, EXx }, 0 },
5244   },
5245
5246   /* PREFIX_VEX_0FDE */
5247   {
5248     { Bad_Opcode },
5249     { Bad_Opcode },
5250     { "vpmaxub",        { XM, Vex, EXx }, 0 },
5251   },
5252
5253   /* PREFIX_VEX_0FDF */
5254   {
5255     { Bad_Opcode },
5256     { Bad_Opcode },
5257     { "vpandn",         { XM, Vex, EXx }, 0 },
5258   },
5259
5260   /* PREFIX_VEX_0FE0 */
5261   {
5262     { Bad_Opcode },
5263     { Bad_Opcode },
5264     { "vpavgb",         { XM, Vex, EXx }, 0 },
5265   },
5266
5267   /* PREFIX_VEX_0FE1 */
5268   {
5269     { Bad_Opcode },
5270     { Bad_Opcode },
5271     { "vpsraw",         { XM, Vex, EXxmm }, 0 },
5272   },
5273
5274   /* PREFIX_VEX_0FE2 */
5275   {
5276     { Bad_Opcode },
5277     { Bad_Opcode },
5278     { "vpsrad",         { XM, Vex, EXxmm }, 0 },
5279   },
5280
5281   /* PREFIX_VEX_0FE3 */
5282   {
5283     { Bad_Opcode },
5284     { Bad_Opcode },
5285     { "vpavgw",         { XM, Vex, EXx }, 0 },
5286   },
5287
5288   /* PREFIX_VEX_0FE4 */
5289   {
5290     { Bad_Opcode },
5291     { Bad_Opcode },
5292     { "vpmulhuw",       { XM, Vex, EXx }, 0 },
5293   },
5294
5295   /* PREFIX_VEX_0FE5 */
5296   {
5297     { Bad_Opcode },
5298     { Bad_Opcode },
5299     { "vpmulhw",        { XM, Vex, EXx }, 0 },
5300   },
5301
5302   /* PREFIX_VEX_0FE6 */
5303   {
5304     { Bad_Opcode },
5305     { "vcvtdq2pd",      { XM, EXxmmq }, 0 },
5306     { "vcvttpd2dq%XY",  { XMM, EXx }, 0 },
5307     { "vcvtpd2dq%XY",   { XMM, EXx }, 0 },
5308   },
5309
5310   /* PREFIX_VEX_0FE7 */
5311   {
5312     { Bad_Opcode },
5313     { Bad_Opcode },
5314     { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) },
5315   },
5316
5317   /* PREFIX_VEX_0FE8 */
5318   {
5319     { Bad_Opcode },
5320     { Bad_Opcode },
5321     { "vpsubsb",        { XM, Vex, EXx }, 0 },
5322   },
5323
5324   /* PREFIX_VEX_0FE9 */
5325   {
5326     { Bad_Opcode },
5327     { Bad_Opcode },
5328     { "vpsubsw",        { XM, Vex, EXx }, 0 },
5329   },
5330
5331   /* PREFIX_VEX_0FEA */
5332   {
5333     { Bad_Opcode },
5334     { Bad_Opcode },
5335     { "vpminsw",        { XM, Vex, EXx }, 0 },
5336   },
5337
5338   /* PREFIX_VEX_0FEB */
5339   {
5340     { Bad_Opcode },
5341     { Bad_Opcode },
5342     { "vpor",           { XM, Vex, EXx }, 0 },
5343   },
5344
5345   /* PREFIX_VEX_0FEC */
5346   {
5347     { Bad_Opcode },
5348     { Bad_Opcode },
5349     { "vpaddsb",        { XM, Vex, EXx }, 0 },
5350   },
5351
5352   /* PREFIX_VEX_0FED */
5353   {
5354     { Bad_Opcode },
5355     { Bad_Opcode },
5356     { "vpaddsw",        { XM, Vex, EXx }, 0 },
5357   },
5358
5359   /* PREFIX_VEX_0FEE */
5360   {
5361     { Bad_Opcode },
5362     { Bad_Opcode },
5363     { "vpmaxsw",        { XM, Vex, EXx }, 0 },
5364   },
5365
5366   /* PREFIX_VEX_0FEF */
5367   {
5368     { Bad_Opcode },
5369     { Bad_Opcode },
5370     { "vpxor",          { XM, Vex, EXx }, 0 },
5371   },
5372
5373   /* PREFIX_VEX_0FF0 */
5374   {
5375     { Bad_Opcode },
5376     { Bad_Opcode },
5377     { Bad_Opcode },
5378     { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
5379   },
5380
5381   /* PREFIX_VEX_0FF1 */
5382   {
5383     { Bad_Opcode },
5384     { Bad_Opcode },
5385     { "vpsllw",         { XM, Vex, EXxmm }, 0 },
5386   },
5387
5388   /* PREFIX_VEX_0FF2 */
5389   {
5390     { Bad_Opcode },
5391     { Bad_Opcode },
5392     { "vpslld",         { XM, Vex, EXxmm }, 0 },
5393   },
5394
5395   /* PREFIX_VEX_0FF3 */
5396   {
5397     { Bad_Opcode },
5398     { Bad_Opcode },
5399     { "vpsllq",         { XM, Vex, EXxmm }, 0 },
5400   },
5401
5402   /* PREFIX_VEX_0FF4 */
5403   {
5404     { Bad_Opcode },
5405     { Bad_Opcode },
5406     { "vpmuludq",       { XM, Vex, EXx }, 0 },
5407   },
5408
5409   /* PREFIX_VEX_0FF5 */
5410   {
5411     { Bad_Opcode },
5412     { Bad_Opcode },
5413     { "vpmaddwd",       { XM, Vex, EXx }, 0 },
5414   },
5415
5416   /* PREFIX_VEX_0FF6 */
5417   {
5418     { Bad_Opcode },
5419     { Bad_Opcode },
5420     { "vpsadbw",        { XM, Vex, EXx }, 0 },
5421   },
5422
5423   /* PREFIX_VEX_0FF7 */
5424   {
5425     { Bad_Opcode },
5426     { Bad_Opcode },
5427     { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) },
5428   },
5429
5430   /* PREFIX_VEX_0FF8 */
5431   {
5432     { Bad_Opcode },
5433     { Bad_Opcode },
5434     { "vpsubb",         { XM, Vex, EXx }, 0 },
5435   },
5436
5437   /* PREFIX_VEX_0FF9 */
5438   {
5439     { Bad_Opcode },
5440     { Bad_Opcode },
5441     { "vpsubw",         { XM, Vex, EXx }, 0 },
5442   },
5443
5444   /* PREFIX_VEX_0FFA */
5445   {
5446     { Bad_Opcode },
5447     { Bad_Opcode },
5448     { "vpsubd",         { XM, Vex, EXx }, 0 },
5449   },
5450
5451   /* PREFIX_VEX_0FFB */
5452   {
5453     { Bad_Opcode },
5454     { Bad_Opcode },
5455     { "vpsubq",         { XM, Vex, EXx }, 0 },
5456   },
5457
5458   /* PREFIX_VEX_0FFC */
5459   {
5460     { Bad_Opcode },
5461     { Bad_Opcode },
5462     { "vpaddb",         { XM, Vex, EXx }, 0 },
5463   },
5464
5465   /* PREFIX_VEX_0FFD */
5466   {
5467     { Bad_Opcode },
5468     { Bad_Opcode },
5469     { "vpaddw",         { XM, Vex, EXx }, 0 },
5470   },
5471
5472   /* PREFIX_VEX_0FFE */
5473   {
5474     { Bad_Opcode },
5475     { Bad_Opcode },
5476     { "vpaddd",         { XM, Vex, EXx }, 0 },
5477   },
5478
5479   /* PREFIX_VEX_0F3800 */
5480   {
5481     { Bad_Opcode },
5482     { Bad_Opcode },
5483     { "vpshufb",        { XM, Vex, EXx }, 0 },
5484   },
5485
5486   /* PREFIX_VEX_0F3801 */
5487   {
5488     { Bad_Opcode },
5489     { Bad_Opcode },
5490     { "vphaddw",        { XM, Vex, EXx }, 0 },
5491   },
5492
5493   /* PREFIX_VEX_0F3802 */
5494   {
5495     { Bad_Opcode },
5496     { Bad_Opcode },
5497     { "vphaddd",        { XM, Vex, EXx }, 0 },
5498   },
5499
5500   /* PREFIX_VEX_0F3803 */
5501   {
5502     { Bad_Opcode },
5503     { Bad_Opcode },
5504     { "vphaddsw",       { XM, Vex, EXx }, 0 },
5505   },
5506
5507   /* PREFIX_VEX_0F3804 */
5508   {
5509     { Bad_Opcode },
5510     { Bad_Opcode },
5511     { "vpmaddubsw",     { XM, Vex, EXx }, 0 },
5512   },
5513
5514   /* PREFIX_VEX_0F3805 */
5515   {
5516     { Bad_Opcode },
5517     { Bad_Opcode },
5518     { "vphsubw",        { XM, Vex, EXx }, 0 },
5519   },
5520
5521   /* PREFIX_VEX_0F3806 */
5522   {
5523     { Bad_Opcode },
5524     { Bad_Opcode },
5525     { "vphsubd",        { XM, Vex, EXx }, 0 },
5526   },
5527
5528   /* PREFIX_VEX_0F3807 */
5529   {
5530     { Bad_Opcode },
5531     { Bad_Opcode },
5532     { "vphsubsw",       { XM, Vex, EXx }, 0 },
5533   },
5534
5535   /* PREFIX_VEX_0F3808 */
5536   {
5537     { Bad_Opcode },
5538     { Bad_Opcode },
5539     { "vpsignb",        { XM, Vex, EXx }, 0 },
5540   },
5541
5542   /* PREFIX_VEX_0F3809 */
5543   {
5544     { Bad_Opcode },
5545     { Bad_Opcode },
5546     { "vpsignw",        { XM, Vex, EXx }, 0 },
5547   },
5548
5549   /* PREFIX_VEX_0F380A */
5550   {
5551     { Bad_Opcode },
5552     { Bad_Opcode },
5553     { "vpsignd",        { XM, Vex, EXx }, 0 },
5554   },
5555
5556   /* PREFIX_VEX_0F380B */
5557   {
5558     { Bad_Opcode },
5559     { Bad_Opcode },
5560     { "vpmulhrsw",      { XM, Vex, EXx }, 0 },
5561   },
5562
5563   /* PREFIX_VEX_0F380C */
5564   {
5565     { Bad_Opcode },
5566     { Bad_Opcode },
5567     { VEX_W_TABLE (VEX_W_0F380C_P_2) },
5568   },
5569
5570   /* PREFIX_VEX_0F380D */
5571   {
5572     { Bad_Opcode },
5573     { Bad_Opcode },
5574     { VEX_W_TABLE (VEX_W_0F380D_P_2) },
5575   },
5576
5577   /* PREFIX_VEX_0F380E */
5578   {
5579     { Bad_Opcode },
5580     { Bad_Opcode },
5581     { VEX_W_TABLE (VEX_W_0F380E_P_2) },
5582   },
5583
5584   /* PREFIX_VEX_0F380F */
5585   {
5586     { Bad_Opcode },
5587     { Bad_Opcode },
5588     { VEX_W_TABLE (VEX_W_0F380F_P_2) },
5589   },
5590
5591   /* PREFIX_VEX_0F3813 */
5592   {
5593     { Bad_Opcode },
5594     { Bad_Opcode },
5595     { "vcvtph2ps", { XM, EXxmmq }, 0 },
5596   },
5597
5598   /* PREFIX_VEX_0F3816 */
5599   {
5600     { Bad_Opcode },
5601     { Bad_Opcode },
5602     { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) },
5603   },
5604
5605   /* PREFIX_VEX_0F3817 */
5606   {
5607     { Bad_Opcode },
5608     { Bad_Opcode },
5609     { "vptest",         { XM, EXx }, 0 },
5610   },
5611
5612   /* PREFIX_VEX_0F3818 */
5613   {
5614     { Bad_Opcode },
5615     { Bad_Opcode },
5616     { VEX_W_TABLE (VEX_W_0F3818_P_2) },
5617   },
5618
5619   /* PREFIX_VEX_0F3819 */
5620   {
5621     { Bad_Opcode },
5622     { Bad_Opcode },
5623     { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) },
5624   },
5625
5626   /* PREFIX_VEX_0F381A */
5627   {
5628     { Bad_Opcode },
5629     { Bad_Opcode },
5630     { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) },
5631   },
5632
5633   /* PREFIX_VEX_0F381C */
5634   {
5635     { Bad_Opcode },
5636     { Bad_Opcode },
5637     { "vpabsb",         { XM, EXx }, 0 },
5638   },
5639
5640   /* PREFIX_VEX_0F381D */
5641   {
5642     { Bad_Opcode },
5643     { Bad_Opcode },
5644     { "vpabsw",         { XM, EXx }, 0 },
5645   },
5646
5647   /* PREFIX_VEX_0F381E */
5648   {
5649     { Bad_Opcode },
5650     { Bad_Opcode },
5651     { "vpabsd",         { XM, EXx }, 0 },
5652   },
5653
5654   /* PREFIX_VEX_0F3820 */
5655   {
5656     { Bad_Opcode },
5657     { Bad_Opcode },
5658     { "vpmovsxbw",      { XM, EXxmmq }, 0 },
5659   },
5660
5661   /* PREFIX_VEX_0F3821 */
5662   {
5663     { Bad_Opcode },
5664     { Bad_Opcode },
5665     { "vpmovsxbd",      { XM, EXxmmqd }, 0 },
5666   },
5667
5668   /* PREFIX_VEX_0F3822 */
5669   {
5670     { Bad_Opcode },
5671     { Bad_Opcode },
5672     { "vpmovsxbq",      { XM, EXxmmdw }, 0 },
5673   },
5674
5675   /* PREFIX_VEX_0F3823 */
5676   {
5677     { Bad_Opcode },
5678     { Bad_Opcode },
5679     { "vpmovsxwd",      { XM, EXxmmq }, 0 },
5680   },
5681
5682   /* PREFIX_VEX_0F3824 */
5683   {
5684     { Bad_Opcode },
5685     { Bad_Opcode },
5686     { "vpmovsxwq",      { XM, EXxmmqd }, 0 },
5687   },
5688
5689   /* PREFIX_VEX_0F3825 */
5690   {
5691     { Bad_Opcode },
5692     { Bad_Opcode },
5693     { "vpmovsxdq",      { XM, EXxmmq }, 0 },
5694   },
5695
5696   /* PREFIX_VEX_0F3828 */
5697   {
5698     { Bad_Opcode },
5699     { Bad_Opcode },
5700     { "vpmuldq",        { XM, Vex, EXx }, 0 },
5701   },
5702
5703   /* PREFIX_VEX_0F3829 */
5704   {
5705     { Bad_Opcode },
5706     { Bad_Opcode },
5707     { "vpcmpeqq",       { XM, Vex, EXx }, 0 },
5708   },
5709
5710   /* PREFIX_VEX_0F382A */
5711   {
5712     { Bad_Opcode },
5713     { Bad_Opcode },
5714     { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) },
5715   },
5716
5717   /* PREFIX_VEX_0F382B */
5718   {
5719     { Bad_Opcode },
5720     { Bad_Opcode },
5721     { "vpackusdw",      { XM, Vex, EXx }, 0 },
5722   },
5723
5724   /* PREFIX_VEX_0F382C */
5725   {
5726     { Bad_Opcode },
5727     { Bad_Opcode },
5728      { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) },
5729   },
5730
5731   /* PREFIX_VEX_0F382D */
5732   {
5733     { Bad_Opcode },
5734     { Bad_Opcode },
5735      { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) },
5736   },
5737
5738   /* PREFIX_VEX_0F382E */
5739   {
5740     { Bad_Opcode },
5741     { Bad_Opcode },
5742      { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) },
5743   },
5744
5745   /* PREFIX_VEX_0F382F */
5746   {
5747     { Bad_Opcode },
5748     { Bad_Opcode },
5749      { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) },
5750   },
5751
5752   /* PREFIX_VEX_0F3830 */
5753   {
5754     { Bad_Opcode },
5755     { Bad_Opcode },
5756     { "vpmovzxbw",      { XM, EXxmmq }, 0 },
5757   },
5758
5759   /* PREFIX_VEX_0F3831 */
5760   {
5761     { Bad_Opcode },
5762     { Bad_Opcode },
5763     { "vpmovzxbd",      { XM, EXxmmqd }, 0 },
5764   },
5765
5766   /* PREFIX_VEX_0F3832 */
5767   {
5768     { Bad_Opcode },
5769     { Bad_Opcode },
5770     { "vpmovzxbq",      { XM, EXxmmdw }, 0 },
5771   },
5772
5773   /* PREFIX_VEX_0F3833 */
5774   {
5775     { Bad_Opcode },
5776     { Bad_Opcode },
5777     { "vpmovzxwd",      { XM, EXxmmq }, 0 },
5778   },
5779
5780   /* PREFIX_VEX_0F3834 */
5781   {
5782     { Bad_Opcode },
5783     { Bad_Opcode },
5784     { "vpmovzxwq",      { XM, EXxmmqd }, 0 },
5785   },
5786
5787   /* PREFIX_VEX_0F3835 */
5788   {
5789     { Bad_Opcode },
5790     { Bad_Opcode },
5791     { "vpmovzxdq",      { XM, EXxmmq }, 0 },
5792   },
5793
5794   /* PREFIX_VEX_0F3836 */
5795   {
5796     { Bad_Opcode },
5797     { Bad_Opcode },
5798     { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) },
5799   },
5800
5801   /* PREFIX_VEX_0F3837 */
5802   {
5803     { Bad_Opcode },
5804     { Bad_Opcode },
5805     { "vpcmpgtq",       { XM, Vex, EXx }, 0 },
5806   },
5807
5808   /* PREFIX_VEX_0F3838 */
5809   {
5810     { Bad_Opcode },
5811     { Bad_Opcode },
5812     { "vpminsb",        { XM, Vex, EXx }, 0 },
5813   },
5814
5815   /* PREFIX_VEX_0F3839 */
5816   {
5817     { Bad_Opcode },
5818     { Bad_Opcode },
5819     { "vpminsd",        { XM, Vex, EXx }, 0 },
5820   },
5821
5822   /* PREFIX_VEX_0F383A */
5823   {
5824     { Bad_Opcode },
5825     { Bad_Opcode },
5826     { "vpminuw",        { XM, Vex, EXx }, 0 },
5827   },
5828
5829   /* PREFIX_VEX_0F383B */
5830   {
5831     { Bad_Opcode },
5832     { Bad_Opcode },
5833     { "vpminud",        { XM, Vex, EXx }, 0 },
5834   },
5835
5836   /* PREFIX_VEX_0F383C */
5837   {
5838     { Bad_Opcode },
5839     { Bad_Opcode },
5840     { "vpmaxsb",        { XM, Vex, EXx }, 0 },
5841   },
5842
5843   /* PREFIX_VEX_0F383D */
5844   {
5845     { Bad_Opcode },
5846     { Bad_Opcode },
5847     { "vpmaxsd",        { XM, Vex, EXx }, 0 },
5848   },
5849
5850   /* PREFIX_VEX_0F383E */
5851   {
5852     { Bad_Opcode },
5853     { Bad_Opcode },
5854     { "vpmaxuw",        { XM, Vex, EXx }, 0 },
5855   },
5856
5857   /* PREFIX_VEX_0F383F */
5858   {
5859     { Bad_Opcode },
5860     { Bad_Opcode },
5861     { "vpmaxud",        { XM, Vex, EXx }, 0 },
5862   },
5863
5864   /* PREFIX_VEX_0F3840 */
5865   {
5866     { Bad_Opcode },
5867     { Bad_Opcode },
5868     { "vpmulld",        { XM, Vex, EXx }, 0 },
5869   },
5870
5871   /* PREFIX_VEX_0F3841 */
5872   {
5873     { Bad_Opcode },
5874     { Bad_Opcode },
5875     { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) },
5876   },
5877
5878   /* PREFIX_VEX_0F3845 */
5879   {
5880     { Bad_Opcode },
5881     { Bad_Opcode },
5882     { "vpsrlv%LW", { XM, Vex, EXx }, 0 },
5883   },
5884
5885   /* PREFIX_VEX_0F3846 */
5886   {
5887     { Bad_Opcode },
5888     { Bad_Opcode },
5889     { VEX_W_TABLE (VEX_W_0F3846_P_2) },
5890   },
5891
5892   /* PREFIX_VEX_0F3847 */
5893   {
5894     { Bad_Opcode },
5895     { Bad_Opcode },
5896     { "vpsllv%LW", { XM, Vex, EXx }, 0 },
5897   },
5898
5899   /* PREFIX_VEX_0F3858 */
5900   {
5901     { Bad_Opcode },
5902     { Bad_Opcode },
5903     { VEX_W_TABLE (VEX_W_0F3858_P_2) },
5904   },
5905
5906   /* PREFIX_VEX_0F3859 */
5907   {
5908     { Bad_Opcode },
5909     { Bad_Opcode },
5910     { VEX_W_TABLE (VEX_W_0F3859_P_2) },
5911   },
5912
5913   /* PREFIX_VEX_0F385A */
5914   {
5915     { Bad_Opcode },
5916     { Bad_Opcode },
5917     { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) },
5918   },
5919
5920   /* PREFIX_VEX_0F3878 */
5921   {
5922     { Bad_Opcode },
5923     { Bad_Opcode },
5924     { VEX_W_TABLE (VEX_W_0F3878_P_2) },
5925   },
5926
5927   /* PREFIX_VEX_0F3879 */
5928   {
5929     { Bad_Opcode },
5930     { Bad_Opcode },
5931     { VEX_W_TABLE (VEX_W_0F3879_P_2) },
5932   },
5933
5934   /* PREFIX_VEX_0F388C */
5935   {
5936     { Bad_Opcode },
5937     { Bad_Opcode },
5938     { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) },
5939   },
5940
5941   /* PREFIX_VEX_0F388E */
5942   {
5943     { Bad_Opcode },
5944     { Bad_Opcode },
5945     { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) },
5946   },
5947
5948   /* PREFIX_VEX_0F3890 */
5949   {
5950     { Bad_Opcode },
5951     { Bad_Opcode },
5952     { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex }, 0 },
5953   },
5954
5955   /* PREFIX_VEX_0F3891 */
5956   {
5957     { Bad_Opcode },
5958     { Bad_Opcode },
5959     { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
5960   },
5961
5962   /* PREFIX_VEX_0F3892 */
5963   {
5964     { Bad_Opcode },
5965     { Bad_Opcode },
5966     { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex }, 0 },
5967   },
5968
5969   /* PREFIX_VEX_0F3893 */
5970   {
5971     { Bad_Opcode },
5972     { Bad_Opcode },
5973     { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
5974   },
5975
5976   /* PREFIX_VEX_0F3896 */
5977   {
5978     { Bad_Opcode },
5979     { Bad_Opcode },
5980     { "vfmaddsub132p%XW", { XM, Vex, EXx }, 0 },
5981   },
5982
5983   /* PREFIX_VEX_0F3897 */
5984   {
5985     { Bad_Opcode },
5986     { Bad_Opcode },
5987     { "vfmsubadd132p%XW", { XM, Vex, EXx }, 0 },
5988   },
5989
5990   /* PREFIX_VEX_0F3898 */
5991   {
5992     { Bad_Opcode },
5993     { Bad_Opcode },
5994     { "vfmadd132p%XW", { XM, Vex, EXx }, 0 },
5995   },
5996
5997   /* PREFIX_VEX_0F3899 */
5998   {
5999     { Bad_Opcode },
6000     { Bad_Opcode },
6001     { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6002   },
6003
6004   /* PREFIX_VEX_0F389A */
6005   {
6006     { Bad_Opcode },
6007     { Bad_Opcode },
6008     { "vfmsub132p%XW", { XM, Vex, EXx }, 0 },
6009   },
6010
6011   /* PREFIX_VEX_0F389B */
6012   {
6013     { Bad_Opcode },
6014     { Bad_Opcode },
6015     { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6016   },
6017
6018   /* PREFIX_VEX_0F389C */
6019   {
6020     { Bad_Opcode },
6021     { Bad_Opcode },
6022     { "vfnmadd132p%XW", { XM, Vex, EXx }, 0 },
6023   },
6024
6025   /* PREFIX_VEX_0F389D */
6026   {
6027     { Bad_Opcode },
6028     { Bad_Opcode },
6029     { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6030   },
6031
6032   /* PREFIX_VEX_0F389E */
6033   {
6034     { Bad_Opcode },
6035     { Bad_Opcode },
6036     { "vfnmsub132p%XW", { XM, Vex, EXx }, 0 },
6037   },
6038
6039   /* PREFIX_VEX_0F389F */
6040   {
6041     { Bad_Opcode },
6042     { Bad_Opcode },
6043     { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6044   },
6045
6046   /* PREFIX_VEX_0F38A6 */
6047   {
6048     { Bad_Opcode },
6049     { Bad_Opcode },
6050     { "vfmaddsub213p%XW", { XM, Vex, EXx }, 0 },
6051     { Bad_Opcode },
6052   },
6053
6054   /* PREFIX_VEX_0F38A7 */
6055   {
6056     { Bad_Opcode },
6057     { Bad_Opcode },
6058     { "vfmsubadd213p%XW", { XM, Vex, EXx }, 0 },
6059   },
6060
6061   /* PREFIX_VEX_0F38A8 */
6062   {
6063     { Bad_Opcode },
6064     { Bad_Opcode },
6065     { "vfmadd213p%XW", { XM, Vex, EXx }, 0 },
6066   },
6067
6068   /* PREFIX_VEX_0F38A9 */
6069   {
6070     { Bad_Opcode },
6071     { Bad_Opcode },
6072     { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6073   },
6074
6075   /* PREFIX_VEX_0F38AA */
6076   {
6077     { Bad_Opcode },
6078     { Bad_Opcode },
6079     { "vfmsub213p%XW", { XM, Vex, EXx }, 0 },
6080   },
6081
6082   /* PREFIX_VEX_0F38AB */
6083   {
6084     { Bad_Opcode },
6085     { Bad_Opcode },
6086     { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6087   },
6088
6089   /* PREFIX_VEX_0F38AC */
6090   {
6091     { Bad_Opcode },
6092     { Bad_Opcode },
6093     { "vfnmadd213p%XW", { XM, Vex, EXx }, 0 },
6094   },
6095
6096   /* PREFIX_VEX_0F38AD */
6097   {
6098     { Bad_Opcode },
6099     { Bad_Opcode },
6100     { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6101   },
6102
6103   /* PREFIX_VEX_0F38AE */
6104   {
6105     { Bad_Opcode },
6106     { Bad_Opcode },
6107     { "vfnmsub213p%XW", { XM, Vex, EXx }, 0 },
6108   },
6109
6110   /* PREFIX_VEX_0F38AF */
6111   {
6112     { Bad_Opcode },
6113     { Bad_Opcode },
6114     { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6115   },
6116
6117   /* PREFIX_VEX_0F38B6 */
6118   {
6119     { Bad_Opcode },
6120     { Bad_Opcode },
6121     { "vfmaddsub231p%XW", { XM, Vex, EXx }, 0 },
6122   },
6123
6124   /* PREFIX_VEX_0F38B7 */
6125   {
6126     { Bad_Opcode },
6127     { Bad_Opcode },
6128     { "vfmsubadd231p%XW", { XM, Vex, EXx }, 0 },
6129   },
6130
6131   /* PREFIX_VEX_0F38B8 */
6132   {
6133     { Bad_Opcode },
6134     { Bad_Opcode },
6135     { "vfmadd231p%XW", { XM, Vex, EXx }, 0 },
6136   },
6137
6138   /* PREFIX_VEX_0F38B9 */
6139   {
6140     { Bad_Opcode },
6141     { Bad_Opcode },
6142     { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6143   },
6144
6145   /* PREFIX_VEX_0F38BA */
6146   {
6147     { Bad_Opcode },
6148     { Bad_Opcode },
6149     { "vfmsub231p%XW", { XM, Vex, EXx }, 0 },
6150   },
6151
6152   /* PREFIX_VEX_0F38BB */
6153   {
6154     { Bad_Opcode },
6155     { Bad_Opcode },
6156     { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6157   },
6158
6159   /* PREFIX_VEX_0F38BC */
6160   {
6161     { Bad_Opcode },
6162     { Bad_Opcode },
6163     { "vfnmadd231p%XW", { XM, Vex, EXx }, 0 },
6164   },
6165
6166   /* PREFIX_VEX_0F38BD */
6167   {
6168     { Bad_Opcode },
6169     { Bad_Opcode },
6170     { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6171   },
6172
6173   /* PREFIX_VEX_0F38BE */
6174   {
6175     { Bad_Opcode },
6176     { Bad_Opcode },
6177     { "vfnmsub231p%XW", { XM, Vex, EXx }, 0 },
6178   },
6179
6180   /* PREFIX_VEX_0F38BF */
6181   {
6182     { Bad_Opcode },
6183     { Bad_Opcode },
6184     { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6185   },
6186
6187   /* PREFIX_VEX_0F38CF */
6188   {
6189     { Bad_Opcode },
6190     { Bad_Opcode },
6191     { VEX_W_TABLE (VEX_W_0F38CF_P_2) },
6192   },
6193
6194   /* PREFIX_VEX_0F38DB */
6195   {
6196     { Bad_Opcode },
6197     { Bad_Opcode },
6198     { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) },
6199   },
6200
6201   /* PREFIX_VEX_0F38DC */
6202   {
6203     { Bad_Opcode },
6204     { Bad_Opcode },
6205     { "vaesenc",        { XM, Vex, EXx }, 0 },
6206   },
6207
6208   /* PREFIX_VEX_0F38DD */
6209   {
6210     { Bad_Opcode },
6211     { Bad_Opcode },
6212     { "vaesenclast",    { XM, Vex, EXx }, 0 },
6213   },
6214
6215   /* PREFIX_VEX_0F38DE */
6216   {
6217     { Bad_Opcode },
6218     { Bad_Opcode },
6219     { "vaesdec",        { XM, Vex, EXx }, 0 },
6220   },
6221
6222   /* PREFIX_VEX_0F38DF */
6223   {
6224     { Bad_Opcode },
6225     { Bad_Opcode },
6226     { "vaesdeclast",    { XM, Vex, EXx }, 0 },
6227   },
6228
6229   /* PREFIX_VEX_0F38F2 */
6230   {
6231     { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) },
6232   },
6233
6234   /* PREFIX_VEX_0F38F3_REG_1 */
6235   {
6236     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) },
6237   },
6238
6239   /* PREFIX_VEX_0F38F3_REG_2 */
6240   {
6241     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) },
6242   },
6243
6244   /* PREFIX_VEX_0F38F3_REG_3 */
6245   {
6246     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) },
6247   },
6248
6249   /* PREFIX_VEX_0F38F5 */
6250   {
6251     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) },
6252     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) },
6253     { Bad_Opcode },
6254     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) },
6255   },
6256
6257   /* PREFIX_VEX_0F38F6 */
6258   {
6259     { Bad_Opcode },
6260     { Bad_Opcode },
6261     { Bad_Opcode },
6262     { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) },
6263   },
6264
6265   /* PREFIX_VEX_0F38F7 */
6266   {
6267     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) },
6268     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) },
6269     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) },
6270     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) },
6271   },
6272
6273   /* PREFIX_VEX_0F3A00 */
6274   {
6275     { Bad_Opcode },
6276     { Bad_Opcode },
6277     { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) },
6278   },
6279
6280   /* PREFIX_VEX_0F3A01 */
6281   {
6282     { Bad_Opcode },
6283     { Bad_Opcode },
6284     { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) },
6285   },
6286
6287   /* PREFIX_VEX_0F3A02 */
6288   {
6289     { Bad_Opcode },
6290     { Bad_Opcode },
6291     { VEX_W_TABLE (VEX_W_0F3A02_P_2) },
6292   },
6293
6294   /* PREFIX_VEX_0F3A04 */
6295   {
6296     { Bad_Opcode },
6297     { Bad_Opcode },
6298     { VEX_W_TABLE (VEX_W_0F3A04_P_2) },
6299   },
6300
6301   /* PREFIX_VEX_0F3A05 */
6302   {
6303     { Bad_Opcode },
6304     { Bad_Opcode },
6305     { VEX_W_TABLE (VEX_W_0F3A05_P_2) },
6306   },
6307
6308   /* PREFIX_VEX_0F3A06 */
6309   {
6310     { Bad_Opcode },
6311     { Bad_Opcode },
6312     { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) },
6313   },
6314
6315   /* PREFIX_VEX_0F3A08 */
6316   {
6317     { Bad_Opcode },
6318     { Bad_Opcode },
6319     { "vroundps",       { XM, EXx, Ib }, 0 },
6320   },
6321
6322   /* PREFIX_VEX_0F3A09 */
6323   {
6324     { Bad_Opcode },
6325     { Bad_Opcode },
6326     { "vroundpd",       { XM, EXx, Ib }, 0 },
6327   },
6328
6329   /* PREFIX_VEX_0F3A0A */
6330   {
6331     { Bad_Opcode },
6332     { Bad_Opcode },
6333     { "vroundss",       { XMScalar, VexScalar, EXxmm_md, Ib }, 0 },
6334   },
6335
6336   /* PREFIX_VEX_0F3A0B */
6337   {
6338     { Bad_Opcode },
6339     { Bad_Opcode },
6340     { "vroundsd",       { XMScalar, VexScalar, EXxmm_mq, Ib }, 0 },
6341   },
6342
6343   /* PREFIX_VEX_0F3A0C */
6344   {
6345     { Bad_Opcode },
6346     { Bad_Opcode },
6347     { "vblendps",       { XM, Vex, EXx, Ib }, 0 },
6348   },
6349
6350   /* PREFIX_VEX_0F3A0D */
6351   {
6352     { Bad_Opcode },
6353     { Bad_Opcode },
6354     { "vblendpd",       { XM, Vex, EXx, Ib }, 0 },
6355   },
6356
6357   /* PREFIX_VEX_0F3A0E */
6358   {
6359     { Bad_Opcode },
6360     { Bad_Opcode },
6361     { "vpblendw",       { XM, Vex, EXx, Ib }, 0 },
6362   },
6363
6364   /* PREFIX_VEX_0F3A0F */
6365   {
6366     { Bad_Opcode },
6367     { Bad_Opcode },
6368     { "vpalignr",       { XM, Vex, EXx, Ib }, 0 },
6369   },
6370
6371   /* PREFIX_VEX_0F3A14 */
6372   {
6373     { Bad_Opcode },
6374     { Bad_Opcode },
6375     { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) },
6376   },
6377
6378   /* PREFIX_VEX_0F3A15 */
6379   {
6380     { Bad_Opcode },
6381     { Bad_Opcode },
6382     { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) },
6383   },
6384
6385   /* PREFIX_VEX_0F3A16 */
6386   {
6387     { Bad_Opcode },
6388     { Bad_Opcode },
6389     { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) },
6390   },
6391
6392   /* PREFIX_VEX_0F3A17 */
6393   {
6394     { Bad_Opcode },
6395     { Bad_Opcode },
6396     { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) },
6397   },
6398
6399   /* PREFIX_VEX_0F3A18 */
6400   {
6401     { Bad_Opcode },
6402     { Bad_Opcode },
6403     { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) },
6404   },
6405
6406   /* PREFIX_VEX_0F3A19 */
6407   {
6408     { Bad_Opcode },
6409     { Bad_Opcode },
6410     { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) },
6411   },
6412
6413   /* PREFIX_VEX_0F3A1D */
6414   {
6415     { Bad_Opcode },
6416     { Bad_Opcode },
6417     { "vcvtps2ph", { EXxmmq, XM, Ib }, 0 },
6418   },
6419
6420   /* PREFIX_VEX_0F3A20 */
6421   {
6422     { Bad_Opcode },
6423     { Bad_Opcode },
6424     { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) },
6425   },
6426
6427   /* PREFIX_VEX_0F3A21 */
6428   {
6429     { Bad_Opcode },
6430     { Bad_Opcode },
6431     { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) },
6432   },
6433
6434   /* PREFIX_VEX_0F3A22 */
6435   {
6436     { Bad_Opcode },
6437     { Bad_Opcode },
6438     { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) },
6439   },
6440
6441   /* PREFIX_VEX_0F3A30 */
6442   {
6443     { Bad_Opcode },
6444     { Bad_Opcode },
6445     { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2) },
6446   },
6447
6448   /* PREFIX_VEX_0F3A31 */
6449   {
6450     { Bad_Opcode },
6451     { Bad_Opcode },
6452     { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2) },
6453   },
6454
6455   /* PREFIX_VEX_0F3A32 */
6456   {
6457     { Bad_Opcode },
6458     { Bad_Opcode },
6459     { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2) },
6460   },
6461
6462   /* PREFIX_VEX_0F3A33 */
6463   {
6464     { Bad_Opcode },
6465     { Bad_Opcode },
6466     { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2) },
6467   },
6468
6469   /* PREFIX_VEX_0F3A38 */
6470   {
6471     { Bad_Opcode },
6472     { Bad_Opcode },
6473     { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) },
6474   },
6475
6476   /* PREFIX_VEX_0F3A39 */
6477   {
6478     { Bad_Opcode },
6479     { Bad_Opcode },
6480     { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) },
6481   },
6482
6483   /* PREFIX_VEX_0F3A40 */
6484   {
6485     { Bad_Opcode },
6486     { Bad_Opcode },
6487     { "vdpps",          { XM, Vex, EXx, Ib }, 0 },
6488   },
6489
6490   /* PREFIX_VEX_0F3A41 */
6491   {
6492     { Bad_Opcode },
6493     { Bad_Opcode },
6494     { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) },
6495   },
6496
6497   /* PREFIX_VEX_0F3A42 */
6498   {
6499     { Bad_Opcode },
6500     { Bad_Opcode },
6501     { "vmpsadbw",       { XM, Vex, EXx, Ib }, 0 },
6502   },
6503
6504   /* PREFIX_VEX_0F3A44 */
6505   {
6506     { Bad_Opcode },
6507     { Bad_Opcode },
6508     { "vpclmulqdq",     { XM, Vex, EXx, PCLMUL }, 0 },
6509   },
6510
6511   /* PREFIX_VEX_0F3A46 */
6512   {
6513     { Bad_Opcode },
6514     { Bad_Opcode },
6515     { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) },
6516   },
6517
6518   /* PREFIX_VEX_0F3A48 */
6519   {
6520     { Bad_Opcode },
6521     { Bad_Opcode },
6522     { VEX_W_TABLE (VEX_W_0F3A48_P_2) },
6523   },
6524
6525   /* PREFIX_VEX_0F3A49 */
6526   {
6527     { Bad_Opcode },
6528     { Bad_Opcode },
6529     { VEX_W_TABLE (VEX_W_0F3A49_P_2) },
6530   },
6531
6532   /* PREFIX_VEX_0F3A4A */
6533   {
6534     { Bad_Opcode },
6535     { Bad_Opcode },
6536     { VEX_W_TABLE (VEX_W_0F3A4A_P_2) },
6537   },
6538
6539   /* PREFIX_VEX_0F3A4B */
6540   {
6541     { Bad_Opcode },
6542     { Bad_Opcode },
6543     { VEX_W_TABLE (VEX_W_0F3A4B_P_2) },
6544   },
6545
6546   /* PREFIX_VEX_0F3A4C */
6547   {
6548     { Bad_Opcode },
6549     { Bad_Opcode },
6550     { VEX_W_TABLE (VEX_W_0F3A4C_P_2) },
6551   },
6552
6553   /* PREFIX_VEX_0F3A5C */
6554   {
6555     { Bad_Opcode },
6556     { Bad_Opcode },
6557     { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6558   },
6559
6560   /* PREFIX_VEX_0F3A5D */
6561   {
6562     { Bad_Opcode },
6563     { Bad_Opcode },
6564     { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6565   },
6566
6567   /* PREFIX_VEX_0F3A5E */
6568   {
6569     { Bad_Opcode },
6570     { Bad_Opcode },
6571     { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6572   },
6573
6574   /* PREFIX_VEX_0F3A5F */
6575   {
6576     { Bad_Opcode },
6577     { Bad_Opcode },
6578     { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6579   },
6580
6581   /* PREFIX_VEX_0F3A60 */
6582   {
6583     { Bad_Opcode },
6584     { Bad_Opcode },
6585     { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) },
6586     { Bad_Opcode },
6587   },
6588
6589   /* PREFIX_VEX_0F3A61 */
6590   {
6591     { Bad_Opcode },
6592     { Bad_Opcode },
6593     { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) },
6594   },
6595
6596   /* PREFIX_VEX_0F3A62 */
6597   {
6598     { Bad_Opcode },
6599     { Bad_Opcode },
6600     { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) },
6601   },
6602
6603   /* PREFIX_VEX_0F3A63 */
6604   {
6605     { Bad_Opcode },
6606     { Bad_Opcode },
6607     { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) },
6608   },
6609
6610   /* PREFIX_VEX_0F3A68 */
6611   {
6612     { Bad_Opcode },
6613     { Bad_Opcode },
6614     { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6615   },
6616
6617   /* PREFIX_VEX_0F3A69 */
6618   {
6619     { Bad_Opcode },
6620     { Bad_Opcode },
6621     { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6622   },
6623
6624   /* PREFIX_VEX_0F3A6A */
6625   {
6626     { Bad_Opcode },
6627     { Bad_Opcode },
6628     { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) },
6629   },
6630
6631   /* PREFIX_VEX_0F3A6B */
6632   {
6633     { Bad_Opcode },
6634     { Bad_Opcode },
6635     { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) },
6636   },
6637
6638   /* PREFIX_VEX_0F3A6C */
6639   {
6640     { Bad_Opcode },
6641     { Bad_Opcode },
6642     { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6643   },
6644
6645   /* PREFIX_VEX_0F3A6D */
6646   {
6647     { Bad_Opcode },
6648     { Bad_Opcode },
6649     { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6650   },
6651
6652   /* PREFIX_VEX_0F3A6E */
6653   {
6654     { Bad_Opcode },
6655     { Bad_Opcode },
6656     { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) },
6657   },
6658
6659   /* PREFIX_VEX_0F3A6F */
6660   {
6661     { Bad_Opcode },
6662     { Bad_Opcode },
6663     { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) },
6664   },
6665
6666   /* PREFIX_VEX_0F3A78 */
6667   {
6668     { Bad_Opcode },
6669     { Bad_Opcode },
6670     { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6671   },
6672
6673   /* PREFIX_VEX_0F3A79 */
6674   {
6675     { Bad_Opcode },
6676     { Bad_Opcode },
6677     { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6678   },
6679
6680   /* PREFIX_VEX_0F3A7A */
6681   {
6682     { Bad_Opcode },
6683     { Bad_Opcode },
6684     { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) },
6685   },
6686
6687   /* PREFIX_VEX_0F3A7B */
6688   {
6689     { Bad_Opcode },
6690     { Bad_Opcode },
6691     { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) },
6692   },
6693
6694   /* PREFIX_VEX_0F3A7C */
6695   {
6696     { Bad_Opcode },
6697     { Bad_Opcode },
6698     { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6699     { Bad_Opcode },
6700   },
6701
6702   /* PREFIX_VEX_0F3A7D */
6703   {
6704     { Bad_Opcode },
6705     { Bad_Opcode },
6706     { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6707   },
6708
6709   /* PREFIX_VEX_0F3A7E */
6710   {
6711     { Bad_Opcode },
6712     { Bad_Opcode },
6713     { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) },
6714   },
6715
6716   /* PREFIX_VEX_0F3A7F */
6717   {
6718     { Bad_Opcode },
6719     { Bad_Opcode },
6720     { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) },
6721   },
6722
6723   /* PREFIX_VEX_0F3ACE */
6724   {
6725     { Bad_Opcode },
6726     { Bad_Opcode },
6727     { VEX_W_TABLE (VEX_W_0F3ACE_P_2) },
6728   },
6729
6730   /* PREFIX_VEX_0F3ACF */
6731   {
6732     { Bad_Opcode },
6733     { Bad_Opcode },
6734     { VEX_W_TABLE (VEX_W_0F3ACF_P_2) },
6735   },
6736
6737   /* PREFIX_VEX_0F3ADF */
6738   {
6739     { Bad_Opcode },
6740     { Bad_Opcode },
6741     { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) },
6742   },
6743
6744   /* PREFIX_VEX_0F3AF0 */
6745   {
6746     { Bad_Opcode },
6747     { Bad_Opcode },
6748     { Bad_Opcode },
6749     { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) },
6750   },
6751
6752 #include "i386-dis-evex-prefix.h"
6753 };
6754
6755 static const struct dis386 x86_64_table[][2] = {
6756   /* X86_64_06 */
6757   {
6758     { "pushP", { es }, 0 },
6759   },
6760
6761   /* X86_64_07 */
6762   {
6763     { "popP", { es }, 0 },
6764   },
6765
6766   /* X86_64_0E */
6767   {
6768     { "pushP", { cs }, 0 },
6769   },
6770
6771   /* X86_64_16 */
6772   {
6773     { "pushP", { ss }, 0 },
6774   },
6775
6776   /* X86_64_17 */
6777   {
6778     { "popP", { ss }, 0 },
6779   },
6780
6781   /* X86_64_1E */
6782   {
6783     { "pushP", { ds }, 0 },
6784   },
6785
6786   /* X86_64_1F */
6787   {
6788     { "popP", { ds }, 0 },
6789   },
6790
6791   /* X86_64_27 */
6792   {
6793     { "daa", { XX }, 0 },
6794   },
6795
6796   /* X86_64_2F */
6797   {
6798     { "das", { XX }, 0 },
6799   },
6800
6801   /* X86_64_37 */
6802   {
6803     { "aaa", { XX }, 0 },
6804   },
6805
6806   /* X86_64_3F */
6807   {
6808     { "aas", { XX }, 0 },
6809   },
6810
6811   /* X86_64_60 */
6812   {
6813     { "pushaP", { XX }, 0 },
6814   },
6815
6816   /* X86_64_61 */
6817   {
6818     { "popaP", { XX }, 0 },
6819   },
6820
6821   /* X86_64_62 */
6822   {
6823     { MOD_TABLE (MOD_62_32BIT) },
6824     { EVEX_TABLE (EVEX_0F) },
6825   },
6826
6827   /* X86_64_63 */
6828   {
6829     { "arpl", { Ew, Gw }, 0 },
6830     { "movs", { { OP_G, movsxd_mode }, { MOVSXD_Fixup, movsxd_mode } }, 0 },
6831   },
6832
6833   /* X86_64_6D */
6834   {
6835     { "ins{R|}", { Yzr, indirDX }, 0 },
6836     { "ins{G|}", { Yzr, indirDX }, 0 },
6837   },
6838
6839   /* X86_64_6F */
6840   {
6841     { "outs{R|}", { indirDXr, Xz }, 0 },
6842     { "outs{G|}", { indirDXr, Xz }, 0 },
6843   },
6844
6845   /* X86_64_82 */
6846   {
6847     /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode.  */
6848     { REG_TABLE (REG_80) },
6849   },
6850
6851   /* X86_64_9A */
6852   {
6853     { "{l|}call{T|}", { Ap }, 0 },
6854   },
6855
6856   /* X86_64_C2 */
6857   {
6858     { "retP",           { Iw, BND }, 0 },
6859     { "ret@",           { Iw, BND }, 0 },
6860   },
6861
6862   /* X86_64_C3 */
6863   {
6864     { "retP",           { BND }, 0 },
6865     { "ret@",           { BND }, 0 },
6866   },
6867
6868   /* X86_64_C4 */
6869   {
6870     { MOD_TABLE (MOD_C4_32BIT) },
6871     { VEX_C4_TABLE (VEX_0F) },
6872   },
6873
6874   /* X86_64_C5 */
6875   {
6876     { MOD_TABLE (MOD_C5_32BIT) },
6877     { VEX_C5_TABLE (VEX_0F) },
6878   },
6879
6880   /* X86_64_CE */
6881   {
6882     { "into", { XX }, 0 },
6883   },
6884
6885   /* X86_64_D4 */
6886   {
6887     { "aam", { Ib }, 0 },
6888   },
6889
6890   /* X86_64_D5 */
6891   {
6892     { "aad", { Ib }, 0 },
6893   },
6894
6895   /* X86_64_E8 */
6896   {
6897     { "callP",          { Jv, BND }, 0 },
6898     { "call@",          { Jv, BND }, 0 }
6899   },
6900
6901   /* X86_64_E9 */
6902   {
6903     { "jmpP",           { Jv, BND }, 0 },
6904     { "jmp@",           { Jv, BND }, 0 }
6905   },
6906
6907   /* X86_64_EA */
6908   {
6909     { "{l|}jmp{T|}", { Ap }, 0 },
6910   },
6911
6912   /* X86_64_0F01_REG_0 */
6913   {
6914     { "sgdt{Q|Q}", { M }, 0 },
6915     { "sgdt", { M }, 0 },
6916   },
6917
6918   /* X86_64_0F01_REG_1 */
6919   {
6920     { "sidt{Q|Q}", { M }, 0 },
6921     { "sidt", { M }, 0 },
6922   },
6923
6924   /* X86_64_0F01_REG_2 */
6925   {
6926     { "lgdt{Q|Q}", { M }, 0 },
6927     { "lgdt", { M }, 0 },
6928   },
6929
6930   /* X86_64_0F01_REG_3 */
6931   {
6932     { "lidt{Q|Q}", { M }, 0 },
6933     { "lidt", { M }, 0 },
6934   },
6935 };
6936
6937 static const struct dis386 three_byte_table[][256] = {
6938
6939   /* THREE_BYTE_0F38 */
6940   {
6941     /* 00 */
6942     { "pshufb",         { MX, EM }, PREFIX_OPCODE },
6943     { "phaddw",         { MX, EM }, PREFIX_OPCODE },
6944     { "phaddd",         { MX, EM }, PREFIX_OPCODE },
6945     { "phaddsw",        { MX, EM }, PREFIX_OPCODE },
6946     { "pmaddubsw",      { MX, EM }, PREFIX_OPCODE },
6947     { "phsubw",         { MX, EM }, PREFIX_OPCODE },
6948     { "phsubd",         { MX, EM }, PREFIX_OPCODE },
6949     { "phsubsw",        { MX, EM }, PREFIX_OPCODE },
6950     /* 08 */
6951     { "psignb",         { MX, EM }, PREFIX_OPCODE },
6952     { "psignw",         { MX, EM }, PREFIX_OPCODE },
6953     { "psignd",         { MX, EM }, PREFIX_OPCODE },
6954     { "pmulhrsw",       { MX, EM }, PREFIX_OPCODE },
6955     { Bad_Opcode },
6956     { Bad_Opcode },
6957     { Bad_Opcode },
6958     { Bad_Opcode },
6959     /* 10 */
6960     { PREFIX_TABLE (PREFIX_0F3810) },
6961     { Bad_Opcode },
6962     { Bad_Opcode },
6963     { Bad_Opcode },
6964     { PREFIX_TABLE (PREFIX_0F3814) },
6965     { PREFIX_TABLE (PREFIX_0F3815) },
6966     { Bad_Opcode },
6967     { PREFIX_TABLE (PREFIX_0F3817) },
6968     /* 18 */
6969     { Bad_Opcode },
6970     { Bad_Opcode },
6971     { Bad_Opcode },
6972     { Bad_Opcode },
6973     { "pabsb",          { MX, EM }, PREFIX_OPCODE },
6974     { "pabsw",          { MX, EM }, PREFIX_OPCODE },
6975     { "pabsd",          { MX, EM }, PREFIX_OPCODE },
6976     { Bad_Opcode },
6977     /* 20 */
6978     { PREFIX_TABLE (PREFIX_0F3820) },
6979     { PREFIX_TABLE (PREFIX_0F3821) },
6980     { PREFIX_TABLE (PREFIX_0F3822) },
6981     { PREFIX_TABLE (PREFIX_0F3823) },
6982     { PREFIX_TABLE (PREFIX_0F3824) },
6983     { PREFIX_TABLE (PREFIX_0F3825) },
6984     { Bad_Opcode },
6985     { Bad_Opcode },
6986     /* 28 */
6987     { PREFIX_TABLE (PREFIX_0F3828) },
6988     { PREFIX_TABLE (PREFIX_0F3829) },
6989     { PREFIX_TABLE (PREFIX_0F382A) },
6990     { PREFIX_TABLE (PREFIX_0F382B) },
6991     { Bad_Opcode },
6992     { Bad_Opcode },
6993     { Bad_Opcode },
6994     { Bad_Opcode },
6995     /* 30 */
6996     { PREFIX_TABLE (PREFIX_0F3830) },
6997     { PREFIX_TABLE (PREFIX_0F3831) },
6998     { PREFIX_TABLE (PREFIX_0F3832) },
6999     { PREFIX_TABLE (PREFIX_0F3833) },
7000     { PREFIX_TABLE (PREFIX_0F3834) },
7001     { PREFIX_TABLE (PREFIX_0F3835) },
7002     { Bad_Opcode },
7003     { PREFIX_TABLE (PREFIX_0F3837) },
7004     /* 38 */
7005     { PREFIX_TABLE (PREFIX_0F3838) },
7006     { PREFIX_TABLE (PREFIX_0F3839) },
7007     { PREFIX_TABLE (PREFIX_0F383A) },
7008     { PREFIX_TABLE (PREFIX_0F383B) },
7009     { PREFIX_TABLE (PREFIX_0F383C) },
7010     { PREFIX_TABLE (PREFIX_0F383D) },
7011     { PREFIX_TABLE (PREFIX_0F383E) },
7012     { PREFIX_TABLE (PREFIX_0F383F) },
7013     /* 40 */
7014     { PREFIX_TABLE (PREFIX_0F3840) },
7015     { PREFIX_TABLE (PREFIX_0F3841) },
7016     { Bad_Opcode },
7017     { Bad_Opcode },
7018     { Bad_Opcode },
7019     { Bad_Opcode },
7020     { Bad_Opcode },
7021     { Bad_Opcode },
7022     /* 48 */
7023     { Bad_Opcode },
7024     { Bad_Opcode },
7025     { Bad_Opcode },
7026     { Bad_Opcode },
7027     { Bad_Opcode },
7028     { Bad_Opcode },
7029     { Bad_Opcode },
7030     { Bad_Opcode },
7031     /* 50 */
7032     { Bad_Opcode },
7033     { Bad_Opcode },
7034     { Bad_Opcode },
7035     { Bad_Opcode },
7036     { Bad_Opcode },
7037     { Bad_Opcode },
7038     { Bad_Opcode },
7039     { Bad_Opcode },
7040     /* 58 */
7041     { Bad_Opcode },
7042     { Bad_Opcode },
7043     { Bad_Opcode },
7044     { Bad_Opcode },
7045     { Bad_Opcode },
7046     { Bad_Opcode },
7047     { Bad_Opcode },
7048     { Bad_Opcode },
7049     /* 60 */
7050     { Bad_Opcode },
7051     { Bad_Opcode },
7052     { Bad_Opcode },
7053     { Bad_Opcode },
7054     { Bad_Opcode },
7055     { Bad_Opcode },
7056     { Bad_Opcode },
7057     { Bad_Opcode },
7058     /* 68 */
7059     { Bad_Opcode },
7060     { Bad_Opcode },
7061     { Bad_Opcode },
7062     { Bad_Opcode },
7063     { Bad_Opcode },
7064     { Bad_Opcode },
7065     { Bad_Opcode },
7066     { Bad_Opcode },
7067     /* 70 */
7068     { Bad_Opcode },
7069     { Bad_Opcode },
7070     { Bad_Opcode },
7071     { Bad_Opcode },
7072     { Bad_Opcode },
7073     { Bad_Opcode },
7074     { Bad_Opcode },
7075     { Bad_Opcode },
7076     /* 78 */
7077     { Bad_Opcode },
7078     { Bad_Opcode },
7079     { Bad_Opcode },
7080     { Bad_Opcode },
7081     { Bad_Opcode },
7082     { Bad_Opcode },
7083     { Bad_Opcode },
7084     { Bad_Opcode },
7085     /* 80 */
7086     { PREFIX_TABLE (PREFIX_0F3880) },
7087     { PREFIX_TABLE (PREFIX_0F3881) },
7088     { PREFIX_TABLE (PREFIX_0F3882) },
7089     { Bad_Opcode },
7090     { Bad_Opcode },
7091     { Bad_Opcode },
7092     { Bad_Opcode },
7093     { Bad_Opcode },
7094     /* 88 */
7095     { Bad_Opcode },
7096     { Bad_Opcode },
7097     { Bad_Opcode },
7098     { Bad_Opcode },
7099     { Bad_Opcode },
7100     { Bad_Opcode },
7101     { Bad_Opcode },
7102     { Bad_Opcode },
7103     /* 90 */
7104     { Bad_Opcode },
7105     { Bad_Opcode },
7106     { Bad_Opcode },
7107     { Bad_Opcode },
7108     { Bad_Opcode },
7109     { Bad_Opcode },
7110     { Bad_Opcode },
7111     { Bad_Opcode },
7112     /* 98 */
7113     { Bad_Opcode },
7114     { Bad_Opcode },
7115     { Bad_Opcode },
7116     { Bad_Opcode },
7117     { Bad_Opcode },
7118     { Bad_Opcode },
7119     { Bad_Opcode },
7120     { Bad_Opcode },
7121     /* a0 */
7122     { Bad_Opcode },
7123     { Bad_Opcode },
7124     { Bad_Opcode },
7125     { Bad_Opcode },
7126     { Bad_Opcode },
7127     { Bad_Opcode },
7128     { Bad_Opcode },
7129     { Bad_Opcode },
7130     /* a8 */
7131     { Bad_Opcode },
7132     { Bad_Opcode },
7133     { Bad_Opcode },
7134     { Bad_Opcode },
7135     { Bad_Opcode },
7136     { Bad_Opcode },
7137     { Bad_Opcode },
7138     { Bad_Opcode },
7139     /* b0 */
7140     { Bad_Opcode },
7141     { Bad_Opcode },
7142     { Bad_Opcode },
7143     { Bad_Opcode },
7144     { Bad_Opcode },
7145     { Bad_Opcode },
7146     { Bad_Opcode },
7147     { Bad_Opcode },
7148     /* b8 */
7149     { Bad_Opcode },
7150     { Bad_Opcode },
7151     { Bad_Opcode },
7152     { Bad_Opcode },
7153     { Bad_Opcode },
7154     { Bad_Opcode },
7155     { Bad_Opcode },
7156     { Bad_Opcode },
7157     /* c0 */
7158     { Bad_Opcode },
7159     { Bad_Opcode },
7160     { Bad_Opcode },
7161     { Bad_Opcode },
7162     { Bad_Opcode },
7163     { Bad_Opcode },
7164     { Bad_Opcode },
7165     { Bad_Opcode },
7166     /* c8 */
7167     { PREFIX_TABLE (PREFIX_0F38C8) },
7168     { PREFIX_TABLE (PREFIX_0F38C9) },
7169     { PREFIX_TABLE (PREFIX_0F38CA) },
7170     { PREFIX_TABLE (PREFIX_0F38CB) },
7171     { PREFIX_TABLE (PREFIX_0F38CC) },
7172     { PREFIX_TABLE (PREFIX_0F38CD) },
7173     { Bad_Opcode },
7174     { PREFIX_TABLE (PREFIX_0F38CF) },
7175     /* d0 */
7176     { Bad_Opcode },
7177     { Bad_Opcode },
7178     { Bad_Opcode },
7179     { Bad_Opcode },
7180     { Bad_Opcode },
7181     { Bad_Opcode },
7182     { Bad_Opcode },
7183     { Bad_Opcode },
7184     /* d8 */
7185     { Bad_Opcode },
7186     { Bad_Opcode },
7187     { Bad_Opcode },
7188     { PREFIX_TABLE (PREFIX_0F38DB) },
7189     { PREFIX_TABLE (PREFIX_0F38DC) },
7190     { PREFIX_TABLE (PREFIX_0F38DD) },
7191     { PREFIX_TABLE (PREFIX_0F38DE) },
7192     { PREFIX_TABLE (PREFIX_0F38DF) },
7193     /* e0 */
7194     { Bad_Opcode },
7195     { Bad_Opcode },
7196     { Bad_Opcode },
7197     { Bad_Opcode },
7198     { Bad_Opcode },
7199     { Bad_Opcode },
7200     { Bad_Opcode },
7201     { Bad_Opcode },
7202     /* e8 */
7203     { Bad_Opcode },
7204     { Bad_Opcode },
7205     { Bad_Opcode },
7206     { Bad_Opcode },
7207     { Bad_Opcode },
7208     { Bad_Opcode },
7209     { Bad_Opcode },
7210     { Bad_Opcode },
7211     /* f0 */
7212     { PREFIX_TABLE (PREFIX_0F38F0) },
7213     { PREFIX_TABLE (PREFIX_0F38F1) },
7214     { Bad_Opcode },
7215     { Bad_Opcode },
7216     { Bad_Opcode },
7217     { PREFIX_TABLE (PREFIX_0F38F5) },
7218     { PREFIX_TABLE (PREFIX_0F38F6) },
7219     { Bad_Opcode },
7220     /* f8 */
7221     { PREFIX_TABLE (PREFIX_0F38F8) },
7222     { PREFIX_TABLE (PREFIX_0F38F9) },
7223     { Bad_Opcode },
7224     { Bad_Opcode },
7225     { Bad_Opcode },
7226     { Bad_Opcode },
7227     { Bad_Opcode },
7228     { Bad_Opcode },
7229   },
7230   /* THREE_BYTE_0F3A */
7231   {
7232     /* 00 */
7233     { Bad_Opcode },
7234     { Bad_Opcode },
7235     { Bad_Opcode },
7236     { Bad_Opcode },
7237     { Bad_Opcode },
7238     { Bad_Opcode },
7239     { Bad_Opcode },
7240     { Bad_Opcode },
7241     /* 08 */
7242     { PREFIX_TABLE (PREFIX_0F3A08) },
7243     { PREFIX_TABLE (PREFIX_0F3A09) },
7244     { PREFIX_TABLE (PREFIX_0F3A0A) },
7245     { PREFIX_TABLE (PREFIX_0F3A0B) },
7246     { PREFIX_TABLE (PREFIX_0F3A0C) },
7247     { PREFIX_TABLE (PREFIX_0F3A0D) },
7248     { PREFIX_TABLE (PREFIX_0F3A0E) },
7249     { "palignr",        { MX, EM, Ib }, PREFIX_OPCODE },
7250     /* 10 */
7251     { Bad_Opcode },
7252     { Bad_Opcode },
7253     { Bad_Opcode },
7254     { Bad_Opcode },
7255     { PREFIX_TABLE (PREFIX_0F3A14) },
7256     { PREFIX_TABLE (PREFIX_0F3A15) },
7257     { PREFIX_TABLE (PREFIX_0F3A16) },
7258     { PREFIX_TABLE (PREFIX_0F3A17) },
7259     /* 18 */
7260     { Bad_Opcode },
7261     { Bad_Opcode },
7262     { Bad_Opcode },
7263     { Bad_Opcode },
7264     { Bad_Opcode },
7265     { Bad_Opcode },
7266     { Bad_Opcode },
7267     { Bad_Opcode },
7268     /* 20 */
7269     { PREFIX_TABLE (PREFIX_0F3A20) },
7270     { PREFIX_TABLE (PREFIX_0F3A21) },
7271     { PREFIX_TABLE (PREFIX_0F3A22) },
7272     { Bad_Opcode },
7273     { Bad_Opcode },
7274     { Bad_Opcode },
7275     { Bad_Opcode },
7276     { Bad_Opcode },
7277     /* 28 */
7278     { Bad_Opcode },
7279     { Bad_Opcode },
7280     { Bad_Opcode },
7281     { Bad_Opcode },
7282     { Bad_Opcode },
7283     { Bad_Opcode },
7284     { Bad_Opcode },
7285     { Bad_Opcode },
7286     /* 30 */
7287     { Bad_Opcode },
7288     { Bad_Opcode },
7289     { Bad_Opcode },
7290     { Bad_Opcode },
7291     { Bad_Opcode },
7292     { Bad_Opcode },
7293     { Bad_Opcode },
7294     { Bad_Opcode },
7295     /* 38 */
7296     { Bad_Opcode },
7297     { Bad_Opcode },
7298     { Bad_Opcode },
7299     { Bad_Opcode },
7300     { Bad_Opcode },
7301     { Bad_Opcode },
7302     { Bad_Opcode },
7303     { Bad_Opcode },
7304     /* 40 */
7305     { PREFIX_TABLE (PREFIX_0F3A40) },
7306     { PREFIX_TABLE (PREFIX_0F3A41) },
7307     { PREFIX_TABLE (PREFIX_0F3A42) },
7308     { Bad_Opcode },
7309     { PREFIX_TABLE (PREFIX_0F3A44) },
7310     { Bad_Opcode },
7311     { Bad_Opcode },
7312     { Bad_Opcode },
7313     /* 48 */
7314     { Bad_Opcode },
7315     { Bad_Opcode },
7316     { Bad_Opcode },
7317     { Bad_Opcode },
7318     { Bad_Opcode },
7319     { Bad_Opcode },
7320     { Bad_Opcode },
7321     { Bad_Opcode },
7322     /* 50 */
7323     { Bad_Opcode },
7324     { Bad_Opcode },
7325     { Bad_Opcode },
7326     { Bad_Opcode },
7327     { Bad_Opcode },
7328     { Bad_Opcode },
7329     { Bad_Opcode },
7330     { Bad_Opcode },
7331     /* 58 */
7332     { Bad_Opcode },
7333     { Bad_Opcode },
7334     { Bad_Opcode },
7335     { Bad_Opcode },
7336     { Bad_Opcode },
7337     { Bad_Opcode },
7338     { Bad_Opcode },
7339     { Bad_Opcode },
7340     /* 60 */
7341     { PREFIX_TABLE (PREFIX_0F3A60) },
7342     { PREFIX_TABLE (PREFIX_0F3A61) },
7343     { PREFIX_TABLE (PREFIX_0F3A62) },
7344     { PREFIX_TABLE (PREFIX_0F3A63) },
7345     { Bad_Opcode },
7346     { Bad_Opcode },
7347     { Bad_Opcode },
7348     { Bad_Opcode },
7349     /* 68 */
7350     { Bad_Opcode },
7351     { Bad_Opcode },
7352     { Bad_Opcode },
7353     { Bad_Opcode },
7354     { Bad_Opcode },
7355     { Bad_Opcode },
7356     { Bad_Opcode },
7357     { Bad_Opcode },
7358     /* 70 */
7359     { Bad_Opcode },
7360     { Bad_Opcode },
7361     { Bad_Opcode },
7362     { Bad_Opcode },
7363     { Bad_Opcode },
7364     { Bad_Opcode },
7365     { Bad_Opcode },
7366     { Bad_Opcode },
7367     /* 78 */
7368     { Bad_Opcode },
7369     { Bad_Opcode },
7370     { Bad_Opcode },
7371     { Bad_Opcode },
7372     { Bad_Opcode },
7373     { Bad_Opcode },
7374     { Bad_Opcode },
7375     { Bad_Opcode },
7376     /* 80 */
7377     { Bad_Opcode },
7378     { Bad_Opcode },
7379     { Bad_Opcode },
7380     { Bad_Opcode },
7381     { Bad_Opcode },
7382     { Bad_Opcode },
7383     { Bad_Opcode },
7384     { Bad_Opcode },
7385     /* 88 */
7386     { Bad_Opcode },
7387     { Bad_Opcode },
7388     { Bad_Opcode },
7389     { Bad_Opcode },
7390     { Bad_Opcode },
7391     { Bad_Opcode },
7392     { Bad_Opcode },
7393     { Bad_Opcode },
7394     /* 90 */
7395     { Bad_Opcode },
7396     { Bad_Opcode },
7397     { Bad_Opcode },
7398     { Bad_Opcode },
7399     { Bad_Opcode },
7400     { Bad_Opcode },
7401     { Bad_Opcode },
7402     { Bad_Opcode },
7403     /* 98 */
7404     { Bad_Opcode },
7405     { Bad_Opcode },
7406     { Bad_Opcode },
7407     { Bad_Opcode },
7408     { Bad_Opcode },
7409     { Bad_Opcode },
7410     { Bad_Opcode },
7411     { Bad_Opcode },
7412     /* a0 */
7413     { Bad_Opcode },
7414     { Bad_Opcode },
7415     { Bad_Opcode },
7416     { Bad_Opcode },
7417     { Bad_Opcode },
7418     { Bad_Opcode },
7419     { Bad_Opcode },
7420     { Bad_Opcode },
7421     /* a8 */
7422     { Bad_Opcode },
7423     { Bad_Opcode },
7424     { Bad_Opcode },
7425     { Bad_Opcode },
7426     { Bad_Opcode },
7427     { Bad_Opcode },
7428     { Bad_Opcode },
7429     { Bad_Opcode },
7430     /* b0 */
7431     { Bad_Opcode },
7432     { Bad_Opcode },
7433     { Bad_Opcode },
7434     { Bad_Opcode },
7435     { Bad_Opcode },
7436     { Bad_Opcode },
7437     { Bad_Opcode },
7438     { Bad_Opcode },
7439     /* b8 */
7440     { Bad_Opcode },
7441     { Bad_Opcode },
7442     { Bad_Opcode },
7443     { Bad_Opcode },
7444     { Bad_Opcode },
7445     { Bad_Opcode },
7446     { Bad_Opcode },
7447     { Bad_Opcode },
7448     /* c0 */
7449     { Bad_Opcode },
7450     { Bad_Opcode },
7451     { Bad_Opcode },
7452     { Bad_Opcode },
7453     { Bad_Opcode },
7454     { Bad_Opcode },
7455     { Bad_Opcode },
7456     { Bad_Opcode },
7457     /* c8 */
7458     { Bad_Opcode },
7459     { Bad_Opcode },
7460     { Bad_Opcode },
7461     { Bad_Opcode },
7462     { PREFIX_TABLE (PREFIX_0F3ACC) },
7463     { Bad_Opcode },
7464     { PREFIX_TABLE (PREFIX_0F3ACE) },
7465     { PREFIX_TABLE (PREFIX_0F3ACF) },
7466     /* d0 */
7467     { Bad_Opcode },
7468     { Bad_Opcode },
7469     { Bad_Opcode },
7470     { Bad_Opcode },
7471     { Bad_Opcode },
7472     { Bad_Opcode },
7473     { Bad_Opcode },
7474     { Bad_Opcode },
7475     /* d8 */
7476     { Bad_Opcode },
7477     { Bad_Opcode },
7478     { Bad_Opcode },
7479     { Bad_Opcode },
7480     { Bad_Opcode },
7481     { Bad_Opcode },
7482     { Bad_Opcode },
7483     { PREFIX_TABLE (PREFIX_0F3ADF) },
7484     /* e0 */
7485     { Bad_Opcode },
7486     { Bad_Opcode },
7487     { Bad_Opcode },
7488     { Bad_Opcode },
7489     { Bad_Opcode },
7490     { Bad_Opcode },
7491     { Bad_Opcode },
7492     { Bad_Opcode },
7493     /* e8 */
7494     { Bad_Opcode },
7495     { Bad_Opcode },
7496     { Bad_Opcode },
7497     { Bad_Opcode },
7498     { Bad_Opcode },
7499     { Bad_Opcode },
7500     { Bad_Opcode },
7501     { Bad_Opcode },
7502     /* f0 */
7503     { Bad_Opcode },
7504     { Bad_Opcode },
7505     { Bad_Opcode },
7506     { Bad_Opcode },
7507     { Bad_Opcode },
7508     { Bad_Opcode },
7509     { Bad_Opcode },
7510     { Bad_Opcode },
7511     /* f8 */
7512     { Bad_Opcode },
7513     { Bad_Opcode },
7514     { Bad_Opcode },
7515     { Bad_Opcode },
7516     { Bad_Opcode },
7517     { Bad_Opcode },
7518     { Bad_Opcode },
7519     { Bad_Opcode },
7520   },
7521 };
7522
7523 static const struct dis386 xop_table[][256] = {
7524   /* XOP_08 */
7525   {
7526     /* 00 */
7527     { Bad_Opcode },
7528     { Bad_Opcode },
7529     { Bad_Opcode },
7530     { Bad_Opcode },
7531     { Bad_Opcode },
7532     { Bad_Opcode },
7533     { Bad_Opcode },
7534     { Bad_Opcode },
7535     /* 08 */
7536     { Bad_Opcode },
7537     { Bad_Opcode },
7538     { Bad_Opcode },
7539     { Bad_Opcode },
7540     { Bad_Opcode },
7541     { Bad_Opcode },
7542     { Bad_Opcode },
7543     { Bad_Opcode },
7544     /* 10 */
7545     { Bad_Opcode },
7546     { Bad_Opcode },
7547     { Bad_Opcode },
7548     { Bad_Opcode },
7549     { Bad_Opcode },
7550     { Bad_Opcode },
7551     { Bad_Opcode },
7552     { Bad_Opcode },
7553     /* 18 */
7554     { Bad_Opcode },
7555     { Bad_Opcode },
7556     { Bad_Opcode },
7557     { Bad_Opcode },
7558     { Bad_Opcode },
7559     { Bad_Opcode },
7560     { Bad_Opcode },
7561     { Bad_Opcode },
7562     /* 20 */
7563     { Bad_Opcode },
7564     { Bad_Opcode },
7565     { Bad_Opcode },
7566     { Bad_Opcode },
7567     { Bad_Opcode },
7568     { Bad_Opcode },
7569     { Bad_Opcode },
7570     { Bad_Opcode },
7571     /* 28 */
7572     { Bad_Opcode },
7573     { Bad_Opcode },
7574     { Bad_Opcode },
7575     { Bad_Opcode },
7576     { Bad_Opcode },
7577     { Bad_Opcode },
7578     { Bad_Opcode },
7579     { Bad_Opcode },
7580     /* 30 */
7581     { Bad_Opcode },
7582     { Bad_Opcode },
7583     { Bad_Opcode },
7584     { Bad_Opcode },
7585     { Bad_Opcode },
7586     { Bad_Opcode },
7587     { Bad_Opcode },
7588     { Bad_Opcode },
7589     /* 38 */
7590     { Bad_Opcode },
7591     { Bad_Opcode },
7592     { Bad_Opcode },
7593     { Bad_Opcode },
7594     { Bad_Opcode },
7595     { Bad_Opcode },
7596     { Bad_Opcode },
7597     { Bad_Opcode },
7598     /* 40 */
7599     { Bad_Opcode },
7600     { Bad_Opcode },
7601     { Bad_Opcode },
7602     { Bad_Opcode },
7603     { Bad_Opcode },
7604     { Bad_Opcode },
7605     { Bad_Opcode },
7606     { Bad_Opcode },
7607     /* 48 */
7608     { Bad_Opcode },
7609     { Bad_Opcode },
7610     { Bad_Opcode },
7611     { Bad_Opcode },
7612     { Bad_Opcode },
7613     { Bad_Opcode },
7614     { Bad_Opcode },
7615     { Bad_Opcode },
7616     /* 50 */
7617     { Bad_Opcode },
7618     { Bad_Opcode },
7619     { Bad_Opcode },
7620     { Bad_Opcode },
7621     { Bad_Opcode },
7622     { Bad_Opcode },
7623     { Bad_Opcode },
7624     { Bad_Opcode },
7625     /* 58 */
7626     { Bad_Opcode },
7627     { Bad_Opcode },
7628     { Bad_Opcode },
7629     { Bad_Opcode },
7630     { Bad_Opcode },
7631     { Bad_Opcode },
7632     { Bad_Opcode },
7633     { Bad_Opcode },
7634     /* 60 */
7635     { Bad_Opcode },
7636     { Bad_Opcode },
7637     { Bad_Opcode },
7638     { Bad_Opcode },
7639     { Bad_Opcode },
7640     { Bad_Opcode },
7641     { Bad_Opcode },
7642     { Bad_Opcode },
7643     /* 68 */
7644     { Bad_Opcode },
7645     { Bad_Opcode },
7646     { Bad_Opcode },
7647     { Bad_Opcode },
7648     { Bad_Opcode },
7649     { Bad_Opcode },
7650     { Bad_Opcode },
7651     { Bad_Opcode },
7652     /* 70 */
7653     { Bad_Opcode },
7654     { Bad_Opcode },
7655     { Bad_Opcode },
7656     { Bad_Opcode },
7657     { Bad_Opcode },
7658     { Bad_Opcode },
7659     { Bad_Opcode },
7660     { Bad_Opcode },
7661     /* 78 */
7662     { Bad_Opcode },
7663     { Bad_Opcode },
7664     { Bad_Opcode },
7665     { Bad_Opcode },
7666     { Bad_Opcode },
7667     { Bad_Opcode },
7668     { Bad_Opcode },
7669     { Bad_Opcode },
7670     /* 80 */
7671     { Bad_Opcode },
7672     { Bad_Opcode },
7673     { Bad_Opcode },
7674     { Bad_Opcode },
7675     { Bad_Opcode },
7676     { "vpmacssww",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7677     { "vpmacsswd",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7678     { "vpmacssdql",     { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7679     /* 88 */
7680     { Bad_Opcode },
7681     { Bad_Opcode },
7682     { Bad_Opcode },
7683     { Bad_Opcode },
7684     { Bad_Opcode },
7685     { Bad_Opcode },
7686     { "vpmacssdd",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7687     { "vpmacssdqh",     { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7688     /* 90 */
7689     { Bad_Opcode },
7690     { Bad_Opcode },
7691     { Bad_Opcode },
7692     { Bad_Opcode },
7693     { Bad_Opcode },
7694     { "vpmacsww",       { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7695     { "vpmacswd",       { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7696     { "vpmacsdql",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7697     /* 98 */
7698     { Bad_Opcode },
7699     { Bad_Opcode },
7700     { Bad_Opcode },
7701     { Bad_Opcode },
7702     { Bad_Opcode },
7703     { Bad_Opcode },
7704     { "vpmacsdd",       { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7705     { "vpmacsdqh",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7706     /* a0 */
7707     { Bad_Opcode },
7708     { Bad_Opcode },
7709     { "vpcmov",         { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7710     { "vpperm",         { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7711     { Bad_Opcode },
7712     { Bad_Opcode },
7713     { "vpmadcsswd",     { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7714     { Bad_Opcode },
7715     /* a8 */
7716     { Bad_Opcode },
7717     { Bad_Opcode },
7718     { Bad_Opcode },
7719     { Bad_Opcode },
7720     { Bad_Opcode },
7721     { Bad_Opcode },
7722     { Bad_Opcode },
7723     { Bad_Opcode },
7724     /* b0 */
7725     { Bad_Opcode },
7726     { Bad_Opcode },
7727     { Bad_Opcode },
7728     { Bad_Opcode },
7729     { Bad_Opcode },
7730     { Bad_Opcode },
7731     { "vpmadcswd",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7732     { Bad_Opcode },
7733     /* b8 */
7734     { Bad_Opcode },
7735     { Bad_Opcode },
7736     { Bad_Opcode },
7737     { Bad_Opcode },
7738     { Bad_Opcode },
7739     { Bad_Opcode },
7740     { Bad_Opcode },
7741     { Bad_Opcode },
7742     /* c0 */
7743     { "vprotb",         { XM, Vex_2src_1, Ib }, 0 },
7744     { "vprotw",         { XM, Vex_2src_1, Ib }, 0 },
7745     { "vprotd",         { XM, Vex_2src_1, Ib }, 0 },
7746     { "vprotq",         { XM, Vex_2src_1, Ib }, 0 },
7747     { Bad_Opcode },
7748     { Bad_Opcode },
7749     { Bad_Opcode },
7750     { Bad_Opcode },
7751     /* c8 */
7752     { Bad_Opcode },
7753     { Bad_Opcode },
7754     { Bad_Opcode },
7755     { Bad_Opcode },
7756     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
7757     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
7758     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
7759     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
7760     /* d0 */
7761     { Bad_Opcode },
7762     { Bad_Opcode },
7763     { Bad_Opcode },
7764     { Bad_Opcode },
7765     { Bad_Opcode },
7766     { Bad_Opcode },
7767     { Bad_Opcode },
7768     { Bad_Opcode },
7769     /* d8 */
7770     { Bad_Opcode },
7771     { Bad_Opcode },
7772     { Bad_Opcode },
7773     { Bad_Opcode },
7774     { Bad_Opcode },
7775     { Bad_Opcode },
7776     { Bad_Opcode },
7777     { Bad_Opcode },
7778     /* e0 */
7779     { Bad_Opcode },
7780     { Bad_Opcode },
7781     { Bad_Opcode },
7782     { Bad_Opcode },
7783     { Bad_Opcode },
7784     { Bad_Opcode },
7785     { Bad_Opcode },
7786     { Bad_Opcode },
7787     /* e8 */
7788     { Bad_Opcode },
7789     { Bad_Opcode },
7790     { Bad_Opcode },
7791     { Bad_Opcode },
7792     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
7793     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
7794     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
7795     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
7796     /* f0 */
7797     { Bad_Opcode },
7798     { Bad_Opcode },
7799     { Bad_Opcode },
7800     { Bad_Opcode },
7801     { Bad_Opcode },
7802     { Bad_Opcode },
7803     { Bad_Opcode },
7804     { Bad_Opcode },
7805     /* f8 */
7806     { Bad_Opcode },
7807     { Bad_Opcode },
7808     { Bad_Opcode },
7809     { Bad_Opcode },
7810     { Bad_Opcode },
7811     { Bad_Opcode },
7812     { Bad_Opcode },
7813     { Bad_Opcode },
7814   },
7815   /* XOP_09 */
7816   {
7817     /* 00 */
7818     { Bad_Opcode },
7819     { REG_TABLE (REG_XOP_TBM_01) },
7820     { REG_TABLE (REG_XOP_TBM_02) },
7821     { Bad_Opcode },
7822     { Bad_Opcode },
7823     { Bad_Opcode },
7824     { Bad_Opcode },
7825     { Bad_Opcode },
7826     /* 08 */
7827     { Bad_Opcode },
7828     { Bad_Opcode },
7829     { Bad_Opcode },
7830     { Bad_Opcode },
7831     { Bad_Opcode },
7832     { Bad_Opcode },
7833     { Bad_Opcode },
7834     { Bad_Opcode },
7835     /* 10 */
7836     { Bad_Opcode },
7837     { Bad_Opcode },
7838     { REG_TABLE (REG_XOP_LWPCB) },
7839     { Bad_Opcode },
7840     { Bad_Opcode },
7841     { Bad_Opcode },
7842     { Bad_Opcode },
7843     { Bad_Opcode },
7844     /* 18 */
7845     { Bad_Opcode },
7846     { Bad_Opcode },
7847     { Bad_Opcode },
7848     { Bad_Opcode },
7849     { Bad_Opcode },
7850     { Bad_Opcode },
7851     { Bad_Opcode },
7852     { Bad_Opcode },
7853     /* 20 */
7854     { Bad_Opcode },
7855     { Bad_Opcode },
7856     { Bad_Opcode },
7857     { Bad_Opcode },
7858     { Bad_Opcode },
7859     { Bad_Opcode },
7860     { Bad_Opcode },
7861     { Bad_Opcode },
7862     /* 28 */
7863     { Bad_Opcode },
7864     { Bad_Opcode },
7865     { Bad_Opcode },
7866     { Bad_Opcode },
7867     { Bad_Opcode },
7868     { Bad_Opcode },
7869     { Bad_Opcode },
7870     { Bad_Opcode },
7871     /* 30 */
7872     { Bad_Opcode },
7873     { Bad_Opcode },
7874     { Bad_Opcode },
7875     { Bad_Opcode },
7876     { Bad_Opcode },
7877     { Bad_Opcode },
7878     { Bad_Opcode },
7879     { Bad_Opcode },
7880     /* 38 */
7881     { Bad_Opcode },
7882     { Bad_Opcode },
7883     { Bad_Opcode },
7884     { Bad_Opcode },
7885     { Bad_Opcode },
7886     { Bad_Opcode },
7887     { Bad_Opcode },
7888     { Bad_Opcode },
7889     /* 40 */
7890     { Bad_Opcode },
7891     { Bad_Opcode },
7892     { Bad_Opcode },
7893     { Bad_Opcode },
7894     { Bad_Opcode },
7895     { Bad_Opcode },
7896     { Bad_Opcode },
7897     { Bad_Opcode },
7898     /* 48 */
7899     { Bad_Opcode },
7900     { Bad_Opcode },
7901     { Bad_Opcode },
7902     { Bad_Opcode },
7903     { Bad_Opcode },
7904     { Bad_Opcode },
7905     { Bad_Opcode },
7906     { Bad_Opcode },
7907     /* 50 */
7908     { Bad_Opcode },
7909     { Bad_Opcode },
7910     { Bad_Opcode },
7911     { Bad_Opcode },
7912     { Bad_Opcode },
7913     { Bad_Opcode },
7914     { Bad_Opcode },
7915     { Bad_Opcode },
7916     /* 58 */
7917     { Bad_Opcode },
7918     { Bad_Opcode },
7919     { Bad_Opcode },
7920     { Bad_Opcode },
7921     { Bad_Opcode },
7922     { Bad_Opcode },
7923     { Bad_Opcode },
7924     { Bad_Opcode },
7925     /* 60 */
7926     { Bad_Opcode },
7927     { Bad_Opcode },
7928     { Bad_Opcode },
7929     { Bad_Opcode },
7930     { Bad_Opcode },
7931     { Bad_Opcode },
7932     { Bad_Opcode },
7933     { Bad_Opcode },
7934     /* 68 */
7935     { Bad_Opcode },
7936     { Bad_Opcode },
7937     { Bad_Opcode },
7938     { Bad_Opcode },
7939     { Bad_Opcode },
7940     { Bad_Opcode },
7941     { Bad_Opcode },
7942     { Bad_Opcode },
7943     /* 70 */
7944     { Bad_Opcode },
7945     { Bad_Opcode },
7946     { Bad_Opcode },
7947     { Bad_Opcode },
7948     { Bad_Opcode },
7949     { Bad_Opcode },
7950     { Bad_Opcode },
7951     { Bad_Opcode },
7952     /* 78 */
7953     { Bad_Opcode },
7954     { Bad_Opcode },
7955     { Bad_Opcode },
7956     { Bad_Opcode },
7957     { Bad_Opcode },
7958     { Bad_Opcode },
7959     { Bad_Opcode },
7960     { Bad_Opcode },
7961     /* 80 */
7962     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) },
7963     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) },
7964     { "vfrczss",        { XM, EXd }, 0 },
7965     { "vfrczsd",        { XM, EXq }, 0 },
7966     { Bad_Opcode },
7967     { Bad_Opcode },
7968     { Bad_Opcode },
7969     { Bad_Opcode },
7970     /* 88 */
7971     { Bad_Opcode },
7972     { Bad_Opcode },
7973     { Bad_Opcode },
7974     { Bad_Opcode },
7975     { Bad_Opcode },
7976     { Bad_Opcode },
7977     { Bad_Opcode },
7978     { Bad_Opcode },
7979     /* 90 */
7980     { "vprotb",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7981     { "vprotw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7982     { "vprotd",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7983     { "vprotq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7984     { "vpshlb",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7985     { "vpshlw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7986     { "vpshld",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7987     { "vpshlq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7988     /* 98 */
7989     { "vpshab",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7990     { "vpshaw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7991     { "vpshad",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7992     { "vpshaq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7993     { Bad_Opcode },
7994     { Bad_Opcode },
7995     { Bad_Opcode },
7996     { Bad_Opcode },
7997     /* a0 */
7998     { Bad_Opcode },
7999     { Bad_Opcode },
8000     { Bad_Opcode },
8001     { Bad_Opcode },
8002     { Bad_Opcode },
8003     { Bad_Opcode },
8004     { Bad_Opcode },
8005     { Bad_Opcode },
8006     /* a8 */
8007     { Bad_Opcode },
8008     { Bad_Opcode },
8009     { Bad_Opcode },
8010     { Bad_Opcode },
8011     { Bad_Opcode },
8012     { Bad_Opcode },
8013     { Bad_Opcode },
8014     { Bad_Opcode },
8015     /* b0 */
8016     { Bad_Opcode },
8017     { Bad_Opcode },
8018     { Bad_Opcode },
8019     { Bad_Opcode },
8020     { Bad_Opcode },
8021     { Bad_Opcode },
8022     { Bad_Opcode },
8023     { Bad_Opcode },
8024     /* b8 */
8025     { Bad_Opcode },
8026     { Bad_Opcode },
8027     { Bad_Opcode },
8028     { Bad_Opcode },
8029     { Bad_Opcode },
8030     { Bad_Opcode },
8031     { Bad_Opcode },
8032     { Bad_Opcode },
8033     /* c0 */
8034     { Bad_Opcode },
8035     { "vphaddbw",       { XM, EXxmm }, 0 },
8036     { "vphaddbd",       { XM, EXxmm }, 0 },
8037     { "vphaddbq",       { XM, EXxmm }, 0 },
8038     { Bad_Opcode },
8039     { Bad_Opcode },
8040     { "vphaddwd",       { XM, EXxmm }, 0 },
8041     { "vphaddwq",       { XM, EXxmm }, 0 },
8042     /* c8 */
8043     { Bad_Opcode },
8044     { Bad_Opcode },
8045     { Bad_Opcode },
8046     { "vphadddq",       { XM, EXxmm }, 0 },
8047     { Bad_Opcode },
8048     { Bad_Opcode },
8049     { Bad_Opcode },
8050     { Bad_Opcode },
8051     /* d0 */
8052     { Bad_Opcode },
8053     { "vphaddubw",      { XM, EXxmm }, 0 },
8054     { "vphaddubd",      { XM, EXxmm }, 0 },
8055     { "vphaddubq",      { XM, EXxmm }, 0 },
8056     { Bad_Opcode },
8057     { Bad_Opcode },
8058     { "vphadduwd",      { XM, EXxmm }, 0 },
8059     { "vphadduwq",      { XM, EXxmm }, 0 },
8060     /* d8 */
8061     { Bad_Opcode },
8062     { Bad_Opcode },
8063     { Bad_Opcode },
8064     { "vphaddudq",      { XM, EXxmm }, 0 },
8065     { Bad_Opcode },
8066     { Bad_Opcode },
8067     { Bad_Opcode },
8068     { Bad_Opcode },
8069     /* e0 */
8070     { Bad_Opcode },
8071     { "vphsubbw",       { XM, EXxmm }, 0 },
8072     { "vphsubwd",       { XM, EXxmm }, 0 },
8073     { "vphsubdq",       { XM, EXxmm }, 0 },
8074     { Bad_Opcode },
8075     { Bad_Opcode },
8076     { Bad_Opcode },
8077     { Bad_Opcode },
8078     /* e8 */
8079     { Bad_Opcode },
8080     { Bad_Opcode },
8081     { Bad_Opcode },
8082     { Bad_Opcode },
8083     { Bad_Opcode },
8084     { Bad_Opcode },
8085     { Bad_Opcode },
8086     { Bad_Opcode },
8087     /* f0 */
8088     { Bad_Opcode },
8089     { Bad_Opcode },
8090     { Bad_Opcode },
8091     { Bad_Opcode },
8092     { Bad_Opcode },
8093     { Bad_Opcode },
8094     { Bad_Opcode },
8095     { Bad_Opcode },
8096     /* f8 */
8097     { Bad_Opcode },
8098     { Bad_Opcode },
8099     { Bad_Opcode },
8100     { Bad_Opcode },
8101     { Bad_Opcode },
8102     { Bad_Opcode },
8103     { Bad_Opcode },
8104     { Bad_Opcode },
8105   },
8106   /* XOP_0A */
8107   {
8108     /* 00 */
8109     { Bad_Opcode },
8110     { Bad_Opcode },
8111     { Bad_Opcode },
8112     { Bad_Opcode },
8113     { Bad_Opcode },
8114     { Bad_Opcode },
8115     { Bad_Opcode },
8116     { Bad_Opcode },
8117     /* 08 */
8118     { Bad_Opcode },
8119     { Bad_Opcode },
8120     { Bad_Opcode },
8121     { Bad_Opcode },
8122     { Bad_Opcode },
8123     { Bad_Opcode },
8124     { Bad_Opcode },
8125     { Bad_Opcode },
8126     /* 10 */
8127     { "bextrS", { Gdq, Edq, Id }, 0 },
8128     { Bad_Opcode },
8129     { REG_TABLE (REG_XOP_LWP) },
8130     { Bad_Opcode },
8131     { Bad_Opcode },
8132     { Bad_Opcode },
8133     { Bad_Opcode },
8134     { Bad_Opcode },
8135     /* 18 */
8136     { Bad_Opcode },
8137     { Bad_Opcode },
8138     { Bad_Opcode },
8139     { Bad_Opcode },
8140     { Bad_Opcode },
8141     { Bad_Opcode },
8142     { Bad_Opcode },
8143     { Bad_Opcode },
8144     /* 20 */
8145     { Bad_Opcode },
8146     { Bad_Opcode },
8147     { Bad_Opcode },
8148     { Bad_Opcode },
8149     { Bad_Opcode },
8150     { Bad_Opcode },
8151     { Bad_Opcode },
8152     { Bad_Opcode },
8153     /* 28 */
8154     { Bad_Opcode },
8155     { Bad_Opcode },
8156     { Bad_Opcode },
8157     { Bad_Opcode },
8158     { Bad_Opcode },
8159     { Bad_Opcode },
8160     { Bad_Opcode },
8161     { Bad_Opcode },
8162     /* 30 */
8163     { Bad_Opcode },
8164     { Bad_Opcode },
8165     { Bad_Opcode },
8166     { Bad_Opcode },
8167     { Bad_Opcode },
8168     { Bad_Opcode },
8169     { Bad_Opcode },
8170     { Bad_Opcode },
8171     /* 38 */
8172     { Bad_Opcode },
8173     { Bad_Opcode },
8174     { Bad_Opcode },
8175     { Bad_Opcode },
8176     { Bad_Opcode },
8177     { Bad_Opcode },
8178     { Bad_Opcode },
8179     { Bad_Opcode },
8180     /* 40 */
8181     { Bad_Opcode },
8182     { Bad_Opcode },
8183     { Bad_Opcode },
8184     { Bad_Opcode },
8185     { Bad_Opcode },
8186     { Bad_Opcode },
8187     { Bad_Opcode },
8188     { Bad_Opcode },
8189     /* 48 */
8190     { Bad_Opcode },
8191     { Bad_Opcode },
8192     { Bad_Opcode },
8193     { Bad_Opcode },
8194     { Bad_Opcode },
8195     { Bad_Opcode },
8196     { Bad_Opcode },
8197     { Bad_Opcode },
8198     /* 50 */
8199     { Bad_Opcode },
8200     { Bad_Opcode },
8201     { Bad_Opcode },
8202     { Bad_Opcode },
8203     { Bad_Opcode },
8204     { Bad_Opcode },
8205     { Bad_Opcode },
8206     { Bad_Opcode },
8207     /* 58 */
8208     { Bad_Opcode },
8209     { Bad_Opcode },
8210     { Bad_Opcode },
8211     { Bad_Opcode },
8212     { Bad_Opcode },
8213     { Bad_Opcode },
8214     { Bad_Opcode },
8215     { Bad_Opcode },
8216     /* 60 */
8217     { Bad_Opcode },
8218     { Bad_Opcode },
8219     { Bad_Opcode },
8220     { Bad_Opcode },
8221     { Bad_Opcode },
8222     { Bad_Opcode },
8223     { Bad_Opcode },
8224     { Bad_Opcode },
8225     /* 68 */
8226     { Bad_Opcode },
8227     { Bad_Opcode },
8228     { Bad_Opcode },
8229     { Bad_Opcode },
8230     { Bad_Opcode },
8231     { Bad_Opcode },
8232     { Bad_Opcode },
8233     { Bad_Opcode },
8234     /* 70 */
8235     { Bad_Opcode },
8236     { Bad_Opcode },
8237     { Bad_Opcode },
8238     { Bad_Opcode },
8239     { Bad_Opcode },
8240     { Bad_Opcode },
8241     { Bad_Opcode },
8242     { Bad_Opcode },
8243     /* 78 */
8244     { Bad_Opcode },
8245     { Bad_Opcode },
8246     { Bad_Opcode },
8247     { Bad_Opcode },
8248     { Bad_Opcode },
8249     { Bad_Opcode },
8250     { Bad_Opcode },
8251     { Bad_Opcode },
8252     /* 80 */
8253     { Bad_Opcode },
8254     { Bad_Opcode },
8255     { Bad_Opcode },
8256     { Bad_Opcode },
8257     { Bad_Opcode },
8258     { Bad_Opcode },
8259     { Bad_Opcode },
8260     { Bad_Opcode },
8261     /* 88 */
8262     { Bad_Opcode },
8263     { Bad_Opcode },
8264     { Bad_Opcode },
8265     { Bad_Opcode },
8266     { Bad_Opcode },
8267     { Bad_Opcode },
8268     { Bad_Opcode },
8269     { Bad_Opcode },
8270     /* 90 */
8271     { Bad_Opcode },
8272     { Bad_Opcode },
8273     { Bad_Opcode },
8274     { Bad_Opcode },
8275     { Bad_Opcode },
8276     { Bad_Opcode },
8277     { Bad_Opcode },
8278     { Bad_Opcode },
8279     /* 98 */
8280     { Bad_Opcode },
8281     { Bad_Opcode },
8282     { Bad_Opcode },
8283     { Bad_Opcode },
8284     { Bad_Opcode },
8285     { Bad_Opcode },
8286     { Bad_Opcode },
8287     { Bad_Opcode },
8288     /* a0 */
8289     { Bad_Opcode },
8290     { Bad_Opcode },
8291     { Bad_Opcode },
8292     { Bad_Opcode },
8293     { Bad_Opcode },
8294     { Bad_Opcode },
8295     { Bad_Opcode },
8296     { Bad_Opcode },
8297     /* a8 */
8298     { Bad_Opcode },
8299     { Bad_Opcode },
8300     { Bad_Opcode },
8301     { Bad_Opcode },
8302     { Bad_Opcode },
8303     { Bad_Opcode },
8304     { Bad_Opcode },
8305     { Bad_Opcode },
8306     /* b0 */
8307     { Bad_Opcode },
8308     { Bad_Opcode },
8309     { Bad_Opcode },
8310     { Bad_Opcode },
8311     { Bad_Opcode },
8312     { Bad_Opcode },
8313     { Bad_Opcode },
8314     { Bad_Opcode },
8315     /* b8 */
8316     { Bad_Opcode },
8317     { Bad_Opcode },
8318     { Bad_Opcode },
8319     { Bad_Opcode },
8320     { Bad_Opcode },
8321     { Bad_Opcode },
8322     { Bad_Opcode },
8323     { Bad_Opcode },
8324     /* c0 */
8325     { Bad_Opcode },
8326     { Bad_Opcode },
8327     { Bad_Opcode },
8328     { Bad_Opcode },
8329     { Bad_Opcode },
8330     { Bad_Opcode },
8331     { Bad_Opcode },
8332     { Bad_Opcode },
8333     /* c8 */
8334     { Bad_Opcode },
8335     { Bad_Opcode },
8336     { Bad_Opcode },
8337     { Bad_Opcode },
8338     { Bad_Opcode },
8339     { Bad_Opcode },
8340     { Bad_Opcode },
8341     { Bad_Opcode },
8342     /* d0 */
8343     { Bad_Opcode },
8344     { Bad_Opcode },
8345     { Bad_Opcode },
8346     { Bad_Opcode },
8347     { Bad_Opcode },
8348     { Bad_Opcode },
8349     { Bad_Opcode },
8350     { Bad_Opcode },
8351     /* d8 */
8352     { Bad_Opcode },
8353     { Bad_Opcode },
8354     { Bad_Opcode },
8355     { Bad_Opcode },
8356     { Bad_Opcode },
8357     { Bad_Opcode },
8358     { Bad_Opcode },
8359     { Bad_Opcode },
8360     /* e0 */
8361     { Bad_Opcode },
8362     { Bad_Opcode },
8363     { Bad_Opcode },
8364     { Bad_Opcode },
8365     { Bad_Opcode },
8366     { Bad_Opcode },
8367     { Bad_Opcode },
8368     { Bad_Opcode },
8369     /* e8 */
8370     { Bad_Opcode },
8371     { Bad_Opcode },
8372     { Bad_Opcode },
8373     { Bad_Opcode },
8374     { Bad_Opcode },
8375     { Bad_Opcode },
8376     { Bad_Opcode },
8377     { Bad_Opcode },
8378     /* f0 */
8379     { Bad_Opcode },
8380     { Bad_Opcode },
8381     { Bad_Opcode },
8382     { Bad_Opcode },
8383     { Bad_Opcode },
8384     { Bad_Opcode },
8385     { Bad_Opcode },
8386     { Bad_Opcode },
8387     /* f8 */
8388     { Bad_Opcode },
8389     { Bad_Opcode },
8390     { Bad_Opcode },
8391     { Bad_Opcode },
8392     { Bad_Opcode },
8393     { Bad_Opcode },
8394     { Bad_Opcode },
8395     { Bad_Opcode },
8396   },
8397 };
8398
8399 static const struct dis386 vex_table[][256] = {
8400   /* VEX_0F */
8401   {
8402     /* 00 */
8403     { Bad_Opcode },
8404     { Bad_Opcode },
8405     { Bad_Opcode },
8406     { Bad_Opcode },
8407     { Bad_Opcode },
8408     { Bad_Opcode },
8409     { Bad_Opcode },
8410     { Bad_Opcode },
8411     /* 08 */
8412     { Bad_Opcode },
8413     { Bad_Opcode },
8414     { Bad_Opcode },
8415     { Bad_Opcode },
8416     { Bad_Opcode },
8417     { Bad_Opcode },
8418     { Bad_Opcode },
8419     { Bad_Opcode },
8420     /* 10 */
8421     { PREFIX_TABLE (PREFIX_VEX_0F10) },
8422     { PREFIX_TABLE (PREFIX_VEX_0F11) },
8423     { PREFIX_TABLE (PREFIX_VEX_0F12) },
8424     { MOD_TABLE (MOD_VEX_0F13) },
8425     { "vunpcklpX",      { XM, Vex, EXx }, PREFIX_OPCODE },
8426     { "vunpckhpX",      { XM, Vex, EXx }, PREFIX_OPCODE },
8427     { PREFIX_TABLE (PREFIX_VEX_0F16) },
8428     { MOD_TABLE (MOD_VEX_0F17) },
8429     /* 18 */
8430     { Bad_Opcode },
8431     { Bad_Opcode },
8432     { Bad_Opcode },
8433     { Bad_Opcode },
8434     { Bad_Opcode },
8435     { Bad_Opcode },
8436     { Bad_Opcode },
8437     { Bad_Opcode },
8438     /* 20 */
8439     { Bad_Opcode },
8440     { Bad_Opcode },
8441     { Bad_Opcode },
8442     { Bad_Opcode },
8443     { Bad_Opcode },
8444     { Bad_Opcode },
8445     { Bad_Opcode },
8446     { Bad_Opcode },
8447     /* 28 */
8448     { "vmovapX",        { XM, EXx }, PREFIX_OPCODE },
8449     { "vmovapX",        { EXxS, XM }, PREFIX_OPCODE },
8450     { PREFIX_TABLE (PREFIX_VEX_0F2A) },
8451     { MOD_TABLE (MOD_VEX_0F2B) },
8452     { PREFIX_TABLE (PREFIX_VEX_0F2C) },
8453     { PREFIX_TABLE (PREFIX_VEX_0F2D) },
8454     { PREFIX_TABLE (PREFIX_VEX_0F2E) },
8455     { PREFIX_TABLE (PREFIX_VEX_0F2F) },
8456     /* 30 */
8457     { Bad_Opcode },
8458     { Bad_Opcode },
8459     { Bad_Opcode },
8460     { Bad_Opcode },
8461     { Bad_Opcode },
8462     { Bad_Opcode },
8463     { Bad_Opcode },
8464     { Bad_Opcode },
8465     /* 38 */
8466     { Bad_Opcode },
8467     { Bad_Opcode },
8468     { Bad_Opcode },
8469     { Bad_Opcode },
8470     { Bad_Opcode },
8471     { Bad_Opcode },
8472     { Bad_Opcode },
8473     { Bad_Opcode },
8474     /* 40 */
8475     { Bad_Opcode },
8476     { PREFIX_TABLE (PREFIX_VEX_0F41) },
8477     { PREFIX_TABLE (PREFIX_VEX_0F42) },
8478     { Bad_Opcode },
8479     { PREFIX_TABLE (PREFIX_VEX_0F44) },
8480     { PREFIX_TABLE (PREFIX_VEX_0F45) },
8481     { PREFIX_TABLE (PREFIX_VEX_0F46) },
8482     { PREFIX_TABLE (PREFIX_VEX_0F47) },
8483     /* 48 */
8484     { Bad_Opcode },
8485     { Bad_Opcode },
8486     { PREFIX_TABLE (PREFIX_VEX_0F4A) },
8487     { PREFIX_TABLE (PREFIX_VEX_0F4B) },
8488     { Bad_Opcode },
8489     { Bad_Opcode },
8490     { Bad_Opcode },
8491     { Bad_Opcode },
8492     /* 50 */
8493     { MOD_TABLE (MOD_VEX_0F50) },
8494     { PREFIX_TABLE (PREFIX_VEX_0F51) },
8495     { PREFIX_TABLE (PREFIX_VEX_0F52) },
8496     { PREFIX_TABLE (PREFIX_VEX_0F53) },
8497     { "vandpX",         { XM, Vex, EXx }, PREFIX_OPCODE },
8498     { "vandnpX",        { XM, Vex, EXx }, PREFIX_OPCODE },
8499     { "vorpX",          { XM, Vex, EXx }, PREFIX_OPCODE },
8500     { "vxorpX",         { XM, Vex, EXx }, PREFIX_OPCODE },
8501     /* 58 */
8502     { PREFIX_TABLE (PREFIX_VEX_0F58) },
8503     { PREFIX_TABLE (PREFIX_VEX_0F59) },
8504     { PREFIX_TABLE (PREFIX_VEX_0F5A) },
8505     { PREFIX_TABLE (PREFIX_VEX_0F5B) },
8506     { PREFIX_TABLE (PREFIX_VEX_0F5C) },
8507     { PREFIX_TABLE (PREFIX_VEX_0F5D) },
8508     { PREFIX_TABLE (PREFIX_VEX_0F5E) },
8509     { PREFIX_TABLE (PREFIX_VEX_0F5F) },
8510     /* 60 */
8511     { PREFIX_TABLE (PREFIX_VEX_0F60) },
8512     { PREFIX_TABLE (PREFIX_VEX_0F61) },
8513     { PREFIX_TABLE (PREFIX_VEX_0F62) },
8514     { PREFIX_TABLE (PREFIX_VEX_0F63) },
8515     { PREFIX_TABLE (PREFIX_VEX_0F64) },
8516     { PREFIX_TABLE (PREFIX_VEX_0F65) },
8517     { PREFIX_TABLE (PREFIX_VEX_0F66) },
8518     { PREFIX_TABLE (PREFIX_VEX_0F67) },
8519     /* 68 */
8520     { PREFIX_TABLE (PREFIX_VEX_0F68) },
8521     { PREFIX_TABLE (PREFIX_VEX_0F69) },
8522     { PREFIX_TABLE (PREFIX_VEX_0F6A) },
8523     { PREFIX_TABLE (PREFIX_VEX_0F6B) },
8524     { PREFIX_TABLE (PREFIX_VEX_0F6C) },
8525     { PREFIX_TABLE (PREFIX_VEX_0F6D) },
8526     { PREFIX_TABLE (PREFIX_VEX_0F6E) },
8527     { PREFIX_TABLE (PREFIX_VEX_0F6F) },
8528     /* 70 */
8529     { PREFIX_TABLE (PREFIX_VEX_0F70) },
8530     { REG_TABLE (REG_VEX_0F71) },
8531     { REG_TABLE (REG_VEX_0F72) },
8532     { REG_TABLE (REG_VEX_0F73) },
8533     { PREFIX_TABLE (PREFIX_VEX_0F74) },
8534     { PREFIX_TABLE (PREFIX_VEX_0F75) },
8535     { PREFIX_TABLE (PREFIX_VEX_0F76) },
8536     { PREFIX_TABLE (PREFIX_VEX_0F77) },
8537     /* 78 */
8538     { Bad_Opcode },
8539     { Bad_Opcode },
8540     { Bad_Opcode },
8541     { Bad_Opcode },
8542     { PREFIX_TABLE (PREFIX_VEX_0F7C) },
8543     { PREFIX_TABLE (PREFIX_VEX_0F7D) },
8544     { PREFIX_TABLE (PREFIX_VEX_0F7E) },
8545     { PREFIX_TABLE (PREFIX_VEX_0F7F) },
8546     /* 80 */
8547     { Bad_Opcode },
8548     { Bad_Opcode },
8549     { Bad_Opcode },
8550     { Bad_Opcode },
8551     { Bad_Opcode },
8552     { Bad_Opcode },
8553     { Bad_Opcode },
8554     { Bad_Opcode },
8555     /* 88 */
8556     { Bad_Opcode },
8557     { Bad_Opcode },
8558     { Bad_Opcode },
8559     { Bad_Opcode },
8560     { Bad_Opcode },
8561     { Bad_Opcode },
8562     { Bad_Opcode },
8563     { Bad_Opcode },
8564     /* 90 */
8565     { PREFIX_TABLE (PREFIX_VEX_0F90) },
8566     { PREFIX_TABLE (PREFIX_VEX_0F91) },
8567     { PREFIX_TABLE (PREFIX_VEX_0F92) },
8568     { PREFIX_TABLE (PREFIX_VEX_0F93) },
8569     { Bad_Opcode },
8570     { Bad_Opcode },
8571     { Bad_Opcode },
8572     { Bad_Opcode },
8573     /* 98 */
8574     { PREFIX_TABLE (PREFIX_VEX_0F98) },
8575     { PREFIX_TABLE (PREFIX_VEX_0F99) },
8576     { Bad_Opcode },
8577     { Bad_Opcode },
8578     { Bad_Opcode },
8579     { Bad_Opcode },
8580     { Bad_Opcode },
8581     { Bad_Opcode },
8582     /* a0 */
8583     { Bad_Opcode },
8584     { Bad_Opcode },
8585     { Bad_Opcode },
8586     { Bad_Opcode },
8587     { Bad_Opcode },
8588     { Bad_Opcode },
8589     { Bad_Opcode },
8590     { Bad_Opcode },
8591     /* a8 */
8592     { Bad_Opcode },
8593     { Bad_Opcode },
8594     { Bad_Opcode },
8595     { Bad_Opcode },
8596     { Bad_Opcode },
8597     { Bad_Opcode },
8598     { REG_TABLE (REG_VEX_0FAE) },
8599     { Bad_Opcode },
8600     /* b0 */
8601     { Bad_Opcode },
8602     { Bad_Opcode },
8603     { Bad_Opcode },
8604     { Bad_Opcode },
8605     { Bad_Opcode },
8606     { Bad_Opcode },
8607     { Bad_Opcode },
8608     { Bad_Opcode },
8609     /* b8 */
8610     { Bad_Opcode },
8611     { Bad_Opcode },
8612     { Bad_Opcode },
8613     { Bad_Opcode },
8614     { Bad_Opcode },
8615     { Bad_Opcode },
8616     { Bad_Opcode },
8617     { Bad_Opcode },
8618     /* c0 */
8619     { Bad_Opcode },
8620     { Bad_Opcode },
8621     { PREFIX_TABLE (PREFIX_VEX_0FC2) },
8622     { Bad_Opcode },
8623     { PREFIX_TABLE (PREFIX_VEX_0FC4) },
8624     { PREFIX_TABLE (PREFIX_VEX_0FC5) },
8625     { "vshufpX",        { XM, Vex, EXx, Ib }, PREFIX_OPCODE },
8626     { Bad_Opcode },
8627     /* c8 */
8628     { Bad_Opcode },
8629     { Bad_Opcode },
8630     { Bad_Opcode },
8631     { Bad_Opcode },
8632     { Bad_Opcode },
8633     { Bad_Opcode },
8634     { Bad_Opcode },
8635     { Bad_Opcode },
8636     /* d0 */
8637     { PREFIX_TABLE (PREFIX_VEX_0FD0) },
8638     { PREFIX_TABLE (PREFIX_VEX_0FD1) },
8639     { PREFIX_TABLE (PREFIX_VEX_0FD2) },
8640     { PREFIX_TABLE (PREFIX_VEX_0FD3) },
8641     { PREFIX_TABLE (PREFIX_VEX_0FD4) },
8642     { PREFIX_TABLE (PREFIX_VEX_0FD5) },
8643     { PREFIX_TABLE (PREFIX_VEX_0FD6) },
8644     { PREFIX_TABLE (PREFIX_VEX_0FD7) },
8645     /* d8 */
8646     { PREFIX_TABLE (PREFIX_VEX_0FD8) },
8647     { PREFIX_TABLE (PREFIX_VEX_0FD9) },
8648     { PREFIX_TABLE (PREFIX_VEX_0FDA) },
8649     { PREFIX_TABLE (PREFIX_VEX_0FDB) },
8650     { PREFIX_TABLE (PREFIX_VEX_0FDC) },
8651     { PREFIX_TABLE (PREFIX_VEX_0FDD) },
8652     { PREFIX_TABLE (PREFIX_VEX_0FDE) },
8653     { PREFIX_TABLE (PREFIX_VEX_0FDF) },
8654     /* e0 */
8655     { PREFIX_TABLE (PREFIX_VEX_0FE0) },
8656     { PREFIX_TABLE (PREFIX_VEX_0FE1) },
8657     { PREFIX_TABLE (PREFIX_VEX_0FE2) },
8658     { PREFIX_TABLE (PREFIX_VEX_0FE3) },
8659     { PREFIX_TABLE (PREFIX_VEX_0FE4) },
8660     { PREFIX_TABLE (PREFIX_VEX_0FE5) },
8661     { PREFIX_TABLE (PREFIX_VEX_0FE6) },
8662     { PREFIX_TABLE (PREFIX_VEX_0FE7) },
8663     /* e8 */
8664     { PREFIX_TABLE (PREFIX_VEX_0FE8) },
8665     { PREFIX_TABLE (PREFIX_VEX_0FE9) },
8666     { PREFIX_TABLE (PREFIX_VEX_0FEA) },
8667     { PREFIX_TABLE (PREFIX_VEX_0FEB) },
8668     { PREFIX_TABLE (PREFIX_VEX_0FEC) },
8669     { PREFIX_TABLE (PREFIX_VEX_0FED) },
8670     { PREFIX_TABLE (PREFIX_VEX_0FEE) },
8671     { PREFIX_TABLE (PREFIX_VEX_0FEF) },
8672     /* f0 */
8673     { PREFIX_TABLE (PREFIX_VEX_0FF0) },
8674     { PREFIX_TABLE (PREFIX_VEX_0FF1) },
8675     { PREFIX_TABLE (PREFIX_VEX_0FF2) },
8676     { PREFIX_TABLE (PREFIX_VEX_0FF3) },
8677     { PREFIX_TABLE (PREFIX_VEX_0FF4) },
8678     { PREFIX_TABLE (PREFIX_VEX_0FF5) },
8679     { PREFIX_TABLE (PREFIX_VEX_0FF6) },
8680     { PREFIX_TABLE (PREFIX_VEX_0FF7) },
8681     /* f8 */
8682     { PREFIX_TABLE (PREFIX_VEX_0FF8) },
8683     { PREFIX_TABLE (PREFIX_VEX_0FF9) },
8684     { PREFIX_TABLE (PREFIX_VEX_0FFA) },
8685     { PREFIX_TABLE (PREFIX_VEX_0FFB) },
8686     { PREFIX_TABLE (PREFIX_VEX_0FFC) },
8687     { PREFIX_TABLE (PREFIX_VEX_0FFD) },
8688     { PREFIX_TABLE (PREFIX_VEX_0FFE) },
8689     { Bad_Opcode },
8690   },
8691   /* VEX_0F38 */
8692   {
8693     /* 00 */
8694     { PREFIX_TABLE (PREFIX_VEX_0F3800) },
8695     { PREFIX_TABLE (PREFIX_VEX_0F3801) },
8696     { PREFIX_TABLE (PREFIX_VEX_0F3802) },
8697     { PREFIX_TABLE (PREFIX_VEX_0F3803) },
8698     { PREFIX_TABLE (PREFIX_VEX_0F3804) },
8699     { PREFIX_TABLE (PREFIX_VEX_0F3805) },
8700     { PREFIX_TABLE (PREFIX_VEX_0F3806) },
8701     { PREFIX_TABLE (PREFIX_VEX_0F3807) },
8702     /* 08 */
8703     { PREFIX_TABLE (PREFIX_VEX_0F3808) },
8704     { PREFIX_TABLE (PREFIX_VEX_0F3809) },
8705     { PREFIX_TABLE (PREFIX_VEX_0F380A) },
8706     { PREFIX_TABLE (PREFIX_VEX_0F380B) },
8707     { PREFIX_TABLE (PREFIX_VEX_0F380C) },
8708     { PREFIX_TABLE (PREFIX_VEX_0F380D) },
8709     { PREFIX_TABLE (PREFIX_VEX_0F380E) },
8710     { PREFIX_TABLE (PREFIX_VEX_0F380F) },
8711     /* 10 */
8712     { Bad_Opcode },
8713     { Bad_Opcode },
8714     { Bad_Opcode },
8715     { PREFIX_TABLE (PREFIX_VEX_0F3813) },
8716     { Bad_Opcode },
8717     { Bad_Opcode },
8718     { PREFIX_TABLE (PREFIX_VEX_0F3816) },
8719     { PREFIX_TABLE (PREFIX_VEX_0F3817) },
8720     /* 18 */
8721     { PREFIX_TABLE (PREFIX_VEX_0F3818) },
8722     { PREFIX_TABLE (PREFIX_VEX_0F3819) },
8723     { PREFIX_TABLE (PREFIX_VEX_0F381A) },
8724     { Bad_Opcode },
8725     { PREFIX_TABLE (PREFIX_VEX_0F381C) },
8726     { PREFIX_TABLE (PREFIX_VEX_0F381D) },
8727     { PREFIX_TABLE (PREFIX_VEX_0F381E) },
8728     { Bad_Opcode },
8729     /* 20 */
8730     { PREFIX_TABLE (PREFIX_VEX_0F3820) },
8731     { PREFIX_TABLE (PREFIX_VEX_0F3821) },
8732     { PREFIX_TABLE (PREFIX_VEX_0F3822) },
8733     { PREFIX_TABLE (PREFIX_VEX_0F3823) },
8734     { PREFIX_TABLE (PREFIX_VEX_0F3824) },
8735     { PREFIX_TABLE (PREFIX_VEX_0F3825) },
8736     { Bad_Opcode },
8737     { Bad_Opcode },
8738     /* 28 */
8739     { PREFIX_TABLE (PREFIX_VEX_0F3828) },
8740     { PREFIX_TABLE (PREFIX_VEX_0F3829) },
8741     { PREFIX_TABLE (PREFIX_VEX_0F382A) },
8742     { PREFIX_TABLE (PREFIX_VEX_0F382B) },
8743     { PREFIX_TABLE (PREFIX_VEX_0F382C) },
8744     { PREFIX_TABLE (PREFIX_VEX_0F382D) },
8745     { PREFIX_TABLE (PREFIX_VEX_0F382E) },
8746     { PREFIX_TABLE (PREFIX_VEX_0F382F) },
8747     /* 30 */
8748     { PREFIX_TABLE (PREFIX_VEX_0F3830) },
8749     { PREFIX_TABLE (PREFIX_VEX_0F3831) },
8750     { PREFIX_TABLE (PREFIX_VEX_0F3832) },
8751     { PREFIX_TABLE (PREFIX_VEX_0F3833) },
8752     { PREFIX_TABLE (PREFIX_VEX_0F3834) },
8753     { PREFIX_TABLE (PREFIX_VEX_0F3835) },
8754     { PREFIX_TABLE (PREFIX_VEX_0F3836) },
8755     { PREFIX_TABLE (PREFIX_VEX_0F3837) },
8756     /* 38 */
8757     { PREFIX_TABLE (PREFIX_VEX_0F3838) },
8758     { PREFIX_TABLE (PREFIX_VEX_0F3839) },
8759     { PREFIX_TABLE (PREFIX_VEX_0F383A) },
8760     { PREFIX_TABLE (PREFIX_VEX_0F383B) },
8761     { PREFIX_TABLE (PREFIX_VEX_0F383C) },
8762     { PREFIX_TABLE (PREFIX_VEX_0F383D) },
8763     { PREFIX_TABLE (PREFIX_VEX_0F383E) },
8764     { PREFIX_TABLE (PREFIX_VEX_0F383F) },
8765     /* 40 */
8766     { PREFIX_TABLE (PREFIX_VEX_0F3840) },
8767     { PREFIX_TABLE (PREFIX_VEX_0F3841) },
8768     { Bad_Opcode },
8769     { Bad_Opcode },
8770     { Bad_Opcode },
8771     { PREFIX_TABLE (PREFIX_VEX_0F3845) },
8772     { PREFIX_TABLE (PREFIX_VEX_0F3846) },
8773     { PREFIX_TABLE (PREFIX_VEX_0F3847) },
8774     /* 48 */
8775     { Bad_Opcode },
8776     { Bad_Opcode },
8777     { Bad_Opcode },
8778     { Bad_Opcode },
8779     { Bad_Opcode },
8780     { Bad_Opcode },
8781     { Bad_Opcode },
8782     { Bad_Opcode },
8783     /* 50 */
8784     { Bad_Opcode },
8785     { Bad_Opcode },
8786     { Bad_Opcode },
8787     { Bad_Opcode },
8788     { Bad_Opcode },
8789     { Bad_Opcode },
8790     { Bad_Opcode },
8791     { Bad_Opcode },
8792     /* 58 */
8793     { PREFIX_TABLE (PREFIX_VEX_0F3858) },
8794     { PREFIX_TABLE (PREFIX_VEX_0F3859) },
8795     { PREFIX_TABLE (PREFIX_VEX_0F385A) },
8796     { Bad_Opcode },
8797     { Bad_Opcode },
8798     { Bad_Opcode },
8799     { Bad_Opcode },
8800     { Bad_Opcode },
8801     /* 60 */
8802     { Bad_Opcode },
8803     { Bad_Opcode },
8804     { Bad_Opcode },
8805     { Bad_Opcode },
8806     { Bad_Opcode },
8807     { Bad_Opcode },
8808     { Bad_Opcode },
8809     { Bad_Opcode },
8810     /* 68 */
8811     { Bad_Opcode },
8812     { Bad_Opcode },
8813     { Bad_Opcode },
8814     { Bad_Opcode },
8815     { Bad_Opcode },
8816     { Bad_Opcode },
8817     { Bad_Opcode },
8818     { Bad_Opcode },
8819     /* 70 */
8820     { Bad_Opcode },
8821     { Bad_Opcode },
8822     { Bad_Opcode },
8823     { Bad_Opcode },
8824     { Bad_Opcode },
8825     { Bad_Opcode },
8826     { Bad_Opcode },
8827     { Bad_Opcode },
8828     /* 78 */
8829     { PREFIX_TABLE (PREFIX_VEX_0F3878) },
8830     { PREFIX_TABLE (PREFIX_VEX_0F3879) },
8831     { Bad_Opcode },
8832     { Bad_Opcode },
8833     { Bad_Opcode },
8834     { Bad_Opcode },
8835     { Bad_Opcode },
8836     { Bad_Opcode },
8837     /* 80 */
8838     { Bad_Opcode },
8839     { Bad_Opcode },
8840     { Bad_Opcode },
8841     { Bad_Opcode },
8842     { Bad_Opcode },
8843     { Bad_Opcode },
8844     { Bad_Opcode },
8845     { Bad_Opcode },
8846     /* 88 */
8847     { Bad_Opcode },
8848     { Bad_Opcode },
8849     { Bad_Opcode },
8850     { Bad_Opcode },
8851     { PREFIX_TABLE (PREFIX_VEX_0F388C) },
8852     { Bad_Opcode },
8853     { PREFIX_TABLE (PREFIX_VEX_0F388E) },
8854     { Bad_Opcode },
8855     /* 90 */
8856     { PREFIX_TABLE (PREFIX_VEX_0F3890) },
8857     { PREFIX_TABLE (PREFIX_VEX_0F3891) },
8858     { PREFIX_TABLE (PREFIX_VEX_0F3892) },
8859     { PREFIX_TABLE (PREFIX_VEX_0F3893) },
8860     { Bad_Opcode },
8861     { Bad_Opcode },
8862     { PREFIX_TABLE (PREFIX_VEX_0F3896) },
8863     { PREFIX_TABLE (PREFIX_VEX_0F3897) },
8864     /* 98 */
8865     { PREFIX_TABLE (PREFIX_VEX_0F3898) },
8866     { PREFIX_TABLE (PREFIX_VEX_0F3899) },
8867     { PREFIX_TABLE (PREFIX_VEX_0F389A) },
8868     { PREFIX_TABLE (PREFIX_VEX_0F389B) },
8869     { PREFIX_TABLE (PREFIX_VEX_0F389C) },
8870     { PREFIX_TABLE (PREFIX_VEX_0F389D) },
8871     { PREFIX_TABLE (PREFIX_VEX_0F389E) },
8872     { PREFIX_TABLE (PREFIX_VEX_0F389F) },
8873     /* a0 */
8874     { Bad_Opcode },
8875     { Bad_Opcode },
8876     { Bad_Opcode },
8877     { Bad_Opcode },
8878     { Bad_Opcode },
8879     { Bad_Opcode },
8880     { PREFIX_TABLE (PREFIX_VEX_0F38A6) },
8881     { PREFIX_TABLE (PREFIX_VEX_0F38A7) },
8882     /* a8 */
8883     { PREFIX_TABLE (PREFIX_VEX_0F38A8) },
8884     { PREFIX_TABLE (PREFIX_VEX_0F38A9) },
8885     { PREFIX_TABLE (PREFIX_VEX_0F38AA) },
8886     { PREFIX_TABLE (PREFIX_VEX_0F38AB) },
8887     { PREFIX_TABLE (PREFIX_VEX_0F38AC) },
8888     { PREFIX_TABLE (PREFIX_VEX_0F38AD) },
8889     { PREFIX_TABLE (PREFIX_VEX_0F38AE) },
8890     { PREFIX_TABLE (PREFIX_VEX_0F38AF) },
8891     /* b0 */
8892     { Bad_Opcode },
8893     { Bad_Opcode },
8894     { Bad_Opcode },
8895     { Bad_Opcode },
8896     { Bad_Opcode },
8897     { Bad_Opcode },
8898     { PREFIX_TABLE (PREFIX_VEX_0F38B6) },
8899     { PREFIX_TABLE (PREFIX_VEX_0F38B7) },
8900     /* b8 */
8901     { PREFIX_TABLE (PREFIX_VEX_0F38B8) },
8902     { PREFIX_TABLE (PREFIX_VEX_0F38B9) },
8903     { PREFIX_TABLE (PREFIX_VEX_0F38BA) },
8904     { PREFIX_TABLE (PREFIX_VEX_0F38BB) },
8905     { PREFIX_TABLE (PREFIX_VEX_0F38BC) },
8906     { PREFIX_TABLE (PREFIX_VEX_0F38BD) },
8907     { PREFIX_TABLE (PREFIX_VEX_0F38BE) },
8908     { PREFIX_TABLE (PREFIX_VEX_0F38BF) },
8909     /* c0 */
8910     { Bad_Opcode },
8911     { Bad_Opcode },
8912     { Bad_Opcode },
8913     { Bad_Opcode },
8914     { Bad_Opcode },
8915     { Bad_Opcode },
8916     { Bad_Opcode },
8917     { Bad_Opcode },
8918     /* c8 */
8919     { Bad_Opcode },
8920     { Bad_Opcode },
8921     { Bad_Opcode },
8922     { Bad_Opcode },
8923     { Bad_Opcode },
8924     { Bad_Opcode },
8925     { Bad_Opcode },
8926     { PREFIX_TABLE (PREFIX_VEX_0F38CF) },
8927     /* d0 */
8928     { Bad_Opcode },
8929     { Bad_Opcode },
8930     { Bad_Opcode },
8931     { Bad_Opcode },
8932     { Bad_Opcode },
8933     { Bad_Opcode },
8934     { Bad_Opcode },
8935     { Bad_Opcode },
8936     /* d8 */
8937     { Bad_Opcode },
8938     { Bad_Opcode },
8939     { Bad_Opcode },
8940     { PREFIX_TABLE (PREFIX_VEX_0F38DB) },
8941     { PREFIX_TABLE (PREFIX_VEX_0F38DC) },
8942     { PREFIX_TABLE (PREFIX_VEX_0F38DD) },
8943     { PREFIX_TABLE (PREFIX_VEX_0F38DE) },
8944     { PREFIX_TABLE (PREFIX_VEX_0F38DF) },
8945     /* e0 */
8946     { Bad_Opcode },
8947     { Bad_Opcode },
8948     { Bad_Opcode },
8949     { Bad_Opcode },
8950     { Bad_Opcode },
8951     { Bad_Opcode },
8952     { Bad_Opcode },
8953     { Bad_Opcode },
8954     /* e8 */
8955     { Bad_Opcode },
8956     { Bad_Opcode },
8957     { Bad_Opcode },
8958     { Bad_Opcode },
8959     { Bad_Opcode },
8960     { Bad_Opcode },
8961     { Bad_Opcode },
8962     { Bad_Opcode },
8963     /* f0 */
8964     { Bad_Opcode },
8965     { Bad_Opcode },
8966     { PREFIX_TABLE (PREFIX_VEX_0F38F2) },
8967     { REG_TABLE (REG_VEX_0F38F3) },
8968     { Bad_Opcode },
8969     { PREFIX_TABLE (PREFIX_VEX_0F38F5) },
8970     { PREFIX_TABLE (PREFIX_VEX_0F38F6) },
8971     { PREFIX_TABLE (PREFIX_VEX_0F38F7) },
8972     /* f8 */
8973     { Bad_Opcode },
8974     { Bad_Opcode },
8975     { Bad_Opcode },
8976     { Bad_Opcode },
8977     { Bad_Opcode },
8978     { Bad_Opcode },
8979     { Bad_Opcode },
8980     { Bad_Opcode },
8981   },
8982   /* VEX_0F3A */
8983   {
8984     /* 00 */
8985     { PREFIX_TABLE (PREFIX_VEX_0F3A00) },
8986     { PREFIX_TABLE (PREFIX_VEX_0F3A01) },
8987     { PREFIX_TABLE (PREFIX_VEX_0F3A02) },
8988     { Bad_Opcode },
8989     { PREFIX_TABLE (PREFIX_VEX_0F3A04) },
8990     { PREFIX_TABLE (PREFIX_VEX_0F3A05) },
8991     { PREFIX_TABLE (PREFIX_VEX_0F3A06) },
8992     { Bad_Opcode },
8993     /* 08 */
8994     { PREFIX_TABLE (PREFIX_VEX_0F3A08) },
8995     { PREFIX_TABLE (PREFIX_VEX_0F3A09) },
8996     { PREFIX_TABLE (PREFIX_VEX_0F3A0A) },
8997     { PREFIX_TABLE (PREFIX_VEX_0F3A0B) },
8998     { PREFIX_TABLE (PREFIX_VEX_0F3A0C) },
8999     { PREFIX_TABLE (PREFIX_VEX_0F3A0D) },
9000     { PREFIX_TABLE (PREFIX_VEX_0F3A0E) },
9001     { PREFIX_TABLE (PREFIX_VEX_0F3A0F) },
9002     /* 10 */
9003     { Bad_Opcode },
9004     { Bad_Opcode },
9005     { Bad_Opcode },
9006     { Bad_Opcode },
9007     { PREFIX_TABLE (PREFIX_VEX_0F3A14) },
9008     { PREFIX_TABLE (PREFIX_VEX_0F3A15) },
9009     { PREFIX_TABLE (PREFIX_VEX_0F3A16) },
9010     { PREFIX_TABLE (PREFIX_VEX_0F3A17) },
9011     /* 18 */
9012     { PREFIX_TABLE (PREFIX_VEX_0F3A18) },
9013     { PREFIX_TABLE (PREFIX_VEX_0F3A19) },
9014     { Bad_Opcode },
9015     { Bad_Opcode },
9016     { Bad_Opcode },
9017     { PREFIX_TABLE (PREFIX_VEX_0F3A1D) },
9018     { Bad_Opcode },
9019     { Bad_Opcode },
9020     /* 20 */
9021     { PREFIX_TABLE (PREFIX_VEX_0F3A20) },
9022     { PREFIX_TABLE (PREFIX_VEX_0F3A21) },
9023     { PREFIX_TABLE (PREFIX_VEX_0F3A22) },
9024     { Bad_Opcode },
9025     { Bad_Opcode },
9026     { Bad_Opcode },
9027     { Bad_Opcode },
9028     { Bad_Opcode },
9029     /* 28 */
9030     { Bad_Opcode },
9031     { Bad_Opcode },
9032     { Bad_Opcode },
9033     { Bad_Opcode },
9034     { Bad_Opcode },
9035     { Bad_Opcode },
9036     { Bad_Opcode },
9037     { Bad_Opcode },
9038     /* 30 */
9039     { PREFIX_TABLE (PREFIX_VEX_0F3A30) },
9040     { PREFIX_TABLE (PREFIX_VEX_0F3A31) },
9041     { PREFIX_TABLE (PREFIX_VEX_0F3A32) },
9042     { PREFIX_TABLE (PREFIX_VEX_0F3A33) },
9043     { Bad_Opcode },
9044     { Bad_Opcode },
9045     { Bad_Opcode },
9046     { Bad_Opcode },
9047     /* 38 */
9048     { PREFIX_TABLE (PREFIX_VEX_0F3A38) },
9049     { PREFIX_TABLE (PREFIX_VEX_0F3A39) },
9050     { Bad_Opcode },
9051     { Bad_Opcode },
9052     { Bad_Opcode },
9053     { Bad_Opcode },
9054     { Bad_Opcode },
9055     { Bad_Opcode },
9056     /* 40 */
9057     { PREFIX_TABLE (PREFIX_VEX_0F3A40) },
9058     { PREFIX_TABLE (PREFIX_VEX_0F3A41) },
9059     { PREFIX_TABLE (PREFIX_VEX_0F3A42) },
9060     { Bad_Opcode },
9061     { PREFIX_TABLE (PREFIX_VEX_0F3A44) },
9062     { Bad_Opcode },
9063     { PREFIX_TABLE (PREFIX_VEX_0F3A46) },
9064     { Bad_Opcode },
9065     /* 48 */
9066     { PREFIX_TABLE (PREFIX_VEX_0F3A48) },
9067     { PREFIX_TABLE (PREFIX_VEX_0F3A49) },
9068     { PREFIX_TABLE (PREFIX_VEX_0F3A4A) },
9069     { PREFIX_TABLE (PREFIX_VEX_0F3A4B) },
9070     { PREFIX_TABLE (PREFIX_VEX_0F3A4C) },
9071     { Bad_Opcode },
9072     { Bad_Opcode },
9073     { Bad_Opcode },
9074     /* 50 */
9075     { Bad_Opcode },
9076     { Bad_Opcode },
9077     { Bad_Opcode },
9078     { Bad_Opcode },
9079     { Bad_Opcode },
9080     { Bad_Opcode },
9081     { Bad_Opcode },
9082     { Bad_Opcode },
9083     /* 58 */
9084     { Bad_Opcode },
9085     { Bad_Opcode },
9086     { Bad_Opcode },
9087     { Bad_Opcode },
9088     { PREFIX_TABLE (PREFIX_VEX_0F3A5C) },
9089     { PREFIX_TABLE (PREFIX_VEX_0F3A5D) },
9090     { PREFIX_TABLE (PREFIX_VEX_0F3A5E) },
9091     { PREFIX_TABLE (PREFIX_VEX_0F3A5F) },
9092     /* 60 */
9093     { PREFIX_TABLE (PREFIX_VEX_0F3A60) },
9094     { PREFIX_TABLE (PREFIX_VEX_0F3A61) },
9095     { PREFIX_TABLE (PREFIX_VEX_0F3A62) },
9096     { PREFIX_TABLE (PREFIX_VEX_0F3A63) },
9097     { Bad_Opcode },
9098     { Bad_Opcode },
9099     { Bad_Opcode },
9100     { Bad_Opcode },
9101     /* 68 */
9102     { PREFIX_TABLE (PREFIX_VEX_0F3A68) },
9103     { PREFIX_TABLE (PREFIX_VEX_0F3A69) },
9104     { PREFIX_TABLE (PREFIX_VEX_0F3A6A) },
9105     { PREFIX_TABLE (PREFIX_VEX_0F3A6B) },
9106     { PREFIX_TABLE (PREFIX_VEX_0F3A6C) },
9107     { PREFIX_TABLE (PREFIX_VEX_0F3A6D) },
9108     { PREFIX_TABLE (PREFIX_VEX_0F3A6E) },
9109     { PREFIX_TABLE (PREFIX_VEX_0F3A6F) },
9110     /* 70 */
9111     { Bad_Opcode },
9112     { Bad_Opcode },
9113     { Bad_Opcode },
9114     { Bad_Opcode },
9115     { Bad_Opcode },
9116     { Bad_Opcode },
9117     { Bad_Opcode },
9118     { Bad_Opcode },
9119     /* 78 */
9120     { PREFIX_TABLE (PREFIX_VEX_0F3A78) },
9121     { PREFIX_TABLE (PREFIX_VEX_0F3A79) },
9122     { PREFIX_TABLE (PREFIX_VEX_0F3A7A) },
9123     { PREFIX_TABLE (PREFIX_VEX_0F3A7B) },
9124     { PREFIX_TABLE (PREFIX_VEX_0F3A7C) },
9125     { PREFIX_TABLE (PREFIX_VEX_0F3A7D) },
9126     { PREFIX_TABLE (PREFIX_VEX_0F3A7E) },
9127     { PREFIX_TABLE (PREFIX_VEX_0F3A7F) },
9128     /* 80 */
9129     { Bad_Opcode },
9130     { Bad_Opcode },
9131     { Bad_Opcode },
9132     { Bad_Opcode },
9133     { Bad_Opcode },
9134     { Bad_Opcode },
9135     { Bad_Opcode },
9136     { Bad_Opcode },
9137     /* 88 */
9138     { Bad_Opcode },
9139     { Bad_Opcode },
9140     { Bad_Opcode },
9141     { Bad_Opcode },
9142     { Bad_Opcode },
9143     { Bad_Opcode },
9144     { Bad_Opcode },
9145     { Bad_Opcode },
9146     /* 90 */
9147     { Bad_Opcode },
9148     { Bad_Opcode },
9149     { Bad_Opcode },
9150     { Bad_Opcode },
9151     { Bad_Opcode },
9152     { Bad_Opcode },
9153     { Bad_Opcode },
9154     { Bad_Opcode },
9155     /* 98 */
9156     { Bad_Opcode },
9157     { Bad_Opcode },
9158     { Bad_Opcode },
9159     { Bad_Opcode },
9160     { Bad_Opcode },
9161     { Bad_Opcode },
9162     { Bad_Opcode },
9163     { Bad_Opcode },
9164     /* a0 */
9165     { Bad_Opcode },
9166     { Bad_Opcode },
9167     { Bad_Opcode },
9168     { Bad_Opcode },
9169     { Bad_Opcode },
9170     { Bad_Opcode },
9171     { Bad_Opcode },
9172     { Bad_Opcode },
9173     /* a8 */
9174     { Bad_Opcode },
9175     { Bad_Opcode },
9176     { Bad_Opcode },
9177     { Bad_Opcode },
9178     { Bad_Opcode },
9179     { Bad_Opcode },
9180     { Bad_Opcode },
9181     { Bad_Opcode },
9182     /* b0 */
9183     { Bad_Opcode },
9184     { Bad_Opcode },
9185     { Bad_Opcode },
9186     { Bad_Opcode },
9187     { Bad_Opcode },
9188     { Bad_Opcode },
9189     { Bad_Opcode },
9190     { Bad_Opcode },
9191     /* b8 */
9192     { Bad_Opcode },
9193     { Bad_Opcode },
9194     { Bad_Opcode },
9195     { Bad_Opcode },
9196     { Bad_Opcode },
9197     { Bad_Opcode },
9198     { Bad_Opcode },
9199     { Bad_Opcode },
9200     /* c0 */
9201     { Bad_Opcode },
9202     { Bad_Opcode },
9203     { Bad_Opcode },
9204     { Bad_Opcode },
9205     { Bad_Opcode },
9206     { Bad_Opcode },
9207     { Bad_Opcode },
9208     { Bad_Opcode },
9209     /* c8 */
9210     { Bad_Opcode },
9211     { Bad_Opcode },
9212     { Bad_Opcode },
9213     { Bad_Opcode },
9214     { Bad_Opcode },
9215     { Bad_Opcode },
9216     { PREFIX_TABLE(PREFIX_VEX_0F3ACE) },
9217     { PREFIX_TABLE(PREFIX_VEX_0F3ACF) },
9218     /* d0 */
9219     { Bad_Opcode },
9220     { Bad_Opcode },
9221     { Bad_Opcode },
9222     { Bad_Opcode },
9223     { Bad_Opcode },
9224     { Bad_Opcode },
9225     { Bad_Opcode },
9226     { Bad_Opcode },
9227     /* d8 */
9228     { Bad_Opcode },
9229     { Bad_Opcode },
9230     { Bad_Opcode },
9231     { Bad_Opcode },
9232     { Bad_Opcode },
9233     { Bad_Opcode },
9234     { Bad_Opcode },
9235     { PREFIX_TABLE (PREFIX_VEX_0F3ADF) },
9236     /* e0 */
9237     { Bad_Opcode },
9238     { Bad_Opcode },
9239     { Bad_Opcode },
9240     { Bad_Opcode },
9241     { Bad_Opcode },
9242     { Bad_Opcode },
9243     { Bad_Opcode },
9244     { Bad_Opcode },
9245     /* e8 */
9246     { Bad_Opcode },
9247     { Bad_Opcode },
9248     { Bad_Opcode },
9249     { Bad_Opcode },
9250     { Bad_Opcode },
9251     { Bad_Opcode },
9252     { Bad_Opcode },
9253     { Bad_Opcode },
9254     /* f0 */
9255     { PREFIX_TABLE (PREFIX_VEX_0F3AF0) },
9256     { Bad_Opcode },
9257     { Bad_Opcode },
9258     { Bad_Opcode },
9259     { Bad_Opcode },
9260     { Bad_Opcode },
9261     { Bad_Opcode },
9262     { Bad_Opcode },
9263     /* f8 */
9264     { Bad_Opcode },
9265     { Bad_Opcode },
9266     { Bad_Opcode },
9267     { Bad_Opcode },
9268     { Bad_Opcode },
9269     { Bad_Opcode },
9270     { Bad_Opcode },
9271     { Bad_Opcode },
9272   },
9273 };
9274
9275 #include "i386-dis-evex.h"
9276
9277 static const struct dis386 vex_len_table[][2] = {
9278   /* VEX_LEN_0F12_P_0_M_0 / VEX_LEN_0F12_P_2_M_0 */
9279   {
9280     { "vmovlpX",        { XM, Vex128, EXq }, 0 },
9281   },
9282
9283   /* VEX_LEN_0F12_P_0_M_1 */
9284   {
9285     { "vmovhlps",       { XM, Vex128, EXq }, 0 },
9286   },
9287
9288   /* VEX_LEN_0F13_M_0 */
9289   {
9290     { "vmovlpX",        { EXq, XM }, PREFIX_OPCODE },
9291   },
9292
9293   /* VEX_LEN_0F16_P_0_M_0 / VEX_LEN_0F16_P_2_M_0 */
9294   {
9295     { "vmovhpX",        { XM, Vex128, EXq }, 0 },
9296   },
9297
9298   /* VEX_LEN_0F16_P_0_M_1 */
9299   {
9300     { "vmovlhps",       { XM, Vex128, EXq }, 0 },
9301   },
9302
9303   /* VEX_LEN_0F17_M_0 */
9304   {
9305     { "vmovhpX",        { EXq, XM }, PREFIX_OPCODE },
9306   },
9307
9308   /* VEX_LEN_0F41_P_0 */
9309   {
9310     { Bad_Opcode },
9311     { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) },
9312   },
9313   /* VEX_LEN_0F41_P_2 */
9314   {
9315     { Bad_Opcode },
9316     { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) },
9317   },
9318   /* VEX_LEN_0F42_P_0 */
9319   {
9320     { Bad_Opcode },
9321     { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) },
9322   },
9323   /* VEX_LEN_0F42_P_2 */
9324   {
9325     { Bad_Opcode },
9326     { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) },
9327   },
9328   /* VEX_LEN_0F44_P_0 */
9329   {
9330     { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) },
9331   },
9332   /* VEX_LEN_0F44_P_2 */
9333   {
9334     { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) },
9335   },
9336   /* VEX_LEN_0F45_P_0 */
9337   {
9338     { Bad_Opcode },
9339     { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) },
9340   },
9341   /* VEX_LEN_0F45_P_2 */
9342   {
9343     { Bad_Opcode },
9344     { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) },
9345   },
9346   /* VEX_LEN_0F46_P_0 */
9347   {
9348     { Bad_Opcode },
9349     { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) },
9350   },
9351   /* VEX_LEN_0F46_P_2 */
9352   {
9353     { Bad_Opcode },
9354     { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) },
9355   },
9356   /* VEX_LEN_0F47_P_0 */
9357   {
9358     { Bad_Opcode },
9359     { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) },
9360   },
9361   /* VEX_LEN_0F47_P_2 */
9362   {
9363     { Bad_Opcode },
9364     { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) },
9365   },
9366   /* VEX_LEN_0F4A_P_0 */
9367   {
9368     { Bad_Opcode },
9369     { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) },
9370   },
9371   /* VEX_LEN_0F4A_P_2 */
9372   {
9373     { Bad_Opcode },
9374     { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) },
9375   },
9376   /* VEX_LEN_0F4B_P_0 */
9377   {
9378     { Bad_Opcode },
9379     { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) },
9380   },
9381   /* VEX_LEN_0F4B_P_2 */
9382   {
9383     { Bad_Opcode },
9384     { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) },
9385   },
9386
9387   /* VEX_LEN_0F6E_P_2 */
9388   {
9389     { "vmovK",          { XMScalar, Edq }, 0 },
9390   },
9391
9392   /* VEX_LEN_0F77_P_1 */
9393   {
9394     { "vzeroupper",     { XX }, 0 },
9395     { "vzeroall",       { XX }, 0 },
9396   },
9397
9398   /* VEX_LEN_0F7E_P_1 */
9399   {
9400     { "vmovq",          { XMScalar, EXxmm_mq }, 0 },
9401   },
9402
9403   /* VEX_LEN_0F7E_P_2 */
9404   {
9405     { "vmovK",          { Edq, XMScalar }, 0 },
9406   },
9407
9408   /* VEX_LEN_0F90_P_0 */
9409   {
9410     { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) },
9411   },
9412
9413   /* VEX_LEN_0F90_P_2 */
9414   {
9415     { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) },
9416   },
9417
9418   /* VEX_LEN_0F91_P_0 */
9419   {
9420     { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) },
9421   },
9422
9423   /* VEX_LEN_0F91_P_2 */
9424   {
9425     { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) },
9426   },
9427
9428   /* VEX_LEN_0F92_P_0 */
9429   {
9430     { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) },
9431   },
9432
9433   /* VEX_LEN_0F92_P_2 */
9434   {
9435     { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) },
9436   },
9437
9438   /* VEX_LEN_0F92_P_3 */
9439   {
9440     { MOD_TABLE (MOD_VEX_0F92_P_3_LEN_0) },
9441   },
9442
9443   /* VEX_LEN_0F93_P_0 */
9444   {
9445     { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) },
9446   },
9447
9448   /* VEX_LEN_0F93_P_2 */
9449   {
9450     { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) },
9451   },
9452
9453   /* VEX_LEN_0F93_P_3 */
9454   {
9455     { MOD_TABLE (MOD_VEX_0F93_P_3_LEN_0) },
9456   },
9457
9458   /* VEX_LEN_0F98_P_0 */
9459   {
9460     { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) },
9461   },
9462
9463   /* VEX_LEN_0F98_P_2 */
9464   {
9465     { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) },
9466   },
9467
9468   /* VEX_LEN_0F99_P_0 */
9469   {
9470     { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) },
9471   },
9472
9473   /* VEX_LEN_0F99_P_2 */
9474   {
9475     { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0) },
9476   },
9477
9478   /* VEX_LEN_0FAE_R_2_M_0 */
9479   {
9480     { "vldmxcsr",       { Md }, 0 },
9481   },
9482
9483   /* VEX_LEN_0FAE_R_3_M_0 */
9484   {
9485     { "vstmxcsr",       { Md }, 0 },
9486   },
9487
9488   /* VEX_LEN_0FC4_P_2 */
9489   {
9490     { "vpinsrw",        { XM, Vex128, Edqw, Ib }, 0 },
9491   },
9492
9493   /* VEX_LEN_0FC5_P_2 */
9494   {
9495     { "vpextrw",        { Gdq, XS, Ib }, 0 },
9496   },
9497
9498   /* VEX_LEN_0FD6_P_2 */
9499   {
9500     { "vmovq",          { EXqVexScalarS, XMScalar }, 0 },
9501   },
9502
9503   /* VEX_LEN_0FF7_P_2 */
9504   {
9505     { "vmaskmovdqu",    { XM, XS }, 0 },
9506   },
9507
9508   /* VEX_LEN_0F3816_P_2 */
9509   {
9510     { Bad_Opcode },
9511     { VEX_W_TABLE (VEX_W_0F3816_P_2) },
9512   },
9513
9514   /* VEX_LEN_0F3819_P_2 */
9515   {
9516     { Bad_Opcode },
9517     { VEX_W_TABLE (VEX_W_0F3819_P_2) },
9518   },
9519
9520   /* VEX_LEN_0F381A_P_2_M_0 */
9521   {
9522     { Bad_Opcode },
9523     { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) },
9524   },
9525
9526   /* VEX_LEN_0F3836_P_2 */
9527   {
9528     { Bad_Opcode },
9529     { VEX_W_TABLE (VEX_W_0F3836_P_2) },
9530   },
9531
9532   /* VEX_LEN_0F3841_P_2 */
9533   {
9534     { "vphminposuw",    { XM, EXx }, 0 },
9535   },
9536
9537   /* VEX_LEN_0F385A_P_2_M_0 */
9538   {
9539     { Bad_Opcode },
9540     { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) },
9541   },
9542
9543   /* VEX_LEN_0F38DB_P_2 */
9544   {
9545     { "vaesimc",        { XM, EXx }, 0 },
9546   },
9547
9548   /* VEX_LEN_0F38F2_P_0 */
9549   {
9550     { "andnS",          { Gdq, VexGdq, Edq }, 0 },
9551   },
9552
9553   /* VEX_LEN_0F38F3_R_1_P_0 */
9554   {
9555     { "blsrS",          { VexGdq, Edq }, 0 },
9556   },
9557
9558   /* VEX_LEN_0F38F3_R_2_P_0 */
9559   {
9560     { "blsmskS",        { VexGdq, Edq }, 0 },
9561   },
9562
9563   /* VEX_LEN_0F38F3_R_3_P_0 */
9564   {
9565     { "blsiS",          { VexGdq, Edq }, 0 },
9566   },
9567
9568   /* VEX_LEN_0F38F5_P_0 */
9569   {
9570     { "bzhiS",          { Gdq, Edq, VexGdq }, 0 },
9571   },
9572
9573   /* VEX_LEN_0F38F5_P_1 */
9574   {
9575     { "pextS",          { Gdq, VexGdq, Edq }, 0 },
9576   },
9577
9578   /* VEX_LEN_0F38F5_P_3 */
9579   {
9580     { "pdepS",          { Gdq, VexGdq, Edq }, 0 },
9581   },
9582
9583   /* VEX_LEN_0F38F6_P_3 */
9584   {
9585     { "mulxS",          { Gdq, VexGdq, Edq }, 0 },
9586   },
9587
9588   /* VEX_LEN_0F38F7_P_0 */
9589   {
9590     { "bextrS",         { Gdq, Edq, VexGdq }, 0 },
9591   },
9592
9593   /* VEX_LEN_0F38F7_P_1 */
9594   {
9595     { "sarxS",          { Gdq, Edq, VexGdq }, 0 },
9596   },
9597
9598   /* VEX_LEN_0F38F7_P_2 */
9599   {
9600     { "shlxS",          { Gdq, Edq, VexGdq }, 0 },
9601   },
9602
9603   /* VEX_LEN_0F38F7_P_3 */
9604   {
9605     { "shrxS",          { Gdq, Edq, VexGdq }, 0 },
9606   },
9607
9608   /* VEX_LEN_0F3A00_P_2 */
9609   {
9610     { Bad_Opcode },
9611     { VEX_W_TABLE (VEX_W_0F3A00_P_2) },
9612   },
9613
9614   /* VEX_LEN_0F3A01_P_2 */
9615   {
9616     { Bad_Opcode },
9617     { VEX_W_TABLE (VEX_W_0F3A01_P_2) },
9618   },
9619
9620   /* VEX_LEN_0F3A06_P_2 */
9621   {
9622     { Bad_Opcode },
9623     { VEX_W_TABLE (VEX_W_0F3A06_P_2) },
9624   },
9625
9626   /* VEX_LEN_0F3A14_P_2 */
9627   {
9628     { "vpextrb",        { Edqb, XM, Ib }, 0 },
9629   },
9630
9631   /* VEX_LEN_0F3A15_P_2 */
9632   {
9633     { "vpextrw",        { Edqw, XM, Ib }, 0 },
9634   },
9635
9636   /* VEX_LEN_0F3A16_P_2  */
9637   {
9638     { "vpextrK",        { Edq, XM, Ib }, 0 },
9639   },
9640
9641   /* VEX_LEN_0F3A17_P_2 */
9642   {
9643     { "vextractps",     { Edqd, XM, Ib }, 0 },
9644   },
9645
9646   /* VEX_LEN_0F3A18_P_2 */
9647   {
9648     { Bad_Opcode },
9649     { VEX_W_TABLE (VEX_W_0F3A18_P_2) },
9650   },
9651
9652   /* VEX_LEN_0F3A19_P_2 */
9653   {
9654     { Bad_Opcode },
9655     { VEX_W_TABLE (VEX_W_0F3A19_P_2) },
9656   },
9657
9658   /* VEX_LEN_0F3A20_P_2 */
9659   {
9660     { "vpinsrb",        { XM, Vex128, Edqb, Ib }, 0 },
9661   },
9662
9663   /* VEX_LEN_0F3A21_P_2 */
9664   {
9665     { "vinsertps",      { XM, Vex128, EXd, Ib }, 0 },
9666   },
9667
9668   /* VEX_LEN_0F3A22_P_2 */
9669   {
9670     { "vpinsrK",        { XM, Vex128, Edq, Ib }, 0 },
9671   },
9672
9673   /* VEX_LEN_0F3A30_P_2 */
9674   {
9675     { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) },
9676   },
9677
9678   /* VEX_LEN_0F3A31_P_2 */
9679   {
9680     { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0) },
9681   },
9682
9683   /* VEX_LEN_0F3A32_P_2 */
9684   {
9685     { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) },
9686   },
9687
9688   /* VEX_LEN_0F3A33_P_2 */
9689   {
9690     { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0) },
9691   },
9692
9693   /* VEX_LEN_0F3A38_P_2 */
9694   {
9695     { Bad_Opcode },
9696     { VEX_W_TABLE (VEX_W_0F3A38_P_2) },
9697   },
9698
9699   /* VEX_LEN_0F3A39_P_2 */
9700   {
9701     { Bad_Opcode },
9702     { VEX_W_TABLE (VEX_W_0F3A39_P_2) },
9703   },
9704
9705   /* VEX_LEN_0F3A41_P_2 */
9706   {
9707     { "vdppd",          { XM, Vex128, EXx, Ib }, 0 },
9708   },
9709
9710   /* VEX_LEN_0F3A46_P_2 */
9711   {
9712     { Bad_Opcode },
9713     { VEX_W_TABLE (VEX_W_0F3A46_P_2) },
9714   },
9715
9716   /* VEX_LEN_0F3A60_P_2 */
9717   {
9718     { "vpcmpestrm",     { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 },
9719   },
9720
9721   /* VEX_LEN_0F3A61_P_2 */
9722   {
9723     { "vpcmpestri",     { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 },
9724   },
9725
9726   /* VEX_LEN_0F3A62_P_2 */
9727   {
9728     { "vpcmpistrm",     { XM, EXx, Ib }, 0 },
9729   },
9730
9731   /* VEX_LEN_0F3A63_P_2 */
9732   {
9733     { "vpcmpistri",     { XM, EXx, Ib }, 0 },
9734   },
9735
9736   /* VEX_LEN_0F3A6A_P_2 */
9737   {
9738     { "vfmaddss",       { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
9739   },
9740
9741   /* VEX_LEN_0F3A6B_P_2 */
9742   {
9743     { "vfmaddsd",       { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
9744   },
9745
9746   /* VEX_LEN_0F3A6E_P_2 */
9747   {
9748     { "vfmsubss",       { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
9749   },
9750
9751   /* VEX_LEN_0F3A6F_P_2 */
9752   {
9753     { "vfmsubsd",       { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
9754   },
9755
9756   /* VEX_LEN_0F3A7A_P_2 */
9757   {
9758     { "vfnmaddss",      { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
9759   },
9760
9761   /* VEX_LEN_0F3A7B_P_2 */
9762   {
9763     { "vfnmaddsd",      { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
9764   },
9765
9766   /* VEX_LEN_0F3A7E_P_2 */
9767   {
9768     { "vfnmsubss",      { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
9769   },
9770
9771   /* VEX_LEN_0F3A7F_P_2 */
9772   {
9773     { "vfnmsubsd",      { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
9774   },
9775
9776   /* VEX_LEN_0F3ADF_P_2 */
9777   {
9778     { "vaeskeygenassist", { XM, EXx, Ib }, 0 },
9779   },
9780
9781   /* VEX_LEN_0F3AF0_P_3 */
9782   {
9783     { "rorxS",          { Gdq, Edq, Ib }, 0 },
9784   },
9785
9786   /* VEX_LEN_0FXOP_08_CC */
9787   {
9788      { "vpcomb",        { XM, Vex128, EXx, VPCOM }, 0 },
9789   },
9790
9791   /* VEX_LEN_0FXOP_08_CD */
9792   {
9793      { "vpcomw",        { XM, Vex128, EXx, VPCOM }, 0 },
9794   },
9795
9796   /* VEX_LEN_0FXOP_08_CE */
9797   {
9798      { "vpcomd",        { XM, Vex128, EXx, VPCOM }, 0 },
9799   },
9800
9801   /* VEX_LEN_0FXOP_08_CF */
9802   {
9803      { "vpcomq",        { XM, Vex128, EXx, VPCOM }, 0 },
9804   },
9805
9806   /* VEX_LEN_0FXOP_08_EC */
9807   {
9808      { "vpcomub",       { XM, Vex128, EXx, VPCOM }, 0 },
9809   },
9810
9811   /* VEX_LEN_0FXOP_08_ED */
9812   {
9813      { "vpcomuw",       { XM, Vex128, EXx, VPCOM }, 0 },
9814   },
9815
9816   /* VEX_LEN_0FXOP_08_EE */
9817   {
9818      { "vpcomud",       { XM, Vex128, EXx, VPCOM }, 0 },
9819   },
9820
9821   /* VEX_LEN_0FXOP_08_EF */
9822   {
9823      { "vpcomuq",       { XM, Vex128, EXx, VPCOM }, 0 },
9824   },
9825
9826   /* VEX_LEN_0FXOP_09_80 */
9827   {
9828     { "vfrczps",        { XM, EXxmm }, 0 },
9829     { "vfrczps",        { XM, EXymmq }, 0 },
9830   },
9831
9832   /* VEX_LEN_0FXOP_09_81 */
9833   {
9834     { "vfrczpd",        { XM, EXxmm }, 0 },
9835     { "vfrczpd",        { XM, EXymmq }, 0 },
9836   },
9837 };
9838
9839 #include "i386-dis-evex-len.h"
9840
9841 static const struct dis386 vex_w_table[][2] = {
9842   {
9843     /* VEX_W_0F41_P_0_LEN_1 */
9844     { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1) },
9845     { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1) },
9846   },
9847   {
9848     /* VEX_W_0F41_P_2_LEN_1 */
9849     { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1) },
9850     { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1) }
9851   },
9852   {
9853     /* VEX_W_0F42_P_0_LEN_1 */
9854     { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1) },
9855     { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1) },
9856   },
9857   {
9858     /* VEX_W_0F42_P_2_LEN_1 */
9859     { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1) },
9860     { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1) },
9861   },
9862   {
9863     /* VEX_W_0F44_P_0_LEN_0 */
9864     { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1) },
9865     { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1) },
9866   },
9867   {
9868     /* VEX_W_0F44_P_2_LEN_0 */
9869     { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1) },
9870     { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1) },
9871   },
9872   {
9873     /* VEX_W_0F45_P_0_LEN_1 */
9874     { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1) },
9875     { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1) },
9876   },
9877   {
9878     /* VEX_W_0F45_P_2_LEN_1 */
9879     { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1) },
9880     { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1) },
9881   },
9882   {
9883     /* VEX_W_0F46_P_0_LEN_1 */
9884     { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1) },
9885     { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1) },
9886   },
9887   {
9888     /* VEX_W_0F46_P_2_LEN_1 */
9889     { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1) },
9890     { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1) },
9891   },
9892   {
9893     /* VEX_W_0F47_P_0_LEN_1 */
9894     { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1) },
9895     { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1) },
9896   },
9897   {
9898     /* VEX_W_0F47_P_2_LEN_1 */
9899     { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1) },
9900     { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1) },
9901   },
9902   {
9903     /* VEX_W_0F4A_P_0_LEN_1 */
9904     { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1) },
9905     { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1) },
9906   },
9907   {
9908     /* VEX_W_0F4A_P_2_LEN_1 */
9909     { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1) },
9910     { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1) },
9911   },
9912   {
9913     /* VEX_W_0F4B_P_0_LEN_1 */
9914     { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1) },
9915     { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1) },
9916   },
9917   {
9918     /* VEX_W_0F4B_P_2_LEN_1 */
9919     { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1) },
9920   },
9921   {
9922     /* VEX_W_0F90_P_0_LEN_0 */
9923     { "kmovw",          { MaskG, MaskE }, 0 },
9924     { "kmovq",          { MaskG, MaskE }, 0 },
9925   },
9926   {
9927     /* VEX_W_0F90_P_2_LEN_0 */
9928     { "kmovb",          { MaskG, MaskBDE }, 0 },
9929     { "kmovd",          { MaskG, MaskBDE }, 0 },
9930   },
9931   {
9932     /* VEX_W_0F91_P_0_LEN_0 */
9933     { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0) },
9934     { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0) },
9935   },
9936   {
9937     /* VEX_W_0F91_P_2_LEN_0 */
9938     { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0) },
9939     { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0) },
9940   },
9941   {
9942     /* VEX_W_0F92_P_0_LEN_0 */
9943     { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0) },
9944   },
9945   {
9946     /* VEX_W_0F92_P_2_LEN_0 */
9947     { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0) },
9948   },
9949   {
9950     /* VEX_W_0F93_P_0_LEN_0 */
9951     { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0) },
9952   },
9953   {
9954     /* VEX_W_0F93_P_2_LEN_0 */
9955     { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0) },
9956   },
9957   {
9958     /* VEX_W_0F98_P_0_LEN_0 */
9959     { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0) },
9960     { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0) },
9961   },
9962   {
9963     /* VEX_W_0F98_P_2_LEN_0 */
9964     { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0) },
9965     { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0) },
9966   },
9967   {
9968     /* VEX_W_0F99_P_0_LEN_0 */
9969     { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0) },
9970     { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0) },
9971   },
9972   {
9973     /* VEX_W_0F99_P_2_LEN_0 */
9974     { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0) },
9975     { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0) },
9976   },
9977   {
9978     /* VEX_W_0F380C_P_2  */
9979     { "vpermilps",      { XM, Vex, EXx }, 0 },
9980   },
9981   {
9982     /* VEX_W_0F380D_P_2  */
9983     { "vpermilpd",      { XM, Vex, EXx }, 0 },
9984   },
9985   {
9986     /* VEX_W_0F380E_P_2  */
9987     { "vtestps",        { XM, EXx }, 0 },
9988   },
9989   {
9990     /* VEX_W_0F380F_P_2  */
9991     { "vtestpd",        { XM, EXx }, 0 },
9992   },
9993   {
9994     /* VEX_W_0F3816_P_2  */
9995     { "vpermps",        { XM, Vex, EXx }, 0 },
9996   },
9997   {
9998     /* VEX_W_0F3818_P_2 */
9999     { "vbroadcastss",   { XM, EXxmm_md }, 0 },
10000   },
10001   {
10002     /* VEX_W_0F3819_P_2 */
10003     { "vbroadcastsd",   { XM, EXxmm_mq }, 0 },
10004   },
10005   {
10006     /* VEX_W_0F381A_P_2_M_0 */
10007     { "vbroadcastf128", { XM, Mxmm }, 0 },
10008   },
10009   {
10010     /* VEX_W_0F382C_P_2_M_0 */
10011     { "vmaskmovps",     { XM, Vex, Mx }, 0 },
10012   },
10013   {
10014     /* VEX_W_0F382D_P_2_M_0 */
10015     { "vmaskmovpd",     { XM, Vex, Mx }, 0 },
10016   },
10017   {
10018     /* VEX_W_0F382E_P_2_M_0 */
10019     { "vmaskmovps",     { Mx, Vex, XM }, 0 },
10020   },
10021   {
10022     /* VEX_W_0F382F_P_2_M_0 */
10023     { "vmaskmovpd",     { Mx, Vex, XM }, 0 },
10024   },
10025   {
10026     /* VEX_W_0F3836_P_2  */
10027     { "vpermd",         { XM, Vex, EXx }, 0 },
10028   },
10029   {
10030     /* VEX_W_0F3846_P_2 */
10031     { "vpsravd",        { XM, Vex, EXx }, 0 },
10032   },
10033   {
10034     /* VEX_W_0F3858_P_2 */
10035     { "vpbroadcastd", { XM, EXxmm_md }, 0 },
10036   },
10037   {
10038     /* VEX_W_0F3859_P_2 */
10039     { "vpbroadcastq",   { XM, EXxmm_mq }, 0 },
10040   },
10041   {
10042     /* VEX_W_0F385A_P_2_M_0 */
10043     { "vbroadcasti128", { XM, Mxmm }, 0 },
10044   },
10045   {
10046     /* VEX_W_0F3878_P_2 */
10047     { "vpbroadcastb",   { XM, EXxmm_mb }, 0 },
10048   },
10049   {
10050     /* VEX_W_0F3879_P_2 */
10051     { "vpbroadcastw",   { XM, EXxmm_mw }, 0 },
10052   },
10053   {
10054     /* VEX_W_0F38CF_P_2 */
10055     { "vgf2p8mulb", { XM, Vex, EXx }, 0 },
10056   },
10057   {
10058     /* VEX_W_0F3A00_P_2 */
10059     { Bad_Opcode },
10060     { "vpermq",         { XM, EXx, Ib }, 0 },
10061   },
10062   {
10063     /* VEX_W_0F3A01_P_2 */
10064     { Bad_Opcode },
10065     { "vpermpd",        { XM, EXx, Ib }, 0 },
10066   },
10067   {
10068     /* VEX_W_0F3A02_P_2 */
10069     { "vpblendd",       { XM, Vex, EXx, Ib }, 0 },
10070   },
10071   {
10072     /* VEX_W_0F3A04_P_2 */
10073     { "vpermilps",      { XM, EXx, Ib }, 0 },
10074   },
10075   {
10076     /* VEX_W_0F3A05_P_2 */
10077     { "vpermilpd",      { XM, EXx, Ib }, 0 },
10078   },
10079   {
10080     /* VEX_W_0F3A06_P_2 */
10081     { "vperm2f128",     { XM, Vex256, EXx, Ib }, 0 },
10082   },
10083   {
10084     /* VEX_W_0F3A18_P_2 */
10085     { "vinsertf128",    { XM, Vex256, EXxmm, Ib }, 0 },
10086   },
10087   {
10088     /* VEX_W_0F3A19_P_2 */
10089     { "vextractf128",   { EXxmm, XM, Ib }, 0 },
10090   },
10091   {
10092     /* VEX_W_0F3A30_P_2_LEN_0 */
10093     { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0) },
10094     { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0) },
10095   },
10096   {
10097     /* VEX_W_0F3A31_P_2_LEN_0 */
10098     { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0) },
10099     { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0) },
10100   },
10101   {
10102     /* VEX_W_0F3A32_P_2_LEN_0 */
10103     { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0) },
10104     { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0) },
10105   },
10106   {
10107     /* VEX_W_0F3A33_P_2_LEN_0 */
10108     { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0) },
10109     { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0) },
10110   },
10111   {
10112     /* VEX_W_0F3A38_P_2 */
10113     { "vinserti128",    { XM, Vex256, EXxmm, Ib }, 0 },
10114   },
10115   {
10116     /* VEX_W_0F3A39_P_2 */
10117     { "vextracti128",   { EXxmm, XM, Ib }, 0 },
10118   },
10119   {
10120     /* VEX_W_0F3A46_P_2 */
10121     { "vperm2i128",     { XM, Vex256, EXx, Ib }, 0 },
10122   },
10123   {
10124     /* VEX_W_0F3A48_P_2 */
10125     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
10126     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
10127   },
10128   {
10129     /* VEX_W_0F3A49_P_2 */
10130     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
10131     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
10132   },
10133   {
10134     /* VEX_W_0F3A4A_P_2 */
10135     { "vblendvps",      { XM, Vex, EXx, XMVexI4 }, 0 },
10136   },
10137   {
10138     /* VEX_W_0F3A4B_P_2 */
10139     { "vblendvpd",      { XM, Vex, EXx, XMVexI4 }, 0 },
10140   },
10141   {
10142     /* VEX_W_0F3A4C_P_2 */
10143     { "vpblendvb",      { XM, Vex, EXx, XMVexI4 }, 0 },
10144   },
10145   {
10146     /* VEX_W_0F3ACE_P_2 */
10147     { Bad_Opcode },
10148     { "vgf2p8affineqb", { XM, Vex, EXx, Ib }, 0 },
10149   },
10150   {
10151     /* VEX_W_0F3ACF_P_2 */
10152     { Bad_Opcode },
10153     { "vgf2p8affineinvqb",  { XM, Vex, EXx, Ib }, 0 },
10154   },
10155
10156 #include "i386-dis-evex-w.h"
10157 };
10158
10159 static const struct dis386 mod_table[][2] = {
10160   {
10161     /* MOD_8D */
10162     { "leaS",           { Gv, M }, 0 },
10163   },
10164   {
10165     /* MOD_C6_REG_7 */
10166     { Bad_Opcode },
10167     { RM_TABLE (RM_C6_REG_7) },
10168   },
10169   {
10170     /* MOD_C7_REG_7 */
10171     { Bad_Opcode },
10172     { RM_TABLE (RM_C7_REG_7) },
10173   },
10174   {
10175     /* MOD_FF_REG_3 */
10176     { "{l|}call^", { indirEp }, 0 },
10177   },
10178   {
10179     /* MOD_FF_REG_5 */
10180     { "{l|}jmp^", { indirEp }, 0 },
10181   },
10182   {
10183     /* MOD_0F01_REG_0 */
10184     { X86_64_TABLE (X86_64_0F01_REG_0) },
10185     { RM_TABLE (RM_0F01_REG_0) },
10186   },
10187   {
10188     /* MOD_0F01_REG_1 */
10189     { X86_64_TABLE (X86_64_0F01_REG_1) },
10190     { RM_TABLE (RM_0F01_REG_1) },
10191   },
10192   {
10193     /* MOD_0F01_REG_2 */
10194     { X86_64_TABLE (X86_64_0F01_REG_2) },
10195     { RM_TABLE (RM_0F01_REG_2) },
10196   },
10197   {
10198     /* MOD_0F01_REG_3 */
10199     { X86_64_TABLE (X86_64_0F01_REG_3) },
10200     { RM_TABLE (RM_0F01_REG_3) },
10201   },
10202   {
10203     /* MOD_0F01_REG_5 */
10204     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_0) },
10205     { RM_TABLE (RM_0F01_REG_5_MOD_3) },
10206   },
10207   {
10208     /* MOD_0F01_REG_7 */
10209     { "invlpg",         { Mb }, 0 },
10210     { RM_TABLE (RM_0F01_REG_7_MOD_3) },
10211   },
10212   {
10213     /* MOD_0F12_PREFIX_0 */
10214     { "movlpX",         { XM, EXq }, 0 },
10215     { "movhlps",        { XM, EXq }, 0 },
10216   },
10217   {
10218     /* MOD_0F12_PREFIX_2 */
10219     { "movlpX", { XM, EXq }, 0 },
10220   },
10221   {
10222     /* MOD_0F13 */
10223     { "movlpX",         { EXq, XM }, PREFIX_OPCODE },
10224   },
10225   {
10226     /* MOD_0F16_PREFIX_0 */
10227     { "movhpX",         { XM, EXq }, 0 },
10228     { "movlhps",        { XM, EXq }, 0 },
10229   },
10230   {
10231     /* MOD_0F16_PREFIX_2 */
10232     { "movhpX", { XM, EXq }, 0 },
10233   },
10234   {
10235     /* MOD_0F17 */
10236     { "movhpX",         { EXq, XM }, PREFIX_OPCODE },
10237   },
10238   {
10239     /* MOD_0F18_REG_0 */
10240     { "prefetchnta",    { Mb }, 0 },
10241   },
10242   {
10243     /* MOD_0F18_REG_1 */
10244     { "prefetcht0",     { Mb }, 0 },
10245   },
10246   {
10247     /* MOD_0F18_REG_2 */
10248     { "prefetcht1",     { Mb }, 0 },
10249   },
10250   {
10251     /* MOD_0F18_REG_3 */
10252     { "prefetcht2",     { Mb }, 0 },
10253   },
10254   {
10255     /* MOD_0F18_REG_4 */
10256     { "nop/reserved",   { Mb }, 0 },
10257   },
10258   {
10259     /* MOD_0F18_REG_5 */
10260     { "nop/reserved",   { Mb }, 0 },
10261   },
10262   {
10263     /* MOD_0F18_REG_6 */
10264     { "nop/reserved",   { Mb }, 0 },
10265   },
10266   {
10267     /* MOD_0F18_REG_7 */
10268     { "nop/reserved",   { Mb }, 0 },
10269   },
10270   {
10271     /* MOD_0F1A_PREFIX_0 */
10272     { "bndldx",         { Gbnd, Mv_bnd }, 0 },
10273     { "nopQ",           { Ev }, 0 },
10274   },
10275   {
10276     /* MOD_0F1B_PREFIX_0 */
10277     { "bndstx",         { Mv_bnd, Gbnd }, 0 },
10278     { "nopQ",           { Ev }, 0 },
10279   },
10280   {
10281     /* MOD_0F1B_PREFIX_1 */
10282     { "bndmk",          { Gbnd, Mv_bnd }, 0 },
10283     { "nopQ",           { Ev }, 0 },
10284   },
10285   {
10286     /* MOD_0F1C_PREFIX_0 */
10287     { REG_TABLE (REG_0F1C_P_0_MOD_0) },
10288     { "nopQ",           { Ev }, 0 },
10289   },
10290   {
10291     /* MOD_0F1E_PREFIX_1 */
10292     { "nopQ",           { Ev }, 0 },
10293     { REG_TABLE (REG_0F1E_P_1_MOD_3) },
10294   },
10295   {
10296     /* MOD_0F24 */
10297     { Bad_Opcode },
10298     { "movL",           { Rd, Td }, 0 },
10299   },
10300   {
10301     /* MOD_0F26 */
10302     { Bad_Opcode },
10303     { "movL",           { Td, Rd }, 0 },
10304   },
10305   {
10306     /* MOD_0F2B_PREFIX_0 */
10307     {"movntps",         { Mx, XM }, PREFIX_OPCODE },
10308   },
10309   {
10310     /* MOD_0F2B_PREFIX_1 */
10311     {"movntss",         { Md, XM }, PREFIX_OPCODE },
10312   },
10313   {
10314     /* MOD_0F2B_PREFIX_2 */
10315     {"movntpd",         { Mx, XM }, PREFIX_OPCODE },
10316   },
10317   {
10318     /* MOD_0F2B_PREFIX_3 */
10319     {"movntsd",         { Mq, XM }, PREFIX_OPCODE },
10320   },
10321   {
10322     /* MOD_0F50 */
10323     { Bad_Opcode },
10324     { "movmskpX",       { Gdq, XS }, PREFIX_OPCODE },
10325   },
10326   {
10327     /* MOD_0F71_REG_2 */
10328     { Bad_Opcode },
10329     { "psrlw",          { MS, Ib }, 0 },
10330   },
10331   {
10332     /* MOD_0F71_REG_4 */
10333     { Bad_Opcode },
10334     { "psraw",          { MS, Ib }, 0 },
10335   },
10336   {
10337     /* MOD_0F71_REG_6 */
10338     { Bad_Opcode },
10339     { "psllw",          { MS, Ib }, 0 },
10340   },
10341   {
10342     /* MOD_0F72_REG_2 */
10343     { Bad_Opcode },
10344     { "psrld",          { MS, Ib }, 0 },
10345   },
10346   {
10347     /* MOD_0F72_REG_4 */
10348     { Bad_Opcode },
10349     { "psrad",          { MS, Ib }, 0 },
10350   },
10351   {
10352     /* MOD_0F72_REG_6 */
10353     { Bad_Opcode },
10354     { "pslld",          { MS, Ib }, 0 },
10355   },
10356   {
10357     /* MOD_0F73_REG_2 */
10358     { Bad_Opcode },
10359     { "psrlq",          { MS, Ib }, 0 },
10360   },
10361   {
10362     /* MOD_0F73_REG_3 */
10363     { Bad_Opcode },
10364     { PREFIX_TABLE (PREFIX_0F73_REG_3) },
10365   },
10366   {
10367     /* MOD_0F73_REG_6 */
10368     { Bad_Opcode },
10369     { "psllq",          { MS, Ib }, 0 },
10370   },
10371   {
10372     /* MOD_0F73_REG_7 */
10373     { Bad_Opcode },
10374     { PREFIX_TABLE (PREFIX_0F73_REG_7) },
10375   },
10376   {
10377     /* MOD_0FAE_REG_0 */
10378     { "fxsave",         { FXSAVE }, 0 },
10379     { PREFIX_TABLE (PREFIX_0FAE_REG_0_MOD_3) },
10380   },
10381   {
10382     /* MOD_0FAE_REG_1 */
10383     { "fxrstor",        { FXSAVE }, 0 },
10384     { PREFIX_TABLE (PREFIX_0FAE_REG_1_MOD_3) },
10385   },
10386   {
10387     /* MOD_0FAE_REG_2 */
10388     { "ldmxcsr",        { Md }, 0 },
10389     { PREFIX_TABLE (PREFIX_0FAE_REG_2_MOD_3) },
10390   },
10391   {
10392     /* MOD_0FAE_REG_3 */
10393     { "stmxcsr",        { Md }, 0 },
10394     { PREFIX_TABLE (PREFIX_0FAE_REG_3_MOD_3) },
10395   },
10396   {
10397     /* MOD_0FAE_REG_4 */
10398     { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_0) },
10399     { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_3) },
10400   },
10401   {
10402     /* MOD_0FAE_REG_5 */
10403     { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_0) },
10404     { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_3) },
10405   },
10406   {
10407     /* MOD_0FAE_REG_6 */
10408     { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_0) },
10409     { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_3) },
10410   },
10411   {
10412     /* MOD_0FAE_REG_7 */
10413     { PREFIX_TABLE (PREFIX_0FAE_REG_7_MOD_0) },
10414     { RM_TABLE (RM_0FAE_REG_7_MOD_3) },
10415   },
10416   {
10417     /* MOD_0FB2 */
10418     { "lssS",           { Gv, Mp }, 0 },
10419   },
10420   {
10421     /* MOD_0FB4 */
10422     { "lfsS",           { Gv, Mp }, 0 },
10423   },
10424   {
10425     /* MOD_0FB5 */
10426     { "lgsS",           { Gv, Mp }, 0 },
10427   },
10428   {
10429     /* MOD_0FC3 */
10430     { PREFIX_TABLE (PREFIX_0FC3_MOD_0) },
10431   },
10432   {
10433     /* MOD_0FC7_REG_3 */
10434     { "xrstors",        { FXSAVE }, 0 },
10435   },
10436   {
10437     /* MOD_0FC7_REG_4 */
10438     { "xsavec",         { FXSAVE }, 0 },
10439   },
10440   {
10441     /* MOD_0FC7_REG_5 */
10442     { "xsaves",         { FXSAVE }, 0 },
10443   },
10444   {
10445     /* MOD_0FC7_REG_6 */
10446     { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_0) },
10447     { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_3) }
10448   },
10449   {
10450     /* MOD_0FC7_REG_7 */
10451     { "vmptrst",        { Mq }, 0 },
10452     { PREFIX_TABLE (PREFIX_0FC7_REG_7_MOD_3) }
10453   },
10454   {
10455     /* MOD_0FD7 */
10456     { Bad_Opcode },
10457     { "pmovmskb",       { Gdq, MS }, 0 },
10458   },
10459   {
10460     /* MOD_0FE7_PREFIX_2 */
10461     { "movntdq",        { Mx, XM }, 0 },
10462   },
10463   {
10464     /* MOD_0FF0_PREFIX_3 */
10465     { "lddqu",          { XM, M }, 0 },
10466   },
10467   {
10468     /* MOD_0F382A_PREFIX_2 */
10469     { "movntdqa",       { XM, Mx }, 0 },
10470   },
10471   {
10472     /* MOD_0F38F5_PREFIX_2 */
10473     { "wrussK",         { M, Gdq }, PREFIX_OPCODE },
10474   },
10475   {
10476     /* MOD_0F38F6_PREFIX_0 */
10477     { "wrssK",          { M, Gdq }, PREFIX_OPCODE },
10478   },
10479   {
10480     /* MOD_0F38F8_PREFIX_1 */
10481     { "enqcmds",        { Gva, M }, PREFIX_OPCODE },
10482   },
10483   {
10484     /* MOD_0F38F8_PREFIX_2 */
10485     { "movdir64b",      { Gva, M }, PREFIX_OPCODE },
10486   },
10487   {
10488     /* MOD_0F38F8_PREFIX_3 */
10489     { "enqcmd",         { Gva, M }, PREFIX_OPCODE },
10490   },
10491   {
10492     /* MOD_0F38F9_PREFIX_0 */
10493     { "movdiri",        { Ev, Gv }, PREFIX_OPCODE },
10494   },
10495   {
10496     /* MOD_62_32BIT */
10497     { "bound{S|}",      { Gv, Ma }, 0 },
10498     { EVEX_TABLE (EVEX_0F) },
10499   },
10500   {
10501     /* MOD_C4_32BIT */
10502     { "lesS",           { Gv, Mp }, 0 },
10503     { VEX_C4_TABLE (VEX_0F) },
10504   },
10505   {
10506     /* MOD_C5_32BIT */
10507     { "ldsS",           { Gv, Mp }, 0 },
10508     { VEX_C5_TABLE (VEX_0F) },
10509   },
10510   {
10511     /* MOD_VEX_0F12_PREFIX_0 */
10512     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
10513     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
10514   },
10515   {
10516     /* MOD_VEX_0F12_PREFIX_2 */
10517     { VEX_LEN_TABLE (VEX_LEN_0F12_P_2_M_0) },
10518   },
10519   {
10520     /* MOD_VEX_0F13 */
10521     { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
10522   },
10523   {
10524     /* MOD_VEX_0F16_PREFIX_0 */
10525     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
10526     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
10527   },
10528   {
10529     /* MOD_VEX_0F16_PREFIX_2 */
10530     { VEX_LEN_TABLE (VEX_LEN_0F16_P_2_M_0) },
10531   },
10532   {
10533     /* MOD_VEX_0F17 */
10534     { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
10535   },
10536   {
10537     /* MOD_VEX_0F2B */
10538     { "vmovntpX",       { Mx, XM }, PREFIX_OPCODE },
10539   },
10540   {
10541     /* MOD_VEX_W_0_0F41_P_0_LEN_1 */
10542     { Bad_Opcode },
10543     { "kandw",          { MaskG, MaskVex, MaskR }, 0 },
10544   },
10545   {
10546     /* MOD_VEX_W_1_0F41_P_0_LEN_1 */
10547     { Bad_Opcode },
10548     { "kandq",          { MaskG, MaskVex, MaskR }, 0 },
10549   },
10550   {
10551     /* MOD_VEX_W_0_0F41_P_2_LEN_1 */
10552     { Bad_Opcode },
10553     { "kandb",          { MaskG, MaskVex, MaskR }, 0 },
10554   },
10555   {
10556     /* MOD_VEX_W_1_0F41_P_2_LEN_1 */
10557     { Bad_Opcode },
10558     { "kandd",          { MaskG, MaskVex, MaskR }, 0 },
10559   },
10560   {
10561     /* MOD_VEX_W_0_0F42_P_0_LEN_1 */
10562     { Bad_Opcode },
10563     { "kandnw",         { MaskG, MaskVex, MaskR }, 0 },
10564   },
10565   {
10566     /* MOD_VEX_W_1_0F42_P_0_LEN_1 */
10567     { Bad_Opcode },
10568     { "kandnq",         { MaskG, MaskVex, MaskR }, 0 },
10569   },
10570   {
10571     /* MOD_VEX_W_0_0F42_P_2_LEN_1 */
10572     { Bad_Opcode },
10573     { "kandnb",         { MaskG, MaskVex, MaskR }, 0 },
10574   },
10575   {
10576     /* MOD_VEX_W_1_0F42_P_2_LEN_1 */
10577     { Bad_Opcode },
10578     { "kandnd",         { MaskG, MaskVex, MaskR }, 0 },
10579   },
10580   {
10581     /* MOD_VEX_W_0_0F44_P_0_LEN_0 */
10582     { Bad_Opcode },
10583     { "knotw",          { MaskG, MaskR }, 0 },
10584   },
10585   {
10586     /* MOD_VEX_W_1_0F44_P_0_LEN_0 */
10587     { Bad_Opcode },
10588     { "knotq",          { MaskG, MaskR }, 0 },
10589   },
10590   {
10591     /* MOD_VEX_W_0_0F44_P_2_LEN_0 */
10592     { Bad_Opcode },
10593     { "knotb",          { MaskG, MaskR }, 0 },
10594   },
10595   {
10596     /* MOD_VEX_W_1_0F44_P_2_LEN_0 */
10597     { Bad_Opcode },
10598     { "knotd",          { MaskG, MaskR }, 0 },
10599   },
10600   {
10601     /* MOD_VEX_W_0_0F45_P_0_LEN_1 */
10602     { Bad_Opcode },
10603     { "korw",       { MaskG, MaskVex, MaskR }, 0 },
10604   },
10605   {
10606     /* MOD_VEX_W_1_0F45_P_0_LEN_1 */
10607     { Bad_Opcode },
10608     { "korq",       { MaskG, MaskVex, MaskR }, 0 },
10609   },
10610   {
10611     /* MOD_VEX_W_0_0F45_P_2_LEN_1 */
10612     { Bad_Opcode },
10613     { "korb",       { MaskG, MaskVex, MaskR }, 0 },
10614   },
10615   {
10616     /* MOD_VEX_W_1_0F45_P_2_LEN_1 */
10617     { Bad_Opcode },
10618     { "kord",       { MaskG, MaskVex, MaskR }, 0 },
10619   },
10620  {
10621     /* MOD_VEX_W_0_0F46_P_0_LEN_1 */
10622     { Bad_Opcode },
10623     { "kxnorw",     { MaskG, MaskVex, MaskR }, 0 },
10624   },
10625   {
10626     /* MOD_VEX_W_1_0F46_P_0_LEN_1 */
10627     { Bad_Opcode },
10628     { "kxnorq",     { MaskG, MaskVex, MaskR }, 0 },
10629   },
10630   {
10631     /* MOD_VEX_W_0_0F46_P_2_LEN_1 */
10632     { Bad_Opcode },
10633     { "kxnorb",     { MaskG, MaskVex, MaskR }, 0 },
10634   },
10635   {
10636     /* MOD_VEX_W_1_0F46_P_2_LEN_1 */
10637     { Bad_Opcode },
10638     { "kxnord",     { MaskG, MaskVex, MaskR }, 0 },
10639   },
10640   {
10641     /* MOD_VEX_W_0_0F47_P_0_LEN_1 */
10642     { Bad_Opcode },
10643     { "kxorw",      { MaskG, MaskVex, MaskR }, 0 },
10644   },
10645   {
10646     /* MOD_VEX_W_1_0F47_P_0_LEN_1 */
10647     { Bad_Opcode },
10648     { "kxorq",      { MaskG, MaskVex, MaskR }, 0 },
10649   },
10650   {
10651     /* MOD_VEX_W_0_0F47_P_2_LEN_1 */
10652     { Bad_Opcode },
10653     { "kxorb",      { MaskG, MaskVex, MaskR }, 0 },
10654   },
10655   {
10656     /* MOD_VEX_W_1_0F47_P_2_LEN_1 */
10657     { Bad_Opcode },
10658     { "kxord",      { MaskG, MaskVex, MaskR }, 0 },
10659   },
10660   {
10661     /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */
10662     { Bad_Opcode },
10663     { "kaddw",          { MaskG, MaskVex, MaskR }, 0 },
10664   },
10665   {
10666     /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */
10667     { Bad_Opcode },
10668     { "kaddq",          { MaskG, MaskVex, MaskR }, 0 },
10669   },
10670   {
10671     /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */
10672     { Bad_Opcode },
10673     { "kaddb",          { MaskG, MaskVex, MaskR }, 0 },
10674   },
10675   {
10676     /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */
10677     { Bad_Opcode },
10678     { "kaddd",          { MaskG, MaskVex, MaskR }, 0 },
10679   },
10680   {
10681     /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */
10682     { Bad_Opcode },
10683     { "kunpckwd",   { MaskG, MaskVex, MaskR }, 0 },
10684   },
10685   {
10686     /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */
10687     { Bad_Opcode },
10688     { "kunpckdq",   { MaskG, MaskVex, MaskR }, 0 },
10689   },
10690   {
10691     /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */
10692     { Bad_Opcode },
10693     { "kunpckbw",   { MaskG, MaskVex, MaskR }, 0 },
10694   },
10695   {
10696     /* MOD_VEX_0F50 */
10697     { Bad_Opcode },
10698     { "vmovmskpX",      { Gdq, XS }, PREFIX_OPCODE },
10699   },
10700   {
10701     /* MOD_VEX_0F71_REG_2 */
10702     { Bad_Opcode },
10703     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) },
10704   },
10705   {
10706     /* MOD_VEX_0F71_REG_4 */
10707     { Bad_Opcode },
10708     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) },
10709   },
10710   {
10711     /* MOD_VEX_0F71_REG_6 */
10712     { Bad_Opcode },
10713     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) },
10714   },
10715   {
10716     /* MOD_VEX_0F72_REG_2 */
10717     { Bad_Opcode },
10718     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) },
10719   },
10720   {
10721     /* MOD_VEX_0F72_REG_4 */
10722     { Bad_Opcode },
10723     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) },
10724   },
10725   {
10726     /* MOD_VEX_0F72_REG_6 */
10727     { Bad_Opcode },
10728     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) },
10729   },
10730   {
10731     /* MOD_VEX_0F73_REG_2 */
10732     { Bad_Opcode },
10733     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) },
10734   },
10735   {
10736     /* MOD_VEX_0F73_REG_3 */
10737     { Bad_Opcode },
10738     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) },
10739   },
10740   {
10741     /* MOD_VEX_0F73_REG_6 */
10742     { Bad_Opcode },
10743     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) },
10744   },
10745   {
10746     /* MOD_VEX_0F73_REG_7 */
10747     { Bad_Opcode },
10748     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) },
10749   },
10750   {
10751     /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
10752     { "kmovw",          { Ew, MaskG }, 0 },
10753     { Bad_Opcode },
10754   },
10755   {
10756     /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
10757     { "kmovq",          { Eq, MaskG }, 0 },
10758     { Bad_Opcode },
10759   },
10760   {
10761     /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
10762     { "kmovb",          { Eb, MaskG }, 0 },
10763     { Bad_Opcode },
10764   },
10765   {
10766     /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
10767     { "kmovd",          { Ed, MaskG }, 0 },
10768     { Bad_Opcode },
10769   },
10770   {
10771     /* MOD_VEX_W_0_0F92_P_0_LEN_0 */
10772     { Bad_Opcode },
10773     { "kmovw",          { MaskG, Rdq }, 0 },
10774   },
10775   {
10776     /* MOD_VEX_W_0_0F92_P_2_LEN_0 */
10777     { Bad_Opcode },
10778     { "kmovb",          { MaskG, Rdq }, 0 },
10779   },
10780   {
10781     /* MOD_VEX_0F92_P_3_LEN_0 */
10782     { Bad_Opcode },
10783     { "kmovK",          { MaskG, Rdq }, 0 },
10784   },
10785   {
10786     /* MOD_VEX_W_0_0F93_P_0_LEN_0 */
10787     { Bad_Opcode },
10788     { "kmovw",          { Gdq, MaskR }, 0 },
10789   },
10790   {
10791     /* MOD_VEX_W_0_0F93_P_2_LEN_0 */
10792     { Bad_Opcode },
10793     { "kmovb",          { Gdq, MaskR }, 0 },
10794   },
10795   {
10796     /* MOD_VEX_0F93_P_3_LEN_0 */
10797     { Bad_Opcode },
10798     { "kmovK",          { Gdq, MaskR }, 0 },
10799   },
10800   {
10801     /* MOD_VEX_W_0_0F98_P_0_LEN_0 */
10802     { Bad_Opcode },
10803     { "kortestw", { MaskG, MaskR }, 0 },
10804   },
10805   {
10806     /* MOD_VEX_W_1_0F98_P_0_LEN_0 */
10807     { Bad_Opcode },
10808     { "kortestq", { MaskG, MaskR }, 0 },
10809   },
10810   {
10811     /* MOD_VEX_W_0_0F98_P_2_LEN_0 */
10812     { Bad_Opcode },
10813     { "kortestb", { MaskG, MaskR }, 0 },
10814   },
10815   {
10816     /* MOD_VEX_W_1_0F98_P_2_LEN_0 */
10817     { Bad_Opcode },
10818     { "kortestd", { MaskG, MaskR }, 0 },
10819   },
10820   {
10821     /* MOD_VEX_W_0_0F99_P_0_LEN_0 */
10822     { Bad_Opcode },
10823     { "ktestw", { MaskG, MaskR }, 0 },
10824   },
10825   {
10826     /* MOD_VEX_W_1_0F99_P_0_LEN_0 */
10827     { Bad_Opcode },
10828     { "ktestq", { MaskG, MaskR }, 0 },
10829   },
10830   {
10831     /* MOD_VEX_W_0_0F99_P_2_LEN_0 */
10832     { Bad_Opcode },
10833     { "ktestb", { MaskG, MaskR }, 0 },
10834   },
10835   {
10836     /* MOD_VEX_W_1_0F99_P_2_LEN_0 */
10837     { Bad_Opcode },
10838     { "ktestd", { MaskG, MaskR }, 0 },
10839   },
10840   {
10841     /* MOD_VEX_0FAE_REG_2 */
10842     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
10843   },
10844   {
10845     /* MOD_VEX_0FAE_REG_3 */
10846     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
10847   },
10848   {
10849     /* MOD_VEX_0FD7_PREFIX_2 */
10850     { Bad_Opcode },
10851     { "vpmovmskb",      { Gdq, XS }, 0 },
10852   },
10853   {
10854     /* MOD_VEX_0FE7_PREFIX_2 */
10855     { "vmovntdq",       { Mx, XM }, 0 },
10856   },
10857   {
10858     /* MOD_VEX_0FF0_PREFIX_3 */
10859     { "vlddqu",         { XM, M }, 0 },
10860   },
10861   {
10862     /* MOD_VEX_0F381A_PREFIX_2 */
10863     { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) },
10864   },
10865   {
10866     /* MOD_VEX_0F382A_PREFIX_2 */
10867     { "vmovntdqa",      { XM, Mx }, 0 },
10868   },
10869   {
10870     /* MOD_VEX_0F382C_PREFIX_2 */
10871     { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) },
10872   },
10873   {
10874     /* MOD_VEX_0F382D_PREFIX_2 */
10875     { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) },
10876   },
10877   {
10878     /* MOD_VEX_0F382E_PREFIX_2 */
10879     { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) },
10880   },
10881   {
10882     /* MOD_VEX_0F382F_PREFIX_2 */
10883     { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) },
10884   },
10885   {
10886     /* MOD_VEX_0F385A_PREFIX_2 */
10887     { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) },
10888   },
10889   {
10890     /* MOD_VEX_0F388C_PREFIX_2 */
10891     { "vpmaskmov%LW",   { XM, Vex, Mx }, 0 },
10892   },
10893   {
10894     /* MOD_VEX_0F388E_PREFIX_2 */
10895     { "vpmaskmov%LW",   { Mx, Vex, XM }, 0 },
10896   },
10897   {
10898     /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */
10899     { Bad_Opcode },
10900     { "kshiftrb",       { MaskG, MaskR, Ib }, 0 },
10901   },
10902   {
10903     /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */
10904     { Bad_Opcode },
10905     { "kshiftrw",       { MaskG, MaskR, Ib }, 0 },
10906   },
10907   {
10908     /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */
10909     { Bad_Opcode },
10910     { "kshiftrd",       { MaskG, MaskR, Ib }, 0 },
10911   },
10912   {
10913     /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */
10914     { Bad_Opcode },
10915     { "kshiftrq",       { MaskG, MaskR, Ib }, 0 },
10916   },
10917   {
10918     /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */
10919     { Bad_Opcode },
10920     { "kshiftlb",       { MaskG, MaskR, Ib }, 0 },
10921   },
10922   {
10923     /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */
10924     { Bad_Opcode },
10925     { "kshiftlw",       { MaskG, MaskR, Ib }, 0 },
10926   },
10927   {
10928     /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */
10929     { Bad_Opcode },
10930     { "kshiftld",       { MaskG, MaskR, Ib }, 0 },
10931   },
10932   {
10933     /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */
10934     { Bad_Opcode },
10935     { "kshiftlq",       { MaskG, MaskR, Ib }, 0 },
10936   },
10937
10938 #include "i386-dis-evex-mod.h"
10939 };
10940
10941 static const struct dis386 rm_table[][8] = {
10942   {
10943     /* RM_C6_REG_7 */
10944     { "xabort",         { Skip_MODRM, Ib }, 0 },
10945   },
10946   {
10947     /* RM_C7_REG_7 */
10948     { "xbeginT",        { Skip_MODRM, Jdqw }, 0 },
10949   },
10950   {
10951     /* RM_0F01_REG_0 */
10952     { "enclv",          { Skip_MODRM }, 0 },
10953     { "vmcall",         { Skip_MODRM }, 0 },
10954     { "vmlaunch",       { Skip_MODRM }, 0 },
10955     { "vmresume",       { Skip_MODRM }, 0 },
10956     { "vmxoff",         { Skip_MODRM }, 0 },
10957     { "pconfig",        { Skip_MODRM }, 0 },
10958   },
10959   {
10960     /* RM_0F01_REG_1 */
10961     { "monitor",        { { OP_Monitor, 0 } }, 0 },
10962     { "mwait",          { { OP_Mwait, 0 } }, 0 },
10963     { "clac",           { Skip_MODRM }, 0 },
10964     { "stac",           { Skip_MODRM }, 0 },
10965     { Bad_Opcode },
10966     { Bad_Opcode },
10967     { Bad_Opcode },
10968     { "encls",          { Skip_MODRM }, 0 },
10969   },
10970   {
10971     /* RM_0F01_REG_2 */
10972     { "xgetbv",         { Skip_MODRM }, 0 },
10973     { "xsetbv",         { Skip_MODRM }, 0 },
10974     { Bad_Opcode },
10975     { Bad_Opcode },
10976     { "vmfunc",         { Skip_MODRM }, 0 },
10977     { "xend",           { Skip_MODRM }, 0 },
10978     { "xtest",          { Skip_MODRM }, 0 },
10979     { "enclu",          { Skip_MODRM }, 0 },
10980   },
10981   {
10982     /* RM_0F01_REG_3 */
10983     { "vmrun",          { Skip_MODRM }, 0 },
10984     { PREFIX_TABLE (PREFIX_0F01_REG_3_RM_1) },
10985     { "vmload",         { Skip_MODRM }, 0 },
10986     { "vmsave",         { Skip_MODRM }, 0 },
10987     { "stgi",           { Skip_MODRM }, 0 },
10988     { "clgi",           { Skip_MODRM }, 0 },
10989     { "skinit",         { Skip_MODRM }, 0 },
10990     { "invlpga",        { Skip_MODRM }, 0 },
10991   },
10992   {
10993     /* RM_0F01_REG_5_MOD_3 */
10994     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_0) },
10995     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_1) },
10996     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_2) },
10997     { Bad_Opcode },
10998     { Bad_Opcode },
10999     { Bad_Opcode },
11000     { "rdpkru",         { Skip_MODRM }, 0 },
11001     { "wrpkru",         { Skip_MODRM }, 0 },
11002   },
11003   {
11004     /* RM_0F01_REG_7_MOD_3 */
11005     { "swapgs",         { Skip_MODRM }, 0  },
11006     { "rdtscp",         { Skip_MODRM }, 0  },
11007     { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_2) },
11008     { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_3) },
11009     { "clzero",         { Skip_MODRM }, 0  },
11010     { "rdpru",          { Skip_MODRM }, 0  },
11011   },
11012   {
11013     /* RM_0F1E_P_1_MOD_3_REG_7 */
11014     { "nopQ",           { Ev }, 0 },
11015     { "nopQ",           { Ev }, 0 },
11016     { "endbr64",        { Skip_MODRM },  PREFIX_OPCODE },
11017     { "endbr32",        { Skip_MODRM },  PREFIX_OPCODE },
11018     { "nopQ",           { Ev }, 0 },
11019     { "nopQ",           { Ev }, 0 },
11020     { "nopQ",           { Ev }, 0 },
11021     { "nopQ",           { Ev }, 0 },
11022   },
11023   {
11024     /* RM_0FAE_REG_6_MOD_3 */
11025     { "mfence",         { Skip_MODRM }, 0 },
11026   },
11027   {
11028     /* RM_0FAE_REG_7_MOD_3 */
11029     { "sfence",         { Skip_MODRM }, 0 },
11030
11031   },
11032 };
11033
11034 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
11035
11036 /* We use the high bit to indicate different name for the same
11037    prefix.  */
11038 #define REP_PREFIX      (0xf3 | 0x100)
11039 #define XACQUIRE_PREFIX (0xf2 | 0x200)
11040 #define XRELEASE_PREFIX (0xf3 | 0x400)
11041 #define BND_PREFIX      (0xf2 | 0x400)
11042 #define NOTRACK_PREFIX  (0x3e | 0x100)
11043
11044 /* Remember if the current op is a jump instruction.  */
11045 static bfd_boolean op_is_jump = FALSE;
11046
11047 static int
11048 ckprefix (void)
11049 {
11050   int newrex, i, length;
11051   rex = 0;
11052   prefixes = 0;
11053   used_prefixes = 0;
11054   rex_used = 0;
11055   last_lock_prefix = -1;
11056   last_repz_prefix = -1;
11057   last_repnz_prefix = -1;
11058   last_data_prefix = -1;
11059   last_addr_prefix = -1;
11060   last_rex_prefix = -1;
11061   last_seg_prefix = -1;
11062   fwait_prefix = -1;
11063   active_seg_prefix = 0;
11064   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
11065     all_prefixes[i] = 0;
11066   i = 0;
11067   length = 0;
11068   /* The maximum instruction length is 15bytes.  */
11069   while (length < MAX_CODE_LENGTH - 1)
11070     {
11071       FETCH_DATA (the_info, codep + 1);
11072       newrex = 0;
11073       switch (*codep)
11074         {
11075         /* REX prefixes family.  */
11076         case 0x40:
11077         case 0x41:
11078         case 0x42:
11079         case 0x43:
11080         case 0x44:
11081         case 0x45:
11082         case 0x46:
11083         case 0x47:
11084         case 0x48:
11085         case 0x49:
11086         case 0x4a:
11087         case 0x4b:
11088         case 0x4c:
11089         case 0x4d:
11090         case 0x4e:
11091         case 0x4f:
11092           if (address_mode == mode_64bit)
11093             newrex = *codep;
11094           else
11095             return 1;
11096           last_rex_prefix = i;
11097           break;
11098         case 0xf3:
11099           prefixes |= PREFIX_REPZ;
11100           last_repz_prefix = i;
11101           break;
11102         case 0xf2:
11103           prefixes |= PREFIX_REPNZ;
11104           last_repnz_prefix = i;
11105           break;
11106         case 0xf0:
11107           prefixes |= PREFIX_LOCK;
11108           last_lock_prefix = i;
11109           break;
11110         case 0x2e:
11111           prefixes |= PREFIX_CS;
11112           last_seg_prefix = i;
11113           active_seg_prefix = PREFIX_CS;
11114           break;
11115         case 0x36:
11116           prefixes |= PREFIX_SS;
11117           last_seg_prefix = i;
11118           active_seg_prefix = PREFIX_SS;
11119           break;
11120         case 0x3e:
11121           prefixes |= PREFIX_DS;
11122           last_seg_prefix = i;
11123           active_seg_prefix = PREFIX_DS;
11124           break;
11125         case 0x26:
11126           prefixes |= PREFIX_ES;
11127           last_seg_prefix = i;
11128           active_seg_prefix = PREFIX_ES;
11129           break;
11130         case 0x64:
11131           prefixes |= PREFIX_FS;
11132           last_seg_prefix = i;
11133           active_seg_prefix = PREFIX_FS;
11134           break;
11135         case 0x65:
11136           prefixes |= PREFIX_GS;
11137           last_seg_prefix = i;
11138           active_seg_prefix = PREFIX_GS;
11139           break;
11140         case 0x66:
11141           prefixes |= PREFIX_DATA;
11142           last_data_prefix = i;
11143           break;
11144         case 0x67:
11145           prefixes |= PREFIX_ADDR;
11146           last_addr_prefix = i;
11147           break;
11148         case FWAIT_OPCODE:
11149           /* fwait is really an instruction.  If there are prefixes
11150              before the fwait, they belong to the fwait, *not* to the
11151              following instruction.  */
11152           fwait_prefix = i;
11153           if (prefixes || rex)
11154             {
11155               prefixes |= PREFIX_FWAIT;
11156               codep++;
11157               /* This ensures that the previous REX prefixes are noticed
11158                  as unused prefixes, as in the return case below.  */
11159               rex_used = rex;
11160               return 1;
11161             }
11162           prefixes = PREFIX_FWAIT;
11163           break;
11164         default:
11165           return 1;
11166         }
11167       /* Rex is ignored when followed by another prefix.  */
11168       if (rex)
11169         {
11170           rex_used = rex;
11171           return 1;
11172         }
11173       if (*codep != FWAIT_OPCODE)
11174         all_prefixes[i++] = *codep;
11175       rex = newrex;
11176       codep++;
11177       length++;
11178     }
11179   return 0;
11180 }
11181
11182 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
11183    prefix byte.  */
11184
11185 static const char *
11186 prefix_name (int pref, int sizeflag)
11187 {
11188   static const char *rexes [16] =
11189     {
11190       "rex",            /* 0x40 */
11191       "rex.B",          /* 0x41 */
11192       "rex.X",          /* 0x42 */
11193       "rex.XB",         /* 0x43 */
11194       "rex.R",          /* 0x44 */
11195       "rex.RB",         /* 0x45 */
11196       "rex.RX",         /* 0x46 */
11197       "rex.RXB",        /* 0x47 */
11198       "rex.W",          /* 0x48 */
11199       "rex.WB",         /* 0x49 */
11200       "rex.WX",         /* 0x4a */
11201       "rex.WXB",        /* 0x4b */
11202       "rex.WR",         /* 0x4c */
11203       "rex.WRB",        /* 0x4d */
11204       "rex.WRX",        /* 0x4e */
11205       "rex.WRXB",       /* 0x4f */
11206     };
11207
11208   switch (pref)
11209     {
11210     /* REX prefixes family.  */
11211     case 0x40:
11212     case 0x41:
11213     case 0x42:
11214     case 0x43:
11215     case 0x44:
11216     case 0x45:
11217     case 0x46:
11218     case 0x47:
11219     case 0x48:
11220     case 0x49:
11221     case 0x4a:
11222     case 0x4b:
11223     case 0x4c:
11224     case 0x4d:
11225     case 0x4e:
11226     case 0x4f:
11227       return rexes [pref - 0x40];
11228     case 0xf3:
11229       return "repz";
11230     case 0xf2:
11231       return "repnz";
11232     case 0xf0:
11233       return "lock";
11234     case 0x2e:
11235       return "cs";
11236     case 0x36:
11237       return "ss";
11238     case 0x3e:
11239       return "ds";
11240     case 0x26:
11241       return "es";
11242     case 0x64:
11243       return "fs";
11244     case 0x65:
11245       return "gs";
11246     case 0x66:
11247       return (sizeflag & DFLAG) ? "data16" : "data32";
11248     case 0x67:
11249       if (address_mode == mode_64bit)
11250         return (sizeflag & AFLAG) ? "addr32" : "addr64";
11251       else
11252         return (sizeflag & AFLAG) ? "addr16" : "addr32";
11253     case FWAIT_OPCODE:
11254       return "fwait";
11255     case REP_PREFIX:
11256       return "rep";
11257     case XACQUIRE_PREFIX:
11258       return "xacquire";
11259     case XRELEASE_PREFIX:
11260       return "xrelease";
11261     case BND_PREFIX:
11262       return "bnd";
11263     case NOTRACK_PREFIX:
11264       return "notrack";
11265     default:
11266       return NULL;
11267     }
11268 }
11269
11270 static char op_out[MAX_OPERANDS][100];
11271 static int op_ad, op_index[MAX_OPERANDS];
11272 static int two_source_ops;
11273 static bfd_vma op_address[MAX_OPERANDS];
11274 static bfd_vma op_riprel[MAX_OPERANDS];
11275 static bfd_vma start_pc;
11276
11277 /*
11278  *   On the 386's of 1988, the maximum length of an instruction is 15 bytes.
11279  *   (see topic "Redundant prefixes" in the "Differences from 8086"
11280  *   section of the "Virtual 8086 Mode" chapter.)
11281  * 'pc' should be the address of this instruction, it will
11282  *   be used to print the target address if this is a relative jump or call
11283  * The function returns the length of this instruction in bytes.
11284  */
11285
11286 static char intel_syntax;
11287 static char intel_mnemonic = !SYSV386_COMPAT;
11288 static char open_char;
11289 static char close_char;
11290 static char separator_char;
11291 static char scale_char;
11292
11293 enum x86_64_isa
11294 {
11295   amd64 = 1,
11296   intel64
11297 };
11298
11299 static enum x86_64_isa isa64;
11300
11301 /* Here for backwards compatibility.  When gdb stops using
11302    print_insn_i386_att and print_insn_i386_intel these functions can
11303    disappear, and print_insn_i386 be merged into print_insn.  */
11304 int
11305 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
11306 {
11307   intel_syntax = 0;
11308
11309   return print_insn (pc, info);
11310 }
11311
11312 int
11313 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
11314 {
11315   intel_syntax = 1;
11316
11317   return print_insn (pc, info);
11318 }
11319
11320 int
11321 print_insn_i386 (bfd_vma pc, disassemble_info *info)
11322 {
11323   intel_syntax = -1;
11324
11325   return print_insn (pc, info);
11326 }
11327
11328 void
11329 print_i386_disassembler_options (FILE *stream)
11330 {
11331   fprintf (stream, _("\n\
11332 The following i386/x86-64 specific disassembler options are supported for use\n\
11333 with the -M switch (multiple options should be separated by commas):\n"));
11334
11335   fprintf (stream, _("  x86-64      Disassemble in 64bit mode\n"));
11336   fprintf (stream, _("  i386        Disassemble in 32bit mode\n"));
11337   fprintf (stream, _("  i8086       Disassemble in 16bit mode\n"));
11338   fprintf (stream, _("  att         Display instruction in AT&T syntax\n"));
11339   fprintf (stream, _("  intel       Display instruction in Intel syntax\n"));
11340   fprintf (stream, _("  att-mnemonic\n"
11341                      "              Display instruction in AT&T mnemonic\n"));
11342   fprintf (stream, _("  intel-mnemonic\n"
11343                      "              Display instruction in Intel mnemonic\n"));
11344   fprintf (stream, _("  addr64      Assume 64bit address size\n"));
11345   fprintf (stream, _("  addr32      Assume 32bit address size\n"));
11346   fprintf (stream, _("  addr16      Assume 16bit address size\n"));
11347   fprintf (stream, _("  data32      Assume 32bit data size\n"));
11348   fprintf (stream, _("  data16      Assume 16bit data size\n"));
11349   fprintf (stream, _("  suffix      Always display instruction suffix in AT&T syntax\n"));
11350   fprintf (stream, _("  amd64       Display instruction in AMD64 ISA\n"));
11351   fprintf (stream, _("  intel64     Display instruction in Intel64 ISA\n"));
11352 }
11353
11354 /* Bad opcode.  */
11355 static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 };
11356
11357 /* Get a pointer to struct dis386 with a valid name.  */
11358
11359 static const struct dis386 *
11360 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
11361 {
11362   int vindex, vex_table_index;
11363
11364   if (dp->name != NULL)
11365     return dp;
11366
11367   switch (dp->op[0].bytemode)
11368     {
11369     case USE_REG_TABLE:
11370       dp = &reg_table[dp->op[1].bytemode][modrm.reg];
11371       break;
11372
11373     case USE_MOD_TABLE:
11374       vindex = modrm.mod == 0x3 ? 1 : 0;
11375       dp = &mod_table[dp->op[1].bytemode][vindex];
11376       break;
11377
11378     case USE_RM_TABLE:
11379       dp = &rm_table[dp->op[1].bytemode][modrm.rm];
11380       break;
11381
11382     case USE_PREFIX_TABLE:
11383       if (need_vex)
11384         {
11385           /* The prefix in VEX is implicit.  */
11386           switch (vex.prefix)
11387             {
11388             case 0:
11389               vindex = 0;
11390               break;
11391             case REPE_PREFIX_OPCODE:
11392               vindex = 1;
11393               break;
11394             case DATA_PREFIX_OPCODE:
11395               vindex = 2;
11396               break;
11397             case REPNE_PREFIX_OPCODE:
11398               vindex = 3;
11399               break;
11400             default:
11401               abort ();
11402               break;
11403             }
11404         }
11405       else
11406         {
11407           int last_prefix = -1;
11408           int prefix = 0;
11409           vindex = 0;
11410           /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
11411              When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
11412              last one wins.  */
11413           if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
11414             {
11415               if (last_repz_prefix > last_repnz_prefix)
11416                 {
11417                   vindex = 1;
11418                   prefix = PREFIX_REPZ;
11419                   last_prefix = last_repz_prefix;
11420                 }
11421               else
11422                 {
11423                   vindex = 3;
11424                   prefix = PREFIX_REPNZ;
11425                   last_prefix = last_repnz_prefix;
11426                 }
11427
11428               /* Check if prefix should be ignored.  */
11429               if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement
11430                      & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT)
11431                    & prefix) != 0)
11432                 vindex = 0;
11433             }
11434
11435           if (vindex == 0 && (prefixes & PREFIX_DATA) != 0)
11436             {
11437               vindex = 2;
11438               prefix = PREFIX_DATA;
11439               last_prefix = last_data_prefix;
11440             }
11441
11442           if (vindex != 0)
11443             {
11444               used_prefixes |= prefix;
11445               all_prefixes[last_prefix] = 0;
11446             }
11447         }
11448       dp = &prefix_table[dp->op[1].bytemode][vindex];
11449       break;
11450
11451     case USE_X86_64_TABLE:
11452       vindex = address_mode == mode_64bit ? 1 : 0;
11453       dp = &x86_64_table[dp->op[1].bytemode][vindex];
11454       break;
11455
11456     case USE_3BYTE_TABLE:
11457       FETCH_DATA (info, codep + 2);
11458       vindex = *codep++;
11459       dp = &three_byte_table[dp->op[1].bytemode][vindex];
11460       end_codep = codep;
11461       modrm.mod = (*codep >> 6) & 3;
11462       modrm.reg = (*codep >> 3) & 7;
11463       modrm.rm = *codep & 7;
11464       break;
11465
11466     case USE_VEX_LEN_TABLE:
11467       if (!need_vex)
11468         abort ();
11469
11470       switch (vex.length)
11471         {
11472         case 128:
11473           vindex = 0;
11474           break;
11475         case 256:
11476           vindex = 1;
11477           break;
11478         default:
11479           abort ();
11480           break;
11481         }
11482
11483       dp = &vex_len_table[dp->op[1].bytemode][vindex];
11484       break;
11485
11486     case USE_EVEX_LEN_TABLE:
11487       if (!vex.evex)
11488         abort ();
11489
11490       switch (vex.length)
11491         {
11492         case 128:
11493           vindex = 0;
11494           break;
11495         case 256:
11496           vindex = 1;
11497           break;
11498         case 512:
11499           vindex = 2;
11500           break;
11501         default:
11502           abort ();
11503           break;
11504         }
11505
11506       dp = &evex_len_table[dp->op[1].bytemode][vindex];
11507       break;
11508
11509     case USE_XOP_8F_TABLE:
11510       FETCH_DATA (info, codep + 3);
11511       rex = ~(*codep >> 5) & 0x7;
11512
11513       /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm".  */
11514       switch ((*codep & 0x1f))
11515         {
11516         default:
11517           dp = &bad_opcode;
11518           return dp;
11519         case 0x8:
11520           vex_table_index = XOP_08;
11521           break;
11522         case 0x9:
11523           vex_table_index = XOP_09;
11524           break;
11525         case 0xa:
11526           vex_table_index = XOP_0A;
11527           break;
11528         }
11529       codep++;
11530       vex.w = *codep & 0x80;
11531       if (vex.w && address_mode == mode_64bit)
11532         rex |= REX_W;
11533
11534       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11535       if (address_mode != mode_64bit)
11536         {
11537           /* In 16/32-bit mode REX_B is silently ignored.  */
11538           rex &= ~REX_B;
11539         }
11540
11541       vex.length = (*codep & 0x4) ? 256 : 128;
11542       switch ((*codep & 0x3))
11543         {
11544         case 0:
11545           break;
11546         case 1:
11547           vex.prefix = DATA_PREFIX_OPCODE;
11548           break;
11549         case 2:
11550           vex.prefix = REPE_PREFIX_OPCODE;
11551           break;
11552         case 3:
11553           vex.prefix = REPNE_PREFIX_OPCODE;
11554           break;
11555         }
11556       need_vex = 1;
11557       need_vex_reg = 1;
11558       codep++;
11559       vindex = *codep++;
11560       dp = &xop_table[vex_table_index][vindex];
11561
11562       end_codep = codep;
11563       FETCH_DATA (info, codep + 1);
11564       modrm.mod = (*codep >> 6) & 3;
11565       modrm.reg = (*codep >> 3) & 7;
11566       modrm.rm = *codep & 7;
11567       break;
11568
11569     case USE_VEX_C4_TABLE:
11570       /* VEX prefix.  */
11571       FETCH_DATA (info, codep + 3);
11572       rex = ~(*codep >> 5) & 0x7;
11573       switch ((*codep & 0x1f))
11574         {
11575         default:
11576           dp = &bad_opcode;
11577           return dp;
11578         case 0x1:
11579           vex_table_index = VEX_0F;
11580           break;
11581         case 0x2:
11582           vex_table_index = VEX_0F38;
11583           break;
11584         case 0x3:
11585           vex_table_index = VEX_0F3A;
11586           break;
11587         }
11588       codep++;
11589       vex.w = *codep & 0x80;
11590       if (address_mode == mode_64bit)
11591         {
11592           if (vex.w)
11593             rex |= REX_W;
11594         }
11595       else
11596         {
11597           /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
11598              is ignored, other REX bits are 0 and the highest bit in
11599              VEX.vvvv is also ignored (but we mustn't clear it here).  */
11600           rex = 0;
11601         }
11602       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11603       vex.length = (*codep & 0x4) ? 256 : 128;
11604       switch ((*codep & 0x3))
11605         {
11606         case 0:
11607           break;
11608         case 1:
11609           vex.prefix = DATA_PREFIX_OPCODE;
11610           break;
11611         case 2:
11612           vex.prefix = REPE_PREFIX_OPCODE;
11613           break;
11614         case 3:
11615           vex.prefix = REPNE_PREFIX_OPCODE;
11616           break;
11617         }
11618       need_vex = 1;
11619       need_vex_reg = 1;
11620       codep++;
11621       vindex = *codep++;
11622       dp = &vex_table[vex_table_index][vindex];
11623       end_codep = codep;
11624       /* There is no MODRM byte for VEX0F 77.  */
11625       if (vex_table_index != VEX_0F || vindex != 0x77)
11626         {
11627           FETCH_DATA (info, codep + 1);
11628           modrm.mod = (*codep >> 6) & 3;
11629           modrm.reg = (*codep >> 3) & 7;
11630           modrm.rm = *codep & 7;
11631         }
11632       break;
11633
11634     case USE_VEX_C5_TABLE:
11635       /* VEX prefix.  */
11636       FETCH_DATA (info, codep + 2);
11637       rex = (*codep & 0x80) ? 0 : REX_R;
11638
11639       /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
11640          VEX.vvvv is 1.  */
11641       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11642       vex.length = (*codep & 0x4) ? 256 : 128;
11643       switch ((*codep & 0x3))
11644         {
11645         case 0:
11646           break;
11647         case 1:
11648           vex.prefix = DATA_PREFIX_OPCODE;
11649           break;
11650         case 2:
11651           vex.prefix = REPE_PREFIX_OPCODE;
11652           break;
11653         case 3:
11654           vex.prefix = REPNE_PREFIX_OPCODE;
11655           break;
11656         }
11657       need_vex = 1;
11658       need_vex_reg = 1;
11659       codep++;
11660       vindex = *codep++;
11661       dp = &vex_table[dp->op[1].bytemode][vindex];
11662       end_codep = codep;
11663       /* There is no MODRM byte for VEX 77.  */
11664       if (vindex != 0x77)
11665         {
11666           FETCH_DATA (info, codep + 1);
11667           modrm.mod = (*codep >> 6) & 3;
11668           modrm.reg = (*codep >> 3) & 7;
11669           modrm.rm = *codep & 7;
11670         }
11671       break;
11672
11673     case USE_VEX_W_TABLE:
11674       if (!need_vex)
11675         abort ();
11676
11677       dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
11678       break;
11679
11680     case USE_EVEX_TABLE:
11681       two_source_ops = 0;
11682       /* EVEX prefix.  */
11683       vex.evex = 1;
11684       FETCH_DATA (info, codep + 4);
11685       /* The first byte after 0x62.  */
11686       rex = ~(*codep >> 5) & 0x7;
11687       vex.r = *codep & 0x10;
11688       switch ((*codep & 0xf))
11689         {
11690         default:
11691           return &bad_opcode;
11692         case 0x1:
11693           vex_table_index = EVEX_0F;
11694           break;
11695         case 0x2:
11696           vex_table_index = EVEX_0F38;
11697           break;
11698         case 0x3:
11699           vex_table_index = EVEX_0F3A;
11700           break;
11701         }
11702
11703       /* The second byte after 0x62.  */
11704       codep++;
11705       vex.w = *codep & 0x80;
11706       if (vex.w && address_mode == mode_64bit)
11707         rex |= REX_W;
11708
11709       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11710
11711       /* The U bit.  */
11712       if (!(*codep & 0x4))
11713         return &bad_opcode;
11714
11715       switch ((*codep & 0x3))
11716         {
11717         case 0:
11718           break;
11719         case 1:
11720           vex.prefix = DATA_PREFIX_OPCODE;
11721           break;
11722         case 2:
11723           vex.prefix = REPE_PREFIX_OPCODE;
11724           break;
11725         case 3:
11726           vex.prefix = REPNE_PREFIX_OPCODE;
11727           break;
11728         }
11729
11730       /* The third byte after 0x62.  */
11731       codep++;
11732
11733       /* Remember the static rounding bits.  */
11734       vex.ll = (*codep >> 5) & 3;
11735       vex.b = (*codep & 0x10) != 0;
11736
11737       vex.v = *codep & 0x8;
11738       vex.mask_register_specifier = *codep & 0x7;
11739       vex.zeroing = *codep & 0x80;
11740
11741       if (address_mode != mode_64bit)
11742         {
11743           /* In 16/32-bit mode silently ignore following bits.  */
11744           rex &= ~REX_B;
11745           vex.r = 1;
11746           vex.v = 1;
11747         }
11748
11749       need_vex = 1;
11750       need_vex_reg = 1;
11751       codep++;
11752       vindex = *codep++;
11753       dp = &evex_table[vex_table_index][vindex];
11754       end_codep = codep;
11755       FETCH_DATA (info, codep + 1);
11756       modrm.mod = (*codep >> 6) & 3;
11757       modrm.reg = (*codep >> 3) & 7;
11758       modrm.rm = *codep & 7;
11759
11760       /* Set vector length.  */
11761       if (modrm.mod == 3 && vex.b)
11762         vex.length = 512;
11763       else
11764         {
11765           switch (vex.ll)
11766             {
11767             case 0x0:
11768               vex.length = 128;
11769               break;
11770             case 0x1:
11771               vex.length = 256;
11772               break;
11773             case 0x2:
11774               vex.length = 512;
11775               break;
11776             default:
11777               return &bad_opcode;
11778             }
11779         }
11780       break;
11781
11782     case 0:
11783       dp = &bad_opcode;
11784       break;
11785
11786     default:
11787       abort ();
11788     }
11789
11790   if (dp->name != NULL)
11791     return dp;
11792   else
11793     return get_valid_dis386 (dp, info);
11794 }
11795
11796 static void
11797 get_sib (disassemble_info *info, int sizeflag)
11798 {
11799   /* If modrm.mod == 3, operand must be register.  */
11800   if (need_modrm
11801       && ((sizeflag & AFLAG) || address_mode == mode_64bit)
11802       && modrm.mod != 3
11803       && modrm.rm == 4)
11804     {
11805       FETCH_DATA (info, codep + 2);
11806       sib.index = (codep [1] >> 3) & 7;
11807       sib.scale = (codep [1] >> 6) & 3;
11808       sib.base = codep [1] & 7;
11809     }
11810 }
11811
11812 static int
11813 print_insn (bfd_vma pc, disassemble_info *info)
11814 {
11815   const struct dis386 *dp;
11816   int i;
11817   char *op_txt[MAX_OPERANDS];
11818   int needcomma;
11819   int sizeflag, orig_sizeflag;
11820   const char *p;
11821   struct dis_private priv;
11822   int prefix_length;
11823
11824   priv.orig_sizeflag = AFLAG | DFLAG;
11825   if ((info->mach & bfd_mach_i386_i386) != 0)
11826     address_mode = mode_32bit;
11827   else if (info->mach == bfd_mach_i386_i8086)
11828     {
11829       address_mode = mode_16bit;
11830       priv.orig_sizeflag = 0;
11831     }
11832   else
11833     address_mode = mode_64bit;
11834
11835   if (intel_syntax == (char) -1)
11836     intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0;
11837
11838   for (p = info->disassembler_options; p != NULL; )
11839     {
11840       if (CONST_STRNEQ (p, "amd64"))
11841         isa64 = amd64;
11842       else if (CONST_STRNEQ (p, "intel64"))
11843         isa64 = intel64;
11844       else if (CONST_STRNEQ (p, "x86-64"))
11845         {
11846           address_mode = mode_64bit;
11847           priv.orig_sizeflag |= AFLAG | DFLAG;
11848         }
11849       else if (CONST_STRNEQ (p, "i386"))
11850         {
11851           address_mode = mode_32bit;
11852           priv.orig_sizeflag |= AFLAG | DFLAG;
11853         }
11854       else if (CONST_STRNEQ (p, "i8086"))
11855         {
11856           address_mode = mode_16bit;
11857           priv.orig_sizeflag &= ~(AFLAG | DFLAG);
11858         }
11859       else if (CONST_STRNEQ (p, "intel"))
11860         {
11861           intel_syntax = 1;
11862           if (CONST_STRNEQ (p + 5, "-mnemonic"))
11863             intel_mnemonic = 1;
11864         }
11865       else if (CONST_STRNEQ (p, "att"))
11866         {
11867           intel_syntax = 0;
11868           if (CONST_STRNEQ (p + 3, "-mnemonic"))
11869             intel_mnemonic = 0;
11870         }
11871       else if (CONST_STRNEQ (p, "addr"))
11872         {
11873           if (address_mode == mode_64bit)
11874             {
11875               if (p[4] == '3' && p[5] == '2')
11876                 priv.orig_sizeflag &= ~AFLAG;
11877               else if (p[4] == '6' && p[5] == '4')
11878                 priv.orig_sizeflag |= AFLAG;
11879             }
11880           else
11881             {
11882               if (p[4] == '1' && p[5] == '6')
11883                 priv.orig_sizeflag &= ~AFLAG;
11884               else if (p[4] == '3' && p[5] == '2')
11885                 priv.orig_sizeflag |= AFLAG;
11886             }
11887         }
11888       else if (CONST_STRNEQ (p, "data"))
11889         {
11890           if (p[4] == '1' && p[5] == '6')
11891             priv.orig_sizeflag &= ~DFLAG;
11892           else if (p[4] == '3' && p[5] == '2')
11893             priv.orig_sizeflag |= DFLAG;
11894         }
11895       else if (CONST_STRNEQ (p, "suffix"))
11896         priv.orig_sizeflag |= SUFFIX_ALWAYS;
11897
11898       p = strchr (p, ',');
11899       if (p != NULL)
11900         p++;
11901     }
11902
11903   if (address_mode == mode_64bit && sizeof (bfd_vma) < 8)
11904     {
11905       (*info->fprintf_func) (info->stream,
11906                              _("64-bit address is disabled"));
11907       return -1;
11908     }
11909
11910   if (intel_syntax)
11911     {
11912       names64 = intel_names64;
11913       names32 = intel_names32;
11914       names16 = intel_names16;
11915       names8 = intel_names8;
11916       names8rex = intel_names8rex;
11917       names_seg = intel_names_seg;
11918       names_mm = intel_names_mm;
11919       names_bnd = intel_names_bnd;
11920       names_xmm = intel_names_xmm;
11921       names_ymm = intel_names_ymm;
11922       names_zmm = intel_names_zmm;
11923       index64 = intel_index64;
11924       index32 = intel_index32;
11925       names_mask = intel_names_mask;
11926       index16 = intel_index16;
11927       open_char = '[';
11928       close_char = ']';
11929       separator_char = '+';
11930       scale_char = '*';
11931     }
11932   else
11933     {
11934       names64 = att_names64;
11935       names32 = att_names32;
11936       names16 = att_names16;
11937       names8 = att_names8;
11938       names8rex = att_names8rex;
11939       names_seg = att_names_seg;
11940       names_mm = att_names_mm;
11941       names_bnd = att_names_bnd;
11942       names_xmm = att_names_xmm;
11943       names_ymm = att_names_ymm;
11944       names_zmm = att_names_zmm;
11945       index64 = att_index64;
11946       index32 = att_index32;
11947       names_mask = att_names_mask;
11948       index16 = att_index16;
11949       open_char = '(';
11950       close_char =  ')';
11951       separator_char = ',';
11952       scale_char = ',';
11953     }
11954
11955   /* The output looks better if we put 7 bytes on a line, since that
11956      puts most long word instructions on a single line.  Use 8 bytes
11957      for Intel L1OM.  */
11958   if ((info->mach & bfd_mach_l1om) != 0)
11959     info->bytes_per_line = 8;
11960   else
11961     info->bytes_per_line = 7;
11962
11963   info->private_data = &priv;
11964   priv.max_fetched = priv.the_buffer;
11965   priv.insn_start = pc;
11966
11967   obuf[0] = 0;
11968   for (i = 0; i < MAX_OPERANDS; ++i)
11969     {
11970       op_out[i][0] = 0;
11971       op_index[i] = -1;
11972     }
11973
11974   the_info = info;
11975   start_pc = pc;
11976   start_codep = priv.the_buffer;
11977   codep = priv.the_buffer;
11978
11979   if (OPCODES_SIGSETJMP (priv.bailout) != 0)
11980     {
11981       const char *name;
11982
11983       /* Getting here means we tried for data but didn't get it.  That
11984          means we have an incomplete instruction of some sort.  Just
11985          print the first byte as a prefix or a .byte pseudo-op.  */
11986       if (codep > priv.the_buffer)
11987         {
11988           name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
11989           if (name != NULL)
11990             (*info->fprintf_func) (info->stream, "%s", name);
11991           else
11992             {
11993               /* Just print the first byte as a .byte instruction.  */
11994               (*info->fprintf_func) (info->stream, ".byte 0x%x",
11995                                      (unsigned int) priv.the_buffer[0]);
11996             }
11997
11998           return 1;
11999         }
12000
12001       return -1;
12002     }
12003
12004   obufp = obuf;
12005   sizeflag = priv.orig_sizeflag;
12006
12007   if (!ckprefix () || rex_used)
12008     {
12009       /* Too many prefixes or unused REX prefixes.  */
12010       for (i = 0;
12011            i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i];
12012            i++)
12013         (*info->fprintf_func) (info->stream, "%s%s",
12014                                i == 0 ? "" : " ",
12015                                prefix_name (all_prefixes[i], sizeflag));
12016       return i;
12017     }
12018
12019   insn_codep = codep;
12020
12021   FETCH_DATA (info, codep + 1);
12022   two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
12023
12024   if (((prefixes & PREFIX_FWAIT)
12025        && ((*codep < 0xd8) || (*codep > 0xdf))))
12026     {
12027       /* Handle prefixes before fwait.  */
12028       for (i = 0; i < fwait_prefix && all_prefixes[i];
12029            i++)
12030         (*info->fprintf_func) (info->stream, "%s ",
12031                                prefix_name (all_prefixes[i], sizeflag));
12032       (*info->fprintf_func) (info->stream, "fwait");
12033       return i + 1;
12034     }
12035
12036   if (*codep == 0x0f)
12037     {
12038       unsigned char threebyte;
12039
12040       codep++;
12041       FETCH_DATA (info, codep + 1);
12042       threebyte = *codep;
12043       dp = &dis386_twobyte[threebyte];
12044       need_modrm = twobyte_has_modrm[*codep];
12045       codep++;
12046     }
12047   else
12048     {
12049       dp = &dis386[*codep];
12050       need_modrm = onebyte_has_modrm[*codep];
12051       codep++;
12052     }
12053
12054   /* Save sizeflag for printing the extra prefixes later before updating
12055      it for mnemonic and operand processing.  The prefix names depend
12056      only on the address mode.  */
12057   orig_sizeflag = sizeflag;
12058   if (prefixes & PREFIX_ADDR)
12059     sizeflag ^= AFLAG;
12060   if ((prefixes & PREFIX_DATA))
12061     sizeflag ^= DFLAG;
12062
12063   end_codep = codep;
12064   if (need_modrm)
12065     {
12066       FETCH_DATA (info, codep + 1);
12067       modrm.mod = (*codep >> 6) & 3;
12068       modrm.reg = (*codep >> 3) & 7;
12069       modrm.rm = *codep & 7;
12070     }
12071
12072   need_vex = 0;
12073   need_vex_reg = 0;
12074   vex_w_done = 0;
12075   memset (&vex, 0, sizeof (vex));
12076
12077   if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
12078     {
12079       get_sib (info, sizeflag);
12080       dofloat (sizeflag);
12081     }
12082   else
12083     {
12084       dp = get_valid_dis386 (dp, info);
12085       if (dp != NULL && putop (dp->name, sizeflag) == 0)
12086         {
12087           get_sib (info, sizeflag);
12088           for (i = 0; i < MAX_OPERANDS; ++i)
12089             {
12090               obufp = op_out[i];
12091               op_ad = MAX_OPERANDS - 1 - i;
12092               if (dp->op[i].rtn)
12093                 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
12094               /* For EVEX instruction after the last operand masking
12095                  should be printed.  */
12096               if (i == 0 && vex.evex)
12097                 {
12098                   /* Don't print {%k0}.  */
12099                   if (vex.mask_register_specifier)
12100                     {
12101                       oappend ("{");
12102                       oappend (names_mask[vex.mask_register_specifier]);
12103                       oappend ("}");
12104                     }
12105                   if (vex.zeroing)
12106                     oappend ("{z}");
12107                 }
12108             }
12109         }
12110     }
12111
12112   /* Clear instruction information.  */
12113   if (the_info)
12114     {
12115       the_info->insn_info_valid = 0;
12116       the_info->branch_delay_insns = 0;
12117       the_info->data_size = 0;
12118       the_info->insn_type = dis_noninsn;
12119       the_info->target = 0;
12120       the_info->target2 = 0;
12121     }
12122
12123   /* Reset jump operation indicator.  */
12124   op_is_jump = FALSE;
12125
12126   {
12127     int jump_detection = 0;
12128
12129     /* Extract flags.  */
12130     for (i = 0; i < MAX_OPERANDS; ++i)
12131       {
12132         if ((dp->op[i].rtn == OP_J)
12133             || (dp->op[i].rtn == OP_indirE))
12134           jump_detection |= 1;
12135         else if ((dp->op[i].rtn == BND_Fixup)
12136                  || (!dp->op[i].rtn && !dp->op[i].bytemode))
12137           jump_detection |= 2;
12138         else if ((dp->op[i].bytemode == cond_jump_mode)
12139                  || (dp->op[i].bytemode == loop_jcxz_mode))
12140           jump_detection |= 4;
12141       }
12142
12143     /* Determine if this is a jump or branch.  */
12144     if ((jump_detection & 0x3) == 0x3)
12145       {
12146         op_is_jump = TRUE;
12147         if (jump_detection & 0x4)
12148           the_info->insn_type = dis_condbranch;
12149         else
12150           the_info->insn_type =
12151             (dp->name && !strncmp(dp->name, "call", 4))
12152             ? dis_jsr : dis_branch;
12153       }
12154   }
12155
12156   /* If VEX.vvvv and EVEX.vvvv are unused, they must be all 1s, which
12157      are all 0s in inverted form.  */
12158   if (need_vex && vex.register_specifier != 0)
12159     {
12160       (*info->fprintf_func) (info->stream, "(bad)");
12161       return end_codep - priv.the_buffer;
12162     }
12163
12164   /* Check if the REX prefix is used.  */
12165   if ((rex ^ rex_used) == 0 && !need_vex && last_rex_prefix >= 0)
12166     all_prefixes[last_rex_prefix] = 0;
12167
12168   /* Check if the SEG prefix is used.  */
12169   if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
12170                    | PREFIX_FS | PREFIX_GS)) != 0
12171       && (used_prefixes & active_seg_prefix) != 0)
12172     all_prefixes[last_seg_prefix] = 0;
12173
12174   /* Check if the ADDR prefix is used.  */
12175   if ((prefixes & PREFIX_ADDR) != 0
12176       && (used_prefixes & PREFIX_ADDR) != 0)
12177     all_prefixes[last_addr_prefix] = 0;
12178
12179   /* Check if the DATA prefix is used.  */
12180   if ((prefixes & PREFIX_DATA) != 0
12181       && (used_prefixes & PREFIX_DATA) != 0
12182       && !need_vex)
12183     all_prefixes[last_data_prefix] = 0;
12184
12185   /* Print the extra prefixes.  */
12186   prefix_length = 0;
12187   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
12188     if (all_prefixes[i])
12189       {
12190         const char *name;
12191         name = prefix_name (all_prefixes[i], orig_sizeflag);
12192         if (name == NULL)
12193           abort ();
12194         prefix_length += strlen (name) + 1;
12195         (*info->fprintf_func) (info->stream, "%s ", name);
12196       }
12197
12198   /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
12199      unused, opcode is invalid.  Since the PREFIX_DATA prefix may be
12200      used by putop and MMX/SSE operand and may be overriden by the
12201      PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
12202      separately.  */
12203   if (dp->prefix_requirement == PREFIX_OPCODE
12204       && (((need_vex
12205             ? vex.prefix == REPE_PREFIX_OPCODE
12206               || vex.prefix == REPNE_PREFIX_OPCODE
12207             : (prefixes
12208                & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
12209            && (used_prefixes
12210                & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
12211           || (((need_vex
12212                 ? vex.prefix == DATA_PREFIX_OPCODE
12213                 : ((prefixes
12214                     & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
12215                    == PREFIX_DATA))
12216                && (used_prefixes & PREFIX_DATA) == 0))
12217           || (vex.evex && !vex.w != !(used_prefixes & PREFIX_DATA))))
12218     {
12219       (*info->fprintf_func) (info->stream, "(bad)");
12220       return end_codep - priv.the_buffer;
12221     }
12222
12223   /* Check maximum code length.  */
12224   if ((codep - start_codep) > MAX_CODE_LENGTH)
12225     {
12226       (*info->fprintf_func) (info->stream, "(bad)");
12227       return MAX_CODE_LENGTH;
12228     }
12229
12230   obufp = mnemonicendp;
12231   for (i = strlen (obuf) + prefix_length; i < 6; i++)
12232     oappend (" ");
12233   oappend (" ");
12234   (*info->fprintf_func) (info->stream, "%s", obuf);
12235
12236   /* The enter and bound instructions are printed with operands in the same
12237      order as the intel book; everything else is printed in reverse order.  */
12238   if (intel_syntax || two_source_ops)
12239     {
12240       bfd_vma riprel;
12241
12242       for (i = 0; i < MAX_OPERANDS; ++i)
12243         op_txt[i] = op_out[i];
12244
12245       if (intel_syntax && dp && dp->op[2].rtn == OP_Rounding
12246           && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL)
12247         {
12248           op_txt[2] = op_out[3];
12249           op_txt[3] = op_out[2];
12250         }
12251
12252       for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
12253         {
12254           op_ad = op_index[i];
12255           op_index[i] = op_index[MAX_OPERANDS - 1 - i];
12256           op_index[MAX_OPERANDS - 1 - i] = op_ad;
12257           riprel = op_riprel[i];
12258           op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
12259           op_riprel[MAX_OPERANDS - 1 - i] = riprel;
12260         }
12261     }
12262   else
12263     {
12264       for (i = 0; i < MAX_OPERANDS; ++i)
12265         op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
12266     }
12267
12268   needcomma = 0;
12269   for (i = 0; i < MAX_OPERANDS; ++i)
12270     if (*op_txt[i])
12271       {
12272         if (needcomma)
12273           (*info->fprintf_func) (info->stream, ",");
12274         if (op_index[i] != -1 && !op_riprel[i])
12275           {
12276             bfd_vma target = (bfd_vma) op_address[op_index[i]];
12277
12278             if (the_info && op_is_jump)
12279               {
12280                 the_info->insn_info_valid = 1;
12281                 the_info->branch_delay_insns = 0;
12282                 the_info->data_size = 0;
12283                 the_info->target = target;
12284                 the_info->target2 = 0;
12285               }
12286             (*info->print_address_func) (target, info);
12287           }
12288         else
12289           (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
12290         needcomma = 1;
12291       }
12292
12293   for (i = 0; i < MAX_OPERANDS; i++)
12294     if (op_index[i] != -1 && op_riprel[i])
12295       {
12296         (*info->fprintf_func) (info->stream, "        # ");
12297         (*info->print_address_func) ((bfd_vma) (start_pc + (codep - start_codep)
12298                                                 + op_address[op_index[i]]), info);
12299         break;
12300       }
12301   return codep - priv.the_buffer;
12302 }
12303
12304 static const char *float_mem[] = {
12305   /* d8 */
12306   "fadd{s|}",
12307   "fmul{s|}",
12308   "fcom{s|}",
12309   "fcomp{s|}",
12310   "fsub{s|}",
12311   "fsubr{s|}",
12312   "fdiv{s|}",
12313   "fdivr{s|}",
12314   /* d9 */
12315   "fld{s|}",
12316   "(bad)",
12317   "fst{s|}",
12318   "fstp{s|}",
12319   "fldenv{C|C}",
12320   "fldcw",
12321   "fNstenv{C|C}",
12322   "fNstcw",
12323   /* da */
12324   "fiadd{l|}",
12325   "fimul{l|}",
12326   "ficom{l|}",
12327   "ficomp{l|}",
12328   "fisub{l|}",
12329   "fisubr{l|}",
12330   "fidiv{l|}",
12331   "fidivr{l|}",
12332   /* db */
12333   "fild{l|}",
12334   "fisttp{l|}",
12335   "fist{l|}",
12336   "fistp{l|}",
12337   "(bad)",
12338   "fld{t|}",
12339   "(bad)",
12340   "fstp{t|}",
12341   /* dc */
12342   "fadd{l|}",
12343   "fmul{l|}",
12344   "fcom{l|}",
12345   "fcomp{l|}",
12346   "fsub{l|}",
12347   "fsubr{l|}",
12348   "fdiv{l|}",
12349   "fdivr{l|}",
12350   /* dd */
12351   "fld{l|}",
12352   "fisttp{ll|}",
12353   "fst{l||}",
12354   "fstp{l|}",
12355   "frstor{C|C}",
12356   "(bad)",
12357   "fNsave{C|C}",
12358   "fNstsw",
12359   /* de */
12360   "fiadd{s|}",
12361   "fimul{s|}",
12362   "ficom{s|}",
12363   "ficomp{s|}",
12364   "fisub{s|}",
12365   "fisubr{s|}",
12366   "fidiv{s|}",
12367   "fidivr{s|}",
12368   /* df */
12369   "fild{s|}",
12370   "fisttp{s|}",
12371   "fist{s|}",
12372   "fistp{s|}",
12373   "fbld",
12374   "fild{ll|}",
12375   "fbstp",
12376   "fistp{ll|}",
12377 };
12378
12379 static const unsigned char float_mem_mode[] = {
12380   /* d8 */
12381   d_mode,
12382   d_mode,
12383   d_mode,
12384   d_mode,
12385   d_mode,
12386   d_mode,
12387   d_mode,
12388   d_mode,
12389   /* d9 */
12390   d_mode,
12391   0,
12392   d_mode,
12393   d_mode,
12394   0,
12395   w_mode,
12396   0,
12397   w_mode,
12398   /* da */
12399   d_mode,
12400   d_mode,
12401   d_mode,
12402   d_mode,
12403   d_mode,
12404   d_mode,
12405   d_mode,
12406   d_mode,
12407   /* db */
12408   d_mode,
12409   d_mode,
12410   d_mode,
12411   d_mode,
12412   0,
12413   t_mode,
12414   0,
12415   t_mode,
12416   /* dc */
12417   q_mode,
12418   q_mode,
12419   q_mode,
12420   q_mode,
12421   q_mode,
12422   q_mode,
12423   q_mode,
12424   q_mode,
12425   /* dd */
12426   q_mode,
12427   q_mode,
12428   q_mode,
12429   q_mode,
12430   0,
12431   0,
12432   0,
12433   w_mode,
12434   /* de */
12435   w_mode,
12436   w_mode,
12437   w_mode,
12438   w_mode,
12439   w_mode,
12440   w_mode,
12441   w_mode,
12442   w_mode,
12443   /* df */
12444   w_mode,
12445   w_mode,
12446   w_mode,
12447   w_mode,
12448   t_mode,
12449   q_mode,
12450   t_mode,
12451   q_mode
12452 };
12453
12454 #define ST { OP_ST, 0 }
12455 #define STi { OP_STi, 0 }
12456
12457 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
12458 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
12459 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
12460 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
12461 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
12462 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
12463 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
12464 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
12465 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
12466
12467 static const struct dis386 float_reg[][8] = {
12468   /* d8 */
12469   {
12470     { "fadd",   { ST, STi }, 0 },
12471     { "fmul",   { ST, STi }, 0 },
12472     { "fcom",   { STi }, 0 },
12473     { "fcomp",  { STi }, 0 },
12474     { "fsub",   { ST, STi }, 0 },
12475     { "fsubr",  { ST, STi }, 0 },
12476     { "fdiv",   { ST, STi }, 0 },
12477     { "fdivr",  { ST, STi }, 0 },
12478   },
12479   /* d9 */
12480   {
12481     { "fld",    { STi }, 0 },
12482     { "fxch",   { STi }, 0 },
12483     { FGRPd9_2 },
12484     { Bad_Opcode },
12485     { FGRPd9_4 },
12486     { FGRPd9_5 },
12487     { FGRPd9_6 },
12488     { FGRPd9_7 },
12489   },
12490   /* da */
12491   {
12492     { "fcmovb", { ST, STi }, 0 },
12493     { "fcmove", { ST, STi }, 0 },
12494     { "fcmovbe",{ ST, STi }, 0 },
12495     { "fcmovu", { ST, STi }, 0 },
12496     { Bad_Opcode },
12497     { FGRPda_5 },
12498     { Bad_Opcode },
12499     { Bad_Opcode },
12500   },
12501   /* db */
12502   {
12503     { "fcmovnb",{ ST, STi }, 0 },
12504     { "fcmovne",{ ST, STi }, 0 },
12505     { "fcmovnbe",{ ST, STi }, 0 },
12506     { "fcmovnu",{ ST, STi }, 0 },
12507     { FGRPdb_4 },
12508     { "fucomi", { ST, STi }, 0 },
12509     { "fcomi",  { ST, STi }, 0 },
12510     { Bad_Opcode },
12511   },
12512   /* dc */
12513   {
12514     { "fadd",   { STi, ST }, 0 },
12515     { "fmul",   { STi, ST }, 0 },
12516     { Bad_Opcode },
12517     { Bad_Opcode },
12518     { "fsub{!M|r}",     { STi, ST }, 0 },
12519     { "fsub{M|}",       { STi, ST }, 0 },
12520     { "fdiv{!M|r}",     { STi, ST }, 0 },
12521     { "fdiv{M|}",       { STi, ST }, 0 },
12522   },
12523   /* dd */
12524   {
12525     { "ffree",  { STi }, 0 },
12526     { Bad_Opcode },
12527     { "fst",    { STi }, 0 },
12528     { "fstp",   { STi }, 0 },
12529     { "fucom",  { STi }, 0 },
12530     { "fucomp", { STi }, 0 },
12531     { Bad_Opcode },
12532     { Bad_Opcode },
12533   },
12534   /* de */
12535   {
12536     { "faddp",  { STi, ST }, 0 },
12537     { "fmulp",  { STi, ST }, 0 },
12538     { Bad_Opcode },
12539     { FGRPde_3 },
12540     { "fsub{!M|r}p",    { STi, ST }, 0 },
12541     { "fsub{M|}p",      { STi, ST }, 0 },
12542     { "fdiv{!M|r}p",    { STi, ST }, 0 },
12543     { "fdiv{M|}p",      { STi, ST }, 0 },
12544   },
12545   /* df */
12546   {
12547     { "ffreep", { STi }, 0 },
12548     { Bad_Opcode },
12549     { Bad_Opcode },
12550     { Bad_Opcode },
12551     { FGRPdf_4 },
12552     { "fucomip", { ST, STi }, 0 },
12553     { "fcomip", { ST, STi }, 0 },
12554     { Bad_Opcode },
12555   },
12556 };
12557
12558 static char *fgrps[][8] = {
12559   /* Bad opcode 0 */
12560   {
12561     "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12562   },
12563
12564   /* d9_2  1 */
12565   {
12566     "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12567   },
12568
12569   /* d9_4  2 */
12570   {
12571     "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
12572   },
12573
12574   /* d9_5  3 */
12575   {
12576     "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
12577   },
12578
12579   /* d9_6  4 */
12580   {
12581     "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
12582   },
12583
12584   /* d9_7  5 */
12585   {
12586     "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
12587   },
12588
12589   /* da_5  6 */
12590   {
12591     "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12592   },
12593
12594   /* db_4  7 */
12595   {
12596     "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
12597     "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
12598   },
12599
12600   /* de_3  8 */
12601   {
12602     "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12603   },
12604
12605   /* df_4  9 */
12606   {
12607     "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12608   },
12609 };
12610
12611 static void
12612 swap_operand (void)
12613 {
12614   mnemonicendp[0] = '.';
12615   mnemonicendp[1] = 's';
12616   mnemonicendp += 2;
12617 }
12618
12619 static void
12620 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
12621                int sizeflag ATTRIBUTE_UNUSED)
12622 {
12623   /* Skip mod/rm byte.  */
12624   MODRM_CHECK;
12625   codep++;
12626 }
12627
12628 static void
12629 dofloat (int sizeflag)
12630 {
12631   const struct dis386 *dp;
12632   unsigned char floatop;
12633
12634   floatop = codep[-1];
12635
12636   if (modrm.mod != 3)
12637     {
12638       int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
12639
12640       putop (float_mem[fp_indx], sizeflag);
12641       obufp = op_out[0];
12642       op_ad = 2;
12643       OP_E (float_mem_mode[fp_indx], sizeflag);
12644       return;
12645     }
12646   /* Skip mod/rm byte.  */
12647   MODRM_CHECK;
12648   codep++;
12649
12650   dp = &float_reg[floatop - 0xd8][modrm.reg];
12651   if (dp->name == NULL)
12652     {
12653       putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
12654
12655       /* Instruction fnstsw is only one with strange arg.  */
12656       if (floatop == 0xdf && codep[-1] == 0xe0)
12657         strcpy (op_out[0], names16[0]);
12658     }
12659   else
12660     {
12661       putop (dp->name, sizeflag);
12662
12663       obufp = op_out[0];
12664       op_ad = 2;
12665       if (dp->op[0].rtn)
12666         (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
12667
12668       obufp = op_out[1];
12669       op_ad = 1;
12670       if (dp->op[1].rtn)
12671         (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
12672     }
12673 }
12674
12675 /* Like oappend (below), but S is a string starting with '%'.
12676    In Intel syntax, the '%' is elided.  */
12677 static void
12678 oappend_maybe_intel (const char *s)
12679 {
12680   oappend (s + intel_syntax);
12681 }
12682
12683 static void
12684 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12685 {
12686   oappend_maybe_intel ("%st");
12687 }
12688
12689 static void
12690 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12691 {
12692   sprintf (scratchbuf, "%%st(%d)", modrm.rm);
12693   oappend_maybe_intel (scratchbuf);
12694 }
12695
12696 /* Capital letters in template are macros.  */
12697 static int
12698 putop (const char *in_template, int sizeflag)
12699 {
12700   const char *p;
12701   int alt = 0;
12702   int cond = 1;
12703   unsigned int l = 0, len = 1;
12704   char last[4];
12705
12706 #define SAVE_LAST(c)                    \
12707   if (l < len && l < sizeof (last))     \
12708     last[l++] = c;                      \
12709   else                                  \
12710     abort ();
12711
12712   for (p = in_template; *p; p++)
12713     {
12714       switch (*p)
12715         {
12716         default:
12717           *obufp++ = *p;
12718           break;
12719         case '%':
12720           len++;
12721           break;
12722         case '!':
12723           cond = 0;
12724           break;
12725         case '{':
12726           if (intel_syntax)
12727             {
12728               while (*++p != '|')
12729                 if (*p == '}' || *p == '\0')
12730                   abort ();
12731               alt = 1;
12732             }
12733           break;
12734         case '|':
12735           while (*++p != '}')
12736             {
12737               if (*p == '\0')
12738                 abort ();
12739             }
12740           break;
12741         case '}':
12742           alt = 0;
12743           break;
12744         case 'A':
12745           if (intel_syntax)
12746             break;
12747           if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
12748             *obufp++ = 'b';
12749           break;
12750         case 'B':
12751           if (l == 0 && len == 1)
12752             {
12753             case_B:
12754               if (intel_syntax)
12755                 break;
12756               if (sizeflag & SUFFIX_ALWAYS)
12757                 *obufp++ = 'b';
12758             }
12759           else
12760             {
12761               if (l != 1
12762                   || len != 2
12763                   || last[0] != 'L')
12764                 {
12765                   SAVE_LAST (*p);
12766                   break;
12767                 }
12768
12769               if (address_mode == mode_64bit
12770                   && !(prefixes & PREFIX_ADDR))
12771                 {
12772                   *obufp++ = 'a';
12773                   *obufp++ = 'b';
12774                   *obufp++ = 's';
12775                 }
12776
12777               goto case_B;
12778             }
12779           break;
12780         case 'C':
12781           if (intel_syntax && !alt)
12782             break;
12783           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
12784             {
12785               if (sizeflag & DFLAG)
12786                 *obufp++ = intel_syntax ? 'd' : 'l';
12787               else
12788                 *obufp++ = intel_syntax ? 'w' : 's';
12789               used_prefixes |= (prefixes & PREFIX_DATA);
12790             }
12791           break;
12792         case 'D':
12793           if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
12794             break;
12795           USED_REX (REX_W);
12796           if (modrm.mod == 3)
12797             {
12798               if (rex & REX_W)
12799                 *obufp++ = 'q';
12800               else
12801                 {
12802                   if (sizeflag & DFLAG)
12803                     *obufp++ = intel_syntax ? 'd' : 'l';
12804                   else
12805                     *obufp++ = 'w';
12806                   used_prefixes |= (prefixes & PREFIX_DATA);
12807                 }
12808             }
12809           else
12810             *obufp++ = 'w';
12811           break;
12812         case 'E':               /* For jcxz/jecxz */
12813           if (address_mode == mode_64bit)
12814             {
12815               if (sizeflag & AFLAG)
12816                 *obufp++ = 'r';
12817               else
12818                 *obufp++ = 'e';
12819             }
12820           else
12821             if (sizeflag & AFLAG)
12822               *obufp++ = 'e';
12823           used_prefixes |= (prefixes & PREFIX_ADDR);
12824           break;
12825         case 'F':
12826           if (intel_syntax)
12827             break;
12828           if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
12829             {
12830               if (sizeflag & AFLAG)
12831                 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
12832               else
12833                 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
12834               used_prefixes |= (prefixes & PREFIX_ADDR);
12835             }
12836           break;
12837         case 'G':
12838           if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
12839             break;
12840           if ((rex & REX_W) || (sizeflag & DFLAG))
12841             *obufp++ = 'l';
12842           else
12843             *obufp++ = 'w';
12844           if (!(rex & REX_W))
12845             used_prefixes |= (prefixes & PREFIX_DATA);
12846           break;
12847         case 'H':
12848           if (intel_syntax)
12849             break;
12850           if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
12851               || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
12852             {
12853               used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
12854               *obufp++ = ',';
12855               *obufp++ = 'p';
12856               if (prefixes & PREFIX_DS)
12857                 *obufp++ = 't';
12858               else
12859                 *obufp++ = 'n';
12860             }
12861           break;
12862         case 'K':
12863           USED_REX (REX_W);
12864           if (rex & REX_W)
12865             *obufp++ = 'q';
12866           else
12867             *obufp++ = 'd';
12868           break;
12869         case 'Z':
12870           if (l != 0 || len != 1)
12871             {
12872               if (l != 1 || len != 2 || last[0] != 'X')
12873                 {
12874                   SAVE_LAST (*p);
12875                   break;
12876                 }
12877               if (!need_vex || !vex.evex)
12878                 abort ();
12879               if (intel_syntax
12880                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
12881                 break;
12882               switch (vex.length)
12883                 {
12884                 case 128:
12885                   *obufp++ = 'x';
12886                   break;
12887                 case 256:
12888                   *obufp++ = 'y';
12889                   break;
12890                 case 512:
12891                   *obufp++ = 'z';
12892                   break;
12893                 default:
12894                   abort ();
12895                 }
12896               break;
12897             }
12898           if (intel_syntax)
12899             break;
12900           if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
12901             {
12902               *obufp++ = 'q';
12903               break;
12904             }
12905           /* Fall through.  */
12906           goto case_L;
12907         case 'L':
12908           if (l != 0 || len != 1)
12909             {
12910               SAVE_LAST (*p);
12911               break;
12912             }
12913         case_L:
12914           if (intel_syntax)
12915             break;
12916           if (sizeflag & SUFFIX_ALWAYS)
12917             *obufp++ = 'l';
12918           break;
12919         case 'M':
12920           if (intel_mnemonic != cond)
12921             *obufp++ = 'r';
12922           break;
12923         case 'N':
12924           if ((prefixes & PREFIX_FWAIT) == 0)
12925             *obufp++ = 'n';
12926           else
12927             used_prefixes |= PREFIX_FWAIT;
12928           break;
12929         case 'O':
12930           USED_REX (REX_W);
12931           if (rex & REX_W)
12932             *obufp++ = 'o';
12933           else if (intel_syntax && (sizeflag & DFLAG))
12934             *obufp++ = 'q';
12935           else
12936             *obufp++ = 'd';
12937           if (!(rex & REX_W))
12938             used_prefixes |= (prefixes & PREFIX_DATA);
12939           break;
12940         case '&':
12941           if (!intel_syntax
12942               && address_mode == mode_64bit
12943               && isa64 == intel64)
12944             {
12945               *obufp++ = 'q';
12946               break;
12947             }
12948           /* Fall through.  */
12949         case 'T':
12950           if (!intel_syntax
12951               && address_mode == mode_64bit
12952               && ((sizeflag & DFLAG) || (rex & REX_W)))
12953             {
12954               *obufp++ = 'q';
12955               break;
12956             }
12957           /* Fall through.  */
12958           goto case_P;
12959         case 'P':
12960           if (l == 0 && len == 1)
12961             {
12962             case_P:
12963               if (intel_syntax)
12964                 {
12965                   if ((rex & REX_W) == 0
12966                       && (prefixes & PREFIX_DATA))
12967                     {
12968                       if ((sizeflag & DFLAG) == 0)
12969                         *obufp++ = 'w';
12970                       used_prefixes |= (prefixes & PREFIX_DATA);
12971                     }
12972                   break;
12973                 }
12974               if ((prefixes & PREFIX_DATA)
12975                   || (rex & REX_W)
12976                   || (sizeflag & SUFFIX_ALWAYS))
12977                 {
12978                   USED_REX (REX_W);
12979                   if (rex & REX_W)
12980                     *obufp++ = 'q';
12981                   else
12982                     {
12983                       if (sizeflag & DFLAG)
12984                         *obufp++ = 'l';
12985                       else
12986                         *obufp++ = 'w';
12987                       used_prefixes |= (prefixes & PREFIX_DATA);
12988                     }
12989                 }
12990             }
12991           else
12992             {
12993               if (l != 1 || len != 2 || last[0] != 'L')
12994                 {
12995                   SAVE_LAST (*p);
12996                   break;
12997                 }
12998
12999               if ((prefixes & PREFIX_DATA)
13000                   || (rex & REX_W)
13001                   || (sizeflag & SUFFIX_ALWAYS))
13002                 {
13003                   USED_REX (REX_W);
13004                   if (rex & REX_W)
13005                     *obufp++ = 'q';
13006                   else
13007                     {
13008                       if (sizeflag & DFLAG)
13009                         *obufp++ = intel_syntax ? 'd' : 'l';
13010                       else
13011                         *obufp++ = 'w';
13012                       used_prefixes |= (prefixes & PREFIX_DATA);
13013                     }
13014                 }
13015             }
13016           break;
13017         case 'U':
13018           if (intel_syntax)
13019             break;
13020           if (address_mode == mode_64bit
13021               && ((sizeflag & DFLAG) || (rex & REX_W)))
13022             {
13023               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13024                 *obufp++ = 'q';
13025               break;
13026             }
13027           /* Fall through.  */
13028           goto case_Q;
13029         case 'Q':
13030           if (l == 0 && len == 1)
13031             {
13032             case_Q:
13033               if (intel_syntax && !alt)
13034                 break;
13035               USED_REX (REX_W);
13036               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13037                 {
13038                   if (rex & REX_W)
13039                     *obufp++ = 'q';
13040                   else
13041                     {
13042                       if (sizeflag & DFLAG)
13043                         *obufp++ = intel_syntax ? 'd' : 'l';
13044                       else
13045                         *obufp++ = 'w';
13046                       used_prefixes |= (prefixes & PREFIX_DATA);
13047                     }
13048                 }
13049             }
13050           else
13051             {
13052               if (l != 1 || len != 2 || last[0] != 'L')
13053                 {
13054                   SAVE_LAST (*p);
13055                   break;
13056                 }
13057               if ((intel_syntax && need_modrm)
13058                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
13059                 break;
13060               if ((rex & REX_W))
13061                 {
13062                   USED_REX (REX_W);
13063                   *obufp++ = 'q';
13064                 }
13065               else if((address_mode == mode_64bit && need_modrm)
13066                       || (sizeflag & SUFFIX_ALWAYS))
13067                 *obufp++ = intel_syntax? 'd' : 'l';
13068             }
13069           break;
13070         case 'R':
13071           USED_REX (REX_W);
13072           if (rex & REX_W)
13073             *obufp++ = 'q';
13074           else if (sizeflag & DFLAG)
13075             {
13076               if (intel_syntax)
13077                   *obufp++ = 'd';
13078               else
13079                   *obufp++ = 'l';
13080             }
13081           else
13082             *obufp++ = 'w';
13083           if (intel_syntax && !p[1]
13084               && ((rex & REX_W) || (sizeflag & DFLAG)))
13085             *obufp++ = 'e';
13086           if (!(rex & REX_W))
13087             used_prefixes |= (prefixes & PREFIX_DATA);
13088           break;
13089         case 'V':
13090           if (l == 0 && len == 1)
13091             {
13092               if (intel_syntax)
13093                 break;
13094               if (address_mode == mode_64bit
13095                   && ((sizeflag & DFLAG) || (rex & REX_W)))
13096                 {
13097                   if (sizeflag & SUFFIX_ALWAYS)
13098                     *obufp++ = 'q';
13099                   break;
13100                 }
13101             }
13102           else
13103             {
13104               if (l != 1
13105                   || len != 2
13106                   || last[0] != 'L')
13107                 {
13108                   SAVE_LAST (*p);
13109                   break;
13110                 }
13111
13112               if (rex & REX_W)
13113                 {
13114                   *obufp++ = 'a';
13115                   *obufp++ = 'b';
13116                   *obufp++ = 's';
13117                 }
13118             }
13119           /* Fall through.  */
13120           goto case_S;
13121         case 'S':
13122           if (l == 0 && len == 1)
13123             {
13124             case_S:
13125               if (intel_syntax)
13126                 break;
13127               if (sizeflag & SUFFIX_ALWAYS)
13128                 {
13129                   if (rex & REX_W)
13130                     *obufp++ = 'q';
13131                   else
13132                     {
13133                       if (sizeflag & DFLAG)
13134                         *obufp++ = 'l';
13135                       else
13136                         *obufp++ = 'w';
13137                       used_prefixes |= (prefixes & PREFIX_DATA);
13138                     }
13139                 }
13140             }
13141           else
13142             {
13143               if (l != 1
13144                   || len != 2
13145                   || last[0] != 'L')
13146                 {
13147                   SAVE_LAST (*p);
13148                   break;
13149                 }
13150
13151               if (address_mode == mode_64bit
13152                   && !(prefixes & PREFIX_ADDR))
13153                 {
13154                   *obufp++ = 'a';
13155                   *obufp++ = 'b';
13156                   *obufp++ = 's';
13157                 }
13158
13159               goto case_S;
13160             }
13161           break;
13162         case 'X':
13163           if (l != 0 || len != 1)
13164             {
13165               SAVE_LAST (*p);
13166               break;
13167             }
13168           if (need_vex
13169               ? vex.prefix == DATA_PREFIX_OPCODE
13170               : prefixes & PREFIX_DATA)
13171             {
13172               *obufp++ = 'd';
13173               used_prefixes |= PREFIX_DATA;
13174             }
13175           else
13176             *obufp++ = 's';
13177           break;
13178         case 'Y':
13179           if (l == 0 && len == 1)
13180             abort ();
13181           else
13182             {
13183               if (l != 1 || len != 2 || last[0] != 'X')
13184                 {
13185                   SAVE_LAST (*p);
13186                   break;
13187                 }
13188               if (!need_vex)
13189                 abort ();
13190               if (intel_syntax
13191                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
13192                 break;
13193               switch (vex.length)
13194                 {
13195                 case 128:
13196                   *obufp++ = 'x';
13197                   break;
13198                 case 256:
13199                   *obufp++ = 'y';
13200                   break;
13201                 case 512:
13202                   if (!vex.evex)
13203                 default:
13204                     abort ();
13205                 }
13206             }
13207           break;
13208         case 'W':
13209           if (l == 0 && len == 1)
13210             {
13211               /* operand size flag for cwtl, cbtw */
13212               USED_REX (REX_W);
13213               if (rex & REX_W)
13214                 {
13215                   if (intel_syntax)
13216                     *obufp++ = 'd';
13217                   else
13218                     *obufp++ = 'l';
13219                 }
13220               else if (sizeflag & DFLAG)
13221                 *obufp++ = 'w';
13222               else
13223                 *obufp++ = 'b';
13224               if (!(rex & REX_W))
13225                 used_prefixes |= (prefixes & PREFIX_DATA);
13226             }
13227           else
13228             {
13229               if (l != 1
13230                   || len != 2
13231                   || (last[0] != 'X'
13232                       && last[0] != 'L'))
13233                 {
13234                   SAVE_LAST (*p);
13235                   break;
13236                 }
13237               if (!need_vex)
13238                 abort ();
13239               if (last[0] == 'X')
13240                 *obufp++ = vex.w ? 'd': 's';
13241               else
13242                 *obufp++ = vex.w ? 'q': 'd';
13243             }
13244           break;
13245         case '^':
13246           if (intel_syntax)
13247             break;
13248           if (isa64 == intel64 && (rex & REX_W))
13249             {
13250               USED_REX (REX_W);
13251               *obufp++ = 'q';
13252               break;
13253             }
13254           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
13255             {
13256               if (sizeflag & DFLAG)
13257                 *obufp++ = 'l';
13258               else
13259                 *obufp++ = 'w';
13260               used_prefixes |= (prefixes & PREFIX_DATA);
13261             }
13262           break;
13263         case '@':
13264           if (intel_syntax)
13265             break;
13266           if (address_mode == mode_64bit
13267               && (isa64 == intel64
13268                   || ((sizeflag & DFLAG) || (rex & REX_W))))
13269               *obufp++ = 'q';
13270           else if ((prefixes & PREFIX_DATA))
13271             {
13272               if (!(sizeflag & DFLAG))
13273                 *obufp++ = 'w';
13274               used_prefixes |= (prefixes & PREFIX_DATA);
13275             }
13276           break;
13277         }
13278     }
13279   *obufp = 0;
13280   mnemonicendp = obufp;
13281   return 0;
13282 }
13283
13284 static void
13285 oappend (const char *s)
13286 {
13287   obufp = stpcpy (obufp, s);
13288 }
13289
13290 static void
13291 append_seg (void)
13292 {
13293   /* Only print the active segment register.  */
13294   if (!active_seg_prefix)
13295     return;
13296
13297   used_prefixes |= active_seg_prefix;
13298   switch (active_seg_prefix)
13299     {
13300     case PREFIX_CS:
13301       oappend_maybe_intel ("%cs:");
13302       break;
13303     case PREFIX_DS:
13304       oappend_maybe_intel ("%ds:");
13305       break;
13306     case PREFIX_SS:
13307       oappend_maybe_intel ("%ss:");
13308       break;
13309     case PREFIX_ES:
13310       oappend_maybe_intel ("%es:");
13311       break;
13312     case PREFIX_FS:
13313       oappend_maybe_intel ("%fs:");
13314       break;
13315     case PREFIX_GS:
13316       oappend_maybe_intel ("%gs:");
13317       break;
13318     default:
13319       break;
13320     }
13321 }
13322
13323 static void
13324 OP_indirE (int bytemode, int sizeflag)
13325 {
13326   if (!intel_syntax)
13327     oappend ("*");
13328   OP_E (bytemode, sizeflag);
13329 }
13330
13331 static void
13332 print_operand_value (char *buf, int hex, bfd_vma disp)
13333 {
13334   if (address_mode == mode_64bit)
13335     {
13336       if (hex)
13337         {
13338           char tmp[30];
13339           int i;
13340           buf[0] = '0';
13341           buf[1] = 'x';
13342           sprintf_vma (tmp, disp);
13343           for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
13344           strcpy (buf + 2, tmp + i);
13345         }
13346       else
13347         {
13348           bfd_signed_vma v = disp;
13349           char tmp[30];
13350           int i;
13351           if (v < 0)
13352             {
13353               *(buf++) = '-';
13354               v = -disp;
13355               /* Check for possible overflow on 0x8000000000000000.  */
13356               if (v < 0)
13357                 {
13358                   strcpy (buf, "9223372036854775808");
13359                   return;
13360                 }
13361             }
13362           if (!v)
13363             {
13364               strcpy (buf, "0");
13365               return;
13366             }
13367
13368           i = 0;
13369           tmp[29] = 0;
13370           while (v)
13371             {
13372               tmp[28 - i] = (v % 10) + '0';
13373               v /= 10;
13374               i++;
13375             }
13376           strcpy (buf, tmp + 29 - i);
13377         }
13378     }
13379   else
13380     {
13381       if (hex)
13382         sprintf (buf, "0x%x", (unsigned int) disp);
13383       else
13384         sprintf (buf, "%d", (int) disp);
13385     }
13386 }
13387
13388 /* Put DISP in BUF as signed hex number.  */
13389
13390 static void
13391 print_displacement (char *buf, bfd_vma disp)
13392 {
13393   bfd_signed_vma val = disp;
13394   char tmp[30];
13395   int i, j = 0;
13396
13397   if (val < 0)
13398     {
13399       buf[j++] = '-';
13400       val = -disp;
13401
13402       /* Check for possible overflow.  */
13403       if (val < 0)
13404         {
13405           switch (address_mode)
13406             {
13407             case mode_64bit:
13408               strcpy (buf + j, "0x8000000000000000");
13409               break;
13410             case mode_32bit:
13411               strcpy (buf + j, "0x80000000");
13412               break;
13413             case mode_16bit:
13414               strcpy (buf + j, "0x8000");
13415               break;
13416             }
13417           return;
13418         }
13419     }
13420
13421   buf[j++] = '0';
13422   buf[j++] = 'x';
13423
13424   sprintf_vma (tmp, (bfd_vma) val);
13425   for (i = 0; tmp[i] == '0'; i++)
13426     continue;
13427   if (tmp[i] == '\0')
13428     i--;
13429   strcpy (buf + j, tmp + i);
13430 }
13431
13432 static void
13433 intel_operand_size (int bytemode, int sizeflag)
13434 {
13435   if (vex.evex
13436       && vex.b
13437       && (bytemode == x_mode
13438           || bytemode == evex_half_bcst_xmmq_mode))
13439     {
13440       if (vex.w)
13441         oappend ("QWORD PTR ");
13442       else
13443         oappend ("DWORD PTR ");
13444       return;
13445     }
13446   switch (bytemode)
13447     {
13448     case b_mode:
13449     case b_swap_mode:
13450     case dqb_mode:
13451     case db_mode:
13452       oappend ("BYTE PTR ");
13453       break;
13454     case w_mode:
13455     case dw_mode:
13456     case dqw_mode:
13457       oappend ("WORD PTR ");
13458       break;
13459     case indir_v_mode:
13460       if (address_mode == mode_64bit && isa64 == intel64)
13461         {
13462           oappend ("QWORD PTR ");
13463           break;
13464         }
13465       /* Fall through.  */
13466     case stack_v_mode:
13467       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
13468         {
13469           oappend ("QWORD PTR ");
13470           break;
13471         }
13472       /* Fall through.  */
13473     case v_mode:
13474     case v_swap_mode:
13475     case dq_mode:
13476       USED_REX (REX_W);
13477       if (rex & REX_W)
13478         oappend ("QWORD PTR ");
13479       else
13480         {
13481           if ((sizeflag & DFLAG) || bytemode == dq_mode)
13482             oappend ("DWORD PTR ");
13483           else
13484             oappend ("WORD PTR ");
13485           used_prefixes |= (prefixes & PREFIX_DATA);
13486         }
13487       break;
13488     case z_mode:
13489       if ((rex & REX_W) || (sizeflag & DFLAG))
13490         *obufp++ = 'D';
13491       oappend ("WORD PTR ");
13492       if (!(rex & REX_W))
13493         used_prefixes |= (prefixes & PREFIX_DATA);
13494       break;
13495     case a_mode:
13496       if (sizeflag & DFLAG)
13497         oappend ("QWORD PTR ");
13498       else
13499         oappend ("DWORD PTR ");
13500       used_prefixes |= (prefixes & PREFIX_DATA);
13501       break;
13502     case movsxd_mode:
13503       if (!(sizeflag & DFLAG) && isa64 == intel64)
13504         oappend ("WORD PTR ");
13505       else
13506         oappend ("DWORD PTR ");
13507       used_prefixes |= (prefixes & PREFIX_DATA);
13508       break;
13509     case d_mode:
13510     case d_scalar_swap_mode:
13511     case d_swap_mode:
13512     case dqd_mode:
13513       oappend ("DWORD PTR ");
13514       break;
13515     case q_mode:
13516     case q_scalar_swap_mode:
13517     case q_swap_mode:
13518       oappend ("QWORD PTR ");
13519       break;
13520     case m_mode:
13521       if (address_mode == mode_64bit)
13522         oappend ("QWORD PTR ");
13523       else
13524         oappend ("DWORD PTR ");
13525       break;
13526     case f_mode:
13527       if (sizeflag & DFLAG)
13528         oappend ("FWORD PTR ");
13529       else
13530         oappend ("DWORD PTR ");
13531       used_prefixes |= (prefixes & PREFIX_DATA);
13532       break;
13533     case t_mode:
13534       oappend ("TBYTE PTR ");
13535       break;
13536     case x_mode:
13537     case x_swap_mode:
13538     case evex_x_gscat_mode:
13539     case evex_x_nobcst_mode:
13540     case b_scalar_mode:
13541     case w_scalar_mode:
13542       if (need_vex)
13543         {
13544           switch (vex.length)
13545             {
13546             case 128:
13547               oappend ("XMMWORD PTR ");
13548               break;
13549             case 256:
13550               oappend ("YMMWORD PTR ");
13551               break;
13552             case 512:
13553               oappend ("ZMMWORD PTR ");
13554               break;
13555             default:
13556               abort ();
13557             }
13558         }
13559       else
13560         oappend ("XMMWORD PTR ");
13561       break;
13562     case xmm_mode:
13563       oappend ("XMMWORD PTR ");
13564       break;
13565     case ymm_mode:
13566       oappend ("YMMWORD PTR ");
13567       break;
13568     case xmmq_mode:
13569     case evex_half_bcst_xmmq_mode:
13570       if (!need_vex)
13571         abort ();
13572
13573       switch (vex.length)
13574         {
13575         case 128:
13576           oappend ("QWORD PTR ");
13577           break;
13578         case 256:
13579           oappend ("XMMWORD PTR ");
13580           break;
13581         case 512:
13582           oappend ("YMMWORD PTR ");
13583           break;
13584         default:
13585           abort ();
13586         }
13587       break;
13588     case xmm_mb_mode:
13589       if (!need_vex)
13590         abort ();
13591
13592       switch (vex.length)
13593         {
13594         case 128:
13595         case 256:
13596         case 512:
13597           oappend ("BYTE PTR ");
13598           break;
13599         default:
13600           abort ();
13601         }
13602       break;
13603     case xmm_mw_mode:
13604       if (!need_vex)
13605         abort ();
13606
13607       switch (vex.length)
13608         {
13609         case 128:
13610         case 256:
13611         case 512:
13612           oappend ("WORD PTR ");
13613           break;
13614         default:
13615           abort ();
13616         }
13617       break;
13618     case xmm_md_mode:
13619       if (!need_vex)
13620         abort ();
13621
13622       switch (vex.length)
13623         {
13624         case 128:
13625         case 256:
13626         case 512:
13627           oappend ("DWORD PTR ");
13628           break;
13629         default:
13630           abort ();
13631         }
13632       break;
13633     case xmm_mq_mode:
13634       if (!need_vex)
13635         abort ();
13636
13637       switch (vex.length)
13638         {
13639         case 128:
13640         case 256:
13641         case 512:
13642           oappend ("QWORD PTR ");
13643           break;
13644         default:
13645           abort ();
13646         }
13647       break;
13648     case xmmdw_mode:
13649       if (!need_vex)
13650         abort ();
13651
13652       switch (vex.length)
13653         {
13654         case 128:
13655           oappend ("WORD PTR ");
13656           break;
13657         case 256:
13658           oappend ("DWORD PTR ");
13659           break;
13660         case 512:
13661           oappend ("QWORD PTR ");
13662           break;
13663         default:
13664           abort ();
13665         }
13666       break;
13667     case xmmqd_mode:
13668       if (!need_vex)
13669         abort ();
13670
13671       switch (vex.length)
13672         {
13673         case 128:
13674           oappend ("DWORD PTR ");
13675           break;
13676         case 256:
13677           oappend ("QWORD PTR ");
13678           break;
13679         case 512:
13680           oappend ("XMMWORD PTR ");
13681           break;
13682         default:
13683           abort ();
13684         }
13685       break;
13686     case ymmq_mode:
13687       if (!need_vex)
13688         abort ();
13689
13690       switch (vex.length)
13691         {
13692         case 128:
13693           oappend ("QWORD PTR ");
13694           break;
13695         case 256:
13696           oappend ("YMMWORD PTR ");
13697           break;
13698         case 512:
13699           oappend ("ZMMWORD PTR ");
13700           break;
13701         default:
13702           abort ();
13703         }
13704       break;
13705     case ymmxmm_mode:
13706       if (!need_vex)
13707         abort ();
13708
13709       switch (vex.length)
13710         {
13711         case 128:
13712         case 256:
13713           oappend ("XMMWORD PTR ");
13714           break;
13715         default:
13716           abort ();
13717         }
13718       break;
13719     case o_mode:
13720       oappend ("OWORD PTR ");
13721       break;
13722     case vex_scalar_w_dq_mode:
13723       if (!need_vex)
13724         abort ();
13725
13726       if (vex.w)
13727         oappend ("QWORD PTR ");
13728       else
13729         oappend ("DWORD PTR ");
13730       break;
13731     case vex_vsib_d_w_dq_mode:
13732     case vex_vsib_q_w_dq_mode:
13733       if (!need_vex)
13734         abort ();
13735
13736       if (!vex.evex)
13737         {
13738           if (vex.w)
13739             oappend ("QWORD PTR ");
13740           else
13741             oappend ("DWORD PTR ");
13742         }
13743       else
13744         {
13745           switch (vex.length)
13746             {
13747             case 128:
13748               oappend ("XMMWORD PTR ");
13749               break;
13750             case 256:
13751               oappend ("YMMWORD PTR ");
13752               break;
13753             case 512:
13754               oappend ("ZMMWORD PTR ");
13755               break;
13756             default:
13757               abort ();
13758             }
13759         }
13760       break;
13761     case vex_vsib_q_w_d_mode:
13762     case vex_vsib_d_w_d_mode:
13763       if (!need_vex || !vex.evex)
13764         abort ();
13765
13766       switch (vex.length)
13767         {
13768         case 128:
13769           oappend ("QWORD PTR ");
13770           break;
13771         case 256:
13772           oappend ("XMMWORD PTR ");
13773           break;
13774         case 512:
13775           oappend ("YMMWORD PTR ");
13776           break;
13777         default:
13778           abort ();
13779         }
13780
13781       break;
13782     case mask_bd_mode:
13783       if (!need_vex || vex.length != 128)
13784         abort ();
13785       if (vex.w)
13786         oappend ("DWORD PTR ");
13787       else
13788         oappend ("BYTE PTR ");
13789       break;
13790     case mask_mode:
13791       if (!need_vex)
13792         abort ();
13793       if (vex.w)
13794         oappend ("QWORD PTR ");
13795       else
13796         oappend ("WORD PTR ");
13797       break;
13798     case v_bnd_mode:
13799     case v_bndmk_mode:
13800     default:
13801       break;
13802     }
13803 }
13804
13805 static void
13806 OP_E_register (int bytemode, int sizeflag)
13807 {
13808   int reg = modrm.rm;
13809   const char **names;
13810
13811   USED_REX (REX_B);
13812   if ((rex & REX_B))
13813     reg += 8;
13814
13815   if ((sizeflag & SUFFIX_ALWAYS)
13816       && (bytemode == b_swap_mode
13817           || bytemode == bnd_swap_mode
13818           || bytemode == v_swap_mode))
13819     swap_operand ();
13820
13821   switch (bytemode)
13822     {
13823     case b_mode:
13824     case b_swap_mode:
13825       USED_REX (0);
13826       if (rex)
13827         names = names8rex;
13828       else
13829         names = names8;
13830       break;
13831     case w_mode:
13832       names = names16;
13833       break;
13834     case d_mode:
13835     case dw_mode:
13836     case db_mode:
13837       names = names32;
13838       break;
13839     case q_mode:
13840       names = names64;
13841       break;
13842     case m_mode:
13843     case v_bnd_mode:
13844       names = address_mode == mode_64bit ? names64 : names32;
13845       break;
13846     case bnd_mode:
13847     case bnd_swap_mode:
13848       if (reg > 0x3)
13849         {
13850           oappend ("(bad)");
13851           return;
13852         }
13853       names = names_bnd;
13854       break;
13855     case indir_v_mode:
13856       if (address_mode == mode_64bit && isa64 == intel64)
13857         {
13858           names = names64;
13859           break;
13860         }
13861       /* Fall through.  */
13862     case stack_v_mode:
13863       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
13864         {
13865           names = names64;
13866           break;
13867         }
13868       bytemode = v_mode;
13869       /* Fall through.  */
13870     case v_mode:
13871     case v_swap_mode:
13872     case dq_mode:
13873     case dqb_mode:
13874     case dqd_mode:
13875     case dqw_mode:
13876       USED_REX (REX_W);
13877       if (rex & REX_W)
13878         names = names64;
13879       else
13880         {
13881           if ((sizeflag & DFLAG)
13882               || (bytemode != v_mode
13883                   && bytemode != v_swap_mode))
13884             names = names32;
13885           else
13886             names = names16;
13887           used_prefixes |= (prefixes & PREFIX_DATA);
13888         }
13889       break;
13890     case movsxd_mode:
13891       if (!(sizeflag & DFLAG) && isa64 == intel64)
13892         names = names16;
13893       else
13894         names = names32;
13895       used_prefixes |= (prefixes & PREFIX_DATA);
13896       break;
13897     case va_mode:
13898       names = (address_mode == mode_64bit
13899                ? names64 : names32);
13900       if (!(prefixes & PREFIX_ADDR))
13901         names = (address_mode == mode_16bit
13902                      ? names16 : names);
13903       else
13904         {
13905           /* Remove "addr16/addr32".  */
13906           all_prefixes[last_addr_prefix] = 0;
13907           names = (address_mode != mode_32bit
13908                        ? names32 : names16);
13909           used_prefixes |= PREFIX_ADDR;
13910         }
13911       break;
13912     case mask_bd_mode:
13913     case mask_mode:
13914       if (reg > 0x7)
13915         {
13916           oappend ("(bad)");
13917           return;
13918         }
13919       names = names_mask;
13920       break;
13921     case 0:
13922       return;
13923     default:
13924       oappend (INTERNAL_DISASSEMBLER_ERROR);
13925       return;
13926     }
13927   oappend (names[reg]);
13928 }
13929
13930 static void
13931 OP_E_memory (int bytemode, int sizeflag)
13932 {
13933   bfd_vma disp = 0;
13934   int add = (rex & REX_B) ? 8 : 0;
13935   int riprel = 0;
13936   int shift;
13937
13938   if (vex.evex)
13939     {
13940       /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0.  */
13941       if (vex.b
13942           && bytemode != x_mode
13943           && bytemode != xmmq_mode
13944           && bytemode != evex_half_bcst_xmmq_mode)
13945         {
13946           BadOp ();
13947           return;
13948         }
13949       switch (bytemode)
13950         {
13951         case dqw_mode:
13952         case dw_mode:
13953           shift = 1;
13954           break;
13955         case dqb_mode:
13956         case db_mode:
13957           shift = 0;
13958           break;
13959         case dq_mode:
13960           if (address_mode != mode_64bit)
13961             {
13962               shift = 2;
13963               break;
13964             }
13965             /* fall through */
13966         case vex_scalar_w_dq_mode:
13967         case vex_vsib_d_w_dq_mode:
13968         case vex_vsib_d_w_d_mode:
13969         case vex_vsib_q_w_dq_mode:
13970         case vex_vsib_q_w_d_mode:
13971         case evex_x_gscat_mode:
13972           shift = vex.w ? 3 : 2;
13973           break;
13974         case x_mode:
13975         case evex_half_bcst_xmmq_mode:
13976         case xmmq_mode:
13977           if (vex.b)
13978             {
13979               shift = vex.w ? 3 : 2;
13980               break;
13981             }
13982           /* Fall through.  */
13983         case xmmqd_mode:
13984         case xmmdw_mode:
13985         case ymmq_mode:
13986         case evex_x_nobcst_mode:
13987         case x_swap_mode:
13988           switch (vex.length)
13989             {
13990             case 128:
13991               shift = 4;
13992               break;
13993             case 256:
13994               shift = 5;
13995               break;
13996             case 512:
13997               shift = 6;
13998               break;
13999             default:
14000               abort ();
14001             }
14002           break;
14003         case ymm_mode:
14004           shift = 5;
14005           break;
14006         case xmm_mode:
14007           shift = 4;
14008           break;
14009         case xmm_mq_mode:
14010         case q_mode:
14011         case q_swap_mode:
14012         case q_scalar_swap_mode:
14013           shift = 3;
14014           break;
14015         case dqd_mode:
14016         case xmm_md_mode:
14017         case d_mode:
14018         case d_swap_mode:
14019         case d_scalar_swap_mode:
14020           shift = 2;
14021           break;
14022         case w_scalar_mode:
14023         case xmm_mw_mode:
14024           shift = 1;
14025           break;
14026         case b_scalar_mode:
14027         case xmm_mb_mode:
14028           shift = 0;
14029           break;
14030         default:
14031           abort ();
14032         }
14033       /* Make necessary corrections to shift for modes that need it.
14034          For these modes we currently have shift 4, 5 or 6 depending on
14035          vex.length (it corresponds to xmmword, ymmword or zmmword
14036          operand).  We might want to make it 3, 4 or 5 (e.g. for
14037          xmmq_mode).  In case of broadcast enabled the corrections
14038          aren't needed, as element size is always 32 or 64 bits.  */
14039       if (!vex.b
14040           && (bytemode == xmmq_mode
14041               || bytemode == evex_half_bcst_xmmq_mode))
14042         shift -= 1;
14043       else if (bytemode == xmmqd_mode)
14044         shift -= 2;
14045       else if (bytemode == xmmdw_mode)
14046         shift -= 3;
14047       else if (bytemode == ymmq_mode && vex.length == 128)
14048         shift -= 1;
14049     }
14050   else
14051     shift = 0;
14052
14053   USED_REX (REX_B);
14054   if (intel_syntax)
14055     intel_operand_size (bytemode, sizeflag);
14056   append_seg ();
14057
14058   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
14059     {
14060       /* 32/64 bit address mode */
14061       int havedisp;
14062       int havesib;
14063       int havebase;
14064       int haveindex;
14065       int needindex;
14066       int needaddr32;
14067       int base, rbase;
14068       int vindex = 0;
14069       int scale = 0;
14070       int addr32flag = !((sizeflag & AFLAG)
14071                          || bytemode == v_bnd_mode
14072                          || bytemode == v_bndmk_mode
14073                          || bytemode == bnd_mode
14074                          || bytemode == bnd_swap_mode);
14075       const char **indexes64 = names64;
14076       const char **indexes32 = names32;
14077
14078       havesib = 0;
14079       havebase = 1;
14080       haveindex = 0;
14081       base = modrm.rm;
14082
14083       if (base == 4)
14084         {
14085           havesib = 1;
14086           vindex = sib.index;
14087           USED_REX (REX_X);
14088           if (rex & REX_X)
14089             vindex += 8;
14090           switch (bytemode)
14091             {
14092             case vex_vsib_d_w_dq_mode:
14093             case vex_vsib_d_w_d_mode:
14094             case vex_vsib_q_w_dq_mode:
14095             case vex_vsib_q_w_d_mode:
14096               if (!need_vex)
14097                 abort ();
14098               if (vex.evex)
14099                 {
14100                   if (!vex.v)
14101                     vindex += 16;
14102                 }
14103
14104               haveindex = 1;
14105               switch (vex.length)
14106                 {
14107                 case 128:
14108                   indexes64 = indexes32 = names_xmm;
14109                   break;
14110                 case 256:
14111                   if (!vex.w
14112                       || bytemode == vex_vsib_q_w_dq_mode
14113                       || bytemode == vex_vsib_q_w_d_mode)
14114                     indexes64 = indexes32 = names_ymm;
14115                   else
14116                     indexes64 = indexes32 = names_xmm;
14117                   break;
14118                 case 512:
14119                   if (!vex.w
14120                       || bytemode == vex_vsib_q_w_dq_mode
14121                       || bytemode == vex_vsib_q_w_d_mode)
14122                     indexes64 = indexes32 = names_zmm;
14123                   else
14124                     indexes64 = indexes32 = names_ymm;
14125                   break;
14126                 default:
14127                   abort ();
14128                 }
14129               break;
14130             default:
14131               haveindex = vindex != 4;
14132               break;
14133             }
14134           scale = sib.scale;
14135           base = sib.base;
14136           codep++;
14137         }
14138       rbase = base + add;
14139
14140       switch (modrm.mod)
14141         {
14142         case 0:
14143           if (base == 5)
14144             {
14145               havebase = 0;
14146               if (address_mode == mode_64bit && !havesib)
14147                 riprel = 1;
14148               disp = get32s ();
14149               if (riprel && bytemode == v_bndmk_mode)
14150                 {
14151                   oappend ("(bad)");
14152                   return;
14153                 }
14154             }
14155           break;
14156         case 1:
14157           FETCH_DATA (the_info, codep + 1);
14158           disp = *codep++;
14159           if ((disp & 0x80) != 0)
14160             disp -= 0x100;
14161           if (vex.evex && shift > 0)
14162             disp <<= shift;
14163           break;
14164         case 2:
14165           disp = get32s ();
14166           break;
14167         }
14168
14169       needindex = 0;
14170       needaddr32 = 0;
14171       if (havesib
14172           && !havebase
14173           && !haveindex
14174           && address_mode != mode_16bit)
14175         {
14176           if (address_mode == mode_64bit)
14177             {
14178               /* Display eiz instead of addr32.  */
14179               needindex = addr32flag;
14180               needaddr32 = 1;
14181             }
14182           else
14183             {
14184               /* In 32-bit mode, we need index register to tell [offset]
14185                  from [eiz*1 + offset].  */
14186               needindex = 1;
14187             }
14188         }
14189
14190       havedisp = (havebase
14191                   || needindex
14192                   || (havesib && (haveindex || scale != 0)));
14193
14194       if (!intel_syntax)
14195         if (modrm.mod != 0 || base == 5)
14196           {
14197             if (havedisp || riprel)
14198               print_displacement (scratchbuf, disp);
14199             else
14200               print_operand_value (scratchbuf, 1, disp);
14201             oappend (scratchbuf);
14202             if (riprel)
14203               {
14204                 set_op (disp, 1);
14205                 oappend (!addr32flag ? "(%rip)" : "(%eip)");
14206               }
14207           }
14208
14209       if ((havebase || haveindex || needindex || needaddr32 || riprel)
14210           && (address_mode != mode_64bit
14211               || ((bytemode != v_bnd_mode)
14212                   && (bytemode != v_bndmk_mode)
14213                   && (bytemode != bnd_mode)
14214                   && (bytemode != bnd_swap_mode))))
14215         used_prefixes |= PREFIX_ADDR;
14216
14217       if (havedisp || (intel_syntax && riprel))
14218         {
14219           *obufp++ = open_char;
14220           if (intel_syntax && riprel)
14221             {
14222               set_op (disp, 1);
14223               oappend (!addr32flag ? "rip" : "eip");
14224             }
14225           *obufp = '\0';
14226           if (havebase)
14227             oappend (address_mode == mode_64bit && !addr32flag
14228                      ? names64[rbase] : names32[rbase]);
14229           if (havesib)
14230             {
14231               /* ESP/RSP won't allow index.  If base isn't ESP/RSP,
14232                  print index to tell base + index from base.  */
14233               if (scale != 0
14234                   || needindex
14235                   || haveindex
14236                   || (havebase && base != ESP_REG_NUM))
14237                 {
14238                   if (!intel_syntax || havebase)
14239                     {
14240                       *obufp++ = separator_char;
14241                       *obufp = '\0';
14242                     }
14243                   if (haveindex)
14244                     oappend (address_mode == mode_64bit && !addr32flag
14245                              ? indexes64[vindex] : indexes32[vindex]);
14246                   else
14247                     oappend (address_mode == mode_64bit && !addr32flag
14248                              ? index64 : index32);
14249
14250                   *obufp++ = scale_char;
14251                   *obufp = '\0';
14252                   sprintf (scratchbuf, "%d", 1 << scale);
14253                   oappend (scratchbuf);
14254                 }
14255             }
14256           if (intel_syntax
14257               && (disp || modrm.mod != 0 || base == 5))
14258             {
14259               if (!havedisp || (bfd_signed_vma) disp >= 0)
14260                 {
14261                   *obufp++ = '+';
14262                   *obufp = '\0';
14263                 }
14264               else if (modrm.mod != 1 && disp != -disp)
14265                 {
14266                   *obufp++ = '-';
14267                   *obufp = '\0';
14268                   disp = - (bfd_signed_vma) disp;
14269                 }
14270
14271               if (havedisp)
14272                 print_displacement (scratchbuf, disp);
14273               else
14274                 print_operand_value (scratchbuf, 1, disp);
14275               oappend (scratchbuf);
14276             }
14277
14278           *obufp++ = close_char;
14279           *obufp = '\0';
14280         }
14281       else if (intel_syntax)
14282         {
14283           if (modrm.mod != 0 || base == 5)
14284             {
14285               if (!active_seg_prefix)
14286                 {
14287                   oappend (names_seg[ds_reg - es_reg]);
14288                   oappend (":");
14289                 }
14290               print_operand_value (scratchbuf, 1, disp);
14291               oappend (scratchbuf);
14292             }
14293         }
14294     }
14295   else if (bytemode == v_bnd_mode
14296            || bytemode == v_bndmk_mode
14297            || bytemode == bnd_mode
14298            || bytemode == bnd_swap_mode)
14299     {
14300       oappend ("(bad)");
14301       return;
14302     }
14303   else
14304     {
14305       /* 16 bit address mode */
14306       used_prefixes |= prefixes & PREFIX_ADDR;
14307       switch (modrm.mod)
14308         {
14309         case 0:
14310           if (modrm.rm == 6)
14311             {
14312               disp = get16 ();
14313               if ((disp & 0x8000) != 0)
14314                 disp -= 0x10000;
14315             }
14316           break;
14317         case 1:
14318           FETCH_DATA (the_info, codep + 1);
14319           disp = *codep++;
14320           if ((disp & 0x80) != 0)
14321             disp -= 0x100;
14322           if (vex.evex && shift > 0)
14323             disp <<= shift;
14324           break;
14325         case 2:
14326           disp = get16 ();
14327           if ((disp & 0x8000) != 0)
14328             disp -= 0x10000;
14329           break;
14330         }
14331
14332       if (!intel_syntax)
14333         if (modrm.mod != 0 || modrm.rm == 6)
14334           {
14335             print_displacement (scratchbuf, disp);
14336             oappend (scratchbuf);
14337           }
14338
14339       if (modrm.mod != 0 || modrm.rm != 6)
14340         {
14341           *obufp++ = open_char;
14342           *obufp = '\0';
14343           oappend (index16[modrm.rm]);
14344           if (intel_syntax
14345               && (disp || modrm.mod != 0 || modrm.rm == 6))
14346             {
14347               if ((bfd_signed_vma) disp >= 0)
14348                 {
14349                   *obufp++ = '+';
14350                   *obufp = '\0';
14351                 }
14352               else if (modrm.mod != 1)
14353                 {
14354                   *obufp++ = '-';
14355                   *obufp = '\0';
14356                   disp = - (bfd_signed_vma) disp;
14357                 }
14358
14359               print_displacement (scratchbuf, disp);
14360               oappend (scratchbuf);
14361             }
14362
14363           *obufp++ = close_char;
14364           *obufp = '\0';
14365         }
14366       else if (intel_syntax)
14367         {
14368           if (!active_seg_prefix)
14369             {
14370               oappend (names_seg[ds_reg - es_reg]);
14371               oappend (":");
14372             }
14373           print_operand_value (scratchbuf, 1, disp & 0xffff);
14374           oappend (scratchbuf);
14375         }
14376     }
14377   if (vex.evex && vex.b
14378       && (bytemode == x_mode
14379           || bytemode == xmmq_mode
14380           || bytemode == evex_half_bcst_xmmq_mode))
14381     {
14382       if (vex.w
14383           || bytemode == xmmq_mode
14384           || bytemode == evex_half_bcst_xmmq_mode)
14385         {
14386           switch (vex.length)
14387             {
14388             case 128:
14389               oappend ("{1to2}");
14390               break;
14391             case 256:
14392               oappend ("{1to4}");
14393               break;
14394             case 512:
14395               oappend ("{1to8}");
14396               break;
14397             default:
14398               abort ();
14399             }
14400         }
14401       else
14402         {
14403           switch (vex.length)
14404             {
14405             case 128:
14406               oappend ("{1to4}");
14407               break;
14408             case 256:
14409               oappend ("{1to8}");
14410               break;
14411             case 512:
14412               oappend ("{1to16}");
14413               break;
14414             default:
14415               abort ();
14416             }
14417         }
14418     }
14419 }
14420
14421 static void
14422 OP_E (int bytemode, int sizeflag)
14423 {
14424   /* Skip mod/rm byte.  */
14425   MODRM_CHECK;
14426   codep++;
14427
14428   if (modrm.mod == 3)
14429     OP_E_register (bytemode, sizeflag);
14430   else
14431     OP_E_memory (bytemode, sizeflag);
14432 }
14433
14434 static void
14435 OP_G (int bytemode, int sizeflag)
14436 {
14437   int add = 0;
14438   const char **names;
14439   USED_REX (REX_R);
14440   if (rex & REX_R)
14441     add += 8;
14442   switch (bytemode)
14443     {
14444     case b_mode:
14445       USED_REX (0);
14446       if (rex)
14447         oappend (names8rex[modrm.reg + add]);
14448       else
14449         oappend (names8[modrm.reg + add]);
14450       break;
14451     case w_mode:
14452       oappend (names16[modrm.reg + add]);
14453       break;
14454     case d_mode:
14455     case db_mode:
14456     case dw_mode:
14457       oappend (names32[modrm.reg + add]);
14458       break;
14459     case q_mode:
14460       oappend (names64[modrm.reg + add]);
14461       break;
14462     case bnd_mode:
14463       if (modrm.reg > 0x3)
14464         {
14465           oappend ("(bad)");
14466           return;
14467         }
14468       oappend (names_bnd[modrm.reg]);
14469       break;
14470     case v_mode:
14471     case dq_mode:
14472     case dqb_mode:
14473     case dqd_mode:
14474     case dqw_mode:
14475     case movsxd_mode:
14476       USED_REX (REX_W);
14477       if (rex & REX_W)
14478         oappend (names64[modrm.reg + add]);
14479       else
14480         {
14481           if ((sizeflag & DFLAG)
14482               || (bytemode != v_mode && bytemode != movsxd_mode))
14483             oappend (names32[modrm.reg + add]);
14484           else
14485             oappend (names16[modrm.reg + add]);
14486           used_prefixes |= (prefixes & PREFIX_DATA);
14487         }
14488       break;
14489     case va_mode:
14490       names = (address_mode == mode_64bit
14491                ? names64 : names32);
14492       if (!(prefixes & PREFIX_ADDR))
14493         {
14494           if (address_mode == mode_16bit)
14495             names = names16;
14496         }
14497       else
14498         {
14499           /* Remove "addr16/addr32".  */
14500           all_prefixes[last_addr_prefix] = 0;
14501           names = (address_mode != mode_32bit
14502                        ? names32 : names16);
14503           used_prefixes |= PREFIX_ADDR;
14504         }
14505       oappend (names[modrm.reg + add]);
14506       break;
14507     case m_mode:
14508       if (address_mode == mode_64bit)
14509         oappend (names64[modrm.reg + add]);
14510       else
14511         oappend (names32[modrm.reg + add]);
14512       break;
14513     case mask_bd_mode:
14514     case mask_mode:
14515       if ((modrm.reg + add) > 0x7)
14516         {
14517           oappend ("(bad)");
14518           return;
14519         }
14520       oappend (names_mask[modrm.reg + add]);
14521       break;
14522     default:
14523       oappend (INTERNAL_DISASSEMBLER_ERROR);
14524       break;
14525     }
14526 }
14527
14528 static bfd_vma
14529 get64 (void)
14530 {
14531   bfd_vma x;
14532 #ifdef BFD64
14533   unsigned int a;
14534   unsigned int b;
14535
14536   FETCH_DATA (the_info, codep + 8);
14537   a = *codep++ & 0xff;
14538   a |= (*codep++ & 0xff) << 8;
14539   a |= (*codep++ & 0xff) << 16;
14540   a |= (*codep++ & 0xffu) << 24;
14541   b = *codep++ & 0xff;
14542   b |= (*codep++ & 0xff) << 8;
14543   b |= (*codep++ & 0xff) << 16;
14544   b |= (*codep++ & 0xffu) << 24;
14545   x = a + ((bfd_vma) b << 32);
14546 #else
14547   abort ();
14548   x = 0;
14549 #endif
14550   return x;
14551 }
14552
14553 static bfd_signed_vma
14554 get32 (void)
14555 {
14556   bfd_signed_vma x = 0;
14557
14558   FETCH_DATA (the_info, codep + 4);
14559   x = *codep++ & (bfd_signed_vma) 0xff;
14560   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
14561   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
14562   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
14563   return x;
14564 }
14565
14566 static bfd_signed_vma
14567 get32s (void)
14568 {
14569   bfd_signed_vma x = 0;
14570
14571   FETCH_DATA (the_info, codep + 4);
14572   x = *codep++ & (bfd_signed_vma) 0xff;
14573   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
14574   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
14575   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
14576
14577   x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
14578
14579   return x;
14580 }
14581
14582 static int
14583 get16 (void)
14584 {
14585   int x = 0;
14586
14587   FETCH_DATA (the_info, codep + 2);
14588   x = *codep++ & 0xff;
14589   x |= (*codep++ & 0xff) << 8;
14590   return x;
14591 }
14592
14593 static void
14594 set_op (bfd_vma op, int riprel)
14595 {
14596   op_index[op_ad] = op_ad;
14597   if (address_mode == mode_64bit)
14598     {
14599       op_address[op_ad] = op;
14600       op_riprel[op_ad] = riprel;
14601     }
14602   else
14603     {
14604       /* Mask to get a 32-bit address.  */
14605       op_address[op_ad] = op & 0xffffffff;
14606       op_riprel[op_ad] = riprel & 0xffffffff;
14607     }
14608 }
14609
14610 static void
14611 OP_REG (int code, int sizeflag)
14612 {
14613   const char *s;
14614   int add;
14615
14616   switch (code)
14617     {
14618     case es_reg: case ss_reg: case cs_reg:
14619     case ds_reg: case fs_reg: case gs_reg:
14620       oappend (names_seg[code - es_reg]);
14621       return;
14622     }
14623
14624   USED_REX (REX_B);
14625   if (rex & REX_B)
14626     add = 8;
14627   else
14628     add = 0;
14629
14630   switch (code)
14631     {
14632     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
14633     case sp_reg: case bp_reg: case si_reg: case di_reg:
14634       s = names16[code - ax_reg + add];
14635       break;
14636     case al_reg: case ah_reg: case cl_reg: case ch_reg:
14637     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
14638       USED_REX (0);
14639       if (rex)
14640         s = names8rex[code - al_reg + add];
14641       else
14642         s = names8[code - al_reg];
14643       break;
14644     case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
14645     case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
14646       if (address_mode == mode_64bit
14647           && ((sizeflag & DFLAG) || (rex & REX_W)))
14648         {
14649           s = names64[code - rAX_reg + add];
14650           break;
14651         }
14652       code += eAX_reg - rAX_reg;
14653       /* Fall through.  */
14654     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
14655     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
14656       USED_REX (REX_W);
14657       if (rex & REX_W)
14658         s = names64[code - eAX_reg + add];
14659       else
14660         {
14661           if (sizeflag & DFLAG)
14662             s = names32[code - eAX_reg + add];
14663           else
14664             s = names16[code - eAX_reg + add];
14665           used_prefixes |= (prefixes & PREFIX_DATA);
14666         }
14667       break;
14668     default:
14669       s = INTERNAL_DISASSEMBLER_ERROR;
14670       break;
14671     }
14672   oappend (s);
14673 }
14674
14675 static void
14676 OP_IMREG (int code, int sizeflag)
14677 {
14678   const char *s;
14679
14680   switch (code)
14681     {
14682     case indir_dx_reg:
14683       if (intel_syntax)
14684         s = "dx";
14685       else
14686         s = "(%dx)";
14687       break;
14688     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
14689     case sp_reg: case bp_reg: case si_reg: case di_reg:
14690       s = names16[code - ax_reg];
14691       break;
14692     case es_reg: case ss_reg: case cs_reg:
14693     case ds_reg: case fs_reg: case gs_reg:
14694       s = names_seg[code - es_reg];
14695       break;
14696     case al_reg: case ah_reg: case cl_reg: case ch_reg:
14697     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
14698       USED_REX (0);
14699       if (rex)
14700         s = names8rex[code - al_reg];
14701       else
14702         s = names8[code - al_reg];
14703       break;
14704     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
14705     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
14706       USED_REX (REX_W);
14707       if (rex & REX_W)
14708         s = names64[code - eAX_reg];
14709       else
14710         {
14711           if (sizeflag & DFLAG)
14712             s = names32[code - eAX_reg];
14713           else
14714             s = names16[code - eAX_reg];
14715           used_prefixes |= (prefixes & PREFIX_DATA);
14716         }
14717       break;
14718     case z_mode_ax_reg:
14719       if ((rex & REX_W) || (sizeflag & DFLAG))
14720         s = *names32;
14721       else
14722         s = *names16;
14723       if (!(rex & REX_W))
14724         used_prefixes |= (prefixes & PREFIX_DATA);
14725       break;
14726     default:
14727       s = INTERNAL_DISASSEMBLER_ERROR;
14728       break;
14729     }
14730   oappend (s);
14731 }
14732
14733 static void
14734 OP_I (int bytemode, int sizeflag)
14735 {
14736   bfd_signed_vma op;
14737   bfd_signed_vma mask = -1;
14738
14739   switch (bytemode)
14740     {
14741     case b_mode:
14742       FETCH_DATA (the_info, codep + 1);
14743       op = *codep++;
14744       mask = 0xff;
14745       break;
14746     case v_mode:
14747       USED_REX (REX_W);
14748       if (rex & REX_W)
14749         op = get32s ();
14750       else
14751         {
14752           if (sizeflag & DFLAG)
14753             {
14754               op = get32 ();
14755               mask = 0xffffffff;
14756             }
14757           else
14758             {
14759               op = get16 ();
14760               mask = 0xfffff;
14761             }
14762           used_prefixes |= (prefixes & PREFIX_DATA);
14763         }
14764       break;
14765     case d_mode:
14766       mask = 0xffffffff;
14767       op = get32 ();
14768       break;
14769     case w_mode:
14770       mask = 0xfffff;
14771       op = get16 ();
14772       break;
14773     case const_1_mode:
14774       if (intel_syntax)
14775         oappend ("1");
14776       return;
14777     default:
14778       oappend (INTERNAL_DISASSEMBLER_ERROR);
14779       return;
14780     }
14781
14782   op &= mask;
14783   scratchbuf[0] = '$';
14784   print_operand_value (scratchbuf + 1, 1, op);
14785   oappend_maybe_intel (scratchbuf);
14786   scratchbuf[0] = '\0';
14787 }
14788
14789 static void
14790 OP_I64 (int bytemode, int sizeflag)
14791 {
14792   if (bytemode != v_mode || address_mode != mode_64bit || !(rex & REX_W))
14793     {
14794       OP_I (bytemode, sizeflag);
14795       return;
14796     }
14797
14798   USED_REX (REX_W);
14799
14800   scratchbuf[0] = '$';
14801   print_operand_value (scratchbuf + 1, 1, get64 ());
14802   oappend_maybe_intel (scratchbuf);
14803   scratchbuf[0] = '\0';
14804 }
14805
14806 static void
14807 OP_sI (int bytemode, int sizeflag)
14808 {
14809   bfd_signed_vma op;
14810
14811   switch (bytemode)
14812     {
14813     case b_mode:
14814     case b_T_mode:
14815       FETCH_DATA (the_info, codep + 1);
14816       op = *codep++;
14817       if ((op & 0x80) != 0)
14818         op -= 0x100;
14819       if (bytemode == b_T_mode)
14820         {
14821           if (address_mode != mode_64bit
14822               || !((sizeflag & DFLAG) || (rex & REX_W)))
14823             {
14824               /* The operand-size prefix is overridden by a REX prefix.  */
14825               if ((sizeflag & DFLAG) || (rex & REX_W))
14826                 op &= 0xffffffff;
14827               else
14828                 op &= 0xffff;
14829           }
14830         }
14831       else
14832         {
14833           if (!(rex & REX_W))
14834             {
14835               if (sizeflag & DFLAG)
14836                 op &= 0xffffffff;
14837               else
14838                 op &= 0xffff;
14839             }
14840         }
14841       break;
14842     case v_mode:
14843       /* The operand-size prefix is overridden by a REX prefix.  */
14844       if ((sizeflag & DFLAG) || (rex & REX_W))
14845         op = get32s ();
14846       else
14847         op = get16 ();
14848       break;
14849     default:
14850       oappend (INTERNAL_DISASSEMBLER_ERROR);
14851       return;
14852     }
14853
14854   scratchbuf[0] = '$';
14855   print_operand_value (scratchbuf + 1, 1, op);
14856   oappend_maybe_intel (scratchbuf);
14857 }
14858
14859 static void
14860 OP_J (int bytemode, int sizeflag)
14861 {
14862   bfd_vma disp;
14863   bfd_vma mask = -1;
14864   bfd_vma segment = 0;
14865
14866   switch (bytemode)
14867     {
14868     case b_mode:
14869       FETCH_DATA (the_info, codep + 1);
14870       disp = *codep++;
14871       if ((disp & 0x80) != 0)
14872         disp -= 0x100;
14873       break;
14874     case v_mode:
14875       if (isa64 != intel64)
14876     case dqw_mode:
14877         USED_REX (REX_W);
14878       if ((sizeflag & DFLAG)
14879           || (address_mode == mode_64bit
14880               && ((isa64 == intel64 && bytemode != dqw_mode)
14881                   || (rex & REX_W))))
14882         disp = get32s ();
14883       else
14884         {
14885           disp = get16 ();
14886           if ((disp & 0x8000) != 0)
14887             disp -= 0x10000;
14888           /* In 16bit mode, address is wrapped around at 64k within
14889              the same segment.  Otherwise, a data16 prefix on a jump
14890              instruction means that the pc is masked to 16 bits after
14891              the displacement is added!  */
14892           mask = 0xffff;
14893           if ((prefixes & PREFIX_DATA) == 0)
14894             segment = ((start_pc + (codep - start_codep))
14895                        & ~((bfd_vma) 0xffff));
14896         }
14897       if (address_mode != mode_64bit
14898           || (isa64 != intel64 && !(rex & REX_W)))
14899         used_prefixes |= (prefixes & PREFIX_DATA);
14900       break;
14901     default:
14902       oappend (INTERNAL_DISASSEMBLER_ERROR);
14903       return;
14904     }
14905   disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment;
14906   set_op (disp, 0);
14907   print_operand_value (scratchbuf, 1, disp);
14908   oappend (scratchbuf);
14909 }
14910
14911 static void
14912 OP_SEG (int bytemode, int sizeflag)
14913 {
14914   if (bytemode == w_mode)
14915     oappend (names_seg[modrm.reg]);
14916   else
14917     OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
14918 }
14919
14920 static void
14921 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
14922 {
14923   int seg, offset;
14924
14925   if (sizeflag & DFLAG)
14926     {
14927       offset = get32 ();
14928       seg = get16 ();
14929     }
14930   else
14931     {
14932       offset = get16 ();
14933       seg = get16 ();
14934     }
14935   used_prefixes |= (prefixes & PREFIX_DATA);
14936   if (intel_syntax)
14937     sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
14938   else
14939     sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
14940   oappend (scratchbuf);
14941 }
14942
14943 static void
14944 OP_OFF (int bytemode, int sizeflag)
14945 {
14946   bfd_vma off;
14947
14948   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
14949     intel_operand_size (bytemode, sizeflag);
14950   append_seg ();
14951
14952   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
14953     off = get32 ();
14954   else
14955     off = get16 ();
14956
14957   if (intel_syntax)
14958     {
14959       if (!active_seg_prefix)
14960         {
14961           oappend (names_seg[ds_reg - es_reg]);
14962           oappend (":");
14963         }
14964     }
14965   print_operand_value (scratchbuf, 1, off);
14966   oappend (scratchbuf);
14967 }
14968
14969 static void
14970 OP_OFF64 (int bytemode, int sizeflag)
14971 {
14972   bfd_vma off;
14973
14974   if (address_mode != mode_64bit
14975       || (prefixes & PREFIX_ADDR))
14976     {
14977       OP_OFF (bytemode, sizeflag);
14978       return;
14979     }
14980
14981   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
14982     intel_operand_size (bytemode, sizeflag);
14983   append_seg ();
14984
14985   off = get64 ();
14986
14987   if (intel_syntax)
14988     {
14989       if (!active_seg_prefix)
14990         {
14991           oappend (names_seg[ds_reg - es_reg]);
14992           oappend (":");
14993         }
14994     }
14995   print_operand_value (scratchbuf, 1, off);
14996   oappend (scratchbuf);
14997 }
14998
14999 static void
15000 ptr_reg (int code, int sizeflag)
15001 {
15002   const char *s;
15003
15004   *obufp++ = open_char;
15005   used_prefixes |= (prefixes & PREFIX_ADDR);
15006   if (address_mode == mode_64bit)
15007     {
15008       if (!(sizeflag & AFLAG))
15009         s = names32[code - eAX_reg];
15010       else
15011         s = names64[code - eAX_reg];
15012     }
15013   else if (sizeflag & AFLAG)
15014     s = names32[code - eAX_reg];
15015   else
15016     s = names16[code - eAX_reg];
15017   oappend (s);
15018   *obufp++ = close_char;
15019   *obufp = 0;
15020 }
15021
15022 static void
15023 OP_ESreg (int code, int sizeflag)
15024 {
15025   if (intel_syntax)
15026     {
15027       switch (codep[-1])
15028         {
15029         case 0x6d:      /* insw/insl */
15030           intel_operand_size (z_mode, sizeflag);
15031           break;
15032         case 0xa5:      /* movsw/movsl/movsq */
15033         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
15034         case 0xab:      /* stosw/stosl */
15035         case 0xaf:      /* scasw/scasl */
15036           intel_operand_size (v_mode, sizeflag);
15037           break;
15038         default:
15039           intel_operand_size (b_mode, sizeflag);
15040         }
15041     }
15042   oappend_maybe_intel ("%es:");
15043   ptr_reg (code, sizeflag);
15044 }
15045
15046 static void
15047 OP_DSreg (int code, int sizeflag)
15048 {
15049   if (intel_syntax)
15050     {
15051       switch (codep[-1])
15052         {
15053         case 0x6f:      /* outsw/outsl */
15054           intel_operand_size (z_mode, sizeflag);
15055           break;
15056         case 0xa5:      /* movsw/movsl/movsq */
15057         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
15058         case 0xad:      /* lodsw/lodsl/lodsq */
15059           intel_operand_size (v_mode, sizeflag);
15060           break;
15061         default:
15062           intel_operand_size (b_mode, sizeflag);
15063         }
15064     }
15065   /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
15066      default segment register DS is printed.  */
15067   if (!active_seg_prefix)
15068     active_seg_prefix = PREFIX_DS;
15069   append_seg ();
15070   ptr_reg (code, sizeflag);
15071 }
15072
15073 static void
15074 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15075 {
15076   int add;
15077   if (rex & REX_R)
15078     {
15079       USED_REX (REX_R);
15080       add = 8;
15081     }
15082   else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
15083     {
15084       all_prefixes[last_lock_prefix] = 0;
15085       used_prefixes |= PREFIX_LOCK;
15086       add = 8;
15087     }
15088   else
15089     add = 0;
15090   sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
15091   oappend_maybe_intel (scratchbuf);
15092 }
15093
15094 static void
15095 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15096 {
15097   int add;
15098   USED_REX (REX_R);
15099   if (rex & REX_R)
15100     add = 8;
15101   else
15102     add = 0;
15103   if (intel_syntax)
15104     sprintf (scratchbuf, "db%d", modrm.reg + add);
15105   else
15106     sprintf (scratchbuf, "%%db%d", modrm.reg + add);
15107   oappend (scratchbuf);
15108 }
15109
15110 static void
15111 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15112 {
15113   sprintf (scratchbuf, "%%tr%d", modrm.reg);
15114   oappend_maybe_intel (scratchbuf);
15115 }
15116
15117 static void
15118 OP_R (int bytemode, int sizeflag)
15119 {
15120   /* Skip mod/rm byte.  */
15121   MODRM_CHECK;
15122   codep++;
15123   OP_E_register (bytemode, sizeflag);
15124 }
15125
15126 static void
15127 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15128 {
15129   int reg = modrm.reg;
15130   const char **names;
15131
15132   used_prefixes |= (prefixes & PREFIX_DATA);
15133   if (prefixes & PREFIX_DATA)
15134     {
15135       names = names_xmm;
15136       USED_REX (REX_R);
15137       if (rex & REX_R)
15138         reg += 8;
15139     }
15140   else
15141     names = names_mm;
15142   oappend (names[reg]);
15143 }
15144
15145 static void
15146 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
15147 {
15148   int reg = modrm.reg;
15149   const char **names;
15150
15151   USED_REX (REX_R);
15152   if (rex & REX_R)
15153     reg += 8;
15154   if (vex.evex)
15155     {
15156       if (!vex.r)
15157         reg += 16;
15158     }
15159
15160   if (need_vex
15161       && bytemode != xmm_mode
15162       && bytemode != xmmq_mode
15163       && bytemode != evex_half_bcst_xmmq_mode
15164       && bytemode != ymm_mode
15165       && bytemode != scalar_mode)
15166     {
15167       switch (vex.length)
15168         {
15169         case 128:
15170           names = names_xmm;
15171           break;
15172         case 256:
15173           if (vex.w
15174               || (bytemode != vex_vsib_q_w_dq_mode
15175                   && bytemode != vex_vsib_q_w_d_mode))
15176             names = names_ymm;
15177           else
15178             names = names_xmm;
15179           break;
15180         case 512:
15181           names = names_zmm;
15182           break;
15183         default:
15184           abort ();
15185         }
15186     }
15187   else if (bytemode == xmmq_mode
15188            || bytemode == evex_half_bcst_xmmq_mode)
15189     {
15190       switch (vex.length)
15191         {
15192         case 128:
15193         case 256:
15194           names = names_xmm;
15195           break;
15196         case 512:
15197           names = names_ymm;
15198           break;
15199         default:
15200           abort ();
15201         }
15202     }
15203   else if (bytemode == ymm_mode)
15204     names = names_ymm;
15205   else
15206     names = names_xmm;
15207   oappend (names[reg]);
15208 }
15209
15210 static void
15211 OP_EM (int bytemode, int sizeflag)
15212 {
15213   int reg;
15214   const char **names;
15215
15216   if (modrm.mod != 3)
15217     {
15218       if (intel_syntax
15219           && (bytemode == v_mode || bytemode == v_swap_mode))
15220         {
15221           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
15222           used_prefixes |= (prefixes & PREFIX_DATA);
15223         }
15224       OP_E (bytemode, sizeflag);
15225       return;
15226     }
15227
15228   if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
15229     swap_operand ();
15230
15231   /* Skip mod/rm byte.  */
15232   MODRM_CHECK;
15233   codep++;
15234   used_prefixes |= (prefixes & PREFIX_DATA);
15235   reg = modrm.rm;
15236   if (prefixes & PREFIX_DATA)
15237     {
15238       names = names_xmm;
15239       USED_REX (REX_B);
15240       if (rex & REX_B)
15241         reg += 8;
15242     }
15243   else
15244     names = names_mm;
15245   oappend (names[reg]);
15246 }
15247
15248 /* cvt* are the only instructions in sse2 which have
15249    both SSE and MMX operands and also have 0x66 prefix
15250    in their opcode. 0x66 was originally used to differentiate
15251    between SSE and MMX instruction(operands). So we have to handle the
15252    cvt* separately using OP_EMC and OP_MXC */
15253 static void
15254 OP_EMC (int bytemode, int sizeflag)
15255 {
15256   if (modrm.mod != 3)
15257     {
15258       if (intel_syntax && bytemode == v_mode)
15259         {
15260           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
15261           used_prefixes |= (prefixes & PREFIX_DATA);
15262         }
15263       OP_E (bytemode, sizeflag);
15264       return;
15265     }
15266
15267   /* Skip mod/rm byte.  */
15268   MODRM_CHECK;
15269   codep++;
15270   used_prefixes |= (prefixes & PREFIX_DATA);
15271   oappend (names_mm[modrm.rm]);
15272 }
15273
15274 static void
15275 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15276 {
15277   used_prefixes |= (prefixes & PREFIX_DATA);
15278   oappend (names_mm[modrm.reg]);
15279 }
15280
15281 static void
15282 OP_EX (int bytemode, int sizeflag)
15283 {
15284   int reg;
15285   const char **names;
15286
15287   /* Skip mod/rm byte.  */
15288   MODRM_CHECK;
15289   codep++;
15290
15291   if (modrm.mod != 3)
15292     {
15293       OP_E_memory (bytemode, sizeflag);
15294       return;
15295     }
15296
15297   reg = modrm.rm;
15298   USED_REX (REX_B);
15299   if (rex & REX_B)
15300     reg += 8;
15301   if (vex.evex)
15302     {
15303       USED_REX (REX_X);
15304       if ((rex & REX_X))
15305         reg += 16;
15306     }
15307
15308   if ((sizeflag & SUFFIX_ALWAYS)
15309       && (bytemode == x_swap_mode
15310           || bytemode == d_swap_mode
15311           || bytemode == d_scalar_swap_mode
15312           || bytemode == q_swap_mode
15313           || bytemode == q_scalar_swap_mode))
15314     swap_operand ();
15315
15316   if (need_vex
15317       && bytemode != xmm_mode
15318       && bytemode != xmmdw_mode
15319       && bytemode != xmmqd_mode
15320       && bytemode != xmm_mb_mode
15321       && bytemode != xmm_mw_mode
15322       && bytemode != xmm_md_mode
15323       && bytemode != xmm_mq_mode
15324       && bytemode != xmmq_mode
15325       && bytemode != evex_half_bcst_xmmq_mode
15326       && bytemode != ymm_mode
15327       && bytemode != d_scalar_swap_mode
15328       && bytemode != q_scalar_swap_mode
15329       && bytemode != vex_scalar_w_dq_mode)
15330     {
15331       switch (vex.length)
15332         {
15333         case 128:
15334           names = names_xmm;
15335           break;
15336         case 256:
15337           names = names_ymm;
15338           break;
15339         case 512:
15340           names = names_zmm;
15341           break;
15342         default:
15343           abort ();
15344         }
15345     }
15346   else if (bytemode == xmmq_mode
15347            || bytemode == evex_half_bcst_xmmq_mode)
15348     {
15349       switch (vex.length)
15350         {
15351         case 128:
15352         case 256:
15353           names = names_xmm;
15354           break;
15355         case 512:
15356           names = names_ymm;
15357           break;
15358         default:
15359           abort ();
15360         }
15361     }
15362   else if (bytemode == ymm_mode)
15363     names = names_ymm;
15364   else
15365     names = names_xmm;
15366   oappend (names[reg]);
15367 }
15368
15369 static void
15370 OP_MS (int bytemode, int sizeflag)
15371 {
15372   if (modrm.mod == 3)
15373     OP_EM (bytemode, sizeflag);
15374   else
15375     BadOp ();
15376 }
15377
15378 static void
15379 OP_XS (int bytemode, int sizeflag)
15380 {
15381   if (modrm.mod == 3)
15382     OP_EX (bytemode, sizeflag);
15383   else
15384     BadOp ();
15385 }
15386
15387 static void
15388 OP_M (int bytemode, int sizeflag)
15389 {
15390   if (modrm.mod == 3)
15391     /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
15392     BadOp ();
15393   else
15394     OP_E (bytemode, sizeflag);
15395 }
15396
15397 static void
15398 OP_0f07 (int bytemode, int sizeflag)
15399 {
15400   if (modrm.mod != 3 || modrm.rm != 0)
15401     BadOp ();
15402   else
15403     OP_E (bytemode, sizeflag);
15404 }
15405
15406 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
15407    32bit mode and "xchg %rax,%rax" in 64bit mode.  */
15408
15409 static void
15410 NOP_Fixup1 (int bytemode, int sizeflag)
15411 {
15412   if ((prefixes & PREFIX_DATA) != 0
15413       || (rex != 0
15414           && rex != 0x48
15415           && address_mode == mode_64bit))
15416     OP_REG (bytemode, sizeflag);
15417   else
15418     strcpy (obuf, "nop");
15419 }
15420
15421 static void
15422 NOP_Fixup2 (int bytemode, int sizeflag)
15423 {
15424   if ((prefixes & PREFIX_DATA) != 0
15425       || (rex != 0
15426           && rex != 0x48
15427           && address_mode == mode_64bit))
15428     OP_IMREG (bytemode, sizeflag);
15429 }
15430
15431 static const char *const Suffix3DNow[] = {
15432 /* 00 */        NULL,           NULL,           NULL,           NULL,
15433 /* 04 */        NULL,           NULL,           NULL,           NULL,
15434 /* 08 */        NULL,           NULL,           NULL,           NULL,
15435 /* 0C */        "pi2fw",        "pi2fd",        NULL,           NULL,
15436 /* 10 */        NULL,           NULL,           NULL,           NULL,
15437 /* 14 */        NULL,           NULL,           NULL,           NULL,
15438 /* 18 */        NULL,           NULL,           NULL,           NULL,
15439 /* 1C */        "pf2iw",        "pf2id",        NULL,           NULL,
15440 /* 20 */        NULL,           NULL,           NULL,           NULL,
15441 /* 24 */        NULL,           NULL,           NULL,           NULL,
15442 /* 28 */        NULL,           NULL,           NULL,           NULL,
15443 /* 2C */        NULL,           NULL,           NULL,           NULL,
15444 /* 30 */        NULL,           NULL,           NULL,           NULL,
15445 /* 34 */        NULL,           NULL,           NULL,           NULL,
15446 /* 38 */        NULL,           NULL,           NULL,           NULL,
15447 /* 3C */        NULL,           NULL,           NULL,           NULL,
15448 /* 40 */        NULL,           NULL,           NULL,           NULL,
15449 /* 44 */        NULL,           NULL,           NULL,           NULL,
15450 /* 48 */        NULL,           NULL,           NULL,           NULL,
15451 /* 4C */        NULL,           NULL,           NULL,           NULL,
15452 /* 50 */        NULL,           NULL,           NULL,           NULL,
15453 /* 54 */        NULL,           NULL,           NULL,           NULL,
15454 /* 58 */        NULL,           NULL,           NULL,           NULL,
15455 /* 5C */        NULL,           NULL,           NULL,           NULL,
15456 /* 60 */        NULL,           NULL,           NULL,           NULL,
15457 /* 64 */        NULL,           NULL,           NULL,           NULL,
15458 /* 68 */        NULL,           NULL,           NULL,           NULL,
15459 /* 6C */        NULL,           NULL,           NULL,           NULL,
15460 /* 70 */        NULL,           NULL,           NULL,           NULL,
15461 /* 74 */        NULL,           NULL,           NULL,           NULL,
15462 /* 78 */        NULL,           NULL,           NULL,           NULL,
15463 /* 7C */        NULL,           NULL,           NULL,           NULL,
15464 /* 80 */        NULL,           NULL,           NULL,           NULL,
15465 /* 84 */        NULL,           NULL,           NULL,           NULL,
15466 /* 88 */        NULL,           NULL,           "pfnacc",       NULL,
15467 /* 8C */        NULL,           NULL,           "pfpnacc",      NULL,
15468 /* 90 */        "pfcmpge",      NULL,           NULL,           NULL,
15469 /* 94 */        "pfmin",        NULL,           "pfrcp",        "pfrsqrt",
15470 /* 98 */        NULL,           NULL,           "pfsub",        NULL,
15471 /* 9C */        NULL,           NULL,           "pfadd",        NULL,
15472 /* A0 */        "pfcmpgt",      NULL,           NULL,           NULL,
15473 /* A4 */        "pfmax",        NULL,           "pfrcpit1",     "pfrsqit1",
15474 /* A8 */        NULL,           NULL,           "pfsubr",       NULL,
15475 /* AC */        NULL,           NULL,           "pfacc",        NULL,
15476 /* B0 */        "pfcmpeq",      NULL,           NULL,           NULL,
15477 /* B4 */        "pfmul",        NULL,           "pfrcpit2",     "pmulhrw",
15478 /* B8 */        NULL,           NULL,           NULL,           "pswapd",
15479 /* BC */        NULL,           NULL,           NULL,           "pavgusb",
15480 /* C0 */        NULL,           NULL,           NULL,           NULL,
15481 /* C4 */        NULL,           NULL,           NULL,           NULL,
15482 /* C8 */        NULL,           NULL,           NULL,           NULL,
15483 /* CC */        NULL,           NULL,           NULL,           NULL,
15484 /* D0 */        NULL,           NULL,           NULL,           NULL,
15485 /* D4 */        NULL,           NULL,           NULL,           NULL,
15486 /* D8 */        NULL,           NULL,           NULL,           NULL,
15487 /* DC */        NULL,           NULL,           NULL,           NULL,
15488 /* E0 */        NULL,           NULL,           NULL,           NULL,
15489 /* E4 */        NULL,           NULL,           NULL,           NULL,
15490 /* E8 */        NULL,           NULL,           NULL,           NULL,
15491 /* EC */        NULL,           NULL,           NULL,           NULL,
15492 /* F0 */        NULL,           NULL,           NULL,           NULL,
15493 /* F4 */        NULL,           NULL,           NULL,           NULL,
15494 /* F8 */        NULL,           NULL,           NULL,           NULL,
15495 /* FC */        NULL,           NULL,           NULL,           NULL,
15496 };
15497
15498 static void
15499 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15500 {
15501   const char *mnemonic;
15502
15503   FETCH_DATA (the_info, codep + 1);
15504   /* AMD 3DNow! instructions are specified by an opcode suffix in the
15505      place where an 8-bit immediate would normally go.  ie. the last
15506      byte of the instruction.  */
15507   obufp = mnemonicendp;
15508   mnemonic = Suffix3DNow[*codep++ & 0xff];
15509   if (mnemonic)
15510     oappend (mnemonic);
15511   else
15512     {
15513       /* Since a variable sized modrm/sib chunk is between the start
15514          of the opcode (0x0f0f) and the opcode suffix, we need to do
15515          all the modrm processing first, and don't know until now that
15516          we have a bad opcode.  This necessitates some cleaning up.  */
15517       op_out[0][0] = '\0';
15518       op_out[1][0] = '\0';
15519       BadOp ();
15520     }
15521   mnemonicendp = obufp;
15522 }
15523
15524 static struct op simd_cmp_op[] =
15525 {
15526   { STRING_COMMA_LEN ("eq") },
15527   { STRING_COMMA_LEN ("lt") },
15528   { STRING_COMMA_LEN ("le") },
15529   { STRING_COMMA_LEN ("unord") },
15530   { STRING_COMMA_LEN ("neq") },
15531   { STRING_COMMA_LEN ("nlt") },
15532   { STRING_COMMA_LEN ("nle") },
15533   { STRING_COMMA_LEN ("ord") }
15534 };
15535
15536 static void
15537 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15538 {
15539   unsigned int cmp_type;
15540
15541   FETCH_DATA (the_info, codep + 1);
15542   cmp_type = *codep++ & 0xff;
15543   if (cmp_type < ARRAY_SIZE (simd_cmp_op))
15544     {
15545       char suffix [3];
15546       char *p = mnemonicendp - 2;
15547       suffix[0] = p[0];
15548       suffix[1] = p[1];
15549       suffix[2] = '\0';
15550       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
15551       mnemonicendp += simd_cmp_op[cmp_type].len;
15552     }
15553   else
15554     {
15555       /* We have a reserved extension byte.  Output it directly.  */
15556       scratchbuf[0] = '$';
15557       print_operand_value (scratchbuf + 1, 1, cmp_type);
15558       oappend_maybe_intel (scratchbuf);
15559       scratchbuf[0] = '\0';
15560     }
15561 }
15562
15563 static void
15564 OP_Mwait (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
15565 {
15566   /* mwait %eax,%ecx / mwaitx %eax,%ecx,%ebx  */
15567   if (!intel_syntax)
15568     {
15569       strcpy (op_out[0], names32[0]);
15570       strcpy (op_out[1], names32[1]);
15571       if (bytemode == eBX_reg)
15572         strcpy (op_out[2], names32[3]);
15573       two_source_ops = 1;
15574     }
15575   /* Skip mod/rm byte.  */
15576   MODRM_CHECK;
15577   codep++;
15578 }
15579
15580 static void
15581 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
15582             int sizeflag ATTRIBUTE_UNUSED)
15583 {
15584   /* monitor %{e,r,}ax,%ecx,%edx"  */
15585   if (!intel_syntax)
15586     {
15587       const char **names = (address_mode == mode_64bit
15588                             ? names64 : names32);
15589
15590       if (prefixes & PREFIX_ADDR)
15591         {
15592           /* Remove "addr16/addr32".  */
15593           all_prefixes[last_addr_prefix] = 0;
15594           names = (address_mode != mode_32bit
15595                    ? names32 : names16);
15596           used_prefixes |= PREFIX_ADDR;
15597         }
15598       else if (address_mode == mode_16bit)
15599         names = names16;
15600       strcpy (op_out[0], names[0]);
15601       strcpy (op_out[1], names32[1]);
15602       strcpy (op_out[2], names32[2]);
15603       two_source_ops = 1;
15604     }
15605   /* Skip mod/rm byte.  */
15606   MODRM_CHECK;
15607   codep++;
15608 }
15609
15610 static void
15611 BadOp (void)
15612 {
15613   /* Throw away prefixes and 1st. opcode byte.  */
15614   codep = insn_codep + 1;
15615   oappend ("(bad)");
15616 }
15617
15618 static void
15619 REP_Fixup (int bytemode, int sizeflag)
15620 {
15621   /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
15622      lods and stos.  */
15623   if (prefixes & PREFIX_REPZ)
15624     all_prefixes[last_repz_prefix] = REP_PREFIX;
15625
15626   switch (bytemode)
15627     {
15628     case al_reg:
15629     case eAX_reg:
15630     case indir_dx_reg:
15631       OP_IMREG (bytemode, sizeflag);
15632       break;
15633     case eDI_reg:
15634       OP_ESreg (bytemode, sizeflag);
15635       break;
15636     case eSI_reg:
15637       OP_DSreg (bytemode, sizeflag);
15638       break;
15639     default:
15640       abort ();
15641       break;
15642     }
15643 }
15644
15645 static void
15646 SEP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15647 {
15648   if ( isa64 != amd64 )
15649     return;
15650
15651   obufp = obuf;
15652   BadOp ();
15653   mnemonicendp = obufp;
15654   ++codep;
15655 }
15656
15657 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
15658    "bnd".  */
15659
15660 static void
15661 BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15662 {
15663   if (prefixes & PREFIX_REPNZ)
15664     all_prefixes[last_repnz_prefix] = BND_PREFIX;
15665 }
15666
15667 /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
15668    "notrack".  */
15669
15670 static void
15671 NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED,
15672                int sizeflag ATTRIBUTE_UNUSED)
15673 {
15674   if (active_seg_prefix == PREFIX_DS
15675       && (address_mode != mode_64bit || last_data_prefix < 0))
15676     {
15677       /* NOTRACK prefix is only valid on indirect branch instructions.
15678          NB: DATA prefix is unsupported for Intel64.  */
15679       active_seg_prefix = 0;
15680       all_prefixes[last_seg_prefix] = NOTRACK_PREFIX;
15681     }
15682 }
15683
15684 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
15685    "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
15686  */
15687
15688 static void
15689 HLE_Fixup1 (int bytemode, int sizeflag)
15690 {
15691   if (modrm.mod != 3
15692       && (prefixes & PREFIX_LOCK) != 0)
15693     {
15694       if (prefixes & PREFIX_REPZ)
15695         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15696       if (prefixes & PREFIX_REPNZ)
15697         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15698     }
15699
15700   OP_E (bytemode, sizeflag);
15701 }
15702
15703 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
15704    "xacquire"/"xrelease" for memory operand.  No check for LOCK prefix.
15705  */
15706
15707 static void
15708 HLE_Fixup2 (int bytemode, int sizeflag)
15709 {
15710   if (modrm.mod != 3)
15711     {
15712       if (prefixes & PREFIX_REPZ)
15713         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15714       if (prefixes & PREFIX_REPNZ)
15715         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15716     }
15717
15718   OP_E (bytemode, sizeflag);
15719 }
15720
15721 /* Similar to OP_E.  But the 0xf3 prefixes should be displayed as
15722    "xrelease" for memory operand.  No check for LOCK prefix.   */
15723
15724 static void
15725 HLE_Fixup3 (int bytemode, int sizeflag)
15726 {
15727   if (modrm.mod != 3
15728       && last_repz_prefix > last_repnz_prefix
15729       && (prefixes & PREFIX_REPZ) != 0)
15730     all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15731
15732   OP_E (bytemode, sizeflag);
15733 }
15734
15735 static void
15736 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
15737 {
15738   USED_REX (REX_W);
15739   if (rex & REX_W)
15740     {
15741       /* Change cmpxchg8b to cmpxchg16b.  */
15742       char *p = mnemonicendp - 2;
15743       mnemonicendp = stpcpy (p, "16b");
15744       bytemode = o_mode;
15745     }
15746   else if ((prefixes & PREFIX_LOCK) != 0)
15747     {
15748       if (prefixes & PREFIX_REPZ)
15749         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15750       if (prefixes & PREFIX_REPNZ)
15751         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15752     }
15753
15754   OP_M (bytemode, sizeflag);
15755 }
15756
15757 static void
15758 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
15759 {
15760   const char **names;
15761
15762   if (need_vex)
15763     {
15764       switch (vex.length)
15765         {
15766         case 128:
15767           names = names_xmm;
15768           break;
15769         case 256:
15770           names = names_ymm;
15771           break;
15772         default:
15773           abort ();
15774         }
15775     }
15776   else
15777     names = names_xmm;
15778   oappend (names[reg]);
15779 }
15780
15781 static void
15782 CRC32_Fixup (int bytemode, int sizeflag)
15783 {
15784   /* Add proper suffix to "crc32".  */
15785   char *p = mnemonicendp;
15786
15787   switch (bytemode)
15788     {
15789     case b_mode:
15790       if (intel_syntax)
15791         goto skip;
15792
15793       *p++ = 'b';
15794       break;
15795     case v_mode:
15796       if (intel_syntax)
15797         goto skip;
15798
15799       USED_REX (REX_W);
15800       if (rex & REX_W)
15801         *p++ = 'q';
15802       else
15803         {
15804           if (sizeflag & DFLAG)
15805             *p++ = 'l';
15806           else
15807             *p++ = 'w';
15808           used_prefixes |= (prefixes & PREFIX_DATA);
15809         }
15810       break;
15811     default:
15812       oappend (INTERNAL_DISASSEMBLER_ERROR);
15813       break;
15814     }
15815   mnemonicendp = p;
15816   *p = '\0';
15817
15818  skip:
15819   if (modrm.mod == 3)
15820     {
15821       int add;
15822
15823       /* Skip mod/rm byte.  */
15824       MODRM_CHECK;
15825       codep++;
15826
15827       USED_REX (REX_B);
15828       add = (rex & REX_B) ? 8 : 0;
15829       if (bytemode == b_mode)
15830         {
15831           USED_REX (0);
15832           if (rex)
15833             oappend (names8rex[modrm.rm + add]);
15834           else
15835             oappend (names8[modrm.rm + add]);
15836         }
15837       else
15838         {
15839           USED_REX (REX_W);
15840           if (rex & REX_W)
15841             oappend (names64[modrm.rm + add]);
15842           else if ((prefixes & PREFIX_DATA))
15843             oappend (names16[modrm.rm + add]);
15844           else
15845             oappend (names32[modrm.rm + add]);
15846         }
15847     }
15848   else
15849     OP_E (bytemode, sizeflag);
15850 }
15851
15852 static void
15853 FXSAVE_Fixup (int bytemode, int sizeflag)
15854 {
15855   /* Add proper suffix to "fxsave" and "fxrstor".  */
15856   USED_REX (REX_W);
15857   if (rex & REX_W)
15858     {
15859       char *p = mnemonicendp;
15860       *p++ = '6';
15861       *p++ = '4';
15862       *p = '\0';
15863       mnemonicendp = p;
15864     }
15865   OP_M (bytemode, sizeflag);
15866 }
15867
15868 static void
15869 PCMPESTR_Fixup (int bytemode, int sizeflag)
15870 {
15871   /* Add proper suffix to "{,v}pcmpestr{i,m}".  */
15872   if (!intel_syntax)
15873     {
15874       char *p = mnemonicendp;
15875
15876       USED_REX (REX_W);
15877       if (rex & REX_W)
15878         *p++ = 'q';
15879       else if (sizeflag & SUFFIX_ALWAYS)
15880         *p++ = 'l';
15881
15882       *p = '\0';
15883       mnemonicendp = p;
15884     }
15885
15886   OP_EX (bytemode, sizeflag);
15887 }
15888
15889 /* Display the destination register operand for instructions with
15890    VEX. */
15891
15892 static void
15893 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
15894 {
15895   int reg;
15896   const char **names;
15897
15898   if (!need_vex)
15899     abort ();
15900
15901   if (!need_vex_reg)
15902     return;
15903
15904   reg = vex.register_specifier;
15905   vex.register_specifier = 0;
15906   if (address_mode != mode_64bit)
15907     reg &= 7;
15908   else if (vex.evex && !vex.v)
15909     reg += 16;
15910
15911   if (bytemode == vex_scalar_mode)
15912     {
15913       oappend (names_xmm[reg]);
15914       return;
15915     }
15916
15917   switch (vex.length)
15918     {
15919     case 128:
15920       switch (bytemode)
15921         {
15922         case vex_mode:
15923         case vex128_mode:
15924         case vex_vsib_q_w_dq_mode:
15925         case vex_vsib_q_w_d_mode:
15926           names = names_xmm;
15927           break;
15928         case dq_mode:
15929           if (rex & REX_W)
15930             names = names64;
15931           else
15932             names = names32;
15933           break;
15934         case mask_bd_mode:
15935         case mask_mode:
15936           if (reg > 0x7)
15937             {
15938               oappend ("(bad)");
15939               return;
15940             }
15941           names = names_mask;
15942           break;
15943         default:
15944           abort ();
15945           return;
15946         }
15947       break;
15948     case 256:
15949       switch (bytemode)
15950         {
15951         case vex_mode:
15952         case vex256_mode:
15953           names = names_ymm;
15954           break;
15955         case vex_vsib_q_w_dq_mode:
15956         case vex_vsib_q_w_d_mode:
15957           names = vex.w ? names_ymm : names_xmm;
15958           break;
15959         case mask_bd_mode:
15960         case mask_mode:
15961           if (reg > 0x7)
15962             {
15963               oappend ("(bad)");
15964               return;
15965             }
15966           names = names_mask;
15967           break;
15968         default:
15969           /* See PR binutils/20893 for a reproducer.  */
15970           oappend ("(bad)");
15971           return;
15972         }
15973       break;
15974     case 512:
15975       names = names_zmm;
15976       break;
15977     default:
15978       abort ();
15979       break;
15980     }
15981   oappend (names[reg]);
15982 }
15983
15984 /* Get the VEX immediate byte without moving codep.  */
15985
15986 static unsigned char
15987 get_vex_imm8 (int sizeflag, int opnum)
15988 {
15989   int bytes_before_imm = 0;
15990
15991   if (modrm.mod != 3)
15992     {
15993       /* There are SIB/displacement bytes.  */
15994       if ((sizeflag & AFLAG) || address_mode == mode_64bit)
15995         {
15996           /* 32/64 bit address mode */
15997           int base = modrm.rm;
15998
15999           /* Check SIB byte.  */
16000           if (base == 4)
16001             {
16002               FETCH_DATA (the_info, codep + 1);
16003               base = *codep & 7;
16004               /* When decoding the third source, don't increase
16005                  bytes_before_imm as this has already been incremented
16006                  by one in OP_E_memory while decoding the second
16007                  source operand.  */
16008               if (opnum == 0)
16009                 bytes_before_imm++;
16010             }
16011
16012           /* Don't increase bytes_before_imm when decoding the third source,
16013              it has already been incremented by OP_E_memory while decoding
16014              the second source operand.  */
16015           if (opnum == 0)
16016             {
16017               switch (modrm.mod)
16018                 {
16019                   case 0:
16020                     /* When modrm.rm == 5 or modrm.rm == 4 and base in
16021                        SIB == 5, there is a 4 byte displacement.  */
16022                     if (base != 5)
16023                       /* No displacement. */
16024                       break;
16025                     /* Fall through.  */
16026                   case 2:
16027                     /* 4 byte displacement.  */
16028                     bytes_before_imm += 4;
16029                     break;
16030                   case 1:
16031                     /* 1 byte displacement.  */
16032                     bytes_before_imm++;
16033                     break;
16034                 }
16035             }
16036         }
16037       else
16038         {
16039           /* 16 bit address mode */
16040           /* Don't increase bytes_before_imm when decoding the third source,
16041              it has already been incremented by OP_E_memory while decoding
16042              the second source operand.  */
16043           if (opnum == 0)
16044             {
16045               switch (modrm.mod)
16046                 {
16047                 case 0:
16048                   /* When modrm.rm == 6, there is a 2 byte displacement.  */
16049                   if (modrm.rm != 6)
16050                     /* No displacement. */
16051                     break;
16052                   /* Fall through.  */
16053                 case 2:
16054                   /* 2 byte displacement.  */
16055                   bytes_before_imm += 2;
16056                   break;
16057                 case 1:
16058                   /* 1 byte displacement: when decoding the third source,
16059                      don't increase bytes_before_imm as this has already
16060                      been incremented by one in OP_E_memory while decoding
16061                      the second source operand.  */
16062                   if (opnum == 0)
16063                     bytes_before_imm++;
16064
16065                   break;
16066                 }
16067             }
16068         }
16069     }
16070
16071   FETCH_DATA (the_info, codep + bytes_before_imm + 1);
16072   return codep [bytes_before_imm];
16073 }
16074
16075 static void
16076 OP_EX_VexReg (int bytemode, int sizeflag, int reg)
16077 {
16078   const char **names;
16079
16080   if (reg == -1 && modrm.mod != 3)
16081     {
16082       OP_E_memory (bytemode, sizeflag);
16083       return;
16084     }
16085   else
16086     {
16087       if (reg == -1)
16088         {
16089           reg = modrm.rm;
16090           USED_REX (REX_B);
16091           if (rex & REX_B)
16092             reg += 8;
16093         }
16094       if (address_mode != mode_64bit)
16095         reg &= 7;
16096     }
16097
16098   switch (vex.length)
16099     {
16100     case 128:
16101       names = names_xmm;
16102       break;
16103     case 256:
16104       names = names_ymm;
16105       break;
16106     default:
16107       abort ();
16108     }
16109   oappend (names[reg]);
16110 }
16111
16112 static void
16113 OP_EX_VexImmW (int bytemode, int sizeflag)
16114 {
16115   int reg = -1;
16116   static unsigned char vex_imm8;
16117
16118   if (vex_w_done == 0)
16119     {
16120       vex_w_done = 1;
16121
16122       /* Skip mod/rm byte.  */
16123       MODRM_CHECK;
16124       codep++;
16125
16126       vex_imm8 = get_vex_imm8 (sizeflag, 0);
16127
16128       if (vex.w)
16129           reg = vex_imm8 >> 4;
16130
16131       OP_EX_VexReg (bytemode, sizeflag, reg);
16132     }
16133   else if (vex_w_done == 1)
16134     {
16135       vex_w_done = 2;
16136
16137       if (!vex.w)
16138           reg = vex_imm8 >> 4;
16139
16140       OP_EX_VexReg (bytemode, sizeflag, reg);
16141     }
16142   else
16143     {
16144       /* Output the imm8 directly.  */
16145       scratchbuf[0] = '$';
16146       print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf);
16147       oappend_maybe_intel (scratchbuf);
16148       scratchbuf[0] = '\0';
16149       codep++;
16150     }
16151 }
16152
16153 static void
16154 OP_Vex_2src (int bytemode, int sizeflag)
16155 {
16156   if (modrm.mod == 3)
16157     {
16158       int reg = modrm.rm;
16159       USED_REX (REX_B);
16160       if (rex & REX_B)
16161         reg += 8;
16162       oappend (names_xmm[reg]);
16163     }
16164   else
16165     {
16166       if (intel_syntax
16167           && (bytemode == v_mode || bytemode == v_swap_mode))
16168         {
16169           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16170           used_prefixes |= (prefixes & PREFIX_DATA);
16171         }
16172       OP_E (bytemode, sizeflag);
16173     }
16174 }
16175
16176 static void
16177 OP_Vex_2src_1 (int bytemode, int sizeflag)
16178 {
16179   if (modrm.mod == 3)
16180     {
16181       /* Skip mod/rm byte.   */
16182       MODRM_CHECK;
16183       codep++;
16184     }
16185
16186   if (vex.w)
16187     {
16188       unsigned int reg = vex.register_specifier;
16189       vex.register_specifier = 0;
16190
16191       if (address_mode != mode_64bit)
16192         reg &= 7;
16193       oappend (names_xmm[reg]);
16194     }
16195   else
16196     OP_Vex_2src (bytemode, sizeflag);
16197 }
16198
16199 static void
16200 OP_Vex_2src_2 (int bytemode, int sizeflag)
16201 {
16202   if (vex.w)
16203     OP_Vex_2src (bytemode, sizeflag);
16204   else
16205     {
16206       unsigned int reg = vex.register_specifier;
16207       vex.register_specifier = 0;
16208
16209       if (address_mode != mode_64bit)
16210         reg &= 7;
16211       oappend (names_xmm[reg]);
16212     }
16213 }
16214
16215 static void
16216 OP_EX_VexW (int bytemode, int sizeflag)
16217 {
16218   int reg = -1;
16219
16220   if (!vex_w_done)
16221     {
16222       /* Skip mod/rm byte.  */
16223       MODRM_CHECK;
16224       codep++;
16225
16226       if (vex.w)
16227         reg = get_vex_imm8 (sizeflag, 0) >> 4;
16228     }
16229   else
16230     {
16231       if (!vex.w)
16232         reg = get_vex_imm8 (sizeflag, 1) >> 4;
16233     }
16234
16235   OP_EX_VexReg (bytemode, sizeflag, reg);
16236
16237   if (vex_w_done)
16238     codep++;
16239   vex_w_done = 1;
16240 }
16241
16242 static void
16243 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16244 {
16245   int reg;
16246   const char **names;
16247
16248   FETCH_DATA (the_info, codep + 1);
16249   reg = *codep++;
16250
16251   if (bytemode != x_mode)
16252     abort ();
16253
16254   reg >>= 4;
16255   if (address_mode != mode_64bit)
16256     reg &= 7;
16257
16258   switch (vex.length)
16259     {
16260     case 128:
16261       names = names_xmm;
16262       break;
16263     case 256:
16264       names = names_ymm;
16265       break;
16266     default:
16267       abort ();
16268     }
16269   oappend (names[reg]);
16270 }
16271
16272 static void
16273 OP_XMM_VexW (int bytemode, int sizeflag)
16274 {
16275   /* Turn off the REX.W bit since it is used for swapping operands
16276      now.  */
16277   rex &= ~REX_W;
16278   OP_XMM (bytemode, sizeflag);
16279 }
16280
16281 static void
16282 OP_EX_Vex (int bytemode, int sizeflag)
16283 {
16284   if (modrm.mod != 3)
16285     need_vex_reg = 0;
16286   OP_EX (bytemode, sizeflag);
16287 }
16288
16289 static void
16290 OP_XMM_Vex (int bytemode, int sizeflag)
16291 {
16292   if (modrm.mod != 3)
16293     need_vex_reg = 0;
16294   OP_XMM (bytemode, sizeflag);
16295 }
16296
16297 static struct op vex_cmp_op[] =
16298 {
16299   { STRING_COMMA_LEN ("eq") },
16300   { STRING_COMMA_LEN ("lt") },
16301   { STRING_COMMA_LEN ("le") },
16302   { STRING_COMMA_LEN ("unord") },
16303   { STRING_COMMA_LEN ("neq") },
16304   { STRING_COMMA_LEN ("nlt") },
16305   { STRING_COMMA_LEN ("nle") },
16306   { STRING_COMMA_LEN ("ord") },
16307   { STRING_COMMA_LEN ("eq_uq") },
16308   { STRING_COMMA_LEN ("nge") },
16309   { STRING_COMMA_LEN ("ngt") },
16310   { STRING_COMMA_LEN ("false") },
16311   { STRING_COMMA_LEN ("neq_oq") },
16312   { STRING_COMMA_LEN ("ge") },
16313   { STRING_COMMA_LEN ("gt") },
16314   { STRING_COMMA_LEN ("true") },
16315   { STRING_COMMA_LEN ("eq_os") },
16316   { STRING_COMMA_LEN ("lt_oq") },
16317   { STRING_COMMA_LEN ("le_oq") },
16318   { STRING_COMMA_LEN ("unord_s") },
16319   { STRING_COMMA_LEN ("neq_us") },
16320   { STRING_COMMA_LEN ("nlt_uq") },
16321   { STRING_COMMA_LEN ("nle_uq") },
16322   { STRING_COMMA_LEN ("ord_s") },
16323   { STRING_COMMA_LEN ("eq_us") },
16324   { STRING_COMMA_LEN ("nge_uq") },
16325   { STRING_COMMA_LEN ("ngt_uq") },
16326   { STRING_COMMA_LEN ("false_os") },
16327   { STRING_COMMA_LEN ("neq_os") },
16328   { STRING_COMMA_LEN ("ge_oq") },
16329   { STRING_COMMA_LEN ("gt_oq") },
16330   { STRING_COMMA_LEN ("true_us") },
16331 };
16332
16333 static void
16334 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16335 {
16336   unsigned int cmp_type;
16337
16338   FETCH_DATA (the_info, codep + 1);
16339   cmp_type = *codep++ & 0xff;
16340   if (cmp_type < ARRAY_SIZE (vex_cmp_op))
16341     {
16342       char suffix [3];
16343       char *p = mnemonicendp - 2;
16344       suffix[0] = p[0];
16345       suffix[1] = p[1];
16346       suffix[2] = '\0';
16347       sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
16348       mnemonicendp += vex_cmp_op[cmp_type].len;
16349     }
16350   else
16351     {
16352       /* We have a reserved extension byte.  Output it directly.  */
16353       scratchbuf[0] = '$';
16354       print_operand_value (scratchbuf + 1, 1, cmp_type);
16355       oappend_maybe_intel (scratchbuf);
16356       scratchbuf[0] = '\0';
16357     }
16358 }
16359
16360 static void
16361 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED,
16362              int sizeflag ATTRIBUTE_UNUSED)
16363 {
16364   unsigned int cmp_type;
16365
16366   if (!vex.evex)
16367     abort ();
16368
16369   FETCH_DATA (the_info, codep + 1);
16370   cmp_type = *codep++ & 0xff;
16371   /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
16372      If it's the case, print suffix, otherwise - print the immediate.  */
16373   if (cmp_type < ARRAY_SIZE (simd_cmp_op)
16374       && cmp_type != 3
16375       && cmp_type != 7)
16376     {
16377       char suffix [3];
16378       char *p = mnemonicendp - 2;
16379
16380       /* vpcmp* can have both one- and two-lettered suffix.  */
16381       if (p[0] == 'p')
16382         {
16383           p++;
16384           suffix[0] = p[0];
16385           suffix[1] = '\0';
16386         }
16387       else
16388         {
16389           suffix[0] = p[0];
16390           suffix[1] = p[1];
16391           suffix[2] = '\0';
16392         }
16393
16394       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
16395       mnemonicendp += simd_cmp_op[cmp_type].len;
16396     }
16397   else
16398     {
16399       /* We have a reserved extension byte.  Output it directly.  */
16400       scratchbuf[0] = '$';
16401       print_operand_value (scratchbuf + 1, 1, cmp_type);
16402       oappend_maybe_intel (scratchbuf);
16403       scratchbuf[0] = '\0';
16404     }
16405 }
16406
16407 static const struct op xop_cmp_op[] =
16408 {
16409   { STRING_COMMA_LEN ("lt") },
16410   { STRING_COMMA_LEN ("le") },
16411   { STRING_COMMA_LEN ("gt") },
16412   { STRING_COMMA_LEN ("ge") },
16413   { STRING_COMMA_LEN ("eq") },
16414   { STRING_COMMA_LEN ("neq") },
16415   { STRING_COMMA_LEN ("false") },
16416   { STRING_COMMA_LEN ("true") }
16417 };
16418
16419 static void
16420 VPCOM_Fixup (int bytemode ATTRIBUTE_UNUSED,
16421              int sizeflag ATTRIBUTE_UNUSED)
16422 {
16423   unsigned int cmp_type;
16424
16425   FETCH_DATA (the_info, codep + 1);
16426   cmp_type = *codep++ & 0xff;
16427   if (cmp_type < ARRAY_SIZE (xop_cmp_op))
16428     {
16429       char suffix[3];
16430       char *p = mnemonicendp - 2;
16431
16432       /* vpcom* can have both one- and two-lettered suffix.  */
16433       if (p[0] == 'm')
16434         {
16435           p++;
16436           suffix[0] = p[0];
16437           suffix[1] = '\0';
16438         }
16439       else
16440         {
16441           suffix[0] = p[0];
16442           suffix[1] = p[1];
16443           suffix[2] = '\0';
16444         }
16445
16446       sprintf (p, "%s%s", xop_cmp_op[cmp_type].name, suffix);
16447       mnemonicendp += xop_cmp_op[cmp_type].len;
16448     }
16449   else
16450     {
16451       /* We have a reserved extension byte.  Output it directly.  */
16452       scratchbuf[0] = '$';
16453       print_operand_value (scratchbuf + 1, 1, cmp_type);
16454       oappend_maybe_intel (scratchbuf);
16455       scratchbuf[0] = '\0';
16456     }
16457 }
16458
16459 static const struct op pclmul_op[] =
16460 {
16461   { STRING_COMMA_LEN ("lql") },
16462   { STRING_COMMA_LEN ("hql") },
16463   { STRING_COMMA_LEN ("lqh") },
16464   { STRING_COMMA_LEN ("hqh") }
16465 };
16466
16467 static void
16468 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
16469               int sizeflag ATTRIBUTE_UNUSED)
16470 {
16471   unsigned int pclmul_type;
16472
16473   FETCH_DATA (the_info, codep + 1);
16474   pclmul_type = *codep++ & 0xff;
16475   switch (pclmul_type)
16476     {
16477     case 0x10:
16478       pclmul_type = 2;
16479       break;
16480     case 0x11:
16481       pclmul_type = 3;
16482       break;
16483     default:
16484       break;
16485     }
16486   if (pclmul_type < ARRAY_SIZE (pclmul_op))
16487     {
16488       char suffix [4];
16489       char *p = mnemonicendp - 3;
16490       suffix[0] = p[0];
16491       suffix[1] = p[1];
16492       suffix[2] = p[2];
16493       suffix[3] = '\0';
16494       sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
16495       mnemonicendp += pclmul_op[pclmul_type].len;
16496     }
16497   else
16498     {
16499       /* We have a reserved extension byte.  Output it directly.  */
16500       scratchbuf[0] = '$';
16501       print_operand_value (scratchbuf + 1, 1, pclmul_type);
16502       oappend_maybe_intel (scratchbuf);
16503       scratchbuf[0] = '\0';
16504     }
16505 }
16506
16507 static void
16508 MOVBE_Fixup (int bytemode, int sizeflag)
16509 {
16510   /* Add proper suffix to "movbe".  */
16511   char *p = mnemonicendp;
16512
16513   switch (bytemode)
16514     {
16515     case v_mode:
16516       if (intel_syntax)
16517         goto skip;
16518
16519       USED_REX (REX_W);
16520       if (sizeflag & SUFFIX_ALWAYS)
16521         {
16522           if (rex & REX_W)
16523             *p++ = 'q';
16524           else
16525             {
16526               if (sizeflag & DFLAG)
16527                 *p++ = 'l';
16528               else
16529                 *p++ = 'w';
16530               used_prefixes |= (prefixes & PREFIX_DATA);
16531             }
16532         }
16533       break;
16534     default:
16535       oappend (INTERNAL_DISASSEMBLER_ERROR);
16536       break;
16537     }
16538   mnemonicendp = p;
16539   *p = '\0';
16540
16541  skip:
16542   OP_M (bytemode, sizeflag);
16543 }
16544
16545 static void
16546 MOVSXD_Fixup (int bytemode, int sizeflag)
16547 {
16548   /* Add proper suffix to "movsxd".  */
16549   char *p = mnemonicendp;
16550
16551   switch (bytemode)
16552     {
16553     case movsxd_mode:
16554       if (intel_syntax)
16555         {
16556           *p++ = 'x';
16557           *p++ = 'd';
16558           goto skip;
16559         }
16560
16561       USED_REX (REX_W);
16562       if (rex & REX_W)
16563         {
16564           *p++ = 'l';
16565           *p++ = 'q';
16566         }
16567       else
16568         {
16569           *p++ = 'x';
16570           *p++ = 'd';
16571         }
16572       break;
16573     default:
16574       oappend (INTERNAL_DISASSEMBLER_ERROR);
16575       break;
16576     }
16577
16578  skip:
16579   mnemonicendp = p;
16580   *p = '\0';
16581   OP_E (bytemode, sizeflag);
16582 }
16583
16584 static void
16585 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16586 {
16587   int reg;
16588   const char **names;
16589
16590   /* Skip mod/rm byte.  */
16591   MODRM_CHECK;
16592   codep++;
16593
16594   if (rex & REX_W)
16595     names = names64;
16596   else
16597     names = names32;
16598
16599   reg = modrm.rm;
16600   USED_REX (REX_B);
16601   if (rex & REX_B)
16602     reg += 8;
16603
16604   oappend (names[reg]);
16605 }
16606
16607 static void
16608 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16609 {
16610   const char **names;
16611   unsigned int reg = vex.register_specifier;
16612   vex.register_specifier = 0;
16613
16614   if (rex & REX_W)
16615     names = names64;
16616   else
16617     names = names32;
16618
16619   if (address_mode != mode_64bit)
16620     reg &= 7;
16621   oappend (names[reg]);
16622 }
16623
16624 static void
16625 OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16626 {
16627   if (!vex.evex
16628       || (bytemode != mask_mode && bytemode != mask_bd_mode))
16629     abort ();
16630
16631   USED_REX (REX_R);
16632   if ((rex & REX_R) != 0 || !vex.r)
16633     {
16634       BadOp ();
16635       return;
16636     }
16637
16638   oappend (names_mask [modrm.reg]);
16639 }
16640
16641 static void
16642 OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16643 {
16644   if (!vex.evex
16645       || (bytemode != evex_rounding_mode
16646           && bytemode != evex_rounding_64_mode
16647           && bytemode != evex_sae_mode))
16648     abort ();
16649   if (modrm.mod == 3 && vex.b)
16650     switch (bytemode)
16651       {
16652       case evex_rounding_64_mode:
16653         if (address_mode != mode_64bit)
16654           {
16655             oappend ("(bad)");
16656             break;
16657           }
16658         /* Fall through.  */
16659       case evex_rounding_mode:
16660         oappend (names_rounding[vex.ll]);
16661         break;
16662       case evex_sae_mode:
16663         oappend ("{sae}");
16664         break;
16665       default:
16666         break;
16667       }
16668 }