opcodes/i386-dis.c

   1 /* Print i386 instructions for GDB, the GNU debugger.
   2    Copyright (C) 1988-2020 Free Software Foundation, Inc.
   3
   4    This file is part of the GNU opcodes library.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    It is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program; if not, write to the Free Software
  18    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  19    MA 02110-1301, USA.  */
  20
  21
  22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
  23    July 1988
  24     modified by John Hassey (hassey@dg-rtp.dg.com)
  25     x86-64 support added by Jan Hubicka (jh@suse.cz)
  26     VIA PadLock support by Michal Ludvig (mludvig@suse.cz).  */
  27
  28 /* The main tables describing the instructions is essentially a copy
  29    of the "Opcode Map" chapter (Appendix A) of the Intel 80386
  30    Programmers Manual.  Usually, there is a capital letter, followed
  31    by a small letter.  The capital letter tell the addressing mode,
  32    and the small letter tells about the operand size.  Refer to
  33    the Intel manual for details.  */
  34
  35 #include "sysdep.h"
  36 #include "disassemble.h"
  37 #include "opintl.h"
  38 #include "opcode/i386.h"
  39 #include "libiberty.h"
  40 #include "safe-ctype.h"
  41
  42 #include <setjmp.h>
  43
  44 static int print_insn (bfd_vma, disassemble_info *);
  45 static void dofloat (int);
  46 static void OP_ST (int, int);
  47 static void OP_STi (int, int);
  48 static int putop (const char *, int);
  49 static void oappend (const char *);
  50 static void append_seg (void);
  51 static void OP_indirE (int, int);
  52 static void print_operand_value (char *, int, bfd_vma);
  53 static void OP_E_register (int, int);
  54 static void OP_E_memory (int, int);
  55 static void print_displacement (char *, bfd_vma);
  56 static void OP_E (int, int);
  57 static void OP_G (int, int);
  58 static bfd_vma get64 (void);
  59 static bfd_signed_vma get32 (void);
  60 static bfd_signed_vma get32s (void);
  61 static int get16 (void);
  62 static void set_op (bfd_vma, int);
  63 static void OP_Skip_MODRM (int, int);
  64 static void OP_REG (int, int);
  65 static void OP_IMREG (int, int);
  66 static void OP_I (int, int);
  67 static void OP_I64 (int, int);
  68 static void OP_sI (int, int);
  69 static void OP_J (int, int);
  70 static void OP_SEG (int, int);
  71 static void OP_DIR (int, int);
  72 static void OP_OFF (int, int);
  73 static void OP_OFF64 (int, int);
  74 static void ptr_reg (int, int);
  75 static void OP_ESreg (int, int);
  76 static void OP_DSreg (int, int);
  77 static void OP_C (int, int);
  78 static void OP_D (int, int);
  79 static void OP_T (int, int);
  80 static void OP_R (int, int);
  81 static void OP_MMX (int, int);
  82 static void OP_XMM (int, int);
  83 static void OP_EM (int, int);
  84 static void OP_EX (int, int);
  85 static void OP_EMC (int,int);
  86 static void OP_MXC (int,int);
  87 static void OP_MS (int, int);
  88 static void OP_XS (int, int);
  89 static void OP_M (int, int);
  90 static void OP_VEX (int, int);
  91 static void OP_EX_Vex (int, int);
  92 static void OP_EX_VexW (int, int);
  93 static void OP_EX_VexImmW (int, int);
  94 static void OP_XMM_Vex (int, int);
  95 static void OP_XMM_VexW (int, int);
  96 static void OP_Rounding (int, int);
  97 static void OP_REG_VexI4 (int, int);
  98 static void PCLMUL_Fixup (int, int);
  99 static void VCMP_Fixup (int, int);
 100 static void VPCMP_Fixup (int, int);
 101 static void VPCOM_Fixup (int, int);
 102 static void OP_0f07 (int, int);
 103 static void OP_Monitor (int, int);
 104 static void OP_Mwait (int, int);
 105 static void NOP_Fixup1 (int, int);
 106 static void NOP_Fixup2 (int, int);
 107 static void OP_3DNowSuffix (int, int);
 108 static void CMP_Fixup (int, int);
 109 static void BadOp (void);
 110 static void REP_Fixup (int, int);
 111 static void SEP_Fixup (int, int);
 112 static void BND_Fixup (int, int);
 113 static void NOTRACK_Fixup (int, int);
 114 static void HLE_Fixup1 (int, int);
 115 static void HLE_Fixup2 (int, int);
 116 static void HLE_Fixup3 (int, int);
 117 static void CMPXCHG8B_Fixup (int, int);
 118 static void XMM_Fixup (int, int);
 119 static void CRC32_Fixup (int, int);
 120 static void FXSAVE_Fixup (int, int);
 121 static void PCMPESTR_Fixup (int, int);
 122 static void OP_LWPCB_E (int, int);
 123 static void OP_LWP_E (int, int);
 124 static void OP_Vex_2src_1 (int, int);
 125 static void OP_Vex_2src_2 (int, int);
 126
 127 static void MOVBE_Fixup (int, int);
 128 static void MOVSXD_Fixup (int, int);
 129
 130 static void OP_Mask (int, int);
 131
 132 struct dis_private {
 133   /* Points to first byte not fetched.  */
 134   bfd_byte *max_fetched;
 135   bfd_byte the_buffer[MAX_MNEM_SIZE];
 136   bfd_vma insn_start;
 137   int orig_sizeflag;
 138   OPCODES_SIGJMP_BUF bailout;
 139 };
 140
 141 enum address_mode
 142 {
 143   mode_16bit,
 144   mode_32bit,
 145   mode_64bit
 146 };
 147
 148 enum address_mode address_mode;
 149
 150 /* Flags for the prefixes for the current instruction.  See below.  */
 151 static int prefixes;
 152
 153 /* REX prefix the current instruction.  See below.  */
 154 static int rex;
 155 /* Bits of REX we've already used.  */
 156 static int rex_used;
 157 /* Mark parts used in the REX prefix.  When we are testing for
 158    empty prefix (for 8bit register REX extension), just mask it
 159    out.  Otherwise test for REX bit is excuse for existence of REX
 160    only in case value is nonzero.  */
 161 #define USED_REX(value)                                 \
 162   {                                                     \
 163     if (value)                                          \
 164       {                                                 \
 165         if ((rex & value))                              \
 166           rex_used |= (value) | REX_OPCODE;             \
 167       }                                                 \
 168     else                                                \
 169       rex_used |= REX_OPCODE;                           \
 170   }
 171
 172 /* Flags for prefixes which we somehow handled when printing the
 173    current instruction.  */
 174 static int used_prefixes;
 175
 176 /* Flags stored in PREFIXES.  */
 177 #define PREFIX_REPZ 1
 178 #define PREFIX_REPNZ 2
 179 #define PREFIX_LOCK 4
 180 #define PREFIX_CS 8
 181 #define PREFIX_SS 0x10
 182 #define PREFIX_DS 0x20
 183 #define PREFIX_ES 0x40
 184 #define PREFIX_FS 0x80
 185 #define PREFIX_GS 0x100
 186 #define PREFIX_DATA 0x200
 187 #define PREFIX_ADDR 0x400
 188 #define PREFIX_FWAIT 0x800
 189
 190 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
 191    to ADDR (exclusive) are valid.  Returns 1 for success, longjmps
 192    on error.  */
 193 #define FETCH_DATA(info, addr) \
 194   ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
 195    ? 1 : fetch_data ((info), (addr)))
 196
 197 static int
 198 fetch_data (struct disassemble_info *info, bfd_byte *addr)
 199 {
 200   int status;
 201   struct dis_private *priv = (struct dis_private *) info->private_data;
 202   bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
 203
 204   if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
 205     status = (*info->read_memory_func) (start,
 206                                         priv->max_fetched,
 207                                         addr - priv->max_fetched,
 208                                         info);
 209   else
 210     status = -1;
 211   if (status != 0)
 212     {
 213       /* If we did manage to read at least one byte, then
 214          print_insn_i386 will do something sensible.  Otherwise, print
 215          an error.  We do that here because this is where we know
 216          STATUS.  */
 217       if (priv->max_fetched == priv->the_buffer)
 218         (*info->memory_error_func) (status, start, info);
 219       OPCODES_SIGLONGJMP (priv->bailout, 1);
 220     }
 221   else
 222     priv->max_fetched = addr;
 223   return 1;
 224 }
 225
 226 /* Possible values for prefix requirement.  */
 227 #define PREFIX_IGNORED_SHIFT    16
 228 #define PREFIX_IGNORED_REPZ     (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
 229 #define PREFIX_IGNORED_REPNZ    (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
 230 #define PREFIX_IGNORED_DATA     (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
 231 #define PREFIX_IGNORED_ADDR     (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
 232 #define PREFIX_IGNORED_LOCK     (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
 233
 234 /* Opcode prefixes.  */
 235 #define PREFIX_OPCODE           (PREFIX_REPZ \
 236                                  | PREFIX_REPNZ \
 237                                  | PREFIX_DATA)
 238
 239 /* Prefixes ignored.  */
 240 #define PREFIX_IGNORED          (PREFIX_IGNORED_REPZ \
 241                                  | PREFIX_IGNORED_REPNZ \
 242                                  | PREFIX_IGNORED_DATA)
 243
 244 #define XX { NULL, 0 }
 245 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
 246
 247 #define Eb { OP_E, b_mode }
 248 #define Ebnd { OP_E, bnd_mode }
 249 #define EbS { OP_E, b_swap_mode }
 250 #define EbndS { OP_E, bnd_swap_mode }
 251 #define Ev { OP_E, v_mode }
 252 #define Eva { OP_E, va_mode }
 253 #define Ev_bnd { OP_E, v_bnd_mode }
 254 #define EvS { OP_E, v_swap_mode }
 255 #define Ed { OP_E, d_mode }
 256 #define Edq { OP_E, dq_mode }
 257 #define Edqw { OP_E, dqw_mode }
 258 #define Edqb { OP_E, dqb_mode }
 259 #define Edb { OP_E, db_mode }
 260 #define Edw { OP_E, dw_mode }
 261 #define Edqd { OP_E, dqd_mode }
 262 #define Eq { OP_E, q_mode }
 263 #define indirEv { OP_indirE, indir_v_mode }
 264 #define indirEp { OP_indirE, f_mode }
 265 #define stackEv { OP_E, stack_v_mode }
 266 #define Em { OP_E, m_mode }
 267 #define Ew { OP_E, w_mode }
 268 #define M { OP_M, 0 }           /* lea, lgdt, etc. */
 269 #define Ma { OP_M, a_mode }
 270 #define Mb { OP_M, b_mode }
 271 #define Md { OP_M, d_mode }
 272 #define Mo { OP_M, o_mode }
 273 #define Mp { OP_M, f_mode }             /* 32 or 48 bit memory operand for LDS, LES etc */
 274 #define Mq { OP_M, q_mode }
 275 #define Mv_bnd { OP_M, v_bndmk_mode }
 276 #define Mx { OP_M, x_mode }
 277 #define Mxmm { OP_M, xmm_mode }
 278 #define Gb { OP_G, b_mode }
 279 #define Gbnd { OP_G, bnd_mode }
 280 #define Gv { OP_G, v_mode }
 281 #define Gd { OP_G, d_mode }
 282 #define Gdq { OP_G, dq_mode }
 283 #define Gm { OP_G, m_mode }
 284 #define Gva { OP_G, va_mode }
 285 #define Gw { OP_G, w_mode }
 286 #define Rd { OP_R, d_mode }
 287 #define Rdq { OP_R, dq_mode }
 288 #define Rm { OP_R, m_mode }
 289 #define Ib { OP_I, b_mode }
 290 #define sIb { OP_sI, b_mode }   /* sign extened byte */
 291 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
 292 #define Iv { OP_I, v_mode }
 293 #define sIv { OP_sI, v_mode }
 294 #define Iv64 { OP_I64, v_mode }
 295 #define Id { OP_I, d_mode }
 296 #define Iw { OP_I, w_mode }
 297 #define I1 { OP_I, const_1_mode }
 298 #define Jb { OP_J, b_mode }
 299 #define Jv { OP_J, v_mode }
 300 #define Jdqw { OP_J, dqw_mode }
 301 #define Cm { OP_C, m_mode }
 302 #define Dm { OP_D, m_mode }
 303 #define Td { OP_T, d_mode }
 304 #define Skip_MODRM { OP_Skip_MODRM, 0 }
 305
 306 #define RMeAX { OP_REG, eAX_reg }
 307 #define RMeBX { OP_REG, eBX_reg }
 308 #define RMeCX { OP_REG, eCX_reg }
 309 #define RMeDX { OP_REG, eDX_reg }
 310 #define RMeSP { OP_REG, eSP_reg }
 311 #define RMeBP { OP_REG, eBP_reg }
 312 #define RMeSI { OP_REG, eSI_reg }
 313 #define RMeDI { OP_REG, eDI_reg }
 314 #define RMrAX { OP_REG, rAX_reg }
 315 #define RMrBX { OP_REG, rBX_reg }
 316 #define RMrCX { OP_REG, rCX_reg }
 317 #define RMrDX { OP_REG, rDX_reg }
 318 #define RMrSP { OP_REG, rSP_reg }
 319 #define RMrBP { OP_REG, rBP_reg }
 320 #define RMrSI { OP_REG, rSI_reg }
 321 #define RMrDI { OP_REG, rDI_reg }
 322 #define RMAL { OP_REG, al_reg }
 323 #define RMCL { OP_REG, cl_reg }
 324 #define RMDL { OP_REG, dl_reg }
 325 #define RMBL { OP_REG, bl_reg }
 326 #define RMAH { OP_REG, ah_reg }
 327 #define RMCH { OP_REG, ch_reg }
 328 #define RMDH { OP_REG, dh_reg }
 329 #define RMBH { OP_REG, bh_reg }
 330 #define RMAX { OP_REG, ax_reg }
 331 #define RMDX { OP_REG, dx_reg }
 332
 333 #define eAX { OP_IMREG, eAX_reg }
 334 #define eBX { OP_IMREG, eBX_reg }
 335 #define eCX { OP_IMREG, eCX_reg }
 336 #define eDX { OP_IMREG, eDX_reg }
 337 #define eSP { OP_IMREG, eSP_reg }
 338 #define eBP { OP_IMREG, eBP_reg }
 339 #define eSI { OP_IMREG, eSI_reg }
 340 #define eDI { OP_IMREG, eDI_reg }
 341 #define AL { OP_IMREG, al_reg }
 342 #define CL { OP_IMREG, cl_reg }
 343 #define DL { OP_IMREG, dl_reg }
 344 #define BL { OP_IMREG, bl_reg }
 345 #define AH { OP_IMREG, ah_reg }
 346 #define CH { OP_IMREG, ch_reg }
 347 #define DH { OP_IMREG, dh_reg }
 348 #define BH { OP_IMREG, bh_reg }
 349 #define AX { OP_IMREG, ax_reg }
 350 #define DX { OP_IMREG, dx_reg }
 351 #define zAX { OP_IMREG, z_mode_ax_reg }
 352 #define indirDX { OP_IMREG, indir_dx_reg }
 353
 354 #define Sw { OP_SEG, w_mode }
 355 #define Sv { OP_SEG, v_mode }
 356 #define Ap { OP_DIR, 0 }
 357 #define Ob { OP_OFF64, b_mode }
 358 #define Ov { OP_OFF64, v_mode }
 359 #define Xb { OP_DSreg, eSI_reg }
 360 #define Xv { OP_DSreg, eSI_reg }
 361 #define Xz { OP_DSreg, eSI_reg }
 362 #define Yb { OP_ESreg, eDI_reg }
 363 #define Yv { OP_ESreg, eDI_reg }
 364 #define DSBX { OP_DSreg, eBX_reg }
 365
 366 #define es { OP_REG, es_reg }
 367 #define ss { OP_REG, ss_reg }
 368 #define cs { OP_REG, cs_reg }
 369 #define ds { OP_REG, ds_reg }
 370 #define fs { OP_REG, fs_reg }
 371 #define gs { OP_REG, gs_reg }
 372
 373 #define MX { OP_MMX, 0 }
 374 #define XM { OP_XMM, 0 }
 375 #define XMScalar { OP_XMM, scalar_mode }
 376 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
 377 #define XMM { OP_XMM, xmm_mode }
 378 #define XMxmmq { OP_XMM, xmmq_mode }
 379 #define EM { OP_EM, v_mode }
 380 #define EMS { OP_EM, v_swap_mode }
 381 #define EMd { OP_EM, d_mode }
 382 #define EMx { OP_EM, x_mode }
 383 #define EXbScalar { OP_EX, b_scalar_mode }
 384 #define EXw { OP_EX, w_mode }
 385 #define EXwScalar { OP_EX, w_scalar_mode }
 386 #define EXd { OP_EX, d_mode }
 387 #define EXdS { OP_EX, d_swap_mode }
 388 #define EXq { OP_EX, q_mode }
 389 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
 390 #define EXqS { OP_EX, q_swap_mode }
 391 #define EXx { OP_EX, x_mode }
 392 #define EXxS { OP_EX, x_swap_mode }
 393 #define EXxmm { OP_EX, xmm_mode }
 394 #define EXymm { OP_EX, ymm_mode }
 395 #define EXxmmq { OP_EX, xmmq_mode }
 396 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
 397 #define EXxmm_mb { OP_EX, xmm_mb_mode }
 398 #define EXxmm_mw { OP_EX, xmm_mw_mode }
 399 #define EXxmm_md { OP_EX, xmm_md_mode }
 400 #define EXxmm_mq { OP_EX, xmm_mq_mode }
 401 #define EXxmmdw { OP_EX, xmmdw_mode }
 402 #define EXxmmqd { OP_EX, xmmqd_mode }
 403 #define EXymmq { OP_EX, ymmq_mode }
 404 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
 405 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
 406 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
 407 #define MS { OP_MS, v_mode }
 408 #define XS { OP_XS, v_mode }
 409 #define EMCq { OP_EMC, q_mode }
 410 #define MXC { OP_MXC, 0 }
 411 #define OPSUF { OP_3DNowSuffix, 0 }
 412 #define SEP { SEP_Fixup, 0 }
 413 #define CMP { CMP_Fixup, 0 }
 414 #define XMM0 { XMM_Fixup, 0 }
 415 #define FXSAVE { FXSAVE_Fixup, 0 }
 416 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
 417 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
 418
 419 #define Vex { OP_VEX, vex_mode }
 420 #define VexScalar { OP_VEX, vex_scalar_mode }
 421 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
 422 #define Vex128 { OP_VEX, vex128_mode }
 423 #define Vex256 { OP_VEX, vex256_mode }
 424 #define VexGdq { OP_VEX, dq_mode }
 425 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
 426 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
 427 #define EXVexW { OP_EX_VexW, x_mode }
 428 #define EXdVexW { OP_EX_VexW, d_mode }
 429 #define EXqVexW { OP_EX_VexW, q_mode }
 430 #define EXVexImmW { OP_EX_VexImmW, x_mode }
 431 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
 432 #define XMVexW { OP_XMM_VexW, 0 }
 433 #define XMVexI4 { OP_REG_VexI4, x_mode }
 434 #define PCLMUL { PCLMUL_Fixup, 0 }
 435 #define VCMP { VCMP_Fixup, 0 }
 436 #define VPCMP { VPCMP_Fixup, 0 }
 437 #define VPCOM { VPCOM_Fixup, 0 }
 438
 439 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
 440 #define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode }
 441 #define EXxEVexS { OP_Rounding, evex_sae_mode }
 442
 443 #define XMask { OP_Mask, mask_mode }
 444 #define MaskG { OP_G, mask_mode }
 445 #define MaskE { OP_E, mask_mode }
 446 #define MaskBDE { OP_E, mask_bd_mode }
 447 #define MaskR { OP_R, mask_mode }
 448 #define MaskVex { OP_VEX, mask_mode }
 449
 450 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
 451 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
 452 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
 453 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
 454
 455 /* Used handle "rep" prefix for string instructions.  */
 456 #define Xbr { REP_Fixup, eSI_reg }
 457 #define Xvr { REP_Fixup, eSI_reg }
 458 #define Ybr { REP_Fixup, eDI_reg }
 459 #define Yvr { REP_Fixup, eDI_reg }
 460 #define Yzr { REP_Fixup, eDI_reg }
 461 #define indirDXr { REP_Fixup, indir_dx_reg }
 462 #define ALr { REP_Fixup, al_reg }
 463 #define eAXr { REP_Fixup, eAX_reg }
 464
 465 /* Used handle HLE prefix for lockable instructions.  */
 466 #define Ebh1 { HLE_Fixup1, b_mode }
 467 #define Evh1 { HLE_Fixup1, v_mode }
 468 #define Ebh2 { HLE_Fixup2, b_mode }
 469 #define Evh2 { HLE_Fixup2, v_mode }
 470 #define Ebh3 { HLE_Fixup3, b_mode }
 471 #define Evh3 { HLE_Fixup3, v_mode }
 472
 473 #define BND { BND_Fixup, 0 }
 474 #define NOTRACK { NOTRACK_Fixup, 0 }
 475
 476 #define cond_jump_flag { NULL, cond_jump_mode }
 477 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
 478
 479 /* bits in sizeflag */
 480 #define SUFFIX_ALWAYS 4
 481 #define AFLAG 2
 482 #define DFLAG 1
 483
 484 enum
 485 {
 486   /* byte operand */
 487   b_mode = 1,
 488   /* byte operand with operand swapped */
 489   b_swap_mode,
 490   /* byte operand, sign extend like 'T' suffix */
 491   b_T_mode,
 492   /* operand size depends on prefixes */
 493   v_mode,
 494   /* operand size depends on prefixes with operand swapped */
 495   v_swap_mode,
 496   /* operand size depends on address prefix */
 497   va_mode,
 498   /* word operand */
 499   w_mode,
 500   /* double word operand  */
 501   d_mode,
 502   /* double word operand with operand swapped */
 503   d_swap_mode,
 504   /* quad word operand */
 505   q_mode,
 506   /* quad word operand with operand swapped */
 507   q_swap_mode,
 508   /* ten-byte operand */
 509   t_mode,
 510   /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand.  In EVEX with
 511      broadcast enabled.  */
 512   x_mode,
 513   /* Similar to x_mode, but with different EVEX mem shifts.  */
 514   evex_x_gscat_mode,
 515   /* Similar to x_mode, but with disabled broadcast.  */
 516   evex_x_nobcst_mode,
 517   /* Similar to x_mode, but with operands swapped and disabled broadcast
 518      in EVEX.  */
 519   x_swap_mode,
 520   /* 16-byte XMM operand */
 521   xmm_mode,
 522   /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
 523      memory operand (depending on vector length).  Broadcast isn't
 524      allowed.  */
 525   xmmq_mode,
 526   /* Same as xmmq_mode, but broadcast is allowed.  */
 527   evex_half_bcst_xmmq_mode,
 528   /* XMM register or byte memory operand */
 529   xmm_mb_mode,
 530   /* XMM register or word memory operand */
 531   xmm_mw_mode,
 532   /* XMM register or double word memory operand */
 533   xmm_md_mode,
 534   /* XMM register or quad word memory operand */
 535   xmm_mq_mode,
 536   /* 16-byte XMM, word, double word or quad word operand.  */
 537   xmmdw_mode,
 538   /* 16-byte XMM, double word, quad word operand or xmm word operand.  */
 539   xmmqd_mode,
 540   /* 32-byte YMM operand */
 541   ymm_mode,
 542   /* quad word, ymmword or zmmword memory operand.  */
 543   ymmq_mode,
 544   /* 32-byte YMM or 16-byte word operand */
 545   ymmxmm_mode,
 546   /* d_mode in 32bit, q_mode in 64bit mode.  */
 547   m_mode,
 548   /* pair of v_mode operands */
 549   a_mode,
 550   cond_jump_mode,
 551   loop_jcxz_mode,
 552   movsxd_mode,
 553   v_bnd_mode,
 554   /* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode.  */
 555   v_bndmk_mode,
 556   /* operand size depends on REX prefixes.  */
 557   dq_mode,
 558   /* registers like dq_mode, memory like w_mode, displacements like
 559      v_mode without considering Intel64 ISA.  */
 560   dqw_mode,
 561   /* bounds operand */
 562   bnd_mode,
 563   /* bounds operand with operand swapped */
 564   bnd_swap_mode,
 565   /* 4- or 6-byte pointer operand */
 566   f_mode,
 567   const_1_mode,
 568   /* v_mode for indirect branch opcodes.  */
 569   indir_v_mode,
 570   /* v_mode for stack-related opcodes.  */
 571   stack_v_mode,
 572   /* non-quad operand size depends on prefixes */
 573   z_mode,
 574   /* 16-byte operand */
 575   o_mode,
 576   /* registers like dq_mode, memory like b_mode.  */
 577   dqb_mode,
 578   /* registers like d_mode, memory like b_mode.  */
 579   db_mode,
 580   /* registers like d_mode, memory like w_mode.  */
 581   dw_mode,
 582   /* registers like dq_mode, memory like d_mode.  */
 583   dqd_mode,
 584   /* normal vex mode */
 585   vex_mode,
 586   /* 128bit vex mode */
 587   vex128_mode,
 588   /* 256bit vex mode */
 589   vex256_mode,
 590
 591   /* Operand size depends on the VEX.W bit, with VSIB dword indices.  */
 592   vex_vsib_d_w_dq_mode,
 593   /* Similar to vex_vsib_d_w_dq_mode, with smaller memory.  */
 594   vex_vsib_d_w_d_mode,
 595   /* Operand size depends on the VEX.W bit, with VSIB qword indices.  */
 596   vex_vsib_q_w_dq_mode,
 597   /* Similar to vex_vsib_q_w_dq_mode, with smaller memory.  */
 598   vex_vsib_q_w_d_mode,
 599
 600   /* scalar, ignore vector length.  */
 601   scalar_mode,
 602   /* like b_mode, ignore vector length.  */
 603   b_scalar_mode,
 604   /* like w_mode, ignore vector length.  */
 605   w_scalar_mode,
 606   /* like d_swap_mode, ignore vector length.  */
 607   d_scalar_swap_mode,
 608   /* like q_swap_mode, ignore vector length.  */
 609   q_scalar_swap_mode,
 610   /* like vex_mode, ignore vector length.  */
 611   vex_scalar_mode,
 612   /* Operand size depends on the VEX.W bit, ignore vector length.  */
 613   vex_scalar_w_dq_mode,
 614
 615   /* Static rounding.  */
 616   evex_rounding_mode,
 617   /* Static rounding, 64-bit mode only.  */
 618   evex_rounding_64_mode,
 619   /* Supress all exceptions.  */
 620   evex_sae_mode,
 621
 622   /* Mask register operand.  */
 623   mask_mode,
 624   /* Mask register operand.  */
 625   mask_bd_mode,
 626
 627   es_reg,
 628   cs_reg,
 629   ss_reg,
 630   ds_reg,
 631   fs_reg,
 632   gs_reg,
 633
 634   eAX_reg,
 635   eCX_reg,
 636   eDX_reg,
 637   eBX_reg,
 638   eSP_reg,
 639   eBP_reg,
 640   eSI_reg,
 641   eDI_reg,
 642
 643   al_reg,
 644   cl_reg,
 645   dl_reg,
 646   bl_reg,
 647   ah_reg,
 648   ch_reg,
 649   dh_reg,
 650   bh_reg,
 651
 652   ax_reg,
 653   cx_reg,
 654   dx_reg,
 655   bx_reg,
 656   sp_reg,
 657   bp_reg,
 658   si_reg,
 659   di_reg,
 660
 661   rAX_reg,
 662   rCX_reg,
 663   rDX_reg,
 664   rBX_reg,
 665   rSP_reg,
 666   rBP_reg,
 667   rSI_reg,
 668   rDI_reg,
 669
 670   z_mode_ax_reg,
 671   indir_dx_reg
 672 };
 673
 674 enum
 675 {
 676   FLOATCODE = 1,
 677   USE_REG_TABLE,
 678   USE_MOD_TABLE,
 679   USE_RM_TABLE,
 680   USE_PREFIX_TABLE,
 681   USE_X86_64_TABLE,
 682   USE_3BYTE_TABLE,
 683   USE_XOP_8F_TABLE,
 684   USE_VEX_C4_TABLE,
 685   USE_VEX_C5_TABLE,
 686   USE_VEX_LEN_TABLE,
 687   USE_VEX_W_TABLE,
 688   USE_EVEX_TABLE,
 689   USE_EVEX_LEN_TABLE
 690 };
 691
 692 #define FLOAT                   NULL, { { NULL, FLOATCODE } }, 0
 693
 694 #define DIS386(T, I)            NULL, { { NULL, (T)}, { NULL,  (I) } }, 0
 695 #define DIS386_PREFIX(T, I, P)          NULL, { { NULL, (T)}, { NULL,  (I) } }, P
 696 #define REG_TABLE(I)            DIS386 (USE_REG_TABLE, (I))
 697 #define MOD_TABLE(I)            DIS386 (USE_MOD_TABLE, (I))
 698 #define RM_TABLE(I)             DIS386 (USE_RM_TABLE, (I))
 699 #define PREFIX_TABLE(I)         DIS386 (USE_PREFIX_TABLE, (I))
 700 #define X86_64_TABLE(I)         DIS386 (USE_X86_64_TABLE, (I))
 701 #define THREE_BYTE_TABLE(I)     DIS386 (USE_3BYTE_TABLE, (I))
 702 #define THREE_BYTE_TABLE_PREFIX(I, P)   DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
 703 #define XOP_8F_TABLE(I)         DIS386 (USE_XOP_8F_TABLE, (I))
 704 #define VEX_C4_TABLE(I)         DIS386 (USE_VEX_C4_TABLE, (I))
 705 #define VEX_C5_TABLE(I)         DIS386 (USE_VEX_C5_TABLE, (I))
 706 #define VEX_LEN_TABLE(I)        DIS386 (USE_VEX_LEN_TABLE, (I))
 707 #define VEX_W_TABLE(I)          DIS386 (USE_VEX_W_TABLE, (I))
 708 #define EVEX_TABLE(I)           DIS386 (USE_EVEX_TABLE, (I))
 709 #define EVEX_LEN_TABLE(I)       DIS386 (USE_EVEX_LEN_TABLE, (I))
 710
 711 enum
 712 {
 713   REG_80 = 0,
 714   REG_81,
 715   REG_83,
 716   REG_8F,
 717   REG_C0,
 718   REG_C1,
 719   REG_C6,
 720   REG_C7,
 721   REG_D0,
 722   REG_D1,
 723   REG_D2,
 724   REG_D3,
 725   REG_F6,
 726   REG_F7,
 727   REG_FE,
 728   REG_FF,
 729   REG_0F00,
 730   REG_0F01,
 731   REG_0F0D,
 732   REG_0F18,
 733   REG_0F1C_P_0_MOD_0,
 734   REG_0F1E_P_1_MOD_3,
 735   REG_0F71,
 736   REG_0F72,
 737   REG_0F73,
 738   REG_0FA6,
 739   REG_0FA7,
 740   REG_0FAE,
 741   REG_0FBA,
 742   REG_0FC7,
 743   REG_VEX_0F71,
 744   REG_VEX_0F72,
 745   REG_VEX_0F73,
 746   REG_VEX_0FAE,
 747   REG_VEX_0F38F3,
 748   REG_XOP_LWPCB,
 749   REG_XOP_LWP,
 750   REG_XOP_TBM_01,
 751   REG_XOP_TBM_02,
 752
 753   REG_EVEX_0F71,
 754   REG_EVEX_0F72,
 755   REG_EVEX_0F73,
 756   REG_EVEX_0F38C6,
 757   REG_EVEX_0F38C7
 758 };
 759
 760 enum
 761 {
 762   MOD_8D = 0,
 763   MOD_C6_REG_7,
 764   MOD_C7_REG_7,
 765   MOD_FF_REG_3,
 766   MOD_FF_REG_5,
 767   MOD_0F01_REG_0,
 768   MOD_0F01_REG_1,
 769   MOD_0F01_REG_2,
 770   MOD_0F01_REG_3,
 771   MOD_0F01_REG_5,
 772   MOD_0F01_REG_7,
 773   MOD_0F12_PREFIX_0,
 774   MOD_0F12_PREFIX_2,
 775   MOD_0F13,
 776   MOD_0F16_PREFIX_0,
 777   MOD_0F16_PREFIX_2,
 778   MOD_0F17,
 779   MOD_0F18_REG_0,
 780   MOD_0F18_REG_1,
 781   MOD_0F18_REG_2,
 782   MOD_0F18_REG_3,
 783   MOD_0F18_REG_4,
 784   MOD_0F18_REG_5,
 785   MOD_0F18_REG_6,
 786   MOD_0F18_REG_7,
 787   MOD_0F1A_PREFIX_0,
 788   MOD_0F1B_PREFIX_0,
 789   MOD_0F1B_PREFIX_1,
 790   MOD_0F1C_PREFIX_0,
 791   MOD_0F1E_PREFIX_1,
 792   MOD_0F24,
 793   MOD_0F26,
 794   MOD_0F2B_PREFIX_0,
 795   MOD_0F2B_PREFIX_1,
 796   MOD_0F2B_PREFIX_2,
 797   MOD_0F2B_PREFIX_3,
 798   MOD_0F50,
 799   MOD_0F71_REG_2,
 800   MOD_0F71_REG_4,
 801   MOD_0F71_REG_6,
 802   MOD_0F72_REG_2,
 803   MOD_0F72_REG_4,
 804   MOD_0F72_REG_6,
 805   MOD_0F73_REG_2,
 806   MOD_0F73_REG_3,
 807   MOD_0F73_REG_6,
 808   MOD_0F73_REG_7,
 809   MOD_0FAE_REG_0,
 810   MOD_0FAE_REG_1,
 811   MOD_0FAE_REG_2,
 812   MOD_0FAE_REG_3,
 813   MOD_0FAE_REG_4,
 814   MOD_0FAE_REG_5,
 815   MOD_0FAE_REG_6,
 816   MOD_0FAE_REG_7,
 817   MOD_0FB2,
 818   MOD_0FB4,
 819   MOD_0FB5,
 820   MOD_0FC3,
 821   MOD_0FC7_REG_3,
 822   MOD_0FC7_REG_4,
 823   MOD_0FC7_REG_5,
 824   MOD_0FC7_REG_6,
 825   MOD_0FC7_REG_7,
 826   MOD_0FD7,
 827   MOD_0FE7_PREFIX_2,
 828   MOD_0FF0_PREFIX_3,
 829   MOD_0F382A_PREFIX_2,
 830   MOD_0F38F5_PREFIX_2,
 831   MOD_0F38F6_PREFIX_0,
 832   MOD_0F38F8_PREFIX_1,
 833   MOD_0F38F8_PREFIX_2,
 834   MOD_0F38F8_PREFIX_3,
 835   MOD_0F38F9_PREFIX_0,
 836   MOD_62_32BIT,
 837   MOD_C4_32BIT,
 838   MOD_C5_32BIT,
 839   MOD_VEX_0F12_PREFIX_0,
 840   MOD_VEX_0F12_PREFIX_2,
 841   MOD_VEX_0F13,
 842   MOD_VEX_0F16_PREFIX_0,
 843   MOD_VEX_0F16_PREFIX_2,
 844   MOD_VEX_0F17,
 845   MOD_VEX_0F2B,
 846   MOD_VEX_W_0_0F41_P_0_LEN_1,
 847   MOD_VEX_W_1_0F41_P_0_LEN_1,
 848   MOD_VEX_W_0_0F41_P_2_LEN_1,
 849   MOD_VEX_W_1_0F41_P_2_LEN_1,
 850   MOD_VEX_W_0_0F42_P_0_LEN_1,
 851   MOD_VEX_W_1_0F42_P_0_LEN_1,
 852   MOD_VEX_W_0_0F42_P_2_LEN_1,
 853   MOD_VEX_W_1_0F42_P_2_LEN_1,
 854   MOD_VEX_W_0_0F44_P_0_LEN_1,
 855   MOD_VEX_W_1_0F44_P_0_LEN_1,
 856   MOD_VEX_W_0_0F44_P_2_LEN_1,
 857   MOD_VEX_W_1_0F44_P_2_LEN_1,
 858   MOD_VEX_W_0_0F45_P_0_LEN_1,
 859   MOD_VEX_W_1_0F45_P_0_LEN_1,
 860   MOD_VEX_W_0_0F45_P_2_LEN_1,
 861   MOD_VEX_W_1_0F45_P_2_LEN_1,
 862   MOD_VEX_W_0_0F46_P_0_LEN_1,
 863   MOD_VEX_W_1_0F46_P_0_LEN_1,
 864   MOD_VEX_W_0_0F46_P_2_LEN_1,
 865   MOD_VEX_W_1_0F46_P_2_LEN_1,
 866   MOD_VEX_W_0_0F47_P_0_LEN_1,
 867   MOD_VEX_W_1_0F47_P_0_LEN_1,
 868   MOD_VEX_W_0_0F47_P_2_LEN_1,
 869   MOD_VEX_W_1_0F47_P_2_LEN_1,
 870   MOD_VEX_W_0_0F4A_P_0_LEN_1,
 871   MOD_VEX_W_1_0F4A_P_0_LEN_1,
 872   MOD_VEX_W_0_0F4A_P_2_LEN_1,
 873   MOD_VEX_W_1_0F4A_P_2_LEN_1,
 874   MOD_VEX_W_0_0F4B_P_0_LEN_1,
 875   MOD_VEX_W_1_0F4B_P_0_LEN_1,
 876   MOD_VEX_W_0_0F4B_P_2_LEN_1,
 877   MOD_VEX_0F50,
 878   MOD_VEX_0F71_REG_2,
 879   MOD_VEX_0F71_REG_4,
 880   MOD_VEX_0F71_REG_6,
 881   MOD_VEX_0F72_REG_2,
 882   MOD_VEX_0F72_REG_4,
 883   MOD_VEX_0F72_REG_6,
 884   MOD_VEX_0F73_REG_2,
 885   MOD_VEX_0F73_REG_3,
 886   MOD_VEX_0F73_REG_6,
 887   MOD_VEX_0F73_REG_7,
 888   MOD_VEX_W_0_0F91_P_0_LEN_0,
 889   MOD_VEX_W_1_0F91_P_0_LEN_0,
 890   MOD_VEX_W_0_0F91_P_2_LEN_0,
 891   MOD_VEX_W_1_0F91_P_2_LEN_0,
 892   MOD_VEX_W_0_0F92_P_0_LEN_0,
 893   MOD_VEX_W_0_0F92_P_2_LEN_0,
 894   MOD_VEX_0F92_P_3_LEN_0,
 895   MOD_VEX_W_0_0F93_P_0_LEN_0,
 896   MOD_VEX_W_0_0F93_P_2_LEN_0,
 897   MOD_VEX_0F93_P_3_LEN_0,
 898   MOD_VEX_W_0_0F98_P_0_LEN_0,
 899   MOD_VEX_W_1_0F98_P_0_LEN_0,
 900   MOD_VEX_W_0_0F98_P_2_LEN_0,
 901   MOD_VEX_W_1_0F98_P_2_LEN_0,
 902   MOD_VEX_W_0_0F99_P_0_LEN_0,
 903   MOD_VEX_W_1_0F99_P_0_LEN_0,
 904   MOD_VEX_W_0_0F99_P_2_LEN_0,
 905   MOD_VEX_W_1_0F99_P_2_LEN_0,
 906   MOD_VEX_0FAE_REG_2,
 907   MOD_VEX_0FAE_REG_3,
 908   MOD_VEX_0FD7_PREFIX_2,
 909   MOD_VEX_0FE7_PREFIX_2,
 910   MOD_VEX_0FF0_PREFIX_3,
 911   MOD_VEX_0F381A_PREFIX_2,
 912   MOD_VEX_0F382A_PREFIX_2,
 913   MOD_VEX_0F382C_PREFIX_2,
 914   MOD_VEX_0F382D_PREFIX_2,
 915   MOD_VEX_0F382E_PREFIX_2,
 916   MOD_VEX_0F382F_PREFIX_2,
 917   MOD_VEX_0F385A_PREFIX_2,
 918   MOD_VEX_0F388C_PREFIX_2,
 919   MOD_VEX_0F388E_PREFIX_2,
 920   MOD_VEX_W_0_0F3A30_P_2_LEN_0,
 921   MOD_VEX_W_1_0F3A30_P_2_LEN_0,
 922   MOD_VEX_W_0_0F3A31_P_2_LEN_0,
 923   MOD_VEX_W_1_0F3A31_P_2_LEN_0,
 924   MOD_VEX_W_0_0F3A32_P_2_LEN_0,
 925   MOD_VEX_W_1_0F3A32_P_2_LEN_0,
 926   MOD_VEX_W_0_0F3A33_P_2_LEN_0,
 927   MOD_VEX_W_1_0F3A33_P_2_LEN_0,
 928
 929   MOD_EVEX_0F12_PREFIX_0,
 930   MOD_EVEX_0F12_PREFIX_2,
 931   MOD_EVEX_0F13,
 932   MOD_EVEX_0F16_PREFIX_0,
 933   MOD_EVEX_0F16_PREFIX_2,
 934   MOD_EVEX_0F17,
 935   MOD_EVEX_0F2B,
 936   MOD_EVEX_0F38C6_REG_1,
 937   MOD_EVEX_0F38C6_REG_2,
 938   MOD_EVEX_0F38C6_REG_5,
 939   MOD_EVEX_0F38C6_REG_6,
 940   MOD_EVEX_0F38C7_REG_1,
 941   MOD_EVEX_0F38C7_REG_2,
 942   MOD_EVEX_0F38C7_REG_5,
 943   MOD_EVEX_0F38C7_REG_6
 944 };
 945
 946 enum
 947 {
 948   RM_C6_REG_7 = 0,
 949   RM_C7_REG_7,
 950   RM_0F01_REG_0,
 951   RM_0F01_REG_1,
 952   RM_0F01_REG_2,
 953   RM_0F01_REG_3,
 954   RM_0F01_REG_5_MOD_3,
 955   RM_0F01_REG_7_MOD_3,
 956   RM_0F1E_P_1_MOD_3_REG_7,
 957   RM_0FAE_REG_6_MOD_3_P_0,
 958   RM_0FAE_REG_7_MOD_3,
 959 };
 960
 961 enum
 962 {
 963   PREFIX_90 = 0,
 964   PREFIX_0F01_REG_3_RM_1,
 965   PREFIX_0F01_REG_5_MOD_0,
 966   PREFIX_0F01_REG_5_MOD_3_RM_0,
 967   PREFIX_0F01_REG_5_MOD_3_RM_1,
 968   PREFIX_0F01_REG_5_MOD_3_RM_2,
 969   PREFIX_0F01_REG_7_MOD_3_RM_2,
 970   PREFIX_0F01_REG_7_MOD_3_RM_3,
 971   PREFIX_0F09,
 972   PREFIX_0F10,
 973   PREFIX_0F11,
 974   PREFIX_0F12,
 975   PREFIX_0F16,
 976   PREFIX_0F1A,
 977   PREFIX_0F1B,
 978   PREFIX_0F1C,
 979   PREFIX_0F1E,
 980   PREFIX_0F2A,
 981   PREFIX_0F2B,
 982   PREFIX_0F2C,
 983   PREFIX_0F2D,
 984   PREFIX_0F2E,
 985   PREFIX_0F2F,
 986   PREFIX_0F51,
 987   PREFIX_0F52,
 988   PREFIX_0F53,
 989   PREFIX_0F58,
 990   PREFIX_0F59,
 991   PREFIX_0F5A,
 992   PREFIX_0F5B,
 993   PREFIX_0F5C,
 994   PREFIX_0F5D,
 995   PREFIX_0F5E,
 996   PREFIX_0F5F,
 997   PREFIX_0F60,
 998   PREFIX_0F61,
 999   PREFIX_0F62,
1000   PREFIX_0F6C,
1001   PREFIX_0F6D,
1002   PREFIX_0F6F,
1003   PREFIX_0F70,
1004   PREFIX_0F73_REG_3,
1005   PREFIX_0F73_REG_7,
1006   PREFIX_0F78,
1007   PREFIX_0F79,
1008   PREFIX_0F7C,
1009   PREFIX_0F7D,
1010   PREFIX_0F7E,
1011   PREFIX_0F7F,
1012   PREFIX_0FAE_REG_0_MOD_3,
1013   PREFIX_0FAE_REG_1_MOD_3,
1014   PREFIX_0FAE_REG_2_MOD_3,
1015   PREFIX_0FAE_REG_3_MOD_3,
1016   PREFIX_0FAE_REG_4_MOD_0,
1017   PREFIX_0FAE_REG_4_MOD_3,
1018   PREFIX_0FAE_REG_5_MOD_0,
1019   PREFIX_0FAE_REG_5_MOD_3,
1020   PREFIX_0FAE_REG_6_MOD_0,
1021   PREFIX_0FAE_REG_6_MOD_3,
1022   PREFIX_0FAE_REG_7_MOD_0,
1023   PREFIX_0FB8,
1024   PREFIX_0FBC,
1025   PREFIX_0FBD,
1026   PREFIX_0FC2,
1027   PREFIX_0FC3_MOD_0,
1028   PREFIX_0FC7_REG_6_MOD_0,
1029   PREFIX_0FC7_REG_6_MOD_3,
1030   PREFIX_0FC7_REG_7_MOD_3,
1031   PREFIX_0FD0,
1032   PREFIX_0FD6,
1033   PREFIX_0FE6,
1034   PREFIX_0FE7,
1035   PREFIX_0FF0,
1036   PREFIX_0FF7,
1037   PREFIX_0F3810,
1038   PREFIX_0F3814,
1039   PREFIX_0F3815,
1040   PREFIX_0F3817,
1041   PREFIX_0F3820,
1042   PREFIX_0F3821,
1043   PREFIX_0F3822,
1044   PREFIX_0F3823,
1045   PREFIX_0F3824,
1046   PREFIX_0F3825,
1047   PREFIX_0F3828,
1048   PREFIX_0F3829,
1049   PREFIX_0F382A,
1050   PREFIX_0F382B,
1051   PREFIX_0F3830,
1052   PREFIX_0F3831,
1053   PREFIX_0F3832,
1054   PREFIX_0F3833,
1055   PREFIX_0F3834,
1056   PREFIX_0F3835,
1057   PREFIX_0F3837,
1058   PREFIX_0F3838,
1059   PREFIX_0F3839,
1060   PREFIX_0F383A,
1061   PREFIX_0F383B,
1062   PREFIX_0F383C,
1063   PREFIX_0F383D,
1064   PREFIX_0F383E,
1065   PREFIX_0F383F,
1066   PREFIX_0F3840,
1067   PREFIX_0F3841,
1068   PREFIX_0F3880,
1069   PREFIX_0F3881,
1070   PREFIX_0F3882,
1071   PREFIX_0F38C8,
1072   PREFIX_0F38C9,
1073   PREFIX_0F38CA,
1074   PREFIX_0F38CB,
1075   PREFIX_0F38CC,
1076   PREFIX_0F38CD,
1077   PREFIX_0F38CF,
1078   PREFIX_0F38DB,
1079   PREFIX_0F38DC,
1080   PREFIX_0F38DD,
1081   PREFIX_0F38DE,
1082   PREFIX_0F38DF,
1083   PREFIX_0F38F0,
1084   PREFIX_0F38F1,
1085   PREFIX_0F38F5,
1086   PREFIX_0F38F6,
1087   PREFIX_0F38F8,
1088   PREFIX_0F38F9,
1089   PREFIX_0F3A08,
1090   PREFIX_0F3A09,
1091   PREFIX_0F3A0A,
1092   PREFIX_0F3A0B,
1093   PREFIX_0F3A0C,
1094   PREFIX_0F3A0D,
1095   PREFIX_0F3A0E,
1096   PREFIX_0F3A14,
1097   PREFIX_0F3A15,
1098   PREFIX_0F3A16,
1099   PREFIX_0F3A17,
1100   PREFIX_0F3A20,
1101   PREFIX_0F3A21,
1102   PREFIX_0F3A22,
1103   PREFIX_0F3A40,
1104   PREFIX_0F3A41,
1105   PREFIX_0F3A42,
1106   PREFIX_0F3A44,
1107   PREFIX_0F3A60,
1108   PREFIX_0F3A61,
1109   PREFIX_0F3A62,
1110   PREFIX_0F3A63,
1111   PREFIX_0F3ACC,
1112   PREFIX_0F3ACE,
1113   PREFIX_0F3ACF,
1114   PREFIX_0F3ADF,
1115   PREFIX_VEX_0F10,
1116   PREFIX_VEX_0F11,
1117   PREFIX_VEX_0F12,
1118   PREFIX_VEX_0F16,
1119   PREFIX_VEX_0F2A,
1120   PREFIX_VEX_0F2C,
1121   PREFIX_VEX_0F2D,
1122   PREFIX_VEX_0F2E,
1123   PREFIX_VEX_0F2F,
1124   PREFIX_VEX_0F41,
1125   PREFIX_VEX_0F42,
1126   PREFIX_VEX_0F44,
1127   PREFIX_VEX_0F45,
1128   PREFIX_VEX_0F46,
1129   PREFIX_VEX_0F47,
1130   PREFIX_VEX_0F4A,
1131   PREFIX_VEX_0F4B,
1132   PREFIX_VEX_0F51,
1133   PREFIX_VEX_0F52,
1134   PREFIX_VEX_0F53,
1135   PREFIX_VEX_0F58,
1136   PREFIX_VEX_0F59,
1137   PREFIX_VEX_0F5A,
1138   PREFIX_VEX_0F5B,
1139   PREFIX_VEX_0F5C,
1140   PREFIX_VEX_0F5D,
1141   PREFIX_VEX_0F5E,
1142   PREFIX_VEX_0F5F,
1143   PREFIX_VEX_0F60,
1144   PREFIX_VEX_0F61,
1145   PREFIX_VEX_0F62,
1146   PREFIX_VEX_0F63,
1147   PREFIX_VEX_0F64,
1148   PREFIX_VEX_0F65,
1149   PREFIX_VEX_0F66,
1150   PREFIX_VEX_0F67,
1151   PREFIX_VEX_0F68,
1152   PREFIX_VEX_0F69,
1153   PREFIX_VEX_0F6A,
1154   PREFIX_VEX_0F6B,
1155   PREFIX_VEX_0F6C,
1156   PREFIX_VEX_0F6D,
1157   PREFIX_VEX_0F6E,
1158   PREFIX_VEX_0F6F,
1159   PREFIX_VEX_0F70,
1160   PREFIX_VEX_0F71_REG_2,
1161   PREFIX_VEX_0F71_REG_4,
1162   PREFIX_VEX_0F71_REG_6,
1163   PREFIX_VEX_0F72_REG_2,
1164   PREFIX_VEX_0F72_REG_4,
1165   PREFIX_VEX_0F72_REG_6,
1166   PREFIX_VEX_0F73_REG_2,
1167   PREFIX_VEX_0F73_REG_3,
1168   PREFIX_VEX_0F73_REG_6,
1169   PREFIX_VEX_0F73_REG_7,
1170   PREFIX_VEX_0F74,
1171   PREFIX_VEX_0F75,
1172   PREFIX_VEX_0F76,
1173   PREFIX_VEX_0F77,
1174   PREFIX_VEX_0F7C,
1175   PREFIX_VEX_0F7D,
1176   PREFIX_VEX_0F7E,
1177   PREFIX_VEX_0F7F,
1178   PREFIX_VEX_0F90,
1179   PREFIX_VEX_0F91,
1180   PREFIX_VEX_0F92,
1181   PREFIX_VEX_0F93,
1182   PREFIX_VEX_0F98,
1183   PREFIX_VEX_0F99,
1184   PREFIX_VEX_0FC2,
1185   PREFIX_VEX_0FC4,
1186   PREFIX_VEX_0FC5,
1187   PREFIX_VEX_0FD0,
1188   PREFIX_VEX_0FD1,
1189   PREFIX_VEX_0FD2,
1190   PREFIX_VEX_0FD3,
1191   PREFIX_VEX_0FD4,
1192   PREFIX_VEX_0FD5,
1193   PREFIX_VEX_0FD6,
1194   PREFIX_VEX_0FD7,
1195   PREFIX_VEX_0FD8,
1196   PREFIX_VEX_0FD9,
1197   PREFIX_VEX_0FDA,
1198   PREFIX_VEX_0FDB,
1199   PREFIX_VEX_0FDC,
1200   PREFIX_VEX_0FDD,
1201   PREFIX_VEX_0FDE,
1202   PREFIX_VEX_0FDF,
1203   PREFIX_VEX_0FE0,
1204   PREFIX_VEX_0FE1,
1205   PREFIX_VEX_0FE2,
1206   PREFIX_VEX_0FE3,
1207   PREFIX_VEX_0FE4,
1208   PREFIX_VEX_0FE5,
1209   PREFIX_VEX_0FE6,
1210   PREFIX_VEX_0FE7,
1211   PREFIX_VEX_0FE8,
1212   PREFIX_VEX_0FE9,
1213   PREFIX_VEX_0FEA,
1214   PREFIX_VEX_0FEB,
1215   PREFIX_VEX_0FEC,
1216   PREFIX_VEX_0FED,
1217   PREFIX_VEX_0FEE,
1218   PREFIX_VEX_0FEF,
1219   PREFIX_VEX_0FF0,
1220   PREFIX_VEX_0FF1,
1221   PREFIX_VEX_0FF2,
1222   PREFIX_VEX_0FF3,
1223   PREFIX_VEX_0FF4,
1224   PREFIX_VEX_0FF5,
1225   PREFIX_VEX_0FF6,
1226   PREFIX_VEX_0FF7,
1227   PREFIX_VEX_0FF8,
1228   PREFIX_VEX_0FF9,
1229   PREFIX_VEX_0FFA,
1230   PREFIX_VEX_0FFB,
1231   PREFIX_VEX_0FFC,
1232   PREFIX_VEX_0FFD,
1233   PREFIX_VEX_0FFE,
1234   PREFIX_VEX_0F3800,
1235   PREFIX_VEX_0F3801,
1236   PREFIX_VEX_0F3802,
1237   PREFIX_VEX_0F3803,
1238   PREFIX_VEX_0F3804,
1239   PREFIX_VEX_0F3805,
1240   PREFIX_VEX_0F3806,
1241   PREFIX_VEX_0F3807,
1242   PREFIX_VEX_0F3808,
1243   PREFIX_VEX_0F3809,
1244   PREFIX_VEX_0F380A,
1245   PREFIX_VEX_0F380B,
1246   PREFIX_VEX_0F380C,
1247   PREFIX_VEX_0F380D,
1248   PREFIX_VEX_0F380E,
1249   PREFIX_VEX_0F380F,
1250   PREFIX_VEX_0F3813,
1251   PREFIX_VEX_0F3816,
1252   PREFIX_VEX_0F3817,
1253   PREFIX_VEX_0F3818,
1254   PREFIX_VEX_0F3819,
1255   PREFIX_VEX_0F381A,
1256   PREFIX_VEX_0F381C,
1257   PREFIX_VEX_0F381D,
1258   PREFIX_VEX_0F381E,
1259   PREFIX_VEX_0F3820,
1260   PREFIX_VEX_0F3821,
1261   PREFIX_VEX_0F3822,
1262   PREFIX_VEX_0F3823,
1263   PREFIX_VEX_0F3824,
1264   PREFIX_VEX_0F3825,
1265   PREFIX_VEX_0F3828,
1266   PREFIX_VEX_0F3829,
1267   PREFIX_VEX_0F382A,
1268   PREFIX_VEX_0F382B,
1269   PREFIX_VEX_0F382C,
1270   PREFIX_VEX_0F382D,
1271   PREFIX_VEX_0F382E,
1272   PREFIX_VEX_0F382F,
1273   PREFIX_VEX_0F3830,
1274   PREFIX_VEX_0F3831,
1275   PREFIX_VEX_0F3832,
1276   PREFIX_VEX_0F3833,
1277   PREFIX_VEX_0F3834,
1278   PREFIX_VEX_0F3835,
1279   PREFIX_VEX_0F3836,
1280   PREFIX_VEX_0F3837,
1281   PREFIX_VEX_0F3838,
1282   PREFIX_VEX_0F3839,
1283   PREFIX_VEX_0F383A,
1284   PREFIX_VEX_0F383B,
1285   PREFIX_VEX_0F383C,
1286   PREFIX_VEX_0F383D,
1287   PREFIX_VEX_0F383E,
1288   PREFIX_VEX_0F383F,
1289   PREFIX_VEX_0F3840,
1290   PREFIX_VEX_0F3841,
1291   PREFIX_VEX_0F3845,
1292   PREFIX_VEX_0F3846,
1293   PREFIX_VEX_0F3847,
1294   PREFIX_VEX_0F3858,
1295   PREFIX_VEX_0F3859,
1296   PREFIX_VEX_0F385A,
1297   PREFIX_VEX_0F3878,
1298   PREFIX_VEX_0F3879,
1299   PREFIX_VEX_0F388C,
1300   PREFIX_VEX_0F388E,
1301   PREFIX_VEX_0F3890,
1302   PREFIX_VEX_0F3891,
1303   PREFIX_VEX_0F3892,
1304   PREFIX_VEX_0F3893,
1305   PREFIX_VEX_0F3896,
1306   PREFIX_VEX_0F3897,
1307   PREFIX_VEX_0F3898,
1308   PREFIX_VEX_0F3899,
1309   PREFIX_VEX_0F389A,
1310   PREFIX_VEX_0F389B,
1311   PREFIX_VEX_0F389C,
1312   PREFIX_VEX_0F389D,
1313   PREFIX_VEX_0F389E,
1314   PREFIX_VEX_0F389F,
1315   PREFIX_VEX_0F38A6,
1316   PREFIX_VEX_0F38A7,
1317   PREFIX_VEX_0F38A8,
1318   PREFIX_VEX_0F38A9,
1319   PREFIX_VEX_0F38AA,
1320   PREFIX_VEX_0F38AB,
1321   PREFIX_VEX_0F38AC,
1322   PREFIX_VEX_0F38AD,
1323   PREFIX_VEX_0F38AE,
1324   PREFIX_VEX_0F38AF,
1325   PREFIX_VEX_0F38B6,
1326   PREFIX_VEX_0F38B7,
1327   PREFIX_VEX_0F38B8,
1328   PREFIX_VEX_0F38B9,
1329   PREFIX_VEX_0F38BA,
1330   PREFIX_VEX_0F38BB,
1331   PREFIX_VEX_0F38BC,
1332   PREFIX_VEX_0F38BD,
1333   PREFIX_VEX_0F38BE,
1334   PREFIX_VEX_0F38BF,
1335   PREFIX_VEX_0F38CF,
1336   PREFIX_VEX_0F38DB,
1337   PREFIX_VEX_0F38DC,
1338   PREFIX_VEX_0F38DD,
1339   PREFIX_VEX_0F38DE,
1340   PREFIX_VEX_0F38DF,
1341   PREFIX_VEX_0F38F2,
1342   PREFIX_VEX_0F38F3_REG_1,
1343   PREFIX_VEX_0F38F3_REG_2,
1344   PREFIX_VEX_0F38F3_REG_3,
1345   PREFIX_VEX_0F38F5,
1346   PREFIX_VEX_0F38F6,
1347   PREFIX_VEX_0F38F7,
1348   PREFIX_VEX_0F3A00,
1349   PREFIX_VEX_0F3A01,
1350   PREFIX_VEX_0F3A02,
1351   PREFIX_VEX_0F3A04,
1352   PREFIX_VEX_0F3A05,
1353   PREFIX_VEX_0F3A06,
1354   PREFIX_VEX_0F3A08,
1355   PREFIX_VEX_0F3A09,
1356   PREFIX_VEX_0F3A0A,
1357   PREFIX_VEX_0F3A0B,
1358   PREFIX_VEX_0F3A0C,
1359   PREFIX_VEX_0F3A0D,
1360   PREFIX_VEX_0F3A0E,
1361   PREFIX_VEX_0F3A0F,
1362   PREFIX_VEX_0F3A14,
1363   PREFIX_VEX_0F3A15,
1364   PREFIX_VEX_0F3A16,
1365   PREFIX_VEX_0F3A17,
1366   PREFIX_VEX_0F3A18,
1367   PREFIX_VEX_0F3A19,
1368   PREFIX_VEX_0F3A1D,
1369   PREFIX_VEX_0F3A20,
1370   PREFIX_VEX_0F3A21,
1371   PREFIX_VEX_0F3A22,
1372   PREFIX_VEX_0F3A30,
1373   PREFIX_VEX_0F3A31,
1374   PREFIX_VEX_0F3A32,
1375   PREFIX_VEX_0F3A33,
1376   PREFIX_VEX_0F3A38,
1377   PREFIX_VEX_0F3A39,
1378   PREFIX_VEX_0F3A40,
1379   PREFIX_VEX_0F3A41,
1380   PREFIX_VEX_0F3A42,
1381   PREFIX_VEX_0F3A44,
1382   PREFIX_VEX_0F3A46,
1383   PREFIX_VEX_0F3A48,
1384   PREFIX_VEX_0F3A49,
1385   PREFIX_VEX_0F3A4A,
1386   PREFIX_VEX_0F3A4B,
1387   PREFIX_VEX_0F3A4C,
1388   PREFIX_VEX_0F3A5C,
1389   PREFIX_VEX_0F3A5D,
1390   PREFIX_VEX_0F3A5E,
1391   PREFIX_VEX_0F3A5F,
1392   PREFIX_VEX_0F3A60,
1393   PREFIX_VEX_0F3A61,
1394   PREFIX_VEX_0F3A62,
1395   PREFIX_VEX_0F3A63,
1396   PREFIX_VEX_0F3A68,
1397   PREFIX_VEX_0F3A69,
1398   PREFIX_VEX_0F3A6A,
1399   PREFIX_VEX_0F3A6B,
1400   PREFIX_VEX_0F3A6C,
1401   PREFIX_VEX_0F3A6D,
1402   PREFIX_VEX_0F3A6E,
1403   PREFIX_VEX_0F3A6F,
1404   PREFIX_VEX_0F3A78,
1405   PREFIX_VEX_0F3A79,
1406   PREFIX_VEX_0F3A7A,
1407   PREFIX_VEX_0F3A7B,
1408   PREFIX_VEX_0F3A7C,
1409   PREFIX_VEX_0F3A7D,
1410   PREFIX_VEX_0F3A7E,
1411   PREFIX_VEX_0F3A7F,
1412   PREFIX_VEX_0F3ACE,
1413   PREFIX_VEX_0F3ACF,
1414   PREFIX_VEX_0F3ADF,
1415   PREFIX_VEX_0F3AF0,
1416
1417   PREFIX_EVEX_0F10,
1418   PREFIX_EVEX_0F11,
1419   PREFIX_EVEX_0F12,
1420   PREFIX_EVEX_0F16,
1421   PREFIX_EVEX_0F2A,
1422   PREFIX_EVEX_0F2C,
1423   PREFIX_EVEX_0F2D,
1424   PREFIX_EVEX_0F2E,
1425   PREFIX_EVEX_0F2F,
1426   PREFIX_EVEX_0F51,
1427   PREFIX_EVEX_0F58,
1428   PREFIX_EVEX_0F59,
1429   PREFIX_EVEX_0F5A,
1430   PREFIX_EVEX_0F5B,
1431   PREFIX_EVEX_0F5C,
1432   PREFIX_EVEX_0F5D,
1433   PREFIX_EVEX_0F5E,
1434   PREFIX_EVEX_0F5F,
1435   PREFIX_EVEX_0F60,
1436   PREFIX_EVEX_0F61,
1437   PREFIX_EVEX_0F62,
1438   PREFIX_EVEX_0F63,
1439   PREFIX_EVEX_0F64,
1440   PREFIX_EVEX_0F65,
1441   PREFIX_EVEX_0F66,
1442   PREFIX_EVEX_0F67,
1443   PREFIX_EVEX_0F68,
1444   PREFIX_EVEX_0F69,
1445   PREFIX_EVEX_0F6A,
1446   PREFIX_EVEX_0F6B,
1447   PREFIX_EVEX_0F6C,
1448   PREFIX_EVEX_0F6D,
1449   PREFIX_EVEX_0F6E,
1450   PREFIX_EVEX_0F6F,
1451   PREFIX_EVEX_0F70,
1452   PREFIX_EVEX_0F71_REG_2,
1453   PREFIX_EVEX_0F71_REG_4,
1454   PREFIX_EVEX_0F71_REG_6,
1455   PREFIX_EVEX_0F72_REG_0,
1456   PREFIX_EVEX_0F72_REG_1,
1457   PREFIX_EVEX_0F72_REG_2,
1458   PREFIX_EVEX_0F72_REG_4,
1459   PREFIX_EVEX_0F72_REG_6,
1460   PREFIX_EVEX_0F73_REG_2,
1461   PREFIX_EVEX_0F73_REG_3,
1462   PREFIX_EVEX_0F73_REG_6,
1463   PREFIX_EVEX_0F73_REG_7,
1464   PREFIX_EVEX_0F74,
1465   PREFIX_EVEX_0F75,
1466   PREFIX_EVEX_0F76,
1467   PREFIX_EVEX_0F78,
1468   PREFIX_EVEX_0F79,
1469   PREFIX_EVEX_0F7A,
1470   PREFIX_EVEX_0F7B,
1471   PREFIX_EVEX_0F7E,
1472   PREFIX_EVEX_0F7F,
1473   PREFIX_EVEX_0FC2,
1474   PREFIX_EVEX_0FC4,
1475   PREFIX_EVEX_0FC5,
1476   PREFIX_EVEX_0FD1,
1477   PREFIX_EVEX_0FD2,
1478   PREFIX_EVEX_0FD3,
1479   PREFIX_EVEX_0FD4,
1480   PREFIX_EVEX_0FD5,
1481   PREFIX_EVEX_0FD6,
1482   PREFIX_EVEX_0FD8,
1483   PREFIX_EVEX_0FD9,
1484   PREFIX_EVEX_0FDA,
1485   PREFIX_EVEX_0FDB,
1486   PREFIX_EVEX_0FDC,
1487   PREFIX_EVEX_0FDD,
1488   PREFIX_EVEX_0FDE,
1489   PREFIX_EVEX_0FDF,
1490   PREFIX_EVEX_0FE0,
1491   PREFIX_EVEX_0FE1,
1492   PREFIX_EVEX_0FE2,
1493   PREFIX_EVEX_0FE3,
1494   PREFIX_EVEX_0FE4,
1495   PREFIX_EVEX_0FE5,
1496   PREFIX_EVEX_0FE6,
1497   PREFIX_EVEX_0FE7,
1498   PREFIX_EVEX_0FE8,
1499   PREFIX_EVEX_0FE9,
1500   PREFIX_EVEX_0FEA,
1501   PREFIX_EVEX_0FEB,
1502   PREFIX_EVEX_0FEC,
1503   PREFIX_EVEX_0FED,
1504   PREFIX_EVEX_0FEE,
1505   PREFIX_EVEX_0FEF,
1506   PREFIX_EVEX_0FF1,
1507   PREFIX_EVEX_0FF2,
1508   PREFIX_EVEX_0FF3,
1509   PREFIX_EVEX_0FF4,
1510   PREFIX_EVEX_0FF5,
1511   PREFIX_EVEX_0FF6,
1512   PREFIX_EVEX_0FF8,
1513   PREFIX_EVEX_0FF9,
1514   PREFIX_EVEX_0FFA,
1515   PREFIX_EVEX_0FFB,
1516   PREFIX_EVEX_0FFC,
1517   PREFIX_EVEX_0FFD,
1518   PREFIX_EVEX_0FFE,
1519   PREFIX_EVEX_0F3800,
1520   PREFIX_EVEX_0F3804,
1521   PREFIX_EVEX_0F380B,
1522   PREFIX_EVEX_0F380C,
1523   PREFIX_EVEX_0F380D,
1524   PREFIX_EVEX_0F3810,
1525   PREFIX_EVEX_0F3811,
1526   PREFIX_EVEX_0F3812,
1527   PREFIX_EVEX_0F3813,
1528   PREFIX_EVEX_0F3814,
1529   PREFIX_EVEX_0F3815,
1530   PREFIX_EVEX_0F3816,
1531   PREFIX_EVEX_0F3818,
1532   PREFIX_EVEX_0F3819,
1533   PREFIX_EVEX_0F381A,
1534   PREFIX_EVEX_0F381B,
1535   PREFIX_EVEX_0F381C,
1536   PREFIX_EVEX_0F381D,
1537   PREFIX_EVEX_0F381E,
1538   PREFIX_EVEX_0F381F,
1539   PREFIX_EVEX_0F3820,
1540   PREFIX_EVEX_0F3821,
1541   PREFIX_EVEX_0F3822,
1542   PREFIX_EVEX_0F3823,
1543   PREFIX_EVEX_0F3824,
1544   PREFIX_EVEX_0F3825,
1545   PREFIX_EVEX_0F3826,
1546   PREFIX_EVEX_0F3827,
1547   PREFIX_EVEX_0F3828,
1548   PREFIX_EVEX_0F3829,
1549   PREFIX_EVEX_0F382A,
1550   PREFIX_EVEX_0F382B,
1551   PREFIX_EVEX_0F382C,
1552   PREFIX_EVEX_0F382D,
1553   PREFIX_EVEX_0F3830,
1554   PREFIX_EVEX_0F3831,
1555   PREFIX_EVEX_0F3832,
1556   PREFIX_EVEX_0F3833,
1557   PREFIX_EVEX_0F3834,
1558   PREFIX_EVEX_0F3835,
1559   PREFIX_EVEX_0F3836,
1560   PREFIX_EVEX_0F3837,
1561   PREFIX_EVEX_0F3838,
1562   PREFIX_EVEX_0F3839,
1563   PREFIX_EVEX_0F383A,
1564   PREFIX_EVEX_0F383B,
1565   PREFIX_EVEX_0F383C,
1566   PREFIX_EVEX_0F383D,
1567   PREFIX_EVEX_0F383E,
1568   PREFIX_EVEX_0F383F,
1569   PREFIX_EVEX_0F3840,
1570   PREFIX_EVEX_0F3842,
1571   PREFIX_EVEX_0F3843,
1572   PREFIX_EVEX_0F3844,
1573   PREFIX_EVEX_0F3845,
1574   PREFIX_EVEX_0F3846,
1575   PREFIX_EVEX_0F3847,
1576   PREFIX_EVEX_0F384C,
1577   PREFIX_EVEX_0F384D,
1578   PREFIX_EVEX_0F384E,
1579   PREFIX_EVEX_0F384F,
1580   PREFIX_EVEX_0F3850,
1581   PREFIX_EVEX_0F3851,
1582   PREFIX_EVEX_0F3852,
1583   PREFIX_EVEX_0F3853,
1584   PREFIX_EVEX_0F3854,
1585   PREFIX_EVEX_0F3855,
1586   PREFIX_EVEX_0F3858,
1587   PREFIX_EVEX_0F3859,
1588   PREFIX_EVEX_0F385A,
1589   PREFIX_EVEX_0F385B,
1590   PREFIX_EVEX_0F3862,
1591   PREFIX_EVEX_0F3863,
1592   PREFIX_EVEX_0F3864,
1593   PREFIX_EVEX_0F3865,
1594   PREFIX_EVEX_0F3866,
1595   PREFIX_EVEX_0F3868,
1596   PREFIX_EVEX_0F3870,
1597   PREFIX_EVEX_0F3871,
1598   PREFIX_EVEX_0F3872,
1599   PREFIX_EVEX_0F3873,
1600   PREFIX_EVEX_0F3875,
1601   PREFIX_EVEX_0F3876,
1602   PREFIX_EVEX_0F3877,
1603   PREFIX_EVEX_0F3878,
1604   PREFIX_EVEX_0F3879,
1605   PREFIX_EVEX_0F387A,
1606   PREFIX_EVEX_0F387B,
1607   PREFIX_EVEX_0F387C,
1608   PREFIX_EVEX_0F387D,
1609   PREFIX_EVEX_0F387E,
1610   PREFIX_EVEX_0F387F,
1611   PREFIX_EVEX_0F3883,
1612   PREFIX_EVEX_0F3888,
1613   PREFIX_EVEX_0F3889,
1614   PREFIX_EVEX_0F388A,
1615   PREFIX_EVEX_0F388B,
1616   PREFIX_EVEX_0F388D,
1617   PREFIX_EVEX_0F388F,
1618   PREFIX_EVEX_0F3890,
1619   PREFIX_EVEX_0F3891,
1620   PREFIX_EVEX_0F3892,
1621   PREFIX_EVEX_0F3893,
1622   PREFIX_EVEX_0F3896,
1623   PREFIX_EVEX_0F3897,
1624   PREFIX_EVEX_0F3898,
1625   PREFIX_EVEX_0F3899,
1626   PREFIX_EVEX_0F389A,
1627   PREFIX_EVEX_0F389B,
1628   PREFIX_EVEX_0F389C,
1629   PREFIX_EVEX_0F389D,
1630   PREFIX_EVEX_0F389E,
1631   PREFIX_EVEX_0F389F,
1632   PREFIX_EVEX_0F38A0,
1633   PREFIX_EVEX_0F38A1,
1634   PREFIX_EVEX_0F38A2,
1635   PREFIX_EVEX_0F38A3,
1636   PREFIX_EVEX_0F38A6,
1637   PREFIX_EVEX_0F38A7,
1638   PREFIX_EVEX_0F38A8,
1639   PREFIX_EVEX_0F38A9,
1640   PREFIX_EVEX_0F38AA,
1641   PREFIX_EVEX_0F38AB,
1642   PREFIX_EVEX_0F38AC,
1643   PREFIX_EVEX_0F38AD,
1644   PREFIX_EVEX_0F38AE,
1645   PREFIX_EVEX_0F38AF,
1646   PREFIX_EVEX_0F38B4,
1647   PREFIX_EVEX_0F38B5,
1648   PREFIX_EVEX_0F38B6,
1649   PREFIX_EVEX_0F38B7,
1650   PREFIX_EVEX_0F38B8,
1651   PREFIX_EVEX_0F38B9,
1652   PREFIX_EVEX_0F38BA,
1653   PREFIX_EVEX_0F38BB,
1654   PREFIX_EVEX_0F38BC,
1655   PREFIX_EVEX_0F38BD,
1656   PREFIX_EVEX_0F38BE,
1657   PREFIX_EVEX_0F38BF,
1658   PREFIX_EVEX_0F38C4,
1659   PREFIX_EVEX_0F38C6_REG_1,
1660   PREFIX_EVEX_0F38C6_REG_2,
1661   PREFIX_EVEX_0F38C6_REG_5,
1662   PREFIX_EVEX_0F38C6_REG_6,
1663   PREFIX_EVEX_0F38C7_REG_1,
1664   PREFIX_EVEX_0F38C7_REG_2,
1665   PREFIX_EVEX_0F38C7_REG_5,
1666   PREFIX_EVEX_0F38C7_REG_6,
1667   PREFIX_EVEX_0F38C8,
1668   PREFIX_EVEX_0F38CA,
1669   PREFIX_EVEX_0F38CB,
1670   PREFIX_EVEX_0F38CC,
1671   PREFIX_EVEX_0F38CD,
1672   PREFIX_EVEX_0F38CF,
1673   PREFIX_EVEX_0F38DC,
1674   PREFIX_EVEX_0F38DD,
1675   PREFIX_EVEX_0F38DE,
1676   PREFIX_EVEX_0F38DF,
1677
1678   PREFIX_EVEX_0F3A00,
1679   PREFIX_EVEX_0F3A01,
1680   PREFIX_EVEX_0F3A03,
1681   PREFIX_EVEX_0F3A04,
1682   PREFIX_EVEX_0F3A05,
1683   PREFIX_EVEX_0F3A08,
1684   PREFIX_EVEX_0F3A09,
1685   PREFIX_EVEX_0F3A0A,
1686   PREFIX_EVEX_0F3A0B,
1687   PREFIX_EVEX_0F3A0F,
1688   PREFIX_EVEX_0F3A14,
1689   PREFIX_EVEX_0F3A15,
1690   PREFIX_EVEX_0F3A16,
1691   PREFIX_EVEX_0F3A17,
1692   PREFIX_EVEX_0F3A18,
1693   PREFIX_EVEX_0F3A19,
1694   PREFIX_EVEX_0F3A1A,
1695   PREFIX_EVEX_0F3A1B,
1696   PREFIX_EVEX_0F3A1D,
1697   PREFIX_EVEX_0F3A1E,
1698   PREFIX_EVEX_0F3A1F,
1699   PREFIX_EVEX_0F3A20,
1700   PREFIX_EVEX_0F3A21,
1701   PREFIX_EVEX_0F3A22,
1702   PREFIX_EVEX_0F3A23,
1703   PREFIX_EVEX_0F3A25,
1704   PREFIX_EVEX_0F3A26,
1705   PREFIX_EVEX_0F3A27,
1706   PREFIX_EVEX_0F3A38,
1707   PREFIX_EVEX_0F3A39,
1708   PREFIX_EVEX_0F3A3A,
1709   PREFIX_EVEX_0F3A3B,
1710   PREFIX_EVEX_0F3A3E,
1711   PREFIX_EVEX_0F3A3F,
1712   PREFIX_EVEX_0F3A42,
1713   PREFIX_EVEX_0F3A43,
1714   PREFIX_EVEX_0F3A44,
1715   PREFIX_EVEX_0F3A50,
1716   PREFIX_EVEX_0F3A51,
1717   PREFIX_EVEX_0F3A54,
1718   PREFIX_EVEX_0F3A55,
1719   PREFIX_EVEX_0F3A56,
1720   PREFIX_EVEX_0F3A57,
1721   PREFIX_EVEX_0F3A66,
1722   PREFIX_EVEX_0F3A67,
1723   PREFIX_EVEX_0F3A70,
1724   PREFIX_EVEX_0F3A71,
1725   PREFIX_EVEX_0F3A72,
1726   PREFIX_EVEX_0F3A73,
1727   PREFIX_EVEX_0F3ACE,
1728   PREFIX_EVEX_0F3ACF
1729 };
1730
1731 enum
1732 {
1733   X86_64_06 = 0,
1734   X86_64_07,
1735   X86_64_0E,
1736   X86_64_16,
1737   X86_64_17,
1738   X86_64_1E,
1739   X86_64_1F,
1740   X86_64_27,
1741   X86_64_2F,
1742   X86_64_37,
1743   X86_64_3F,
1744   X86_64_60,
1745   X86_64_61,
1746   X86_64_62,
1747   X86_64_63,
1748   X86_64_6D,
1749   X86_64_6F,
1750   X86_64_82,
1751   X86_64_9A,
1752   X86_64_C2,
1753   X86_64_C3,
1754   X86_64_C4,
1755   X86_64_C5,
1756   X86_64_CE,
1757   X86_64_D4,
1758   X86_64_D5,
1759   X86_64_E8,
1760   X86_64_E9,
1761   X86_64_EA,
1762   X86_64_0F01_REG_0,
1763   X86_64_0F01_REG_1,
1764   X86_64_0F01_REG_2,
1765   X86_64_0F01_REG_3
1766 };
1767
1768 enum
1769 {
1770   THREE_BYTE_0F38 = 0,
1771   THREE_BYTE_0F3A
1772 };
1773
1774 enum
1775 {
1776   XOP_08 = 0,
1777   XOP_09,
1778   XOP_0A
1779 };
1780
1781 enum
1782 {
1783   VEX_0F = 0,
1784   VEX_0F38,
1785   VEX_0F3A
1786 };
1787
1788 enum
1789 {
1790   EVEX_0F = 0,
1791   EVEX_0F38,
1792   EVEX_0F3A
1793 };
1794
1795 enum
1796 {
1797   VEX_LEN_0F12_P_0_M_0 = 0,
1798   VEX_LEN_0F12_P_0_M_1,
1799 #define VEX_LEN_0F12_P_2_M_0 VEX_LEN_0F12_P_0_M_0
1800   VEX_LEN_0F13_M_0,
1801   VEX_LEN_0F16_P_0_M_0,
1802   VEX_LEN_0F16_P_0_M_1,
1803 #define VEX_LEN_0F16_P_2_M_0 VEX_LEN_0F16_P_0_M_0
1804   VEX_LEN_0F17_M_0,
1805   VEX_LEN_0F41_P_0,
1806   VEX_LEN_0F41_P_2,
1807   VEX_LEN_0F42_P_0,
1808   VEX_LEN_0F42_P_2,
1809   VEX_LEN_0F44_P_0,
1810   VEX_LEN_0F44_P_2,
1811   VEX_LEN_0F45_P_0,
1812   VEX_LEN_0F45_P_2,
1813   VEX_LEN_0F46_P_0,
1814   VEX_LEN_0F46_P_2,
1815   VEX_LEN_0F47_P_0,
1816   VEX_LEN_0F47_P_2,
1817   VEX_LEN_0F4A_P_0,
1818   VEX_LEN_0F4A_P_2,
1819   VEX_LEN_0F4B_P_0,
1820   VEX_LEN_0F4B_P_2,
1821   VEX_LEN_0F6E_P_2,
1822   VEX_LEN_0F77_P_0,
1823   VEX_LEN_0F7E_P_1,
1824   VEX_LEN_0F7E_P_2,
1825   VEX_LEN_0F90_P_0,
1826   VEX_LEN_0F90_P_2,
1827   VEX_LEN_0F91_P_0,
1828   VEX_LEN_0F91_P_2,
1829   VEX_LEN_0F92_P_0,
1830   VEX_LEN_0F92_P_2,
1831   VEX_LEN_0F92_P_3,
1832   VEX_LEN_0F93_P_0,
1833   VEX_LEN_0F93_P_2,
1834   VEX_LEN_0F93_P_3,
1835   VEX_LEN_0F98_P_0,
1836   VEX_LEN_0F98_P_2,
1837   VEX_LEN_0F99_P_0,
1838   VEX_LEN_0F99_P_2,
1839   VEX_LEN_0FAE_R_2_M_0,
1840   VEX_LEN_0FAE_R_3_M_0,
1841   VEX_LEN_0FC4_P_2,
1842   VEX_LEN_0FC5_P_2,
1843   VEX_LEN_0FD6_P_2,
1844   VEX_LEN_0FF7_P_2,
1845   VEX_LEN_0F3816_P_2,
1846   VEX_LEN_0F3819_P_2,
1847   VEX_LEN_0F381A_P_2_M_0,
1848   VEX_LEN_0F3836_P_2,
1849   VEX_LEN_0F3841_P_2,
1850   VEX_LEN_0F385A_P_2_M_0,
1851   VEX_LEN_0F38DB_P_2,
1852   VEX_LEN_0F38F2_P_0,
1853   VEX_LEN_0F38F3_R_1_P_0,
1854   VEX_LEN_0F38F3_R_2_P_0,
1855   VEX_LEN_0F38F3_R_3_P_0,
1856   VEX_LEN_0F38F5_P_0,
1857   VEX_LEN_0F38F5_P_1,
1858   VEX_LEN_0F38F5_P_3,
1859   VEX_LEN_0F38F6_P_3,
1860   VEX_LEN_0F38F7_P_0,
1861   VEX_LEN_0F38F7_P_1,
1862   VEX_LEN_0F38F7_P_2,
1863   VEX_LEN_0F38F7_P_3,
1864   VEX_LEN_0F3A00_P_2,
1865   VEX_LEN_0F3A01_P_2,
1866   VEX_LEN_0F3A06_P_2,
1867   VEX_LEN_0F3A14_P_2,
1868   VEX_LEN_0F3A15_P_2,
1869   VEX_LEN_0F3A16_P_2,
1870   VEX_LEN_0F3A17_P_2,
1871   VEX_LEN_0F3A18_P_2,
1872   VEX_LEN_0F3A19_P_2,
1873   VEX_LEN_0F3A20_P_2,
1874   VEX_LEN_0F3A21_P_2,
1875   VEX_LEN_0F3A22_P_2,
1876   VEX_LEN_0F3A30_P_2,
1877   VEX_LEN_0F3A31_P_2,
1878   VEX_LEN_0F3A32_P_2,
1879   VEX_LEN_0F3A33_P_2,
1880   VEX_LEN_0F3A38_P_2,
1881   VEX_LEN_0F3A39_P_2,
1882   VEX_LEN_0F3A41_P_2,
1883   VEX_LEN_0F3A46_P_2,
1884   VEX_LEN_0F3A60_P_2,
1885   VEX_LEN_0F3A61_P_2,
1886   VEX_LEN_0F3A62_P_2,
1887   VEX_LEN_0F3A63_P_2,
1888   VEX_LEN_0F3A6A_P_2,
1889   VEX_LEN_0F3A6B_P_2,
1890   VEX_LEN_0F3A6E_P_2,
1891   VEX_LEN_0F3A6F_P_2,
1892   VEX_LEN_0F3A7A_P_2,
1893   VEX_LEN_0F3A7B_P_2,
1894   VEX_LEN_0F3A7E_P_2,
1895   VEX_LEN_0F3A7F_P_2,
1896   VEX_LEN_0F3ADF_P_2,
1897   VEX_LEN_0F3AF0_P_3,
1898   VEX_LEN_0FXOP_08_CC,
1899   VEX_LEN_0FXOP_08_CD,
1900   VEX_LEN_0FXOP_08_CE,
1901   VEX_LEN_0FXOP_08_CF,
1902   VEX_LEN_0FXOP_08_EC,
1903   VEX_LEN_0FXOP_08_ED,
1904   VEX_LEN_0FXOP_08_EE,
1905   VEX_LEN_0FXOP_08_EF,
1906   VEX_LEN_0FXOP_09_80,
1907   VEX_LEN_0FXOP_09_81
1908 };
1909
1910 enum
1911 {
1912   EVEX_LEN_0F6E_P_2 = 0,
1913   EVEX_LEN_0F7E_P_1,
1914   EVEX_LEN_0F7E_P_2,
1915   EVEX_LEN_0FD6_P_2,
1916   EVEX_LEN_0F3819_P_2_W_0,
1917   EVEX_LEN_0F3819_P_2_W_1,
1918   EVEX_LEN_0F381A_P_2_W_0,
1919   EVEX_LEN_0F381A_P_2_W_1,
1920   EVEX_LEN_0F381B_P_2_W_0,
1921   EVEX_LEN_0F381B_P_2_W_1,
1922   EVEX_LEN_0F385A_P_2_W_0,
1923   EVEX_LEN_0F385A_P_2_W_1,
1924   EVEX_LEN_0F385B_P_2_W_0,
1925   EVEX_LEN_0F385B_P_2_W_1,
1926   EVEX_LEN_0F38C6_REG_1_PREFIX_2,
1927   EVEX_LEN_0F38C6_REG_2_PREFIX_2,
1928   EVEX_LEN_0F38C6_REG_5_PREFIX_2,
1929   EVEX_LEN_0F38C6_REG_6_PREFIX_2,
1930   EVEX_LEN_0F38C7_R_1_P_2_W_0,
1931   EVEX_LEN_0F38C7_R_1_P_2_W_1,
1932   EVEX_LEN_0F38C7_R_2_P_2_W_0,
1933   EVEX_LEN_0F38C7_R_2_P_2_W_1,
1934   EVEX_LEN_0F38C7_R_5_P_2_W_0,
1935   EVEX_LEN_0F38C7_R_5_P_2_W_1,
1936   EVEX_LEN_0F38C7_R_6_P_2_W_0,
1937   EVEX_LEN_0F38C7_R_6_P_2_W_1,
1938   EVEX_LEN_0F3A18_P_2_W_0,
1939   EVEX_LEN_0F3A18_P_2_W_1,
1940   EVEX_LEN_0F3A19_P_2_W_0,
1941   EVEX_LEN_0F3A19_P_2_W_1,
1942   EVEX_LEN_0F3A1A_P_2_W_0,
1943   EVEX_LEN_0F3A1A_P_2_W_1,
1944   EVEX_LEN_0F3A1B_P_2_W_0,
1945   EVEX_LEN_0F3A1B_P_2_W_1,
1946   EVEX_LEN_0F3A23_P_2_W_0,
1947   EVEX_LEN_0F3A23_P_2_W_1,
1948   EVEX_LEN_0F3A38_P_2_W_0,
1949   EVEX_LEN_0F3A38_P_2_W_1,
1950   EVEX_LEN_0F3A39_P_2_W_0,
1951   EVEX_LEN_0F3A39_P_2_W_1,
1952   EVEX_LEN_0F3A3A_P_2_W_0,
1953   EVEX_LEN_0F3A3A_P_2_W_1,
1954   EVEX_LEN_0F3A3B_P_2_W_0,
1955   EVEX_LEN_0F3A3B_P_2_W_1,
1956   EVEX_LEN_0F3A43_P_2_W_0,
1957   EVEX_LEN_0F3A43_P_2_W_1
1958 };
1959
1960 enum
1961 {
1962   VEX_W_0F41_P_0_LEN_1 = 0,
1963   VEX_W_0F41_P_2_LEN_1,
1964   VEX_W_0F42_P_0_LEN_1,
1965   VEX_W_0F42_P_2_LEN_1,
1966   VEX_W_0F44_P_0_LEN_0,
1967   VEX_W_0F44_P_2_LEN_0,
1968   VEX_W_0F45_P_0_LEN_1,
1969   VEX_W_0F45_P_2_LEN_1,
1970   VEX_W_0F46_P_0_LEN_1,
1971   VEX_W_0F46_P_2_LEN_1,
1972   VEX_W_0F47_P_0_LEN_1,
1973   VEX_W_0F47_P_2_LEN_1,
1974   VEX_W_0F4A_P_0_LEN_1,
1975   VEX_W_0F4A_P_2_LEN_1,
1976   VEX_W_0F4B_P_0_LEN_1,
1977   VEX_W_0F4B_P_2_LEN_1,
1978   VEX_W_0F90_P_0_LEN_0,
1979   VEX_W_0F90_P_2_LEN_0,
1980   VEX_W_0F91_P_0_LEN_0,
1981   VEX_W_0F91_P_2_LEN_0,
1982   VEX_W_0F92_P_0_LEN_0,
1983   VEX_W_0F92_P_2_LEN_0,
1984   VEX_W_0F93_P_0_LEN_0,
1985   VEX_W_0F93_P_2_LEN_0,
1986   VEX_W_0F98_P_0_LEN_0,
1987   VEX_W_0F98_P_2_LEN_0,
1988   VEX_W_0F99_P_0_LEN_0,
1989   VEX_W_0F99_P_2_LEN_0,
1990   VEX_W_0F380C_P_2,
1991   VEX_W_0F380D_P_2,
1992   VEX_W_0F380E_P_2,
1993   VEX_W_0F380F_P_2,
1994   VEX_W_0F3816_P_2,
1995   VEX_W_0F3818_P_2,
1996   VEX_W_0F3819_P_2,
1997   VEX_W_0F381A_P_2_M_0,
1998   VEX_W_0F382C_P_2_M_0,
1999   VEX_W_0F382D_P_2_M_0,
2000   VEX_W_0F382E_P_2_M_0,
2001   VEX_W_0F382F_P_2_M_0,
2002   VEX_W_0F3836_P_2,
2003   VEX_W_0F3846_P_2,
2004   VEX_W_0F3858_P_2,
2005   VEX_W_0F3859_P_2,
2006   VEX_W_0F385A_P_2_M_0,
2007   VEX_W_0F3878_P_2,
2008   VEX_W_0F3879_P_2,
2009   VEX_W_0F38CF_P_2,
2010   VEX_W_0F3A00_P_2,
2011   VEX_W_0F3A01_P_2,
2012   VEX_W_0F3A02_P_2,
2013   VEX_W_0F3A04_P_2,
2014   VEX_W_0F3A05_P_2,
2015   VEX_W_0F3A06_P_2,
2016   VEX_W_0F3A18_P_2,
2017   VEX_W_0F3A19_P_2,
2018   VEX_W_0F3A30_P_2_LEN_0,
2019   VEX_W_0F3A31_P_2_LEN_0,
2020   VEX_W_0F3A32_P_2_LEN_0,
2021   VEX_W_0F3A33_P_2_LEN_0,
2022   VEX_W_0F3A38_P_2,
2023   VEX_W_0F3A39_P_2,
2024   VEX_W_0F3A46_P_2,
2025   VEX_W_0F3A48_P_2,
2026   VEX_W_0F3A49_P_2,
2027   VEX_W_0F3A4A_P_2,
2028   VEX_W_0F3A4B_P_2,
2029   VEX_W_0F3A4C_P_2,
2030   VEX_W_0F3ACE_P_2,
2031   VEX_W_0F3ACF_P_2,
2032
2033   EVEX_W_0F10_P_1,
2034   EVEX_W_0F10_P_3,
2035   EVEX_W_0F11_P_1,
2036   EVEX_W_0F11_P_3,
2037   EVEX_W_0F12_P_0_M_1,
2038   EVEX_W_0F12_P_1,
2039   EVEX_W_0F12_P_3,
2040   EVEX_W_0F16_P_0_M_1,
2041   EVEX_W_0F16_P_1,
2042   EVEX_W_0F2A_P_3,
2043   EVEX_W_0F51_P_1,
2044   EVEX_W_0F51_P_3,
2045   EVEX_W_0F58_P_1,
2046   EVEX_W_0F58_P_3,
2047   EVEX_W_0F59_P_1,
2048   EVEX_W_0F59_P_3,
2049   EVEX_W_0F5A_P_0,
2050   EVEX_W_0F5A_P_1,
2051   EVEX_W_0F5A_P_2,
2052   EVEX_W_0F5A_P_3,
2053   EVEX_W_0F5B_P_0,
2054   EVEX_W_0F5B_P_1,
2055   EVEX_W_0F5B_P_2,
2056   EVEX_W_0F5C_P_1,
2057   EVEX_W_0F5C_P_3,
2058   EVEX_W_0F5D_P_1,
2059   EVEX_W_0F5D_P_3,
2060   EVEX_W_0F5E_P_1,
2061   EVEX_W_0F5E_P_3,
2062   EVEX_W_0F5F_P_1,
2063   EVEX_W_0F5F_P_3,
2064   EVEX_W_0F62_P_2,
2065   EVEX_W_0F66_P_2,
2066   EVEX_W_0F6A_P_2,
2067   EVEX_W_0F6B_P_2,
2068   EVEX_W_0F6C_P_2,
2069   EVEX_W_0F6D_P_2,
2070   EVEX_W_0F6F_P_1,
2071   EVEX_W_0F6F_P_2,
2072   EVEX_W_0F6F_P_3,
2073   EVEX_W_0F70_P_2,
2074   EVEX_W_0F72_R_2_P_2,
2075   EVEX_W_0F72_R_6_P_2,
2076   EVEX_W_0F73_R_2_P_2,
2077   EVEX_W_0F73_R_6_P_2,
2078   EVEX_W_0F76_P_2,
2079   EVEX_W_0F78_P_0,
2080   EVEX_W_0F78_P_2,
2081   EVEX_W_0F79_P_0,
2082   EVEX_W_0F79_P_2,
2083   EVEX_W_0F7A_P_1,
2084   EVEX_W_0F7A_P_2,
2085   EVEX_W_0F7A_P_3,
2086   EVEX_W_0F7B_P_2,
2087   EVEX_W_0F7B_P_3,
2088   EVEX_W_0F7E_P_1,
2089   EVEX_W_0F7F_P_1,
2090   EVEX_W_0F7F_P_2,
2091   EVEX_W_0F7F_P_3,
2092   EVEX_W_0FC2_P_1,
2093   EVEX_W_0FC2_P_3,
2094   EVEX_W_0FD2_P_2,
2095   EVEX_W_0FD3_P_2,
2096   EVEX_W_0FD4_P_2,
2097   EVEX_W_0FD6_P_2,
2098   EVEX_W_0FE6_P_1,
2099   EVEX_W_0FE6_P_2,
2100   EVEX_W_0FE6_P_3,
2101   EVEX_W_0FE7_P_2,
2102   EVEX_W_0FF2_P_2,
2103   EVEX_W_0FF3_P_2,
2104   EVEX_W_0FF4_P_2,
2105   EVEX_W_0FFA_P_2,
2106   EVEX_W_0FFB_P_2,
2107   EVEX_W_0FFE_P_2,
2108   EVEX_W_0F380C_P_2,
2109   EVEX_W_0F380D_P_2,
2110   EVEX_W_0F3810_P_1,
2111   EVEX_W_0F3810_P_2,
2112   EVEX_W_0F3811_P_1,
2113   EVEX_W_0F3811_P_2,
2114   EVEX_W_0F3812_P_1,
2115   EVEX_W_0F3812_P_2,
2116   EVEX_W_0F3813_P_1,
2117   EVEX_W_0F3813_P_2,
2118   EVEX_W_0F3814_P_1,
2119   EVEX_W_0F3815_P_1,
2120   EVEX_W_0F3818_P_2,
2121   EVEX_W_0F3819_P_2,
2122   EVEX_W_0F381A_P_2,
2123   EVEX_W_0F381B_P_2,
2124   EVEX_W_0F381E_P_2,
2125   EVEX_W_0F381F_P_2,
2126   EVEX_W_0F3820_P_1,
2127   EVEX_W_0F3821_P_1,
2128   EVEX_W_0F3822_P_1,
2129   EVEX_W_0F3823_P_1,
2130   EVEX_W_0F3824_P_1,
2131   EVEX_W_0F3825_P_1,
2132   EVEX_W_0F3825_P_2,
2133   EVEX_W_0F3826_P_1,
2134   EVEX_W_0F3826_P_2,
2135   EVEX_W_0F3828_P_1,
2136   EVEX_W_0F3828_P_2,
2137   EVEX_W_0F3829_P_1,
2138   EVEX_W_0F3829_P_2,
2139   EVEX_W_0F382A_P_1,
2140   EVEX_W_0F382A_P_2,
2141   EVEX_W_0F382B_P_2,
2142   EVEX_W_0F3830_P_1,
2143   EVEX_W_0F3831_P_1,
2144   EVEX_W_0F3832_P_1,
2145   EVEX_W_0F3833_P_1,
2146   EVEX_W_0F3834_P_1,
2147   EVEX_W_0F3835_P_1,
2148   EVEX_W_0F3835_P_2,
2149   EVEX_W_0F3837_P_2,
2150   EVEX_W_0F3838_P_1,
2151   EVEX_W_0F3839_P_1,
2152   EVEX_W_0F383A_P_1,
2153   EVEX_W_0F3840_P_2,
2154   EVEX_W_0F3852_P_1,
2155   EVEX_W_0F3854_P_2,
2156   EVEX_W_0F3855_P_2,
2157   EVEX_W_0F3858_P_2,
2158   EVEX_W_0F3859_P_2,
2159   EVEX_W_0F385A_P_2,
2160   EVEX_W_0F385B_P_2,
2161   EVEX_W_0F3862_P_2,
2162   EVEX_W_0F3863_P_2,
2163   EVEX_W_0F3866_P_2,
2164   EVEX_W_0F3868_P_3,
2165   EVEX_W_0F3870_P_2,
2166   EVEX_W_0F3871_P_2,
2167   EVEX_W_0F3872_P_1,
2168   EVEX_W_0F3872_P_2,
2169   EVEX_W_0F3872_P_3,
2170   EVEX_W_0F3873_P_2,
2171   EVEX_W_0F3875_P_2,
2172   EVEX_W_0F3878_P_2,
2173   EVEX_W_0F3879_P_2,
2174   EVEX_W_0F387A_P_2,
2175   EVEX_W_0F387B_P_2,
2176   EVEX_W_0F387D_P_2,
2177   EVEX_W_0F3883_P_2,
2178   EVEX_W_0F388D_P_2,
2179   EVEX_W_0F3891_P_2,
2180   EVEX_W_0F3893_P_2,
2181   EVEX_W_0F38A1_P_2,
2182   EVEX_W_0F38A3_P_2,
2183   EVEX_W_0F38C7_R_1_P_2,
2184   EVEX_W_0F38C7_R_2_P_2,
2185   EVEX_W_0F38C7_R_5_P_2,
2186   EVEX_W_0F38C7_R_6_P_2,
2187
2188   EVEX_W_0F3A00_P_2,
2189   EVEX_W_0F3A01_P_2,
2190   EVEX_W_0F3A04_P_2,
2191   EVEX_W_0F3A05_P_2,
2192   EVEX_W_0F3A08_P_2,
2193   EVEX_W_0F3A09_P_2,
2194   EVEX_W_0F3A0A_P_2,
2195   EVEX_W_0F3A0B_P_2,
2196   EVEX_W_0F3A18_P_2,
2197   EVEX_W_0F3A19_P_2,
2198   EVEX_W_0F3A1A_P_2,
2199   EVEX_W_0F3A1B_P_2,
2200   EVEX_W_0F3A1D_P_2,
2201   EVEX_W_0F3A21_P_2,
2202   EVEX_W_0F3A23_P_2,
2203   EVEX_W_0F3A38_P_2,
2204   EVEX_W_0F3A39_P_2,
2205   EVEX_W_0F3A3A_P_2,
2206   EVEX_W_0F3A3B_P_2,
2207   EVEX_W_0F3A3E_P_2,
2208   EVEX_W_0F3A3F_P_2,
2209   EVEX_W_0F3A42_P_2,
2210   EVEX_W_0F3A43_P_2,
2211   EVEX_W_0F3A50_P_2,
2212   EVEX_W_0F3A51_P_2,
2213   EVEX_W_0F3A56_P_2,
2214   EVEX_W_0F3A57_P_2,
2215   EVEX_W_0F3A66_P_2,
2216   EVEX_W_0F3A67_P_2,
2217   EVEX_W_0F3A70_P_2,
2218   EVEX_W_0F3A71_P_2,
2219   EVEX_W_0F3A72_P_2,
2220   EVEX_W_0F3A73_P_2,
2221   EVEX_W_0F3ACE_P_2,
2222   EVEX_W_0F3ACF_P_2
2223 };
2224
2225 typedef void (*op_rtn) (int bytemode, int sizeflag);
2226
2227 struct dis386 {
2228   const char *name;
2229   struct
2230     {
2231       op_rtn rtn;
2232       int bytemode;
2233     } op[MAX_OPERANDS];
2234   unsigned int prefix_requirement;
2235 };
2236
2237 /* Upper case letters in the instruction names here are macros.
2238    'A' => print 'b' if no register operands or suffix_always is true
2239    'B' => print 'b' if suffix_always is true
2240    'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2241           size prefix
2242    'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2243           suffix_always is true
2244    'E' => print 'e' if 32-bit form of jcxz
2245    'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2246    'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2247    'H' => print ",pt" or ",pn" branch hint
2248    'I' unused.
2249    'J' unused.
2250    'K' => print 'd' or 'q' if rex prefix is present.
2251    'L' => print 'l' if suffix_always is true
2252    'M' => print 'r' if intel_mnemonic is false.
2253    'N' => print 'n' if instruction has no wait "prefix"
2254    'O' => print 'd' or 'o' (or 'q' in Intel mode)
2255    'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2256           or suffix_always is true.  print 'q' if rex prefix is present.
2257    'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2258           is true
2259    'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2260    'S' => print 'w', 'l' or 'q' if suffix_always is true
2261    'T' => print 'q' in 64bit mode if instruction has no operand size
2262           prefix and behave as 'P' otherwise
2263    'U' => print 'q' in 64bit mode if instruction has no operand size
2264           prefix and behave as 'Q' otherwise
2265    'V' => print 'q' in 64bit mode if instruction has no operand size
2266           prefix and behave as 'S' otherwise
2267    'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2268    'X' => print 's', 'd' depending on data16 prefix (for XMM)
2269    'Y' unused.
2270    'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2271    '!' => change condition from true to false or from false to true.
2272    '%' => add 1 upper case letter to the macro.
2273    '^' => print 'w', 'l', or 'q' (Intel64 ISA only) depending on operand size
2274           prefix or suffix_always is true (lcall/ljmp).
2275    '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending
2276           on operand size prefix.
2277    '&' => print 'q' in 64bit mode for Intel64 ISA or if instruction
2278           has no operand size prefix for AMD64 ISA, behave as 'P'
2279           otherwise
2280
2281    2 upper case letter macros:
2282    "XY" => print 'x' or 'y' if suffix_always is true or no register
2283            operands and no broadcast.
2284    "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
2285            register operands and no broadcast.
2286    "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2287    "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory
2288            operand or no operand at all in 64bit mode, or if suffix_always
2289            is true.
2290    "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2291    "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2292    "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2293    "LW" => print 'd', 'q' depending on the VEX.W bit
2294    "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
2295            an operand size prefix, or suffix_always is true.  print
2296            'q' if rex prefix is present.
2297
2298    Many of the above letters print nothing in Intel mode.  See "putop"
2299    for the details.
2300
2301    Braces '{' and '}', and vertical bars '|', indicate alternative
2302    mnemonic strings for AT&T and Intel.  */
2303
2304 static const struct dis386 dis386[] = {
2305   /* 00 */
2306   { "addB",             { Ebh1, Gb }, 0 },
2307   { "addS",             { Evh1, Gv }, 0 },
2308   { "addB",             { Gb, EbS }, 0 },
2309   { "addS",             { Gv, EvS }, 0 },
2310   { "addB",             { AL, Ib }, 0 },
2311   { "addS",             { eAX, Iv }, 0 },
2312   { X86_64_TABLE (X86_64_06) },
2313   { X86_64_TABLE (X86_64_07) },
2314   /* 08 */
2315   { "orB",              { Ebh1, Gb }, 0 },
2316   { "orS",              { Evh1, Gv }, 0 },
2317   { "orB",              { Gb, EbS }, 0 },
2318   { "orS",              { Gv, EvS }, 0 },
2319   { "orB",              { AL, Ib }, 0 },
2320   { "orS",              { eAX, Iv }, 0 },
2321   { X86_64_TABLE (X86_64_0E) },
2322   { Bad_Opcode },       /* 0x0f extended opcode escape */
2323   /* 10 */
2324   { "adcB",             { Ebh1, Gb }, 0 },
2325   { "adcS",             { Evh1, Gv }, 0 },
2326   { "adcB",             { Gb, EbS }, 0 },
2327   { "adcS",             { Gv, EvS }, 0 },
2328   { "adcB",             { AL, Ib }, 0 },
2329   { "adcS",             { eAX, Iv }, 0 },
2330   { X86_64_TABLE (X86_64_16) },
2331   { X86_64_TABLE (X86_64_17) },
2332   /* 18 */
2333   { "sbbB",             { Ebh1, Gb }, 0 },
2334   { "sbbS",             { Evh1, Gv }, 0 },
2335   { "sbbB",             { Gb, EbS }, 0 },
2336   { "sbbS",             { Gv, EvS }, 0 },
2337   { "sbbB",             { AL, Ib }, 0 },
2338   { "sbbS",             { eAX, Iv }, 0 },
2339   { X86_64_TABLE (X86_64_1E) },
2340   { X86_64_TABLE (X86_64_1F) },
2341   /* 20 */
2342   { "andB",             { Ebh1, Gb }, 0 },
2343   { "andS",             { Evh1, Gv }, 0 },
2344   { "andB",             { Gb, EbS }, 0 },
2345   { "andS",             { Gv, EvS }, 0 },
2346   { "andB",             { AL, Ib }, 0 },
2347   { "andS",             { eAX, Iv }, 0 },
2348   { Bad_Opcode },       /* SEG ES prefix */
2349   { X86_64_TABLE (X86_64_27) },
2350   /* 28 */
2351   { "subB",             { Ebh1, Gb }, 0 },
2352   { "subS",             { Evh1, Gv }, 0 },
2353   { "subB",             { Gb, EbS }, 0 },
2354   { "subS",             { Gv, EvS }, 0 },
2355   { "subB",             { AL, Ib }, 0 },
2356   { "subS",             { eAX, Iv }, 0 },
2357   { Bad_Opcode },       /* SEG CS prefix */
2358   { X86_64_TABLE (X86_64_2F) },
2359   /* 30 */
2360   { "xorB",             { Ebh1, Gb }, 0 },
2361   { "xorS",             { Evh1, Gv }, 0 },
2362   { "xorB",             { Gb, EbS }, 0 },
2363   { "xorS",             { Gv, EvS }, 0 },
2364   { "xorB",             { AL, Ib }, 0 },
2365   { "xorS",             { eAX, Iv }, 0 },
2366   { Bad_Opcode },       /* SEG SS prefix */
2367   { X86_64_TABLE (X86_64_37) },
2368   /* 38 */
2369   { "cmpB",             { Eb, Gb }, 0 },
2370   { "cmpS",             { Ev, Gv }, 0 },
2371   { "cmpB",             { Gb, EbS }, 0 },
2372   { "cmpS",             { Gv, EvS }, 0 },
2373   { "cmpB",             { AL, Ib }, 0 },
2374   { "cmpS",             { eAX, Iv }, 0 },
2375   { Bad_Opcode },       /* SEG DS prefix */
2376   { X86_64_TABLE (X86_64_3F) },
2377   /* 40 */
2378   { "inc{S|}",          { RMeAX }, 0 },
2379   { "inc{S|}",          { RMeCX }, 0 },
2380   { "inc{S|}",          { RMeDX }, 0 },
2381   { "inc{S|}",          { RMeBX }, 0 },
2382   { "inc{S|}",          { RMeSP }, 0 },
2383   { "inc{S|}",          { RMeBP }, 0 },
2384   { "inc{S|}",          { RMeSI }, 0 },
2385   { "inc{S|}",          { RMeDI }, 0 },
2386   /* 48 */
2387   { "dec{S|}",          { RMeAX }, 0 },
2388   { "dec{S|}",          { RMeCX }, 0 },
2389   { "dec{S|}",          { RMeDX }, 0 },
2390   { "dec{S|}",          { RMeBX }, 0 },
2391   { "dec{S|}",          { RMeSP }, 0 },
2392   { "dec{S|}",          { RMeBP }, 0 },
2393   { "dec{S|}",          { RMeSI }, 0 },
2394   { "dec{S|}",          { RMeDI }, 0 },
2395   /* 50 */
2396   { "pushV",            { RMrAX }, 0 },
2397   { "pushV",            { RMrCX }, 0 },
2398   { "pushV",            { RMrDX }, 0 },
2399   { "pushV",            { RMrBX }, 0 },
2400   { "pushV",            { RMrSP }, 0 },
2401   { "pushV",            { RMrBP }, 0 },
2402   { "pushV",            { RMrSI }, 0 },
2403   { "pushV",            { RMrDI }, 0 },
2404   /* 58 */
2405   { "popV",             { RMrAX }, 0 },
2406   { "popV",             { RMrCX }, 0 },
2407   { "popV",             { RMrDX }, 0 },
2408   { "popV",             { RMrBX }, 0 },
2409   { "popV",             { RMrSP }, 0 },
2410   { "popV",             { RMrBP }, 0 },
2411   { "popV",             { RMrSI }, 0 },
2412   { "popV",             { RMrDI }, 0 },
2413   /* 60 */
2414   { X86_64_TABLE (X86_64_60) },
2415   { X86_64_TABLE (X86_64_61) },
2416   { X86_64_TABLE (X86_64_62) },
2417   { X86_64_TABLE (X86_64_63) },
2418   { Bad_Opcode },       /* seg fs */
2419   { Bad_Opcode },       /* seg gs */
2420   { Bad_Opcode },       /* op size prefix */
2421   { Bad_Opcode },       /* adr size prefix */
2422   /* 68 */
2423   { "pushT",            { sIv }, 0 },
2424   { "imulS",            { Gv, Ev, Iv }, 0 },
2425   { "pushT",            { sIbT }, 0 },
2426   { "imulS",            { Gv, Ev, sIb }, 0 },
2427   { "ins{b|}",          { Ybr, indirDX }, 0 },
2428   { X86_64_TABLE (X86_64_6D) },
2429   { "outs{b|}",         { indirDXr, Xb }, 0 },
2430   { X86_64_TABLE (X86_64_6F) },
2431   /* 70 */
2432   { "joH",              { Jb, BND, cond_jump_flag }, 0 },
2433   { "jnoH",             { Jb, BND, cond_jump_flag }, 0 },
2434   { "jbH",              { Jb, BND, cond_jump_flag }, 0 },
2435   { "jaeH",             { Jb, BND, cond_jump_flag }, 0 },
2436   { "jeH",              { Jb, BND, cond_jump_flag }, 0 },
2437   { "jneH",             { Jb, BND, cond_jump_flag }, 0 },
2438   { "jbeH",             { Jb, BND, cond_jump_flag }, 0 },
2439   { "jaH",              { Jb, BND, cond_jump_flag }, 0 },
2440   /* 78 */
2441   { "jsH",              { Jb, BND, cond_jump_flag }, 0 },
2442   { "jnsH",             { Jb, BND, cond_jump_flag }, 0 },
2443   { "jpH",              { Jb, BND, cond_jump_flag }, 0 },
2444   { "jnpH",             { Jb, BND, cond_jump_flag }, 0 },
2445   { "jlH",              { Jb, BND, cond_jump_flag }, 0 },
2446   { "jgeH",             { Jb, BND, cond_jump_flag }, 0 },
2447   { "jleH",             { Jb, BND, cond_jump_flag }, 0 },
2448   { "jgH",              { Jb, BND, cond_jump_flag }, 0 },
2449   /* 80 */
2450   { REG_TABLE (REG_80) },
2451   { REG_TABLE (REG_81) },
2452   { X86_64_TABLE (X86_64_82) },
2453   { REG_TABLE (REG_83) },
2454   { "testB",            { Eb, Gb }, 0 },
2455   { "testS",            { Ev, Gv }, 0 },
2456   { "xchgB",            { Ebh2, Gb }, 0 },
2457   { "xchgS",            { Evh2, Gv }, 0 },
2458   /* 88 */
2459   { "movB",             { Ebh3, Gb }, 0 },
2460   { "movS",             { Evh3, Gv }, 0 },
2461   { "movB",             { Gb, EbS }, 0 },
2462   { "movS",             { Gv, EvS }, 0 },
2463   { "movD",             { Sv, Sw }, 0 },
2464   { MOD_TABLE (MOD_8D) },
2465   { "movD",             { Sw, Sv }, 0 },
2466   { REG_TABLE (REG_8F) },
2467   /* 90 */
2468   { PREFIX_TABLE (PREFIX_90) },
2469   { "xchgS",            { RMeCX, eAX }, 0 },
2470   { "xchgS",            { RMeDX, eAX }, 0 },
2471   { "xchgS",            { RMeBX, eAX }, 0 },
2472   { "xchgS",            { RMeSP, eAX }, 0 },
2473   { "xchgS",            { RMeBP, eAX }, 0 },
2474   { "xchgS",            { RMeSI, eAX }, 0 },
2475   { "xchgS",            { RMeDI, eAX }, 0 },
2476   /* 98 */
2477   { "cW{t|}R",          { XX }, 0 },
2478   { "cR{t|}O",          { XX }, 0 },
2479   { X86_64_TABLE (X86_64_9A) },
2480   { Bad_Opcode },       /* fwait */
2481   { "pushfT",           { XX }, 0 },
2482   { "popfT",            { XX }, 0 },
2483   { "sahf",             { XX }, 0 },
2484   { "lahf",             { XX }, 0 },
2485   /* a0 */
2486   { "mov%LB",           { AL, Ob }, 0 },
2487   { "mov%LS",           { eAX, Ov }, 0 },
2488   { "mov%LB",           { Ob, AL }, 0 },
2489   { "mov%LS",           { Ov, eAX }, 0 },
2490   { "movs{b|}",         { Ybr, Xb }, 0 },
2491   { "movs{R|}",         { Yvr, Xv }, 0 },
2492   { "cmps{b|}",         { Xb, Yb }, 0 },
2493   { "cmps{R|}",         { Xv, Yv }, 0 },
2494   /* a8 */
2495   { "testB",            { AL, Ib }, 0 },
2496   { "testS",            { eAX, Iv }, 0 },
2497   { "stosB",            { Ybr, AL }, 0 },
2498   { "stosS",            { Yvr, eAX }, 0 },
2499   { "lodsB",            { ALr, Xb }, 0 },
2500   { "lodsS",            { eAXr, Xv }, 0 },
2501   { "scasB",            { AL, Yb }, 0 },
2502   { "scasS",            { eAX, Yv }, 0 },
2503   /* b0 */
2504   { "movB",             { RMAL, Ib }, 0 },
2505   { "movB",             { RMCL, Ib }, 0 },
2506   { "movB",             { RMDL, Ib }, 0 },
2507   { "movB",             { RMBL, Ib }, 0 },
2508   { "movB",             { RMAH, Ib }, 0 },
2509   { "movB",             { RMCH, Ib }, 0 },
2510   { "movB",             { RMDH, Ib }, 0 },
2511   { "movB",             { RMBH, Ib }, 0 },
2512   /* b8 */
2513   { "mov%LV",           { RMeAX, Iv64 }, 0 },
2514   { "mov%LV",           { RMeCX, Iv64 }, 0 },
2515   { "mov%LV",           { RMeDX, Iv64 }, 0 },
2516   { "mov%LV",           { RMeBX, Iv64 }, 0 },
2517   { "mov%LV",           { RMeSP, Iv64 }, 0 },
2518   { "mov%LV",           { RMeBP, Iv64 }, 0 },
2519   { "mov%LV",           { RMeSI, Iv64 }, 0 },
2520   { "mov%LV",           { RMeDI, Iv64 }, 0 },
2521   /* c0 */
2522   { REG_TABLE (REG_C0) },
2523   { REG_TABLE (REG_C1) },
2524   { X86_64_TABLE (X86_64_C2) },
2525   { X86_64_TABLE (X86_64_C3) },
2526   { X86_64_TABLE (X86_64_C4) },
2527   { X86_64_TABLE (X86_64_C5) },
2528   { REG_TABLE (REG_C6) },
2529   { REG_TABLE (REG_C7) },
2530   /* c8 */
2531   { "enterT",           { Iw, Ib }, 0 },
2532   { "leaveT",           { XX }, 0 },
2533   { "{l|}ret{|f}P",     { Iw }, 0 },
2534   { "{l|}ret{|f}P",     { XX }, 0 },
2535   { "int3",             { XX }, 0 },
2536   { "int",              { Ib }, 0 },
2537   { X86_64_TABLE (X86_64_CE) },
2538   { "iret%LP",          { XX }, 0 },
2539   /* d0 */
2540   { REG_TABLE (REG_D0) },
2541   { REG_TABLE (REG_D1) },
2542   { REG_TABLE (REG_D2) },
2543   { REG_TABLE (REG_D3) },
2544   { X86_64_TABLE (X86_64_D4) },
2545   { X86_64_TABLE (X86_64_D5) },
2546   { Bad_Opcode },
2547   { "xlat",             { DSBX }, 0 },
2548   /* d8 */
2549   { FLOAT },
2550   { FLOAT },
2551   { FLOAT },
2552   { FLOAT },
2553   { FLOAT },
2554   { FLOAT },
2555   { FLOAT },
2556   { FLOAT },
2557   /* e0 */
2558   { "loopneFH",         { Jb, XX, loop_jcxz_flag }, 0 },
2559   { "loopeFH",          { Jb, XX, loop_jcxz_flag }, 0 },
2560   { "loopFH",           { Jb, XX, loop_jcxz_flag }, 0 },
2561   { "jEcxzH",           { Jb, XX, loop_jcxz_flag }, 0 },
2562   { "inB",              { AL, Ib }, 0 },
2563   { "inG",              { zAX, Ib }, 0 },
2564   { "outB",             { Ib, AL }, 0 },
2565   { "outG",             { Ib, zAX }, 0 },
2566   /* e8 */
2567   { X86_64_TABLE (X86_64_E8) },
2568   { X86_64_TABLE (X86_64_E9) },
2569   { X86_64_TABLE (X86_64_EA) },
2570   { "jmp",              { Jb, BND }, 0 },
2571   { "inB",              { AL, indirDX }, 0 },
2572   { "inG",              { zAX, indirDX }, 0 },
2573   { "outB",             { indirDX, AL }, 0 },
2574   { "outG",             { indirDX, zAX }, 0 },
2575   /* f0 */
2576   { Bad_Opcode },       /* lock prefix */
2577   { "icebp",            { XX }, 0 },
2578   { Bad_Opcode },       /* repne */
2579   { Bad_Opcode },       /* repz */
2580   { "hlt",              { XX }, 0 },
2581   { "cmc",              { XX }, 0 },
2582   { REG_TABLE (REG_F6) },
2583   { REG_TABLE (REG_F7) },
2584   /* f8 */
2585   { "clc",              { XX }, 0 },
2586   { "stc",              { XX }, 0 },
2587   { "cli",              { XX }, 0 },
2588   { "sti",              { XX }, 0 },
2589   { "cld",              { XX }, 0 },
2590   { "std",              { XX }, 0 },
2591   { REG_TABLE (REG_FE) },
2592   { REG_TABLE (REG_FF) },
2593 };
2594
2595 static const struct dis386 dis386_twobyte[] = {
2596   /* 00 */
2597   { REG_TABLE (REG_0F00 ) },
2598   { REG_TABLE (REG_0F01 ) },
2599   { "larS",             { Gv, Ew }, 0 },
2600   { "lslS",             { Gv, Ew }, 0 },
2601   { Bad_Opcode },
2602   { "syscall",          { XX }, 0 },
2603   { "clts",             { XX }, 0 },
2604   { "sysret%LQ",                { XX }, 0 },
2605   /* 08 */
2606   { "invd",             { XX }, 0 },
2607   { PREFIX_TABLE (PREFIX_0F09) },
2608   { Bad_Opcode },
2609   { "ud2",              { XX }, 0 },
2610   { Bad_Opcode },
2611   { REG_TABLE (REG_0F0D) },
2612   { "femms",            { XX }, 0 },
2613   { "",                 { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix.  */
2614   /* 10 */
2615   { PREFIX_TABLE (PREFIX_0F10) },
2616   { PREFIX_TABLE (PREFIX_0F11) },
2617   { PREFIX_TABLE (PREFIX_0F12) },
2618   { MOD_TABLE (MOD_0F13) },
2619   { "unpcklpX",         { XM, EXx }, PREFIX_OPCODE },
2620   { "unpckhpX",         { XM, EXx }, PREFIX_OPCODE },
2621   { PREFIX_TABLE (PREFIX_0F16) },
2622   { MOD_TABLE (MOD_0F17) },
2623   /* 18 */
2624   { REG_TABLE (REG_0F18) },
2625   { "nopQ",             { Ev }, 0 },
2626   { PREFIX_TABLE (PREFIX_0F1A) },
2627   { PREFIX_TABLE (PREFIX_0F1B) },
2628   { PREFIX_TABLE (PREFIX_0F1C) },
2629   { "nopQ",             { Ev }, 0 },
2630   { PREFIX_TABLE (PREFIX_0F1E) },
2631   { "nopQ",             { Ev }, 0 },
2632   /* 20 */
2633   { "movZ",             { Rm, Cm }, 0 },
2634   { "movZ",             { Rm, Dm }, 0 },
2635   { "movZ",             { Cm, Rm }, 0 },
2636   { "movZ",             { Dm, Rm }, 0 },
2637   { MOD_TABLE (MOD_0F24) },
2638   { Bad_Opcode },
2639   { MOD_TABLE (MOD_0F26) },
2640   { Bad_Opcode },
2641   /* 28 */
2642   { "movapX",           { XM, EXx }, PREFIX_OPCODE },
2643   { "movapX",           { EXxS, XM }, PREFIX_OPCODE },
2644   { PREFIX_TABLE (PREFIX_0F2A) },
2645   { PREFIX_TABLE (PREFIX_0F2B) },
2646   { PREFIX_TABLE (PREFIX_0F2C) },
2647   { PREFIX_TABLE (PREFIX_0F2D) },
2648   { PREFIX_TABLE (PREFIX_0F2E) },
2649   { PREFIX_TABLE (PREFIX_0F2F) },
2650   /* 30 */
2651   { "wrmsr",            { XX }, 0 },
2652   { "rdtsc",            { XX }, 0 },
2653   { "rdmsr",            { XX }, 0 },
2654   { "rdpmc",            { XX }, 0 },
2655   { "sysenter",         { SEP }, 0 },
2656   { "sysexit",          { SEP }, 0 },
2657   { Bad_Opcode },
2658   { "getsec",           { XX }, 0 },
2659   /* 38 */
2660   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) },
2661   { Bad_Opcode },
2662   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) },
2663   { Bad_Opcode },
2664   { Bad_Opcode },
2665   { Bad_Opcode },
2666   { Bad_Opcode },
2667   { Bad_Opcode },
2668   /* 40 */
2669   { "cmovoS",           { Gv, Ev }, 0 },
2670   { "cmovnoS",          { Gv, Ev }, 0 },
2671   { "cmovbS",           { Gv, Ev }, 0 },
2672   { "cmovaeS",          { Gv, Ev }, 0 },
2673   { "cmoveS",           { Gv, Ev }, 0 },
2674   { "cmovneS",          { Gv, Ev }, 0 },
2675   { "cmovbeS",          { Gv, Ev }, 0 },
2676   { "cmovaS",           { Gv, Ev }, 0 },
2677   /* 48 */
2678   { "cmovsS",           { Gv, Ev }, 0 },
2679   { "cmovnsS",          { Gv, Ev }, 0 },
2680   { "cmovpS",           { Gv, Ev }, 0 },
2681   { "cmovnpS",          { Gv, Ev }, 0 },
2682   { "cmovlS",           { Gv, Ev }, 0 },
2683   { "cmovgeS",          { Gv, Ev }, 0 },
2684   { "cmovleS",          { Gv, Ev }, 0 },
2685   { "cmovgS",           { Gv, Ev }, 0 },
2686   /* 50 */
2687   { MOD_TABLE (MOD_0F50) },
2688   { PREFIX_TABLE (PREFIX_0F51) },
2689   { PREFIX_TABLE (PREFIX_0F52) },
2690   { PREFIX_TABLE (PREFIX_0F53) },
2691   { "andpX",            { XM, EXx }, PREFIX_OPCODE },
2692   { "andnpX",           { XM, EXx }, PREFIX_OPCODE },
2693   { "orpX",             { XM, EXx }, PREFIX_OPCODE },
2694   { "xorpX",            { XM, EXx }, PREFIX_OPCODE },
2695   /* 58 */
2696   { PREFIX_TABLE (PREFIX_0F58) },
2697   { PREFIX_TABLE (PREFIX_0F59) },
2698   { PREFIX_TABLE (PREFIX_0F5A) },
2699   { PREFIX_TABLE (PREFIX_0F5B) },
2700   { PREFIX_TABLE (PREFIX_0F5C) },
2701   { PREFIX_TABLE (PREFIX_0F5D) },
2702   { PREFIX_TABLE (PREFIX_0F5E) },
2703   { PREFIX_TABLE (PREFIX_0F5F) },
2704   /* 60 */
2705   { PREFIX_TABLE (PREFIX_0F60) },
2706   { PREFIX_TABLE (PREFIX_0F61) },
2707   { PREFIX_TABLE (PREFIX_0F62) },
2708   { "packsswb",         { MX, EM }, PREFIX_OPCODE },
2709   { "pcmpgtb",          { MX, EM }, PREFIX_OPCODE },
2710   { "pcmpgtw",          { MX, EM }, PREFIX_OPCODE },
2711   { "pcmpgtd",          { MX, EM }, PREFIX_OPCODE },
2712   { "packuswb",         { MX, EM }, PREFIX_OPCODE },
2713   /* 68 */
2714   { "punpckhbw",        { MX, EM }, PREFIX_OPCODE },
2715   { "punpckhwd",        { MX, EM }, PREFIX_OPCODE },
2716   { "punpckhdq",        { MX, EM }, PREFIX_OPCODE },
2717   { "packssdw",         { MX, EM }, PREFIX_OPCODE },
2718   { PREFIX_TABLE (PREFIX_0F6C) },
2719   { PREFIX_TABLE (PREFIX_0F6D) },
2720   { "movK",             { MX, Edq }, PREFIX_OPCODE },
2721   { PREFIX_TABLE (PREFIX_0F6F) },
2722   /* 70 */
2723   { PREFIX_TABLE (PREFIX_0F70) },
2724   { REG_TABLE (REG_0F71) },
2725   { REG_TABLE (REG_0F72) },
2726   { REG_TABLE (REG_0F73) },
2727   { "pcmpeqb",          { MX, EM }, PREFIX_OPCODE },
2728   { "pcmpeqw",          { MX, EM }, PREFIX_OPCODE },
2729   { "pcmpeqd",          { MX, EM }, PREFIX_OPCODE },
2730   { "emms",             { XX }, PREFIX_OPCODE },
2731   /* 78 */
2732   { PREFIX_TABLE (PREFIX_0F78) },
2733   { PREFIX_TABLE (PREFIX_0F79) },
2734   { Bad_Opcode },
2735   { Bad_Opcode },
2736   { PREFIX_TABLE (PREFIX_0F7C) },
2737   { PREFIX_TABLE (PREFIX_0F7D) },
2738   { PREFIX_TABLE (PREFIX_0F7E) },
2739   { PREFIX_TABLE (PREFIX_0F7F) },
2740   /* 80 */
2741   { "joH",              { Jv, BND, cond_jump_flag }, 0 },
2742   { "jnoH",             { Jv, BND, cond_jump_flag }, 0 },
2743   { "jbH",              { Jv, BND, cond_jump_flag }, 0 },
2744   { "jaeH",             { Jv, BND, cond_jump_flag }, 0 },
2745   { "jeH",              { Jv, BND, cond_jump_flag }, 0 },
2746   { "jneH",             { Jv, BND, cond_jump_flag }, 0 },
2747   { "jbeH",             { Jv, BND, cond_jump_flag }, 0 },
2748   { "jaH",              { Jv, BND, cond_jump_flag }, 0 },
2749   /* 88 */
2750   { "jsH",              { Jv, BND, cond_jump_flag }, 0 },
2751   { "jnsH",             { Jv, BND, cond_jump_flag }, 0 },
2752   { "jpH",              { Jv, BND, cond_jump_flag }, 0 },
2753   { "jnpH",             { Jv, BND, cond_jump_flag }, 0 },
2754   { "jlH",              { Jv, BND, cond_jump_flag }, 0 },
2755   { "jgeH",             { Jv, BND, cond_jump_flag }, 0 },
2756   { "jleH",             { Jv, BND, cond_jump_flag }, 0 },
2757   { "jgH",              { Jv, BND, cond_jump_flag }, 0 },
2758   /* 90 */
2759   { "seto",             { Eb }, 0 },
2760   { "setno",            { Eb }, 0 },
2761   { "setb",             { Eb }, 0 },
2762   { "setae",            { Eb }, 0 },
2763   { "sete",             { Eb }, 0 },
2764   { "setne",            { Eb }, 0 },
2765   { "setbe",            { Eb }, 0 },
2766   { "seta",             { Eb }, 0 },
2767   /* 98 */
2768   { "sets",             { Eb }, 0 },
2769   { "setns",            { Eb }, 0 },
2770   { "setp",             { Eb }, 0 },
2771   { "setnp",            { Eb }, 0 },
2772   { "setl",             { Eb }, 0 },
2773   { "setge",            { Eb }, 0 },
2774   { "setle",            { Eb }, 0 },
2775   { "setg",             { Eb }, 0 },
2776   /* a0 */
2777   { "pushT",            { fs }, 0 },
2778   { "popT",             { fs }, 0 },
2779   { "cpuid",            { XX }, 0 },
2780   { "btS",              { Ev, Gv }, 0 },
2781   { "shldS",            { Ev, Gv, Ib }, 0 },
2782   { "shldS",            { Ev, Gv, CL }, 0 },
2783   { REG_TABLE (REG_0FA6) },
2784   { REG_TABLE (REG_0FA7) },
2785   /* a8 */
2786   { "pushT",            { gs }, 0 },
2787   { "popT",             { gs }, 0 },
2788   { "rsm",              { XX }, 0 },
2789   { "btsS",             { Evh1, Gv }, 0 },
2790   { "shrdS",            { Ev, Gv, Ib }, 0 },
2791   { "shrdS",            { Ev, Gv, CL }, 0 },
2792   { REG_TABLE (REG_0FAE) },
2793   { "imulS",            { Gv, Ev }, 0 },
2794   /* b0 */
2795   { "cmpxchgB",         { Ebh1, Gb }, 0 },
2796   { "cmpxchgS",         { Evh1, Gv }, 0 },
2797   { MOD_TABLE (MOD_0FB2) },
2798   { "btrS",             { Evh1, Gv }, 0 },
2799   { MOD_TABLE (MOD_0FB4) },
2800   { MOD_TABLE (MOD_0FB5) },
2801   { "movz{bR|x}",       { Gv, Eb }, 0 },
2802   { "movz{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movzww ! */
2803   /* b8 */
2804   { PREFIX_TABLE (PREFIX_0FB8) },
2805   { "ud1S",             { Gv, Ev }, 0 },
2806   { REG_TABLE (REG_0FBA) },
2807   { "btcS",             { Evh1, Gv }, 0 },
2808   { PREFIX_TABLE (PREFIX_0FBC) },
2809   { PREFIX_TABLE (PREFIX_0FBD) },
2810   { "movs{bR|x}",       { Gv, Eb }, 0 },
2811   { "movs{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movsww ! */
2812   /* c0 */
2813   { "xaddB",            { Ebh1, Gb }, 0 },
2814   { "xaddS",            { Evh1, Gv }, 0 },
2815   { PREFIX_TABLE (PREFIX_0FC2) },
2816   { MOD_TABLE (MOD_0FC3) },
2817   { "pinsrw",           { MX, Edqw, Ib }, PREFIX_OPCODE },
2818   { "pextrw",           { Gdq, MS, Ib }, PREFIX_OPCODE },
2819   { "shufpX",           { XM, EXx, Ib }, PREFIX_OPCODE },
2820   { REG_TABLE (REG_0FC7) },
2821   /* c8 */
2822   { "bswap",            { RMeAX }, 0 },
2823   { "bswap",            { RMeCX }, 0 },
2824   { "bswap",            { RMeDX }, 0 },
2825   { "bswap",            { RMeBX }, 0 },
2826   { "bswap",            { RMeSP }, 0 },
2827   { "bswap",            { RMeBP }, 0 },
2828   { "bswap",            { RMeSI }, 0 },
2829   { "bswap",            { RMeDI }, 0 },
2830   /* d0 */
2831   { PREFIX_TABLE (PREFIX_0FD0) },
2832   { "psrlw",            { MX, EM }, PREFIX_OPCODE },
2833   { "psrld",            { MX, EM }, PREFIX_OPCODE },
2834   { "psrlq",            { MX, EM }, PREFIX_OPCODE },
2835   { "paddq",            { MX, EM }, PREFIX_OPCODE },
2836   { "pmullw",           { MX, EM }, PREFIX_OPCODE },
2837   { PREFIX_TABLE (PREFIX_0FD6) },
2838   { MOD_TABLE (MOD_0FD7) },
2839   /* d8 */
2840   { "psubusb",          { MX, EM }, PREFIX_OPCODE },
2841   { "psubusw",          { MX, EM }, PREFIX_OPCODE },
2842   { "pminub",           { MX, EM }, PREFIX_OPCODE },
2843   { "pand",             { MX, EM }, PREFIX_OPCODE },
2844   { "paddusb",          { MX, EM }, PREFIX_OPCODE },
2845   { "paddusw",          { MX, EM }, PREFIX_OPCODE },
2846   { "pmaxub",           { MX, EM }, PREFIX_OPCODE },
2847   { "pandn",            { MX, EM }, PREFIX_OPCODE },
2848   /* e0 */
2849   { "pavgb",            { MX, EM }, PREFIX_OPCODE },
2850   { "psraw",            { MX, EM }, PREFIX_OPCODE },
2851   { "psrad",            { MX, EM }, PREFIX_OPCODE },
2852   { "pavgw",            { MX, EM }, PREFIX_OPCODE },
2853   { "pmulhuw",          { MX, EM }, PREFIX_OPCODE },
2854   { "pmulhw",           { MX, EM }, PREFIX_OPCODE },
2855   { PREFIX_TABLE (PREFIX_0FE6) },
2856   { PREFIX_TABLE (PREFIX_0FE7) },
2857   /* e8 */
2858   { "psubsb",           { MX, EM }, PREFIX_OPCODE },
2859   { "psubsw",           { MX, EM }, PREFIX_OPCODE },
2860   { "pminsw",           { MX, EM }, PREFIX_OPCODE },
2861   { "por",              { MX, EM }, PREFIX_OPCODE },
2862   { "paddsb",           { MX, EM }, PREFIX_OPCODE },
2863   { "paddsw",           { MX, EM }, PREFIX_OPCODE },
2864   { "pmaxsw",           { MX, EM }, PREFIX_OPCODE },
2865   { "pxor",             { MX, EM }, PREFIX_OPCODE },
2866   /* f0 */
2867   { PREFIX_TABLE (PREFIX_0FF0) },
2868   { "psllw",            { MX, EM }, PREFIX_OPCODE },
2869   { "pslld",            { MX, EM }, PREFIX_OPCODE },
2870   { "psllq",            { MX, EM }, PREFIX_OPCODE },
2871   { "pmuludq",          { MX, EM }, PREFIX_OPCODE },
2872   { "pmaddwd",          { MX, EM }, PREFIX_OPCODE },
2873   { "psadbw",           { MX, EM }, PREFIX_OPCODE },
2874   { PREFIX_TABLE (PREFIX_0FF7) },
2875   /* f8 */
2876   { "psubb",            { MX, EM }, PREFIX_OPCODE },
2877   { "psubw",            { MX, EM }, PREFIX_OPCODE },
2878   { "psubd",            { MX, EM }, PREFIX_OPCODE },
2879   { "psubq",            { MX, EM }, PREFIX_OPCODE },
2880   { "paddb",            { MX, EM }, PREFIX_OPCODE },
2881   { "paddw",            { MX, EM }, PREFIX_OPCODE },
2882   { "paddd",            { MX, EM }, PREFIX_OPCODE },
2883   { "ud0S",             { Gv, Ev }, 0 },
2884 };
2885
2886 static const unsigned char onebyte_has_modrm[256] = {
2887   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2888   /*       -------------------------------        */
2889   /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2890   /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2891   /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2892   /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2893   /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2894   /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2895   /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2896   /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2897   /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2898   /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2899   /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2900   /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2901   /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2902   /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2903   /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2904   /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1  /* f0 */
2905   /*       -------------------------------        */
2906   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2907 };
2908
2909 static const unsigned char twobyte_has_modrm[256] = {
2910   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2911   /*       -------------------------------        */
2912   /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2913   /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2914   /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2915   /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2916   /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2917   /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2918   /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2919   /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2920   /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2921   /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2922   /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2923   /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */
2924   /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2925   /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2926   /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2927   /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1  /* ff */
2928   /*       -------------------------------        */
2929   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2930 };
2931
2932 static char obuf[100];
2933 static char *obufp;
2934 static char *mnemonicendp;
2935 static char scratchbuf[100];
2936 static unsigned char *start_codep;
2937 static unsigned char *insn_codep;
2938 static unsigned char *codep;
2939 static unsigned char *end_codep;
2940 static int last_lock_prefix;
2941 static int last_repz_prefix;
2942 static int last_repnz_prefix;
2943 static int last_data_prefix;
2944 static int last_addr_prefix;
2945 static int last_rex_prefix;
2946 static int last_seg_prefix;
2947 static int fwait_prefix;
2948 /* The active segment register prefix.  */
2949 static int active_seg_prefix;
2950 #define MAX_CODE_LENGTH 15
2951 /* We can up to 14 prefixes since the maximum instruction length is
2952    15bytes.  */
2953 static int all_prefixes[MAX_CODE_LENGTH - 1];
2954 static disassemble_info *the_info;
2955 static struct
2956   {
2957     int mod;
2958     int reg;
2959     int rm;
2960   }
2961 modrm;
2962 static unsigned char need_modrm;
2963 static struct
2964   {
2965     int scale;
2966     int index;
2967     int base;
2968   }
2969 sib;
2970 static struct
2971   {
2972     int register_specifier;
2973     int length;
2974     int prefix;
2975     int w;
2976     int evex;
2977     int r;
2978     int v;
2979     int mask_register_specifier;
2980     int zeroing;
2981     int ll;
2982     int b;
2983   }
2984 vex;
2985 static unsigned char need_vex;
2986 static unsigned char need_vex_reg;
2987 static unsigned char vex_w_done;
2988
2989 struct op
2990   {
2991     const char *name;
2992     unsigned int len;
2993   };
2994
2995 /* If we are accessing mod/rm/reg without need_modrm set, then the
2996    values are stale.  Hitting this abort likely indicates that you
2997    need to update onebyte_has_modrm or twobyte_has_modrm.  */
2998 #define MODRM_CHECK  if (!need_modrm) abort ()
2999
3000 static const char **names64;
3001 static const char **names32;
3002 static const char **names16;
3003 static const char **names8;
3004 static const char **names8rex;
3005 static const char **names_seg;
3006 static const char *index64;
3007 static const char *index32;
3008 static const char **index16;
3009 static const char **names_bnd;
3010
3011 static const char *intel_names64[] = {
3012   "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
3013   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3014 };
3015 static const char *intel_names32[] = {
3016   "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
3017   "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
3018 };
3019 static const char *intel_names16[] = {
3020   "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
3021   "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
3022 };
3023 static const char *intel_names8[] = {
3024   "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
3025 };
3026 static const char *intel_names8rex[] = {
3027   "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
3028   "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
3029 };
3030 static const char *intel_names_seg[] = {
3031   "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
3032 };
3033 static const char *intel_index64 = "riz";
3034 static const char *intel_index32 = "eiz";
3035 static const char *intel_index16[] = {
3036   "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
3037 };
3038
3039 static const char *att_names64[] = {
3040   "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
3041   "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
3042 };
3043 static const char *att_names32[] = {
3044   "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
3045   "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
3046 };
3047 static const char *att_names16[] = {
3048   "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
3049   "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
3050 };
3051 static const char *att_names8[] = {
3052   "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
3053 };
3054 static const char *att_names8rex[] = {
3055   "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
3056   "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
3057 };
3058 static const char *att_names_seg[] = {
3059   "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
3060 };
3061 static const char *att_index64 = "%riz";
3062 static const char *att_index32 = "%eiz";
3063 static const char *att_index16[] = {
3064   "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
3065 };
3066
3067 static const char **names_mm;
3068 static const char *intel_names_mm[] = {
3069   "mm0", "mm1", "mm2", "mm3",
3070   "mm4", "mm5", "mm6", "mm7"
3071 };
3072 static const char *att_names_mm[] = {
3073   "%mm0", "%mm1", "%mm2", "%mm3",
3074   "%mm4", "%mm5", "%mm6", "%mm7"
3075 };
3076
3077 static const char *intel_names_bnd[] = {
3078   "bnd0", "bnd1", "bnd2", "bnd3"
3079 };
3080
3081 static const char *att_names_bnd[] = {
3082   "%bnd0", "%bnd1", "%bnd2", "%bnd3"
3083 };
3084
3085 static const char **names_xmm;
3086 static const char *intel_names_xmm[] = {
3087   "xmm0", "xmm1", "xmm2", "xmm3",
3088   "xmm4", "xmm5", "xmm6", "xmm7",
3089   "xmm8", "xmm9", "xmm10", "xmm11",
3090   "xmm12", "xmm13", "xmm14", "xmm15",
3091   "xmm16", "xmm17", "xmm18", "xmm19",
3092   "xmm20", "xmm21", "xmm22", "xmm23",
3093   "xmm24", "xmm25", "xmm26", "xmm27",
3094   "xmm28", "xmm29", "xmm30", "xmm31"
3095 };
3096 static const char *att_names_xmm[] = {
3097   "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3098   "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3099   "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3100   "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3101   "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3102   "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3103   "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3104   "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3105 };
3106
3107 static const char **names_ymm;
3108 static const char *intel_names_ymm[] = {
3109   "ymm0", "ymm1", "ymm2", "ymm3",
3110   "ymm4", "ymm5", "ymm6", "ymm7",
3111   "ymm8", "ymm9", "ymm10", "ymm11",
3112   "ymm12", "ymm13", "ymm14", "ymm15",
3113   "ymm16", "ymm17", "ymm18", "ymm19",
3114   "ymm20", "ymm21", "ymm22", "ymm23",
3115   "ymm24", "ymm25", "ymm26", "ymm27",
3116   "ymm28", "ymm29", "ymm30", "ymm31"
3117 };
3118 static const char *att_names_ymm[] = {
3119   "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3120   "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3121   "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3122   "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3123   "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3124   "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3125   "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3126   "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3127 };
3128
3129 static const char **names_zmm;
3130 static const char *intel_names_zmm[] = {
3131   "zmm0", "zmm1", "zmm2", "zmm3",
3132   "zmm4", "zmm5", "zmm6", "zmm7",
3133   "zmm8", "zmm9", "zmm10", "zmm11",
3134   "zmm12", "zmm13", "zmm14", "zmm15",
3135   "zmm16", "zmm17", "zmm18", "zmm19",
3136   "zmm20", "zmm21", "zmm22", "zmm23",
3137   "zmm24", "zmm25", "zmm26", "zmm27",
3138   "zmm28", "zmm29", "zmm30", "zmm31"
3139 };
3140 static const char *att_names_zmm[] = {
3141   "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3142   "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3143   "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3144   "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3145   "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3146   "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3147   "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3148   "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3149 };
3150
3151 static const char **names_mask;
3152 static const char *intel_names_mask[] = {
3153   "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3154 };
3155 static const char *att_names_mask[] = {
3156   "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3157 };
3158
3159 static const char *names_rounding[] =
3160 {
3161   "{rn-sae}",
3162   "{rd-sae}",
3163   "{ru-sae}",
3164   "{rz-sae}"
3165 };
3166
3167 static const struct dis386 reg_table[][8] = {
3168   /* REG_80 */
3169   {
3170     { "addA",   { Ebh1, Ib }, 0 },
3171     { "orA",    { Ebh1, Ib }, 0 },
3172     { "adcA",   { Ebh1, Ib }, 0 },
3173     { "sbbA",   { Ebh1, Ib }, 0 },
3174     { "andA",   { Ebh1, Ib }, 0 },
3175     { "subA",   { Ebh1, Ib }, 0 },
3176     { "xorA",   { Ebh1, Ib }, 0 },
3177     { "cmpA",   { Eb, Ib }, 0 },
3178   },
3179   /* REG_81 */
3180   {
3181     { "addQ",   { Evh1, Iv }, 0 },
3182     { "orQ",    { Evh1, Iv }, 0 },
3183     { "adcQ",   { Evh1, Iv }, 0 },
3184     { "sbbQ",   { Evh1, Iv }, 0 },
3185     { "andQ",   { Evh1, Iv }, 0 },
3186     { "subQ",   { Evh1, Iv }, 0 },
3187     { "xorQ",   { Evh1, Iv }, 0 },
3188     { "cmpQ",   { Ev, Iv }, 0 },
3189   },
3190   /* REG_83 */
3191   {
3192     { "addQ",   { Evh1, sIb }, 0 },
3193     { "orQ",    { Evh1, sIb }, 0 },
3194     { "adcQ",   { Evh1, sIb }, 0 },
3195     { "sbbQ",   { Evh1, sIb }, 0 },
3196     { "andQ",   { Evh1, sIb }, 0 },
3197     { "subQ",   { Evh1, sIb }, 0 },
3198     { "xorQ",   { Evh1, sIb }, 0 },
3199     { "cmpQ",   { Ev, sIb }, 0 },
3200   },
3201   /* REG_8F */
3202   {
3203     { "popU",   { stackEv }, 0 },
3204     { XOP_8F_TABLE (XOP_09) },
3205     { Bad_Opcode },
3206     { Bad_Opcode },
3207     { Bad_Opcode },
3208     { XOP_8F_TABLE (XOP_09) },
3209   },
3210   /* REG_C0 */
3211   {
3212     { "rolA",   { Eb, Ib }, 0 },
3213     { "rorA",   { Eb, Ib }, 0 },
3214     { "rclA",   { Eb, Ib }, 0 },
3215     { "rcrA",   { Eb, Ib }, 0 },
3216     { "shlA",   { Eb, Ib }, 0 },
3217     { "shrA",   { Eb, Ib }, 0 },
3218     { "shlA",   { Eb, Ib }, 0 },
3219     { "sarA",   { Eb, Ib }, 0 },
3220   },
3221   /* REG_C1 */
3222   {
3223     { "rolQ",   { Ev, Ib }, 0 },
3224     { "rorQ",   { Ev, Ib }, 0 },
3225     { "rclQ",   { Ev, Ib }, 0 },
3226     { "rcrQ",   { Ev, Ib }, 0 },
3227     { "shlQ",   { Ev, Ib }, 0 },
3228     { "shrQ",   { Ev, Ib }, 0 },
3229     { "shlQ",   { Ev, Ib }, 0 },
3230     { "sarQ",   { Ev, Ib }, 0 },
3231   },
3232   /* REG_C6 */
3233   {
3234     { "movA",   { Ebh3, Ib }, 0 },
3235     { Bad_Opcode },
3236     { Bad_Opcode },
3237     { Bad_Opcode },
3238     { Bad_Opcode },
3239     { Bad_Opcode },
3240     { Bad_Opcode },
3241     { MOD_TABLE (MOD_C6_REG_7) },
3242   },
3243   /* REG_C7 */
3244   {
3245     { "movQ",   { Evh3, Iv }, 0 },
3246     { Bad_Opcode },
3247     { Bad_Opcode },
3248     { Bad_Opcode },
3249     { Bad_Opcode },
3250     { Bad_Opcode },
3251     { Bad_Opcode },
3252     { MOD_TABLE (MOD_C7_REG_7) },
3253   },
3254   /* REG_D0 */
3255   {
3256     { "rolA",   { Eb, I1 }, 0 },
3257     { "rorA",   { Eb, I1 }, 0 },
3258     { "rclA",   { Eb, I1 }, 0 },
3259     { "rcrA",   { Eb, I1 }, 0 },
3260     { "shlA",   { Eb, I1 }, 0 },
3261     { "shrA",   { Eb, I1 }, 0 },
3262     { "shlA",   { Eb, I1 }, 0 },
3263     { "sarA",   { Eb, I1 }, 0 },
3264   },
3265   /* REG_D1 */
3266   {
3267     { "rolQ",   { Ev, I1 }, 0 },
3268     { "rorQ",   { Ev, I1 }, 0 },
3269     { "rclQ",   { Ev, I1 }, 0 },
3270     { "rcrQ",   { Ev, I1 }, 0 },
3271     { "shlQ",   { Ev, I1 }, 0 },
3272     { "shrQ",   { Ev, I1 }, 0 },
3273     { "shlQ",   { Ev, I1 }, 0 },
3274     { "sarQ",   { Ev, I1 }, 0 },
3275   },
3276   /* REG_D2 */
3277   {
3278     { "rolA",   { Eb, CL }, 0 },
3279     { "rorA",   { Eb, CL }, 0 },
3280     { "rclA",   { Eb, CL }, 0 },
3281     { "rcrA",   { Eb, CL }, 0 },
3282     { "shlA",   { Eb, CL }, 0 },
3283     { "shrA",   { Eb, CL }, 0 },
3284     { "shlA",   { Eb, CL }, 0 },
3285     { "sarA",   { Eb, CL }, 0 },
3286   },
3287   /* REG_D3 */
3288   {
3289     { "rolQ",   { Ev, CL }, 0 },
3290     { "rorQ",   { Ev, CL }, 0 },
3291     { "rclQ",   { Ev, CL }, 0 },
3292     { "rcrQ",   { Ev, CL }, 0 },
3293     { "shlQ",   { Ev, CL }, 0 },
3294     { "shrQ",   { Ev, CL }, 0 },
3295     { "shlQ",   { Ev, CL }, 0 },
3296     { "sarQ",   { Ev, CL }, 0 },
3297   },
3298   /* REG_F6 */
3299   {
3300     { "testA",  { Eb, Ib }, 0 },
3301     { "testA",  { Eb, Ib }, 0 },
3302     { "notA",   { Ebh1 }, 0 },
3303     { "negA",   { Ebh1 }, 0 },
3304     { "mulA",   { Eb }, 0 },    /* Don't print the implicit %al register,  */
3305     { "imulA",  { Eb }, 0 },    /* to distinguish these opcodes from other */
3306     { "divA",   { Eb }, 0 },    /* mul/imul opcodes.  Do the same for div  */
3307     { "idivA",  { Eb }, 0 },    /* and idiv for consistency.               */
3308   },
3309   /* REG_F7 */
3310   {
3311     { "testQ",  { Ev, Iv }, 0 },
3312     { "testQ",  { Ev, Iv }, 0 },
3313     { "notQ",   { Evh1 }, 0 },
3314     { "negQ",   { Evh1 }, 0 },
3315     { "mulQ",   { Ev }, 0 },    /* Don't print the implicit register.  */
3316     { "imulQ",  { Ev }, 0 },
3317     { "divQ",   { Ev }, 0 },
3318     { "idivQ",  { Ev }, 0 },
3319   },
3320   /* REG_FE */
3321   {
3322     { "incA",   { Ebh1 }, 0 },
3323     { "decA",   { Ebh1 }, 0 },
3324   },
3325   /* REG_FF */
3326   {
3327     { "incQ",   { Evh1 }, 0 },
3328     { "decQ",   { Evh1 }, 0 },
3329     { "call{&|}", { NOTRACK, indirEv, BND }, 0 },
3330     { MOD_TABLE (MOD_FF_REG_3) },
3331     { "jmp{&|}", { NOTRACK, indirEv, BND }, 0 },
3332     { MOD_TABLE (MOD_FF_REG_5) },
3333     { "pushU",  { stackEv }, 0 },
3334     { Bad_Opcode },
3335   },
3336   /* REG_0F00 */
3337   {
3338     { "sldtD",  { Sv }, 0 },
3339     { "strD",   { Sv }, 0 },
3340     { "lldt",   { Ew }, 0 },
3341     { "ltr",    { Ew }, 0 },
3342     { "verr",   { Ew }, 0 },
3343     { "verw",   { Ew }, 0 },
3344     { Bad_Opcode },
3345     { Bad_Opcode },
3346   },
3347   /* REG_0F01 */
3348   {
3349     { MOD_TABLE (MOD_0F01_REG_0) },
3350     { MOD_TABLE (MOD_0F01_REG_1) },
3351     { MOD_TABLE (MOD_0F01_REG_2) },
3352     { MOD_TABLE (MOD_0F01_REG_3) },
3353     { "smswD",  { Sv }, 0 },
3354     { MOD_TABLE (MOD_0F01_REG_5) },
3355     { "lmsw",   { Ew }, 0 },
3356     { MOD_TABLE (MOD_0F01_REG_7) },
3357   },
3358   /* REG_0F0D */
3359   {
3360     { "prefetch",       { Mb }, 0 },
3361     { "prefetchw",      { Mb }, 0 },
3362     { "prefetchwt1",    { Mb }, 0 },
3363     { "prefetch",       { Mb }, 0 },
3364     { "prefetch",       { Mb }, 0 },
3365     { "prefetch",       { Mb }, 0 },
3366     { "prefetch",       { Mb }, 0 },
3367     { "prefetch",       { Mb }, 0 },
3368   },
3369   /* REG_0F18 */
3370   {
3371     { MOD_TABLE (MOD_0F18_REG_0) },
3372     { MOD_TABLE (MOD_0F18_REG_1) },
3373     { MOD_TABLE (MOD_0F18_REG_2) },
3374     { MOD_TABLE (MOD_0F18_REG_3) },
3375     { MOD_TABLE (MOD_0F18_REG_4) },
3376     { MOD_TABLE (MOD_0F18_REG_5) },
3377     { MOD_TABLE (MOD_0F18_REG_6) },
3378     { MOD_TABLE (MOD_0F18_REG_7) },
3379   },
3380   /* REG_0F1C_P_0_MOD_0 */
3381   {
3382     { "cldemote",       { Mb }, 0 },
3383     { "nopQ",           { Ev }, 0 },
3384     { "nopQ",           { Ev }, 0 },
3385     { "nopQ",           { Ev }, 0 },
3386     { "nopQ",           { Ev }, 0 },
3387     { "nopQ",           { Ev }, 0 },
3388     { "nopQ",           { Ev }, 0 },
3389     { "nopQ",           { Ev }, 0 },
3390   },
3391   /* REG_0F1E_P_1_MOD_3 */
3392   {
3393     { "nopQ",           { Ev }, 0 },
3394     { "rdsspK",         { Rdq }, PREFIX_OPCODE },
3395     { "nopQ",           { Ev }, 0 },
3396     { "nopQ",           { Ev }, 0 },
3397     { "nopQ",           { Ev }, 0 },
3398     { "nopQ",           { Ev }, 0 },
3399     { "nopQ",           { Ev }, 0 },
3400     { RM_TABLE (RM_0F1E_P_1_MOD_3_REG_7) },
3401   },
3402   /* REG_0F71 */
3403   {
3404     { Bad_Opcode },
3405     { Bad_Opcode },
3406     { MOD_TABLE (MOD_0F71_REG_2) },
3407     { Bad_Opcode },
3408     { MOD_TABLE (MOD_0F71_REG_4) },
3409     { Bad_Opcode },
3410     { MOD_TABLE (MOD_0F71_REG_6) },
3411   },
3412   /* REG_0F72 */
3413   {
3414     { Bad_Opcode },
3415     { Bad_Opcode },
3416     { MOD_TABLE (MOD_0F72_REG_2) },
3417     { Bad_Opcode },
3418     { MOD_TABLE (MOD_0F72_REG_4) },
3419     { Bad_Opcode },
3420     { MOD_TABLE (MOD_0F72_REG_6) },
3421   },
3422   /* REG_0F73 */
3423   {
3424     { Bad_Opcode },
3425     { Bad_Opcode },
3426     { MOD_TABLE (MOD_0F73_REG_2) },
3427     { MOD_TABLE (MOD_0F73_REG_3) },
3428     { Bad_Opcode },
3429     { Bad_Opcode },
3430     { MOD_TABLE (MOD_0F73_REG_6) },
3431     { MOD_TABLE (MOD_0F73_REG_7) },
3432   },
3433   /* REG_0FA6 */
3434   {
3435     { "montmul",        { { OP_0f07, 0 } }, 0 },
3436     { "xsha1",          { { OP_0f07, 0 } }, 0 },
3437     { "xsha256",        { { OP_0f07, 0 } }, 0 },
3438   },
3439   /* REG_0FA7 */
3440   {
3441     { "xstore-rng",     { { OP_0f07, 0 } }, 0 },
3442     { "xcrypt-ecb",     { { OP_0f07, 0 } }, 0 },
3443     { "xcrypt-cbc",     { { OP_0f07, 0 } }, 0 },
3444     { "xcrypt-ctr",     { { OP_0f07, 0 } }, 0 },
3445     { "xcrypt-cfb",     { { OP_0f07, 0 } }, 0 },
3446     { "xcrypt-ofb",     { { OP_0f07, 0 } }, 0 },
3447   },
3448   /* REG_0FAE */
3449   {
3450     { MOD_TABLE (MOD_0FAE_REG_0) },
3451     { MOD_TABLE (MOD_0FAE_REG_1) },
3452     { MOD_TABLE (MOD_0FAE_REG_2) },
3453     { MOD_TABLE (MOD_0FAE_REG_3) },
3454     { MOD_TABLE (MOD_0FAE_REG_4) },
3455     { MOD_TABLE (MOD_0FAE_REG_5) },
3456     { MOD_TABLE (MOD_0FAE_REG_6) },
3457     { MOD_TABLE (MOD_0FAE_REG_7) },
3458   },
3459   /* REG_0FBA */
3460   {
3461     { Bad_Opcode },
3462     { Bad_Opcode },
3463     { Bad_Opcode },
3464     { Bad_Opcode },
3465     { "btQ",    { Ev, Ib }, 0 },
3466     { "btsQ",   { Evh1, Ib }, 0 },
3467     { "btrQ",   { Evh1, Ib }, 0 },
3468     { "btcQ",   { Evh1, Ib }, 0 },
3469   },
3470   /* REG_0FC7 */
3471   {
3472     { Bad_Opcode },
3473     { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 },
3474     { Bad_Opcode },
3475     { MOD_TABLE (MOD_0FC7_REG_3) },
3476     { MOD_TABLE (MOD_0FC7_REG_4) },
3477     { MOD_TABLE (MOD_0FC7_REG_5) },
3478     { MOD_TABLE (MOD_0FC7_REG_6) },
3479     { MOD_TABLE (MOD_0FC7_REG_7) },
3480   },
3481   /* REG_VEX_0F71 */
3482   {
3483     { Bad_Opcode },
3484     { Bad_Opcode },
3485     { MOD_TABLE (MOD_VEX_0F71_REG_2) },
3486     { Bad_Opcode },
3487     { MOD_TABLE (MOD_VEX_0F71_REG_4) },
3488     { Bad_Opcode },
3489     { MOD_TABLE (MOD_VEX_0F71_REG_6) },
3490   },
3491   /* REG_VEX_0F72 */
3492   {
3493     { Bad_Opcode },
3494     { Bad_Opcode },
3495     { MOD_TABLE (MOD_VEX_0F72_REG_2) },
3496     { Bad_Opcode },
3497     { MOD_TABLE (MOD_VEX_0F72_REG_4) },
3498     { Bad_Opcode },
3499     { MOD_TABLE (MOD_VEX_0F72_REG_6) },
3500   },
3501   /* REG_VEX_0F73 */
3502   {
3503     { Bad_Opcode },
3504     { Bad_Opcode },
3505     { MOD_TABLE (MOD_VEX_0F73_REG_2) },
3506     { MOD_TABLE (MOD_VEX_0F73_REG_3) },
3507     { Bad_Opcode },
3508     { Bad_Opcode },
3509     { MOD_TABLE (MOD_VEX_0F73_REG_6) },
3510     { MOD_TABLE (MOD_VEX_0F73_REG_7) },
3511   },
3512   /* REG_VEX_0FAE */
3513   {
3514     { Bad_Opcode },
3515     { Bad_Opcode },
3516     { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
3517     { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
3518   },
3519   /* REG_VEX_0F38F3 */
3520   {
3521     { Bad_Opcode },
3522     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) },
3523     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) },
3524     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) },
3525   },
3526   /* REG_XOP_LWPCB */
3527   {
3528     { "llwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3529     { "slwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3530   },
3531   /* REG_XOP_LWP */
3532   {
3533     { "lwpins", { { OP_LWP_E, 0 }, Ed, Id }, 0 },
3534     { "lwpval", { { OP_LWP_E, 0 }, Ed, Id }, 0 },
3535   },
3536   /* REG_XOP_TBM_01 */
3537   {
3538     { Bad_Opcode },
3539     { "blcfill",        { { OP_LWP_E, 0 }, Edq }, 0 },
3540     { "blsfill",        { { OP_LWP_E, 0 }, Edq }, 0 },
3541     { "blcs",   { { OP_LWP_E, 0 }, Edq }, 0 },
3542     { "tzmsk",  { { OP_LWP_E, 0 }, Edq }, 0 },
3543     { "blcic",  { { OP_LWP_E, 0 }, Edq }, 0 },
3544     { "blsic",  { { OP_LWP_E, 0 }, Edq }, 0 },
3545     { "t1mskc", { { OP_LWP_E, 0 }, Edq }, 0 },
3546   },
3547   /* REG_XOP_TBM_02 */
3548   {
3549     { Bad_Opcode },
3550     { "blcmsk", { { OP_LWP_E, 0 }, Edq }, 0 },
3551     { Bad_Opcode },
3552     { Bad_Opcode },
3553     { Bad_Opcode },
3554     { Bad_Opcode },
3555     { "blci",   { { OP_LWP_E, 0 }, Edq }, 0 },
3556   },
3557
3558 #include "i386-dis-evex-reg.h"
3559 };
3560
3561 static const struct dis386 prefix_table[][4] = {
3562   /* PREFIX_90 */
3563   {
3564     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3565     { "pause", { XX }, 0 },
3566     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3567     { NULL, { { NULL, 0 } }, PREFIX_IGNORED }
3568   },
3569
3570   /* PREFIX_0F01_REG_3_RM_1 */
3571   {
3572     { "vmmcall",        { Skip_MODRM }, 0 },
3573     { "vmgexit",        { Skip_MODRM }, 0 },
3574     { Bad_Opcode },
3575     { "vmgexit",        { Skip_MODRM }, 0 },
3576   },
3577
3578   /* PREFIX_0F01_REG_5_MOD_0 */
3579   {
3580     { Bad_Opcode },
3581     { "rstorssp",       { Mq }, PREFIX_OPCODE },
3582   },
3583
3584   /* PREFIX_0F01_REG_5_MOD_3_RM_0 */
3585   {
3586     { "serialize",      { Skip_MODRM }, PREFIX_OPCODE },
3587     { "setssbsy",       { Skip_MODRM }, PREFIX_OPCODE },
3588     { Bad_Opcode },
3589     { "xsusldtrk",      { Skip_MODRM }, PREFIX_OPCODE },
3590   },
3591
3592   /* PREFIX_0F01_REG_5_MOD_3_RM_1 */
3593   {
3594     { Bad_Opcode },
3595     { Bad_Opcode },
3596     { Bad_Opcode },
3597     { "xresldtrk",     { Skip_MODRM }, PREFIX_OPCODE },
3598   },
3599
3600   /* PREFIX_0F01_REG_5_MOD_3_RM_2 */
3601   {
3602     { Bad_Opcode },
3603     { "saveprevssp",    { Skip_MODRM }, PREFIX_OPCODE },
3604   },
3605
3606   /* PREFIX_0F01_REG_7_MOD_3_RM_2 */
3607   {
3608     { "monitorx",       { { OP_Monitor, 0 } }, 0  },
3609     { "mcommit",        { Skip_MODRM }, 0 },
3610   },
3611
3612   /* PREFIX_0F01_REG_7_MOD_3_RM_3 */
3613   {
3614     { "mwaitx",         { { OP_Mwait, eBX_reg } }, 0  },
3615   },
3616
3617   /* PREFIX_0F09 */
3618   {
3619     { "wbinvd",   { XX }, 0 },
3620     { "wbnoinvd", { XX }, 0 },
3621   },
3622
3623   /* PREFIX_0F10 */
3624   {
3625     { "movups", { XM, EXx }, PREFIX_OPCODE },
3626     { "movss",  { XM, EXd }, PREFIX_OPCODE },
3627     { "movupd", { XM, EXx }, PREFIX_OPCODE },
3628     { "movsd",  { XM, EXq }, PREFIX_OPCODE },
3629   },
3630
3631   /* PREFIX_0F11 */
3632   {
3633     { "movups", { EXxS, XM }, PREFIX_OPCODE },
3634     { "movss",  { EXdS, XM }, PREFIX_OPCODE },
3635     { "movupd", { EXxS, XM }, PREFIX_OPCODE },
3636     { "movsd",  { EXqS, XM }, PREFIX_OPCODE },
3637   },
3638
3639   /* PREFIX_0F12 */
3640   {
3641     { MOD_TABLE (MOD_0F12_PREFIX_0) },
3642     { "movsldup", { XM, EXx }, PREFIX_OPCODE },
3643     { MOD_TABLE (MOD_0F12_PREFIX_2) },
3644     { "movddup", { XM, EXq }, PREFIX_OPCODE },
3645   },
3646
3647   /* PREFIX_0F16 */
3648   {
3649     { MOD_TABLE (MOD_0F16_PREFIX_0) },
3650     { "movshdup", { XM, EXx }, PREFIX_OPCODE },
3651     { MOD_TABLE (MOD_0F16_PREFIX_2) },
3652   },
3653
3654   /* PREFIX_0F1A */
3655   {
3656     { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3657     { "bndcl",  { Gbnd, Ev_bnd }, 0 },
3658     { "bndmov", { Gbnd, Ebnd }, 0 },
3659     { "bndcu",  { Gbnd, Ev_bnd }, 0 },
3660   },
3661
3662   /* PREFIX_0F1B */
3663   {
3664     { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3665     { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3666     { "bndmov", { EbndS, Gbnd }, 0 },
3667     { "bndcn",  { Gbnd, Ev_bnd }, 0 },
3668   },
3669
3670   /* PREFIX_0F1C */
3671   {
3672     { MOD_TABLE (MOD_0F1C_PREFIX_0) },
3673     { "nopQ",   { Ev }, PREFIX_OPCODE },
3674     { "nopQ",   { Ev }, PREFIX_OPCODE },
3675     { "nopQ",   { Ev }, PREFIX_OPCODE },
3676   },
3677
3678   /* PREFIX_0F1E */
3679   {
3680     { "nopQ",   { Ev }, PREFIX_OPCODE },
3681     { MOD_TABLE (MOD_0F1E_PREFIX_1) },
3682     { "nopQ",   { Ev }, PREFIX_OPCODE },
3683     { "nopQ",   { Ev }, PREFIX_OPCODE },
3684   },
3685
3686   /* PREFIX_0F2A */
3687   {
3688     { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE },
3689     { "cvtsi2ss%LQ", { XM, Edq }, PREFIX_OPCODE },
3690     { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE },
3691     { "cvtsi2sd%LQ", { XM, Edq }, 0 },
3692   },
3693
3694   /* PREFIX_0F2B */
3695   {
3696     { MOD_TABLE (MOD_0F2B_PREFIX_0) },
3697     { MOD_TABLE (MOD_0F2B_PREFIX_1) },
3698     { MOD_TABLE (MOD_0F2B_PREFIX_2) },
3699     { MOD_TABLE (MOD_0F2B_PREFIX_3) },
3700   },
3701
3702   /* PREFIX_0F2C */
3703   {
3704     { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE },
3705     { "cvttss2si", { Gdq, EXd }, PREFIX_OPCODE },
3706     { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3707     { "cvttsd2si", { Gdq, EXq }, PREFIX_OPCODE },
3708   },
3709
3710   /* PREFIX_0F2D */
3711   {
3712     { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE },
3713     { "cvtss2si", { Gdq, EXd }, PREFIX_OPCODE },
3714     { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3715     { "cvtsd2si", { Gdq, EXq }, PREFIX_OPCODE },
3716   },
3717
3718   /* PREFIX_0F2E */
3719   {
3720     { "ucomiss",{ XM, EXd }, 0 },
3721     { Bad_Opcode },
3722     { "ucomisd",{ XM, EXq }, 0 },
3723   },
3724
3725   /* PREFIX_0F2F */
3726   {
3727     { "comiss", { XM, EXd }, 0 },
3728     { Bad_Opcode },
3729     { "comisd", { XM, EXq }, 0 },
3730   },
3731
3732   /* PREFIX_0F51 */
3733   {
3734     { "sqrtps", { XM, EXx }, PREFIX_OPCODE },
3735     { "sqrtss", { XM, EXd }, PREFIX_OPCODE },
3736     { "sqrtpd", { XM, EXx }, PREFIX_OPCODE },
3737     { "sqrtsd", { XM, EXq }, PREFIX_OPCODE },
3738   },
3739
3740   /* PREFIX_0F52 */
3741   {
3742     { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE },
3743     { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE },
3744   },
3745
3746   /* PREFIX_0F53 */
3747   {
3748     { "rcpps",  { XM, EXx }, PREFIX_OPCODE },
3749     { "rcpss",  { XM, EXd }, PREFIX_OPCODE },
3750   },
3751
3752   /* PREFIX_0F58 */
3753   {
3754     { "addps", { XM, EXx }, PREFIX_OPCODE },
3755     { "addss", { XM, EXd }, PREFIX_OPCODE },
3756     { "addpd", { XM, EXx }, PREFIX_OPCODE },
3757     { "addsd", { XM, EXq }, PREFIX_OPCODE },
3758   },
3759
3760   /* PREFIX_0F59 */
3761   {
3762     { "mulps",  { XM, EXx }, PREFIX_OPCODE },
3763     { "mulss",  { XM, EXd }, PREFIX_OPCODE },
3764     { "mulpd",  { XM, EXx }, PREFIX_OPCODE },
3765     { "mulsd",  { XM, EXq }, PREFIX_OPCODE },
3766   },
3767
3768   /* PREFIX_0F5A */
3769   {
3770     { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE },
3771     { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE },
3772     { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE },
3773     { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE },
3774   },
3775
3776   /* PREFIX_0F5B */
3777   {
3778     { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE },
3779     { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE },
3780     { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE },
3781   },
3782
3783   /* PREFIX_0F5C */
3784   {
3785     { "subps",  { XM, EXx }, PREFIX_OPCODE },
3786     { "subss",  { XM, EXd }, PREFIX_OPCODE },
3787     { "subpd",  { XM, EXx }, PREFIX_OPCODE },
3788     { "subsd",  { XM, EXq }, PREFIX_OPCODE },
3789   },
3790
3791   /* PREFIX_0F5D */
3792   {
3793     { "minps",  { XM, EXx }, PREFIX_OPCODE },
3794     { "minss",  { XM, EXd }, PREFIX_OPCODE },
3795     { "minpd",  { XM, EXx }, PREFIX_OPCODE },
3796     { "minsd",  { XM, EXq }, PREFIX_OPCODE },
3797   },
3798
3799   /* PREFIX_0F5E */
3800   {
3801     { "divps",  { XM, EXx }, PREFIX_OPCODE },
3802     { "divss",  { XM, EXd }, PREFIX_OPCODE },
3803     { "divpd",  { XM, EXx }, PREFIX_OPCODE },
3804     { "divsd",  { XM, EXq }, PREFIX_OPCODE },
3805   },
3806
3807   /* PREFIX_0F5F */
3808   {
3809     { "maxps",  { XM, EXx }, PREFIX_OPCODE },
3810     { "maxss",  { XM, EXd }, PREFIX_OPCODE },
3811     { "maxpd",  { XM, EXx }, PREFIX_OPCODE },
3812     { "maxsd",  { XM, EXq }, PREFIX_OPCODE },
3813   },
3814
3815   /* PREFIX_0F60 */
3816   {
3817     { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE },
3818     { Bad_Opcode },
3819     { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE },
3820   },
3821
3822   /* PREFIX_0F61 */
3823   {
3824     { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE },
3825     { Bad_Opcode },
3826     { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE },
3827   },
3828
3829   /* PREFIX_0F62 */
3830   {
3831     { "punpckldq",{ MX, EMd }, PREFIX_OPCODE },
3832     { Bad_Opcode },
3833     { "punpckldq",{ MX, EMx }, PREFIX_OPCODE },
3834   },
3835
3836   /* PREFIX_0F6C */
3837   {
3838     { Bad_Opcode },
3839     { Bad_Opcode },
3840     { "punpcklqdq", { XM, EXx }, PREFIX_OPCODE },
3841   },
3842
3843   /* PREFIX_0F6D */
3844   {
3845     { Bad_Opcode },
3846     { Bad_Opcode },
3847     { "punpckhqdq", { XM, EXx }, PREFIX_OPCODE },
3848   },
3849
3850   /* PREFIX_0F6F */
3851   {
3852     { "movq",   { MX, EM }, PREFIX_OPCODE },
3853     { "movdqu", { XM, EXx }, PREFIX_OPCODE },
3854     { "movdqa", { XM, EXx }, PREFIX_OPCODE },
3855   },
3856
3857   /* PREFIX_0F70 */
3858   {
3859     { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE },
3860     { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3861     { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE },
3862     { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3863   },
3864
3865   /* PREFIX_0F73_REG_3 */
3866   {
3867     { Bad_Opcode },
3868     { Bad_Opcode },
3869     { "psrldq", { XS, Ib }, 0 },
3870   },
3871
3872   /* PREFIX_0F73_REG_7 */
3873   {
3874     { Bad_Opcode },
3875     { Bad_Opcode },
3876     { "pslldq", { XS, Ib }, 0 },
3877   },
3878
3879   /* PREFIX_0F78 */
3880   {
3881     {"vmread",  { Em, Gm }, 0 },
3882     { Bad_Opcode },
3883     {"extrq",   { XS, Ib, Ib }, 0 },
3884     {"insertq", { XM, XS, Ib, Ib }, 0 },
3885   },
3886
3887   /* PREFIX_0F79 */
3888   {
3889     {"vmwrite", { Gm, Em }, 0 },
3890     { Bad_Opcode },
3891     {"extrq",   { XM, XS }, 0 },
3892     {"insertq", { XM, XS }, 0 },
3893   },
3894
3895   /* PREFIX_0F7C */
3896   {
3897     { Bad_Opcode },
3898     { Bad_Opcode },
3899     { "haddpd", { XM, EXx }, PREFIX_OPCODE },
3900     { "haddps", { XM, EXx }, PREFIX_OPCODE },
3901   },
3902
3903   /* PREFIX_0F7D */
3904   {
3905     { Bad_Opcode },
3906     { Bad_Opcode },
3907     { "hsubpd", { XM, EXx }, PREFIX_OPCODE },
3908     { "hsubps", { XM, EXx }, PREFIX_OPCODE },
3909   },
3910
3911   /* PREFIX_0F7E */
3912   {
3913     { "movK",   { Edq, MX }, PREFIX_OPCODE },
3914     { "movq",   { XM, EXq }, PREFIX_OPCODE },
3915     { "movK",   { Edq, XM }, PREFIX_OPCODE },
3916   },
3917
3918   /* PREFIX_0F7F */
3919   {
3920     { "movq",   { EMS, MX }, PREFIX_OPCODE },
3921     { "movdqu", { EXxS, XM }, PREFIX_OPCODE },
3922     { "movdqa", { EXxS, XM }, PREFIX_OPCODE },
3923   },
3924
3925   /* PREFIX_0FAE_REG_0_MOD_3 */
3926   {
3927     { Bad_Opcode },
3928     { "rdfsbase", { Ev }, 0 },
3929   },
3930
3931   /* PREFIX_0FAE_REG_1_MOD_3 */
3932   {
3933     { Bad_Opcode },
3934     { "rdgsbase", { Ev }, 0 },
3935   },
3936
3937   /* PREFIX_0FAE_REG_2_MOD_3 */
3938   {
3939     { Bad_Opcode },
3940     { "wrfsbase", { Ev }, 0 },
3941   },
3942
3943   /* PREFIX_0FAE_REG_3_MOD_3 */
3944   {
3945     { Bad_Opcode },
3946     { "wrgsbase", { Ev }, 0 },
3947   },
3948
3949   /* PREFIX_0FAE_REG_4_MOD_0 */
3950   {
3951     { "xsave",  { FXSAVE }, 0 },
3952     { "ptwrite%LQ", { Edq }, 0 },
3953   },
3954
3955   /* PREFIX_0FAE_REG_4_MOD_3 */
3956   {
3957     { Bad_Opcode },
3958     { "ptwrite%LQ", { Edq }, 0 },
3959   },
3960
3961   /* PREFIX_0FAE_REG_5_MOD_0 */
3962   {
3963     { "xrstor",         { FXSAVE }, PREFIX_OPCODE },
3964   },
3965
3966   /* PREFIX_0FAE_REG_5_MOD_3 */
3967   {
3968     { "lfence",         { Skip_MODRM }, 0 },
3969     { "incsspK",        { Rdq }, PREFIX_OPCODE },
3970   },
3971
3972   /* PREFIX_0FAE_REG_6_MOD_0 */
3973   {
3974     { "xsaveopt",       { FXSAVE }, PREFIX_OPCODE },
3975     { "clrssbsy",       { Mq }, PREFIX_OPCODE },
3976     { "clwb",   { Mb }, PREFIX_OPCODE },
3977   },
3978
3979   /* PREFIX_0FAE_REG_6_MOD_3 */
3980   {
3981     { RM_TABLE (RM_0FAE_REG_6_MOD_3_P_0) },
3982     { "umonitor",       { Eva }, PREFIX_OPCODE },
3983     { "tpause", { Edq }, PREFIX_OPCODE },
3984     { "umwait", { Edq }, PREFIX_OPCODE },
3985   },
3986
3987   /* PREFIX_0FAE_REG_7_MOD_0 */
3988   {
3989     { "clflush",        { Mb }, 0 },
3990     { Bad_Opcode },
3991     { "clflushopt",     { Mb }, 0 },
3992   },
3993
3994   /* PREFIX_0FB8 */
3995   {
3996     { Bad_Opcode },
3997     { "popcntS", { Gv, Ev }, 0 },
3998   },
3999
4000   /* PREFIX_0FBC */
4001   {
4002     { "bsfS",   { Gv, Ev }, 0 },
4003     { "tzcntS", { Gv, Ev }, 0 },
4004     { "bsfS",   { Gv, Ev }, 0 },
4005   },
4006
4007   /* PREFIX_0FBD */
4008   {
4009     { "bsrS",   { Gv, Ev }, 0 },
4010     { "lzcntS", { Gv, Ev }, 0 },
4011     { "bsrS",   { Gv, Ev }, 0 },
4012   },
4013
4014   /* PREFIX_0FC2 */
4015   {
4016     { "cmpps",  { XM, EXx, CMP }, PREFIX_OPCODE },
4017     { "cmpss",  { XM, EXd, CMP }, PREFIX_OPCODE },
4018     { "cmppd",  { XM, EXx, CMP }, PREFIX_OPCODE },
4019     { "cmpsd",  { XM, EXq, CMP }, PREFIX_OPCODE },
4020   },
4021
4022   /* PREFIX_0FC3_MOD_0 */
4023   {
4024     { "movntiS", { Edq, Gdq }, PREFIX_OPCODE },
4025   },
4026
4027   /* PREFIX_0FC7_REG_6_MOD_0 */
4028   {
4029     { "vmptrld",{ Mq }, 0 },
4030     { "vmxon",  { Mq }, 0 },
4031     { "vmclear",{ Mq }, 0 },
4032   },
4033
4034   /* PREFIX_0FC7_REG_6_MOD_3 */
4035   {
4036     { "rdrand", { Ev }, 0 },
4037     { Bad_Opcode },
4038     { "rdrand", { Ev }, 0 }
4039   },
4040
4041   /* PREFIX_0FC7_REG_7_MOD_3 */
4042   {
4043     { "rdseed", { Ev }, 0 },
4044     { "rdpid",  { Em }, 0 },
4045     { "rdseed", { Ev }, 0 },
4046   },
4047
4048   /* PREFIX_0FD0 */
4049   {
4050     { Bad_Opcode },
4051     { Bad_Opcode },
4052     { "addsubpd", { XM, EXx }, 0 },
4053     { "addsubps", { XM, EXx }, 0 },
4054   },
4055
4056   /* PREFIX_0FD6 */
4057   {
4058     { Bad_Opcode },
4059     { "movq2dq",{ XM, MS }, 0 },
4060     { "movq",   { EXqS, XM }, 0 },
4061     { "movdq2q",{ MX, XS }, 0 },
4062   },
4063
4064   /* PREFIX_0FE6 */
4065   {
4066     { Bad_Opcode },
4067     { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE },
4068     { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE },
4069     { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE },
4070   },
4071
4072   /* PREFIX_0FE7 */
4073   {
4074     { "movntq", { Mq, MX }, PREFIX_OPCODE },
4075     { Bad_Opcode },
4076     { MOD_TABLE (MOD_0FE7_PREFIX_2) },
4077   },
4078
4079   /* PREFIX_0FF0 */
4080   {
4081     { Bad_Opcode },
4082     { Bad_Opcode },
4083     { Bad_Opcode },
4084     { MOD_TABLE (MOD_0FF0_PREFIX_3) },
4085   },
4086
4087   /* PREFIX_0FF7 */
4088   {
4089     { "maskmovq", { MX, MS }, PREFIX_OPCODE },
4090     { Bad_Opcode },
4091     { "maskmovdqu", { XM, XS }, PREFIX_OPCODE },
4092   },
4093
4094   /* PREFIX_0F3810 */
4095   {
4096     { Bad_Opcode },
4097     { Bad_Opcode },
4098     { "pblendvb", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4099   },
4100
4101   /* PREFIX_0F3814 */
4102   {
4103     { Bad_Opcode },
4104     { Bad_Opcode },
4105     { "blendvps", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4106   },
4107
4108   /* PREFIX_0F3815 */
4109   {
4110     { Bad_Opcode },
4111     { Bad_Opcode },
4112     { "blendvpd", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4113   },
4114
4115   /* PREFIX_0F3817 */
4116   {
4117     { Bad_Opcode },
4118     { Bad_Opcode },
4119     { "ptest",  { XM, EXx }, PREFIX_OPCODE },
4120   },
4121
4122   /* PREFIX_0F3820 */
4123   {
4124     { Bad_Opcode },
4125     { Bad_Opcode },
4126     { "pmovsxbw", { XM, EXq }, PREFIX_OPCODE },
4127   },
4128
4129   /* PREFIX_0F3821 */
4130   {
4131     { Bad_Opcode },
4132     { Bad_Opcode },
4133     { "pmovsxbd", { XM, EXd }, PREFIX_OPCODE },
4134   },
4135
4136   /* PREFIX_0F3822 */
4137   {
4138     { Bad_Opcode },
4139     { Bad_Opcode },
4140     { "pmovsxbq", { XM, EXw }, PREFIX_OPCODE },
4141   },
4142
4143   /* PREFIX_0F3823 */
4144   {
4145     { Bad_Opcode },
4146     { Bad_Opcode },
4147     { "pmovsxwd", { XM, EXq }, PREFIX_OPCODE },
4148   },
4149
4150   /* PREFIX_0F3824 */
4151   {
4152     { Bad_Opcode },
4153     { Bad_Opcode },
4154     { "pmovsxwq", { XM, EXd }, PREFIX_OPCODE },
4155   },
4156
4157   /* PREFIX_0F3825 */
4158   {
4159     { Bad_Opcode },
4160     { Bad_Opcode },
4161     { "pmovsxdq", { XM, EXq }, PREFIX_OPCODE },
4162   },
4163
4164   /* PREFIX_0F3828 */
4165   {
4166     { Bad_Opcode },
4167     { Bad_Opcode },
4168     { "pmuldq", { XM, EXx }, PREFIX_OPCODE },
4169   },
4170
4171   /* PREFIX_0F3829 */
4172   {
4173     { Bad_Opcode },
4174     { Bad_Opcode },
4175     { "pcmpeqq", { XM, EXx }, PREFIX_OPCODE },
4176   },
4177
4178   /* PREFIX_0F382A */
4179   {
4180     { Bad_Opcode },
4181     { Bad_Opcode },
4182     { MOD_TABLE (MOD_0F382A_PREFIX_2) },
4183   },
4184
4185   /* PREFIX_0F382B */
4186   {
4187     { Bad_Opcode },
4188     { Bad_Opcode },
4189     { "packusdw", { XM, EXx }, PREFIX_OPCODE },
4190   },
4191
4192   /* PREFIX_0F3830 */
4193   {
4194     { Bad_Opcode },
4195     { Bad_Opcode },
4196     { "pmovzxbw", { XM, EXq }, PREFIX_OPCODE },
4197   },
4198
4199   /* PREFIX_0F3831 */
4200   {
4201     { Bad_Opcode },
4202     { Bad_Opcode },
4203     { "pmovzxbd", { XM, EXd }, PREFIX_OPCODE },
4204   },
4205
4206   /* PREFIX_0F3832 */
4207   {
4208     { Bad_Opcode },
4209     { Bad_Opcode },
4210     { "pmovzxbq", { XM, EXw }, PREFIX_OPCODE },
4211   },
4212
4213   /* PREFIX_0F3833 */
4214   {
4215     { Bad_Opcode },
4216     { Bad_Opcode },
4217     { "pmovzxwd", { XM, EXq }, PREFIX_OPCODE },
4218   },
4219
4220   /* PREFIX_0F3834 */
4221   {
4222     { Bad_Opcode },
4223     { Bad_Opcode },
4224     { "pmovzxwq", { XM, EXd }, PREFIX_OPCODE },
4225   },
4226
4227   /* PREFIX_0F3835 */
4228   {
4229     { Bad_Opcode },
4230     { Bad_Opcode },
4231     { "pmovzxdq", { XM, EXq }, PREFIX_OPCODE },
4232   },
4233
4234   /* PREFIX_0F3837 */
4235   {
4236     { Bad_Opcode },
4237     { Bad_Opcode },
4238     { "pcmpgtq", { XM, EXx }, PREFIX_OPCODE },
4239   },
4240
4241   /* PREFIX_0F3838 */
4242   {
4243     { Bad_Opcode },
4244     { Bad_Opcode },
4245     { "pminsb", { XM, EXx }, PREFIX_OPCODE },
4246   },
4247
4248   /* PREFIX_0F3839 */
4249   {
4250     { Bad_Opcode },
4251     { Bad_Opcode },
4252     { "pminsd", { XM, EXx }, PREFIX_OPCODE },
4253   },
4254
4255   /* PREFIX_0F383A */
4256   {
4257     { Bad_Opcode },
4258     { Bad_Opcode },
4259     { "pminuw", { XM, EXx }, PREFIX_OPCODE },
4260   },
4261
4262   /* PREFIX_0F383B */
4263   {
4264     { Bad_Opcode },
4265     { Bad_Opcode },
4266     { "pminud", { XM, EXx }, PREFIX_OPCODE },
4267   },
4268
4269   /* PREFIX_0F383C */
4270   {
4271     { Bad_Opcode },
4272     { Bad_Opcode },
4273     { "pmaxsb", { XM, EXx }, PREFIX_OPCODE },
4274   },
4275
4276   /* PREFIX_0F383D */
4277   {
4278     { Bad_Opcode },
4279     { Bad_Opcode },
4280     { "pmaxsd", { XM, EXx }, PREFIX_OPCODE },
4281   },
4282
4283   /* PREFIX_0F383E */
4284   {
4285     { Bad_Opcode },
4286     { Bad_Opcode },
4287     { "pmaxuw", { XM, EXx }, PREFIX_OPCODE },
4288   },
4289
4290   /* PREFIX_0F383F */
4291   {
4292     { Bad_Opcode },
4293     { Bad_Opcode },
4294     { "pmaxud", { XM, EXx }, PREFIX_OPCODE },
4295   },
4296
4297   /* PREFIX_0F3840 */
4298   {
4299     { Bad_Opcode },
4300     { Bad_Opcode },
4301     { "pmulld", { XM, EXx }, PREFIX_OPCODE },
4302   },
4303
4304   /* PREFIX_0F3841 */
4305   {
4306     { Bad_Opcode },
4307     { Bad_Opcode },
4308     { "phminposuw", { XM, EXx }, PREFIX_OPCODE },
4309   },
4310
4311   /* PREFIX_0F3880 */
4312   {
4313     { Bad_Opcode },
4314     { Bad_Opcode },
4315     { "invept", { Gm, Mo }, PREFIX_OPCODE },
4316   },
4317
4318   /* PREFIX_0F3881 */
4319   {
4320     { Bad_Opcode },
4321     { Bad_Opcode },
4322     { "invvpid", { Gm, Mo }, PREFIX_OPCODE },
4323   },
4324
4325   /* PREFIX_0F3882 */
4326   {
4327     { Bad_Opcode },
4328     { Bad_Opcode },
4329     { "invpcid", { Gm, M }, PREFIX_OPCODE },
4330   },
4331
4332   /* PREFIX_0F38C8 */
4333   {
4334     { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE },
4335   },
4336
4337   /* PREFIX_0F38C9 */
4338   {
4339     { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE },
4340   },
4341
4342   /* PREFIX_0F38CA */
4343   {
4344     { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE },
4345   },
4346
4347   /* PREFIX_0F38CB */
4348   {
4349     { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE },
4350   },
4351
4352   /* PREFIX_0F38CC */
4353   {
4354     { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE },
4355   },
4356
4357   /* PREFIX_0F38CD */
4358   {
4359     { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE },
4360   },
4361
4362   /* PREFIX_0F38CF */
4363   {
4364     { Bad_Opcode },
4365     { Bad_Opcode },
4366     { "gf2p8mulb", { XM, EXxmm }, PREFIX_OPCODE },
4367   },
4368
4369   /* PREFIX_0F38DB */
4370   {
4371     { Bad_Opcode },
4372     { Bad_Opcode },
4373     { "aesimc", { XM, EXx }, PREFIX_OPCODE },
4374   },
4375
4376   /* PREFIX_0F38DC */
4377   {
4378     { Bad_Opcode },
4379     { Bad_Opcode },
4380     { "aesenc", { XM, EXx }, PREFIX_OPCODE },
4381   },
4382
4383   /* PREFIX_0F38DD */
4384   {
4385     { Bad_Opcode },
4386     { Bad_Opcode },
4387     { "aesenclast", { XM, EXx }, PREFIX_OPCODE },
4388   },
4389
4390   /* PREFIX_0F38DE */
4391   {
4392     { Bad_Opcode },
4393     { Bad_Opcode },
4394     { "aesdec", { XM, EXx }, PREFIX_OPCODE },
4395   },
4396
4397   /* PREFIX_0F38DF */
4398   {
4399     { Bad_Opcode },
4400     { Bad_Opcode },
4401     { "aesdeclast", { XM, EXx }, PREFIX_OPCODE },
4402   },
4403
4404   /* PREFIX_0F38F0 */
4405   {
4406     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4407     { Bad_Opcode },
4408     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4409     { "crc32",  { Gdq, { CRC32_Fixup, b_mode } }, PREFIX_OPCODE },
4410   },
4411
4412   /* PREFIX_0F38F1 */
4413   {
4414     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4415     { Bad_Opcode },
4416     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4417     { "crc32",  { Gdq, { CRC32_Fixup, v_mode } }, PREFIX_OPCODE },
4418   },
4419
4420   /* PREFIX_0F38F5 */
4421   {
4422     { Bad_Opcode },
4423     { Bad_Opcode },
4424     { MOD_TABLE (MOD_0F38F5_PREFIX_2) },
4425   },
4426
4427   /* PREFIX_0F38F6 */
4428   {
4429     { MOD_TABLE (MOD_0F38F6_PREFIX_0) },
4430     { "adoxS",  { Gdq, Edq}, PREFIX_OPCODE },
4431     { "adcxS",  { Gdq, Edq}, PREFIX_OPCODE },
4432     { Bad_Opcode },
4433   },
4434
4435   /* PREFIX_0F38F8 */
4436   {
4437     { Bad_Opcode },
4438     { MOD_TABLE (MOD_0F38F8_PREFIX_1) },
4439     { MOD_TABLE (MOD_0F38F8_PREFIX_2) },
4440     { MOD_TABLE (MOD_0F38F8_PREFIX_3) },
4441   },
4442
4443   /* PREFIX_0F38F9 */
4444   {
4445     { MOD_TABLE (MOD_0F38F9_PREFIX_0) },
4446   },
4447
4448   /* PREFIX_0F3A08 */
4449   {
4450     { Bad_Opcode },
4451     { Bad_Opcode },
4452     { "roundps", { XM, EXx, Ib }, PREFIX_OPCODE },
4453   },
4454
4455   /* PREFIX_0F3A09 */
4456   {
4457     { Bad_Opcode },
4458     { Bad_Opcode },
4459     { "roundpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4460   },
4461
4462   /* PREFIX_0F3A0A */
4463   {
4464     { Bad_Opcode },
4465     { Bad_Opcode },
4466     { "roundss", { XM, EXd, Ib }, PREFIX_OPCODE },
4467   },
4468
4469   /* PREFIX_0F3A0B */
4470   {
4471     { Bad_Opcode },
4472     { Bad_Opcode },
4473     { "roundsd", { XM, EXq, Ib }, PREFIX_OPCODE },
4474   },
4475
4476   /* PREFIX_0F3A0C */
4477   {
4478     { Bad_Opcode },
4479     { Bad_Opcode },
4480     { "blendps", { XM, EXx, Ib }, PREFIX_OPCODE },
4481   },
4482
4483   /* PREFIX_0F3A0D */
4484   {
4485     { Bad_Opcode },
4486     { Bad_Opcode },
4487     { "blendpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4488   },
4489
4490   /* PREFIX_0F3A0E */
4491   {
4492     { Bad_Opcode },
4493     { Bad_Opcode },
4494     { "pblendw", { XM, EXx, Ib }, PREFIX_OPCODE },
4495   },
4496
4497   /* PREFIX_0F3A14 */
4498   {
4499     { Bad_Opcode },
4500     { Bad_Opcode },
4501     { "pextrb", { Edqb, XM, Ib }, PREFIX_OPCODE },
4502   },
4503
4504   /* PREFIX_0F3A15 */
4505   {
4506     { Bad_Opcode },
4507     { Bad_Opcode },
4508     { "pextrw", { Edqw, XM, Ib }, PREFIX_OPCODE },
4509   },
4510
4511   /* PREFIX_0F3A16 */
4512   {
4513     { Bad_Opcode },
4514     { Bad_Opcode },
4515     { "pextrK", { Edq, XM, Ib }, PREFIX_OPCODE },
4516   },
4517
4518   /* PREFIX_0F3A17 */
4519   {
4520     { Bad_Opcode },
4521     { Bad_Opcode },
4522     { "extractps", { Edqd, XM, Ib }, PREFIX_OPCODE },
4523   },
4524
4525   /* PREFIX_0F3A20 */
4526   {
4527     { Bad_Opcode },
4528     { Bad_Opcode },
4529     { "pinsrb", { XM, Edqb, Ib }, PREFIX_OPCODE },
4530   },
4531
4532   /* PREFIX_0F3A21 */
4533   {
4534     { Bad_Opcode },
4535     { Bad_Opcode },
4536     { "insertps", { XM, EXd, Ib }, PREFIX_OPCODE },
4537   },
4538
4539   /* PREFIX_0F3A22 */
4540   {
4541     { Bad_Opcode },
4542     { Bad_Opcode },
4543     { "pinsrK", { XM, Edq, Ib }, PREFIX_OPCODE },
4544   },
4545
4546   /* PREFIX_0F3A40 */
4547   {
4548     { Bad_Opcode },
4549     { Bad_Opcode },
4550     { "dpps",   { XM, EXx, Ib }, PREFIX_OPCODE },
4551   },
4552
4553   /* PREFIX_0F3A41 */
4554   {
4555     { Bad_Opcode },
4556     { Bad_Opcode },
4557     { "dppd",   { XM, EXx, Ib }, PREFIX_OPCODE },
4558   },
4559
4560   /* PREFIX_0F3A42 */
4561   {
4562     { Bad_Opcode },
4563     { Bad_Opcode },
4564     { "mpsadbw", { XM, EXx, Ib }, PREFIX_OPCODE },
4565   },
4566
4567   /* PREFIX_0F3A44 */
4568   {
4569     { Bad_Opcode },
4570     { Bad_Opcode },
4571     { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_OPCODE },
4572   },
4573
4574   /* PREFIX_0F3A60 */
4575   {
4576     { Bad_Opcode },
4577     { Bad_Opcode },
4578     { "pcmpestrm", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE },
4579   },
4580
4581   /* PREFIX_0F3A61 */
4582   {
4583     { Bad_Opcode },
4584     { Bad_Opcode },
4585     { "pcmpestri", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE },
4586   },
4587
4588   /* PREFIX_0F3A62 */
4589   {
4590     { Bad_Opcode },
4591     { Bad_Opcode },
4592     { "pcmpistrm", { XM, EXx, Ib }, PREFIX_OPCODE },
4593   },
4594
4595   /* PREFIX_0F3A63 */
4596   {
4597     { Bad_Opcode },
4598     { Bad_Opcode },
4599     { "pcmpistri", { XM, EXx, Ib }, PREFIX_OPCODE },
4600   },
4601
4602   /* PREFIX_0F3ACC */
4603   {
4604     { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4605   },
4606
4607   /* PREFIX_0F3ACE */
4608   {
4609     { Bad_Opcode },
4610     { Bad_Opcode },
4611     { "gf2p8affineqb", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4612   },
4613
4614   /* PREFIX_0F3ACF */
4615   {
4616     { Bad_Opcode },
4617     { Bad_Opcode },
4618     { "gf2p8affineinvqb", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4619   },
4620
4621   /* PREFIX_0F3ADF */
4622   {
4623     { Bad_Opcode },
4624     { Bad_Opcode },
4625     { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_OPCODE },
4626   },
4627
4628   /* PREFIX_VEX_0F10 */
4629   {
4630     { "vmovups",        { XM, EXx }, 0 },
4631     { "vmovss",         { XMVexScalar, VexScalar, EXxmm_md }, 0 },
4632     { "vmovupd",        { XM, EXx }, 0 },
4633     { "vmovsd",         { XMVexScalar, VexScalar, EXxmm_mq }, 0 },
4634   },
4635
4636   /* PREFIX_VEX_0F11 */
4637   {
4638     { "vmovups",        { EXxS, XM }, 0 },
4639     { "vmovss",         { EXdVexScalarS, VexScalar, XMScalar }, 0 },
4640     { "vmovupd",        { EXxS, XM }, 0 },
4641     { "vmovsd",         { EXqVexScalarS, VexScalar, XMScalar }, 0 },
4642   },
4643
4644   /* PREFIX_VEX_0F12 */
4645   {
4646     { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
4647     { "vmovsldup",      { XM, EXx }, 0 },
4648     { MOD_TABLE (MOD_VEX_0F12_PREFIX_2) },
4649     { "vmovddup",       { XM, EXymmq }, 0 },
4650   },
4651
4652   /* PREFIX_VEX_0F16 */
4653   {
4654     { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
4655     { "vmovshdup",      { XM, EXx }, 0 },
4656     { MOD_TABLE (MOD_VEX_0F16_PREFIX_2) },
4657   },
4658
4659   /* PREFIX_VEX_0F2A */
4660   {
4661     { Bad_Opcode },
4662     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Edq }, 0 },
4663     { Bad_Opcode },
4664     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Edq }, 0 },
4665   },
4666
4667   /* PREFIX_VEX_0F2C */
4668   {
4669     { Bad_Opcode },
4670     { "vcvttss2si",     { Gdq, EXxmm_md }, 0 },
4671     { Bad_Opcode },
4672     { "vcvttsd2si",     { Gdq, EXxmm_mq }, 0 },
4673   },
4674
4675   /* PREFIX_VEX_0F2D */
4676   {
4677     { Bad_Opcode },
4678     { "vcvtss2si",      { Gdq, EXxmm_md }, 0 },
4679     { Bad_Opcode },
4680     { "vcvtsd2si",      { Gdq, EXxmm_mq }, 0 },
4681   },
4682
4683   /* PREFIX_VEX_0F2E */
4684   {
4685     { "vucomiss",       { XMScalar, EXxmm_md }, 0 },
4686     { Bad_Opcode },
4687     { "vucomisd",       { XMScalar, EXxmm_mq }, 0 },
4688   },
4689
4690   /* PREFIX_VEX_0F2F */
4691   {
4692     { "vcomiss",        { XMScalar, EXxmm_md }, 0 },
4693     { Bad_Opcode },
4694     { "vcomisd",        { XMScalar, EXxmm_mq }, 0 },
4695   },
4696
4697   /* PREFIX_VEX_0F41 */
4698   {
4699     { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) },
4700     { Bad_Opcode },
4701     { VEX_LEN_TABLE (VEX_LEN_0F41_P_2) },
4702   },
4703
4704   /* PREFIX_VEX_0F42 */
4705   {
4706     { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) },
4707     { Bad_Opcode },
4708     { VEX_LEN_TABLE (VEX_LEN_0F42_P_2) },
4709   },
4710
4711   /* PREFIX_VEX_0F44 */
4712   {
4713     { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) },
4714     { Bad_Opcode },
4715     { VEX_LEN_TABLE (VEX_LEN_0F44_P_2) },
4716   },
4717
4718   /* PREFIX_VEX_0F45 */
4719   {
4720     { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) },
4721     { Bad_Opcode },
4722     { VEX_LEN_TABLE (VEX_LEN_0F45_P_2) },
4723   },
4724
4725   /* PREFIX_VEX_0F46 */
4726   {
4727     { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) },
4728     { Bad_Opcode },
4729     { VEX_LEN_TABLE (VEX_LEN_0F46_P_2) },
4730   },
4731
4732   /* PREFIX_VEX_0F47 */
4733   {
4734     { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) },
4735     { Bad_Opcode },
4736     { VEX_LEN_TABLE (VEX_LEN_0F47_P_2) },
4737   },
4738
4739   /* PREFIX_VEX_0F4A */
4740   {
4741     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0) },
4742     { Bad_Opcode },
4743     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2) },
4744   },
4745
4746   /* PREFIX_VEX_0F4B */
4747   {
4748     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0) },
4749     { Bad_Opcode },
4750     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) },
4751   },
4752
4753   /* PREFIX_VEX_0F51 */
4754   {
4755     { "vsqrtps",        { XM, EXx }, 0 },
4756     { "vsqrtss",        { XMScalar, VexScalar, EXxmm_md }, 0 },
4757     { "vsqrtpd",        { XM, EXx }, 0 },
4758     { "vsqrtsd",        { XMScalar, VexScalar, EXxmm_mq }, 0 },
4759   },
4760
4761   /* PREFIX_VEX_0F52 */
4762   {
4763     { "vrsqrtps",       { XM, EXx }, 0 },
4764     { "vrsqrtss",       { XMScalar, VexScalar, EXxmm_md }, 0 },
4765   },
4766
4767   /* PREFIX_VEX_0F53 */
4768   {
4769     { "vrcpps",         { XM, EXx }, 0 },
4770     { "vrcpss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
4771   },
4772
4773   /* PREFIX_VEX_0F58 */
4774   {
4775     { "vaddps",         { XM, Vex, EXx }, 0 },
4776     { "vaddss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
4777     { "vaddpd",         { XM, Vex, EXx }, 0 },
4778     { "vaddsd",         { XMScalar, VexScalar, EXxmm_mq }, 0 },
4779   },
4780
4781   /* PREFIX_VEX_0F59 */
4782   {
4783     { "vmulps",         { XM, Vex, EXx }, 0 },
4784     { "vmulss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
4785     { "vmulpd",         { XM, Vex, EXx }, 0 },
4786     { "vmulsd",         { XMScalar, VexScalar, EXxmm_mq }, 0 },
4787   },
4788
4789   /* PREFIX_VEX_0F5A */
4790   {
4791     { "vcvtps2pd",      { XM, EXxmmq }, 0 },
4792     { "vcvtss2sd",      { XMScalar, VexScalar, EXxmm_md }, 0 },
4793     { "vcvtpd2ps%XY",{ XMM, EXx }, 0 },
4794     { "vcvtsd2ss",      { XMScalar, VexScalar, EXxmm_mq }, 0 },
4795   },
4796
4797   /* PREFIX_VEX_0F5B */
4798   {
4799     { "vcvtdq2ps",      { XM, EXx }, 0 },
4800     { "vcvttps2dq",     { XM, EXx }, 0 },
4801     { "vcvtps2dq",      { XM, EXx }, 0 },
4802   },
4803
4804   /* PREFIX_VEX_0F5C */
4805   {
4806     { "vsubps",         { XM, Vex, EXx }, 0 },
4807     { "vsubss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
4808     { "vsubpd",         { XM, Vex, EXx }, 0 },
4809     { "vsubsd",         { XMScalar, VexScalar, EXxmm_mq }, 0 },
4810   },
4811
4812   /* PREFIX_VEX_0F5D */
4813   {
4814     { "vminps",         { XM, Vex, EXx }, 0 },
4815     { "vminss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
4816     { "vminpd",         { XM, Vex, EXx }, 0 },
4817     { "vminsd",         { XMScalar, VexScalar, EXxmm_mq }, 0 },
4818   },
4819
4820   /* PREFIX_VEX_0F5E */
4821   {
4822     { "vdivps",         { XM, Vex, EXx }, 0 },
4823     { "vdivss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
4824     { "vdivpd",         { XM, Vex, EXx }, 0 },
4825     { "vdivsd",         { XMScalar, VexScalar, EXxmm_mq }, 0 },
4826   },
4827
4828   /* PREFIX_VEX_0F5F */
4829   {
4830     { "vmaxps",         { XM, Vex, EXx }, 0 },
4831     { "vmaxss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
4832     { "vmaxpd",         { XM, Vex, EXx }, 0 },
4833     { "vmaxsd",         { XMScalar, VexScalar, EXxmm_mq }, 0 },
4834   },
4835
4836   /* PREFIX_VEX_0F60 */
4837   {
4838     { Bad_Opcode },
4839     { Bad_Opcode },
4840     { "vpunpcklbw",     { XM, Vex, EXx }, 0 },
4841   },
4842
4843   /* PREFIX_VEX_0F61 */
4844   {
4845     { Bad_Opcode },
4846     { Bad_Opcode },
4847     { "vpunpcklwd",     { XM, Vex, EXx }, 0 },
4848   },
4849
4850   /* PREFIX_VEX_0F62 */
4851   {
4852     { Bad_Opcode },
4853     { Bad_Opcode },
4854     { "vpunpckldq",     { XM, Vex, EXx }, 0 },
4855   },
4856
4857   /* PREFIX_VEX_0F63 */
4858   {
4859     { Bad_Opcode },
4860     { Bad_Opcode },
4861     { "vpacksswb",      { XM, Vex, EXx }, 0 },
4862   },
4863
4864   /* PREFIX_VEX_0F64 */
4865   {
4866     { Bad_Opcode },
4867     { Bad_Opcode },
4868     { "vpcmpgtb",       { XM, Vex, EXx }, 0 },
4869   },
4870
4871   /* PREFIX_VEX_0F65 */
4872   {
4873     { Bad_Opcode },
4874     { Bad_Opcode },
4875     { "vpcmpgtw",       { XM, Vex, EXx }, 0 },
4876   },
4877
4878   /* PREFIX_VEX_0F66 */
4879   {
4880     { Bad_Opcode },
4881     { Bad_Opcode },
4882     { "vpcmpgtd",       { XM, Vex, EXx }, 0 },
4883   },
4884
4885   /* PREFIX_VEX_0F67 */
4886   {
4887     { Bad_Opcode },
4888     { Bad_Opcode },
4889     { "vpackuswb",      { XM, Vex, EXx }, 0 },
4890   },
4891
4892   /* PREFIX_VEX_0F68 */
4893   {
4894     { Bad_Opcode },
4895     { Bad_Opcode },
4896     { "vpunpckhbw",     { XM, Vex, EXx }, 0 },
4897   },
4898
4899   /* PREFIX_VEX_0F69 */
4900   {
4901     { Bad_Opcode },
4902     { Bad_Opcode },
4903     { "vpunpckhwd",     { XM, Vex, EXx }, 0 },
4904   },
4905
4906   /* PREFIX_VEX_0F6A */
4907   {
4908     { Bad_Opcode },
4909     { Bad_Opcode },
4910     { "vpunpckhdq",     { XM, Vex, EXx }, 0 },
4911   },
4912
4913   /* PREFIX_VEX_0F6B */
4914   {
4915     { Bad_Opcode },
4916     { Bad_Opcode },
4917     { "vpackssdw",      { XM, Vex, EXx }, 0 },
4918   },
4919
4920   /* PREFIX_VEX_0F6C */
4921   {
4922     { Bad_Opcode },
4923     { Bad_Opcode },
4924     { "vpunpcklqdq",    { XM, Vex, EXx }, 0 },
4925   },
4926
4927   /* PREFIX_VEX_0F6D */
4928   {
4929     { Bad_Opcode },
4930     { Bad_Opcode },
4931     { "vpunpckhqdq",    { XM, Vex, EXx }, 0 },
4932   },
4933
4934   /* PREFIX_VEX_0F6E */
4935   {
4936     { Bad_Opcode },
4937     { Bad_Opcode },
4938     { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) },
4939   },
4940
4941   /* PREFIX_VEX_0F6F */
4942   {
4943     { Bad_Opcode },
4944     { "vmovdqu",        { XM, EXx }, 0 },
4945     { "vmovdqa",        { XM, EXx }, 0 },
4946   },
4947
4948   /* PREFIX_VEX_0F70 */
4949   {
4950     { Bad_Opcode },
4951     { "vpshufhw",       { XM, EXx, Ib }, 0 },
4952     { "vpshufd",        { XM, EXx, Ib }, 0 },
4953     { "vpshuflw",       { XM, EXx, Ib }, 0 },
4954   },
4955
4956   /* PREFIX_VEX_0F71_REG_2 */
4957   {
4958     { Bad_Opcode },
4959     { Bad_Opcode },
4960     { "vpsrlw",         { Vex, XS, Ib }, 0 },
4961   },
4962
4963   /* PREFIX_VEX_0F71_REG_4 */
4964   {
4965     { Bad_Opcode },
4966     { Bad_Opcode },
4967     { "vpsraw",         { Vex, XS, Ib }, 0 },
4968   },
4969
4970   /* PREFIX_VEX_0F71_REG_6 */
4971   {
4972     { Bad_Opcode },
4973     { Bad_Opcode },
4974     { "vpsllw",         { Vex, XS, Ib }, 0 },
4975   },
4976
4977   /* PREFIX_VEX_0F72_REG_2 */
4978   {
4979     { Bad_Opcode },
4980     { Bad_Opcode },
4981     { "vpsrld",         { Vex, XS, Ib }, 0 },
4982   },
4983
4984   /* PREFIX_VEX_0F72_REG_4 */
4985   {
4986     { Bad_Opcode },
4987     { Bad_Opcode },
4988     { "vpsrad",         { Vex, XS, Ib }, 0 },
4989   },
4990
4991   /* PREFIX_VEX_0F72_REG_6 */
4992   {
4993     { Bad_Opcode },
4994     { Bad_Opcode },
4995     { "vpslld",         { Vex, XS, Ib }, 0 },
4996   },
4997
4998   /* PREFIX_VEX_0F73_REG_2 */
4999   {
5000     { Bad_Opcode },
5001     { Bad_Opcode },
5002     { "vpsrlq",         { Vex, XS, Ib }, 0 },
5003   },
5004
5005   /* PREFIX_VEX_0F73_REG_3 */
5006   {
5007     { Bad_Opcode },
5008     { Bad_Opcode },
5009     { "vpsrldq",        { Vex, XS, Ib }, 0 },
5010   },
5011
5012   /* PREFIX_VEX_0F73_REG_6 */
5013   {
5014     { Bad_Opcode },
5015     { Bad_Opcode },
5016     { "vpsllq",         { Vex, XS, Ib }, 0 },
5017   },
5018
5019   /* PREFIX_VEX_0F73_REG_7 */
5020   {
5021     { Bad_Opcode },
5022     { Bad_Opcode },
5023     { "vpslldq",        { Vex, XS, Ib }, 0 },
5024   },
5025
5026   /* PREFIX_VEX_0F74 */
5027   {
5028     { Bad_Opcode },
5029     { Bad_Opcode },
5030     { "vpcmpeqb",       { XM, Vex, EXx }, 0 },
5031   },
5032
5033   /* PREFIX_VEX_0F75 */
5034   {
5035     { Bad_Opcode },
5036     { Bad_Opcode },
5037     { "vpcmpeqw",       { XM, Vex, EXx }, 0 },
5038   },
5039
5040   /* PREFIX_VEX_0F76 */
5041   {
5042     { Bad_Opcode },
5043     { Bad_Opcode },
5044     { "vpcmpeqd",       { XM, Vex, EXx }, 0 },
5045   },
5046
5047   /* PREFIX_VEX_0F77 */
5048   {
5049     { VEX_LEN_TABLE (VEX_LEN_0F77_P_0) },
5050   },
5051
5052   /* PREFIX_VEX_0F7C */
5053   {
5054     { Bad_Opcode },
5055     { Bad_Opcode },
5056     { "vhaddpd",        { XM, Vex, EXx }, 0 },
5057     { "vhaddps",        { XM, Vex, EXx }, 0 },
5058   },
5059
5060   /* PREFIX_VEX_0F7D */
5061   {
5062     { Bad_Opcode },
5063     { Bad_Opcode },
5064     { "vhsubpd",        { XM, Vex, EXx }, 0 },
5065     { "vhsubps",        { XM, Vex, EXx }, 0 },
5066   },
5067
5068   /* PREFIX_VEX_0F7E */
5069   {
5070     { Bad_Opcode },
5071     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
5072     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
5073   },
5074
5075   /* PREFIX_VEX_0F7F */
5076   {
5077     { Bad_Opcode },
5078     { "vmovdqu",        { EXxS, XM }, 0 },
5079     { "vmovdqa",        { EXxS, XM }, 0 },
5080   },
5081
5082   /* PREFIX_VEX_0F90 */
5083   {
5084     { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) },
5085     { Bad_Opcode },
5086     { VEX_LEN_TABLE (VEX_LEN_0F90_P_2) },
5087   },
5088
5089   /* PREFIX_VEX_0F91 */
5090   {
5091     { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) },
5092     { Bad_Opcode },
5093     { VEX_LEN_TABLE (VEX_LEN_0F91_P_2) },
5094   },
5095
5096   /* PREFIX_VEX_0F92 */
5097   {
5098     { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) },
5099     { Bad_Opcode },
5100     { VEX_LEN_TABLE (VEX_LEN_0F92_P_2) },
5101     { VEX_LEN_TABLE (VEX_LEN_0F92_P_3) },
5102   },
5103
5104   /* PREFIX_VEX_0F93 */
5105   {
5106     { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) },
5107     { Bad_Opcode },
5108     { VEX_LEN_TABLE (VEX_LEN_0F93_P_2) },
5109     { VEX_LEN_TABLE (VEX_LEN_0F93_P_3) },
5110   },
5111
5112   /* PREFIX_VEX_0F98 */
5113   {
5114     { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) },
5115     { Bad_Opcode },
5116     { VEX_LEN_TABLE (VEX_LEN_0F98_P_2) },
5117   },
5118
5119   /* PREFIX_VEX_0F99 */
5120   {
5121     { VEX_LEN_TABLE (VEX_LEN_0F99_P_0) },
5122     { Bad_Opcode },
5123     { VEX_LEN_TABLE (VEX_LEN_0F99_P_2) },
5124   },
5125
5126   /* PREFIX_VEX_0FC2 */
5127   {
5128     { "vcmpps",         { XM, Vex, EXx, VCMP }, 0 },
5129     { "vcmpss",         { XMScalar, VexScalar, EXxmm_md, VCMP }, 0 },
5130     { "vcmppd",         { XM, Vex, EXx, VCMP }, 0 },
5131     { "vcmpsd",         { XMScalar, VexScalar, EXxmm_mq, VCMP }, 0 },
5132   },
5133
5134   /* PREFIX_VEX_0FC4 */
5135   {
5136     { Bad_Opcode },
5137     { Bad_Opcode },
5138     { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) },
5139   },
5140
5141   /* PREFIX_VEX_0FC5 */
5142   {
5143     { Bad_Opcode },
5144     { Bad_Opcode },
5145     { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) },
5146   },
5147
5148   /* PREFIX_VEX_0FD0 */
5149   {
5150     { Bad_Opcode },
5151     { Bad_Opcode },
5152     { "vaddsubpd",      { XM, Vex, EXx }, 0 },
5153     { "vaddsubps",      { XM, Vex, EXx }, 0 },
5154   },
5155
5156   /* PREFIX_VEX_0FD1 */
5157   {
5158     { Bad_Opcode },
5159     { Bad_Opcode },
5160     { "vpsrlw",         { XM, Vex, EXxmm }, 0 },
5161   },
5162
5163   /* PREFIX_VEX_0FD2 */
5164   {
5165     { Bad_Opcode },
5166     { Bad_Opcode },
5167     { "vpsrld",         { XM, Vex, EXxmm }, 0 },
5168   },
5169
5170   /* PREFIX_VEX_0FD3 */
5171   {
5172     { Bad_Opcode },
5173     { Bad_Opcode },
5174     { "vpsrlq",         { XM, Vex, EXxmm }, 0 },
5175   },
5176
5177   /* PREFIX_VEX_0FD4 */
5178   {
5179     { Bad_Opcode },
5180     { Bad_Opcode },
5181     { "vpaddq",         { XM, Vex, EXx }, 0 },
5182   },
5183
5184   /* PREFIX_VEX_0FD5 */
5185   {
5186     { Bad_Opcode },
5187     { Bad_Opcode },
5188     { "vpmullw",        { XM, Vex, EXx }, 0 },
5189   },
5190
5191   /* PREFIX_VEX_0FD6 */
5192   {
5193     { Bad_Opcode },
5194     { Bad_Opcode },
5195     { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) },
5196   },
5197
5198   /* PREFIX_VEX_0FD7 */
5199   {
5200     { Bad_Opcode },
5201     { Bad_Opcode },
5202     { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) },
5203   },
5204
5205   /* PREFIX_VEX_0FD8 */
5206   {
5207     { Bad_Opcode },
5208     { Bad_Opcode },
5209     { "vpsubusb",       { XM, Vex, EXx }, 0 },
5210   },
5211
5212   /* PREFIX_VEX_0FD9 */
5213   {
5214     { Bad_Opcode },
5215     { Bad_Opcode },
5216     { "vpsubusw",       { XM, Vex, EXx }, 0 },
5217   },
5218
5219   /* PREFIX_VEX_0FDA */
5220   {
5221     { Bad_Opcode },
5222     { Bad_Opcode },
5223     { "vpminub",        { XM, Vex, EXx }, 0 },
5224   },
5225
5226   /* PREFIX_VEX_0FDB */
5227   {
5228     { Bad_Opcode },
5229     { Bad_Opcode },
5230     { "vpand",          { XM, Vex, EXx }, 0 },
5231   },
5232
5233   /* PREFIX_VEX_0FDC */
5234   {
5235     { Bad_Opcode },
5236     { Bad_Opcode },
5237     { "vpaddusb",       { XM, Vex, EXx }, 0 },
5238   },
5239
5240   /* PREFIX_VEX_0FDD */
5241   {
5242     { Bad_Opcode },
5243     { Bad_Opcode },
5244     { "vpaddusw",       { XM, Vex, EXx }, 0 },
5245   },
5246
5247   /* PREFIX_VEX_0FDE */
5248   {
5249     { Bad_Opcode },
5250     { Bad_Opcode },
5251     { "vpmaxub",        { XM, Vex, EXx }, 0 },
5252   },
5253
5254   /* PREFIX_VEX_0FDF */
5255   {
5256     { Bad_Opcode },
5257     { Bad_Opcode },
5258     { "vpandn",         { XM, Vex, EXx }, 0 },
5259   },
5260
5261   /* PREFIX_VEX_0FE0 */
5262   {
5263     { Bad_Opcode },
5264     { Bad_Opcode },
5265     { "vpavgb",         { XM, Vex, EXx }, 0 },
5266   },
5267
5268   /* PREFIX_VEX_0FE1 */
5269   {
5270     { Bad_Opcode },
5271     { Bad_Opcode },
5272     { "vpsraw",         { XM, Vex, EXxmm }, 0 },
5273   },
5274
5275   /* PREFIX_VEX_0FE2 */
5276   {
5277     { Bad_Opcode },
5278     { Bad_Opcode },
5279     { "vpsrad",         { XM, Vex, EXxmm }, 0 },
5280   },
5281
5282   /* PREFIX_VEX_0FE3 */
5283   {
5284     { Bad_Opcode },
5285     { Bad_Opcode },
5286     { "vpavgw",         { XM, Vex, EXx }, 0 },
5287   },
5288
5289   /* PREFIX_VEX_0FE4 */
5290   {
5291     { Bad_Opcode },
5292     { Bad_Opcode },
5293     { "vpmulhuw",       { XM, Vex, EXx }, 0 },
5294   },
5295
5296   /* PREFIX_VEX_0FE5 */
5297   {
5298     { Bad_Opcode },
5299     { Bad_Opcode },
5300     { "vpmulhw",        { XM, Vex, EXx }, 0 },
5301   },
5302
5303   /* PREFIX_VEX_0FE6 */
5304   {
5305     { Bad_Opcode },
5306     { "vcvtdq2pd",      { XM, EXxmmq }, 0 },
5307     { "vcvttpd2dq%XY",  { XMM, EXx }, 0 },
5308     { "vcvtpd2dq%XY",   { XMM, EXx }, 0 },
5309   },
5310
5311   /* PREFIX_VEX_0FE7 */
5312   {
5313     { Bad_Opcode },
5314     { Bad_Opcode },
5315     { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) },
5316   },
5317
5318   /* PREFIX_VEX_0FE8 */
5319   {
5320     { Bad_Opcode },
5321     { Bad_Opcode },
5322     { "vpsubsb",        { XM, Vex, EXx }, 0 },
5323   },
5324
5325   /* PREFIX_VEX_0FE9 */
5326   {
5327     { Bad_Opcode },
5328     { Bad_Opcode },
5329     { "vpsubsw",        { XM, Vex, EXx }, 0 },
5330   },
5331
5332   /* PREFIX_VEX_0FEA */
5333   {
5334     { Bad_Opcode },
5335     { Bad_Opcode },
5336     { "vpminsw",        { XM, Vex, EXx }, 0 },
5337   },
5338
5339   /* PREFIX_VEX_0FEB */
5340   {
5341     { Bad_Opcode },
5342     { Bad_Opcode },
5343     { "vpor",           { XM, Vex, EXx }, 0 },
5344   },
5345
5346   /* PREFIX_VEX_0FEC */
5347   {
5348     { Bad_Opcode },
5349     { Bad_Opcode },
5350     { "vpaddsb",        { XM, Vex, EXx }, 0 },
5351   },
5352
5353   /* PREFIX_VEX_0FED */
5354   {
5355     { Bad_Opcode },
5356     { Bad_Opcode },
5357     { "vpaddsw",        { XM, Vex, EXx }, 0 },
5358   },
5359
5360   /* PREFIX_VEX_0FEE */
5361   {
5362     { Bad_Opcode },
5363     { Bad_Opcode },
5364     { "vpmaxsw",        { XM, Vex, EXx }, 0 },
5365   },
5366
5367   /* PREFIX_VEX_0FEF */
5368   {
5369     { Bad_Opcode },
5370     { Bad_Opcode },
5371     { "vpxor",          { XM, Vex, EXx }, 0 },
5372   },
5373
5374   /* PREFIX_VEX_0FF0 */
5375   {
5376     { Bad_Opcode },
5377     { Bad_Opcode },
5378     { Bad_Opcode },
5379     { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
5380   },
5381
5382   /* PREFIX_VEX_0FF1 */
5383   {
5384     { Bad_Opcode },
5385     { Bad_Opcode },
5386     { "vpsllw",         { XM, Vex, EXxmm }, 0 },
5387   },
5388
5389   /* PREFIX_VEX_0FF2 */
5390   {
5391     { Bad_Opcode },
5392     { Bad_Opcode },
5393     { "vpslld",         { XM, Vex, EXxmm }, 0 },
5394   },
5395
5396   /* PREFIX_VEX_0FF3 */
5397   {
5398     { Bad_Opcode },
5399     { Bad_Opcode },
5400     { "vpsllq",         { XM, Vex, EXxmm }, 0 },
5401   },
5402
5403   /* PREFIX_VEX_0FF4 */
5404   {
5405     { Bad_Opcode },
5406     { Bad_Opcode },
5407     { "vpmuludq",       { XM, Vex, EXx }, 0 },
5408   },
5409
5410   /* PREFIX_VEX_0FF5 */
5411   {
5412     { Bad_Opcode },
5413     { Bad_Opcode },
5414     { "vpmaddwd",       { XM, Vex, EXx }, 0 },
5415   },
5416
5417   /* PREFIX_VEX_0FF6 */
5418   {
5419     { Bad_Opcode },
5420     { Bad_Opcode },
5421     { "vpsadbw",        { XM, Vex, EXx }, 0 },
5422   },
5423
5424   /* PREFIX_VEX_0FF7 */
5425   {
5426     { Bad_Opcode },
5427     { Bad_Opcode },
5428     { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) },
5429   },
5430
5431   /* PREFIX_VEX_0FF8 */
5432   {
5433     { Bad_Opcode },
5434     { Bad_Opcode },
5435     { "vpsubb",         { XM, Vex, EXx }, 0 },
5436   },
5437
5438   /* PREFIX_VEX_0FF9 */
5439   {
5440     { Bad_Opcode },
5441     { Bad_Opcode },
5442     { "vpsubw",         { XM, Vex, EXx }, 0 },
5443   },
5444
5445   /* PREFIX_VEX_0FFA */
5446   {
5447     { Bad_Opcode },
5448     { Bad_Opcode },
5449     { "vpsubd",         { XM, Vex, EXx }, 0 },
5450   },
5451
5452   /* PREFIX_VEX_0FFB */
5453   {
5454     { Bad_Opcode },
5455     { Bad_Opcode },
5456     { "vpsubq",         { XM, Vex, EXx }, 0 },
5457   },
5458
5459   /* PREFIX_VEX_0FFC */
5460   {
5461     { Bad_Opcode },
5462     { Bad_Opcode },
5463     { "vpaddb",         { XM, Vex, EXx }, 0 },
5464   },
5465
5466   /* PREFIX_VEX_0FFD */
5467   {
5468     { Bad_Opcode },
5469     { Bad_Opcode },
5470     { "vpaddw",         { XM, Vex, EXx }, 0 },
5471   },
5472
5473   /* PREFIX_VEX_0FFE */
5474   {
5475     { Bad_Opcode },
5476     { Bad_Opcode },
5477     { "vpaddd",         { XM, Vex, EXx }, 0 },
5478   },
5479
5480   /* PREFIX_VEX_0F3800 */
5481   {
5482     { Bad_Opcode },
5483     { Bad_Opcode },
5484     { "vpshufb",        { XM, Vex, EXx }, 0 },
5485   },
5486
5487   /* PREFIX_VEX_0F3801 */
5488   {
5489     { Bad_Opcode },
5490     { Bad_Opcode },
5491     { "vphaddw",        { XM, Vex, EXx }, 0 },
5492   },
5493
5494   /* PREFIX_VEX_0F3802 */
5495   {
5496     { Bad_Opcode },
5497     { Bad_Opcode },
5498     { "vphaddd",        { XM, Vex, EXx }, 0 },
5499   },
5500
5501   /* PREFIX_VEX_0F3803 */
5502   {
5503     { Bad_Opcode },
5504     { Bad_Opcode },
5505     { "vphaddsw",       { XM, Vex, EXx }, 0 },
5506   },
5507
5508   /* PREFIX_VEX_0F3804 */
5509   {
5510     { Bad_Opcode },
5511     { Bad_Opcode },
5512     { "vpmaddubsw",     { XM, Vex, EXx }, 0 },
5513   },
5514
5515   /* PREFIX_VEX_0F3805 */
5516   {
5517     { Bad_Opcode },
5518     { Bad_Opcode },
5519     { "vphsubw",        { XM, Vex, EXx }, 0 },
5520   },
5521
5522   /* PREFIX_VEX_0F3806 */
5523   {
5524     { Bad_Opcode },
5525     { Bad_Opcode },
5526     { "vphsubd",        { XM, Vex, EXx }, 0 },
5527   },
5528
5529   /* PREFIX_VEX_0F3807 */
5530   {
5531     { Bad_Opcode },
5532     { Bad_Opcode },
5533     { "vphsubsw",       { XM, Vex, EXx }, 0 },
5534   },
5535
5536   /* PREFIX_VEX_0F3808 */
5537   {
5538     { Bad_Opcode },
5539     { Bad_Opcode },
5540     { "vpsignb",        { XM, Vex, EXx }, 0 },
5541   },
5542
5543   /* PREFIX_VEX_0F3809 */
5544   {
5545     { Bad_Opcode },
5546     { Bad_Opcode },
5547     { "vpsignw",        { XM, Vex, EXx }, 0 },
5548   },
5549
5550   /* PREFIX_VEX_0F380A */
5551   {
5552     { Bad_Opcode },
5553     { Bad_Opcode },
5554     { "vpsignd",        { XM, Vex, EXx }, 0 },
5555   },
5556
5557   /* PREFIX_VEX_0F380B */
5558   {
5559     { Bad_Opcode },
5560     { Bad_Opcode },
5561     { "vpmulhrsw",      { XM, Vex, EXx }, 0 },
5562   },
5563
5564   /* PREFIX_VEX_0F380C */
5565   {
5566     { Bad_Opcode },
5567     { Bad_Opcode },
5568     { VEX_W_TABLE (VEX_W_0F380C_P_2) },
5569   },
5570
5571   /* PREFIX_VEX_0F380D */
5572   {
5573     { Bad_Opcode },
5574     { Bad_Opcode },
5575     { VEX_W_TABLE (VEX_W_0F380D_P_2) },
5576   },
5577
5578   /* PREFIX_VEX_0F380E */
5579   {
5580     { Bad_Opcode },
5581     { Bad_Opcode },
5582     { VEX_W_TABLE (VEX_W_0F380E_P_2) },
5583   },
5584
5585   /* PREFIX_VEX_0F380F */
5586   {
5587     { Bad_Opcode },
5588     { Bad_Opcode },
5589     { VEX_W_TABLE (VEX_W_0F380F_P_2) },
5590   },
5591
5592   /* PREFIX_VEX_0F3813 */
5593   {
5594     { Bad_Opcode },
5595     { Bad_Opcode },
5596     { "vcvtph2ps", { XM, EXxmmq }, 0 },
5597   },
5598
5599   /* PREFIX_VEX_0F3816 */
5600   {
5601     { Bad_Opcode },
5602     { Bad_Opcode },
5603     { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) },
5604   },
5605
5606   /* PREFIX_VEX_0F3817 */
5607   {
5608     { Bad_Opcode },
5609     { Bad_Opcode },
5610     { "vptest",         { XM, EXx }, 0 },
5611   },
5612
5613   /* PREFIX_VEX_0F3818 */
5614   {
5615     { Bad_Opcode },
5616     { Bad_Opcode },
5617     { VEX_W_TABLE (VEX_W_0F3818_P_2) },
5618   },
5619
5620   /* PREFIX_VEX_0F3819 */
5621   {
5622     { Bad_Opcode },
5623     { Bad_Opcode },
5624     { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) },
5625   },
5626
5627   /* PREFIX_VEX_0F381A */
5628   {
5629     { Bad_Opcode },
5630     { Bad_Opcode },
5631     { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) },
5632   },
5633
5634   /* PREFIX_VEX_0F381C */
5635   {
5636     { Bad_Opcode },
5637     { Bad_Opcode },
5638     { "vpabsb",         { XM, EXx }, 0 },
5639   },
5640
5641   /* PREFIX_VEX_0F381D */
5642   {
5643     { Bad_Opcode },
5644     { Bad_Opcode },
5645     { "vpabsw",         { XM, EXx }, 0 },
5646   },
5647
5648   /* PREFIX_VEX_0F381E */
5649   {
5650     { Bad_Opcode },
5651     { Bad_Opcode },
5652     { "vpabsd",         { XM, EXx }, 0 },
5653   },
5654
5655   /* PREFIX_VEX_0F3820 */
5656   {
5657     { Bad_Opcode },
5658     { Bad_Opcode },
5659     { "vpmovsxbw",      { XM, EXxmmq }, 0 },
5660   },
5661
5662   /* PREFIX_VEX_0F3821 */
5663   {
5664     { Bad_Opcode },
5665     { Bad_Opcode },
5666     { "vpmovsxbd",      { XM, EXxmmqd }, 0 },
5667   },
5668
5669   /* PREFIX_VEX_0F3822 */
5670   {
5671     { Bad_Opcode },
5672     { Bad_Opcode },
5673     { "vpmovsxbq",      { XM, EXxmmdw }, 0 },
5674   },
5675
5676   /* PREFIX_VEX_0F3823 */
5677   {
5678     { Bad_Opcode },
5679     { Bad_Opcode },
5680     { "vpmovsxwd",      { XM, EXxmmq }, 0 },
5681   },
5682
5683   /* PREFIX_VEX_0F3824 */
5684   {
5685     { Bad_Opcode },
5686     { Bad_Opcode },
5687     { "vpmovsxwq",      { XM, EXxmmqd }, 0 },
5688   },
5689
5690   /* PREFIX_VEX_0F3825 */
5691   {
5692     { Bad_Opcode },
5693     { Bad_Opcode },
5694     { "vpmovsxdq",      { XM, EXxmmq }, 0 },
5695   },
5696
5697   /* PREFIX_VEX_0F3828 */
5698   {
5699     { Bad_Opcode },
5700     { Bad_Opcode },
5701     { "vpmuldq",        { XM, Vex, EXx }, 0 },
5702   },
5703
5704   /* PREFIX_VEX_0F3829 */
5705   {
5706     { Bad_Opcode },
5707     { Bad_Opcode },
5708     { "vpcmpeqq",       { XM, Vex, EXx }, 0 },
5709   },
5710
5711   /* PREFIX_VEX_0F382A */
5712   {
5713     { Bad_Opcode },
5714     { Bad_Opcode },
5715     { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) },
5716   },
5717
5718   /* PREFIX_VEX_0F382B */
5719   {
5720     { Bad_Opcode },
5721     { Bad_Opcode },
5722     { "vpackusdw",      { XM, Vex, EXx }, 0 },
5723   },
5724
5725   /* PREFIX_VEX_0F382C */
5726   {
5727     { Bad_Opcode },
5728     { Bad_Opcode },
5729      { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) },
5730   },
5731
5732   /* PREFIX_VEX_0F382D */
5733   {
5734     { Bad_Opcode },
5735     { Bad_Opcode },
5736      { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) },
5737   },
5738
5739   /* PREFIX_VEX_0F382E */
5740   {
5741     { Bad_Opcode },
5742     { Bad_Opcode },
5743      { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) },
5744   },
5745
5746   /* PREFIX_VEX_0F382F */
5747   {
5748     { Bad_Opcode },
5749     { Bad_Opcode },
5750      { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) },
5751   },
5752
5753   /* PREFIX_VEX_0F3830 */
5754   {
5755     { Bad_Opcode },
5756     { Bad_Opcode },
5757     { "vpmovzxbw",      { XM, EXxmmq }, 0 },
5758   },
5759
5760   /* PREFIX_VEX_0F3831 */
5761   {
5762     { Bad_Opcode },
5763     { Bad_Opcode },
5764     { "vpmovzxbd",      { XM, EXxmmqd }, 0 },
5765   },
5766
5767   /* PREFIX_VEX_0F3832 */
5768   {
5769     { Bad_Opcode },
5770     { Bad_Opcode },
5771     { "vpmovzxbq",      { XM, EXxmmdw }, 0 },
5772   },
5773
5774   /* PREFIX_VEX_0F3833 */
5775   {
5776     { Bad_Opcode },
5777     { Bad_Opcode },
5778     { "vpmovzxwd",      { XM, EXxmmq }, 0 },
5779   },
5780
5781   /* PREFIX_VEX_0F3834 */
5782   {
5783     { Bad_Opcode },
5784     { Bad_Opcode },
5785     { "vpmovzxwq",      { XM, EXxmmqd }, 0 },
5786   },
5787
5788   /* PREFIX_VEX_0F3835 */
5789   {
5790     { Bad_Opcode },
5791     { Bad_Opcode },
5792     { "vpmovzxdq",      { XM, EXxmmq }, 0 },
5793   },
5794
5795   /* PREFIX_VEX_0F3836 */
5796   {
5797     { Bad_Opcode },
5798     { Bad_Opcode },
5799     { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) },
5800   },
5801
5802   /* PREFIX_VEX_0F3837 */
5803   {
5804     { Bad_Opcode },
5805     { Bad_Opcode },
5806     { "vpcmpgtq",       { XM, Vex, EXx }, 0 },
5807   },
5808
5809   /* PREFIX_VEX_0F3838 */
5810   {
5811     { Bad_Opcode },
5812     { Bad_Opcode },
5813     { "vpminsb",        { XM, Vex, EXx }, 0 },
5814   },
5815
5816   /* PREFIX_VEX_0F3839 */
5817   {
5818     { Bad_Opcode },
5819     { Bad_Opcode },
5820     { "vpminsd",        { XM, Vex, EXx }, 0 },
5821   },
5822
5823   /* PREFIX_VEX_0F383A */
5824   {
5825     { Bad_Opcode },
5826     { Bad_Opcode },
5827     { "vpminuw",        { XM, Vex, EXx }, 0 },
5828   },
5829
5830   /* PREFIX_VEX_0F383B */
5831   {
5832     { Bad_Opcode },
5833     { Bad_Opcode },
5834     { "vpminud",        { XM, Vex, EXx }, 0 },
5835   },
5836
5837   /* PREFIX_VEX_0F383C */
5838   {
5839     { Bad_Opcode },
5840     { Bad_Opcode },
5841     { "vpmaxsb",        { XM, Vex, EXx }, 0 },
5842   },
5843
5844   /* PREFIX_VEX_0F383D */
5845   {
5846     { Bad_Opcode },
5847     { Bad_Opcode },
5848     { "vpmaxsd",        { XM, Vex, EXx }, 0 },
5849   },
5850
5851   /* PREFIX_VEX_0F383E */
5852   {
5853     { Bad_Opcode },
5854     { Bad_Opcode },
5855     { "vpmaxuw",        { XM, Vex, EXx }, 0 },
5856   },
5857
5858   /* PREFIX_VEX_0F383F */
5859   {
5860     { Bad_Opcode },
5861     { Bad_Opcode },
5862     { "vpmaxud",        { XM, Vex, EXx }, 0 },
5863   },
5864
5865   /* PREFIX_VEX_0F3840 */
5866   {
5867     { Bad_Opcode },
5868     { Bad_Opcode },
5869     { "vpmulld",        { XM, Vex, EXx }, 0 },
5870   },
5871
5872   /* PREFIX_VEX_0F3841 */
5873   {
5874     { Bad_Opcode },
5875     { Bad_Opcode },
5876     { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) },
5877   },
5878
5879   /* PREFIX_VEX_0F3845 */
5880   {
5881     { Bad_Opcode },
5882     { Bad_Opcode },
5883     { "vpsrlv%LW", { XM, Vex, EXx }, 0 },
5884   },
5885
5886   /* PREFIX_VEX_0F3846 */
5887   {
5888     { Bad_Opcode },
5889     { Bad_Opcode },
5890     { VEX_W_TABLE (VEX_W_0F3846_P_2) },
5891   },
5892
5893   /* PREFIX_VEX_0F3847 */
5894   {
5895     { Bad_Opcode },
5896     { Bad_Opcode },
5897     { "vpsllv%LW", { XM, Vex, EXx }, 0 },
5898   },
5899
5900   /* PREFIX_VEX_0F3858 */
5901   {
5902     { Bad_Opcode },
5903     { Bad_Opcode },
5904     { VEX_W_TABLE (VEX_W_0F3858_P_2) },
5905   },
5906
5907   /* PREFIX_VEX_0F3859 */
5908   {
5909     { Bad_Opcode },
5910     { Bad_Opcode },
5911     { VEX_W_TABLE (VEX_W_0F3859_P_2) },
5912   },
5913
5914   /* PREFIX_VEX_0F385A */
5915   {
5916     { Bad_Opcode },
5917     { Bad_Opcode },
5918     { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) },
5919   },
5920
5921   /* PREFIX_VEX_0F3878 */
5922   {
5923     { Bad_Opcode },
5924     { Bad_Opcode },
5925     { VEX_W_TABLE (VEX_W_0F3878_P_2) },
5926   },
5927
5928   /* PREFIX_VEX_0F3879 */
5929   {
5930     { Bad_Opcode },
5931     { Bad_Opcode },
5932     { VEX_W_TABLE (VEX_W_0F3879_P_2) },
5933   },
5934
5935   /* PREFIX_VEX_0F388C */
5936   {
5937     { Bad_Opcode },
5938     { Bad_Opcode },
5939     { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) },
5940   },
5941
5942   /* PREFIX_VEX_0F388E */
5943   {
5944     { Bad_Opcode },
5945     { Bad_Opcode },
5946     { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) },
5947   },
5948
5949   /* PREFIX_VEX_0F3890 */
5950   {
5951     { Bad_Opcode },
5952     { Bad_Opcode },
5953     { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex }, 0 },
5954   },
5955
5956   /* PREFIX_VEX_0F3891 */
5957   {
5958     { Bad_Opcode },
5959     { Bad_Opcode },
5960     { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
5961   },
5962
5963   /* PREFIX_VEX_0F3892 */
5964   {
5965     { Bad_Opcode },
5966     { Bad_Opcode },
5967     { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex }, 0 },
5968   },
5969
5970   /* PREFIX_VEX_0F3893 */
5971   {
5972     { Bad_Opcode },
5973     { Bad_Opcode },
5974     { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
5975   },
5976
5977   /* PREFIX_VEX_0F3896 */
5978   {
5979     { Bad_Opcode },
5980     { Bad_Opcode },
5981     { "vfmaddsub132p%XW", { XM, Vex, EXx }, 0 },
5982   },
5983
5984   /* PREFIX_VEX_0F3897 */
5985   {
5986     { Bad_Opcode },
5987     { Bad_Opcode },
5988     { "vfmsubadd132p%XW", { XM, Vex, EXx }, 0 },
5989   },
5990
5991   /* PREFIX_VEX_0F3898 */
5992   {
5993     { Bad_Opcode },
5994     { Bad_Opcode },
5995     { "vfmadd132p%XW", { XM, Vex, EXx }, 0 },
5996   },
5997
5998   /* PREFIX_VEX_0F3899 */
5999   {
6000     { Bad_Opcode },
6001     { Bad_Opcode },
6002     { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6003   },
6004
6005   /* PREFIX_VEX_0F389A */
6006   {
6007     { Bad_Opcode },
6008     { Bad_Opcode },
6009     { "vfmsub132p%XW", { XM, Vex, EXx }, 0 },
6010   },
6011
6012   /* PREFIX_VEX_0F389B */
6013   {
6014     { Bad_Opcode },
6015     { Bad_Opcode },
6016     { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6017   },
6018
6019   /* PREFIX_VEX_0F389C */
6020   {
6021     { Bad_Opcode },
6022     { Bad_Opcode },
6023     { "vfnmadd132p%XW", { XM, Vex, EXx }, 0 },
6024   },
6025
6026   /* PREFIX_VEX_0F389D */
6027   {
6028     { Bad_Opcode },
6029     { Bad_Opcode },
6030     { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6031   },
6032
6033   /* PREFIX_VEX_0F389E */
6034   {
6035     { Bad_Opcode },
6036     { Bad_Opcode },
6037     { "vfnmsub132p%XW", { XM, Vex, EXx }, 0 },
6038   },
6039
6040   /* PREFIX_VEX_0F389F */
6041   {
6042     { Bad_Opcode },
6043     { Bad_Opcode },
6044     { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6045   },
6046
6047   /* PREFIX_VEX_0F38A6 */
6048   {
6049     { Bad_Opcode },
6050     { Bad_Opcode },
6051     { "vfmaddsub213p%XW", { XM, Vex, EXx }, 0 },
6052     { Bad_Opcode },
6053   },
6054
6055   /* PREFIX_VEX_0F38A7 */
6056   {
6057     { Bad_Opcode },
6058     { Bad_Opcode },
6059     { "vfmsubadd213p%XW", { XM, Vex, EXx }, 0 },
6060   },
6061
6062   /* PREFIX_VEX_0F38A8 */
6063   {
6064     { Bad_Opcode },
6065     { Bad_Opcode },
6066     { "vfmadd213p%XW", { XM, Vex, EXx }, 0 },
6067   },
6068
6069   /* PREFIX_VEX_0F38A9 */
6070   {
6071     { Bad_Opcode },
6072     { Bad_Opcode },
6073     { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6074   },
6075
6076   /* PREFIX_VEX_0F38AA */
6077   {
6078     { Bad_Opcode },
6079     { Bad_Opcode },
6080     { "vfmsub213p%XW", { XM, Vex, EXx }, 0 },
6081   },
6082
6083   /* PREFIX_VEX_0F38AB */
6084   {
6085     { Bad_Opcode },
6086     { Bad_Opcode },
6087     { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6088   },
6089
6090   /* PREFIX_VEX_0F38AC */
6091   {
6092     { Bad_Opcode },
6093     { Bad_Opcode },
6094     { "vfnmadd213p%XW", { XM, Vex, EXx }, 0 },
6095   },
6096
6097   /* PREFIX_VEX_0F38AD */
6098   {
6099     { Bad_Opcode },
6100     { Bad_Opcode },
6101     { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6102   },
6103
6104   /* PREFIX_VEX_0F38AE */
6105   {
6106     { Bad_Opcode },
6107     { Bad_Opcode },
6108     { "vfnmsub213p%XW", { XM, Vex, EXx }, 0 },
6109   },
6110
6111   /* PREFIX_VEX_0F38AF */
6112   {
6113     { Bad_Opcode },
6114     { Bad_Opcode },
6115     { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6116   },
6117
6118   /* PREFIX_VEX_0F38B6 */
6119   {
6120     { Bad_Opcode },
6121     { Bad_Opcode },
6122     { "vfmaddsub231p%XW", { XM, Vex, EXx }, 0 },
6123   },
6124
6125   /* PREFIX_VEX_0F38B7 */
6126   {
6127     { Bad_Opcode },
6128     { Bad_Opcode },
6129     { "vfmsubadd231p%XW", { XM, Vex, EXx }, 0 },
6130   },
6131
6132   /* PREFIX_VEX_0F38B8 */
6133   {
6134     { Bad_Opcode },
6135     { Bad_Opcode },
6136     { "vfmadd231p%XW", { XM, Vex, EXx }, 0 },
6137   },
6138
6139   /* PREFIX_VEX_0F38B9 */
6140   {
6141     { Bad_Opcode },
6142     { Bad_Opcode },
6143     { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6144   },
6145
6146   /* PREFIX_VEX_0F38BA */
6147   {
6148     { Bad_Opcode },
6149     { Bad_Opcode },
6150     { "vfmsub231p%XW", { XM, Vex, EXx }, 0 },
6151   },
6152
6153   /* PREFIX_VEX_0F38BB */
6154   {
6155     { Bad_Opcode },
6156     { Bad_Opcode },
6157     { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6158   },
6159
6160   /* PREFIX_VEX_0F38BC */
6161   {
6162     { Bad_Opcode },
6163     { Bad_Opcode },
6164     { "vfnmadd231p%XW", { XM, Vex, EXx }, 0 },
6165   },
6166
6167   /* PREFIX_VEX_0F38BD */
6168   {
6169     { Bad_Opcode },
6170     { Bad_Opcode },
6171     { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6172   },
6173
6174   /* PREFIX_VEX_0F38BE */
6175   {
6176     { Bad_Opcode },
6177     { Bad_Opcode },
6178     { "vfnmsub231p%XW", { XM, Vex, EXx }, 0 },
6179   },
6180
6181   /* PREFIX_VEX_0F38BF */
6182   {
6183     { Bad_Opcode },
6184     { Bad_Opcode },
6185     { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6186   },
6187
6188   /* PREFIX_VEX_0F38CF */
6189   {
6190     { Bad_Opcode },
6191     { Bad_Opcode },
6192     { VEX_W_TABLE (VEX_W_0F38CF_P_2) },
6193   },
6194
6195   /* PREFIX_VEX_0F38DB */
6196   {
6197     { Bad_Opcode },
6198     { Bad_Opcode },
6199     { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) },
6200   },
6201
6202   /* PREFIX_VEX_0F38DC */
6203   {
6204     { Bad_Opcode },
6205     { Bad_Opcode },
6206     { "vaesenc",        { XM, Vex, EXx }, 0 },
6207   },
6208
6209   /* PREFIX_VEX_0F38DD */
6210   {
6211     { Bad_Opcode },
6212     { Bad_Opcode },
6213     { "vaesenclast",    { XM, Vex, EXx }, 0 },
6214   },
6215
6216   /* PREFIX_VEX_0F38DE */
6217   {
6218     { Bad_Opcode },
6219     { Bad_Opcode },
6220     { "vaesdec",        { XM, Vex, EXx }, 0 },
6221   },
6222
6223   /* PREFIX_VEX_0F38DF */
6224   {
6225     { Bad_Opcode },
6226     { Bad_Opcode },
6227     { "vaesdeclast",    { XM, Vex, EXx }, 0 },
6228   },
6229
6230   /* PREFIX_VEX_0F38F2 */
6231   {
6232     { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) },
6233   },
6234
6235   /* PREFIX_VEX_0F38F3_REG_1 */
6236   {
6237     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) },
6238   },
6239
6240   /* PREFIX_VEX_0F38F3_REG_2 */
6241   {
6242     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) },
6243   },
6244
6245   /* PREFIX_VEX_0F38F3_REG_3 */
6246   {
6247     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) },
6248   },
6249
6250   /* PREFIX_VEX_0F38F5 */
6251   {
6252     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) },
6253     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) },
6254     { Bad_Opcode },
6255     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) },
6256   },
6257
6258   /* PREFIX_VEX_0F38F6 */
6259   {
6260     { Bad_Opcode },
6261     { Bad_Opcode },
6262     { Bad_Opcode },
6263     { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) },
6264   },
6265
6266   /* PREFIX_VEX_0F38F7 */
6267   {
6268     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) },
6269     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) },
6270     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) },
6271     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) },
6272   },
6273
6274   /* PREFIX_VEX_0F3A00 */
6275   {
6276     { Bad_Opcode },
6277     { Bad_Opcode },
6278     { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) },
6279   },
6280
6281   /* PREFIX_VEX_0F3A01 */
6282   {
6283     { Bad_Opcode },
6284     { Bad_Opcode },
6285     { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) },
6286   },
6287
6288   /* PREFIX_VEX_0F3A02 */
6289   {
6290     { Bad_Opcode },
6291     { Bad_Opcode },
6292     { VEX_W_TABLE (VEX_W_0F3A02_P_2) },
6293   },
6294
6295   /* PREFIX_VEX_0F3A04 */
6296   {
6297     { Bad_Opcode },
6298     { Bad_Opcode },
6299     { VEX_W_TABLE (VEX_W_0F3A04_P_2) },
6300   },
6301
6302   /* PREFIX_VEX_0F3A05 */
6303   {
6304     { Bad_Opcode },
6305     { Bad_Opcode },
6306     { VEX_W_TABLE (VEX_W_0F3A05_P_2) },
6307   },
6308
6309   /* PREFIX_VEX_0F3A06 */
6310   {
6311     { Bad_Opcode },
6312     { Bad_Opcode },
6313     { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) },
6314   },
6315
6316   /* PREFIX_VEX_0F3A08 */
6317   {
6318     { Bad_Opcode },
6319     { Bad_Opcode },
6320     { "vroundps",       { XM, EXx, Ib }, 0 },
6321   },
6322
6323   /* PREFIX_VEX_0F3A09 */
6324   {
6325     { Bad_Opcode },
6326     { Bad_Opcode },
6327     { "vroundpd",       { XM, EXx, Ib }, 0 },
6328   },
6329
6330   /* PREFIX_VEX_0F3A0A */
6331   {
6332     { Bad_Opcode },
6333     { Bad_Opcode },
6334     { "vroundss",       { XMScalar, VexScalar, EXxmm_md, Ib }, 0 },
6335   },
6336
6337   /* PREFIX_VEX_0F3A0B */
6338   {
6339     { Bad_Opcode },
6340     { Bad_Opcode },
6341     { "vroundsd",       { XMScalar, VexScalar, EXxmm_mq, Ib }, 0 },
6342   },
6343
6344   /* PREFIX_VEX_0F3A0C */
6345   {
6346     { Bad_Opcode },
6347     { Bad_Opcode },
6348     { "vblendps",       { XM, Vex, EXx, Ib }, 0 },
6349   },
6350
6351   /* PREFIX_VEX_0F3A0D */
6352   {
6353     { Bad_Opcode },
6354     { Bad_Opcode },
6355     { "vblendpd",       { XM, Vex, EXx, Ib }, 0 },
6356   },
6357
6358   /* PREFIX_VEX_0F3A0E */
6359   {
6360     { Bad_Opcode },
6361     { Bad_Opcode },
6362     { "vpblendw",       { XM, Vex, EXx, Ib }, 0 },
6363   },
6364
6365   /* PREFIX_VEX_0F3A0F */
6366   {
6367     { Bad_Opcode },
6368     { Bad_Opcode },
6369     { "vpalignr",       { XM, Vex, EXx, Ib }, 0 },
6370   },
6371
6372   /* PREFIX_VEX_0F3A14 */
6373   {
6374     { Bad_Opcode },
6375     { Bad_Opcode },
6376     { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) },
6377   },
6378
6379   /* PREFIX_VEX_0F3A15 */
6380   {
6381     { Bad_Opcode },
6382     { Bad_Opcode },
6383     { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) },
6384   },
6385
6386   /* PREFIX_VEX_0F3A16 */
6387   {
6388     { Bad_Opcode },
6389     { Bad_Opcode },
6390     { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) },
6391   },
6392
6393   /* PREFIX_VEX_0F3A17 */
6394   {
6395     { Bad_Opcode },
6396     { Bad_Opcode },
6397     { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) },
6398   },
6399
6400   /* PREFIX_VEX_0F3A18 */
6401   {
6402     { Bad_Opcode },
6403     { Bad_Opcode },
6404     { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) },
6405   },
6406
6407   /* PREFIX_VEX_0F3A19 */
6408   {
6409     { Bad_Opcode },
6410     { Bad_Opcode },
6411     { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) },
6412   },
6413
6414   /* PREFIX_VEX_0F3A1D */
6415   {
6416     { Bad_Opcode },
6417     { Bad_Opcode },
6418     { "vcvtps2ph", { EXxmmq, XM, Ib }, 0 },
6419   },
6420
6421   /* PREFIX_VEX_0F3A20 */
6422   {
6423     { Bad_Opcode },
6424     { Bad_Opcode },
6425     { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) },
6426   },
6427
6428   /* PREFIX_VEX_0F3A21 */
6429   {
6430     { Bad_Opcode },
6431     { Bad_Opcode },
6432     { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) },
6433   },
6434
6435   /* PREFIX_VEX_0F3A22 */
6436   {
6437     { Bad_Opcode },
6438     { Bad_Opcode },
6439     { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) },
6440   },
6441
6442   /* PREFIX_VEX_0F3A30 */
6443   {
6444     { Bad_Opcode },
6445     { Bad_Opcode },
6446     { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2) },
6447   },
6448
6449   /* PREFIX_VEX_0F3A31 */
6450   {
6451     { Bad_Opcode },
6452     { Bad_Opcode },
6453     { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2) },
6454   },
6455
6456   /* PREFIX_VEX_0F3A32 */
6457   {
6458     { Bad_Opcode },
6459     { Bad_Opcode },
6460     { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2) },
6461   },
6462
6463   /* PREFIX_VEX_0F3A33 */
6464   {
6465     { Bad_Opcode },
6466     { Bad_Opcode },
6467     { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2) },
6468   },
6469
6470   /* PREFIX_VEX_0F3A38 */
6471   {
6472     { Bad_Opcode },
6473     { Bad_Opcode },
6474     { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) },
6475   },
6476
6477   /* PREFIX_VEX_0F3A39 */
6478   {
6479     { Bad_Opcode },
6480     { Bad_Opcode },
6481     { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) },
6482   },
6483
6484   /* PREFIX_VEX_0F3A40 */
6485   {
6486     { Bad_Opcode },
6487     { Bad_Opcode },
6488     { "vdpps",          { XM, Vex, EXx, Ib }, 0 },
6489   },
6490
6491   /* PREFIX_VEX_0F3A41 */
6492   {
6493     { Bad_Opcode },
6494     { Bad_Opcode },
6495     { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) },
6496   },
6497
6498   /* PREFIX_VEX_0F3A42 */
6499   {
6500     { Bad_Opcode },
6501     { Bad_Opcode },
6502     { "vmpsadbw",       { XM, Vex, EXx, Ib }, 0 },
6503   },
6504
6505   /* PREFIX_VEX_0F3A44 */
6506   {
6507     { Bad_Opcode },
6508     { Bad_Opcode },
6509     { "vpclmulqdq",     { XM, Vex, EXx, PCLMUL }, 0 },
6510   },
6511
6512   /* PREFIX_VEX_0F3A46 */
6513   {
6514     { Bad_Opcode },
6515     { Bad_Opcode },
6516     { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) },
6517   },
6518
6519   /* PREFIX_VEX_0F3A48 */
6520   {
6521     { Bad_Opcode },
6522     { Bad_Opcode },
6523     { VEX_W_TABLE (VEX_W_0F3A48_P_2) },
6524   },
6525
6526   /* PREFIX_VEX_0F3A49 */
6527   {
6528     { Bad_Opcode },
6529     { Bad_Opcode },
6530     { VEX_W_TABLE (VEX_W_0F3A49_P_2) },
6531   },
6532
6533   /* PREFIX_VEX_0F3A4A */
6534   {
6535     { Bad_Opcode },
6536     { Bad_Opcode },
6537     { VEX_W_TABLE (VEX_W_0F3A4A_P_2) },
6538   },
6539
6540   /* PREFIX_VEX_0F3A4B */
6541   {
6542     { Bad_Opcode },
6543     { Bad_Opcode },
6544     { VEX_W_TABLE (VEX_W_0F3A4B_P_2) },
6545   },
6546
6547   /* PREFIX_VEX_0F3A4C */
6548   {
6549     { Bad_Opcode },
6550     { Bad_Opcode },
6551     { VEX_W_TABLE (VEX_W_0F3A4C_P_2) },
6552   },
6553
6554   /* PREFIX_VEX_0F3A5C */
6555   {
6556     { Bad_Opcode },
6557     { Bad_Opcode },
6558     { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6559   },
6560
6561   /* PREFIX_VEX_0F3A5D */
6562   {
6563     { Bad_Opcode },
6564     { Bad_Opcode },
6565     { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6566   },
6567
6568   /* PREFIX_VEX_0F3A5E */
6569   {
6570     { Bad_Opcode },
6571     { Bad_Opcode },
6572     { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6573   },
6574
6575   /* PREFIX_VEX_0F3A5F */
6576   {
6577     { Bad_Opcode },
6578     { Bad_Opcode },
6579     { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6580   },
6581
6582   /* PREFIX_VEX_0F3A60 */
6583   {
6584     { Bad_Opcode },
6585     { Bad_Opcode },
6586     { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) },
6587     { Bad_Opcode },
6588   },
6589
6590   /* PREFIX_VEX_0F3A61 */
6591   {
6592     { Bad_Opcode },
6593     { Bad_Opcode },
6594     { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) },
6595   },
6596
6597   /* PREFIX_VEX_0F3A62 */
6598   {
6599     { Bad_Opcode },
6600     { Bad_Opcode },
6601     { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) },
6602   },
6603
6604   /* PREFIX_VEX_0F3A63 */
6605   {
6606     { Bad_Opcode },
6607     { Bad_Opcode },
6608     { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) },
6609   },
6610
6611   /* PREFIX_VEX_0F3A68 */
6612   {
6613     { Bad_Opcode },
6614     { Bad_Opcode },
6615     { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6616   },
6617
6618   /* PREFIX_VEX_0F3A69 */
6619   {
6620     { Bad_Opcode },
6621     { Bad_Opcode },
6622     { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6623   },
6624
6625   /* PREFIX_VEX_0F3A6A */
6626   {
6627     { Bad_Opcode },
6628     { Bad_Opcode },
6629     { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) },
6630   },
6631
6632   /* PREFIX_VEX_0F3A6B */
6633   {
6634     { Bad_Opcode },
6635     { Bad_Opcode },
6636     { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) },
6637   },
6638
6639   /* PREFIX_VEX_0F3A6C */
6640   {
6641     { Bad_Opcode },
6642     { Bad_Opcode },
6643     { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6644   },
6645
6646   /* PREFIX_VEX_0F3A6D */
6647   {
6648     { Bad_Opcode },
6649     { Bad_Opcode },
6650     { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6651   },
6652
6653   /* PREFIX_VEX_0F3A6E */
6654   {
6655     { Bad_Opcode },
6656     { Bad_Opcode },
6657     { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) },
6658   },
6659
6660   /* PREFIX_VEX_0F3A6F */
6661   {
6662     { Bad_Opcode },
6663     { Bad_Opcode },
6664     { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) },
6665   },
6666
6667   /* PREFIX_VEX_0F3A78 */
6668   {
6669     { Bad_Opcode },
6670     { Bad_Opcode },
6671     { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6672   },
6673
6674   /* PREFIX_VEX_0F3A79 */
6675   {
6676     { Bad_Opcode },
6677     { Bad_Opcode },
6678     { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6679   },
6680
6681   /* PREFIX_VEX_0F3A7A */
6682   {
6683     { Bad_Opcode },
6684     { Bad_Opcode },
6685     { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) },
6686   },
6687
6688   /* PREFIX_VEX_0F3A7B */
6689   {
6690     { Bad_Opcode },
6691     { Bad_Opcode },
6692     { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) },
6693   },
6694
6695   /* PREFIX_VEX_0F3A7C */
6696   {
6697     { Bad_Opcode },
6698     { Bad_Opcode },
6699     { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6700     { Bad_Opcode },
6701   },
6702
6703   /* PREFIX_VEX_0F3A7D */
6704   {
6705     { Bad_Opcode },
6706     { Bad_Opcode },
6707     { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6708   },
6709
6710   /* PREFIX_VEX_0F3A7E */
6711   {
6712     { Bad_Opcode },
6713     { Bad_Opcode },
6714     { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) },
6715   },
6716
6717   /* PREFIX_VEX_0F3A7F */
6718   {
6719     { Bad_Opcode },
6720     { Bad_Opcode },
6721     { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) },
6722   },
6723
6724   /* PREFIX_VEX_0F3ACE */
6725   {
6726     { Bad_Opcode },
6727     { Bad_Opcode },
6728     { VEX_W_TABLE (VEX_W_0F3ACE_P_2) },
6729   },
6730
6731   /* PREFIX_VEX_0F3ACF */
6732   {
6733     { Bad_Opcode },
6734     { Bad_Opcode },
6735     { VEX_W_TABLE (VEX_W_0F3ACF_P_2) },
6736   },
6737
6738   /* PREFIX_VEX_0F3ADF */
6739   {
6740     { Bad_Opcode },
6741     { Bad_Opcode },
6742     { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) },
6743   },
6744
6745   /* PREFIX_VEX_0F3AF0 */
6746   {
6747     { Bad_Opcode },
6748     { Bad_Opcode },
6749     { Bad_Opcode },
6750     { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) },
6751   },
6752
6753 #include "i386-dis-evex-prefix.h"
6754 };
6755
6756 static const struct dis386 x86_64_table[][2] = {
6757   /* X86_64_06 */
6758   {
6759     { "pushP", { es }, 0 },
6760   },
6761
6762   /* X86_64_07 */
6763   {
6764     { "popP", { es }, 0 },
6765   },
6766
6767   /* X86_64_0E */
6768   {
6769     { "pushP", { cs }, 0 },
6770   },
6771
6772   /* X86_64_16 */
6773   {
6774     { "pushP", { ss }, 0 },
6775   },
6776
6777   /* X86_64_17 */
6778   {
6779     { "popP", { ss }, 0 },
6780   },
6781
6782   /* X86_64_1E */
6783   {
6784     { "pushP", { ds }, 0 },
6785   },
6786
6787   /* X86_64_1F */
6788   {
6789     { "popP", { ds }, 0 },
6790   },
6791
6792   /* X86_64_27 */
6793   {
6794     { "daa", { XX }, 0 },
6795   },
6796
6797   /* X86_64_2F */
6798   {
6799     { "das", { XX }, 0 },
6800   },
6801
6802   /* X86_64_37 */
6803   {
6804     { "aaa", { XX }, 0 },
6805   },
6806
6807   /* X86_64_3F */
6808   {
6809     { "aas", { XX }, 0 },
6810   },
6811
6812   /* X86_64_60 */
6813   {
6814     { "pushaP", { XX }, 0 },
6815   },
6816
6817   /* X86_64_61 */
6818   {
6819     { "popaP", { XX }, 0 },
6820   },
6821
6822   /* X86_64_62 */
6823   {
6824     { MOD_TABLE (MOD_62_32BIT) },
6825     { EVEX_TABLE (EVEX_0F) },
6826   },
6827
6828   /* X86_64_63 */
6829   {
6830     { "arpl", { Ew, Gw }, 0 },
6831     { "movs", { { OP_G, movsxd_mode }, { MOVSXD_Fixup, movsxd_mode } }, 0 },
6832   },
6833
6834   /* X86_64_6D */
6835   {
6836     { "ins{R|}", { Yzr, indirDX }, 0 },
6837     { "ins{G|}", { Yzr, indirDX }, 0 },
6838   },
6839
6840   /* X86_64_6F */
6841   {
6842     { "outs{R|}", { indirDXr, Xz }, 0 },
6843     { "outs{G|}", { indirDXr, Xz }, 0 },
6844   },
6845
6846   /* X86_64_82 */
6847   {
6848     /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode.  */
6849     { REG_TABLE (REG_80) },
6850   },
6851
6852   /* X86_64_9A */
6853   {
6854     { "{l|}call{T|}", { Ap }, 0 },
6855   },
6856
6857   /* X86_64_C2 */
6858   {
6859     { "retP",           { Iw, BND }, 0 },
6860     { "ret@",           { Iw, BND }, 0 },
6861   },
6862
6863   /* X86_64_C3 */
6864   {
6865     { "retP",           { BND }, 0 },
6866     { "ret@",           { BND }, 0 },
6867   },
6868
6869   /* X86_64_C4 */
6870   {
6871     { MOD_TABLE (MOD_C4_32BIT) },
6872     { VEX_C4_TABLE (VEX_0F) },
6873   },
6874
6875   /* X86_64_C5 */
6876   {
6877     { MOD_TABLE (MOD_C5_32BIT) },
6878     { VEX_C5_TABLE (VEX_0F) },
6879   },
6880
6881   /* X86_64_CE */
6882   {
6883     { "into", { XX }, 0 },
6884   },
6885
6886   /* X86_64_D4 */
6887   {
6888     { "aam", { Ib }, 0 },
6889   },
6890
6891   /* X86_64_D5 */
6892   {
6893     { "aad", { Ib }, 0 },
6894   },
6895
6896   /* X86_64_E8 */
6897   {
6898     { "callP",          { Jv, BND }, 0 },
6899     { "call@",          { Jv, BND }, 0 }
6900   },
6901
6902   /* X86_64_E9 */
6903   {
6904     { "jmpP",           { Jv, BND }, 0 },
6905     { "jmp@",           { Jv, BND }, 0 }
6906   },
6907
6908   /* X86_64_EA */
6909   {
6910     { "{l|}jmp{T|}", { Ap }, 0 },
6911   },
6912
6913   /* X86_64_0F01_REG_0 */
6914   {
6915     { "sgdt{Q|Q}", { M }, 0 },
6916     { "sgdt", { M }, 0 },
6917   },
6918
6919   /* X86_64_0F01_REG_1 */
6920   {
6921     { "sidt{Q|Q}", { M }, 0 },
6922     { "sidt", { M }, 0 },
6923   },
6924
6925   /* X86_64_0F01_REG_2 */
6926   {
6927     { "lgdt{Q|Q}", { M }, 0 },
6928     { "lgdt", { M }, 0 },
6929   },
6930
6931   /* X86_64_0F01_REG_3 */
6932   {
6933     { "lidt{Q|Q}", { M }, 0 },
6934     { "lidt", { M }, 0 },
6935   },
6936 };
6937
6938 static const struct dis386 three_byte_table[][256] = {
6939
6940   /* THREE_BYTE_0F38 */
6941   {
6942     /* 00 */
6943     { "pshufb",         { MX, EM }, PREFIX_OPCODE },
6944     { "phaddw",         { MX, EM }, PREFIX_OPCODE },
6945     { "phaddd",         { MX, EM }, PREFIX_OPCODE },
6946     { "phaddsw",        { MX, EM }, PREFIX_OPCODE },
6947     { "pmaddubsw",      { MX, EM }, PREFIX_OPCODE },
6948     { "phsubw",         { MX, EM }, PREFIX_OPCODE },
6949     { "phsubd",         { MX, EM }, PREFIX_OPCODE },
6950     { "phsubsw",        { MX, EM }, PREFIX_OPCODE },
6951     /* 08 */
6952     { "psignb",         { MX, EM }, PREFIX_OPCODE },
6953     { "psignw",         { MX, EM }, PREFIX_OPCODE },
6954     { "psignd",         { MX, EM }, PREFIX_OPCODE },
6955     { "pmulhrsw",       { MX, EM }, PREFIX_OPCODE },
6956     { Bad_Opcode },
6957     { Bad_Opcode },
6958     { Bad_Opcode },
6959     { Bad_Opcode },
6960     /* 10 */
6961     { PREFIX_TABLE (PREFIX_0F3810) },
6962     { Bad_Opcode },
6963     { Bad_Opcode },
6964     { Bad_Opcode },
6965     { PREFIX_TABLE (PREFIX_0F3814) },
6966     { PREFIX_TABLE (PREFIX_0F3815) },
6967     { Bad_Opcode },
6968     { PREFIX_TABLE (PREFIX_0F3817) },
6969     /* 18 */
6970     { Bad_Opcode },
6971     { Bad_Opcode },
6972     { Bad_Opcode },
6973     { Bad_Opcode },
6974     { "pabsb",          { MX, EM }, PREFIX_OPCODE },
6975     { "pabsw",          { MX, EM }, PREFIX_OPCODE },
6976     { "pabsd",          { MX, EM }, PREFIX_OPCODE },
6977     { Bad_Opcode },
6978     /* 20 */
6979     { PREFIX_TABLE (PREFIX_0F3820) },
6980     { PREFIX_TABLE (PREFIX_0F3821) },
6981     { PREFIX_TABLE (PREFIX_0F3822) },
6982     { PREFIX_TABLE (PREFIX_0F3823) },
6983     { PREFIX_TABLE (PREFIX_0F3824) },
6984     { PREFIX_TABLE (PREFIX_0F3825) },
6985     { Bad_Opcode },
6986     { Bad_Opcode },
6987     /* 28 */
6988     { PREFIX_TABLE (PREFIX_0F3828) },
6989     { PREFIX_TABLE (PREFIX_0F3829) },
6990     { PREFIX_TABLE (PREFIX_0F382A) },
6991     { PREFIX_TABLE (PREFIX_0F382B) },
6992     { Bad_Opcode },
6993     { Bad_Opcode },
6994     { Bad_Opcode },
6995     { Bad_Opcode },
6996     /* 30 */
6997     { PREFIX_TABLE (PREFIX_0F3830) },
6998     { PREFIX_TABLE (PREFIX_0F3831) },
6999     { PREFIX_TABLE (PREFIX_0F3832) },
7000     { PREFIX_TABLE (PREFIX_0F3833) },
7001     { PREFIX_TABLE (PREFIX_0F3834) },
7002     { PREFIX_TABLE (PREFIX_0F3835) },
7003     { Bad_Opcode },
7004     { PREFIX_TABLE (PREFIX_0F3837) },
7005     /* 38 */
7006     { PREFIX_TABLE (PREFIX_0F3838) },
7007     { PREFIX_TABLE (PREFIX_0F3839) },
7008     { PREFIX_TABLE (PREFIX_0F383A) },
7009     { PREFIX_TABLE (PREFIX_0F383B) },
7010     { PREFIX_TABLE (PREFIX_0F383C) },
7011     { PREFIX_TABLE (PREFIX_0F383D) },
7012     { PREFIX_TABLE (PREFIX_0F383E) },
7013     { PREFIX_TABLE (PREFIX_0F383F) },
7014     /* 40 */
7015     { PREFIX_TABLE (PREFIX_0F3840) },
7016     { PREFIX_TABLE (PREFIX_0F3841) },
7017     { Bad_Opcode },
7018     { Bad_Opcode },
7019     { Bad_Opcode },
7020     { Bad_Opcode },
7021     { Bad_Opcode },
7022     { Bad_Opcode },
7023     /* 48 */
7024     { Bad_Opcode },
7025     { Bad_Opcode },
7026     { Bad_Opcode },
7027     { Bad_Opcode },
7028     { Bad_Opcode },
7029     { Bad_Opcode },
7030     { Bad_Opcode },
7031     { Bad_Opcode },
7032     /* 50 */
7033     { Bad_Opcode },
7034     { Bad_Opcode },
7035     { Bad_Opcode },
7036     { Bad_Opcode },
7037     { Bad_Opcode },
7038     { Bad_Opcode },
7039     { Bad_Opcode },
7040     { Bad_Opcode },
7041     /* 58 */
7042     { Bad_Opcode },
7043     { Bad_Opcode },
7044     { Bad_Opcode },
7045     { Bad_Opcode },
7046     { Bad_Opcode },
7047     { Bad_Opcode },
7048     { Bad_Opcode },
7049     { Bad_Opcode },
7050     /* 60 */
7051     { Bad_Opcode },
7052     { Bad_Opcode },
7053     { Bad_Opcode },
7054     { Bad_Opcode },
7055     { Bad_Opcode },
7056     { Bad_Opcode },
7057     { Bad_Opcode },
7058     { Bad_Opcode },
7059     /* 68 */
7060     { Bad_Opcode },
7061     { Bad_Opcode },
7062     { Bad_Opcode },
7063     { Bad_Opcode },
7064     { Bad_Opcode },
7065     { Bad_Opcode },
7066     { Bad_Opcode },
7067     { Bad_Opcode },
7068     /* 70 */
7069     { Bad_Opcode },
7070     { Bad_Opcode },
7071     { Bad_Opcode },
7072     { Bad_Opcode },
7073     { Bad_Opcode },
7074     { Bad_Opcode },
7075     { Bad_Opcode },
7076     { Bad_Opcode },
7077     /* 78 */
7078     { Bad_Opcode },
7079     { Bad_Opcode },
7080     { Bad_Opcode },
7081     { Bad_Opcode },
7082     { Bad_Opcode },
7083     { Bad_Opcode },
7084     { Bad_Opcode },
7085     { Bad_Opcode },
7086     /* 80 */
7087     { PREFIX_TABLE (PREFIX_0F3880) },
7088     { PREFIX_TABLE (PREFIX_0F3881) },
7089     { PREFIX_TABLE (PREFIX_0F3882) },
7090     { Bad_Opcode },
7091     { Bad_Opcode },
7092     { Bad_Opcode },
7093     { Bad_Opcode },
7094     { Bad_Opcode },
7095     /* 88 */
7096     { Bad_Opcode },
7097     { Bad_Opcode },
7098     { Bad_Opcode },
7099     { Bad_Opcode },
7100     { Bad_Opcode },
7101     { Bad_Opcode },
7102     { Bad_Opcode },
7103     { Bad_Opcode },
7104     /* 90 */
7105     { Bad_Opcode },
7106     { Bad_Opcode },
7107     { Bad_Opcode },
7108     { Bad_Opcode },
7109     { Bad_Opcode },
7110     { Bad_Opcode },
7111     { Bad_Opcode },
7112     { Bad_Opcode },
7113     /* 98 */
7114     { Bad_Opcode },
7115     { Bad_Opcode },
7116     { Bad_Opcode },
7117     { Bad_Opcode },
7118     { Bad_Opcode },
7119     { Bad_Opcode },
7120     { Bad_Opcode },
7121     { Bad_Opcode },
7122     /* a0 */
7123     { Bad_Opcode },
7124     { Bad_Opcode },
7125     { Bad_Opcode },
7126     { Bad_Opcode },
7127     { Bad_Opcode },
7128     { Bad_Opcode },
7129     { Bad_Opcode },
7130     { Bad_Opcode },
7131     /* a8 */
7132     { Bad_Opcode },
7133     { Bad_Opcode },
7134     { Bad_Opcode },
7135     { Bad_Opcode },
7136     { Bad_Opcode },
7137     { Bad_Opcode },
7138     { Bad_Opcode },
7139     { Bad_Opcode },
7140     /* b0 */
7141     { Bad_Opcode },
7142     { Bad_Opcode },
7143     { Bad_Opcode },
7144     { Bad_Opcode },
7145     { Bad_Opcode },
7146     { Bad_Opcode },
7147     { Bad_Opcode },
7148     { Bad_Opcode },
7149     /* b8 */
7150     { Bad_Opcode },
7151     { Bad_Opcode },
7152     { Bad_Opcode },
7153     { Bad_Opcode },
7154     { Bad_Opcode },
7155     { Bad_Opcode },
7156     { Bad_Opcode },
7157     { Bad_Opcode },
7158     /* c0 */
7159     { Bad_Opcode },
7160     { Bad_Opcode },
7161     { Bad_Opcode },
7162     { Bad_Opcode },
7163     { Bad_Opcode },
7164     { Bad_Opcode },
7165     { Bad_Opcode },
7166     { Bad_Opcode },
7167     /* c8 */
7168     { PREFIX_TABLE (PREFIX_0F38C8) },
7169     { PREFIX_TABLE (PREFIX_0F38C9) },
7170     { PREFIX_TABLE (PREFIX_0F38CA) },
7171     { PREFIX_TABLE (PREFIX_0F38CB) },
7172     { PREFIX_TABLE (PREFIX_0F38CC) },
7173     { PREFIX_TABLE (PREFIX_0F38CD) },
7174     { Bad_Opcode },
7175     { PREFIX_TABLE (PREFIX_0F38CF) },
7176     /* d0 */
7177     { Bad_Opcode },
7178     { Bad_Opcode },
7179     { Bad_Opcode },
7180     { Bad_Opcode },
7181     { Bad_Opcode },
7182     { Bad_Opcode },
7183     { Bad_Opcode },
7184     { Bad_Opcode },
7185     /* d8 */
7186     { Bad_Opcode },
7187     { Bad_Opcode },
7188     { Bad_Opcode },
7189     { PREFIX_TABLE (PREFIX_0F38DB) },
7190     { PREFIX_TABLE (PREFIX_0F38DC) },
7191     { PREFIX_TABLE (PREFIX_0F38DD) },
7192     { PREFIX_TABLE (PREFIX_0F38DE) },
7193     { PREFIX_TABLE (PREFIX_0F38DF) },
7194     /* e0 */
7195     { Bad_Opcode },
7196     { Bad_Opcode },
7197     { Bad_Opcode },
7198     { Bad_Opcode },
7199     { Bad_Opcode },
7200     { Bad_Opcode },
7201     { Bad_Opcode },
7202     { Bad_Opcode },
7203     /* e8 */
7204     { Bad_Opcode },
7205     { Bad_Opcode },
7206     { Bad_Opcode },
7207     { Bad_Opcode },
7208     { Bad_Opcode },
7209     { Bad_Opcode },
7210     { Bad_Opcode },
7211     { Bad_Opcode },
7212     /* f0 */
7213     { PREFIX_TABLE (PREFIX_0F38F0) },
7214     { PREFIX_TABLE (PREFIX_0F38F1) },
7215     { Bad_Opcode },
7216     { Bad_Opcode },
7217     { Bad_Opcode },
7218     { PREFIX_TABLE (PREFIX_0F38F5) },
7219     { PREFIX_TABLE (PREFIX_0F38F6) },
7220     { Bad_Opcode },
7221     /* f8 */
7222     { PREFIX_TABLE (PREFIX_0F38F8) },
7223     { PREFIX_TABLE (PREFIX_0F38F9) },
7224     { Bad_Opcode },
7225     { Bad_Opcode },
7226     { Bad_Opcode },
7227     { Bad_Opcode },
7228     { Bad_Opcode },
7229     { Bad_Opcode },
7230   },
7231   /* THREE_BYTE_0F3A */
7232   {
7233     /* 00 */
7234     { Bad_Opcode },
7235     { Bad_Opcode },
7236     { Bad_Opcode },
7237     { Bad_Opcode },
7238     { Bad_Opcode },
7239     { Bad_Opcode },
7240     { Bad_Opcode },
7241     { Bad_Opcode },
7242     /* 08 */
7243     { PREFIX_TABLE (PREFIX_0F3A08) },
7244     { PREFIX_TABLE (PREFIX_0F3A09) },
7245     { PREFIX_TABLE (PREFIX_0F3A0A) },
7246     { PREFIX_TABLE (PREFIX_0F3A0B) },
7247     { PREFIX_TABLE (PREFIX_0F3A0C) },
7248     { PREFIX_TABLE (PREFIX_0F3A0D) },
7249     { PREFIX_TABLE (PREFIX_0F3A0E) },
7250     { "palignr",        { MX, EM, Ib }, PREFIX_OPCODE },
7251     /* 10 */
7252     { Bad_Opcode },
7253     { Bad_Opcode },
7254     { Bad_Opcode },
7255     { Bad_Opcode },
7256     { PREFIX_TABLE (PREFIX_0F3A14) },
7257     { PREFIX_TABLE (PREFIX_0F3A15) },
7258     { PREFIX_TABLE (PREFIX_0F3A16) },
7259     { PREFIX_TABLE (PREFIX_0F3A17) },
7260     /* 18 */
7261     { Bad_Opcode },
7262     { Bad_Opcode },
7263     { Bad_Opcode },
7264     { Bad_Opcode },
7265     { Bad_Opcode },
7266     { Bad_Opcode },
7267     { Bad_Opcode },
7268     { Bad_Opcode },
7269     /* 20 */
7270     { PREFIX_TABLE (PREFIX_0F3A20) },
7271     { PREFIX_TABLE (PREFIX_0F3A21) },
7272     { PREFIX_TABLE (PREFIX_0F3A22) },
7273     { Bad_Opcode },
7274     { Bad_Opcode },
7275     { Bad_Opcode },
7276     { Bad_Opcode },
7277     { Bad_Opcode },
7278     /* 28 */
7279     { Bad_Opcode },
7280     { Bad_Opcode },
7281     { Bad_Opcode },
7282     { Bad_Opcode },
7283     { Bad_Opcode },
7284     { Bad_Opcode },
7285     { Bad_Opcode },
7286     { Bad_Opcode },
7287     /* 30 */
7288     { Bad_Opcode },
7289     { Bad_Opcode },
7290     { Bad_Opcode },
7291     { Bad_Opcode },
7292     { Bad_Opcode },
7293     { Bad_Opcode },
7294     { Bad_Opcode },
7295     { Bad_Opcode },
7296     /* 38 */
7297     { Bad_Opcode },
7298     { Bad_Opcode },
7299     { Bad_Opcode },
7300     { Bad_Opcode },
7301     { Bad_Opcode },
7302     { Bad_Opcode },
7303     { Bad_Opcode },
7304     { Bad_Opcode },
7305     /* 40 */
7306     { PREFIX_TABLE (PREFIX_0F3A40) },
7307     { PREFIX_TABLE (PREFIX_0F3A41) },
7308     { PREFIX_TABLE (PREFIX_0F3A42) },
7309     { Bad_Opcode },
7310     { PREFIX_TABLE (PREFIX_0F3A44) },
7311     { Bad_Opcode },
7312     { Bad_Opcode },
7313     { Bad_Opcode },
7314     /* 48 */
7315     { Bad_Opcode },
7316     { Bad_Opcode },
7317     { Bad_Opcode },
7318     { Bad_Opcode },
7319     { Bad_Opcode },
7320     { Bad_Opcode },
7321     { Bad_Opcode },
7322     { Bad_Opcode },
7323     /* 50 */
7324     { Bad_Opcode },
7325     { Bad_Opcode },
7326     { Bad_Opcode },
7327     { Bad_Opcode },
7328     { Bad_Opcode },
7329     { Bad_Opcode },
7330     { Bad_Opcode },
7331     { Bad_Opcode },
7332     /* 58 */
7333     { Bad_Opcode },
7334     { Bad_Opcode },
7335     { Bad_Opcode },
7336     { Bad_Opcode },
7337     { Bad_Opcode },
7338     { Bad_Opcode },
7339     { Bad_Opcode },
7340     { Bad_Opcode },
7341     /* 60 */
7342     { PREFIX_TABLE (PREFIX_0F3A60) },
7343     { PREFIX_TABLE (PREFIX_0F3A61) },
7344     { PREFIX_TABLE (PREFIX_0F3A62) },
7345     { PREFIX_TABLE (PREFIX_0F3A63) },
7346     { Bad_Opcode },
7347     { Bad_Opcode },
7348     { Bad_Opcode },
7349     { Bad_Opcode },
7350     /* 68 */
7351     { Bad_Opcode },
7352     { Bad_Opcode },
7353     { Bad_Opcode },
7354     { Bad_Opcode },
7355     { Bad_Opcode },
7356     { Bad_Opcode },
7357     { Bad_Opcode },
7358     { Bad_Opcode },
7359     /* 70 */
7360     { Bad_Opcode },
7361     { Bad_Opcode },
7362     { Bad_Opcode },
7363     { Bad_Opcode },
7364     { Bad_Opcode },
7365     { Bad_Opcode },
7366     { Bad_Opcode },
7367     { Bad_Opcode },
7368     /* 78 */
7369     { Bad_Opcode },
7370     { Bad_Opcode },
7371     { Bad_Opcode },
7372     { Bad_Opcode },
7373     { Bad_Opcode },
7374     { Bad_Opcode },
7375     { Bad_Opcode },
7376     { Bad_Opcode },
7377     /* 80 */
7378     { Bad_Opcode },
7379     { Bad_Opcode },
7380     { Bad_Opcode },
7381     { Bad_Opcode },
7382     { Bad_Opcode },
7383     { Bad_Opcode },
7384     { Bad_Opcode },
7385     { Bad_Opcode },
7386     /* 88 */
7387     { Bad_Opcode },
7388     { Bad_Opcode },
7389     { Bad_Opcode },
7390     { Bad_Opcode },
7391     { Bad_Opcode },
7392     { Bad_Opcode },
7393     { Bad_Opcode },
7394     { Bad_Opcode },
7395     /* 90 */
7396     { Bad_Opcode },
7397     { Bad_Opcode },
7398     { Bad_Opcode },
7399     { Bad_Opcode },
7400     { Bad_Opcode },
7401     { Bad_Opcode },
7402     { Bad_Opcode },
7403     { Bad_Opcode },
7404     /* 98 */
7405     { Bad_Opcode },
7406     { Bad_Opcode },
7407     { Bad_Opcode },
7408     { Bad_Opcode },
7409     { Bad_Opcode },
7410     { Bad_Opcode },
7411     { Bad_Opcode },
7412     { Bad_Opcode },
7413     /* a0 */
7414     { Bad_Opcode },
7415     { Bad_Opcode },
7416     { Bad_Opcode },
7417     { Bad_Opcode },
7418     { Bad_Opcode },
7419     { Bad_Opcode },
7420     { Bad_Opcode },
7421     { Bad_Opcode },
7422     /* a8 */
7423     { Bad_Opcode },
7424     { Bad_Opcode },
7425     { Bad_Opcode },
7426     { Bad_Opcode },
7427     { Bad_Opcode },
7428     { Bad_Opcode },
7429     { Bad_Opcode },
7430     { Bad_Opcode },
7431     /* b0 */
7432     { Bad_Opcode },
7433     { Bad_Opcode },
7434     { Bad_Opcode },
7435     { Bad_Opcode },
7436     { Bad_Opcode },
7437     { Bad_Opcode },
7438     { Bad_Opcode },
7439     { Bad_Opcode },
7440     /* b8 */
7441     { Bad_Opcode },
7442     { Bad_Opcode },
7443     { Bad_Opcode },
7444     { Bad_Opcode },
7445     { Bad_Opcode },
7446     { Bad_Opcode },
7447     { Bad_Opcode },
7448     { Bad_Opcode },
7449     /* c0 */
7450     { Bad_Opcode },
7451     { Bad_Opcode },
7452     { Bad_Opcode },
7453     { Bad_Opcode },
7454     { Bad_Opcode },
7455     { Bad_Opcode },
7456     { Bad_Opcode },
7457     { Bad_Opcode },
7458     /* c8 */
7459     { Bad_Opcode },
7460     { Bad_Opcode },
7461     { Bad_Opcode },
7462     { Bad_Opcode },
7463     { PREFIX_TABLE (PREFIX_0F3ACC) },
7464     { Bad_Opcode },
7465     { PREFIX_TABLE (PREFIX_0F3ACE) },
7466     { PREFIX_TABLE (PREFIX_0F3ACF) },
7467     /* d0 */
7468     { Bad_Opcode },
7469     { Bad_Opcode },
7470     { Bad_Opcode },
7471     { Bad_Opcode },
7472     { Bad_Opcode },
7473     { Bad_Opcode },
7474     { Bad_Opcode },
7475     { Bad_Opcode },
7476     /* d8 */
7477     { Bad_Opcode },
7478     { Bad_Opcode },
7479     { Bad_Opcode },
7480     { Bad_Opcode },
7481     { Bad_Opcode },
7482     { Bad_Opcode },
7483     { Bad_Opcode },
7484     { PREFIX_TABLE (PREFIX_0F3ADF) },
7485     /* e0 */
7486     { Bad_Opcode },
7487     { Bad_Opcode },
7488     { Bad_Opcode },
7489     { Bad_Opcode },
7490     { Bad_Opcode },
7491     { Bad_Opcode },
7492     { Bad_Opcode },
7493     { Bad_Opcode },
7494     /* e8 */
7495     { Bad_Opcode },
7496     { Bad_Opcode },
7497     { Bad_Opcode },
7498     { Bad_Opcode },
7499     { Bad_Opcode },
7500     { Bad_Opcode },
7501     { Bad_Opcode },
7502     { Bad_Opcode },
7503     /* f0 */
7504     { Bad_Opcode },
7505     { Bad_Opcode },
7506     { Bad_Opcode },
7507     { Bad_Opcode },
7508     { Bad_Opcode },
7509     { Bad_Opcode },
7510     { Bad_Opcode },
7511     { Bad_Opcode },
7512     /* f8 */
7513     { Bad_Opcode },
7514     { Bad_Opcode },
7515     { Bad_Opcode },
7516     { Bad_Opcode },
7517     { Bad_Opcode },
7518     { Bad_Opcode },
7519     { Bad_Opcode },
7520     { Bad_Opcode },
7521   },
7522 };
7523
7524 static const struct dis386 xop_table[][256] = {
7525   /* XOP_08 */
7526   {
7527     /* 00 */
7528     { Bad_Opcode },
7529     { Bad_Opcode },
7530     { Bad_Opcode },
7531     { Bad_Opcode },
7532     { Bad_Opcode },
7533     { Bad_Opcode },
7534     { Bad_Opcode },
7535     { Bad_Opcode },
7536     /* 08 */
7537     { Bad_Opcode },
7538     { Bad_Opcode },
7539     { Bad_Opcode },
7540     { Bad_Opcode },
7541     { Bad_Opcode },
7542     { Bad_Opcode },
7543     { Bad_Opcode },
7544     { Bad_Opcode },
7545     /* 10 */
7546     { Bad_Opcode },
7547     { Bad_Opcode },
7548     { Bad_Opcode },
7549     { Bad_Opcode },
7550     { Bad_Opcode },
7551     { Bad_Opcode },
7552     { Bad_Opcode },
7553     { Bad_Opcode },
7554     /* 18 */
7555     { Bad_Opcode },
7556     { Bad_Opcode },
7557     { Bad_Opcode },
7558     { Bad_Opcode },
7559     { Bad_Opcode },
7560     { Bad_Opcode },
7561     { Bad_Opcode },
7562     { Bad_Opcode },
7563     /* 20 */
7564     { Bad_Opcode },
7565     { Bad_Opcode },
7566     { Bad_Opcode },
7567     { Bad_Opcode },
7568     { Bad_Opcode },
7569     { Bad_Opcode },
7570     { Bad_Opcode },
7571     { Bad_Opcode },
7572     /* 28 */
7573     { Bad_Opcode },
7574     { Bad_Opcode },
7575     { Bad_Opcode },
7576     { Bad_Opcode },
7577     { Bad_Opcode },
7578     { Bad_Opcode },
7579     { Bad_Opcode },
7580     { Bad_Opcode },
7581     /* 30 */
7582     { Bad_Opcode },
7583     { Bad_Opcode },
7584     { Bad_Opcode },
7585     { Bad_Opcode },
7586     { Bad_Opcode },
7587     { Bad_Opcode },
7588     { Bad_Opcode },
7589     { Bad_Opcode },
7590     /* 38 */
7591     { Bad_Opcode },
7592     { Bad_Opcode },
7593     { Bad_Opcode },
7594     { Bad_Opcode },
7595     { Bad_Opcode },
7596     { Bad_Opcode },
7597     { Bad_Opcode },
7598     { Bad_Opcode },
7599     /* 40 */
7600     { Bad_Opcode },
7601     { Bad_Opcode },
7602     { Bad_Opcode },
7603     { Bad_Opcode },
7604     { Bad_Opcode },
7605     { Bad_Opcode },
7606     { Bad_Opcode },
7607     { Bad_Opcode },
7608     /* 48 */
7609     { Bad_Opcode },
7610     { Bad_Opcode },
7611     { Bad_Opcode },
7612     { Bad_Opcode },
7613     { Bad_Opcode },
7614     { Bad_Opcode },
7615     { Bad_Opcode },
7616     { Bad_Opcode },
7617     /* 50 */
7618     { Bad_Opcode },
7619     { Bad_Opcode },
7620     { Bad_Opcode },
7621     { Bad_Opcode },
7622     { Bad_Opcode },
7623     { Bad_Opcode },
7624     { Bad_Opcode },
7625     { Bad_Opcode },
7626     /* 58 */
7627     { Bad_Opcode },
7628     { Bad_Opcode },
7629     { Bad_Opcode },
7630     { Bad_Opcode },
7631     { Bad_Opcode },
7632     { Bad_Opcode },
7633     { Bad_Opcode },
7634     { Bad_Opcode },
7635     /* 60 */
7636     { Bad_Opcode },
7637     { Bad_Opcode },
7638     { Bad_Opcode },
7639     { Bad_Opcode },
7640     { Bad_Opcode },
7641     { Bad_Opcode },
7642     { Bad_Opcode },
7643     { Bad_Opcode },
7644     /* 68 */
7645     { Bad_Opcode },
7646     { Bad_Opcode },
7647     { Bad_Opcode },
7648     { Bad_Opcode },
7649     { Bad_Opcode },
7650     { Bad_Opcode },
7651     { Bad_Opcode },
7652     { Bad_Opcode },
7653     /* 70 */
7654     { Bad_Opcode },
7655     { Bad_Opcode },
7656     { Bad_Opcode },
7657     { Bad_Opcode },
7658     { Bad_Opcode },
7659     { Bad_Opcode },
7660     { Bad_Opcode },
7661     { Bad_Opcode },
7662     /* 78 */
7663     { Bad_Opcode },
7664     { Bad_Opcode },
7665     { Bad_Opcode },
7666     { Bad_Opcode },
7667     { Bad_Opcode },
7668     { Bad_Opcode },
7669     { Bad_Opcode },
7670     { Bad_Opcode },
7671     /* 80 */
7672     { Bad_Opcode },
7673     { Bad_Opcode },
7674     { Bad_Opcode },
7675     { Bad_Opcode },
7676     { Bad_Opcode },
7677     { "vpmacssww",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7678     { "vpmacsswd",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7679     { "vpmacssdql",     { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7680     /* 88 */
7681     { Bad_Opcode },
7682     { Bad_Opcode },
7683     { Bad_Opcode },
7684     { Bad_Opcode },
7685     { Bad_Opcode },
7686     { Bad_Opcode },
7687     { "vpmacssdd",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7688     { "vpmacssdqh",     { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7689     /* 90 */
7690     { Bad_Opcode },
7691     { Bad_Opcode },
7692     { Bad_Opcode },
7693     { Bad_Opcode },
7694     { Bad_Opcode },
7695     { "vpmacsww",       { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7696     { "vpmacswd",       { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7697     { "vpmacsdql",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7698     /* 98 */
7699     { Bad_Opcode },
7700     { Bad_Opcode },
7701     { Bad_Opcode },
7702     { Bad_Opcode },
7703     { Bad_Opcode },
7704     { Bad_Opcode },
7705     { "vpmacsdd",       { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7706     { "vpmacsdqh",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7707     /* a0 */
7708     { Bad_Opcode },
7709     { Bad_Opcode },
7710     { "vpcmov",         { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7711     { "vpperm",         { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7712     { Bad_Opcode },
7713     { Bad_Opcode },
7714     { "vpmadcsswd",     { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7715     { Bad_Opcode },
7716     /* a8 */
7717     { Bad_Opcode },
7718     { Bad_Opcode },
7719     { Bad_Opcode },
7720     { Bad_Opcode },
7721     { Bad_Opcode },
7722     { Bad_Opcode },
7723     { Bad_Opcode },
7724     { Bad_Opcode },
7725     /* b0 */
7726     { Bad_Opcode },
7727     { Bad_Opcode },
7728     { Bad_Opcode },
7729     { Bad_Opcode },
7730     { Bad_Opcode },
7731     { Bad_Opcode },
7732     { "vpmadcswd",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7733     { Bad_Opcode },
7734     /* b8 */
7735     { Bad_Opcode },
7736     { Bad_Opcode },
7737     { Bad_Opcode },
7738     { Bad_Opcode },
7739     { Bad_Opcode },
7740     { Bad_Opcode },
7741     { Bad_Opcode },
7742     { Bad_Opcode },
7743     /* c0 */
7744     { "vprotb",         { XM, Vex_2src_1, Ib }, 0 },
7745     { "vprotw",         { XM, Vex_2src_1, Ib }, 0 },
7746     { "vprotd",         { XM, Vex_2src_1, Ib }, 0 },
7747     { "vprotq",         { XM, Vex_2src_1, Ib }, 0 },
7748     { Bad_Opcode },
7749     { Bad_Opcode },
7750     { Bad_Opcode },
7751     { Bad_Opcode },
7752     /* c8 */
7753     { Bad_Opcode },
7754     { Bad_Opcode },
7755     { Bad_Opcode },
7756     { Bad_Opcode },
7757     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
7758     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
7759     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
7760     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
7761     /* d0 */
7762     { Bad_Opcode },
7763     { Bad_Opcode },
7764     { Bad_Opcode },
7765     { Bad_Opcode },
7766     { Bad_Opcode },
7767     { Bad_Opcode },
7768     { Bad_Opcode },
7769     { Bad_Opcode },
7770     /* d8 */
7771     { Bad_Opcode },
7772     { Bad_Opcode },
7773     { Bad_Opcode },
7774     { Bad_Opcode },
7775     { Bad_Opcode },
7776     { Bad_Opcode },
7777     { Bad_Opcode },
7778     { Bad_Opcode },
7779     /* e0 */
7780     { Bad_Opcode },
7781     { Bad_Opcode },
7782     { Bad_Opcode },
7783     { Bad_Opcode },
7784     { Bad_Opcode },
7785     { Bad_Opcode },
7786     { Bad_Opcode },
7787     { Bad_Opcode },
7788     /* e8 */
7789     { Bad_Opcode },
7790     { Bad_Opcode },
7791     { Bad_Opcode },
7792     { Bad_Opcode },
7793     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
7794     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
7795     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
7796     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
7797     /* f0 */
7798     { Bad_Opcode },
7799     { Bad_Opcode },
7800     { Bad_Opcode },
7801     { Bad_Opcode },
7802     { Bad_Opcode },
7803     { Bad_Opcode },
7804     { Bad_Opcode },
7805     { Bad_Opcode },
7806     /* f8 */
7807     { Bad_Opcode },
7808     { Bad_Opcode },
7809     { Bad_Opcode },
7810     { Bad_Opcode },
7811     { Bad_Opcode },
7812     { Bad_Opcode },
7813     { Bad_Opcode },
7814     { Bad_Opcode },
7815   },
7816   /* XOP_09 */
7817   {
7818     /* 00 */
7819     { Bad_Opcode },
7820     { REG_TABLE (REG_XOP_TBM_01) },
7821     { REG_TABLE (REG_XOP_TBM_02) },
7822     { Bad_Opcode },
7823     { Bad_Opcode },
7824     { Bad_Opcode },
7825     { Bad_Opcode },
7826     { Bad_Opcode },
7827     /* 08 */
7828     { Bad_Opcode },
7829     { Bad_Opcode },
7830     { Bad_Opcode },
7831     { Bad_Opcode },
7832     { Bad_Opcode },
7833     { Bad_Opcode },
7834     { Bad_Opcode },
7835     { Bad_Opcode },
7836     /* 10 */
7837     { Bad_Opcode },
7838     { Bad_Opcode },
7839     { REG_TABLE (REG_XOP_LWPCB) },
7840     { Bad_Opcode },
7841     { Bad_Opcode },
7842     { Bad_Opcode },
7843     { Bad_Opcode },
7844     { Bad_Opcode },
7845     /* 18 */
7846     { Bad_Opcode },
7847     { Bad_Opcode },
7848     { Bad_Opcode },
7849     { Bad_Opcode },
7850     { Bad_Opcode },
7851     { Bad_Opcode },
7852     { Bad_Opcode },
7853     { Bad_Opcode },
7854     /* 20 */
7855     { Bad_Opcode },
7856     { Bad_Opcode },
7857     { Bad_Opcode },
7858     { Bad_Opcode },
7859     { Bad_Opcode },
7860     { Bad_Opcode },
7861     { Bad_Opcode },
7862     { Bad_Opcode },
7863     /* 28 */
7864     { Bad_Opcode },
7865     { Bad_Opcode },
7866     { Bad_Opcode },
7867     { Bad_Opcode },
7868     { Bad_Opcode },
7869     { Bad_Opcode },
7870     { Bad_Opcode },
7871     { Bad_Opcode },
7872     /* 30 */
7873     { Bad_Opcode },
7874     { Bad_Opcode },
7875     { Bad_Opcode },
7876     { Bad_Opcode },
7877     { Bad_Opcode },
7878     { Bad_Opcode },
7879     { Bad_Opcode },
7880     { Bad_Opcode },
7881     /* 38 */
7882     { Bad_Opcode },
7883     { Bad_Opcode },
7884     { Bad_Opcode },
7885     { Bad_Opcode },
7886     { Bad_Opcode },
7887     { Bad_Opcode },
7888     { Bad_Opcode },
7889     { Bad_Opcode },
7890     /* 40 */
7891     { Bad_Opcode },
7892     { Bad_Opcode },
7893     { Bad_Opcode },
7894     { Bad_Opcode },
7895     { Bad_Opcode },
7896     { Bad_Opcode },
7897     { Bad_Opcode },
7898     { Bad_Opcode },
7899     /* 48 */
7900     { Bad_Opcode },
7901     { Bad_Opcode },
7902     { Bad_Opcode },
7903     { Bad_Opcode },
7904     { Bad_Opcode },
7905     { Bad_Opcode },
7906     { Bad_Opcode },
7907     { Bad_Opcode },
7908     /* 50 */
7909     { Bad_Opcode },
7910     { Bad_Opcode },
7911     { Bad_Opcode },
7912     { Bad_Opcode },
7913     { Bad_Opcode },
7914     { Bad_Opcode },
7915     { Bad_Opcode },
7916     { Bad_Opcode },
7917     /* 58 */
7918     { Bad_Opcode },
7919     { Bad_Opcode },
7920     { Bad_Opcode },
7921     { Bad_Opcode },
7922     { Bad_Opcode },
7923     { Bad_Opcode },
7924     { Bad_Opcode },
7925     { Bad_Opcode },
7926     /* 60 */
7927     { Bad_Opcode },
7928     { Bad_Opcode },
7929     { Bad_Opcode },
7930     { Bad_Opcode },
7931     { Bad_Opcode },
7932     { Bad_Opcode },
7933     { Bad_Opcode },
7934     { Bad_Opcode },
7935     /* 68 */
7936     { Bad_Opcode },
7937     { Bad_Opcode },
7938     { Bad_Opcode },
7939     { Bad_Opcode },
7940     { Bad_Opcode },
7941     { Bad_Opcode },
7942     { Bad_Opcode },
7943     { Bad_Opcode },
7944     /* 70 */
7945     { Bad_Opcode },
7946     { Bad_Opcode },
7947     { Bad_Opcode },
7948     { Bad_Opcode },
7949     { Bad_Opcode },
7950     { Bad_Opcode },
7951     { Bad_Opcode },
7952     { Bad_Opcode },
7953     /* 78 */
7954     { Bad_Opcode },
7955     { Bad_Opcode },
7956     { Bad_Opcode },
7957     { Bad_Opcode },
7958     { Bad_Opcode },
7959     { Bad_Opcode },
7960     { Bad_Opcode },
7961     { Bad_Opcode },
7962     /* 80 */
7963     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) },
7964     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) },
7965     { "vfrczss",        { XM, EXd }, 0 },
7966     { "vfrczsd",        { XM, EXq }, 0 },
7967     { Bad_Opcode },
7968     { Bad_Opcode },
7969     { Bad_Opcode },
7970     { Bad_Opcode },
7971     /* 88 */
7972     { Bad_Opcode },
7973     { Bad_Opcode },
7974     { Bad_Opcode },
7975     { Bad_Opcode },
7976     { Bad_Opcode },
7977     { Bad_Opcode },
7978     { Bad_Opcode },
7979     { Bad_Opcode },
7980     /* 90 */
7981     { "vprotb",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7982     { "vprotw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7983     { "vprotd",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7984     { "vprotq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7985     { "vpshlb",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7986     { "vpshlw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7987     { "vpshld",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7988     { "vpshlq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7989     /* 98 */
7990     { "vpshab",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7991     { "vpshaw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7992     { "vpshad",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7993     { "vpshaq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7994     { Bad_Opcode },
7995     { Bad_Opcode },
7996     { Bad_Opcode },
7997     { Bad_Opcode },
7998     /* a0 */
7999     { Bad_Opcode },
8000     { Bad_Opcode },
8001     { Bad_Opcode },
8002     { Bad_Opcode },
8003     { Bad_Opcode },
8004     { Bad_Opcode },
8005     { Bad_Opcode },
8006     { Bad_Opcode },
8007     /* a8 */
8008     { Bad_Opcode },
8009     { Bad_Opcode },
8010     { Bad_Opcode },
8011     { Bad_Opcode },
8012     { Bad_Opcode },
8013     { Bad_Opcode },
8014     { Bad_Opcode },
8015     { Bad_Opcode },
8016     /* b0 */
8017     { Bad_Opcode },
8018     { Bad_Opcode },
8019     { Bad_Opcode },
8020     { Bad_Opcode },
8021     { Bad_Opcode },
8022     { Bad_Opcode },
8023     { Bad_Opcode },
8024     { Bad_Opcode },
8025     /* b8 */
8026     { Bad_Opcode },
8027     { Bad_Opcode },
8028     { Bad_Opcode },
8029     { Bad_Opcode },
8030     { Bad_Opcode },
8031     { Bad_Opcode },
8032     { Bad_Opcode },
8033     { Bad_Opcode },
8034     /* c0 */
8035     { Bad_Opcode },
8036     { "vphaddbw",       { XM, EXxmm }, 0 },
8037     { "vphaddbd",       { XM, EXxmm }, 0 },
8038     { "vphaddbq",       { XM, EXxmm }, 0 },
8039     { Bad_Opcode },
8040     { Bad_Opcode },
8041     { "vphaddwd",       { XM, EXxmm }, 0 },
8042     { "vphaddwq",       { XM, EXxmm }, 0 },
8043     /* c8 */
8044     { Bad_Opcode },
8045     { Bad_Opcode },
8046     { Bad_Opcode },
8047     { "vphadddq",       { XM, EXxmm }, 0 },
8048     { Bad_Opcode },
8049     { Bad_Opcode },
8050     { Bad_Opcode },
8051     { Bad_Opcode },
8052     /* d0 */
8053     { Bad_Opcode },
8054     { "vphaddubw",      { XM, EXxmm }, 0 },
8055     { "vphaddubd",      { XM, EXxmm }, 0 },
8056     { "vphaddubq",      { XM, EXxmm }, 0 },
8057     { Bad_Opcode },
8058     { Bad_Opcode },
8059     { "vphadduwd",      { XM, EXxmm }, 0 },
8060     { "vphadduwq",      { XM, EXxmm }, 0 },
8061     /* d8 */
8062     { Bad_Opcode },
8063     { Bad_Opcode },
8064     { Bad_Opcode },
8065     { "vphaddudq",      { XM, EXxmm }, 0 },
8066     { Bad_Opcode },
8067     { Bad_Opcode },
8068     { Bad_Opcode },
8069     { Bad_Opcode },
8070     /* e0 */
8071     { Bad_Opcode },
8072     { "vphsubbw",       { XM, EXxmm }, 0 },
8073     { "vphsubwd",       { XM, EXxmm }, 0 },
8074     { "vphsubdq",       { XM, EXxmm }, 0 },
8075     { Bad_Opcode },
8076     { Bad_Opcode },
8077     { Bad_Opcode },
8078     { Bad_Opcode },
8079     /* e8 */
8080     { Bad_Opcode },
8081     { Bad_Opcode },
8082     { Bad_Opcode },
8083     { Bad_Opcode },
8084     { Bad_Opcode },
8085     { Bad_Opcode },
8086     { Bad_Opcode },
8087     { Bad_Opcode },
8088     /* f0 */
8089     { Bad_Opcode },
8090     { Bad_Opcode },
8091     { Bad_Opcode },
8092     { Bad_Opcode },
8093     { Bad_Opcode },
8094     { Bad_Opcode },
8095     { Bad_Opcode },
8096     { Bad_Opcode },
8097     /* f8 */
8098     { Bad_Opcode },
8099     { Bad_Opcode },
8100     { Bad_Opcode },
8101     { Bad_Opcode },
8102     { Bad_Opcode },
8103     { Bad_Opcode },
8104     { Bad_Opcode },
8105     { Bad_Opcode },
8106   },
8107   /* XOP_0A */
8108   {
8109     /* 00 */
8110     { Bad_Opcode },
8111     { Bad_Opcode },
8112     { Bad_Opcode },
8113     { Bad_Opcode },
8114     { Bad_Opcode },
8115     { Bad_Opcode },
8116     { Bad_Opcode },
8117     { Bad_Opcode },
8118     /* 08 */
8119     { Bad_Opcode },
8120     { Bad_Opcode },
8121     { Bad_Opcode },
8122     { Bad_Opcode },
8123     { Bad_Opcode },
8124     { Bad_Opcode },
8125     { Bad_Opcode },
8126     { Bad_Opcode },
8127     /* 10 */
8128     { "bextrS", { Gdq, Edq, Id }, 0 },
8129     { Bad_Opcode },
8130     { REG_TABLE (REG_XOP_LWP) },
8131     { Bad_Opcode },
8132     { Bad_Opcode },
8133     { Bad_Opcode },
8134     { Bad_Opcode },
8135     { Bad_Opcode },
8136     /* 18 */
8137     { Bad_Opcode },
8138     { Bad_Opcode },
8139     { Bad_Opcode },
8140     { Bad_Opcode },
8141     { Bad_Opcode },
8142     { Bad_Opcode },
8143     { Bad_Opcode },
8144     { Bad_Opcode },
8145     /* 20 */
8146     { Bad_Opcode },
8147     { Bad_Opcode },
8148     { Bad_Opcode },
8149     { Bad_Opcode },
8150     { Bad_Opcode },
8151     { Bad_Opcode },
8152     { Bad_Opcode },
8153     { Bad_Opcode },
8154     /* 28 */
8155     { Bad_Opcode },
8156     { Bad_Opcode },
8157     { Bad_Opcode },
8158     { Bad_Opcode },
8159     { Bad_Opcode },
8160     { Bad_Opcode },
8161     { Bad_Opcode },
8162     { Bad_Opcode },
8163     /* 30 */
8164     { Bad_Opcode },
8165     { Bad_Opcode },
8166     { Bad_Opcode },
8167     { Bad_Opcode },
8168     { Bad_Opcode },
8169     { Bad_Opcode },
8170     { Bad_Opcode },
8171     { Bad_Opcode },
8172     /* 38 */
8173     { Bad_Opcode },
8174     { Bad_Opcode },
8175     { Bad_Opcode },
8176     { Bad_Opcode },
8177     { Bad_Opcode },
8178     { Bad_Opcode },
8179     { Bad_Opcode },
8180     { Bad_Opcode },
8181     /* 40 */
8182     { Bad_Opcode },
8183     { Bad_Opcode },
8184     { Bad_Opcode },
8185     { Bad_Opcode },
8186     { Bad_Opcode },
8187     { Bad_Opcode },
8188     { Bad_Opcode },
8189     { Bad_Opcode },
8190     /* 48 */
8191     { Bad_Opcode },
8192     { Bad_Opcode },
8193     { Bad_Opcode },
8194     { Bad_Opcode },
8195     { Bad_Opcode },
8196     { Bad_Opcode },
8197     { Bad_Opcode },
8198     { Bad_Opcode },
8199     /* 50 */
8200     { Bad_Opcode },
8201     { Bad_Opcode },
8202     { Bad_Opcode },
8203     { Bad_Opcode },
8204     { Bad_Opcode },
8205     { Bad_Opcode },
8206     { Bad_Opcode },
8207     { Bad_Opcode },
8208     /* 58 */
8209     { Bad_Opcode },
8210     { Bad_Opcode },
8211     { Bad_Opcode },
8212     { Bad_Opcode },
8213     { Bad_Opcode },
8214     { Bad_Opcode },
8215     { Bad_Opcode },
8216     { Bad_Opcode },
8217     /* 60 */
8218     { Bad_Opcode },
8219     { Bad_Opcode },
8220     { Bad_Opcode },
8221     { Bad_Opcode },
8222     { Bad_Opcode },
8223     { Bad_Opcode },
8224     { Bad_Opcode },
8225     { Bad_Opcode },
8226     /* 68 */
8227     { Bad_Opcode },
8228     { Bad_Opcode },
8229     { Bad_Opcode },
8230     { Bad_Opcode },
8231     { Bad_Opcode },
8232     { Bad_Opcode },
8233     { Bad_Opcode },
8234     { Bad_Opcode },
8235     /* 70 */
8236     { Bad_Opcode },
8237     { Bad_Opcode },
8238     { Bad_Opcode },
8239     { Bad_Opcode },
8240     { Bad_Opcode },
8241     { Bad_Opcode },
8242     { Bad_Opcode },
8243     { Bad_Opcode },
8244     /* 78 */
8245     { Bad_Opcode },
8246     { Bad_Opcode },
8247     { Bad_Opcode },
8248     { Bad_Opcode },
8249     { Bad_Opcode },
8250     { Bad_Opcode },
8251     { Bad_Opcode },
8252     { Bad_Opcode },
8253     /* 80 */
8254     { Bad_Opcode },
8255     { Bad_Opcode },
8256     { Bad_Opcode },
8257     { Bad_Opcode },
8258     { Bad_Opcode },
8259     { Bad_Opcode },
8260     { Bad_Opcode },
8261     { Bad_Opcode },
8262     /* 88 */
8263     { Bad_Opcode },
8264     { Bad_Opcode },
8265     { Bad_Opcode },
8266     { Bad_Opcode },
8267     { Bad_Opcode },
8268     { Bad_Opcode },
8269     { Bad_Opcode },
8270     { Bad_Opcode },
8271     /* 90 */
8272     { Bad_Opcode },
8273     { Bad_Opcode },
8274     { Bad_Opcode },
8275     { Bad_Opcode },
8276     { Bad_Opcode },
8277     { Bad_Opcode },
8278     { Bad_Opcode },
8279     { Bad_Opcode },
8280     /* 98 */
8281     { Bad_Opcode },
8282     { Bad_Opcode },
8283     { Bad_Opcode },
8284     { Bad_Opcode },
8285     { Bad_Opcode },
8286     { Bad_Opcode },
8287     { Bad_Opcode },
8288     { Bad_Opcode },
8289     /* a0 */
8290     { Bad_Opcode },
8291     { Bad_Opcode },
8292     { Bad_Opcode },
8293     { Bad_Opcode },
8294     { Bad_Opcode },
8295     { Bad_Opcode },
8296     { Bad_Opcode },
8297     { Bad_Opcode },
8298     /* a8 */
8299     { Bad_Opcode },
8300     { Bad_Opcode },
8301     { Bad_Opcode },
8302     { Bad_Opcode },
8303     { Bad_Opcode },
8304     { Bad_Opcode },
8305     { Bad_Opcode },
8306     { Bad_Opcode },
8307     /* b0 */
8308     { Bad_Opcode },
8309     { Bad_Opcode },
8310     { Bad_Opcode },
8311     { Bad_Opcode },
8312     { Bad_Opcode },
8313     { Bad_Opcode },
8314     { Bad_Opcode },
8315     { Bad_Opcode },
8316     /* b8 */
8317     { Bad_Opcode },
8318     { Bad_Opcode },
8319     { Bad_Opcode },
8320     { Bad_Opcode },
8321     { Bad_Opcode },
8322     { Bad_Opcode },
8323     { Bad_Opcode },
8324     { Bad_Opcode },
8325     /* c0 */
8326     { Bad_Opcode },
8327     { Bad_Opcode },
8328     { Bad_Opcode },
8329     { Bad_Opcode },
8330     { Bad_Opcode },
8331     { Bad_Opcode },
8332     { Bad_Opcode },
8333     { Bad_Opcode },
8334     /* c8 */
8335     { Bad_Opcode },
8336     { Bad_Opcode },
8337     { Bad_Opcode },
8338     { Bad_Opcode },
8339     { Bad_Opcode },
8340     { Bad_Opcode },
8341     { Bad_Opcode },
8342     { Bad_Opcode },
8343     /* d0 */
8344     { Bad_Opcode },
8345     { Bad_Opcode },
8346     { Bad_Opcode },
8347     { Bad_Opcode },
8348     { Bad_Opcode },
8349     { Bad_Opcode },
8350     { Bad_Opcode },
8351     { Bad_Opcode },
8352     /* d8 */
8353     { Bad_Opcode },
8354     { Bad_Opcode },
8355     { Bad_Opcode },
8356     { Bad_Opcode },
8357     { Bad_Opcode },
8358     { Bad_Opcode },
8359     { Bad_Opcode },
8360     { Bad_Opcode },
8361     /* e0 */
8362     { Bad_Opcode },
8363     { Bad_Opcode },
8364     { Bad_Opcode },
8365     { Bad_Opcode },
8366     { Bad_Opcode },
8367     { Bad_Opcode },
8368     { Bad_Opcode },
8369     { Bad_Opcode },
8370     /* e8 */
8371     { Bad_Opcode },
8372     { Bad_Opcode },
8373     { Bad_Opcode },
8374     { Bad_Opcode },
8375     { Bad_Opcode },
8376     { Bad_Opcode },
8377     { Bad_Opcode },
8378     { Bad_Opcode },
8379     /* f0 */
8380     { Bad_Opcode },
8381     { Bad_Opcode },
8382     { Bad_Opcode },
8383     { Bad_Opcode },
8384     { Bad_Opcode },
8385     { Bad_Opcode },
8386     { Bad_Opcode },
8387     { Bad_Opcode },
8388     /* f8 */
8389     { Bad_Opcode },
8390     { Bad_Opcode },
8391     { Bad_Opcode },
8392     { Bad_Opcode },
8393     { Bad_Opcode },
8394     { Bad_Opcode },
8395     { Bad_Opcode },
8396     { Bad_Opcode },
8397   },
8398 };
8399
8400 static const struct dis386 vex_table[][256] = {
8401   /* VEX_0F */
8402   {
8403     /* 00 */
8404     { Bad_Opcode },
8405     { Bad_Opcode },
8406     { Bad_Opcode },
8407     { Bad_Opcode },
8408     { Bad_Opcode },
8409     { Bad_Opcode },
8410     { Bad_Opcode },
8411     { Bad_Opcode },
8412     /* 08 */
8413     { Bad_Opcode },
8414     { Bad_Opcode },
8415     { Bad_Opcode },
8416     { Bad_Opcode },
8417     { Bad_Opcode },
8418     { Bad_Opcode },
8419     { Bad_Opcode },
8420     { Bad_Opcode },
8421     /* 10 */
8422     { PREFIX_TABLE (PREFIX_VEX_0F10) },
8423     { PREFIX_TABLE (PREFIX_VEX_0F11) },
8424     { PREFIX_TABLE (PREFIX_VEX_0F12) },
8425     { MOD_TABLE (MOD_VEX_0F13) },
8426     { "vunpcklpX",      { XM, Vex, EXx }, PREFIX_OPCODE },
8427     { "vunpckhpX",      { XM, Vex, EXx }, PREFIX_OPCODE },
8428     { PREFIX_TABLE (PREFIX_VEX_0F16) },
8429     { MOD_TABLE (MOD_VEX_0F17) },
8430     /* 18 */
8431     { Bad_Opcode },
8432     { Bad_Opcode },
8433     { Bad_Opcode },
8434     { Bad_Opcode },
8435     { Bad_Opcode },
8436     { Bad_Opcode },
8437     { Bad_Opcode },
8438     { Bad_Opcode },
8439     /* 20 */
8440     { Bad_Opcode },
8441     { Bad_Opcode },
8442     { Bad_Opcode },
8443     { Bad_Opcode },
8444     { Bad_Opcode },
8445     { Bad_Opcode },
8446     { Bad_Opcode },
8447     { Bad_Opcode },
8448     /* 28 */
8449     { "vmovapX",        { XM, EXx }, PREFIX_OPCODE },
8450     { "vmovapX",        { EXxS, XM }, PREFIX_OPCODE },
8451     { PREFIX_TABLE (PREFIX_VEX_0F2A) },
8452     { MOD_TABLE (MOD_VEX_0F2B) },
8453     { PREFIX_TABLE (PREFIX_VEX_0F2C) },
8454     { PREFIX_TABLE (PREFIX_VEX_0F2D) },
8455     { PREFIX_TABLE (PREFIX_VEX_0F2E) },
8456     { PREFIX_TABLE (PREFIX_VEX_0F2F) },
8457     /* 30 */
8458     { Bad_Opcode },
8459     { Bad_Opcode },
8460     { Bad_Opcode },
8461     { Bad_Opcode },
8462     { Bad_Opcode },
8463     { Bad_Opcode },
8464     { Bad_Opcode },
8465     { Bad_Opcode },
8466     /* 38 */
8467     { Bad_Opcode },
8468     { Bad_Opcode },
8469     { Bad_Opcode },
8470     { Bad_Opcode },
8471     { Bad_Opcode },
8472     { Bad_Opcode },
8473     { Bad_Opcode },
8474     { Bad_Opcode },
8475     /* 40 */
8476     { Bad_Opcode },
8477     { PREFIX_TABLE (PREFIX_VEX_0F41) },
8478     { PREFIX_TABLE (PREFIX_VEX_0F42) },
8479     { Bad_Opcode },
8480     { PREFIX_TABLE (PREFIX_VEX_0F44) },
8481     { PREFIX_TABLE (PREFIX_VEX_0F45) },
8482     { PREFIX_TABLE (PREFIX_VEX_0F46) },
8483     { PREFIX_TABLE (PREFIX_VEX_0F47) },
8484     /* 48 */
8485     { Bad_Opcode },
8486     { Bad_Opcode },
8487     { PREFIX_TABLE (PREFIX_VEX_0F4A) },
8488     { PREFIX_TABLE (PREFIX_VEX_0F4B) },
8489     { Bad_Opcode },
8490     { Bad_Opcode },
8491     { Bad_Opcode },
8492     { Bad_Opcode },
8493     /* 50 */
8494     { MOD_TABLE (MOD_VEX_0F50) },
8495     { PREFIX_TABLE (PREFIX_VEX_0F51) },
8496     { PREFIX_TABLE (PREFIX_VEX_0F52) },
8497     { PREFIX_TABLE (PREFIX_VEX_0F53) },
8498     { "vandpX",         { XM, Vex, EXx }, PREFIX_OPCODE },
8499     { "vandnpX",        { XM, Vex, EXx }, PREFIX_OPCODE },
8500     { "vorpX",          { XM, Vex, EXx }, PREFIX_OPCODE },
8501     { "vxorpX",         { XM, Vex, EXx }, PREFIX_OPCODE },
8502     /* 58 */
8503     { PREFIX_TABLE (PREFIX_VEX_0F58) },
8504     { PREFIX_TABLE (PREFIX_VEX_0F59) },
8505     { PREFIX_TABLE (PREFIX_VEX_0F5A) },
8506     { PREFIX_TABLE (PREFIX_VEX_0F5B) },
8507     { PREFIX_TABLE (PREFIX_VEX_0F5C) },
8508     { PREFIX_TABLE (PREFIX_VEX_0F5D) },
8509     { PREFIX_TABLE (PREFIX_VEX_0F5E) },
8510     { PREFIX_TABLE (PREFIX_VEX_0F5F) },
8511     /* 60 */
8512     { PREFIX_TABLE (PREFIX_VEX_0F60) },
8513     { PREFIX_TABLE (PREFIX_VEX_0F61) },
8514     { PREFIX_TABLE (PREFIX_VEX_0F62) },
8515     { PREFIX_TABLE (PREFIX_VEX_0F63) },
8516     { PREFIX_TABLE (PREFIX_VEX_0F64) },
8517     { PREFIX_TABLE (PREFIX_VEX_0F65) },
8518     { PREFIX_TABLE (PREFIX_VEX_0F66) },
8519     { PREFIX_TABLE (PREFIX_VEX_0F67) },
8520     /* 68 */
8521     { PREFIX_TABLE (PREFIX_VEX_0F68) },
8522     { PREFIX_TABLE (PREFIX_VEX_0F69) },
8523     { PREFIX_TABLE (PREFIX_VEX_0F6A) },
8524     { PREFIX_TABLE (PREFIX_VEX_0F6B) },
8525     { PREFIX_TABLE (PREFIX_VEX_0F6C) },
8526     { PREFIX_TABLE (PREFIX_VEX_0F6D) },
8527     { PREFIX_TABLE (PREFIX_VEX_0F6E) },
8528     { PREFIX_TABLE (PREFIX_VEX_0F6F) },
8529     /* 70 */
8530     { PREFIX_TABLE (PREFIX_VEX_0F70) },
8531     { REG_TABLE (REG_VEX_0F71) },
8532     { REG_TABLE (REG_VEX_0F72) },
8533     { REG_TABLE (REG_VEX_0F73) },
8534     { PREFIX_TABLE (PREFIX_VEX_0F74) },
8535     { PREFIX_TABLE (PREFIX_VEX_0F75) },
8536     { PREFIX_TABLE (PREFIX_VEX_0F76) },
8537     { PREFIX_TABLE (PREFIX_VEX_0F77) },
8538     /* 78 */
8539     { Bad_Opcode },
8540     { Bad_Opcode },
8541     { Bad_Opcode },
8542     { Bad_Opcode },
8543     { PREFIX_TABLE (PREFIX_VEX_0F7C) },
8544     { PREFIX_TABLE (PREFIX_VEX_0F7D) },
8545     { PREFIX_TABLE (PREFIX_VEX_0F7E) },
8546     { PREFIX_TABLE (PREFIX_VEX_0F7F) },
8547     /* 80 */
8548     { Bad_Opcode },
8549     { Bad_Opcode },
8550     { Bad_Opcode },
8551     { Bad_Opcode },
8552     { Bad_Opcode },
8553     { Bad_Opcode },
8554     { Bad_Opcode },
8555     { Bad_Opcode },
8556     /* 88 */
8557     { Bad_Opcode },
8558     { Bad_Opcode },
8559     { Bad_Opcode },
8560     { Bad_Opcode },
8561     { Bad_Opcode },
8562     { Bad_Opcode },
8563     { Bad_Opcode },
8564     { Bad_Opcode },
8565     /* 90 */
8566     { PREFIX_TABLE (PREFIX_VEX_0F90) },
8567     { PREFIX_TABLE (PREFIX_VEX_0F91) },
8568     { PREFIX_TABLE (PREFIX_VEX_0F92) },
8569     { PREFIX_TABLE (PREFIX_VEX_0F93) },
8570     { Bad_Opcode },
8571     { Bad_Opcode },
8572     { Bad_Opcode },
8573     { Bad_Opcode },
8574     /* 98 */
8575     { PREFIX_TABLE (PREFIX_VEX_0F98) },
8576     { PREFIX_TABLE (PREFIX_VEX_0F99) },
8577     { Bad_Opcode },
8578     { Bad_Opcode },
8579     { Bad_Opcode },
8580     { Bad_Opcode },
8581     { Bad_Opcode },
8582     { Bad_Opcode },
8583     /* a0 */
8584     { Bad_Opcode },
8585     { Bad_Opcode },
8586     { Bad_Opcode },
8587     { Bad_Opcode },
8588     { Bad_Opcode },
8589     { Bad_Opcode },
8590     { Bad_Opcode },
8591     { Bad_Opcode },
8592     /* a8 */
8593     { Bad_Opcode },
8594     { Bad_Opcode },
8595     { Bad_Opcode },
8596     { Bad_Opcode },
8597     { Bad_Opcode },
8598     { Bad_Opcode },
8599     { REG_TABLE (REG_VEX_0FAE) },
8600     { Bad_Opcode },
8601     /* b0 */
8602     { Bad_Opcode },
8603     { Bad_Opcode },
8604     { Bad_Opcode },
8605     { Bad_Opcode },
8606     { Bad_Opcode },
8607     { Bad_Opcode },
8608     { Bad_Opcode },
8609     { Bad_Opcode },
8610     /* b8 */
8611     { Bad_Opcode },
8612     { Bad_Opcode },
8613     { Bad_Opcode },
8614     { Bad_Opcode },
8615     { Bad_Opcode },
8616     { Bad_Opcode },
8617     { Bad_Opcode },
8618     { Bad_Opcode },
8619     /* c0 */
8620     { Bad_Opcode },
8621     { Bad_Opcode },
8622     { PREFIX_TABLE (PREFIX_VEX_0FC2) },
8623     { Bad_Opcode },
8624     { PREFIX_TABLE (PREFIX_VEX_0FC4) },
8625     { PREFIX_TABLE (PREFIX_VEX_0FC5) },
8626     { "vshufpX",        { XM, Vex, EXx, Ib }, PREFIX_OPCODE },
8627     { Bad_Opcode },
8628     /* c8 */
8629     { Bad_Opcode },
8630     { Bad_Opcode },
8631     { Bad_Opcode },
8632     { Bad_Opcode },
8633     { Bad_Opcode },
8634     { Bad_Opcode },
8635     { Bad_Opcode },
8636     { Bad_Opcode },
8637     /* d0 */
8638     { PREFIX_TABLE (PREFIX_VEX_0FD0) },
8639     { PREFIX_TABLE (PREFIX_VEX_0FD1) },
8640     { PREFIX_TABLE (PREFIX_VEX_0FD2) },
8641     { PREFIX_TABLE (PREFIX_VEX_0FD3) },
8642     { PREFIX_TABLE (PREFIX_VEX_0FD4) },
8643     { PREFIX_TABLE (PREFIX_VEX_0FD5) },
8644     { PREFIX_TABLE (PREFIX_VEX_0FD6) },
8645     { PREFIX_TABLE (PREFIX_VEX_0FD7) },
8646     /* d8 */
8647     { PREFIX_TABLE (PREFIX_VEX_0FD8) },
8648     { PREFIX_TABLE (PREFIX_VEX_0FD9) },
8649     { PREFIX_TABLE (PREFIX_VEX_0FDA) },
8650     { PREFIX_TABLE (PREFIX_VEX_0FDB) },
8651     { PREFIX_TABLE (PREFIX_VEX_0FDC) },
8652     { PREFIX_TABLE (PREFIX_VEX_0FDD) },
8653     { PREFIX_TABLE (PREFIX_VEX_0FDE) },
8654     { PREFIX_TABLE (PREFIX_VEX_0FDF) },
8655     /* e0 */
8656     { PREFIX_TABLE (PREFIX_VEX_0FE0) },
8657     { PREFIX_TABLE (PREFIX_VEX_0FE1) },
8658     { PREFIX_TABLE (PREFIX_VEX_0FE2) },
8659     { PREFIX_TABLE (PREFIX_VEX_0FE3) },
8660     { PREFIX_TABLE (PREFIX_VEX_0FE4) },
8661     { PREFIX_TABLE (PREFIX_VEX_0FE5) },
8662     { PREFIX_TABLE (PREFIX_VEX_0FE6) },
8663     { PREFIX_TABLE (PREFIX_VEX_0FE7) },
8664     /* e8 */
8665     { PREFIX_TABLE (PREFIX_VEX_0FE8) },
8666     { PREFIX_TABLE (PREFIX_VEX_0FE9) },
8667     { PREFIX_TABLE (PREFIX_VEX_0FEA) },
8668     { PREFIX_TABLE (PREFIX_VEX_0FEB) },
8669     { PREFIX_TABLE (PREFIX_VEX_0FEC) },
8670     { PREFIX_TABLE (PREFIX_VEX_0FED) },
8671     { PREFIX_TABLE (PREFIX_VEX_0FEE) },
8672     { PREFIX_TABLE (PREFIX_VEX_0FEF) },
8673     /* f0 */
8674     { PREFIX_TABLE (PREFIX_VEX_0FF0) },
8675     { PREFIX_TABLE (PREFIX_VEX_0FF1) },
8676     { PREFIX_TABLE (PREFIX_VEX_0FF2) },
8677     { PREFIX_TABLE (PREFIX_VEX_0FF3) },
8678     { PREFIX_TABLE (PREFIX_VEX_0FF4) },
8679     { PREFIX_TABLE (PREFIX_VEX_0FF5) },
8680     { PREFIX_TABLE (PREFIX_VEX_0FF6) },
8681     { PREFIX_TABLE (PREFIX_VEX_0FF7) },
8682     /* f8 */
8683     { PREFIX_TABLE (PREFIX_VEX_0FF8) },
8684     { PREFIX_TABLE (PREFIX_VEX_0FF9) },
8685     { PREFIX_TABLE (PREFIX_VEX_0FFA) },
8686     { PREFIX_TABLE (PREFIX_VEX_0FFB) },
8687     { PREFIX_TABLE (PREFIX_VEX_0FFC) },
8688     { PREFIX_TABLE (PREFIX_VEX_0FFD) },
8689     { PREFIX_TABLE (PREFIX_VEX_0FFE) },
8690     { Bad_Opcode },
8691   },
8692   /* VEX_0F38 */
8693   {
8694     /* 00 */
8695     { PREFIX_TABLE (PREFIX_VEX_0F3800) },
8696     { PREFIX_TABLE (PREFIX_VEX_0F3801) },
8697     { PREFIX_TABLE (PREFIX_VEX_0F3802) },
8698     { PREFIX_TABLE (PREFIX_VEX_0F3803) },
8699     { PREFIX_TABLE (PREFIX_VEX_0F3804) },
8700     { PREFIX_TABLE (PREFIX_VEX_0F3805) },
8701     { PREFIX_TABLE (PREFIX_VEX_0F3806) },
8702     { PREFIX_TABLE (PREFIX_VEX_0F3807) },
8703     /* 08 */
8704     { PREFIX_TABLE (PREFIX_VEX_0F3808) },
8705     { PREFIX_TABLE (PREFIX_VEX_0F3809) },
8706     { PREFIX_TABLE (PREFIX_VEX_0F380A) },
8707     { PREFIX_TABLE (PREFIX_VEX_0F380B) },
8708     { PREFIX_TABLE (PREFIX_VEX_0F380C) },
8709     { PREFIX_TABLE (PREFIX_VEX_0F380D) },
8710     { PREFIX_TABLE (PREFIX_VEX_0F380E) },
8711     { PREFIX_TABLE (PREFIX_VEX_0F380F) },
8712     /* 10 */
8713     { Bad_Opcode },
8714     { Bad_Opcode },
8715     { Bad_Opcode },
8716     { PREFIX_TABLE (PREFIX_VEX_0F3813) },
8717     { Bad_Opcode },
8718     { Bad_Opcode },
8719     { PREFIX_TABLE (PREFIX_VEX_0F3816) },
8720     { PREFIX_TABLE (PREFIX_VEX_0F3817) },
8721     /* 18 */
8722     { PREFIX_TABLE (PREFIX_VEX_0F3818) },
8723     { PREFIX_TABLE (PREFIX_VEX_0F3819) },
8724     { PREFIX_TABLE (PREFIX_VEX_0F381A) },
8725     { Bad_Opcode },
8726     { PREFIX_TABLE (PREFIX_VEX_0F381C) },
8727     { PREFIX_TABLE (PREFIX_VEX_0F381D) },
8728     { PREFIX_TABLE (PREFIX_VEX_0F381E) },
8729     { Bad_Opcode },
8730     /* 20 */
8731     { PREFIX_TABLE (PREFIX_VEX_0F3820) },
8732     { PREFIX_TABLE (PREFIX_VEX_0F3821) },
8733     { PREFIX_TABLE (PREFIX_VEX_0F3822) },
8734     { PREFIX_TABLE (PREFIX_VEX_0F3823) },
8735     { PREFIX_TABLE (PREFIX_VEX_0F3824) },
8736     { PREFIX_TABLE (PREFIX_VEX_0F3825) },
8737     { Bad_Opcode },
8738     { Bad_Opcode },
8739     /* 28 */
8740     { PREFIX_TABLE (PREFIX_VEX_0F3828) },
8741     { PREFIX_TABLE (PREFIX_VEX_0F3829) },
8742     { PREFIX_TABLE (PREFIX_VEX_0F382A) },
8743     { PREFIX_TABLE (PREFIX_VEX_0F382B) },
8744     { PREFIX_TABLE (PREFIX_VEX_0F382C) },
8745     { PREFIX_TABLE (PREFIX_VEX_0F382D) },
8746     { PREFIX_TABLE (PREFIX_VEX_0F382E) },
8747     { PREFIX_TABLE (PREFIX_VEX_0F382F) },
8748     /* 30 */
8749     { PREFIX_TABLE (PREFIX_VEX_0F3830) },
8750     { PREFIX_TABLE (PREFIX_VEX_0F3831) },
8751     { PREFIX_TABLE (PREFIX_VEX_0F3832) },
8752     { PREFIX_TABLE (PREFIX_VEX_0F3833) },
8753     { PREFIX_TABLE (PREFIX_VEX_0F3834) },
8754     { PREFIX_TABLE (PREFIX_VEX_0F3835) },
8755     { PREFIX_TABLE (PREFIX_VEX_0F3836) },
8756     { PREFIX_TABLE (PREFIX_VEX_0F3837) },
8757     /* 38 */
8758     { PREFIX_TABLE (PREFIX_VEX_0F3838) },
8759     { PREFIX_TABLE (PREFIX_VEX_0F3839) },
8760     { PREFIX_TABLE (PREFIX_VEX_0F383A) },
8761     { PREFIX_TABLE (PREFIX_VEX_0F383B) },
8762     { PREFIX_TABLE (PREFIX_VEX_0F383C) },
8763     { PREFIX_TABLE (PREFIX_VEX_0F383D) },
8764     { PREFIX_TABLE (PREFIX_VEX_0F383E) },
8765     { PREFIX_TABLE (PREFIX_VEX_0F383F) },
8766     /* 40 */
8767     { PREFIX_TABLE (PREFIX_VEX_0F3840) },
8768     { PREFIX_TABLE (PREFIX_VEX_0F3841) },
8769     { Bad_Opcode },
8770     { Bad_Opcode },
8771     { Bad_Opcode },
8772     { PREFIX_TABLE (PREFIX_VEX_0F3845) },
8773     { PREFIX_TABLE (PREFIX_VEX_0F3846) },
8774     { PREFIX_TABLE (PREFIX_VEX_0F3847) },
8775     /* 48 */
8776     { Bad_Opcode },
8777     { Bad_Opcode },
8778     { Bad_Opcode },
8779     { Bad_Opcode },
8780     { Bad_Opcode },
8781     { Bad_Opcode },
8782     { Bad_Opcode },
8783     { Bad_Opcode },
8784     /* 50 */
8785     { Bad_Opcode },
8786     { Bad_Opcode },
8787     { Bad_Opcode },
8788     { Bad_Opcode },
8789     { Bad_Opcode },
8790     { Bad_Opcode },
8791     { Bad_Opcode },
8792     { Bad_Opcode },
8793     /* 58 */
8794     { PREFIX_TABLE (PREFIX_VEX_0F3858) },
8795     { PREFIX_TABLE (PREFIX_VEX_0F3859) },
8796     { PREFIX_TABLE (PREFIX_VEX_0F385A) },
8797     { Bad_Opcode },
8798     { Bad_Opcode },
8799     { Bad_Opcode },
8800     { Bad_Opcode },
8801     { Bad_Opcode },
8802     /* 60 */
8803     { Bad_Opcode },
8804     { Bad_Opcode },
8805     { Bad_Opcode },
8806     { Bad_Opcode },
8807     { Bad_Opcode },
8808     { Bad_Opcode },
8809     { Bad_Opcode },
8810     { Bad_Opcode },
8811     /* 68 */
8812     { Bad_Opcode },
8813     { Bad_Opcode },
8814     { Bad_Opcode },
8815     { Bad_Opcode },
8816     { Bad_Opcode },
8817     { Bad_Opcode },
8818     { Bad_Opcode },
8819     { Bad_Opcode },
8820     /* 70 */
8821     { Bad_Opcode },
8822     { Bad_Opcode },
8823     { Bad_Opcode },
8824     { Bad_Opcode },
8825     { Bad_Opcode },
8826     { Bad_Opcode },
8827     { Bad_Opcode },
8828     { Bad_Opcode },
8829     /* 78 */
8830     { PREFIX_TABLE (PREFIX_VEX_0F3878) },
8831     { PREFIX_TABLE (PREFIX_VEX_0F3879) },
8832     { Bad_Opcode },
8833     { Bad_Opcode },
8834     { Bad_Opcode },
8835     { Bad_Opcode },
8836     { Bad_Opcode },
8837     { Bad_Opcode },
8838     /* 80 */
8839     { Bad_Opcode },
8840     { Bad_Opcode },
8841     { Bad_Opcode },
8842     { Bad_Opcode },
8843     { Bad_Opcode },
8844     { Bad_Opcode },
8845     { Bad_Opcode },
8846     { Bad_Opcode },
8847     /* 88 */
8848     { Bad_Opcode },
8849     { Bad_Opcode },
8850     { Bad_Opcode },
8851     { Bad_Opcode },
8852     { PREFIX_TABLE (PREFIX_VEX_0F388C) },
8853     { Bad_Opcode },
8854     { PREFIX_TABLE (PREFIX_VEX_0F388E) },
8855     { Bad_Opcode },
8856     /* 90 */
8857     { PREFIX_TABLE (PREFIX_VEX_0F3890) },
8858     { PREFIX_TABLE (PREFIX_VEX_0F3891) },
8859     { PREFIX_TABLE (PREFIX_VEX_0F3892) },
8860     { PREFIX_TABLE (PREFIX_VEX_0F3893) },
8861     { Bad_Opcode },
8862     { Bad_Opcode },
8863     { PREFIX_TABLE (PREFIX_VEX_0F3896) },
8864     { PREFIX_TABLE (PREFIX_VEX_0F3897) },
8865     /* 98 */
8866     { PREFIX_TABLE (PREFIX_VEX_0F3898) },
8867     { PREFIX_TABLE (PREFIX_VEX_0F3899) },
8868     { PREFIX_TABLE (PREFIX_VEX_0F389A) },
8869     { PREFIX_TABLE (PREFIX_VEX_0F389B) },
8870     { PREFIX_TABLE (PREFIX_VEX_0F389C) },
8871     { PREFIX_TABLE (PREFIX_VEX_0F389D) },
8872     { PREFIX_TABLE (PREFIX_VEX_0F389E) },
8873     { PREFIX_TABLE (PREFIX_VEX_0F389F) },
8874     /* a0 */
8875     { Bad_Opcode },
8876     { Bad_Opcode },
8877     { Bad_Opcode },
8878     { Bad_Opcode },
8879     { Bad_Opcode },
8880     { Bad_Opcode },
8881     { PREFIX_TABLE (PREFIX_VEX_0F38A6) },
8882     { PREFIX_TABLE (PREFIX_VEX_0F38A7) },
8883     /* a8 */
8884     { PREFIX_TABLE (PREFIX_VEX_0F38A8) },
8885     { PREFIX_TABLE (PREFIX_VEX_0F38A9) },
8886     { PREFIX_TABLE (PREFIX_VEX_0F38AA) },
8887     { PREFIX_TABLE (PREFIX_VEX_0F38AB) },
8888     { PREFIX_TABLE (PREFIX_VEX_0F38AC) },
8889     { PREFIX_TABLE (PREFIX_VEX_0F38AD) },
8890     { PREFIX_TABLE (PREFIX_VEX_0F38AE) },
8891     { PREFIX_TABLE (PREFIX_VEX_0F38AF) },
8892     /* b0 */
8893     { Bad_Opcode },
8894     { Bad_Opcode },
8895     { Bad_Opcode },
8896     { Bad_Opcode },
8897     { Bad_Opcode },
8898     { Bad_Opcode },
8899     { PREFIX_TABLE (PREFIX_VEX_0F38B6) },
8900     { PREFIX_TABLE (PREFIX_VEX_0F38B7) },
8901     /* b8 */
8902     { PREFIX_TABLE (PREFIX_VEX_0F38B8) },
8903     { PREFIX_TABLE (PREFIX_VEX_0F38B9) },
8904     { PREFIX_TABLE (PREFIX_VEX_0F38BA) },
8905     { PREFIX_TABLE (PREFIX_VEX_0F38BB) },
8906     { PREFIX_TABLE (PREFIX_VEX_0F38BC) },
8907     { PREFIX_TABLE (PREFIX_VEX_0F38BD) },
8908     { PREFIX_TABLE (PREFIX_VEX_0F38BE) },
8909     { PREFIX_TABLE (PREFIX_VEX_0F38BF) },
8910     /* c0 */
8911     { Bad_Opcode },
8912     { Bad_Opcode },
8913     { Bad_Opcode },
8914     { Bad_Opcode },
8915     { Bad_Opcode },
8916     { Bad_Opcode },
8917     { Bad_Opcode },
8918     { Bad_Opcode },
8919     /* c8 */
8920     { Bad_Opcode },
8921     { Bad_Opcode },
8922     { Bad_Opcode },
8923     { Bad_Opcode },
8924     { Bad_Opcode },
8925     { Bad_Opcode },
8926     { Bad_Opcode },
8927     { PREFIX_TABLE (PREFIX_VEX_0F38CF) },
8928     /* d0 */
8929     { Bad_Opcode },
8930     { Bad_Opcode },
8931     { Bad_Opcode },
8932     { Bad_Opcode },
8933     { Bad_Opcode },
8934     { Bad_Opcode },
8935     { Bad_Opcode },
8936     { Bad_Opcode },
8937     /* d8 */
8938     { Bad_Opcode },
8939     { Bad_Opcode },
8940     { Bad_Opcode },
8941     { PREFIX_TABLE (PREFIX_VEX_0F38DB) },
8942     { PREFIX_TABLE (PREFIX_VEX_0F38DC) },
8943     { PREFIX_TABLE (PREFIX_VEX_0F38DD) },
8944     { PREFIX_TABLE (PREFIX_VEX_0F38DE) },
8945     { PREFIX_TABLE (PREFIX_VEX_0F38DF) },
8946     /* e0 */
8947     { Bad_Opcode },
8948     { Bad_Opcode },
8949     { Bad_Opcode },
8950     { Bad_Opcode },
8951     { Bad_Opcode },
8952     { Bad_Opcode },
8953     { Bad_Opcode },
8954     { Bad_Opcode },
8955     /* e8 */
8956     { Bad_Opcode },
8957     { Bad_Opcode },
8958     { Bad_Opcode },
8959     { Bad_Opcode },
8960     { Bad_Opcode },
8961     { Bad_Opcode },
8962     { Bad_Opcode },
8963     { Bad_Opcode },
8964     /* f0 */
8965     { Bad_Opcode },
8966     { Bad_Opcode },
8967     { PREFIX_TABLE (PREFIX_VEX_0F38F2) },
8968     { REG_TABLE (REG_VEX_0F38F3) },
8969     { Bad_Opcode },
8970     { PREFIX_TABLE (PREFIX_VEX_0F38F5) },
8971     { PREFIX_TABLE (PREFIX_VEX_0F38F6) },
8972     { PREFIX_TABLE (PREFIX_VEX_0F38F7) },
8973     /* f8 */
8974     { Bad_Opcode },
8975     { Bad_Opcode },
8976     { Bad_Opcode },
8977     { Bad_Opcode },
8978     { Bad_Opcode },
8979     { Bad_Opcode },
8980     { Bad_Opcode },
8981     { Bad_Opcode },
8982   },
8983   /* VEX_0F3A */
8984   {
8985     /* 00 */
8986     { PREFIX_TABLE (PREFIX_VEX_0F3A00) },
8987     { PREFIX_TABLE (PREFIX_VEX_0F3A01) },
8988     { PREFIX_TABLE (PREFIX_VEX_0F3A02) },
8989     { Bad_Opcode },
8990     { PREFIX_TABLE (PREFIX_VEX_0F3A04) },
8991     { PREFIX_TABLE (PREFIX_VEX_0F3A05) },
8992     { PREFIX_TABLE (PREFIX_VEX_0F3A06) },
8993     { Bad_Opcode },
8994     /* 08 */
8995     { PREFIX_TABLE (PREFIX_VEX_0F3A08) },
8996     { PREFIX_TABLE (PREFIX_VEX_0F3A09) },
8997     { PREFIX_TABLE (PREFIX_VEX_0F3A0A) },
8998     { PREFIX_TABLE (PREFIX_VEX_0F3A0B) },
8999     { PREFIX_TABLE (PREFIX_VEX_0F3A0C) },
9000     { PREFIX_TABLE (PREFIX_VEX_0F3A0D) },
9001     { PREFIX_TABLE (PREFIX_VEX_0F3A0E) },
9002     { PREFIX_TABLE (PREFIX_VEX_0F3A0F) },
9003     /* 10 */
9004     { Bad_Opcode },
9005     { Bad_Opcode },
9006     { Bad_Opcode },
9007     { Bad_Opcode },
9008     { PREFIX_TABLE (PREFIX_VEX_0F3A14) },
9009     { PREFIX_TABLE (PREFIX_VEX_0F3A15) },
9010     { PREFIX_TABLE (PREFIX_VEX_0F3A16) },
9011     { PREFIX_TABLE (PREFIX_VEX_0F3A17) },
9012     /* 18 */
9013     { PREFIX_TABLE (PREFIX_VEX_0F3A18) },
9014     { PREFIX_TABLE (PREFIX_VEX_0F3A19) },
9015     { Bad_Opcode },
9016     { Bad_Opcode },
9017     { Bad_Opcode },
9018     { PREFIX_TABLE (PREFIX_VEX_0F3A1D) },
9019     { Bad_Opcode },
9020     { Bad_Opcode },
9021     /* 20 */
9022     { PREFIX_TABLE (PREFIX_VEX_0F3A20) },
9023     { PREFIX_TABLE (PREFIX_VEX_0F3A21) },
9024     { PREFIX_TABLE (PREFIX_VEX_0F3A22) },
9025     { Bad_Opcode },
9026     { Bad_Opcode },
9027     { Bad_Opcode },
9028     { Bad_Opcode },
9029     { Bad_Opcode },
9030     /* 28 */
9031     { Bad_Opcode },
9032     { Bad_Opcode },
9033     { Bad_Opcode },
9034     { Bad_Opcode },
9035     { Bad_Opcode },
9036     { Bad_Opcode },
9037     { Bad_Opcode },
9038     { Bad_Opcode },
9039     /* 30 */
9040     { PREFIX_TABLE (PREFIX_VEX_0F3A30) },
9041     { PREFIX_TABLE (PREFIX_VEX_0F3A31) },
9042     { PREFIX_TABLE (PREFIX_VEX_0F3A32) },
9043     { PREFIX_TABLE (PREFIX_VEX_0F3A33) },
9044     { Bad_Opcode },
9045     { Bad_Opcode },
9046     { Bad_Opcode },
9047     { Bad_Opcode },
9048     /* 38 */
9049     { PREFIX_TABLE (PREFIX_VEX_0F3A38) },
9050     { PREFIX_TABLE (PREFIX_VEX_0F3A39) },
9051     { Bad_Opcode },
9052     { Bad_Opcode },
9053     { Bad_Opcode },
9054     { Bad_Opcode },
9055     { Bad_Opcode },
9056     { Bad_Opcode },
9057     /* 40 */
9058     { PREFIX_TABLE (PREFIX_VEX_0F3A40) },
9059     { PREFIX_TABLE (PREFIX_VEX_0F3A41) },
9060     { PREFIX_TABLE (PREFIX_VEX_0F3A42) },
9061     { Bad_Opcode },
9062     { PREFIX_TABLE (PREFIX_VEX_0F3A44) },
9063     { Bad_Opcode },
9064     { PREFIX_TABLE (PREFIX_VEX_0F3A46) },
9065     { Bad_Opcode },
9066     /* 48 */
9067     { PREFIX_TABLE (PREFIX_VEX_0F3A48) },
9068     { PREFIX_TABLE (PREFIX_VEX_0F3A49) },
9069     { PREFIX_TABLE (PREFIX_VEX_0F3A4A) },
9070     { PREFIX_TABLE (PREFIX_VEX_0F3A4B) },
9071     { PREFIX_TABLE (PREFIX_VEX_0F3A4C) },
9072     { Bad_Opcode },
9073     { Bad_Opcode },
9074     { Bad_Opcode },
9075     /* 50 */
9076     { Bad_Opcode },
9077     { Bad_Opcode },
9078     { Bad_Opcode },
9079     { Bad_Opcode },
9080     { Bad_Opcode },
9081     { Bad_Opcode },
9082     { Bad_Opcode },
9083     { Bad_Opcode },
9084     /* 58 */
9085     { Bad_Opcode },
9086     { Bad_Opcode },
9087     { Bad_Opcode },
9088     { Bad_Opcode },
9089     { PREFIX_TABLE (PREFIX_VEX_0F3A5C) },
9090     { PREFIX_TABLE (PREFIX_VEX_0F3A5D) },
9091     { PREFIX_TABLE (PREFIX_VEX_0F3A5E) },
9092     { PREFIX_TABLE (PREFIX_VEX_0F3A5F) },
9093     /* 60 */
9094     { PREFIX_TABLE (PREFIX_VEX_0F3A60) },
9095     { PREFIX_TABLE (PREFIX_VEX_0F3A61) },
9096     { PREFIX_TABLE (PREFIX_VEX_0F3A62) },
9097     { PREFIX_TABLE (PREFIX_VEX_0F3A63) },
9098     { Bad_Opcode },
9099     { Bad_Opcode },
9100     { Bad_Opcode },
9101     { Bad_Opcode },
9102     /* 68 */
9103     { PREFIX_TABLE (PREFIX_VEX_0F3A68) },
9104     { PREFIX_TABLE (PREFIX_VEX_0F3A69) },
9105     { PREFIX_TABLE (PREFIX_VEX_0F3A6A) },
9106     { PREFIX_TABLE (PREFIX_VEX_0F3A6B) },
9107     { PREFIX_TABLE (PREFIX_VEX_0F3A6C) },
9108     { PREFIX_TABLE (PREFIX_VEX_0F3A6D) },
9109     { PREFIX_TABLE (PREFIX_VEX_0F3A6E) },
9110     { PREFIX_TABLE (PREFIX_VEX_0F3A6F) },
9111     /* 70 */
9112     { Bad_Opcode },
9113     { Bad_Opcode },
9114     { Bad_Opcode },
9115     { Bad_Opcode },
9116     { Bad_Opcode },
9117     { Bad_Opcode },
9118     { Bad_Opcode },
9119     { Bad_Opcode },
9120     /* 78 */
9121     { PREFIX_TABLE (PREFIX_VEX_0F3A78) },
9122     { PREFIX_TABLE (PREFIX_VEX_0F3A79) },
9123     { PREFIX_TABLE (PREFIX_VEX_0F3A7A) },
9124     { PREFIX_TABLE (PREFIX_VEX_0F3A7B) },
9125     { PREFIX_TABLE (PREFIX_VEX_0F3A7C) },
9126     { PREFIX_TABLE (PREFIX_VEX_0F3A7D) },
9127     { PREFIX_TABLE (PREFIX_VEX_0F3A7E) },
9128     { PREFIX_TABLE (PREFIX_VEX_0F3A7F) },
9129     /* 80 */
9130     { Bad_Opcode },
9131     { Bad_Opcode },
9132     { Bad_Opcode },
9133     { Bad_Opcode },
9134     { Bad_Opcode },
9135     { Bad_Opcode },
9136     { Bad_Opcode },
9137     { Bad_Opcode },
9138     /* 88 */
9139     { Bad_Opcode },
9140     { Bad_Opcode },
9141     { Bad_Opcode },
9142     { Bad_Opcode },
9143     { Bad_Opcode },
9144     { Bad_Opcode },
9145     { Bad_Opcode },
9146     { Bad_Opcode },
9147     /* 90 */
9148     { Bad_Opcode },
9149     { Bad_Opcode },
9150     { Bad_Opcode },
9151     { Bad_Opcode },
9152     { Bad_Opcode },
9153     { Bad_Opcode },
9154     { Bad_Opcode },
9155     { Bad_Opcode },
9156     /* 98 */
9157     { Bad_Opcode },
9158     { Bad_Opcode },
9159     { Bad_Opcode },
9160     { Bad_Opcode },
9161     { Bad_Opcode },
9162     { Bad_Opcode },
9163     { Bad_Opcode },
9164     { Bad_Opcode },
9165     /* a0 */
9166     { Bad_Opcode },
9167     { Bad_Opcode },
9168     { Bad_Opcode },
9169     { Bad_Opcode },
9170     { Bad_Opcode },
9171     { Bad_Opcode },
9172     { Bad_Opcode },
9173     { Bad_Opcode },
9174     /* a8 */
9175     { Bad_Opcode },
9176     { Bad_Opcode },
9177     { Bad_Opcode },
9178     { Bad_Opcode },
9179     { Bad_Opcode },
9180     { Bad_Opcode },
9181     { Bad_Opcode },
9182     { Bad_Opcode },
9183     /* b0 */
9184     { Bad_Opcode },
9185     { Bad_Opcode },
9186     { Bad_Opcode },
9187     { Bad_Opcode },
9188     { Bad_Opcode },
9189     { Bad_Opcode },
9190     { Bad_Opcode },
9191     { Bad_Opcode },
9192     /* b8 */
9193     { Bad_Opcode },
9194     { Bad_Opcode },
9195     { Bad_Opcode },
9196     { Bad_Opcode },
9197     { Bad_Opcode },
9198     { Bad_Opcode },
9199     { Bad_Opcode },
9200     { Bad_Opcode },
9201     /* c0 */
9202     { Bad_Opcode },
9203     { Bad_Opcode },
9204     { Bad_Opcode },
9205     { Bad_Opcode },
9206     { Bad_Opcode },
9207     { Bad_Opcode },
9208     { Bad_Opcode },
9209     { Bad_Opcode },
9210     /* c8 */
9211     { Bad_Opcode },
9212     { Bad_Opcode },
9213     { Bad_Opcode },
9214     { Bad_Opcode },
9215     { Bad_Opcode },
9216     { Bad_Opcode },
9217     { PREFIX_TABLE(PREFIX_VEX_0F3ACE) },
9218     { PREFIX_TABLE(PREFIX_VEX_0F3ACF) },
9219     /* d0 */
9220     { Bad_Opcode },
9221     { Bad_Opcode },
9222     { Bad_Opcode },
9223     { Bad_Opcode },
9224     { Bad_Opcode },
9225     { Bad_Opcode },
9226     { Bad_Opcode },
9227     { Bad_Opcode },
9228     /* d8 */
9229     { Bad_Opcode },
9230     { Bad_Opcode },
9231     { Bad_Opcode },
9232     { Bad_Opcode },
9233     { Bad_Opcode },
9234     { Bad_Opcode },
9235     { Bad_Opcode },
9236     { PREFIX_TABLE (PREFIX_VEX_0F3ADF) },
9237     /* e0 */
9238     { Bad_Opcode },
9239     { Bad_Opcode },
9240     { Bad_Opcode },
9241     { Bad_Opcode },
9242     { Bad_Opcode },
9243     { Bad_Opcode },
9244     { Bad_Opcode },
9245     { Bad_Opcode },
9246     /* e8 */
9247     { Bad_Opcode },
9248     { Bad_Opcode },
9249     { Bad_Opcode },
9250     { Bad_Opcode },
9251     { Bad_Opcode },
9252     { Bad_Opcode },
9253     { Bad_Opcode },
9254     { Bad_Opcode },
9255     /* f0 */
9256     { PREFIX_TABLE (PREFIX_VEX_0F3AF0) },
9257     { Bad_Opcode },
9258     { Bad_Opcode },
9259     { Bad_Opcode },
9260     { Bad_Opcode },
9261     { Bad_Opcode },
9262     { Bad_Opcode },
9263     { Bad_Opcode },
9264     /* f8 */
9265     { Bad_Opcode },
9266     { Bad_Opcode },
9267     { Bad_Opcode },
9268     { Bad_Opcode },
9269     { Bad_Opcode },
9270     { Bad_Opcode },
9271     { Bad_Opcode },
9272     { Bad_Opcode },
9273   },
9274 };
9275
9276 #include "i386-dis-evex.h"
9277
9278 static const struct dis386 vex_len_table[][2] = {
9279   /* VEX_LEN_0F12_P_0_M_0 / VEX_LEN_0F12_P_2_M_0 */
9280   {
9281     { "vmovlpX",        { XM, Vex128, EXq }, 0 },
9282   },
9283
9284   /* VEX_LEN_0F12_P_0_M_1 */
9285   {
9286     { "vmovhlps",       { XM, Vex128, EXq }, 0 },
9287   },
9288
9289   /* VEX_LEN_0F13_M_0 */
9290   {
9291     { "vmovlpX",        { EXq, XM }, PREFIX_OPCODE },
9292   },
9293
9294   /* VEX_LEN_0F16_P_0_M_0 / VEX_LEN_0F16_P_2_M_0 */
9295   {
9296     { "vmovhpX",        { XM, Vex128, EXq }, 0 },
9297   },
9298
9299   /* VEX_LEN_0F16_P_0_M_1 */
9300   {
9301     { "vmovlhps",       { XM, Vex128, EXq }, 0 },
9302   },
9303
9304   /* VEX_LEN_0F17_M_0 */
9305   {
9306     { "vmovhpX",        { EXq, XM }, PREFIX_OPCODE },
9307   },
9308
9309   /* VEX_LEN_0F41_P_0 */
9310   {
9311     { Bad_Opcode },
9312     { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) },
9313   },
9314   /* VEX_LEN_0F41_P_2 */
9315   {
9316     { Bad_Opcode },
9317     { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) },
9318   },
9319   /* VEX_LEN_0F42_P_0 */
9320   {
9321     { Bad_Opcode },
9322     { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) },
9323   },
9324   /* VEX_LEN_0F42_P_2 */
9325   {
9326     { Bad_Opcode },
9327     { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) },
9328   },
9329   /* VEX_LEN_0F44_P_0 */
9330   {
9331     { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) },
9332   },
9333   /* VEX_LEN_0F44_P_2 */
9334   {
9335     { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) },
9336   },
9337   /* VEX_LEN_0F45_P_0 */
9338   {
9339     { Bad_Opcode },
9340     { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) },
9341   },
9342   /* VEX_LEN_0F45_P_2 */
9343   {
9344     { Bad_Opcode },
9345     { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) },
9346   },
9347   /* VEX_LEN_0F46_P_0 */
9348   {
9349     { Bad_Opcode },
9350     { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) },
9351   },
9352   /* VEX_LEN_0F46_P_2 */
9353   {
9354     { Bad_Opcode },
9355     { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) },
9356   },
9357   /* VEX_LEN_0F47_P_0 */
9358   {
9359     { Bad_Opcode },
9360     { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) },
9361   },
9362   /* VEX_LEN_0F47_P_2 */
9363   {
9364     { Bad_Opcode },
9365     { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) },
9366   },
9367   /* VEX_LEN_0F4A_P_0 */
9368   {
9369     { Bad_Opcode },
9370     { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) },
9371   },
9372   /* VEX_LEN_0F4A_P_2 */
9373   {
9374     { Bad_Opcode },
9375     { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) },
9376   },
9377   /* VEX_LEN_0F4B_P_0 */
9378   {
9379     { Bad_Opcode },
9380     { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) },
9381   },
9382   /* VEX_LEN_0F4B_P_2 */
9383   {
9384     { Bad_Opcode },
9385     { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) },
9386   },
9387
9388   /* VEX_LEN_0F6E_P_2 */
9389   {
9390     { "vmovK",          { XMScalar, Edq }, 0 },
9391   },
9392
9393   /* VEX_LEN_0F77_P_1 */
9394   {
9395     { "vzeroupper",     { XX }, 0 },
9396     { "vzeroall",       { XX }, 0 },
9397   },
9398
9399   /* VEX_LEN_0F7E_P_1 */
9400   {
9401     { "vmovq",          { XMScalar, EXxmm_mq }, 0 },
9402   },
9403
9404   /* VEX_LEN_0F7E_P_2 */
9405   {
9406     { "vmovK",          { Edq, XMScalar }, 0 },
9407   },
9408
9409   /* VEX_LEN_0F90_P_0 */
9410   {
9411     { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) },
9412   },
9413
9414   /* VEX_LEN_0F90_P_2 */
9415   {
9416     { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) },
9417   },
9418
9419   /* VEX_LEN_0F91_P_0 */
9420   {
9421     { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) },
9422   },
9423
9424   /* VEX_LEN_0F91_P_2 */
9425   {
9426     { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) },
9427   },
9428
9429   /* VEX_LEN_0F92_P_0 */
9430   {
9431     { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) },
9432   },
9433
9434   /* VEX_LEN_0F92_P_2 */
9435   {
9436     { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) },
9437   },
9438
9439   /* VEX_LEN_0F92_P_3 */
9440   {
9441     { MOD_TABLE (MOD_VEX_0F92_P_3_LEN_0) },
9442   },
9443
9444   /* VEX_LEN_0F93_P_0 */
9445   {
9446     { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) },
9447   },
9448
9449   /* VEX_LEN_0F93_P_2 */
9450   {
9451     { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) },
9452   },
9453
9454   /* VEX_LEN_0F93_P_3 */
9455   {
9456     { MOD_TABLE (MOD_VEX_0F93_P_3_LEN_0) },
9457   },
9458
9459   /* VEX_LEN_0F98_P_0 */
9460   {
9461     { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) },
9462   },
9463
9464   /* VEX_LEN_0F98_P_2 */
9465   {
9466     { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) },
9467   },
9468
9469   /* VEX_LEN_0F99_P_0 */
9470   {
9471     { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) },
9472   },
9473
9474   /* VEX_LEN_0F99_P_2 */
9475   {
9476     { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0) },
9477   },
9478
9479   /* VEX_LEN_0FAE_R_2_M_0 */
9480   {
9481     { "vldmxcsr",       { Md }, 0 },
9482   },
9483
9484   /* VEX_LEN_0FAE_R_3_M_0 */
9485   {
9486     { "vstmxcsr",       { Md }, 0 },
9487   },
9488
9489   /* VEX_LEN_0FC4_P_2 */
9490   {
9491     { "vpinsrw",        { XM, Vex128, Edqw, Ib }, 0 },
9492   },
9493
9494   /* VEX_LEN_0FC5_P_2 */
9495   {
9496     { "vpextrw",        { Gdq, XS, Ib }, 0 },
9497   },
9498
9499   /* VEX_LEN_0FD6_P_2 */
9500   {
9501     { "vmovq",          { EXqScalarS, XMScalar }, 0 },
9502   },
9503
9504   /* VEX_LEN_0FF7_P_2 */
9505   {
9506     { "vmaskmovdqu",    { XM, XS }, 0 },
9507   },
9508
9509   /* VEX_LEN_0F3816_P_2 */
9510   {
9511     { Bad_Opcode },
9512     { VEX_W_TABLE (VEX_W_0F3816_P_2) },
9513   },
9514
9515   /* VEX_LEN_0F3819_P_2 */
9516   {
9517     { Bad_Opcode },
9518     { VEX_W_TABLE (VEX_W_0F3819_P_2) },
9519   },
9520
9521   /* VEX_LEN_0F381A_P_2_M_0 */
9522   {
9523     { Bad_Opcode },
9524     { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) },
9525   },
9526
9527   /* VEX_LEN_0F3836_P_2 */
9528   {
9529     { Bad_Opcode },
9530     { VEX_W_TABLE (VEX_W_0F3836_P_2) },
9531   },
9532
9533   /* VEX_LEN_0F3841_P_2 */
9534   {
9535     { "vphminposuw",    { XM, EXx }, 0 },
9536   },
9537
9538   /* VEX_LEN_0F385A_P_2_M_0 */
9539   {
9540     { Bad_Opcode },
9541     { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) },
9542   },
9543
9544   /* VEX_LEN_0F38DB_P_2 */
9545   {
9546     { "vaesimc",        { XM, EXx }, 0 },
9547   },
9548
9549   /* VEX_LEN_0F38F2_P_0 */
9550   {
9551     { "andnS",          { Gdq, VexGdq, Edq }, 0 },
9552   },
9553
9554   /* VEX_LEN_0F38F3_R_1_P_0 */
9555   {
9556     { "blsrS",          { VexGdq, Edq }, 0 },
9557   },
9558
9559   /* VEX_LEN_0F38F3_R_2_P_0 */
9560   {
9561     { "blsmskS",        { VexGdq, Edq }, 0 },
9562   },
9563
9564   /* VEX_LEN_0F38F3_R_3_P_0 */
9565   {
9566     { "blsiS",          { VexGdq, Edq }, 0 },
9567   },
9568
9569   /* VEX_LEN_0F38F5_P_0 */
9570   {
9571     { "bzhiS",          { Gdq, Edq, VexGdq }, 0 },
9572   },
9573
9574   /* VEX_LEN_0F38F5_P_1 */
9575   {
9576     { "pextS",          { Gdq, VexGdq, Edq }, 0 },
9577   },
9578
9579   /* VEX_LEN_0F38F5_P_3 */
9580   {
9581     { "pdepS",          { Gdq, VexGdq, Edq }, 0 },
9582   },
9583
9584   /* VEX_LEN_0F38F6_P_3 */
9585   {
9586     { "mulxS",          { Gdq, VexGdq, Edq }, 0 },
9587   },
9588
9589   /* VEX_LEN_0F38F7_P_0 */
9590   {
9591     { "bextrS",         { Gdq, Edq, VexGdq }, 0 },
9592   },
9593
9594   /* VEX_LEN_0F38F7_P_1 */
9595   {
9596     { "sarxS",          { Gdq, Edq, VexGdq }, 0 },
9597   },
9598
9599   /* VEX_LEN_0F38F7_P_2 */
9600   {
9601     { "shlxS",          { Gdq, Edq, VexGdq }, 0 },
9602   },
9603
9604   /* VEX_LEN_0F38F7_P_3 */
9605   {
9606     { "shrxS",          { Gdq, Edq, VexGdq }, 0 },
9607   },
9608
9609   /* VEX_LEN_0F3A00_P_2 */
9610   {
9611     { Bad_Opcode },
9612     { VEX_W_TABLE (VEX_W_0F3A00_P_2) },
9613   },
9614
9615   /* VEX_LEN_0F3A01_P_2 */
9616   {
9617     { Bad_Opcode },
9618     { VEX_W_TABLE (VEX_W_0F3A01_P_2) },
9619   },
9620
9621   /* VEX_LEN_0F3A06_P_2 */
9622   {
9623     { Bad_Opcode },
9624     { VEX_W_TABLE (VEX_W_0F3A06_P_2) },
9625   },
9626
9627   /* VEX_LEN_0F3A14_P_2 */
9628   {
9629     { "vpextrb",        { Edqb, XM, Ib }, 0 },
9630   },
9631
9632   /* VEX_LEN_0F3A15_P_2 */
9633   {
9634     { "vpextrw",        { Edqw, XM, Ib }, 0 },
9635   },
9636
9637   /* VEX_LEN_0F3A16_P_2  */
9638   {
9639     { "vpextrK",        { Edq, XM, Ib }, 0 },
9640   },
9641
9642   /* VEX_LEN_0F3A17_P_2 */
9643   {
9644     { "vextractps",     { Edqd, XM, Ib }, 0 },
9645   },
9646
9647   /* VEX_LEN_0F3A18_P_2 */
9648   {
9649     { Bad_Opcode },
9650     { VEX_W_TABLE (VEX_W_0F3A18_P_2) },
9651   },
9652
9653   /* VEX_LEN_0F3A19_P_2 */
9654   {
9655     { Bad_Opcode },
9656     { VEX_W_TABLE (VEX_W_0F3A19_P_2) },
9657   },
9658
9659   /* VEX_LEN_0F3A20_P_2 */
9660   {
9661     { "vpinsrb",        { XM, Vex128, Edqb, Ib }, 0 },
9662   },
9663
9664   /* VEX_LEN_0F3A21_P_2 */
9665   {
9666     { "vinsertps",      { XM, Vex128, EXd, Ib }, 0 },
9667   },
9668
9669   /* VEX_LEN_0F3A22_P_2 */
9670   {
9671     { "vpinsrK",        { XM, Vex128, Edq, Ib }, 0 },
9672   },
9673
9674   /* VEX_LEN_0F3A30_P_2 */
9675   {
9676     { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) },
9677   },
9678
9679   /* VEX_LEN_0F3A31_P_2 */
9680   {
9681     { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0) },
9682   },
9683
9684   /* VEX_LEN_0F3A32_P_2 */
9685   {
9686     { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) },
9687   },
9688
9689   /* VEX_LEN_0F3A33_P_2 */
9690   {
9691     { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0) },
9692   },
9693
9694   /* VEX_LEN_0F3A38_P_2 */
9695   {
9696     { Bad_Opcode },
9697     { VEX_W_TABLE (VEX_W_0F3A38_P_2) },
9698   },
9699
9700   /* VEX_LEN_0F3A39_P_2 */
9701   {
9702     { Bad_Opcode },
9703     { VEX_W_TABLE (VEX_W_0F3A39_P_2) },
9704   },
9705
9706   /* VEX_LEN_0F3A41_P_2 */
9707   {
9708     { "vdppd",          { XM, Vex128, EXx, Ib }, 0 },
9709   },
9710
9711   /* VEX_LEN_0F3A46_P_2 */
9712   {
9713     { Bad_Opcode },
9714     { VEX_W_TABLE (VEX_W_0F3A46_P_2) },
9715   },
9716
9717   /* VEX_LEN_0F3A60_P_2 */
9718   {
9719     { "vpcmpestrm",     { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 },
9720   },
9721
9722   /* VEX_LEN_0F3A61_P_2 */
9723   {
9724     { "vpcmpestri",     { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 },
9725   },
9726
9727   /* VEX_LEN_0F3A62_P_2 */
9728   {
9729     { "vpcmpistrm",     { XM, EXx, Ib }, 0 },
9730   },
9731
9732   /* VEX_LEN_0F3A63_P_2 */
9733   {
9734     { "vpcmpistri",     { XM, EXx, Ib }, 0 },
9735   },
9736
9737   /* VEX_LEN_0F3A6A_P_2 */
9738   {
9739     { "vfmaddss",       { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
9740   },
9741
9742   /* VEX_LEN_0F3A6B_P_2 */
9743   {
9744     { "vfmaddsd",       { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
9745   },
9746
9747   /* VEX_LEN_0F3A6E_P_2 */
9748   {
9749     { "vfmsubss",       { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
9750   },
9751
9752   /* VEX_LEN_0F3A6F_P_2 */
9753   {
9754     { "vfmsubsd",       { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
9755   },
9756
9757   /* VEX_LEN_0F3A7A_P_2 */
9758   {
9759     { "vfnmaddss",      { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
9760   },
9761
9762   /* VEX_LEN_0F3A7B_P_2 */
9763   {
9764     { "vfnmaddsd",      { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
9765   },
9766
9767   /* VEX_LEN_0F3A7E_P_2 */
9768   {
9769     { "vfnmsubss",      { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
9770   },
9771
9772   /* VEX_LEN_0F3A7F_P_2 */
9773   {
9774     { "vfnmsubsd",      { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
9775   },
9776
9777   /* VEX_LEN_0F3ADF_P_2 */
9778   {
9779     { "vaeskeygenassist", { XM, EXx, Ib }, 0 },
9780   },
9781
9782   /* VEX_LEN_0F3AF0_P_3 */
9783   {
9784     { "rorxS",          { Gdq, Edq, Ib }, 0 },
9785   },
9786
9787   /* VEX_LEN_0FXOP_08_CC */
9788   {
9789      { "vpcomb",        { XM, Vex128, EXx, VPCOM }, 0 },
9790   },
9791
9792   /* VEX_LEN_0FXOP_08_CD */
9793   {
9794      { "vpcomw",        { XM, Vex128, EXx, VPCOM }, 0 },
9795   },
9796
9797   /* VEX_LEN_0FXOP_08_CE */
9798   {
9799      { "vpcomd",        { XM, Vex128, EXx, VPCOM }, 0 },
9800   },
9801
9802   /* VEX_LEN_0FXOP_08_CF */
9803   {
9804      { "vpcomq",        { XM, Vex128, EXx, VPCOM }, 0 },
9805   },
9806
9807   /* VEX_LEN_0FXOP_08_EC */
9808   {
9809      { "vpcomub",       { XM, Vex128, EXx, VPCOM }, 0 },
9810   },
9811
9812   /* VEX_LEN_0FXOP_08_ED */
9813   {
9814      { "vpcomuw",       { XM, Vex128, EXx, VPCOM }, 0 },
9815   },
9816
9817   /* VEX_LEN_0FXOP_08_EE */
9818   {
9819      { "vpcomud",       { XM, Vex128, EXx, VPCOM }, 0 },
9820   },
9821
9822   /* VEX_LEN_0FXOP_08_EF */
9823   {
9824      { "vpcomuq",       { XM, Vex128, EXx, VPCOM }, 0 },
9825   },
9826
9827   /* VEX_LEN_0FXOP_09_80 */
9828   {
9829     { "vfrczps",        { XM, EXxmm }, 0 },
9830     { "vfrczps",        { XM, EXymmq }, 0 },
9831   },
9832
9833   /* VEX_LEN_0FXOP_09_81 */
9834   {
9835     { "vfrczpd",        { XM, EXxmm }, 0 },
9836     { "vfrczpd",        { XM, EXymmq }, 0 },
9837   },
9838 };
9839
9840 #include "i386-dis-evex-len.h"
9841
9842 static const struct dis386 vex_w_table[][2] = {
9843   {
9844     /* VEX_W_0F41_P_0_LEN_1 */
9845     { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1) },
9846     { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1) },
9847   },
9848   {
9849     /* VEX_W_0F41_P_2_LEN_1 */
9850     { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1) },
9851     { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1) }
9852   },
9853   {
9854     /* VEX_W_0F42_P_0_LEN_1 */
9855     { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1) },
9856     { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1) },
9857   },
9858   {
9859     /* VEX_W_0F42_P_2_LEN_1 */
9860     { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1) },
9861     { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1) },
9862   },
9863   {
9864     /* VEX_W_0F44_P_0_LEN_0 */
9865     { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1) },
9866     { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1) },
9867   },
9868   {
9869     /* VEX_W_0F44_P_2_LEN_0 */
9870     { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1) },
9871     { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1) },
9872   },
9873   {
9874     /* VEX_W_0F45_P_0_LEN_1 */
9875     { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1) },
9876     { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1) },
9877   },
9878   {
9879     /* VEX_W_0F45_P_2_LEN_1 */
9880     { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1) },
9881     { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1) },
9882   },
9883   {
9884     /* VEX_W_0F46_P_0_LEN_1 */
9885     { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1) },
9886     { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1) },
9887   },
9888   {
9889     /* VEX_W_0F46_P_2_LEN_1 */
9890     { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1) },
9891     { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1) },
9892   },
9893   {
9894     /* VEX_W_0F47_P_0_LEN_1 */
9895     { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1) },
9896     { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1) },
9897   },
9898   {
9899     /* VEX_W_0F47_P_2_LEN_1 */
9900     { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1) },
9901     { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1) },
9902   },
9903   {
9904     /* VEX_W_0F4A_P_0_LEN_1 */
9905     { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1) },
9906     { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1) },
9907   },
9908   {
9909     /* VEX_W_0F4A_P_2_LEN_1 */
9910     { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1) },
9911     { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1) },
9912   },
9913   {
9914     /* VEX_W_0F4B_P_0_LEN_1 */
9915     { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1) },
9916     { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1) },
9917   },
9918   {
9919     /* VEX_W_0F4B_P_2_LEN_1 */
9920     { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1) },
9921   },
9922   {
9923     /* VEX_W_0F90_P_0_LEN_0 */
9924     { "kmovw",          { MaskG, MaskE }, 0 },
9925     { "kmovq",          { MaskG, MaskE }, 0 },
9926   },
9927   {
9928     /* VEX_W_0F90_P_2_LEN_0 */
9929     { "kmovb",          { MaskG, MaskBDE }, 0 },
9930     { "kmovd",          { MaskG, MaskBDE }, 0 },
9931   },
9932   {
9933     /* VEX_W_0F91_P_0_LEN_0 */
9934     { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0) },
9935     { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0) },
9936   },
9937   {
9938     /* VEX_W_0F91_P_2_LEN_0 */
9939     { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0) },
9940     { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0) },
9941   },
9942   {
9943     /* VEX_W_0F92_P_0_LEN_0 */
9944     { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0) },
9945   },
9946   {
9947     /* VEX_W_0F92_P_2_LEN_0 */
9948     { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0) },
9949   },
9950   {
9951     /* VEX_W_0F93_P_0_LEN_0 */
9952     { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0) },
9953   },
9954   {
9955     /* VEX_W_0F93_P_2_LEN_0 */
9956     { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0) },
9957   },
9958   {
9959     /* VEX_W_0F98_P_0_LEN_0 */
9960     { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0) },
9961     { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0) },
9962   },
9963   {
9964     /* VEX_W_0F98_P_2_LEN_0 */
9965     { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0) },
9966     { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0) },
9967   },
9968   {
9969     /* VEX_W_0F99_P_0_LEN_0 */
9970     { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0) },
9971     { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0) },
9972   },
9973   {
9974     /* VEX_W_0F99_P_2_LEN_0 */
9975     { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0) },
9976     { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0) },
9977   },
9978   {
9979     /* VEX_W_0F380C_P_2  */
9980     { "vpermilps",      { XM, Vex, EXx }, 0 },
9981   },
9982   {
9983     /* VEX_W_0F380D_P_2  */
9984     { "vpermilpd",      { XM, Vex, EXx }, 0 },
9985   },
9986   {
9987     /* VEX_W_0F380E_P_2  */
9988     { "vtestps",        { XM, EXx }, 0 },
9989   },
9990   {
9991     /* VEX_W_0F380F_P_2  */
9992     { "vtestpd",        { XM, EXx }, 0 },
9993   },
9994   {
9995     /* VEX_W_0F3816_P_2  */
9996     { "vpermps",        { XM, Vex, EXx }, 0 },
9997   },
9998   {
9999     /* VEX_W_0F3818_P_2 */
10000     { "vbroadcastss",   { XM, EXxmm_md }, 0 },
10001   },
10002   {
10003     /* VEX_W_0F3819_P_2 */
10004     { "vbroadcastsd",   { XM, EXxmm_mq }, 0 },
10005   },
10006   {
10007     /* VEX_W_0F381A_P_2_M_0 */
10008     { "vbroadcastf128", { XM, Mxmm }, 0 },
10009   },
10010   {
10011     /* VEX_W_0F382C_P_2_M_0 */
10012     { "vmaskmovps",     { XM, Vex, Mx }, 0 },
10013   },
10014   {
10015     /* VEX_W_0F382D_P_2_M_0 */
10016     { "vmaskmovpd",     { XM, Vex, Mx }, 0 },
10017   },
10018   {
10019     /* VEX_W_0F382E_P_2_M_0 */
10020     { "vmaskmovps",     { Mx, Vex, XM }, 0 },
10021   },
10022   {
10023     /* VEX_W_0F382F_P_2_M_0 */
10024     { "vmaskmovpd",     { Mx, Vex, XM }, 0 },
10025   },
10026   {
10027     /* VEX_W_0F3836_P_2  */
10028     { "vpermd",         { XM, Vex, EXx }, 0 },
10029   },
10030   {
10031     /* VEX_W_0F3846_P_2 */
10032     { "vpsravd",        { XM, Vex, EXx }, 0 },
10033   },
10034   {
10035     /* VEX_W_0F3858_P_2 */
10036     { "vpbroadcastd", { XM, EXxmm_md }, 0 },
10037   },
10038   {
10039     /* VEX_W_0F3859_P_2 */
10040     { "vpbroadcastq",   { XM, EXxmm_mq }, 0 },
10041   },
10042   {
10043     /* VEX_W_0F385A_P_2_M_0 */
10044     { "vbroadcasti128", { XM, Mxmm }, 0 },
10045   },
10046   {
10047     /* VEX_W_0F3878_P_2 */
10048     { "vpbroadcastb",   { XM, EXxmm_mb }, 0 },
10049   },
10050   {
10051     /* VEX_W_0F3879_P_2 */
10052     { "vpbroadcastw",   { XM, EXxmm_mw }, 0 },
10053   },
10054   {
10055     /* VEX_W_0F38CF_P_2 */
10056     { "vgf2p8mulb", { XM, Vex, EXx }, 0 },
10057   },
10058   {
10059     /* VEX_W_0F3A00_P_2 */
10060     { Bad_Opcode },
10061     { "vpermq",         { XM, EXx, Ib }, 0 },
10062   },
10063   {
10064     /* VEX_W_0F3A01_P_2 */
10065     { Bad_Opcode },
10066     { "vpermpd",        { XM, EXx, Ib }, 0 },
10067   },
10068   {
10069     /* VEX_W_0F3A02_P_2 */
10070     { "vpblendd",       { XM, Vex, EXx, Ib }, 0 },
10071   },
10072   {
10073     /* VEX_W_0F3A04_P_2 */
10074     { "vpermilps",      { XM, EXx, Ib }, 0 },
10075   },
10076   {
10077     /* VEX_W_0F3A05_P_2 */
10078     { "vpermilpd",      { XM, EXx, Ib }, 0 },
10079   },
10080   {
10081     /* VEX_W_0F3A06_P_2 */
10082     { "vperm2f128",     { XM, Vex256, EXx, Ib }, 0 },
10083   },
10084   {
10085     /* VEX_W_0F3A18_P_2 */
10086     { "vinsertf128",    { XM, Vex256, EXxmm, Ib }, 0 },
10087   },
10088   {
10089     /* VEX_W_0F3A19_P_2 */
10090     { "vextractf128",   { EXxmm, XM, Ib }, 0 },
10091   },
10092   {
10093     /* VEX_W_0F3A30_P_2_LEN_0 */
10094     { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0) },
10095     { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0) },
10096   },
10097   {
10098     /* VEX_W_0F3A31_P_2_LEN_0 */
10099     { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0) },
10100     { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0) },
10101   },
10102   {
10103     /* VEX_W_0F3A32_P_2_LEN_0 */
10104     { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0) },
10105     { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0) },
10106   },
10107   {
10108     /* VEX_W_0F3A33_P_2_LEN_0 */
10109     { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0) },
10110     { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0) },
10111   },
10112   {
10113     /* VEX_W_0F3A38_P_2 */
10114     { "vinserti128",    { XM, Vex256, EXxmm, Ib }, 0 },
10115   },
10116   {
10117     /* VEX_W_0F3A39_P_2 */
10118     { "vextracti128",   { EXxmm, XM, Ib }, 0 },
10119   },
10120   {
10121     /* VEX_W_0F3A46_P_2 */
10122     { "vperm2i128",     { XM, Vex256, EXx, Ib }, 0 },
10123   },
10124   {
10125     /* VEX_W_0F3A48_P_2 */
10126     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
10127     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
10128   },
10129   {
10130     /* VEX_W_0F3A49_P_2 */
10131     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
10132     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
10133   },
10134   {
10135     /* VEX_W_0F3A4A_P_2 */
10136     { "vblendvps",      { XM, Vex, EXx, XMVexI4 }, 0 },
10137   },
10138   {
10139     /* VEX_W_0F3A4B_P_2 */
10140     { "vblendvpd",      { XM, Vex, EXx, XMVexI4 }, 0 },
10141   },
10142   {
10143     /* VEX_W_0F3A4C_P_2 */
10144     { "vpblendvb",      { XM, Vex, EXx, XMVexI4 }, 0 },
10145   },
10146   {
10147     /* VEX_W_0F3ACE_P_2 */
10148     { Bad_Opcode },
10149     { "vgf2p8affineqb", { XM, Vex, EXx, Ib }, 0 },
10150   },
10151   {
10152     /* VEX_W_0F3ACF_P_2 */
10153     { Bad_Opcode },
10154     { "vgf2p8affineinvqb",  { XM, Vex, EXx, Ib }, 0 },
10155   },
10156
10157 #include "i386-dis-evex-w.h"
10158 };
10159
10160 static const struct dis386 mod_table[][2] = {
10161   {
10162     /* MOD_8D */
10163     { "leaS",           { Gv, M }, 0 },
10164   },
10165   {
10166     /* MOD_C6_REG_7 */
10167     { Bad_Opcode },
10168     { RM_TABLE (RM_C6_REG_7) },
10169   },
10170   {
10171     /* MOD_C7_REG_7 */
10172     { Bad_Opcode },
10173     { RM_TABLE (RM_C7_REG_7) },
10174   },
10175   {
10176     /* MOD_FF_REG_3 */
10177     { "{l|}call^", { indirEp }, 0 },
10178   },
10179   {
10180     /* MOD_FF_REG_5 */
10181     { "{l|}jmp^", { indirEp }, 0 },
10182   },
10183   {
10184     /* MOD_0F01_REG_0 */
10185     { X86_64_TABLE (X86_64_0F01_REG_0) },
10186     { RM_TABLE (RM_0F01_REG_0) },
10187   },
10188   {
10189     /* MOD_0F01_REG_1 */
10190     { X86_64_TABLE (X86_64_0F01_REG_1) },
10191     { RM_TABLE (RM_0F01_REG_1) },
10192   },
10193   {
10194     /* MOD_0F01_REG_2 */
10195     { X86_64_TABLE (X86_64_0F01_REG_2) },
10196     { RM_TABLE (RM_0F01_REG_2) },
10197   },
10198   {
10199     /* MOD_0F01_REG_3 */
10200     { X86_64_TABLE (X86_64_0F01_REG_3) },
10201     { RM_TABLE (RM_0F01_REG_3) },
10202   },
10203   {
10204     /* MOD_0F01_REG_5 */
10205     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_0) },
10206     { RM_TABLE (RM_0F01_REG_5_MOD_3) },
10207   },
10208   {
10209     /* MOD_0F01_REG_7 */
10210     { "invlpg",         { Mb }, 0 },
10211     { RM_TABLE (RM_0F01_REG_7_MOD_3) },
10212   },
10213   {
10214     /* MOD_0F12_PREFIX_0 */
10215     { "movlpX",         { XM, EXq }, 0 },
10216     { "movhlps",        { XM, EXq }, 0 },
10217   },
10218   {
10219     /* MOD_0F12_PREFIX_2 */
10220     { "movlpX", { XM, EXq }, 0 },
10221   },
10222   {
10223     /* MOD_0F13 */
10224     { "movlpX",         { EXq, XM }, PREFIX_OPCODE },
10225   },
10226   {
10227     /* MOD_0F16_PREFIX_0 */
10228     { "movhpX",         { XM, EXq }, 0 },
10229     { "movlhps",        { XM, EXq }, 0 },
10230   },
10231   {
10232     /* MOD_0F16_PREFIX_2 */
10233     { "movhpX", { XM, EXq }, 0 },
10234   },
10235   {
10236     /* MOD_0F17 */
10237     { "movhpX",         { EXq, XM }, PREFIX_OPCODE },
10238   },
10239   {
10240     /* MOD_0F18_REG_0 */
10241     { "prefetchnta",    { Mb }, 0 },
10242   },
10243   {
10244     /* MOD_0F18_REG_1 */
10245     { "prefetcht0",     { Mb }, 0 },
10246   },
10247   {
10248     /* MOD_0F18_REG_2 */
10249     { "prefetcht1",     { Mb }, 0 },
10250   },
10251   {
10252     /* MOD_0F18_REG_3 */
10253     { "prefetcht2",     { Mb }, 0 },
10254   },
10255   {
10256     /* MOD_0F18_REG_4 */
10257     { "nop/reserved",   { Mb }, 0 },
10258   },
10259   {
10260     /* MOD_0F18_REG_5 */
10261     { "nop/reserved",   { Mb }, 0 },
10262   },
10263   {
10264     /* MOD_0F18_REG_6 */
10265     { "nop/reserved",   { Mb }, 0 },
10266   },
10267   {
10268     /* MOD_0F18_REG_7 */
10269     { "nop/reserved",   { Mb }, 0 },
10270   },
10271   {
10272     /* MOD_0F1A_PREFIX_0 */
10273     { "bndldx",         { Gbnd, Mv_bnd }, 0 },
10274     { "nopQ",           { Ev }, 0 },
10275   },
10276   {
10277     /* MOD_0F1B_PREFIX_0 */
10278     { "bndstx",         { Mv_bnd, Gbnd }, 0 },
10279     { "nopQ",           { Ev }, 0 },
10280   },
10281   {
10282     /* MOD_0F1B_PREFIX_1 */
10283     { "bndmk",          { Gbnd, Mv_bnd }, 0 },
10284     { "nopQ",           { Ev }, 0 },
10285   },
10286   {
10287     /* MOD_0F1C_PREFIX_0 */
10288     { REG_TABLE (REG_0F1C_P_0_MOD_0) },
10289     { "nopQ",           { Ev }, 0 },
10290   },
10291   {
10292     /* MOD_0F1E_PREFIX_1 */
10293     { "nopQ",           { Ev }, 0 },
10294     { REG_TABLE (REG_0F1E_P_1_MOD_3) },
10295   },
10296   {
10297     /* MOD_0F24 */
10298     { Bad_Opcode },
10299     { "movL",           { Rd, Td }, 0 },
10300   },
10301   {
10302     /* MOD_0F26 */
10303     { Bad_Opcode },
10304     { "movL",           { Td, Rd }, 0 },
10305   },
10306   {
10307     /* MOD_0F2B_PREFIX_0 */
10308     {"movntps",         { Mx, XM }, PREFIX_OPCODE },
10309   },
10310   {
10311     /* MOD_0F2B_PREFIX_1 */
10312     {"movntss",         { Md, XM }, PREFIX_OPCODE },
10313   },
10314   {
10315     /* MOD_0F2B_PREFIX_2 */
10316     {"movntpd",         { Mx, XM }, PREFIX_OPCODE },
10317   },
10318   {
10319     /* MOD_0F2B_PREFIX_3 */
10320     {"movntsd",         { Mq, XM }, PREFIX_OPCODE },
10321   },
10322   {
10323     /* MOD_0F50 */
10324     { Bad_Opcode },
10325     { "movmskpX",       { Gdq, XS }, PREFIX_OPCODE },
10326   },
10327   {
10328     /* MOD_0F71_REG_2 */
10329     { Bad_Opcode },
10330     { "psrlw",          { MS, Ib }, 0 },
10331   },
10332   {
10333     /* MOD_0F71_REG_4 */
10334     { Bad_Opcode },
10335     { "psraw",          { MS, Ib }, 0 },
10336   },
10337   {
10338     /* MOD_0F71_REG_6 */
10339     { Bad_Opcode },
10340     { "psllw",          { MS, Ib }, 0 },
10341   },
10342   {
10343     /* MOD_0F72_REG_2 */
10344     { Bad_Opcode },
10345     { "psrld",          { MS, Ib }, 0 },
10346   },
10347   {
10348     /* MOD_0F72_REG_4 */
10349     { Bad_Opcode },
10350     { "psrad",          { MS, Ib }, 0 },
10351   },
10352   {
10353     /* MOD_0F72_REG_6 */
10354     { Bad_Opcode },
10355     { "pslld",          { MS, Ib }, 0 },
10356   },
10357   {
10358     /* MOD_0F73_REG_2 */
10359     { Bad_Opcode },
10360     { "psrlq",          { MS, Ib }, 0 },
10361   },
10362   {
10363     /* MOD_0F73_REG_3 */
10364     { Bad_Opcode },
10365     { PREFIX_TABLE (PREFIX_0F73_REG_3) },
10366   },
10367   {
10368     /* MOD_0F73_REG_6 */
10369     { Bad_Opcode },
10370     { "psllq",          { MS, Ib }, 0 },
10371   },
10372   {
10373     /* MOD_0F73_REG_7 */
10374     { Bad_Opcode },
10375     { PREFIX_TABLE (PREFIX_0F73_REG_7) },
10376   },
10377   {
10378     /* MOD_0FAE_REG_0 */
10379     { "fxsave",         { FXSAVE }, 0 },
10380     { PREFIX_TABLE (PREFIX_0FAE_REG_0_MOD_3) },
10381   },
10382   {
10383     /* MOD_0FAE_REG_1 */
10384     { "fxrstor",        { FXSAVE }, 0 },
10385     { PREFIX_TABLE (PREFIX_0FAE_REG_1_MOD_3) },
10386   },
10387   {
10388     /* MOD_0FAE_REG_2 */
10389     { "ldmxcsr",        { Md }, 0 },
10390     { PREFIX_TABLE (PREFIX_0FAE_REG_2_MOD_3) },
10391   },
10392   {
10393     /* MOD_0FAE_REG_3 */
10394     { "stmxcsr",        { Md }, 0 },
10395     { PREFIX_TABLE (PREFIX_0FAE_REG_3_MOD_3) },
10396   },
10397   {
10398     /* MOD_0FAE_REG_4 */
10399     { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_0) },
10400     { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_3) },
10401   },
10402   {
10403     /* MOD_0FAE_REG_5 */
10404     { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_0) },
10405     { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_3) },
10406   },
10407   {
10408     /* MOD_0FAE_REG_6 */
10409     { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_0) },
10410     { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_3) },
10411   },
10412   {
10413     /* MOD_0FAE_REG_7 */
10414     { PREFIX_TABLE (PREFIX_0FAE_REG_7_MOD_0) },
10415     { RM_TABLE (RM_0FAE_REG_7_MOD_3) },
10416   },
10417   {
10418     /* MOD_0FB2 */
10419     { "lssS",           { Gv, Mp }, 0 },
10420   },
10421   {
10422     /* MOD_0FB4 */
10423     { "lfsS",           { Gv, Mp }, 0 },
10424   },
10425   {
10426     /* MOD_0FB5 */
10427     { "lgsS",           { Gv, Mp }, 0 },
10428   },
10429   {
10430     /* MOD_0FC3 */
10431     { PREFIX_TABLE (PREFIX_0FC3_MOD_0) },
10432   },
10433   {
10434     /* MOD_0FC7_REG_3 */
10435     { "xrstors",        { FXSAVE }, 0 },
10436   },
10437   {
10438     /* MOD_0FC7_REG_4 */
10439     { "xsavec",         { FXSAVE }, 0 },
10440   },
10441   {
10442     /* MOD_0FC7_REG_5 */
10443     { "xsaves",         { FXSAVE }, 0 },
10444   },
10445   {
10446     /* MOD_0FC7_REG_6 */
10447     { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_0) },
10448     { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_3) }
10449   },
10450   {
10451     /* MOD_0FC7_REG_7 */
10452     { "vmptrst",        { Mq }, 0 },
10453     { PREFIX_TABLE (PREFIX_0FC7_REG_7_MOD_3) }
10454   },
10455   {
10456     /* MOD_0FD7 */
10457     { Bad_Opcode },
10458     { "pmovmskb",       { Gdq, MS }, 0 },
10459   },
10460   {
10461     /* MOD_0FE7_PREFIX_2 */
10462     { "movntdq",        { Mx, XM }, 0 },
10463   },
10464   {
10465     /* MOD_0FF0_PREFIX_3 */
10466     { "lddqu",          { XM, M }, 0 },
10467   },
10468   {
10469     /* MOD_0F382A_PREFIX_2 */
10470     { "movntdqa",       { XM, Mx }, 0 },
10471   },
10472   {
10473     /* MOD_0F38F5_PREFIX_2 */
10474     { "wrussK",         { M, Gdq }, PREFIX_OPCODE },
10475   },
10476   {
10477     /* MOD_0F38F6_PREFIX_0 */
10478     { "wrssK",          { M, Gdq }, PREFIX_OPCODE },
10479   },
10480   {
10481     /* MOD_0F38F8_PREFIX_1 */
10482     { "enqcmds",        { Gva, M }, PREFIX_OPCODE },
10483   },
10484   {
10485     /* MOD_0F38F8_PREFIX_2 */
10486     { "movdir64b",      { Gva, M }, PREFIX_OPCODE },
10487   },
10488   {
10489     /* MOD_0F38F8_PREFIX_3 */
10490     { "enqcmd",         { Gva, M }, PREFIX_OPCODE },
10491   },
10492   {
10493     /* MOD_0F38F9_PREFIX_0 */
10494     { "movdiri",        { Ev, Gv }, PREFIX_OPCODE },
10495   },
10496   {
10497     /* MOD_62_32BIT */
10498     { "bound{S|}",      { Gv, Ma }, 0 },
10499     { EVEX_TABLE (EVEX_0F) },
10500   },
10501   {
10502     /* MOD_C4_32BIT */
10503     { "lesS",           { Gv, Mp }, 0 },
10504     { VEX_C4_TABLE (VEX_0F) },
10505   },
10506   {
10507     /* MOD_C5_32BIT */
10508     { "ldsS",           { Gv, Mp }, 0 },
10509     { VEX_C5_TABLE (VEX_0F) },
10510   },
10511   {
10512     /* MOD_VEX_0F12_PREFIX_0 */
10513     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
10514     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
10515   },
10516   {
10517     /* MOD_VEX_0F12_PREFIX_2 */
10518     { VEX_LEN_TABLE (VEX_LEN_0F12_P_2_M_0) },
10519   },
10520   {
10521     /* MOD_VEX_0F13 */
10522     { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
10523   },
10524   {
10525     /* MOD_VEX_0F16_PREFIX_0 */
10526     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
10527     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
10528   },
10529   {
10530     /* MOD_VEX_0F16_PREFIX_2 */
10531     { VEX_LEN_TABLE (VEX_LEN_0F16_P_2_M_0) },
10532   },
10533   {
10534     /* MOD_VEX_0F17 */
10535     { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
10536   },
10537   {
10538     /* MOD_VEX_0F2B */
10539     { "vmovntpX",       { Mx, XM }, PREFIX_OPCODE },
10540   },
10541   {
10542     /* MOD_VEX_W_0_0F41_P_0_LEN_1 */
10543     { Bad_Opcode },
10544     { "kandw",          { MaskG, MaskVex, MaskR }, 0 },
10545   },
10546   {
10547     /* MOD_VEX_W_1_0F41_P_0_LEN_1 */
10548     { Bad_Opcode },
10549     { "kandq",          { MaskG, MaskVex, MaskR }, 0 },
10550   },
10551   {
10552     /* MOD_VEX_W_0_0F41_P_2_LEN_1 */
10553     { Bad_Opcode },
10554     { "kandb",          { MaskG, MaskVex, MaskR }, 0 },
10555   },
10556   {
10557     /* MOD_VEX_W_1_0F41_P_2_LEN_1 */
10558     { Bad_Opcode },
10559     { "kandd",          { MaskG, MaskVex, MaskR }, 0 },
10560   },
10561   {
10562     /* MOD_VEX_W_0_0F42_P_0_LEN_1 */
10563     { Bad_Opcode },
10564     { "kandnw",         { MaskG, MaskVex, MaskR }, 0 },
10565   },
10566   {
10567     /* MOD_VEX_W_1_0F42_P_0_LEN_1 */
10568     { Bad_Opcode },
10569     { "kandnq",         { MaskG, MaskVex, MaskR }, 0 },
10570   },
10571   {
10572     /* MOD_VEX_W_0_0F42_P_2_LEN_1 */
10573     { Bad_Opcode },
10574     { "kandnb",         { MaskG, MaskVex, MaskR }, 0 },
10575   },
10576   {
10577     /* MOD_VEX_W_1_0F42_P_2_LEN_1 */
10578     { Bad_Opcode },
10579     { "kandnd",         { MaskG, MaskVex, MaskR }, 0 },
10580   },
10581   {
10582     /* MOD_VEX_W_0_0F44_P_0_LEN_0 */
10583     { Bad_Opcode },
10584     { "knotw",          { MaskG, MaskR }, 0 },
10585   },
10586   {
10587     /* MOD_VEX_W_1_0F44_P_0_LEN_0 */
10588     { Bad_Opcode },
10589     { "knotq",          { MaskG, MaskR }, 0 },
10590   },
10591   {
10592     /* MOD_VEX_W_0_0F44_P_2_LEN_0 */
10593     { Bad_Opcode },
10594     { "knotb",          { MaskG, MaskR }, 0 },
10595   },
10596   {
10597     /* MOD_VEX_W_1_0F44_P_2_LEN_0 */
10598     { Bad_Opcode },
10599     { "knotd",          { MaskG, MaskR }, 0 },
10600   },
10601   {
10602     /* MOD_VEX_W_0_0F45_P_0_LEN_1 */
10603     { Bad_Opcode },
10604     { "korw",       { MaskG, MaskVex, MaskR }, 0 },
10605   },
10606   {
10607     /* MOD_VEX_W_1_0F45_P_0_LEN_1 */
10608     { Bad_Opcode },
10609     { "korq",       { MaskG, MaskVex, MaskR }, 0 },
10610   },
10611   {
10612     /* MOD_VEX_W_0_0F45_P_2_LEN_1 */
10613     { Bad_Opcode },
10614     { "korb",       { MaskG, MaskVex, MaskR }, 0 },
10615   },
10616   {
10617     /* MOD_VEX_W_1_0F45_P_2_LEN_1 */
10618     { Bad_Opcode },
10619     { "kord",       { MaskG, MaskVex, MaskR }, 0 },
10620   },
10621  {
10622     /* MOD_VEX_W_0_0F46_P_0_LEN_1 */
10623     { Bad_Opcode },
10624     { "kxnorw",     { MaskG, MaskVex, MaskR }, 0 },
10625   },
10626   {
10627     /* MOD_VEX_W_1_0F46_P_0_LEN_1 */
10628     { Bad_Opcode },
10629     { "kxnorq",     { MaskG, MaskVex, MaskR }, 0 },
10630   },
10631   {
10632     /* MOD_VEX_W_0_0F46_P_2_LEN_1 */
10633     { Bad_Opcode },
10634     { "kxnorb",     { MaskG, MaskVex, MaskR }, 0 },
10635   },
10636   {
10637     /* MOD_VEX_W_1_0F46_P_2_LEN_1 */
10638     { Bad_Opcode },
10639     { "kxnord",     { MaskG, MaskVex, MaskR }, 0 },
10640   },
10641   {
10642     /* MOD_VEX_W_0_0F47_P_0_LEN_1 */
10643     { Bad_Opcode },
10644     { "kxorw",      { MaskG, MaskVex, MaskR }, 0 },
10645   },
10646   {
10647     /* MOD_VEX_W_1_0F47_P_0_LEN_1 */
10648     { Bad_Opcode },
10649     { "kxorq",      { MaskG, MaskVex, MaskR }, 0 },
10650   },
10651   {
10652     /* MOD_VEX_W_0_0F47_P_2_LEN_1 */
10653     { Bad_Opcode },
10654     { "kxorb",      { MaskG, MaskVex, MaskR }, 0 },
10655   },
10656   {
10657     /* MOD_VEX_W_1_0F47_P_2_LEN_1 */
10658     { Bad_Opcode },
10659     { "kxord",      { MaskG, MaskVex, MaskR }, 0 },
10660   },
10661   {
10662     /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */
10663     { Bad_Opcode },
10664     { "kaddw",          { MaskG, MaskVex, MaskR }, 0 },
10665   },
10666   {
10667     /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */
10668     { Bad_Opcode },
10669     { "kaddq",          { MaskG, MaskVex, MaskR }, 0 },
10670   },
10671   {
10672     /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */
10673     { Bad_Opcode },
10674     { "kaddb",          { MaskG, MaskVex, MaskR }, 0 },
10675   },
10676   {
10677     /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */
10678     { Bad_Opcode },
10679     { "kaddd",          { MaskG, MaskVex, MaskR }, 0 },
10680   },
10681   {
10682     /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */
10683     { Bad_Opcode },
10684     { "kunpckwd",   { MaskG, MaskVex, MaskR }, 0 },
10685   },
10686   {
10687     /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */
10688     { Bad_Opcode },
10689     { "kunpckdq",   { MaskG, MaskVex, MaskR }, 0 },
10690   },
10691   {
10692     /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */
10693     { Bad_Opcode },
10694     { "kunpckbw",   { MaskG, MaskVex, MaskR }, 0 },
10695   },
10696   {
10697     /* MOD_VEX_0F50 */
10698     { Bad_Opcode },
10699     { "vmovmskpX",      { Gdq, XS }, PREFIX_OPCODE },
10700   },
10701   {
10702     /* MOD_VEX_0F71_REG_2 */
10703     { Bad_Opcode },
10704     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) },
10705   },
10706   {
10707     /* MOD_VEX_0F71_REG_4 */
10708     { Bad_Opcode },
10709     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) },
10710   },
10711   {
10712     /* MOD_VEX_0F71_REG_6 */
10713     { Bad_Opcode },
10714     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) },
10715   },
10716   {
10717     /* MOD_VEX_0F72_REG_2 */
10718     { Bad_Opcode },
10719     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) },
10720   },
10721   {
10722     /* MOD_VEX_0F72_REG_4 */
10723     { Bad_Opcode },
10724     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) },
10725   },
10726   {
10727     /* MOD_VEX_0F72_REG_6 */
10728     { Bad_Opcode },
10729     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) },
10730   },
10731   {
10732     /* MOD_VEX_0F73_REG_2 */
10733     { Bad_Opcode },
10734     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) },
10735   },
10736   {
10737     /* MOD_VEX_0F73_REG_3 */
10738     { Bad_Opcode },
10739     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) },
10740   },
10741   {
10742     /* MOD_VEX_0F73_REG_6 */
10743     { Bad_Opcode },
10744     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) },
10745   },
10746   {
10747     /* MOD_VEX_0F73_REG_7 */
10748     { Bad_Opcode },
10749     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) },
10750   },
10751   {
10752     /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
10753     { "kmovw",          { Ew, MaskG }, 0 },
10754     { Bad_Opcode },
10755   },
10756   {
10757     /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
10758     { "kmovq",          { Eq, MaskG }, 0 },
10759     { Bad_Opcode },
10760   },
10761   {
10762     /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
10763     { "kmovb",          { Eb, MaskG }, 0 },
10764     { Bad_Opcode },
10765   },
10766   {
10767     /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
10768     { "kmovd",          { Ed, MaskG }, 0 },
10769     { Bad_Opcode },
10770   },
10771   {
10772     /* MOD_VEX_W_0_0F92_P_0_LEN_0 */
10773     { Bad_Opcode },
10774     { "kmovw",          { MaskG, Rdq }, 0 },
10775   },
10776   {
10777     /* MOD_VEX_W_0_0F92_P_2_LEN_0 */
10778     { Bad_Opcode },
10779     { "kmovb",          { MaskG, Rdq }, 0 },
10780   },
10781   {
10782     /* MOD_VEX_0F92_P_3_LEN_0 */
10783     { Bad_Opcode },
10784     { "kmovK",          { MaskG, Rdq }, 0 },
10785   },
10786   {
10787     /* MOD_VEX_W_0_0F93_P_0_LEN_0 */
10788     { Bad_Opcode },
10789     { "kmovw",          { Gdq, MaskR }, 0 },
10790   },
10791   {
10792     /* MOD_VEX_W_0_0F93_P_2_LEN_0 */
10793     { Bad_Opcode },
10794     { "kmovb",          { Gdq, MaskR }, 0 },
10795   },
10796   {
10797     /* MOD_VEX_0F93_P_3_LEN_0 */
10798     { Bad_Opcode },
10799     { "kmovK",          { Gdq, MaskR }, 0 },
10800   },
10801   {
10802     /* MOD_VEX_W_0_0F98_P_0_LEN_0 */
10803     { Bad_Opcode },
10804     { "kortestw", { MaskG, MaskR }, 0 },
10805   },
10806   {
10807     /* MOD_VEX_W_1_0F98_P_0_LEN_0 */
10808     { Bad_Opcode },
10809     { "kortestq", { MaskG, MaskR }, 0 },
10810   },
10811   {
10812     /* MOD_VEX_W_0_0F98_P_2_LEN_0 */
10813     { Bad_Opcode },
10814     { "kortestb", { MaskG, MaskR }, 0 },
10815   },
10816   {
10817     /* MOD_VEX_W_1_0F98_P_2_LEN_0 */
10818     { Bad_Opcode },
10819     { "kortestd", { MaskG, MaskR }, 0 },
10820   },
10821   {
10822     /* MOD_VEX_W_0_0F99_P_0_LEN_0 */
10823     { Bad_Opcode },
10824     { "ktestw", { MaskG, MaskR }, 0 },
10825   },
10826   {
10827     /* MOD_VEX_W_1_0F99_P_0_LEN_0 */
10828     { Bad_Opcode },
10829     { "ktestq", { MaskG, MaskR }, 0 },
10830   },
10831   {
10832     /* MOD_VEX_W_0_0F99_P_2_LEN_0 */
10833     { Bad_Opcode },
10834     { "ktestb", { MaskG, MaskR }, 0 },
10835   },
10836   {
10837     /* MOD_VEX_W_1_0F99_P_2_LEN_0 */
10838     { Bad_Opcode },
10839     { "ktestd", { MaskG, MaskR }, 0 },
10840   },
10841   {
10842     /* MOD_VEX_0FAE_REG_2 */
10843     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
10844   },
10845   {
10846     /* MOD_VEX_0FAE_REG_3 */
10847     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
10848   },
10849   {
10850     /* MOD_VEX_0FD7_PREFIX_2 */
10851     { Bad_Opcode },
10852     { "vpmovmskb",      { Gdq, XS }, 0 },
10853   },
10854   {
10855     /* MOD_VEX_0FE7_PREFIX_2 */
10856     { "vmovntdq",       { Mx, XM }, 0 },
10857   },
10858   {
10859     /* MOD_VEX_0FF0_PREFIX_3 */
10860     { "vlddqu",         { XM, M }, 0 },
10861   },
10862   {
10863     /* MOD_VEX_0F381A_PREFIX_2 */
10864     { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) },
10865   },
10866   {
10867     /* MOD_VEX_0F382A_PREFIX_2 */
10868     { "vmovntdqa",      { XM, Mx }, 0 },
10869   },
10870   {
10871     /* MOD_VEX_0F382C_PREFIX_2 */
10872     { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) },
10873   },
10874   {
10875     /* MOD_VEX_0F382D_PREFIX_2 */
10876     { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) },
10877   },
10878   {
10879     /* MOD_VEX_0F382E_PREFIX_2 */
10880     { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) },
10881   },
10882   {
10883     /* MOD_VEX_0F382F_PREFIX_2 */
10884     { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) },
10885   },
10886   {
10887     /* MOD_VEX_0F385A_PREFIX_2 */
10888     { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) },
10889   },
10890   {
10891     /* MOD_VEX_0F388C_PREFIX_2 */
10892     { "vpmaskmov%LW",   { XM, Vex, Mx }, 0 },
10893   },
10894   {
10895     /* MOD_VEX_0F388E_PREFIX_2 */
10896     { "vpmaskmov%LW",   { Mx, Vex, XM }, 0 },
10897   },
10898   {
10899     /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */
10900     { Bad_Opcode },
10901     { "kshiftrb",       { MaskG, MaskR, Ib }, 0 },
10902   },
10903   {
10904     /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */
10905     { Bad_Opcode },
10906     { "kshiftrw",       { MaskG, MaskR, Ib }, 0 },
10907   },
10908   {
10909     /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */
10910     { Bad_Opcode },
10911     { "kshiftrd",       { MaskG, MaskR, Ib }, 0 },
10912   },
10913   {
10914     /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */
10915     { Bad_Opcode },
10916     { "kshiftrq",       { MaskG, MaskR, Ib }, 0 },
10917   },
10918   {
10919     /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */
10920     { Bad_Opcode },
10921     { "kshiftlb",       { MaskG, MaskR, Ib }, 0 },
10922   },
10923   {
10924     /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */
10925     { Bad_Opcode },
10926     { "kshiftlw",       { MaskG, MaskR, Ib }, 0 },
10927   },
10928   {
10929     /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */
10930     { Bad_Opcode },
10931     { "kshiftld",       { MaskG, MaskR, Ib }, 0 },
10932   },
10933   {
10934     /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */
10935     { Bad_Opcode },
10936     { "kshiftlq",       { MaskG, MaskR, Ib }, 0 },
10937   },
10938
10939 #include "i386-dis-evex-mod.h"
10940 };
10941
10942 static const struct dis386 rm_table[][8] = {
10943   {
10944     /* RM_C6_REG_7 */
10945     { "xabort",         { Skip_MODRM, Ib }, 0 },
10946   },
10947   {
10948     /* RM_C7_REG_7 */
10949     { "xbeginT",        { Skip_MODRM, Jdqw }, 0 },
10950   },
10951   {
10952     /* RM_0F01_REG_0 */
10953     { "enclv",          { Skip_MODRM }, 0 },
10954     { "vmcall",         { Skip_MODRM }, 0 },
10955     { "vmlaunch",       { Skip_MODRM }, 0 },
10956     { "vmresume",       { Skip_MODRM }, 0 },
10957     { "vmxoff",         { Skip_MODRM }, 0 },
10958     { "pconfig",        { Skip_MODRM }, 0 },
10959   },
10960   {
10961     /* RM_0F01_REG_1 */
10962     { "monitor",        { { OP_Monitor, 0 } }, 0 },
10963     { "mwait",          { { OP_Mwait, 0 } }, 0 },
10964     { "clac",           { Skip_MODRM }, 0 },
10965     { "stac",           { Skip_MODRM }, 0 },
10966     { Bad_Opcode },
10967     { Bad_Opcode },
10968     { Bad_Opcode },
10969     { "encls",          { Skip_MODRM }, 0 },
10970   },
10971   {
10972     /* RM_0F01_REG_2 */
10973     { "xgetbv",         { Skip_MODRM }, 0 },
10974     { "xsetbv",         { Skip_MODRM }, 0 },
10975     { Bad_Opcode },
10976     { Bad_Opcode },
10977     { "vmfunc",         { Skip_MODRM }, 0 },
10978     { "xend",           { Skip_MODRM }, 0 },
10979     { "xtest",          { Skip_MODRM }, 0 },
10980     { "enclu",          { Skip_MODRM }, 0 },
10981   },
10982   {
10983     /* RM_0F01_REG_3 */
10984     { "vmrun",          { Skip_MODRM }, 0 },
10985     { PREFIX_TABLE (PREFIX_0F01_REG_3_RM_1) },
10986     { "vmload",         { Skip_MODRM }, 0 },
10987     { "vmsave",         { Skip_MODRM }, 0 },
10988     { "stgi",           { Skip_MODRM }, 0 },
10989     { "clgi",           { Skip_MODRM }, 0 },
10990     { "skinit",         { Skip_MODRM }, 0 },
10991     { "invlpga",        { Skip_MODRM }, 0 },
10992   },
10993   {
10994     /* RM_0F01_REG_5_MOD_3 */
10995     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_0) },
10996     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_1) },
10997     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_2) },
10998     { Bad_Opcode },
10999     { Bad_Opcode },
11000     { Bad_Opcode },
11001     { "rdpkru",         { Skip_MODRM }, 0 },
11002     { "wrpkru",         { Skip_MODRM }, 0 },
11003   },
11004   {
11005     /* RM_0F01_REG_7_MOD_3 */
11006     { "swapgs",         { Skip_MODRM }, 0  },
11007     { "rdtscp",         { Skip_MODRM }, 0  },
11008     { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_2) },
11009     { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_3) },
11010     { "clzero",         { Skip_MODRM }, 0  },
11011     { "rdpru",          { Skip_MODRM }, 0  },
11012   },
11013   {
11014     /* RM_0F1E_P_1_MOD_3_REG_7 */
11015     { "nopQ",           { Ev }, 0 },
11016     { "nopQ",           { Ev }, 0 },
11017     { "endbr64",        { Skip_MODRM },  PREFIX_OPCODE },
11018     { "endbr32",        { Skip_MODRM },  PREFIX_OPCODE },
11019     { "nopQ",           { Ev }, 0 },
11020     { "nopQ",           { Ev }, 0 },
11021     { "nopQ",           { Ev }, 0 },
11022     { "nopQ",           { Ev }, 0 },
11023   },
11024   {
11025     /* RM_0FAE_REG_6_MOD_3 */
11026     { "mfence",         { Skip_MODRM }, 0 },
11027   },
11028   {
11029     /* RM_0FAE_REG_7_MOD_3 */
11030     { "sfence",         { Skip_MODRM }, 0 },
11031
11032   },
11033 };
11034
11035 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
11036
11037 /* We use the high bit to indicate different name for the same
11038    prefix.  */
11039 #define REP_PREFIX      (0xf3 | 0x100)
11040 #define XACQUIRE_PREFIX (0xf2 | 0x200)
11041 #define XRELEASE_PREFIX (0xf3 | 0x400)
11042 #define BND_PREFIX      (0xf2 | 0x400)
11043 #define NOTRACK_PREFIX  (0x3e | 0x100)
11044
11045 /* Remember if the current op is a jump instruction.  */
11046 static bfd_boolean op_is_jump = FALSE;
11047
11048 static int
11049 ckprefix (void)
11050 {
11051   int newrex, i, length;
11052   rex = 0;
11053   prefixes = 0;
11054   used_prefixes = 0;
11055   rex_used = 0;
11056   last_lock_prefix = -1;
11057   last_repz_prefix = -1;
11058   last_repnz_prefix = -1;
11059   last_data_prefix = -1;
11060   last_addr_prefix = -1;
11061   last_rex_prefix = -1;
11062   last_seg_prefix = -1;
11063   fwait_prefix = -1;
11064   active_seg_prefix = 0;
11065   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
11066     all_prefixes[i] = 0;
11067   i = 0;
11068   length = 0;
11069   /* The maximum instruction length is 15bytes.  */
11070   while (length < MAX_CODE_LENGTH - 1)
11071     {
11072       FETCH_DATA (the_info, codep + 1);
11073       newrex = 0;
11074       switch (*codep)
11075         {
11076         /* REX prefixes family.  */
11077         case 0x40:
11078         case 0x41:
11079         case 0x42:
11080         case 0x43:
11081         case 0x44:
11082         case 0x45:
11083         case 0x46:
11084         case 0x47:
11085         case 0x48:
11086         case 0x49:
11087         case 0x4a:
11088         case 0x4b:
11089         case 0x4c:
11090         case 0x4d:
11091         case 0x4e:
11092         case 0x4f:
11093           if (address_mode == mode_64bit)
11094             newrex = *codep;
11095           else
11096             return 1;
11097           last_rex_prefix = i;
11098           break;
11099         case 0xf3:
11100           prefixes |= PREFIX_REPZ;
11101           last_repz_prefix = i;
11102           break;
11103         case 0xf2:
11104           prefixes |= PREFIX_REPNZ;
11105           last_repnz_prefix = i;
11106           break;
11107         case 0xf0:
11108           prefixes |= PREFIX_LOCK;
11109           last_lock_prefix = i;
11110           break;
11111         case 0x2e:
11112           prefixes |= PREFIX_CS;
11113           last_seg_prefix = i;
11114           active_seg_prefix = PREFIX_CS;
11115           break;
11116         case 0x36:
11117           prefixes |= PREFIX_SS;
11118           last_seg_prefix = i;
11119           active_seg_prefix = PREFIX_SS;
11120           break;
11121         case 0x3e:
11122           prefixes |= PREFIX_DS;
11123           last_seg_prefix = i;
11124           active_seg_prefix = PREFIX_DS;
11125           break;
11126         case 0x26:
11127           prefixes |= PREFIX_ES;
11128           last_seg_prefix = i;
11129           active_seg_prefix = PREFIX_ES;
11130           break;
11131         case 0x64:
11132           prefixes |= PREFIX_FS;
11133           last_seg_prefix = i;
11134           active_seg_prefix = PREFIX_FS;
11135           break;
11136         case 0x65:
11137           prefixes |= PREFIX_GS;
11138           last_seg_prefix = i;
11139           active_seg_prefix = PREFIX_GS;
11140           break;
11141         case 0x66:
11142           prefixes |= PREFIX_DATA;
11143           last_data_prefix = i;
11144           break;
11145         case 0x67:
11146           prefixes |= PREFIX_ADDR;
11147           last_addr_prefix = i;
11148           break;
11149         case FWAIT_OPCODE:
11150           /* fwait is really an instruction.  If there are prefixes
11151              before the fwait, they belong to the fwait, *not* to the
11152              following instruction.  */
11153           fwait_prefix = i;
11154           if (prefixes || rex)
11155             {
11156               prefixes |= PREFIX_FWAIT;
11157               codep++;
11158               /* This ensures that the previous REX prefixes are noticed
11159                  as unused prefixes, as in the return case below.  */
11160               rex_used = rex;
11161               return 1;
11162             }
11163           prefixes = PREFIX_FWAIT;
11164           break;
11165         default:
11166           return 1;
11167         }
11168       /* Rex is ignored when followed by another prefix.  */
11169       if (rex)
11170         {
11171           rex_used = rex;
11172           return 1;
11173         }
11174       if (*codep != FWAIT_OPCODE)
11175         all_prefixes[i++] = *codep;
11176       rex = newrex;
11177       codep++;
11178       length++;
11179     }
11180   return 0;
11181 }
11182
11183 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
11184    prefix byte.  */
11185
11186 static const char *
11187 prefix_name (int pref, int sizeflag)
11188 {
11189   static const char *rexes [16] =
11190     {
11191       "rex",            /* 0x40 */
11192       "rex.B",          /* 0x41 */
11193       "rex.X",          /* 0x42 */
11194       "rex.XB",         /* 0x43 */
11195       "rex.R",          /* 0x44 */
11196       "rex.RB",         /* 0x45 */
11197       "rex.RX",         /* 0x46 */
11198       "rex.RXB",        /* 0x47 */
11199       "rex.W",          /* 0x48 */
11200       "rex.WB",         /* 0x49 */
11201       "rex.WX",         /* 0x4a */
11202       "rex.WXB",        /* 0x4b */
11203       "rex.WR",         /* 0x4c */
11204       "rex.WRB",        /* 0x4d */
11205       "rex.WRX",        /* 0x4e */
11206       "rex.WRXB",       /* 0x4f */
11207     };
11208
11209   switch (pref)
11210     {
11211     /* REX prefixes family.  */
11212     case 0x40:
11213     case 0x41:
11214     case 0x42:
11215     case 0x43:
11216     case 0x44:
11217     case 0x45:
11218     case 0x46:
11219     case 0x47:
11220     case 0x48:
11221     case 0x49:
11222     case 0x4a:
11223     case 0x4b:
11224     case 0x4c:
11225     case 0x4d:
11226     case 0x4e:
11227     case 0x4f:
11228       return rexes [pref - 0x40];
11229     case 0xf3:
11230       return "repz";
11231     case 0xf2:
11232       return "repnz";
11233     case 0xf0:
11234       return "lock";
11235     case 0x2e:
11236       return "cs";
11237     case 0x36:
11238       return "ss";
11239     case 0x3e:
11240       return "ds";
11241     case 0x26:
11242       return "es";
11243     case 0x64:
11244       return "fs";
11245     case 0x65:
11246       return "gs";
11247     case 0x66:
11248       return (sizeflag & DFLAG) ? "data16" : "data32";
11249     case 0x67:
11250       if (address_mode == mode_64bit)
11251         return (sizeflag & AFLAG) ? "addr32" : "addr64";
11252       else
11253         return (sizeflag & AFLAG) ? "addr16" : "addr32";
11254     case FWAIT_OPCODE:
11255       return "fwait";
11256     case REP_PREFIX:
11257       return "rep";
11258     case XACQUIRE_PREFIX:
11259       return "xacquire";
11260     case XRELEASE_PREFIX:
11261       return "xrelease";
11262     case BND_PREFIX:
11263       return "bnd";
11264     case NOTRACK_PREFIX:
11265       return "notrack";
11266     default:
11267       return NULL;
11268     }
11269 }
11270
11271 static char op_out[MAX_OPERANDS][100];
11272 static int op_ad, op_index[MAX_OPERANDS];
11273 static int two_source_ops;
11274 static bfd_vma op_address[MAX_OPERANDS];
11275 static bfd_vma op_riprel[MAX_OPERANDS];
11276 static bfd_vma start_pc;
11277
11278 /*
11279  *   On the 386's of 1988, the maximum length of an instruction is 15 bytes.
11280  *   (see topic "Redundant prefixes" in the "Differences from 8086"
11281  *   section of the "Virtual 8086 Mode" chapter.)
11282  * 'pc' should be the address of this instruction, it will
11283  *   be used to print the target address if this is a relative jump or call
11284  * The function returns the length of this instruction in bytes.
11285  */
11286
11287 static char intel_syntax;
11288 static char intel_mnemonic = !SYSV386_COMPAT;
11289 static char open_char;
11290 static char close_char;
11291 static char separator_char;
11292 static char scale_char;
11293
11294 enum x86_64_isa
11295 {
11296   amd64 = 1,
11297   intel64
11298 };
11299
11300 static enum x86_64_isa isa64;
11301
11302 /* Here for backwards compatibility.  When gdb stops using
11303    print_insn_i386_att and print_insn_i386_intel these functions can
11304    disappear, and print_insn_i386 be merged into print_insn.  */
11305 int
11306 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
11307 {
11308   intel_syntax = 0;
11309
11310   return print_insn (pc, info);
11311 }
11312
11313 int
11314 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
11315 {
11316   intel_syntax = 1;
11317
11318   return print_insn (pc, info);
11319 }
11320
11321 int
11322 print_insn_i386 (bfd_vma pc, disassemble_info *info)
11323 {
11324   intel_syntax = -1;
11325
11326   return print_insn (pc, info);
11327 }
11328
11329 void
11330 print_i386_disassembler_options (FILE *stream)
11331 {
11332   fprintf (stream, _("\n\
11333 The following i386/x86-64 specific disassembler options are supported for use\n\
11334 with the -M switch (multiple options should be separated by commas):\n"));
11335
11336   fprintf (stream, _("  x86-64      Disassemble in 64bit mode\n"));
11337   fprintf (stream, _("  i386        Disassemble in 32bit mode\n"));
11338   fprintf (stream, _("  i8086       Disassemble in 16bit mode\n"));
11339   fprintf (stream, _("  att         Display instruction in AT&T syntax\n"));
11340   fprintf (stream, _("  intel       Display instruction in Intel syntax\n"));
11341   fprintf (stream, _("  att-mnemonic\n"
11342                      "              Display instruction in AT&T mnemonic\n"));
11343   fprintf (stream, _("  intel-mnemonic\n"
11344                      "              Display instruction in Intel mnemonic\n"));
11345   fprintf (stream, _("  addr64      Assume 64bit address size\n"));
11346   fprintf (stream, _("  addr32      Assume 32bit address size\n"));
11347   fprintf (stream, _("  addr16      Assume 16bit address size\n"));
11348   fprintf (stream, _("  data32      Assume 32bit data size\n"));
11349   fprintf (stream, _("  data16      Assume 16bit data size\n"));
11350   fprintf (stream, _("  suffix      Always display instruction suffix in AT&T syntax\n"));
11351   fprintf (stream, _("  amd64       Display instruction in AMD64 ISA\n"));
11352   fprintf (stream, _("  intel64     Display instruction in Intel64 ISA\n"));
11353 }
11354
11355 /* Bad opcode.  */
11356 static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 };
11357
11358 /* Get a pointer to struct dis386 with a valid name.  */
11359
11360 static const struct dis386 *
11361 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
11362 {
11363   int vindex, vex_table_index;
11364
11365   if (dp->name != NULL)
11366     return dp;
11367
11368   switch (dp->op[0].bytemode)
11369     {
11370     case USE_REG_TABLE:
11371       dp = &reg_table[dp->op[1].bytemode][modrm.reg];
11372       break;
11373
11374     case USE_MOD_TABLE:
11375       vindex = modrm.mod == 0x3 ? 1 : 0;
11376       dp = &mod_table[dp->op[1].bytemode][vindex];
11377       break;
11378
11379     case USE_RM_TABLE:
11380       dp = &rm_table[dp->op[1].bytemode][modrm.rm];
11381       break;
11382
11383     case USE_PREFIX_TABLE:
11384       if (need_vex)
11385         {
11386           /* The prefix in VEX is implicit.  */
11387           switch (vex.prefix)
11388             {
11389             case 0:
11390               vindex = 0;
11391               break;
11392             case REPE_PREFIX_OPCODE:
11393               vindex = 1;
11394               break;
11395             case DATA_PREFIX_OPCODE:
11396               vindex = 2;
11397               break;
11398             case REPNE_PREFIX_OPCODE:
11399               vindex = 3;
11400               break;
11401             default:
11402               abort ();
11403               break;
11404             }
11405         }
11406       else
11407         {
11408           int last_prefix = -1;
11409           int prefix = 0;
11410           vindex = 0;
11411           /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
11412              When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
11413              last one wins.  */
11414           if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
11415             {
11416               if (last_repz_prefix > last_repnz_prefix)
11417                 {
11418                   vindex = 1;
11419                   prefix = PREFIX_REPZ;
11420                   last_prefix = last_repz_prefix;
11421                 }
11422               else
11423                 {
11424                   vindex = 3;
11425                   prefix = PREFIX_REPNZ;
11426                   last_prefix = last_repnz_prefix;
11427                 }
11428
11429               /* Check if prefix should be ignored.  */
11430               if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement
11431                      & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT)
11432                    & prefix) != 0)
11433                 vindex = 0;
11434             }
11435
11436           if (vindex == 0 && (prefixes & PREFIX_DATA) != 0)
11437             {
11438               vindex = 2;
11439               prefix = PREFIX_DATA;
11440               last_prefix = last_data_prefix;
11441             }
11442
11443           if (vindex != 0)
11444             {
11445               used_prefixes |= prefix;
11446               all_prefixes[last_prefix] = 0;
11447             }
11448         }
11449       dp = &prefix_table[dp->op[1].bytemode][vindex];
11450       break;
11451
11452     case USE_X86_64_TABLE:
11453       vindex = address_mode == mode_64bit ? 1 : 0;
11454       dp = &x86_64_table[dp->op[1].bytemode][vindex];
11455       break;
11456
11457     case USE_3BYTE_TABLE:
11458       FETCH_DATA (info, codep + 2);
11459       vindex = *codep++;
11460       dp = &three_byte_table[dp->op[1].bytemode][vindex];
11461       end_codep = codep;
11462       modrm.mod = (*codep >> 6) & 3;
11463       modrm.reg = (*codep >> 3) & 7;
11464       modrm.rm = *codep & 7;
11465       break;
11466
11467     case USE_VEX_LEN_TABLE:
11468       if (!need_vex)
11469         abort ();
11470
11471       switch (vex.length)
11472         {
11473         case 128:
11474           vindex = 0;
11475           break;
11476         case 256:
11477           vindex = 1;
11478           break;
11479         default:
11480           abort ();
11481           break;
11482         }
11483
11484       dp = &vex_len_table[dp->op[1].bytemode][vindex];
11485       break;
11486
11487     case USE_EVEX_LEN_TABLE:
11488       if (!vex.evex)
11489         abort ();
11490
11491       switch (vex.length)
11492         {
11493         case 128:
11494           vindex = 0;
11495           break;
11496         case 256:
11497           vindex = 1;
11498           break;
11499         case 512:
11500           vindex = 2;
11501           break;
11502         default:
11503           abort ();
11504           break;
11505         }
11506
11507       dp = &evex_len_table[dp->op[1].bytemode][vindex];
11508       break;
11509
11510     case USE_XOP_8F_TABLE:
11511       FETCH_DATA (info, codep + 3);
11512       rex = ~(*codep >> 5) & 0x7;
11513
11514       /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm".  */
11515       switch ((*codep & 0x1f))
11516         {
11517         default:
11518           dp = &bad_opcode;
11519           return dp;
11520         case 0x8:
11521           vex_table_index = XOP_08;
11522           break;
11523         case 0x9:
11524           vex_table_index = XOP_09;
11525           break;
11526         case 0xa:
11527           vex_table_index = XOP_0A;
11528           break;
11529         }
11530       codep++;
11531       vex.w = *codep & 0x80;
11532       if (vex.w && address_mode == mode_64bit)
11533         rex |= REX_W;
11534
11535       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11536       if (address_mode != mode_64bit)
11537         {
11538           /* In 16/32-bit mode REX_B is silently ignored.  */
11539           rex &= ~REX_B;
11540         }
11541
11542       vex.length = (*codep & 0x4) ? 256 : 128;
11543       switch ((*codep & 0x3))
11544         {
11545         case 0:
11546           break;
11547         case 1:
11548           vex.prefix = DATA_PREFIX_OPCODE;
11549           break;
11550         case 2:
11551           vex.prefix = REPE_PREFIX_OPCODE;
11552           break;
11553         case 3:
11554           vex.prefix = REPNE_PREFIX_OPCODE;
11555           break;
11556         }
11557       need_vex = 1;
11558       need_vex_reg = 1;
11559       codep++;
11560       vindex = *codep++;
11561       dp = &xop_table[vex_table_index][vindex];
11562
11563       end_codep = codep;
11564       FETCH_DATA (info, codep + 1);
11565       modrm.mod = (*codep >> 6) & 3;
11566       modrm.reg = (*codep >> 3) & 7;
11567       modrm.rm = *codep & 7;
11568       break;
11569
11570     case USE_VEX_C4_TABLE:
11571       /* VEX prefix.  */
11572       FETCH_DATA (info, codep + 3);
11573       rex = ~(*codep >> 5) & 0x7;
11574       switch ((*codep & 0x1f))
11575         {
11576         default:
11577           dp = &bad_opcode;
11578           return dp;
11579         case 0x1:
11580           vex_table_index = VEX_0F;
11581           break;
11582         case 0x2:
11583           vex_table_index = VEX_0F38;
11584           break;
11585         case 0x3:
11586           vex_table_index = VEX_0F3A;
11587           break;
11588         }
11589       codep++;
11590       vex.w = *codep & 0x80;
11591       if (address_mode == mode_64bit)
11592         {
11593           if (vex.w)
11594             rex |= REX_W;
11595         }
11596       else
11597         {
11598           /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
11599              is ignored, other REX bits are 0 and the highest bit in
11600              VEX.vvvv is also ignored (but we mustn't clear it here).  */
11601           rex = 0;
11602         }
11603       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11604       vex.length = (*codep & 0x4) ? 256 : 128;
11605       switch ((*codep & 0x3))
11606         {
11607         case 0:
11608           break;
11609         case 1:
11610           vex.prefix = DATA_PREFIX_OPCODE;
11611           break;
11612         case 2:
11613           vex.prefix = REPE_PREFIX_OPCODE;
11614           break;
11615         case 3:
11616           vex.prefix = REPNE_PREFIX_OPCODE;
11617           break;
11618         }
11619       need_vex = 1;
11620       need_vex_reg = 1;
11621       codep++;
11622       vindex = *codep++;
11623       dp = &vex_table[vex_table_index][vindex];
11624       end_codep = codep;
11625       /* There is no MODRM byte for VEX0F 77.  */
11626       if (vex_table_index != VEX_0F || vindex != 0x77)
11627         {
11628           FETCH_DATA (info, codep + 1);
11629           modrm.mod = (*codep >> 6) & 3;
11630           modrm.reg = (*codep >> 3) & 7;
11631           modrm.rm = *codep & 7;
11632         }
11633       break;
11634
11635     case USE_VEX_C5_TABLE:
11636       /* VEX prefix.  */
11637       FETCH_DATA (info, codep + 2);
11638       rex = (*codep & 0x80) ? 0 : REX_R;
11639
11640       /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
11641          VEX.vvvv is 1.  */
11642       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11643       vex.length = (*codep & 0x4) ? 256 : 128;
11644       switch ((*codep & 0x3))
11645         {
11646         case 0:
11647           break;
11648         case 1:
11649           vex.prefix = DATA_PREFIX_OPCODE;
11650           break;
11651         case 2:
11652           vex.prefix = REPE_PREFIX_OPCODE;
11653           break;
11654         case 3:
11655           vex.prefix = REPNE_PREFIX_OPCODE;
11656           break;
11657         }
11658       need_vex = 1;
11659       need_vex_reg = 1;
11660       codep++;
11661       vindex = *codep++;
11662       dp = &vex_table[dp->op[1].bytemode][vindex];
11663       end_codep = codep;
11664       /* There is no MODRM byte for VEX 77.  */
11665       if (vindex != 0x77)
11666         {
11667           FETCH_DATA (info, codep + 1);
11668           modrm.mod = (*codep >> 6) & 3;
11669           modrm.reg = (*codep >> 3) & 7;
11670           modrm.rm = *codep & 7;
11671         }
11672       break;
11673
11674     case USE_VEX_W_TABLE:
11675       if (!need_vex)
11676         abort ();
11677
11678       dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
11679       break;
11680
11681     case USE_EVEX_TABLE:
11682       two_source_ops = 0;
11683       /* EVEX prefix.  */
11684       vex.evex = 1;
11685       FETCH_DATA (info, codep + 4);
11686       /* The first byte after 0x62.  */
11687       rex = ~(*codep >> 5) & 0x7;
11688       vex.r = *codep & 0x10;
11689       switch ((*codep & 0xf))
11690         {
11691         default:
11692           return &bad_opcode;
11693         case 0x1:
11694           vex_table_index = EVEX_0F;
11695           break;
11696         case 0x2:
11697           vex_table_index = EVEX_0F38;
11698           break;
11699         case 0x3:
11700           vex_table_index = EVEX_0F3A;
11701           break;
11702         }
11703
11704       /* The second byte after 0x62.  */
11705       codep++;
11706       vex.w = *codep & 0x80;
11707       if (vex.w && address_mode == mode_64bit)
11708         rex |= REX_W;
11709
11710       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11711
11712       /* The U bit.  */
11713       if (!(*codep & 0x4))
11714         return &bad_opcode;
11715
11716       switch ((*codep & 0x3))
11717         {
11718         case 0:
11719           break;
11720         case 1:
11721           vex.prefix = DATA_PREFIX_OPCODE;
11722           break;
11723         case 2:
11724           vex.prefix = REPE_PREFIX_OPCODE;
11725           break;
11726         case 3:
11727           vex.prefix = REPNE_PREFIX_OPCODE;
11728           break;
11729         }
11730
11731       /* The third byte after 0x62.  */
11732       codep++;
11733
11734       /* Remember the static rounding bits.  */
11735       vex.ll = (*codep >> 5) & 3;
11736       vex.b = (*codep & 0x10) != 0;
11737
11738       vex.v = *codep & 0x8;
11739       vex.mask_register_specifier = *codep & 0x7;
11740       vex.zeroing = *codep & 0x80;
11741
11742       if (address_mode != mode_64bit)
11743         {
11744           /* In 16/32-bit mode silently ignore following bits.  */
11745           rex &= ~REX_B;
11746           vex.r = 1;
11747           vex.v = 1;
11748         }
11749
11750       need_vex = 1;
11751       need_vex_reg = 1;
11752       codep++;
11753       vindex = *codep++;
11754       dp = &evex_table[vex_table_index][vindex];
11755       end_codep = codep;
11756       FETCH_DATA (info, codep + 1);
11757       modrm.mod = (*codep >> 6) & 3;
11758       modrm.reg = (*codep >> 3) & 7;
11759       modrm.rm = *codep & 7;
11760
11761       /* Set vector length.  */
11762       if (modrm.mod == 3 && vex.b)
11763         vex.length = 512;
11764       else
11765         {
11766           switch (vex.ll)
11767             {
11768             case 0x0:
11769               vex.length = 128;
11770               break;
11771             case 0x1:
11772               vex.length = 256;
11773               break;
11774             case 0x2:
11775               vex.length = 512;
11776               break;
11777             default:
11778               return &bad_opcode;
11779             }
11780         }
11781       break;
11782
11783     case 0:
11784       dp = &bad_opcode;
11785       break;
11786
11787     default:
11788       abort ();
11789     }
11790
11791   if (dp->name != NULL)
11792     return dp;
11793   else
11794     return get_valid_dis386 (dp, info);
11795 }
11796
11797 static void
11798 get_sib (disassemble_info *info, int sizeflag)
11799 {
11800   /* If modrm.mod == 3, operand must be register.  */
11801   if (need_modrm
11802       && ((sizeflag & AFLAG) || address_mode == mode_64bit)
11803       && modrm.mod != 3
11804       && modrm.rm == 4)
11805     {
11806       FETCH_DATA (info, codep + 2);
11807       sib.index = (codep [1] >> 3) & 7;
11808       sib.scale = (codep [1] >> 6) & 3;
11809       sib.base = codep [1] & 7;
11810     }
11811 }
11812
11813 static int
11814 print_insn (bfd_vma pc, disassemble_info *info)
11815 {
11816   const struct dis386 *dp;
11817   int i;
11818   char *op_txt[MAX_OPERANDS];
11819   int needcomma;
11820   int sizeflag, orig_sizeflag;
11821   const char *p;
11822   struct dis_private priv;
11823   int prefix_length;
11824
11825   priv.orig_sizeflag = AFLAG | DFLAG;
11826   if ((info->mach & bfd_mach_i386_i386) != 0)
11827     address_mode = mode_32bit;
11828   else if (info->mach == bfd_mach_i386_i8086)
11829     {
11830       address_mode = mode_16bit;
11831       priv.orig_sizeflag = 0;
11832     }
11833   else
11834     address_mode = mode_64bit;
11835
11836   if (intel_syntax == (char) -1)
11837     intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0;
11838
11839   for (p = info->disassembler_options; p != NULL; )
11840     {
11841       if (CONST_STRNEQ (p, "amd64"))
11842         isa64 = amd64;
11843       else if (CONST_STRNEQ (p, "intel64"))
11844         isa64 = intel64;
11845       else if (CONST_STRNEQ (p, "x86-64"))
11846         {
11847           address_mode = mode_64bit;
11848           priv.orig_sizeflag |= AFLAG | DFLAG;
11849         }
11850       else if (CONST_STRNEQ (p, "i386"))
11851         {
11852           address_mode = mode_32bit;
11853           priv.orig_sizeflag |= AFLAG | DFLAG;
11854         }
11855       else if (CONST_STRNEQ (p, "i8086"))
11856         {
11857           address_mode = mode_16bit;
11858           priv.orig_sizeflag &= ~(AFLAG | DFLAG);
11859         }
11860       else if (CONST_STRNEQ (p, "intel"))
11861         {
11862           intel_syntax = 1;
11863           if (CONST_STRNEQ (p + 5, "-mnemonic"))
11864             intel_mnemonic = 1;
11865         }
11866       else if (CONST_STRNEQ (p, "att"))
11867         {
11868           intel_syntax = 0;
11869           if (CONST_STRNEQ (p + 3, "-mnemonic"))
11870             intel_mnemonic = 0;
11871         }
11872       else if (CONST_STRNEQ (p, "addr"))
11873         {
11874           if (address_mode == mode_64bit)
11875             {
11876               if (p[4] == '3' && p[5] == '2')
11877                 priv.orig_sizeflag &= ~AFLAG;
11878               else if (p[4] == '6' && p[5] == '4')
11879                 priv.orig_sizeflag |= AFLAG;
11880             }
11881           else
11882             {
11883               if (p[4] == '1' && p[5] == '6')
11884                 priv.orig_sizeflag &= ~AFLAG;
11885               else if (p[4] == '3' && p[5] == '2')
11886                 priv.orig_sizeflag |= AFLAG;
11887             }
11888         }
11889       else if (CONST_STRNEQ (p, "data"))
11890         {
11891           if (p[4] == '1' && p[5] == '6')
11892             priv.orig_sizeflag &= ~DFLAG;
11893           else if (p[4] == '3' && p[5] == '2')
11894             priv.orig_sizeflag |= DFLAG;
11895         }
11896       else if (CONST_STRNEQ (p, "suffix"))
11897         priv.orig_sizeflag |= SUFFIX_ALWAYS;
11898
11899       p = strchr (p, ',');
11900       if (p != NULL)
11901         p++;
11902     }
11903
11904   if (address_mode == mode_64bit && sizeof (bfd_vma) < 8)
11905     {
11906       (*info->fprintf_func) (info->stream,
11907                              _("64-bit address is disabled"));
11908       return -1;
11909     }
11910
11911   if (intel_syntax)
11912     {
11913       names64 = intel_names64;
11914       names32 = intel_names32;
11915       names16 = intel_names16;
11916       names8 = intel_names8;
11917       names8rex = intel_names8rex;
11918       names_seg = intel_names_seg;
11919       names_mm = intel_names_mm;
11920       names_bnd = intel_names_bnd;
11921       names_xmm = intel_names_xmm;
11922       names_ymm = intel_names_ymm;
11923       names_zmm = intel_names_zmm;
11924       index64 = intel_index64;
11925       index32 = intel_index32;
11926       names_mask = intel_names_mask;
11927       index16 = intel_index16;
11928       open_char = '[';
11929       close_char = ']';
11930       separator_char = '+';
11931       scale_char = '*';
11932     }
11933   else
11934     {
11935       names64 = att_names64;
11936       names32 = att_names32;
11937       names16 = att_names16;
11938       names8 = att_names8;
11939       names8rex = att_names8rex;
11940       names_seg = att_names_seg;
11941       names_mm = att_names_mm;
11942       names_bnd = att_names_bnd;
11943       names_xmm = att_names_xmm;
11944       names_ymm = att_names_ymm;
11945       names_zmm = att_names_zmm;
11946       index64 = att_index64;
11947       index32 = att_index32;
11948       names_mask = att_names_mask;
11949       index16 = att_index16;
11950       open_char = '(';
11951       close_char =  ')';
11952       separator_char = ',';
11953       scale_char = ',';
11954     }
11955
11956   /* The output looks better if we put 7 bytes on a line, since that
11957      puts most long word instructions on a single line.  Use 8 bytes
11958      for Intel L1OM.  */
11959   if ((info->mach & bfd_mach_l1om) != 0)
11960     info->bytes_per_line = 8;
11961   else
11962     info->bytes_per_line = 7;
11963
11964   info->private_data = &priv;
11965   priv.max_fetched = priv.the_buffer;
11966   priv.insn_start = pc;
11967
11968   obuf[0] = 0;
11969   for (i = 0; i < MAX_OPERANDS; ++i)
11970     {
11971       op_out[i][0] = 0;
11972       op_index[i] = -1;
11973     }
11974
11975   the_info = info;
11976   start_pc = pc;
11977   start_codep = priv.the_buffer;
11978   codep = priv.the_buffer;
11979
11980   if (OPCODES_SIGSETJMP (priv.bailout) != 0)
11981     {
11982       const char *name;
11983
11984       /* Getting here means we tried for data but didn't get it.  That
11985          means we have an incomplete instruction of some sort.  Just
11986          print the first byte as a prefix or a .byte pseudo-op.  */
11987       if (codep > priv.the_buffer)
11988         {
11989           name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
11990           if (name != NULL)
11991             (*info->fprintf_func) (info->stream, "%s", name);
11992           else
11993             {
11994               /* Just print the first byte as a .byte instruction.  */
11995               (*info->fprintf_func) (info->stream, ".byte 0x%x",
11996                                      (unsigned int) priv.the_buffer[0]);
11997             }
11998
11999           return 1;
12000         }
12001
12002       return -1;
12003     }
12004
12005   obufp = obuf;
12006   sizeflag = priv.orig_sizeflag;
12007
12008   if (!ckprefix () || rex_used)
12009     {
12010       /* Too many prefixes or unused REX prefixes.  */
12011       for (i = 0;
12012            i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i];
12013            i++)
12014         (*info->fprintf_func) (info->stream, "%s%s",
12015                                i == 0 ? "" : " ",
12016                                prefix_name (all_prefixes[i], sizeflag));
12017       return i;
12018     }
12019
12020   insn_codep = codep;
12021
12022   FETCH_DATA (info, codep + 1);
12023   two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
12024
12025   if (((prefixes & PREFIX_FWAIT)
12026        && ((*codep < 0xd8) || (*codep > 0xdf))))
12027     {
12028       /* Handle prefixes before fwait.  */
12029       for (i = 0; i < fwait_prefix && all_prefixes[i];
12030            i++)
12031         (*info->fprintf_func) (info->stream, "%s ",
12032                                prefix_name (all_prefixes[i], sizeflag));
12033       (*info->fprintf_func) (info->stream, "fwait");
12034       return i + 1;
12035     }
12036
12037   if (*codep == 0x0f)
12038     {
12039       unsigned char threebyte;
12040
12041       codep++;
12042       FETCH_DATA (info, codep + 1);
12043       threebyte = *codep;
12044       dp = &dis386_twobyte[threebyte];
12045       need_modrm = twobyte_has_modrm[*codep];
12046       codep++;
12047     }
12048   else
12049     {
12050       dp = &dis386[*codep];
12051       need_modrm = onebyte_has_modrm[*codep];
12052       codep++;
12053     }
12054
12055   /* Save sizeflag for printing the extra prefixes later before updating
12056      it for mnemonic and operand processing.  The prefix names depend
12057      only on the address mode.  */
12058   orig_sizeflag = sizeflag;
12059   if (prefixes & PREFIX_ADDR)
12060     sizeflag ^= AFLAG;
12061   if ((prefixes & PREFIX_DATA))
12062     sizeflag ^= DFLAG;
12063
12064   end_codep = codep;
12065   if (need_modrm)
12066     {
12067       FETCH_DATA (info, codep + 1);
12068       modrm.mod = (*codep >> 6) & 3;
12069       modrm.reg = (*codep >> 3) & 7;
12070       modrm.rm = *codep & 7;
12071     }
12072
12073   need_vex = 0;
12074   need_vex_reg = 0;
12075   vex_w_done = 0;
12076   memset (&vex, 0, sizeof (vex));
12077
12078   if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
12079     {
12080       get_sib (info, sizeflag);
12081       dofloat (sizeflag);
12082     }
12083   else
12084     {
12085       dp = get_valid_dis386 (dp, info);
12086       if (dp != NULL && putop (dp->name, sizeflag) == 0)
12087         {
12088           get_sib (info, sizeflag);
12089           for (i = 0; i < MAX_OPERANDS; ++i)
12090             {
12091               obufp = op_out[i];
12092               op_ad = MAX_OPERANDS - 1 - i;
12093               if (dp->op[i].rtn)
12094                 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
12095               /* For EVEX instruction after the last operand masking
12096                  should be printed.  */
12097               if (i == 0 && vex.evex)
12098                 {
12099                   /* Don't print {%k0}.  */
12100                   if (vex.mask_register_specifier)
12101                     {
12102                       oappend ("{");
12103                       oappend (names_mask[vex.mask_register_specifier]);
12104                       oappend ("}");
12105                     }
12106                   if (vex.zeroing)
12107                     oappend ("{z}");
12108                 }
12109             }
12110         }
12111     }
12112
12113   /* Clear instruction information.  */
12114   if (the_info)
12115     {
12116       the_info->insn_info_valid = 0;
12117       the_info->branch_delay_insns = 0;
12118       the_info->data_size = 0;
12119       the_info->insn_type = dis_noninsn;
12120       the_info->target = 0;
12121       the_info->target2 = 0;
12122     }
12123
12124   /* Reset jump operation indicator.  */
12125   op_is_jump = FALSE;
12126
12127   {
12128     int jump_detection = 0;
12129
12130     /* Extract flags.  */
12131     for (i = 0; i < MAX_OPERANDS; ++i)
12132       {
12133         if ((dp->op[i].rtn == OP_J)
12134             || (dp->op[i].rtn == OP_indirE))
12135           jump_detection |= 1;
12136         else if ((dp->op[i].rtn == BND_Fixup)
12137                  || (!dp->op[i].rtn && !dp->op[i].bytemode))
12138           jump_detection |= 2;
12139         else if ((dp->op[i].bytemode == cond_jump_mode)
12140                  || (dp->op[i].bytemode == loop_jcxz_mode))
12141           jump_detection |= 4;
12142       }
12143
12144     /* Determine if this is a jump or branch.  */
12145     if ((jump_detection & 0x3) == 0x3)
12146       {
12147         op_is_jump = TRUE;
12148         if (jump_detection & 0x4)
12149           the_info->insn_type = dis_condbranch;
12150         else
12151           the_info->insn_type =
12152             (dp->name && !strncmp(dp->name, "call", 4))
12153             ? dis_jsr : dis_branch;
12154       }
12155   }
12156
12157   /* If VEX.vvvv and EVEX.vvvv are unused, they must be all 1s, which
12158      are all 0s in inverted form.  */
12159   if (need_vex && vex.register_specifier != 0)
12160     {
12161       (*info->fprintf_func) (info->stream, "(bad)");
12162       return end_codep - priv.the_buffer;
12163     }
12164
12165   /* Check if the REX prefix is used.  */
12166   if ((rex ^ rex_used) == 0 && !need_vex && last_rex_prefix >= 0)
12167     all_prefixes[last_rex_prefix] = 0;
12168
12169   /* Check if the SEG prefix is used.  */
12170   if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
12171                    | PREFIX_FS | PREFIX_GS)) != 0
12172       && (used_prefixes & active_seg_prefix) != 0)
12173     all_prefixes[last_seg_prefix] = 0;
12174
12175   /* Check if the ADDR prefix is used.  */
12176   if ((prefixes & PREFIX_ADDR) != 0
12177       && (used_prefixes & PREFIX_ADDR) != 0)
12178     all_prefixes[last_addr_prefix] = 0;
12179
12180   /* Check if the DATA prefix is used.  */
12181   if ((prefixes & PREFIX_DATA) != 0
12182       && (used_prefixes & PREFIX_DATA) != 0
12183       && !need_vex)
12184     all_prefixes[last_data_prefix] = 0;
12185
12186   /* Print the extra prefixes.  */
12187   prefix_length = 0;
12188   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
12189     if (all_prefixes[i])
12190       {
12191         const char *name;
12192         name = prefix_name (all_prefixes[i], orig_sizeflag);
12193         if (name == NULL)
12194           abort ();
12195         prefix_length += strlen (name) + 1;
12196         (*info->fprintf_func) (info->stream, "%s ", name);
12197       }
12198
12199   /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
12200      unused, opcode is invalid.  Since the PREFIX_DATA prefix may be
12201      used by putop and MMX/SSE operand and may be overriden by the
12202      PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
12203      separately.  */
12204   if (dp->prefix_requirement == PREFIX_OPCODE
12205       && (((need_vex
12206             ? vex.prefix == REPE_PREFIX_OPCODE
12207               || vex.prefix == REPNE_PREFIX_OPCODE
12208             : (prefixes
12209                & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
12210            && (used_prefixes
12211                & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
12212           || (((need_vex
12213                 ? vex.prefix == DATA_PREFIX_OPCODE
12214                 : ((prefixes
12215                     & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
12216                    == PREFIX_DATA))
12217                && (used_prefixes & PREFIX_DATA) == 0))
12218           || (vex.evex && !vex.w != !(used_prefixes & PREFIX_DATA))))
12219     {
12220       (*info->fprintf_func) (info->stream, "(bad)");
12221       return end_codep - priv.the_buffer;
12222     }
12223
12224   /* Check maximum code length.  */
12225   if ((codep - start_codep) > MAX_CODE_LENGTH)
12226     {
12227       (*info->fprintf_func) (info->stream, "(bad)");
12228       return MAX_CODE_LENGTH;
12229     }
12230
12231   obufp = mnemonicendp;
12232   for (i = strlen (obuf) + prefix_length; i < 6; i++)
12233     oappend (" ");
12234   oappend (" ");
12235   (*info->fprintf_func) (info->stream, "%s", obuf);
12236
12237   /* The enter and bound instructions are printed with operands in the same
12238      order as the intel book; everything else is printed in reverse order.  */
12239   if (intel_syntax || two_source_ops)
12240     {
12241       bfd_vma riprel;
12242
12243       for (i = 0; i < MAX_OPERANDS; ++i)
12244         op_txt[i] = op_out[i];
12245
12246       if (intel_syntax && dp && dp->op[2].rtn == OP_Rounding
12247           && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL)
12248         {
12249           op_txt[2] = op_out[3];
12250           op_txt[3] = op_out[2];
12251         }
12252
12253       for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
12254         {
12255           op_ad = op_index[i];
12256           op_index[i] = op_index[MAX_OPERANDS - 1 - i];
12257           op_index[MAX_OPERANDS - 1 - i] = op_ad;
12258           riprel = op_riprel[i];
12259           op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
12260           op_riprel[MAX_OPERANDS - 1 - i] = riprel;
12261         }
12262     }
12263   else
12264     {
12265       for (i = 0; i < MAX_OPERANDS; ++i)
12266         op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
12267     }
12268
12269   needcomma = 0;
12270   for (i = 0; i < MAX_OPERANDS; ++i)
12271     if (*op_txt[i])
12272       {
12273         if (needcomma)
12274           (*info->fprintf_func) (info->stream, ",");
12275         if (op_index[i] != -1 && !op_riprel[i])
12276           {
12277             bfd_vma target = (bfd_vma) op_address[op_index[i]];
12278
12279             if (the_info && op_is_jump)
12280               {
12281                 the_info->insn_info_valid = 1;
12282                 the_info->branch_delay_insns = 0;
12283                 the_info->data_size = 0;
12284                 the_info->target = target;
12285                 the_info->target2 = 0;
12286               }
12287             (*info->print_address_func) (target, info);
12288           }
12289         else
12290           (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
12291         needcomma = 1;
12292       }
12293
12294   for (i = 0; i < MAX_OPERANDS; i++)
12295     if (op_index[i] != -1 && op_riprel[i])
12296       {
12297         (*info->fprintf_func) (info->stream, "        # ");
12298         (*info->print_address_func) ((bfd_vma) (start_pc + (codep - start_codep)
12299                                                 + op_address[op_index[i]]), info);
12300         break;
12301       }
12302   return codep - priv.the_buffer;
12303 }
12304
12305 static const char *float_mem[] = {
12306   /* d8 */
12307   "fadd{s|}",
12308   "fmul{s|}",
12309   "fcom{s|}",
12310   "fcomp{s|}",
12311   "fsub{s|}",
12312   "fsubr{s|}",
12313   "fdiv{s|}",
12314   "fdivr{s|}",
12315   /* d9 */
12316   "fld{s|}",
12317   "(bad)",
12318   "fst{s|}",
12319   "fstp{s|}",
12320   "fldenv{C|C}",
12321   "fldcw",
12322   "fNstenv{C|C}",
12323   "fNstcw",
12324   /* da */
12325   "fiadd{l|}",
12326   "fimul{l|}",
12327   "ficom{l|}",
12328   "ficomp{l|}",
12329   "fisub{l|}",
12330   "fisubr{l|}",
12331   "fidiv{l|}",
12332   "fidivr{l|}",
12333   /* db */
12334   "fild{l|}",
12335   "fisttp{l|}",
12336   "fist{l|}",
12337   "fistp{l|}",
12338   "(bad)",
12339   "fld{t|}",
12340   "(bad)",
12341   "fstp{t|}",
12342   /* dc */
12343   "fadd{l|}",
12344   "fmul{l|}",
12345   "fcom{l|}",
12346   "fcomp{l|}",
12347   "fsub{l|}",
12348   "fsubr{l|}",
12349   "fdiv{l|}",
12350   "fdivr{l|}",
12351   /* dd */
12352   "fld{l|}",
12353   "fisttp{ll|}",
12354   "fst{l||}",
12355   "fstp{l|}",
12356   "frstor{C|C}",
12357   "(bad)",
12358   "fNsave{C|C}",
12359   "fNstsw",
12360   /* de */
12361   "fiadd{s|}",
12362   "fimul{s|}",
12363   "ficom{s|}",
12364   "ficomp{s|}",
12365   "fisub{s|}",
12366   "fisubr{s|}",
12367   "fidiv{s|}",
12368   "fidivr{s|}",
12369   /* df */
12370   "fild{s|}",
12371   "fisttp{s|}",
12372   "fist{s|}",
12373   "fistp{s|}",
12374   "fbld",
12375   "fild{ll|}",
12376   "fbstp",
12377   "fistp{ll|}",
12378 };
12379
12380 static const unsigned char float_mem_mode[] = {
12381   /* d8 */
12382   d_mode,
12383   d_mode,
12384   d_mode,
12385   d_mode,
12386   d_mode,
12387   d_mode,
12388   d_mode,
12389   d_mode,
12390   /* d9 */
12391   d_mode,
12392   0,
12393   d_mode,
12394   d_mode,
12395   0,
12396   w_mode,
12397   0,
12398   w_mode,
12399   /* da */
12400   d_mode,
12401   d_mode,
12402   d_mode,
12403   d_mode,
12404   d_mode,
12405   d_mode,
12406   d_mode,
12407   d_mode,
12408   /* db */
12409   d_mode,
12410   d_mode,
12411   d_mode,
12412   d_mode,
12413   0,
12414   t_mode,
12415   0,
12416   t_mode,
12417   /* dc */
12418   q_mode,
12419   q_mode,
12420   q_mode,
12421   q_mode,
12422   q_mode,
12423   q_mode,
12424   q_mode,
12425   q_mode,
12426   /* dd */
12427   q_mode,
12428   q_mode,
12429   q_mode,
12430   q_mode,
12431   0,
12432   0,
12433   0,
12434   w_mode,
12435   /* de */
12436   w_mode,
12437   w_mode,
12438   w_mode,
12439   w_mode,
12440   w_mode,
12441   w_mode,
12442   w_mode,
12443   w_mode,
12444   /* df */
12445   w_mode,
12446   w_mode,
12447   w_mode,
12448   w_mode,
12449   t_mode,
12450   q_mode,
12451   t_mode,
12452   q_mode
12453 };
12454
12455 #define ST { OP_ST, 0 }
12456 #define STi { OP_STi, 0 }
12457
12458 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
12459 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
12460 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
12461 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
12462 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
12463 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
12464 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
12465 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
12466 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
12467
12468 static const struct dis386 float_reg[][8] = {
12469   /* d8 */
12470   {
12471     { "fadd",   { ST, STi }, 0 },
12472     { "fmul",   { ST, STi }, 0 },
12473     { "fcom",   { STi }, 0 },
12474     { "fcomp",  { STi }, 0 },
12475     { "fsub",   { ST, STi }, 0 },
12476     { "fsubr",  { ST, STi }, 0 },
12477     { "fdiv",   { ST, STi }, 0 },
12478     { "fdivr",  { ST, STi }, 0 },
12479   },
12480   /* d9 */
12481   {
12482     { "fld",    { STi }, 0 },
12483     { "fxch",   { STi }, 0 },
12484     { FGRPd9_2 },
12485     { Bad_Opcode },
12486     { FGRPd9_4 },
12487     { FGRPd9_5 },
12488     { FGRPd9_6 },
12489     { FGRPd9_7 },
12490   },
12491   /* da */
12492   {
12493     { "fcmovb", { ST, STi }, 0 },
12494     { "fcmove", { ST, STi }, 0 },
12495     { "fcmovbe",{ ST, STi }, 0 },
12496     { "fcmovu", { ST, STi }, 0 },
12497     { Bad_Opcode },
12498     { FGRPda_5 },
12499     { Bad_Opcode },
12500     { Bad_Opcode },
12501   },
12502   /* db */
12503   {
12504     { "fcmovnb",{ ST, STi }, 0 },
12505     { "fcmovne",{ ST, STi }, 0 },
12506     { "fcmovnbe",{ ST, STi }, 0 },
12507     { "fcmovnu",{ ST, STi }, 0 },
12508     { FGRPdb_4 },
12509     { "fucomi", { ST, STi }, 0 },
12510     { "fcomi",  { ST, STi }, 0 },
12511     { Bad_Opcode },
12512   },
12513   /* dc */
12514   {
12515     { "fadd",   { STi, ST }, 0 },
12516     { "fmul",   { STi, ST }, 0 },
12517     { Bad_Opcode },
12518     { Bad_Opcode },
12519     { "fsub{!M|r}",     { STi, ST }, 0 },
12520     { "fsub{M|}",       { STi, ST }, 0 },
12521     { "fdiv{!M|r}",     { STi, ST }, 0 },
12522     { "fdiv{M|}",       { STi, ST }, 0 },
12523   },
12524   /* dd */
12525   {
12526     { "ffree",  { STi }, 0 },
12527     { Bad_Opcode },
12528     { "fst",    { STi }, 0 },
12529     { "fstp",   { STi }, 0 },
12530     { "fucom",  { STi }, 0 },
12531     { "fucomp", { STi }, 0 },
12532     { Bad_Opcode },
12533     { Bad_Opcode },
12534   },
12535   /* de */
12536   {
12537     { "faddp",  { STi, ST }, 0 },
12538     { "fmulp",  { STi, ST }, 0 },
12539     { Bad_Opcode },
12540     { FGRPde_3 },
12541     { "fsub{!M|r}p",    { STi, ST }, 0 },
12542     { "fsub{M|}p",      { STi, ST }, 0 },
12543     { "fdiv{!M|r}p",    { STi, ST }, 0 },
12544     { "fdiv{M|}p",      { STi, ST }, 0 },
12545   },
12546   /* df */
12547   {
12548     { "ffreep", { STi }, 0 },
12549     { Bad_Opcode },
12550     { Bad_Opcode },
12551     { Bad_Opcode },
12552     { FGRPdf_4 },
12553     { "fucomip", { ST, STi }, 0 },
12554     { "fcomip", { ST, STi }, 0 },
12555     { Bad_Opcode },
12556   },
12557 };
12558
12559 static char *fgrps[][8] = {
12560   /* Bad opcode 0 */
12561   {
12562     "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12563   },
12564
12565   /* d9_2  1 */
12566   {
12567     "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12568   },
12569
12570   /* d9_4  2 */
12571   {
12572     "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
12573   },
12574
12575   /* d9_5  3 */
12576   {
12577     "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
12578   },
12579
12580   /* d9_6  4 */
12581   {
12582     "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
12583   },
12584
12585   /* d9_7  5 */
12586   {
12587     "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
12588   },
12589
12590   /* da_5  6 */
12591   {
12592     "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12593   },
12594
12595   /* db_4  7 */
12596   {
12597     "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
12598     "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
12599   },
12600
12601   /* de_3  8 */
12602   {
12603     "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12604   },
12605
12606   /* df_4  9 */
12607   {
12608     "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12609   },
12610 };
12611
12612 static void
12613 swap_operand (void)
12614 {
12615   mnemonicendp[0] = '.';
12616   mnemonicendp[1] = 's';
12617   mnemonicendp += 2;
12618 }
12619
12620 static void
12621 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
12622                int sizeflag ATTRIBUTE_UNUSED)
12623 {
12624   /* Skip mod/rm byte.  */
12625   MODRM_CHECK;
12626   codep++;
12627 }
12628
12629 static void
12630 dofloat (int sizeflag)
12631 {
12632   const struct dis386 *dp;
12633   unsigned char floatop;
12634
12635   floatop = codep[-1];
12636
12637   if (modrm.mod != 3)
12638     {
12639       int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
12640
12641       putop (float_mem[fp_indx], sizeflag);
12642       obufp = op_out[0];
12643       op_ad = 2;
12644       OP_E (float_mem_mode[fp_indx], sizeflag);
12645       return;
12646     }
12647   /* Skip mod/rm byte.  */
12648   MODRM_CHECK;
12649   codep++;
12650
12651   dp = &float_reg[floatop - 0xd8][modrm.reg];
12652   if (dp->name == NULL)
12653     {
12654       putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
12655
12656       /* Instruction fnstsw is only one with strange arg.  */
12657       if (floatop == 0xdf && codep[-1] == 0xe0)
12658         strcpy (op_out[0], names16[0]);
12659     }
12660   else
12661     {
12662       putop (dp->name, sizeflag);
12663
12664       obufp = op_out[0];
12665       op_ad = 2;
12666       if (dp->op[0].rtn)
12667         (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
12668
12669       obufp = op_out[1];
12670       op_ad = 1;
12671       if (dp->op[1].rtn)
12672         (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
12673     }
12674 }
12675
12676 /* Like oappend (below), but S is a string starting with '%'.
12677    In Intel syntax, the '%' is elided.  */
12678 static void
12679 oappend_maybe_intel (const char *s)
12680 {
12681   oappend (s + intel_syntax);
12682 }
12683
12684 static void
12685 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12686 {
12687   oappend_maybe_intel ("%st");
12688 }
12689
12690 static void
12691 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12692 {
12693   sprintf (scratchbuf, "%%st(%d)", modrm.rm);
12694   oappend_maybe_intel (scratchbuf);
12695 }
12696
12697 /* Capital letters in template are macros.  */
12698 static int
12699 putop (const char *in_template, int sizeflag)
12700 {
12701   const char *p;
12702   int alt = 0;
12703   int cond = 1;
12704   unsigned int l = 0, len = 1;
12705   char last[4];
12706
12707 #define SAVE_LAST(c)                    \
12708   if (l < len && l < sizeof (last))     \
12709     last[l++] = c;                      \
12710   else                                  \
12711     abort ();
12712
12713   for (p = in_template; *p; p++)
12714     {
12715       switch (*p)
12716         {
12717         default:
12718           *obufp++ = *p;
12719           break;
12720         case '%':
12721           len++;
12722           break;
12723         case '!':
12724           cond = 0;
12725           break;
12726         case '{':
12727           if (intel_syntax)
12728             {
12729               while (*++p != '|')
12730                 if (*p == '}' || *p == '\0')
12731                   abort ();
12732               alt = 1;
12733             }
12734           break;
12735         case '|':
12736           while (*++p != '}')
12737             {
12738               if (*p == '\0')
12739                 abort ();
12740             }
12741           break;
12742         case '}':
12743           alt = 0;
12744           break;
12745         case 'A':
12746           if (intel_syntax)
12747             break;
12748           if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
12749             *obufp++ = 'b';
12750           break;
12751         case 'B':
12752           if (l == 0 && len == 1)
12753             {
12754             case_B:
12755               if (intel_syntax)
12756                 break;
12757               if (sizeflag & SUFFIX_ALWAYS)
12758                 *obufp++ = 'b';
12759             }
12760           else
12761             {
12762               if (l != 1
12763                   || len != 2
12764                   || last[0] != 'L')
12765                 {
12766                   SAVE_LAST (*p);
12767                   break;
12768                 }
12769
12770               if (address_mode == mode_64bit
12771                   && !(prefixes & PREFIX_ADDR))
12772                 {
12773                   *obufp++ = 'a';
12774                   *obufp++ = 'b';
12775                   *obufp++ = 's';
12776                 }
12777
12778               goto case_B;
12779             }
12780           break;
12781         case 'C':
12782           if (intel_syntax && !alt)
12783             break;
12784           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
12785             {
12786               if (sizeflag & DFLAG)
12787                 *obufp++ = intel_syntax ? 'd' : 'l';
12788               else
12789                 *obufp++ = intel_syntax ? 'w' : 's';
12790               used_prefixes |= (prefixes & PREFIX_DATA);
12791             }
12792           break;
12793         case 'D':
12794           if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
12795             break;
12796           USED_REX (REX_W);
12797           if (modrm.mod == 3)
12798             {
12799               if (rex & REX_W)
12800                 *obufp++ = 'q';
12801               else
12802                 {
12803                   if (sizeflag & DFLAG)
12804                     *obufp++ = intel_syntax ? 'd' : 'l';
12805                   else
12806                     *obufp++ = 'w';
12807                   used_prefixes |= (prefixes & PREFIX_DATA);
12808                 }
12809             }
12810           else
12811             *obufp++ = 'w';
12812           break;
12813         case 'E':               /* For jcxz/jecxz */
12814           if (address_mode == mode_64bit)
12815             {
12816               if (sizeflag & AFLAG)
12817                 *obufp++ = 'r';
12818               else
12819                 *obufp++ = 'e';
12820             }
12821           else
12822             if (sizeflag & AFLAG)
12823               *obufp++ = 'e';
12824           used_prefixes |= (prefixes & PREFIX_ADDR);
12825           break;
12826         case 'F':
12827           if (intel_syntax)
12828             break;
12829           if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
12830             {
12831               if (sizeflag & AFLAG)
12832                 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
12833               else
12834                 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
12835               used_prefixes |= (prefixes & PREFIX_ADDR);
12836             }
12837           break;
12838         case 'G':
12839           if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
12840             break;
12841           if ((rex & REX_W) || (sizeflag & DFLAG))
12842             *obufp++ = 'l';
12843           else
12844             *obufp++ = 'w';
12845           if (!(rex & REX_W))
12846             used_prefixes |= (prefixes & PREFIX_DATA);
12847           break;
12848         case 'H':
12849           if (intel_syntax)
12850             break;
12851           if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
12852               || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
12853             {
12854               used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
12855               *obufp++ = ',';
12856               *obufp++ = 'p';
12857               if (prefixes & PREFIX_DS)
12858                 *obufp++ = 't';
12859               else
12860                 *obufp++ = 'n';
12861             }
12862           break;
12863         case 'K':
12864           USED_REX (REX_W);
12865           if (rex & REX_W)
12866             *obufp++ = 'q';
12867           else
12868             *obufp++ = 'd';
12869           break;
12870         case 'Z':
12871           if (l != 0 || len != 1)
12872             {
12873               if (l != 1 || len != 2 || last[0] != 'X')
12874                 {
12875                   SAVE_LAST (*p);
12876                   break;
12877                 }
12878               if (!need_vex || !vex.evex)
12879                 abort ();
12880               if (intel_syntax
12881                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
12882                 break;
12883               switch (vex.length)
12884                 {
12885                 case 128:
12886                   *obufp++ = 'x';
12887                   break;
12888                 case 256:
12889                   *obufp++ = 'y';
12890                   break;
12891                 case 512:
12892                   *obufp++ = 'z';
12893                   break;
12894                 default:
12895                   abort ();
12896                 }
12897               break;
12898             }
12899           if (intel_syntax)
12900             break;
12901           if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
12902             {
12903               *obufp++ = 'q';
12904               break;
12905             }
12906           /* Fall through.  */
12907           goto case_L;
12908         case 'L':
12909           if (l != 0 || len != 1)
12910             {
12911               SAVE_LAST (*p);
12912               break;
12913             }
12914         case_L:
12915           if (intel_syntax)
12916             break;
12917           if (sizeflag & SUFFIX_ALWAYS)
12918             *obufp++ = 'l';
12919           break;
12920         case 'M':
12921           if (intel_mnemonic != cond)
12922             *obufp++ = 'r';
12923           break;
12924         case 'N':
12925           if ((prefixes & PREFIX_FWAIT) == 0)
12926             *obufp++ = 'n';
12927           else
12928             used_prefixes |= PREFIX_FWAIT;
12929           break;
12930         case 'O':
12931           USED_REX (REX_W);
12932           if (rex & REX_W)
12933             *obufp++ = 'o';
12934           else if (intel_syntax && (sizeflag & DFLAG))
12935             *obufp++ = 'q';
12936           else
12937             *obufp++ = 'd';
12938           if (!(rex & REX_W))
12939             used_prefixes |= (prefixes & PREFIX_DATA);
12940           break;
12941         case '&':
12942           if (!intel_syntax
12943               && address_mode == mode_64bit
12944               && isa64 == intel64)
12945             {
12946               *obufp++ = 'q';
12947               break;
12948             }
12949           /* Fall through.  */
12950         case 'T':
12951           if (!intel_syntax
12952               && address_mode == mode_64bit
12953               && ((sizeflag & DFLAG) || (rex & REX_W)))
12954             {
12955               *obufp++ = 'q';
12956               break;
12957             }
12958           /* Fall through.  */
12959           goto case_P;
12960         case 'P':
12961           if (l == 0 && len == 1)
12962             {
12963             case_P:
12964               if (intel_syntax)
12965                 {
12966                   if ((rex & REX_W) == 0
12967                       && (prefixes & PREFIX_DATA))
12968                     {
12969                       if ((sizeflag & DFLAG) == 0)
12970                         *obufp++ = 'w';
12971                       used_prefixes |= (prefixes & PREFIX_DATA);
12972                     }
12973                   break;
12974                 }
12975               if ((prefixes & PREFIX_DATA)
12976                   || (rex & REX_W)
12977                   || (sizeflag & SUFFIX_ALWAYS))
12978                 {
12979                   USED_REX (REX_W);
12980                   if (rex & REX_W)
12981                     *obufp++ = 'q';
12982                   else
12983                     {
12984                       if (sizeflag & DFLAG)
12985                         *obufp++ = 'l';
12986                       else
12987                         *obufp++ = 'w';
12988                       used_prefixes |= (prefixes & PREFIX_DATA);
12989                     }
12990                 }
12991             }
12992           else
12993             {
12994               if (l != 1 || len != 2 || last[0] != 'L')
12995                 {
12996                   SAVE_LAST (*p);
12997                   break;
12998                 }
12999
13000               if ((prefixes & PREFIX_DATA)
13001                   || (rex & REX_W)
13002                   || (sizeflag & SUFFIX_ALWAYS))
13003                 {
13004                   USED_REX (REX_W);
13005                   if (rex & REX_W)
13006                     *obufp++ = 'q';
13007                   else
13008                     {
13009                       if (sizeflag & DFLAG)
13010                         *obufp++ = intel_syntax ? 'd' : 'l';
13011                       else
13012                         *obufp++ = 'w';
13013                       used_prefixes |= (prefixes & PREFIX_DATA);
13014                     }
13015                 }
13016             }
13017           break;
13018         case 'U':
13019           if (intel_syntax)
13020             break;
13021           if (address_mode == mode_64bit
13022               && ((sizeflag & DFLAG) || (rex & REX_W)))
13023             {
13024               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13025                 *obufp++ = 'q';
13026               break;
13027             }
13028           /* Fall through.  */
13029           goto case_Q;
13030         case 'Q':
13031           if (l == 0 && len == 1)
13032             {
13033             case_Q:
13034               if (intel_syntax && !alt)
13035                 break;
13036               USED_REX (REX_W);
13037               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13038                 {
13039                   if (rex & REX_W)
13040                     *obufp++ = 'q';
13041                   else
13042                     {
13043                       if (sizeflag & DFLAG)
13044                         *obufp++ = intel_syntax ? 'd' : 'l';
13045                       else
13046                         *obufp++ = 'w';
13047                       used_prefixes |= (prefixes & PREFIX_DATA);
13048                     }
13049                 }
13050             }
13051           else
13052             {
13053               if (l != 1 || len != 2 || last[0] != 'L')
13054                 {
13055                   SAVE_LAST (*p);
13056                   break;
13057                 }
13058               if ((intel_syntax && need_modrm)
13059                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
13060                 break;
13061               if ((rex & REX_W))
13062                 {
13063                   USED_REX (REX_W);
13064                   *obufp++ = 'q';
13065                 }
13066               else if((address_mode == mode_64bit && need_modrm)
13067                       || (sizeflag & SUFFIX_ALWAYS))
13068                 *obufp++ = intel_syntax? 'd' : 'l';
13069             }
13070           break;
13071         case 'R':
13072           USED_REX (REX_W);
13073           if (rex & REX_W)
13074             *obufp++ = 'q';
13075           else if (sizeflag & DFLAG)
13076             {
13077               if (intel_syntax)
13078                   *obufp++ = 'd';
13079               else
13080                   *obufp++ = 'l';
13081             }
13082           else
13083             *obufp++ = 'w';
13084           if (intel_syntax && !p[1]
13085               && ((rex & REX_W) || (sizeflag & DFLAG)))
13086             *obufp++ = 'e';
13087           if (!(rex & REX_W))
13088             used_prefixes |= (prefixes & PREFIX_DATA);
13089           break;
13090         case 'V':
13091           if (l == 0 && len == 1)
13092             {
13093               if (intel_syntax)
13094                 break;
13095               if (address_mode == mode_64bit
13096                   && ((sizeflag & DFLAG) || (rex & REX_W)))
13097                 {
13098                   if (sizeflag & SUFFIX_ALWAYS)
13099                     *obufp++ = 'q';
13100                   break;
13101                 }
13102             }
13103           else
13104             {
13105               if (l != 1
13106                   || len != 2
13107                   || last[0] != 'L')
13108                 {
13109                   SAVE_LAST (*p);
13110                   break;
13111                 }
13112
13113               if (rex & REX_W)
13114                 {
13115                   *obufp++ = 'a';
13116                   *obufp++ = 'b';
13117                   *obufp++ = 's';
13118                 }
13119             }
13120           /* Fall through.  */
13121           goto case_S;
13122         case 'S':
13123           if (l == 0 && len == 1)
13124             {
13125             case_S:
13126               if (intel_syntax)
13127                 break;
13128               if (sizeflag & SUFFIX_ALWAYS)
13129                 {
13130                   if (rex & REX_W)
13131                     *obufp++ = 'q';
13132                   else
13133                     {
13134                       if (sizeflag & DFLAG)
13135                         *obufp++ = 'l';
13136                       else
13137                         *obufp++ = 'w';
13138                       used_prefixes |= (prefixes & PREFIX_DATA);
13139                     }
13140                 }
13141             }
13142           else
13143             {
13144               if (l != 1
13145                   || len != 2
13146                   || last[0] != 'L')
13147                 {
13148                   SAVE_LAST (*p);
13149                   break;
13150                 }
13151
13152               if (address_mode == mode_64bit
13153                   && !(prefixes & PREFIX_ADDR))
13154                 {
13155                   *obufp++ = 'a';
13156                   *obufp++ = 'b';
13157                   *obufp++ = 's';
13158                 }
13159
13160               goto case_S;
13161             }
13162           break;
13163         case 'X':
13164           if (l != 0 || len != 1)
13165             {
13166               SAVE_LAST (*p);
13167               break;
13168             }
13169           if (need_vex
13170               ? vex.prefix == DATA_PREFIX_OPCODE
13171               : prefixes & PREFIX_DATA)
13172             {
13173               *obufp++ = 'd';
13174               used_prefixes |= PREFIX_DATA;
13175             }
13176           else
13177             *obufp++ = 's';
13178           break;
13179         case 'Y':
13180           if (l == 0 && len == 1)
13181             abort ();
13182           else
13183             {
13184               if (l != 1 || len != 2 || last[0] != 'X')
13185                 {
13186                   SAVE_LAST (*p);
13187                   break;
13188                 }
13189               if (!need_vex)
13190                 abort ();
13191               if (intel_syntax
13192                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
13193                 break;
13194               switch (vex.length)
13195                 {
13196                 case 128:
13197                   *obufp++ = 'x';
13198                   break;
13199                 case 256:
13200                   *obufp++ = 'y';
13201                   break;
13202                 case 512:
13203                   if (!vex.evex)
13204                 default:
13205                     abort ();
13206                 }
13207             }
13208           break;
13209         case 'W':
13210           if (l == 0 && len == 1)
13211             {
13212               /* operand size flag for cwtl, cbtw */
13213               USED_REX (REX_W);
13214               if (rex & REX_W)
13215                 {
13216                   if (intel_syntax)
13217                     *obufp++ = 'd';
13218                   else
13219                     *obufp++ = 'l';
13220                 }
13221               else if (sizeflag & DFLAG)
13222                 *obufp++ = 'w';
13223               else
13224                 *obufp++ = 'b';
13225               if (!(rex & REX_W))
13226                 used_prefixes |= (prefixes & PREFIX_DATA);
13227             }
13228           else
13229             {
13230               if (l != 1
13231                   || len != 2
13232                   || (last[0] != 'X'
13233                       && last[0] != 'L'))
13234                 {
13235                   SAVE_LAST (*p);
13236                   break;
13237                 }
13238               if (!need_vex)
13239                 abort ();
13240               if (last[0] == 'X')
13241                 *obufp++ = vex.w ? 'd': 's';
13242               else
13243                 *obufp++ = vex.w ? 'q': 'd';
13244             }
13245           break;
13246         case '^':
13247           if (intel_syntax)
13248             break;
13249           if (isa64 == intel64 && (rex & REX_W))
13250             {
13251               USED_REX (REX_W);
13252               *obufp++ = 'q';
13253               break;
13254             }
13255           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
13256             {
13257               if (sizeflag & DFLAG)
13258                 *obufp++ = 'l';
13259               else
13260                 *obufp++ = 'w';
13261               used_prefixes |= (prefixes & PREFIX_DATA);
13262             }
13263           break;
13264         case '@':
13265           if (intel_syntax)
13266             break;
13267           if (address_mode == mode_64bit
13268               && (isa64 == intel64
13269                   || ((sizeflag & DFLAG) || (rex & REX_W))))
13270               *obufp++ = 'q';
13271           else if ((prefixes & PREFIX_DATA))
13272             {
13273               if (!(sizeflag & DFLAG))
13274                 *obufp++ = 'w';
13275               used_prefixes |= (prefixes & PREFIX_DATA);
13276             }
13277           break;
13278         }
13279     }
13280   *obufp = 0;
13281   mnemonicendp = obufp;
13282   return 0;
13283 }
13284
13285 static void
13286 oappend (const char *s)
13287 {
13288   obufp = stpcpy (obufp, s);
13289 }
13290
13291 static void
13292 append_seg (void)
13293 {
13294   /* Only print the active segment register.  */
13295   if (!active_seg_prefix)
13296     return;
13297
13298   used_prefixes |= active_seg_prefix;
13299   switch (active_seg_prefix)
13300     {
13301     case PREFIX_CS:
13302       oappend_maybe_intel ("%cs:");
13303       break;
13304     case PREFIX_DS:
13305       oappend_maybe_intel ("%ds:");
13306       break;
13307     case PREFIX_SS:
13308       oappend_maybe_intel ("%ss:");
13309       break;
13310     case PREFIX_ES:
13311       oappend_maybe_intel ("%es:");
13312       break;
13313     case PREFIX_FS:
13314       oappend_maybe_intel ("%fs:");
13315       break;
13316     case PREFIX_GS:
13317       oappend_maybe_intel ("%gs:");
13318       break;
13319     default:
13320       break;
13321     }
13322 }
13323
13324 static void
13325 OP_indirE (int bytemode, int sizeflag)
13326 {
13327   if (!intel_syntax)
13328     oappend ("*");
13329   OP_E (bytemode, sizeflag);
13330 }
13331
13332 static void
13333 print_operand_value (char *buf, int hex, bfd_vma disp)
13334 {
13335   if (address_mode == mode_64bit)
13336     {
13337       if (hex)
13338         {
13339           char tmp[30];
13340           int i;
13341           buf[0] = '0';
13342           buf[1] = 'x';
13343           sprintf_vma (tmp, disp);
13344           for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
13345           strcpy (buf + 2, tmp + i);
13346         }
13347       else
13348         {
13349           bfd_signed_vma v = disp;
13350           char tmp[30];
13351           int i;
13352           if (v < 0)
13353             {
13354               *(buf++) = '-';
13355               v = -disp;
13356               /* Check for possible overflow on 0x8000000000000000.  */
13357               if (v < 0)
13358                 {
13359                   strcpy (buf, "9223372036854775808");
13360                   return;
13361                 }
13362             }
13363           if (!v)
13364             {
13365               strcpy (buf, "0");
13366               return;
13367             }
13368
13369           i = 0;
13370           tmp[29] = 0;
13371           while (v)
13372             {
13373               tmp[28 - i] = (v % 10) + '0';
13374               v /= 10;
13375               i++;
13376             }
13377           strcpy (buf, tmp + 29 - i);
13378         }
13379     }
13380   else
13381     {
13382       if (hex)
13383         sprintf (buf, "0x%x", (unsigned int) disp);
13384       else
13385         sprintf (buf, "%d", (int) disp);
13386     }
13387 }
13388
13389 /* Put DISP in BUF as signed hex number.  */
13390
13391 static void
13392 print_displacement (char *buf, bfd_vma disp)
13393 {
13394   bfd_signed_vma val = disp;
13395   char tmp[30];
13396   int i, j = 0;
13397
13398   if (val < 0)
13399     {
13400       buf[j++] = '-';
13401       val = -disp;
13402
13403       /* Check for possible overflow.  */
13404       if (val < 0)
13405         {
13406           switch (address_mode)
13407             {
13408             case mode_64bit:
13409               strcpy (buf + j, "0x8000000000000000");
13410               break;
13411             case mode_32bit:
13412               strcpy (buf + j, "0x80000000");
13413               break;
13414             case mode_16bit:
13415               strcpy (buf + j, "0x8000");
13416               break;
13417             }
13418           return;
13419         }
13420     }
13421
13422   buf[j++] = '0';
13423   buf[j++] = 'x';
13424
13425   sprintf_vma (tmp, (bfd_vma) val);
13426   for (i = 0; tmp[i] == '0'; i++)
13427     continue;
13428   if (tmp[i] == '\0')
13429     i--;
13430   strcpy (buf + j, tmp + i);
13431 }
13432
13433 static void
13434 intel_operand_size (int bytemode, int sizeflag)
13435 {
13436   if (vex.evex
13437       && vex.b
13438       && (bytemode == x_mode
13439           || bytemode == evex_half_bcst_xmmq_mode))
13440     {
13441       if (vex.w)
13442         oappend ("QWORD PTR ");
13443       else
13444         oappend ("DWORD PTR ");
13445       return;
13446     }
13447   switch (bytemode)
13448     {
13449     case b_mode:
13450     case b_swap_mode:
13451     case dqb_mode:
13452     case db_mode:
13453       oappend ("BYTE PTR ");
13454       break;
13455     case w_mode:
13456     case dw_mode:
13457     case dqw_mode:
13458       oappend ("WORD PTR ");
13459       break;
13460     case indir_v_mode:
13461       if (address_mode == mode_64bit && isa64 == intel64)
13462         {
13463           oappend ("QWORD PTR ");
13464           break;
13465         }
13466       /* Fall through.  */
13467     case stack_v_mode:
13468       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
13469         {
13470           oappend ("QWORD PTR ");
13471           break;
13472         }
13473       /* Fall through.  */
13474     case v_mode:
13475     case v_swap_mode:
13476     case dq_mode:
13477       USED_REX (REX_W);
13478       if (rex & REX_W)
13479         oappend ("QWORD PTR ");
13480       else
13481         {
13482           if ((sizeflag & DFLAG) || bytemode == dq_mode)
13483             oappend ("DWORD PTR ");
13484           else
13485             oappend ("WORD PTR ");
13486           used_prefixes |= (prefixes & PREFIX_DATA);
13487         }
13488       break;
13489     case z_mode:
13490       if ((rex & REX_W) || (sizeflag & DFLAG))
13491         *obufp++ = 'D';
13492       oappend ("WORD PTR ");
13493       if (!(rex & REX_W))
13494         used_prefixes |= (prefixes & PREFIX_DATA);
13495       break;
13496     case a_mode:
13497       if (sizeflag & DFLAG)
13498         oappend ("QWORD PTR ");
13499       else
13500         oappend ("DWORD PTR ");
13501       used_prefixes |= (prefixes & PREFIX_DATA);
13502       break;
13503     case movsxd_mode:
13504       if (!(sizeflag & DFLAG) && isa64 == intel64)
13505         oappend ("WORD PTR ");
13506       else
13507         oappend ("DWORD PTR ");
13508       used_prefixes |= (prefixes & PREFIX_DATA);
13509       break;
13510     case d_mode:
13511     case d_scalar_swap_mode:
13512     case d_swap_mode:
13513     case dqd_mode:
13514       oappend ("DWORD PTR ");
13515       break;
13516     case q_mode:
13517     case q_scalar_swap_mode:
13518     case q_swap_mode:
13519       oappend ("QWORD PTR ");
13520       break;
13521     case m_mode:
13522       if (address_mode == mode_64bit)
13523         oappend ("QWORD PTR ");
13524       else
13525         oappend ("DWORD PTR ");
13526       break;
13527     case f_mode:
13528       if (sizeflag & DFLAG)
13529         oappend ("FWORD PTR ");
13530       else
13531         oappend ("DWORD PTR ");
13532       used_prefixes |= (prefixes & PREFIX_DATA);
13533       break;
13534     case t_mode:
13535       oappend ("TBYTE PTR ");
13536       break;
13537     case x_mode:
13538     case x_swap_mode:
13539     case evex_x_gscat_mode:
13540     case evex_x_nobcst_mode:
13541     case b_scalar_mode:
13542     case w_scalar_mode:
13543       if (need_vex)
13544         {
13545           switch (vex.length)
13546             {
13547             case 128:
13548               oappend ("XMMWORD PTR ");
13549               break;
13550             case 256:
13551               oappend ("YMMWORD PTR ");
13552               break;
13553             case 512:
13554               oappend ("ZMMWORD PTR ");
13555               break;
13556             default:
13557               abort ();
13558             }
13559         }
13560       else
13561         oappend ("XMMWORD PTR ");
13562       break;
13563     case xmm_mode:
13564       oappend ("XMMWORD PTR ");
13565       break;
13566     case ymm_mode:
13567       oappend ("YMMWORD PTR ");
13568       break;
13569     case xmmq_mode:
13570     case evex_half_bcst_xmmq_mode:
13571       if (!need_vex)
13572         abort ();
13573
13574       switch (vex.length)
13575         {
13576         case 128:
13577           oappend ("QWORD PTR ");
13578           break;
13579         case 256:
13580           oappend ("XMMWORD PTR ");
13581           break;
13582         case 512:
13583           oappend ("YMMWORD PTR ");
13584           break;
13585         default:
13586           abort ();
13587         }
13588       break;
13589     case xmm_mb_mode:
13590       if (!need_vex)
13591         abort ();
13592
13593       switch (vex.length)
13594         {
13595         case 128:
13596         case 256:
13597         case 512:
13598           oappend ("BYTE PTR ");
13599           break;
13600         default:
13601           abort ();
13602         }
13603       break;
13604     case xmm_mw_mode:
13605       if (!need_vex)
13606         abort ();
13607
13608       switch (vex.length)
13609         {
13610         case 128:
13611         case 256:
13612         case 512:
13613           oappend ("WORD PTR ");
13614           break;
13615         default:
13616           abort ();
13617         }
13618       break;
13619     case xmm_md_mode:
13620       if (!need_vex)
13621         abort ();
13622
13623       switch (vex.length)
13624         {
13625         case 128:
13626         case 256:
13627         case 512:
13628           oappend ("DWORD PTR ");
13629           break;
13630         default:
13631           abort ();
13632         }
13633       break;
13634     case xmm_mq_mode:
13635       if (!need_vex)
13636         abort ();
13637
13638       switch (vex.length)
13639         {
13640         case 128:
13641         case 256:
13642         case 512:
13643           oappend ("QWORD PTR ");
13644           break;
13645         default:
13646           abort ();
13647         }
13648       break;
13649     case xmmdw_mode:
13650       if (!need_vex)
13651         abort ();
13652
13653       switch (vex.length)
13654         {
13655         case 128:
13656           oappend ("WORD PTR ");
13657           break;
13658         case 256:
13659           oappend ("DWORD PTR ");
13660           break;
13661         case 512:
13662           oappend ("QWORD PTR ");
13663           break;
13664         default:
13665           abort ();
13666         }
13667       break;
13668     case xmmqd_mode:
13669       if (!need_vex)
13670         abort ();
13671
13672       switch (vex.length)
13673         {
13674         case 128:
13675           oappend ("DWORD PTR ");
13676           break;
13677         case 256:
13678           oappend ("QWORD PTR ");
13679           break;
13680         case 512:
13681           oappend ("XMMWORD PTR ");
13682           break;
13683         default:
13684           abort ();
13685         }
13686       break;
13687     case ymmq_mode:
13688       if (!need_vex)
13689         abort ();
13690
13691       switch (vex.length)
13692         {
13693         case 128:
13694           oappend ("QWORD PTR ");
13695           break;
13696         case 256:
13697           oappend ("YMMWORD PTR ");
13698           break;
13699         case 512:
13700           oappend ("ZMMWORD PTR ");
13701           break;
13702         default:
13703           abort ();
13704         }
13705       break;
13706     case ymmxmm_mode:
13707       if (!need_vex)
13708         abort ();
13709
13710       switch (vex.length)
13711         {
13712         case 128:
13713         case 256:
13714           oappend ("XMMWORD PTR ");
13715           break;
13716         default:
13717           abort ();
13718         }
13719       break;
13720     case o_mode:
13721       oappend ("OWORD PTR ");
13722       break;
13723     case vex_scalar_w_dq_mode:
13724       if (!need_vex)
13725         abort ();
13726
13727       if (vex.w)
13728         oappend ("QWORD PTR ");
13729       else
13730         oappend ("DWORD PTR ");
13731       break;
13732     case vex_vsib_d_w_dq_mode:
13733     case vex_vsib_q_w_dq_mode:
13734       if (!need_vex)
13735         abort ();
13736
13737       if (!vex.evex)
13738         {
13739           if (vex.w)
13740             oappend ("QWORD PTR ");
13741           else
13742             oappend ("DWORD PTR ");
13743         }
13744       else
13745         {
13746           switch (vex.length)
13747             {
13748             case 128:
13749               oappend ("XMMWORD PTR ");
13750               break;
13751             case 256:
13752               oappend ("YMMWORD PTR ");
13753               break;
13754             case 512:
13755               oappend ("ZMMWORD PTR ");
13756               break;
13757             default:
13758               abort ();
13759             }
13760         }
13761       break;
13762     case vex_vsib_q_w_d_mode:
13763     case vex_vsib_d_w_d_mode:
13764       if (!need_vex || !vex.evex)
13765         abort ();
13766
13767       switch (vex.length)
13768         {
13769         case 128:
13770           oappend ("QWORD PTR ");
13771           break;
13772         case 256:
13773           oappend ("XMMWORD PTR ");
13774           break;
13775         case 512:
13776           oappend ("YMMWORD PTR ");
13777           break;
13778         default:
13779           abort ();
13780         }
13781
13782       break;
13783     case mask_bd_mode:
13784       if (!need_vex || vex.length != 128)
13785         abort ();
13786       if (vex.w)
13787         oappend ("DWORD PTR ");
13788       else
13789         oappend ("BYTE PTR ");
13790       break;
13791     case mask_mode:
13792       if (!need_vex)
13793         abort ();
13794       if (vex.w)
13795         oappend ("QWORD PTR ");
13796       else
13797         oappend ("WORD PTR ");
13798       break;
13799     case v_bnd_mode:
13800     case v_bndmk_mode:
13801     default:
13802       break;
13803     }
13804 }
13805
13806 static void
13807 OP_E_register (int bytemode, int sizeflag)
13808 {
13809   int reg = modrm.rm;
13810   const char **names;
13811
13812   USED_REX (REX_B);
13813   if ((rex & REX_B))
13814     reg += 8;
13815
13816   if ((sizeflag & SUFFIX_ALWAYS)
13817       && (bytemode == b_swap_mode
13818           || bytemode == bnd_swap_mode
13819           || bytemode == v_swap_mode))
13820     swap_operand ();
13821
13822   switch (bytemode)
13823     {
13824     case b_mode:
13825     case b_swap_mode:
13826       USED_REX (0);
13827       if (rex)
13828         names = names8rex;
13829       else
13830         names = names8;
13831       break;
13832     case w_mode:
13833       names = names16;
13834       break;
13835     case d_mode:
13836     case dw_mode:
13837     case db_mode:
13838       names = names32;
13839       break;
13840     case q_mode:
13841       names = names64;
13842       break;
13843     case m_mode:
13844     case v_bnd_mode:
13845       names = address_mode == mode_64bit ? names64 : names32;
13846       break;
13847     case bnd_mode:
13848     case bnd_swap_mode:
13849       if (reg > 0x3)
13850         {
13851           oappend ("(bad)");
13852           return;
13853         }
13854       names = names_bnd;
13855       break;
13856     case indir_v_mode:
13857       if (address_mode == mode_64bit && isa64 == intel64)
13858         {
13859           names = names64;
13860           break;
13861         }
13862       /* Fall through.  */
13863     case stack_v_mode:
13864       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
13865         {
13866           names = names64;
13867           break;
13868         }
13869       bytemode = v_mode;
13870       /* Fall through.  */
13871     case v_mode:
13872     case v_swap_mode:
13873     case dq_mode:
13874     case dqb_mode:
13875     case dqd_mode:
13876     case dqw_mode:
13877       USED_REX (REX_W);
13878       if (rex & REX_W)
13879         names = names64;
13880       else
13881         {
13882           if ((sizeflag & DFLAG)
13883               || (bytemode != v_mode
13884                   && bytemode != v_swap_mode))
13885             names = names32;
13886           else
13887             names = names16;
13888           used_prefixes |= (prefixes & PREFIX_DATA);
13889         }
13890       break;
13891     case movsxd_mode:
13892       if (!(sizeflag & DFLAG) && isa64 == intel64)
13893         names = names16;
13894       else
13895         names = names32;
13896       used_prefixes |= (prefixes & PREFIX_DATA);
13897       break;
13898     case va_mode:
13899       names = (address_mode == mode_64bit
13900                ? names64 : names32);
13901       if (!(prefixes & PREFIX_ADDR))
13902         names = (address_mode == mode_16bit
13903                      ? names16 : names);
13904       else
13905         {
13906           /* Remove "addr16/addr32".  */
13907           all_prefixes[last_addr_prefix] = 0;
13908           names = (address_mode != mode_32bit
13909                        ? names32 : names16);
13910           used_prefixes |= PREFIX_ADDR;
13911         }
13912       break;
13913     case mask_bd_mode:
13914     case mask_mode:
13915       if (reg > 0x7)
13916         {
13917           oappend ("(bad)");
13918           return;
13919         }
13920       names = names_mask;
13921       break;
13922     case 0:
13923       return;
13924     default:
13925       oappend (INTERNAL_DISASSEMBLER_ERROR);
13926       return;
13927     }
13928   oappend (names[reg]);
13929 }
13930
13931 static void
13932 OP_E_memory (int bytemode, int sizeflag)
13933 {
13934   bfd_vma disp = 0;
13935   int add = (rex & REX_B) ? 8 : 0;
13936   int riprel = 0;
13937   int shift;
13938
13939   if (vex.evex)
13940     {
13941       /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0.  */
13942       if (vex.b
13943           && bytemode != x_mode
13944           && bytemode != xmmq_mode
13945           && bytemode != evex_half_bcst_xmmq_mode)
13946         {
13947           BadOp ();
13948           return;
13949         }
13950       switch (bytemode)
13951         {
13952         case dqw_mode:
13953         case dw_mode:
13954           shift = 1;
13955           break;
13956         case dqb_mode:
13957         case db_mode:
13958           shift = 0;
13959           break;
13960         case dq_mode:
13961           if (address_mode != mode_64bit)
13962             {
13963               shift = 2;
13964               break;
13965             }
13966             /* fall through */
13967         case vex_scalar_w_dq_mode:
13968         case vex_vsib_d_w_dq_mode:
13969         case vex_vsib_d_w_d_mode:
13970         case vex_vsib_q_w_dq_mode:
13971         case vex_vsib_q_w_d_mode:
13972         case evex_x_gscat_mode:
13973           shift = vex.w ? 3 : 2;
13974           break;
13975         case x_mode:
13976         case evex_half_bcst_xmmq_mode:
13977         case xmmq_mode:
13978           if (vex.b)
13979             {
13980               shift = vex.w ? 3 : 2;
13981               break;
13982             }
13983           /* Fall through.  */
13984         case xmmqd_mode:
13985         case xmmdw_mode:
13986         case ymmq_mode:
13987         case evex_x_nobcst_mode:
13988         case x_swap_mode:
13989           switch (vex.length)
13990             {
13991             case 128:
13992               shift = 4;
13993               break;
13994             case 256:
13995               shift = 5;
13996               break;
13997             case 512:
13998               shift = 6;
13999               break;
14000             default:
14001               abort ();
14002             }
14003           break;
14004         case ymm_mode:
14005           shift = 5;
14006           break;
14007         case xmm_mode:
14008           shift = 4;
14009           break;
14010         case xmm_mq_mode:
14011         case q_mode:
14012         case q_swap_mode:
14013         case q_scalar_swap_mode:
14014           shift = 3;
14015           break;
14016         case dqd_mode:
14017         case xmm_md_mode:
14018         case d_mode:
14019         case d_swap_mode:
14020         case d_scalar_swap_mode:
14021           shift = 2;
14022           break;
14023         case w_scalar_mode:
14024         case xmm_mw_mode:
14025           shift = 1;
14026           break;
14027         case b_scalar_mode:
14028         case xmm_mb_mode:
14029           shift = 0;
14030           break;
14031         default:
14032           abort ();
14033         }
14034       /* Make necessary corrections to shift for modes that need it.
14035          For these modes we currently have shift 4, 5 or 6 depending on
14036          vex.length (it corresponds to xmmword, ymmword or zmmword
14037          operand).  We might want to make it 3, 4 or 5 (e.g. for
14038          xmmq_mode).  In case of broadcast enabled the corrections
14039          aren't needed, as element size is always 32 or 64 bits.  */
14040       if (!vex.b
14041           && (bytemode == xmmq_mode
14042               || bytemode == evex_half_bcst_xmmq_mode))
14043         shift -= 1;
14044       else if (bytemode == xmmqd_mode)
14045         shift -= 2;
14046       else if (bytemode == xmmdw_mode)
14047         shift -= 3;
14048       else if (bytemode == ymmq_mode && vex.length == 128)
14049         shift -= 1;
14050     }
14051   else
14052     shift = 0;
14053
14054   USED_REX (REX_B);
14055   if (intel_syntax)
14056     intel_operand_size (bytemode, sizeflag);
14057   append_seg ();
14058
14059   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
14060     {
14061       /* 32/64 bit address mode */
14062       int havedisp;
14063       int havesib;
14064       int havebase;
14065       int haveindex;
14066       int needindex;
14067       int needaddr32;
14068       int base, rbase;
14069       int vindex = 0;
14070       int scale = 0;
14071       int addr32flag = !((sizeflag & AFLAG)
14072                          || bytemode == v_bnd_mode
14073                          || bytemode == v_bndmk_mode
14074                          || bytemode == bnd_mode
14075                          || bytemode == bnd_swap_mode);
14076       const char **indexes64 = names64;
14077       const char **indexes32 = names32;
14078
14079       havesib = 0;
14080       havebase = 1;
14081       haveindex = 0;
14082       base = modrm.rm;
14083
14084       if (base == 4)
14085         {
14086           havesib = 1;
14087           vindex = sib.index;
14088           USED_REX (REX_X);
14089           if (rex & REX_X)
14090             vindex += 8;
14091           switch (bytemode)
14092             {
14093             case vex_vsib_d_w_dq_mode:
14094             case vex_vsib_d_w_d_mode:
14095             case vex_vsib_q_w_dq_mode:
14096             case vex_vsib_q_w_d_mode:
14097               if (!need_vex)
14098                 abort ();
14099               if (vex.evex)
14100                 {
14101                   if (!vex.v)
14102                     vindex += 16;
14103                 }
14104
14105               haveindex = 1;
14106               switch (vex.length)
14107                 {
14108                 case 128:
14109                   indexes64 = indexes32 = names_xmm;
14110                   break;
14111                 case 256:
14112                   if (!vex.w
14113                       || bytemode == vex_vsib_q_w_dq_mode
14114                       || bytemode == vex_vsib_q_w_d_mode)
14115                     indexes64 = indexes32 = names_ymm;
14116                   else
14117                     indexes64 = indexes32 = names_xmm;
14118                   break;
14119                 case 512:
14120                   if (!vex.w
14121                       || bytemode == vex_vsib_q_w_dq_mode
14122                       || bytemode == vex_vsib_q_w_d_mode)
14123                     indexes64 = indexes32 = names_zmm;
14124                   else
14125                     indexes64 = indexes32 = names_ymm;
14126                   break;
14127                 default:
14128                   abort ();
14129                 }
14130               break;
14131             default:
14132               haveindex = vindex != 4;
14133               break;
14134             }
14135           scale = sib.scale;
14136           base = sib.base;
14137           codep++;
14138         }
14139       rbase = base + add;
14140
14141       switch (modrm.mod)
14142         {
14143         case 0:
14144           if (base == 5)
14145             {
14146               havebase = 0;
14147               if (address_mode == mode_64bit && !havesib)
14148                 riprel = 1;
14149               disp = get32s ();
14150               if (riprel && bytemode == v_bndmk_mode)
14151                 {
14152                   oappend ("(bad)");
14153                   return;
14154                 }
14155             }
14156           break;
14157         case 1:
14158           FETCH_DATA (the_info, codep + 1);
14159           disp = *codep++;
14160           if ((disp & 0x80) != 0)
14161             disp -= 0x100;
14162           if (vex.evex && shift > 0)
14163             disp <<= shift;
14164           break;
14165         case 2:
14166           disp = get32s ();
14167           break;
14168         }
14169
14170       needindex = 0;
14171       needaddr32 = 0;
14172       if (havesib
14173           && !havebase
14174           && !haveindex
14175           && address_mode != mode_16bit)
14176         {
14177           if (address_mode == mode_64bit)
14178             {
14179               /* Display eiz instead of addr32.  */
14180               needindex = addr32flag;
14181               needaddr32 = 1;
14182             }
14183           else
14184             {
14185               /* In 32-bit mode, we need index register to tell [offset]
14186                  from [eiz*1 + offset].  */
14187               needindex = 1;
14188             }
14189         }
14190
14191       havedisp = (havebase
14192                   || needindex
14193                   || (havesib && (haveindex || scale != 0)));
14194
14195       if (!intel_syntax)
14196         if (modrm.mod != 0 || base == 5)
14197           {
14198             if (havedisp || riprel)
14199               print_displacement (scratchbuf, disp);
14200             else
14201               print_operand_value (scratchbuf, 1, disp);
14202             oappend (scratchbuf);
14203             if (riprel)
14204               {
14205                 set_op (disp, 1);
14206                 oappend (!addr32flag ? "(%rip)" : "(%eip)");
14207               }
14208           }
14209
14210       if ((havebase || haveindex || needindex || needaddr32 || riprel)
14211           && (address_mode != mode_64bit
14212               || ((bytemode != v_bnd_mode)
14213                   && (bytemode != v_bndmk_mode)
14214                   && (bytemode != bnd_mode)
14215                   && (bytemode != bnd_swap_mode))))
14216         used_prefixes |= PREFIX_ADDR;
14217
14218       if (havedisp || (intel_syntax && riprel))
14219         {
14220           *obufp++ = open_char;
14221           if (intel_syntax && riprel)
14222             {
14223               set_op (disp, 1);
14224               oappend (!addr32flag ? "rip" : "eip");
14225             }
14226           *obufp = '\0';
14227           if (havebase)
14228             oappend (address_mode == mode_64bit && !addr32flag
14229                      ? names64[rbase] : names32[rbase]);
14230           if (havesib)
14231             {
14232               /* ESP/RSP won't allow index.  If base isn't ESP/RSP,
14233                  print index to tell base + index from base.  */
14234               if (scale != 0
14235                   || needindex
14236                   || haveindex
14237                   || (havebase && base != ESP_REG_NUM))
14238                 {
14239                   if (!intel_syntax || havebase)
14240                     {
14241                       *obufp++ = separator_char;
14242                       *obufp = '\0';
14243                     }
14244                   if (haveindex)
14245                     oappend (address_mode == mode_64bit && !addr32flag
14246                              ? indexes64[vindex] : indexes32[vindex]);
14247                   else
14248                     oappend (address_mode == mode_64bit && !addr32flag
14249                              ? index64 : index32);
14250
14251                   *obufp++ = scale_char;
14252                   *obufp = '\0';
14253                   sprintf (scratchbuf, "%d", 1 << scale);
14254                   oappend (scratchbuf);
14255                 }
14256             }
14257           if (intel_syntax
14258               && (disp || modrm.mod != 0 || base == 5))
14259             {
14260               if (!havedisp || (bfd_signed_vma) disp >= 0)
14261                 {
14262                   *obufp++ = '+';
14263                   *obufp = '\0';
14264                 }
14265               else if (modrm.mod != 1 && disp != -disp)
14266                 {
14267                   *obufp++ = '-';
14268                   *obufp = '\0';
14269                   disp = - (bfd_signed_vma) disp;
14270                 }
14271
14272               if (havedisp)
14273                 print_displacement (scratchbuf, disp);
14274               else
14275                 print_operand_value (scratchbuf, 1, disp);
14276               oappend (scratchbuf);
14277             }
14278
14279           *obufp++ = close_char;
14280           *obufp = '\0';
14281         }
14282       else if (intel_syntax)
14283         {
14284           if (modrm.mod != 0 || base == 5)
14285             {
14286               if (!active_seg_prefix)
14287                 {
14288                   oappend (names_seg[ds_reg - es_reg]);
14289                   oappend (":");
14290                 }
14291               print_operand_value (scratchbuf, 1, disp);
14292               oappend (scratchbuf);
14293             }
14294         }
14295     }
14296   else if (bytemode == v_bnd_mode
14297            || bytemode == v_bndmk_mode
14298            || bytemode == bnd_mode
14299            || bytemode == bnd_swap_mode)
14300     {
14301       oappend ("(bad)");
14302       return;
14303     }
14304   else
14305     {
14306       /* 16 bit address mode */
14307       used_prefixes |= prefixes & PREFIX_ADDR;
14308       switch (modrm.mod)
14309         {
14310         case 0:
14311           if (modrm.rm == 6)
14312             {
14313               disp = get16 ();
14314               if ((disp & 0x8000) != 0)
14315                 disp -= 0x10000;
14316             }
14317           break;
14318         case 1:
14319           FETCH_DATA (the_info, codep + 1);
14320           disp = *codep++;
14321           if ((disp & 0x80) != 0)
14322             disp -= 0x100;
14323           if (vex.evex && shift > 0)
14324             disp <<= shift;
14325           break;
14326         case 2:
14327           disp = get16 ();
14328           if ((disp & 0x8000) != 0)
14329             disp -= 0x10000;
14330           break;
14331         }
14332
14333       if (!intel_syntax)
14334         if (modrm.mod != 0 || modrm.rm == 6)
14335           {
14336             print_displacement (scratchbuf, disp);
14337             oappend (scratchbuf);
14338           }
14339
14340       if (modrm.mod != 0 || modrm.rm != 6)
14341         {
14342           *obufp++ = open_char;
14343           *obufp = '\0';
14344           oappend (index16[modrm.rm]);
14345           if (intel_syntax
14346               && (disp || modrm.mod != 0 || modrm.rm == 6))
14347             {
14348               if ((bfd_signed_vma) disp >= 0)
14349                 {
14350                   *obufp++ = '+';
14351                   *obufp = '\0';
14352                 }
14353               else if (modrm.mod != 1)
14354                 {
14355                   *obufp++ = '-';
14356                   *obufp = '\0';
14357                   disp = - (bfd_signed_vma) disp;
14358                 }
14359
14360               print_displacement (scratchbuf, disp);
14361               oappend (scratchbuf);
14362             }
14363
14364           *obufp++ = close_char;
14365           *obufp = '\0';
14366         }
14367       else if (intel_syntax)
14368         {
14369           if (!active_seg_prefix)
14370             {
14371               oappend (names_seg[ds_reg - es_reg]);
14372               oappend (":");
14373             }
14374           print_operand_value (scratchbuf, 1, disp & 0xffff);
14375           oappend (scratchbuf);
14376         }
14377     }
14378   if (vex.evex && vex.b
14379       && (bytemode == x_mode
14380           || bytemode == xmmq_mode
14381           || bytemode == evex_half_bcst_xmmq_mode))
14382     {
14383       if (vex.w
14384           || bytemode == xmmq_mode
14385           || bytemode == evex_half_bcst_xmmq_mode)
14386         {
14387           switch (vex.length)
14388             {
14389             case 128:
14390               oappend ("{1to2}");
14391               break;
14392             case 256:
14393               oappend ("{1to4}");
14394               break;
14395             case 512:
14396               oappend ("{1to8}");
14397               break;
14398             default:
14399               abort ();
14400             }
14401         }
14402       else
14403         {
14404           switch (vex.length)
14405             {
14406             case 128:
14407               oappend ("{1to4}");
14408               break;
14409             case 256:
14410               oappend ("{1to8}");
14411               break;
14412             case 512:
14413               oappend ("{1to16}");
14414               break;
14415             default:
14416               abort ();
14417             }
14418         }
14419     }
14420 }
14421
14422 static void
14423 OP_E (int bytemode, int sizeflag)
14424 {
14425   /* Skip mod/rm byte.  */
14426   MODRM_CHECK;
14427   codep++;
14428
14429   if (modrm.mod == 3)
14430     OP_E_register (bytemode, sizeflag);
14431   else
14432     OP_E_memory (bytemode, sizeflag);
14433 }
14434
14435 static void
14436 OP_G (int bytemode, int sizeflag)
14437 {
14438   int add = 0;
14439   const char **names;
14440   USED_REX (REX_R);
14441   if (rex & REX_R)
14442     add += 8;
14443   switch (bytemode)
14444     {
14445     case b_mode:
14446       USED_REX (0);
14447       if (rex)
14448         oappend (names8rex[modrm.reg + add]);
14449       else
14450         oappend (names8[modrm.reg + add]);
14451       break;
14452     case w_mode:
14453       oappend (names16[modrm.reg + add]);
14454       break;
14455     case d_mode:
14456     case db_mode:
14457     case dw_mode:
14458       oappend (names32[modrm.reg + add]);
14459       break;
14460     case q_mode:
14461       oappend (names64[modrm.reg + add]);
14462       break;
14463     case bnd_mode:
14464       if (modrm.reg > 0x3)
14465         {
14466           oappend ("(bad)");
14467           return;
14468         }
14469       oappend (names_bnd[modrm.reg]);
14470       break;
14471     case v_mode:
14472     case dq_mode:
14473     case dqb_mode:
14474     case dqd_mode:
14475     case dqw_mode:
14476     case movsxd_mode:
14477       USED_REX (REX_W);
14478       if (rex & REX_W)
14479         oappend (names64[modrm.reg + add]);
14480       else
14481         {
14482           if ((sizeflag & DFLAG)
14483               || (bytemode != v_mode && bytemode != movsxd_mode))
14484             oappend (names32[modrm.reg + add]);
14485           else
14486             oappend (names16[modrm.reg + add]);
14487           used_prefixes |= (prefixes & PREFIX_DATA);
14488         }
14489       break;
14490     case va_mode:
14491       names = (address_mode == mode_64bit
14492                ? names64 : names32);
14493       if (!(prefixes & PREFIX_ADDR))
14494         {
14495           if (address_mode == mode_16bit)
14496             names = names16;
14497         }
14498       else
14499         {
14500           /* Remove "addr16/addr32".  */
14501           all_prefixes[last_addr_prefix] = 0;
14502           names = (address_mode != mode_32bit
14503                        ? names32 : names16);
14504           used_prefixes |= PREFIX_ADDR;
14505         }
14506       oappend (names[modrm.reg + add]);
14507       break;
14508     case m_mode:
14509       if (address_mode == mode_64bit)
14510         oappend (names64[modrm.reg + add]);
14511       else
14512         oappend (names32[modrm.reg + add]);
14513       break;
14514     case mask_bd_mode:
14515     case mask_mode:
14516       if ((modrm.reg + add) > 0x7)
14517         {
14518           oappend ("(bad)");
14519           return;
14520         }
14521       oappend (names_mask[modrm.reg + add]);
14522       break;
14523     default:
14524       oappend (INTERNAL_DISASSEMBLER_ERROR);
14525       break;
14526     }
14527 }
14528
14529 static bfd_vma
14530 get64 (void)
14531 {
14532   bfd_vma x;
14533 #ifdef BFD64
14534   unsigned int a;
14535   unsigned int b;
14536
14537   FETCH_DATA (the_info, codep + 8);
14538   a = *codep++ & 0xff;
14539   a |= (*codep++ & 0xff) << 8;
14540   a |= (*codep++ & 0xff) << 16;
14541   a |= (*codep++ & 0xffu) << 24;
14542   b = *codep++ & 0xff;
14543   b |= (*codep++ & 0xff) << 8;
14544   b |= (*codep++ & 0xff) << 16;
14545   b |= (*codep++ & 0xffu) << 24;
14546   x = a + ((bfd_vma) b << 32);
14547 #else
14548   abort ();
14549   x = 0;
14550 #endif
14551   return x;
14552 }
14553
14554 static bfd_signed_vma
14555 get32 (void)
14556 {
14557   bfd_signed_vma x = 0;
14558
14559   FETCH_DATA (the_info, codep + 4);
14560   x = *codep++ & (bfd_signed_vma) 0xff;
14561   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
14562   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
14563   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
14564   return x;
14565 }
14566
14567 static bfd_signed_vma
14568 get32s (void)
14569 {
14570   bfd_signed_vma x = 0;
14571
14572   FETCH_DATA (the_info, codep + 4);
14573   x = *codep++ & (bfd_signed_vma) 0xff;
14574   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
14575   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
14576   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
14577
14578   x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
14579
14580   return x;
14581 }
14582
14583 static int
14584 get16 (void)
14585 {
14586   int x = 0;
14587
14588   FETCH_DATA (the_info, codep + 2);
14589   x = *codep++ & 0xff;
14590   x |= (*codep++ & 0xff) << 8;
14591   return x;
14592 }
14593
14594 static void
14595 set_op (bfd_vma op, int riprel)
14596 {
14597   op_index[op_ad] = op_ad;
14598   if (address_mode == mode_64bit)
14599     {
14600       op_address[op_ad] = op;
14601       op_riprel[op_ad] = riprel;
14602     }
14603   else
14604     {
14605       /* Mask to get a 32-bit address.  */
14606       op_address[op_ad] = op & 0xffffffff;
14607       op_riprel[op_ad] = riprel & 0xffffffff;
14608     }
14609 }
14610
14611 static void
14612 OP_REG (int code, int sizeflag)
14613 {
14614   const char *s;
14615   int add;
14616
14617   switch (code)
14618     {
14619     case es_reg: case ss_reg: case cs_reg:
14620     case ds_reg: case fs_reg: case gs_reg:
14621       oappend (names_seg[code - es_reg]);
14622       return;
14623     }
14624
14625   USED_REX (REX_B);
14626   if (rex & REX_B)
14627     add = 8;
14628   else
14629     add = 0;
14630
14631   switch (code)
14632     {
14633     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
14634     case sp_reg: case bp_reg: case si_reg: case di_reg:
14635       s = names16[code - ax_reg + add];
14636       break;
14637     case al_reg: case ah_reg: case cl_reg: case ch_reg:
14638     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
14639       USED_REX (0);
14640       if (rex)
14641         s = names8rex[code - al_reg + add];
14642       else
14643         s = names8[code - al_reg];
14644       break;
14645     case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
14646     case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
14647       if (address_mode == mode_64bit
14648           && ((sizeflag & DFLAG) || (rex & REX_W)))
14649         {
14650           s = names64[code - rAX_reg + add];
14651           break;
14652         }
14653       code += eAX_reg - rAX_reg;
14654       /* Fall through.  */
14655     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
14656     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
14657       USED_REX (REX_W);
14658       if (rex & REX_W)
14659         s = names64[code - eAX_reg + add];
14660       else
14661         {
14662           if (sizeflag & DFLAG)
14663             s = names32[code - eAX_reg + add];
14664           else
14665             s = names16[code - eAX_reg + add];
14666           used_prefixes |= (prefixes & PREFIX_DATA);
14667         }
14668       break;
14669     default:
14670       s = INTERNAL_DISASSEMBLER_ERROR;
14671       break;
14672     }
14673   oappend (s);
14674 }
14675
14676 static void
14677 OP_IMREG (int code, int sizeflag)
14678 {
14679   const char *s;
14680
14681   switch (code)
14682     {
14683     case indir_dx_reg:
14684       if (intel_syntax)
14685         s = "dx";
14686       else
14687         s = "(%dx)";
14688       break;
14689     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
14690     case sp_reg: case bp_reg: case si_reg: case di_reg:
14691       s = names16[code - ax_reg];
14692       break;
14693     case es_reg: case ss_reg: case cs_reg:
14694     case ds_reg: case fs_reg: case gs_reg:
14695       s = names_seg[code - es_reg];
14696       break;
14697     case al_reg: case ah_reg: case cl_reg: case ch_reg:
14698     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
14699       USED_REX (0);
14700       if (rex)
14701         s = names8rex[code - al_reg];
14702       else
14703         s = names8[code - al_reg];
14704       break;
14705     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
14706     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
14707       USED_REX (REX_W);
14708       if (rex & REX_W)
14709         s = names64[code - eAX_reg];
14710       else
14711         {
14712           if (sizeflag & DFLAG)
14713             s = names32[code - eAX_reg];
14714           else
14715             s = names16[code - eAX_reg];
14716           used_prefixes |= (prefixes & PREFIX_DATA);
14717         }
14718       break;
14719     case z_mode_ax_reg:
14720       if ((rex & REX_W) || (sizeflag & DFLAG))
14721         s = *names32;
14722       else
14723         s = *names16;
14724       if (!(rex & REX_W))
14725         used_prefixes |= (prefixes & PREFIX_DATA);
14726       break;
14727     default:
14728       s = INTERNAL_DISASSEMBLER_ERROR;
14729       break;
14730     }
14731   oappend (s);
14732 }
14733
14734 static void
14735 OP_I (int bytemode, int sizeflag)
14736 {
14737   bfd_signed_vma op;
14738   bfd_signed_vma mask = -1;
14739
14740   switch (bytemode)
14741     {
14742     case b_mode:
14743       FETCH_DATA (the_info, codep + 1);
14744       op = *codep++;
14745       mask = 0xff;
14746       break;
14747     case v_mode:
14748       USED_REX (REX_W);
14749       if (rex & REX_W)
14750         op = get32s ();
14751       else
14752         {
14753           if (sizeflag & DFLAG)
14754             {
14755               op = get32 ();
14756               mask = 0xffffffff;
14757             }
14758           else
14759             {
14760               op = get16 ();
14761               mask = 0xfffff;
14762             }
14763           used_prefixes |= (prefixes & PREFIX_DATA);
14764         }
14765       break;
14766     case d_mode:
14767       mask = 0xffffffff;
14768       op = get32 ();
14769       break;
14770     case w_mode:
14771       mask = 0xfffff;
14772       op = get16 ();
14773       break;
14774     case const_1_mode:
14775       if (intel_syntax)
14776         oappend ("1");
14777       return;
14778     default:
14779       oappend (INTERNAL_DISASSEMBLER_ERROR);
14780       return;
14781     }
14782
14783   op &= mask;
14784   scratchbuf[0] = '$';
14785   print_operand_value (scratchbuf + 1, 1, op);
14786   oappend_maybe_intel (scratchbuf);
14787   scratchbuf[0] = '\0';
14788 }
14789
14790 static void
14791 OP_I64 (int bytemode, int sizeflag)
14792 {
14793   if (bytemode != v_mode || address_mode != mode_64bit || !(rex & REX_W))
14794     {
14795       OP_I (bytemode, sizeflag);
14796       return;
14797     }
14798
14799   USED_REX (REX_W);
14800
14801   scratchbuf[0] = '$';
14802   print_operand_value (scratchbuf + 1, 1, get64 ());
14803   oappend_maybe_intel (scratchbuf);
14804   scratchbuf[0] = '\0';
14805 }
14806
14807 static void
14808 OP_sI (int bytemode, int sizeflag)
14809 {
14810   bfd_signed_vma op;
14811
14812   switch (bytemode)
14813     {
14814     case b_mode:
14815     case b_T_mode:
14816       FETCH_DATA (the_info, codep + 1);
14817       op = *codep++;
14818       if ((op & 0x80) != 0)
14819         op -= 0x100;
14820       if (bytemode == b_T_mode)
14821         {
14822           if (address_mode != mode_64bit
14823               || !((sizeflag & DFLAG) || (rex & REX_W)))
14824             {
14825               /* The operand-size prefix is overridden by a REX prefix.  */
14826               if ((sizeflag & DFLAG) || (rex & REX_W))
14827                 op &= 0xffffffff;
14828               else
14829                 op &= 0xffff;
14830           }
14831         }
14832       else
14833         {
14834           if (!(rex & REX_W))
14835             {
14836               if (sizeflag & DFLAG)
14837                 op &= 0xffffffff;
14838               else
14839                 op &= 0xffff;
14840             }
14841         }
14842       break;
14843     case v_mode:
14844       /* The operand-size prefix is overridden by a REX prefix.  */
14845       if ((sizeflag & DFLAG) || (rex & REX_W))
14846         op = get32s ();
14847       else
14848         op = get16 ();
14849       break;
14850     default:
14851       oappend (INTERNAL_DISASSEMBLER_ERROR);
14852       return;
14853     }
14854
14855   scratchbuf[0] = '$';
14856   print_operand_value (scratchbuf + 1, 1, op);
14857   oappend_maybe_intel (scratchbuf);
14858 }
14859
14860 static void
14861 OP_J (int bytemode, int sizeflag)
14862 {
14863   bfd_vma disp;
14864   bfd_vma mask = -1;
14865   bfd_vma segment = 0;
14866
14867   switch (bytemode)
14868     {
14869     case b_mode:
14870       FETCH_DATA (the_info, codep + 1);
14871       disp = *codep++;
14872       if ((disp & 0x80) != 0)
14873         disp -= 0x100;
14874       break;
14875     case v_mode:
14876       if (isa64 != intel64)
14877     case dqw_mode:
14878         USED_REX (REX_W);
14879       if ((sizeflag & DFLAG)
14880           || (address_mode == mode_64bit
14881               && ((isa64 == intel64 && bytemode != dqw_mode)
14882                   || (rex & REX_W))))
14883         disp = get32s ();
14884       else
14885         {
14886           disp = get16 ();
14887           if ((disp & 0x8000) != 0)
14888             disp -= 0x10000;
14889           /* In 16bit mode, address is wrapped around at 64k within
14890              the same segment.  Otherwise, a data16 prefix on a jump
14891              instruction means that the pc is masked to 16 bits after
14892              the displacement is added!  */
14893           mask = 0xffff;
14894           if ((prefixes & PREFIX_DATA) == 0)
14895             segment = ((start_pc + (codep - start_codep))
14896                        & ~((bfd_vma) 0xffff));
14897         }
14898       if (address_mode != mode_64bit
14899           || (isa64 != intel64 && !(rex & REX_W)))
14900         used_prefixes |= (prefixes & PREFIX_DATA);
14901       break;
14902     default:
14903       oappend (INTERNAL_DISASSEMBLER_ERROR);
14904       return;
14905     }
14906   disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment;
14907   set_op (disp, 0);
14908   print_operand_value (scratchbuf, 1, disp);
14909   oappend (scratchbuf);
14910 }
14911
14912 static void
14913 OP_SEG (int bytemode, int sizeflag)
14914 {
14915   if (bytemode == w_mode)
14916     oappend (names_seg[modrm.reg]);
14917   else
14918     OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
14919 }
14920
14921 static void
14922 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
14923 {
14924   int seg, offset;
14925
14926   if (sizeflag & DFLAG)
14927     {
14928       offset = get32 ();
14929       seg = get16 ();
14930     }
14931   else
14932     {
14933       offset = get16 ();
14934       seg = get16 ();
14935     }
14936   used_prefixes |= (prefixes & PREFIX_DATA);
14937   if (intel_syntax)
14938     sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
14939   else
14940     sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
14941   oappend (scratchbuf);
14942 }
14943
14944 static void
14945 OP_OFF (int bytemode, int sizeflag)
14946 {
14947   bfd_vma off;
14948
14949   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
14950     intel_operand_size (bytemode, sizeflag);
14951   append_seg ();
14952
14953   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
14954     off = get32 ();
14955   else
14956     off = get16 ();
14957
14958   if (intel_syntax)
14959     {
14960       if (!active_seg_prefix)
14961         {
14962           oappend (names_seg[ds_reg - es_reg]);
14963           oappend (":");
14964         }
14965     }
14966   print_operand_value (scratchbuf, 1, off);
14967   oappend (scratchbuf);
14968 }
14969
14970 static void
14971 OP_OFF64 (int bytemode, int sizeflag)
14972 {
14973   bfd_vma off;
14974
14975   if (address_mode != mode_64bit
14976       || (prefixes & PREFIX_ADDR))
14977     {
14978       OP_OFF (bytemode, sizeflag);
14979       return;
14980     }
14981
14982   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
14983     intel_operand_size (bytemode, sizeflag);
14984   append_seg ();
14985
14986   off = get64 ();
14987
14988   if (intel_syntax)
14989     {
14990       if (!active_seg_prefix)
14991         {
14992           oappend (names_seg[ds_reg - es_reg]);
14993           oappend (":");
14994         }
14995     }
14996   print_operand_value (scratchbuf, 1, off);
14997   oappend (scratchbuf);
14998 }
14999
15000 static void
15001 ptr_reg (int code, int sizeflag)
15002 {
15003   const char *s;
15004
15005   *obufp++ = open_char;
15006   used_prefixes |= (prefixes & PREFIX_ADDR);
15007   if (address_mode == mode_64bit)
15008     {
15009       if (!(sizeflag & AFLAG))
15010         s = names32[code - eAX_reg];
15011       else
15012         s = names64[code - eAX_reg];
15013     }
15014   else if (sizeflag & AFLAG)
15015     s = names32[code - eAX_reg];
15016   else
15017     s = names16[code - eAX_reg];
15018   oappend (s);
15019   *obufp++ = close_char;
15020   *obufp = 0;
15021 }
15022
15023 static void
15024 OP_ESreg (int code, int sizeflag)
15025 {
15026   if (intel_syntax)
15027     {
15028       switch (codep[-1])
15029         {
15030         case 0x6d:      /* insw/insl */
15031           intel_operand_size (z_mode, sizeflag);
15032           break;
15033         case 0xa5:      /* movsw/movsl/movsq */
15034         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
15035         case 0xab:      /* stosw/stosl */
15036         case 0xaf:      /* scasw/scasl */
15037           intel_operand_size (v_mode, sizeflag);
15038           break;
15039         default:
15040           intel_operand_size (b_mode, sizeflag);
15041         }
15042     }
15043   oappend_maybe_intel ("%es:");
15044   ptr_reg (code, sizeflag);
15045 }
15046
15047 static void
15048 OP_DSreg (int code, int sizeflag)
15049 {
15050   if (intel_syntax)
15051     {
15052       switch (codep[-1])
15053         {
15054         case 0x6f:      /* outsw/outsl */
15055           intel_operand_size (z_mode, sizeflag);
15056           break;
15057         case 0xa5:      /* movsw/movsl/movsq */
15058         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
15059         case 0xad:      /* lodsw/lodsl/lodsq */
15060           intel_operand_size (v_mode, sizeflag);
15061           break;
15062         default:
15063           intel_operand_size (b_mode, sizeflag);
15064         }
15065     }
15066   /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
15067      default segment register DS is printed.  */
15068   if (!active_seg_prefix)
15069     active_seg_prefix = PREFIX_DS;
15070   append_seg ();
15071   ptr_reg (code, sizeflag);
15072 }
15073
15074 static void
15075 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15076 {
15077   int add;
15078   if (rex & REX_R)
15079     {
15080       USED_REX (REX_R);
15081       add = 8;
15082     }
15083   else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
15084     {
15085       all_prefixes[last_lock_prefix] = 0;
15086       used_prefixes |= PREFIX_LOCK;
15087       add = 8;
15088     }
15089   else
15090     add = 0;
15091   sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
15092   oappend_maybe_intel (scratchbuf);
15093 }
15094
15095 static void
15096 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15097 {
15098   int add;
15099   USED_REX (REX_R);
15100   if (rex & REX_R)
15101     add = 8;
15102   else
15103     add = 0;
15104   if (intel_syntax)
15105     sprintf (scratchbuf, "db%d", modrm.reg + add);
15106   else
15107     sprintf (scratchbuf, "%%db%d", modrm.reg + add);
15108   oappend (scratchbuf);
15109 }
15110
15111 static void
15112 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15113 {
15114   sprintf (scratchbuf, "%%tr%d", modrm.reg);
15115   oappend_maybe_intel (scratchbuf);
15116 }
15117
15118 static void
15119 OP_R (int bytemode, int sizeflag)
15120 {
15121   /* Skip mod/rm byte.  */
15122   MODRM_CHECK;
15123   codep++;
15124   OP_E_register (bytemode, sizeflag);
15125 }
15126
15127 static void
15128 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15129 {
15130   int reg = modrm.reg;
15131   const char **names;
15132
15133   used_prefixes |= (prefixes & PREFIX_DATA);
15134   if (prefixes & PREFIX_DATA)
15135     {
15136       names = names_xmm;
15137       USED_REX (REX_R);
15138       if (rex & REX_R)
15139         reg += 8;
15140     }
15141   else
15142     names = names_mm;
15143   oappend (names[reg]);
15144 }
15145
15146 static void
15147 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
15148 {
15149   int reg = modrm.reg;
15150   const char **names;
15151
15152   USED_REX (REX_R);
15153   if (rex & REX_R)
15154     reg += 8;
15155   if (vex.evex)
15156     {
15157       if (!vex.r)
15158         reg += 16;
15159     }
15160
15161   if (need_vex
15162       && bytemode != xmm_mode
15163       && bytemode != xmmq_mode
15164       && bytemode != evex_half_bcst_xmmq_mode
15165       && bytemode != ymm_mode
15166       && bytemode != scalar_mode)
15167     {
15168       switch (vex.length)
15169         {
15170         case 128:
15171           names = names_xmm;
15172           break;
15173         case 256:
15174           if (vex.w
15175               || (bytemode != vex_vsib_q_w_dq_mode
15176                   && bytemode != vex_vsib_q_w_d_mode))
15177             names = names_ymm;
15178           else
15179             names = names_xmm;
15180           break;
15181         case 512:
15182           names = names_zmm;
15183           break;
15184         default:
15185           abort ();
15186         }
15187     }
15188   else if (bytemode == xmmq_mode
15189            || bytemode == evex_half_bcst_xmmq_mode)
15190     {
15191       switch (vex.length)
15192         {
15193         case 128:
15194         case 256:
15195           names = names_xmm;
15196           break;
15197         case 512:
15198           names = names_ymm;
15199           break;
15200         default:
15201           abort ();
15202         }
15203     }
15204   else if (bytemode == ymm_mode)
15205     names = names_ymm;
15206   else
15207     names = names_xmm;
15208   oappend (names[reg]);
15209 }
15210
15211 static void
15212 OP_EM (int bytemode, int sizeflag)
15213 {
15214   int reg;
15215   const char **names;
15216
15217   if (modrm.mod != 3)
15218     {
15219       if (intel_syntax
15220           && (bytemode == v_mode || bytemode == v_swap_mode))
15221         {
15222           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
15223           used_prefixes |= (prefixes & PREFIX_DATA);
15224         }
15225       OP_E (bytemode, sizeflag);
15226       return;
15227     }
15228
15229   if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
15230     swap_operand ();
15231
15232   /* Skip mod/rm byte.  */
15233   MODRM_CHECK;
15234   codep++;
15235   used_prefixes |= (prefixes & PREFIX_DATA);
15236   reg = modrm.rm;
15237   if (prefixes & PREFIX_DATA)
15238     {
15239       names = names_xmm;
15240       USED_REX (REX_B);
15241       if (rex & REX_B)
15242         reg += 8;
15243     }
15244   else
15245     names = names_mm;
15246   oappend (names[reg]);
15247 }
15248
15249 /* cvt* are the only instructions in sse2 which have
15250    both SSE and MMX operands and also have 0x66 prefix
15251    in their opcode. 0x66 was originally used to differentiate
15252    between SSE and MMX instruction(operands). So we have to handle the
15253    cvt* separately using OP_EMC and OP_MXC */
15254 static void
15255 OP_EMC (int bytemode, int sizeflag)
15256 {
15257   if (modrm.mod != 3)
15258     {
15259       if (intel_syntax && bytemode == v_mode)
15260         {
15261           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
15262           used_prefixes |= (prefixes & PREFIX_DATA);
15263         }
15264       OP_E (bytemode, sizeflag);
15265       return;
15266     }
15267
15268   /* Skip mod/rm byte.  */
15269   MODRM_CHECK;
15270   codep++;
15271   used_prefixes |= (prefixes & PREFIX_DATA);
15272   oappend (names_mm[modrm.rm]);
15273 }
15274
15275 static void
15276 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15277 {
15278   used_prefixes |= (prefixes & PREFIX_DATA);
15279   oappend (names_mm[modrm.reg]);
15280 }
15281
15282 static void
15283 OP_EX (int bytemode, int sizeflag)
15284 {
15285   int reg;
15286   const char **names;
15287
15288   /* Skip mod/rm byte.  */
15289   MODRM_CHECK;
15290   codep++;
15291
15292   if (modrm.mod != 3)
15293     {
15294       OP_E_memory (bytemode, sizeflag);
15295       return;
15296     }
15297
15298   reg = modrm.rm;
15299   USED_REX (REX_B);
15300   if (rex & REX_B)
15301     reg += 8;
15302   if (vex.evex)
15303     {
15304       USED_REX (REX_X);
15305       if ((rex & REX_X))
15306         reg += 16;
15307     }
15308
15309   if ((sizeflag & SUFFIX_ALWAYS)
15310       && (bytemode == x_swap_mode
15311           || bytemode == d_swap_mode
15312           || bytemode == d_scalar_swap_mode
15313           || bytemode == q_swap_mode
15314           || bytemode == q_scalar_swap_mode))
15315     swap_operand ();
15316
15317   if (need_vex
15318       && bytemode != xmm_mode
15319       && bytemode != xmmdw_mode
15320       && bytemode != xmmqd_mode
15321       && bytemode != xmm_mb_mode
15322       && bytemode != xmm_mw_mode
15323       && bytemode != xmm_md_mode
15324       && bytemode != xmm_mq_mode
15325       && bytemode != xmmq_mode
15326       && bytemode != evex_half_bcst_xmmq_mode
15327       && bytemode != ymm_mode
15328       && bytemode != d_scalar_swap_mode
15329       && bytemode != q_scalar_swap_mode
15330       && bytemode != vex_scalar_w_dq_mode)
15331     {
15332       switch (vex.length)
15333         {
15334         case 128:
15335           names = names_xmm;
15336           break;
15337         case 256:
15338           names = names_ymm;
15339           break;
15340         case 512:
15341           names = names_zmm;
15342           break;
15343         default:
15344           abort ();
15345         }
15346     }
15347   else if (bytemode == xmmq_mode
15348            || bytemode == evex_half_bcst_xmmq_mode)
15349     {
15350       switch (vex.length)
15351         {
15352         case 128:
15353         case 256:
15354           names = names_xmm;
15355           break;
15356         case 512:
15357           names = names_ymm;
15358           break;
15359         default:
15360           abort ();
15361         }
15362     }
15363   else if (bytemode == ymm_mode)
15364     names = names_ymm;
15365   else
15366     names = names_xmm;
15367   oappend (names[reg]);
15368 }
15369
15370 static void
15371 OP_MS (int bytemode, int sizeflag)
15372 {
15373   if (modrm.mod == 3)
15374     OP_EM (bytemode, sizeflag);
15375   else
15376     BadOp ();
15377 }
15378
15379 static void
15380 OP_XS (int bytemode, int sizeflag)
15381 {
15382   if (modrm.mod == 3)
15383     OP_EX (bytemode, sizeflag);
15384   else
15385     BadOp ();
15386 }
15387
15388 static void
15389 OP_M (int bytemode, int sizeflag)
15390 {
15391   if (modrm.mod == 3)
15392     /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
15393     BadOp ();
15394   else
15395     OP_E (bytemode, sizeflag);
15396 }
15397
15398 static void
15399 OP_0f07 (int bytemode, int sizeflag)
15400 {
15401   if (modrm.mod != 3 || modrm.rm != 0)
15402     BadOp ();
15403   else
15404     OP_E (bytemode, sizeflag);
15405 }
15406
15407 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
15408    32bit mode and "xchg %rax,%rax" in 64bit mode.  */
15409
15410 static void
15411 NOP_Fixup1 (int bytemode, int sizeflag)
15412 {
15413   if ((prefixes & PREFIX_DATA) != 0
15414       || (rex != 0
15415           && rex != 0x48
15416           && address_mode == mode_64bit))
15417     OP_REG (bytemode, sizeflag);
15418   else
15419     strcpy (obuf, "nop");
15420 }
15421
15422 static void
15423 NOP_Fixup2 (int bytemode, int sizeflag)
15424 {
15425   if ((prefixes & PREFIX_DATA) != 0
15426       || (rex != 0
15427           && rex != 0x48
15428           && address_mode == mode_64bit))
15429     OP_IMREG (bytemode, sizeflag);
15430 }
15431
15432 static const char *const Suffix3DNow[] = {
15433 /* 00 */        NULL,           NULL,           NULL,           NULL,
15434 /* 04 */        NULL,           NULL,           NULL,           NULL,
15435 /* 08 */        NULL,           NULL,           NULL,           NULL,
15436 /* 0C */        "pi2fw",        "pi2fd",        NULL,           NULL,
15437 /* 10 */        NULL,           NULL,           NULL,           NULL,
15438 /* 14 */        NULL,           NULL,           NULL,           NULL,
15439 /* 18 */        NULL,           NULL,           NULL,           NULL,
15440 /* 1C */        "pf2iw",        "pf2id",        NULL,           NULL,
15441 /* 20 */        NULL,           NULL,           NULL,           NULL,
15442 /* 24 */        NULL,           NULL,           NULL,           NULL,
15443 /* 28 */        NULL,           NULL,           NULL,           NULL,
15444 /* 2C */        NULL,           NULL,           NULL,           NULL,
15445 /* 30 */        NULL,           NULL,           NULL,           NULL,
15446 /* 34 */        NULL,           NULL,           NULL,           NULL,
15447 /* 38 */        NULL,           NULL,           NULL,           NULL,
15448 /* 3C */        NULL,           NULL,           NULL,           NULL,
15449 /* 40 */        NULL,           NULL,           NULL,           NULL,
15450 /* 44 */        NULL,           NULL,           NULL,           NULL,
15451 /* 48 */        NULL,           NULL,           NULL,           NULL,
15452 /* 4C */        NULL,           NULL,           NULL,           NULL,
15453 /* 50 */        NULL,           NULL,           NULL,           NULL,
15454 /* 54 */        NULL,           NULL,           NULL,           NULL,
15455 /* 58 */        NULL,           NULL,           NULL,           NULL,
15456 /* 5C */        NULL,           NULL,           NULL,           NULL,
15457 /* 60 */        NULL,           NULL,           NULL,           NULL,
15458 /* 64 */        NULL,           NULL,           NULL,           NULL,
15459 /* 68 */        NULL,           NULL,           NULL,           NULL,
15460 /* 6C */        NULL,           NULL,           NULL,           NULL,
15461 /* 70 */        NULL,           NULL,           NULL,           NULL,
15462 /* 74 */        NULL,           NULL,           NULL,           NULL,
15463 /* 78 */        NULL,           NULL,           NULL,           NULL,
15464 /* 7C */        NULL,           NULL,           NULL,           NULL,
15465 /* 80 */        NULL,           NULL,           NULL,           NULL,
15466 /* 84 */        NULL,           NULL,           NULL,           NULL,
15467 /* 88 */        NULL,           NULL,           "pfnacc",       NULL,
15468 /* 8C */        NULL,           NULL,           "pfpnacc",      NULL,
15469 /* 90 */        "pfcmpge",      NULL,           NULL,           NULL,
15470 /* 94 */        "pfmin",        NULL,           "pfrcp",        "pfrsqrt",
15471 /* 98 */        NULL,           NULL,           "pfsub",        NULL,
15472 /* 9C */        NULL,           NULL,           "pfadd",        NULL,
15473 /* A0 */        "pfcmpgt",      NULL,           NULL,           NULL,
15474 /* A4 */        "pfmax",        NULL,           "pfrcpit1",     "pfrsqit1",
15475 /* A8 */        NULL,           NULL,           "pfsubr",       NULL,
15476 /* AC */        NULL,           NULL,           "pfacc",        NULL,
15477 /* B0 */        "pfcmpeq",      NULL,           NULL,           NULL,
15478 /* B4 */        "pfmul",        NULL,           "pfrcpit2",     "pmulhrw",
15479 /* B8 */        NULL,           NULL,           NULL,           "pswapd",
15480 /* BC */        NULL,           NULL,           NULL,           "pavgusb",
15481 /* C0 */        NULL,           NULL,           NULL,           NULL,
15482 /* C4 */        NULL,           NULL,           NULL,           NULL,
15483 /* C8 */        NULL,           NULL,           NULL,           NULL,
15484 /* CC */        NULL,           NULL,           NULL,           NULL,
15485 /* D0 */        NULL,           NULL,           NULL,           NULL,
15486 /* D4 */        NULL,           NULL,           NULL,           NULL,
15487 /* D8 */        NULL,           NULL,           NULL,           NULL,
15488 /* DC */        NULL,           NULL,           NULL,           NULL,
15489 /* E0 */        NULL,           NULL,           NULL,           NULL,
15490 /* E4 */        NULL,           NULL,           NULL,           NULL,
15491 /* E8 */        NULL,           NULL,           NULL,           NULL,
15492 /* EC */        NULL,           NULL,           NULL,           NULL,
15493 /* F0 */        NULL,           NULL,           NULL,           NULL,
15494 /* F4 */        NULL,           NULL,           NULL,           NULL,
15495 /* F8 */        NULL,           NULL,           NULL,           NULL,
15496 /* FC */        NULL,           NULL,           NULL,           NULL,
15497 };
15498
15499 static void
15500 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15501 {
15502   const char *mnemonic;
15503
15504   FETCH_DATA (the_info, codep + 1);
15505   /* AMD 3DNow! instructions are specified by an opcode suffix in the
15506      place where an 8-bit immediate would normally go.  ie. the last
15507      byte of the instruction.  */
15508   obufp = mnemonicendp;
15509   mnemonic = Suffix3DNow[*codep++ & 0xff];
15510   if (mnemonic)
15511     oappend (mnemonic);
15512   else
15513     {
15514       /* Since a variable sized modrm/sib chunk is between the start
15515          of the opcode (0x0f0f) and the opcode suffix, we need to do
15516          all the modrm processing first, and don't know until now that
15517          we have a bad opcode.  This necessitates some cleaning up.  */
15518       op_out[0][0] = '\0';
15519       op_out[1][0] = '\0';
15520       BadOp ();
15521     }
15522   mnemonicendp = obufp;
15523 }
15524
15525 static struct op simd_cmp_op[] =
15526 {
15527   { STRING_COMMA_LEN ("eq") },
15528   { STRING_COMMA_LEN ("lt") },
15529   { STRING_COMMA_LEN ("le") },
15530   { STRING_COMMA_LEN ("unord") },
15531   { STRING_COMMA_LEN ("neq") },
15532   { STRING_COMMA_LEN ("nlt") },
15533   { STRING_COMMA_LEN ("nle") },
15534   { STRING_COMMA_LEN ("ord") }
15535 };
15536
15537 static void
15538 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15539 {
15540   unsigned int cmp_type;
15541
15542   FETCH_DATA (the_info, codep + 1);
15543   cmp_type = *codep++ & 0xff;
15544   if (cmp_type < ARRAY_SIZE (simd_cmp_op))
15545     {
15546       char suffix [3];
15547       char *p = mnemonicendp - 2;
15548       suffix[0] = p[0];
15549       suffix[1] = p[1];
15550       suffix[2] = '\0';
15551       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
15552       mnemonicendp += simd_cmp_op[cmp_type].len;
15553     }
15554   else
15555     {
15556       /* We have a reserved extension byte.  Output it directly.  */
15557       scratchbuf[0] = '$';
15558       print_operand_value (scratchbuf + 1, 1, cmp_type);
15559       oappend_maybe_intel (scratchbuf);
15560       scratchbuf[0] = '\0';
15561     }
15562 }
15563
15564 static void
15565 OP_Mwait (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
15566 {
15567   /* mwait %eax,%ecx / mwaitx %eax,%ecx,%ebx  */
15568   if (!intel_syntax)
15569     {
15570       strcpy (op_out[0], names32[0]);
15571       strcpy (op_out[1], names32[1]);
15572       if (bytemode == eBX_reg)
15573         strcpy (op_out[2], names32[3]);
15574       two_source_ops = 1;
15575     }
15576   /* Skip mod/rm byte.  */
15577   MODRM_CHECK;
15578   codep++;
15579 }
15580
15581 static void
15582 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
15583             int sizeflag ATTRIBUTE_UNUSED)
15584 {
15585   /* monitor %{e,r,}ax,%ecx,%edx"  */
15586   if (!intel_syntax)
15587     {
15588       const char **names = (address_mode == mode_64bit
15589                             ? names64 : names32);
15590
15591       if (prefixes & PREFIX_ADDR)
15592         {
15593           /* Remove "addr16/addr32".  */
15594           all_prefixes[last_addr_prefix] = 0;
15595           names = (address_mode != mode_32bit
15596                    ? names32 : names16);
15597           used_prefixes |= PREFIX_ADDR;
15598         }
15599       else if (address_mode == mode_16bit)
15600         names = names16;
15601       strcpy (op_out[0], names[0]);
15602       strcpy (op_out[1], names32[1]);
15603       strcpy (op_out[2], names32[2]);
15604       two_source_ops = 1;
15605     }
15606   /* Skip mod/rm byte.  */
15607   MODRM_CHECK;
15608   codep++;
15609 }
15610
15611 static void
15612 BadOp (void)
15613 {
15614   /* Throw away prefixes and 1st. opcode byte.  */
15615   codep = insn_codep + 1;
15616   oappend ("(bad)");
15617 }
15618
15619 static void
15620 REP_Fixup (int bytemode, int sizeflag)
15621 {
15622   /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
15623      lods and stos.  */
15624   if (prefixes & PREFIX_REPZ)
15625     all_prefixes[last_repz_prefix] = REP_PREFIX;
15626
15627   switch (bytemode)
15628     {
15629     case al_reg:
15630     case eAX_reg:
15631     case indir_dx_reg:
15632       OP_IMREG (bytemode, sizeflag);
15633       break;
15634     case eDI_reg:
15635       OP_ESreg (bytemode, sizeflag);
15636       break;
15637     case eSI_reg:
15638       OP_DSreg (bytemode, sizeflag);
15639       break;
15640     default:
15641       abort ();
15642       break;
15643     }
15644 }
15645
15646 static void
15647 SEP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15648 {
15649   if ( isa64 != amd64 )
15650     return;
15651
15652   obufp = obuf;
15653   BadOp ();
15654   mnemonicendp = obufp;
15655   ++codep;
15656 }
15657
15658 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
15659    "bnd".  */
15660
15661 static void
15662 BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15663 {
15664   if (prefixes & PREFIX_REPNZ)
15665     all_prefixes[last_repnz_prefix] = BND_PREFIX;
15666 }
15667
15668 /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
15669    "notrack".  */
15670
15671 static void
15672 NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED,
15673                int sizeflag ATTRIBUTE_UNUSED)
15674 {
15675   if (active_seg_prefix == PREFIX_DS
15676       && (address_mode != mode_64bit || last_data_prefix < 0))
15677     {
15678       /* NOTRACK prefix is only valid on indirect branch instructions.
15679          NB: DATA prefix is unsupported for Intel64.  */
15680       active_seg_prefix = 0;
15681       all_prefixes[last_seg_prefix] = NOTRACK_PREFIX;
15682     }
15683 }
15684
15685 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
15686    "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
15687  */
15688
15689 static void
15690 HLE_Fixup1 (int bytemode, int sizeflag)
15691 {
15692   if (modrm.mod != 3
15693       && (prefixes & PREFIX_LOCK) != 0)
15694     {
15695       if (prefixes & PREFIX_REPZ)
15696         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15697       if (prefixes & PREFIX_REPNZ)
15698         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15699     }
15700
15701   OP_E (bytemode, sizeflag);
15702 }
15703
15704 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
15705    "xacquire"/"xrelease" for memory operand.  No check for LOCK prefix.
15706  */
15707
15708 static void
15709 HLE_Fixup2 (int bytemode, int sizeflag)
15710 {
15711   if (modrm.mod != 3)
15712     {
15713       if (prefixes & PREFIX_REPZ)
15714         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15715       if (prefixes & PREFIX_REPNZ)
15716         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15717     }
15718
15719   OP_E (bytemode, sizeflag);
15720 }
15721
15722 /* Similar to OP_E.  But the 0xf3 prefixes should be displayed as
15723    "xrelease" for memory operand.  No check for LOCK prefix.   */
15724
15725 static void
15726 HLE_Fixup3 (int bytemode, int sizeflag)
15727 {
15728   if (modrm.mod != 3
15729       && last_repz_prefix > last_repnz_prefix
15730       && (prefixes & PREFIX_REPZ) != 0)
15731     all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15732
15733   OP_E (bytemode, sizeflag);
15734 }
15735
15736 static void
15737 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
15738 {
15739   USED_REX (REX_W);
15740   if (rex & REX_W)
15741     {
15742       /* Change cmpxchg8b to cmpxchg16b.  */
15743       char *p = mnemonicendp - 2;
15744       mnemonicendp = stpcpy (p, "16b");
15745       bytemode = o_mode;
15746     }
15747   else if ((prefixes & PREFIX_LOCK) != 0)
15748     {
15749       if (prefixes & PREFIX_REPZ)
15750         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15751       if (prefixes & PREFIX_REPNZ)
15752         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15753     }
15754
15755   OP_M (bytemode, sizeflag);
15756 }
15757
15758 static void
15759 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
15760 {
15761   const char **names;
15762
15763   if (need_vex)
15764     {
15765       switch (vex.length)
15766         {
15767         case 128:
15768           names = names_xmm;
15769           break;
15770         case 256:
15771           names = names_ymm;
15772           break;
15773         default:
15774           abort ();
15775         }
15776     }
15777   else
15778     names = names_xmm;
15779   oappend (names[reg]);
15780 }
15781
15782 static void
15783 CRC32_Fixup (int bytemode, int sizeflag)
15784 {
15785   /* Add proper suffix to "crc32".  */
15786   char *p = mnemonicendp;
15787
15788   switch (bytemode)
15789     {
15790     case b_mode:
15791       if (intel_syntax)
15792         goto skip;
15793
15794       *p++ = 'b';
15795       break;
15796     case v_mode:
15797       if (intel_syntax)
15798         goto skip;
15799
15800       USED_REX (REX_W);
15801       if (rex & REX_W)
15802         *p++ = 'q';
15803       else
15804         {
15805           if (sizeflag & DFLAG)
15806             *p++ = 'l';
15807           else
15808             *p++ = 'w';
15809           used_prefixes |= (prefixes & PREFIX_DATA);
15810         }
15811       break;
15812     default:
15813       oappend (INTERNAL_DISASSEMBLER_ERROR);
15814       break;
15815     }
15816   mnemonicendp = p;
15817   *p = '\0';
15818
15819  skip:
15820   if (modrm.mod == 3)
15821     {
15822       int add;
15823
15824       /* Skip mod/rm byte.  */
15825       MODRM_CHECK;
15826       codep++;
15827
15828       USED_REX (REX_B);
15829       add = (rex & REX_B) ? 8 : 0;
15830       if (bytemode == b_mode)
15831         {
15832           USED_REX (0);
15833           if (rex)
15834             oappend (names8rex[modrm.rm + add]);
15835           else
15836             oappend (names8[modrm.rm + add]);
15837         }
15838       else
15839         {
15840           USED_REX (REX_W);
15841           if (rex & REX_W)
15842             oappend (names64[modrm.rm + add]);
15843           else if ((prefixes & PREFIX_DATA))
15844             oappend (names16[modrm.rm + add]);
15845           else
15846             oappend (names32[modrm.rm + add]);
15847         }
15848     }
15849   else
15850     OP_E (bytemode, sizeflag);
15851 }
15852
15853 static void
15854 FXSAVE_Fixup (int bytemode, int sizeflag)
15855 {
15856   /* Add proper suffix to "fxsave" and "fxrstor".  */
15857   USED_REX (REX_W);
15858   if (rex & REX_W)
15859     {
15860       char *p = mnemonicendp;
15861       *p++ = '6';
15862       *p++ = '4';
15863       *p = '\0';
15864       mnemonicendp = p;
15865     }
15866   OP_M (bytemode, sizeflag);
15867 }
15868
15869 static void
15870 PCMPESTR_Fixup (int bytemode, int sizeflag)
15871 {
15872   /* Add proper suffix to "{,v}pcmpestr{i,m}".  */
15873   if (!intel_syntax)
15874     {
15875       char *p = mnemonicendp;
15876
15877       USED_REX (REX_W);
15878       if (rex & REX_W)
15879         *p++ = 'q';
15880       else if (sizeflag & SUFFIX_ALWAYS)
15881         *p++ = 'l';
15882
15883       *p = '\0';
15884       mnemonicendp = p;
15885     }
15886
15887   OP_EX (bytemode, sizeflag);
15888 }
15889
15890 /* Display the destination register operand for instructions with
15891    VEX. */
15892
15893 static void
15894 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
15895 {
15896   int reg;
15897   const char **names;
15898
15899   if (!need_vex)
15900     abort ();
15901
15902   if (!need_vex_reg)
15903     return;
15904
15905   reg = vex.register_specifier;
15906   vex.register_specifier = 0;
15907   if (address_mode != mode_64bit)
15908     reg &= 7;
15909   else if (vex.evex && !vex.v)
15910     reg += 16;
15911
15912   if (bytemode == vex_scalar_mode)
15913     {
15914       oappend (names_xmm[reg]);
15915       return;
15916     }
15917
15918   switch (vex.length)
15919     {
15920     case 128:
15921       switch (bytemode)
15922         {
15923         case vex_mode:
15924         case vex128_mode:
15925         case vex_vsib_q_w_dq_mode:
15926         case vex_vsib_q_w_d_mode:
15927           names = names_xmm;
15928           break;
15929         case dq_mode:
15930           if (rex & REX_W)
15931             names = names64;
15932           else
15933             names = names32;
15934           break;
15935         case mask_bd_mode:
15936         case mask_mode:
15937           if (reg > 0x7)
15938             {
15939               oappend ("(bad)");
15940               return;
15941             }
15942           names = names_mask;
15943           break;
15944         default:
15945           abort ();
15946           return;
15947         }
15948       break;
15949     case 256:
15950       switch (bytemode)
15951         {
15952         case vex_mode:
15953         case vex256_mode:
15954           names = names_ymm;
15955           break;
15956         case vex_vsib_q_w_dq_mode:
15957         case vex_vsib_q_w_d_mode:
15958           names = vex.w ? names_ymm : names_xmm;
15959           break;
15960         case mask_bd_mode:
15961         case mask_mode:
15962           if (reg > 0x7)
15963             {
15964               oappend ("(bad)");
15965               return;
15966             }
15967           names = names_mask;
15968           break;
15969         default:
15970           /* See PR binutils/20893 for a reproducer.  */
15971           oappend ("(bad)");
15972           return;
15973         }
15974       break;
15975     case 512:
15976       names = names_zmm;
15977       break;
15978     default:
15979       abort ();
15980       break;
15981     }
15982   oappend (names[reg]);
15983 }
15984
15985 /* Get the VEX immediate byte without moving codep.  */
15986
15987 static unsigned char
15988 get_vex_imm8 (int sizeflag, int opnum)
15989 {
15990   int bytes_before_imm = 0;
15991
15992   if (modrm.mod != 3)
15993     {
15994       /* There are SIB/displacement bytes.  */
15995       if ((sizeflag & AFLAG) || address_mode == mode_64bit)
15996         {
15997           /* 32/64 bit address mode */
15998           int base = modrm.rm;
15999
16000           /* Check SIB byte.  */
16001           if (base == 4)
16002             {
16003               FETCH_DATA (the_info, codep + 1);
16004               base = *codep & 7;
16005               /* When decoding the third source, don't increase
16006                  bytes_before_imm as this has already been incremented
16007                  by one in OP_E_memory while decoding the second
16008                  source operand.  */
16009               if (opnum == 0)
16010                 bytes_before_imm++;
16011             }
16012
16013           /* Don't increase bytes_before_imm when decoding the third source,
16014              it has already been incremented by OP_E_memory while decoding
16015              the second source operand.  */
16016           if (opnum == 0)
16017             {
16018               switch (modrm.mod)
16019                 {
16020                   case 0:
16021                     /* When modrm.rm == 5 or modrm.rm == 4 and base in
16022                        SIB == 5, there is a 4 byte displacement.  */
16023                     if (base != 5)
16024                       /* No displacement. */
16025                       break;
16026                     /* Fall through.  */
16027                   case 2:
16028                     /* 4 byte displacement.  */
16029                     bytes_before_imm += 4;
16030                     break;
16031                   case 1:
16032                     /* 1 byte displacement.  */
16033                     bytes_before_imm++;
16034                     break;
16035                 }
16036             }
16037         }
16038       else
16039         {
16040           /* 16 bit address mode */
16041           /* Don't increase bytes_before_imm when decoding the third source,
16042              it has already been incremented by OP_E_memory while decoding
16043              the second source operand.  */
16044           if (opnum == 0)
16045             {
16046               switch (modrm.mod)
16047                 {
16048                 case 0:
16049                   /* When modrm.rm == 6, there is a 2 byte displacement.  */
16050                   if (modrm.rm != 6)
16051                     /* No displacement. */
16052                     break;
16053                   /* Fall through.  */
16054                 case 2:
16055                   /* 2 byte displacement.  */
16056                   bytes_before_imm += 2;
16057                   break;
16058                 case 1:
16059                   /* 1 byte displacement: when decoding the third source,
16060                      don't increase bytes_before_imm as this has already
16061                      been incremented by one in OP_E_memory while decoding
16062                      the second source operand.  */
16063                   if (opnum == 0)
16064                     bytes_before_imm++;
16065
16066                   break;
16067                 }
16068             }
16069         }
16070     }
16071
16072   FETCH_DATA (the_info, codep + bytes_before_imm + 1);
16073   return codep [bytes_before_imm];
16074 }
16075
16076 static void
16077 OP_EX_VexReg (int bytemode, int sizeflag, int reg)
16078 {
16079   const char **names;
16080
16081   if (reg == -1 && modrm.mod != 3)
16082     {
16083       OP_E_memory (bytemode, sizeflag);
16084       return;
16085     }
16086   else
16087     {
16088       if (reg == -1)
16089         {
16090           reg = modrm.rm;
16091           USED_REX (REX_B);
16092           if (rex & REX_B)
16093             reg += 8;
16094         }
16095       if (address_mode != mode_64bit)
16096         reg &= 7;
16097     }
16098
16099   switch (vex.length)
16100     {
16101     case 128:
16102       names = names_xmm;
16103       break;
16104     case 256:
16105       names = names_ymm;
16106       break;
16107     default:
16108       abort ();
16109     }
16110   oappend (names[reg]);
16111 }
16112
16113 static void
16114 OP_EX_VexImmW (int bytemode, int sizeflag)
16115 {
16116   int reg = -1;
16117   static unsigned char vex_imm8;
16118
16119   if (vex_w_done == 0)
16120     {
16121       vex_w_done = 1;
16122
16123       /* Skip mod/rm byte.  */
16124       MODRM_CHECK;
16125       codep++;
16126
16127       vex_imm8 = get_vex_imm8 (sizeflag, 0);
16128
16129       if (vex.w)
16130           reg = vex_imm8 >> 4;
16131
16132       OP_EX_VexReg (bytemode, sizeflag, reg);
16133     }
16134   else if (vex_w_done == 1)
16135     {
16136       vex_w_done = 2;
16137
16138       if (!vex.w)
16139           reg = vex_imm8 >> 4;
16140
16141       OP_EX_VexReg (bytemode, sizeflag, reg);
16142     }
16143   else
16144     {
16145       /* Output the imm8 directly.  */
16146       scratchbuf[0] = '$';
16147       print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf);
16148       oappend_maybe_intel (scratchbuf);
16149       scratchbuf[0] = '\0';
16150       codep++;
16151     }
16152 }
16153
16154 static void
16155 OP_Vex_2src (int bytemode, int sizeflag)
16156 {
16157   if (modrm.mod == 3)
16158     {
16159       int reg = modrm.rm;
16160       USED_REX (REX_B);
16161       if (rex & REX_B)
16162         reg += 8;
16163       oappend (names_xmm[reg]);
16164     }
16165   else
16166     {
16167       if (intel_syntax
16168           && (bytemode == v_mode || bytemode == v_swap_mode))
16169         {
16170           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16171           used_prefixes |= (prefixes & PREFIX_DATA);
16172         }
16173       OP_E (bytemode, sizeflag);
16174     }
16175 }
16176
16177 static void
16178 OP_Vex_2src_1 (int bytemode, int sizeflag)
16179 {
16180   if (modrm.mod == 3)
16181     {
16182       /* Skip mod/rm byte.   */
16183       MODRM_CHECK;
16184       codep++;
16185     }
16186
16187   if (vex.w)
16188     {
16189       unsigned int reg = vex.register_specifier;
16190       vex.register_specifier = 0;
16191
16192       if (address_mode != mode_64bit)
16193         reg &= 7;
16194       oappend (names_xmm[reg]);
16195     }
16196   else
16197     OP_Vex_2src (bytemode, sizeflag);
16198 }
16199
16200 static void
16201 OP_Vex_2src_2 (int bytemode, int sizeflag)
16202 {
16203   if (vex.w)
16204     OP_Vex_2src (bytemode, sizeflag);
16205   else
16206     {
16207       unsigned int reg = vex.register_specifier;
16208       vex.register_specifier = 0;
16209
16210       if (address_mode != mode_64bit)
16211         reg &= 7;
16212       oappend (names_xmm[reg]);
16213     }
16214 }
16215
16216 static void
16217 OP_EX_VexW (int bytemode, int sizeflag)
16218 {
16219   int reg = -1;
16220
16221   if (!vex_w_done)
16222     {
16223       /* Skip mod/rm byte.  */
16224       MODRM_CHECK;
16225       codep++;
16226
16227       if (vex.w)
16228         reg = get_vex_imm8 (sizeflag, 0) >> 4;
16229     }
16230   else
16231     {
16232       if (!vex.w)
16233         reg = get_vex_imm8 (sizeflag, 1) >> 4;
16234     }
16235
16236   OP_EX_VexReg (bytemode, sizeflag, reg);
16237
16238   if (vex_w_done)
16239     codep++;
16240   vex_w_done = 1;
16241 }
16242
16243 static void
16244 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16245 {
16246   int reg;
16247   const char **names;
16248
16249   FETCH_DATA (the_info, codep + 1);
16250   reg = *codep++;
16251
16252   if (bytemode != x_mode)
16253     abort ();
16254
16255   reg >>= 4;
16256   if (address_mode != mode_64bit)
16257     reg &= 7;
16258
16259   switch (vex.length)
16260     {
16261     case 128:
16262       names = names_xmm;
16263       break;
16264     case 256:
16265       names = names_ymm;
16266       break;
16267     default:
16268       abort ();
16269     }
16270   oappend (names[reg]);
16271 }
16272
16273 static void
16274 OP_XMM_VexW (int bytemode, int sizeflag)
16275 {
16276   /* Turn off the REX.W bit since it is used for swapping operands
16277      now.  */
16278   rex &= ~REX_W;
16279   OP_XMM (bytemode, sizeflag);
16280 }
16281
16282 static void
16283 OP_EX_Vex (int bytemode, int sizeflag)
16284 {
16285   if (modrm.mod != 3)
16286     need_vex_reg = 0;
16287   OP_EX (bytemode, sizeflag);
16288 }
16289
16290 static void
16291 OP_XMM_Vex (int bytemode, int sizeflag)
16292 {
16293   if (modrm.mod != 3)
16294     need_vex_reg = 0;
16295   OP_XMM (bytemode, sizeflag);
16296 }
16297
16298 static struct op vex_cmp_op[] =
16299 {
16300   { STRING_COMMA_LEN ("eq") },
16301   { STRING_COMMA_LEN ("lt") },
16302   { STRING_COMMA_LEN ("le") },
16303   { STRING_COMMA_LEN ("unord") },
16304   { STRING_COMMA_LEN ("neq") },
16305   { STRING_COMMA_LEN ("nlt") },
16306   { STRING_COMMA_LEN ("nle") },
16307   { STRING_COMMA_LEN ("ord") },
16308   { STRING_COMMA_LEN ("eq_uq") },
16309   { STRING_COMMA_LEN ("nge") },
16310   { STRING_COMMA_LEN ("ngt") },
16311   { STRING_COMMA_LEN ("false") },
16312   { STRING_COMMA_LEN ("neq_oq") },
16313   { STRING_COMMA_LEN ("ge") },
16314   { STRING_COMMA_LEN ("gt") },
16315   { STRING_COMMA_LEN ("true") },
16316   { STRING_COMMA_LEN ("eq_os") },
16317   { STRING_COMMA_LEN ("lt_oq") },
16318   { STRING_COMMA_LEN ("le_oq") },
16319   { STRING_COMMA_LEN ("unord_s") },
16320   { STRING_COMMA_LEN ("neq_us") },
16321   { STRING_COMMA_LEN ("nlt_uq") },
16322   { STRING_COMMA_LEN ("nle_uq") },
16323   { STRING_COMMA_LEN ("ord_s") },
16324   { STRING_COMMA_LEN ("eq_us") },
16325   { STRING_COMMA_LEN ("nge_uq") },
16326   { STRING_COMMA_LEN ("ngt_uq") },
16327   { STRING_COMMA_LEN ("false_os") },
16328   { STRING_COMMA_LEN ("neq_os") },
16329   { STRING_COMMA_LEN ("ge_oq") },
16330   { STRING_COMMA_LEN ("gt_oq") },
16331   { STRING_COMMA_LEN ("true_us") },
16332 };
16333
16334 static void
16335 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16336 {
16337   unsigned int cmp_type;
16338
16339   FETCH_DATA (the_info, codep + 1);
16340   cmp_type = *codep++ & 0xff;
16341   if (cmp_type < ARRAY_SIZE (vex_cmp_op))
16342     {
16343       char suffix [3];
16344       char *p = mnemonicendp - 2;
16345       suffix[0] = p[0];
16346       suffix[1] = p[1];
16347       suffix[2] = '\0';
16348       sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
16349       mnemonicendp += vex_cmp_op[cmp_type].len;
16350     }
16351   else
16352     {
16353       /* We have a reserved extension byte.  Output it directly.  */
16354       scratchbuf[0] = '$';
16355       print_operand_value (scratchbuf + 1, 1, cmp_type);
16356       oappend_maybe_intel (scratchbuf);
16357       scratchbuf[0] = '\0';
16358     }
16359 }
16360
16361 static void
16362 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED,
16363              int sizeflag ATTRIBUTE_UNUSED)
16364 {
16365   unsigned int cmp_type;
16366
16367   if (!vex.evex)
16368     abort ();
16369
16370   FETCH_DATA (the_info, codep + 1);
16371   cmp_type = *codep++ & 0xff;
16372   /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
16373      If it's the case, print suffix, otherwise - print the immediate.  */
16374   if (cmp_type < ARRAY_SIZE (simd_cmp_op)
16375       && cmp_type != 3
16376       && cmp_type != 7)
16377     {
16378       char suffix [3];
16379       char *p = mnemonicendp - 2;
16380
16381       /* vpcmp* can have both one- and two-lettered suffix.  */
16382       if (p[0] == 'p')
16383         {
16384           p++;
16385           suffix[0] = p[0];
16386           suffix[1] = '\0';
16387         }
16388       else
16389         {
16390           suffix[0] = p[0];
16391           suffix[1] = p[1];
16392           suffix[2] = '\0';
16393         }
16394
16395       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
16396       mnemonicendp += simd_cmp_op[cmp_type].len;
16397     }
16398   else
16399     {
16400       /* We have a reserved extension byte.  Output it directly.  */
16401       scratchbuf[0] = '$';
16402       print_operand_value (scratchbuf + 1, 1, cmp_type);
16403       oappend_maybe_intel (scratchbuf);
16404       scratchbuf[0] = '\0';
16405     }
16406 }
16407
16408 static const struct op xop_cmp_op[] =
16409 {
16410   { STRING_COMMA_LEN ("lt") },
16411   { STRING_COMMA_LEN ("le") },
16412   { STRING_COMMA_LEN ("gt") },
16413   { STRING_COMMA_LEN ("ge") },
16414   { STRING_COMMA_LEN ("eq") },
16415   { STRING_COMMA_LEN ("neq") },
16416   { STRING_COMMA_LEN ("false") },
16417   { STRING_COMMA_LEN ("true") }
16418 };
16419
16420 static void
16421 VPCOM_Fixup (int bytemode ATTRIBUTE_UNUSED,
16422              int sizeflag ATTRIBUTE_UNUSED)
16423 {
16424   unsigned int cmp_type;
16425
16426   FETCH_DATA (the_info, codep + 1);
16427   cmp_type = *codep++ & 0xff;
16428   if (cmp_type < ARRAY_SIZE (xop_cmp_op))
16429     {
16430       char suffix[3];
16431       char *p = mnemonicendp - 2;
16432
16433       /* vpcom* can have both one- and two-lettered suffix.  */
16434       if (p[0] == 'm')
16435         {
16436           p++;
16437           suffix[0] = p[0];
16438           suffix[1] = '\0';
16439         }
16440       else
16441         {
16442           suffix[0] = p[0];
16443           suffix[1] = p[1];
16444           suffix[2] = '\0';
16445         }
16446
16447       sprintf (p, "%s%s", xop_cmp_op[cmp_type].name, suffix);
16448       mnemonicendp += xop_cmp_op[cmp_type].len;
16449     }
16450   else
16451     {
16452       /* We have a reserved extension byte.  Output it directly.  */
16453       scratchbuf[0] = '$';
16454       print_operand_value (scratchbuf + 1, 1, cmp_type);
16455       oappend_maybe_intel (scratchbuf);
16456       scratchbuf[0] = '\0';
16457     }
16458 }
16459
16460 static const struct op pclmul_op[] =
16461 {
16462   { STRING_COMMA_LEN ("lql") },
16463   { STRING_COMMA_LEN ("hql") },
16464   { STRING_COMMA_LEN ("lqh") },
16465   { STRING_COMMA_LEN ("hqh") }
16466 };
16467
16468 static void
16469 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
16470               int sizeflag ATTRIBUTE_UNUSED)
16471 {
16472   unsigned int pclmul_type;
16473
16474   FETCH_DATA (the_info, codep + 1);
16475   pclmul_type = *codep++ & 0xff;
16476   switch (pclmul_type)
16477     {
16478     case 0x10:
16479       pclmul_type = 2;
16480       break;
16481     case 0x11:
16482       pclmul_type = 3;
16483       break;
16484     default:
16485       break;
16486     }
16487   if (pclmul_type < ARRAY_SIZE (pclmul_op))
16488     {
16489       char suffix [4];
16490       char *p = mnemonicendp - 3;
16491       suffix[0] = p[0];
16492       suffix[1] = p[1];
16493       suffix[2] = p[2];
16494       suffix[3] = '\0';
16495       sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
16496       mnemonicendp += pclmul_op[pclmul_type].len;
16497     }
16498   else
16499     {
16500       /* We have a reserved extension byte.  Output it directly.  */
16501       scratchbuf[0] = '$';
16502       print_operand_value (scratchbuf + 1, 1, pclmul_type);
16503       oappend_maybe_intel (scratchbuf);
16504       scratchbuf[0] = '\0';
16505     }
16506 }
16507
16508 static void
16509 MOVBE_Fixup (int bytemode, int sizeflag)
16510 {
16511   /* Add proper suffix to "movbe".  */
16512   char *p = mnemonicendp;
16513
16514   switch (bytemode)
16515     {
16516     case v_mode:
16517       if (intel_syntax)
16518         goto skip;
16519
16520       USED_REX (REX_W);
16521       if (sizeflag & SUFFIX_ALWAYS)
16522         {
16523           if (rex & REX_W)
16524             *p++ = 'q';
16525           else
16526             {
16527               if (sizeflag & DFLAG)
16528                 *p++ = 'l';
16529               else
16530                 *p++ = 'w';
16531               used_prefixes |= (prefixes & PREFIX_DATA);
16532             }
16533         }
16534       break;
16535     default:
16536       oappend (INTERNAL_DISASSEMBLER_ERROR);
16537       break;
16538     }
16539   mnemonicendp = p;
16540   *p = '\0';
16541
16542  skip:
16543   OP_M (bytemode, sizeflag);
16544 }
16545
16546 static void
16547 MOVSXD_Fixup (int bytemode, int sizeflag)
16548 {
16549   /* Add proper suffix to "movsxd".  */
16550   char *p = mnemonicendp;
16551
16552   switch (bytemode)
16553     {
16554     case movsxd_mode:
16555       if (intel_syntax)
16556         {
16557           *p++ = 'x';
16558           *p++ = 'd';
16559           goto skip;
16560         }
16561
16562       USED_REX (REX_W);
16563       if (rex & REX_W)
16564         {
16565           *p++ = 'l';
16566           *p++ = 'q';
16567         }
16568       else
16569         {
16570           *p++ = 'x';
16571           *p++ = 'd';
16572         }
16573       break;
16574     default:
16575       oappend (INTERNAL_DISASSEMBLER_ERROR);
16576       break;
16577     }
16578
16579  skip:
16580   mnemonicendp = p;
16581   *p = '\0';
16582   OP_E (bytemode, sizeflag);
16583 }
16584
16585 static void
16586 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16587 {
16588   int reg;
16589   const char **names;
16590
16591   /* Skip mod/rm byte.  */
16592   MODRM_CHECK;
16593   codep++;
16594
16595   if (rex & REX_W)
16596     names = names64;
16597   else
16598     names = names32;
16599
16600   reg = modrm.rm;
16601   USED_REX (REX_B);
16602   if (rex & REX_B)
16603     reg += 8;
16604
16605   oappend (names[reg]);
16606 }
16607
16608 static void
16609 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16610 {
16611   const char **names;
16612   unsigned int reg = vex.register_specifier;
16613   vex.register_specifier = 0;
16614
16615   if (rex & REX_W)
16616     names = names64;
16617   else
16618     names = names32;
16619
16620   if (address_mode != mode_64bit)
16621     reg &= 7;
16622   oappend (names[reg]);
16623 }
16624
16625 static void
16626 OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16627 {
16628   if (!vex.evex
16629       || (bytemode != mask_mode && bytemode != mask_bd_mode))
16630     abort ();
16631
16632   USED_REX (REX_R);
16633   if ((rex & REX_R) != 0 || !vex.r)
16634     {
16635       BadOp ();
16636       return;
16637     }
16638
16639   oappend (names_mask [modrm.reg]);
16640 }
16641
16642 static void
16643 OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16644 {
16645   if (!vex.evex
16646       || (bytemode != evex_rounding_mode
16647           && bytemode != evex_rounding_64_mode
16648           && bytemode != evex_sae_mode))
16649     abort ();
16650   if (modrm.mod == 3 && vex.b)
16651     switch (bytemode)
16652       {
16653       case evex_rounding_64_mode:
16654         if (address_mode != mode_64bit)
16655           {
16656             oappend ("(bad)");
16657             break;
16658           }
16659         /* Fall through.  */
16660       case evex_rounding_mode:
16661         oappend (names_rounding[vex.ll]);
16662         break;
16663       case evex_sae_mode:
16664         oappend ("{sae}");
16665         break;
16666       default:
16667         break;
16668       }
16669 }