1 /* Print i386 instructions for GDB, the GNU debugger.
2 Copyright (C) 1988-2020 Free Software Foundation, Inc.
4 This file is part of the GNU opcodes library.
6 This library is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 It is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
24 modified by John Hassey (hassey@dg-rtp.dg.com)
25 x86-64 support added by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */
28 /* The main tables describing the instructions is essentially a copy
29 of the "Opcode Map" chapter (Appendix A) of the Intel 80386
30 Programmers Manual. Usually, there is a capital letter, followed
31 by a small letter. The capital letter tell the addressing mode,
32 and the small letter tells about the operand size. Refer to
33 the Intel manual for details. */
36 #include "disassemble.h"
38 #include "opcode/i386.h"
39 #include "libiberty.h"
40 #include "safe-ctype.h"
44 static int print_insn (bfd_vma
, disassemble_info
*);
45 static void dofloat (int);
46 static void OP_ST (int, int);
47 static void OP_STi (int, int);
48 static int putop (const char *, int);
49 static void oappend (const char *);
50 static void append_seg (void);
51 static void OP_indirE (int, int);
52 static void print_operand_value (char *, int, bfd_vma
);
53 static void OP_E_register (int, int);
54 static void OP_E_memory (int, int);
55 static void print_displacement (char *, bfd_vma
);
56 static void OP_E (int, int);
57 static void OP_G (int, int);
58 static bfd_vma
get64 (void);
59 static bfd_signed_vma
get32 (void);
60 static bfd_signed_vma
get32s (void);
61 static int get16 (void);
62 static void set_op (bfd_vma
, int);
63 static void OP_Skip_MODRM (int, int);
64 static void OP_REG (int, int);
65 static void OP_IMREG (int, int);
66 static void OP_I (int, int);
67 static void OP_I64 (int, int);
68 static void OP_sI (int, int);
69 static void OP_J (int, int);
70 static void OP_SEG (int, int);
71 static void OP_DIR (int, int);
72 static void OP_OFF (int, int);
73 static void OP_OFF64 (int, int);
74 static void ptr_reg (int, int);
75 static void OP_ESreg (int, int);
76 static void OP_DSreg (int, int);
77 static void OP_C (int, int);
78 static void OP_D (int, int);
79 static void OP_T (int, int);
80 static void OP_R (int, int);
81 static void OP_MMX (int, int);
82 static void OP_XMM (int, int);
83 static void OP_EM (int, int);
84 static void OP_EX (int, int);
85 static void OP_EMC (int,int);
86 static void OP_MXC (int,int);
87 static void OP_MS (int, int);
88 static void OP_XS (int, int);
89 static void OP_M (int, int);
90 static void OP_VEX (int, int);
91 static void OP_EX_Vex (int, int);
92 static void OP_EX_VexW (int, int);
93 static void OP_EX_VexImmW (int, int);
94 static void OP_XMM_Vex (int, int);
95 static void OP_XMM_VexW (int, int);
96 static void OP_Rounding (int, int);
97 static void OP_REG_VexI4 (int, int);
98 static void PCLMUL_Fixup (int, int);
99 static void VCMP_Fixup (int, int);
100 static void VPCMP_Fixup (int, int);
101 static void VPCOM_Fixup (int, int);
102 static void OP_0f07 (int, int);
103 static void OP_Monitor (int, int);
104 static void OP_Mwait (int, int);
105 static void NOP_Fixup1 (int, int);
106 static void NOP_Fixup2 (int, int);
107 static void OP_3DNowSuffix (int, int);
108 static void CMP_Fixup (int, int);
109 static void BadOp (void);
110 static void REP_Fixup (int, int);
111 static void SEP_Fixup (int, int);
112 static void BND_Fixup (int, int);
113 static void NOTRACK_Fixup (int, int);
114 static void HLE_Fixup1 (int, int);
115 static void HLE_Fixup2 (int, int);
116 static void HLE_Fixup3 (int, int);
117 static void CMPXCHG8B_Fixup (int, int);
118 static void XMM_Fixup (int, int);
119 static void CRC32_Fixup (int, int);
120 static void FXSAVE_Fixup (int, int);
121 static void PCMPESTR_Fixup (int, int);
122 static void OP_LWPCB_E (int, int);
123 static void OP_LWP_E (int, int);
124 static void OP_Vex_2src_1 (int, int);
125 static void OP_Vex_2src_2 (int, int);
127 static void MOVBE_Fixup (int, int);
128 static void MOVSXD_Fixup (int, int);
130 static void OP_Mask (int, int);
133 /* Points to first byte not fetched. */
134 bfd_byte
*max_fetched
;
135 bfd_byte the_buffer
[MAX_MNEM_SIZE
];
138 OPCODES_SIGJMP_BUF bailout
;
148 enum address_mode address_mode
;
150 /* Flags for the prefixes for the current instruction. See below. */
153 /* REX prefix the current instruction. See below. */
155 /* Bits of REX we've already used. */
157 /* Mark parts used in the REX prefix. When we are testing for
158 empty prefix (for 8bit register REX extension), just mask it
159 out. Otherwise test for REX bit is excuse for existence of REX
160 only in case value is nonzero. */
161 #define USED_REX(value) \
166 rex_used |= (value) | REX_OPCODE; \
169 rex_used |= REX_OPCODE; \
172 /* Flags for prefixes which we somehow handled when printing the
173 current instruction. */
174 static int used_prefixes
;
176 /* Flags stored in PREFIXES. */
177 #define PREFIX_REPZ 1
178 #define PREFIX_REPNZ 2
179 #define PREFIX_LOCK 4
181 #define PREFIX_SS 0x10
182 #define PREFIX_DS 0x20
183 #define PREFIX_ES 0x40
184 #define PREFIX_FS 0x80
185 #define PREFIX_GS 0x100
186 #define PREFIX_DATA 0x200
187 #define PREFIX_ADDR 0x400
188 #define PREFIX_FWAIT 0x800
190 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
191 to ADDR (exclusive) are valid. Returns 1 for success, longjmps
193 #define FETCH_DATA(info, addr) \
194 ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
195 ? 1 : fetch_data ((info), (addr)))
198 fetch_data (struct disassemble_info
*info
, bfd_byte
*addr
)
201 struct dis_private
*priv
= (struct dis_private
*) info
->private_data
;
202 bfd_vma start
= priv
->insn_start
+ (priv
->max_fetched
- priv
->the_buffer
);
204 if (addr
<= priv
->the_buffer
+ MAX_MNEM_SIZE
)
205 status
= (*info
->read_memory_func
) (start
,
207 addr
- priv
->max_fetched
,
213 /* If we did manage to read at least one byte, then
214 print_insn_i386 will do something sensible. Otherwise, print
215 an error. We do that here because this is where we know
217 if (priv
->max_fetched
== priv
->the_buffer
)
218 (*info
->memory_error_func
) (status
, start
, info
);
219 OPCODES_SIGLONGJMP (priv
->bailout
, 1);
222 priv
->max_fetched
= addr
;
226 /* Possible values for prefix requirement. */
227 #define PREFIX_IGNORED_SHIFT 16
228 #define PREFIX_IGNORED_REPZ (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
229 #define PREFIX_IGNORED_REPNZ (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
230 #define PREFIX_IGNORED_DATA (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
231 #define PREFIX_IGNORED_ADDR (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
232 #define PREFIX_IGNORED_LOCK (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
234 /* Opcode prefixes. */
235 #define PREFIX_OPCODE (PREFIX_REPZ \
239 /* Prefixes ignored. */
240 #define PREFIX_IGNORED (PREFIX_IGNORED_REPZ \
241 | PREFIX_IGNORED_REPNZ \
242 | PREFIX_IGNORED_DATA)
244 #define XX { NULL, 0 }
245 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
247 #define Eb { OP_E, b_mode }
248 #define Ebnd { OP_E, bnd_mode }
249 #define EbS { OP_E, b_swap_mode }
250 #define EbndS { OP_E, bnd_swap_mode }
251 #define Ev { OP_E, v_mode }
252 #define Eva { OP_E, va_mode }
253 #define Ev_bnd { OP_E, v_bnd_mode }
254 #define EvS { OP_E, v_swap_mode }
255 #define Ed { OP_E, d_mode }
256 #define Edq { OP_E, dq_mode }
257 #define Edqw { OP_E, dqw_mode }
258 #define Edqb { OP_E, dqb_mode }
259 #define Edb { OP_E, db_mode }
260 #define Edw { OP_E, dw_mode }
261 #define Edqd { OP_E, dqd_mode }
262 #define Eq { OP_E, q_mode }
263 #define indirEv { OP_indirE, indir_v_mode }
264 #define indirEp { OP_indirE, f_mode }
265 #define stackEv { OP_E, stack_v_mode }
266 #define Em { OP_E, m_mode }
267 #define Ew { OP_E, w_mode }
268 #define M { OP_M, 0 } /* lea, lgdt, etc. */
269 #define Ma { OP_M, a_mode }
270 #define Mb { OP_M, b_mode }
271 #define Md { OP_M, d_mode }
272 #define Mo { OP_M, o_mode }
273 #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */
274 #define Mq { OP_M, q_mode }
275 #define Mv_bnd { OP_M, v_bndmk_mode }
276 #define Mx { OP_M, x_mode }
277 #define Mxmm { OP_M, xmm_mode }
278 #define Gb { OP_G, b_mode }
279 #define Gbnd { OP_G, bnd_mode }
280 #define Gv { OP_G, v_mode }
281 #define Gd { OP_G, d_mode }
282 #define Gdq { OP_G, dq_mode }
283 #define Gm { OP_G, m_mode }
284 #define Gva { OP_G, va_mode }
285 #define Gw { OP_G, w_mode }
286 #define Rd { OP_R, d_mode }
287 #define Rdq { OP_R, dq_mode }
288 #define Rm { OP_R, m_mode }
289 #define Ib { OP_I, b_mode }
290 #define sIb { OP_sI, b_mode } /* sign extened byte */
291 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
292 #define Iv { OP_I, v_mode }
293 #define sIv { OP_sI, v_mode }
294 #define Iv64 { OP_I64, v_mode }
295 #define Id { OP_I, d_mode }
296 #define Iw { OP_I, w_mode }
297 #define I1 { OP_I, const_1_mode }
298 #define Jb { OP_J, b_mode }
299 #define Jv { OP_J, v_mode }
300 #define Jdqw { OP_J, dqw_mode }
301 #define Cm { OP_C, m_mode }
302 #define Dm { OP_D, m_mode }
303 #define Td { OP_T, d_mode }
304 #define Skip_MODRM { OP_Skip_MODRM, 0 }
306 #define RMeAX { OP_REG, eAX_reg }
307 #define RMeBX { OP_REG, eBX_reg }
308 #define RMeCX { OP_REG, eCX_reg }
309 #define RMeDX { OP_REG, eDX_reg }
310 #define RMeSP { OP_REG, eSP_reg }
311 #define RMeBP { OP_REG, eBP_reg }
312 #define RMeSI { OP_REG, eSI_reg }
313 #define RMeDI { OP_REG, eDI_reg }
314 #define RMrAX { OP_REG, rAX_reg }
315 #define RMrBX { OP_REG, rBX_reg }
316 #define RMrCX { OP_REG, rCX_reg }
317 #define RMrDX { OP_REG, rDX_reg }
318 #define RMrSP { OP_REG, rSP_reg }
319 #define RMrBP { OP_REG, rBP_reg }
320 #define RMrSI { OP_REG, rSI_reg }
321 #define RMrDI { OP_REG, rDI_reg }
322 #define RMAL { OP_REG, al_reg }
323 #define RMCL { OP_REG, cl_reg }
324 #define RMDL { OP_REG, dl_reg }
325 #define RMBL { OP_REG, bl_reg }
326 #define RMAH { OP_REG, ah_reg }
327 #define RMCH { OP_REG, ch_reg }
328 #define RMDH { OP_REG, dh_reg }
329 #define RMBH { OP_REG, bh_reg }
330 #define RMAX { OP_REG, ax_reg }
331 #define RMDX { OP_REG, dx_reg }
333 #define eAX { OP_IMREG, eAX_reg }
334 #define eBX { OP_IMREG, eBX_reg }
335 #define eCX { OP_IMREG, eCX_reg }
336 #define eDX { OP_IMREG, eDX_reg }
337 #define eSP { OP_IMREG, eSP_reg }
338 #define eBP { OP_IMREG, eBP_reg }
339 #define eSI { OP_IMREG, eSI_reg }
340 #define eDI { OP_IMREG, eDI_reg }
341 #define AL { OP_IMREG, al_reg }
342 #define CL { OP_IMREG, cl_reg }
343 #define DL { OP_IMREG, dl_reg }
344 #define BL { OP_IMREG, bl_reg }
345 #define AH { OP_IMREG, ah_reg }
346 #define CH { OP_IMREG, ch_reg }
347 #define DH { OP_IMREG, dh_reg }
348 #define BH { OP_IMREG, bh_reg }
349 #define AX { OP_IMREG, ax_reg }
350 #define DX { OP_IMREG, dx_reg }
351 #define zAX { OP_IMREG, z_mode_ax_reg }
352 #define indirDX { OP_IMREG, indir_dx_reg }
354 #define Sw { OP_SEG, w_mode }
355 #define Sv { OP_SEG, v_mode }
356 #define Ap { OP_DIR, 0 }
357 #define Ob { OP_OFF64, b_mode }
358 #define Ov { OP_OFF64, v_mode }
359 #define Xb { OP_DSreg, eSI_reg }
360 #define Xv { OP_DSreg, eSI_reg }
361 #define Xz { OP_DSreg, eSI_reg }
362 #define Yb { OP_ESreg, eDI_reg }
363 #define Yv { OP_ESreg, eDI_reg }
364 #define DSBX { OP_DSreg, eBX_reg }
366 #define es { OP_REG, es_reg }
367 #define ss { OP_REG, ss_reg }
368 #define cs { OP_REG, cs_reg }
369 #define ds { OP_REG, ds_reg }
370 #define fs { OP_REG, fs_reg }
371 #define gs { OP_REG, gs_reg }
373 #define MX { OP_MMX, 0 }
374 #define XM { OP_XMM, 0 }
375 #define XMScalar { OP_XMM, scalar_mode }
376 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
377 #define XMM { OP_XMM, xmm_mode }
378 #define XMxmmq { OP_XMM, xmmq_mode }
379 #define EM { OP_EM, v_mode }
380 #define EMS { OP_EM, v_swap_mode }
381 #define EMd { OP_EM, d_mode }
382 #define EMx { OP_EM, x_mode }
383 #define EXbScalar { OP_EX, b_scalar_mode }
384 #define EXw { OP_EX, w_mode }
385 #define EXwScalar { OP_EX, w_scalar_mode }
386 #define EXd { OP_EX, d_mode }
387 #define EXdS { OP_EX, d_swap_mode }
388 #define EXq { OP_EX, q_mode }
389 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
390 #define EXqS { OP_EX, q_swap_mode }
391 #define EXx { OP_EX, x_mode }
392 #define EXxS { OP_EX, x_swap_mode }
393 #define EXxmm { OP_EX, xmm_mode }
394 #define EXymm { OP_EX, ymm_mode }
395 #define EXxmmq { OP_EX, xmmq_mode }
396 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
397 #define EXxmm_mb { OP_EX, xmm_mb_mode }
398 #define EXxmm_mw { OP_EX, xmm_mw_mode }
399 #define EXxmm_md { OP_EX, xmm_md_mode }
400 #define EXxmm_mq { OP_EX, xmm_mq_mode }
401 #define EXxmmdw { OP_EX, xmmdw_mode }
402 #define EXxmmqd { OP_EX, xmmqd_mode }
403 #define EXymmq { OP_EX, ymmq_mode }
404 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
405 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
406 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
407 #define MS { OP_MS, v_mode }
408 #define XS { OP_XS, v_mode }
409 #define EMCq { OP_EMC, q_mode }
410 #define MXC { OP_MXC, 0 }
411 #define OPSUF { OP_3DNowSuffix, 0 }
412 #define SEP { SEP_Fixup, 0 }
413 #define CMP { CMP_Fixup, 0 }
414 #define XMM0 { XMM_Fixup, 0 }
415 #define FXSAVE { FXSAVE_Fixup, 0 }
416 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
417 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
419 #define Vex { OP_VEX, vex_mode }
420 #define VexScalar { OP_VEX, vex_scalar_mode }
421 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
422 #define Vex128 { OP_VEX, vex128_mode }
423 #define Vex256 { OP_VEX, vex256_mode }
424 #define VexGdq { OP_VEX, dq_mode }
425 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
426 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
427 #define EXVexW { OP_EX_VexW, x_mode }
428 #define EXdVexW { OP_EX_VexW, d_mode }
429 #define EXqVexW { OP_EX_VexW, q_mode }
430 #define EXVexImmW { OP_EX_VexImmW, x_mode }
431 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
432 #define XMVexW { OP_XMM_VexW, 0 }
433 #define XMVexI4 { OP_REG_VexI4, x_mode }
434 #define PCLMUL { PCLMUL_Fixup, 0 }
435 #define VCMP { VCMP_Fixup, 0 }
436 #define VPCMP { VPCMP_Fixup, 0 }
437 #define VPCOM { VPCOM_Fixup, 0 }
439 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
440 #define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode }
441 #define EXxEVexS { OP_Rounding, evex_sae_mode }
443 #define XMask { OP_Mask, mask_mode }
444 #define MaskG { OP_G, mask_mode }
445 #define MaskE { OP_E, mask_mode }
446 #define MaskBDE { OP_E, mask_bd_mode }
447 #define MaskR { OP_R, mask_mode }
448 #define MaskVex { OP_VEX, mask_mode }
450 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
451 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
452 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
453 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
455 /* Used handle "rep" prefix for string instructions. */
456 #define Xbr { REP_Fixup, eSI_reg }
457 #define Xvr { REP_Fixup, eSI_reg }
458 #define Ybr { REP_Fixup, eDI_reg }
459 #define Yvr { REP_Fixup, eDI_reg }
460 #define Yzr { REP_Fixup, eDI_reg }
461 #define indirDXr { REP_Fixup, indir_dx_reg }
462 #define ALr { REP_Fixup, al_reg }
463 #define eAXr { REP_Fixup, eAX_reg }
465 /* Used handle HLE prefix for lockable instructions. */
466 #define Ebh1 { HLE_Fixup1, b_mode }
467 #define Evh1 { HLE_Fixup1, v_mode }
468 #define Ebh2 { HLE_Fixup2, b_mode }
469 #define Evh2 { HLE_Fixup2, v_mode }
470 #define Ebh3 { HLE_Fixup3, b_mode }
471 #define Evh3 { HLE_Fixup3, v_mode }
473 #define BND { BND_Fixup, 0 }
474 #define NOTRACK { NOTRACK_Fixup, 0 }
476 #define cond_jump_flag { NULL, cond_jump_mode }
477 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
479 /* bits in sizeflag */
480 #define SUFFIX_ALWAYS 4
488 /* byte operand with operand swapped */
490 /* byte operand, sign extend like 'T' suffix */
492 /* operand size depends on prefixes */
494 /* operand size depends on prefixes with operand swapped */
496 /* operand size depends on address prefix */
500 /* double word operand */
502 /* double word operand with operand swapped */
504 /* quad word operand */
506 /* quad word operand with operand swapped */
508 /* ten-byte operand */
510 /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand. In EVEX with
511 broadcast enabled. */
513 /* Similar to x_mode, but with different EVEX mem shifts. */
515 /* Similar to x_mode, but with disabled broadcast. */
517 /* Similar to x_mode, but with operands swapped and disabled broadcast
520 /* 16-byte XMM operand */
522 /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
523 memory operand (depending on vector length). Broadcast isn't
526 /* Same as xmmq_mode, but broadcast is allowed. */
527 evex_half_bcst_xmmq_mode
,
528 /* XMM register or byte memory operand */
530 /* XMM register or word memory operand */
532 /* XMM register or double word memory operand */
534 /* XMM register or quad word memory operand */
536 /* 16-byte XMM, word, double word or quad word operand. */
538 /* 16-byte XMM, double word, quad word operand or xmm word operand. */
540 /* 32-byte YMM operand */
542 /* quad word, ymmword or zmmword memory operand. */
544 /* 32-byte YMM or 16-byte word operand */
546 /* d_mode in 32bit, q_mode in 64bit mode. */
548 /* pair of v_mode operands */
554 /* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode. */
556 /* operand size depends on REX prefixes. */
558 /* registers like dq_mode, memory like w_mode, displacements like
559 v_mode without considering Intel64 ISA. */
563 /* bounds operand with operand swapped */
565 /* 4- or 6-byte pointer operand */
568 /* v_mode for indirect branch opcodes. */
570 /* v_mode for stack-related opcodes. */
572 /* non-quad operand size depends on prefixes */
574 /* 16-byte operand */
576 /* registers like dq_mode, memory like b_mode. */
578 /* registers like d_mode, memory like b_mode. */
580 /* registers like d_mode, memory like w_mode. */
582 /* registers like dq_mode, memory like d_mode. */
584 /* normal vex mode */
586 /* 128bit vex mode */
588 /* 256bit vex mode */
591 /* Operand size depends on the VEX.W bit, with VSIB dword indices. */
592 vex_vsib_d_w_dq_mode
,
593 /* Similar to vex_vsib_d_w_dq_mode, with smaller memory. */
595 /* Operand size depends on the VEX.W bit, with VSIB qword indices. */
596 vex_vsib_q_w_dq_mode
,
597 /* Similar to vex_vsib_q_w_dq_mode, with smaller memory. */
600 /* scalar, ignore vector length. */
602 /* like b_mode, ignore vector length. */
604 /* like w_mode, ignore vector length. */
606 /* like d_swap_mode, ignore vector length. */
608 /* like q_swap_mode, ignore vector length. */
610 /* like vex_mode, ignore vector length. */
612 /* Operand size depends on the VEX.W bit, ignore vector length. */
613 vex_scalar_w_dq_mode
,
615 /* Static rounding. */
617 /* Static rounding, 64-bit mode only. */
618 evex_rounding_64_mode
,
619 /* Supress all exceptions. */
622 /* Mask register operand. */
624 /* Mask register operand. */
692 #define FLOAT NULL, { { NULL, FLOATCODE } }, 0
694 #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }, 0
695 #define DIS386_PREFIX(T, I, P) NULL, { { NULL, (T)}, { NULL, (I) } }, P
696 #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I))
697 #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I))
698 #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I))
699 #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I))
700 #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I))
701 #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I))
702 #define THREE_BYTE_TABLE_PREFIX(I, P) DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
703 #define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I))
704 #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I))
705 #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I))
706 #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I))
707 #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I))
708 #define EVEX_TABLE(I) DIS386 (USE_EVEX_TABLE, (I))
709 #define EVEX_LEN_TABLE(I) DIS386 (USE_EVEX_LEN_TABLE, (I))
839 MOD_VEX_0F12_PREFIX_0
,
840 MOD_VEX_0F12_PREFIX_2
,
842 MOD_VEX_0F16_PREFIX_0
,
843 MOD_VEX_0F16_PREFIX_2
,
846 MOD_VEX_W_0_0F41_P_0_LEN_1
,
847 MOD_VEX_W_1_0F41_P_0_LEN_1
,
848 MOD_VEX_W_0_0F41_P_2_LEN_1
,
849 MOD_VEX_W_1_0F41_P_2_LEN_1
,
850 MOD_VEX_W_0_0F42_P_0_LEN_1
,
851 MOD_VEX_W_1_0F42_P_0_LEN_1
,
852 MOD_VEX_W_0_0F42_P_2_LEN_1
,
853 MOD_VEX_W_1_0F42_P_2_LEN_1
,
854 MOD_VEX_W_0_0F44_P_0_LEN_1
,
855 MOD_VEX_W_1_0F44_P_0_LEN_1
,
856 MOD_VEX_W_0_0F44_P_2_LEN_1
,
857 MOD_VEX_W_1_0F44_P_2_LEN_1
,
858 MOD_VEX_W_0_0F45_P_0_LEN_1
,
859 MOD_VEX_W_1_0F45_P_0_LEN_1
,
860 MOD_VEX_W_0_0F45_P_2_LEN_1
,
861 MOD_VEX_W_1_0F45_P_2_LEN_1
,
862 MOD_VEX_W_0_0F46_P_0_LEN_1
,
863 MOD_VEX_W_1_0F46_P_0_LEN_1
,
864 MOD_VEX_W_0_0F46_P_2_LEN_1
,
865 MOD_VEX_W_1_0F46_P_2_LEN_1
,
866 MOD_VEX_W_0_0F47_P_0_LEN_1
,
867 MOD_VEX_W_1_0F47_P_0_LEN_1
,
868 MOD_VEX_W_0_0F47_P_2_LEN_1
,
869 MOD_VEX_W_1_0F47_P_2_LEN_1
,
870 MOD_VEX_W_0_0F4A_P_0_LEN_1
,
871 MOD_VEX_W_1_0F4A_P_0_LEN_1
,
872 MOD_VEX_W_0_0F4A_P_2_LEN_1
,
873 MOD_VEX_W_1_0F4A_P_2_LEN_1
,
874 MOD_VEX_W_0_0F4B_P_0_LEN_1
,
875 MOD_VEX_W_1_0F4B_P_0_LEN_1
,
876 MOD_VEX_W_0_0F4B_P_2_LEN_1
,
888 MOD_VEX_W_0_0F91_P_0_LEN_0
,
889 MOD_VEX_W_1_0F91_P_0_LEN_0
,
890 MOD_VEX_W_0_0F91_P_2_LEN_0
,
891 MOD_VEX_W_1_0F91_P_2_LEN_0
,
892 MOD_VEX_W_0_0F92_P_0_LEN_0
,
893 MOD_VEX_W_0_0F92_P_2_LEN_0
,
894 MOD_VEX_0F92_P_3_LEN_0
,
895 MOD_VEX_W_0_0F93_P_0_LEN_0
,
896 MOD_VEX_W_0_0F93_P_2_LEN_0
,
897 MOD_VEX_0F93_P_3_LEN_0
,
898 MOD_VEX_W_0_0F98_P_0_LEN_0
,
899 MOD_VEX_W_1_0F98_P_0_LEN_0
,
900 MOD_VEX_W_0_0F98_P_2_LEN_0
,
901 MOD_VEX_W_1_0F98_P_2_LEN_0
,
902 MOD_VEX_W_0_0F99_P_0_LEN_0
,
903 MOD_VEX_W_1_0F99_P_0_LEN_0
,
904 MOD_VEX_W_0_0F99_P_2_LEN_0
,
905 MOD_VEX_W_1_0F99_P_2_LEN_0
,
908 MOD_VEX_0FD7_PREFIX_2
,
909 MOD_VEX_0FE7_PREFIX_2
,
910 MOD_VEX_0FF0_PREFIX_3
,
911 MOD_VEX_0F381A_PREFIX_2
,
912 MOD_VEX_0F382A_PREFIX_2
,
913 MOD_VEX_0F382C_PREFIX_2
,
914 MOD_VEX_0F382D_PREFIX_2
,
915 MOD_VEX_0F382E_PREFIX_2
,
916 MOD_VEX_0F382F_PREFIX_2
,
917 MOD_VEX_0F385A_PREFIX_2
,
918 MOD_VEX_0F388C_PREFIX_2
,
919 MOD_VEX_0F388E_PREFIX_2
,
920 MOD_VEX_W_0_0F3A30_P_2_LEN_0
,
921 MOD_VEX_W_1_0F3A30_P_2_LEN_0
,
922 MOD_VEX_W_0_0F3A31_P_2_LEN_0
,
923 MOD_VEX_W_1_0F3A31_P_2_LEN_0
,
924 MOD_VEX_W_0_0F3A32_P_2_LEN_0
,
925 MOD_VEX_W_1_0F3A32_P_2_LEN_0
,
926 MOD_VEX_W_0_0F3A33_P_2_LEN_0
,
927 MOD_VEX_W_1_0F3A33_P_2_LEN_0
,
929 MOD_EVEX_0F12_PREFIX_0
,
930 MOD_EVEX_0F12_PREFIX_2
,
932 MOD_EVEX_0F16_PREFIX_0
,
933 MOD_EVEX_0F16_PREFIX_2
,
936 MOD_EVEX_0F38C6_REG_1
,
937 MOD_EVEX_0F38C6_REG_2
,
938 MOD_EVEX_0F38C6_REG_5
,
939 MOD_EVEX_0F38C6_REG_6
,
940 MOD_EVEX_0F38C7_REG_1
,
941 MOD_EVEX_0F38C7_REG_2
,
942 MOD_EVEX_0F38C7_REG_5
,
943 MOD_EVEX_0F38C7_REG_6
956 RM_0F1E_P_1_MOD_3_REG_7
,
957 RM_0FAE_REG_6_MOD_3_P_0
,
964 PREFIX_0F01_REG_3_RM_1
,
965 PREFIX_0F01_REG_5_MOD_0
,
966 PREFIX_0F01_REG_5_MOD_3_RM_0
,
967 PREFIX_0F01_REG_5_MOD_3_RM_1
,
968 PREFIX_0F01_REG_5_MOD_3_RM_2
,
969 PREFIX_0F01_REG_7_MOD_3_RM_2
,
970 PREFIX_0F01_REG_7_MOD_3_RM_3
,
1012 PREFIX_0FAE_REG_0_MOD_3
,
1013 PREFIX_0FAE_REG_1_MOD_3
,
1014 PREFIX_0FAE_REG_2_MOD_3
,
1015 PREFIX_0FAE_REG_3_MOD_3
,
1016 PREFIX_0FAE_REG_4_MOD_0
,
1017 PREFIX_0FAE_REG_4_MOD_3
,
1018 PREFIX_0FAE_REG_5_MOD_0
,
1019 PREFIX_0FAE_REG_5_MOD_3
,
1020 PREFIX_0FAE_REG_6_MOD_0
,
1021 PREFIX_0FAE_REG_6_MOD_3
,
1022 PREFIX_0FAE_REG_7_MOD_0
,
1028 PREFIX_0FC7_REG_6_MOD_0
,
1029 PREFIX_0FC7_REG_6_MOD_3
,
1030 PREFIX_0FC7_REG_7_MOD_3
,
1160 PREFIX_VEX_0F71_REG_2
,
1161 PREFIX_VEX_0F71_REG_4
,
1162 PREFIX_VEX_0F71_REG_6
,
1163 PREFIX_VEX_0F72_REG_2
,
1164 PREFIX_VEX_0F72_REG_4
,
1165 PREFIX_VEX_0F72_REG_6
,
1166 PREFIX_VEX_0F73_REG_2
,
1167 PREFIX_VEX_0F73_REG_3
,
1168 PREFIX_VEX_0F73_REG_6
,
1169 PREFIX_VEX_0F73_REG_7
,
1342 PREFIX_VEX_0F38F3_REG_1
,
1343 PREFIX_VEX_0F38F3_REG_2
,
1344 PREFIX_VEX_0F38F3_REG_3
,
1452 PREFIX_EVEX_0F71_REG_2
,
1453 PREFIX_EVEX_0F71_REG_4
,
1454 PREFIX_EVEX_0F71_REG_6
,
1455 PREFIX_EVEX_0F72_REG_0
,
1456 PREFIX_EVEX_0F72_REG_1
,
1457 PREFIX_EVEX_0F72_REG_2
,
1458 PREFIX_EVEX_0F72_REG_4
,
1459 PREFIX_EVEX_0F72_REG_6
,
1460 PREFIX_EVEX_0F73_REG_2
,
1461 PREFIX_EVEX_0F73_REG_3
,
1462 PREFIX_EVEX_0F73_REG_6
,
1463 PREFIX_EVEX_0F73_REG_7
,
1659 PREFIX_EVEX_0F38C6_REG_1
,
1660 PREFIX_EVEX_0F38C6_REG_2
,
1661 PREFIX_EVEX_0F38C6_REG_5
,
1662 PREFIX_EVEX_0F38C6_REG_6
,
1663 PREFIX_EVEX_0F38C7_REG_1
,
1664 PREFIX_EVEX_0F38C7_REG_2
,
1665 PREFIX_EVEX_0F38C7_REG_5
,
1666 PREFIX_EVEX_0F38C7_REG_6
,
1770 THREE_BYTE_0F38
= 0,
1797 VEX_LEN_0F12_P_0_M_0
= 0,
1798 VEX_LEN_0F12_P_0_M_1
,
1799 #define VEX_LEN_0F12_P_2_M_0 VEX_LEN_0F12_P_0_M_0
1801 VEX_LEN_0F16_P_0_M_0
,
1802 VEX_LEN_0F16_P_0_M_1
,
1803 #define VEX_LEN_0F16_P_2_M_0 VEX_LEN_0F16_P_0_M_0
1839 VEX_LEN_0FAE_R_2_M_0
,
1840 VEX_LEN_0FAE_R_3_M_0
,
1847 VEX_LEN_0F381A_P_2_M_0
,
1850 VEX_LEN_0F385A_P_2_M_0
,
1853 VEX_LEN_0F38F3_R_1_P_0
,
1854 VEX_LEN_0F38F3_R_2_P_0
,
1855 VEX_LEN_0F38F3_R_3_P_0
,
1898 VEX_LEN_0FXOP_08_CC
,
1899 VEX_LEN_0FXOP_08_CD
,
1900 VEX_LEN_0FXOP_08_CE
,
1901 VEX_LEN_0FXOP_08_CF
,
1902 VEX_LEN_0FXOP_08_EC
,
1903 VEX_LEN_0FXOP_08_ED
,
1904 VEX_LEN_0FXOP_08_EE
,
1905 VEX_LEN_0FXOP_08_EF
,
1906 VEX_LEN_0FXOP_09_80
,
1912 EVEX_LEN_0F6E_P_2
= 0,
1916 EVEX_LEN_0F3819_P_2_W_0
,
1917 EVEX_LEN_0F3819_P_2_W_1
,
1918 EVEX_LEN_0F381A_P_2_W_0
,
1919 EVEX_LEN_0F381A_P_2_W_1
,
1920 EVEX_LEN_0F381B_P_2_W_0
,
1921 EVEX_LEN_0F381B_P_2_W_1
,
1922 EVEX_LEN_0F385A_P_2_W_0
,
1923 EVEX_LEN_0F385A_P_2_W_1
,
1924 EVEX_LEN_0F385B_P_2_W_0
,
1925 EVEX_LEN_0F385B_P_2_W_1
,
1926 EVEX_LEN_0F38C6_REG_1_PREFIX_2
,
1927 EVEX_LEN_0F38C6_REG_2_PREFIX_2
,
1928 EVEX_LEN_0F38C6_REG_5_PREFIX_2
,
1929 EVEX_LEN_0F38C6_REG_6_PREFIX_2
,
1930 EVEX_LEN_0F38C7_R_1_P_2_W_0
,
1931 EVEX_LEN_0F38C7_R_1_P_2_W_1
,
1932 EVEX_LEN_0F38C7_R_2_P_2_W_0
,
1933 EVEX_LEN_0F38C7_R_2_P_2_W_1
,
1934 EVEX_LEN_0F38C7_R_5_P_2_W_0
,
1935 EVEX_LEN_0F38C7_R_5_P_2_W_1
,
1936 EVEX_LEN_0F38C7_R_6_P_2_W_0
,
1937 EVEX_LEN_0F38C7_R_6_P_2_W_1
,
1938 EVEX_LEN_0F3A18_P_2_W_0
,
1939 EVEX_LEN_0F3A18_P_2_W_1
,
1940 EVEX_LEN_0F3A19_P_2_W_0
,
1941 EVEX_LEN_0F3A19_P_2_W_1
,
1942 EVEX_LEN_0F3A1A_P_2_W_0
,
1943 EVEX_LEN_0F3A1A_P_2_W_1
,
1944 EVEX_LEN_0F3A1B_P_2_W_0
,
1945 EVEX_LEN_0F3A1B_P_2_W_1
,
1946 EVEX_LEN_0F3A23_P_2_W_0
,
1947 EVEX_LEN_0F3A23_P_2_W_1
,
1948 EVEX_LEN_0F3A38_P_2_W_0
,
1949 EVEX_LEN_0F3A38_P_2_W_1
,
1950 EVEX_LEN_0F3A39_P_2_W_0
,
1951 EVEX_LEN_0F3A39_P_2_W_1
,
1952 EVEX_LEN_0F3A3A_P_2_W_0
,
1953 EVEX_LEN_0F3A3A_P_2_W_1
,
1954 EVEX_LEN_0F3A3B_P_2_W_0
,
1955 EVEX_LEN_0F3A3B_P_2_W_1
,
1956 EVEX_LEN_0F3A43_P_2_W_0
,
1957 EVEX_LEN_0F3A43_P_2_W_1
1962 VEX_W_0F41_P_0_LEN_1
= 0,
1963 VEX_W_0F41_P_2_LEN_1
,
1964 VEX_W_0F42_P_0_LEN_1
,
1965 VEX_W_0F42_P_2_LEN_1
,
1966 VEX_W_0F44_P_0_LEN_0
,
1967 VEX_W_0F44_P_2_LEN_0
,
1968 VEX_W_0F45_P_0_LEN_1
,
1969 VEX_W_0F45_P_2_LEN_1
,
1970 VEX_W_0F46_P_0_LEN_1
,
1971 VEX_W_0F46_P_2_LEN_1
,
1972 VEX_W_0F47_P_0_LEN_1
,
1973 VEX_W_0F47_P_2_LEN_1
,
1974 VEX_W_0F4A_P_0_LEN_1
,
1975 VEX_W_0F4A_P_2_LEN_1
,
1976 VEX_W_0F4B_P_0_LEN_1
,
1977 VEX_W_0F4B_P_2_LEN_1
,
1978 VEX_W_0F90_P_0_LEN_0
,
1979 VEX_W_0F90_P_2_LEN_0
,
1980 VEX_W_0F91_P_0_LEN_0
,
1981 VEX_W_0F91_P_2_LEN_0
,
1982 VEX_W_0F92_P_0_LEN_0
,
1983 VEX_W_0F92_P_2_LEN_0
,
1984 VEX_W_0F93_P_0_LEN_0
,
1985 VEX_W_0F93_P_2_LEN_0
,
1986 VEX_W_0F98_P_0_LEN_0
,
1987 VEX_W_0F98_P_2_LEN_0
,
1988 VEX_W_0F99_P_0_LEN_0
,
1989 VEX_W_0F99_P_2_LEN_0
,
1997 VEX_W_0F381A_P_2_M_0
,
1998 VEX_W_0F382C_P_2_M_0
,
1999 VEX_W_0F382D_P_2_M_0
,
2000 VEX_W_0F382E_P_2_M_0
,
2001 VEX_W_0F382F_P_2_M_0
,
2006 VEX_W_0F385A_P_2_M_0
,
2018 VEX_W_0F3A30_P_2_LEN_0
,
2019 VEX_W_0F3A31_P_2_LEN_0
,
2020 VEX_W_0F3A32_P_2_LEN_0
,
2021 VEX_W_0F3A33_P_2_LEN_0
,
2037 EVEX_W_0F12_P_0_M_1
,
2040 EVEX_W_0F16_P_0_M_1
,
2074 EVEX_W_0F72_R_2_P_2
,
2075 EVEX_W_0F72_R_6_P_2
,
2076 EVEX_W_0F73_R_2_P_2
,
2077 EVEX_W_0F73_R_6_P_2
,
2183 EVEX_W_0F38C7_R_1_P_2
,
2184 EVEX_W_0F38C7_R_2_P_2
,
2185 EVEX_W_0F38C7_R_5_P_2
,
2186 EVEX_W_0F38C7_R_6_P_2
,
2225 typedef void (*op_rtn
) (int bytemode
, int sizeflag
);
2234 unsigned int prefix_requirement
;
2237 /* Upper case letters in the instruction names here are macros.
2238 'A' => print 'b' if no register operands or suffix_always is true
2239 'B' => print 'b' if suffix_always is true
2240 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2242 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2243 suffix_always is true
2244 'E' => print 'e' if 32-bit form of jcxz
2245 'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2246 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2247 'H' => print ",pt" or ",pn" branch hint
2250 'K' => print 'd' or 'q' if rex prefix is present.
2251 'L' => print 'l' if suffix_always is true
2252 'M' => print 'r' if intel_mnemonic is false.
2253 'N' => print 'n' if instruction has no wait "prefix"
2254 'O' => print 'd' or 'o' (or 'q' in Intel mode)
2255 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2256 or suffix_always is true. print 'q' if rex prefix is present.
2257 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2259 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2260 'S' => print 'w', 'l' or 'q' if suffix_always is true
2261 'T' => print 'q' in 64bit mode if instruction has no operand size
2262 prefix and behave as 'P' otherwise
2263 'U' => print 'q' in 64bit mode if instruction has no operand size
2264 prefix and behave as 'Q' otherwise
2265 'V' => print 'q' in 64bit mode if instruction has no operand size
2266 prefix and behave as 'S' otherwise
2267 'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2268 'X' => print 's', 'd' depending on data16 prefix (for XMM)
2270 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2271 '!' => change condition from true to false or from false to true.
2272 '%' => add 1 upper case letter to the macro.
2273 '^' => print 'w', 'l', or 'q' (Intel64 ISA only) depending on operand size
2274 prefix or suffix_always is true (lcall/ljmp).
2275 '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending
2276 on operand size prefix.
2277 '&' => print 'q' in 64bit mode for Intel64 ISA or if instruction
2278 has no operand size prefix for AMD64 ISA, behave as 'P'
2281 2 upper case letter macros:
2282 "XY" => print 'x' or 'y' if suffix_always is true or no register
2283 operands and no broadcast.
2284 "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
2285 register operands and no broadcast.
2286 "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2287 "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory
2288 operand or no operand at all in 64bit mode, or if suffix_always
2290 "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2291 "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2292 "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2293 "LW" => print 'd', 'q' depending on the VEX.W bit
2294 "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
2295 an operand size prefix, or suffix_always is true. print
2296 'q' if rex prefix is present.
2298 Many of the above letters print nothing in Intel mode. See "putop"
2301 Braces '{' and '}', and vertical bars '|', indicate alternative
2302 mnemonic strings for AT&T and Intel. */
2304 static const struct dis386 dis386
[] = {
2306 { "addB", { Ebh1
, Gb
}, 0 },
2307 { "addS", { Evh1
, Gv
}, 0 },
2308 { "addB", { Gb
, EbS
}, 0 },
2309 { "addS", { Gv
, EvS
}, 0 },
2310 { "addB", { AL
, Ib
}, 0 },
2311 { "addS", { eAX
, Iv
}, 0 },
2312 { X86_64_TABLE (X86_64_06
) },
2313 { X86_64_TABLE (X86_64_07
) },
2315 { "orB", { Ebh1
, Gb
}, 0 },
2316 { "orS", { Evh1
, Gv
}, 0 },
2317 { "orB", { Gb
, EbS
}, 0 },
2318 { "orS", { Gv
, EvS
}, 0 },
2319 { "orB", { AL
, Ib
}, 0 },
2320 { "orS", { eAX
, Iv
}, 0 },
2321 { X86_64_TABLE (X86_64_0E
) },
2322 { Bad_Opcode
}, /* 0x0f extended opcode escape */
2324 { "adcB", { Ebh1
, Gb
}, 0 },
2325 { "adcS", { Evh1
, Gv
}, 0 },
2326 { "adcB", { Gb
, EbS
}, 0 },
2327 { "adcS", { Gv
, EvS
}, 0 },
2328 { "adcB", { AL
, Ib
}, 0 },
2329 { "adcS", { eAX
, Iv
}, 0 },
2330 { X86_64_TABLE (X86_64_16
) },
2331 { X86_64_TABLE (X86_64_17
) },
2333 { "sbbB", { Ebh1
, Gb
}, 0 },
2334 { "sbbS", { Evh1
, Gv
}, 0 },
2335 { "sbbB", { Gb
, EbS
}, 0 },
2336 { "sbbS", { Gv
, EvS
}, 0 },
2337 { "sbbB", { AL
, Ib
}, 0 },
2338 { "sbbS", { eAX
, Iv
}, 0 },
2339 { X86_64_TABLE (X86_64_1E
) },
2340 { X86_64_TABLE (X86_64_1F
) },
2342 { "andB", { Ebh1
, Gb
}, 0 },
2343 { "andS", { Evh1
, Gv
}, 0 },
2344 { "andB", { Gb
, EbS
}, 0 },
2345 { "andS", { Gv
, EvS
}, 0 },
2346 { "andB", { AL
, Ib
}, 0 },
2347 { "andS", { eAX
, Iv
}, 0 },
2348 { Bad_Opcode
}, /* SEG ES prefix */
2349 { X86_64_TABLE (X86_64_27
) },
2351 { "subB", { Ebh1
, Gb
}, 0 },
2352 { "subS", { Evh1
, Gv
}, 0 },
2353 { "subB", { Gb
, EbS
}, 0 },
2354 { "subS", { Gv
, EvS
}, 0 },
2355 { "subB", { AL
, Ib
}, 0 },
2356 { "subS", { eAX
, Iv
}, 0 },
2357 { Bad_Opcode
}, /* SEG CS prefix */
2358 { X86_64_TABLE (X86_64_2F
) },
2360 { "xorB", { Ebh1
, Gb
}, 0 },
2361 { "xorS", { Evh1
, Gv
}, 0 },
2362 { "xorB", { Gb
, EbS
}, 0 },
2363 { "xorS", { Gv
, EvS
}, 0 },
2364 { "xorB", { AL
, Ib
}, 0 },
2365 { "xorS", { eAX
, Iv
}, 0 },
2366 { Bad_Opcode
}, /* SEG SS prefix */
2367 { X86_64_TABLE (X86_64_37
) },
2369 { "cmpB", { Eb
, Gb
}, 0 },
2370 { "cmpS", { Ev
, Gv
}, 0 },
2371 { "cmpB", { Gb
, EbS
}, 0 },
2372 { "cmpS", { Gv
, EvS
}, 0 },
2373 { "cmpB", { AL
, Ib
}, 0 },
2374 { "cmpS", { eAX
, Iv
}, 0 },
2375 { Bad_Opcode
}, /* SEG DS prefix */
2376 { X86_64_TABLE (X86_64_3F
) },
2378 { "inc{S|}", { RMeAX
}, 0 },
2379 { "inc{S|}", { RMeCX
}, 0 },
2380 { "inc{S|}", { RMeDX
}, 0 },
2381 { "inc{S|}", { RMeBX
}, 0 },
2382 { "inc{S|}", { RMeSP
}, 0 },
2383 { "inc{S|}", { RMeBP
}, 0 },
2384 { "inc{S|}", { RMeSI
}, 0 },
2385 { "inc{S|}", { RMeDI
}, 0 },
2387 { "dec{S|}", { RMeAX
}, 0 },
2388 { "dec{S|}", { RMeCX
}, 0 },
2389 { "dec{S|}", { RMeDX
}, 0 },
2390 { "dec{S|}", { RMeBX
}, 0 },
2391 { "dec{S|}", { RMeSP
}, 0 },
2392 { "dec{S|}", { RMeBP
}, 0 },
2393 { "dec{S|}", { RMeSI
}, 0 },
2394 { "dec{S|}", { RMeDI
}, 0 },
2396 { "pushV", { RMrAX
}, 0 },
2397 { "pushV", { RMrCX
}, 0 },
2398 { "pushV", { RMrDX
}, 0 },
2399 { "pushV", { RMrBX
}, 0 },
2400 { "pushV", { RMrSP
}, 0 },
2401 { "pushV", { RMrBP
}, 0 },
2402 { "pushV", { RMrSI
}, 0 },
2403 { "pushV", { RMrDI
}, 0 },
2405 { "popV", { RMrAX
}, 0 },
2406 { "popV", { RMrCX
}, 0 },
2407 { "popV", { RMrDX
}, 0 },
2408 { "popV", { RMrBX
}, 0 },
2409 { "popV", { RMrSP
}, 0 },
2410 { "popV", { RMrBP
}, 0 },
2411 { "popV", { RMrSI
}, 0 },
2412 { "popV", { RMrDI
}, 0 },
2414 { X86_64_TABLE (X86_64_60
) },
2415 { X86_64_TABLE (X86_64_61
) },
2416 { X86_64_TABLE (X86_64_62
) },
2417 { X86_64_TABLE (X86_64_63
) },
2418 { Bad_Opcode
}, /* seg fs */
2419 { Bad_Opcode
}, /* seg gs */
2420 { Bad_Opcode
}, /* op size prefix */
2421 { Bad_Opcode
}, /* adr size prefix */
2423 { "pushT", { sIv
}, 0 },
2424 { "imulS", { Gv
, Ev
, Iv
}, 0 },
2425 { "pushT", { sIbT
}, 0 },
2426 { "imulS", { Gv
, Ev
, sIb
}, 0 },
2427 { "ins{b|}", { Ybr
, indirDX
}, 0 },
2428 { X86_64_TABLE (X86_64_6D
) },
2429 { "outs{b|}", { indirDXr
, Xb
}, 0 },
2430 { X86_64_TABLE (X86_64_6F
) },
2432 { "joH", { Jb
, BND
, cond_jump_flag
}, 0 },
2433 { "jnoH", { Jb
, BND
, cond_jump_flag
}, 0 },
2434 { "jbH", { Jb
, BND
, cond_jump_flag
}, 0 },
2435 { "jaeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2436 { "jeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2437 { "jneH", { Jb
, BND
, cond_jump_flag
}, 0 },
2438 { "jbeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2439 { "jaH", { Jb
, BND
, cond_jump_flag
}, 0 },
2441 { "jsH", { Jb
, BND
, cond_jump_flag
}, 0 },
2442 { "jnsH", { Jb
, BND
, cond_jump_flag
}, 0 },
2443 { "jpH", { Jb
, BND
, cond_jump_flag
}, 0 },
2444 { "jnpH", { Jb
, BND
, cond_jump_flag
}, 0 },
2445 { "jlH", { Jb
, BND
, cond_jump_flag
}, 0 },
2446 { "jgeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2447 { "jleH", { Jb
, BND
, cond_jump_flag
}, 0 },
2448 { "jgH", { Jb
, BND
, cond_jump_flag
}, 0 },
2450 { REG_TABLE (REG_80
) },
2451 { REG_TABLE (REG_81
) },
2452 { X86_64_TABLE (X86_64_82
) },
2453 { REG_TABLE (REG_83
) },
2454 { "testB", { Eb
, Gb
}, 0 },
2455 { "testS", { Ev
, Gv
}, 0 },
2456 { "xchgB", { Ebh2
, Gb
}, 0 },
2457 { "xchgS", { Evh2
, Gv
}, 0 },
2459 { "movB", { Ebh3
, Gb
}, 0 },
2460 { "movS", { Evh3
, Gv
}, 0 },
2461 { "movB", { Gb
, EbS
}, 0 },
2462 { "movS", { Gv
, EvS
}, 0 },
2463 { "movD", { Sv
, Sw
}, 0 },
2464 { MOD_TABLE (MOD_8D
) },
2465 { "movD", { Sw
, Sv
}, 0 },
2466 { REG_TABLE (REG_8F
) },
2468 { PREFIX_TABLE (PREFIX_90
) },
2469 { "xchgS", { RMeCX
, eAX
}, 0 },
2470 { "xchgS", { RMeDX
, eAX
}, 0 },
2471 { "xchgS", { RMeBX
, eAX
}, 0 },
2472 { "xchgS", { RMeSP
, eAX
}, 0 },
2473 { "xchgS", { RMeBP
, eAX
}, 0 },
2474 { "xchgS", { RMeSI
, eAX
}, 0 },
2475 { "xchgS", { RMeDI
, eAX
}, 0 },
2477 { "cW{t|}R", { XX
}, 0 },
2478 { "cR{t|}O", { XX
}, 0 },
2479 { X86_64_TABLE (X86_64_9A
) },
2480 { Bad_Opcode
}, /* fwait */
2481 { "pushfT", { XX
}, 0 },
2482 { "popfT", { XX
}, 0 },
2483 { "sahf", { XX
}, 0 },
2484 { "lahf", { XX
}, 0 },
2486 { "mov%LB", { AL
, Ob
}, 0 },
2487 { "mov%LS", { eAX
, Ov
}, 0 },
2488 { "mov%LB", { Ob
, AL
}, 0 },
2489 { "mov%LS", { Ov
, eAX
}, 0 },
2490 { "movs{b|}", { Ybr
, Xb
}, 0 },
2491 { "movs{R|}", { Yvr
, Xv
}, 0 },
2492 { "cmps{b|}", { Xb
, Yb
}, 0 },
2493 { "cmps{R|}", { Xv
, Yv
}, 0 },
2495 { "testB", { AL
, Ib
}, 0 },
2496 { "testS", { eAX
, Iv
}, 0 },
2497 { "stosB", { Ybr
, AL
}, 0 },
2498 { "stosS", { Yvr
, eAX
}, 0 },
2499 { "lodsB", { ALr
, Xb
}, 0 },
2500 { "lodsS", { eAXr
, Xv
}, 0 },
2501 { "scasB", { AL
, Yb
}, 0 },
2502 { "scasS", { eAX
, Yv
}, 0 },
2504 { "movB", { RMAL
, Ib
}, 0 },
2505 { "movB", { RMCL
, Ib
}, 0 },
2506 { "movB", { RMDL
, Ib
}, 0 },
2507 { "movB", { RMBL
, Ib
}, 0 },
2508 { "movB", { RMAH
, Ib
}, 0 },
2509 { "movB", { RMCH
, Ib
}, 0 },
2510 { "movB", { RMDH
, Ib
}, 0 },
2511 { "movB", { RMBH
, Ib
}, 0 },
2513 { "mov%LV", { RMeAX
, Iv64
}, 0 },
2514 { "mov%LV", { RMeCX
, Iv64
}, 0 },
2515 { "mov%LV", { RMeDX
, Iv64
}, 0 },
2516 { "mov%LV", { RMeBX
, Iv64
}, 0 },
2517 { "mov%LV", { RMeSP
, Iv64
}, 0 },
2518 { "mov%LV", { RMeBP
, Iv64
}, 0 },
2519 { "mov%LV", { RMeSI
, Iv64
}, 0 },
2520 { "mov%LV", { RMeDI
, Iv64
}, 0 },
2522 { REG_TABLE (REG_C0
) },
2523 { REG_TABLE (REG_C1
) },
2524 { X86_64_TABLE (X86_64_C2
) },
2525 { X86_64_TABLE (X86_64_C3
) },
2526 { X86_64_TABLE (X86_64_C4
) },
2527 { X86_64_TABLE (X86_64_C5
) },
2528 { REG_TABLE (REG_C6
) },
2529 { REG_TABLE (REG_C7
) },
2531 { "enterT", { Iw
, Ib
}, 0 },
2532 { "leaveT", { XX
}, 0 },
2533 { "{l|}ret{|f}P", { Iw
}, 0 },
2534 { "{l|}ret{|f}P", { XX
}, 0 },
2535 { "int3", { XX
}, 0 },
2536 { "int", { Ib
}, 0 },
2537 { X86_64_TABLE (X86_64_CE
) },
2538 { "iret%LP", { XX
}, 0 },
2540 { REG_TABLE (REG_D0
) },
2541 { REG_TABLE (REG_D1
) },
2542 { REG_TABLE (REG_D2
) },
2543 { REG_TABLE (REG_D3
) },
2544 { X86_64_TABLE (X86_64_D4
) },
2545 { X86_64_TABLE (X86_64_D5
) },
2547 { "xlat", { DSBX
}, 0 },
2558 { "loopneFH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2559 { "loopeFH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2560 { "loopFH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2561 { "jEcxzH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2562 { "inB", { AL
, Ib
}, 0 },
2563 { "inG", { zAX
, Ib
}, 0 },
2564 { "outB", { Ib
, AL
}, 0 },
2565 { "outG", { Ib
, zAX
}, 0 },
2567 { X86_64_TABLE (X86_64_E8
) },
2568 { X86_64_TABLE (X86_64_E9
) },
2569 { X86_64_TABLE (X86_64_EA
) },
2570 { "jmp", { Jb
, BND
}, 0 },
2571 { "inB", { AL
, indirDX
}, 0 },
2572 { "inG", { zAX
, indirDX
}, 0 },
2573 { "outB", { indirDX
, AL
}, 0 },
2574 { "outG", { indirDX
, zAX
}, 0 },
2576 { Bad_Opcode
}, /* lock prefix */
2577 { "icebp", { XX
}, 0 },
2578 { Bad_Opcode
}, /* repne */
2579 { Bad_Opcode
}, /* repz */
2580 { "hlt", { XX
}, 0 },
2581 { "cmc", { XX
}, 0 },
2582 { REG_TABLE (REG_F6
) },
2583 { REG_TABLE (REG_F7
) },
2585 { "clc", { XX
}, 0 },
2586 { "stc", { XX
}, 0 },
2587 { "cli", { XX
}, 0 },
2588 { "sti", { XX
}, 0 },
2589 { "cld", { XX
}, 0 },
2590 { "std", { XX
}, 0 },
2591 { REG_TABLE (REG_FE
) },
2592 { REG_TABLE (REG_FF
) },
2595 static const struct dis386 dis386_twobyte
[] = {
2597 { REG_TABLE (REG_0F00
) },
2598 { REG_TABLE (REG_0F01
) },
2599 { "larS", { Gv
, Ew
}, 0 },
2600 { "lslS", { Gv
, Ew
}, 0 },
2602 { "syscall", { XX
}, 0 },
2603 { "clts", { XX
}, 0 },
2604 { "sysret%LQ", { XX
}, 0 },
2606 { "invd", { XX
}, 0 },
2607 { PREFIX_TABLE (PREFIX_0F09
) },
2609 { "ud2", { XX
}, 0 },
2611 { REG_TABLE (REG_0F0D
) },
2612 { "femms", { XX
}, 0 },
2613 { "", { MX
, EM
, OPSUF
}, 0 }, /* See OP_3DNowSuffix. */
2615 { PREFIX_TABLE (PREFIX_0F10
) },
2616 { PREFIX_TABLE (PREFIX_0F11
) },
2617 { PREFIX_TABLE (PREFIX_0F12
) },
2618 { MOD_TABLE (MOD_0F13
) },
2619 { "unpcklpX", { XM
, EXx
}, PREFIX_OPCODE
},
2620 { "unpckhpX", { XM
, EXx
}, PREFIX_OPCODE
},
2621 { PREFIX_TABLE (PREFIX_0F16
) },
2622 { MOD_TABLE (MOD_0F17
) },
2624 { REG_TABLE (REG_0F18
) },
2625 { "nopQ", { Ev
}, 0 },
2626 { PREFIX_TABLE (PREFIX_0F1A
) },
2627 { PREFIX_TABLE (PREFIX_0F1B
) },
2628 { PREFIX_TABLE (PREFIX_0F1C
) },
2629 { "nopQ", { Ev
}, 0 },
2630 { PREFIX_TABLE (PREFIX_0F1E
) },
2631 { "nopQ", { Ev
}, 0 },
2633 { "movZ", { Rm
, Cm
}, 0 },
2634 { "movZ", { Rm
, Dm
}, 0 },
2635 { "movZ", { Cm
, Rm
}, 0 },
2636 { "movZ", { Dm
, Rm
}, 0 },
2637 { MOD_TABLE (MOD_0F24
) },
2639 { MOD_TABLE (MOD_0F26
) },
2642 { "movapX", { XM
, EXx
}, PREFIX_OPCODE
},
2643 { "movapX", { EXxS
, XM
}, PREFIX_OPCODE
},
2644 { PREFIX_TABLE (PREFIX_0F2A
) },
2645 { PREFIX_TABLE (PREFIX_0F2B
) },
2646 { PREFIX_TABLE (PREFIX_0F2C
) },
2647 { PREFIX_TABLE (PREFIX_0F2D
) },
2648 { PREFIX_TABLE (PREFIX_0F2E
) },
2649 { PREFIX_TABLE (PREFIX_0F2F
) },
2651 { "wrmsr", { XX
}, 0 },
2652 { "rdtsc", { XX
}, 0 },
2653 { "rdmsr", { XX
}, 0 },
2654 { "rdpmc", { XX
}, 0 },
2655 { "sysenter", { SEP
}, 0 },
2656 { "sysexit", { SEP
}, 0 },
2658 { "getsec", { XX
}, 0 },
2660 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38
, PREFIX_OPCODE
) },
2662 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A
, PREFIX_OPCODE
) },
2669 { "cmovoS", { Gv
, Ev
}, 0 },
2670 { "cmovnoS", { Gv
, Ev
}, 0 },
2671 { "cmovbS", { Gv
, Ev
}, 0 },
2672 { "cmovaeS", { Gv
, Ev
}, 0 },
2673 { "cmoveS", { Gv
, Ev
}, 0 },
2674 { "cmovneS", { Gv
, Ev
}, 0 },
2675 { "cmovbeS", { Gv
, Ev
}, 0 },
2676 { "cmovaS", { Gv
, Ev
}, 0 },
2678 { "cmovsS", { Gv
, Ev
}, 0 },
2679 { "cmovnsS", { Gv
, Ev
}, 0 },
2680 { "cmovpS", { Gv
, Ev
}, 0 },
2681 { "cmovnpS", { Gv
, Ev
}, 0 },
2682 { "cmovlS", { Gv
, Ev
}, 0 },
2683 { "cmovgeS", { Gv
, Ev
}, 0 },
2684 { "cmovleS", { Gv
, Ev
}, 0 },
2685 { "cmovgS", { Gv
, Ev
}, 0 },
2687 { MOD_TABLE (MOD_0F50
) },
2688 { PREFIX_TABLE (PREFIX_0F51
) },
2689 { PREFIX_TABLE (PREFIX_0F52
) },
2690 { PREFIX_TABLE (PREFIX_0F53
) },
2691 { "andpX", { XM
, EXx
}, PREFIX_OPCODE
},
2692 { "andnpX", { XM
, EXx
}, PREFIX_OPCODE
},
2693 { "orpX", { XM
, EXx
}, PREFIX_OPCODE
},
2694 { "xorpX", { XM
, EXx
}, PREFIX_OPCODE
},
2696 { PREFIX_TABLE (PREFIX_0F58
) },
2697 { PREFIX_TABLE (PREFIX_0F59
) },
2698 { PREFIX_TABLE (PREFIX_0F5A
) },
2699 { PREFIX_TABLE (PREFIX_0F5B
) },
2700 { PREFIX_TABLE (PREFIX_0F5C
) },
2701 { PREFIX_TABLE (PREFIX_0F5D
) },
2702 { PREFIX_TABLE (PREFIX_0F5E
) },
2703 { PREFIX_TABLE (PREFIX_0F5F
) },
2705 { PREFIX_TABLE (PREFIX_0F60
) },
2706 { PREFIX_TABLE (PREFIX_0F61
) },
2707 { PREFIX_TABLE (PREFIX_0F62
) },
2708 { "packsswb", { MX
, EM
}, PREFIX_OPCODE
},
2709 { "pcmpgtb", { MX
, EM
}, PREFIX_OPCODE
},
2710 { "pcmpgtw", { MX
, EM
}, PREFIX_OPCODE
},
2711 { "pcmpgtd", { MX
, EM
}, PREFIX_OPCODE
},
2712 { "packuswb", { MX
, EM
}, PREFIX_OPCODE
},
2714 { "punpckhbw", { MX
, EM
}, PREFIX_OPCODE
},
2715 { "punpckhwd", { MX
, EM
}, PREFIX_OPCODE
},
2716 { "punpckhdq", { MX
, EM
}, PREFIX_OPCODE
},
2717 { "packssdw", { MX
, EM
}, PREFIX_OPCODE
},
2718 { PREFIX_TABLE (PREFIX_0F6C
) },
2719 { PREFIX_TABLE (PREFIX_0F6D
) },
2720 { "movK", { MX
, Edq
}, PREFIX_OPCODE
},
2721 { PREFIX_TABLE (PREFIX_0F6F
) },
2723 { PREFIX_TABLE (PREFIX_0F70
) },
2724 { REG_TABLE (REG_0F71
) },
2725 { REG_TABLE (REG_0F72
) },
2726 { REG_TABLE (REG_0F73
) },
2727 { "pcmpeqb", { MX
, EM
}, PREFIX_OPCODE
},
2728 { "pcmpeqw", { MX
, EM
}, PREFIX_OPCODE
},
2729 { "pcmpeqd", { MX
, EM
}, PREFIX_OPCODE
},
2730 { "emms", { XX
}, PREFIX_OPCODE
},
2732 { PREFIX_TABLE (PREFIX_0F78
) },
2733 { PREFIX_TABLE (PREFIX_0F79
) },
2736 { PREFIX_TABLE (PREFIX_0F7C
) },
2737 { PREFIX_TABLE (PREFIX_0F7D
) },
2738 { PREFIX_TABLE (PREFIX_0F7E
) },
2739 { PREFIX_TABLE (PREFIX_0F7F
) },
2741 { "joH", { Jv
, BND
, cond_jump_flag
}, 0 },
2742 { "jnoH", { Jv
, BND
, cond_jump_flag
}, 0 },
2743 { "jbH", { Jv
, BND
, cond_jump_flag
}, 0 },
2744 { "jaeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2745 { "jeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2746 { "jneH", { Jv
, BND
, cond_jump_flag
}, 0 },
2747 { "jbeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2748 { "jaH", { Jv
, BND
, cond_jump_flag
}, 0 },
2750 { "jsH", { Jv
, BND
, cond_jump_flag
}, 0 },
2751 { "jnsH", { Jv
, BND
, cond_jump_flag
}, 0 },
2752 { "jpH", { Jv
, BND
, cond_jump_flag
}, 0 },
2753 { "jnpH", { Jv
, BND
, cond_jump_flag
}, 0 },
2754 { "jlH", { Jv
, BND
, cond_jump_flag
}, 0 },
2755 { "jgeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2756 { "jleH", { Jv
, BND
, cond_jump_flag
}, 0 },
2757 { "jgH", { Jv
, BND
, cond_jump_flag
}, 0 },
2759 { "seto", { Eb
}, 0 },
2760 { "setno", { Eb
}, 0 },
2761 { "setb", { Eb
}, 0 },
2762 { "setae", { Eb
}, 0 },
2763 { "sete", { Eb
}, 0 },
2764 { "setne", { Eb
}, 0 },
2765 { "setbe", { Eb
}, 0 },
2766 { "seta", { Eb
}, 0 },
2768 { "sets", { Eb
}, 0 },
2769 { "setns", { Eb
}, 0 },
2770 { "setp", { Eb
}, 0 },
2771 { "setnp", { Eb
}, 0 },
2772 { "setl", { Eb
}, 0 },
2773 { "setge", { Eb
}, 0 },
2774 { "setle", { Eb
}, 0 },
2775 { "setg", { Eb
}, 0 },
2777 { "pushT", { fs
}, 0 },
2778 { "popT", { fs
}, 0 },
2779 { "cpuid", { XX
}, 0 },
2780 { "btS", { Ev
, Gv
}, 0 },
2781 { "shldS", { Ev
, Gv
, Ib
}, 0 },
2782 { "shldS", { Ev
, Gv
, CL
}, 0 },
2783 { REG_TABLE (REG_0FA6
) },
2784 { REG_TABLE (REG_0FA7
) },
2786 { "pushT", { gs
}, 0 },
2787 { "popT", { gs
}, 0 },
2788 { "rsm", { XX
}, 0 },
2789 { "btsS", { Evh1
, Gv
}, 0 },
2790 { "shrdS", { Ev
, Gv
, Ib
}, 0 },
2791 { "shrdS", { Ev
, Gv
, CL
}, 0 },
2792 { REG_TABLE (REG_0FAE
) },
2793 { "imulS", { Gv
, Ev
}, 0 },
2795 { "cmpxchgB", { Ebh1
, Gb
}, 0 },
2796 { "cmpxchgS", { Evh1
, Gv
}, 0 },
2797 { MOD_TABLE (MOD_0FB2
) },
2798 { "btrS", { Evh1
, Gv
}, 0 },
2799 { MOD_TABLE (MOD_0FB4
) },
2800 { MOD_TABLE (MOD_0FB5
) },
2801 { "movz{bR|x}", { Gv
, Eb
}, 0 },
2802 { "movz{wR|x}", { Gv
, Ew
}, 0 }, /* yes, there really is movzww ! */
2804 { PREFIX_TABLE (PREFIX_0FB8
) },
2805 { "ud1S", { Gv
, Ev
}, 0 },
2806 { REG_TABLE (REG_0FBA
) },
2807 { "btcS", { Evh1
, Gv
}, 0 },
2808 { PREFIX_TABLE (PREFIX_0FBC
) },
2809 { PREFIX_TABLE (PREFIX_0FBD
) },
2810 { "movs{bR|x}", { Gv
, Eb
}, 0 },
2811 { "movs{wR|x}", { Gv
, Ew
}, 0 }, /* yes, there really is movsww ! */
2813 { "xaddB", { Ebh1
, Gb
}, 0 },
2814 { "xaddS", { Evh1
, Gv
}, 0 },
2815 { PREFIX_TABLE (PREFIX_0FC2
) },
2816 { MOD_TABLE (MOD_0FC3
) },
2817 { "pinsrw", { MX
, Edqw
, Ib
}, PREFIX_OPCODE
},
2818 { "pextrw", { Gdq
, MS
, Ib
}, PREFIX_OPCODE
},
2819 { "shufpX", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
2820 { REG_TABLE (REG_0FC7
) },
2822 { "bswap", { RMeAX
}, 0 },
2823 { "bswap", { RMeCX
}, 0 },
2824 { "bswap", { RMeDX
}, 0 },
2825 { "bswap", { RMeBX
}, 0 },
2826 { "bswap", { RMeSP
}, 0 },
2827 { "bswap", { RMeBP
}, 0 },
2828 { "bswap", { RMeSI
}, 0 },
2829 { "bswap", { RMeDI
}, 0 },
2831 { PREFIX_TABLE (PREFIX_0FD0
) },
2832 { "psrlw", { MX
, EM
}, PREFIX_OPCODE
},
2833 { "psrld", { MX
, EM
}, PREFIX_OPCODE
},
2834 { "psrlq", { MX
, EM
}, PREFIX_OPCODE
},
2835 { "paddq", { MX
, EM
}, PREFIX_OPCODE
},
2836 { "pmullw", { MX
, EM
}, PREFIX_OPCODE
},
2837 { PREFIX_TABLE (PREFIX_0FD6
) },
2838 { MOD_TABLE (MOD_0FD7
) },
2840 { "psubusb", { MX
, EM
}, PREFIX_OPCODE
},
2841 { "psubusw", { MX
, EM
}, PREFIX_OPCODE
},
2842 { "pminub", { MX
, EM
}, PREFIX_OPCODE
},
2843 { "pand", { MX
, EM
}, PREFIX_OPCODE
},
2844 { "paddusb", { MX
, EM
}, PREFIX_OPCODE
},
2845 { "paddusw", { MX
, EM
}, PREFIX_OPCODE
},
2846 { "pmaxub", { MX
, EM
}, PREFIX_OPCODE
},
2847 { "pandn", { MX
, EM
}, PREFIX_OPCODE
},
2849 { "pavgb", { MX
, EM
}, PREFIX_OPCODE
},
2850 { "psraw", { MX
, EM
}, PREFIX_OPCODE
},
2851 { "psrad", { MX
, EM
}, PREFIX_OPCODE
},
2852 { "pavgw", { MX
, EM
}, PREFIX_OPCODE
},
2853 { "pmulhuw", { MX
, EM
}, PREFIX_OPCODE
},
2854 { "pmulhw", { MX
, EM
}, PREFIX_OPCODE
},
2855 { PREFIX_TABLE (PREFIX_0FE6
) },
2856 { PREFIX_TABLE (PREFIX_0FE7
) },
2858 { "psubsb", { MX
, EM
}, PREFIX_OPCODE
},
2859 { "psubsw", { MX
, EM
}, PREFIX_OPCODE
},
2860 { "pminsw", { MX
, EM
}, PREFIX_OPCODE
},
2861 { "por", { MX
, EM
}, PREFIX_OPCODE
},
2862 { "paddsb", { MX
, EM
}, PREFIX_OPCODE
},
2863 { "paddsw", { MX
, EM
}, PREFIX_OPCODE
},
2864 { "pmaxsw", { MX
, EM
}, PREFIX_OPCODE
},
2865 { "pxor", { MX
, EM
}, PREFIX_OPCODE
},
2867 { PREFIX_TABLE (PREFIX_0FF0
) },
2868 { "psllw", { MX
, EM
}, PREFIX_OPCODE
},
2869 { "pslld", { MX
, EM
}, PREFIX_OPCODE
},
2870 { "psllq", { MX
, EM
}, PREFIX_OPCODE
},
2871 { "pmuludq", { MX
, EM
}, PREFIX_OPCODE
},
2872 { "pmaddwd", { MX
, EM
}, PREFIX_OPCODE
},
2873 { "psadbw", { MX
, EM
}, PREFIX_OPCODE
},
2874 { PREFIX_TABLE (PREFIX_0FF7
) },
2876 { "psubb", { MX
, EM
}, PREFIX_OPCODE
},
2877 { "psubw", { MX
, EM
}, PREFIX_OPCODE
},
2878 { "psubd", { MX
, EM
}, PREFIX_OPCODE
},
2879 { "psubq", { MX
, EM
}, PREFIX_OPCODE
},
2880 { "paddb", { MX
, EM
}, PREFIX_OPCODE
},
2881 { "paddw", { MX
, EM
}, PREFIX_OPCODE
},
2882 { "paddd", { MX
, EM
}, PREFIX_OPCODE
},
2883 { "ud0S", { Gv
, Ev
}, 0 },
2886 static const unsigned char onebyte_has_modrm
[256] = {
2887 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2888 /* ------------------------------- */
2889 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2890 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2891 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2892 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2893 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2894 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2895 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2896 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2897 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2898 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2899 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2900 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2901 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2902 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2903 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2904 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
2905 /* ------------------------------- */
2906 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2909 static const unsigned char twobyte_has_modrm
[256] = {
2910 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2911 /* ------------------------------- */
2912 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2913 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2914 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2915 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2916 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2917 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2918 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2919 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2920 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2921 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2922 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2923 /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */
2924 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2925 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2926 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2927 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1 /* ff */
2928 /* ------------------------------- */
2929 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2932 static char obuf
[100];
2934 static char *mnemonicendp
;
2935 static char scratchbuf
[100];
2936 static unsigned char *start_codep
;
2937 static unsigned char *insn_codep
;
2938 static unsigned char *codep
;
2939 static unsigned char *end_codep
;
2940 static int last_lock_prefix
;
2941 static int last_repz_prefix
;
2942 static int last_repnz_prefix
;
2943 static int last_data_prefix
;
2944 static int last_addr_prefix
;
2945 static int last_rex_prefix
;
2946 static int last_seg_prefix
;
2947 static int fwait_prefix
;
2948 /* The active segment register prefix. */
2949 static int active_seg_prefix
;
2950 #define MAX_CODE_LENGTH 15
2951 /* We can up to 14 prefixes since the maximum instruction length is
2953 static int all_prefixes
[MAX_CODE_LENGTH
- 1];
2954 static disassemble_info
*the_info
;
2962 static unsigned char need_modrm
;
2972 int register_specifier
;
2979 int mask_register_specifier
;
2985 static unsigned char need_vex
;
2986 static unsigned char need_vex_reg
;
2987 static unsigned char vex_w_done
;
2995 /* If we are accessing mod/rm/reg without need_modrm set, then the
2996 values are stale. Hitting this abort likely indicates that you
2997 need to update onebyte_has_modrm or twobyte_has_modrm. */
2998 #define MODRM_CHECK if (!need_modrm) abort ()
3000 static const char **names64
;
3001 static const char **names32
;
3002 static const char **names16
;
3003 static const char **names8
;
3004 static const char **names8rex
;
3005 static const char **names_seg
;
3006 static const char *index64
;
3007 static const char *index32
;
3008 static const char **index16
;
3009 static const char **names_bnd
;
3011 static const char *intel_names64
[] = {
3012 "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
3013 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3015 static const char *intel_names32
[] = {
3016 "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
3017 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
3019 static const char *intel_names16
[] = {
3020 "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
3021 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
3023 static const char *intel_names8
[] = {
3024 "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
3026 static const char *intel_names8rex
[] = {
3027 "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
3028 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
3030 static const char *intel_names_seg
[] = {
3031 "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
3033 static const char *intel_index64
= "riz";
3034 static const char *intel_index32
= "eiz";
3035 static const char *intel_index16
[] = {
3036 "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
3039 static const char *att_names64
[] = {
3040 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
3041 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
3043 static const char *att_names32
[] = {
3044 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
3045 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
3047 static const char *att_names16
[] = {
3048 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
3049 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
3051 static const char *att_names8
[] = {
3052 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
3054 static const char *att_names8rex
[] = {
3055 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
3056 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
3058 static const char *att_names_seg
[] = {
3059 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
3061 static const char *att_index64
= "%riz";
3062 static const char *att_index32
= "%eiz";
3063 static const char *att_index16
[] = {
3064 "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
3067 static const char **names_mm
;
3068 static const char *intel_names_mm
[] = {
3069 "mm0", "mm1", "mm2", "mm3",
3070 "mm4", "mm5", "mm6", "mm7"
3072 static const char *att_names_mm
[] = {
3073 "%mm0", "%mm1", "%mm2", "%mm3",
3074 "%mm4", "%mm5", "%mm6", "%mm7"
3077 static const char *intel_names_bnd
[] = {
3078 "bnd0", "bnd1", "bnd2", "bnd3"
3081 static const char *att_names_bnd
[] = {
3082 "%bnd0", "%bnd1", "%bnd2", "%bnd3"
3085 static const char **names_xmm
;
3086 static const char *intel_names_xmm
[] = {
3087 "xmm0", "xmm1", "xmm2", "xmm3",
3088 "xmm4", "xmm5", "xmm6", "xmm7",
3089 "xmm8", "xmm9", "xmm10", "xmm11",
3090 "xmm12", "xmm13", "xmm14", "xmm15",
3091 "xmm16", "xmm17", "xmm18", "xmm19",
3092 "xmm20", "xmm21", "xmm22", "xmm23",
3093 "xmm24", "xmm25", "xmm26", "xmm27",
3094 "xmm28", "xmm29", "xmm30", "xmm31"
3096 static const char *att_names_xmm
[] = {
3097 "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3098 "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3099 "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3100 "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3101 "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3102 "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3103 "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3104 "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3107 static const char **names_ymm
;
3108 static const char *intel_names_ymm
[] = {
3109 "ymm0", "ymm1", "ymm2", "ymm3",
3110 "ymm4", "ymm5", "ymm6", "ymm7",
3111 "ymm8", "ymm9", "ymm10", "ymm11",
3112 "ymm12", "ymm13", "ymm14", "ymm15",
3113 "ymm16", "ymm17", "ymm18", "ymm19",
3114 "ymm20", "ymm21", "ymm22", "ymm23",
3115 "ymm24", "ymm25", "ymm26", "ymm27",
3116 "ymm28", "ymm29", "ymm30", "ymm31"
3118 static const char *att_names_ymm
[] = {
3119 "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3120 "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3121 "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3122 "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3123 "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3124 "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3125 "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3126 "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3129 static const char **names_zmm
;
3130 static const char *intel_names_zmm
[] = {
3131 "zmm0", "zmm1", "zmm2", "zmm3",
3132 "zmm4", "zmm5", "zmm6", "zmm7",
3133 "zmm8", "zmm9", "zmm10", "zmm11",
3134 "zmm12", "zmm13", "zmm14", "zmm15",
3135 "zmm16", "zmm17", "zmm18", "zmm19",
3136 "zmm20", "zmm21", "zmm22", "zmm23",
3137 "zmm24", "zmm25", "zmm26", "zmm27",
3138 "zmm28", "zmm29", "zmm30", "zmm31"
3140 static const char *att_names_zmm
[] = {
3141 "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3142 "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3143 "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3144 "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3145 "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3146 "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3147 "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3148 "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3151 static const char **names_mask
;
3152 static const char *intel_names_mask
[] = {
3153 "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3155 static const char *att_names_mask
[] = {
3156 "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3159 static const char *names_rounding
[] =
3167 static const struct dis386 reg_table
[][8] = {
3170 { "addA", { Ebh1
, Ib
}, 0 },
3171 { "orA", { Ebh1
, Ib
}, 0 },
3172 { "adcA", { Ebh1
, Ib
}, 0 },
3173 { "sbbA", { Ebh1
, Ib
}, 0 },
3174 { "andA", { Ebh1
, Ib
}, 0 },
3175 { "subA", { Ebh1
, Ib
}, 0 },
3176 { "xorA", { Ebh1
, Ib
}, 0 },
3177 { "cmpA", { Eb
, Ib
}, 0 },
3181 { "addQ", { Evh1
, Iv
}, 0 },
3182 { "orQ", { Evh1
, Iv
}, 0 },
3183 { "adcQ", { Evh1
, Iv
}, 0 },
3184 { "sbbQ", { Evh1
, Iv
}, 0 },
3185 { "andQ", { Evh1
, Iv
}, 0 },
3186 { "subQ", { Evh1
, Iv
}, 0 },
3187 { "xorQ", { Evh1
, Iv
}, 0 },
3188 { "cmpQ", { Ev
, Iv
}, 0 },
3192 { "addQ", { Evh1
, sIb
}, 0 },
3193 { "orQ", { Evh1
, sIb
}, 0 },
3194 { "adcQ", { Evh1
, sIb
}, 0 },
3195 { "sbbQ", { Evh1
, sIb
}, 0 },
3196 { "andQ", { Evh1
, sIb
}, 0 },
3197 { "subQ", { Evh1
, sIb
}, 0 },
3198 { "xorQ", { Evh1
, sIb
}, 0 },
3199 { "cmpQ", { Ev
, sIb
}, 0 },
3203 { "popU", { stackEv
}, 0 },
3204 { XOP_8F_TABLE (XOP_09
) },
3208 { XOP_8F_TABLE (XOP_09
) },
3212 { "rolA", { Eb
, Ib
}, 0 },
3213 { "rorA", { Eb
, Ib
}, 0 },
3214 { "rclA", { Eb
, Ib
}, 0 },
3215 { "rcrA", { Eb
, Ib
}, 0 },
3216 { "shlA", { Eb
, Ib
}, 0 },
3217 { "shrA", { Eb
, Ib
}, 0 },
3218 { "shlA", { Eb
, Ib
}, 0 },
3219 { "sarA", { Eb
, Ib
}, 0 },
3223 { "rolQ", { Ev
, Ib
}, 0 },
3224 { "rorQ", { Ev
, Ib
}, 0 },
3225 { "rclQ", { Ev
, Ib
}, 0 },
3226 { "rcrQ", { Ev
, Ib
}, 0 },
3227 { "shlQ", { Ev
, Ib
}, 0 },
3228 { "shrQ", { Ev
, Ib
}, 0 },
3229 { "shlQ", { Ev
, Ib
}, 0 },
3230 { "sarQ", { Ev
, Ib
}, 0 },
3234 { "movA", { Ebh3
, Ib
}, 0 },
3241 { MOD_TABLE (MOD_C6_REG_7
) },
3245 { "movQ", { Evh3
, Iv
}, 0 },
3252 { MOD_TABLE (MOD_C7_REG_7
) },
3256 { "rolA", { Eb
, I1
}, 0 },
3257 { "rorA", { Eb
, I1
}, 0 },
3258 { "rclA", { Eb
, I1
}, 0 },
3259 { "rcrA", { Eb
, I1
}, 0 },
3260 { "shlA", { Eb
, I1
}, 0 },
3261 { "shrA", { Eb
, I1
}, 0 },
3262 { "shlA", { Eb
, I1
}, 0 },
3263 { "sarA", { Eb
, I1
}, 0 },
3267 { "rolQ", { Ev
, I1
}, 0 },
3268 { "rorQ", { Ev
, I1
}, 0 },
3269 { "rclQ", { Ev
, I1
}, 0 },
3270 { "rcrQ", { Ev
, I1
}, 0 },
3271 { "shlQ", { Ev
, I1
}, 0 },
3272 { "shrQ", { Ev
, I1
}, 0 },
3273 { "shlQ", { Ev
, I1
}, 0 },
3274 { "sarQ", { Ev
, I1
}, 0 },
3278 { "rolA", { Eb
, CL
}, 0 },
3279 { "rorA", { Eb
, CL
}, 0 },
3280 { "rclA", { Eb
, CL
}, 0 },
3281 { "rcrA", { Eb
, CL
}, 0 },
3282 { "shlA", { Eb
, CL
}, 0 },
3283 { "shrA", { Eb
, CL
}, 0 },
3284 { "shlA", { Eb
, CL
}, 0 },
3285 { "sarA", { Eb
, CL
}, 0 },
3289 { "rolQ", { Ev
, CL
}, 0 },
3290 { "rorQ", { Ev
, CL
}, 0 },
3291 { "rclQ", { Ev
, CL
}, 0 },
3292 { "rcrQ", { Ev
, CL
}, 0 },
3293 { "shlQ", { Ev
, CL
}, 0 },
3294 { "shrQ", { Ev
, CL
}, 0 },
3295 { "shlQ", { Ev
, CL
}, 0 },
3296 { "sarQ", { Ev
, CL
}, 0 },
3300 { "testA", { Eb
, Ib
}, 0 },
3301 { "testA", { Eb
, Ib
}, 0 },
3302 { "notA", { Ebh1
}, 0 },
3303 { "negA", { Ebh1
}, 0 },
3304 { "mulA", { Eb
}, 0 }, /* Don't print the implicit %al register, */
3305 { "imulA", { Eb
}, 0 }, /* to distinguish these opcodes from other */
3306 { "divA", { Eb
}, 0 }, /* mul/imul opcodes. Do the same for div */
3307 { "idivA", { Eb
}, 0 }, /* and idiv for consistency. */
3311 { "testQ", { Ev
, Iv
}, 0 },
3312 { "testQ", { Ev
, Iv
}, 0 },
3313 { "notQ", { Evh1
}, 0 },
3314 { "negQ", { Evh1
}, 0 },
3315 { "mulQ", { Ev
}, 0 }, /* Don't print the implicit register. */
3316 { "imulQ", { Ev
}, 0 },
3317 { "divQ", { Ev
}, 0 },
3318 { "idivQ", { Ev
}, 0 },
3322 { "incA", { Ebh1
}, 0 },
3323 { "decA", { Ebh1
}, 0 },
3327 { "incQ", { Evh1
}, 0 },
3328 { "decQ", { Evh1
}, 0 },
3329 { "call{&|}", { NOTRACK
, indirEv
, BND
}, 0 },
3330 { MOD_TABLE (MOD_FF_REG_3
) },
3331 { "jmp{&|}", { NOTRACK
, indirEv
, BND
}, 0 },
3332 { MOD_TABLE (MOD_FF_REG_5
) },
3333 { "pushU", { stackEv
}, 0 },
3338 { "sldtD", { Sv
}, 0 },
3339 { "strD", { Sv
}, 0 },
3340 { "lldt", { Ew
}, 0 },
3341 { "ltr", { Ew
}, 0 },
3342 { "verr", { Ew
}, 0 },
3343 { "verw", { Ew
}, 0 },
3349 { MOD_TABLE (MOD_0F01_REG_0
) },
3350 { MOD_TABLE (MOD_0F01_REG_1
) },
3351 { MOD_TABLE (MOD_0F01_REG_2
) },
3352 { MOD_TABLE (MOD_0F01_REG_3
) },
3353 { "smswD", { Sv
}, 0 },
3354 { MOD_TABLE (MOD_0F01_REG_5
) },
3355 { "lmsw", { Ew
}, 0 },
3356 { MOD_TABLE (MOD_0F01_REG_7
) },
3360 { "prefetch", { Mb
}, 0 },
3361 { "prefetchw", { Mb
}, 0 },
3362 { "prefetchwt1", { Mb
}, 0 },
3363 { "prefetch", { Mb
}, 0 },
3364 { "prefetch", { Mb
}, 0 },
3365 { "prefetch", { Mb
}, 0 },
3366 { "prefetch", { Mb
}, 0 },
3367 { "prefetch", { Mb
}, 0 },
3371 { MOD_TABLE (MOD_0F18_REG_0
) },
3372 { MOD_TABLE (MOD_0F18_REG_1
) },
3373 { MOD_TABLE (MOD_0F18_REG_2
) },
3374 { MOD_TABLE (MOD_0F18_REG_3
) },
3375 { MOD_TABLE (MOD_0F18_REG_4
) },
3376 { MOD_TABLE (MOD_0F18_REG_5
) },
3377 { MOD_TABLE (MOD_0F18_REG_6
) },
3378 { MOD_TABLE (MOD_0F18_REG_7
) },
3380 /* REG_0F1C_P_0_MOD_0 */
3382 { "cldemote", { Mb
}, 0 },
3383 { "nopQ", { Ev
}, 0 },
3384 { "nopQ", { Ev
}, 0 },
3385 { "nopQ", { Ev
}, 0 },
3386 { "nopQ", { Ev
}, 0 },
3387 { "nopQ", { Ev
}, 0 },
3388 { "nopQ", { Ev
}, 0 },
3389 { "nopQ", { Ev
}, 0 },
3391 /* REG_0F1E_P_1_MOD_3 */
3393 { "nopQ", { Ev
}, 0 },
3394 { "rdsspK", { Rdq
}, PREFIX_OPCODE
},
3395 { "nopQ", { Ev
}, 0 },
3396 { "nopQ", { Ev
}, 0 },
3397 { "nopQ", { Ev
}, 0 },
3398 { "nopQ", { Ev
}, 0 },
3399 { "nopQ", { Ev
}, 0 },
3400 { RM_TABLE (RM_0F1E_P_1_MOD_3_REG_7
) },
3406 { MOD_TABLE (MOD_0F71_REG_2
) },
3408 { MOD_TABLE (MOD_0F71_REG_4
) },
3410 { MOD_TABLE (MOD_0F71_REG_6
) },
3416 { MOD_TABLE (MOD_0F72_REG_2
) },
3418 { MOD_TABLE (MOD_0F72_REG_4
) },
3420 { MOD_TABLE (MOD_0F72_REG_6
) },
3426 { MOD_TABLE (MOD_0F73_REG_2
) },
3427 { MOD_TABLE (MOD_0F73_REG_3
) },
3430 { MOD_TABLE (MOD_0F73_REG_6
) },
3431 { MOD_TABLE (MOD_0F73_REG_7
) },
3435 { "montmul", { { OP_0f07
, 0 } }, 0 },
3436 { "xsha1", { { OP_0f07
, 0 } }, 0 },
3437 { "xsha256", { { OP_0f07
, 0 } }, 0 },
3441 { "xstore-rng", { { OP_0f07
, 0 } }, 0 },
3442 { "xcrypt-ecb", { { OP_0f07
, 0 } }, 0 },
3443 { "xcrypt-cbc", { { OP_0f07
, 0 } }, 0 },
3444 { "xcrypt-ctr", { { OP_0f07
, 0 } }, 0 },
3445 { "xcrypt-cfb", { { OP_0f07
, 0 } }, 0 },
3446 { "xcrypt-ofb", { { OP_0f07
, 0 } }, 0 },
3450 { MOD_TABLE (MOD_0FAE_REG_0
) },
3451 { MOD_TABLE (MOD_0FAE_REG_1
) },
3452 { MOD_TABLE (MOD_0FAE_REG_2
) },
3453 { MOD_TABLE (MOD_0FAE_REG_3
) },
3454 { MOD_TABLE (MOD_0FAE_REG_4
) },
3455 { MOD_TABLE (MOD_0FAE_REG_5
) },
3456 { MOD_TABLE (MOD_0FAE_REG_6
) },
3457 { MOD_TABLE (MOD_0FAE_REG_7
) },
3465 { "btQ", { Ev
, Ib
}, 0 },
3466 { "btsQ", { Evh1
, Ib
}, 0 },
3467 { "btrQ", { Evh1
, Ib
}, 0 },
3468 { "btcQ", { Evh1
, Ib
}, 0 },
3473 { "cmpxchg8b", { { CMPXCHG8B_Fixup
, q_mode
} }, 0 },
3475 { MOD_TABLE (MOD_0FC7_REG_3
) },
3476 { MOD_TABLE (MOD_0FC7_REG_4
) },
3477 { MOD_TABLE (MOD_0FC7_REG_5
) },
3478 { MOD_TABLE (MOD_0FC7_REG_6
) },
3479 { MOD_TABLE (MOD_0FC7_REG_7
) },
3485 { MOD_TABLE (MOD_VEX_0F71_REG_2
) },
3487 { MOD_TABLE (MOD_VEX_0F71_REG_4
) },
3489 { MOD_TABLE (MOD_VEX_0F71_REG_6
) },
3495 { MOD_TABLE (MOD_VEX_0F72_REG_2
) },
3497 { MOD_TABLE (MOD_VEX_0F72_REG_4
) },
3499 { MOD_TABLE (MOD_VEX_0F72_REG_6
) },
3505 { MOD_TABLE (MOD_VEX_0F73_REG_2
) },
3506 { MOD_TABLE (MOD_VEX_0F73_REG_3
) },
3509 { MOD_TABLE (MOD_VEX_0F73_REG_6
) },
3510 { MOD_TABLE (MOD_VEX_0F73_REG_7
) },
3516 { MOD_TABLE (MOD_VEX_0FAE_REG_2
) },
3517 { MOD_TABLE (MOD_VEX_0FAE_REG_3
) },
3519 /* REG_VEX_0F38F3 */
3522 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1
) },
3523 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2
) },
3524 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3
) },
3528 { "llwpcb", { { OP_LWPCB_E
, 0 } }, 0 },
3529 { "slwpcb", { { OP_LWPCB_E
, 0 } }, 0 },
3533 { "lwpins", { { OP_LWP_E
, 0 }, Ed
, Id
}, 0 },
3534 { "lwpval", { { OP_LWP_E
, 0 }, Ed
, Id
}, 0 },
3536 /* REG_XOP_TBM_01 */
3539 { "blcfill", { { OP_LWP_E
, 0 }, Edq
}, 0 },
3540 { "blsfill", { { OP_LWP_E
, 0 }, Edq
}, 0 },
3541 { "blcs", { { OP_LWP_E
, 0 }, Edq
}, 0 },
3542 { "tzmsk", { { OP_LWP_E
, 0 }, Edq
}, 0 },
3543 { "blcic", { { OP_LWP_E
, 0 }, Edq
}, 0 },
3544 { "blsic", { { OP_LWP_E
, 0 }, Edq
}, 0 },
3545 { "t1mskc", { { OP_LWP_E
, 0 }, Edq
}, 0 },
3547 /* REG_XOP_TBM_02 */
3550 { "blcmsk", { { OP_LWP_E
, 0 }, Edq
}, 0 },
3555 { "blci", { { OP_LWP_E
, 0 }, Edq
}, 0 },
3558 #include "i386-dis-evex-reg.h"
3561 static const struct dis386 prefix_table
[][4] = {
3564 { "xchgS", { { NOP_Fixup1
, eAX_reg
}, { NOP_Fixup2
, eAX_reg
} }, 0 },
3565 { "pause", { XX
}, 0 },
3566 { "xchgS", { { NOP_Fixup1
, eAX_reg
}, { NOP_Fixup2
, eAX_reg
} }, 0 },
3567 { NULL
, { { NULL
, 0 } }, PREFIX_IGNORED
}
3570 /* PREFIX_0F01_REG_3_RM_1 */
3572 { "vmmcall", { Skip_MODRM
}, 0 },
3573 { "vmgexit", { Skip_MODRM
}, 0 },
3575 { "vmgexit", { Skip_MODRM
}, 0 },
3578 /* PREFIX_0F01_REG_5_MOD_0 */
3581 { "rstorssp", { Mq
}, PREFIX_OPCODE
},
3584 /* PREFIX_0F01_REG_5_MOD_3_RM_0 */
3586 { "serialize", { Skip_MODRM
}, PREFIX_OPCODE
},
3587 { "setssbsy", { Skip_MODRM
}, PREFIX_OPCODE
},
3589 { "xsusldtrk", { Skip_MODRM
}, PREFIX_OPCODE
},
3592 /* PREFIX_0F01_REG_5_MOD_3_RM_1 */
3597 { "xresldtrk", { Skip_MODRM
}, PREFIX_OPCODE
},
3600 /* PREFIX_0F01_REG_5_MOD_3_RM_2 */
3603 { "saveprevssp", { Skip_MODRM
}, PREFIX_OPCODE
},
3606 /* PREFIX_0F01_REG_7_MOD_3_RM_2 */
3608 { "monitorx", { { OP_Monitor
, 0 } }, 0 },
3609 { "mcommit", { Skip_MODRM
}, 0 },
3612 /* PREFIX_0F01_REG_7_MOD_3_RM_3 */
3614 { "mwaitx", { { OP_Mwait
, eBX_reg
} }, 0 },
3619 { "wbinvd", { XX
}, 0 },
3620 { "wbnoinvd", { XX
}, 0 },
3625 { "movups", { XM
, EXx
}, PREFIX_OPCODE
},
3626 { "movss", { XM
, EXd
}, PREFIX_OPCODE
},
3627 { "movupd", { XM
, EXx
}, PREFIX_OPCODE
},
3628 { "movsd", { XM
, EXq
}, PREFIX_OPCODE
},
3633 { "movups", { EXxS
, XM
}, PREFIX_OPCODE
},
3634 { "movss", { EXdS
, XM
}, PREFIX_OPCODE
},
3635 { "movupd", { EXxS
, XM
}, PREFIX_OPCODE
},
3636 { "movsd", { EXqS
, XM
}, PREFIX_OPCODE
},
3641 { MOD_TABLE (MOD_0F12_PREFIX_0
) },
3642 { "movsldup", { XM
, EXx
}, PREFIX_OPCODE
},
3643 { MOD_TABLE (MOD_0F12_PREFIX_2
) },
3644 { "movddup", { XM
, EXq
}, PREFIX_OPCODE
},
3649 { MOD_TABLE (MOD_0F16_PREFIX_0
) },
3650 { "movshdup", { XM
, EXx
}, PREFIX_OPCODE
},
3651 { MOD_TABLE (MOD_0F16_PREFIX_2
) },
3656 { MOD_TABLE (MOD_0F1A_PREFIX_0
) },
3657 { "bndcl", { Gbnd
, Ev_bnd
}, 0 },
3658 { "bndmov", { Gbnd
, Ebnd
}, 0 },
3659 { "bndcu", { Gbnd
, Ev_bnd
}, 0 },
3664 { MOD_TABLE (MOD_0F1B_PREFIX_0
) },
3665 { MOD_TABLE (MOD_0F1B_PREFIX_1
) },
3666 { "bndmov", { EbndS
, Gbnd
}, 0 },
3667 { "bndcn", { Gbnd
, Ev_bnd
}, 0 },
3672 { MOD_TABLE (MOD_0F1C_PREFIX_0
) },
3673 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3674 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3675 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3680 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3681 { MOD_TABLE (MOD_0F1E_PREFIX_1
) },
3682 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3683 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3688 { "cvtpi2ps", { XM
, EMCq
}, PREFIX_OPCODE
},
3689 { "cvtsi2ss%LQ", { XM
, Edq
}, PREFIX_OPCODE
},
3690 { "cvtpi2pd", { XM
, EMCq
}, PREFIX_OPCODE
},
3691 { "cvtsi2sd%LQ", { XM
, Edq
}, 0 },
3696 { MOD_TABLE (MOD_0F2B_PREFIX_0
) },
3697 { MOD_TABLE (MOD_0F2B_PREFIX_1
) },
3698 { MOD_TABLE (MOD_0F2B_PREFIX_2
) },
3699 { MOD_TABLE (MOD_0F2B_PREFIX_3
) },
3704 { "cvttps2pi", { MXC
, EXq
}, PREFIX_OPCODE
},
3705 { "cvttss2si", { Gdq
, EXd
}, PREFIX_OPCODE
},
3706 { "cvttpd2pi", { MXC
, EXx
}, PREFIX_OPCODE
},
3707 { "cvttsd2si", { Gdq
, EXq
}, PREFIX_OPCODE
},
3712 { "cvtps2pi", { MXC
, EXq
}, PREFIX_OPCODE
},
3713 { "cvtss2si", { Gdq
, EXd
}, PREFIX_OPCODE
},
3714 { "cvtpd2pi", { MXC
, EXx
}, PREFIX_OPCODE
},
3715 { "cvtsd2si", { Gdq
, EXq
}, PREFIX_OPCODE
},
3720 { "ucomiss",{ XM
, EXd
}, 0 },
3722 { "ucomisd",{ XM
, EXq
}, 0 },
3727 { "comiss", { XM
, EXd
}, 0 },
3729 { "comisd", { XM
, EXq
}, 0 },
3734 { "sqrtps", { XM
, EXx
}, PREFIX_OPCODE
},
3735 { "sqrtss", { XM
, EXd
}, PREFIX_OPCODE
},
3736 { "sqrtpd", { XM
, EXx
}, PREFIX_OPCODE
},
3737 { "sqrtsd", { XM
, EXq
}, PREFIX_OPCODE
},
3742 { "rsqrtps",{ XM
, EXx
}, PREFIX_OPCODE
},
3743 { "rsqrtss",{ XM
, EXd
}, PREFIX_OPCODE
},
3748 { "rcpps", { XM
, EXx
}, PREFIX_OPCODE
},
3749 { "rcpss", { XM
, EXd
}, PREFIX_OPCODE
},
3754 { "addps", { XM
, EXx
}, PREFIX_OPCODE
},
3755 { "addss", { XM
, EXd
}, PREFIX_OPCODE
},
3756 { "addpd", { XM
, EXx
}, PREFIX_OPCODE
},
3757 { "addsd", { XM
, EXq
}, PREFIX_OPCODE
},
3762 { "mulps", { XM
, EXx
}, PREFIX_OPCODE
},
3763 { "mulss", { XM
, EXd
}, PREFIX_OPCODE
},
3764 { "mulpd", { XM
, EXx
}, PREFIX_OPCODE
},
3765 { "mulsd", { XM
, EXq
}, PREFIX_OPCODE
},
3770 { "cvtps2pd", { XM
, EXq
}, PREFIX_OPCODE
},
3771 { "cvtss2sd", { XM
, EXd
}, PREFIX_OPCODE
},
3772 { "cvtpd2ps", { XM
, EXx
}, PREFIX_OPCODE
},
3773 { "cvtsd2ss", { XM
, EXq
}, PREFIX_OPCODE
},
3778 { "cvtdq2ps", { XM
, EXx
}, PREFIX_OPCODE
},
3779 { "cvttps2dq", { XM
, EXx
}, PREFIX_OPCODE
},
3780 { "cvtps2dq", { XM
, EXx
}, PREFIX_OPCODE
},
3785 { "subps", { XM
, EXx
}, PREFIX_OPCODE
},
3786 { "subss", { XM
, EXd
}, PREFIX_OPCODE
},
3787 { "subpd", { XM
, EXx
}, PREFIX_OPCODE
},
3788 { "subsd", { XM
, EXq
}, PREFIX_OPCODE
},
3793 { "minps", { XM
, EXx
}, PREFIX_OPCODE
},
3794 { "minss", { XM
, EXd
}, PREFIX_OPCODE
},
3795 { "minpd", { XM
, EXx
}, PREFIX_OPCODE
},
3796 { "minsd", { XM
, EXq
}, PREFIX_OPCODE
},
3801 { "divps", { XM
, EXx
}, PREFIX_OPCODE
},
3802 { "divss", { XM
, EXd
}, PREFIX_OPCODE
},
3803 { "divpd", { XM
, EXx
}, PREFIX_OPCODE
},
3804 { "divsd", { XM
, EXq
}, PREFIX_OPCODE
},
3809 { "maxps", { XM
, EXx
}, PREFIX_OPCODE
},
3810 { "maxss", { XM
, EXd
}, PREFIX_OPCODE
},
3811 { "maxpd", { XM
, EXx
}, PREFIX_OPCODE
},
3812 { "maxsd", { XM
, EXq
}, PREFIX_OPCODE
},
3817 { "punpcklbw",{ MX
, EMd
}, PREFIX_OPCODE
},
3819 { "punpcklbw",{ MX
, EMx
}, PREFIX_OPCODE
},
3824 { "punpcklwd",{ MX
, EMd
}, PREFIX_OPCODE
},
3826 { "punpcklwd",{ MX
, EMx
}, PREFIX_OPCODE
},
3831 { "punpckldq",{ MX
, EMd
}, PREFIX_OPCODE
},
3833 { "punpckldq",{ MX
, EMx
}, PREFIX_OPCODE
},
3840 { "punpcklqdq", { XM
, EXx
}, PREFIX_OPCODE
},
3847 { "punpckhqdq", { XM
, EXx
}, PREFIX_OPCODE
},
3852 { "movq", { MX
, EM
}, PREFIX_OPCODE
},
3853 { "movdqu", { XM
, EXx
}, PREFIX_OPCODE
},
3854 { "movdqa", { XM
, EXx
}, PREFIX_OPCODE
},
3859 { "pshufw", { MX
, EM
, Ib
}, PREFIX_OPCODE
},
3860 { "pshufhw",{ XM
, EXx
, Ib
}, PREFIX_OPCODE
},
3861 { "pshufd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
3862 { "pshuflw",{ XM
, EXx
, Ib
}, PREFIX_OPCODE
},
3865 /* PREFIX_0F73_REG_3 */
3869 { "psrldq", { XS
, Ib
}, 0 },
3872 /* PREFIX_0F73_REG_7 */
3876 { "pslldq", { XS
, Ib
}, 0 },
3881 {"vmread", { Em
, Gm
}, 0 },
3883 {"extrq", { XS
, Ib
, Ib
}, 0 },
3884 {"insertq", { XM
, XS
, Ib
, Ib
}, 0 },
3889 {"vmwrite", { Gm
, Em
}, 0 },
3891 {"extrq", { XM
, XS
}, 0 },
3892 {"insertq", { XM
, XS
}, 0 },
3899 { "haddpd", { XM
, EXx
}, PREFIX_OPCODE
},
3900 { "haddps", { XM
, EXx
}, PREFIX_OPCODE
},
3907 { "hsubpd", { XM
, EXx
}, PREFIX_OPCODE
},
3908 { "hsubps", { XM
, EXx
}, PREFIX_OPCODE
},
3913 { "movK", { Edq
, MX
}, PREFIX_OPCODE
},
3914 { "movq", { XM
, EXq
}, PREFIX_OPCODE
},
3915 { "movK", { Edq
, XM
}, PREFIX_OPCODE
},
3920 { "movq", { EMS
, MX
}, PREFIX_OPCODE
},
3921 { "movdqu", { EXxS
, XM
}, PREFIX_OPCODE
},
3922 { "movdqa", { EXxS
, XM
}, PREFIX_OPCODE
},
3925 /* PREFIX_0FAE_REG_0_MOD_3 */
3928 { "rdfsbase", { Ev
}, 0 },
3931 /* PREFIX_0FAE_REG_1_MOD_3 */
3934 { "rdgsbase", { Ev
}, 0 },
3937 /* PREFIX_0FAE_REG_2_MOD_3 */
3940 { "wrfsbase", { Ev
}, 0 },
3943 /* PREFIX_0FAE_REG_3_MOD_3 */
3946 { "wrgsbase", { Ev
}, 0 },
3949 /* PREFIX_0FAE_REG_4_MOD_0 */
3951 { "xsave", { FXSAVE
}, 0 },
3952 { "ptwrite%LQ", { Edq
}, 0 },
3955 /* PREFIX_0FAE_REG_4_MOD_3 */
3958 { "ptwrite%LQ", { Edq
}, 0 },
3961 /* PREFIX_0FAE_REG_5_MOD_0 */
3963 { "xrstor", { FXSAVE
}, PREFIX_OPCODE
},
3966 /* PREFIX_0FAE_REG_5_MOD_3 */
3968 { "lfence", { Skip_MODRM
}, 0 },
3969 { "incsspK", { Rdq
}, PREFIX_OPCODE
},
3972 /* PREFIX_0FAE_REG_6_MOD_0 */
3974 { "xsaveopt", { FXSAVE
}, PREFIX_OPCODE
},
3975 { "clrssbsy", { Mq
}, PREFIX_OPCODE
},
3976 { "clwb", { Mb
}, PREFIX_OPCODE
},
3979 /* PREFIX_0FAE_REG_6_MOD_3 */
3981 { RM_TABLE (RM_0FAE_REG_6_MOD_3_P_0
) },
3982 { "umonitor", { Eva
}, PREFIX_OPCODE
},
3983 { "tpause", { Edq
}, PREFIX_OPCODE
},
3984 { "umwait", { Edq
}, PREFIX_OPCODE
},
3987 /* PREFIX_0FAE_REG_7_MOD_0 */
3989 { "clflush", { Mb
}, 0 },
3991 { "clflushopt", { Mb
}, 0 },
3997 { "popcntS", { Gv
, Ev
}, 0 },
4002 { "bsfS", { Gv
, Ev
}, 0 },
4003 { "tzcntS", { Gv
, Ev
}, 0 },
4004 { "bsfS", { Gv
, Ev
}, 0 },
4009 { "bsrS", { Gv
, Ev
}, 0 },
4010 { "lzcntS", { Gv
, Ev
}, 0 },
4011 { "bsrS", { Gv
, Ev
}, 0 },
4016 { "cmpps", { XM
, EXx
, CMP
}, PREFIX_OPCODE
},
4017 { "cmpss", { XM
, EXd
, CMP
}, PREFIX_OPCODE
},
4018 { "cmppd", { XM
, EXx
, CMP
}, PREFIX_OPCODE
},
4019 { "cmpsd", { XM
, EXq
, CMP
}, PREFIX_OPCODE
},
4022 /* PREFIX_0FC3_MOD_0 */
4024 { "movntiS", { Edq
, Gdq
}, PREFIX_OPCODE
},
4027 /* PREFIX_0FC7_REG_6_MOD_0 */
4029 { "vmptrld",{ Mq
}, 0 },
4030 { "vmxon", { Mq
}, 0 },
4031 { "vmclear",{ Mq
}, 0 },
4034 /* PREFIX_0FC7_REG_6_MOD_3 */
4036 { "rdrand", { Ev
}, 0 },
4038 { "rdrand", { Ev
}, 0 }
4041 /* PREFIX_0FC7_REG_7_MOD_3 */
4043 { "rdseed", { Ev
}, 0 },
4044 { "rdpid", { Em
}, 0 },
4045 { "rdseed", { Ev
}, 0 },
4052 { "addsubpd", { XM
, EXx
}, 0 },
4053 { "addsubps", { XM
, EXx
}, 0 },
4059 { "movq2dq",{ XM
, MS
}, 0 },
4060 { "movq", { EXqS
, XM
}, 0 },
4061 { "movdq2q",{ MX
, XS
}, 0 },
4067 { "cvtdq2pd", { XM
, EXq
}, PREFIX_OPCODE
},
4068 { "cvttpd2dq", { XM
, EXx
}, PREFIX_OPCODE
},
4069 { "cvtpd2dq", { XM
, EXx
}, PREFIX_OPCODE
},
4074 { "movntq", { Mq
, MX
}, PREFIX_OPCODE
},
4076 { MOD_TABLE (MOD_0FE7_PREFIX_2
) },
4084 { MOD_TABLE (MOD_0FF0_PREFIX_3
) },
4089 { "maskmovq", { MX
, MS
}, PREFIX_OPCODE
},
4091 { "maskmovdqu", { XM
, XS
}, PREFIX_OPCODE
},
4098 { "pblendvb", { XM
, EXx
, XMM0
}, PREFIX_OPCODE
},
4105 { "blendvps", { XM
, EXx
, XMM0
}, PREFIX_OPCODE
},
4112 { "blendvpd", { XM
, EXx
, XMM0
}, PREFIX_OPCODE
},
4119 { "ptest", { XM
, EXx
}, PREFIX_OPCODE
},
4126 { "pmovsxbw", { XM
, EXq
}, PREFIX_OPCODE
},
4133 { "pmovsxbd", { XM
, EXd
}, PREFIX_OPCODE
},
4140 { "pmovsxbq", { XM
, EXw
}, PREFIX_OPCODE
},
4147 { "pmovsxwd", { XM
, EXq
}, PREFIX_OPCODE
},
4154 { "pmovsxwq", { XM
, EXd
}, PREFIX_OPCODE
},
4161 { "pmovsxdq", { XM
, EXq
}, PREFIX_OPCODE
},
4168 { "pmuldq", { XM
, EXx
}, PREFIX_OPCODE
},
4175 { "pcmpeqq", { XM
, EXx
}, PREFIX_OPCODE
},
4182 { MOD_TABLE (MOD_0F382A_PREFIX_2
) },
4189 { "packusdw", { XM
, EXx
}, PREFIX_OPCODE
},
4196 { "pmovzxbw", { XM
, EXq
}, PREFIX_OPCODE
},
4203 { "pmovzxbd", { XM
, EXd
}, PREFIX_OPCODE
},
4210 { "pmovzxbq", { XM
, EXw
}, PREFIX_OPCODE
},
4217 { "pmovzxwd", { XM
, EXq
}, PREFIX_OPCODE
},
4224 { "pmovzxwq", { XM
, EXd
}, PREFIX_OPCODE
},
4231 { "pmovzxdq", { XM
, EXq
}, PREFIX_OPCODE
},
4238 { "pcmpgtq", { XM
, EXx
}, PREFIX_OPCODE
},
4245 { "pminsb", { XM
, EXx
}, PREFIX_OPCODE
},
4252 { "pminsd", { XM
, EXx
}, PREFIX_OPCODE
},
4259 { "pminuw", { XM
, EXx
}, PREFIX_OPCODE
},
4266 { "pminud", { XM
, EXx
}, PREFIX_OPCODE
},
4273 { "pmaxsb", { XM
, EXx
}, PREFIX_OPCODE
},
4280 { "pmaxsd", { XM
, EXx
}, PREFIX_OPCODE
},
4287 { "pmaxuw", { XM
, EXx
}, PREFIX_OPCODE
},
4294 { "pmaxud", { XM
, EXx
}, PREFIX_OPCODE
},
4301 { "pmulld", { XM
, EXx
}, PREFIX_OPCODE
},
4308 { "phminposuw", { XM
, EXx
}, PREFIX_OPCODE
},
4315 { "invept", { Gm
, Mo
}, PREFIX_OPCODE
},
4322 { "invvpid", { Gm
, Mo
}, PREFIX_OPCODE
},
4329 { "invpcid", { Gm
, M
}, PREFIX_OPCODE
},
4334 { "sha1nexte", { XM
, EXxmm
}, PREFIX_OPCODE
},
4339 { "sha1msg1", { XM
, EXxmm
}, PREFIX_OPCODE
},
4344 { "sha1msg2", { XM
, EXxmm
}, PREFIX_OPCODE
},
4349 { "sha256rnds2", { XM
, EXxmm
, XMM0
}, PREFIX_OPCODE
},
4354 { "sha256msg1", { XM
, EXxmm
}, PREFIX_OPCODE
},
4359 { "sha256msg2", { XM
, EXxmm
}, PREFIX_OPCODE
},
4366 { "gf2p8mulb", { XM
, EXxmm
}, PREFIX_OPCODE
},
4373 { "aesimc", { XM
, EXx
}, PREFIX_OPCODE
},
4380 { "aesenc", { XM
, EXx
}, PREFIX_OPCODE
},
4387 { "aesenclast", { XM
, EXx
}, PREFIX_OPCODE
},
4394 { "aesdec", { XM
, EXx
}, PREFIX_OPCODE
},
4401 { "aesdeclast", { XM
, EXx
}, PREFIX_OPCODE
},
4406 { "movbeS", { Gv
, { MOVBE_Fixup
, v_mode
} }, PREFIX_OPCODE
},
4408 { "movbeS", { Gv
, { MOVBE_Fixup
, v_mode
} }, PREFIX_OPCODE
},
4409 { "crc32", { Gdq
, { CRC32_Fixup
, b_mode
} }, PREFIX_OPCODE
},
4414 { "movbeS", { { MOVBE_Fixup
, v_mode
}, Gv
}, PREFIX_OPCODE
},
4416 { "movbeS", { { MOVBE_Fixup
, v_mode
}, Gv
}, PREFIX_OPCODE
},
4417 { "crc32", { Gdq
, { CRC32_Fixup
, v_mode
} }, PREFIX_OPCODE
},
4424 { MOD_TABLE (MOD_0F38F5_PREFIX_2
) },
4429 { MOD_TABLE (MOD_0F38F6_PREFIX_0
) },
4430 { "adoxS", { Gdq
, Edq
}, PREFIX_OPCODE
},
4431 { "adcxS", { Gdq
, Edq
}, PREFIX_OPCODE
},
4438 { MOD_TABLE (MOD_0F38F8_PREFIX_1
) },
4439 { MOD_TABLE (MOD_0F38F8_PREFIX_2
) },
4440 { MOD_TABLE (MOD_0F38F8_PREFIX_3
) },
4445 { MOD_TABLE (MOD_0F38F9_PREFIX_0
) },
4452 { "roundps", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4459 { "roundpd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4466 { "roundss", { XM
, EXd
, Ib
}, PREFIX_OPCODE
},
4473 { "roundsd", { XM
, EXq
, Ib
}, PREFIX_OPCODE
},
4480 { "blendps", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4487 { "blendpd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4494 { "pblendw", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4501 { "pextrb", { Edqb
, XM
, Ib
}, PREFIX_OPCODE
},
4508 { "pextrw", { Edqw
, XM
, Ib
}, PREFIX_OPCODE
},
4515 { "pextrK", { Edq
, XM
, Ib
}, PREFIX_OPCODE
},
4522 { "extractps", { Edqd
, XM
, Ib
}, PREFIX_OPCODE
},
4529 { "pinsrb", { XM
, Edqb
, Ib
}, PREFIX_OPCODE
},
4536 { "insertps", { XM
, EXd
, Ib
}, PREFIX_OPCODE
},
4543 { "pinsrK", { XM
, Edq
, Ib
}, PREFIX_OPCODE
},
4550 { "dpps", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4557 { "dppd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4564 { "mpsadbw", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4571 { "pclmulqdq", { XM
, EXx
, PCLMUL
}, PREFIX_OPCODE
},
4578 { "pcmpestrm", { XM
, { PCMPESTR_Fixup
, x_mode
}, Ib
}, PREFIX_OPCODE
},
4585 { "pcmpestri", { XM
, { PCMPESTR_Fixup
, x_mode
}, Ib
}, PREFIX_OPCODE
},
4592 { "pcmpistrm", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4599 { "pcmpistri", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4604 { "sha1rnds4", { XM
, EXxmm
, Ib
}, PREFIX_OPCODE
},
4611 { "gf2p8affineqb", { XM
, EXxmm
, Ib
}, PREFIX_OPCODE
},
4618 { "gf2p8affineinvqb", { XM
, EXxmm
, Ib
}, PREFIX_OPCODE
},
4625 { "aeskeygenassist", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4628 /* PREFIX_VEX_0F10 */
4630 { "vmovups", { XM
, EXx
}, 0 },
4631 { "vmovss", { XMVexScalar
, VexScalar
, EXxmm_md
}, 0 },
4632 { "vmovupd", { XM
, EXx
}, 0 },
4633 { "vmovsd", { XMVexScalar
, VexScalar
, EXxmm_mq
}, 0 },
4636 /* PREFIX_VEX_0F11 */
4638 { "vmovups", { EXxS
, XM
}, 0 },
4639 { "vmovss", { EXdVexScalarS
, VexScalar
, XMScalar
}, 0 },
4640 { "vmovupd", { EXxS
, XM
}, 0 },
4641 { "vmovsd", { EXqVexScalarS
, VexScalar
, XMScalar
}, 0 },
4644 /* PREFIX_VEX_0F12 */
4646 { MOD_TABLE (MOD_VEX_0F12_PREFIX_0
) },
4647 { "vmovsldup", { XM
, EXx
}, 0 },
4648 { MOD_TABLE (MOD_VEX_0F12_PREFIX_2
) },
4649 { "vmovddup", { XM
, EXymmq
}, 0 },
4652 /* PREFIX_VEX_0F16 */
4654 { MOD_TABLE (MOD_VEX_0F16_PREFIX_0
) },
4655 { "vmovshdup", { XM
, EXx
}, 0 },
4656 { MOD_TABLE (MOD_VEX_0F16_PREFIX_2
) },
4659 /* PREFIX_VEX_0F2A */
4662 { "vcvtsi2ss%LQ", { XMScalar
, VexScalar
, Edq
}, 0 },
4664 { "vcvtsi2sd%LQ", { XMScalar
, VexScalar
, Edq
}, 0 },
4667 /* PREFIX_VEX_0F2C */
4670 { "vcvttss2si", { Gdq
, EXxmm_md
}, 0 },
4672 { "vcvttsd2si", { Gdq
, EXxmm_mq
}, 0 },
4675 /* PREFIX_VEX_0F2D */
4678 { "vcvtss2si", { Gdq
, EXxmm_md
}, 0 },
4680 { "vcvtsd2si", { Gdq
, EXxmm_mq
}, 0 },
4683 /* PREFIX_VEX_0F2E */
4685 { "vucomiss", { XMScalar
, EXxmm_md
}, 0 },
4687 { "vucomisd", { XMScalar
, EXxmm_mq
}, 0 },
4690 /* PREFIX_VEX_0F2F */
4692 { "vcomiss", { XMScalar
, EXxmm_md
}, 0 },
4694 { "vcomisd", { XMScalar
, EXxmm_mq
}, 0 },
4697 /* PREFIX_VEX_0F41 */
4699 { VEX_LEN_TABLE (VEX_LEN_0F41_P_0
) },
4701 { VEX_LEN_TABLE (VEX_LEN_0F41_P_2
) },
4704 /* PREFIX_VEX_0F42 */
4706 { VEX_LEN_TABLE (VEX_LEN_0F42_P_0
) },
4708 { VEX_LEN_TABLE (VEX_LEN_0F42_P_2
) },
4711 /* PREFIX_VEX_0F44 */
4713 { VEX_LEN_TABLE (VEX_LEN_0F44_P_0
) },
4715 { VEX_LEN_TABLE (VEX_LEN_0F44_P_2
) },
4718 /* PREFIX_VEX_0F45 */
4720 { VEX_LEN_TABLE (VEX_LEN_0F45_P_0
) },
4722 { VEX_LEN_TABLE (VEX_LEN_0F45_P_2
) },
4725 /* PREFIX_VEX_0F46 */
4727 { VEX_LEN_TABLE (VEX_LEN_0F46_P_0
) },
4729 { VEX_LEN_TABLE (VEX_LEN_0F46_P_2
) },
4732 /* PREFIX_VEX_0F47 */
4734 { VEX_LEN_TABLE (VEX_LEN_0F47_P_0
) },
4736 { VEX_LEN_TABLE (VEX_LEN_0F47_P_2
) },
4739 /* PREFIX_VEX_0F4A */
4741 { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0
) },
4743 { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2
) },
4746 /* PREFIX_VEX_0F4B */
4748 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0
) },
4750 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2
) },
4753 /* PREFIX_VEX_0F51 */
4755 { "vsqrtps", { XM
, EXx
}, 0 },
4756 { "vsqrtss", { XMScalar
, VexScalar
, EXxmm_md
}, 0 },
4757 { "vsqrtpd", { XM
, EXx
}, 0 },
4758 { "vsqrtsd", { XMScalar
, VexScalar
, EXxmm_mq
}, 0 },
4761 /* PREFIX_VEX_0F52 */
4763 { "vrsqrtps", { XM
, EXx
}, 0 },
4764 { "vrsqrtss", { XMScalar
, VexScalar
, EXxmm_md
}, 0 },
4767 /* PREFIX_VEX_0F53 */
4769 { "vrcpps", { XM
, EXx
}, 0 },
4770 { "vrcpss", { XMScalar
, VexScalar
, EXxmm_md
}, 0 },
4773 /* PREFIX_VEX_0F58 */
4775 { "vaddps", { XM
, Vex
, EXx
}, 0 },
4776 { "vaddss", { XMScalar
, VexScalar
, EXxmm_md
}, 0 },
4777 { "vaddpd", { XM
, Vex
, EXx
}, 0 },
4778 { "vaddsd", { XMScalar
, VexScalar
, EXxmm_mq
}, 0 },
4781 /* PREFIX_VEX_0F59 */
4783 { "vmulps", { XM
, Vex
, EXx
}, 0 },
4784 { "vmulss", { XMScalar
, VexScalar
, EXxmm_md
}, 0 },
4785 { "vmulpd", { XM
, Vex
, EXx
}, 0 },
4786 { "vmulsd", { XMScalar
, VexScalar
, EXxmm_mq
}, 0 },
4789 /* PREFIX_VEX_0F5A */
4791 { "vcvtps2pd", { XM
, EXxmmq
}, 0 },
4792 { "vcvtss2sd", { XMScalar
, VexScalar
, EXxmm_md
}, 0 },
4793 { "vcvtpd2ps%XY",{ XMM
, EXx
}, 0 },
4794 { "vcvtsd2ss", { XMScalar
, VexScalar
, EXxmm_mq
}, 0 },
4797 /* PREFIX_VEX_0F5B */
4799 { "vcvtdq2ps", { XM
, EXx
}, 0 },
4800 { "vcvttps2dq", { XM
, EXx
}, 0 },
4801 { "vcvtps2dq", { XM
, EXx
}, 0 },
4804 /* PREFIX_VEX_0F5C */
4806 { "vsubps", { XM
, Vex
, EXx
}, 0 },
4807 { "vsubss", { XMScalar
, VexScalar
, EXxmm_md
}, 0 },
4808 { "vsubpd", { XM
, Vex
, EXx
}, 0 },
4809 { "vsubsd", { XMScalar
, VexScalar
, EXxmm_mq
}, 0 },
4812 /* PREFIX_VEX_0F5D */
4814 { "vminps", { XM
, Vex
, EXx
}, 0 },
4815 { "vminss", { XMScalar
, VexScalar
, EXxmm_md
}, 0 },
4816 { "vminpd", { XM
, Vex
, EXx
}, 0 },
4817 { "vminsd", { XMScalar
, VexScalar
, EXxmm_mq
}, 0 },
4820 /* PREFIX_VEX_0F5E */
4822 { "vdivps", { XM
, Vex
, EXx
}, 0 },
4823 { "vdivss", { XMScalar
, VexScalar
, EXxmm_md
}, 0 },
4824 { "vdivpd", { XM
, Vex
, EXx
}, 0 },
4825 { "vdivsd", { XMScalar
, VexScalar
, EXxmm_mq
}, 0 },
4828 /* PREFIX_VEX_0F5F */
4830 { "vmaxps", { XM
, Vex
, EXx
}, 0 },
4831 { "vmaxss", { XMScalar
, VexScalar
, EXxmm_md
}, 0 },
4832 { "vmaxpd", { XM
, Vex
, EXx
}, 0 },
4833 { "vmaxsd", { XMScalar
, VexScalar
, EXxmm_mq
}, 0 },
4836 /* PREFIX_VEX_0F60 */
4840 { "vpunpcklbw", { XM
, Vex
, EXx
}, 0 },
4843 /* PREFIX_VEX_0F61 */
4847 { "vpunpcklwd", { XM
, Vex
, EXx
}, 0 },
4850 /* PREFIX_VEX_0F62 */
4854 { "vpunpckldq", { XM
, Vex
, EXx
}, 0 },
4857 /* PREFIX_VEX_0F63 */
4861 { "vpacksswb", { XM
, Vex
, EXx
}, 0 },
4864 /* PREFIX_VEX_0F64 */
4868 { "vpcmpgtb", { XM
, Vex
, EXx
}, 0 },
4871 /* PREFIX_VEX_0F65 */
4875 { "vpcmpgtw", { XM
, Vex
, EXx
}, 0 },
4878 /* PREFIX_VEX_0F66 */
4882 { "vpcmpgtd", { XM
, Vex
, EXx
}, 0 },
4885 /* PREFIX_VEX_0F67 */
4889 { "vpackuswb", { XM
, Vex
, EXx
}, 0 },
4892 /* PREFIX_VEX_0F68 */
4896 { "vpunpckhbw", { XM
, Vex
, EXx
}, 0 },
4899 /* PREFIX_VEX_0F69 */
4903 { "vpunpckhwd", { XM
, Vex
, EXx
}, 0 },
4906 /* PREFIX_VEX_0F6A */
4910 { "vpunpckhdq", { XM
, Vex
, EXx
}, 0 },
4913 /* PREFIX_VEX_0F6B */
4917 { "vpackssdw", { XM
, Vex
, EXx
}, 0 },
4920 /* PREFIX_VEX_0F6C */
4924 { "vpunpcklqdq", { XM
, Vex
, EXx
}, 0 },
4927 /* PREFIX_VEX_0F6D */
4931 { "vpunpckhqdq", { XM
, Vex
, EXx
}, 0 },
4934 /* PREFIX_VEX_0F6E */
4938 { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2
) },
4941 /* PREFIX_VEX_0F6F */
4944 { "vmovdqu", { XM
, EXx
}, 0 },
4945 { "vmovdqa", { XM
, EXx
}, 0 },
4948 /* PREFIX_VEX_0F70 */
4951 { "vpshufhw", { XM
, EXx
, Ib
}, 0 },
4952 { "vpshufd", { XM
, EXx
, Ib
}, 0 },
4953 { "vpshuflw", { XM
, EXx
, Ib
}, 0 },
4956 /* PREFIX_VEX_0F71_REG_2 */
4960 { "vpsrlw", { Vex
, XS
, Ib
}, 0 },
4963 /* PREFIX_VEX_0F71_REG_4 */
4967 { "vpsraw", { Vex
, XS
, Ib
}, 0 },
4970 /* PREFIX_VEX_0F71_REG_6 */
4974 { "vpsllw", { Vex
, XS
, Ib
}, 0 },
4977 /* PREFIX_VEX_0F72_REG_2 */
4981 { "vpsrld", { Vex
, XS
, Ib
}, 0 },
4984 /* PREFIX_VEX_0F72_REG_4 */
4988 { "vpsrad", { Vex
, XS
, Ib
}, 0 },
4991 /* PREFIX_VEX_0F72_REG_6 */
4995 { "vpslld", { Vex
, XS
, Ib
}, 0 },
4998 /* PREFIX_VEX_0F73_REG_2 */
5002 { "vpsrlq", { Vex
, XS
, Ib
}, 0 },
5005 /* PREFIX_VEX_0F73_REG_3 */
5009 { "vpsrldq", { Vex
, XS
, Ib
}, 0 },
5012 /* PREFIX_VEX_0F73_REG_6 */
5016 { "vpsllq", { Vex
, XS
, Ib
}, 0 },
5019 /* PREFIX_VEX_0F73_REG_7 */
5023 { "vpslldq", { Vex
, XS
, Ib
}, 0 },
5026 /* PREFIX_VEX_0F74 */
5030 { "vpcmpeqb", { XM
, Vex
, EXx
}, 0 },
5033 /* PREFIX_VEX_0F75 */
5037 { "vpcmpeqw", { XM
, Vex
, EXx
}, 0 },
5040 /* PREFIX_VEX_0F76 */
5044 { "vpcmpeqd", { XM
, Vex
, EXx
}, 0 },
5047 /* PREFIX_VEX_0F77 */
5049 { VEX_LEN_TABLE (VEX_LEN_0F77_P_0
) },
5052 /* PREFIX_VEX_0F7C */
5056 { "vhaddpd", { XM
, Vex
, EXx
}, 0 },
5057 { "vhaddps", { XM
, Vex
, EXx
}, 0 },
5060 /* PREFIX_VEX_0F7D */
5064 { "vhsubpd", { XM
, Vex
, EXx
}, 0 },
5065 { "vhsubps", { XM
, Vex
, EXx
}, 0 },
5068 /* PREFIX_VEX_0F7E */
5071 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1
) },
5072 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2
) },
5075 /* PREFIX_VEX_0F7F */
5078 { "vmovdqu", { EXxS
, XM
}, 0 },
5079 { "vmovdqa", { EXxS
, XM
}, 0 },
5082 /* PREFIX_VEX_0F90 */
5084 { VEX_LEN_TABLE (VEX_LEN_0F90_P_0
) },
5086 { VEX_LEN_TABLE (VEX_LEN_0F90_P_2
) },
5089 /* PREFIX_VEX_0F91 */
5091 { VEX_LEN_TABLE (VEX_LEN_0F91_P_0
) },
5093 { VEX_LEN_TABLE (VEX_LEN_0F91_P_2
) },
5096 /* PREFIX_VEX_0F92 */
5098 { VEX_LEN_TABLE (VEX_LEN_0F92_P_0
) },
5100 { VEX_LEN_TABLE (VEX_LEN_0F92_P_2
) },
5101 { VEX_LEN_TABLE (VEX_LEN_0F92_P_3
) },
5104 /* PREFIX_VEX_0F93 */
5106 { VEX_LEN_TABLE (VEX_LEN_0F93_P_0
) },
5108 { VEX_LEN_TABLE (VEX_LEN_0F93_P_2
) },
5109 { VEX_LEN_TABLE (VEX_LEN_0F93_P_3
) },
5112 /* PREFIX_VEX_0F98 */
5114 { VEX_LEN_TABLE (VEX_LEN_0F98_P_0
) },
5116 { VEX_LEN_TABLE (VEX_LEN_0F98_P_2
) },
5119 /* PREFIX_VEX_0F99 */
5121 { VEX_LEN_TABLE (VEX_LEN_0F99_P_0
) },
5123 { VEX_LEN_TABLE (VEX_LEN_0F99_P_2
) },
5126 /* PREFIX_VEX_0FC2 */
5128 { "vcmpps", { XM
, Vex
, EXx
, VCMP
}, 0 },
5129 { "vcmpss", { XMScalar
, VexScalar
, EXxmm_md
, VCMP
}, 0 },
5130 { "vcmppd", { XM
, Vex
, EXx
, VCMP
}, 0 },
5131 { "vcmpsd", { XMScalar
, VexScalar
, EXxmm_mq
, VCMP
}, 0 },
5134 /* PREFIX_VEX_0FC4 */
5138 { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2
) },
5141 /* PREFIX_VEX_0FC5 */
5145 { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2
) },
5148 /* PREFIX_VEX_0FD0 */
5152 { "vaddsubpd", { XM
, Vex
, EXx
}, 0 },
5153 { "vaddsubps", { XM
, Vex
, EXx
}, 0 },
5156 /* PREFIX_VEX_0FD1 */
5160 { "vpsrlw", { XM
, Vex
, EXxmm
}, 0 },
5163 /* PREFIX_VEX_0FD2 */
5167 { "vpsrld", { XM
, Vex
, EXxmm
}, 0 },
5170 /* PREFIX_VEX_0FD3 */
5174 { "vpsrlq", { XM
, Vex
, EXxmm
}, 0 },
5177 /* PREFIX_VEX_0FD4 */
5181 { "vpaddq", { XM
, Vex
, EXx
}, 0 },
5184 /* PREFIX_VEX_0FD5 */
5188 { "vpmullw", { XM
, Vex
, EXx
}, 0 },
5191 /* PREFIX_VEX_0FD6 */
5195 { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2
) },
5198 /* PREFIX_VEX_0FD7 */
5202 { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2
) },
5205 /* PREFIX_VEX_0FD8 */
5209 { "vpsubusb", { XM
, Vex
, EXx
}, 0 },
5212 /* PREFIX_VEX_0FD9 */
5216 { "vpsubusw", { XM
, Vex
, EXx
}, 0 },
5219 /* PREFIX_VEX_0FDA */
5223 { "vpminub", { XM
, Vex
, EXx
}, 0 },
5226 /* PREFIX_VEX_0FDB */
5230 { "vpand", { XM
, Vex
, EXx
}, 0 },
5233 /* PREFIX_VEX_0FDC */
5237 { "vpaddusb", { XM
, Vex
, EXx
}, 0 },
5240 /* PREFIX_VEX_0FDD */
5244 { "vpaddusw", { XM
, Vex
, EXx
}, 0 },
5247 /* PREFIX_VEX_0FDE */
5251 { "vpmaxub", { XM
, Vex
, EXx
}, 0 },
5254 /* PREFIX_VEX_0FDF */
5258 { "vpandn", { XM
, Vex
, EXx
}, 0 },
5261 /* PREFIX_VEX_0FE0 */
5265 { "vpavgb", { XM
, Vex
, EXx
}, 0 },
5268 /* PREFIX_VEX_0FE1 */
5272 { "vpsraw", { XM
, Vex
, EXxmm
}, 0 },
5275 /* PREFIX_VEX_0FE2 */
5279 { "vpsrad", { XM
, Vex
, EXxmm
}, 0 },
5282 /* PREFIX_VEX_0FE3 */
5286 { "vpavgw", { XM
, Vex
, EXx
}, 0 },
5289 /* PREFIX_VEX_0FE4 */
5293 { "vpmulhuw", { XM
, Vex
, EXx
}, 0 },
5296 /* PREFIX_VEX_0FE5 */
5300 { "vpmulhw", { XM
, Vex
, EXx
}, 0 },
5303 /* PREFIX_VEX_0FE6 */
5306 { "vcvtdq2pd", { XM
, EXxmmq
}, 0 },
5307 { "vcvttpd2dq%XY", { XMM
, EXx
}, 0 },
5308 { "vcvtpd2dq%XY", { XMM
, EXx
}, 0 },
5311 /* PREFIX_VEX_0FE7 */
5315 { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2
) },
5318 /* PREFIX_VEX_0FE8 */
5322 { "vpsubsb", { XM
, Vex
, EXx
}, 0 },
5325 /* PREFIX_VEX_0FE9 */
5329 { "vpsubsw", { XM
, Vex
, EXx
}, 0 },
5332 /* PREFIX_VEX_0FEA */
5336 { "vpminsw", { XM
, Vex
, EXx
}, 0 },
5339 /* PREFIX_VEX_0FEB */
5343 { "vpor", { XM
, Vex
, EXx
}, 0 },
5346 /* PREFIX_VEX_0FEC */
5350 { "vpaddsb", { XM
, Vex
, EXx
}, 0 },
5353 /* PREFIX_VEX_0FED */
5357 { "vpaddsw", { XM
, Vex
, EXx
}, 0 },
5360 /* PREFIX_VEX_0FEE */
5364 { "vpmaxsw", { XM
, Vex
, EXx
}, 0 },
5367 /* PREFIX_VEX_0FEF */
5371 { "vpxor", { XM
, Vex
, EXx
}, 0 },
5374 /* PREFIX_VEX_0FF0 */
5379 { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3
) },
5382 /* PREFIX_VEX_0FF1 */
5386 { "vpsllw", { XM
, Vex
, EXxmm
}, 0 },
5389 /* PREFIX_VEX_0FF2 */
5393 { "vpslld", { XM
, Vex
, EXxmm
}, 0 },
5396 /* PREFIX_VEX_0FF3 */
5400 { "vpsllq", { XM
, Vex
, EXxmm
}, 0 },
5403 /* PREFIX_VEX_0FF4 */
5407 { "vpmuludq", { XM
, Vex
, EXx
}, 0 },
5410 /* PREFIX_VEX_0FF5 */
5414 { "vpmaddwd", { XM
, Vex
, EXx
}, 0 },
5417 /* PREFIX_VEX_0FF6 */
5421 { "vpsadbw", { XM
, Vex
, EXx
}, 0 },
5424 /* PREFIX_VEX_0FF7 */
5428 { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2
) },
5431 /* PREFIX_VEX_0FF8 */
5435 { "vpsubb", { XM
, Vex
, EXx
}, 0 },
5438 /* PREFIX_VEX_0FF9 */
5442 { "vpsubw", { XM
, Vex
, EXx
}, 0 },
5445 /* PREFIX_VEX_0FFA */
5449 { "vpsubd", { XM
, Vex
, EXx
}, 0 },
5452 /* PREFIX_VEX_0FFB */
5456 { "vpsubq", { XM
, Vex
, EXx
}, 0 },
5459 /* PREFIX_VEX_0FFC */
5463 { "vpaddb", { XM
, Vex
, EXx
}, 0 },
5466 /* PREFIX_VEX_0FFD */
5470 { "vpaddw", { XM
, Vex
, EXx
}, 0 },
5473 /* PREFIX_VEX_0FFE */
5477 { "vpaddd", { XM
, Vex
, EXx
}, 0 },
5480 /* PREFIX_VEX_0F3800 */
5484 { "vpshufb", { XM
, Vex
, EXx
}, 0 },
5487 /* PREFIX_VEX_0F3801 */
5491 { "vphaddw", { XM
, Vex
, EXx
}, 0 },
5494 /* PREFIX_VEX_0F3802 */
5498 { "vphaddd", { XM
, Vex
, EXx
}, 0 },
5501 /* PREFIX_VEX_0F3803 */
5505 { "vphaddsw", { XM
, Vex
, EXx
}, 0 },
5508 /* PREFIX_VEX_0F3804 */
5512 { "vpmaddubsw", { XM
, Vex
, EXx
}, 0 },
5515 /* PREFIX_VEX_0F3805 */
5519 { "vphsubw", { XM
, Vex
, EXx
}, 0 },
5522 /* PREFIX_VEX_0F3806 */
5526 { "vphsubd", { XM
, Vex
, EXx
}, 0 },
5529 /* PREFIX_VEX_0F3807 */
5533 { "vphsubsw", { XM
, Vex
, EXx
}, 0 },
5536 /* PREFIX_VEX_0F3808 */
5540 { "vpsignb", { XM
, Vex
, EXx
}, 0 },
5543 /* PREFIX_VEX_0F3809 */
5547 { "vpsignw", { XM
, Vex
, EXx
}, 0 },
5550 /* PREFIX_VEX_0F380A */
5554 { "vpsignd", { XM
, Vex
, EXx
}, 0 },
5557 /* PREFIX_VEX_0F380B */
5561 { "vpmulhrsw", { XM
, Vex
, EXx
}, 0 },
5564 /* PREFIX_VEX_0F380C */
5568 { VEX_W_TABLE (VEX_W_0F380C_P_2
) },
5571 /* PREFIX_VEX_0F380D */
5575 { VEX_W_TABLE (VEX_W_0F380D_P_2
) },
5578 /* PREFIX_VEX_0F380E */
5582 { VEX_W_TABLE (VEX_W_0F380E_P_2
) },
5585 /* PREFIX_VEX_0F380F */
5589 { VEX_W_TABLE (VEX_W_0F380F_P_2
) },
5592 /* PREFIX_VEX_0F3813 */
5596 { "vcvtph2ps", { XM
, EXxmmq
}, 0 },
5599 /* PREFIX_VEX_0F3816 */
5603 { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2
) },
5606 /* PREFIX_VEX_0F3817 */
5610 { "vptest", { XM
, EXx
}, 0 },
5613 /* PREFIX_VEX_0F3818 */
5617 { VEX_W_TABLE (VEX_W_0F3818_P_2
) },
5620 /* PREFIX_VEX_0F3819 */
5624 { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2
) },
5627 /* PREFIX_VEX_0F381A */
5631 { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2
) },
5634 /* PREFIX_VEX_0F381C */
5638 { "vpabsb", { XM
, EXx
}, 0 },
5641 /* PREFIX_VEX_0F381D */
5645 { "vpabsw", { XM
, EXx
}, 0 },
5648 /* PREFIX_VEX_0F381E */
5652 { "vpabsd", { XM
, EXx
}, 0 },
5655 /* PREFIX_VEX_0F3820 */
5659 { "vpmovsxbw", { XM
, EXxmmq
}, 0 },
5662 /* PREFIX_VEX_0F3821 */
5666 { "vpmovsxbd", { XM
, EXxmmqd
}, 0 },
5669 /* PREFIX_VEX_0F3822 */
5673 { "vpmovsxbq", { XM
, EXxmmdw
}, 0 },
5676 /* PREFIX_VEX_0F3823 */
5680 { "vpmovsxwd", { XM
, EXxmmq
}, 0 },
5683 /* PREFIX_VEX_0F3824 */
5687 { "vpmovsxwq", { XM
, EXxmmqd
}, 0 },
5690 /* PREFIX_VEX_0F3825 */
5694 { "vpmovsxdq", { XM
, EXxmmq
}, 0 },
5697 /* PREFIX_VEX_0F3828 */
5701 { "vpmuldq", { XM
, Vex
, EXx
}, 0 },
5704 /* PREFIX_VEX_0F3829 */
5708 { "vpcmpeqq", { XM
, Vex
, EXx
}, 0 },
5711 /* PREFIX_VEX_0F382A */
5715 { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2
) },
5718 /* PREFIX_VEX_0F382B */
5722 { "vpackusdw", { XM
, Vex
, EXx
}, 0 },
5725 /* PREFIX_VEX_0F382C */
5729 { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2
) },
5732 /* PREFIX_VEX_0F382D */
5736 { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2
) },
5739 /* PREFIX_VEX_0F382E */
5743 { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2
) },
5746 /* PREFIX_VEX_0F382F */
5750 { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2
) },
5753 /* PREFIX_VEX_0F3830 */
5757 { "vpmovzxbw", { XM
, EXxmmq
}, 0 },
5760 /* PREFIX_VEX_0F3831 */
5764 { "vpmovzxbd", { XM
, EXxmmqd
}, 0 },
5767 /* PREFIX_VEX_0F3832 */
5771 { "vpmovzxbq", { XM
, EXxmmdw
}, 0 },
5774 /* PREFIX_VEX_0F3833 */
5778 { "vpmovzxwd", { XM
, EXxmmq
}, 0 },
5781 /* PREFIX_VEX_0F3834 */
5785 { "vpmovzxwq", { XM
, EXxmmqd
}, 0 },
5788 /* PREFIX_VEX_0F3835 */
5792 { "vpmovzxdq", { XM
, EXxmmq
}, 0 },
5795 /* PREFIX_VEX_0F3836 */
5799 { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2
) },
5802 /* PREFIX_VEX_0F3837 */
5806 { "vpcmpgtq", { XM
, Vex
, EXx
}, 0 },
5809 /* PREFIX_VEX_0F3838 */
5813 { "vpminsb", { XM
, Vex
, EXx
}, 0 },
5816 /* PREFIX_VEX_0F3839 */
5820 { "vpminsd", { XM
, Vex
, EXx
}, 0 },
5823 /* PREFIX_VEX_0F383A */
5827 { "vpminuw", { XM
, Vex
, EXx
}, 0 },
5830 /* PREFIX_VEX_0F383B */
5834 { "vpminud", { XM
, Vex
, EXx
}, 0 },
5837 /* PREFIX_VEX_0F383C */
5841 { "vpmaxsb", { XM
, Vex
, EXx
}, 0 },
5844 /* PREFIX_VEX_0F383D */
5848 { "vpmaxsd", { XM
, Vex
, EXx
}, 0 },
5851 /* PREFIX_VEX_0F383E */
5855 { "vpmaxuw", { XM
, Vex
, EXx
}, 0 },
5858 /* PREFIX_VEX_0F383F */
5862 { "vpmaxud", { XM
, Vex
, EXx
}, 0 },
5865 /* PREFIX_VEX_0F3840 */
5869 { "vpmulld", { XM
, Vex
, EXx
}, 0 },
5872 /* PREFIX_VEX_0F3841 */
5876 { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2
) },
5879 /* PREFIX_VEX_0F3845 */
5883 { "vpsrlv%LW", { XM
, Vex
, EXx
}, 0 },
5886 /* PREFIX_VEX_0F3846 */
5890 { VEX_W_TABLE (VEX_W_0F3846_P_2
) },
5893 /* PREFIX_VEX_0F3847 */
5897 { "vpsllv%LW", { XM
, Vex
, EXx
}, 0 },
5900 /* PREFIX_VEX_0F3858 */
5904 { VEX_W_TABLE (VEX_W_0F3858_P_2
) },
5907 /* PREFIX_VEX_0F3859 */
5911 { VEX_W_TABLE (VEX_W_0F3859_P_2
) },
5914 /* PREFIX_VEX_0F385A */
5918 { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2
) },
5921 /* PREFIX_VEX_0F3878 */
5925 { VEX_W_TABLE (VEX_W_0F3878_P_2
) },
5928 /* PREFIX_VEX_0F3879 */
5932 { VEX_W_TABLE (VEX_W_0F3879_P_2
) },
5935 /* PREFIX_VEX_0F388C */
5939 { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2
) },
5942 /* PREFIX_VEX_0F388E */
5946 { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2
) },
5949 /* PREFIX_VEX_0F3890 */
5953 { "vpgatherd%LW", { XM
, MVexVSIBDWpX
, Vex
}, 0 },
5956 /* PREFIX_VEX_0F3891 */
5960 { "vpgatherq%LW", { XMGatherQ
, MVexVSIBQWpX
, VexGatherQ
}, 0 },
5963 /* PREFIX_VEX_0F3892 */
5967 { "vgatherdp%XW", { XM
, MVexVSIBDWpX
, Vex
}, 0 },
5970 /* PREFIX_VEX_0F3893 */
5974 { "vgatherqp%XW", { XMGatherQ
, MVexVSIBQWpX
, VexGatherQ
}, 0 },
5977 /* PREFIX_VEX_0F3896 */
5981 { "vfmaddsub132p%XW", { XM
, Vex
, EXx
}, 0 },
5984 /* PREFIX_VEX_0F3897 */
5988 { "vfmsubadd132p%XW", { XM
, Vex
, EXx
}, 0 },
5991 /* PREFIX_VEX_0F3898 */
5995 { "vfmadd132p%XW", { XM
, Vex
, EXx
}, 0 },
5998 /* PREFIX_VEX_0F3899 */
6002 { "vfmadd132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6005 /* PREFIX_VEX_0F389A */
6009 { "vfmsub132p%XW", { XM
, Vex
, EXx
}, 0 },
6012 /* PREFIX_VEX_0F389B */
6016 { "vfmsub132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6019 /* PREFIX_VEX_0F389C */
6023 { "vfnmadd132p%XW", { XM
, Vex
, EXx
}, 0 },
6026 /* PREFIX_VEX_0F389D */
6030 { "vfnmadd132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6033 /* PREFIX_VEX_0F389E */
6037 { "vfnmsub132p%XW", { XM
, Vex
, EXx
}, 0 },
6040 /* PREFIX_VEX_0F389F */
6044 { "vfnmsub132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6047 /* PREFIX_VEX_0F38A6 */
6051 { "vfmaddsub213p%XW", { XM
, Vex
, EXx
}, 0 },
6055 /* PREFIX_VEX_0F38A7 */
6059 { "vfmsubadd213p%XW", { XM
, Vex
, EXx
}, 0 },
6062 /* PREFIX_VEX_0F38A8 */
6066 { "vfmadd213p%XW", { XM
, Vex
, EXx
}, 0 },
6069 /* PREFIX_VEX_0F38A9 */
6073 { "vfmadd213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6076 /* PREFIX_VEX_0F38AA */
6080 { "vfmsub213p%XW", { XM
, Vex
, EXx
}, 0 },
6083 /* PREFIX_VEX_0F38AB */
6087 { "vfmsub213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6090 /* PREFIX_VEX_0F38AC */
6094 { "vfnmadd213p%XW", { XM
, Vex
, EXx
}, 0 },
6097 /* PREFIX_VEX_0F38AD */
6101 { "vfnmadd213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6104 /* PREFIX_VEX_0F38AE */
6108 { "vfnmsub213p%XW", { XM
, Vex
, EXx
}, 0 },
6111 /* PREFIX_VEX_0F38AF */
6115 { "vfnmsub213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6118 /* PREFIX_VEX_0F38B6 */
6122 { "vfmaddsub231p%XW", { XM
, Vex
, EXx
}, 0 },
6125 /* PREFIX_VEX_0F38B7 */
6129 { "vfmsubadd231p%XW", { XM
, Vex
, EXx
}, 0 },
6132 /* PREFIX_VEX_0F38B8 */
6136 { "vfmadd231p%XW", { XM
, Vex
, EXx
}, 0 },
6139 /* PREFIX_VEX_0F38B9 */
6143 { "vfmadd231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6146 /* PREFIX_VEX_0F38BA */
6150 { "vfmsub231p%XW", { XM
, Vex
, EXx
}, 0 },
6153 /* PREFIX_VEX_0F38BB */
6157 { "vfmsub231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6160 /* PREFIX_VEX_0F38BC */
6164 { "vfnmadd231p%XW", { XM
, Vex
, EXx
}, 0 },
6167 /* PREFIX_VEX_0F38BD */
6171 { "vfnmadd231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6174 /* PREFIX_VEX_0F38BE */
6178 { "vfnmsub231p%XW", { XM
, Vex
, EXx
}, 0 },
6181 /* PREFIX_VEX_0F38BF */
6185 { "vfnmsub231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6188 /* PREFIX_VEX_0F38CF */
6192 { VEX_W_TABLE (VEX_W_0F38CF_P_2
) },
6195 /* PREFIX_VEX_0F38DB */
6199 { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2
) },
6202 /* PREFIX_VEX_0F38DC */
6206 { "vaesenc", { XM
, Vex
, EXx
}, 0 },
6209 /* PREFIX_VEX_0F38DD */
6213 { "vaesenclast", { XM
, Vex
, EXx
}, 0 },
6216 /* PREFIX_VEX_0F38DE */
6220 { "vaesdec", { XM
, Vex
, EXx
}, 0 },
6223 /* PREFIX_VEX_0F38DF */
6227 { "vaesdeclast", { XM
, Vex
, EXx
}, 0 },
6230 /* PREFIX_VEX_0F38F2 */
6232 { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0
) },
6235 /* PREFIX_VEX_0F38F3_REG_1 */
6237 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0
) },
6240 /* PREFIX_VEX_0F38F3_REG_2 */
6242 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0
) },
6245 /* PREFIX_VEX_0F38F3_REG_3 */
6247 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0
) },
6250 /* PREFIX_VEX_0F38F5 */
6252 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0
) },
6253 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1
) },
6255 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3
) },
6258 /* PREFIX_VEX_0F38F6 */
6263 { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3
) },
6266 /* PREFIX_VEX_0F38F7 */
6268 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0
) },
6269 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1
) },
6270 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2
) },
6271 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3
) },
6274 /* PREFIX_VEX_0F3A00 */
6278 { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2
) },
6281 /* PREFIX_VEX_0F3A01 */
6285 { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2
) },
6288 /* PREFIX_VEX_0F3A02 */
6292 { VEX_W_TABLE (VEX_W_0F3A02_P_2
) },
6295 /* PREFIX_VEX_0F3A04 */
6299 { VEX_W_TABLE (VEX_W_0F3A04_P_2
) },
6302 /* PREFIX_VEX_0F3A05 */
6306 { VEX_W_TABLE (VEX_W_0F3A05_P_2
) },
6309 /* PREFIX_VEX_0F3A06 */
6313 { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2
) },
6316 /* PREFIX_VEX_0F3A08 */
6320 { "vroundps", { XM
, EXx
, Ib
}, 0 },
6323 /* PREFIX_VEX_0F3A09 */
6327 { "vroundpd", { XM
, EXx
, Ib
}, 0 },
6330 /* PREFIX_VEX_0F3A0A */
6334 { "vroundss", { XMScalar
, VexScalar
, EXxmm_md
, Ib
}, 0 },
6337 /* PREFIX_VEX_0F3A0B */
6341 { "vroundsd", { XMScalar
, VexScalar
, EXxmm_mq
, Ib
}, 0 },
6344 /* PREFIX_VEX_0F3A0C */
6348 { "vblendps", { XM
, Vex
, EXx
, Ib
}, 0 },
6351 /* PREFIX_VEX_0F3A0D */
6355 { "vblendpd", { XM
, Vex
, EXx
, Ib
}, 0 },
6358 /* PREFIX_VEX_0F3A0E */
6362 { "vpblendw", { XM
, Vex
, EXx
, Ib
}, 0 },
6365 /* PREFIX_VEX_0F3A0F */
6369 { "vpalignr", { XM
, Vex
, EXx
, Ib
}, 0 },
6372 /* PREFIX_VEX_0F3A14 */
6376 { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2
) },
6379 /* PREFIX_VEX_0F3A15 */
6383 { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2
) },
6386 /* PREFIX_VEX_0F3A16 */
6390 { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2
) },
6393 /* PREFIX_VEX_0F3A17 */
6397 { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2
) },
6400 /* PREFIX_VEX_0F3A18 */
6404 { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2
) },
6407 /* PREFIX_VEX_0F3A19 */
6411 { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2
) },
6414 /* PREFIX_VEX_0F3A1D */
6418 { "vcvtps2ph", { EXxmmq
, XM
, Ib
}, 0 },
6421 /* PREFIX_VEX_0F3A20 */
6425 { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2
) },
6428 /* PREFIX_VEX_0F3A21 */
6432 { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2
) },
6435 /* PREFIX_VEX_0F3A22 */
6439 { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2
) },
6442 /* PREFIX_VEX_0F3A30 */
6446 { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2
) },
6449 /* PREFIX_VEX_0F3A31 */
6453 { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2
) },
6456 /* PREFIX_VEX_0F3A32 */
6460 { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2
) },
6463 /* PREFIX_VEX_0F3A33 */
6467 { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2
) },
6470 /* PREFIX_VEX_0F3A38 */
6474 { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2
) },
6477 /* PREFIX_VEX_0F3A39 */
6481 { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2
) },
6484 /* PREFIX_VEX_0F3A40 */
6488 { "vdpps", { XM
, Vex
, EXx
, Ib
}, 0 },
6491 /* PREFIX_VEX_0F3A41 */
6495 { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2
) },
6498 /* PREFIX_VEX_0F3A42 */
6502 { "vmpsadbw", { XM
, Vex
, EXx
, Ib
}, 0 },
6505 /* PREFIX_VEX_0F3A44 */
6509 { "vpclmulqdq", { XM
, Vex
, EXx
, PCLMUL
}, 0 },
6512 /* PREFIX_VEX_0F3A46 */
6516 { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2
) },
6519 /* PREFIX_VEX_0F3A48 */
6523 { VEX_W_TABLE (VEX_W_0F3A48_P_2
) },
6526 /* PREFIX_VEX_0F3A49 */
6530 { VEX_W_TABLE (VEX_W_0F3A49_P_2
) },
6533 /* PREFIX_VEX_0F3A4A */
6537 { VEX_W_TABLE (VEX_W_0F3A4A_P_2
) },
6540 /* PREFIX_VEX_0F3A4B */
6544 { VEX_W_TABLE (VEX_W_0F3A4B_P_2
) },
6547 /* PREFIX_VEX_0F3A4C */
6551 { VEX_W_TABLE (VEX_W_0F3A4C_P_2
) },
6554 /* PREFIX_VEX_0F3A5C */
6558 { "vfmaddsubps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6561 /* PREFIX_VEX_0F3A5D */
6565 { "vfmaddsubpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6568 /* PREFIX_VEX_0F3A5E */
6572 { "vfmsubaddps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6575 /* PREFIX_VEX_0F3A5F */
6579 { "vfmsubaddpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6582 /* PREFIX_VEX_0F3A60 */
6586 { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2
) },
6590 /* PREFIX_VEX_0F3A61 */
6594 { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2
) },
6597 /* PREFIX_VEX_0F3A62 */
6601 { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2
) },
6604 /* PREFIX_VEX_0F3A63 */
6608 { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2
) },
6611 /* PREFIX_VEX_0F3A68 */
6615 { "vfmaddps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6618 /* PREFIX_VEX_0F3A69 */
6622 { "vfmaddpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6625 /* PREFIX_VEX_0F3A6A */
6629 { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2
) },
6632 /* PREFIX_VEX_0F3A6B */
6636 { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2
) },
6639 /* PREFIX_VEX_0F3A6C */
6643 { "vfmsubps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6646 /* PREFIX_VEX_0F3A6D */
6650 { "vfmsubpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6653 /* PREFIX_VEX_0F3A6E */
6657 { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2
) },
6660 /* PREFIX_VEX_0F3A6F */
6664 { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2
) },
6667 /* PREFIX_VEX_0F3A78 */
6671 { "vfnmaddps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6674 /* PREFIX_VEX_0F3A79 */
6678 { "vfnmaddpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6681 /* PREFIX_VEX_0F3A7A */
6685 { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2
) },
6688 /* PREFIX_VEX_0F3A7B */
6692 { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2
) },
6695 /* PREFIX_VEX_0F3A7C */
6699 { "vfnmsubps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6703 /* PREFIX_VEX_0F3A7D */
6707 { "vfnmsubpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6710 /* PREFIX_VEX_0F3A7E */
6714 { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2
) },
6717 /* PREFIX_VEX_0F3A7F */
6721 { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2
) },
6724 /* PREFIX_VEX_0F3ACE */
6728 { VEX_W_TABLE (VEX_W_0F3ACE_P_2
) },
6731 /* PREFIX_VEX_0F3ACF */
6735 { VEX_W_TABLE (VEX_W_0F3ACF_P_2
) },
6738 /* PREFIX_VEX_0F3ADF */
6742 { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2
) },
6745 /* PREFIX_VEX_0F3AF0 */
6750 { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3
) },
6753 #include "i386-dis-evex-prefix.h"
6756 static const struct dis386 x86_64_table
[][2] = {
6759 { "pushP", { es
}, 0 },
6764 { "popP", { es
}, 0 },
6769 { "pushP", { cs
}, 0 },
6774 { "pushP", { ss
}, 0 },
6779 { "popP", { ss
}, 0 },
6784 { "pushP", { ds
}, 0 },
6789 { "popP", { ds
}, 0 },
6794 { "daa", { XX
}, 0 },
6799 { "das", { XX
}, 0 },
6804 { "aaa", { XX
}, 0 },
6809 { "aas", { XX
}, 0 },
6814 { "pushaP", { XX
}, 0 },
6819 { "popaP", { XX
}, 0 },
6824 { MOD_TABLE (MOD_62_32BIT
) },
6825 { EVEX_TABLE (EVEX_0F
) },
6830 { "arpl", { Ew
, Gw
}, 0 },
6831 { "movs", { { OP_G
, movsxd_mode
}, { MOVSXD_Fixup
, movsxd_mode
} }, 0 },
6836 { "ins{R|}", { Yzr
, indirDX
}, 0 },
6837 { "ins{G|}", { Yzr
, indirDX
}, 0 },
6842 { "outs{R|}", { indirDXr
, Xz
}, 0 },
6843 { "outs{G|}", { indirDXr
, Xz
}, 0 },
6848 /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode. */
6849 { REG_TABLE (REG_80
) },
6854 { "{l|}call{T|}", { Ap
}, 0 },
6859 { "retP", { Iw
, BND
}, 0 },
6860 { "ret@", { Iw
, BND
}, 0 },
6865 { "retP", { BND
}, 0 },
6866 { "ret@", { BND
}, 0 },
6871 { MOD_TABLE (MOD_C4_32BIT
) },
6872 { VEX_C4_TABLE (VEX_0F
) },
6877 { MOD_TABLE (MOD_C5_32BIT
) },
6878 { VEX_C5_TABLE (VEX_0F
) },
6883 { "into", { XX
}, 0 },
6888 { "aam", { Ib
}, 0 },
6893 { "aad", { Ib
}, 0 },
6898 { "callP", { Jv
, BND
}, 0 },
6899 { "call@", { Jv
, BND
}, 0 }
6904 { "jmpP", { Jv
, BND
}, 0 },
6905 { "jmp@", { Jv
, BND
}, 0 }
6910 { "{l|}jmp{T|}", { Ap
}, 0 },
6913 /* X86_64_0F01_REG_0 */
6915 { "sgdt{Q|Q}", { M
}, 0 },
6916 { "sgdt", { M
}, 0 },
6919 /* X86_64_0F01_REG_1 */
6921 { "sidt{Q|Q}", { M
}, 0 },
6922 { "sidt", { M
}, 0 },
6925 /* X86_64_0F01_REG_2 */
6927 { "lgdt{Q|Q}", { M
}, 0 },
6928 { "lgdt", { M
}, 0 },
6931 /* X86_64_0F01_REG_3 */
6933 { "lidt{Q|Q}", { M
}, 0 },
6934 { "lidt", { M
}, 0 },
6938 static const struct dis386 three_byte_table
[][256] = {
6940 /* THREE_BYTE_0F38 */
6943 { "pshufb", { MX
, EM
}, PREFIX_OPCODE
},
6944 { "phaddw", { MX
, EM
}, PREFIX_OPCODE
},
6945 { "phaddd", { MX
, EM
}, PREFIX_OPCODE
},
6946 { "phaddsw", { MX
, EM
}, PREFIX_OPCODE
},
6947 { "pmaddubsw", { MX
, EM
}, PREFIX_OPCODE
},
6948 { "phsubw", { MX
, EM
}, PREFIX_OPCODE
},
6949 { "phsubd", { MX
, EM
}, PREFIX_OPCODE
},
6950 { "phsubsw", { MX
, EM
}, PREFIX_OPCODE
},
6952 { "psignb", { MX
, EM
}, PREFIX_OPCODE
},
6953 { "psignw", { MX
, EM
}, PREFIX_OPCODE
},
6954 { "psignd", { MX
, EM
}, PREFIX_OPCODE
},
6955 { "pmulhrsw", { MX
, EM
}, PREFIX_OPCODE
},
6961 { PREFIX_TABLE (PREFIX_0F3810
) },
6965 { PREFIX_TABLE (PREFIX_0F3814
) },
6966 { PREFIX_TABLE (PREFIX_0F3815
) },
6968 { PREFIX_TABLE (PREFIX_0F3817
) },
6974 { "pabsb", { MX
, EM
}, PREFIX_OPCODE
},
6975 { "pabsw", { MX
, EM
}, PREFIX_OPCODE
},
6976 { "pabsd", { MX
, EM
}, PREFIX_OPCODE
},
6979 { PREFIX_TABLE (PREFIX_0F3820
) },
6980 { PREFIX_TABLE (PREFIX_0F3821
) },
6981 { PREFIX_TABLE (PREFIX_0F3822
) },
6982 { PREFIX_TABLE (PREFIX_0F3823
) },
6983 { PREFIX_TABLE (PREFIX_0F3824
) },
6984 { PREFIX_TABLE (PREFIX_0F3825
) },
6988 { PREFIX_TABLE (PREFIX_0F3828
) },
6989 { PREFIX_TABLE (PREFIX_0F3829
) },
6990 { PREFIX_TABLE (PREFIX_0F382A
) },
6991 { PREFIX_TABLE (PREFIX_0F382B
) },
6997 { PREFIX_TABLE (PREFIX_0F3830
) },
6998 { PREFIX_TABLE (PREFIX_0F3831
) },
6999 { PREFIX_TABLE (PREFIX_0F3832
) },
7000 { PREFIX_TABLE (PREFIX_0F3833
) },
7001 { PREFIX_TABLE (PREFIX_0F3834
) },
7002 { PREFIX_TABLE (PREFIX_0F3835
) },
7004 { PREFIX_TABLE (PREFIX_0F3837
) },
7006 { PREFIX_TABLE (PREFIX_0F3838
) },
7007 { PREFIX_TABLE (PREFIX_0F3839
) },
7008 { PREFIX_TABLE (PREFIX_0F383A
) },
7009 { PREFIX_TABLE (PREFIX_0F383B
) },
7010 { PREFIX_TABLE (PREFIX_0F383C
) },
7011 { PREFIX_TABLE (PREFIX_0F383D
) },
7012 { PREFIX_TABLE (PREFIX_0F383E
) },
7013 { PREFIX_TABLE (PREFIX_0F383F
) },
7015 { PREFIX_TABLE (PREFIX_0F3840
) },
7016 { PREFIX_TABLE (PREFIX_0F3841
) },
7087 { PREFIX_TABLE (PREFIX_0F3880
) },
7088 { PREFIX_TABLE (PREFIX_0F3881
) },
7089 { PREFIX_TABLE (PREFIX_0F3882
) },
7168 { PREFIX_TABLE (PREFIX_0F38C8
) },
7169 { PREFIX_TABLE (PREFIX_0F38C9
) },
7170 { PREFIX_TABLE (PREFIX_0F38CA
) },
7171 { PREFIX_TABLE (PREFIX_0F38CB
) },
7172 { PREFIX_TABLE (PREFIX_0F38CC
) },
7173 { PREFIX_TABLE (PREFIX_0F38CD
) },
7175 { PREFIX_TABLE (PREFIX_0F38CF
) },
7189 { PREFIX_TABLE (PREFIX_0F38DB
) },
7190 { PREFIX_TABLE (PREFIX_0F38DC
) },
7191 { PREFIX_TABLE (PREFIX_0F38DD
) },
7192 { PREFIX_TABLE (PREFIX_0F38DE
) },
7193 { PREFIX_TABLE (PREFIX_0F38DF
) },
7213 { PREFIX_TABLE (PREFIX_0F38F0
) },
7214 { PREFIX_TABLE (PREFIX_0F38F1
) },
7218 { PREFIX_TABLE (PREFIX_0F38F5
) },
7219 { PREFIX_TABLE (PREFIX_0F38F6
) },
7222 { PREFIX_TABLE (PREFIX_0F38F8
) },
7223 { PREFIX_TABLE (PREFIX_0F38F9
) },
7231 /* THREE_BYTE_0F3A */
7243 { PREFIX_TABLE (PREFIX_0F3A08
) },
7244 { PREFIX_TABLE (PREFIX_0F3A09
) },
7245 { PREFIX_TABLE (PREFIX_0F3A0A
) },
7246 { PREFIX_TABLE (PREFIX_0F3A0B
) },
7247 { PREFIX_TABLE (PREFIX_0F3A0C
) },
7248 { PREFIX_TABLE (PREFIX_0F3A0D
) },
7249 { PREFIX_TABLE (PREFIX_0F3A0E
) },
7250 { "palignr", { MX
, EM
, Ib
}, PREFIX_OPCODE
},
7256 { PREFIX_TABLE (PREFIX_0F3A14
) },
7257 { PREFIX_TABLE (PREFIX_0F3A15
) },
7258 { PREFIX_TABLE (PREFIX_0F3A16
) },
7259 { PREFIX_TABLE (PREFIX_0F3A17
) },
7270 { PREFIX_TABLE (PREFIX_0F3A20
) },
7271 { PREFIX_TABLE (PREFIX_0F3A21
) },
7272 { PREFIX_TABLE (PREFIX_0F3A22
) },
7306 { PREFIX_TABLE (PREFIX_0F3A40
) },
7307 { PREFIX_TABLE (PREFIX_0F3A41
) },
7308 { PREFIX_TABLE (PREFIX_0F3A42
) },
7310 { PREFIX_TABLE (PREFIX_0F3A44
) },
7342 { PREFIX_TABLE (PREFIX_0F3A60
) },
7343 { PREFIX_TABLE (PREFIX_0F3A61
) },
7344 { PREFIX_TABLE (PREFIX_0F3A62
) },
7345 { PREFIX_TABLE (PREFIX_0F3A63
) },
7463 { PREFIX_TABLE (PREFIX_0F3ACC
) },
7465 { PREFIX_TABLE (PREFIX_0F3ACE
) },
7466 { PREFIX_TABLE (PREFIX_0F3ACF
) },
7484 { PREFIX_TABLE (PREFIX_0F3ADF
) },
7524 static const struct dis386 xop_table
[][256] = {
7677 { "vpmacssww", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7678 { "vpmacsswd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7679 { "vpmacssdql", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7687 { "vpmacssdd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7688 { "vpmacssdqh", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7695 { "vpmacsww", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7696 { "vpmacswd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7697 { "vpmacsdql", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7705 { "vpmacsdd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7706 { "vpmacsdqh", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7710 { "vpcmov", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7711 { "vpperm", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7714 { "vpmadcsswd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7732 { "vpmadcswd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7744 { "vprotb", { XM
, Vex_2src_1
, Ib
}, 0 },
7745 { "vprotw", { XM
, Vex_2src_1
, Ib
}, 0 },
7746 { "vprotd", { XM
, Vex_2src_1
, Ib
}, 0 },
7747 { "vprotq", { XM
, Vex_2src_1
, Ib
}, 0 },
7757 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC
) },
7758 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD
) },
7759 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE
) },
7760 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF
) },
7793 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC
) },
7794 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED
) },
7795 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE
) },
7796 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF
) },
7820 { REG_TABLE (REG_XOP_TBM_01
) },
7821 { REG_TABLE (REG_XOP_TBM_02
) },
7839 { REG_TABLE (REG_XOP_LWPCB
) },
7963 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80
) },
7964 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81
) },
7965 { "vfrczss", { XM
, EXd
}, 0 },
7966 { "vfrczsd", { XM
, EXq
}, 0 },
7981 { "vprotb", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
7982 { "vprotw", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
7983 { "vprotd", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
7984 { "vprotq", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
7985 { "vpshlb", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
7986 { "vpshlw", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
7987 { "vpshld", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
7988 { "vpshlq", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
7990 { "vpshab", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
7991 { "vpshaw", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
7992 { "vpshad", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
7993 { "vpshaq", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8036 { "vphaddbw", { XM
, EXxmm
}, 0 },
8037 { "vphaddbd", { XM
, EXxmm
}, 0 },
8038 { "vphaddbq", { XM
, EXxmm
}, 0 },
8041 { "vphaddwd", { XM
, EXxmm
}, 0 },
8042 { "vphaddwq", { XM
, EXxmm
}, 0 },
8047 { "vphadddq", { XM
, EXxmm
}, 0 },
8054 { "vphaddubw", { XM
, EXxmm
}, 0 },
8055 { "vphaddubd", { XM
, EXxmm
}, 0 },
8056 { "vphaddubq", { XM
, EXxmm
}, 0 },
8059 { "vphadduwd", { XM
, EXxmm
}, 0 },
8060 { "vphadduwq", { XM
, EXxmm
}, 0 },
8065 { "vphaddudq", { XM
, EXxmm
}, 0 },
8072 { "vphsubbw", { XM
, EXxmm
}, 0 },
8073 { "vphsubwd", { XM
, EXxmm
}, 0 },
8074 { "vphsubdq", { XM
, EXxmm
}, 0 },
8128 { "bextrS", { Gdq
, Edq
, Id
}, 0 },
8130 { REG_TABLE (REG_XOP_LWP
) },
8400 static const struct dis386 vex_table
[][256] = {
8422 { PREFIX_TABLE (PREFIX_VEX_0F10
) },
8423 { PREFIX_TABLE (PREFIX_VEX_0F11
) },
8424 { PREFIX_TABLE (PREFIX_VEX_0F12
) },
8425 { MOD_TABLE (MOD_VEX_0F13
) },
8426 { "vunpcklpX", { XM
, Vex
, EXx
}, PREFIX_OPCODE
},
8427 { "vunpckhpX", { XM
, Vex
, EXx
}, PREFIX_OPCODE
},
8428 { PREFIX_TABLE (PREFIX_VEX_0F16
) },
8429 { MOD_TABLE (MOD_VEX_0F17
) },
8449 { "vmovapX", { XM
, EXx
}, PREFIX_OPCODE
},
8450 { "vmovapX", { EXxS
, XM
}, PREFIX_OPCODE
},
8451 { PREFIX_TABLE (PREFIX_VEX_0F2A
) },
8452 { MOD_TABLE (MOD_VEX_0F2B
) },
8453 { PREFIX_TABLE (PREFIX_VEX_0F2C
) },
8454 { PREFIX_TABLE (PREFIX_VEX_0F2D
) },
8455 { PREFIX_TABLE (PREFIX_VEX_0F2E
) },
8456 { PREFIX_TABLE (PREFIX_VEX_0F2F
) },
8477 { PREFIX_TABLE (PREFIX_VEX_0F41
) },
8478 { PREFIX_TABLE (PREFIX_VEX_0F42
) },
8480 { PREFIX_TABLE (PREFIX_VEX_0F44
) },
8481 { PREFIX_TABLE (PREFIX_VEX_0F45
) },
8482 { PREFIX_TABLE (PREFIX_VEX_0F46
) },
8483 { PREFIX_TABLE (PREFIX_VEX_0F47
) },
8487 { PREFIX_TABLE (PREFIX_VEX_0F4A
) },
8488 { PREFIX_TABLE (PREFIX_VEX_0F4B
) },
8494 { MOD_TABLE (MOD_VEX_0F50
) },
8495 { PREFIX_TABLE (PREFIX_VEX_0F51
) },
8496 { PREFIX_TABLE (PREFIX_VEX_0F52
) },
8497 { PREFIX_TABLE (PREFIX_VEX_0F53
) },
8498 { "vandpX", { XM
, Vex
, EXx
}, PREFIX_OPCODE
},
8499 { "vandnpX", { XM
, Vex
, EXx
}, PREFIX_OPCODE
},
8500 { "vorpX", { XM
, Vex
, EXx
}, PREFIX_OPCODE
},
8501 { "vxorpX", { XM
, Vex
, EXx
}, PREFIX_OPCODE
},
8503 { PREFIX_TABLE (PREFIX_VEX_0F58
) },
8504 { PREFIX_TABLE (PREFIX_VEX_0F59
) },
8505 { PREFIX_TABLE (PREFIX_VEX_0F5A
) },
8506 { PREFIX_TABLE (PREFIX_VEX_0F5B
) },
8507 { PREFIX_TABLE (PREFIX_VEX_0F5C
) },
8508 { PREFIX_TABLE (PREFIX_VEX_0F5D
) },
8509 { PREFIX_TABLE (PREFIX_VEX_0F5E
) },
8510 { PREFIX_TABLE (PREFIX_VEX_0F5F
) },
8512 { PREFIX_TABLE (PREFIX_VEX_0F60
) },
8513 { PREFIX_TABLE (PREFIX_VEX_0F61
) },
8514 { PREFIX_TABLE (PREFIX_VEX_0F62
) },
8515 { PREFIX_TABLE (PREFIX_VEX_0F63
) },
8516 { PREFIX_TABLE (PREFIX_VEX_0F64
) },
8517 { PREFIX_TABLE (PREFIX_VEX_0F65
) },
8518 { PREFIX_TABLE (PREFIX_VEX_0F66
) },
8519 { PREFIX_TABLE (PREFIX_VEX_0F67
) },
8521 { PREFIX_TABLE (PREFIX_VEX_0F68
) },
8522 { PREFIX_TABLE (PREFIX_VEX_0F69
) },
8523 { PREFIX_TABLE (PREFIX_VEX_0F6A
) },
8524 { PREFIX_TABLE (PREFIX_VEX_0F6B
) },
8525 { PREFIX_TABLE (PREFIX_VEX_0F6C
) },
8526 { PREFIX_TABLE (PREFIX_VEX_0F6D
) },
8527 { PREFIX_TABLE (PREFIX_VEX_0F6E
) },
8528 { PREFIX_TABLE (PREFIX_VEX_0F6F
) },
8530 { PREFIX_TABLE (PREFIX_VEX_0F70
) },
8531 { REG_TABLE (REG_VEX_0F71
) },
8532 { REG_TABLE (REG_VEX_0F72
) },
8533 { REG_TABLE (REG_VEX_0F73
) },
8534 { PREFIX_TABLE (PREFIX_VEX_0F74
) },
8535 { PREFIX_TABLE (PREFIX_VEX_0F75
) },
8536 { PREFIX_TABLE (PREFIX_VEX_0F76
) },
8537 { PREFIX_TABLE (PREFIX_VEX_0F77
) },
8543 { PREFIX_TABLE (PREFIX_VEX_0F7C
) },
8544 { PREFIX_TABLE (PREFIX_VEX_0F7D
) },
8545 { PREFIX_TABLE (PREFIX_VEX_0F7E
) },
8546 { PREFIX_TABLE (PREFIX_VEX_0F7F
) },
8566 { PREFIX_TABLE (PREFIX_VEX_0F90
) },
8567 { PREFIX_TABLE (PREFIX_VEX_0F91
) },
8568 { PREFIX_TABLE (PREFIX_VEX_0F92
) },
8569 { PREFIX_TABLE (PREFIX_VEX_0F93
) },
8575 { PREFIX_TABLE (PREFIX_VEX_0F98
) },
8576 { PREFIX_TABLE (PREFIX_VEX_0F99
) },
8599 { REG_TABLE (REG_VEX_0FAE
) },
8622 { PREFIX_TABLE (PREFIX_VEX_0FC2
) },
8624 { PREFIX_TABLE (PREFIX_VEX_0FC4
) },
8625 { PREFIX_TABLE (PREFIX_VEX_0FC5
) },
8626 { "vshufpX", { XM
, Vex
, EXx
, Ib
}, PREFIX_OPCODE
},
8638 { PREFIX_TABLE (PREFIX_VEX_0FD0
) },
8639 { PREFIX_TABLE (PREFIX_VEX_0FD1
) },
8640 { PREFIX_TABLE (PREFIX_VEX_0FD2
) },
8641 { PREFIX_TABLE (PREFIX_VEX_0FD3
) },
8642 { PREFIX_TABLE (PREFIX_VEX_0FD4
) },
8643 { PREFIX_TABLE (PREFIX_VEX_0FD5
) },
8644 { PREFIX_TABLE (PREFIX_VEX_0FD6
) },
8645 { PREFIX_TABLE (PREFIX_VEX_0FD7
) },
8647 { PREFIX_TABLE (PREFIX_VEX_0FD8
) },
8648 { PREFIX_TABLE (PREFIX_VEX_0FD9
) },
8649 { PREFIX_TABLE (PREFIX_VEX_0FDA
) },
8650 { PREFIX_TABLE (PREFIX_VEX_0FDB
) },
8651 { PREFIX_TABLE (PREFIX_VEX_0FDC
) },
8652 { PREFIX_TABLE (PREFIX_VEX_0FDD
) },
8653 { PREFIX_TABLE (PREFIX_VEX_0FDE
) },
8654 { PREFIX_TABLE (PREFIX_VEX_0FDF
) },
8656 { PREFIX_TABLE (PREFIX_VEX_0FE0
) },
8657 { PREFIX_TABLE (PREFIX_VEX_0FE1
) },
8658 { PREFIX_TABLE (PREFIX_VEX_0FE2
) },
8659 { PREFIX_TABLE (PREFIX_VEX_0FE3
) },
8660 { PREFIX_TABLE (PREFIX_VEX_0FE4
) },
8661 { PREFIX_TABLE (PREFIX_VEX_0FE5
) },
8662 { PREFIX_TABLE (PREFIX_VEX_0FE6
) },
8663 { PREFIX_TABLE (PREFIX_VEX_0FE7
) },
8665 { PREFIX_TABLE (PREFIX_VEX_0FE8
) },
8666 { PREFIX_TABLE (PREFIX_VEX_0FE9
) },
8667 { PREFIX_TABLE (PREFIX_VEX_0FEA
) },
8668 { PREFIX_TABLE (PREFIX_VEX_0FEB
) },
8669 { PREFIX_TABLE (PREFIX_VEX_0FEC
) },
8670 { PREFIX_TABLE (PREFIX_VEX_0FED
) },
8671 { PREFIX_TABLE (PREFIX_VEX_0FEE
) },
8672 { PREFIX_TABLE (PREFIX_VEX_0FEF
) },
8674 { PREFIX_TABLE (PREFIX_VEX_0FF0
) },
8675 { PREFIX_TABLE (PREFIX_VEX_0FF1
) },
8676 { PREFIX_TABLE (PREFIX_VEX_0FF2
) },
8677 { PREFIX_TABLE (PREFIX_VEX_0FF3
) },
8678 { PREFIX_TABLE (PREFIX_VEX_0FF4
) },
8679 { PREFIX_TABLE (PREFIX_VEX_0FF5
) },
8680 { PREFIX_TABLE (PREFIX_VEX_0FF6
) },
8681 { PREFIX_TABLE (PREFIX_VEX_0FF7
) },
8683 { PREFIX_TABLE (PREFIX_VEX_0FF8
) },
8684 { PREFIX_TABLE (PREFIX_VEX_0FF9
) },
8685 { PREFIX_TABLE (PREFIX_VEX_0FFA
) },
8686 { PREFIX_TABLE (PREFIX_VEX_0FFB
) },
8687 { PREFIX_TABLE (PREFIX_VEX_0FFC
) },
8688 { PREFIX_TABLE (PREFIX_VEX_0FFD
) },
8689 { PREFIX_TABLE (PREFIX_VEX_0FFE
) },
8695 { PREFIX_TABLE (PREFIX_VEX_0F3800
) },
8696 { PREFIX_TABLE (PREFIX_VEX_0F3801
) },
8697 { PREFIX_TABLE (PREFIX_VEX_0F3802
) },
8698 { PREFIX_TABLE (PREFIX_VEX_0F3803
) },
8699 { PREFIX_TABLE (PREFIX_VEX_0F3804
) },
8700 { PREFIX_TABLE (PREFIX_VEX_0F3805
) },
8701 { PREFIX_TABLE (PREFIX_VEX_0F3806
) },
8702 { PREFIX_TABLE (PREFIX_VEX_0F3807
) },
8704 { PREFIX_TABLE (PREFIX_VEX_0F3808
) },
8705 { PREFIX_TABLE (PREFIX_VEX_0F3809
) },
8706 { PREFIX_TABLE (PREFIX_VEX_0F380A
) },
8707 { PREFIX_TABLE (PREFIX_VEX_0F380B
) },
8708 { PREFIX_TABLE (PREFIX_VEX_0F380C
) },
8709 { PREFIX_TABLE (PREFIX_VEX_0F380D
) },
8710 { PREFIX_TABLE (PREFIX_VEX_0F380E
) },
8711 { PREFIX_TABLE (PREFIX_VEX_0F380F
) },
8716 { PREFIX_TABLE (PREFIX_VEX_0F3813
) },
8719 { PREFIX_TABLE (PREFIX_VEX_0F3816
) },
8720 { PREFIX_TABLE (PREFIX_VEX_0F3817
) },
8722 { PREFIX_TABLE (PREFIX_VEX_0F3818
) },
8723 { PREFIX_TABLE (PREFIX_VEX_0F3819
) },
8724 { PREFIX_TABLE (PREFIX_VEX_0F381A
) },
8726 { PREFIX_TABLE (PREFIX_VEX_0F381C
) },
8727 { PREFIX_TABLE (PREFIX_VEX_0F381D
) },
8728 { PREFIX_TABLE (PREFIX_VEX_0F381E
) },
8731 { PREFIX_TABLE (PREFIX_VEX_0F3820
) },
8732 { PREFIX_TABLE (PREFIX_VEX_0F3821
) },
8733 { PREFIX_TABLE (PREFIX_VEX_0F3822
) },
8734 { PREFIX_TABLE (PREFIX_VEX_0F3823
) },
8735 { PREFIX_TABLE (PREFIX_VEX_0F3824
) },
8736 { PREFIX_TABLE (PREFIX_VEX_0F3825
) },
8740 { PREFIX_TABLE (PREFIX_VEX_0F3828
) },
8741 { PREFIX_TABLE (PREFIX_VEX_0F3829
) },
8742 { PREFIX_TABLE (PREFIX_VEX_0F382A
) },
8743 { PREFIX_TABLE (PREFIX_VEX_0F382B
) },
8744 { PREFIX_TABLE (PREFIX_VEX_0F382C
) },
8745 { PREFIX_TABLE (PREFIX_VEX_0F382D
) },
8746 { PREFIX_TABLE (PREFIX_VEX_0F382E
) },
8747 { PREFIX_TABLE (PREFIX_VEX_0F382F
) },
8749 { PREFIX_TABLE (PREFIX_VEX_0F3830
) },
8750 { PREFIX_TABLE (PREFIX_VEX_0F3831
) },
8751 { PREFIX_TABLE (PREFIX_VEX_0F3832
) },
8752 { PREFIX_TABLE (PREFIX_VEX_0F3833
) },
8753 { PREFIX_TABLE (PREFIX_VEX_0F3834
) },
8754 { PREFIX_TABLE (PREFIX_VEX_0F3835
) },
8755 { PREFIX_TABLE (PREFIX_VEX_0F3836
) },
8756 { PREFIX_TABLE (PREFIX_VEX_0F3837
) },
8758 { PREFIX_TABLE (PREFIX_VEX_0F3838
) },
8759 { PREFIX_TABLE (PREFIX_VEX_0F3839
) },
8760 { PREFIX_TABLE (PREFIX_VEX_0F383A
) },
8761 { PREFIX_TABLE (PREFIX_VEX_0F383B
) },
8762 { PREFIX_TABLE (PREFIX_VEX_0F383C
) },
8763 { PREFIX_TABLE (PREFIX_VEX_0F383D
) },
8764 { PREFIX_TABLE (PREFIX_VEX_0F383E
) },
8765 { PREFIX_TABLE (PREFIX_VEX_0F383F
) },
8767 { PREFIX_TABLE (PREFIX_VEX_0F3840
) },
8768 { PREFIX_TABLE (PREFIX_VEX_0F3841
) },
8772 { PREFIX_TABLE (PREFIX_VEX_0F3845
) },
8773 { PREFIX_TABLE (PREFIX_VEX_0F3846
) },
8774 { PREFIX_TABLE (PREFIX_VEX_0F3847
) },
8794 { PREFIX_TABLE (PREFIX_VEX_0F3858
) },
8795 { PREFIX_TABLE (PREFIX_VEX_0F3859
) },
8796 { PREFIX_TABLE (PREFIX_VEX_0F385A
) },
8830 { PREFIX_TABLE (PREFIX_VEX_0F3878
) },
8831 { PREFIX_TABLE (PREFIX_VEX_0F3879
) },
8852 { PREFIX_TABLE (PREFIX_VEX_0F388C
) },
8854 { PREFIX_TABLE (PREFIX_VEX_0F388E
) },
8857 { PREFIX_TABLE (PREFIX_VEX_0F3890
) },
8858 { PREFIX_TABLE (PREFIX_VEX_0F3891
) },
8859 { PREFIX_TABLE (PREFIX_VEX_0F3892
) },
8860 { PREFIX_TABLE (PREFIX_VEX_0F3893
) },
8863 { PREFIX_TABLE (PREFIX_VEX_0F3896
) },
8864 { PREFIX_TABLE (PREFIX_VEX_0F3897
) },
8866 { PREFIX_TABLE (PREFIX_VEX_0F3898
) },
8867 { PREFIX_TABLE (PREFIX_VEX_0F3899
) },
8868 { PREFIX_TABLE (PREFIX_VEX_0F389A
) },
8869 { PREFIX_TABLE (PREFIX_VEX_0F389B
) },
8870 { PREFIX_TABLE (PREFIX_VEX_0F389C
) },
8871 { PREFIX_TABLE (PREFIX_VEX_0F389D
) },
8872 { PREFIX_TABLE (PREFIX_VEX_0F389E
) },
8873 { PREFIX_TABLE (PREFIX_VEX_0F389F
) },
8881 { PREFIX_TABLE (PREFIX_VEX_0F38A6
) },
8882 { PREFIX_TABLE (PREFIX_VEX_0F38A7
) },
8884 { PREFIX_TABLE (PREFIX_VEX_0F38A8
) },
8885 { PREFIX_TABLE (PREFIX_VEX_0F38A9
) },
8886 { PREFIX_TABLE (PREFIX_VEX_0F38AA
) },
8887 { PREFIX_TABLE (PREFIX_VEX_0F38AB
) },
8888 { PREFIX_TABLE (PREFIX_VEX_0F38AC
) },
8889 { PREFIX_TABLE (PREFIX_VEX_0F38AD
) },
8890 { PREFIX_TABLE (PREFIX_VEX_0F38AE
) },
8891 { PREFIX_TABLE (PREFIX_VEX_0F38AF
) },
8899 { PREFIX_TABLE (PREFIX_VEX_0F38B6
) },
8900 { PREFIX_TABLE (PREFIX_VEX_0F38B7
) },
8902 { PREFIX_TABLE (PREFIX_VEX_0F38B8
) },
8903 { PREFIX_TABLE (PREFIX_VEX_0F38B9
) },
8904 { PREFIX_TABLE (PREFIX_VEX_0F38BA
) },
8905 { PREFIX_TABLE (PREFIX_VEX_0F38BB
) },
8906 { PREFIX_TABLE (PREFIX_VEX_0F38BC
) },
8907 { PREFIX_TABLE (PREFIX_VEX_0F38BD
) },
8908 { PREFIX_TABLE (PREFIX_VEX_0F38BE
) },
8909 { PREFIX_TABLE (PREFIX_VEX_0F38BF
) },
8927 { PREFIX_TABLE (PREFIX_VEX_0F38CF
) },
8941 { PREFIX_TABLE (PREFIX_VEX_0F38DB
) },
8942 { PREFIX_TABLE (PREFIX_VEX_0F38DC
) },
8943 { PREFIX_TABLE (PREFIX_VEX_0F38DD
) },
8944 { PREFIX_TABLE (PREFIX_VEX_0F38DE
) },
8945 { PREFIX_TABLE (PREFIX_VEX_0F38DF
) },
8967 { PREFIX_TABLE (PREFIX_VEX_0F38F2
) },
8968 { REG_TABLE (REG_VEX_0F38F3
) },
8970 { PREFIX_TABLE (PREFIX_VEX_0F38F5
) },
8971 { PREFIX_TABLE (PREFIX_VEX_0F38F6
) },
8972 { PREFIX_TABLE (PREFIX_VEX_0F38F7
) },
8986 { PREFIX_TABLE (PREFIX_VEX_0F3A00
) },
8987 { PREFIX_TABLE (PREFIX_VEX_0F3A01
) },
8988 { PREFIX_TABLE (PREFIX_VEX_0F3A02
) },
8990 { PREFIX_TABLE (PREFIX_VEX_0F3A04
) },
8991 { PREFIX_TABLE (PREFIX_VEX_0F3A05
) },
8992 { PREFIX_TABLE (PREFIX_VEX_0F3A06
) },
8995 { PREFIX_TABLE (PREFIX_VEX_0F3A08
) },
8996 { PREFIX_TABLE (PREFIX_VEX_0F3A09
) },
8997 { PREFIX_TABLE (PREFIX_VEX_0F3A0A
) },
8998 { PREFIX_TABLE (PREFIX_VEX_0F3A0B
) },
8999 { PREFIX_TABLE (PREFIX_VEX_0F3A0C
) },
9000 { PREFIX_TABLE (PREFIX_VEX_0F3A0D
) },
9001 { PREFIX_TABLE (PREFIX_VEX_0F3A0E
) },
9002 { PREFIX_TABLE (PREFIX_VEX_0F3A0F
) },
9008 { PREFIX_TABLE (PREFIX_VEX_0F3A14
) },
9009 { PREFIX_TABLE (PREFIX_VEX_0F3A15
) },
9010 { PREFIX_TABLE (PREFIX_VEX_0F3A16
) },
9011 { PREFIX_TABLE (PREFIX_VEX_0F3A17
) },
9013 { PREFIX_TABLE (PREFIX_VEX_0F3A18
) },
9014 { PREFIX_TABLE (PREFIX_VEX_0F3A19
) },
9018 { PREFIX_TABLE (PREFIX_VEX_0F3A1D
) },
9022 { PREFIX_TABLE (PREFIX_VEX_0F3A20
) },
9023 { PREFIX_TABLE (PREFIX_VEX_0F3A21
) },
9024 { PREFIX_TABLE (PREFIX_VEX_0F3A22
) },
9040 { PREFIX_TABLE (PREFIX_VEX_0F3A30
) },
9041 { PREFIX_TABLE (PREFIX_VEX_0F3A31
) },
9042 { PREFIX_TABLE (PREFIX_VEX_0F3A32
) },
9043 { PREFIX_TABLE (PREFIX_VEX_0F3A33
) },
9049 { PREFIX_TABLE (PREFIX_VEX_0F3A38
) },
9050 { PREFIX_TABLE (PREFIX_VEX_0F3A39
) },
9058 { PREFIX_TABLE (PREFIX_VEX_0F3A40
) },
9059 { PREFIX_TABLE (PREFIX_VEX_0F3A41
) },
9060 { PREFIX_TABLE (PREFIX_VEX_0F3A42
) },
9062 { PREFIX_TABLE (PREFIX_VEX_0F3A44
) },
9064 { PREFIX_TABLE (PREFIX_VEX_0F3A46
) },
9067 { PREFIX_TABLE (PREFIX_VEX_0F3A48
) },
9068 { PREFIX_TABLE (PREFIX_VEX_0F3A49
) },
9069 { PREFIX_TABLE (PREFIX_VEX_0F3A4A
) },
9070 { PREFIX_TABLE (PREFIX_VEX_0F3A4B
) },
9071 { PREFIX_TABLE (PREFIX_VEX_0F3A4C
) },
9089 { PREFIX_TABLE (PREFIX_VEX_0F3A5C
) },
9090 { PREFIX_TABLE (PREFIX_VEX_0F3A5D
) },
9091 { PREFIX_TABLE (PREFIX_VEX_0F3A5E
) },
9092 { PREFIX_TABLE (PREFIX_VEX_0F3A5F
) },
9094 { PREFIX_TABLE (PREFIX_VEX_0F3A60
) },
9095 { PREFIX_TABLE (PREFIX_VEX_0F3A61
) },
9096 { PREFIX_TABLE (PREFIX_VEX_0F3A62
) },
9097 { PREFIX_TABLE (PREFIX_VEX_0F3A63
) },
9103 { PREFIX_TABLE (PREFIX_VEX_0F3A68
) },
9104 { PREFIX_TABLE (PREFIX_VEX_0F3A69
) },
9105 { PREFIX_TABLE (PREFIX_VEX_0F3A6A
) },
9106 { PREFIX_TABLE (PREFIX_VEX_0F3A6B
) },
9107 { PREFIX_TABLE (PREFIX_VEX_0F3A6C
) },
9108 { PREFIX_TABLE (PREFIX_VEX_0F3A6D
) },
9109 { PREFIX_TABLE (PREFIX_VEX_0F3A6E
) },
9110 { PREFIX_TABLE (PREFIX_VEX_0F3A6F
) },
9121 { PREFIX_TABLE (PREFIX_VEX_0F3A78
) },
9122 { PREFIX_TABLE (PREFIX_VEX_0F3A79
) },
9123 { PREFIX_TABLE (PREFIX_VEX_0F3A7A
) },
9124 { PREFIX_TABLE (PREFIX_VEX_0F3A7B
) },
9125 { PREFIX_TABLE (PREFIX_VEX_0F3A7C
) },
9126 { PREFIX_TABLE (PREFIX_VEX_0F3A7D
) },
9127 { PREFIX_TABLE (PREFIX_VEX_0F3A7E
) },
9128 { PREFIX_TABLE (PREFIX_VEX_0F3A7F
) },
9217 { PREFIX_TABLE(PREFIX_VEX_0F3ACE
) },
9218 { PREFIX_TABLE(PREFIX_VEX_0F3ACF
) },
9236 { PREFIX_TABLE (PREFIX_VEX_0F3ADF
) },
9256 { PREFIX_TABLE (PREFIX_VEX_0F3AF0
) },
9276 #include "i386-dis-evex.h"
9278 static const struct dis386 vex_len_table
[][2] = {
9279 /* VEX_LEN_0F12_P_0_M_0 / VEX_LEN_0F12_P_2_M_0 */
9281 { "vmovlpX", { XM
, Vex128
, EXq
}, 0 },
9284 /* VEX_LEN_0F12_P_0_M_1 */
9286 { "vmovhlps", { XM
, Vex128
, EXq
}, 0 },
9289 /* VEX_LEN_0F13_M_0 */
9291 { "vmovlpX", { EXq
, XM
}, PREFIX_OPCODE
},
9294 /* VEX_LEN_0F16_P_0_M_0 / VEX_LEN_0F16_P_2_M_0 */
9296 { "vmovhpX", { XM
, Vex128
, EXq
}, 0 },
9299 /* VEX_LEN_0F16_P_0_M_1 */
9301 { "vmovlhps", { XM
, Vex128
, EXq
}, 0 },
9304 /* VEX_LEN_0F17_M_0 */
9306 { "vmovhpX", { EXq
, XM
}, PREFIX_OPCODE
},
9309 /* VEX_LEN_0F41_P_0 */
9312 { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1
) },
9314 /* VEX_LEN_0F41_P_2 */
9317 { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1
) },
9319 /* VEX_LEN_0F42_P_0 */
9322 { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1
) },
9324 /* VEX_LEN_0F42_P_2 */
9327 { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1
) },
9329 /* VEX_LEN_0F44_P_0 */
9331 { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0
) },
9333 /* VEX_LEN_0F44_P_2 */
9335 { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0
) },
9337 /* VEX_LEN_0F45_P_0 */
9340 { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1
) },
9342 /* VEX_LEN_0F45_P_2 */
9345 { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1
) },
9347 /* VEX_LEN_0F46_P_0 */
9350 { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1
) },
9352 /* VEX_LEN_0F46_P_2 */
9355 { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1
) },
9357 /* VEX_LEN_0F47_P_0 */
9360 { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1
) },
9362 /* VEX_LEN_0F47_P_2 */
9365 { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1
) },
9367 /* VEX_LEN_0F4A_P_0 */
9370 { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1
) },
9372 /* VEX_LEN_0F4A_P_2 */
9375 { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1
) },
9377 /* VEX_LEN_0F4B_P_0 */
9380 { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1
) },
9382 /* VEX_LEN_0F4B_P_2 */
9385 { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1
) },
9388 /* VEX_LEN_0F6E_P_2 */
9390 { "vmovK", { XMScalar
, Edq
}, 0 },
9393 /* VEX_LEN_0F77_P_1 */
9395 { "vzeroupper", { XX
}, 0 },
9396 { "vzeroall", { XX
}, 0 },
9399 /* VEX_LEN_0F7E_P_1 */
9401 { "vmovq", { XMScalar
, EXxmm_mq
}, 0 },
9404 /* VEX_LEN_0F7E_P_2 */
9406 { "vmovK", { Edq
, XMScalar
}, 0 },
9409 /* VEX_LEN_0F90_P_0 */
9411 { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0
) },
9414 /* VEX_LEN_0F90_P_2 */
9416 { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0
) },
9419 /* VEX_LEN_0F91_P_0 */
9421 { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0
) },
9424 /* VEX_LEN_0F91_P_2 */
9426 { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0
) },
9429 /* VEX_LEN_0F92_P_0 */
9431 { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0
) },
9434 /* VEX_LEN_0F92_P_2 */
9436 { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0
) },
9439 /* VEX_LEN_0F92_P_3 */
9441 { MOD_TABLE (MOD_VEX_0F92_P_3_LEN_0
) },
9444 /* VEX_LEN_0F93_P_0 */
9446 { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0
) },
9449 /* VEX_LEN_0F93_P_2 */
9451 { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0
) },
9454 /* VEX_LEN_0F93_P_3 */
9456 { MOD_TABLE (MOD_VEX_0F93_P_3_LEN_0
) },
9459 /* VEX_LEN_0F98_P_0 */
9461 { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0
) },
9464 /* VEX_LEN_0F98_P_2 */
9466 { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0
) },
9469 /* VEX_LEN_0F99_P_0 */
9471 { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0
) },
9474 /* VEX_LEN_0F99_P_2 */
9476 { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0
) },
9479 /* VEX_LEN_0FAE_R_2_M_0 */
9481 { "vldmxcsr", { Md
}, 0 },
9484 /* VEX_LEN_0FAE_R_3_M_0 */
9486 { "vstmxcsr", { Md
}, 0 },
9489 /* VEX_LEN_0FC4_P_2 */
9491 { "vpinsrw", { XM
, Vex128
, Edqw
, Ib
}, 0 },
9494 /* VEX_LEN_0FC5_P_2 */
9496 { "vpextrw", { Gdq
, XS
, Ib
}, 0 },
9499 /* VEX_LEN_0FD6_P_2 */
9501 { "vmovq", { EXqScalarS
, XMScalar
}, 0 },
9504 /* VEX_LEN_0FF7_P_2 */
9506 { "vmaskmovdqu", { XM
, XS
}, 0 },
9509 /* VEX_LEN_0F3816_P_2 */
9512 { VEX_W_TABLE (VEX_W_0F3816_P_2
) },
9515 /* VEX_LEN_0F3819_P_2 */
9518 { VEX_W_TABLE (VEX_W_0F3819_P_2
) },
9521 /* VEX_LEN_0F381A_P_2_M_0 */
9524 { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0
) },
9527 /* VEX_LEN_0F3836_P_2 */
9530 { VEX_W_TABLE (VEX_W_0F3836_P_2
) },
9533 /* VEX_LEN_0F3841_P_2 */
9535 { "vphminposuw", { XM
, EXx
}, 0 },
9538 /* VEX_LEN_0F385A_P_2_M_0 */
9541 { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0
) },
9544 /* VEX_LEN_0F38DB_P_2 */
9546 { "vaesimc", { XM
, EXx
}, 0 },
9549 /* VEX_LEN_0F38F2_P_0 */
9551 { "andnS", { Gdq
, VexGdq
, Edq
}, 0 },
9554 /* VEX_LEN_0F38F3_R_1_P_0 */
9556 { "blsrS", { VexGdq
, Edq
}, 0 },
9559 /* VEX_LEN_0F38F3_R_2_P_0 */
9561 { "blsmskS", { VexGdq
, Edq
}, 0 },
9564 /* VEX_LEN_0F38F3_R_3_P_0 */
9566 { "blsiS", { VexGdq
, Edq
}, 0 },
9569 /* VEX_LEN_0F38F5_P_0 */
9571 { "bzhiS", { Gdq
, Edq
, VexGdq
}, 0 },
9574 /* VEX_LEN_0F38F5_P_1 */
9576 { "pextS", { Gdq
, VexGdq
, Edq
}, 0 },
9579 /* VEX_LEN_0F38F5_P_3 */
9581 { "pdepS", { Gdq
, VexGdq
, Edq
}, 0 },
9584 /* VEX_LEN_0F38F6_P_3 */
9586 { "mulxS", { Gdq
, VexGdq
, Edq
}, 0 },
9589 /* VEX_LEN_0F38F7_P_0 */
9591 { "bextrS", { Gdq
, Edq
, VexGdq
}, 0 },
9594 /* VEX_LEN_0F38F7_P_1 */
9596 { "sarxS", { Gdq
, Edq
, VexGdq
}, 0 },
9599 /* VEX_LEN_0F38F7_P_2 */
9601 { "shlxS", { Gdq
, Edq
, VexGdq
}, 0 },
9604 /* VEX_LEN_0F38F7_P_3 */
9606 { "shrxS", { Gdq
, Edq
, VexGdq
}, 0 },
9609 /* VEX_LEN_0F3A00_P_2 */
9612 { VEX_W_TABLE (VEX_W_0F3A00_P_2
) },
9615 /* VEX_LEN_0F3A01_P_2 */
9618 { VEX_W_TABLE (VEX_W_0F3A01_P_2
) },
9621 /* VEX_LEN_0F3A06_P_2 */
9624 { VEX_W_TABLE (VEX_W_0F3A06_P_2
) },
9627 /* VEX_LEN_0F3A14_P_2 */
9629 { "vpextrb", { Edqb
, XM
, Ib
}, 0 },
9632 /* VEX_LEN_0F3A15_P_2 */
9634 { "vpextrw", { Edqw
, XM
, Ib
}, 0 },
9637 /* VEX_LEN_0F3A16_P_2 */
9639 { "vpextrK", { Edq
, XM
, Ib
}, 0 },
9642 /* VEX_LEN_0F3A17_P_2 */
9644 { "vextractps", { Edqd
, XM
, Ib
}, 0 },
9647 /* VEX_LEN_0F3A18_P_2 */
9650 { VEX_W_TABLE (VEX_W_0F3A18_P_2
) },
9653 /* VEX_LEN_0F3A19_P_2 */
9656 { VEX_W_TABLE (VEX_W_0F3A19_P_2
) },
9659 /* VEX_LEN_0F3A20_P_2 */
9661 { "vpinsrb", { XM
, Vex128
, Edqb
, Ib
}, 0 },
9664 /* VEX_LEN_0F3A21_P_2 */
9666 { "vinsertps", { XM
, Vex128
, EXd
, Ib
}, 0 },
9669 /* VEX_LEN_0F3A22_P_2 */
9671 { "vpinsrK", { XM
, Vex128
, Edq
, Ib
}, 0 },
9674 /* VEX_LEN_0F3A30_P_2 */
9676 { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0
) },
9679 /* VEX_LEN_0F3A31_P_2 */
9681 { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0
) },
9684 /* VEX_LEN_0F3A32_P_2 */
9686 { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0
) },
9689 /* VEX_LEN_0F3A33_P_2 */
9691 { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0
) },
9694 /* VEX_LEN_0F3A38_P_2 */
9697 { VEX_W_TABLE (VEX_W_0F3A38_P_2
) },
9700 /* VEX_LEN_0F3A39_P_2 */
9703 { VEX_W_TABLE (VEX_W_0F3A39_P_2
) },
9706 /* VEX_LEN_0F3A41_P_2 */
9708 { "vdppd", { XM
, Vex128
, EXx
, Ib
}, 0 },
9711 /* VEX_LEN_0F3A46_P_2 */
9714 { VEX_W_TABLE (VEX_W_0F3A46_P_2
) },
9717 /* VEX_LEN_0F3A60_P_2 */
9719 { "vpcmpestrm", { XM
, { PCMPESTR_Fixup
, x_mode
}, Ib
}, 0 },
9722 /* VEX_LEN_0F3A61_P_2 */
9724 { "vpcmpestri", { XM
, { PCMPESTR_Fixup
, x_mode
}, Ib
}, 0 },
9727 /* VEX_LEN_0F3A62_P_2 */
9729 { "vpcmpistrm", { XM
, EXx
, Ib
}, 0 },
9732 /* VEX_LEN_0F3A63_P_2 */
9734 { "vpcmpistri", { XM
, EXx
, Ib
}, 0 },
9737 /* VEX_LEN_0F3A6A_P_2 */
9739 { "vfmaddss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
}, 0 },
9742 /* VEX_LEN_0F3A6B_P_2 */
9744 { "vfmaddsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
}, 0 },
9747 /* VEX_LEN_0F3A6E_P_2 */
9749 { "vfmsubss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
}, 0 },
9752 /* VEX_LEN_0F3A6F_P_2 */
9754 { "vfmsubsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
}, 0 },
9757 /* VEX_LEN_0F3A7A_P_2 */
9759 { "vfnmaddss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
}, 0 },
9762 /* VEX_LEN_0F3A7B_P_2 */
9764 { "vfnmaddsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
}, 0 },
9767 /* VEX_LEN_0F3A7E_P_2 */
9769 { "vfnmsubss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
}, 0 },
9772 /* VEX_LEN_0F3A7F_P_2 */
9774 { "vfnmsubsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
}, 0 },
9777 /* VEX_LEN_0F3ADF_P_2 */
9779 { "vaeskeygenassist", { XM
, EXx
, Ib
}, 0 },
9782 /* VEX_LEN_0F3AF0_P_3 */
9784 { "rorxS", { Gdq
, Edq
, Ib
}, 0 },
9787 /* VEX_LEN_0FXOP_08_CC */
9789 { "vpcomb", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9792 /* VEX_LEN_0FXOP_08_CD */
9794 { "vpcomw", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9797 /* VEX_LEN_0FXOP_08_CE */
9799 { "vpcomd", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9802 /* VEX_LEN_0FXOP_08_CF */
9804 { "vpcomq", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9807 /* VEX_LEN_0FXOP_08_EC */
9809 { "vpcomub", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9812 /* VEX_LEN_0FXOP_08_ED */
9814 { "vpcomuw", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9817 /* VEX_LEN_0FXOP_08_EE */
9819 { "vpcomud", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9822 /* VEX_LEN_0FXOP_08_EF */
9824 { "vpcomuq", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9827 /* VEX_LEN_0FXOP_09_80 */
9829 { "vfrczps", { XM
, EXxmm
}, 0 },
9830 { "vfrczps", { XM
, EXymmq
}, 0 },
9833 /* VEX_LEN_0FXOP_09_81 */
9835 { "vfrczpd", { XM
, EXxmm
}, 0 },
9836 { "vfrczpd", { XM
, EXymmq
}, 0 },
9840 #include "i386-dis-evex-len.h"
9842 static const struct dis386 vex_w_table
[][2] = {
9844 /* VEX_W_0F41_P_0_LEN_1 */
9845 { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1
) },
9846 { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1
) },
9849 /* VEX_W_0F41_P_2_LEN_1 */
9850 { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1
) },
9851 { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1
) }
9854 /* VEX_W_0F42_P_0_LEN_1 */
9855 { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1
) },
9856 { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1
) },
9859 /* VEX_W_0F42_P_2_LEN_1 */
9860 { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1
) },
9861 { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1
) },
9864 /* VEX_W_0F44_P_0_LEN_0 */
9865 { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1
) },
9866 { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1
) },
9869 /* VEX_W_0F44_P_2_LEN_0 */
9870 { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1
) },
9871 { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1
) },
9874 /* VEX_W_0F45_P_0_LEN_1 */
9875 { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1
) },
9876 { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1
) },
9879 /* VEX_W_0F45_P_2_LEN_1 */
9880 { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1
) },
9881 { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1
) },
9884 /* VEX_W_0F46_P_0_LEN_1 */
9885 { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1
) },
9886 { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1
) },
9889 /* VEX_W_0F46_P_2_LEN_1 */
9890 { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1
) },
9891 { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1
) },
9894 /* VEX_W_0F47_P_0_LEN_1 */
9895 { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1
) },
9896 { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1
) },
9899 /* VEX_W_0F47_P_2_LEN_1 */
9900 { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1
) },
9901 { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1
) },
9904 /* VEX_W_0F4A_P_0_LEN_1 */
9905 { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1
) },
9906 { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1
) },
9909 /* VEX_W_0F4A_P_2_LEN_1 */
9910 { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1
) },
9911 { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1
) },
9914 /* VEX_W_0F4B_P_0_LEN_1 */
9915 { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1
) },
9916 { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1
) },
9919 /* VEX_W_0F4B_P_2_LEN_1 */
9920 { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1
) },
9923 /* VEX_W_0F90_P_0_LEN_0 */
9924 { "kmovw", { MaskG
, MaskE
}, 0 },
9925 { "kmovq", { MaskG
, MaskE
}, 0 },
9928 /* VEX_W_0F90_P_2_LEN_0 */
9929 { "kmovb", { MaskG
, MaskBDE
}, 0 },
9930 { "kmovd", { MaskG
, MaskBDE
}, 0 },
9933 /* VEX_W_0F91_P_0_LEN_0 */
9934 { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0
) },
9935 { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0
) },
9938 /* VEX_W_0F91_P_2_LEN_0 */
9939 { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0
) },
9940 { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0
) },
9943 /* VEX_W_0F92_P_0_LEN_0 */
9944 { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0
) },
9947 /* VEX_W_0F92_P_2_LEN_0 */
9948 { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0
) },
9951 /* VEX_W_0F93_P_0_LEN_0 */
9952 { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0
) },
9955 /* VEX_W_0F93_P_2_LEN_0 */
9956 { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0
) },
9959 /* VEX_W_0F98_P_0_LEN_0 */
9960 { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0
) },
9961 { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0
) },
9964 /* VEX_W_0F98_P_2_LEN_0 */
9965 { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0
) },
9966 { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0
) },
9969 /* VEX_W_0F99_P_0_LEN_0 */
9970 { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0
) },
9971 { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0
) },
9974 /* VEX_W_0F99_P_2_LEN_0 */
9975 { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0
) },
9976 { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0
) },
9979 /* VEX_W_0F380C_P_2 */
9980 { "vpermilps", { XM
, Vex
, EXx
}, 0 },
9983 /* VEX_W_0F380D_P_2 */
9984 { "vpermilpd", { XM
, Vex
, EXx
}, 0 },
9987 /* VEX_W_0F380E_P_2 */
9988 { "vtestps", { XM
, EXx
}, 0 },
9991 /* VEX_W_0F380F_P_2 */
9992 { "vtestpd", { XM
, EXx
}, 0 },
9995 /* VEX_W_0F3816_P_2 */
9996 { "vpermps", { XM
, Vex
, EXx
}, 0 },
9999 /* VEX_W_0F3818_P_2 */
10000 { "vbroadcastss", { XM
, EXxmm_md
}, 0 },
10003 /* VEX_W_0F3819_P_2 */
10004 { "vbroadcastsd", { XM
, EXxmm_mq
}, 0 },
10007 /* VEX_W_0F381A_P_2_M_0 */
10008 { "vbroadcastf128", { XM
, Mxmm
}, 0 },
10011 /* VEX_W_0F382C_P_2_M_0 */
10012 { "vmaskmovps", { XM
, Vex
, Mx
}, 0 },
10015 /* VEX_W_0F382D_P_2_M_0 */
10016 { "vmaskmovpd", { XM
, Vex
, Mx
}, 0 },
10019 /* VEX_W_0F382E_P_2_M_0 */
10020 { "vmaskmovps", { Mx
, Vex
, XM
}, 0 },
10023 /* VEX_W_0F382F_P_2_M_0 */
10024 { "vmaskmovpd", { Mx
, Vex
, XM
}, 0 },
10027 /* VEX_W_0F3836_P_2 */
10028 { "vpermd", { XM
, Vex
, EXx
}, 0 },
10031 /* VEX_W_0F3846_P_2 */
10032 { "vpsravd", { XM
, Vex
, EXx
}, 0 },
10035 /* VEX_W_0F3858_P_2 */
10036 { "vpbroadcastd", { XM
, EXxmm_md
}, 0 },
10039 /* VEX_W_0F3859_P_2 */
10040 { "vpbroadcastq", { XM
, EXxmm_mq
}, 0 },
10043 /* VEX_W_0F385A_P_2_M_0 */
10044 { "vbroadcasti128", { XM
, Mxmm
}, 0 },
10047 /* VEX_W_0F3878_P_2 */
10048 { "vpbroadcastb", { XM
, EXxmm_mb
}, 0 },
10051 /* VEX_W_0F3879_P_2 */
10052 { "vpbroadcastw", { XM
, EXxmm_mw
}, 0 },
10055 /* VEX_W_0F38CF_P_2 */
10056 { "vgf2p8mulb", { XM
, Vex
, EXx
}, 0 },
10059 /* VEX_W_0F3A00_P_2 */
10061 { "vpermq", { XM
, EXx
, Ib
}, 0 },
10064 /* VEX_W_0F3A01_P_2 */
10066 { "vpermpd", { XM
, EXx
, Ib
}, 0 },
10069 /* VEX_W_0F3A02_P_2 */
10070 { "vpblendd", { XM
, Vex
, EXx
, Ib
}, 0 },
10073 /* VEX_W_0F3A04_P_2 */
10074 { "vpermilps", { XM
, EXx
, Ib
}, 0 },
10077 /* VEX_W_0F3A05_P_2 */
10078 { "vpermilpd", { XM
, EXx
, Ib
}, 0 },
10081 /* VEX_W_0F3A06_P_2 */
10082 { "vperm2f128", { XM
, Vex256
, EXx
, Ib
}, 0 },
10085 /* VEX_W_0F3A18_P_2 */
10086 { "vinsertf128", { XM
, Vex256
, EXxmm
, Ib
}, 0 },
10089 /* VEX_W_0F3A19_P_2 */
10090 { "vextractf128", { EXxmm
, XM
, Ib
}, 0 },
10093 /* VEX_W_0F3A30_P_2_LEN_0 */
10094 { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0
) },
10095 { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0
) },
10098 /* VEX_W_0F3A31_P_2_LEN_0 */
10099 { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0
) },
10100 { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0
) },
10103 /* VEX_W_0F3A32_P_2_LEN_0 */
10104 { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0
) },
10105 { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0
) },
10108 /* VEX_W_0F3A33_P_2_LEN_0 */
10109 { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0
) },
10110 { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0
) },
10113 /* VEX_W_0F3A38_P_2 */
10114 { "vinserti128", { XM
, Vex256
, EXxmm
, Ib
}, 0 },
10117 /* VEX_W_0F3A39_P_2 */
10118 { "vextracti128", { EXxmm
, XM
, Ib
}, 0 },
10121 /* VEX_W_0F3A46_P_2 */
10122 { "vperm2i128", { XM
, Vex256
, EXx
, Ib
}, 0 },
10125 /* VEX_W_0F3A48_P_2 */
10126 { "vpermil2ps", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
}, 0 },
10127 { "vpermil2ps", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
}, 0 },
10130 /* VEX_W_0F3A49_P_2 */
10131 { "vpermil2pd", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
}, 0 },
10132 { "vpermil2pd", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
}, 0 },
10135 /* VEX_W_0F3A4A_P_2 */
10136 { "vblendvps", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
10139 /* VEX_W_0F3A4B_P_2 */
10140 { "vblendvpd", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
10143 /* VEX_W_0F3A4C_P_2 */
10144 { "vpblendvb", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
10147 /* VEX_W_0F3ACE_P_2 */
10149 { "vgf2p8affineqb", { XM
, Vex
, EXx
, Ib
}, 0 },
10152 /* VEX_W_0F3ACF_P_2 */
10154 { "vgf2p8affineinvqb", { XM
, Vex
, EXx
, Ib
}, 0 },
10157 #include "i386-dis-evex-w.h"
10160 static const struct dis386 mod_table
[][2] = {
10163 { "leaS", { Gv
, M
}, 0 },
10168 { RM_TABLE (RM_C6_REG_7
) },
10173 { RM_TABLE (RM_C7_REG_7
) },
10177 { "{l|}call^", { indirEp
}, 0 },
10181 { "{l|}jmp^", { indirEp
}, 0 },
10184 /* MOD_0F01_REG_0 */
10185 { X86_64_TABLE (X86_64_0F01_REG_0
) },
10186 { RM_TABLE (RM_0F01_REG_0
) },
10189 /* MOD_0F01_REG_1 */
10190 { X86_64_TABLE (X86_64_0F01_REG_1
) },
10191 { RM_TABLE (RM_0F01_REG_1
) },
10194 /* MOD_0F01_REG_2 */
10195 { X86_64_TABLE (X86_64_0F01_REG_2
) },
10196 { RM_TABLE (RM_0F01_REG_2
) },
10199 /* MOD_0F01_REG_3 */
10200 { X86_64_TABLE (X86_64_0F01_REG_3
) },
10201 { RM_TABLE (RM_0F01_REG_3
) },
10204 /* MOD_0F01_REG_5 */
10205 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_0
) },
10206 { RM_TABLE (RM_0F01_REG_5_MOD_3
) },
10209 /* MOD_0F01_REG_7 */
10210 { "invlpg", { Mb
}, 0 },
10211 { RM_TABLE (RM_0F01_REG_7_MOD_3
) },
10214 /* MOD_0F12_PREFIX_0 */
10215 { "movlpX", { XM
, EXq
}, 0 },
10216 { "movhlps", { XM
, EXq
}, 0 },
10219 /* MOD_0F12_PREFIX_2 */
10220 { "movlpX", { XM
, EXq
}, 0 },
10224 { "movlpX", { EXq
, XM
}, PREFIX_OPCODE
},
10227 /* MOD_0F16_PREFIX_0 */
10228 { "movhpX", { XM
, EXq
}, 0 },
10229 { "movlhps", { XM
, EXq
}, 0 },
10232 /* MOD_0F16_PREFIX_2 */
10233 { "movhpX", { XM
, EXq
}, 0 },
10237 { "movhpX", { EXq
, XM
}, PREFIX_OPCODE
},
10240 /* MOD_0F18_REG_0 */
10241 { "prefetchnta", { Mb
}, 0 },
10244 /* MOD_0F18_REG_1 */
10245 { "prefetcht0", { Mb
}, 0 },
10248 /* MOD_0F18_REG_2 */
10249 { "prefetcht1", { Mb
}, 0 },
10252 /* MOD_0F18_REG_3 */
10253 { "prefetcht2", { Mb
}, 0 },
10256 /* MOD_0F18_REG_4 */
10257 { "nop/reserved", { Mb
}, 0 },
10260 /* MOD_0F18_REG_5 */
10261 { "nop/reserved", { Mb
}, 0 },
10264 /* MOD_0F18_REG_6 */
10265 { "nop/reserved", { Mb
}, 0 },
10268 /* MOD_0F18_REG_7 */
10269 { "nop/reserved", { Mb
}, 0 },
10272 /* MOD_0F1A_PREFIX_0 */
10273 { "bndldx", { Gbnd
, Mv_bnd
}, 0 },
10274 { "nopQ", { Ev
}, 0 },
10277 /* MOD_0F1B_PREFIX_0 */
10278 { "bndstx", { Mv_bnd
, Gbnd
}, 0 },
10279 { "nopQ", { Ev
}, 0 },
10282 /* MOD_0F1B_PREFIX_1 */
10283 { "bndmk", { Gbnd
, Mv_bnd
}, 0 },
10284 { "nopQ", { Ev
}, 0 },
10287 /* MOD_0F1C_PREFIX_0 */
10288 { REG_TABLE (REG_0F1C_P_0_MOD_0
) },
10289 { "nopQ", { Ev
}, 0 },
10292 /* MOD_0F1E_PREFIX_1 */
10293 { "nopQ", { Ev
}, 0 },
10294 { REG_TABLE (REG_0F1E_P_1_MOD_3
) },
10299 { "movL", { Rd
, Td
}, 0 },
10304 { "movL", { Td
, Rd
}, 0 },
10307 /* MOD_0F2B_PREFIX_0 */
10308 {"movntps", { Mx
, XM
}, PREFIX_OPCODE
},
10311 /* MOD_0F2B_PREFIX_1 */
10312 {"movntss", { Md
, XM
}, PREFIX_OPCODE
},
10315 /* MOD_0F2B_PREFIX_2 */
10316 {"movntpd", { Mx
, XM
}, PREFIX_OPCODE
},
10319 /* MOD_0F2B_PREFIX_3 */
10320 {"movntsd", { Mq
, XM
}, PREFIX_OPCODE
},
10325 { "movmskpX", { Gdq
, XS
}, PREFIX_OPCODE
},
10328 /* MOD_0F71_REG_2 */
10330 { "psrlw", { MS
, Ib
}, 0 },
10333 /* MOD_0F71_REG_4 */
10335 { "psraw", { MS
, Ib
}, 0 },
10338 /* MOD_0F71_REG_6 */
10340 { "psllw", { MS
, Ib
}, 0 },
10343 /* MOD_0F72_REG_2 */
10345 { "psrld", { MS
, Ib
}, 0 },
10348 /* MOD_0F72_REG_4 */
10350 { "psrad", { MS
, Ib
}, 0 },
10353 /* MOD_0F72_REG_6 */
10355 { "pslld", { MS
, Ib
}, 0 },
10358 /* MOD_0F73_REG_2 */
10360 { "psrlq", { MS
, Ib
}, 0 },
10363 /* MOD_0F73_REG_3 */
10365 { PREFIX_TABLE (PREFIX_0F73_REG_3
) },
10368 /* MOD_0F73_REG_6 */
10370 { "psllq", { MS
, Ib
}, 0 },
10373 /* MOD_0F73_REG_7 */
10375 { PREFIX_TABLE (PREFIX_0F73_REG_7
) },
10378 /* MOD_0FAE_REG_0 */
10379 { "fxsave", { FXSAVE
}, 0 },
10380 { PREFIX_TABLE (PREFIX_0FAE_REG_0_MOD_3
) },
10383 /* MOD_0FAE_REG_1 */
10384 { "fxrstor", { FXSAVE
}, 0 },
10385 { PREFIX_TABLE (PREFIX_0FAE_REG_1_MOD_3
) },
10388 /* MOD_0FAE_REG_2 */
10389 { "ldmxcsr", { Md
}, 0 },
10390 { PREFIX_TABLE (PREFIX_0FAE_REG_2_MOD_3
) },
10393 /* MOD_0FAE_REG_3 */
10394 { "stmxcsr", { Md
}, 0 },
10395 { PREFIX_TABLE (PREFIX_0FAE_REG_3_MOD_3
) },
10398 /* MOD_0FAE_REG_4 */
10399 { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_0
) },
10400 { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_3
) },
10403 /* MOD_0FAE_REG_5 */
10404 { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_0
) },
10405 { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_3
) },
10408 /* MOD_0FAE_REG_6 */
10409 { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_0
) },
10410 { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_3
) },
10413 /* MOD_0FAE_REG_7 */
10414 { PREFIX_TABLE (PREFIX_0FAE_REG_7_MOD_0
) },
10415 { RM_TABLE (RM_0FAE_REG_7_MOD_3
) },
10419 { "lssS", { Gv
, Mp
}, 0 },
10423 { "lfsS", { Gv
, Mp
}, 0 },
10427 { "lgsS", { Gv
, Mp
}, 0 },
10431 { PREFIX_TABLE (PREFIX_0FC3_MOD_0
) },
10434 /* MOD_0FC7_REG_3 */
10435 { "xrstors", { FXSAVE
}, 0 },
10438 /* MOD_0FC7_REG_4 */
10439 { "xsavec", { FXSAVE
}, 0 },
10442 /* MOD_0FC7_REG_5 */
10443 { "xsaves", { FXSAVE
}, 0 },
10446 /* MOD_0FC7_REG_6 */
10447 { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_0
) },
10448 { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_3
) }
10451 /* MOD_0FC7_REG_7 */
10452 { "vmptrst", { Mq
}, 0 },
10453 { PREFIX_TABLE (PREFIX_0FC7_REG_7_MOD_3
) }
10458 { "pmovmskb", { Gdq
, MS
}, 0 },
10461 /* MOD_0FE7_PREFIX_2 */
10462 { "movntdq", { Mx
, XM
}, 0 },
10465 /* MOD_0FF0_PREFIX_3 */
10466 { "lddqu", { XM
, M
}, 0 },
10469 /* MOD_0F382A_PREFIX_2 */
10470 { "movntdqa", { XM
, Mx
}, 0 },
10473 /* MOD_0F38F5_PREFIX_2 */
10474 { "wrussK", { M
, Gdq
}, PREFIX_OPCODE
},
10477 /* MOD_0F38F6_PREFIX_0 */
10478 { "wrssK", { M
, Gdq
}, PREFIX_OPCODE
},
10481 /* MOD_0F38F8_PREFIX_1 */
10482 { "enqcmds", { Gva
, M
}, PREFIX_OPCODE
},
10485 /* MOD_0F38F8_PREFIX_2 */
10486 { "movdir64b", { Gva
, M
}, PREFIX_OPCODE
},
10489 /* MOD_0F38F8_PREFIX_3 */
10490 { "enqcmd", { Gva
, M
}, PREFIX_OPCODE
},
10493 /* MOD_0F38F9_PREFIX_0 */
10494 { "movdiri", { Ev
, Gv
}, PREFIX_OPCODE
},
10498 { "bound{S|}", { Gv
, Ma
}, 0 },
10499 { EVEX_TABLE (EVEX_0F
) },
10503 { "lesS", { Gv
, Mp
}, 0 },
10504 { VEX_C4_TABLE (VEX_0F
) },
10508 { "ldsS", { Gv
, Mp
}, 0 },
10509 { VEX_C5_TABLE (VEX_0F
) },
10512 /* MOD_VEX_0F12_PREFIX_0 */
10513 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0
) },
10514 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1
) },
10517 /* MOD_VEX_0F12_PREFIX_2 */
10518 { VEX_LEN_TABLE (VEX_LEN_0F12_P_2_M_0
) },
10522 { VEX_LEN_TABLE (VEX_LEN_0F13_M_0
) },
10525 /* MOD_VEX_0F16_PREFIX_0 */
10526 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0
) },
10527 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1
) },
10530 /* MOD_VEX_0F16_PREFIX_2 */
10531 { VEX_LEN_TABLE (VEX_LEN_0F16_P_2_M_0
) },
10535 { VEX_LEN_TABLE (VEX_LEN_0F17_M_0
) },
10539 { "vmovntpX", { Mx
, XM
}, PREFIX_OPCODE
},
10542 /* MOD_VEX_W_0_0F41_P_0_LEN_1 */
10544 { "kandw", { MaskG
, MaskVex
, MaskR
}, 0 },
10547 /* MOD_VEX_W_1_0F41_P_0_LEN_1 */
10549 { "kandq", { MaskG
, MaskVex
, MaskR
}, 0 },
10552 /* MOD_VEX_W_0_0F41_P_2_LEN_1 */
10554 { "kandb", { MaskG
, MaskVex
, MaskR
}, 0 },
10557 /* MOD_VEX_W_1_0F41_P_2_LEN_1 */
10559 { "kandd", { MaskG
, MaskVex
, MaskR
}, 0 },
10562 /* MOD_VEX_W_0_0F42_P_0_LEN_1 */
10564 { "kandnw", { MaskG
, MaskVex
, MaskR
}, 0 },
10567 /* MOD_VEX_W_1_0F42_P_0_LEN_1 */
10569 { "kandnq", { MaskG
, MaskVex
, MaskR
}, 0 },
10572 /* MOD_VEX_W_0_0F42_P_2_LEN_1 */
10574 { "kandnb", { MaskG
, MaskVex
, MaskR
}, 0 },
10577 /* MOD_VEX_W_1_0F42_P_2_LEN_1 */
10579 { "kandnd", { MaskG
, MaskVex
, MaskR
}, 0 },
10582 /* MOD_VEX_W_0_0F44_P_0_LEN_0 */
10584 { "knotw", { MaskG
, MaskR
}, 0 },
10587 /* MOD_VEX_W_1_0F44_P_0_LEN_0 */
10589 { "knotq", { MaskG
, MaskR
}, 0 },
10592 /* MOD_VEX_W_0_0F44_P_2_LEN_0 */
10594 { "knotb", { MaskG
, MaskR
}, 0 },
10597 /* MOD_VEX_W_1_0F44_P_2_LEN_0 */
10599 { "knotd", { MaskG
, MaskR
}, 0 },
10602 /* MOD_VEX_W_0_0F45_P_0_LEN_1 */
10604 { "korw", { MaskG
, MaskVex
, MaskR
}, 0 },
10607 /* MOD_VEX_W_1_0F45_P_0_LEN_1 */
10609 { "korq", { MaskG
, MaskVex
, MaskR
}, 0 },
10612 /* MOD_VEX_W_0_0F45_P_2_LEN_1 */
10614 { "korb", { MaskG
, MaskVex
, MaskR
}, 0 },
10617 /* MOD_VEX_W_1_0F45_P_2_LEN_1 */
10619 { "kord", { MaskG
, MaskVex
, MaskR
}, 0 },
10622 /* MOD_VEX_W_0_0F46_P_0_LEN_1 */
10624 { "kxnorw", { MaskG
, MaskVex
, MaskR
}, 0 },
10627 /* MOD_VEX_W_1_0F46_P_0_LEN_1 */
10629 { "kxnorq", { MaskG
, MaskVex
, MaskR
}, 0 },
10632 /* MOD_VEX_W_0_0F46_P_2_LEN_1 */
10634 { "kxnorb", { MaskG
, MaskVex
, MaskR
}, 0 },
10637 /* MOD_VEX_W_1_0F46_P_2_LEN_1 */
10639 { "kxnord", { MaskG
, MaskVex
, MaskR
}, 0 },
10642 /* MOD_VEX_W_0_0F47_P_0_LEN_1 */
10644 { "kxorw", { MaskG
, MaskVex
, MaskR
}, 0 },
10647 /* MOD_VEX_W_1_0F47_P_0_LEN_1 */
10649 { "kxorq", { MaskG
, MaskVex
, MaskR
}, 0 },
10652 /* MOD_VEX_W_0_0F47_P_2_LEN_1 */
10654 { "kxorb", { MaskG
, MaskVex
, MaskR
}, 0 },
10657 /* MOD_VEX_W_1_0F47_P_2_LEN_1 */
10659 { "kxord", { MaskG
, MaskVex
, MaskR
}, 0 },
10662 /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */
10664 { "kaddw", { MaskG
, MaskVex
, MaskR
}, 0 },
10667 /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */
10669 { "kaddq", { MaskG
, MaskVex
, MaskR
}, 0 },
10672 /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */
10674 { "kaddb", { MaskG
, MaskVex
, MaskR
}, 0 },
10677 /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */
10679 { "kaddd", { MaskG
, MaskVex
, MaskR
}, 0 },
10682 /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */
10684 { "kunpckwd", { MaskG
, MaskVex
, MaskR
}, 0 },
10687 /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */
10689 { "kunpckdq", { MaskG
, MaskVex
, MaskR
}, 0 },
10692 /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */
10694 { "kunpckbw", { MaskG
, MaskVex
, MaskR
}, 0 },
10699 { "vmovmskpX", { Gdq
, XS
}, PREFIX_OPCODE
},
10702 /* MOD_VEX_0F71_REG_2 */
10704 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2
) },
10707 /* MOD_VEX_0F71_REG_4 */
10709 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4
) },
10712 /* MOD_VEX_0F71_REG_6 */
10714 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6
) },
10717 /* MOD_VEX_0F72_REG_2 */
10719 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2
) },
10722 /* MOD_VEX_0F72_REG_4 */
10724 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4
) },
10727 /* MOD_VEX_0F72_REG_6 */
10729 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6
) },
10732 /* MOD_VEX_0F73_REG_2 */
10734 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2
) },
10737 /* MOD_VEX_0F73_REG_3 */
10739 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3
) },
10742 /* MOD_VEX_0F73_REG_6 */
10744 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6
) },
10747 /* MOD_VEX_0F73_REG_7 */
10749 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7
) },
10752 /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
10753 { "kmovw", { Ew
, MaskG
}, 0 },
10757 /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
10758 { "kmovq", { Eq
, MaskG
}, 0 },
10762 /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
10763 { "kmovb", { Eb
, MaskG
}, 0 },
10767 /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
10768 { "kmovd", { Ed
, MaskG
}, 0 },
10772 /* MOD_VEX_W_0_0F92_P_0_LEN_0 */
10774 { "kmovw", { MaskG
, Rdq
}, 0 },
10777 /* MOD_VEX_W_0_0F92_P_2_LEN_0 */
10779 { "kmovb", { MaskG
, Rdq
}, 0 },
10782 /* MOD_VEX_0F92_P_3_LEN_0 */
10784 { "kmovK", { MaskG
, Rdq
}, 0 },
10787 /* MOD_VEX_W_0_0F93_P_0_LEN_0 */
10789 { "kmovw", { Gdq
, MaskR
}, 0 },
10792 /* MOD_VEX_W_0_0F93_P_2_LEN_0 */
10794 { "kmovb", { Gdq
, MaskR
}, 0 },
10797 /* MOD_VEX_0F93_P_3_LEN_0 */
10799 { "kmovK", { Gdq
, MaskR
}, 0 },
10802 /* MOD_VEX_W_0_0F98_P_0_LEN_0 */
10804 { "kortestw", { MaskG
, MaskR
}, 0 },
10807 /* MOD_VEX_W_1_0F98_P_0_LEN_0 */
10809 { "kortestq", { MaskG
, MaskR
}, 0 },
10812 /* MOD_VEX_W_0_0F98_P_2_LEN_0 */
10814 { "kortestb", { MaskG
, MaskR
}, 0 },
10817 /* MOD_VEX_W_1_0F98_P_2_LEN_0 */
10819 { "kortestd", { MaskG
, MaskR
}, 0 },
10822 /* MOD_VEX_W_0_0F99_P_0_LEN_0 */
10824 { "ktestw", { MaskG
, MaskR
}, 0 },
10827 /* MOD_VEX_W_1_0F99_P_0_LEN_0 */
10829 { "ktestq", { MaskG
, MaskR
}, 0 },
10832 /* MOD_VEX_W_0_0F99_P_2_LEN_0 */
10834 { "ktestb", { MaskG
, MaskR
}, 0 },
10837 /* MOD_VEX_W_1_0F99_P_2_LEN_0 */
10839 { "ktestd", { MaskG
, MaskR
}, 0 },
10842 /* MOD_VEX_0FAE_REG_2 */
10843 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0
) },
10846 /* MOD_VEX_0FAE_REG_3 */
10847 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0
) },
10850 /* MOD_VEX_0FD7_PREFIX_2 */
10852 { "vpmovmskb", { Gdq
, XS
}, 0 },
10855 /* MOD_VEX_0FE7_PREFIX_2 */
10856 { "vmovntdq", { Mx
, XM
}, 0 },
10859 /* MOD_VEX_0FF0_PREFIX_3 */
10860 { "vlddqu", { XM
, M
}, 0 },
10863 /* MOD_VEX_0F381A_PREFIX_2 */
10864 { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0
) },
10867 /* MOD_VEX_0F382A_PREFIX_2 */
10868 { "vmovntdqa", { XM
, Mx
}, 0 },
10871 /* MOD_VEX_0F382C_PREFIX_2 */
10872 { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0
) },
10875 /* MOD_VEX_0F382D_PREFIX_2 */
10876 { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0
) },
10879 /* MOD_VEX_0F382E_PREFIX_2 */
10880 { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0
) },
10883 /* MOD_VEX_0F382F_PREFIX_2 */
10884 { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0
) },
10887 /* MOD_VEX_0F385A_PREFIX_2 */
10888 { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0
) },
10891 /* MOD_VEX_0F388C_PREFIX_2 */
10892 { "vpmaskmov%LW", { XM
, Vex
, Mx
}, 0 },
10895 /* MOD_VEX_0F388E_PREFIX_2 */
10896 { "vpmaskmov%LW", { Mx
, Vex
, XM
}, 0 },
10899 /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */
10901 { "kshiftrb", { MaskG
, MaskR
, Ib
}, 0 },
10904 /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */
10906 { "kshiftrw", { MaskG
, MaskR
, Ib
}, 0 },
10909 /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */
10911 { "kshiftrd", { MaskG
, MaskR
, Ib
}, 0 },
10914 /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */
10916 { "kshiftrq", { MaskG
, MaskR
, Ib
}, 0 },
10919 /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */
10921 { "kshiftlb", { MaskG
, MaskR
, Ib
}, 0 },
10924 /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */
10926 { "kshiftlw", { MaskG
, MaskR
, Ib
}, 0 },
10929 /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */
10931 { "kshiftld", { MaskG
, MaskR
, Ib
}, 0 },
10934 /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */
10936 { "kshiftlq", { MaskG
, MaskR
, Ib
}, 0 },
10939 #include "i386-dis-evex-mod.h"
10942 static const struct dis386 rm_table
[][8] = {
10945 { "xabort", { Skip_MODRM
, Ib
}, 0 },
10949 { "xbeginT", { Skip_MODRM
, Jdqw
}, 0 },
10952 /* RM_0F01_REG_0 */
10953 { "enclv", { Skip_MODRM
}, 0 },
10954 { "vmcall", { Skip_MODRM
}, 0 },
10955 { "vmlaunch", { Skip_MODRM
}, 0 },
10956 { "vmresume", { Skip_MODRM
}, 0 },
10957 { "vmxoff", { Skip_MODRM
}, 0 },
10958 { "pconfig", { Skip_MODRM
}, 0 },
10961 /* RM_0F01_REG_1 */
10962 { "monitor", { { OP_Monitor
, 0 } }, 0 },
10963 { "mwait", { { OP_Mwait
, 0 } }, 0 },
10964 { "clac", { Skip_MODRM
}, 0 },
10965 { "stac", { Skip_MODRM
}, 0 },
10969 { "encls", { Skip_MODRM
}, 0 },
10972 /* RM_0F01_REG_2 */
10973 { "xgetbv", { Skip_MODRM
}, 0 },
10974 { "xsetbv", { Skip_MODRM
}, 0 },
10977 { "vmfunc", { Skip_MODRM
}, 0 },
10978 { "xend", { Skip_MODRM
}, 0 },
10979 { "xtest", { Skip_MODRM
}, 0 },
10980 { "enclu", { Skip_MODRM
}, 0 },
10983 /* RM_0F01_REG_3 */
10984 { "vmrun", { Skip_MODRM
}, 0 },
10985 { PREFIX_TABLE (PREFIX_0F01_REG_3_RM_1
) },
10986 { "vmload", { Skip_MODRM
}, 0 },
10987 { "vmsave", { Skip_MODRM
}, 0 },
10988 { "stgi", { Skip_MODRM
}, 0 },
10989 { "clgi", { Skip_MODRM
}, 0 },
10990 { "skinit", { Skip_MODRM
}, 0 },
10991 { "invlpga", { Skip_MODRM
}, 0 },
10994 /* RM_0F01_REG_5_MOD_3 */
10995 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_0
) },
10996 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_1
) },
10997 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_2
) },
11001 { "rdpkru", { Skip_MODRM
}, 0 },
11002 { "wrpkru", { Skip_MODRM
}, 0 },
11005 /* RM_0F01_REG_7_MOD_3 */
11006 { "swapgs", { Skip_MODRM
}, 0 },
11007 { "rdtscp", { Skip_MODRM
}, 0 },
11008 { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_2
) },
11009 { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_3
) },
11010 { "clzero", { Skip_MODRM
}, 0 },
11011 { "rdpru", { Skip_MODRM
}, 0 },
11014 /* RM_0F1E_P_1_MOD_3_REG_7 */
11015 { "nopQ", { Ev
}, 0 },
11016 { "nopQ", { Ev
}, 0 },
11017 { "endbr64", { Skip_MODRM
}, PREFIX_OPCODE
},
11018 { "endbr32", { Skip_MODRM
}, PREFIX_OPCODE
},
11019 { "nopQ", { Ev
}, 0 },
11020 { "nopQ", { Ev
}, 0 },
11021 { "nopQ", { Ev
}, 0 },
11022 { "nopQ", { Ev
}, 0 },
11025 /* RM_0FAE_REG_6_MOD_3 */
11026 { "mfence", { Skip_MODRM
}, 0 },
11029 /* RM_0FAE_REG_7_MOD_3 */
11030 { "sfence", { Skip_MODRM
}, 0 },
11035 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
11037 /* We use the high bit to indicate different name for the same
11039 #define REP_PREFIX (0xf3 | 0x100)
11040 #define XACQUIRE_PREFIX (0xf2 | 0x200)
11041 #define XRELEASE_PREFIX (0xf3 | 0x400)
11042 #define BND_PREFIX (0xf2 | 0x400)
11043 #define NOTRACK_PREFIX (0x3e | 0x100)
11045 /* Remember if the current op is a jump instruction. */
11046 static bfd_boolean op_is_jump
= FALSE
;
11051 int newrex
, i
, length
;
11056 last_lock_prefix
= -1;
11057 last_repz_prefix
= -1;
11058 last_repnz_prefix
= -1;
11059 last_data_prefix
= -1;
11060 last_addr_prefix
= -1;
11061 last_rex_prefix
= -1;
11062 last_seg_prefix
= -1;
11064 active_seg_prefix
= 0;
11065 for (i
= 0; i
< (int) ARRAY_SIZE (all_prefixes
); i
++)
11066 all_prefixes
[i
] = 0;
11069 /* The maximum instruction length is 15bytes. */
11070 while (length
< MAX_CODE_LENGTH
- 1)
11072 FETCH_DATA (the_info
, codep
+ 1);
11076 /* REX prefixes family. */
11093 if (address_mode
== mode_64bit
)
11097 last_rex_prefix
= i
;
11100 prefixes
|= PREFIX_REPZ
;
11101 last_repz_prefix
= i
;
11104 prefixes
|= PREFIX_REPNZ
;
11105 last_repnz_prefix
= i
;
11108 prefixes
|= PREFIX_LOCK
;
11109 last_lock_prefix
= i
;
11112 prefixes
|= PREFIX_CS
;
11113 last_seg_prefix
= i
;
11114 active_seg_prefix
= PREFIX_CS
;
11117 prefixes
|= PREFIX_SS
;
11118 last_seg_prefix
= i
;
11119 active_seg_prefix
= PREFIX_SS
;
11122 prefixes
|= PREFIX_DS
;
11123 last_seg_prefix
= i
;
11124 active_seg_prefix
= PREFIX_DS
;
11127 prefixes
|= PREFIX_ES
;
11128 last_seg_prefix
= i
;
11129 active_seg_prefix
= PREFIX_ES
;
11132 prefixes
|= PREFIX_FS
;
11133 last_seg_prefix
= i
;
11134 active_seg_prefix
= PREFIX_FS
;
11137 prefixes
|= PREFIX_GS
;
11138 last_seg_prefix
= i
;
11139 active_seg_prefix
= PREFIX_GS
;
11142 prefixes
|= PREFIX_DATA
;
11143 last_data_prefix
= i
;
11146 prefixes
|= PREFIX_ADDR
;
11147 last_addr_prefix
= i
;
11150 /* fwait is really an instruction. If there are prefixes
11151 before the fwait, they belong to the fwait, *not* to the
11152 following instruction. */
11154 if (prefixes
|| rex
)
11156 prefixes
|= PREFIX_FWAIT
;
11158 /* This ensures that the previous REX prefixes are noticed
11159 as unused prefixes, as in the return case below. */
11163 prefixes
= PREFIX_FWAIT
;
11168 /* Rex is ignored when followed by another prefix. */
11174 if (*codep
!= FWAIT_OPCODE
)
11175 all_prefixes
[i
++] = *codep
;
11183 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
11186 static const char *
11187 prefix_name (int pref
, int sizeflag
)
11189 static const char *rexes
[16] =
11192 "rex.B", /* 0x41 */
11193 "rex.X", /* 0x42 */
11194 "rex.XB", /* 0x43 */
11195 "rex.R", /* 0x44 */
11196 "rex.RB", /* 0x45 */
11197 "rex.RX", /* 0x46 */
11198 "rex.RXB", /* 0x47 */
11199 "rex.W", /* 0x48 */
11200 "rex.WB", /* 0x49 */
11201 "rex.WX", /* 0x4a */
11202 "rex.WXB", /* 0x4b */
11203 "rex.WR", /* 0x4c */
11204 "rex.WRB", /* 0x4d */
11205 "rex.WRX", /* 0x4e */
11206 "rex.WRXB", /* 0x4f */
11211 /* REX prefixes family. */
11228 return rexes
[pref
- 0x40];
11248 return (sizeflag
& DFLAG
) ? "data16" : "data32";
11250 if (address_mode
== mode_64bit
)
11251 return (sizeflag
& AFLAG
) ? "addr32" : "addr64";
11253 return (sizeflag
& AFLAG
) ? "addr16" : "addr32";
11258 case XACQUIRE_PREFIX
:
11260 case XRELEASE_PREFIX
:
11264 case NOTRACK_PREFIX
:
11271 static char op_out
[MAX_OPERANDS
][100];
11272 static int op_ad
, op_index
[MAX_OPERANDS
];
11273 static int two_source_ops
;
11274 static bfd_vma op_address
[MAX_OPERANDS
];
11275 static bfd_vma op_riprel
[MAX_OPERANDS
];
11276 static bfd_vma start_pc
;
11279 * On the 386's of 1988, the maximum length of an instruction is 15 bytes.
11280 * (see topic "Redundant prefixes" in the "Differences from 8086"
11281 * section of the "Virtual 8086 Mode" chapter.)
11282 * 'pc' should be the address of this instruction, it will
11283 * be used to print the target address if this is a relative jump or call
11284 * The function returns the length of this instruction in bytes.
11287 static char intel_syntax
;
11288 static char intel_mnemonic
= !SYSV386_COMPAT
;
11289 static char open_char
;
11290 static char close_char
;
11291 static char separator_char
;
11292 static char scale_char
;
11300 static enum x86_64_isa isa64
;
11302 /* Here for backwards compatibility. When gdb stops using
11303 print_insn_i386_att and print_insn_i386_intel these functions can
11304 disappear, and print_insn_i386 be merged into print_insn. */
11306 print_insn_i386_att (bfd_vma pc
, disassemble_info
*info
)
11310 return print_insn (pc
, info
);
11314 print_insn_i386_intel (bfd_vma pc
, disassemble_info
*info
)
11318 return print_insn (pc
, info
);
11322 print_insn_i386 (bfd_vma pc
, disassemble_info
*info
)
11326 return print_insn (pc
, info
);
11330 print_i386_disassembler_options (FILE *stream
)
11332 fprintf (stream
, _("\n\
11333 The following i386/x86-64 specific disassembler options are supported for use\n\
11334 with the -M switch (multiple options should be separated by commas):\n"));
11336 fprintf (stream
, _(" x86-64 Disassemble in 64bit mode\n"));
11337 fprintf (stream
, _(" i386 Disassemble in 32bit mode\n"));
11338 fprintf (stream
, _(" i8086 Disassemble in 16bit mode\n"));
11339 fprintf (stream
, _(" att Display instruction in AT&T syntax\n"));
11340 fprintf (stream
, _(" intel Display instruction in Intel syntax\n"));
11341 fprintf (stream
, _(" att-mnemonic\n"
11342 " Display instruction in AT&T mnemonic\n"));
11343 fprintf (stream
, _(" intel-mnemonic\n"
11344 " Display instruction in Intel mnemonic\n"));
11345 fprintf (stream
, _(" addr64 Assume 64bit address size\n"));
11346 fprintf (stream
, _(" addr32 Assume 32bit address size\n"));
11347 fprintf (stream
, _(" addr16 Assume 16bit address size\n"));
11348 fprintf (stream
, _(" data32 Assume 32bit data size\n"));
11349 fprintf (stream
, _(" data16 Assume 16bit data size\n"));
11350 fprintf (stream
, _(" suffix Always display instruction suffix in AT&T syntax\n"));
11351 fprintf (stream
, _(" amd64 Display instruction in AMD64 ISA\n"));
11352 fprintf (stream
, _(" intel64 Display instruction in Intel64 ISA\n"));
11356 static const struct dis386 bad_opcode
= { "(bad)", { XX
}, 0 };
11358 /* Get a pointer to struct dis386 with a valid name. */
11360 static const struct dis386
*
11361 get_valid_dis386 (const struct dis386
*dp
, disassemble_info
*info
)
11363 int vindex
, vex_table_index
;
11365 if (dp
->name
!= NULL
)
11368 switch (dp
->op
[0].bytemode
)
11370 case USE_REG_TABLE
:
11371 dp
= ®_table
[dp
->op
[1].bytemode
][modrm
.reg
];
11374 case USE_MOD_TABLE
:
11375 vindex
= modrm
.mod
== 0x3 ? 1 : 0;
11376 dp
= &mod_table
[dp
->op
[1].bytemode
][vindex
];
11380 dp
= &rm_table
[dp
->op
[1].bytemode
][modrm
.rm
];
11383 case USE_PREFIX_TABLE
:
11386 /* The prefix in VEX is implicit. */
11387 switch (vex
.prefix
)
11392 case REPE_PREFIX_OPCODE
:
11395 case DATA_PREFIX_OPCODE
:
11398 case REPNE_PREFIX_OPCODE
:
11408 int last_prefix
= -1;
11411 /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
11412 When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
11414 if ((prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
)) != 0)
11416 if (last_repz_prefix
> last_repnz_prefix
)
11419 prefix
= PREFIX_REPZ
;
11420 last_prefix
= last_repz_prefix
;
11425 prefix
= PREFIX_REPNZ
;
11426 last_prefix
= last_repnz_prefix
;
11429 /* Check if prefix should be ignored. */
11430 if ((((prefix_table
[dp
->op
[1].bytemode
][vindex
].prefix_requirement
11431 & PREFIX_IGNORED
) >> PREFIX_IGNORED_SHIFT
)
11436 if (vindex
== 0 && (prefixes
& PREFIX_DATA
) != 0)
11439 prefix
= PREFIX_DATA
;
11440 last_prefix
= last_data_prefix
;
11445 used_prefixes
|= prefix
;
11446 all_prefixes
[last_prefix
] = 0;
11449 dp
= &prefix_table
[dp
->op
[1].bytemode
][vindex
];
11452 case USE_X86_64_TABLE
:
11453 vindex
= address_mode
== mode_64bit
? 1 : 0;
11454 dp
= &x86_64_table
[dp
->op
[1].bytemode
][vindex
];
11457 case USE_3BYTE_TABLE
:
11458 FETCH_DATA (info
, codep
+ 2);
11460 dp
= &three_byte_table
[dp
->op
[1].bytemode
][vindex
];
11462 modrm
.mod
= (*codep
>> 6) & 3;
11463 modrm
.reg
= (*codep
>> 3) & 7;
11464 modrm
.rm
= *codep
& 7;
11467 case USE_VEX_LEN_TABLE
:
11471 switch (vex
.length
)
11484 dp
= &vex_len_table
[dp
->op
[1].bytemode
][vindex
];
11487 case USE_EVEX_LEN_TABLE
:
11491 switch (vex
.length
)
11507 dp
= &evex_len_table
[dp
->op
[1].bytemode
][vindex
];
11510 case USE_XOP_8F_TABLE
:
11511 FETCH_DATA (info
, codep
+ 3);
11512 rex
= ~(*codep
>> 5) & 0x7;
11514 /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */
11515 switch ((*codep
& 0x1f))
11521 vex_table_index
= XOP_08
;
11524 vex_table_index
= XOP_09
;
11527 vex_table_index
= XOP_0A
;
11531 vex
.w
= *codep
& 0x80;
11532 if (vex
.w
&& address_mode
== mode_64bit
)
11535 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
11536 if (address_mode
!= mode_64bit
)
11538 /* In 16/32-bit mode REX_B is silently ignored. */
11542 vex
.length
= (*codep
& 0x4) ? 256 : 128;
11543 switch ((*codep
& 0x3))
11548 vex
.prefix
= DATA_PREFIX_OPCODE
;
11551 vex
.prefix
= REPE_PREFIX_OPCODE
;
11554 vex
.prefix
= REPNE_PREFIX_OPCODE
;
11561 dp
= &xop_table
[vex_table_index
][vindex
];
11564 FETCH_DATA (info
, codep
+ 1);
11565 modrm
.mod
= (*codep
>> 6) & 3;
11566 modrm
.reg
= (*codep
>> 3) & 7;
11567 modrm
.rm
= *codep
& 7;
11570 case USE_VEX_C4_TABLE
:
11572 FETCH_DATA (info
, codep
+ 3);
11573 rex
= ~(*codep
>> 5) & 0x7;
11574 switch ((*codep
& 0x1f))
11580 vex_table_index
= VEX_0F
;
11583 vex_table_index
= VEX_0F38
;
11586 vex_table_index
= VEX_0F3A
;
11590 vex
.w
= *codep
& 0x80;
11591 if (address_mode
== mode_64bit
)
11598 /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
11599 is ignored, other REX bits are 0 and the highest bit in
11600 VEX.vvvv is also ignored (but we mustn't clear it here). */
11603 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
11604 vex
.length
= (*codep
& 0x4) ? 256 : 128;
11605 switch ((*codep
& 0x3))
11610 vex
.prefix
= DATA_PREFIX_OPCODE
;
11613 vex
.prefix
= REPE_PREFIX_OPCODE
;
11616 vex
.prefix
= REPNE_PREFIX_OPCODE
;
11623 dp
= &vex_table
[vex_table_index
][vindex
];
11625 /* There is no MODRM byte for VEX0F 77. */
11626 if (vex_table_index
!= VEX_0F
|| vindex
!= 0x77)
11628 FETCH_DATA (info
, codep
+ 1);
11629 modrm
.mod
= (*codep
>> 6) & 3;
11630 modrm
.reg
= (*codep
>> 3) & 7;
11631 modrm
.rm
= *codep
& 7;
11635 case USE_VEX_C5_TABLE
:
11637 FETCH_DATA (info
, codep
+ 2);
11638 rex
= (*codep
& 0x80) ? 0 : REX_R
;
11640 /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
11642 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
11643 vex
.length
= (*codep
& 0x4) ? 256 : 128;
11644 switch ((*codep
& 0x3))
11649 vex
.prefix
= DATA_PREFIX_OPCODE
;
11652 vex
.prefix
= REPE_PREFIX_OPCODE
;
11655 vex
.prefix
= REPNE_PREFIX_OPCODE
;
11662 dp
= &vex_table
[dp
->op
[1].bytemode
][vindex
];
11664 /* There is no MODRM byte for VEX 77. */
11665 if (vindex
!= 0x77)
11667 FETCH_DATA (info
, codep
+ 1);
11668 modrm
.mod
= (*codep
>> 6) & 3;
11669 modrm
.reg
= (*codep
>> 3) & 7;
11670 modrm
.rm
= *codep
& 7;
11674 case USE_VEX_W_TABLE
:
11678 dp
= &vex_w_table
[dp
->op
[1].bytemode
][vex
.w
? 1 : 0];
11681 case USE_EVEX_TABLE
:
11682 two_source_ops
= 0;
11685 FETCH_DATA (info
, codep
+ 4);
11686 /* The first byte after 0x62. */
11687 rex
= ~(*codep
>> 5) & 0x7;
11688 vex
.r
= *codep
& 0x10;
11689 switch ((*codep
& 0xf))
11692 return &bad_opcode
;
11694 vex_table_index
= EVEX_0F
;
11697 vex_table_index
= EVEX_0F38
;
11700 vex_table_index
= EVEX_0F3A
;
11704 /* The second byte after 0x62. */
11706 vex
.w
= *codep
& 0x80;
11707 if (vex
.w
&& address_mode
== mode_64bit
)
11710 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
11713 if (!(*codep
& 0x4))
11714 return &bad_opcode
;
11716 switch ((*codep
& 0x3))
11721 vex
.prefix
= DATA_PREFIX_OPCODE
;
11724 vex
.prefix
= REPE_PREFIX_OPCODE
;
11727 vex
.prefix
= REPNE_PREFIX_OPCODE
;
11731 /* The third byte after 0x62. */
11734 /* Remember the static rounding bits. */
11735 vex
.ll
= (*codep
>> 5) & 3;
11736 vex
.b
= (*codep
& 0x10) != 0;
11738 vex
.v
= *codep
& 0x8;
11739 vex
.mask_register_specifier
= *codep
& 0x7;
11740 vex
.zeroing
= *codep
& 0x80;
11742 if (address_mode
!= mode_64bit
)
11744 /* In 16/32-bit mode silently ignore following bits. */
11754 dp
= &evex_table
[vex_table_index
][vindex
];
11756 FETCH_DATA (info
, codep
+ 1);
11757 modrm
.mod
= (*codep
>> 6) & 3;
11758 modrm
.reg
= (*codep
>> 3) & 7;
11759 modrm
.rm
= *codep
& 7;
11761 /* Set vector length. */
11762 if (modrm
.mod
== 3 && vex
.b
)
11778 return &bad_opcode
;
11791 if (dp
->name
!= NULL
)
11794 return get_valid_dis386 (dp
, info
);
11798 get_sib (disassemble_info
*info
, int sizeflag
)
11800 /* If modrm.mod == 3, operand must be register. */
11802 && ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
11806 FETCH_DATA (info
, codep
+ 2);
11807 sib
.index
= (codep
[1] >> 3) & 7;
11808 sib
.scale
= (codep
[1] >> 6) & 3;
11809 sib
.base
= codep
[1] & 7;
11814 print_insn (bfd_vma pc
, disassemble_info
*info
)
11816 const struct dis386
*dp
;
11818 char *op_txt
[MAX_OPERANDS
];
11820 int sizeflag
, orig_sizeflag
;
11822 struct dis_private priv
;
11825 priv
.orig_sizeflag
= AFLAG
| DFLAG
;
11826 if ((info
->mach
& bfd_mach_i386_i386
) != 0)
11827 address_mode
= mode_32bit
;
11828 else if (info
->mach
== bfd_mach_i386_i8086
)
11830 address_mode
= mode_16bit
;
11831 priv
.orig_sizeflag
= 0;
11834 address_mode
= mode_64bit
;
11836 if (intel_syntax
== (char) -1)
11837 intel_syntax
= (info
->mach
& bfd_mach_i386_intel_syntax
) != 0;
11839 for (p
= info
->disassembler_options
; p
!= NULL
; )
11841 if (CONST_STRNEQ (p
, "amd64"))
11843 else if (CONST_STRNEQ (p
, "intel64"))
11845 else if (CONST_STRNEQ (p
, "x86-64"))
11847 address_mode
= mode_64bit
;
11848 priv
.orig_sizeflag
|= AFLAG
| DFLAG
;
11850 else if (CONST_STRNEQ (p
, "i386"))
11852 address_mode
= mode_32bit
;
11853 priv
.orig_sizeflag
|= AFLAG
| DFLAG
;
11855 else if (CONST_STRNEQ (p
, "i8086"))
11857 address_mode
= mode_16bit
;
11858 priv
.orig_sizeflag
&= ~(AFLAG
| DFLAG
);
11860 else if (CONST_STRNEQ (p
, "intel"))
11863 if (CONST_STRNEQ (p
+ 5, "-mnemonic"))
11864 intel_mnemonic
= 1;
11866 else if (CONST_STRNEQ (p
, "att"))
11869 if (CONST_STRNEQ (p
+ 3, "-mnemonic"))
11870 intel_mnemonic
= 0;
11872 else if (CONST_STRNEQ (p
, "addr"))
11874 if (address_mode
== mode_64bit
)
11876 if (p
[4] == '3' && p
[5] == '2')
11877 priv
.orig_sizeflag
&= ~AFLAG
;
11878 else if (p
[4] == '6' && p
[5] == '4')
11879 priv
.orig_sizeflag
|= AFLAG
;
11883 if (p
[4] == '1' && p
[5] == '6')
11884 priv
.orig_sizeflag
&= ~AFLAG
;
11885 else if (p
[4] == '3' && p
[5] == '2')
11886 priv
.orig_sizeflag
|= AFLAG
;
11889 else if (CONST_STRNEQ (p
, "data"))
11891 if (p
[4] == '1' && p
[5] == '6')
11892 priv
.orig_sizeflag
&= ~DFLAG
;
11893 else if (p
[4] == '3' && p
[5] == '2')
11894 priv
.orig_sizeflag
|= DFLAG
;
11896 else if (CONST_STRNEQ (p
, "suffix"))
11897 priv
.orig_sizeflag
|= SUFFIX_ALWAYS
;
11899 p
= strchr (p
, ',');
11904 if (address_mode
== mode_64bit
&& sizeof (bfd_vma
) < 8)
11906 (*info
->fprintf_func
) (info
->stream
,
11907 _("64-bit address is disabled"));
11913 names64
= intel_names64
;
11914 names32
= intel_names32
;
11915 names16
= intel_names16
;
11916 names8
= intel_names8
;
11917 names8rex
= intel_names8rex
;
11918 names_seg
= intel_names_seg
;
11919 names_mm
= intel_names_mm
;
11920 names_bnd
= intel_names_bnd
;
11921 names_xmm
= intel_names_xmm
;
11922 names_ymm
= intel_names_ymm
;
11923 names_zmm
= intel_names_zmm
;
11924 index64
= intel_index64
;
11925 index32
= intel_index32
;
11926 names_mask
= intel_names_mask
;
11927 index16
= intel_index16
;
11930 separator_char
= '+';
11935 names64
= att_names64
;
11936 names32
= att_names32
;
11937 names16
= att_names16
;
11938 names8
= att_names8
;
11939 names8rex
= att_names8rex
;
11940 names_seg
= att_names_seg
;
11941 names_mm
= att_names_mm
;
11942 names_bnd
= att_names_bnd
;
11943 names_xmm
= att_names_xmm
;
11944 names_ymm
= att_names_ymm
;
11945 names_zmm
= att_names_zmm
;
11946 index64
= att_index64
;
11947 index32
= att_index32
;
11948 names_mask
= att_names_mask
;
11949 index16
= att_index16
;
11952 separator_char
= ',';
11956 /* The output looks better if we put 7 bytes on a line, since that
11957 puts most long word instructions on a single line. Use 8 bytes
11959 if ((info
->mach
& bfd_mach_l1om
) != 0)
11960 info
->bytes_per_line
= 8;
11962 info
->bytes_per_line
= 7;
11964 info
->private_data
= &priv
;
11965 priv
.max_fetched
= priv
.the_buffer
;
11966 priv
.insn_start
= pc
;
11969 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
11977 start_codep
= priv
.the_buffer
;
11978 codep
= priv
.the_buffer
;
11980 if (OPCODES_SIGSETJMP (priv
.bailout
) != 0)
11984 /* Getting here means we tried for data but didn't get it. That
11985 means we have an incomplete instruction of some sort. Just
11986 print the first byte as a prefix or a .byte pseudo-op. */
11987 if (codep
> priv
.the_buffer
)
11989 name
= prefix_name (priv
.the_buffer
[0], priv
.orig_sizeflag
);
11991 (*info
->fprintf_func
) (info
->stream
, "%s", name
);
11994 /* Just print the first byte as a .byte instruction. */
11995 (*info
->fprintf_func
) (info
->stream
, ".byte 0x%x",
11996 (unsigned int) priv
.the_buffer
[0]);
12006 sizeflag
= priv
.orig_sizeflag
;
12008 if (!ckprefix () || rex_used
)
12010 /* Too many prefixes or unused REX prefixes. */
12012 i
< (int) ARRAY_SIZE (all_prefixes
) && all_prefixes
[i
];
12014 (*info
->fprintf_func
) (info
->stream
, "%s%s",
12016 prefix_name (all_prefixes
[i
], sizeflag
));
12020 insn_codep
= codep
;
12022 FETCH_DATA (info
, codep
+ 1);
12023 two_source_ops
= (*codep
== 0x62) || (*codep
== 0xc8);
12025 if (((prefixes
& PREFIX_FWAIT
)
12026 && ((*codep
< 0xd8) || (*codep
> 0xdf))))
12028 /* Handle prefixes before fwait. */
12029 for (i
= 0; i
< fwait_prefix
&& all_prefixes
[i
];
12031 (*info
->fprintf_func
) (info
->stream
, "%s ",
12032 prefix_name (all_prefixes
[i
], sizeflag
));
12033 (*info
->fprintf_func
) (info
->stream
, "fwait");
12037 if (*codep
== 0x0f)
12039 unsigned char threebyte
;
12042 FETCH_DATA (info
, codep
+ 1);
12043 threebyte
= *codep
;
12044 dp
= &dis386_twobyte
[threebyte
];
12045 need_modrm
= twobyte_has_modrm
[*codep
];
12050 dp
= &dis386
[*codep
];
12051 need_modrm
= onebyte_has_modrm
[*codep
];
12055 /* Save sizeflag for printing the extra prefixes later before updating
12056 it for mnemonic and operand processing. The prefix names depend
12057 only on the address mode. */
12058 orig_sizeflag
= sizeflag
;
12059 if (prefixes
& PREFIX_ADDR
)
12061 if ((prefixes
& PREFIX_DATA
))
12067 FETCH_DATA (info
, codep
+ 1);
12068 modrm
.mod
= (*codep
>> 6) & 3;
12069 modrm
.reg
= (*codep
>> 3) & 7;
12070 modrm
.rm
= *codep
& 7;
12076 memset (&vex
, 0, sizeof (vex
));
12078 if (dp
->name
== NULL
&& dp
->op
[0].bytemode
== FLOATCODE
)
12080 get_sib (info
, sizeflag
);
12081 dofloat (sizeflag
);
12085 dp
= get_valid_dis386 (dp
, info
);
12086 if (dp
!= NULL
&& putop (dp
->name
, sizeflag
) == 0)
12088 get_sib (info
, sizeflag
);
12089 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
12092 op_ad
= MAX_OPERANDS
- 1 - i
;
12094 (*dp
->op
[i
].rtn
) (dp
->op
[i
].bytemode
, sizeflag
);
12095 /* For EVEX instruction after the last operand masking
12096 should be printed. */
12097 if (i
== 0 && vex
.evex
)
12099 /* Don't print {%k0}. */
12100 if (vex
.mask_register_specifier
)
12103 oappend (names_mask
[vex
.mask_register_specifier
]);
12113 /* Clear instruction information. */
12116 the_info
->insn_info_valid
= 0;
12117 the_info
->branch_delay_insns
= 0;
12118 the_info
->data_size
= 0;
12119 the_info
->insn_type
= dis_noninsn
;
12120 the_info
->target
= 0;
12121 the_info
->target2
= 0;
12124 /* Reset jump operation indicator. */
12125 op_is_jump
= FALSE
;
12128 int jump_detection
= 0;
12130 /* Extract flags. */
12131 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
12133 if ((dp
->op
[i
].rtn
== OP_J
)
12134 || (dp
->op
[i
].rtn
== OP_indirE
))
12135 jump_detection
|= 1;
12136 else if ((dp
->op
[i
].rtn
== BND_Fixup
)
12137 || (!dp
->op
[i
].rtn
&& !dp
->op
[i
].bytemode
))
12138 jump_detection
|= 2;
12139 else if ((dp
->op
[i
].bytemode
== cond_jump_mode
)
12140 || (dp
->op
[i
].bytemode
== loop_jcxz_mode
))
12141 jump_detection
|= 4;
12144 /* Determine if this is a jump or branch. */
12145 if ((jump_detection
& 0x3) == 0x3)
12148 if (jump_detection
& 0x4)
12149 the_info
->insn_type
= dis_condbranch
;
12151 the_info
->insn_type
=
12152 (dp
->name
&& !strncmp(dp
->name
, "call", 4))
12153 ? dis_jsr
: dis_branch
;
12157 /* If VEX.vvvv and EVEX.vvvv are unused, they must be all 1s, which
12158 are all 0s in inverted form. */
12159 if (need_vex
&& vex
.register_specifier
!= 0)
12161 (*info
->fprintf_func
) (info
->stream
, "(bad)");
12162 return end_codep
- priv
.the_buffer
;
12165 /* Check if the REX prefix is used. */
12166 if ((rex
^ rex_used
) == 0 && !need_vex
&& last_rex_prefix
>= 0)
12167 all_prefixes
[last_rex_prefix
] = 0;
12169 /* Check if the SEG prefix is used. */
12170 if ((prefixes
& (PREFIX_CS
| PREFIX_SS
| PREFIX_DS
| PREFIX_ES
12171 | PREFIX_FS
| PREFIX_GS
)) != 0
12172 && (used_prefixes
& active_seg_prefix
) != 0)
12173 all_prefixes
[last_seg_prefix
] = 0;
12175 /* Check if the ADDR prefix is used. */
12176 if ((prefixes
& PREFIX_ADDR
) != 0
12177 && (used_prefixes
& PREFIX_ADDR
) != 0)
12178 all_prefixes
[last_addr_prefix
] = 0;
12180 /* Check if the DATA prefix is used. */
12181 if ((prefixes
& PREFIX_DATA
) != 0
12182 && (used_prefixes
& PREFIX_DATA
) != 0
12184 all_prefixes
[last_data_prefix
] = 0;
12186 /* Print the extra prefixes. */
12188 for (i
= 0; i
< (int) ARRAY_SIZE (all_prefixes
); i
++)
12189 if (all_prefixes
[i
])
12192 name
= prefix_name (all_prefixes
[i
], orig_sizeflag
);
12195 prefix_length
+= strlen (name
) + 1;
12196 (*info
->fprintf_func
) (info
->stream
, "%s ", name
);
12199 /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
12200 unused, opcode is invalid. Since the PREFIX_DATA prefix may be
12201 used by putop and MMX/SSE operand and may be overriden by the
12202 PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
12204 if (dp
->prefix_requirement
== PREFIX_OPCODE
12206 ? vex
.prefix
== REPE_PREFIX_OPCODE
12207 || vex
.prefix
== REPNE_PREFIX_OPCODE
12209 & (PREFIX_REPZ
| PREFIX_REPNZ
)) != 0)
12211 & (PREFIX_REPZ
| PREFIX_REPNZ
)) == 0)
12213 ? vex
.prefix
== DATA_PREFIX_OPCODE
12215 & (PREFIX_REPZ
| PREFIX_REPNZ
| PREFIX_DATA
))
12217 && (used_prefixes
& PREFIX_DATA
) == 0))
12218 || (vex
.evex
&& !vex
.w
!= !(used_prefixes
& PREFIX_DATA
))))
12220 (*info
->fprintf_func
) (info
->stream
, "(bad)");
12221 return end_codep
- priv
.the_buffer
;
12224 /* Check maximum code length. */
12225 if ((codep
- start_codep
) > MAX_CODE_LENGTH
)
12227 (*info
->fprintf_func
) (info
->stream
, "(bad)");
12228 return MAX_CODE_LENGTH
;
12231 obufp
= mnemonicendp
;
12232 for (i
= strlen (obuf
) + prefix_length
; i
< 6; i
++)
12235 (*info
->fprintf_func
) (info
->stream
, "%s", obuf
);
12237 /* The enter and bound instructions are printed with operands in the same
12238 order as the intel book; everything else is printed in reverse order. */
12239 if (intel_syntax
|| two_source_ops
)
12243 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
12244 op_txt
[i
] = op_out
[i
];
12246 if (intel_syntax
&& dp
&& dp
->op
[2].rtn
== OP_Rounding
12247 && dp
->op
[3].rtn
== OP_E
&& dp
->op
[4].rtn
== NULL
)
12249 op_txt
[2] = op_out
[3];
12250 op_txt
[3] = op_out
[2];
12253 for (i
= 0; i
< (MAX_OPERANDS
>> 1); ++i
)
12255 op_ad
= op_index
[i
];
12256 op_index
[i
] = op_index
[MAX_OPERANDS
- 1 - i
];
12257 op_index
[MAX_OPERANDS
- 1 - i
] = op_ad
;
12258 riprel
= op_riprel
[i
];
12259 op_riprel
[i
] = op_riprel
[MAX_OPERANDS
- 1 - i
];
12260 op_riprel
[MAX_OPERANDS
- 1 - i
] = riprel
;
12265 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
12266 op_txt
[MAX_OPERANDS
- 1 - i
] = op_out
[i
];
12270 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
12274 (*info
->fprintf_func
) (info
->stream
, ",");
12275 if (op_index
[i
] != -1 && !op_riprel
[i
])
12277 bfd_vma target
= (bfd_vma
) op_address
[op_index
[i
]];
12279 if (the_info
&& op_is_jump
)
12281 the_info
->insn_info_valid
= 1;
12282 the_info
->branch_delay_insns
= 0;
12283 the_info
->data_size
= 0;
12284 the_info
->target
= target
;
12285 the_info
->target2
= 0;
12287 (*info
->print_address_func
) (target
, info
);
12290 (*info
->fprintf_func
) (info
->stream
, "%s", op_txt
[i
]);
12294 for (i
= 0; i
< MAX_OPERANDS
; i
++)
12295 if (op_index
[i
] != -1 && op_riprel
[i
])
12297 (*info
->fprintf_func
) (info
->stream
, " # ");
12298 (*info
->print_address_func
) ((bfd_vma
) (start_pc
+ (codep
- start_codep
)
12299 + op_address
[op_index
[i
]]), info
);
12302 return codep
- priv
.the_buffer
;
12305 static const char *float_mem
[] = {
12380 static const unsigned char float_mem_mode
[] = {
12455 #define ST { OP_ST, 0 }
12456 #define STi { OP_STi, 0 }
12458 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
12459 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
12460 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
12461 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
12462 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
12463 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
12464 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
12465 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
12466 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
12468 static const struct dis386 float_reg
[][8] = {
12471 { "fadd", { ST
, STi
}, 0 },
12472 { "fmul", { ST
, STi
}, 0 },
12473 { "fcom", { STi
}, 0 },
12474 { "fcomp", { STi
}, 0 },
12475 { "fsub", { ST
, STi
}, 0 },
12476 { "fsubr", { ST
, STi
}, 0 },
12477 { "fdiv", { ST
, STi
}, 0 },
12478 { "fdivr", { ST
, STi
}, 0 },
12482 { "fld", { STi
}, 0 },
12483 { "fxch", { STi
}, 0 },
12493 { "fcmovb", { ST
, STi
}, 0 },
12494 { "fcmove", { ST
, STi
}, 0 },
12495 { "fcmovbe",{ ST
, STi
}, 0 },
12496 { "fcmovu", { ST
, STi
}, 0 },
12504 { "fcmovnb",{ ST
, STi
}, 0 },
12505 { "fcmovne",{ ST
, STi
}, 0 },
12506 { "fcmovnbe",{ ST
, STi
}, 0 },
12507 { "fcmovnu",{ ST
, STi
}, 0 },
12509 { "fucomi", { ST
, STi
}, 0 },
12510 { "fcomi", { ST
, STi
}, 0 },
12515 { "fadd", { STi
, ST
}, 0 },
12516 { "fmul", { STi
, ST
}, 0 },
12519 { "fsub{!M|r}", { STi
, ST
}, 0 },
12520 { "fsub{M|}", { STi
, ST
}, 0 },
12521 { "fdiv{!M|r}", { STi
, ST
}, 0 },
12522 { "fdiv{M|}", { STi
, ST
}, 0 },
12526 { "ffree", { STi
}, 0 },
12528 { "fst", { STi
}, 0 },
12529 { "fstp", { STi
}, 0 },
12530 { "fucom", { STi
}, 0 },
12531 { "fucomp", { STi
}, 0 },
12537 { "faddp", { STi
, ST
}, 0 },
12538 { "fmulp", { STi
, ST
}, 0 },
12541 { "fsub{!M|r}p", { STi
, ST
}, 0 },
12542 { "fsub{M|}p", { STi
, ST
}, 0 },
12543 { "fdiv{!M|r}p", { STi
, ST
}, 0 },
12544 { "fdiv{M|}p", { STi
, ST
}, 0 },
12548 { "ffreep", { STi
}, 0 },
12553 { "fucomip", { ST
, STi
}, 0 },
12554 { "fcomip", { ST
, STi
}, 0 },
12559 static char *fgrps
[][8] = {
12562 "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12567 "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12572 "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
12577 "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
12582 "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
12587 "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
12592 "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12597 "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
12598 "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
12603 "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12608 "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12613 swap_operand (void)
12615 mnemonicendp
[0] = '.';
12616 mnemonicendp
[1] = 's';
12621 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED
,
12622 int sizeflag ATTRIBUTE_UNUSED
)
12624 /* Skip mod/rm byte. */
12630 dofloat (int sizeflag
)
12632 const struct dis386
*dp
;
12633 unsigned char floatop
;
12635 floatop
= codep
[-1];
12637 if (modrm
.mod
!= 3)
12639 int fp_indx
= (floatop
- 0xd8) * 8 + modrm
.reg
;
12641 putop (float_mem
[fp_indx
], sizeflag
);
12644 OP_E (float_mem_mode
[fp_indx
], sizeflag
);
12647 /* Skip mod/rm byte. */
12651 dp
= &float_reg
[floatop
- 0xd8][modrm
.reg
];
12652 if (dp
->name
== NULL
)
12654 putop (fgrps
[dp
->op
[0].bytemode
][modrm
.rm
], sizeflag
);
12656 /* Instruction fnstsw is only one with strange arg. */
12657 if (floatop
== 0xdf && codep
[-1] == 0xe0)
12658 strcpy (op_out
[0], names16
[0]);
12662 putop (dp
->name
, sizeflag
);
12667 (*dp
->op
[0].rtn
) (dp
->op
[0].bytemode
, sizeflag
);
12672 (*dp
->op
[1].rtn
) (dp
->op
[1].bytemode
, sizeflag
);
12676 /* Like oappend (below), but S is a string starting with '%'.
12677 In Intel syntax, the '%' is elided. */
12679 oappend_maybe_intel (const char *s
)
12681 oappend (s
+ intel_syntax
);
12685 OP_ST (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
12687 oappend_maybe_intel ("%st");
12691 OP_STi (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
12693 sprintf (scratchbuf
, "%%st(%d)", modrm
.rm
);
12694 oappend_maybe_intel (scratchbuf
);
12697 /* Capital letters in template are macros. */
12699 putop (const char *in_template
, int sizeflag
)
12704 unsigned int l
= 0, len
= 1;
12707 #define SAVE_LAST(c) \
12708 if (l < len && l < sizeof (last)) \
12713 for (p
= in_template
; *p
; p
++)
12729 while (*++p
!= '|')
12730 if (*p
== '}' || *p
== '\0')
12736 while (*++p
!= '}')
12748 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
12752 if (l
== 0 && len
== 1)
12757 if (sizeflag
& SUFFIX_ALWAYS
)
12770 if (address_mode
== mode_64bit
12771 && !(prefixes
& PREFIX_ADDR
))
12782 if (intel_syntax
&& !alt
)
12784 if ((prefixes
& PREFIX_DATA
) || (sizeflag
& SUFFIX_ALWAYS
))
12786 if (sizeflag
& DFLAG
)
12787 *obufp
++ = intel_syntax
? 'd' : 'l';
12789 *obufp
++ = intel_syntax
? 'w' : 's';
12790 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12794 if (intel_syntax
|| !(sizeflag
& SUFFIX_ALWAYS
))
12797 if (modrm
.mod
== 3)
12803 if (sizeflag
& DFLAG
)
12804 *obufp
++ = intel_syntax
? 'd' : 'l';
12807 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12813 case 'E': /* For jcxz/jecxz */
12814 if (address_mode
== mode_64bit
)
12816 if (sizeflag
& AFLAG
)
12822 if (sizeflag
& AFLAG
)
12824 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
12829 if ((prefixes
& PREFIX_ADDR
) || (sizeflag
& SUFFIX_ALWAYS
))
12831 if (sizeflag
& AFLAG
)
12832 *obufp
++ = address_mode
== mode_64bit
? 'q' : 'l';
12834 *obufp
++ = address_mode
== mode_64bit
? 'l' : 'w';
12835 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
12839 if (intel_syntax
|| (obufp
[-1] != 's' && !(sizeflag
& SUFFIX_ALWAYS
)))
12841 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
12845 if (!(rex
& REX_W
))
12846 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12851 if ((prefixes
& (PREFIX_CS
| PREFIX_DS
)) == PREFIX_CS
12852 || (prefixes
& (PREFIX_CS
| PREFIX_DS
)) == PREFIX_DS
)
12854 used_prefixes
|= prefixes
& (PREFIX_CS
| PREFIX_DS
);
12857 if (prefixes
& PREFIX_DS
)
12871 if (l
!= 0 || len
!= 1)
12873 if (l
!= 1 || len
!= 2 || last
[0] != 'X')
12878 if (!need_vex
|| !vex
.evex
)
12881 || ((modrm
.mod
== 3 || vex
.b
) && !(sizeflag
& SUFFIX_ALWAYS
)))
12883 switch (vex
.length
)
12901 if (address_mode
== mode_64bit
&& (sizeflag
& SUFFIX_ALWAYS
))
12906 /* Fall through. */
12909 if (l
!= 0 || len
!= 1)
12917 if (sizeflag
& SUFFIX_ALWAYS
)
12921 if (intel_mnemonic
!= cond
)
12925 if ((prefixes
& PREFIX_FWAIT
) == 0)
12928 used_prefixes
|= PREFIX_FWAIT
;
12934 else if (intel_syntax
&& (sizeflag
& DFLAG
))
12938 if (!(rex
& REX_W
))
12939 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12943 && address_mode
== mode_64bit
12944 && isa64
== intel64
)
12949 /* Fall through. */
12952 && address_mode
== mode_64bit
12953 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
12958 /* Fall through. */
12961 if (l
== 0 && len
== 1)
12966 if ((rex
& REX_W
) == 0
12967 && (prefixes
& PREFIX_DATA
))
12969 if ((sizeflag
& DFLAG
) == 0)
12971 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12975 if ((prefixes
& PREFIX_DATA
)
12977 || (sizeflag
& SUFFIX_ALWAYS
))
12984 if (sizeflag
& DFLAG
)
12988 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12994 if (l
!= 1 || len
!= 2 || last
[0] != 'L')
13000 if ((prefixes
& PREFIX_DATA
)
13002 || (sizeflag
& SUFFIX_ALWAYS
))
13009 if (sizeflag
& DFLAG
)
13010 *obufp
++ = intel_syntax
? 'd' : 'l';
13013 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13021 if (address_mode
== mode_64bit
13022 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
13024 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
13028 /* Fall through. */
13031 if (l
== 0 && len
== 1)
13034 if (intel_syntax
&& !alt
)
13037 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
13043 if (sizeflag
& DFLAG
)
13044 *obufp
++ = intel_syntax
? 'd' : 'l';
13047 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13053 if (l
!= 1 || len
!= 2 || last
[0] != 'L')
13058 if ((intel_syntax
&& need_modrm
)
13059 || (modrm
.mod
== 3 && !(sizeflag
& SUFFIX_ALWAYS
)))
13066 else if((address_mode
== mode_64bit
&& need_modrm
)
13067 || (sizeflag
& SUFFIX_ALWAYS
))
13068 *obufp
++ = intel_syntax
? 'd' : 'l';
13075 else if (sizeflag
& DFLAG
)
13084 if (intel_syntax
&& !p
[1]
13085 && ((rex
& REX_W
) || (sizeflag
& DFLAG
)))
13087 if (!(rex
& REX_W
))
13088 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13091 if (l
== 0 && len
== 1)
13095 if (address_mode
== mode_64bit
13096 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
13098 if (sizeflag
& SUFFIX_ALWAYS
)
13120 /* Fall through. */
13123 if (l
== 0 && len
== 1)
13128 if (sizeflag
& SUFFIX_ALWAYS
)
13134 if (sizeflag
& DFLAG
)
13138 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13152 if (address_mode
== mode_64bit
13153 && !(prefixes
& PREFIX_ADDR
))
13164 if (l
!= 0 || len
!= 1)
13170 ? vex
.prefix
== DATA_PREFIX_OPCODE
13171 : prefixes
& PREFIX_DATA
)
13174 used_prefixes
|= PREFIX_DATA
;
13180 if (l
== 0 && len
== 1)
13184 if (l
!= 1 || len
!= 2 || last
[0] != 'X')
13192 || ((modrm
.mod
== 3 || vex
.b
) && !(sizeflag
& SUFFIX_ALWAYS
)))
13194 switch (vex
.length
)
13210 if (l
== 0 && len
== 1)
13212 /* operand size flag for cwtl, cbtw */
13221 else if (sizeflag
& DFLAG
)
13225 if (!(rex
& REX_W
))
13226 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13233 && last
[0] != 'L'))
13240 if (last
[0] == 'X')
13241 *obufp
++ = vex
.w
? 'd': 's';
13243 *obufp
++ = vex
.w
? 'q': 'd';
13249 if (isa64
== intel64
&& (rex
& REX_W
))
13255 if ((prefixes
& PREFIX_DATA
) || (sizeflag
& SUFFIX_ALWAYS
))
13257 if (sizeflag
& DFLAG
)
13261 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13267 if (address_mode
== mode_64bit
13268 && (isa64
== intel64
13269 || ((sizeflag
& DFLAG
) || (rex
& REX_W
))))
13271 else if ((prefixes
& PREFIX_DATA
))
13273 if (!(sizeflag
& DFLAG
))
13275 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13281 mnemonicendp
= obufp
;
13286 oappend (const char *s
)
13288 obufp
= stpcpy (obufp
, s
);
13294 /* Only print the active segment register. */
13295 if (!active_seg_prefix
)
13298 used_prefixes
|= active_seg_prefix
;
13299 switch (active_seg_prefix
)
13302 oappend_maybe_intel ("%cs:");
13305 oappend_maybe_intel ("%ds:");
13308 oappend_maybe_intel ("%ss:");
13311 oappend_maybe_intel ("%es:");
13314 oappend_maybe_intel ("%fs:");
13317 oappend_maybe_intel ("%gs:");
13325 OP_indirE (int bytemode
, int sizeflag
)
13329 OP_E (bytemode
, sizeflag
);
13333 print_operand_value (char *buf
, int hex
, bfd_vma disp
)
13335 if (address_mode
== mode_64bit
)
13343 sprintf_vma (tmp
, disp
);
13344 for (i
= 0; tmp
[i
] == '0' && tmp
[i
+ 1]; i
++);
13345 strcpy (buf
+ 2, tmp
+ i
);
13349 bfd_signed_vma v
= disp
;
13356 /* Check for possible overflow on 0x8000000000000000. */
13359 strcpy (buf
, "9223372036854775808");
13373 tmp
[28 - i
] = (v
% 10) + '0';
13377 strcpy (buf
, tmp
+ 29 - i
);
13383 sprintf (buf
, "0x%x", (unsigned int) disp
);
13385 sprintf (buf
, "%d", (int) disp
);
13389 /* Put DISP in BUF as signed hex number. */
13392 print_displacement (char *buf
, bfd_vma disp
)
13394 bfd_signed_vma val
= disp
;
13403 /* Check for possible overflow. */
13406 switch (address_mode
)
13409 strcpy (buf
+ j
, "0x8000000000000000");
13412 strcpy (buf
+ j
, "0x80000000");
13415 strcpy (buf
+ j
, "0x8000");
13425 sprintf_vma (tmp
, (bfd_vma
) val
);
13426 for (i
= 0; tmp
[i
] == '0'; i
++)
13428 if (tmp
[i
] == '\0')
13430 strcpy (buf
+ j
, tmp
+ i
);
13434 intel_operand_size (int bytemode
, int sizeflag
)
13438 && (bytemode
== x_mode
13439 || bytemode
== evex_half_bcst_xmmq_mode
))
13442 oappend ("QWORD PTR ");
13444 oappend ("DWORD PTR ");
13453 oappend ("BYTE PTR ");
13458 oappend ("WORD PTR ");
13461 if (address_mode
== mode_64bit
&& isa64
== intel64
)
13463 oappend ("QWORD PTR ");
13466 /* Fall through. */
13468 if (address_mode
== mode_64bit
&& ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
13470 oappend ("QWORD PTR ");
13473 /* Fall through. */
13479 oappend ("QWORD PTR ");
13482 if ((sizeflag
& DFLAG
) || bytemode
== dq_mode
)
13483 oappend ("DWORD PTR ");
13485 oappend ("WORD PTR ");
13486 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13490 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
13492 oappend ("WORD PTR ");
13493 if (!(rex
& REX_W
))
13494 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13497 if (sizeflag
& DFLAG
)
13498 oappend ("QWORD PTR ");
13500 oappend ("DWORD PTR ");
13501 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13504 if (!(sizeflag
& DFLAG
) && isa64
== intel64
)
13505 oappend ("WORD PTR ");
13507 oappend ("DWORD PTR ");
13508 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13511 case d_scalar_swap_mode
:
13514 oappend ("DWORD PTR ");
13517 case q_scalar_swap_mode
:
13519 oappend ("QWORD PTR ");
13522 if (address_mode
== mode_64bit
)
13523 oappend ("QWORD PTR ");
13525 oappend ("DWORD PTR ");
13528 if (sizeflag
& DFLAG
)
13529 oappend ("FWORD PTR ");
13531 oappend ("DWORD PTR ");
13532 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13535 oappend ("TBYTE PTR ");
13539 case evex_x_gscat_mode
:
13540 case evex_x_nobcst_mode
:
13541 case b_scalar_mode
:
13542 case w_scalar_mode
:
13545 switch (vex
.length
)
13548 oappend ("XMMWORD PTR ");
13551 oappend ("YMMWORD PTR ");
13554 oappend ("ZMMWORD PTR ");
13561 oappend ("XMMWORD PTR ");
13564 oappend ("XMMWORD PTR ");
13567 oappend ("YMMWORD PTR ");
13570 case evex_half_bcst_xmmq_mode
:
13574 switch (vex
.length
)
13577 oappend ("QWORD PTR ");
13580 oappend ("XMMWORD PTR ");
13583 oappend ("YMMWORD PTR ");
13593 switch (vex
.length
)
13598 oappend ("BYTE PTR ");
13608 switch (vex
.length
)
13613 oappend ("WORD PTR ");
13623 switch (vex
.length
)
13628 oappend ("DWORD PTR ");
13638 switch (vex
.length
)
13643 oappend ("QWORD PTR ");
13653 switch (vex
.length
)
13656 oappend ("WORD PTR ");
13659 oappend ("DWORD PTR ");
13662 oappend ("QWORD PTR ");
13672 switch (vex
.length
)
13675 oappend ("DWORD PTR ");
13678 oappend ("QWORD PTR ");
13681 oappend ("XMMWORD PTR ");
13691 switch (vex
.length
)
13694 oappend ("QWORD PTR ");
13697 oappend ("YMMWORD PTR ");
13700 oappend ("ZMMWORD PTR ");
13710 switch (vex
.length
)
13714 oappend ("XMMWORD PTR ");
13721 oappend ("OWORD PTR ");
13723 case vex_scalar_w_dq_mode
:
13728 oappend ("QWORD PTR ");
13730 oappend ("DWORD PTR ");
13732 case vex_vsib_d_w_dq_mode
:
13733 case vex_vsib_q_w_dq_mode
:
13740 oappend ("QWORD PTR ");
13742 oappend ("DWORD PTR ");
13746 switch (vex
.length
)
13749 oappend ("XMMWORD PTR ");
13752 oappend ("YMMWORD PTR ");
13755 oappend ("ZMMWORD PTR ");
13762 case vex_vsib_q_w_d_mode
:
13763 case vex_vsib_d_w_d_mode
:
13764 if (!need_vex
|| !vex
.evex
)
13767 switch (vex
.length
)
13770 oappend ("QWORD PTR ");
13773 oappend ("XMMWORD PTR ");
13776 oappend ("YMMWORD PTR ");
13784 if (!need_vex
|| vex
.length
!= 128)
13787 oappend ("DWORD PTR ");
13789 oappend ("BYTE PTR ");
13795 oappend ("QWORD PTR ");
13797 oappend ("WORD PTR ");
13807 OP_E_register (int bytemode
, int sizeflag
)
13809 int reg
= modrm
.rm
;
13810 const char **names
;
13816 if ((sizeflag
& SUFFIX_ALWAYS
)
13817 && (bytemode
== b_swap_mode
13818 || bytemode
== bnd_swap_mode
13819 || bytemode
== v_swap_mode
))
13845 names
= address_mode
== mode_64bit
? names64
: names32
;
13848 case bnd_swap_mode
:
13857 if (address_mode
== mode_64bit
&& isa64
== intel64
)
13862 /* Fall through. */
13864 if (address_mode
== mode_64bit
&& ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
13870 /* Fall through. */
13882 if ((sizeflag
& DFLAG
)
13883 || (bytemode
!= v_mode
13884 && bytemode
!= v_swap_mode
))
13888 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13892 if (!(sizeflag
& DFLAG
) && isa64
== intel64
)
13896 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13899 names
= (address_mode
== mode_64bit
13900 ? names64
: names32
);
13901 if (!(prefixes
& PREFIX_ADDR
))
13902 names
= (address_mode
== mode_16bit
13903 ? names16
: names
);
13906 /* Remove "addr16/addr32". */
13907 all_prefixes
[last_addr_prefix
] = 0;
13908 names
= (address_mode
!= mode_32bit
13909 ? names32
: names16
);
13910 used_prefixes
|= PREFIX_ADDR
;
13920 names
= names_mask
;
13925 oappend (INTERNAL_DISASSEMBLER_ERROR
);
13928 oappend (names
[reg
]);
13932 OP_E_memory (int bytemode
, int sizeflag
)
13935 int add
= (rex
& REX_B
) ? 8 : 0;
13941 /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0. */
13943 && bytemode
!= x_mode
13944 && bytemode
!= xmmq_mode
13945 && bytemode
!= evex_half_bcst_xmmq_mode
)
13961 if (address_mode
!= mode_64bit
)
13967 case vex_scalar_w_dq_mode
:
13968 case vex_vsib_d_w_dq_mode
:
13969 case vex_vsib_d_w_d_mode
:
13970 case vex_vsib_q_w_dq_mode
:
13971 case vex_vsib_q_w_d_mode
:
13972 case evex_x_gscat_mode
:
13973 shift
= vex
.w
? 3 : 2;
13976 case evex_half_bcst_xmmq_mode
:
13980 shift
= vex
.w
? 3 : 2;
13983 /* Fall through. */
13987 case evex_x_nobcst_mode
:
13989 switch (vex
.length
)
14013 case q_scalar_swap_mode
:
14020 case d_scalar_swap_mode
:
14023 case w_scalar_mode
:
14027 case b_scalar_mode
:
14034 /* Make necessary corrections to shift for modes that need it.
14035 For these modes we currently have shift 4, 5 or 6 depending on
14036 vex.length (it corresponds to xmmword, ymmword or zmmword
14037 operand). We might want to make it 3, 4 or 5 (e.g. for
14038 xmmq_mode). In case of broadcast enabled the corrections
14039 aren't needed, as element size is always 32 or 64 bits. */
14041 && (bytemode
== xmmq_mode
14042 || bytemode
== evex_half_bcst_xmmq_mode
))
14044 else if (bytemode
== xmmqd_mode
)
14046 else if (bytemode
== xmmdw_mode
)
14048 else if (bytemode
== ymmq_mode
&& vex
.length
== 128)
14056 intel_operand_size (bytemode
, sizeflag
);
14059 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
14061 /* 32/64 bit address mode */
14071 int addr32flag
= !((sizeflag
& AFLAG
)
14072 || bytemode
== v_bnd_mode
14073 || bytemode
== v_bndmk_mode
14074 || bytemode
== bnd_mode
14075 || bytemode
== bnd_swap_mode
);
14076 const char **indexes64
= names64
;
14077 const char **indexes32
= names32
;
14087 vindex
= sib
.index
;
14093 case vex_vsib_d_w_dq_mode
:
14094 case vex_vsib_d_w_d_mode
:
14095 case vex_vsib_q_w_dq_mode
:
14096 case vex_vsib_q_w_d_mode
:
14106 switch (vex
.length
)
14109 indexes64
= indexes32
= names_xmm
;
14113 || bytemode
== vex_vsib_q_w_dq_mode
14114 || bytemode
== vex_vsib_q_w_d_mode
)
14115 indexes64
= indexes32
= names_ymm
;
14117 indexes64
= indexes32
= names_xmm
;
14121 || bytemode
== vex_vsib_q_w_dq_mode
14122 || bytemode
== vex_vsib_q_w_d_mode
)
14123 indexes64
= indexes32
= names_zmm
;
14125 indexes64
= indexes32
= names_ymm
;
14132 haveindex
= vindex
!= 4;
14139 rbase
= base
+ add
;
14147 if (address_mode
== mode_64bit
&& !havesib
)
14150 if (riprel
&& bytemode
== v_bndmk_mode
)
14158 FETCH_DATA (the_info
, codep
+ 1);
14160 if ((disp
& 0x80) != 0)
14162 if (vex
.evex
&& shift
> 0)
14175 && address_mode
!= mode_16bit
)
14177 if (address_mode
== mode_64bit
)
14179 /* Display eiz instead of addr32. */
14180 needindex
= addr32flag
;
14185 /* In 32-bit mode, we need index register to tell [offset]
14186 from [eiz*1 + offset]. */
14191 havedisp
= (havebase
14193 || (havesib
&& (haveindex
|| scale
!= 0)));
14196 if (modrm
.mod
!= 0 || base
== 5)
14198 if (havedisp
|| riprel
)
14199 print_displacement (scratchbuf
, disp
);
14201 print_operand_value (scratchbuf
, 1, disp
);
14202 oappend (scratchbuf
);
14206 oappend (!addr32flag
? "(%rip)" : "(%eip)");
14210 if ((havebase
|| haveindex
|| needindex
|| needaddr32
|| riprel
)
14211 && (address_mode
!= mode_64bit
14212 || ((bytemode
!= v_bnd_mode
)
14213 && (bytemode
!= v_bndmk_mode
)
14214 && (bytemode
!= bnd_mode
)
14215 && (bytemode
!= bnd_swap_mode
))))
14216 used_prefixes
|= PREFIX_ADDR
;
14218 if (havedisp
|| (intel_syntax
&& riprel
))
14220 *obufp
++ = open_char
;
14221 if (intel_syntax
&& riprel
)
14224 oappend (!addr32flag
? "rip" : "eip");
14228 oappend (address_mode
== mode_64bit
&& !addr32flag
14229 ? names64
[rbase
] : names32
[rbase
]);
14232 /* ESP/RSP won't allow index. If base isn't ESP/RSP,
14233 print index to tell base + index from base. */
14237 || (havebase
&& base
!= ESP_REG_NUM
))
14239 if (!intel_syntax
|| havebase
)
14241 *obufp
++ = separator_char
;
14245 oappend (address_mode
== mode_64bit
&& !addr32flag
14246 ? indexes64
[vindex
] : indexes32
[vindex
]);
14248 oappend (address_mode
== mode_64bit
&& !addr32flag
14249 ? index64
: index32
);
14251 *obufp
++ = scale_char
;
14253 sprintf (scratchbuf
, "%d", 1 << scale
);
14254 oappend (scratchbuf
);
14258 && (disp
|| modrm
.mod
!= 0 || base
== 5))
14260 if (!havedisp
|| (bfd_signed_vma
) disp
>= 0)
14265 else if (modrm
.mod
!= 1 && disp
!= -disp
)
14269 disp
= - (bfd_signed_vma
) disp
;
14273 print_displacement (scratchbuf
, disp
);
14275 print_operand_value (scratchbuf
, 1, disp
);
14276 oappend (scratchbuf
);
14279 *obufp
++ = close_char
;
14282 else if (intel_syntax
)
14284 if (modrm
.mod
!= 0 || base
== 5)
14286 if (!active_seg_prefix
)
14288 oappend (names_seg
[ds_reg
- es_reg
]);
14291 print_operand_value (scratchbuf
, 1, disp
);
14292 oappend (scratchbuf
);
14296 else if (bytemode
== v_bnd_mode
14297 || bytemode
== v_bndmk_mode
14298 || bytemode
== bnd_mode
14299 || bytemode
== bnd_swap_mode
)
14306 /* 16 bit address mode */
14307 used_prefixes
|= prefixes
& PREFIX_ADDR
;
14314 if ((disp
& 0x8000) != 0)
14319 FETCH_DATA (the_info
, codep
+ 1);
14321 if ((disp
& 0x80) != 0)
14323 if (vex
.evex
&& shift
> 0)
14328 if ((disp
& 0x8000) != 0)
14334 if (modrm
.mod
!= 0 || modrm
.rm
== 6)
14336 print_displacement (scratchbuf
, disp
);
14337 oappend (scratchbuf
);
14340 if (modrm
.mod
!= 0 || modrm
.rm
!= 6)
14342 *obufp
++ = open_char
;
14344 oappend (index16
[modrm
.rm
]);
14346 && (disp
|| modrm
.mod
!= 0 || modrm
.rm
== 6))
14348 if ((bfd_signed_vma
) disp
>= 0)
14353 else if (modrm
.mod
!= 1)
14357 disp
= - (bfd_signed_vma
) disp
;
14360 print_displacement (scratchbuf
, disp
);
14361 oappend (scratchbuf
);
14364 *obufp
++ = close_char
;
14367 else if (intel_syntax
)
14369 if (!active_seg_prefix
)
14371 oappend (names_seg
[ds_reg
- es_reg
]);
14374 print_operand_value (scratchbuf
, 1, disp
& 0xffff);
14375 oappend (scratchbuf
);
14378 if (vex
.evex
&& vex
.b
14379 && (bytemode
== x_mode
14380 || bytemode
== xmmq_mode
14381 || bytemode
== evex_half_bcst_xmmq_mode
))
14384 || bytemode
== xmmq_mode
14385 || bytemode
== evex_half_bcst_xmmq_mode
)
14387 switch (vex
.length
)
14390 oappend ("{1to2}");
14393 oappend ("{1to4}");
14396 oappend ("{1to8}");
14404 switch (vex
.length
)
14407 oappend ("{1to4}");
14410 oappend ("{1to8}");
14413 oappend ("{1to16}");
14423 OP_E (int bytemode
, int sizeflag
)
14425 /* Skip mod/rm byte. */
14429 if (modrm
.mod
== 3)
14430 OP_E_register (bytemode
, sizeflag
);
14432 OP_E_memory (bytemode
, sizeflag
);
14436 OP_G (int bytemode
, int sizeflag
)
14439 const char **names
;
14448 oappend (names8rex
[modrm
.reg
+ add
]);
14450 oappend (names8
[modrm
.reg
+ add
]);
14453 oappend (names16
[modrm
.reg
+ add
]);
14458 oappend (names32
[modrm
.reg
+ add
]);
14461 oappend (names64
[modrm
.reg
+ add
]);
14464 if (modrm
.reg
> 0x3)
14469 oappend (names_bnd
[modrm
.reg
]);
14479 oappend (names64
[modrm
.reg
+ add
]);
14482 if ((sizeflag
& DFLAG
)
14483 || (bytemode
!= v_mode
&& bytemode
!= movsxd_mode
))
14484 oappend (names32
[modrm
.reg
+ add
]);
14486 oappend (names16
[modrm
.reg
+ add
]);
14487 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14491 names
= (address_mode
== mode_64bit
14492 ? names64
: names32
);
14493 if (!(prefixes
& PREFIX_ADDR
))
14495 if (address_mode
== mode_16bit
)
14500 /* Remove "addr16/addr32". */
14501 all_prefixes
[last_addr_prefix
] = 0;
14502 names
= (address_mode
!= mode_32bit
14503 ? names32
: names16
);
14504 used_prefixes
|= PREFIX_ADDR
;
14506 oappend (names
[modrm
.reg
+ add
]);
14509 if (address_mode
== mode_64bit
)
14510 oappend (names64
[modrm
.reg
+ add
]);
14512 oappend (names32
[modrm
.reg
+ add
]);
14516 if ((modrm
.reg
+ add
) > 0x7)
14521 oappend (names_mask
[modrm
.reg
+ add
]);
14524 oappend (INTERNAL_DISASSEMBLER_ERROR
);
14537 FETCH_DATA (the_info
, codep
+ 8);
14538 a
= *codep
++ & 0xff;
14539 a
|= (*codep
++ & 0xff) << 8;
14540 a
|= (*codep
++ & 0xff) << 16;
14541 a
|= (*codep
++ & 0xffu
) << 24;
14542 b
= *codep
++ & 0xff;
14543 b
|= (*codep
++ & 0xff) << 8;
14544 b
|= (*codep
++ & 0xff) << 16;
14545 b
|= (*codep
++ & 0xffu
) << 24;
14546 x
= a
+ ((bfd_vma
) b
<< 32);
14554 static bfd_signed_vma
14557 bfd_signed_vma x
= 0;
14559 FETCH_DATA (the_info
, codep
+ 4);
14560 x
= *codep
++ & (bfd_signed_vma
) 0xff;
14561 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 8;
14562 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 16;
14563 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 24;
14567 static bfd_signed_vma
14570 bfd_signed_vma x
= 0;
14572 FETCH_DATA (the_info
, codep
+ 4);
14573 x
= *codep
++ & (bfd_signed_vma
) 0xff;
14574 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 8;
14575 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 16;
14576 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 24;
14578 x
= (x
^ ((bfd_signed_vma
) 1 << 31)) - ((bfd_signed_vma
) 1 << 31);
14588 FETCH_DATA (the_info
, codep
+ 2);
14589 x
= *codep
++ & 0xff;
14590 x
|= (*codep
++ & 0xff) << 8;
14595 set_op (bfd_vma op
, int riprel
)
14597 op_index
[op_ad
] = op_ad
;
14598 if (address_mode
== mode_64bit
)
14600 op_address
[op_ad
] = op
;
14601 op_riprel
[op_ad
] = riprel
;
14605 /* Mask to get a 32-bit address. */
14606 op_address
[op_ad
] = op
& 0xffffffff;
14607 op_riprel
[op_ad
] = riprel
& 0xffffffff;
14612 OP_REG (int code
, int sizeflag
)
14619 case es_reg
: case ss_reg
: case cs_reg
:
14620 case ds_reg
: case fs_reg
: case gs_reg
:
14621 oappend (names_seg
[code
- es_reg
]);
14633 case ax_reg
: case cx_reg
: case dx_reg
: case bx_reg
:
14634 case sp_reg
: case bp_reg
: case si_reg
: case di_reg
:
14635 s
= names16
[code
- ax_reg
+ add
];
14637 case al_reg
: case ah_reg
: case cl_reg
: case ch_reg
:
14638 case dl_reg
: case dh_reg
: case bl_reg
: case bh_reg
:
14641 s
= names8rex
[code
- al_reg
+ add
];
14643 s
= names8
[code
- al_reg
];
14645 case rAX_reg
: case rCX_reg
: case rDX_reg
: case rBX_reg
:
14646 case rSP_reg
: case rBP_reg
: case rSI_reg
: case rDI_reg
:
14647 if (address_mode
== mode_64bit
14648 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
14650 s
= names64
[code
- rAX_reg
+ add
];
14653 code
+= eAX_reg
- rAX_reg
;
14654 /* Fall through. */
14655 case eAX_reg
: case eCX_reg
: case eDX_reg
: case eBX_reg
:
14656 case eSP_reg
: case eBP_reg
: case eSI_reg
: case eDI_reg
:
14659 s
= names64
[code
- eAX_reg
+ add
];
14662 if (sizeflag
& DFLAG
)
14663 s
= names32
[code
- eAX_reg
+ add
];
14665 s
= names16
[code
- eAX_reg
+ add
];
14666 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14670 s
= INTERNAL_DISASSEMBLER_ERROR
;
14677 OP_IMREG (int code
, int sizeflag
)
14689 case ax_reg
: case cx_reg
: case dx_reg
: case bx_reg
:
14690 case sp_reg
: case bp_reg
: case si_reg
: case di_reg
:
14691 s
= names16
[code
- ax_reg
];
14693 case es_reg
: case ss_reg
: case cs_reg
:
14694 case ds_reg
: case fs_reg
: case gs_reg
:
14695 s
= names_seg
[code
- es_reg
];
14697 case al_reg
: case ah_reg
: case cl_reg
: case ch_reg
:
14698 case dl_reg
: case dh_reg
: case bl_reg
: case bh_reg
:
14701 s
= names8rex
[code
- al_reg
];
14703 s
= names8
[code
- al_reg
];
14705 case eAX_reg
: case eCX_reg
: case eDX_reg
: case eBX_reg
:
14706 case eSP_reg
: case eBP_reg
: case eSI_reg
: case eDI_reg
:
14709 s
= names64
[code
- eAX_reg
];
14712 if (sizeflag
& DFLAG
)
14713 s
= names32
[code
- eAX_reg
];
14715 s
= names16
[code
- eAX_reg
];
14716 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14719 case z_mode_ax_reg
:
14720 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
14724 if (!(rex
& REX_W
))
14725 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14728 s
= INTERNAL_DISASSEMBLER_ERROR
;
14735 OP_I (int bytemode
, int sizeflag
)
14738 bfd_signed_vma mask
= -1;
14743 FETCH_DATA (the_info
, codep
+ 1);
14753 if (sizeflag
& DFLAG
)
14763 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14779 oappend (INTERNAL_DISASSEMBLER_ERROR
);
14784 scratchbuf
[0] = '$';
14785 print_operand_value (scratchbuf
+ 1, 1, op
);
14786 oappend_maybe_intel (scratchbuf
);
14787 scratchbuf
[0] = '\0';
14791 OP_I64 (int bytemode
, int sizeflag
)
14793 if (bytemode
!= v_mode
|| address_mode
!= mode_64bit
|| !(rex
& REX_W
))
14795 OP_I (bytemode
, sizeflag
);
14801 scratchbuf
[0] = '$';
14802 print_operand_value (scratchbuf
+ 1, 1, get64 ());
14803 oappend_maybe_intel (scratchbuf
);
14804 scratchbuf
[0] = '\0';
14808 OP_sI (int bytemode
, int sizeflag
)
14816 FETCH_DATA (the_info
, codep
+ 1);
14818 if ((op
& 0x80) != 0)
14820 if (bytemode
== b_T_mode
)
14822 if (address_mode
!= mode_64bit
14823 || !((sizeflag
& DFLAG
) || (rex
& REX_W
)))
14825 /* The operand-size prefix is overridden by a REX prefix. */
14826 if ((sizeflag
& DFLAG
) || (rex
& REX_W
))
14834 if (!(rex
& REX_W
))
14836 if (sizeflag
& DFLAG
)
14844 /* The operand-size prefix is overridden by a REX prefix. */
14845 if ((sizeflag
& DFLAG
) || (rex
& REX_W
))
14851 oappend (INTERNAL_DISASSEMBLER_ERROR
);
14855 scratchbuf
[0] = '$';
14856 print_operand_value (scratchbuf
+ 1, 1, op
);
14857 oappend_maybe_intel (scratchbuf
);
14861 OP_J (int bytemode
, int sizeflag
)
14865 bfd_vma segment
= 0;
14870 FETCH_DATA (the_info
, codep
+ 1);
14872 if ((disp
& 0x80) != 0)
14876 if (isa64
!= intel64
)
14879 if ((sizeflag
& DFLAG
)
14880 || (address_mode
== mode_64bit
14881 && ((isa64
== intel64
&& bytemode
!= dqw_mode
)
14882 || (rex
& REX_W
))))
14887 if ((disp
& 0x8000) != 0)
14889 /* In 16bit mode, address is wrapped around at 64k within
14890 the same segment. Otherwise, a data16 prefix on a jump
14891 instruction means that the pc is masked to 16 bits after
14892 the displacement is added! */
14894 if ((prefixes
& PREFIX_DATA
) == 0)
14895 segment
= ((start_pc
+ (codep
- start_codep
))
14896 & ~((bfd_vma
) 0xffff));
14898 if (address_mode
!= mode_64bit
14899 || (isa64
!= intel64
&& !(rex
& REX_W
)))
14900 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14903 oappend (INTERNAL_DISASSEMBLER_ERROR
);
14906 disp
= ((start_pc
+ (codep
- start_codep
) + disp
) & mask
) | segment
;
14908 print_operand_value (scratchbuf
, 1, disp
);
14909 oappend (scratchbuf
);
14913 OP_SEG (int bytemode
, int sizeflag
)
14915 if (bytemode
== w_mode
)
14916 oappend (names_seg
[modrm
.reg
]);
14918 OP_E (modrm
.mod
== 3 ? bytemode
: w_mode
, sizeflag
);
14922 OP_DIR (int dummy ATTRIBUTE_UNUSED
, int sizeflag
)
14926 if (sizeflag
& DFLAG
)
14936 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14938 sprintf (scratchbuf
, "0x%x:0x%x", seg
, offset
);
14940 sprintf (scratchbuf
, "$0x%x,$0x%x", seg
, offset
);
14941 oappend (scratchbuf
);
14945 OP_OFF (int bytemode
, int sizeflag
)
14949 if (intel_syntax
&& (sizeflag
& SUFFIX_ALWAYS
))
14950 intel_operand_size (bytemode
, sizeflag
);
14953 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
14960 if (!active_seg_prefix
)
14962 oappend (names_seg
[ds_reg
- es_reg
]);
14966 print_operand_value (scratchbuf
, 1, off
);
14967 oappend (scratchbuf
);
14971 OP_OFF64 (int bytemode
, int sizeflag
)
14975 if (address_mode
!= mode_64bit
14976 || (prefixes
& PREFIX_ADDR
))
14978 OP_OFF (bytemode
, sizeflag
);
14982 if (intel_syntax
&& (sizeflag
& SUFFIX_ALWAYS
))
14983 intel_operand_size (bytemode
, sizeflag
);
14990 if (!active_seg_prefix
)
14992 oappend (names_seg
[ds_reg
- es_reg
]);
14996 print_operand_value (scratchbuf
, 1, off
);
14997 oappend (scratchbuf
);
15001 ptr_reg (int code
, int sizeflag
)
15005 *obufp
++ = open_char
;
15006 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
15007 if (address_mode
== mode_64bit
)
15009 if (!(sizeflag
& AFLAG
))
15010 s
= names32
[code
- eAX_reg
];
15012 s
= names64
[code
- eAX_reg
];
15014 else if (sizeflag
& AFLAG
)
15015 s
= names32
[code
- eAX_reg
];
15017 s
= names16
[code
- eAX_reg
];
15019 *obufp
++ = close_char
;
15024 OP_ESreg (int code
, int sizeflag
)
15030 case 0x6d: /* insw/insl */
15031 intel_operand_size (z_mode
, sizeflag
);
15033 case 0xa5: /* movsw/movsl/movsq */
15034 case 0xa7: /* cmpsw/cmpsl/cmpsq */
15035 case 0xab: /* stosw/stosl */
15036 case 0xaf: /* scasw/scasl */
15037 intel_operand_size (v_mode
, sizeflag
);
15040 intel_operand_size (b_mode
, sizeflag
);
15043 oappend_maybe_intel ("%es:");
15044 ptr_reg (code
, sizeflag
);
15048 OP_DSreg (int code
, int sizeflag
)
15054 case 0x6f: /* outsw/outsl */
15055 intel_operand_size (z_mode
, sizeflag
);
15057 case 0xa5: /* movsw/movsl/movsq */
15058 case 0xa7: /* cmpsw/cmpsl/cmpsq */
15059 case 0xad: /* lodsw/lodsl/lodsq */
15060 intel_operand_size (v_mode
, sizeflag
);
15063 intel_operand_size (b_mode
, sizeflag
);
15066 /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
15067 default segment register DS is printed. */
15068 if (!active_seg_prefix
)
15069 active_seg_prefix
= PREFIX_DS
;
15071 ptr_reg (code
, sizeflag
);
15075 OP_C (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15083 else if (address_mode
!= mode_64bit
&& (prefixes
& PREFIX_LOCK
))
15085 all_prefixes
[last_lock_prefix
] = 0;
15086 used_prefixes
|= PREFIX_LOCK
;
15091 sprintf (scratchbuf
, "%%cr%d", modrm
.reg
+ add
);
15092 oappend_maybe_intel (scratchbuf
);
15096 OP_D (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15105 sprintf (scratchbuf
, "db%d", modrm
.reg
+ add
);
15107 sprintf (scratchbuf
, "%%db%d", modrm
.reg
+ add
);
15108 oappend (scratchbuf
);
15112 OP_T (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15114 sprintf (scratchbuf
, "%%tr%d", modrm
.reg
);
15115 oappend_maybe_intel (scratchbuf
);
15119 OP_R (int bytemode
, int sizeflag
)
15121 /* Skip mod/rm byte. */
15124 OP_E_register (bytemode
, sizeflag
);
15128 OP_MMX (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15130 int reg
= modrm
.reg
;
15131 const char **names
;
15133 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15134 if (prefixes
& PREFIX_DATA
)
15143 oappend (names
[reg
]);
15147 OP_XMM (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
15149 int reg
= modrm
.reg
;
15150 const char **names
;
15162 && bytemode
!= xmm_mode
15163 && bytemode
!= xmmq_mode
15164 && bytemode
!= evex_half_bcst_xmmq_mode
15165 && bytemode
!= ymm_mode
15166 && bytemode
!= scalar_mode
)
15168 switch (vex
.length
)
15175 || (bytemode
!= vex_vsib_q_w_dq_mode
15176 && bytemode
!= vex_vsib_q_w_d_mode
))
15188 else if (bytemode
== xmmq_mode
15189 || bytemode
== evex_half_bcst_xmmq_mode
)
15191 switch (vex
.length
)
15204 else if (bytemode
== ymm_mode
)
15208 oappend (names
[reg
]);
15212 OP_EM (int bytemode
, int sizeflag
)
15215 const char **names
;
15217 if (modrm
.mod
!= 3)
15220 && (bytemode
== v_mode
|| bytemode
== v_swap_mode
))
15222 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
15223 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15225 OP_E (bytemode
, sizeflag
);
15229 if ((sizeflag
& SUFFIX_ALWAYS
) && bytemode
== v_swap_mode
)
15232 /* Skip mod/rm byte. */
15235 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15237 if (prefixes
& PREFIX_DATA
)
15246 oappend (names
[reg
]);
15249 /* cvt* are the only instructions in sse2 which have
15250 both SSE and MMX operands and also have 0x66 prefix
15251 in their opcode. 0x66 was originally used to differentiate
15252 between SSE and MMX instruction(operands). So we have to handle the
15253 cvt* separately using OP_EMC and OP_MXC */
15255 OP_EMC (int bytemode
, int sizeflag
)
15257 if (modrm
.mod
!= 3)
15259 if (intel_syntax
&& bytemode
== v_mode
)
15261 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
15262 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15264 OP_E (bytemode
, sizeflag
);
15268 /* Skip mod/rm byte. */
15271 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15272 oappend (names_mm
[modrm
.rm
]);
15276 OP_MXC (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15278 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15279 oappend (names_mm
[modrm
.reg
]);
15283 OP_EX (int bytemode
, int sizeflag
)
15286 const char **names
;
15288 /* Skip mod/rm byte. */
15292 if (modrm
.mod
!= 3)
15294 OP_E_memory (bytemode
, sizeflag
);
15309 if ((sizeflag
& SUFFIX_ALWAYS
)
15310 && (bytemode
== x_swap_mode
15311 || bytemode
== d_swap_mode
15312 || bytemode
== d_scalar_swap_mode
15313 || bytemode
== q_swap_mode
15314 || bytemode
== q_scalar_swap_mode
))
15318 && bytemode
!= xmm_mode
15319 && bytemode
!= xmmdw_mode
15320 && bytemode
!= xmmqd_mode
15321 && bytemode
!= xmm_mb_mode
15322 && bytemode
!= xmm_mw_mode
15323 && bytemode
!= xmm_md_mode
15324 && bytemode
!= xmm_mq_mode
15325 && bytemode
!= xmmq_mode
15326 && bytemode
!= evex_half_bcst_xmmq_mode
15327 && bytemode
!= ymm_mode
15328 && bytemode
!= d_scalar_swap_mode
15329 && bytemode
!= q_scalar_swap_mode
15330 && bytemode
!= vex_scalar_w_dq_mode
)
15332 switch (vex
.length
)
15347 else if (bytemode
== xmmq_mode
15348 || bytemode
== evex_half_bcst_xmmq_mode
)
15350 switch (vex
.length
)
15363 else if (bytemode
== ymm_mode
)
15367 oappend (names
[reg
]);
15371 OP_MS (int bytemode
, int sizeflag
)
15373 if (modrm
.mod
== 3)
15374 OP_EM (bytemode
, sizeflag
);
15380 OP_XS (int bytemode
, int sizeflag
)
15382 if (modrm
.mod
== 3)
15383 OP_EX (bytemode
, sizeflag
);
15389 OP_M (int bytemode
, int sizeflag
)
15391 if (modrm
.mod
== 3)
15392 /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
15395 OP_E (bytemode
, sizeflag
);
15399 OP_0f07 (int bytemode
, int sizeflag
)
15401 if (modrm
.mod
!= 3 || modrm
.rm
!= 0)
15404 OP_E (bytemode
, sizeflag
);
15407 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
15408 32bit mode and "xchg %rax,%rax" in 64bit mode. */
15411 NOP_Fixup1 (int bytemode
, int sizeflag
)
15413 if ((prefixes
& PREFIX_DATA
) != 0
15416 && address_mode
== mode_64bit
))
15417 OP_REG (bytemode
, sizeflag
);
15419 strcpy (obuf
, "nop");
15423 NOP_Fixup2 (int bytemode
, int sizeflag
)
15425 if ((prefixes
& PREFIX_DATA
) != 0
15428 && address_mode
== mode_64bit
))
15429 OP_IMREG (bytemode
, sizeflag
);
15432 static const char *const Suffix3DNow
[] = {
15433 /* 00 */ NULL
, NULL
, NULL
, NULL
,
15434 /* 04 */ NULL
, NULL
, NULL
, NULL
,
15435 /* 08 */ NULL
, NULL
, NULL
, NULL
,
15436 /* 0C */ "pi2fw", "pi2fd", NULL
, NULL
,
15437 /* 10 */ NULL
, NULL
, NULL
, NULL
,
15438 /* 14 */ NULL
, NULL
, NULL
, NULL
,
15439 /* 18 */ NULL
, NULL
, NULL
, NULL
,
15440 /* 1C */ "pf2iw", "pf2id", NULL
, NULL
,
15441 /* 20 */ NULL
, NULL
, NULL
, NULL
,
15442 /* 24 */ NULL
, NULL
, NULL
, NULL
,
15443 /* 28 */ NULL
, NULL
, NULL
, NULL
,
15444 /* 2C */ NULL
, NULL
, NULL
, NULL
,
15445 /* 30 */ NULL
, NULL
, NULL
, NULL
,
15446 /* 34 */ NULL
, NULL
, NULL
, NULL
,
15447 /* 38 */ NULL
, NULL
, NULL
, NULL
,
15448 /* 3C */ NULL
, NULL
, NULL
, NULL
,
15449 /* 40 */ NULL
, NULL
, NULL
, NULL
,
15450 /* 44 */ NULL
, NULL
, NULL
, NULL
,
15451 /* 48 */ NULL
, NULL
, NULL
, NULL
,
15452 /* 4C */ NULL
, NULL
, NULL
, NULL
,
15453 /* 50 */ NULL
, NULL
, NULL
, NULL
,
15454 /* 54 */ NULL
, NULL
, NULL
, NULL
,
15455 /* 58 */ NULL
, NULL
, NULL
, NULL
,
15456 /* 5C */ NULL
, NULL
, NULL
, NULL
,
15457 /* 60 */ NULL
, NULL
, NULL
, NULL
,
15458 /* 64 */ NULL
, NULL
, NULL
, NULL
,
15459 /* 68 */ NULL
, NULL
, NULL
, NULL
,
15460 /* 6C */ NULL
, NULL
, NULL
, NULL
,
15461 /* 70 */ NULL
, NULL
, NULL
, NULL
,
15462 /* 74 */ NULL
, NULL
, NULL
, NULL
,
15463 /* 78 */ NULL
, NULL
, NULL
, NULL
,
15464 /* 7C */ NULL
, NULL
, NULL
, NULL
,
15465 /* 80 */ NULL
, NULL
, NULL
, NULL
,
15466 /* 84 */ NULL
, NULL
, NULL
, NULL
,
15467 /* 88 */ NULL
, NULL
, "pfnacc", NULL
,
15468 /* 8C */ NULL
, NULL
, "pfpnacc", NULL
,
15469 /* 90 */ "pfcmpge", NULL
, NULL
, NULL
,
15470 /* 94 */ "pfmin", NULL
, "pfrcp", "pfrsqrt",
15471 /* 98 */ NULL
, NULL
, "pfsub", NULL
,
15472 /* 9C */ NULL
, NULL
, "pfadd", NULL
,
15473 /* A0 */ "pfcmpgt", NULL
, NULL
, NULL
,
15474 /* A4 */ "pfmax", NULL
, "pfrcpit1", "pfrsqit1",
15475 /* A8 */ NULL
, NULL
, "pfsubr", NULL
,
15476 /* AC */ NULL
, NULL
, "pfacc", NULL
,
15477 /* B0 */ "pfcmpeq", NULL
, NULL
, NULL
,
15478 /* B4 */ "pfmul", NULL
, "pfrcpit2", "pmulhrw",
15479 /* B8 */ NULL
, NULL
, NULL
, "pswapd",
15480 /* BC */ NULL
, NULL
, NULL
, "pavgusb",
15481 /* C0 */ NULL
, NULL
, NULL
, NULL
,
15482 /* C4 */ NULL
, NULL
, NULL
, NULL
,
15483 /* C8 */ NULL
, NULL
, NULL
, NULL
,
15484 /* CC */ NULL
, NULL
, NULL
, NULL
,
15485 /* D0 */ NULL
, NULL
, NULL
, NULL
,
15486 /* D4 */ NULL
, NULL
, NULL
, NULL
,
15487 /* D8 */ NULL
, NULL
, NULL
, NULL
,
15488 /* DC */ NULL
, NULL
, NULL
, NULL
,
15489 /* E0 */ NULL
, NULL
, NULL
, NULL
,
15490 /* E4 */ NULL
, NULL
, NULL
, NULL
,
15491 /* E8 */ NULL
, NULL
, NULL
, NULL
,
15492 /* EC */ NULL
, NULL
, NULL
, NULL
,
15493 /* F0 */ NULL
, NULL
, NULL
, NULL
,
15494 /* F4 */ NULL
, NULL
, NULL
, NULL
,
15495 /* F8 */ NULL
, NULL
, NULL
, NULL
,
15496 /* FC */ NULL
, NULL
, NULL
, NULL
,
15500 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15502 const char *mnemonic
;
15504 FETCH_DATA (the_info
, codep
+ 1);
15505 /* AMD 3DNow! instructions are specified by an opcode suffix in the
15506 place where an 8-bit immediate would normally go. ie. the last
15507 byte of the instruction. */
15508 obufp
= mnemonicendp
;
15509 mnemonic
= Suffix3DNow
[*codep
++ & 0xff];
15511 oappend (mnemonic
);
15514 /* Since a variable sized modrm/sib chunk is between the start
15515 of the opcode (0x0f0f) and the opcode suffix, we need to do
15516 all the modrm processing first, and don't know until now that
15517 we have a bad opcode. This necessitates some cleaning up. */
15518 op_out
[0][0] = '\0';
15519 op_out
[1][0] = '\0';
15522 mnemonicendp
= obufp
;
15525 static struct op simd_cmp_op
[] =
15527 { STRING_COMMA_LEN ("eq") },
15528 { STRING_COMMA_LEN ("lt") },
15529 { STRING_COMMA_LEN ("le") },
15530 { STRING_COMMA_LEN ("unord") },
15531 { STRING_COMMA_LEN ("neq") },
15532 { STRING_COMMA_LEN ("nlt") },
15533 { STRING_COMMA_LEN ("nle") },
15534 { STRING_COMMA_LEN ("ord") }
15538 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15540 unsigned int cmp_type
;
15542 FETCH_DATA (the_info
, codep
+ 1);
15543 cmp_type
= *codep
++ & 0xff;
15544 if (cmp_type
< ARRAY_SIZE (simd_cmp_op
))
15547 char *p
= mnemonicendp
- 2;
15551 sprintf (p
, "%s%s", simd_cmp_op
[cmp_type
].name
, suffix
);
15552 mnemonicendp
+= simd_cmp_op
[cmp_type
].len
;
15556 /* We have a reserved extension byte. Output it directly. */
15557 scratchbuf
[0] = '$';
15558 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
15559 oappend_maybe_intel (scratchbuf
);
15560 scratchbuf
[0] = '\0';
15565 OP_Mwait (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
15567 /* mwait %eax,%ecx / mwaitx %eax,%ecx,%ebx */
15570 strcpy (op_out
[0], names32
[0]);
15571 strcpy (op_out
[1], names32
[1]);
15572 if (bytemode
== eBX_reg
)
15573 strcpy (op_out
[2], names32
[3]);
15574 two_source_ops
= 1;
15576 /* Skip mod/rm byte. */
15582 OP_Monitor (int bytemode ATTRIBUTE_UNUSED
,
15583 int sizeflag ATTRIBUTE_UNUSED
)
15585 /* monitor %{e,r,}ax,%ecx,%edx" */
15588 const char **names
= (address_mode
== mode_64bit
15589 ? names64
: names32
);
15591 if (prefixes
& PREFIX_ADDR
)
15593 /* Remove "addr16/addr32". */
15594 all_prefixes
[last_addr_prefix
] = 0;
15595 names
= (address_mode
!= mode_32bit
15596 ? names32
: names16
);
15597 used_prefixes
|= PREFIX_ADDR
;
15599 else if (address_mode
== mode_16bit
)
15601 strcpy (op_out
[0], names
[0]);
15602 strcpy (op_out
[1], names32
[1]);
15603 strcpy (op_out
[2], names32
[2]);
15604 two_source_ops
= 1;
15606 /* Skip mod/rm byte. */
15614 /* Throw away prefixes and 1st. opcode byte. */
15615 codep
= insn_codep
+ 1;
15620 REP_Fixup (int bytemode
, int sizeflag
)
15622 /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
15624 if (prefixes
& PREFIX_REPZ
)
15625 all_prefixes
[last_repz_prefix
] = REP_PREFIX
;
15632 OP_IMREG (bytemode
, sizeflag
);
15635 OP_ESreg (bytemode
, sizeflag
);
15638 OP_DSreg (bytemode
, sizeflag
);
15647 SEP_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15649 if ( isa64
!= amd64
)
15654 mnemonicendp
= obufp
;
15658 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
15662 BND_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15664 if (prefixes
& PREFIX_REPNZ
)
15665 all_prefixes
[last_repnz_prefix
] = BND_PREFIX
;
15668 /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
15672 NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED
,
15673 int sizeflag ATTRIBUTE_UNUSED
)
15675 if (active_seg_prefix
== PREFIX_DS
15676 && (address_mode
!= mode_64bit
|| last_data_prefix
< 0))
15678 /* NOTRACK prefix is only valid on indirect branch instructions.
15679 NB: DATA prefix is unsupported for Intel64. */
15680 active_seg_prefix
= 0;
15681 all_prefixes
[last_seg_prefix
] = NOTRACK_PREFIX
;
15685 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
15686 "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
15690 HLE_Fixup1 (int bytemode
, int sizeflag
)
15693 && (prefixes
& PREFIX_LOCK
) != 0)
15695 if (prefixes
& PREFIX_REPZ
)
15696 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
15697 if (prefixes
& PREFIX_REPNZ
)
15698 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
15701 OP_E (bytemode
, sizeflag
);
15704 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
15705 "xacquire"/"xrelease" for memory operand. No check for LOCK prefix.
15709 HLE_Fixup2 (int bytemode
, int sizeflag
)
15711 if (modrm
.mod
!= 3)
15713 if (prefixes
& PREFIX_REPZ
)
15714 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
15715 if (prefixes
& PREFIX_REPNZ
)
15716 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
15719 OP_E (bytemode
, sizeflag
);
15722 /* Similar to OP_E. But the 0xf3 prefixes should be displayed as
15723 "xrelease" for memory operand. No check for LOCK prefix. */
15726 HLE_Fixup3 (int bytemode
, int sizeflag
)
15729 && last_repz_prefix
> last_repnz_prefix
15730 && (prefixes
& PREFIX_REPZ
) != 0)
15731 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
15733 OP_E (bytemode
, sizeflag
);
15737 CMPXCHG8B_Fixup (int bytemode
, int sizeflag
)
15742 /* Change cmpxchg8b to cmpxchg16b. */
15743 char *p
= mnemonicendp
- 2;
15744 mnemonicendp
= stpcpy (p
, "16b");
15747 else if ((prefixes
& PREFIX_LOCK
) != 0)
15749 if (prefixes
& PREFIX_REPZ
)
15750 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
15751 if (prefixes
& PREFIX_REPNZ
)
15752 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
15755 OP_M (bytemode
, sizeflag
);
15759 XMM_Fixup (int reg
, int sizeflag ATTRIBUTE_UNUSED
)
15761 const char **names
;
15765 switch (vex
.length
)
15779 oappend (names
[reg
]);
15783 CRC32_Fixup (int bytemode
, int sizeflag
)
15785 /* Add proper suffix to "crc32". */
15786 char *p
= mnemonicendp
;
15805 if (sizeflag
& DFLAG
)
15809 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15813 oappend (INTERNAL_DISASSEMBLER_ERROR
);
15820 if (modrm
.mod
== 3)
15824 /* Skip mod/rm byte. */
15829 add
= (rex
& REX_B
) ? 8 : 0;
15830 if (bytemode
== b_mode
)
15834 oappend (names8rex
[modrm
.rm
+ add
]);
15836 oappend (names8
[modrm
.rm
+ add
]);
15842 oappend (names64
[modrm
.rm
+ add
]);
15843 else if ((prefixes
& PREFIX_DATA
))
15844 oappend (names16
[modrm
.rm
+ add
]);
15846 oappend (names32
[modrm
.rm
+ add
]);
15850 OP_E (bytemode
, sizeflag
);
15854 FXSAVE_Fixup (int bytemode
, int sizeflag
)
15856 /* Add proper suffix to "fxsave" and "fxrstor". */
15860 char *p
= mnemonicendp
;
15866 OP_M (bytemode
, sizeflag
);
15870 PCMPESTR_Fixup (int bytemode
, int sizeflag
)
15872 /* Add proper suffix to "{,v}pcmpestr{i,m}". */
15875 char *p
= mnemonicendp
;
15880 else if (sizeflag
& SUFFIX_ALWAYS
)
15887 OP_EX (bytemode
, sizeflag
);
15890 /* Display the destination register operand for instructions with
15894 OP_VEX (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
15897 const char **names
;
15905 reg
= vex
.register_specifier
;
15906 vex
.register_specifier
= 0;
15907 if (address_mode
!= mode_64bit
)
15909 else if (vex
.evex
&& !vex
.v
)
15912 if (bytemode
== vex_scalar_mode
)
15914 oappend (names_xmm
[reg
]);
15918 switch (vex
.length
)
15925 case vex_vsib_q_w_dq_mode
:
15926 case vex_vsib_q_w_d_mode
:
15942 names
= names_mask
;
15956 case vex_vsib_q_w_dq_mode
:
15957 case vex_vsib_q_w_d_mode
:
15958 names
= vex
.w
? names_ymm
: names_xmm
;
15967 names
= names_mask
;
15970 /* See PR binutils/20893 for a reproducer. */
15982 oappend (names
[reg
]);
15985 /* Get the VEX immediate byte without moving codep. */
15987 static unsigned char
15988 get_vex_imm8 (int sizeflag
, int opnum
)
15990 int bytes_before_imm
= 0;
15992 if (modrm
.mod
!= 3)
15994 /* There are SIB/displacement bytes. */
15995 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
15997 /* 32/64 bit address mode */
15998 int base
= modrm
.rm
;
16000 /* Check SIB byte. */
16003 FETCH_DATA (the_info
, codep
+ 1);
16005 /* When decoding the third source, don't increase
16006 bytes_before_imm as this has already been incremented
16007 by one in OP_E_memory while decoding the second
16010 bytes_before_imm
++;
16013 /* Don't increase bytes_before_imm when decoding the third source,
16014 it has already been incremented by OP_E_memory while decoding
16015 the second source operand. */
16021 /* When modrm.rm == 5 or modrm.rm == 4 and base in
16022 SIB == 5, there is a 4 byte displacement. */
16024 /* No displacement. */
16026 /* Fall through. */
16028 /* 4 byte displacement. */
16029 bytes_before_imm
+= 4;
16032 /* 1 byte displacement. */
16033 bytes_before_imm
++;
16040 /* 16 bit address mode */
16041 /* Don't increase bytes_before_imm when decoding the third source,
16042 it has already been incremented by OP_E_memory while decoding
16043 the second source operand. */
16049 /* When modrm.rm == 6, there is a 2 byte displacement. */
16051 /* No displacement. */
16053 /* Fall through. */
16055 /* 2 byte displacement. */
16056 bytes_before_imm
+= 2;
16059 /* 1 byte displacement: when decoding the third source,
16060 don't increase bytes_before_imm as this has already
16061 been incremented by one in OP_E_memory while decoding
16062 the second source operand. */
16064 bytes_before_imm
++;
16072 FETCH_DATA (the_info
, codep
+ bytes_before_imm
+ 1);
16073 return codep
[bytes_before_imm
];
16077 OP_EX_VexReg (int bytemode
, int sizeflag
, int reg
)
16079 const char **names
;
16081 if (reg
== -1 && modrm
.mod
!= 3)
16083 OP_E_memory (bytemode
, sizeflag
);
16095 if (address_mode
!= mode_64bit
)
16099 switch (vex
.length
)
16110 oappend (names
[reg
]);
16114 OP_EX_VexImmW (int bytemode
, int sizeflag
)
16117 static unsigned char vex_imm8
;
16119 if (vex_w_done
== 0)
16123 /* Skip mod/rm byte. */
16127 vex_imm8
= get_vex_imm8 (sizeflag
, 0);
16130 reg
= vex_imm8
>> 4;
16132 OP_EX_VexReg (bytemode
, sizeflag
, reg
);
16134 else if (vex_w_done
== 1)
16139 reg
= vex_imm8
>> 4;
16141 OP_EX_VexReg (bytemode
, sizeflag
, reg
);
16145 /* Output the imm8 directly. */
16146 scratchbuf
[0] = '$';
16147 print_operand_value (scratchbuf
+ 1, 1, vex_imm8
& 0xf);
16148 oappend_maybe_intel (scratchbuf
);
16149 scratchbuf
[0] = '\0';
16155 OP_Vex_2src (int bytemode
, int sizeflag
)
16157 if (modrm
.mod
== 3)
16159 int reg
= modrm
.rm
;
16163 oappend (names_xmm
[reg
]);
16168 && (bytemode
== v_mode
|| bytemode
== v_swap_mode
))
16170 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
16171 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16173 OP_E (bytemode
, sizeflag
);
16178 OP_Vex_2src_1 (int bytemode
, int sizeflag
)
16180 if (modrm
.mod
== 3)
16182 /* Skip mod/rm byte. */
16189 unsigned int reg
= vex
.register_specifier
;
16190 vex
.register_specifier
= 0;
16192 if (address_mode
!= mode_64bit
)
16194 oappend (names_xmm
[reg
]);
16197 OP_Vex_2src (bytemode
, sizeflag
);
16201 OP_Vex_2src_2 (int bytemode
, int sizeflag
)
16204 OP_Vex_2src (bytemode
, sizeflag
);
16207 unsigned int reg
= vex
.register_specifier
;
16208 vex
.register_specifier
= 0;
16210 if (address_mode
!= mode_64bit
)
16212 oappend (names_xmm
[reg
]);
16217 OP_EX_VexW (int bytemode
, int sizeflag
)
16223 /* Skip mod/rm byte. */
16228 reg
= get_vex_imm8 (sizeflag
, 0) >> 4;
16233 reg
= get_vex_imm8 (sizeflag
, 1) >> 4;
16236 OP_EX_VexReg (bytemode
, sizeflag
, reg
);
16244 OP_REG_VexI4 (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
16247 const char **names
;
16249 FETCH_DATA (the_info
, codep
+ 1);
16252 if (bytemode
!= x_mode
)
16256 if (address_mode
!= mode_64bit
)
16259 switch (vex
.length
)
16270 oappend (names
[reg
]);
16274 OP_XMM_VexW (int bytemode
, int sizeflag
)
16276 /* Turn off the REX.W bit since it is used for swapping operands
16279 OP_XMM (bytemode
, sizeflag
);
16283 OP_EX_Vex (int bytemode
, int sizeflag
)
16285 if (modrm
.mod
!= 3)
16287 OP_EX (bytemode
, sizeflag
);
16291 OP_XMM_Vex (int bytemode
, int sizeflag
)
16293 if (modrm
.mod
!= 3)
16295 OP_XMM (bytemode
, sizeflag
);
16298 static struct op vex_cmp_op
[] =
16300 { STRING_COMMA_LEN ("eq") },
16301 { STRING_COMMA_LEN ("lt") },
16302 { STRING_COMMA_LEN ("le") },
16303 { STRING_COMMA_LEN ("unord") },
16304 { STRING_COMMA_LEN ("neq") },
16305 { STRING_COMMA_LEN ("nlt") },
16306 { STRING_COMMA_LEN ("nle") },
16307 { STRING_COMMA_LEN ("ord") },
16308 { STRING_COMMA_LEN ("eq_uq") },
16309 { STRING_COMMA_LEN ("nge") },
16310 { STRING_COMMA_LEN ("ngt") },
16311 { STRING_COMMA_LEN ("false") },
16312 { STRING_COMMA_LEN ("neq_oq") },
16313 { STRING_COMMA_LEN ("ge") },
16314 { STRING_COMMA_LEN ("gt") },
16315 { STRING_COMMA_LEN ("true") },
16316 { STRING_COMMA_LEN ("eq_os") },
16317 { STRING_COMMA_LEN ("lt_oq") },
16318 { STRING_COMMA_LEN ("le_oq") },
16319 { STRING_COMMA_LEN ("unord_s") },
16320 { STRING_COMMA_LEN ("neq_us") },
16321 { STRING_COMMA_LEN ("nlt_uq") },
16322 { STRING_COMMA_LEN ("nle_uq") },
16323 { STRING_COMMA_LEN ("ord_s") },
16324 { STRING_COMMA_LEN ("eq_us") },
16325 { STRING_COMMA_LEN ("nge_uq") },
16326 { STRING_COMMA_LEN ("ngt_uq") },
16327 { STRING_COMMA_LEN ("false_os") },
16328 { STRING_COMMA_LEN ("neq_os") },
16329 { STRING_COMMA_LEN ("ge_oq") },
16330 { STRING_COMMA_LEN ("gt_oq") },
16331 { STRING_COMMA_LEN ("true_us") },
16335 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16337 unsigned int cmp_type
;
16339 FETCH_DATA (the_info
, codep
+ 1);
16340 cmp_type
= *codep
++ & 0xff;
16341 if (cmp_type
< ARRAY_SIZE (vex_cmp_op
))
16344 char *p
= mnemonicendp
- 2;
16348 sprintf (p
, "%s%s", vex_cmp_op
[cmp_type
].name
, suffix
);
16349 mnemonicendp
+= vex_cmp_op
[cmp_type
].len
;
16353 /* We have a reserved extension byte. Output it directly. */
16354 scratchbuf
[0] = '$';
16355 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
16356 oappend_maybe_intel (scratchbuf
);
16357 scratchbuf
[0] = '\0';
16362 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED
,
16363 int sizeflag ATTRIBUTE_UNUSED
)
16365 unsigned int cmp_type
;
16370 FETCH_DATA (the_info
, codep
+ 1);
16371 cmp_type
= *codep
++ & 0xff;
16372 /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
16373 If it's the case, print suffix, otherwise - print the immediate. */
16374 if (cmp_type
< ARRAY_SIZE (simd_cmp_op
)
16379 char *p
= mnemonicendp
- 2;
16381 /* vpcmp* can have both one- and two-lettered suffix. */
16395 sprintf (p
, "%s%s", simd_cmp_op
[cmp_type
].name
, suffix
);
16396 mnemonicendp
+= simd_cmp_op
[cmp_type
].len
;
16400 /* We have a reserved extension byte. Output it directly. */
16401 scratchbuf
[0] = '$';
16402 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
16403 oappend_maybe_intel (scratchbuf
);
16404 scratchbuf
[0] = '\0';
16408 static const struct op xop_cmp_op
[] =
16410 { STRING_COMMA_LEN ("lt") },
16411 { STRING_COMMA_LEN ("le") },
16412 { STRING_COMMA_LEN ("gt") },
16413 { STRING_COMMA_LEN ("ge") },
16414 { STRING_COMMA_LEN ("eq") },
16415 { STRING_COMMA_LEN ("neq") },
16416 { STRING_COMMA_LEN ("false") },
16417 { STRING_COMMA_LEN ("true") }
16421 VPCOM_Fixup (int bytemode ATTRIBUTE_UNUSED
,
16422 int sizeflag ATTRIBUTE_UNUSED
)
16424 unsigned int cmp_type
;
16426 FETCH_DATA (the_info
, codep
+ 1);
16427 cmp_type
= *codep
++ & 0xff;
16428 if (cmp_type
< ARRAY_SIZE (xop_cmp_op
))
16431 char *p
= mnemonicendp
- 2;
16433 /* vpcom* can have both one- and two-lettered suffix. */
16447 sprintf (p
, "%s%s", xop_cmp_op
[cmp_type
].name
, suffix
);
16448 mnemonicendp
+= xop_cmp_op
[cmp_type
].len
;
16452 /* We have a reserved extension byte. Output it directly. */
16453 scratchbuf
[0] = '$';
16454 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
16455 oappend_maybe_intel (scratchbuf
);
16456 scratchbuf
[0] = '\0';
16460 static const struct op pclmul_op
[] =
16462 { STRING_COMMA_LEN ("lql") },
16463 { STRING_COMMA_LEN ("hql") },
16464 { STRING_COMMA_LEN ("lqh") },
16465 { STRING_COMMA_LEN ("hqh") }
16469 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED
,
16470 int sizeflag ATTRIBUTE_UNUSED
)
16472 unsigned int pclmul_type
;
16474 FETCH_DATA (the_info
, codep
+ 1);
16475 pclmul_type
= *codep
++ & 0xff;
16476 switch (pclmul_type
)
16487 if (pclmul_type
< ARRAY_SIZE (pclmul_op
))
16490 char *p
= mnemonicendp
- 3;
16495 sprintf (p
, "%s%s", pclmul_op
[pclmul_type
].name
, suffix
);
16496 mnemonicendp
+= pclmul_op
[pclmul_type
].len
;
16500 /* We have a reserved extension byte. Output it directly. */
16501 scratchbuf
[0] = '$';
16502 print_operand_value (scratchbuf
+ 1, 1, pclmul_type
);
16503 oappend_maybe_intel (scratchbuf
);
16504 scratchbuf
[0] = '\0';
16509 MOVBE_Fixup (int bytemode
, int sizeflag
)
16511 /* Add proper suffix to "movbe". */
16512 char *p
= mnemonicendp
;
16521 if (sizeflag
& SUFFIX_ALWAYS
)
16527 if (sizeflag
& DFLAG
)
16531 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16536 oappend (INTERNAL_DISASSEMBLER_ERROR
);
16543 OP_M (bytemode
, sizeflag
);
16547 MOVSXD_Fixup (int bytemode
, int sizeflag
)
16549 /* Add proper suffix to "movsxd". */
16550 char *p
= mnemonicendp
;
16575 oappend (INTERNAL_DISASSEMBLER_ERROR
);
16582 OP_E (bytemode
, sizeflag
);
16586 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16589 const char **names
;
16591 /* Skip mod/rm byte. */
16605 oappend (names
[reg
]);
16609 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16611 const char **names
;
16612 unsigned int reg
= vex
.register_specifier
;
16613 vex
.register_specifier
= 0;
16620 if (address_mode
!= mode_64bit
)
16622 oappend (names
[reg
]);
16626 OP_Mask (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
16629 || (bytemode
!= mask_mode
&& bytemode
!= mask_bd_mode
))
16633 if ((rex
& REX_R
) != 0 || !vex
.r
)
16639 oappend (names_mask
[modrm
.reg
]);
16643 OP_Rounding (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
16646 || (bytemode
!= evex_rounding_mode
16647 && bytemode
!= evex_rounding_64_mode
16648 && bytemode
!= evex_sae_mode
))
16650 if (modrm
.mod
== 3 && vex
.b
)
16653 case evex_rounding_64_mode
:
16654 if (address_mode
!= mode_64bit
)
16659 /* Fall through. */
16660 case evex_rounding_mode
:
16661 oappend (names_rounding
[vex
.ll
]);
16663 case evex_sae_mode
: