1 /* Print i386 instructions for GDB, the GNU debugger.
2 Copyright (C) 1988-2020 Free Software Foundation, Inc.
4 This file is part of the GNU opcodes library.
6 This library is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 It is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
24 modified by John Hassey (hassey@dg-rtp.dg.com)
25 x86-64 support added by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */
28 /* The main tables describing the instructions is essentially a copy
29 of the "Opcode Map" chapter (Appendix A) of the Intel 80386
30 Programmers Manual. Usually, there is a capital letter, followed
31 by a small letter. The capital letter tell the addressing mode,
32 and the small letter tells about the operand size. Refer to
33 the Intel manual for details. */
36 #include "disassemble.h"
38 #include "opcode/i386.h"
39 #include "libiberty.h"
40 #include "safe-ctype.h"
44 static int print_insn (bfd_vma
, disassemble_info
*);
45 static void dofloat (int);
46 static void OP_ST (int, int);
47 static void OP_STi (int, int);
48 static int putop (const char *, int);
49 static void oappend (const char *);
50 static void append_seg (void);
51 static void OP_indirE (int, int);
52 static void print_operand_value (char *, int, bfd_vma
);
53 static void OP_E_register (int, int);
54 static void OP_E_memory (int, int);
55 static void print_displacement (char *, bfd_vma
);
56 static void OP_E (int, int);
57 static void OP_G (int, int);
58 static bfd_vma
get64 (void);
59 static bfd_signed_vma
get32 (void);
60 static bfd_signed_vma
get32s (void);
61 static int get16 (void);
62 static void set_op (bfd_vma
, int);
63 static void OP_Skip_MODRM (int, int);
64 static void OP_REG (int, int);
65 static void OP_IMREG (int, int);
66 static void OP_I (int, int);
67 static void OP_I64 (int, int);
68 static void OP_sI (int, int);
69 static void OP_J (int, int);
70 static void OP_SEG (int, int);
71 static void OP_DIR (int, int);
72 static void OP_OFF (int, int);
73 static void OP_OFF64 (int, int);
74 static void ptr_reg (int, int);
75 static void OP_ESreg (int, int);
76 static void OP_DSreg (int, int);
77 static void OP_C (int, int);
78 static void OP_D (int, int);
79 static void OP_T (int, int);
80 static void OP_R (int, int);
81 static void OP_MMX (int, int);
82 static void OP_XMM (int, int);
83 static void OP_EM (int, int);
84 static void OP_EX (int, int);
85 static void OP_EMC (int,int);
86 static void OP_MXC (int,int);
87 static void OP_MS (int, int);
88 static void OP_XS (int, int);
89 static void OP_M (int, int);
90 static void OP_VEX (int, int);
91 static void OP_EX_Vex (int, int);
92 static void OP_EX_VexW (int, int);
93 static void OP_EX_VexImmW (int, int);
94 static void OP_XMM_Vex (int, int);
95 static void OP_XMM_VexW (int, int);
96 static void OP_Rounding (int, int);
97 static void OP_REG_VexI4 (int, int);
98 static void PCLMUL_Fixup (int, int);
99 static void VCMP_Fixup (int, int);
100 static void VPCMP_Fixup (int, int);
101 static void VPCOM_Fixup (int, int);
102 static void OP_0f07 (int, int);
103 static void OP_Monitor (int, int);
104 static void OP_Mwait (int, int);
105 static void NOP_Fixup1 (int, int);
106 static void NOP_Fixup2 (int, int);
107 static void OP_3DNowSuffix (int, int);
108 static void CMP_Fixup (int, int);
109 static void BadOp (void);
110 static void REP_Fixup (int, int);
111 static void SEP_Fixup (int, int);
112 static void BND_Fixup (int, int);
113 static void NOTRACK_Fixup (int, int);
114 static void HLE_Fixup1 (int, int);
115 static void HLE_Fixup2 (int, int);
116 static void HLE_Fixup3 (int, int);
117 static void CMPXCHG8B_Fixup (int, int);
118 static void XMM_Fixup (int, int);
119 static void CRC32_Fixup (int, int);
120 static void FXSAVE_Fixup (int, int);
121 static void PCMPESTR_Fixup (int, int);
122 static void OP_LWPCB_E (int, int);
123 static void OP_LWP_E (int, int);
124 static void OP_Vex_2src_1 (int, int);
125 static void OP_Vex_2src_2 (int, int);
127 static void MOVBE_Fixup (int, int);
128 static void MOVSXD_Fixup (int, int);
130 static void OP_Mask (int, int);
133 /* Points to first byte not fetched. */
134 bfd_byte
*max_fetched
;
135 bfd_byte the_buffer
[MAX_MNEM_SIZE
];
138 OPCODES_SIGJMP_BUF bailout
;
148 enum address_mode address_mode
;
150 /* Flags for the prefixes for the current instruction. See below. */
153 /* REX prefix the current instruction. See below. */
155 /* Bits of REX we've already used. */
157 /* Mark parts used in the REX prefix. When we are testing for
158 empty prefix (for 8bit register REX extension), just mask it
159 out. Otherwise test for REX bit is excuse for existence of REX
160 only in case value is nonzero. */
161 #define USED_REX(value) \
166 rex_used |= (value) | REX_OPCODE; \
169 rex_used |= REX_OPCODE; \
172 /* Flags for prefixes which we somehow handled when printing the
173 current instruction. */
174 static int used_prefixes
;
176 /* Flags stored in PREFIXES. */
177 #define PREFIX_REPZ 1
178 #define PREFIX_REPNZ 2
179 #define PREFIX_LOCK 4
181 #define PREFIX_SS 0x10
182 #define PREFIX_DS 0x20
183 #define PREFIX_ES 0x40
184 #define PREFIX_FS 0x80
185 #define PREFIX_GS 0x100
186 #define PREFIX_DATA 0x200
187 #define PREFIX_ADDR 0x400
188 #define PREFIX_FWAIT 0x800
190 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
191 to ADDR (exclusive) are valid. Returns 1 for success, longjmps
193 #define FETCH_DATA(info, addr) \
194 ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
195 ? 1 : fetch_data ((info), (addr)))
198 fetch_data (struct disassemble_info
*info
, bfd_byte
*addr
)
201 struct dis_private
*priv
= (struct dis_private
*) info
->private_data
;
202 bfd_vma start
= priv
->insn_start
+ (priv
->max_fetched
- priv
->the_buffer
);
204 if (addr
<= priv
->the_buffer
+ MAX_MNEM_SIZE
)
205 status
= (*info
->read_memory_func
) (start
,
207 addr
- priv
->max_fetched
,
213 /* If we did manage to read at least one byte, then
214 print_insn_i386 will do something sensible. Otherwise, print
215 an error. We do that here because this is where we know
217 if (priv
->max_fetched
== priv
->the_buffer
)
218 (*info
->memory_error_func
) (status
, start
, info
);
219 OPCODES_SIGLONGJMP (priv
->bailout
, 1);
222 priv
->max_fetched
= addr
;
226 /* Possible values for prefix requirement. */
227 #define PREFIX_IGNORED_SHIFT 16
228 #define PREFIX_IGNORED_REPZ (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
229 #define PREFIX_IGNORED_REPNZ (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
230 #define PREFIX_IGNORED_DATA (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
231 #define PREFIX_IGNORED_ADDR (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
232 #define PREFIX_IGNORED_LOCK (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
234 /* Opcode prefixes. */
235 #define PREFIX_OPCODE (PREFIX_REPZ \
239 /* Prefixes ignored. */
240 #define PREFIX_IGNORED (PREFIX_IGNORED_REPZ \
241 | PREFIX_IGNORED_REPNZ \
242 | PREFIX_IGNORED_DATA)
244 #define XX { NULL, 0 }
245 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
247 #define Eb { OP_E, b_mode }
248 #define Ebnd { OP_E, bnd_mode }
249 #define EbS { OP_E, b_swap_mode }
250 #define EbndS { OP_E, bnd_swap_mode }
251 #define Ev { OP_E, v_mode }
252 #define Eva { OP_E, va_mode }
253 #define Ev_bnd { OP_E, v_bnd_mode }
254 #define EvS { OP_E, v_swap_mode }
255 #define Ed { OP_E, d_mode }
256 #define Edq { OP_E, dq_mode }
257 #define Edqw { OP_E, dqw_mode }
258 #define Edqb { OP_E, dqb_mode }
259 #define Edb { OP_E, db_mode }
260 #define Edw { OP_E, dw_mode }
261 #define Edqd { OP_E, dqd_mode }
262 #define Eq { OP_E, q_mode }
263 #define indirEv { OP_indirE, indir_v_mode }
264 #define indirEp { OP_indirE, f_mode }
265 #define stackEv { OP_E, stack_v_mode }
266 #define Em { OP_E, m_mode }
267 #define Ew { OP_E, w_mode }
268 #define M { OP_M, 0 } /* lea, lgdt, etc. */
269 #define Ma { OP_M, a_mode }
270 #define Mb { OP_M, b_mode }
271 #define Md { OP_M, d_mode }
272 #define Mo { OP_M, o_mode }
273 #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */
274 #define Mq { OP_M, q_mode }
275 #define Mv_bnd { OP_M, v_bndmk_mode }
276 #define Mx { OP_M, x_mode }
277 #define Mxmm { OP_M, xmm_mode }
278 #define Gb { OP_G, b_mode }
279 #define Gbnd { OP_G, bnd_mode }
280 #define Gv { OP_G, v_mode }
281 #define Gd { OP_G, d_mode }
282 #define Gdq { OP_G, dq_mode }
283 #define Gm { OP_G, m_mode }
284 #define Gva { OP_G, va_mode }
285 #define Gw { OP_G, w_mode }
286 #define Rd { OP_R, d_mode }
287 #define Rdq { OP_R, dq_mode }
288 #define Rm { OP_R, m_mode }
289 #define Ib { OP_I, b_mode }
290 #define sIb { OP_sI, b_mode } /* sign extened byte */
291 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
292 #define Iv { OP_I, v_mode }
293 #define sIv { OP_sI, v_mode }
294 #define Iv64 { OP_I64, v_mode }
295 #define Id { OP_I, d_mode }
296 #define Iw { OP_I, w_mode }
297 #define I1 { OP_I, const_1_mode }
298 #define Jb { OP_J, b_mode }
299 #define Jv { OP_J, v_mode }
300 #define Jdqw { OP_J, dqw_mode }
301 #define Cm { OP_C, m_mode }
302 #define Dm { OP_D, m_mode }
303 #define Td { OP_T, d_mode }
304 #define Skip_MODRM { OP_Skip_MODRM, 0 }
306 #define RMeAX { OP_REG, eAX_reg }
307 #define RMeBX { OP_REG, eBX_reg }
308 #define RMeCX { OP_REG, eCX_reg }
309 #define RMeDX { OP_REG, eDX_reg }
310 #define RMeSP { OP_REG, eSP_reg }
311 #define RMeBP { OP_REG, eBP_reg }
312 #define RMeSI { OP_REG, eSI_reg }
313 #define RMeDI { OP_REG, eDI_reg }
314 #define RMrAX { OP_REG, rAX_reg }
315 #define RMrBX { OP_REG, rBX_reg }
316 #define RMrCX { OP_REG, rCX_reg }
317 #define RMrDX { OP_REG, rDX_reg }
318 #define RMrSP { OP_REG, rSP_reg }
319 #define RMrBP { OP_REG, rBP_reg }
320 #define RMrSI { OP_REG, rSI_reg }
321 #define RMrDI { OP_REG, rDI_reg }
322 #define RMAL { OP_REG, al_reg }
323 #define RMCL { OP_REG, cl_reg }
324 #define RMDL { OP_REG, dl_reg }
325 #define RMBL { OP_REG, bl_reg }
326 #define RMAH { OP_REG, ah_reg }
327 #define RMCH { OP_REG, ch_reg }
328 #define RMDH { OP_REG, dh_reg }
329 #define RMBH { OP_REG, bh_reg }
330 #define RMAX { OP_REG, ax_reg }
331 #define RMDX { OP_REG, dx_reg }
333 #define eAX { OP_IMREG, eAX_reg }
334 #define eBX { OP_IMREG, eBX_reg }
335 #define eCX { OP_IMREG, eCX_reg }
336 #define eDX { OP_IMREG, eDX_reg }
337 #define eSP { OP_IMREG, eSP_reg }
338 #define eBP { OP_IMREG, eBP_reg }
339 #define eSI { OP_IMREG, eSI_reg }
340 #define eDI { OP_IMREG, eDI_reg }
341 #define AL { OP_IMREG, al_reg }
342 #define CL { OP_IMREG, cl_reg }
343 #define DL { OP_IMREG, dl_reg }
344 #define BL { OP_IMREG, bl_reg }
345 #define AH { OP_IMREG, ah_reg }
346 #define CH { OP_IMREG, ch_reg }
347 #define DH { OP_IMREG, dh_reg }
348 #define BH { OP_IMREG, bh_reg }
349 #define AX { OP_IMREG, ax_reg }
350 #define DX { OP_IMREG, dx_reg }
351 #define zAX { OP_IMREG, z_mode_ax_reg }
352 #define indirDX { OP_IMREG, indir_dx_reg }
354 #define Sw { OP_SEG, w_mode }
355 #define Sv { OP_SEG, v_mode }
356 #define Ap { OP_DIR, 0 }
357 #define Ob { OP_OFF64, b_mode }
358 #define Ov { OP_OFF64, v_mode }
359 #define Xb { OP_DSreg, eSI_reg }
360 #define Xv { OP_DSreg, eSI_reg }
361 #define Xz { OP_DSreg, eSI_reg }
362 #define Yb { OP_ESreg, eDI_reg }
363 #define Yv { OP_ESreg, eDI_reg }
364 #define DSBX { OP_DSreg, eBX_reg }
366 #define es { OP_REG, es_reg }
367 #define ss { OP_REG, ss_reg }
368 #define cs { OP_REG, cs_reg }
369 #define ds { OP_REG, ds_reg }
370 #define fs { OP_REG, fs_reg }
371 #define gs { OP_REG, gs_reg }
373 #define MX { OP_MMX, 0 }
374 #define XM { OP_XMM, 0 }
375 #define XMScalar { OP_XMM, scalar_mode }
376 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
377 #define XMM { OP_XMM, xmm_mode }
378 #define XMxmmq { OP_XMM, xmmq_mode }
379 #define EM { OP_EM, v_mode }
380 #define EMS { OP_EM, v_swap_mode }
381 #define EMd { OP_EM, d_mode }
382 #define EMx { OP_EM, x_mode }
383 #define EXbScalar { OP_EX, b_scalar_mode }
384 #define EXw { OP_EX, w_mode }
385 #define EXwScalar { OP_EX, w_scalar_mode }
386 #define EXd { OP_EX, d_mode }
387 #define EXdS { OP_EX, d_swap_mode }
388 #define EXq { OP_EX, q_mode }
389 #define EXqS { OP_EX, q_swap_mode }
390 #define EXx { OP_EX, x_mode }
391 #define EXxS { OP_EX, x_swap_mode }
392 #define EXxmm { OP_EX, xmm_mode }
393 #define EXymm { OP_EX, ymm_mode }
394 #define EXxmmq { OP_EX, xmmq_mode }
395 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
396 #define EXxmm_mb { OP_EX, xmm_mb_mode }
397 #define EXxmm_mw { OP_EX, xmm_mw_mode }
398 #define EXxmm_md { OP_EX, xmm_md_mode }
399 #define EXxmm_mq { OP_EX, xmm_mq_mode }
400 #define EXxmmdw { OP_EX, xmmdw_mode }
401 #define EXxmmqd { OP_EX, xmmqd_mode }
402 #define EXymmq { OP_EX, ymmq_mode }
403 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
404 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
405 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
406 #define MS { OP_MS, v_mode }
407 #define XS { OP_XS, v_mode }
408 #define EMCq { OP_EMC, q_mode }
409 #define MXC { OP_MXC, 0 }
410 #define OPSUF { OP_3DNowSuffix, 0 }
411 #define SEP { SEP_Fixup, 0 }
412 #define CMP { CMP_Fixup, 0 }
413 #define XMM0 { XMM_Fixup, 0 }
414 #define FXSAVE { FXSAVE_Fixup, 0 }
415 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
416 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
418 #define Vex { OP_VEX, vex_mode }
419 #define VexScalar { OP_VEX, vex_scalar_mode }
420 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
421 #define Vex128 { OP_VEX, vex128_mode }
422 #define Vex256 { OP_VEX, vex256_mode }
423 #define VexGdq { OP_VEX, dq_mode }
424 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
425 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
426 #define EXVexW { OP_EX_VexW, x_mode }
427 #define EXdVexW { OP_EX_VexW, d_mode }
428 #define EXqVexW { OP_EX_VexW, q_mode }
429 #define EXVexImmW { OP_EX_VexImmW, x_mode }
430 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
431 #define XMVexW { OP_XMM_VexW, 0 }
432 #define XMVexI4 { OP_REG_VexI4, x_mode }
433 #define PCLMUL { PCLMUL_Fixup, 0 }
434 #define VCMP { VCMP_Fixup, 0 }
435 #define VPCMP { VPCMP_Fixup, 0 }
436 #define VPCOM { VPCOM_Fixup, 0 }
438 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
439 #define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode }
440 #define EXxEVexS { OP_Rounding, evex_sae_mode }
442 #define XMask { OP_Mask, mask_mode }
443 #define MaskG { OP_G, mask_mode }
444 #define MaskE { OP_E, mask_mode }
445 #define MaskBDE { OP_E, mask_bd_mode }
446 #define MaskR { OP_R, mask_mode }
447 #define MaskVex { OP_VEX, mask_mode }
449 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
450 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
451 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
452 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
454 /* Used handle "rep" prefix for string instructions. */
455 #define Xbr { REP_Fixup, eSI_reg }
456 #define Xvr { REP_Fixup, eSI_reg }
457 #define Ybr { REP_Fixup, eDI_reg }
458 #define Yvr { REP_Fixup, eDI_reg }
459 #define Yzr { REP_Fixup, eDI_reg }
460 #define indirDXr { REP_Fixup, indir_dx_reg }
461 #define ALr { REP_Fixup, al_reg }
462 #define eAXr { REP_Fixup, eAX_reg }
464 /* Used handle HLE prefix for lockable instructions. */
465 #define Ebh1 { HLE_Fixup1, b_mode }
466 #define Evh1 { HLE_Fixup1, v_mode }
467 #define Ebh2 { HLE_Fixup2, b_mode }
468 #define Evh2 { HLE_Fixup2, v_mode }
469 #define Ebh3 { HLE_Fixup3, b_mode }
470 #define Evh3 { HLE_Fixup3, v_mode }
472 #define BND { BND_Fixup, 0 }
473 #define NOTRACK { NOTRACK_Fixup, 0 }
475 #define cond_jump_flag { NULL, cond_jump_mode }
476 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
478 /* bits in sizeflag */
479 #define SUFFIX_ALWAYS 4
487 /* byte operand with operand swapped */
489 /* byte operand, sign extend like 'T' suffix */
491 /* operand size depends on prefixes */
493 /* operand size depends on prefixes with operand swapped */
495 /* operand size depends on address prefix */
499 /* double word operand */
501 /* double word operand with operand swapped */
503 /* quad word operand */
505 /* quad word operand with operand swapped */
507 /* ten-byte operand */
509 /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand. In EVEX with
510 broadcast enabled. */
512 /* Similar to x_mode, but with different EVEX mem shifts. */
514 /* Similar to x_mode, but with disabled broadcast. */
516 /* Similar to x_mode, but with operands swapped and disabled broadcast
519 /* 16-byte XMM operand */
521 /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
522 memory operand (depending on vector length). Broadcast isn't
525 /* Same as xmmq_mode, but broadcast is allowed. */
526 evex_half_bcst_xmmq_mode
,
527 /* XMM register or byte memory operand */
529 /* XMM register or word memory operand */
531 /* XMM register or double word memory operand */
533 /* XMM register or quad word memory operand */
535 /* 16-byte XMM, word, double word or quad word operand. */
537 /* 16-byte XMM, double word, quad word operand or xmm word operand. */
539 /* 32-byte YMM operand */
541 /* quad word, ymmword or zmmword memory operand. */
543 /* 32-byte YMM or 16-byte word operand */
545 /* d_mode in 32bit, q_mode in 64bit mode. */
547 /* pair of v_mode operands */
553 /* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode. */
555 /* operand size depends on REX prefixes. */
557 /* registers like dq_mode, memory like w_mode, displacements like
558 v_mode without considering Intel64 ISA. */
562 /* bounds operand with operand swapped */
564 /* 4- or 6-byte pointer operand */
567 /* v_mode for indirect branch opcodes. */
569 /* v_mode for stack-related opcodes. */
571 /* non-quad operand size depends on prefixes */
573 /* 16-byte operand */
575 /* registers like dq_mode, memory like b_mode. */
577 /* registers like d_mode, memory like b_mode. */
579 /* registers like d_mode, memory like w_mode. */
581 /* registers like dq_mode, memory like d_mode. */
583 /* normal vex mode */
585 /* 128bit vex mode */
587 /* 256bit vex mode */
590 /* Operand size depends on the VEX.W bit, with VSIB dword indices. */
591 vex_vsib_d_w_dq_mode
,
592 /* Similar to vex_vsib_d_w_dq_mode, with smaller memory. */
594 /* Operand size depends on the VEX.W bit, with VSIB qword indices. */
595 vex_vsib_q_w_dq_mode
,
596 /* Similar to vex_vsib_q_w_dq_mode, with smaller memory. */
599 /* scalar, ignore vector length. */
601 /* like b_mode, ignore vector length. */
603 /* like w_mode, ignore vector length. */
605 /* like d_swap_mode, ignore vector length. */
607 /* like q_swap_mode, ignore vector length. */
609 /* like vex_mode, ignore vector length. */
611 /* Operand size depends on the VEX.W bit, ignore vector length. */
612 vex_scalar_w_dq_mode
,
614 /* Static rounding. */
616 /* Static rounding, 64-bit mode only. */
617 evex_rounding_64_mode
,
618 /* Supress all exceptions. */
621 /* Mask register operand. */
623 /* Mask register operand. */
691 #define FLOAT NULL, { { NULL, FLOATCODE } }, 0
693 #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }, 0
694 #define DIS386_PREFIX(T, I, P) NULL, { { NULL, (T)}, { NULL, (I) } }, P
695 #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I))
696 #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I))
697 #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I))
698 #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I))
699 #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I))
700 #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I))
701 #define THREE_BYTE_TABLE_PREFIX(I, P) DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
702 #define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I))
703 #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I))
704 #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I))
705 #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I))
706 #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I))
707 #define EVEX_TABLE(I) DIS386 (USE_EVEX_TABLE, (I))
708 #define EVEX_LEN_TABLE(I) DIS386 (USE_EVEX_LEN_TABLE, (I))
838 MOD_VEX_0F12_PREFIX_0
,
839 MOD_VEX_0F12_PREFIX_2
,
841 MOD_VEX_0F16_PREFIX_0
,
842 MOD_VEX_0F16_PREFIX_2
,
845 MOD_VEX_W_0_0F41_P_0_LEN_1
,
846 MOD_VEX_W_1_0F41_P_0_LEN_1
,
847 MOD_VEX_W_0_0F41_P_2_LEN_1
,
848 MOD_VEX_W_1_0F41_P_2_LEN_1
,
849 MOD_VEX_W_0_0F42_P_0_LEN_1
,
850 MOD_VEX_W_1_0F42_P_0_LEN_1
,
851 MOD_VEX_W_0_0F42_P_2_LEN_1
,
852 MOD_VEX_W_1_0F42_P_2_LEN_1
,
853 MOD_VEX_W_0_0F44_P_0_LEN_1
,
854 MOD_VEX_W_1_0F44_P_0_LEN_1
,
855 MOD_VEX_W_0_0F44_P_2_LEN_1
,
856 MOD_VEX_W_1_0F44_P_2_LEN_1
,
857 MOD_VEX_W_0_0F45_P_0_LEN_1
,
858 MOD_VEX_W_1_0F45_P_0_LEN_1
,
859 MOD_VEX_W_0_0F45_P_2_LEN_1
,
860 MOD_VEX_W_1_0F45_P_2_LEN_1
,
861 MOD_VEX_W_0_0F46_P_0_LEN_1
,
862 MOD_VEX_W_1_0F46_P_0_LEN_1
,
863 MOD_VEX_W_0_0F46_P_2_LEN_1
,
864 MOD_VEX_W_1_0F46_P_2_LEN_1
,
865 MOD_VEX_W_0_0F47_P_0_LEN_1
,
866 MOD_VEX_W_1_0F47_P_0_LEN_1
,
867 MOD_VEX_W_0_0F47_P_2_LEN_1
,
868 MOD_VEX_W_1_0F47_P_2_LEN_1
,
869 MOD_VEX_W_0_0F4A_P_0_LEN_1
,
870 MOD_VEX_W_1_0F4A_P_0_LEN_1
,
871 MOD_VEX_W_0_0F4A_P_2_LEN_1
,
872 MOD_VEX_W_1_0F4A_P_2_LEN_1
,
873 MOD_VEX_W_0_0F4B_P_0_LEN_1
,
874 MOD_VEX_W_1_0F4B_P_0_LEN_1
,
875 MOD_VEX_W_0_0F4B_P_2_LEN_1
,
887 MOD_VEX_W_0_0F91_P_0_LEN_0
,
888 MOD_VEX_W_1_0F91_P_0_LEN_0
,
889 MOD_VEX_W_0_0F91_P_2_LEN_0
,
890 MOD_VEX_W_1_0F91_P_2_LEN_0
,
891 MOD_VEX_W_0_0F92_P_0_LEN_0
,
892 MOD_VEX_W_0_0F92_P_2_LEN_0
,
893 MOD_VEX_0F92_P_3_LEN_0
,
894 MOD_VEX_W_0_0F93_P_0_LEN_0
,
895 MOD_VEX_W_0_0F93_P_2_LEN_0
,
896 MOD_VEX_0F93_P_3_LEN_0
,
897 MOD_VEX_W_0_0F98_P_0_LEN_0
,
898 MOD_VEX_W_1_0F98_P_0_LEN_0
,
899 MOD_VEX_W_0_0F98_P_2_LEN_0
,
900 MOD_VEX_W_1_0F98_P_2_LEN_0
,
901 MOD_VEX_W_0_0F99_P_0_LEN_0
,
902 MOD_VEX_W_1_0F99_P_0_LEN_0
,
903 MOD_VEX_W_0_0F99_P_2_LEN_0
,
904 MOD_VEX_W_1_0F99_P_2_LEN_0
,
907 MOD_VEX_0FD7_PREFIX_2
,
908 MOD_VEX_0FE7_PREFIX_2
,
909 MOD_VEX_0FF0_PREFIX_3
,
910 MOD_VEX_0F381A_PREFIX_2
,
911 MOD_VEX_0F382A_PREFIX_2
,
912 MOD_VEX_0F382C_PREFIX_2
,
913 MOD_VEX_0F382D_PREFIX_2
,
914 MOD_VEX_0F382E_PREFIX_2
,
915 MOD_VEX_0F382F_PREFIX_2
,
916 MOD_VEX_0F385A_PREFIX_2
,
917 MOD_VEX_0F388C_PREFIX_2
,
918 MOD_VEX_0F388E_PREFIX_2
,
919 MOD_VEX_W_0_0F3A30_P_2_LEN_0
,
920 MOD_VEX_W_1_0F3A30_P_2_LEN_0
,
921 MOD_VEX_W_0_0F3A31_P_2_LEN_0
,
922 MOD_VEX_W_1_0F3A31_P_2_LEN_0
,
923 MOD_VEX_W_0_0F3A32_P_2_LEN_0
,
924 MOD_VEX_W_1_0F3A32_P_2_LEN_0
,
925 MOD_VEX_W_0_0F3A33_P_2_LEN_0
,
926 MOD_VEX_W_1_0F3A33_P_2_LEN_0
,
928 MOD_EVEX_0F12_PREFIX_0
,
929 MOD_EVEX_0F12_PREFIX_2
,
931 MOD_EVEX_0F16_PREFIX_0
,
932 MOD_EVEX_0F16_PREFIX_2
,
935 MOD_EVEX_0F381A_P_2_W_0
,
936 MOD_EVEX_0F381A_P_2_W_1
,
937 MOD_EVEX_0F381B_P_2_W_0
,
938 MOD_EVEX_0F381B_P_2_W_1
,
939 MOD_EVEX_0F385A_P_2_W_0
,
940 MOD_EVEX_0F385A_P_2_W_1
,
941 MOD_EVEX_0F385B_P_2_W_0
,
942 MOD_EVEX_0F385B_P_2_W_1
,
943 MOD_EVEX_0F38C6_REG_1
,
944 MOD_EVEX_0F38C6_REG_2
,
945 MOD_EVEX_0F38C6_REG_5
,
946 MOD_EVEX_0F38C6_REG_6
,
947 MOD_EVEX_0F38C7_REG_1
,
948 MOD_EVEX_0F38C7_REG_2
,
949 MOD_EVEX_0F38C7_REG_5
,
950 MOD_EVEX_0F38C7_REG_6
963 RM_0F1E_P_1_MOD_3_REG_7
,
964 RM_0FAE_REG_6_MOD_3_P_0
,
971 PREFIX_0F01_REG_3_RM_1
,
972 PREFIX_0F01_REG_5_MOD_0
,
973 PREFIX_0F01_REG_5_MOD_3_RM_0
,
974 PREFIX_0F01_REG_5_MOD_3_RM_1
,
975 PREFIX_0F01_REG_5_MOD_3_RM_2
,
976 PREFIX_0F01_REG_7_MOD_3_RM_2
,
977 PREFIX_0F01_REG_7_MOD_3_RM_3
,
1019 PREFIX_0FAE_REG_0_MOD_3
,
1020 PREFIX_0FAE_REG_1_MOD_3
,
1021 PREFIX_0FAE_REG_2_MOD_3
,
1022 PREFIX_0FAE_REG_3_MOD_3
,
1023 PREFIX_0FAE_REG_4_MOD_0
,
1024 PREFIX_0FAE_REG_4_MOD_3
,
1025 PREFIX_0FAE_REG_5_MOD_0
,
1026 PREFIX_0FAE_REG_5_MOD_3
,
1027 PREFIX_0FAE_REG_6_MOD_0
,
1028 PREFIX_0FAE_REG_6_MOD_3
,
1029 PREFIX_0FAE_REG_7_MOD_0
,
1035 PREFIX_0FC7_REG_6_MOD_0
,
1036 PREFIX_0FC7_REG_6_MOD_3
,
1037 PREFIX_0FC7_REG_7_MOD_3
,
1167 PREFIX_VEX_0F71_REG_2
,
1168 PREFIX_VEX_0F71_REG_4
,
1169 PREFIX_VEX_0F71_REG_6
,
1170 PREFIX_VEX_0F72_REG_2
,
1171 PREFIX_VEX_0F72_REG_4
,
1172 PREFIX_VEX_0F72_REG_6
,
1173 PREFIX_VEX_0F73_REG_2
,
1174 PREFIX_VEX_0F73_REG_3
,
1175 PREFIX_VEX_0F73_REG_6
,
1176 PREFIX_VEX_0F73_REG_7
,
1349 PREFIX_VEX_0F38F3_REG_1
,
1350 PREFIX_VEX_0F38F3_REG_2
,
1351 PREFIX_VEX_0F38F3_REG_3
,
1448 PREFIX_EVEX_0F71_REG_2
,
1449 PREFIX_EVEX_0F71_REG_4
,
1450 PREFIX_EVEX_0F71_REG_6
,
1451 PREFIX_EVEX_0F72_REG_0
,
1452 PREFIX_EVEX_0F72_REG_1
,
1453 PREFIX_EVEX_0F72_REG_2
,
1454 PREFIX_EVEX_0F72_REG_4
,
1455 PREFIX_EVEX_0F72_REG_6
,
1456 PREFIX_EVEX_0F73_REG_2
,
1457 PREFIX_EVEX_0F73_REG_3
,
1458 PREFIX_EVEX_0F73_REG_6
,
1459 PREFIX_EVEX_0F73_REG_7
,
1581 PREFIX_EVEX_0F38C6_REG_1
,
1582 PREFIX_EVEX_0F38C6_REG_2
,
1583 PREFIX_EVEX_0F38C6_REG_5
,
1584 PREFIX_EVEX_0F38C6_REG_6
,
1585 PREFIX_EVEX_0F38C7_REG_1
,
1586 PREFIX_EVEX_0F38C7_REG_2
,
1587 PREFIX_EVEX_0F38C7_REG_5
,
1588 PREFIX_EVEX_0F38C7_REG_6
,
1681 THREE_BYTE_0F38
= 0,
1708 VEX_LEN_0F12_P_0_M_0
= 0,
1709 VEX_LEN_0F12_P_0_M_1
,
1710 #define VEX_LEN_0F12_P_2_M_0 VEX_LEN_0F12_P_0_M_0
1712 VEX_LEN_0F16_P_0_M_0
,
1713 VEX_LEN_0F16_P_0_M_1
,
1714 #define VEX_LEN_0F16_P_2_M_0 VEX_LEN_0F16_P_0_M_0
1750 VEX_LEN_0FAE_R_2_M_0
,
1751 VEX_LEN_0FAE_R_3_M_0
,
1758 VEX_LEN_0F381A_P_2_M_0
,
1761 VEX_LEN_0F385A_P_2_M_0
,
1764 VEX_LEN_0F38F3_R_1_P_0
,
1765 VEX_LEN_0F38F3_R_2_P_0
,
1766 VEX_LEN_0F38F3_R_3_P_0
,
1809 VEX_LEN_0FXOP_08_CC
,
1810 VEX_LEN_0FXOP_08_CD
,
1811 VEX_LEN_0FXOP_08_CE
,
1812 VEX_LEN_0FXOP_08_CF
,
1813 VEX_LEN_0FXOP_08_EC
,
1814 VEX_LEN_0FXOP_08_ED
,
1815 VEX_LEN_0FXOP_08_EE
,
1816 VEX_LEN_0FXOP_08_EF
,
1817 VEX_LEN_0FXOP_09_82_W_0
,
1818 VEX_LEN_0FXOP_09_83_W_0
,
1823 EVEX_LEN_0F6E_P_2
= 0,
1829 EVEX_LEN_0F3816_P_2
,
1830 EVEX_LEN_0F3819_P_2_W_0
,
1831 EVEX_LEN_0F3819_P_2_W_1
,
1832 EVEX_LEN_0F381A_P_2_W_0_M_0
,
1833 EVEX_LEN_0F381A_P_2_W_1_M_0
,
1834 EVEX_LEN_0F381B_P_2_W_0_M_0
,
1835 EVEX_LEN_0F381B_P_2_W_1_M_0
,
1836 EVEX_LEN_0F3836_P_2
,
1837 EVEX_LEN_0F385A_P_2_W_0_M_0
,
1838 EVEX_LEN_0F385A_P_2_W_1_M_0
,
1839 EVEX_LEN_0F385B_P_2_W_0_M_0
,
1840 EVEX_LEN_0F385B_P_2_W_1_M_0
,
1841 EVEX_LEN_0F38C6_REG_1_PREFIX_2
,
1842 EVEX_LEN_0F38C6_REG_2_PREFIX_2
,
1843 EVEX_LEN_0F38C6_REG_5_PREFIX_2
,
1844 EVEX_LEN_0F38C6_REG_6_PREFIX_2
,
1845 EVEX_LEN_0F38C7_R_1_P_2_W_0
,
1846 EVEX_LEN_0F38C7_R_1_P_2_W_1
,
1847 EVEX_LEN_0F38C7_R_2_P_2_W_0
,
1848 EVEX_LEN_0F38C7_R_2_P_2_W_1
,
1849 EVEX_LEN_0F38C7_R_5_P_2_W_0
,
1850 EVEX_LEN_0F38C7_R_5_P_2_W_1
,
1851 EVEX_LEN_0F38C7_R_6_P_2_W_0
,
1852 EVEX_LEN_0F38C7_R_6_P_2_W_1
,
1853 EVEX_LEN_0F3A00_P_2_W_1
,
1854 EVEX_LEN_0F3A01_P_2_W_1
,
1855 EVEX_LEN_0F3A14_P_2
,
1856 EVEX_LEN_0F3A15_P_2
,
1857 EVEX_LEN_0F3A16_P_2
,
1858 EVEX_LEN_0F3A17_P_2
,
1859 EVEX_LEN_0F3A18_P_2_W_0
,
1860 EVEX_LEN_0F3A18_P_2_W_1
,
1861 EVEX_LEN_0F3A19_P_2_W_0
,
1862 EVEX_LEN_0F3A19_P_2_W_1
,
1863 EVEX_LEN_0F3A1A_P_2_W_0
,
1864 EVEX_LEN_0F3A1A_P_2_W_1
,
1865 EVEX_LEN_0F3A1B_P_2_W_0
,
1866 EVEX_LEN_0F3A1B_P_2_W_1
,
1867 EVEX_LEN_0F3A20_P_2
,
1868 EVEX_LEN_0F3A21_P_2_W_0
,
1869 EVEX_LEN_0F3A22_P_2
,
1870 EVEX_LEN_0F3A23_P_2_W_0
,
1871 EVEX_LEN_0F3A23_P_2_W_1
,
1872 EVEX_LEN_0F3A38_P_2_W_0
,
1873 EVEX_LEN_0F3A38_P_2_W_1
,
1874 EVEX_LEN_0F3A39_P_2_W_0
,
1875 EVEX_LEN_0F3A39_P_2_W_1
,
1876 EVEX_LEN_0F3A3A_P_2_W_0
,
1877 EVEX_LEN_0F3A3A_P_2_W_1
,
1878 EVEX_LEN_0F3A3B_P_2_W_0
,
1879 EVEX_LEN_0F3A3B_P_2_W_1
,
1880 EVEX_LEN_0F3A43_P_2_W_0
,
1881 EVEX_LEN_0F3A43_P_2_W_1
1886 VEX_W_0F41_P_0_LEN_1
= 0,
1887 VEX_W_0F41_P_2_LEN_1
,
1888 VEX_W_0F42_P_0_LEN_1
,
1889 VEX_W_0F42_P_2_LEN_1
,
1890 VEX_W_0F44_P_0_LEN_0
,
1891 VEX_W_0F44_P_2_LEN_0
,
1892 VEX_W_0F45_P_0_LEN_1
,
1893 VEX_W_0F45_P_2_LEN_1
,
1894 VEX_W_0F46_P_0_LEN_1
,
1895 VEX_W_0F46_P_2_LEN_1
,
1896 VEX_W_0F47_P_0_LEN_1
,
1897 VEX_W_0F47_P_2_LEN_1
,
1898 VEX_W_0F4A_P_0_LEN_1
,
1899 VEX_W_0F4A_P_2_LEN_1
,
1900 VEX_W_0F4B_P_0_LEN_1
,
1901 VEX_W_0F4B_P_2_LEN_1
,
1902 VEX_W_0F90_P_0_LEN_0
,
1903 VEX_W_0F90_P_2_LEN_0
,
1904 VEX_W_0F91_P_0_LEN_0
,
1905 VEX_W_0F91_P_2_LEN_0
,
1906 VEX_W_0F92_P_0_LEN_0
,
1907 VEX_W_0F92_P_2_LEN_0
,
1908 VEX_W_0F93_P_0_LEN_0
,
1909 VEX_W_0F93_P_2_LEN_0
,
1910 VEX_W_0F98_P_0_LEN_0
,
1911 VEX_W_0F98_P_2_LEN_0
,
1912 VEX_W_0F99_P_0_LEN_0
,
1913 VEX_W_0F99_P_2_LEN_0
,
1922 VEX_W_0F381A_P_2_M_0
,
1923 VEX_W_0F382C_P_2_M_0
,
1924 VEX_W_0F382D_P_2_M_0
,
1925 VEX_W_0F382E_P_2_M_0
,
1926 VEX_W_0F382F_P_2_M_0
,
1931 VEX_W_0F385A_P_2_M_0
,
1944 VEX_W_0F3A30_P_2_LEN_0
,
1945 VEX_W_0F3A31_P_2_LEN_0
,
1946 VEX_W_0F3A32_P_2_LEN_0
,
1947 VEX_W_0F3A33_P_2_LEN_0
,
1968 EVEX_W_0F12_P_0_M_1
,
1971 EVEX_W_0F16_P_0_M_1
,
2005 EVEX_W_0F72_R_2_P_2
,
2006 EVEX_W_0F72_R_6_P_2
,
2007 EVEX_W_0F73_R_2_P_2
,
2008 EVEX_W_0F73_R_6_P_2
,
2093 EVEX_W_0F38C7_R_1_P_2
,
2094 EVEX_W_0F38C7_R_2_P_2
,
2095 EVEX_W_0F38C7_R_5_P_2
,
2096 EVEX_W_0F38C7_R_6_P_2
,
2121 typedef void (*op_rtn
) (int bytemode
, int sizeflag
);
2130 unsigned int prefix_requirement
;
2133 /* Upper case letters in the instruction names here are macros.
2134 'A' => print 'b' if no register operands or suffix_always is true
2135 'B' => print 'b' if suffix_always is true
2136 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2138 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2139 suffix_always is true
2140 'E' => print 'e' if 32-bit form of jcxz
2141 'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2142 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2143 'H' => print ",pt" or ",pn" branch hint
2146 'K' => print 'd' or 'q' if rex prefix is present.
2147 'L' => print 'l' if suffix_always is true
2148 'M' => print 'r' if intel_mnemonic is false.
2149 'N' => print 'n' if instruction has no wait "prefix"
2150 'O' => print 'd' or 'o' (or 'q' in Intel mode)
2151 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2152 or suffix_always is true. print 'q' if rex prefix is present.
2153 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2155 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2156 'S' => print 'w', 'l' or 'q' if suffix_always is true
2157 'T' => print 'q' in 64bit mode if instruction has no operand size
2158 prefix and behave as 'P' otherwise
2159 'U' => print 'q' in 64bit mode if instruction has no operand size
2160 prefix and behave as 'Q' otherwise
2161 'V' => print 'q' in 64bit mode if instruction has no operand size
2162 prefix and behave as 'S' otherwise
2163 'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2164 'X' => print 's', 'd' depending on data16 prefix (for XMM)
2166 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2167 '!' => change condition from true to false or from false to true.
2168 '%' => add 1 upper case letter to the macro.
2169 '^' => print 'w', 'l', or 'q' (Intel64 ISA only) depending on operand size
2170 prefix or suffix_always is true (lcall/ljmp).
2171 '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending
2172 on operand size prefix.
2173 '&' => print 'q' in 64bit mode for Intel64 ISA or if instruction
2174 has no operand size prefix for AMD64 ISA, behave as 'P'
2177 2 upper case letter macros:
2178 "XY" => print 'x' or 'y' if suffix_always is true or no register
2179 operands and no broadcast.
2180 "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
2181 register operands and no broadcast.
2182 "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2183 "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory
2184 operand or no operand at all in 64bit mode, or if suffix_always
2186 "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2187 "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2188 "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2189 "LW" => print 'd', 'q' depending on the VEX.W bit
2190 "BW" => print 'b' or 'w' depending on the EVEX.W bit
2191 "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
2192 an operand size prefix, or suffix_always is true. print
2193 'q' if rex prefix is present.
2195 Many of the above letters print nothing in Intel mode. See "putop"
2198 Braces '{' and '}', and vertical bars '|', indicate alternative
2199 mnemonic strings for AT&T and Intel. */
2201 static const struct dis386 dis386
[] = {
2203 { "addB", { Ebh1
, Gb
}, 0 },
2204 { "addS", { Evh1
, Gv
}, 0 },
2205 { "addB", { Gb
, EbS
}, 0 },
2206 { "addS", { Gv
, EvS
}, 0 },
2207 { "addB", { AL
, Ib
}, 0 },
2208 { "addS", { eAX
, Iv
}, 0 },
2209 { X86_64_TABLE (X86_64_06
) },
2210 { X86_64_TABLE (X86_64_07
) },
2212 { "orB", { Ebh1
, Gb
}, 0 },
2213 { "orS", { Evh1
, Gv
}, 0 },
2214 { "orB", { Gb
, EbS
}, 0 },
2215 { "orS", { Gv
, EvS
}, 0 },
2216 { "orB", { AL
, Ib
}, 0 },
2217 { "orS", { eAX
, Iv
}, 0 },
2218 { X86_64_TABLE (X86_64_0E
) },
2219 { Bad_Opcode
}, /* 0x0f extended opcode escape */
2221 { "adcB", { Ebh1
, Gb
}, 0 },
2222 { "adcS", { Evh1
, Gv
}, 0 },
2223 { "adcB", { Gb
, EbS
}, 0 },
2224 { "adcS", { Gv
, EvS
}, 0 },
2225 { "adcB", { AL
, Ib
}, 0 },
2226 { "adcS", { eAX
, Iv
}, 0 },
2227 { X86_64_TABLE (X86_64_16
) },
2228 { X86_64_TABLE (X86_64_17
) },
2230 { "sbbB", { Ebh1
, Gb
}, 0 },
2231 { "sbbS", { Evh1
, Gv
}, 0 },
2232 { "sbbB", { Gb
, EbS
}, 0 },
2233 { "sbbS", { Gv
, EvS
}, 0 },
2234 { "sbbB", { AL
, Ib
}, 0 },
2235 { "sbbS", { eAX
, Iv
}, 0 },
2236 { X86_64_TABLE (X86_64_1E
) },
2237 { X86_64_TABLE (X86_64_1F
) },
2239 { "andB", { Ebh1
, Gb
}, 0 },
2240 { "andS", { Evh1
, Gv
}, 0 },
2241 { "andB", { Gb
, EbS
}, 0 },
2242 { "andS", { Gv
, EvS
}, 0 },
2243 { "andB", { AL
, Ib
}, 0 },
2244 { "andS", { eAX
, Iv
}, 0 },
2245 { Bad_Opcode
}, /* SEG ES prefix */
2246 { X86_64_TABLE (X86_64_27
) },
2248 { "subB", { Ebh1
, Gb
}, 0 },
2249 { "subS", { Evh1
, Gv
}, 0 },
2250 { "subB", { Gb
, EbS
}, 0 },
2251 { "subS", { Gv
, EvS
}, 0 },
2252 { "subB", { AL
, Ib
}, 0 },
2253 { "subS", { eAX
, Iv
}, 0 },
2254 { Bad_Opcode
}, /* SEG CS prefix */
2255 { X86_64_TABLE (X86_64_2F
) },
2257 { "xorB", { Ebh1
, Gb
}, 0 },
2258 { "xorS", { Evh1
, Gv
}, 0 },
2259 { "xorB", { Gb
, EbS
}, 0 },
2260 { "xorS", { Gv
, EvS
}, 0 },
2261 { "xorB", { AL
, Ib
}, 0 },
2262 { "xorS", { eAX
, Iv
}, 0 },
2263 { Bad_Opcode
}, /* SEG SS prefix */
2264 { X86_64_TABLE (X86_64_37
) },
2266 { "cmpB", { Eb
, Gb
}, 0 },
2267 { "cmpS", { Ev
, Gv
}, 0 },
2268 { "cmpB", { Gb
, EbS
}, 0 },
2269 { "cmpS", { Gv
, EvS
}, 0 },
2270 { "cmpB", { AL
, Ib
}, 0 },
2271 { "cmpS", { eAX
, Iv
}, 0 },
2272 { Bad_Opcode
}, /* SEG DS prefix */
2273 { X86_64_TABLE (X86_64_3F
) },
2275 { "inc{S|}", { RMeAX
}, 0 },
2276 { "inc{S|}", { RMeCX
}, 0 },
2277 { "inc{S|}", { RMeDX
}, 0 },
2278 { "inc{S|}", { RMeBX
}, 0 },
2279 { "inc{S|}", { RMeSP
}, 0 },
2280 { "inc{S|}", { RMeBP
}, 0 },
2281 { "inc{S|}", { RMeSI
}, 0 },
2282 { "inc{S|}", { RMeDI
}, 0 },
2284 { "dec{S|}", { RMeAX
}, 0 },
2285 { "dec{S|}", { RMeCX
}, 0 },
2286 { "dec{S|}", { RMeDX
}, 0 },
2287 { "dec{S|}", { RMeBX
}, 0 },
2288 { "dec{S|}", { RMeSP
}, 0 },
2289 { "dec{S|}", { RMeBP
}, 0 },
2290 { "dec{S|}", { RMeSI
}, 0 },
2291 { "dec{S|}", { RMeDI
}, 0 },
2293 { "pushV", { RMrAX
}, 0 },
2294 { "pushV", { RMrCX
}, 0 },
2295 { "pushV", { RMrDX
}, 0 },
2296 { "pushV", { RMrBX
}, 0 },
2297 { "pushV", { RMrSP
}, 0 },
2298 { "pushV", { RMrBP
}, 0 },
2299 { "pushV", { RMrSI
}, 0 },
2300 { "pushV", { RMrDI
}, 0 },
2302 { "popV", { RMrAX
}, 0 },
2303 { "popV", { RMrCX
}, 0 },
2304 { "popV", { RMrDX
}, 0 },
2305 { "popV", { RMrBX
}, 0 },
2306 { "popV", { RMrSP
}, 0 },
2307 { "popV", { RMrBP
}, 0 },
2308 { "popV", { RMrSI
}, 0 },
2309 { "popV", { RMrDI
}, 0 },
2311 { X86_64_TABLE (X86_64_60
) },
2312 { X86_64_TABLE (X86_64_61
) },
2313 { X86_64_TABLE (X86_64_62
) },
2314 { X86_64_TABLE (X86_64_63
) },
2315 { Bad_Opcode
}, /* seg fs */
2316 { Bad_Opcode
}, /* seg gs */
2317 { Bad_Opcode
}, /* op size prefix */
2318 { Bad_Opcode
}, /* adr size prefix */
2320 { "pushT", { sIv
}, 0 },
2321 { "imulS", { Gv
, Ev
, Iv
}, 0 },
2322 { "pushT", { sIbT
}, 0 },
2323 { "imulS", { Gv
, Ev
, sIb
}, 0 },
2324 { "ins{b|}", { Ybr
, indirDX
}, 0 },
2325 { X86_64_TABLE (X86_64_6D
) },
2326 { "outs{b|}", { indirDXr
, Xb
}, 0 },
2327 { X86_64_TABLE (X86_64_6F
) },
2329 { "joH", { Jb
, BND
, cond_jump_flag
}, 0 },
2330 { "jnoH", { Jb
, BND
, cond_jump_flag
}, 0 },
2331 { "jbH", { Jb
, BND
, cond_jump_flag
}, 0 },
2332 { "jaeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2333 { "jeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2334 { "jneH", { Jb
, BND
, cond_jump_flag
}, 0 },
2335 { "jbeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2336 { "jaH", { Jb
, BND
, cond_jump_flag
}, 0 },
2338 { "jsH", { Jb
, BND
, cond_jump_flag
}, 0 },
2339 { "jnsH", { Jb
, BND
, cond_jump_flag
}, 0 },
2340 { "jpH", { Jb
, BND
, cond_jump_flag
}, 0 },
2341 { "jnpH", { Jb
, BND
, cond_jump_flag
}, 0 },
2342 { "jlH", { Jb
, BND
, cond_jump_flag
}, 0 },
2343 { "jgeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2344 { "jleH", { Jb
, BND
, cond_jump_flag
}, 0 },
2345 { "jgH", { Jb
, BND
, cond_jump_flag
}, 0 },
2347 { REG_TABLE (REG_80
) },
2348 { REG_TABLE (REG_81
) },
2349 { X86_64_TABLE (X86_64_82
) },
2350 { REG_TABLE (REG_83
) },
2351 { "testB", { Eb
, Gb
}, 0 },
2352 { "testS", { Ev
, Gv
}, 0 },
2353 { "xchgB", { Ebh2
, Gb
}, 0 },
2354 { "xchgS", { Evh2
, Gv
}, 0 },
2356 { "movB", { Ebh3
, Gb
}, 0 },
2357 { "movS", { Evh3
, Gv
}, 0 },
2358 { "movB", { Gb
, EbS
}, 0 },
2359 { "movS", { Gv
, EvS
}, 0 },
2360 { "movD", { Sv
, Sw
}, 0 },
2361 { MOD_TABLE (MOD_8D
) },
2362 { "movD", { Sw
, Sv
}, 0 },
2363 { REG_TABLE (REG_8F
) },
2365 { PREFIX_TABLE (PREFIX_90
) },
2366 { "xchgS", { RMeCX
, eAX
}, 0 },
2367 { "xchgS", { RMeDX
, eAX
}, 0 },
2368 { "xchgS", { RMeBX
, eAX
}, 0 },
2369 { "xchgS", { RMeSP
, eAX
}, 0 },
2370 { "xchgS", { RMeBP
, eAX
}, 0 },
2371 { "xchgS", { RMeSI
, eAX
}, 0 },
2372 { "xchgS", { RMeDI
, eAX
}, 0 },
2374 { "cW{t|}R", { XX
}, 0 },
2375 { "cR{t|}O", { XX
}, 0 },
2376 { X86_64_TABLE (X86_64_9A
) },
2377 { Bad_Opcode
}, /* fwait */
2378 { "pushfT", { XX
}, 0 },
2379 { "popfT", { XX
}, 0 },
2380 { "sahf", { XX
}, 0 },
2381 { "lahf", { XX
}, 0 },
2383 { "mov%LB", { AL
, Ob
}, 0 },
2384 { "mov%LS", { eAX
, Ov
}, 0 },
2385 { "mov%LB", { Ob
, AL
}, 0 },
2386 { "mov%LS", { Ov
, eAX
}, 0 },
2387 { "movs{b|}", { Ybr
, Xb
}, 0 },
2388 { "movs{R|}", { Yvr
, Xv
}, 0 },
2389 { "cmps{b|}", { Xb
, Yb
}, 0 },
2390 { "cmps{R|}", { Xv
, Yv
}, 0 },
2392 { "testB", { AL
, Ib
}, 0 },
2393 { "testS", { eAX
, Iv
}, 0 },
2394 { "stosB", { Ybr
, AL
}, 0 },
2395 { "stosS", { Yvr
, eAX
}, 0 },
2396 { "lodsB", { ALr
, Xb
}, 0 },
2397 { "lodsS", { eAXr
, Xv
}, 0 },
2398 { "scasB", { AL
, Yb
}, 0 },
2399 { "scasS", { eAX
, Yv
}, 0 },
2401 { "movB", { RMAL
, Ib
}, 0 },
2402 { "movB", { RMCL
, Ib
}, 0 },
2403 { "movB", { RMDL
, Ib
}, 0 },
2404 { "movB", { RMBL
, Ib
}, 0 },
2405 { "movB", { RMAH
, Ib
}, 0 },
2406 { "movB", { RMCH
, Ib
}, 0 },
2407 { "movB", { RMDH
, Ib
}, 0 },
2408 { "movB", { RMBH
, Ib
}, 0 },
2410 { "mov%LV", { RMeAX
, Iv64
}, 0 },
2411 { "mov%LV", { RMeCX
, Iv64
}, 0 },
2412 { "mov%LV", { RMeDX
, Iv64
}, 0 },
2413 { "mov%LV", { RMeBX
, Iv64
}, 0 },
2414 { "mov%LV", { RMeSP
, Iv64
}, 0 },
2415 { "mov%LV", { RMeBP
, Iv64
}, 0 },
2416 { "mov%LV", { RMeSI
, Iv64
}, 0 },
2417 { "mov%LV", { RMeDI
, Iv64
}, 0 },
2419 { REG_TABLE (REG_C0
) },
2420 { REG_TABLE (REG_C1
) },
2421 { X86_64_TABLE (X86_64_C2
) },
2422 { X86_64_TABLE (X86_64_C3
) },
2423 { X86_64_TABLE (X86_64_C4
) },
2424 { X86_64_TABLE (X86_64_C5
) },
2425 { REG_TABLE (REG_C6
) },
2426 { REG_TABLE (REG_C7
) },
2428 { "enterT", { Iw
, Ib
}, 0 },
2429 { "leaveT", { XX
}, 0 },
2430 { "{l|}ret{|f}P", { Iw
}, 0 },
2431 { "{l|}ret{|f}P", { XX
}, 0 },
2432 { "int3", { XX
}, 0 },
2433 { "int", { Ib
}, 0 },
2434 { X86_64_TABLE (X86_64_CE
) },
2435 { "iret%LP", { XX
}, 0 },
2437 { REG_TABLE (REG_D0
) },
2438 { REG_TABLE (REG_D1
) },
2439 { REG_TABLE (REG_D2
) },
2440 { REG_TABLE (REG_D3
) },
2441 { X86_64_TABLE (X86_64_D4
) },
2442 { X86_64_TABLE (X86_64_D5
) },
2444 { "xlat", { DSBX
}, 0 },
2455 { "loopneFH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2456 { "loopeFH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2457 { "loopFH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2458 { "jEcxzH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2459 { "inB", { AL
, Ib
}, 0 },
2460 { "inG", { zAX
, Ib
}, 0 },
2461 { "outB", { Ib
, AL
}, 0 },
2462 { "outG", { Ib
, zAX
}, 0 },
2464 { X86_64_TABLE (X86_64_E8
) },
2465 { X86_64_TABLE (X86_64_E9
) },
2466 { X86_64_TABLE (X86_64_EA
) },
2467 { "jmp", { Jb
, BND
}, 0 },
2468 { "inB", { AL
, indirDX
}, 0 },
2469 { "inG", { zAX
, indirDX
}, 0 },
2470 { "outB", { indirDX
, AL
}, 0 },
2471 { "outG", { indirDX
, zAX
}, 0 },
2473 { Bad_Opcode
}, /* lock prefix */
2474 { "icebp", { XX
}, 0 },
2475 { Bad_Opcode
}, /* repne */
2476 { Bad_Opcode
}, /* repz */
2477 { "hlt", { XX
}, 0 },
2478 { "cmc", { XX
}, 0 },
2479 { REG_TABLE (REG_F6
) },
2480 { REG_TABLE (REG_F7
) },
2482 { "clc", { XX
}, 0 },
2483 { "stc", { XX
}, 0 },
2484 { "cli", { XX
}, 0 },
2485 { "sti", { XX
}, 0 },
2486 { "cld", { XX
}, 0 },
2487 { "std", { XX
}, 0 },
2488 { REG_TABLE (REG_FE
) },
2489 { REG_TABLE (REG_FF
) },
2492 static const struct dis386 dis386_twobyte
[] = {
2494 { REG_TABLE (REG_0F00
) },
2495 { REG_TABLE (REG_0F01
) },
2496 { "larS", { Gv
, Ew
}, 0 },
2497 { "lslS", { Gv
, Ew
}, 0 },
2499 { "syscall", { XX
}, 0 },
2500 { "clts", { XX
}, 0 },
2501 { "sysret%LQ", { XX
}, 0 },
2503 { "invd", { XX
}, 0 },
2504 { PREFIX_TABLE (PREFIX_0F09
) },
2506 { "ud2", { XX
}, 0 },
2508 { REG_TABLE (REG_0F0D
) },
2509 { "femms", { XX
}, 0 },
2510 { "", { MX
, EM
, OPSUF
}, 0 }, /* See OP_3DNowSuffix. */
2512 { PREFIX_TABLE (PREFIX_0F10
) },
2513 { PREFIX_TABLE (PREFIX_0F11
) },
2514 { PREFIX_TABLE (PREFIX_0F12
) },
2515 { MOD_TABLE (MOD_0F13
) },
2516 { "unpcklpX", { XM
, EXx
}, PREFIX_OPCODE
},
2517 { "unpckhpX", { XM
, EXx
}, PREFIX_OPCODE
},
2518 { PREFIX_TABLE (PREFIX_0F16
) },
2519 { MOD_TABLE (MOD_0F17
) },
2521 { REG_TABLE (REG_0F18
) },
2522 { "nopQ", { Ev
}, 0 },
2523 { PREFIX_TABLE (PREFIX_0F1A
) },
2524 { PREFIX_TABLE (PREFIX_0F1B
) },
2525 { PREFIX_TABLE (PREFIX_0F1C
) },
2526 { "nopQ", { Ev
}, 0 },
2527 { PREFIX_TABLE (PREFIX_0F1E
) },
2528 { "nopQ", { Ev
}, 0 },
2530 { "movZ", { Rm
, Cm
}, 0 },
2531 { "movZ", { Rm
, Dm
}, 0 },
2532 { "movZ", { Cm
, Rm
}, 0 },
2533 { "movZ", { Dm
, Rm
}, 0 },
2534 { MOD_TABLE (MOD_0F24
) },
2536 { MOD_TABLE (MOD_0F26
) },
2539 { "movapX", { XM
, EXx
}, PREFIX_OPCODE
},
2540 { "movapX", { EXxS
, XM
}, PREFIX_OPCODE
},
2541 { PREFIX_TABLE (PREFIX_0F2A
) },
2542 { PREFIX_TABLE (PREFIX_0F2B
) },
2543 { PREFIX_TABLE (PREFIX_0F2C
) },
2544 { PREFIX_TABLE (PREFIX_0F2D
) },
2545 { PREFIX_TABLE (PREFIX_0F2E
) },
2546 { PREFIX_TABLE (PREFIX_0F2F
) },
2548 { "wrmsr", { XX
}, 0 },
2549 { "rdtsc", { XX
}, 0 },
2550 { "rdmsr", { XX
}, 0 },
2551 { "rdpmc", { XX
}, 0 },
2552 { "sysenter", { SEP
}, 0 },
2553 { "sysexit", { SEP
}, 0 },
2555 { "getsec", { XX
}, 0 },
2557 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38
, PREFIX_OPCODE
) },
2559 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A
, PREFIX_OPCODE
) },
2566 { "cmovoS", { Gv
, Ev
}, 0 },
2567 { "cmovnoS", { Gv
, Ev
}, 0 },
2568 { "cmovbS", { Gv
, Ev
}, 0 },
2569 { "cmovaeS", { Gv
, Ev
}, 0 },
2570 { "cmoveS", { Gv
, Ev
}, 0 },
2571 { "cmovneS", { Gv
, Ev
}, 0 },
2572 { "cmovbeS", { Gv
, Ev
}, 0 },
2573 { "cmovaS", { Gv
, Ev
}, 0 },
2575 { "cmovsS", { Gv
, Ev
}, 0 },
2576 { "cmovnsS", { Gv
, Ev
}, 0 },
2577 { "cmovpS", { Gv
, Ev
}, 0 },
2578 { "cmovnpS", { Gv
, Ev
}, 0 },
2579 { "cmovlS", { Gv
, Ev
}, 0 },
2580 { "cmovgeS", { Gv
, Ev
}, 0 },
2581 { "cmovleS", { Gv
, Ev
}, 0 },
2582 { "cmovgS", { Gv
, Ev
}, 0 },
2584 { MOD_TABLE (MOD_0F50
) },
2585 { PREFIX_TABLE (PREFIX_0F51
) },
2586 { PREFIX_TABLE (PREFIX_0F52
) },
2587 { PREFIX_TABLE (PREFIX_0F53
) },
2588 { "andpX", { XM
, EXx
}, PREFIX_OPCODE
},
2589 { "andnpX", { XM
, EXx
}, PREFIX_OPCODE
},
2590 { "orpX", { XM
, EXx
}, PREFIX_OPCODE
},
2591 { "xorpX", { XM
, EXx
}, PREFIX_OPCODE
},
2593 { PREFIX_TABLE (PREFIX_0F58
) },
2594 { PREFIX_TABLE (PREFIX_0F59
) },
2595 { PREFIX_TABLE (PREFIX_0F5A
) },
2596 { PREFIX_TABLE (PREFIX_0F5B
) },
2597 { PREFIX_TABLE (PREFIX_0F5C
) },
2598 { PREFIX_TABLE (PREFIX_0F5D
) },
2599 { PREFIX_TABLE (PREFIX_0F5E
) },
2600 { PREFIX_TABLE (PREFIX_0F5F
) },
2602 { PREFIX_TABLE (PREFIX_0F60
) },
2603 { PREFIX_TABLE (PREFIX_0F61
) },
2604 { PREFIX_TABLE (PREFIX_0F62
) },
2605 { "packsswb", { MX
, EM
}, PREFIX_OPCODE
},
2606 { "pcmpgtb", { MX
, EM
}, PREFIX_OPCODE
},
2607 { "pcmpgtw", { MX
, EM
}, PREFIX_OPCODE
},
2608 { "pcmpgtd", { MX
, EM
}, PREFIX_OPCODE
},
2609 { "packuswb", { MX
, EM
}, PREFIX_OPCODE
},
2611 { "punpckhbw", { MX
, EM
}, PREFIX_OPCODE
},
2612 { "punpckhwd", { MX
, EM
}, PREFIX_OPCODE
},
2613 { "punpckhdq", { MX
, EM
}, PREFIX_OPCODE
},
2614 { "packssdw", { MX
, EM
}, PREFIX_OPCODE
},
2615 { PREFIX_TABLE (PREFIX_0F6C
) },
2616 { PREFIX_TABLE (PREFIX_0F6D
) },
2617 { "movK", { MX
, Edq
}, PREFIX_OPCODE
},
2618 { PREFIX_TABLE (PREFIX_0F6F
) },
2620 { PREFIX_TABLE (PREFIX_0F70
) },
2621 { REG_TABLE (REG_0F71
) },
2622 { REG_TABLE (REG_0F72
) },
2623 { REG_TABLE (REG_0F73
) },
2624 { "pcmpeqb", { MX
, EM
}, PREFIX_OPCODE
},
2625 { "pcmpeqw", { MX
, EM
}, PREFIX_OPCODE
},
2626 { "pcmpeqd", { MX
, EM
}, PREFIX_OPCODE
},
2627 { "emms", { XX
}, PREFIX_OPCODE
},
2629 { PREFIX_TABLE (PREFIX_0F78
) },
2630 { PREFIX_TABLE (PREFIX_0F79
) },
2633 { PREFIX_TABLE (PREFIX_0F7C
) },
2634 { PREFIX_TABLE (PREFIX_0F7D
) },
2635 { PREFIX_TABLE (PREFIX_0F7E
) },
2636 { PREFIX_TABLE (PREFIX_0F7F
) },
2638 { "joH", { Jv
, BND
, cond_jump_flag
}, 0 },
2639 { "jnoH", { Jv
, BND
, cond_jump_flag
}, 0 },
2640 { "jbH", { Jv
, BND
, cond_jump_flag
}, 0 },
2641 { "jaeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2642 { "jeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2643 { "jneH", { Jv
, BND
, cond_jump_flag
}, 0 },
2644 { "jbeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2645 { "jaH", { Jv
, BND
, cond_jump_flag
}, 0 },
2647 { "jsH", { Jv
, BND
, cond_jump_flag
}, 0 },
2648 { "jnsH", { Jv
, BND
, cond_jump_flag
}, 0 },
2649 { "jpH", { Jv
, BND
, cond_jump_flag
}, 0 },
2650 { "jnpH", { Jv
, BND
, cond_jump_flag
}, 0 },
2651 { "jlH", { Jv
, BND
, cond_jump_flag
}, 0 },
2652 { "jgeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2653 { "jleH", { Jv
, BND
, cond_jump_flag
}, 0 },
2654 { "jgH", { Jv
, BND
, cond_jump_flag
}, 0 },
2656 { "seto", { Eb
}, 0 },
2657 { "setno", { Eb
}, 0 },
2658 { "setb", { Eb
}, 0 },
2659 { "setae", { Eb
}, 0 },
2660 { "sete", { Eb
}, 0 },
2661 { "setne", { Eb
}, 0 },
2662 { "setbe", { Eb
}, 0 },
2663 { "seta", { Eb
}, 0 },
2665 { "sets", { Eb
}, 0 },
2666 { "setns", { Eb
}, 0 },
2667 { "setp", { Eb
}, 0 },
2668 { "setnp", { Eb
}, 0 },
2669 { "setl", { Eb
}, 0 },
2670 { "setge", { Eb
}, 0 },
2671 { "setle", { Eb
}, 0 },
2672 { "setg", { Eb
}, 0 },
2674 { "pushT", { fs
}, 0 },
2675 { "popT", { fs
}, 0 },
2676 { "cpuid", { XX
}, 0 },
2677 { "btS", { Ev
, Gv
}, 0 },
2678 { "shldS", { Ev
, Gv
, Ib
}, 0 },
2679 { "shldS", { Ev
, Gv
, CL
}, 0 },
2680 { REG_TABLE (REG_0FA6
) },
2681 { REG_TABLE (REG_0FA7
) },
2683 { "pushT", { gs
}, 0 },
2684 { "popT", { gs
}, 0 },
2685 { "rsm", { XX
}, 0 },
2686 { "btsS", { Evh1
, Gv
}, 0 },
2687 { "shrdS", { Ev
, Gv
, Ib
}, 0 },
2688 { "shrdS", { Ev
, Gv
, CL
}, 0 },
2689 { REG_TABLE (REG_0FAE
) },
2690 { "imulS", { Gv
, Ev
}, 0 },
2692 { "cmpxchgB", { Ebh1
, Gb
}, 0 },
2693 { "cmpxchgS", { Evh1
, Gv
}, 0 },
2694 { MOD_TABLE (MOD_0FB2
) },
2695 { "btrS", { Evh1
, Gv
}, 0 },
2696 { MOD_TABLE (MOD_0FB4
) },
2697 { MOD_TABLE (MOD_0FB5
) },
2698 { "movz{bR|x}", { Gv
, Eb
}, 0 },
2699 { "movz{wR|x}", { Gv
, Ew
}, 0 }, /* yes, there really is movzww ! */
2701 { PREFIX_TABLE (PREFIX_0FB8
) },
2702 { "ud1S", { Gv
, Ev
}, 0 },
2703 { REG_TABLE (REG_0FBA
) },
2704 { "btcS", { Evh1
, Gv
}, 0 },
2705 { PREFIX_TABLE (PREFIX_0FBC
) },
2706 { PREFIX_TABLE (PREFIX_0FBD
) },
2707 { "movs{bR|x}", { Gv
, Eb
}, 0 },
2708 { "movs{wR|x}", { Gv
, Ew
}, 0 }, /* yes, there really is movsww ! */
2710 { "xaddB", { Ebh1
, Gb
}, 0 },
2711 { "xaddS", { Evh1
, Gv
}, 0 },
2712 { PREFIX_TABLE (PREFIX_0FC2
) },
2713 { MOD_TABLE (MOD_0FC3
) },
2714 { "pinsrw", { MX
, Edqw
, Ib
}, PREFIX_OPCODE
},
2715 { "pextrw", { Gdq
, MS
, Ib
}, PREFIX_OPCODE
},
2716 { "shufpX", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
2717 { REG_TABLE (REG_0FC7
) },
2719 { "bswap", { RMeAX
}, 0 },
2720 { "bswap", { RMeCX
}, 0 },
2721 { "bswap", { RMeDX
}, 0 },
2722 { "bswap", { RMeBX
}, 0 },
2723 { "bswap", { RMeSP
}, 0 },
2724 { "bswap", { RMeBP
}, 0 },
2725 { "bswap", { RMeSI
}, 0 },
2726 { "bswap", { RMeDI
}, 0 },
2728 { PREFIX_TABLE (PREFIX_0FD0
) },
2729 { "psrlw", { MX
, EM
}, PREFIX_OPCODE
},
2730 { "psrld", { MX
, EM
}, PREFIX_OPCODE
},
2731 { "psrlq", { MX
, EM
}, PREFIX_OPCODE
},
2732 { "paddq", { MX
, EM
}, PREFIX_OPCODE
},
2733 { "pmullw", { MX
, EM
}, PREFIX_OPCODE
},
2734 { PREFIX_TABLE (PREFIX_0FD6
) },
2735 { MOD_TABLE (MOD_0FD7
) },
2737 { "psubusb", { MX
, EM
}, PREFIX_OPCODE
},
2738 { "psubusw", { MX
, EM
}, PREFIX_OPCODE
},
2739 { "pminub", { MX
, EM
}, PREFIX_OPCODE
},
2740 { "pand", { MX
, EM
}, PREFIX_OPCODE
},
2741 { "paddusb", { MX
, EM
}, PREFIX_OPCODE
},
2742 { "paddusw", { MX
, EM
}, PREFIX_OPCODE
},
2743 { "pmaxub", { MX
, EM
}, PREFIX_OPCODE
},
2744 { "pandn", { MX
, EM
}, PREFIX_OPCODE
},
2746 { "pavgb", { MX
, EM
}, PREFIX_OPCODE
},
2747 { "psraw", { MX
, EM
}, PREFIX_OPCODE
},
2748 { "psrad", { MX
, EM
}, PREFIX_OPCODE
},
2749 { "pavgw", { MX
, EM
}, PREFIX_OPCODE
},
2750 { "pmulhuw", { MX
, EM
}, PREFIX_OPCODE
},
2751 { "pmulhw", { MX
, EM
}, PREFIX_OPCODE
},
2752 { PREFIX_TABLE (PREFIX_0FE6
) },
2753 { PREFIX_TABLE (PREFIX_0FE7
) },
2755 { "psubsb", { MX
, EM
}, PREFIX_OPCODE
},
2756 { "psubsw", { MX
, EM
}, PREFIX_OPCODE
},
2757 { "pminsw", { MX
, EM
}, PREFIX_OPCODE
},
2758 { "por", { MX
, EM
}, PREFIX_OPCODE
},
2759 { "paddsb", { MX
, EM
}, PREFIX_OPCODE
},
2760 { "paddsw", { MX
, EM
}, PREFIX_OPCODE
},
2761 { "pmaxsw", { MX
, EM
}, PREFIX_OPCODE
},
2762 { "pxor", { MX
, EM
}, PREFIX_OPCODE
},
2764 { PREFIX_TABLE (PREFIX_0FF0
) },
2765 { "psllw", { MX
, EM
}, PREFIX_OPCODE
},
2766 { "pslld", { MX
, EM
}, PREFIX_OPCODE
},
2767 { "psllq", { MX
, EM
}, PREFIX_OPCODE
},
2768 { "pmuludq", { MX
, EM
}, PREFIX_OPCODE
},
2769 { "pmaddwd", { MX
, EM
}, PREFIX_OPCODE
},
2770 { "psadbw", { MX
, EM
}, PREFIX_OPCODE
},
2771 { PREFIX_TABLE (PREFIX_0FF7
) },
2773 { "psubb", { MX
, EM
}, PREFIX_OPCODE
},
2774 { "psubw", { MX
, EM
}, PREFIX_OPCODE
},
2775 { "psubd", { MX
, EM
}, PREFIX_OPCODE
},
2776 { "psubq", { MX
, EM
}, PREFIX_OPCODE
},
2777 { "paddb", { MX
, EM
}, PREFIX_OPCODE
},
2778 { "paddw", { MX
, EM
}, PREFIX_OPCODE
},
2779 { "paddd", { MX
, EM
}, PREFIX_OPCODE
},
2780 { "ud0S", { Gv
, Ev
}, 0 },
2783 static const unsigned char onebyte_has_modrm
[256] = {
2784 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2785 /* ------------------------------- */
2786 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2787 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2788 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2789 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2790 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2791 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2792 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2793 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2794 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2795 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2796 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2797 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2798 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2799 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2800 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2801 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
2802 /* ------------------------------- */
2803 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2806 static const unsigned char twobyte_has_modrm
[256] = {
2807 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2808 /* ------------------------------- */
2809 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2810 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2811 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2812 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2813 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2814 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2815 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2816 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2817 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2818 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2819 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2820 /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */
2821 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2822 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2823 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2824 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1 /* ff */
2825 /* ------------------------------- */
2826 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2829 static char obuf
[100];
2831 static char *mnemonicendp
;
2832 static char scratchbuf
[100];
2833 static unsigned char *start_codep
;
2834 static unsigned char *insn_codep
;
2835 static unsigned char *codep
;
2836 static unsigned char *end_codep
;
2837 static int last_lock_prefix
;
2838 static int last_repz_prefix
;
2839 static int last_repnz_prefix
;
2840 static int last_data_prefix
;
2841 static int last_addr_prefix
;
2842 static int last_rex_prefix
;
2843 static int last_seg_prefix
;
2844 static int fwait_prefix
;
2845 /* The active segment register prefix. */
2846 static int active_seg_prefix
;
2847 #define MAX_CODE_LENGTH 15
2848 /* We can up to 14 prefixes since the maximum instruction length is
2850 static int all_prefixes
[MAX_CODE_LENGTH
- 1];
2851 static disassemble_info
*the_info
;
2859 static unsigned char need_modrm
;
2869 int register_specifier
;
2876 int mask_register_specifier
;
2882 static unsigned char need_vex
;
2883 static unsigned char need_vex_reg
;
2884 static unsigned char vex_w_done
;
2892 /* If we are accessing mod/rm/reg without need_modrm set, then the
2893 values are stale. Hitting this abort likely indicates that you
2894 need to update onebyte_has_modrm or twobyte_has_modrm. */
2895 #define MODRM_CHECK if (!need_modrm) abort ()
2897 static const char **names64
;
2898 static const char **names32
;
2899 static const char **names16
;
2900 static const char **names8
;
2901 static const char **names8rex
;
2902 static const char **names_seg
;
2903 static const char *index64
;
2904 static const char *index32
;
2905 static const char **index16
;
2906 static const char **names_bnd
;
2908 static const char *intel_names64
[] = {
2909 "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
2910 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
2912 static const char *intel_names32
[] = {
2913 "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
2914 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
2916 static const char *intel_names16
[] = {
2917 "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
2918 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
2920 static const char *intel_names8
[] = {
2921 "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
2923 static const char *intel_names8rex
[] = {
2924 "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
2925 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
2927 static const char *intel_names_seg
[] = {
2928 "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
2930 static const char *intel_index64
= "riz";
2931 static const char *intel_index32
= "eiz";
2932 static const char *intel_index16
[] = {
2933 "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
2936 static const char *att_names64
[] = {
2937 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
2938 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
2940 static const char *att_names32
[] = {
2941 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
2942 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
2944 static const char *att_names16
[] = {
2945 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
2946 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
2948 static const char *att_names8
[] = {
2949 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
2951 static const char *att_names8rex
[] = {
2952 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
2953 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
2955 static const char *att_names_seg
[] = {
2956 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
2958 static const char *att_index64
= "%riz";
2959 static const char *att_index32
= "%eiz";
2960 static const char *att_index16
[] = {
2961 "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
2964 static const char **names_mm
;
2965 static const char *intel_names_mm
[] = {
2966 "mm0", "mm1", "mm2", "mm3",
2967 "mm4", "mm5", "mm6", "mm7"
2969 static const char *att_names_mm
[] = {
2970 "%mm0", "%mm1", "%mm2", "%mm3",
2971 "%mm4", "%mm5", "%mm6", "%mm7"
2974 static const char *intel_names_bnd
[] = {
2975 "bnd0", "bnd1", "bnd2", "bnd3"
2978 static const char *att_names_bnd
[] = {
2979 "%bnd0", "%bnd1", "%bnd2", "%bnd3"
2982 static const char **names_xmm
;
2983 static const char *intel_names_xmm
[] = {
2984 "xmm0", "xmm1", "xmm2", "xmm3",
2985 "xmm4", "xmm5", "xmm6", "xmm7",
2986 "xmm8", "xmm9", "xmm10", "xmm11",
2987 "xmm12", "xmm13", "xmm14", "xmm15",
2988 "xmm16", "xmm17", "xmm18", "xmm19",
2989 "xmm20", "xmm21", "xmm22", "xmm23",
2990 "xmm24", "xmm25", "xmm26", "xmm27",
2991 "xmm28", "xmm29", "xmm30", "xmm31"
2993 static const char *att_names_xmm
[] = {
2994 "%xmm0", "%xmm1", "%xmm2", "%xmm3",
2995 "%xmm4", "%xmm5", "%xmm6", "%xmm7",
2996 "%xmm8", "%xmm9", "%xmm10", "%xmm11",
2997 "%xmm12", "%xmm13", "%xmm14", "%xmm15",
2998 "%xmm16", "%xmm17", "%xmm18", "%xmm19",
2999 "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3000 "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3001 "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3004 static const char **names_ymm
;
3005 static const char *intel_names_ymm
[] = {
3006 "ymm0", "ymm1", "ymm2", "ymm3",
3007 "ymm4", "ymm5", "ymm6", "ymm7",
3008 "ymm8", "ymm9", "ymm10", "ymm11",
3009 "ymm12", "ymm13", "ymm14", "ymm15",
3010 "ymm16", "ymm17", "ymm18", "ymm19",
3011 "ymm20", "ymm21", "ymm22", "ymm23",
3012 "ymm24", "ymm25", "ymm26", "ymm27",
3013 "ymm28", "ymm29", "ymm30", "ymm31"
3015 static const char *att_names_ymm
[] = {
3016 "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3017 "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3018 "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3019 "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3020 "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3021 "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3022 "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3023 "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3026 static const char **names_zmm
;
3027 static const char *intel_names_zmm
[] = {
3028 "zmm0", "zmm1", "zmm2", "zmm3",
3029 "zmm4", "zmm5", "zmm6", "zmm7",
3030 "zmm8", "zmm9", "zmm10", "zmm11",
3031 "zmm12", "zmm13", "zmm14", "zmm15",
3032 "zmm16", "zmm17", "zmm18", "zmm19",
3033 "zmm20", "zmm21", "zmm22", "zmm23",
3034 "zmm24", "zmm25", "zmm26", "zmm27",
3035 "zmm28", "zmm29", "zmm30", "zmm31"
3037 static const char *att_names_zmm
[] = {
3038 "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3039 "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3040 "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3041 "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3042 "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3043 "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3044 "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3045 "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3048 static const char **names_mask
;
3049 static const char *intel_names_mask
[] = {
3050 "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3052 static const char *att_names_mask
[] = {
3053 "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3056 static const char *names_rounding
[] =
3064 static const struct dis386 reg_table
[][8] = {
3067 { "addA", { Ebh1
, Ib
}, 0 },
3068 { "orA", { Ebh1
, Ib
}, 0 },
3069 { "adcA", { Ebh1
, Ib
}, 0 },
3070 { "sbbA", { Ebh1
, Ib
}, 0 },
3071 { "andA", { Ebh1
, Ib
}, 0 },
3072 { "subA", { Ebh1
, Ib
}, 0 },
3073 { "xorA", { Ebh1
, Ib
}, 0 },
3074 { "cmpA", { Eb
, Ib
}, 0 },
3078 { "addQ", { Evh1
, Iv
}, 0 },
3079 { "orQ", { Evh1
, Iv
}, 0 },
3080 { "adcQ", { Evh1
, Iv
}, 0 },
3081 { "sbbQ", { Evh1
, Iv
}, 0 },
3082 { "andQ", { Evh1
, Iv
}, 0 },
3083 { "subQ", { Evh1
, Iv
}, 0 },
3084 { "xorQ", { Evh1
, Iv
}, 0 },
3085 { "cmpQ", { Ev
, Iv
}, 0 },
3089 { "addQ", { Evh1
, sIb
}, 0 },
3090 { "orQ", { Evh1
, sIb
}, 0 },
3091 { "adcQ", { Evh1
, sIb
}, 0 },
3092 { "sbbQ", { Evh1
, sIb
}, 0 },
3093 { "andQ", { Evh1
, sIb
}, 0 },
3094 { "subQ", { Evh1
, sIb
}, 0 },
3095 { "xorQ", { Evh1
, sIb
}, 0 },
3096 { "cmpQ", { Ev
, sIb
}, 0 },
3100 { "popU", { stackEv
}, 0 },
3101 { XOP_8F_TABLE (XOP_09
) },
3105 { XOP_8F_TABLE (XOP_09
) },
3109 { "rolA", { Eb
, Ib
}, 0 },
3110 { "rorA", { Eb
, Ib
}, 0 },
3111 { "rclA", { Eb
, Ib
}, 0 },
3112 { "rcrA", { Eb
, Ib
}, 0 },
3113 { "shlA", { Eb
, Ib
}, 0 },
3114 { "shrA", { Eb
, Ib
}, 0 },
3115 { "shlA", { Eb
, Ib
}, 0 },
3116 { "sarA", { Eb
, Ib
}, 0 },
3120 { "rolQ", { Ev
, Ib
}, 0 },
3121 { "rorQ", { Ev
, Ib
}, 0 },
3122 { "rclQ", { Ev
, Ib
}, 0 },
3123 { "rcrQ", { Ev
, Ib
}, 0 },
3124 { "shlQ", { Ev
, Ib
}, 0 },
3125 { "shrQ", { Ev
, Ib
}, 0 },
3126 { "shlQ", { Ev
, Ib
}, 0 },
3127 { "sarQ", { Ev
, Ib
}, 0 },
3131 { "movA", { Ebh3
, Ib
}, 0 },
3138 { MOD_TABLE (MOD_C6_REG_7
) },
3142 { "movQ", { Evh3
, Iv
}, 0 },
3149 { MOD_TABLE (MOD_C7_REG_7
) },
3153 { "rolA", { Eb
, I1
}, 0 },
3154 { "rorA", { Eb
, I1
}, 0 },
3155 { "rclA", { Eb
, I1
}, 0 },
3156 { "rcrA", { Eb
, I1
}, 0 },
3157 { "shlA", { Eb
, I1
}, 0 },
3158 { "shrA", { Eb
, I1
}, 0 },
3159 { "shlA", { Eb
, I1
}, 0 },
3160 { "sarA", { Eb
, I1
}, 0 },
3164 { "rolQ", { Ev
, I1
}, 0 },
3165 { "rorQ", { Ev
, I1
}, 0 },
3166 { "rclQ", { Ev
, I1
}, 0 },
3167 { "rcrQ", { Ev
, I1
}, 0 },
3168 { "shlQ", { Ev
, I1
}, 0 },
3169 { "shrQ", { Ev
, I1
}, 0 },
3170 { "shlQ", { Ev
, I1
}, 0 },
3171 { "sarQ", { Ev
, I1
}, 0 },
3175 { "rolA", { Eb
, CL
}, 0 },
3176 { "rorA", { Eb
, CL
}, 0 },
3177 { "rclA", { Eb
, CL
}, 0 },
3178 { "rcrA", { Eb
, CL
}, 0 },
3179 { "shlA", { Eb
, CL
}, 0 },
3180 { "shrA", { Eb
, CL
}, 0 },
3181 { "shlA", { Eb
, CL
}, 0 },
3182 { "sarA", { Eb
, CL
}, 0 },
3186 { "rolQ", { Ev
, CL
}, 0 },
3187 { "rorQ", { Ev
, CL
}, 0 },
3188 { "rclQ", { Ev
, CL
}, 0 },
3189 { "rcrQ", { Ev
, CL
}, 0 },
3190 { "shlQ", { Ev
, CL
}, 0 },
3191 { "shrQ", { Ev
, CL
}, 0 },
3192 { "shlQ", { Ev
, CL
}, 0 },
3193 { "sarQ", { Ev
, CL
}, 0 },
3197 { "testA", { Eb
, Ib
}, 0 },
3198 { "testA", { Eb
, Ib
}, 0 },
3199 { "notA", { Ebh1
}, 0 },
3200 { "negA", { Ebh1
}, 0 },
3201 { "mulA", { Eb
}, 0 }, /* Don't print the implicit %al register, */
3202 { "imulA", { Eb
}, 0 }, /* to distinguish these opcodes from other */
3203 { "divA", { Eb
}, 0 }, /* mul/imul opcodes. Do the same for div */
3204 { "idivA", { Eb
}, 0 }, /* and idiv for consistency. */
3208 { "testQ", { Ev
, Iv
}, 0 },
3209 { "testQ", { Ev
, Iv
}, 0 },
3210 { "notQ", { Evh1
}, 0 },
3211 { "negQ", { Evh1
}, 0 },
3212 { "mulQ", { Ev
}, 0 }, /* Don't print the implicit register. */
3213 { "imulQ", { Ev
}, 0 },
3214 { "divQ", { Ev
}, 0 },
3215 { "idivQ", { Ev
}, 0 },
3219 { "incA", { Ebh1
}, 0 },
3220 { "decA", { Ebh1
}, 0 },
3224 { "incQ", { Evh1
}, 0 },
3225 { "decQ", { Evh1
}, 0 },
3226 { "call{&|}", { NOTRACK
, indirEv
, BND
}, 0 },
3227 { MOD_TABLE (MOD_FF_REG_3
) },
3228 { "jmp{&|}", { NOTRACK
, indirEv
, BND
}, 0 },
3229 { MOD_TABLE (MOD_FF_REG_5
) },
3230 { "pushU", { stackEv
}, 0 },
3235 { "sldtD", { Sv
}, 0 },
3236 { "strD", { Sv
}, 0 },
3237 { "lldt", { Ew
}, 0 },
3238 { "ltr", { Ew
}, 0 },
3239 { "verr", { Ew
}, 0 },
3240 { "verw", { Ew
}, 0 },
3246 { MOD_TABLE (MOD_0F01_REG_0
) },
3247 { MOD_TABLE (MOD_0F01_REG_1
) },
3248 { MOD_TABLE (MOD_0F01_REG_2
) },
3249 { MOD_TABLE (MOD_0F01_REG_3
) },
3250 { "smswD", { Sv
}, 0 },
3251 { MOD_TABLE (MOD_0F01_REG_5
) },
3252 { "lmsw", { Ew
}, 0 },
3253 { MOD_TABLE (MOD_0F01_REG_7
) },
3257 { "prefetch", { Mb
}, 0 },
3258 { "prefetchw", { Mb
}, 0 },
3259 { "prefetchwt1", { Mb
}, 0 },
3260 { "prefetch", { Mb
}, 0 },
3261 { "prefetch", { Mb
}, 0 },
3262 { "prefetch", { Mb
}, 0 },
3263 { "prefetch", { Mb
}, 0 },
3264 { "prefetch", { Mb
}, 0 },
3268 { MOD_TABLE (MOD_0F18_REG_0
) },
3269 { MOD_TABLE (MOD_0F18_REG_1
) },
3270 { MOD_TABLE (MOD_0F18_REG_2
) },
3271 { MOD_TABLE (MOD_0F18_REG_3
) },
3272 { MOD_TABLE (MOD_0F18_REG_4
) },
3273 { MOD_TABLE (MOD_0F18_REG_5
) },
3274 { MOD_TABLE (MOD_0F18_REG_6
) },
3275 { MOD_TABLE (MOD_0F18_REG_7
) },
3277 /* REG_0F1C_P_0_MOD_0 */
3279 { "cldemote", { Mb
}, 0 },
3280 { "nopQ", { Ev
}, 0 },
3281 { "nopQ", { Ev
}, 0 },
3282 { "nopQ", { Ev
}, 0 },
3283 { "nopQ", { Ev
}, 0 },
3284 { "nopQ", { Ev
}, 0 },
3285 { "nopQ", { Ev
}, 0 },
3286 { "nopQ", { Ev
}, 0 },
3288 /* REG_0F1E_P_1_MOD_3 */
3290 { "nopQ", { Ev
}, 0 },
3291 { "rdsspK", { Rdq
}, PREFIX_OPCODE
},
3292 { "nopQ", { Ev
}, 0 },
3293 { "nopQ", { Ev
}, 0 },
3294 { "nopQ", { Ev
}, 0 },
3295 { "nopQ", { Ev
}, 0 },
3296 { "nopQ", { Ev
}, 0 },
3297 { RM_TABLE (RM_0F1E_P_1_MOD_3_REG_7
) },
3303 { MOD_TABLE (MOD_0F71_REG_2
) },
3305 { MOD_TABLE (MOD_0F71_REG_4
) },
3307 { MOD_TABLE (MOD_0F71_REG_6
) },
3313 { MOD_TABLE (MOD_0F72_REG_2
) },
3315 { MOD_TABLE (MOD_0F72_REG_4
) },
3317 { MOD_TABLE (MOD_0F72_REG_6
) },
3323 { MOD_TABLE (MOD_0F73_REG_2
) },
3324 { MOD_TABLE (MOD_0F73_REG_3
) },
3327 { MOD_TABLE (MOD_0F73_REG_6
) },
3328 { MOD_TABLE (MOD_0F73_REG_7
) },
3332 { "montmul", { { OP_0f07
, 0 } }, 0 },
3333 { "xsha1", { { OP_0f07
, 0 } }, 0 },
3334 { "xsha256", { { OP_0f07
, 0 } }, 0 },
3338 { "xstore-rng", { { OP_0f07
, 0 } }, 0 },
3339 { "xcrypt-ecb", { { OP_0f07
, 0 } }, 0 },
3340 { "xcrypt-cbc", { { OP_0f07
, 0 } }, 0 },
3341 { "xcrypt-ctr", { { OP_0f07
, 0 } }, 0 },
3342 { "xcrypt-cfb", { { OP_0f07
, 0 } }, 0 },
3343 { "xcrypt-ofb", { { OP_0f07
, 0 } }, 0 },
3347 { MOD_TABLE (MOD_0FAE_REG_0
) },
3348 { MOD_TABLE (MOD_0FAE_REG_1
) },
3349 { MOD_TABLE (MOD_0FAE_REG_2
) },
3350 { MOD_TABLE (MOD_0FAE_REG_3
) },
3351 { MOD_TABLE (MOD_0FAE_REG_4
) },
3352 { MOD_TABLE (MOD_0FAE_REG_5
) },
3353 { MOD_TABLE (MOD_0FAE_REG_6
) },
3354 { MOD_TABLE (MOD_0FAE_REG_7
) },
3362 { "btQ", { Ev
, Ib
}, 0 },
3363 { "btsQ", { Evh1
, Ib
}, 0 },
3364 { "btrQ", { Evh1
, Ib
}, 0 },
3365 { "btcQ", { Evh1
, Ib
}, 0 },
3370 { "cmpxchg8b", { { CMPXCHG8B_Fixup
, q_mode
} }, 0 },
3372 { MOD_TABLE (MOD_0FC7_REG_3
) },
3373 { MOD_TABLE (MOD_0FC7_REG_4
) },
3374 { MOD_TABLE (MOD_0FC7_REG_5
) },
3375 { MOD_TABLE (MOD_0FC7_REG_6
) },
3376 { MOD_TABLE (MOD_0FC7_REG_7
) },
3382 { MOD_TABLE (MOD_VEX_0F71_REG_2
) },
3384 { MOD_TABLE (MOD_VEX_0F71_REG_4
) },
3386 { MOD_TABLE (MOD_VEX_0F71_REG_6
) },
3392 { MOD_TABLE (MOD_VEX_0F72_REG_2
) },
3394 { MOD_TABLE (MOD_VEX_0F72_REG_4
) },
3396 { MOD_TABLE (MOD_VEX_0F72_REG_6
) },
3402 { MOD_TABLE (MOD_VEX_0F73_REG_2
) },
3403 { MOD_TABLE (MOD_VEX_0F73_REG_3
) },
3406 { MOD_TABLE (MOD_VEX_0F73_REG_6
) },
3407 { MOD_TABLE (MOD_VEX_0F73_REG_7
) },
3413 { MOD_TABLE (MOD_VEX_0FAE_REG_2
) },
3414 { MOD_TABLE (MOD_VEX_0FAE_REG_3
) },
3416 /* REG_VEX_0F38F3 */
3419 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1
) },
3420 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2
) },
3421 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3
) },
3425 { "llwpcb", { { OP_LWPCB_E
, 0 } }, 0 },
3426 { "slwpcb", { { OP_LWPCB_E
, 0 } }, 0 },
3430 { "lwpins", { { OP_LWP_E
, 0 }, Ed
, Id
}, 0 },
3431 { "lwpval", { { OP_LWP_E
, 0 }, Ed
, Id
}, 0 },
3433 /* REG_XOP_TBM_01 */
3436 { "blcfill", { { OP_LWP_E
, 0 }, Edq
}, 0 },
3437 { "blsfill", { { OP_LWP_E
, 0 }, Edq
}, 0 },
3438 { "blcs", { { OP_LWP_E
, 0 }, Edq
}, 0 },
3439 { "tzmsk", { { OP_LWP_E
, 0 }, Edq
}, 0 },
3440 { "blcic", { { OP_LWP_E
, 0 }, Edq
}, 0 },
3441 { "blsic", { { OP_LWP_E
, 0 }, Edq
}, 0 },
3442 { "t1mskc", { { OP_LWP_E
, 0 }, Edq
}, 0 },
3444 /* REG_XOP_TBM_02 */
3447 { "blcmsk", { { OP_LWP_E
, 0 }, Edq
}, 0 },
3452 { "blci", { { OP_LWP_E
, 0 }, Edq
}, 0 },
3455 #include "i386-dis-evex-reg.h"
3458 static const struct dis386 prefix_table
[][4] = {
3461 { "xchgS", { { NOP_Fixup1
, eAX_reg
}, { NOP_Fixup2
, eAX_reg
} }, 0 },
3462 { "pause", { XX
}, 0 },
3463 { "xchgS", { { NOP_Fixup1
, eAX_reg
}, { NOP_Fixup2
, eAX_reg
} }, 0 },
3464 { NULL
, { { NULL
, 0 } }, PREFIX_IGNORED
}
3467 /* PREFIX_0F01_REG_3_RM_1 */
3469 { "vmmcall", { Skip_MODRM
}, 0 },
3470 { "vmgexit", { Skip_MODRM
}, 0 },
3472 { "vmgexit", { Skip_MODRM
}, 0 },
3475 /* PREFIX_0F01_REG_5_MOD_0 */
3478 { "rstorssp", { Mq
}, PREFIX_OPCODE
},
3481 /* PREFIX_0F01_REG_5_MOD_3_RM_0 */
3483 { "serialize", { Skip_MODRM
}, PREFIX_OPCODE
},
3484 { "setssbsy", { Skip_MODRM
}, PREFIX_OPCODE
},
3486 { "xsusldtrk", { Skip_MODRM
}, PREFIX_OPCODE
},
3489 /* PREFIX_0F01_REG_5_MOD_3_RM_1 */
3494 { "xresldtrk", { Skip_MODRM
}, PREFIX_OPCODE
},
3497 /* PREFIX_0F01_REG_5_MOD_3_RM_2 */
3500 { "saveprevssp", { Skip_MODRM
}, PREFIX_OPCODE
},
3503 /* PREFIX_0F01_REG_7_MOD_3_RM_2 */
3505 { "monitorx", { { OP_Monitor
, 0 } }, 0 },
3506 { "mcommit", { Skip_MODRM
}, 0 },
3509 /* PREFIX_0F01_REG_7_MOD_3_RM_3 */
3511 { "mwaitx", { { OP_Mwait
, eBX_reg
} }, 0 },
3516 { "wbinvd", { XX
}, 0 },
3517 { "wbnoinvd", { XX
}, 0 },
3522 { "movups", { XM
, EXx
}, PREFIX_OPCODE
},
3523 { "movss", { XM
, EXd
}, PREFIX_OPCODE
},
3524 { "movupd", { XM
, EXx
}, PREFIX_OPCODE
},
3525 { "movsd", { XM
, EXq
}, PREFIX_OPCODE
},
3530 { "movups", { EXxS
, XM
}, PREFIX_OPCODE
},
3531 { "movss", { EXdS
, XM
}, PREFIX_OPCODE
},
3532 { "movupd", { EXxS
, XM
}, PREFIX_OPCODE
},
3533 { "movsd", { EXqS
, XM
}, PREFIX_OPCODE
},
3538 { MOD_TABLE (MOD_0F12_PREFIX_0
) },
3539 { "movsldup", { XM
, EXx
}, PREFIX_OPCODE
},
3540 { MOD_TABLE (MOD_0F12_PREFIX_2
) },
3541 { "movddup", { XM
, EXq
}, PREFIX_OPCODE
},
3546 { MOD_TABLE (MOD_0F16_PREFIX_0
) },
3547 { "movshdup", { XM
, EXx
}, PREFIX_OPCODE
},
3548 { MOD_TABLE (MOD_0F16_PREFIX_2
) },
3553 { MOD_TABLE (MOD_0F1A_PREFIX_0
) },
3554 { "bndcl", { Gbnd
, Ev_bnd
}, 0 },
3555 { "bndmov", { Gbnd
, Ebnd
}, 0 },
3556 { "bndcu", { Gbnd
, Ev_bnd
}, 0 },
3561 { MOD_TABLE (MOD_0F1B_PREFIX_0
) },
3562 { MOD_TABLE (MOD_0F1B_PREFIX_1
) },
3563 { "bndmov", { EbndS
, Gbnd
}, 0 },
3564 { "bndcn", { Gbnd
, Ev_bnd
}, 0 },
3569 { MOD_TABLE (MOD_0F1C_PREFIX_0
) },
3570 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3571 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3572 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3577 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3578 { MOD_TABLE (MOD_0F1E_PREFIX_1
) },
3579 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3580 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3585 { "cvtpi2ps", { XM
, EMCq
}, PREFIX_OPCODE
},
3586 { "cvtsi2ss%LQ", { XM
, Edq
}, PREFIX_OPCODE
},
3587 { "cvtpi2pd", { XM
, EMCq
}, PREFIX_OPCODE
},
3588 { "cvtsi2sd%LQ", { XM
, Edq
}, 0 },
3593 { MOD_TABLE (MOD_0F2B_PREFIX_0
) },
3594 { MOD_TABLE (MOD_0F2B_PREFIX_1
) },
3595 { MOD_TABLE (MOD_0F2B_PREFIX_2
) },
3596 { MOD_TABLE (MOD_0F2B_PREFIX_3
) },
3601 { "cvttps2pi", { MXC
, EXq
}, PREFIX_OPCODE
},
3602 { "cvttss2si", { Gdq
, EXd
}, PREFIX_OPCODE
},
3603 { "cvttpd2pi", { MXC
, EXx
}, PREFIX_OPCODE
},
3604 { "cvttsd2si", { Gdq
, EXq
}, PREFIX_OPCODE
},
3609 { "cvtps2pi", { MXC
, EXq
}, PREFIX_OPCODE
},
3610 { "cvtss2si", { Gdq
, EXd
}, PREFIX_OPCODE
},
3611 { "cvtpd2pi", { MXC
, EXx
}, PREFIX_OPCODE
},
3612 { "cvtsd2si", { Gdq
, EXq
}, PREFIX_OPCODE
},
3617 { "ucomiss",{ XM
, EXd
}, 0 },
3619 { "ucomisd",{ XM
, EXq
}, 0 },
3624 { "comiss", { XM
, EXd
}, 0 },
3626 { "comisd", { XM
, EXq
}, 0 },
3631 { "sqrtps", { XM
, EXx
}, PREFIX_OPCODE
},
3632 { "sqrtss", { XM
, EXd
}, PREFIX_OPCODE
},
3633 { "sqrtpd", { XM
, EXx
}, PREFIX_OPCODE
},
3634 { "sqrtsd", { XM
, EXq
}, PREFIX_OPCODE
},
3639 { "rsqrtps",{ XM
, EXx
}, PREFIX_OPCODE
},
3640 { "rsqrtss",{ XM
, EXd
}, PREFIX_OPCODE
},
3645 { "rcpps", { XM
, EXx
}, PREFIX_OPCODE
},
3646 { "rcpss", { XM
, EXd
}, PREFIX_OPCODE
},
3651 { "addps", { XM
, EXx
}, PREFIX_OPCODE
},
3652 { "addss", { XM
, EXd
}, PREFIX_OPCODE
},
3653 { "addpd", { XM
, EXx
}, PREFIX_OPCODE
},
3654 { "addsd", { XM
, EXq
}, PREFIX_OPCODE
},
3659 { "mulps", { XM
, EXx
}, PREFIX_OPCODE
},
3660 { "mulss", { XM
, EXd
}, PREFIX_OPCODE
},
3661 { "mulpd", { XM
, EXx
}, PREFIX_OPCODE
},
3662 { "mulsd", { XM
, EXq
}, PREFIX_OPCODE
},
3667 { "cvtps2pd", { XM
, EXq
}, PREFIX_OPCODE
},
3668 { "cvtss2sd", { XM
, EXd
}, PREFIX_OPCODE
},
3669 { "cvtpd2ps", { XM
, EXx
}, PREFIX_OPCODE
},
3670 { "cvtsd2ss", { XM
, EXq
}, PREFIX_OPCODE
},
3675 { "cvtdq2ps", { XM
, EXx
}, PREFIX_OPCODE
},
3676 { "cvttps2dq", { XM
, EXx
}, PREFIX_OPCODE
},
3677 { "cvtps2dq", { XM
, EXx
}, PREFIX_OPCODE
},
3682 { "subps", { XM
, EXx
}, PREFIX_OPCODE
},
3683 { "subss", { XM
, EXd
}, PREFIX_OPCODE
},
3684 { "subpd", { XM
, EXx
}, PREFIX_OPCODE
},
3685 { "subsd", { XM
, EXq
}, PREFIX_OPCODE
},
3690 { "minps", { XM
, EXx
}, PREFIX_OPCODE
},
3691 { "minss", { XM
, EXd
}, PREFIX_OPCODE
},
3692 { "minpd", { XM
, EXx
}, PREFIX_OPCODE
},
3693 { "minsd", { XM
, EXq
}, PREFIX_OPCODE
},
3698 { "divps", { XM
, EXx
}, PREFIX_OPCODE
},
3699 { "divss", { XM
, EXd
}, PREFIX_OPCODE
},
3700 { "divpd", { XM
, EXx
}, PREFIX_OPCODE
},
3701 { "divsd", { XM
, EXq
}, PREFIX_OPCODE
},
3706 { "maxps", { XM
, EXx
}, PREFIX_OPCODE
},
3707 { "maxss", { XM
, EXd
}, PREFIX_OPCODE
},
3708 { "maxpd", { XM
, EXx
}, PREFIX_OPCODE
},
3709 { "maxsd", { XM
, EXq
}, PREFIX_OPCODE
},
3714 { "punpcklbw",{ MX
, EMd
}, PREFIX_OPCODE
},
3716 { "punpcklbw",{ MX
, EMx
}, PREFIX_OPCODE
},
3721 { "punpcklwd",{ MX
, EMd
}, PREFIX_OPCODE
},
3723 { "punpcklwd",{ MX
, EMx
}, PREFIX_OPCODE
},
3728 { "punpckldq",{ MX
, EMd
}, PREFIX_OPCODE
},
3730 { "punpckldq",{ MX
, EMx
}, PREFIX_OPCODE
},
3737 { "punpcklqdq", { XM
, EXx
}, PREFIX_OPCODE
},
3744 { "punpckhqdq", { XM
, EXx
}, PREFIX_OPCODE
},
3749 { "movq", { MX
, EM
}, PREFIX_OPCODE
},
3750 { "movdqu", { XM
, EXx
}, PREFIX_OPCODE
},
3751 { "movdqa", { XM
, EXx
}, PREFIX_OPCODE
},
3756 { "pshufw", { MX
, EM
, Ib
}, PREFIX_OPCODE
},
3757 { "pshufhw",{ XM
, EXx
, Ib
}, PREFIX_OPCODE
},
3758 { "pshufd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
3759 { "pshuflw",{ XM
, EXx
, Ib
}, PREFIX_OPCODE
},
3762 /* PREFIX_0F73_REG_3 */
3766 { "psrldq", { XS
, Ib
}, 0 },
3769 /* PREFIX_0F73_REG_7 */
3773 { "pslldq", { XS
, Ib
}, 0 },
3778 {"vmread", { Em
, Gm
}, 0 },
3780 {"extrq", { XS
, Ib
, Ib
}, 0 },
3781 {"insertq", { XM
, XS
, Ib
, Ib
}, 0 },
3786 {"vmwrite", { Gm
, Em
}, 0 },
3788 {"extrq", { XM
, XS
}, 0 },
3789 {"insertq", { XM
, XS
}, 0 },
3796 { "haddpd", { XM
, EXx
}, PREFIX_OPCODE
},
3797 { "haddps", { XM
, EXx
}, PREFIX_OPCODE
},
3804 { "hsubpd", { XM
, EXx
}, PREFIX_OPCODE
},
3805 { "hsubps", { XM
, EXx
}, PREFIX_OPCODE
},
3810 { "movK", { Edq
, MX
}, PREFIX_OPCODE
},
3811 { "movq", { XM
, EXq
}, PREFIX_OPCODE
},
3812 { "movK", { Edq
, XM
}, PREFIX_OPCODE
},
3817 { "movq", { EMS
, MX
}, PREFIX_OPCODE
},
3818 { "movdqu", { EXxS
, XM
}, PREFIX_OPCODE
},
3819 { "movdqa", { EXxS
, XM
}, PREFIX_OPCODE
},
3822 /* PREFIX_0FAE_REG_0_MOD_3 */
3825 { "rdfsbase", { Ev
}, 0 },
3828 /* PREFIX_0FAE_REG_1_MOD_3 */
3831 { "rdgsbase", { Ev
}, 0 },
3834 /* PREFIX_0FAE_REG_2_MOD_3 */
3837 { "wrfsbase", { Ev
}, 0 },
3840 /* PREFIX_0FAE_REG_3_MOD_3 */
3843 { "wrgsbase", { Ev
}, 0 },
3846 /* PREFIX_0FAE_REG_4_MOD_0 */
3848 { "xsave", { FXSAVE
}, 0 },
3849 { "ptwrite%LQ", { Edq
}, 0 },
3852 /* PREFIX_0FAE_REG_4_MOD_3 */
3855 { "ptwrite%LQ", { Edq
}, 0 },
3858 /* PREFIX_0FAE_REG_5_MOD_0 */
3860 { "xrstor", { FXSAVE
}, PREFIX_OPCODE
},
3863 /* PREFIX_0FAE_REG_5_MOD_3 */
3865 { "lfence", { Skip_MODRM
}, 0 },
3866 { "incsspK", { Rdq
}, PREFIX_OPCODE
},
3869 /* PREFIX_0FAE_REG_6_MOD_0 */
3871 { "xsaveopt", { FXSAVE
}, PREFIX_OPCODE
},
3872 { "clrssbsy", { Mq
}, PREFIX_OPCODE
},
3873 { "clwb", { Mb
}, PREFIX_OPCODE
},
3876 /* PREFIX_0FAE_REG_6_MOD_3 */
3878 { RM_TABLE (RM_0FAE_REG_6_MOD_3_P_0
) },
3879 { "umonitor", { Eva
}, PREFIX_OPCODE
},
3880 { "tpause", { Edq
}, PREFIX_OPCODE
},
3881 { "umwait", { Edq
}, PREFIX_OPCODE
},
3884 /* PREFIX_0FAE_REG_7_MOD_0 */
3886 { "clflush", { Mb
}, 0 },
3888 { "clflushopt", { Mb
}, 0 },
3894 { "popcntS", { Gv
, Ev
}, 0 },
3899 { "bsfS", { Gv
, Ev
}, 0 },
3900 { "tzcntS", { Gv
, Ev
}, 0 },
3901 { "bsfS", { Gv
, Ev
}, 0 },
3906 { "bsrS", { Gv
, Ev
}, 0 },
3907 { "lzcntS", { Gv
, Ev
}, 0 },
3908 { "bsrS", { Gv
, Ev
}, 0 },
3913 { "cmpps", { XM
, EXx
, CMP
}, PREFIX_OPCODE
},
3914 { "cmpss", { XM
, EXd
, CMP
}, PREFIX_OPCODE
},
3915 { "cmppd", { XM
, EXx
, CMP
}, PREFIX_OPCODE
},
3916 { "cmpsd", { XM
, EXq
, CMP
}, PREFIX_OPCODE
},
3919 /* PREFIX_0FC3_MOD_0 */
3921 { "movntiS", { Edq
, Gdq
}, PREFIX_OPCODE
},
3924 /* PREFIX_0FC7_REG_6_MOD_0 */
3926 { "vmptrld",{ Mq
}, 0 },
3927 { "vmxon", { Mq
}, 0 },
3928 { "vmclear",{ Mq
}, 0 },
3931 /* PREFIX_0FC7_REG_6_MOD_3 */
3933 { "rdrand", { Ev
}, 0 },
3935 { "rdrand", { Ev
}, 0 }
3938 /* PREFIX_0FC7_REG_7_MOD_3 */
3940 { "rdseed", { Ev
}, 0 },
3941 { "rdpid", { Em
}, 0 },
3942 { "rdseed", { Ev
}, 0 },
3949 { "addsubpd", { XM
, EXx
}, 0 },
3950 { "addsubps", { XM
, EXx
}, 0 },
3956 { "movq2dq",{ XM
, MS
}, 0 },
3957 { "movq", { EXqS
, XM
}, 0 },
3958 { "movdq2q",{ MX
, XS
}, 0 },
3964 { "cvtdq2pd", { XM
, EXq
}, PREFIX_OPCODE
},
3965 { "cvttpd2dq", { XM
, EXx
}, PREFIX_OPCODE
},
3966 { "cvtpd2dq", { XM
, EXx
}, PREFIX_OPCODE
},
3971 { "movntq", { Mq
, MX
}, PREFIX_OPCODE
},
3973 { MOD_TABLE (MOD_0FE7_PREFIX_2
) },
3981 { MOD_TABLE (MOD_0FF0_PREFIX_3
) },
3986 { "maskmovq", { MX
, MS
}, PREFIX_OPCODE
},
3988 { "maskmovdqu", { XM
, XS
}, PREFIX_OPCODE
},
3995 { "pblendvb", { XM
, EXx
, XMM0
}, PREFIX_OPCODE
},
4002 { "blendvps", { XM
, EXx
, XMM0
}, PREFIX_OPCODE
},
4009 { "blendvpd", { XM
, EXx
, XMM0
}, PREFIX_OPCODE
},
4016 { "ptest", { XM
, EXx
}, PREFIX_OPCODE
},
4023 { "pmovsxbw", { XM
, EXq
}, PREFIX_OPCODE
},
4030 { "pmovsxbd", { XM
, EXd
}, PREFIX_OPCODE
},
4037 { "pmovsxbq", { XM
, EXw
}, PREFIX_OPCODE
},
4044 { "pmovsxwd", { XM
, EXq
}, PREFIX_OPCODE
},
4051 { "pmovsxwq", { XM
, EXd
}, PREFIX_OPCODE
},
4058 { "pmovsxdq", { XM
, EXq
}, PREFIX_OPCODE
},
4065 { "pmuldq", { XM
, EXx
}, PREFIX_OPCODE
},
4072 { "pcmpeqq", { XM
, EXx
}, PREFIX_OPCODE
},
4079 { MOD_TABLE (MOD_0F382A_PREFIX_2
) },
4086 { "packusdw", { XM
, EXx
}, PREFIX_OPCODE
},
4093 { "pmovzxbw", { XM
, EXq
}, PREFIX_OPCODE
},
4100 { "pmovzxbd", { XM
, EXd
}, PREFIX_OPCODE
},
4107 { "pmovzxbq", { XM
, EXw
}, PREFIX_OPCODE
},
4114 { "pmovzxwd", { XM
, EXq
}, PREFIX_OPCODE
},
4121 { "pmovzxwq", { XM
, EXd
}, PREFIX_OPCODE
},
4128 { "pmovzxdq", { XM
, EXq
}, PREFIX_OPCODE
},
4135 { "pcmpgtq", { XM
, EXx
}, PREFIX_OPCODE
},
4142 { "pminsb", { XM
, EXx
}, PREFIX_OPCODE
},
4149 { "pminsd", { XM
, EXx
}, PREFIX_OPCODE
},
4156 { "pminuw", { XM
, EXx
}, PREFIX_OPCODE
},
4163 { "pminud", { XM
, EXx
}, PREFIX_OPCODE
},
4170 { "pmaxsb", { XM
, EXx
}, PREFIX_OPCODE
},
4177 { "pmaxsd", { XM
, EXx
}, PREFIX_OPCODE
},
4184 { "pmaxuw", { XM
, EXx
}, PREFIX_OPCODE
},
4191 { "pmaxud", { XM
, EXx
}, PREFIX_OPCODE
},
4198 { "pmulld", { XM
, EXx
}, PREFIX_OPCODE
},
4205 { "phminposuw", { XM
, EXx
}, PREFIX_OPCODE
},
4212 { "invept", { Gm
, Mo
}, PREFIX_OPCODE
},
4219 { "invvpid", { Gm
, Mo
}, PREFIX_OPCODE
},
4226 { "invpcid", { Gm
, M
}, PREFIX_OPCODE
},
4231 { "sha1nexte", { XM
, EXxmm
}, PREFIX_OPCODE
},
4236 { "sha1msg1", { XM
, EXxmm
}, PREFIX_OPCODE
},
4241 { "sha1msg2", { XM
, EXxmm
}, PREFIX_OPCODE
},
4246 { "sha256rnds2", { XM
, EXxmm
, XMM0
}, PREFIX_OPCODE
},
4251 { "sha256msg1", { XM
, EXxmm
}, PREFIX_OPCODE
},
4256 { "sha256msg2", { XM
, EXxmm
}, PREFIX_OPCODE
},
4263 { "gf2p8mulb", { XM
, EXxmm
}, PREFIX_OPCODE
},
4270 { "aesimc", { XM
, EXx
}, PREFIX_OPCODE
},
4277 { "aesenc", { XM
, EXx
}, PREFIX_OPCODE
},
4284 { "aesenclast", { XM
, EXx
}, PREFIX_OPCODE
},
4291 { "aesdec", { XM
, EXx
}, PREFIX_OPCODE
},
4298 { "aesdeclast", { XM
, EXx
}, PREFIX_OPCODE
},
4303 { "movbeS", { Gv
, { MOVBE_Fixup
, v_mode
} }, PREFIX_OPCODE
},
4305 { "movbeS", { Gv
, { MOVBE_Fixup
, v_mode
} }, PREFIX_OPCODE
},
4306 { "crc32", { Gdq
, { CRC32_Fixup
, b_mode
} }, PREFIX_OPCODE
},
4311 { "movbeS", { { MOVBE_Fixup
, v_mode
}, Gv
}, PREFIX_OPCODE
},
4313 { "movbeS", { { MOVBE_Fixup
, v_mode
}, Gv
}, PREFIX_OPCODE
},
4314 { "crc32", { Gdq
, { CRC32_Fixup
, v_mode
} }, PREFIX_OPCODE
},
4321 { MOD_TABLE (MOD_0F38F5_PREFIX_2
) },
4326 { MOD_TABLE (MOD_0F38F6_PREFIX_0
) },
4327 { "adoxS", { Gdq
, Edq
}, PREFIX_OPCODE
},
4328 { "adcxS", { Gdq
, Edq
}, PREFIX_OPCODE
},
4335 { MOD_TABLE (MOD_0F38F8_PREFIX_1
) },
4336 { MOD_TABLE (MOD_0F38F8_PREFIX_2
) },
4337 { MOD_TABLE (MOD_0F38F8_PREFIX_3
) },
4342 { MOD_TABLE (MOD_0F38F9_PREFIX_0
) },
4349 { "roundps", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4356 { "roundpd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4363 { "roundss", { XM
, EXd
, Ib
}, PREFIX_OPCODE
},
4370 { "roundsd", { XM
, EXq
, Ib
}, PREFIX_OPCODE
},
4377 { "blendps", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4384 { "blendpd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4391 { "pblendw", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4398 { "pextrb", { Edqb
, XM
, Ib
}, PREFIX_OPCODE
},
4405 { "pextrw", { Edqw
, XM
, Ib
}, PREFIX_OPCODE
},
4412 { "pextrK", { Edq
, XM
, Ib
}, PREFIX_OPCODE
},
4419 { "extractps", { Edqd
, XM
, Ib
}, PREFIX_OPCODE
},
4426 { "pinsrb", { XM
, Edqb
, Ib
}, PREFIX_OPCODE
},
4433 { "insertps", { XM
, EXd
, Ib
}, PREFIX_OPCODE
},
4440 { "pinsrK", { XM
, Edq
, Ib
}, PREFIX_OPCODE
},
4447 { "dpps", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4454 { "dppd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4461 { "mpsadbw", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4468 { "pclmulqdq", { XM
, EXx
, PCLMUL
}, PREFIX_OPCODE
},
4475 { "pcmpestrm", { XM
, { PCMPESTR_Fixup
, x_mode
}, Ib
}, PREFIX_OPCODE
},
4482 { "pcmpestri", { XM
, { PCMPESTR_Fixup
, x_mode
}, Ib
}, PREFIX_OPCODE
},
4489 { "pcmpistrm", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4496 { "pcmpistri", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4501 { "sha1rnds4", { XM
, EXxmm
, Ib
}, PREFIX_OPCODE
},
4508 { "gf2p8affineqb", { XM
, EXxmm
, Ib
}, PREFIX_OPCODE
},
4515 { "gf2p8affineinvqb", { XM
, EXxmm
, Ib
}, PREFIX_OPCODE
},
4522 { "aeskeygenassist", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4525 /* PREFIX_VEX_0F10 */
4527 { "vmovups", { XM
, EXx
}, 0 },
4528 { "vmovss", { XMVexScalar
, VexScalar
, EXxmm_md
}, 0 },
4529 { "vmovupd", { XM
, EXx
}, 0 },
4530 { "vmovsd", { XMVexScalar
, VexScalar
, EXxmm_mq
}, 0 },
4533 /* PREFIX_VEX_0F11 */
4535 { "vmovups", { EXxS
, XM
}, 0 },
4536 { "vmovss", { EXdVexScalarS
, VexScalar
, XMScalar
}, 0 },
4537 { "vmovupd", { EXxS
, XM
}, 0 },
4538 { "vmovsd", { EXqVexScalarS
, VexScalar
, XMScalar
}, 0 },
4541 /* PREFIX_VEX_0F12 */
4543 { MOD_TABLE (MOD_VEX_0F12_PREFIX_0
) },
4544 { "vmovsldup", { XM
, EXx
}, 0 },
4545 { MOD_TABLE (MOD_VEX_0F12_PREFIX_2
) },
4546 { "vmovddup", { XM
, EXymmq
}, 0 },
4549 /* PREFIX_VEX_0F16 */
4551 { MOD_TABLE (MOD_VEX_0F16_PREFIX_0
) },
4552 { "vmovshdup", { XM
, EXx
}, 0 },
4553 { MOD_TABLE (MOD_VEX_0F16_PREFIX_2
) },
4556 /* PREFIX_VEX_0F2A */
4559 { "vcvtsi2ss%LQ", { XMScalar
, VexScalar
, Edq
}, 0 },
4561 { "vcvtsi2sd%LQ", { XMScalar
, VexScalar
, Edq
}, 0 },
4564 /* PREFIX_VEX_0F2C */
4567 { "vcvttss2si", { Gdq
, EXxmm_md
}, 0 },
4569 { "vcvttsd2si", { Gdq
, EXxmm_mq
}, 0 },
4572 /* PREFIX_VEX_0F2D */
4575 { "vcvtss2si", { Gdq
, EXxmm_md
}, 0 },
4577 { "vcvtsd2si", { Gdq
, EXxmm_mq
}, 0 },
4580 /* PREFIX_VEX_0F2E */
4582 { "vucomiss", { XMScalar
, EXxmm_md
}, 0 },
4584 { "vucomisd", { XMScalar
, EXxmm_mq
}, 0 },
4587 /* PREFIX_VEX_0F2F */
4589 { "vcomiss", { XMScalar
, EXxmm_md
}, 0 },
4591 { "vcomisd", { XMScalar
, EXxmm_mq
}, 0 },
4594 /* PREFIX_VEX_0F41 */
4596 { VEX_LEN_TABLE (VEX_LEN_0F41_P_0
) },
4598 { VEX_LEN_TABLE (VEX_LEN_0F41_P_2
) },
4601 /* PREFIX_VEX_0F42 */
4603 { VEX_LEN_TABLE (VEX_LEN_0F42_P_0
) },
4605 { VEX_LEN_TABLE (VEX_LEN_0F42_P_2
) },
4608 /* PREFIX_VEX_0F44 */
4610 { VEX_LEN_TABLE (VEX_LEN_0F44_P_0
) },
4612 { VEX_LEN_TABLE (VEX_LEN_0F44_P_2
) },
4615 /* PREFIX_VEX_0F45 */
4617 { VEX_LEN_TABLE (VEX_LEN_0F45_P_0
) },
4619 { VEX_LEN_TABLE (VEX_LEN_0F45_P_2
) },
4622 /* PREFIX_VEX_0F46 */
4624 { VEX_LEN_TABLE (VEX_LEN_0F46_P_0
) },
4626 { VEX_LEN_TABLE (VEX_LEN_0F46_P_2
) },
4629 /* PREFIX_VEX_0F47 */
4631 { VEX_LEN_TABLE (VEX_LEN_0F47_P_0
) },
4633 { VEX_LEN_TABLE (VEX_LEN_0F47_P_2
) },
4636 /* PREFIX_VEX_0F4A */
4638 { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0
) },
4640 { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2
) },
4643 /* PREFIX_VEX_0F4B */
4645 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0
) },
4647 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2
) },
4650 /* PREFIX_VEX_0F51 */
4652 { "vsqrtps", { XM
, EXx
}, 0 },
4653 { "vsqrtss", { XMScalar
, VexScalar
, EXxmm_md
}, 0 },
4654 { "vsqrtpd", { XM
, EXx
}, 0 },
4655 { "vsqrtsd", { XMScalar
, VexScalar
, EXxmm_mq
}, 0 },
4658 /* PREFIX_VEX_0F52 */
4660 { "vrsqrtps", { XM
, EXx
}, 0 },
4661 { "vrsqrtss", { XMScalar
, VexScalar
, EXxmm_md
}, 0 },
4664 /* PREFIX_VEX_0F53 */
4666 { "vrcpps", { XM
, EXx
}, 0 },
4667 { "vrcpss", { XMScalar
, VexScalar
, EXxmm_md
}, 0 },
4670 /* PREFIX_VEX_0F58 */
4672 { "vaddps", { XM
, Vex
, EXx
}, 0 },
4673 { "vaddss", { XMScalar
, VexScalar
, EXxmm_md
}, 0 },
4674 { "vaddpd", { XM
, Vex
, EXx
}, 0 },
4675 { "vaddsd", { XMScalar
, VexScalar
, EXxmm_mq
}, 0 },
4678 /* PREFIX_VEX_0F59 */
4680 { "vmulps", { XM
, Vex
, EXx
}, 0 },
4681 { "vmulss", { XMScalar
, VexScalar
, EXxmm_md
}, 0 },
4682 { "vmulpd", { XM
, Vex
, EXx
}, 0 },
4683 { "vmulsd", { XMScalar
, VexScalar
, EXxmm_mq
}, 0 },
4686 /* PREFIX_VEX_0F5A */
4688 { "vcvtps2pd", { XM
, EXxmmq
}, 0 },
4689 { "vcvtss2sd", { XMScalar
, VexScalar
, EXxmm_md
}, 0 },
4690 { "vcvtpd2ps%XY",{ XMM
, EXx
}, 0 },
4691 { "vcvtsd2ss", { XMScalar
, VexScalar
, EXxmm_mq
}, 0 },
4694 /* PREFIX_VEX_0F5B */
4696 { "vcvtdq2ps", { XM
, EXx
}, 0 },
4697 { "vcvttps2dq", { XM
, EXx
}, 0 },
4698 { "vcvtps2dq", { XM
, EXx
}, 0 },
4701 /* PREFIX_VEX_0F5C */
4703 { "vsubps", { XM
, Vex
, EXx
}, 0 },
4704 { "vsubss", { XMScalar
, VexScalar
, EXxmm_md
}, 0 },
4705 { "vsubpd", { XM
, Vex
, EXx
}, 0 },
4706 { "vsubsd", { XMScalar
, VexScalar
, EXxmm_mq
}, 0 },
4709 /* PREFIX_VEX_0F5D */
4711 { "vminps", { XM
, Vex
, EXx
}, 0 },
4712 { "vminss", { XMScalar
, VexScalar
, EXxmm_md
}, 0 },
4713 { "vminpd", { XM
, Vex
, EXx
}, 0 },
4714 { "vminsd", { XMScalar
, VexScalar
, EXxmm_mq
}, 0 },
4717 /* PREFIX_VEX_0F5E */
4719 { "vdivps", { XM
, Vex
, EXx
}, 0 },
4720 { "vdivss", { XMScalar
, VexScalar
, EXxmm_md
}, 0 },
4721 { "vdivpd", { XM
, Vex
, EXx
}, 0 },
4722 { "vdivsd", { XMScalar
, VexScalar
, EXxmm_mq
}, 0 },
4725 /* PREFIX_VEX_0F5F */
4727 { "vmaxps", { XM
, Vex
, EXx
}, 0 },
4728 { "vmaxss", { XMScalar
, VexScalar
, EXxmm_md
}, 0 },
4729 { "vmaxpd", { XM
, Vex
, EXx
}, 0 },
4730 { "vmaxsd", { XMScalar
, VexScalar
, EXxmm_mq
}, 0 },
4733 /* PREFIX_VEX_0F60 */
4737 { "vpunpcklbw", { XM
, Vex
, EXx
}, 0 },
4740 /* PREFIX_VEX_0F61 */
4744 { "vpunpcklwd", { XM
, Vex
, EXx
}, 0 },
4747 /* PREFIX_VEX_0F62 */
4751 { "vpunpckldq", { XM
, Vex
, EXx
}, 0 },
4754 /* PREFIX_VEX_0F63 */
4758 { "vpacksswb", { XM
, Vex
, EXx
}, 0 },
4761 /* PREFIX_VEX_0F64 */
4765 { "vpcmpgtb", { XM
, Vex
, EXx
}, 0 },
4768 /* PREFIX_VEX_0F65 */
4772 { "vpcmpgtw", { XM
, Vex
, EXx
}, 0 },
4775 /* PREFIX_VEX_0F66 */
4779 { "vpcmpgtd", { XM
, Vex
, EXx
}, 0 },
4782 /* PREFIX_VEX_0F67 */
4786 { "vpackuswb", { XM
, Vex
, EXx
}, 0 },
4789 /* PREFIX_VEX_0F68 */
4793 { "vpunpckhbw", { XM
, Vex
, EXx
}, 0 },
4796 /* PREFIX_VEX_0F69 */
4800 { "vpunpckhwd", { XM
, Vex
, EXx
}, 0 },
4803 /* PREFIX_VEX_0F6A */
4807 { "vpunpckhdq", { XM
, Vex
, EXx
}, 0 },
4810 /* PREFIX_VEX_0F6B */
4814 { "vpackssdw", { XM
, Vex
, EXx
}, 0 },
4817 /* PREFIX_VEX_0F6C */
4821 { "vpunpcklqdq", { XM
, Vex
, EXx
}, 0 },
4824 /* PREFIX_VEX_0F6D */
4828 { "vpunpckhqdq", { XM
, Vex
, EXx
}, 0 },
4831 /* PREFIX_VEX_0F6E */
4835 { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2
) },
4838 /* PREFIX_VEX_0F6F */
4841 { "vmovdqu", { XM
, EXx
}, 0 },
4842 { "vmovdqa", { XM
, EXx
}, 0 },
4845 /* PREFIX_VEX_0F70 */
4848 { "vpshufhw", { XM
, EXx
, Ib
}, 0 },
4849 { "vpshufd", { XM
, EXx
, Ib
}, 0 },
4850 { "vpshuflw", { XM
, EXx
, Ib
}, 0 },
4853 /* PREFIX_VEX_0F71_REG_2 */
4857 { "vpsrlw", { Vex
, XS
, Ib
}, 0 },
4860 /* PREFIX_VEX_0F71_REG_4 */
4864 { "vpsraw", { Vex
, XS
, Ib
}, 0 },
4867 /* PREFIX_VEX_0F71_REG_6 */
4871 { "vpsllw", { Vex
, XS
, Ib
}, 0 },
4874 /* PREFIX_VEX_0F72_REG_2 */
4878 { "vpsrld", { Vex
, XS
, Ib
}, 0 },
4881 /* PREFIX_VEX_0F72_REG_4 */
4885 { "vpsrad", { Vex
, XS
, Ib
}, 0 },
4888 /* PREFIX_VEX_0F72_REG_6 */
4892 { "vpslld", { Vex
, XS
, Ib
}, 0 },
4895 /* PREFIX_VEX_0F73_REG_2 */
4899 { "vpsrlq", { Vex
, XS
, Ib
}, 0 },
4902 /* PREFIX_VEX_0F73_REG_3 */
4906 { "vpsrldq", { Vex
, XS
, Ib
}, 0 },
4909 /* PREFIX_VEX_0F73_REG_6 */
4913 { "vpsllq", { Vex
, XS
, Ib
}, 0 },
4916 /* PREFIX_VEX_0F73_REG_7 */
4920 { "vpslldq", { Vex
, XS
, Ib
}, 0 },
4923 /* PREFIX_VEX_0F74 */
4927 { "vpcmpeqb", { XM
, Vex
, EXx
}, 0 },
4930 /* PREFIX_VEX_0F75 */
4934 { "vpcmpeqw", { XM
, Vex
, EXx
}, 0 },
4937 /* PREFIX_VEX_0F76 */
4941 { "vpcmpeqd", { XM
, Vex
, EXx
}, 0 },
4944 /* PREFIX_VEX_0F77 */
4946 { VEX_LEN_TABLE (VEX_LEN_0F77_P_0
) },
4949 /* PREFIX_VEX_0F7C */
4953 { "vhaddpd", { XM
, Vex
, EXx
}, 0 },
4954 { "vhaddps", { XM
, Vex
, EXx
}, 0 },
4957 /* PREFIX_VEX_0F7D */
4961 { "vhsubpd", { XM
, Vex
, EXx
}, 0 },
4962 { "vhsubps", { XM
, Vex
, EXx
}, 0 },
4965 /* PREFIX_VEX_0F7E */
4968 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1
) },
4969 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2
) },
4972 /* PREFIX_VEX_0F7F */
4975 { "vmovdqu", { EXxS
, XM
}, 0 },
4976 { "vmovdqa", { EXxS
, XM
}, 0 },
4979 /* PREFIX_VEX_0F90 */
4981 { VEX_LEN_TABLE (VEX_LEN_0F90_P_0
) },
4983 { VEX_LEN_TABLE (VEX_LEN_0F90_P_2
) },
4986 /* PREFIX_VEX_0F91 */
4988 { VEX_LEN_TABLE (VEX_LEN_0F91_P_0
) },
4990 { VEX_LEN_TABLE (VEX_LEN_0F91_P_2
) },
4993 /* PREFIX_VEX_0F92 */
4995 { VEX_LEN_TABLE (VEX_LEN_0F92_P_0
) },
4997 { VEX_LEN_TABLE (VEX_LEN_0F92_P_2
) },
4998 { VEX_LEN_TABLE (VEX_LEN_0F92_P_3
) },
5001 /* PREFIX_VEX_0F93 */
5003 { VEX_LEN_TABLE (VEX_LEN_0F93_P_0
) },
5005 { VEX_LEN_TABLE (VEX_LEN_0F93_P_2
) },
5006 { VEX_LEN_TABLE (VEX_LEN_0F93_P_3
) },
5009 /* PREFIX_VEX_0F98 */
5011 { VEX_LEN_TABLE (VEX_LEN_0F98_P_0
) },
5013 { VEX_LEN_TABLE (VEX_LEN_0F98_P_2
) },
5016 /* PREFIX_VEX_0F99 */
5018 { VEX_LEN_TABLE (VEX_LEN_0F99_P_0
) },
5020 { VEX_LEN_TABLE (VEX_LEN_0F99_P_2
) },
5023 /* PREFIX_VEX_0FC2 */
5025 { "vcmpps", { XM
, Vex
, EXx
, VCMP
}, 0 },
5026 { "vcmpss", { XMScalar
, VexScalar
, EXxmm_md
, VCMP
}, 0 },
5027 { "vcmppd", { XM
, Vex
, EXx
, VCMP
}, 0 },
5028 { "vcmpsd", { XMScalar
, VexScalar
, EXxmm_mq
, VCMP
}, 0 },
5031 /* PREFIX_VEX_0FC4 */
5035 { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2
) },
5038 /* PREFIX_VEX_0FC5 */
5042 { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2
) },
5045 /* PREFIX_VEX_0FD0 */
5049 { "vaddsubpd", { XM
, Vex
, EXx
}, 0 },
5050 { "vaddsubps", { XM
, Vex
, EXx
}, 0 },
5053 /* PREFIX_VEX_0FD1 */
5057 { "vpsrlw", { XM
, Vex
, EXxmm
}, 0 },
5060 /* PREFIX_VEX_0FD2 */
5064 { "vpsrld", { XM
, Vex
, EXxmm
}, 0 },
5067 /* PREFIX_VEX_0FD3 */
5071 { "vpsrlq", { XM
, Vex
, EXxmm
}, 0 },
5074 /* PREFIX_VEX_0FD4 */
5078 { "vpaddq", { XM
, Vex
, EXx
}, 0 },
5081 /* PREFIX_VEX_0FD5 */
5085 { "vpmullw", { XM
, Vex
, EXx
}, 0 },
5088 /* PREFIX_VEX_0FD6 */
5092 { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2
) },
5095 /* PREFIX_VEX_0FD7 */
5099 { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2
) },
5102 /* PREFIX_VEX_0FD8 */
5106 { "vpsubusb", { XM
, Vex
, EXx
}, 0 },
5109 /* PREFIX_VEX_0FD9 */
5113 { "vpsubusw", { XM
, Vex
, EXx
}, 0 },
5116 /* PREFIX_VEX_0FDA */
5120 { "vpminub", { XM
, Vex
, EXx
}, 0 },
5123 /* PREFIX_VEX_0FDB */
5127 { "vpand", { XM
, Vex
, EXx
}, 0 },
5130 /* PREFIX_VEX_0FDC */
5134 { "vpaddusb", { XM
, Vex
, EXx
}, 0 },
5137 /* PREFIX_VEX_0FDD */
5141 { "vpaddusw", { XM
, Vex
, EXx
}, 0 },
5144 /* PREFIX_VEX_0FDE */
5148 { "vpmaxub", { XM
, Vex
, EXx
}, 0 },
5151 /* PREFIX_VEX_0FDF */
5155 { "vpandn", { XM
, Vex
, EXx
}, 0 },
5158 /* PREFIX_VEX_0FE0 */
5162 { "vpavgb", { XM
, Vex
, EXx
}, 0 },
5165 /* PREFIX_VEX_0FE1 */
5169 { "vpsraw", { XM
, Vex
, EXxmm
}, 0 },
5172 /* PREFIX_VEX_0FE2 */
5176 { "vpsrad", { XM
, Vex
, EXxmm
}, 0 },
5179 /* PREFIX_VEX_0FE3 */
5183 { "vpavgw", { XM
, Vex
, EXx
}, 0 },
5186 /* PREFIX_VEX_0FE4 */
5190 { "vpmulhuw", { XM
, Vex
, EXx
}, 0 },
5193 /* PREFIX_VEX_0FE5 */
5197 { "vpmulhw", { XM
, Vex
, EXx
}, 0 },
5200 /* PREFIX_VEX_0FE6 */
5203 { "vcvtdq2pd", { XM
, EXxmmq
}, 0 },
5204 { "vcvttpd2dq%XY", { XMM
, EXx
}, 0 },
5205 { "vcvtpd2dq%XY", { XMM
, EXx
}, 0 },
5208 /* PREFIX_VEX_0FE7 */
5212 { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2
) },
5215 /* PREFIX_VEX_0FE8 */
5219 { "vpsubsb", { XM
, Vex
, EXx
}, 0 },
5222 /* PREFIX_VEX_0FE9 */
5226 { "vpsubsw", { XM
, Vex
, EXx
}, 0 },
5229 /* PREFIX_VEX_0FEA */
5233 { "vpminsw", { XM
, Vex
, EXx
}, 0 },
5236 /* PREFIX_VEX_0FEB */
5240 { "vpor", { XM
, Vex
, EXx
}, 0 },
5243 /* PREFIX_VEX_0FEC */
5247 { "vpaddsb", { XM
, Vex
, EXx
}, 0 },
5250 /* PREFIX_VEX_0FED */
5254 { "vpaddsw", { XM
, Vex
, EXx
}, 0 },
5257 /* PREFIX_VEX_0FEE */
5261 { "vpmaxsw", { XM
, Vex
, EXx
}, 0 },
5264 /* PREFIX_VEX_0FEF */
5268 { "vpxor", { XM
, Vex
, EXx
}, 0 },
5271 /* PREFIX_VEX_0FF0 */
5276 { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3
) },
5279 /* PREFIX_VEX_0FF1 */
5283 { "vpsllw", { XM
, Vex
, EXxmm
}, 0 },
5286 /* PREFIX_VEX_0FF2 */
5290 { "vpslld", { XM
, Vex
, EXxmm
}, 0 },
5293 /* PREFIX_VEX_0FF3 */
5297 { "vpsllq", { XM
, Vex
, EXxmm
}, 0 },
5300 /* PREFIX_VEX_0FF4 */
5304 { "vpmuludq", { XM
, Vex
, EXx
}, 0 },
5307 /* PREFIX_VEX_0FF5 */
5311 { "vpmaddwd", { XM
, Vex
, EXx
}, 0 },
5314 /* PREFIX_VEX_0FF6 */
5318 { "vpsadbw", { XM
, Vex
, EXx
}, 0 },
5321 /* PREFIX_VEX_0FF7 */
5325 { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2
) },
5328 /* PREFIX_VEX_0FF8 */
5332 { "vpsubb", { XM
, Vex
, EXx
}, 0 },
5335 /* PREFIX_VEX_0FF9 */
5339 { "vpsubw", { XM
, Vex
, EXx
}, 0 },
5342 /* PREFIX_VEX_0FFA */
5346 { "vpsubd", { XM
, Vex
, EXx
}, 0 },
5349 /* PREFIX_VEX_0FFB */
5353 { "vpsubq", { XM
, Vex
, EXx
}, 0 },
5356 /* PREFIX_VEX_0FFC */
5360 { "vpaddb", { XM
, Vex
, EXx
}, 0 },
5363 /* PREFIX_VEX_0FFD */
5367 { "vpaddw", { XM
, Vex
, EXx
}, 0 },
5370 /* PREFIX_VEX_0FFE */
5374 { "vpaddd", { XM
, Vex
, EXx
}, 0 },
5377 /* PREFIX_VEX_0F3800 */
5381 { "vpshufb", { XM
, Vex
, EXx
}, 0 },
5384 /* PREFIX_VEX_0F3801 */
5388 { "vphaddw", { XM
, Vex
, EXx
}, 0 },
5391 /* PREFIX_VEX_0F3802 */
5395 { "vphaddd", { XM
, Vex
, EXx
}, 0 },
5398 /* PREFIX_VEX_0F3803 */
5402 { "vphaddsw", { XM
, Vex
, EXx
}, 0 },
5405 /* PREFIX_VEX_0F3804 */
5409 { "vpmaddubsw", { XM
, Vex
, EXx
}, 0 },
5412 /* PREFIX_VEX_0F3805 */
5416 { "vphsubw", { XM
, Vex
, EXx
}, 0 },
5419 /* PREFIX_VEX_0F3806 */
5423 { "vphsubd", { XM
, Vex
, EXx
}, 0 },
5426 /* PREFIX_VEX_0F3807 */
5430 { "vphsubsw", { XM
, Vex
, EXx
}, 0 },
5433 /* PREFIX_VEX_0F3808 */
5437 { "vpsignb", { XM
, Vex
, EXx
}, 0 },
5440 /* PREFIX_VEX_0F3809 */
5444 { "vpsignw", { XM
, Vex
, EXx
}, 0 },
5447 /* PREFIX_VEX_0F380A */
5451 { "vpsignd", { XM
, Vex
, EXx
}, 0 },
5454 /* PREFIX_VEX_0F380B */
5458 { "vpmulhrsw", { XM
, Vex
, EXx
}, 0 },
5461 /* PREFIX_VEX_0F380C */
5465 { VEX_W_TABLE (VEX_W_0F380C_P_2
) },
5468 /* PREFIX_VEX_0F380D */
5472 { VEX_W_TABLE (VEX_W_0F380D_P_2
) },
5475 /* PREFIX_VEX_0F380E */
5479 { VEX_W_TABLE (VEX_W_0F380E_P_2
) },
5482 /* PREFIX_VEX_0F380F */
5486 { VEX_W_TABLE (VEX_W_0F380F_P_2
) },
5489 /* PREFIX_VEX_0F3813 */
5493 { VEX_W_TABLE (VEX_W_0F3813_P_2
) },
5496 /* PREFIX_VEX_0F3816 */
5500 { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2
) },
5503 /* PREFIX_VEX_0F3817 */
5507 { "vptest", { XM
, EXx
}, 0 },
5510 /* PREFIX_VEX_0F3818 */
5514 { VEX_W_TABLE (VEX_W_0F3818_P_2
) },
5517 /* PREFIX_VEX_0F3819 */
5521 { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2
) },
5524 /* PREFIX_VEX_0F381A */
5528 { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2
) },
5531 /* PREFIX_VEX_0F381C */
5535 { "vpabsb", { XM
, EXx
}, 0 },
5538 /* PREFIX_VEX_0F381D */
5542 { "vpabsw", { XM
, EXx
}, 0 },
5545 /* PREFIX_VEX_0F381E */
5549 { "vpabsd", { XM
, EXx
}, 0 },
5552 /* PREFIX_VEX_0F3820 */
5556 { "vpmovsxbw", { XM
, EXxmmq
}, 0 },
5559 /* PREFIX_VEX_0F3821 */
5563 { "vpmovsxbd", { XM
, EXxmmqd
}, 0 },
5566 /* PREFIX_VEX_0F3822 */
5570 { "vpmovsxbq", { XM
, EXxmmdw
}, 0 },
5573 /* PREFIX_VEX_0F3823 */
5577 { "vpmovsxwd", { XM
, EXxmmq
}, 0 },
5580 /* PREFIX_VEX_0F3824 */
5584 { "vpmovsxwq", { XM
, EXxmmqd
}, 0 },
5587 /* PREFIX_VEX_0F3825 */
5591 { "vpmovsxdq", { XM
, EXxmmq
}, 0 },
5594 /* PREFIX_VEX_0F3828 */
5598 { "vpmuldq", { XM
, Vex
, EXx
}, 0 },
5601 /* PREFIX_VEX_0F3829 */
5605 { "vpcmpeqq", { XM
, Vex
, EXx
}, 0 },
5608 /* PREFIX_VEX_0F382A */
5612 { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2
) },
5615 /* PREFIX_VEX_0F382B */
5619 { "vpackusdw", { XM
, Vex
, EXx
}, 0 },
5622 /* PREFIX_VEX_0F382C */
5626 { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2
) },
5629 /* PREFIX_VEX_0F382D */
5633 { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2
) },
5636 /* PREFIX_VEX_0F382E */
5640 { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2
) },
5643 /* PREFIX_VEX_0F382F */
5647 { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2
) },
5650 /* PREFIX_VEX_0F3830 */
5654 { "vpmovzxbw", { XM
, EXxmmq
}, 0 },
5657 /* PREFIX_VEX_0F3831 */
5661 { "vpmovzxbd", { XM
, EXxmmqd
}, 0 },
5664 /* PREFIX_VEX_0F3832 */
5668 { "vpmovzxbq", { XM
, EXxmmdw
}, 0 },
5671 /* PREFIX_VEX_0F3833 */
5675 { "vpmovzxwd", { XM
, EXxmmq
}, 0 },
5678 /* PREFIX_VEX_0F3834 */
5682 { "vpmovzxwq", { XM
, EXxmmqd
}, 0 },
5685 /* PREFIX_VEX_0F3835 */
5689 { "vpmovzxdq", { XM
, EXxmmq
}, 0 },
5692 /* PREFIX_VEX_0F3836 */
5696 { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2
) },
5699 /* PREFIX_VEX_0F3837 */
5703 { "vpcmpgtq", { XM
, Vex
, EXx
}, 0 },
5706 /* PREFIX_VEX_0F3838 */
5710 { "vpminsb", { XM
, Vex
, EXx
}, 0 },
5713 /* PREFIX_VEX_0F3839 */
5717 { "vpminsd", { XM
, Vex
, EXx
}, 0 },
5720 /* PREFIX_VEX_0F383A */
5724 { "vpminuw", { XM
, Vex
, EXx
}, 0 },
5727 /* PREFIX_VEX_0F383B */
5731 { "vpminud", { XM
, Vex
, EXx
}, 0 },
5734 /* PREFIX_VEX_0F383C */
5738 { "vpmaxsb", { XM
, Vex
, EXx
}, 0 },
5741 /* PREFIX_VEX_0F383D */
5745 { "vpmaxsd", { XM
, Vex
, EXx
}, 0 },
5748 /* PREFIX_VEX_0F383E */
5752 { "vpmaxuw", { XM
, Vex
, EXx
}, 0 },
5755 /* PREFIX_VEX_0F383F */
5759 { "vpmaxud", { XM
, Vex
, EXx
}, 0 },
5762 /* PREFIX_VEX_0F3840 */
5766 { "vpmulld", { XM
, Vex
, EXx
}, 0 },
5769 /* PREFIX_VEX_0F3841 */
5773 { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2
) },
5776 /* PREFIX_VEX_0F3845 */
5780 { "vpsrlv%LW", { XM
, Vex
, EXx
}, 0 },
5783 /* PREFIX_VEX_0F3846 */
5787 { VEX_W_TABLE (VEX_W_0F3846_P_2
) },
5790 /* PREFIX_VEX_0F3847 */
5794 { "vpsllv%LW", { XM
, Vex
, EXx
}, 0 },
5797 /* PREFIX_VEX_0F3858 */
5801 { VEX_W_TABLE (VEX_W_0F3858_P_2
) },
5804 /* PREFIX_VEX_0F3859 */
5808 { VEX_W_TABLE (VEX_W_0F3859_P_2
) },
5811 /* PREFIX_VEX_0F385A */
5815 { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2
) },
5818 /* PREFIX_VEX_0F3878 */
5822 { VEX_W_TABLE (VEX_W_0F3878_P_2
) },
5825 /* PREFIX_VEX_0F3879 */
5829 { VEX_W_TABLE (VEX_W_0F3879_P_2
) },
5832 /* PREFIX_VEX_0F388C */
5836 { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2
) },
5839 /* PREFIX_VEX_0F388E */
5843 { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2
) },
5846 /* PREFIX_VEX_0F3890 */
5850 { "vpgatherd%LW", { XM
, MVexVSIBDWpX
, Vex
}, 0 },
5853 /* PREFIX_VEX_0F3891 */
5857 { "vpgatherq%LW", { XMGatherQ
, MVexVSIBQWpX
, VexGatherQ
}, 0 },
5860 /* PREFIX_VEX_0F3892 */
5864 { "vgatherdp%XW", { XM
, MVexVSIBDWpX
, Vex
}, 0 },
5867 /* PREFIX_VEX_0F3893 */
5871 { "vgatherqp%XW", { XMGatherQ
, MVexVSIBQWpX
, VexGatherQ
}, 0 },
5874 /* PREFIX_VEX_0F3896 */
5878 { "vfmaddsub132p%XW", { XM
, Vex
, EXx
, EXxEVexR
}, 0 },
5881 /* PREFIX_VEX_0F3897 */
5885 { "vfmsubadd132p%XW", { XM
, Vex
, EXx
, EXxEVexR
}, 0 },
5888 /* PREFIX_VEX_0F3898 */
5892 { "vfmadd132p%XW", { XM
, Vex
, EXx
, EXxEVexR
}, 0 },
5895 /* PREFIX_VEX_0F3899 */
5899 { "vfmadd132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
, EXxEVexR
}, 0 },
5902 /* PREFIX_VEX_0F389A */
5906 { "vfmsub132p%XW", { XM
, Vex
, EXx
}, 0 },
5909 /* PREFIX_VEX_0F389B */
5913 { "vfmsub132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
5916 /* PREFIX_VEX_0F389C */
5920 { "vfnmadd132p%XW", { XM
, Vex
, EXx
, EXxEVexR
}, 0 },
5923 /* PREFIX_VEX_0F389D */
5927 { "vfnmadd132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
, EXxEVexR
}, 0 },
5930 /* PREFIX_VEX_0F389E */
5934 { "vfnmsub132p%XW", { XM
, Vex
, EXx
, EXxEVexR
}, 0 },
5937 /* PREFIX_VEX_0F389F */
5941 { "vfnmsub132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
, EXxEVexR
}, 0 },
5944 /* PREFIX_VEX_0F38A6 */
5948 { "vfmaddsub213p%XW", { XM
, Vex
, EXx
, EXxEVexR
}, 0 },
5952 /* PREFIX_VEX_0F38A7 */
5956 { "vfmsubadd213p%XW", { XM
, Vex
, EXx
, EXxEVexR
}, 0 },
5959 /* PREFIX_VEX_0F38A8 */
5963 { "vfmadd213p%XW", { XM
, Vex
, EXx
, EXxEVexR
}, 0 },
5966 /* PREFIX_VEX_0F38A9 */
5970 { "vfmadd213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
, EXxEVexR
}, 0 },
5973 /* PREFIX_VEX_0F38AA */
5977 { "vfmsub213p%XW", { XM
, Vex
, EXx
}, 0 },
5980 /* PREFIX_VEX_0F38AB */
5984 { "vfmsub213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
5987 /* PREFIX_VEX_0F38AC */
5991 { "vfnmadd213p%XW", { XM
, Vex
, EXx
, EXxEVexR
}, 0 },
5994 /* PREFIX_VEX_0F38AD */
5998 { "vfnmadd213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
, EXxEVexR
}, 0 },
6001 /* PREFIX_VEX_0F38AE */
6005 { "vfnmsub213p%XW", { XM
, Vex
, EXx
, EXxEVexR
}, 0 },
6008 /* PREFIX_VEX_0F38AF */
6012 { "vfnmsub213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
, EXxEVexR
}, 0 },
6015 /* PREFIX_VEX_0F38B6 */
6019 { "vfmaddsub231p%XW", { XM
, Vex
, EXx
, EXxEVexR
}, 0 },
6022 /* PREFIX_VEX_0F38B7 */
6026 { "vfmsubadd231p%XW", { XM
, Vex
, EXx
, EXxEVexR
}, 0 },
6029 /* PREFIX_VEX_0F38B8 */
6033 { "vfmadd231p%XW", { XM
, Vex
, EXx
, EXxEVexR
}, 0 },
6036 /* PREFIX_VEX_0F38B9 */
6040 { "vfmadd231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
, EXxEVexR
}, 0 },
6043 /* PREFIX_VEX_0F38BA */
6047 { "vfmsub231p%XW", { XM
, Vex
, EXx
, EXxEVexR
}, 0 },
6050 /* PREFIX_VEX_0F38BB */
6054 { "vfmsub231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
, EXxEVexR
}, 0 },
6057 /* PREFIX_VEX_0F38BC */
6061 { "vfnmadd231p%XW", { XM
, Vex
, EXx
, EXxEVexR
}, 0 },
6064 /* PREFIX_VEX_0F38BD */
6068 { "vfnmadd231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
, EXxEVexR
}, 0 },
6071 /* PREFIX_VEX_0F38BE */
6075 { "vfnmsub231p%XW", { XM
, Vex
, EXx
, EXxEVexR
}, 0 },
6078 /* PREFIX_VEX_0F38BF */
6082 { "vfnmsub231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
, EXxEVexR
}, 0 },
6085 /* PREFIX_VEX_0F38CF */
6089 { VEX_W_TABLE (VEX_W_0F38CF_P_2
) },
6092 /* PREFIX_VEX_0F38DB */
6096 { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2
) },
6099 /* PREFIX_VEX_0F38DC */
6103 { "vaesenc", { XM
, Vex
, EXx
}, 0 },
6106 /* PREFIX_VEX_0F38DD */
6110 { "vaesenclast", { XM
, Vex
, EXx
}, 0 },
6113 /* PREFIX_VEX_0F38DE */
6117 { "vaesdec", { XM
, Vex
, EXx
}, 0 },
6120 /* PREFIX_VEX_0F38DF */
6124 { "vaesdeclast", { XM
, Vex
, EXx
}, 0 },
6127 /* PREFIX_VEX_0F38F2 */
6129 { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0
) },
6132 /* PREFIX_VEX_0F38F3_REG_1 */
6134 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0
) },
6137 /* PREFIX_VEX_0F38F3_REG_2 */
6139 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0
) },
6142 /* PREFIX_VEX_0F38F3_REG_3 */
6144 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0
) },
6147 /* PREFIX_VEX_0F38F5 */
6149 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0
) },
6150 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1
) },
6152 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3
) },
6155 /* PREFIX_VEX_0F38F6 */
6160 { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3
) },
6163 /* PREFIX_VEX_0F38F7 */
6165 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0
) },
6166 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1
) },
6167 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2
) },
6168 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3
) },
6171 /* PREFIX_VEX_0F3A00 */
6175 { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2
) },
6178 /* PREFIX_VEX_0F3A01 */
6182 { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2
) },
6185 /* PREFIX_VEX_0F3A02 */
6189 { VEX_W_TABLE (VEX_W_0F3A02_P_2
) },
6192 /* PREFIX_VEX_0F3A04 */
6196 { VEX_W_TABLE (VEX_W_0F3A04_P_2
) },
6199 /* PREFIX_VEX_0F3A05 */
6203 { VEX_W_TABLE (VEX_W_0F3A05_P_2
) },
6206 /* PREFIX_VEX_0F3A06 */
6210 { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2
) },
6213 /* PREFIX_VEX_0F3A08 */
6217 { "vroundps", { XM
, EXx
, Ib
}, 0 },
6220 /* PREFIX_VEX_0F3A09 */
6224 { "vroundpd", { XM
, EXx
, Ib
}, 0 },
6227 /* PREFIX_VEX_0F3A0A */
6231 { "vroundss", { XMScalar
, VexScalar
, EXxmm_md
, Ib
}, 0 },
6234 /* PREFIX_VEX_0F3A0B */
6238 { "vroundsd", { XMScalar
, VexScalar
, EXxmm_mq
, Ib
}, 0 },
6241 /* PREFIX_VEX_0F3A0C */
6245 { "vblendps", { XM
, Vex
, EXx
, Ib
}, 0 },
6248 /* PREFIX_VEX_0F3A0D */
6252 { "vblendpd", { XM
, Vex
, EXx
, Ib
}, 0 },
6255 /* PREFIX_VEX_0F3A0E */
6259 { "vpblendw", { XM
, Vex
, EXx
, Ib
}, 0 },
6262 /* PREFIX_VEX_0F3A0F */
6266 { "vpalignr", { XM
, Vex
, EXx
, Ib
}, 0 },
6269 /* PREFIX_VEX_0F3A14 */
6273 { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2
) },
6276 /* PREFIX_VEX_0F3A15 */
6280 { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2
) },
6283 /* PREFIX_VEX_0F3A16 */
6287 { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2
) },
6290 /* PREFIX_VEX_0F3A17 */
6294 { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2
) },
6297 /* PREFIX_VEX_0F3A18 */
6301 { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2
) },
6304 /* PREFIX_VEX_0F3A19 */
6308 { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2
) },
6311 /* PREFIX_VEX_0F3A1D */
6315 { VEX_W_TABLE (VEX_W_0F3A1D_P_2
) },
6318 /* PREFIX_VEX_0F3A20 */
6322 { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2
) },
6325 /* PREFIX_VEX_0F3A21 */
6329 { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2
) },
6332 /* PREFIX_VEX_0F3A22 */
6336 { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2
) },
6339 /* PREFIX_VEX_0F3A30 */
6343 { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2
) },
6346 /* PREFIX_VEX_0F3A31 */
6350 { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2
) },
6353 /* PREFIX_VEX_0F3A32 */
6357 { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2
) },
6360 /* PREFIX_VEX_0F3A33 */
6364 { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2
) },
6367 /* PREFIX_VEX_0F3A38 */
6371 { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2
) },
6374 /* PREFIX_VEX_0F3A39 */
6378 { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2
) },
6381 /* PREFIX_VEX_0F3A40 */
6385 { "vdpps", { XM
, Vex
, EXx
, Ib
}, 0 },
6388 /* PREFIX_VEX_0F3A41 */
6392 { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2
) },
6395 /* PREFIX_VEX_0F3A42 */
6399 { "vmpsadbw", { XM
, Vex
, EXx
, Ib
}, 0 },
6402 /* PREFIX_VEX_0F3A44 */
6406 { "vpclmulqdq", { XM
, Vex
, EXx
, PCLMUL
}, 0 },
6409 /* PREFIX_VEX_0F3A46 */
6413 { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2
) },
6416 /* PREFIX_VEX_0F3A48 */
6420 { VEX_W_TABLE (VEX_W_0F3A48_P_2
) },
6423 /* PREFIX_VEX_0F3A49 */
6427 { VEX_W_TABLE (VEX_W_0F3A49_P_2
) },
6430 /* PREFIX_VEX_0F3A4A */
6434 { VEX_W_TABLE (VEX_W_0F3A4A_P_2
) },
6437 /* PREFIX_VEX_0F3A4B */
6441 { VEX_W_TABLE (VEX_W_0F3A4B_P_2
) },
6444 /* PREFIX_VEX_0F3A4C */
6448 { VEX_W_TABLE (VEX_W_0F3A4C_P_2
) },
6451 /* PREFIX_VEX_0F3A5C */
6455 { "vfmaddsubps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6458 /* PREFIX_VEX_0F3A5D */
6462 { "vfmaddsubpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6465 /* PREFIX_VEX_0F3A5E */
6469 { "vfmsubaddps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6472 /* PREFIX_VEX_0F3A5F */
6476 { "vfmsubaddpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6479 /* PREFIX_VEX_0F3A60 */
6483 { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2
) },
6487 /* PREFIX_VEX_0F3A61 */
6491 { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2
) },
6494 /* PREFIX_VEX_0F3A62 */
6498 { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2
) },
6501 /* PREFIX_VEX_0F3A63 */
6505 { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2
) },
6508 /* PREFIX_VEX_0F3A68 */
6512 { "vfmaddps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6515 /* PREFIX_VEX_0F3A69 */
6519 { "vfmaddpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6522 /* PREFIX_VEX_0F3A6A */
6526 { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2
) },
6529 /* PREFIX_VEX_0F3A6B */
6533 { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2
) },
6536 /* PREFIX_VEX_0F3A6C */
6540 { "vfmsubps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6543 /* PREFIX_VEX_0F3A6D */
6547 { "vfmsubpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6550 /* PREFIX_VEX_0F3A6E */
6554 { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2
) },
6557 /* PREFIX_VEX_0F3A6F */
6561 { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2
) },
6564 /* PREFIX_VEX_0F3A78 */
6568 { "vfnmaddps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6571 /* PREFIX_VEX_0F3A79 */
6575 { "vfnmaddpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6578 /* PREFIX_VEX_0F3A7A */
6582 { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2
) },
6585 /* PREFIX_VEX_0F3A7B */
6589 { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2
) },
6592 /* PREFIX_VEX_0F3A7C */
6596 { "vfnmsubps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6600 /* PREFIX_VEX_0F3A7D */
6604 { "vfnmsubpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6607 /* PREFIX_VEX_0F3A7E */
6611 { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2
) },
6614 /* PREFIX_VEX_0F3A7F */
6618 { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2
) },
6621 /* PREFIX_VEX_0F3ACE */
6625 { VEX_W_TABLE (VEX_W_0F3ACE_P_2
) },
6628 /* PREFIX_VEX_0F3ACF */
6632 { VEX_W_TABLE (VEX_W_0F3ACF_P_2
) },
6635 /* PREFIX_VEX_0F3ADF */
6639 { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2
) },
6642 /* PREFIX_VEX_0F3AF0 */
6647 { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3
) },
6650 #include "i386-dis-evex-prefix.h"
6653 static const struct dis386 x86_64_table
[][2] = {
6656 { "pushP", { es
}, 0 },
6661 { "popP", { es
}, 0 },
6666 { "pushP", { cs
}, 0 },
6671 { "pushP", { ss
}, 0 },
6676 { "popP", { ss
}, 0 },
6681 { "pushP", { ds
}, 0 },
6686 { "popP", { ds
}, 0 },
6691 { "daa", { XX
}, 0 },
6696 { "das", { XX
}, 0 },
6701 { "aaa", { XX
}, 0 },
6706 { "aas", { XX
}, 0 },
6711 { "pushaP", { XX
}, 0 },
6716 { "popaP", { XX
}, 0 },
6721 { MOD_TABLE (MOD_62_32BIT
) },
6722 { EVEX_TABLE (EVEX_0F
) },
6727 { "arpl", { Ew
, Gw
}, 0 },
6728 { "movs", { { OP_G
, movsxd_mode
}, { MOVSXD_Fixup
, movsxd_mode
} }, 0 },
6733 { "ins{R|}", { Yzr
, indirDX
}, 0 },
6734 { "ins{G|}", { Yzr
, indirDX
}, 0 },
6739 { "outs{R|}", { indirDXr
, Xz
}, 0 },
6740 { "outs{G|}", { indirDXr
, Xz
}, 0 },
6745 /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode. */
6746 { REG_TABLE (REG_80
) },
6751 { "{l|}call{T|}", { Ap
}, 0 },
6756 { "retP", { Iw
, BND
}, 0 },
6757 { "ret@", { Iw
, BND
}, 0 },
6762 { "retP", { BND
}, 0 },
6763 { "ret@", { BND
}, 0 },
6768 { MOD_TABLE (MOD_C4_32BIT
) },
6769 { VEX_C4_TABLE (VEX_0F
) },
6774 { MOD_TABLE (MOD_C5_32BIT
) },
6775 { VEX_C5_TABLE (VEX_0F
) },
6780 { "into", { XX
}, 0 },
6785 { "aam", { Ib
}, 0 },
6790 { "aad", { Ib
}, 0 },
6795 { "callP", { Jv
, BND
}, 0 },
6796 { "call@", { Jv
, BND
}, 0 }
6801 { "jmpP", { Jv
, BND
}, 0 },
6802 { "jmp@", { Jv
, BND
}, 0 }
6807 { "{l|}jmp{T|}", { Ap
}, 0 },
6810 /* X86_64_0F01_REG_0 */
6812 { "sgdt{Q|Q}", { M
}, 0 },
6813 { "sgdt", { M
}, 0 },
6816 /* X86_64_0F01_REG_1 */
6818 { "sidt{Q|Q}", { M
}, 0 },
6819 { "sidt", { M
}, 0 },
6822 /* X86_64_0F01_REG_2 */
6824 { "lgdt{Q|Q}", { M
}, 0 },
6825 { "lgdt", { M
}, 0 },
6828 /* X86_64_0F01_REG_3 */
6830 { "lidt{Q|Q}", { M
}, 0 },
6831 { "lidt", { M
}, 0 },
6835 static const struct dis386 three_byte_table
[][256] = {
6837 /* THREE_BYTE_0F38 */
6840 { "pshufb", { MX
, EM
}, PREFIX_OPCODE
},
6841 { "phaddw", { MX
, EM
}, PREFIX_OPCODE
},
6842 { "phaddd", { MX
, EM
}, PREFIX_OPCODE
},
6843 { "phaddsw", { MX
, EM
}, PREFIX_OPCODE
},
6844 { "pmaddubsw", { MX
, EM
}, PREFIX_OPCODE
},
6845 { "phsubw", { MX
, EM
}, PREFIX_OPCODE
},
6846 { "phsubd", { MX
, EM
}, PREFIX_OPCODE
},
6847 { "phsubsw", { MX
, EM
}, PREFIX_OPCODE
},
6849 { "psignb", { MX
, EM
}, PREFIX_OPCODE
},
6850 { "psignw", { MX
, EM
}, PREFIX_OPCODE
},
6851 { "psignd", { MX
, EM
}, PREFIX_OPCODE
},
6852 { "pmulhrsw", { MX
, EM
}, PREFIX_OPCODE
},
6858 { PREFIX_TABLE (PREFIX_0F3810
) },
6862 { PREFIX_TABLE (PREFIX_0F3814
) },
6863 { PREFIX_TABLE (PREFIX_0F3815
) },
6865 { PREFIX_TABLE (PREFIX_0F3817
) },
6871 { "pabsb", { MX
, EM
}, PREFIX_OPCODE
},
6872 { "pabsw", { MX
, EM
}, PREFIX_OPCODE
},
6873 { "pabsd", { MX
, EM
}, PREFIX_OPCODE
},
6876 { PREFIX_TABLE (PREFIX_0F3820
) },
6877 { PREFIX_TABLE (PREFIX_0F3821
) },
6878 { PREFIX_TABLE (PREFIX_0F3822
) },
6879 { PREFIX_TABLE (PREFIX_0F3823
) },
6880 { PREFIX_TABLE (PREFIX_0F3824
) },
6881 { PREFIX_TABLE (PREFIX_0F3825
) },
6885 { PREFIX_TABLE (PREFIX_0F3828
) },
6886 { PREFIX_TABLE (PREFIX_0F3829
) },
6887 { PREFIX_TABLE (PREFIX_0F382A
) },
6888 { PREFIX_TABLE (PREFIX_0F382B
) },
6894 { PREFIX_TABLE (PREFIX_0F3830
) },
6895 { PREFIX_TABLE (PREFIX_0F3831
) },
6896 { PREFIX_TABLE (PREFIX_0F3832
) },
6897 { PREFIX_TABLE (PREFIX_0F3833
) },
6898 { PREFIX_TABLE (PREFIX_0F3834
) },
6899 { PREFIX_TABLE (PREFIX_0F3835
) },
6901 { PREFIX_TABLE (PREFIX_0F3837
) },
6903 { PREFIX_TABLE (PREFIX_0F3838
) },
6904 { PREFIX_TABLE (PREFIX_0F3839
) },
6905 { PREFIX_TABLE (PREFIX_0F383A
) },
6906 { PREFIX_TABLE (PREFIX_0F383B
) },
6907 { PREFIX_TABLE (PREFIX_0F383C
) },
6908 { PREFIX_TABLE (PREFIX_0F383D
) },
6909 { PREFIX_TABLE (PREFIX_0F383E
) },
6910 { PREFIX_TABLE (PREFIX_0F383F
) },
6912 { PREFIX_TABLE (PREFIX_0F3840
) },
6913 { PREFIX_TABLE (PREFIX_0F3841
) },
6984 { PREFIX_TABLE (PREFIX_0F3880
) },
6985 { PREFIX_TABLE (PREFIX_0F3881
) },
6986 { PREFIX_TABLE (PREFIX_0F3882
) },
7065 { PREFIX_TABLE (PREFIX_0F38C8
) },
7066 { PREFIX_TABLE (PREFIX_0F38C9
) },
7067 { PREFIX_TABLE (PREFIX_0F38CA
) },
7068 { PREFIX_TABLE (PREFIX_0F38CB
) },
7069 { PREFIX_TABLE (PREFIX_0F38CC
) },
7070 { PREFIX_TABLE (PREFIX_0F38CD
) },
7072 { PREFIX_TABLE (PREFIX_0F38CF
) },
7086 { PREFIX_TABLE (PREFIX_0F38DB
) },
7087 { PREFIX_TABLE (PREFIX_0F38DC
) },
7088 { PREFIX_TABLE (PREFIX_0F38DD
) },
7089 { PREFIX_TABLE (PREFIX_0F38DE
) },
7090 { PREFIX_TABLE (PREFIX_0F38DF
) },
7110 { PREFIX_TABLE (PREFIX_0F38F0
) },
7111 { PREFIX_TABLE (PREFIX_0F38F1
) },
7115 { PREFIX_TABLE (PREFIX_0F38F5
) },
7116 { PREFIX_TABLE (PREFIX_0F38F6
) },
7119 { PREFIX_TABLE (PREFIX_0F38F8
) },
7120 { PREFIX_TABLE (PREFIX_0F38F9
) },
7128 /* THREE_BYTE_0F3A */
7140 { PREFIX_TABLE (PREFIX_0F3A08
) },
7141 { PREFIX_TABLE (PREFIX_0F3A09
) },
7142 { PREFIX_TABLE (PREFIX_0F3A0A
) },
7143 { PREFIX_TABLE (PREFIX_0F3A0B
) },
7144 { PREFIX_TABLE (PREFIX_0F3A0C
) },
7145 { PREFIX_TABLE (PREFIX_0F3A0D
) },
7146 { PREFIX_TABLE (PREFIX_0F3A0E
) },
7147 { "palignr", { MX
, EM
, Ib
}, PREFIX_OPCODE
},
7153 { PREFIX_TABLE (PREFIX_0F3A14
) },
7154 { PREFIX_TABLE (PREFIX_0F3A15
) },
7155 { PREFIX_TABLE (PREFIX_0F3A16
) },
7156 { PREFIX_TABLE (PREFIX_0F3A17
) },
7167 { PREFIX_TABLE (PREFIX_0F3A20
) },
7168 { PREFIX_TABLE (PREFIX_0F3A21
) },
7169 { PREFIX_TABLE (PREFIX_0F3A22
) },
7203 { PREFIX_TABLE (PREFIX_0F3A40
) },
7204 { PREFIX_TABLE (PREFIX_0F3A41
) },
7205 { PREFIX_TABLE (PREFIX_0F3A42
) },
7207 { PREFIX_TABLE (PREFIX_0F3A44
) },
7239 { PREFIX_TABLE (PREFIX_0F3A60
) },
7240 { PREFIX_TABLE (PREFIX_0F3A61
) },
7241 { PREFIX_TABLE (PREFIX_0F3A62
) },
7242 { PREFIX_TABLE (PREFIX_0F3A63
) },
7360 { PREFIX_TABLE (PREFIX_0F3ACC
) },
7362 { PREFIX_TABLE (PREFIX_0F3ACE
) },
7363 { PREFIX_TABLE (PREFIX_0F3ACF
) },
7381 { PREFIX_TABLE (PREFIX_0F3ADF
) },
7421 static const struct dis386 xop_table
[][256] = {
7574 { "vpmacssww", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7575 { "vpmacsswd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7576 { "vpmacssdql", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7584 { "vpmacssdd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7585 { "vpmacssdqh", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7592 { "vpmacsww", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7593 { "vpmacswd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7594 { "vpmacsdql", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7602 { "vpmacsdd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7603 { "vpmacsdqh", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7607 { "vpcmov", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7608 { "vpperm", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7611 { "vpmadcsswd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7629 { "vpmadcswd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7641 { "vprotb", { XM
, Vex_2src_1
, Ib
}, 0 },
7642 { "vprotw", { XM
, Vex_2src_1
, Ib
}, 0 },
7643 { "vprotd", { XM
, Vex_2src_1
, Ib
}, 0 },
7644 { "vprotq", { XM
, Vex_2src_1
, Ib
}, 0 },
7654 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC
) },
7655 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD
) },
7656 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE
) },
7657 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF
) },
7690 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC
) },
7691 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED
) },
7692 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE
) },
7693 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF
) },
7717 { REG_TABLE (REG_XOP_TBM_01
) },
7718 { REG_TABLE (REG_XOP_TBM_02
) },
7736 { REG_TABLE (REG_XOP_LWPCB
) },
7860 { VEX_W_TABLE (VEX_W_0FXOP_09_80
) },
7861 { VEX_W_TABLE (VEX_W_0FXOP_09_81
) },
7862 { VEX_W_TABLE (VEX_W_0FXOP_09_82
) },
7863 { VEX_W_TABLE (VEX_W_0FXOP_09_83
) },
7878 { "vprotb", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
7879 { "vprotw", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
7880 { "vprotd", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
7881 { "vprotq", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
7882 { "vpshlb", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
7883 { "vpshlw", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
7884 { "vpshld", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
7885 { "vpshlq", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
7887 { "vpshab", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
7888 { "vpshaw", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
7889 { "vpshad", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
7890 { "vpshaq", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
7933 { "vphaddbw", { XM
, EXxmm
}, 0 },
7934 { "vphaddbd", { XM
, EXxmm
}, 0 },
7935 { "vphaddbq", { XM
, EXxmm
}, 0 },
7938 { "vphaddwd", { XM
, EXxmm
}, 0 },
7939 { "vphaddwq", { XM
, EXxmm
}, 0 },
7944 { "vphadddq", { XM
, EXxmm
}, 0 },
7951 { "vphaddubw", { XM
, EXxmm
}, 0 },
7952 { "vphaddubd", { XM
, EXxmm
}, 0 },
7953 { "vphaddubq", { XM
, EXxmm
}, 0 },
7956 { "vphadduwd", { XM
, EXxmm
}, 0 },
7957 { "vphadduwq", { XM
, EXxmm
}, 0 },
7962 { "vphaddudq", { XM
, EXxmm
}, 0 },
7969 { "vphsubbw", { XM
, EXxmm
}, 0 },
7970 { "vphsubwd", { XM
, EXxmm
}, 0 },
7971 { "vphsubdq", { XM
, EXxmm
}, 0 },
8025 { "bextrS", { Gdq
, Edq
, Id
}, 0 },
8027 { REG_TABLE (REG_XOP_LWP
) },
8297 static const struct dis386 vex_table
[][256] = {
8319 { PREFIX_TABLE (PREFIX_VEX_0F10
) },
8320 { PREFIX_TABLE (PREFIX_VEX_0F11
) },
8321 { PREFIX_TABLE (PREFIX_VEX_0F12
) },
8322 { MOD_TABLE (MOD_VEX_0F13
) },
8323 { "vunpcklpX", { XM
, Vex
, EXx
}, PREFIX_OPCODE
},
8324 { "vunpckhpX", { XM
, Vex
, EXx
}, PREFIX_OPCODE
},
8325 { PREFIX_TABLE (PREFIX_VEX_0F16
) },
8326 { MOD_TABLE (MOD_VEX_0F17
) },
8346 { "vmovapX", { XM
, EXx
}, PREFIX_OPCODE
},
8347 { "vmovapX", { EXxS
, XM
}, PREFIX_OPCODE
},
8348 { PREFIX_TABLE (PREFIX_VEX_0F2A
) },
8349 { MOD_TABLE (MOD_VEX_0F2B
) },
8350 { PREFIX_TABLE (PREFIX_VEX_0F2C
) },
8351 { PREFIX_TABLE (PREFIX_VEX_0F2D
) },
8352 { PREFIX_TABLE (PREFIX_VEX_0F2E
) },
8353 { PREFIX_TABLE (PREFIX_VEX_0F2F
) },
8374 { PREFIX_TABLE (PREFIX_VEX_0F41
) },
8375 { PREFIX_TABLE (PREFIX_VEX_0F42
) },
8377 { PREFIX_TABLE (PREFIX_VEX_0F44
) },
8378 { PREFIX_TABLE (PREFIX_VEX_0F45
) },
8379 { PREFIX_TABLE (PREFIX_VEX_0F46
) },
8380 { PREFIX_TABLE (PREFIX_VEX_0F47
) },
8384 { PREFIX_TABLE (PREFIX_VEX_0F4A
) },
8385 { PREFIX_TABLE (PREFIX_VEX_0F4B
) },
8391 { MOD_TABLE (MOD_VEX_0F50
) },
8392 { PREFIX_TABLE (PREFIX_VEX_0F51
) },
8393 { PREFIX_TABLE (PREFIX_VEX_0F52
) },
8394 { PREFIX_TABLE (PREFIX_VEX_0F53
) },
8395 { "vandpX", { XM
, Vex
, EXx
}, PREFIX_OPCODE
},
8396 { "vandnpX", { XM
, Vex
, EXx
}, PREFIX_OPCODE
},
8397 { "vorpX", { XM
, Vex
, EXx
}, PREFIX_OPCODE
},
8398 { "vxorpX", { XM
, Vex
, EXx
}, PREFIX_OPCODE
},
8400 { PREFIX_TABLE (PREFIX_VEX_0F58
) },
8401 { PREFIX_TABLE (PREFIX_VEX_0F59
) },
8402 { PREFIX_TABLE (PREFIX_VEX_0F5A
) },
8403 { PREFIX_TABLE (PREFIX_VEX_0F5B
) },
8404 { PREFIX_TABLE (PREFIX_VEX_0F5C
) },
8405 { PREFIX_TABLE (PREFIX_VEX_0F5D
) },
8406 { PREFIX_TABLE (PREFIX_VEX_0F5E
) },
8407 { PREFIX_TABLE (PREFIX_VEX_0F5F
) },
8409 { PREFIX_TABLE (PREFIX_VEX_0F60
) },
8410 { PREFIX_TABLE (PREFIX_VEX_0F61
) },
8411 { PREFIX_TABLE (PREFIX_VEX_0F62
) },
8412 { PREFIX_TABLE (PREFIX_VEX_0F63
) },
8413 { PREFIX_TABLE (PREFIX_VEX_0F64
) },
8414 { PREFIX_TABLE (PREFIX_VEX_0F65
) },
8415 { PREFIX_TABLE (PREFIX_VEX_0F66
) },
8416 { PREFIX_TABLE (PREFIX_VEX_0F67
) },
8418 { PREFIX_TABLE (PREFIX_VEX_0F68
) },
8419 { PREFIX_TABLE (PREFIX_VEX_0F69
) },
8420 { PREFIX_TABLE (PREFIX_VEX_0F6A
) },
8421 { PREFIX_TABLE (PREFIX_VEX_0F6B
) },
8422 { PREFIX_TABLE (PREFIX_VEX_0F6C
) },
8423 { PREFIX_TABLE (PREFIX_VEX_0F6D
) },
8424 { PREFIX_TABLE (PREFIX_VEX_0F6E
) },
8425 { PREFIX_TABLE (PREFIX_VEX_0F6F
) },
8427 { PREFIX_TABLE (PREFIX_VEX_0F70
) },
8428 { REG_TABLE (REG_VEX_0F71
) },
8429 { REG_TABLE (REG_VEX_0F72
) },
8430 { REG_TABLE (REG_VEX_0F73
) },
8431 { PREFIX_TABLE (PREFIX_VEX_0F74
) },
8432 { PREFIX_TABLE (PREFIX_VEX_0F75
) },
8433 { PREFIX_TABLE (PREFIX_VEX_0F76
) },
8434 { PREFIX_TABLE (PREFIX_VEX_0F77
) },
8440 { PREFIX_TABLE (PREFIX_VEX_0F7C
) },
8441 { PREFIX_TABLE (PREFIX_VEX_0F7D
) },
8442 { PREFIX_TABLE (PREFIX_VEX_0F7E
) },
8443 { PREFIX_TABLE (PREFIX_VEX_0F7F
) },
8463 { PREFIX_TABLE (PREFIX_VEX_0F90
) },
8464 { PREFIX_TABLE (PREFIX_VEX_0F91
) },
8465 { PREFIX_TABLE (PREFIX_VEX_0F92
) },
8466 { PREFIX_TABLE (PREFIX_VEX_0F93
) },
8472 { PREFIX_TABLE (PREFIX_VEX_0F98
) },
8473 { PREFIX_TABLE (PREFIX_VEX_0F99
) },
8496 { REG_TABLE (REG_VEX_0FAE
) },
8519 { PREFIX_TABLE (PREFIX_VEX_0FC2
) },
8521 { PREFIX_TABLE (PREFIX_VEX_0FC4
) },
8522 { PREFIX_TABLE (PREFIX_VEX_0FC5
) },
8523 { "vshufpX", { XM
, Vex
, EXx
, Ib
}, PREFIX_OPCODE
},
8535 { PREFIX_TABLE (PREFIX_VEX_0FD0
) },
8536 { PREFIX_TABLE (PREFIX_VEX_0FD1
) },
8537 { PREFIX_TABLE (PREFIX_VEX_0FD2
) },
8538 { PREFIX_TABLE (PREFIX_VEX_0FD3
) },
8539 { PREFIX_TABLE (PREFIX_VEX_0FD4
) },
8540 { PREFIX_TABLE (PREFIX_VEX_0FD5
) },
8541 { PREFIX_TABLE (PREFIX_VEX_0FD6
) },
8542 { PREFIX_TABLE (PREFIX_VEX_0FD7
) },
8544 { PREFIX_TABLE (PREFIX_VEX_0FD8
) },
8545 { PREFIX_TABLE (PREFIX_VEX_0FD9
) },
8546 { PREFIX_TABLE (PREFIX_VEX_0FDA
) },
8547 { PREFIX_TABLE (PREFIX_VEX_0FDB
) },
8548 { PREFIX_TABLE (PREFIX_VEX_0FDC
) },
8549 { PREFIX_TABLE (PREFIX_VEX_0FDD
) },
8550 { PREFIX_TABLE (PREFIX_VEX_0FDE
) },
8551 { PREFIX_TABLE (PREFIX_VEX_0FDF
) },
8553 { PREFIX_TABLE (PREFIX_VEX_0FE0
) },
8554 { PREFIX_TABLE (PREFIX_VEX_0FE1
) },
8555 { PREFIX_TABLE (PREFIX_VEX_0FE2
) },
8556 { PREFIX_TABLE (PREFIX_VEX_0FE3
) },
8557 { PREFIX_TABLE (PREFIX_VEX_0FE4
) },
8558 { PREFIX_TABLE (PREFIX_VEX_0FE5
) },
8559 { PREFIX_TABLE (PREFIX_VEX_0FE6
) },
8560 { PREFIX_TABLE (PREFIX_VEX_0FE7
) },
8562 { PREFIX_TABLE (PREFIX_VEX_0FE8
) },
8563 { PREFIX_TABLE (PREFIX_VEX_0FE9
) },
8564 { PREFIX_TABLE (PREFIX_VEX_0FEA
) },
8565 { PREFIX_TABLE (PREFIX_VEX_0FEB
) },
8566 { PREFIX_TABLE (PREFIX_VEX_0FEC
) },
8567 { PREFIX_TABLE (PREFIX_VEX_0FED
) },
8568 { PREFIX_TABLE (PREFIX_VEX_0FEE
) },
8569 { PREFIX_TABLE (PREFIX_VEX_0FEF
) },
8571 { PREFIX_TABLE (PREFIX_VEX_0FF0
) },
8572 { PREFIX_TABLE (PREFIX_VEX_0FF1
) },
8573 { PREFIX_TABLE (PREFIX_VEX_0FF2
) },
8574 { PREFIX_TABLE (PREFIX_VEX_0FF3
) },
8575 { PREFIX_TABLE (PREFIX_VEX_0FF4
) },
8576 { PREFIX_TABLE (PREFIX_VEX_0FF5
) },
8577 { PREFIX_TABLE (PREFIX_VEX_0FF6
) },
8578 { PREFIX_TABLE (PREFIX_VEX_0FF7
) },
8580 { PREFIX_TABLE (PREFIX_VEX_0FF8
) },
8581 { PREFIX_TABLE (PREFIX_VEX_0FF9
) },
8582 { PREFIX_TABLE (PREFIX_VEX_0FFA
) },
8583 { PREFIX_TABLE (PREFIX_VEX_0FFB
) },
8584 { PREFIX_TABLE (PREFIX_VEX_0FFC
) },
8585 { PREFIX_TABLE (PREFIX_VEX_0FFD
) },
8586 { PREFIX_TABLE (PREFIX_VEX_0FFE
) },
8592 { PREFIX_TABLE (PREFIX_VEX_0F3800
) },
8593 { PREFIX_TABLE (PREFIX_VEX_0F3801
) },
8594 { PREFIX_TABLE (PREFIX_VEX_0F3802
) },
8595 { PREFIX_TABLE (PREFIX_VEX_0F3803
) },
8596 { PREFIX_TABLE (PREFIX_VEX_0F3804
) },
8597 { PREFIX_TABLE (PREFIX_VEX_0F3805
) },
8598 { PREFIX_TABLE (PREFIX_VEX_0F3806
) },
8599 { PREFIX_TABLE (PREFIX_VEX_0F3807
) },
8601 { PREFIX_TABLE (PREFIX_VEX_0F3808
) },
8602 { PREFIX_TABLE (PREFIX_VEX_0F3809
) },
8603 { PREFIX_TABLE (PREFIX_VEX_0F380A
) },
8604 { PREFIX_TABLE (PREFIX_VEX_0F380B
) },
8605 { PREFIX_TABLE (PREFIX_VEX_0F380C
) },
8606 { PREFIX_TABLE (PREFIX_VEX_0F380D
) },
8607 { PREFIX_TABLE (PREFIX_VEX_0F380E
) },
8608 { PREFIX_TABLE (PREFIX_VEX_0F380F
) },
8613 { PREFIX_TABLE (PREFIX_VEX_0F3813
) },
8616 { PREFIX_TABLE (PREFIX_VEX_0F3816
) },
8617 { PREFIX_TABLE (PREFIX_VEX_0F3817
) },
8619 { PREFIX_TABLE (PREFIX_VEX_0F3818
) },
8620 { PREFIX_TABLE (PREFIX_VEX_0F3819
) },
8621 { PREFIX_TABLE (PREFIX_VEX_0F381A
) },
8623 { PREFIX_TABLE (PREFIX_VEX_0F381C
) },
8624 { PREFIX_TABLE (PREFIX_VEX_0F381D
) },
8625 { PREFIX_TABLE (PREFIX_VEX_0F381E
) },
8628 { PREFIX_TABLE (PREFIX_VEX_0F3820
) },
8629 { PREFIX_TABLE (PREFIX_VEX_0F3821
) },
8630 { PREFIX_TABLE (PREFIX_VEX_0F3822
) },
8631 { PREFIX_TABLE (PREFIX_VEX_0F3823
) },
8632 { PREFIX_TABLE (PREFIX_VEX_0F3824
) },
8633 { PREFIX_TABLE (PREFIX_VEX_0F3825
) },
8637 { PREFIX_TABLE (PREFIX_VEX_0F3828
) },
8638 { PREFIX_TABLE (PREFIX_VEX_0F3829
) },
8639 { PREFIX_TABLE (PREFIX_VEX_0F382A
) },
8640 { PREFIX_TABLE (PREFIX_VEX_0F382B
) },
8641 { PREFIX_TABLE (PREFIX_VEX_0F382C
) },
8642 { PREFIX_TABLE (PREFIX_VEX_0F382D
) },
8643 { PREFIX_TABLE (PREFIX_VEX_0F382E
) },
8644 { PREFIX_TABLE (PREFIX_VEX_0F382F
) },
8646 { PREFIX_TABLE (PREFIX_VEX_0F3830
) },
8647 { PREFIX_TABLE (PREFIX_VEX_0F3831
) },
8648 { PREFIX_TABLE (PREFIX_VEX_0F3832
) },
8649 { PREFIX_TABLE (PREFIX_VEX_0F3833
) },
8650 { PREFIX_TABLE (PREFIX_VEX_0F3834
) },
8651 { PREFIX_TABLE (PREFIX_VEX_0F3835
) },
8652 { PREFIX_TABLE (PREFIX_VEX_0F3836
) },
8653 { PREFIX_TABLE (PREFIX_VEX_0F3837
) },
8655 { PREFIX_TABLE (PREFIX_VEX_0F3838
) },
8656 { PREFIX_TABLE (PREFIX_VEX_0F3839
) },
8657 { PREFIX_TABLE (PREFIX_VEX_0F383A
) },
8658 { PREFIX_TABLE (PREFIX_VEX_0F383B
) },
8659 { PREFIX_TABLE (PREFIX_VEX_0F383C
) },
8660 { PREFIX_TABLE (PREFIX_VEX_0F383D
) },
8661 { PREFIX_TABLE (PREFIX_VEX_0F383E
) },
8662 { PREFIX_TABLE (PREFIX_VEX_0F383F
) },
8664 { PREFIX_TABLE (PREFIX_VEX_0F3840
) },
8665 { PREFIX_TABLE (PREFIX_VEX_0F3841
) },
8669 { PREFIX_TABLE (PREFIX_VEX_0F3845
) },
8670 { PREFIX_TABLE (PREFIX_VEX_0F3846
) },
8671 { PREFIX_TABLE (PREFIX_VEX_0F3847
) },
8691 { PREFIX_TABLE (PREFIX_VEX_0F3858
) },
8692 { PREFIX_TABLE (PREFIX_VEX_0F3859
) },
8693 { PREFIX_TABLE (PREFIX_VEX_0F385A
) },
8727 { PREFIX_TABLE (PREFIX_VEX_0F3878
) },
8728 { PREFIX_TABLE (PREFIX_VEX_0F3879
) },
8749 { PREFIX_TABLE (PREFIX_VEX_0F388C
) },
8751 { PREFIX_TABLE (PREFIX_VEX_0F388E
) },
8754 { PREFIX_TABLE (PREFIX_VEX_0F3890
) },
8755 { PREFIX_TABLE (PREFIX_VEX_0F3891
) },
8756 { PREFIX_TABLE (PREFIX_VEX_0F3892
) },
8757 { PREFIX_TABLE (PREFIX_VEX_0F3893
) },
8760 { PREFIX_TABLE (PREFIX_VEX_0F3896
) },
8761 { PREFIX_TABLE (PREFIX_VEX_0F3897
) },
8763 { PREFIX_TABLE (PREFIX_VEX_0F3898
) },
8764 { PREFIX_TABLE (PREFIX_VEX_0F3899
) },
8765 { PREFIX_TABLE (PREFIX_VEX_0F389A
) },
8766 { PREFIX_TABLE (PREFIX_VEX_0F389B
) },
8767 { PREFIX_TABLE (PREFIX_VEX_0F389C
) },
8768 { PREFIX_TABLE (PREFIX_VEX_0F389D
) },
8769 { PREFIX_TABLE (PREFIX_VEX_0F389E
) },
8770 { PREFIX_TABLE (PREFIX_VEX_0F389F
) },
8778 { PREFIX_TABLE (PREFIX_VEX_0F38A6
) },
8779 { PREFIX_TABLE (PREFIX_VEX_0F38A7
) },
8781 { PREFIX_TABLE (PREFIX_VEX_0F38A8
) },
8782 { PREFIX_TABLE (PREFIX_VEX_0F38A9
) },
8783 { PREFIX_TABLE (PREFIX_VEX_0F38AA
) },
8784 { PREFIX_TABLE (PREFIX_VEX_0F38AB
) },
8785 { PREFIX_TABLE (PREFIX_VEX_0F38AC
) },
8786 { PREFIX_TABLE (PREFIX_VEX_0F38AD
) },
8787 { PREFIX_TABLE (PREFIX_VEX_0F38AE
) },
8788 { PREFIX_TABLE (PREFIX_VEX_0F38AF
) },
8796 { PREFIX_TABLE (PREFIX_VEX_0F38B6
) },
8797 { PREFIX_TABLE (PREFIX_VEX_0F38B7
) },
8799 { PREFIX_TABLE (PREFIX_VEX_0F38B8
) },
8800 { PREFIX_TABLE (PREFIX_VEX_0F38B9
) },
8801 { PREFIX_TABLE (PREFIX_VEX_0F38BA
) },
8802 { PREFIX_TABLE (PREFIX_VEX_0F38BB
) },
8803 { PREFIX_TABLE (PREFIX_VEX_0F38BC
) },
8804 { PREFIX_TABLE (PREFIX_VEX_0F38BD
) },
8805 { PREFIX_TABLE (PREFIX_VEX_0F38BE
) },
8806 { PREFIX_TABLE (PREFIX_VEX_0F38BF
) },
8824 { PREFIX_TABLE (PREFIX_VEX_0F38CF
) },
8838 { PREFIX_TABLE (PREFIX_VEX_0F38DB
) },
8839 { PREFIX_TABLE (PREFIX_VEX_0F38DC
) },
8840 { PREFIX_TABLE (PREFIX_VEX_0F38DD
) },
8841 { PREFIX_TABLE (PREFIX_VEX_0F38DE
) },
8842 { PREFIX_TABLE (PREFIX_VEX_0F38DF
) },
8864 { PREFIX_TABLE (PREFIX_VEX_0F38F2
) },
8865 { REG_TABLE (REG_VEX_0F38F3
) },
8867 { PREFIX_TABLE (PREFIX_VEX_0F38F5
) },
8868 { PREFIX_TABLE (PREFIX_VEX_0F38F6
) },
8869 { PREFIX_TABLE (PREFIX_VEX_0F38F7
) },
8883 { PREFIX_TABLE (PREFIX_VEX_0F3A00
) },
8884 { PREFIX_TABLE (PREFIX_VEX_0F3A01
) },
8885 { PREFIX_TABLE (PREFIX_VEX_0F3A02
) },
8887 { PREFIX_TABLE (PREFIX_VEX_0F3A04
) },
8888 { PREFIX_TABLE (PREFIX_VEX_0F3A05
) },
8889 { PREFIX_TABLE (PREFIX_VEX_0F3A06
) },
8892 { PREFIX_TABLE (PREFIX_VEX_0F3A08
) },
8893 { PREFIX_TABLE (PREFIX_VEX_0F3A09
) },
8894 { PREFIX_TABLE (PREFIX_VEX_0F3A0A
) },
8895 { PREFIX_TABLE (PREFIX_VEX_0F3A0B
) },
8896 { PREFIX_TABLE (PREFIX_VEX_0F3A0C
) },
8897 { PREFIX_TABLE (PREFIX_VEX_0F3A0D
) },
8898 { PREFIX_TABLE (PREFIX_VEX_0F3A0E
) },
8899 { PREFIX_TABLE (PREFIX_VEX_0F3A0F
) },
8905 { PREFIX_TABLE (PREFIX_VEX_0F3A14
) },
8906 { PREFIX_TABLE (PREFIX_VEX_0F3A15
) },
8907 { PREFIX_TABLE (PREFIX_VEX_0F3A16
) },
8908 { PREFIX_TABLE (PREFIX_VEX_0F3A17
) },
8910 { PREFIX_TABLE (PREFIX_VEX_0F3A18
) },
8911 { PREFIX_TABLE (PREFIX_VEX_0F3A19
) },
8915 { PREFIX_TABLE (PREFIX_VEX_0F3A1D
) },
8919 { PREFIX_TABLE (PREFIX_VEX_0F3A20
) },
8920 { PREFIX_TABLE (PREFIX_VEX_0F3A21
) },
8921 { PREFIX_TABLE (PREFIX_VEX_0F3A22
) },
8937 { PREFIX_TABLE (PREFIX_VEX_0F3A30
) },
8938 { PREFIX_TABLE (PREFIX_VEX_0F3A31
) },
8939 { PREFIX_TABLE (PREFIX_VEX_0F3A32
) },
8940 { PREFIX_TABLE (PREFIX_VEX_0F3A33
) },
8946 { PREFIX_TABLE (PREFIX_VEX_0F3A38
) },
8947 { PREFIX_TABLE (PREFIX_VEX_0F3A39
) },
8955 { PREFIX_TABLE (PREFIX_VEX_0F3A40
) },
8956 { PREFIX_TABLE (PREFIX_VEX_0F3A41
) },
8957 { PREFIX_TABLE (PREFIX_VEX_0F3A42
) },
8959 { PREFIX_TABLE (PREFIX_VEX_0F3A44
) },
8961 { PREFIX_TABLE (PREFIX_VEX_0F3A46
) },
8964 { PREFIX_TABLE (PREFIX_VEX_0F3A48
) },
8965 { PREFIX_TABLE (PREFIX_VEX_0F3A49
) },
8966 { PREFIX_TABLE (PREFIX_VEX_0F3A4A
) },
8967 { PREFIX_TABLE (PREFIX_VEX_0F3A4B
) },
8968 { PREFIX_TABLE (PREFIX_VEX_0F3A4C
) },
8986 { PREFIX_TABLE (PREFIX_VEX_0F3A5C
) },
8987 { PREFIX_TABLE (PREFIX_VEX_0F3A5D
) },
8988 { PREFIX_TABLE (PREFIX_VEX_0F3A5E
) },
8989 { PREFIX_TABLE (PREFIX_VEX_0F3A5F
) },
8991 { PREFIX_TABLE (PREFIX_VEX_0F3A60
) },
8992 { PREFIX_TABLE (PREFIX_VEX_0F3A61
) },
8993 { PREFIX_TABLE (PREFIX_VEX_0F3A62
) },
8994 { PREFIX_TABLE (PREFIX_VEX_0F3A63
) },
9000 { PREFIX_TABLE (PREFIX_VEX_0F3A68
) },
9001 { PREFIX_TABLE (PREFIX_VEX_0F3A69
) },
9002 { PREFIX_TABLE (PREFIX_VEX_0F3A6A
) },
9003 { PREFIX_TABLE (PREFIX_VEX_0F3A6B
) },
9004 { PREFIX_TABLE (PREFIX_VEX_0F3A6C
) },
9005 { PREFIX_TABLE (PREFIX_VEX_0F3A6D
) },
9006 { PREFIX_TABLE (PREFIX_VEX_0F3A6E
) },
9007 { PREFIX_TABLE (PREFIX_VEX_0F3A6F
) },
9018 { PREFIX_TABLE (PREFIX_VEX_0F3A78
) },
9019 { PREFIX_TABLE (PREFIX_VEX_0F3A79
) },
9020 { PREFIX_TABLE (PREFIX_VEX_0F3A7A
) },
9021 { PREFIX_TABLE (PREFIX_VEX_0F3A7B
) },
9022 { PREFIX_TABLE (PREFIX_VEX_0F3A7C
) },
9023 { PREFIX_TABLE (PREFIX_VEX_0F3A7D
) },
9024 { PREFIX_TABLE (PREFIX_VEX_0F3A7E
) },
9025 { PREFIX_TABLE (PREFIX_VEX_0F3A7F
) },
9114 { PREFIX_TABLE(PREFIX_VEX_0F3ACE
) },
9115 { PREFIX_TABLE(PREFIX_VEX_0F3ACF
) },
9133 { PREFIX_TABLE (PREFIX_VEX_0F3ADF
) },
9153 { PREFIX_TABLE (PREFIX_VEX_0F3AF0
) },
9173 #include "i386-dis-evex.h"
9175 static const struct dis386 vex_len_table
[][2] = {
9176 /* VEX_LEN_0F12_P_0_M_0 / VEX_LEN_0F12_P_2_M_0 */
9178 { "vmovlpX", { XM
, Vex128
, EXq
}, 0 },
9181 /* VEX_LEN_0F12_P_0_M_1 */
9183 { "vmovhlps", { XM
, Vex128
, EXq
}, 0 },
9186 /* VEX_LEN_0F13_M_0 */
9188 { "vmovlpX", { EXq
, XM
}, PREFIX_OPCODE
},
9191 /* VEX_LEN_0F16_P_0_M_0 / VEX_LEN_0F16_P_2_M_0 */
9193 { "vmovhpX", { XM
, Vex128
, EXq
}, 0 },
9196 /* VEX_LEN_0F16_P_0_M_1 */
9198 { "vmovlhps", { XM
, Vex128
, EXq
}, 0 },
9201 /* VEX_LEN_0F17_M_0 */
9203 { "vmovhpX", { EXq
, XM
}, PREFIX_OPCODE
},
9206 /* VEX_LEN_0F41_P_0 */
9209 { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1
) },
9211 /* VEX_LEN_0F41_P_2 */
9214 { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1
) },
9216 /* VEX_LEN_0F42_P_0 */
9219 { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1
) },
9221 /* VEX_LEN_0F42_P_2 */
9224 { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1
) },
9226 /* VEX_LEN_0F44_P_0 */
9228 { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0
) },
9230 /* VEX_LEN_0F44_P_2 */
9232 { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0
) },
9234 /* VEX_LEN_0F45_P_0 */
9237 { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1
) },
9239 /* VEX_LEN_0F45_P_2 */
9242 { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1
) },
9244 /* VEX_LEN_0F46_P_0 */
9247 { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1
) },
9249 /* VEX_LEN_0F46_P_2 */
9252 { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1
) },
9254 /* VEX_LEN_0F47_P_0 */
9257 { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1
) },
9259 /* VEX_LEN_0F47_P_2 */
9262 { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1
) },
9264 /* VEX_LEN_0F4A_P_0 */
9267 { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1
) },
9269 /* VEX_LEN_0F4A_P_2 */
9272 { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1
) },
9274 /* VEX_LEN_0F4B_P_0 */
9277 { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1
) },
9279 /* VEX_LEN_0F4B_P_2 */
9282 { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1
) },
9285 /* VEX_LEN_0F6E_P_2 */
9287 { "vmovK", { XMScalar
, Edq
}, 0 },
9290 /* VEX_LEN_0F77_P_1 */
9292 { "vzeroupper", { XX
}, 0 },
9293 { "vzeroall", { XX
}, 0 },
9296 /* VEX_LEN_0F7E_P_1 */
9298 { "vmovq", { XMScalar
, EXxmm_mq
}, 0 },
9301 /* VEX_LEN_0F7E_P_2 */
9303 { "vmovK", { Edq
, XMScalar
}, 0 },
9306 /* VEX_LEN_0F90_P_0 */
9308 { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0
) },
9311 /* VEX_LEN_0F90_P_2 */
9313 { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0
) },
9316 /* VEX_LEN_0F91_P_0 */
9318 { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0
) },
9321 /* VEX_LEN_0F91_P_2 */
9323 { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0
) },
9326 /* VEX_LEN_0F92_P_0 */
9328 { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0
) },
9331 /* VEX_LEN_0F92_P_2 */
9333 { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0
) },
9336 /* VEX_LEN_0F92_P_3 */
9338 { MOD_TABLE (MOD_VEX_0F92_P_3_LEN_0
) },
9341 /* VEX_LEN_0F93_P_0 */
9343 { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0
) },
9346 /* VEX_LEN_0F93_P_2 */
9348 { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0
) },
9351 /* VEX_LEN_0F93_P_3 */
9353 { MOD_TABLE (MOD_VEX_0F93_P_3_LEN_0
) },
9356 /* VEX_LEN_0F98_P_0 */
9358 { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0
) },
9361 /* VEX_LEN_0F98_P_2 */
9363 { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0
) },
9366 /* VEX_LEN_0F99_P_0 */
9368 { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0
) },
9371 /* VEX_LEN_0F99_P_2 */
9373 { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0
) },
9376 /* VEX_LEN_0FAE_R_2_M_0 */
9378 { "vldmxcsr", { Md
}, 0 },
9381 /* VEX_LEN_0FAE_R_3_M_0 */
9383 { "vstmxcsr", { Md
}, 0 },
9386 /* VEX_LEN_0FC4_P_2 */
9388 { "vpinsrw", { XM
, Vex128
, Edqw
, Ib
}, 0 },
9391 /* VEX_LEN_0FC5_P_2 */
9393 { "vpextrw", { Gdq
, XS
, Ib
}, 0 },
9396 /* VEX_LEN_0FD6_P_2 */
9398 { "vmovq", { EXqVexScalarS
, XMScalar
}, 0 },
9401 /* VEX_LEN_0FF7_P_2 */
9403 { "vmaskmovdqu", { XM
, XS
}, 0 },
9406 /* VEX_LEN_0F3816_P_2 */
9409 { VEX_W_TABLE (VEX_W_0F3816_P_2
) },
9412 /* VEX_LEN_0F3819_P_2 */
9415 { VEX_W_TABLE (VEX_W_0F3819_P_2
) },
9418 /* VEX_LEN_0F381A_P_2_M_0 */
9421 { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0
) },
9424 /* VEX_LEN_0F3836_P_2 */
9427 { VEX_W_TABLE (VEX_W_0F3836_P_2
) },
9430 /* VEX_LEN_0F3841_P_2 */
9432 { "vphminposuw", { XM
, EXx
}, 0 },
9435 /* VEX_LEN_0F385A_P_2_M_0 */
9438 { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0
) },
9441 /* VEX_LEN_0F38DB_P_2 */
9443 { "vaesimc", { XM
, EXx
}, 0 },
9446 /* VEX_LEN_0F38F2_P_0 */
9448 { "andnS", { Gdq
, VexGdq
, Edq
}, 0 },
9451 /* VEX_LEN_0F38F3_R_1_P_0 */
9453 { "blsrS", { VexGdq
, Edq
}, 0 },
9456 /* VEX_LEN_0F38F3_R_2_P_0 */
9458 { "blsmskS", { VexGdq
, Edq
}, 0 },
9461 /* VEX_LEN_0F38F3_R_3_P_0 */
9463 { "blsiS", { VexGdq
, Edq
}, 0 },
9466 /* VEX_LEN_0F38F5_P_0 */
9468 { "bzhiS", { Gdq
, Edq
, VexGdq
}, 0 },
9471 /* VEX_LEN_0F38F5_P_1 */
9473 { "pextS", { Gdq
, VexGdq
, Edq
}, 0 },
9476 /* VEX_LEN_0F38F5_P_3 */
9478 { "pdepS", { Gdq
, VexGdq
, Edq
}, 0 },
9481 /* VEX_LEN_0F38F6_P_3 */
9483 { "mulxS", { Gdq
, VexGdq
, Edq
}, 0 },
9486 /* VEX_LEN_0F38F7_P_0 */
9488 { "bextrS", { Gdq
, Edq
, VexGdq
}, 0 },
9491 /* VEX_LEN_0F38F7_P_1 */
9493 { "sarxS", { Gdq
, Edq
, VexGdq
}, 0 },
9496 /* VEX_LEN_0F38F7_P_2 */
9498 { "shlxS", { Gdq
, Edq
, VexGdq
}, 0 },
9501 /* VEX_LEN_0F38F7_P_3 */
9503 { "shrxS", { Gdq
, Edq
, VexGdq
}, 0 },
9506 /* VEX_LEN_0F3A00_P_2 */
9509 { VEX_W_TABLE (VEX_W_0F3A00_P_2
) },
9512 /* VEX_LEN_0F3A01_P_2 */
9515 { VEX_W_TABLE (VEX_W_0F3A01_P_2
) },
9518 /* VEX_LEN_0F3A06_P_2 */
9521 { VEX_W_TABLE (VEX_W_0F3A06_P_2
) },
9524 /* VEX_LEN_0F3A14_P_2 */
9526 { "vpextrb", { Edqb
, XM
, Ib
}, 0 },
9529 /* VEX_LEN_0F3A15_P_2 */
9531 { "vpextrw", { Edqw
, XM
, Ib
}, 0 },
9534 /* VEX_LEN_0F3A16_P_2 */
9536 { "vpextrK", { Edq
, XM
, Ib
}, 0 },
9539 /* VEX_LEN_0F3A17_P_2 */
9541 { "vextractps", { Edqd
, XM
, Ib
}, 0 },
9544 /* VEX_LEN_0F3A18_P_2 */
9547 { VEX_W_TABLE (VEX_W_0F3A18_P_2
) },
9550 /* VEX_LEN_0F3A19_P_2 */
9553 { VEX_W_TABLE (VEX_W_0F3A19_P_2
) },
9556 /* VEX_LEN_0F3A20_P_2 */
9558 { "vpinsrb", { XM
, Vex128
, Edqb
, Ib
}, 0 },
9561 /* VEX_LEN_0F3A21_P_2 */
9563 { "vinsertps", { XM
, Vex128
, EXd
, Ib
}, 0 },
9566 /* VEX_LEN_0F3A22_P_2 */
9568 { "vpinsrK", { XM
, Vex128
, Edq
, Ib
}, 0 },
9571 /* VEX_LEN_0F3A30_P_2 */
9573 { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0
) },
9576 /* VEX_LEN_0F3A31_P_2 */
9578 { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0
) },
9581 /* VEX_LEN_0F3A32_P_2 */
9583 { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0
) },
9586 /* VEX_LEN_0F3A33_P_2 */
9588 { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0
) },
9591 /* VEX_LEN_0F3A38_P_2 */
9594 { VEX_W_TABLE (VEX_W_0F3A38_P_2
) },
9597 /* VEX_LEN_0F3A39_P_2 */
9600 { VEX_W_TABLE (VEX_W_0F3A39_P_2
) },
9603 /* VEX_LEN_0F3A41_P_2 */
9605 { "vdppd", { XM
, Vex128
, EXx
, Ib
}, 0 },
9608 /* VEX_LEN_0F3A46_P_2 */
9611 { VEX_W_TABLE (VEX_W_0F3A46_P_2
) },
9614 /* VEX_LEN_0F3A60_P_2 */
9616 { "vpcmpestrm", { XM
, { PCMPESTR_Fixup
, x_mode
}, Ib
}, 0 },
9619 /* VEX_LEN_0F3A61_P_2 */
9621 { "vpcmpestri", { XM
, { PCMPESTR_Fixup
, x_mode
}, Ib
}, 0 },
9624 /* VEX_LEN_0F3A62_P_2 */
9626 { "vpcmpistrm", { XM
, EXx
, Ib
}, 0 },
9629 /* VEX_LEN_0F3A63_P_2 */
9631 { "vpcmpistri", { XM
, EXx
, Ib
}, 0 },
9634 /* VEX_LEN_0F3A6A_P_2 */
9636 { "vfmaddss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
}, 0 },
9639 /* VEX_LEN_0F3A6B_P_2 */
9641 { "vfmaddsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
}, 0 },
9644 /* VEX_LEN_0F3A6E_P_2 */
9646 { "vfmsubss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
}, 0 },
9649 /* VEX_LEN_0F3A6F_P_2 */
9651 { "vfmsubsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
}, 0 },
9654 /* VEX_LEN_0F3A7A_P_2 */
9656 { "vfnmaddss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
}, 0 },
9659 /* VEX_LEN_0F3A7B_P_2 */
9661 { "vfnmaddsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
}, 0 },
9664 /* VEX_LEN_0F3A7E_P_2 */
9666 { "vfnmsubss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
}, 0 },
9669 /* VEX_LEN_0F3A7F_P_2 */
9671 { "vfnmsubsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
}, 0 },
9674 /* VEX_LEN_0F3ADF_P_2 */
9676 { "vaeskeygenassist", { XM
, EXx
, Ib
}, 0 },
9679 /* VEX_LEN_0F3AF0_P_3 */
9681 { "rorxS", { Gdq
, Edq
, Ib
}, 0 },
9684 /* VEX_LEN_0FXOP_08_CC */
9686 { "vpcomb", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9689 /* VEX_LEN_0FXOP_08_CD */
9691 { "vpcomw", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9694 /* VEX_LEN_0FXOP_08_CE */
9696 { "vpcomd", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9699 /* VEX_LEN_0FXOP_08_CF */
9701 { "vpcomq", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9704 /* VEX_LEN_0FXOP_08_EC */
9706 { "vpcomub", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9709 /* VEX_LEN_0FXOP_08_ED */
9711 { "vpcomuw", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9714 /* VEX_LEN_0FXOP_08_EE */
9716 { "vpcomud", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9719 /* VEX_LEN_0FXOP_08_EF */
9721 { "vpcomuq", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9724 /* VEX_LEN_0FXOP_09_82_W_0 */
9726 { "vfrczss", { XM
, EXd
}, 0 },
9729 /* VEX_LEN_0FXOP_09_83_W_0 */
9731 { "vfrczsd", { XM
, EXq
}, 0 },
9735 #include "i386-dis-evex-len.h"
9737 static const struct dis386 vex_w_table
[][2] = {
9739 /* VEX_W_0F41_P_0_LEN_1 */
9740 { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1
) },
9741 { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1
) },
9744 /* VEX_W_0F41_P_2_LEN_1 */
9745 { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1
) },
9746 { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1
) }
9749 /* VEX_W_0F42_P_0_LEN_1 */
9750 { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1
) },
9751 { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1
) },
9754 /* VEX_W_0F42_P_2_LEN_1 */
9755 { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1
) },
9756 { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1
) },
9759 /* VEX_W_0F44_P_0_LEN_0 */
9760 { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1
) },
9761 { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1
) },
9764 /* VEX_W_0F44_P_2_LEN_0 */
9765 { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1
) },
9766 { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1
) },
9769 /* VEX_W_0F45_P_0_LEN_1 */
9770 { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1
) },
9771 { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1
) },
9774 /* VEX_W_0F45_P_2_LEN_1 */
9775 { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1
) },
9776 { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1
) },
9779 /* VEX_W_0F46_P_0_LEN_1 */
9780 { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1
) },
9781 { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1
) },
9784 /* VEX_W_0F46_P_2_LEN_1 */
9785 { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1
) },
9786 { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1
) },
9789 /* VEX_W_0F47_P_0_LEN_1 */
9790 { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1
) },
9791 { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1
) },
9794 /* VEX_W_0F47_P_2_LEN_1 */
9795 { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1
) },
9796 { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1
) },
9799 /* VEX_W_0F4A_P_0_LEN_1 */
9800 { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1
) },
9801 { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1
) },
9804 /* VEX_W_0F4A_P_2_LEN_1 */
9805 { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1
) },
9806 { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1
) },
9809 /* VEX_W_0F4B_P_0_LEN_1 */
9810 { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1
) },
9811 { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1
) },
9814 /* VEX_W_0F4B_P_2_LEN_1 */
9815 { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1
) },
9818 /* VEX_W_0F90_P_0_LEN_0 */
9819 { "kmovw", { MaskG
, MaskE
}, 0 },
9820 { "kmovq", { MaskG
, MaskE
}, 0 },
9823 /* VEX_W_0F90_P_2_LEN_0 */
9824 { "kmovb", { MaskG
, MaskBDE
}, 0 },
9825 { "kmovd", { MaskG
, MaskBDE
}, 0 },
9828 /* VEX_W_0F91_P_0_LEN_0 */
9829 { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0
) },
9830 { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0
) },
9833 /* VEX_W_0F91_P_2_LEN_0 */
9834 { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0
) },
9835 { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0
) },
9838 /* VEX_W_0F92_P_0_LEN_0 */
9839 { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0
) },
9842 /* VEX_W_0F92_P_2_LEN_0 */
9843 { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0
) },
9846 /* VEX_W_0F93_P_0_LEN_0 */
9847 { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0
) },
9850 /* VEX_W_0F93_P_2_LEN_0 */
9851 { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0
) },
9854 /* VEX_W_0F98_P_0_LEN_0 */
9855 { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0
) },
9856 { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0
) },
9859 /* VEX_W_0F98_P_2_LEN_0 */
9860 { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0
) },
9861 { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0
) },
9864 /* VEX_W_0F99_P_0_LEN_0 */
9865 { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0
) },
9866 { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0
) },
9869 /* VEX_W_0F99_P_2_LEN_0 */
9870 { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0
) },
9871 { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0
) },
9874 /* VEX_W_0F380C_P_2 */
9875 { "vpermilps", { XM
, Vex
, EXx
}, 0 },
9878 /* VEX_W_0F380D_P_2 */
9879 { "vpermilpd", { XM
, Vex
, EXx
}, 0 },
9882 /* VEX_W_0F380E_P_2 */
9883 { "vtestps", { XM
, EXx
}, 0 },
9886 /* VEX_W_0F380F_P_2 */
9887 { "vtestpd", { XM
, EXx
}, 0 },
9890 /* VEX_W_0F3813_P_2 */
9891 { "vcvtph2ps", { XM
, EXxmmq
}, 0 },
9894 /* VEX_W_0F3816_P_2 */
9895 { "vpermps", { XM
, Vex
, EXx
}, 0 },
9898 /* VEX_W_0F3818_P_2 */
9899 { "vbroadcastss", { XM
, EXxmm_md
}, 0 },
9902 /* VEX_W_0F3819_P_2 */
9903 { "vbroadcastsd", { XM
, EXxmm_mq
}, 0 },
9906 /* VEX_W_0F381A_P_2_M_0 */
9907 { "vbroadcastf128", { XM
, Mxmm
}, 0 },
9910 /* VEX_W_0F382C_P_2_M_0 */
9911 { "vmaskmovps", { XM
, Vex
, Mx
}, 0 },
9914 /* VEX_W_0F382D_P_2_M_0 */
9915 { "vmaskmovpd", { XM
, Vex
, Mx
}, 0 },
9918 /* VEX_W_0F382E_P_2_M_0 */
9919 { "vmaskmovps", { Mx
, Vex
, XM
}, 0 },
9922 /* VEX_W_0F382F_P_2_M_0 */
9923 { "vmaskmovpd", { Mx
, Vex
, XM
}, 0 },
9926 /* VEX_W_0F3836_P_2 */
9927 { "vpermd", { XM
, Vex
, EXx
}, 0 },
9930 /* VEX_W_0F3846_P_2 */
9931 { "vpsravd", { XM
, Vex
, EXx
}, 0 },
9934 /* VEX_W_0F3858_P_2 */
9935 { "vpbroadcastd", { XM
, EXxmm_md
}, 0 },
9938 /* VEX_W_0F3859_P_2 */
9939 { "vpbroadcastq", { XM
, EXxmm_mq
}, 0 },
9942 /* VEX_W_0F385A_P_2_M_0 */
9943 { "vbroadcasti128", { XM
, Mxmm
}, 0 },
9946 /* VEX_W_0F3878_P_2 */
9947 { "vpbroadcastb", { XM
, EXxmm_mb
}, 0 },
9950 /* VEX_W_0F3879_P_2 */
9951 { "vpbroadcastw", { XM
, EXxmm_mw
}, 0 },
9954 /* VEX_W_0F38CF_P_2 */
9955 { "vgf2p8mulb", { XM
, Vex
, EXx
}, 0 },
9958 /* VEX_W_0F3A00_P_2 */
9960 { "vpermq", { XM
, EXx
, Ib
}, 0 },
9963 /* VEX_W_0F3A01_P_2 */
9965 { "vpermpd", { XM
, EXx
, Ib
}, 0 },
9968 /* VEX_W_0F3A02_P_2 */
9969 { "vpblendd", { XM
, Vex
, EXx
, Ib
}, 0 },
9972 /* VEX_W_0F3A04_P_2 */
9973 { "vpermilps", { XM
, EXx
, Ib
}, 0 },
9976 /* VEX_W_0F3A05_P_2 */
9977 { "vpermilpd", { XM
, EXx
, Ib
}, 0 },
9980 /* VEX_W_0F3A06_P_2 */
9981 { "vperm2f128", { XM
, Vex256
, EXx
, Ib
}, 0 },
9984 /* VEX_W_0F3A18_P_2 */
9985 { "vinsertf128", { XM
, Vex256
, EXxmm
, Ib
}, 0 },
9988 /* VEX_W_0F3A19_P_2 */
9989 { "vextractf128", { EXxmm
, XM
, Ib
}, 0 },
9992 /* VEX_W_0F3A1D_P_2 */
9993 { "vcvtps2ph", { EXxmmq
, XM
, EXxEVexS
, Ib
}, 0 },
9996 /* VEX_W_0F3A30_P_2_LEN_0 */
9997 { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0
) },
9998 { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0
) },
10001 /* VEX_W_0F3A31_P_2_LEN_0 */
10002 { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0
) },
10003 { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0
) },
10006 /* VEX_W_0F3A32_P_2_LEN_0 */
10007 { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0
) },
10008 { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0
) },
10011 /* VEX_W_0F3A33_P_2_LEN_0 */
10012 { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0
) },
10013 { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0
) },
10016 /* VEX_W_0F3A38_P_2 */
10017 { "vinserti128", { XM
, Vex256
, EXxmm
, Ib
}, 0 },
10020 /* VEX_W_0F3A39_P_2 */
10021 { "vextracti128", { EXxmm
, XM
, Ib
}, 0 },
10024 /* VEX_W_0F3A46_P_2 */
10025 { "vperm2i128", { XM
, Vex256
, EXx
, Ib
}, 0 },
10028 /* VEX_W_0F3A48_P_2 */
10029 { "vpermil2ps", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
}, 0 },
10030 { "vpermil2ps", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
}, 0 },
10033 /* VEX_W_0F3A49_P_2 */
10034 { "vpermil2pd", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
}, 0 },
10035 { "vpermil2pd", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
}, 0 },
10038 /* VEX_W_0F3A4A_P_2 */
10039 { "vblendvps", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
10042 /* VEX_W_0F3A4B_P_2 */
10043 { "vblendvpd", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
10046 /* VEX_W_0F3A4C_P_2 */
10047 { "vpblendvb", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
10050 /* VEX_W_0F3ACE_P_2 */
10052 { "vgf2p8affineqb", { XM
, Vex
, EXx
, Ib
}, 0 },
10055 /* VEX_W_0F3ACF_P_2 */
10057 { "vgf2p8affineinvqb", { XM
, Vex
, EXx
, Ib
}, 0 },
10059 /* VEX_W_0FXOP_09_80 */
10061 { "vfrczps", { XM
, EXx
}, 0 },
10063 /* VEX_W_0FXOP_09_81 */
10065 { "vfrczpd", { XM
, EXx
}, 0 },
10067 /* VEX_W_0FXOP_09_82 */
10069 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_82_W_0
) },
10071 /* VEX_W_0FXOP_09_83 */
10073 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_83_W_0
) },
10076 #include "i386-dis-evex-w.h"
10079 static const struct dis386 mod_table
[][2] = {
10082 { "leaS", { Gv
, M
}, 0 },
10087 { RM_TABLE (RM_C6_REG_7
) },
10092 { RM_TABLE (RM_C7_REG_7
) },
10096 { "{l|}call^", { indirEp
}, 0 },
10100 { "{l|}jmp^", { indirEp
}, 0 },
10103 /* MOD_0F01_REG_0 */
10104 { X86_64_TABLE (X86_64_0F01_REG_0
) },
10105 { RM_TABLE (RM_0F01_REG_0
) },
10108 /* MOD_0F01_REG_1 */
10109 { X86_64_TABLE (X86_64_0F01_REG_1
) },
10110 { RM_TABLE (RM_0F01_REG_1
) },
10113 /* MOD_0F01_REG_2 */
10114 { X86_64_TABLE (X86_64_0F01_REG_2
) },
10115 { RM_TABLE (RM_0F01_REG_2
) },
10118 /* MOD_0F01_REG_3 */
10119 { X86_64_TABLE (X86_64_0F01_REG_3
) },
10120 { RM_TABLE (RM_0F01_REG_3
) },
10123 /* MOD_0F01_REG_5 */
10124 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_0
) },
10125 { RM_TABLE (RM_0F01_REG_5_MOD_3
) },
10128 /* MOD_0F01_REG_7 */
10129 { "invlpg", { Mb
}, 0 },
10130 { RM_TABLE (RM_0F01_REG_7_MOD_3
) },
10133 /* MOD_0F12_PREFIX_0 */
10134 { "movlpX", { XM
, EXq
}, 0 },
10135 { "movhlps", { XM
, EXq
}, 0 },
10138 /* MOD_0F12_PREFIX_2 */
10139 { "movlpX", { XM
, EXq
}, 0 },
10143 { "movlpX", { EXq
, XM
}, PREFIX_OPCODE
},
10146 /* MOD_0F16_PREFIX_0 */
10147 { "movhpX", { XM
, EXq
}, 0 },
10148 { "movlhps", { XM
, EXq
}, 0 },
10151 /* MOD_0F16_PREFIX_2 */
10152 { "movhpX", { XM
, EXq
}, 0 },
10156 { "movhpX", { EXq
, XM
}, PREFIX_OPCODE
},
10159 /* MOD_0F18_REG_0 */
10160 { "prefetchnta", { Mb
}, 0 },
10163 /* MOD_0F18_REG_1 */
10164 { "prefetcht0", { Mb
}, 0 },
10167 /* MOD_0F18_REG_2 */
10168 { "prefetcht1", { Mb
}, 0 },
10171 /* MOD_0F18_REG_3 */
10172 { "prefetcht2", { Mb
}, 0 },
10175 /* MOD_0F18_REG_4 */
10176 { "nop/reserved", { Mb
}, 0 },
10179 /* MOD_0F18_REG_5 */
10180 { "nop/reserved", { Mb
}, 0 },
10183 /* MOD_0F18_REG_6 */
10184 { "nop/reserved", { Mb
}, 0 },
10187 /* MOD_0F18_REG_7 */
10188 { "nop/reserved", { Mb
}, 0 },
10191 /* MOD_0F1A_PREFIX_0 */
10192 { "bndldx", { Gbnd
, Mv_bnd
}, 0 },
10193 { "nopQ", { Ev
}, 0 },
10196 /* MOD_0F1B_PREFIX_0 */
10197 { "bndstx", { Mv_bnd
, Gbnd
}, 0 },
10198 { "nopQ", { Ev
}, 0 },
10201 /* MOD_0F1B_PREFIX_1 */
10202 { "bndmk", { Gbnd
, Mv_bnd
}, 0 },
10203 { "nopQ", { Ev
}, 0 },
10206 /* MOD_0F1C_PREFIX_0 */
10207 { REG_TABLE (REG_0F1C_P_0_MOD_0
) },
10208 { "nopQ", { Ev
}, 0 },
10211 /* MOD_0F1E_PREFIX_1 */
10212 { "nopQ", { Ev
}, 0 },
10213 { REG_TABLE (REG_0F1E_P_1_MOD_3
) },
10218 { "movL", { Rd
, Td
}, 0 },
10223 { "movL", { Td
, Rd
}, 0 },
10226 /* MOD_0F2B_PREFIX_0 */
10227 {"movntps", { Mx
, XM
}, PREFIX_OPCODE
},
10230 /* MOD_0F2B_PREFIX_1 */
10231 {"movntss", { Md
, XM
}, PREFIX_OPCODE
},
10234 /* MOD_0F2B_PREFIX_2 */
10235 {"movntpd", { Mx
, XM
}, PREFIX_OPCODE
},
10238 /* MOD_0F2B_PREFIX_3 */
10239 {"movntsd", { Mq
, XM
}, PREFIX_OPCODE
},
10244 { "movmskpX", { Gdq
, XS
}, PREFIX_OPCODE
},
10247 /* MOD_0F71_REG_2 */
10249 { "psrlw", { MS
, Ib
}, 0 },
10252 /* MOD_0F71_REG_4 */
10254 { "psraw", { MS
, Ib
}, 0 },
10257 /* MOD_0F71_REG_6 */
10259 { "psllw", { MS
, Ib
}, 0 },
10262 /* MOD_0F72_REG_2 */
10264 { "psrld", { MS
, Ib
}, 0 },
10267 /* MOD_0F72_REG_4 */
10269 { "psrad", { MS
, Ib
}, 0 },
10272 /* MOD_0F72_REG_6 */
10274 { "pslld", { MS
, Ib
}, 0 },
10277 /* MOD_0F73_REG_2 */
10279 { "psrlq", { MS
, Ib
}, 0 },
10282 /* MOD_0F73_REG_3 */
10284 { PREFIX_TABLE (PREFIX_0F73_REG_3
) },
10287 /* MOD_0F73_REG_6 */
10289 { "psllq", { MS
, Ib
}, 0 },
10292 /* MOD_0F73_REG_7 */
10294 { PREFIX_TABLE (PREFIX_0F73_REG_7
) },
10297 /* MOD_0FAE_REG_0 */
10298 { "fxsave", { FXSAVE
}, 0 },
10299 { PREFIX_TABLE (PREFIX_0FAE_REG_0_MOD_3
) },
10302 /* MOD_0FAE_REG_1 */
10303 { "fxrstor", { FXSAVE
}, 0 },
10304 { PREFIX_TABLE (PREFIX_0FAE_REG_1_MOD_3
) },
10307 /* MOD_0FAE_REG_2 */
10308 { "ldmxcsr", { Md
}, 0 },
10309 { PREFIX_TABLE (PREFIX_0FAE_REG_2_MOD_3
) },
10312 /* MOD_0FAE_REG_3 */
10313 { "stmxcsr", { Md
}, 0 },
10314 { PREFIX_TABLE (PREFIX_0FAE_REG_3_MOD_3
) },
10317 /* MOD_0FAE_REG_4 */
10318 { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_0
) },
10319 { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_3
) },
10322 /* MOD_0FAE_REG_5 */
10323 { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_0
) },
10324 { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_3
) },
10327 /* MOD_0FAE_REG_6 */
10328 { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_0
) },
10329 { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_3
) },
10332 /* MOD_0FAE_REG_7 */
10333 { PREFIX_TABLE (PREFIX_0FAE_REG_7_MOD_0
) },
10334 { RM_TABLE (RM_0FAE_REG_7_MOD_3
) },
10338 { "lssS", { Gv
, Mp
}, 0 },
10342 { "lfsS", { Gv
, Mp
}, 0 },
10346 { "lgsS", { Gv
, Mp
}, 0 },
10350 { PREFIX_TABLE (PREFIX_0FC3_MOD_0
) },
10353 /* MOD_0FC7_REG_3 */
10354 { "xrstors", { FXSAVE
}, 0 },
10357 /* MOD_0FC7_REG_4 */
10358 { "xsavec", { FXSAVE
}, 0 },
10361 /* MOD_0FC7_REG_5 */
10362 { "xsaves", { FXSAVE
}, 0 },
10365 /* MOD_0FC7_REG_6 */
10366 { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_0
) },
10367 { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_3
) }
10370 /* MOD_0FC7_REG_7 */
10371 { "vmptrst", { Mq
}, 0 },
10372 { PREFIX_TABLE (PREFIX_0FC7_REG_7_MOD_3
) }
10377 { "pmovmskb", { Gdq
, MS
}, 0 },
10380 /* MOD_0FE7_PREFIX_2 */
10381 { "movntdq", { Mx
, XM
}, 0 },
10384 /* MOD_0FF0_PREFIX_3 */
10385 { "lddqu", { XM
, M
}, 0 },
10388 /* MOD_0F382A_PREFIX_2 */
10389 { "movntdqa", { XM
, Mx
}, 0 },
10392 /* MOD_0F38F5_PREFIX_2 */
10393 { "wrussK", { M
, Gdq
}, PREFIX_OPCODE
},
10396 /* MOD_0F38F6_PREFIX_0 */
10397 { "wrssK", { M
, Gdq
}, PREFIX_OPCODE
},
10400 /* MOD_0F38F8_PREFIX_1 */
10401 { "enqcmds", { Gva
, M
}, PREFIX_OPCODE
},
10404 /* MOD_0F38F8_PREFIX_2 */
10405 { "movdir64b", { Gva
, M
}, PREFIX_OPCODE
},
10408 /* MOD_0F38F8_PREFIX_3 */
10409 { "enqcmd", { Gva
, M
}, PREFIX_OPCODE
},
10412 /* MOD_0F38F9_PREFIX_0 */
10413 { "movdiri", { Ev
, Gv
}, PREFIX_OPCODE
},
10417 { "bound{S|}", { Gv
, Ma
}, 0 },
10418 { EVEX_TABLE (EVEX_0F
) },
10422 { "lesS", { Gv
, Mp
}, 0 },
10423 { VEX_C4_TABLE (VEX_0F
) },
10427 { "ldsS", { Gv
, Mp
}, 0 },
10428 { VEX_C5_TABLE (VEX_0F
) },
10431 /* MOD_VEX_0F12_PREFIX_0 */
10432 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0
) },
10433 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1
) },
10436 /* MOD_VEX_0F12_PREFIX_2 */
10437 { VEX_LEN_TABLE (VEX_LEN_0F12_P_2_M_0
) },
10441 { VEX_LEN_TABLE (VEX_LEN_0F13_M_0
) },
10444 /* MOD_VEX_0F16_PREFIX_0 */
10445 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0
) },
10446 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1
) },
10449 /* MOD_VEX_0F16_PREFIX_2 */
10450 { VEX_LEN_TABLE (VEX_LEN_0F16_P_2_M_0
) },
10454 { VEX_LEN_TABLE (VEX_LEN_0F17_M_0
) },
10458 { "vmovntpX", { Mx
, XM
}, PREFIX_OPCODE
},
10461 /* MOD_VEX_W_0_0F41_P_0_LEN_1 */
10463 { "kandw", { MaskG
, MaskVex
, MaskR
}, 0 },
10466 /* MOD_VEX_W_1_0F41_P_0_LEN_1 */
10468 { "kandq", { MaskG
, MaskVex
, MaskR
}, 0 },
10471 /* MOD_VEX_W_0_0F41_P_2_LEN_1 */
10473 { "kandb", { MaskG
, MaskVex
, MaskR
}, 0 },
10476 /* MOD_VEX_W_1_0F41_P_2_LEN_1 */
10478 { "kandd", { MaskG
, MaskVex
, MaskR
}, 0 },
10481 /* MOD_VEX_W_0_0F42_P_0_LEN_1 */
10483 { "kandnw", { MaskG
, MaskVex
, MaskR
}, 0 },
10486 /* MOD_VEX_W_1_0F42_P_0_LEN_1 */
10488 { "kandnq", { MaskG
, MaskVex
, MaskR
}, 0 },
10491 /* MOD_VEX_W_0_0F42_P_2_LEN_1 */
10493 { "kandnb", { MaskG
, MaskVex
, MaskR
}, 0 },
10496 /* MOD_VEX_W_1_0F42_P_2_LEN_1 */
10498 { "kandnd", { MaskG
, MaskVex
, MaskR
}, 0 },
10501 /* MOD_VEX_W_0_0F44_P_0_LEN_0 */
10503 { "knotw", { MaskG
, MaskR
}, 0 },
10506 /* MOD_VEX_W_1_0F44_P_0_LEN_0 */
10508 { "knotq", { MaskG
, MaskR
}, 0 },
10511 /* MOD_VEX_W_0_0F44_P_2_LEN_0 */
10513 { "knotb", { MaskG
, MaskR
}, 0 },
10516 /* MOD_VEX_W_1_0F44_P_2_LEN_0 */
10518 { "knotd", { MaskG
, MaskR
}, 0 },
10521 /* MOD_VEX_W_0_0F45_P_0_LEN_1 */
10523 { "korw", { MaskG
, MaskVex
, MaskR
}, 0 },
10526 /* MOD_VEX_W_1_0F45_P_0_LEN_1 */
10528 { "korq", { MaskG
, MaskVex
, MaskR
}, 0 },
10531 /* MOD_VEX_W_0_0F45_P_2_LEN_1 */
10533 { "korb", { MaskG
, MaskVex
, MaskR
}, 0 },
10536 /* MOD_VEX_W_1_0F45_P_2_LEN_1 */
10538 { "kord", { MaskG
, MaskVex
, MaskR
}, 0 },
10541 /* MOD_VEX_W_0_0F46_P_0_LEN_1 */
10543 { "kxnorw", { MaskG
, MaskVex
, MaskR
}, 0 },
10546 /* MOD_VEX_W_1_0F46_P_0_LEN_1 */
10548 { "kxnorq", { MaskG
, MaskVex
, MaskR
}, 0 },
10551 /* MOD_VEX_W_0_0F46_P_2_LEN_1 */
10553 { "kxnorb", { MaskG
, MaskVex
, MaskR
}, 0 },
10556 /* MOD_VEX_W_1_0F46_P_2_LEN_1 */
10558 { "kxnord", { MaskG
, MaskVex
, MaskR
}, 0 },
10561 /* MOD_VEX_W_0_0F47_P_0_LEN_1 */
10563 { "kxorw", { MaskG
, MaskVex
, MaskR
}, 0 },
10566 /* MOD_VEX_W_1_0F47_P_0_LEN_1 */
10568 { "kxorq", { MaskG
, MaskVex
, MaskR
}, 0 },
10571 /* MOD_VEX_W_0_0F47_P_2_LEN_1 */
10573 { "kxorb", { MaskG
, MaskVex
, MaskR
}, 0 },
10576 /* MOD_VEX_W_1_0F47_P_2_LEN_1 */
10578 { "kxord", { MaskG
, MaskVex
, MaskR
}, 0 },
10581 /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */
10583 { "kaddw", { MaskG
, MaskVex
, MaskR
}, 0 },
10586 /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */
10588 { "kaddq", { MaskG
, MaskVex
, MaskR
}, 0 },
10591 /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */
10593 { "kaddb", { MaskG
, MaskVex
, MaskR
}, 0 },
10596 /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */
10598 { "kaddd", { MaskG
, MaskVex
, MaskR
}, 0 },
10601 /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */
10603 { "kunpckwd", { MaskG
, MaskVex
, MaskR
}, 0 },
10606 /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */
10608 { "kunpckdq", { MaskG
, MaskVex
, MaskR
}, 0 },
10611 /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */
10613 { "kunpckbw", { MaskG
, MaskVex
, MaskR
}, 0 },
10618 { "vmovmskpX", { Gdq
, XS
}, PREFIX_OPCODE
},
10621 /* MOD_VEX_0F71_REG_2 */
10623 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2
) },
10626 /* MOD_VEX_0F71_REG_4 */
10628 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4
) },
10631 /* MOD_VEX_0F71_REG_6 */
10633 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6
) },
10636 /* MOD_VEX_0F72_REG_2 */
10638 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2
) },
10641 /* MOD_VEX_0F72_REG_4 */
10643 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4
) },
10646 /* MOD_VEX_0F72_REG_6 */
10648 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6
) },
10651 /* MOD_VEX_0F73_REG_2 */
10653 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2
) },
10656 /* MOD_VEX_0F73_REG_3 */
10658 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3
) },
10661 /* MOD_VEX_0F73_REG_6 */
10663 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6
) },
10666 /* MOD_VEX_0F73_REG_7 */
10668 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7
) },
10671 /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
10672 { "kmovw", { Ew
, MaskG
}, 0 },
10676 /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
10677 { "kmovq", { Eq
, MaskG
}, 0 },
10681 /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
10682 { "kmovb", { Eb
, MaskG
}, 0 },
10686 /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
10687 { "kmovd", { Ed
, MaskG
}, 0 },
10691 /* MOD_VEX_W_0_0F92_P_0_LEN_0 */
10693 { "kmovw", { MaskG
, Rdq
}, 0 },
10696 /* MOD_VEX_W_0_0F92_P_2_LEN_0 */
10698 { "kmovb", { MaskG
, Rdq
}, 0 },
10701 /* MOD_VEX_0F92_P_3_LEN_0 */
10703 { "kmovK", { MaskG
, Rdq
}, 0 },
10706 /* MOD_VEX_W_0_0F93_P_0_LEN_0 */
10708 { "kmovw", { Gdq
, MaskR
}, 0 },
10711 /* MOD_VEX_W_0_0F93_P_2_LEN_0 */
10713 { "kmovb", { Gdq
, MaskR
}, 0 },
10716 /* MOD_VEX_0F93_P_3_LEN_0 */
10718 { "kmovK", { Gdq
, MaskR
}, 0 },
10721 /* MOD_VEX_W_0_0F98_P_0_LEN_0 */
10723 { "kortestw", { MaskG
, MaskR
}, 0 },
10726 /* MOD_VEX_W_1_0F98_P_0_LEN_0 */
10728 { "kortestq", { MaskG
, MaskR
}, 0 },
10731 /* MOD_VEX_W_0_0F98_P_2_LEN_0 */
10733 { "kortestb", { MaskG
, MaskR
}, 0 },
10736 /* MOD_VEX_W_1_0F98_P_2_LEN_0 */
10738 { "kortestd", { MaskG
, MaskR
}, 0 },
10741 /* MOD_VEX_W_0_0F99_P_0_LEN_0 */
10743 { "ktestw", { MaskG
, MaskR
}, 0 },
10746 /* MOD_VEX_W_1_0F99_P_0_LEN_0 */
10748 { "ktestq", { MaskG
, MaskR
}, 0 },
10751 /* MOD_VEX_W_0_0F99_P_2_LEN_0 */
10753 { "ktestb", { MaskG
, MaskR
}, 0 },
10756 /* MOD_VEX_W_1_0F99_P_2_LEN_0 */
10758 { "ktestd", { MaskG
, MaskR
}, 0 },
10761 /* MOD_VEX_0FAE_REG_2 */
10762 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0
) },
10765 /* MOD_VEX_0FAE_REG_3 */
10766 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0
) },
10769 /* MOD_VEX_0FD7_PREFIX_2 */
10771 { "vpmovmskb", { Gdq
, XS
}, 0 },
10774 /* MOD_VEX_0FE7_PREFIX_2 */
10775 { "vmovntdq", { Mx
, XM
}, 0 },
10778 /* MOD_VEX_0FF0_PREFIX_3 */
10779 { "vlddqu", { XM
, M
}, 0 },
10782 /* MOD_VEX_0F381A_PREFIX_2 */
10783 { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0
) },
10786 /* MOD_VEX_0F382A_PREFIX_2 */
10787 { "vmovntdqa", { XM
, Mx
}, 0 },
10790 /* MOD_VEX_0F382C_PREFIX_2 */
10791 { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0
) },
10794 /* MOD_VEX_0F382D_PREFIX_2 */
10795 { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0
) },
10798 /* MOD_VEX_0F382E_PREFIX_2 */
10799 { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0
) },
10802 /* MOD_VEX_0F382F_PREFIX_2 */
10803 { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0
) },
10806 /* MOD_VEX_0F385A_PREFIX_2 */
10807 { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0
) },
10810 /* MOD_VEX_0F388C_PREFIX_2 */
10811 { "vpmaskmov%LW", { XM
, Vex
, Mx
}, 0 },
10814 /* MOD_VEX_0F388E_PREFIX_2 */
10815 { "vpmaskmov%LW", { Mx
, Vex
, XM
}, 0 },
10818 /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */
10820 { "kshiftrb", { MaskG
, MaskR
, Ib
}, 0 },
10823 /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */
10825 { "kshiftrw", { MaskG
, MaskR
, Ib
}, 0 },
10828 /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */
10830 { "kshiftrd", { MaskG
, MaskR
, Ib
}, 0 },
10833 /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */
10835 { "kshiftrq", { MaskG
, MaskR
, Ib
}, 0 },
10838 /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */
10840 { "kshiftlb", { MaskG
, MaskR
, Ib
}, 0 },
10843 /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */
10845 { "kshiftlw", { MaskG
, MaskR
, Ib
}, 0 },
10848 /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */
10850 { "kshiftld", { MaskG
, MaskR
, Ib
}, 0 },
10853 /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */
10855 { "kshiftlq", { MaskG
, MaskR
, Ib
}, 0 },
10858 #include "i386-dis-evex-mod.h"
10861 static const struct dis386 rm_table
[][8] = {
10864 { "xabort", { Skip_MODRM
, Ib
}, 0 },
10868 { "xbeginT", { Skip_MODRM
, Jdqw
}, 0 },
10871 /* RM_0F01_REG_0 */
10872 { "enclv", { Skip_MODRM
}, 0 },
10873 { "vmcall", { Skip_MODRM
}, 0 },
10874 { "vmlaunch", { Skip_MODRM
}, 0 },
10875 { "vmresume", { Skip_MODRM
}, 0 },
10876 { "vmxoff", { Skip_MODRM
}, 0 },
10877 { "pconfig", { Skip_MODRM
}, 0 },
10880 /* RM_0F01_REG_1 */
10881 { "monitor", { { OP_Monitor
, 0 } }, 0 },
10882 { "mwait", { { OP_Mwait
, 0 } }, 0 },
10883 { "clac", { Skip_MODRM
}, 0 },
10884 { "stac", { Skip_MODRM
}, 0 },
10888 { "encls", { Skip_MODRM
}, 0 },
10891 /* RM_0F01_REG_2 */
10892 { "xgetbv", { Skip_MODRM
}, 0 },
10893 { "xsetbv", { Skip_MODRM
}, 0 },
10896 { "vmfunc", { Skip_MODRM
}, 0 },
10897 { "xend", { Skip_MODRM
}, 0 },
10898 { "xtest", { Skip_MODRM
}, 0 },
10899 { "enclu", { Skip_MODRM
}, 0 },
10902 /* RM_0F01_REG_3 */
10903 { "vmrun", { Skip_MODRM
}, 0 },
10904 { PREFIX_TABLE (PREFIX_0F01_REG_3_RM_1
) },
10905 { "vmload", { Skip_MODRM
}, 0 },
10906 { "vmsave", { Skip_MODRM
}, 0 },
10907 { "stgi", { Skip_MODRM
}, 0 },
10908 { "clgi", { Skip_MODRM
}, 0 },
10909 { "skinit", { Skip_MODRM
}, 0 },
10910 { "invlpga", { Skip_MODRM
}, 0 },
10913 /* RM_0F01_REG_5_MOD_3 */
10914 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_0
) },
10915 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_1
) },
10916 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_2
) },
10920 { "rdpkru", { Skip_MODRM
}, 0 },
10921 { "wrpkru", { Skip_MODRM
}, 0 },
10924 /* RM_0F01_REG_7_MOD_3 */
10925 { "swapgs", { Skip_MODRM
}, 0 },
10926 { "rdtscp", { Skip_MODRM
}, 0 },
10927 { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_2
) },
10928 { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_3
) },
10929 { "clzero", { Skip_MODRM
}, 0 },
10930 { "rdpru", { Skip_MODRM
}, 0 },
10933 /* RM_0F1E_P_1_MOD_3_REG_7 */
10934 { "nopQ", { Ev
}, 0 },
10935 { "nopQ", { Ev
}, 0 },
10936 { "endbr64", { Skip_MODRM
}, PREFIX_OPCODE
},
10937 { "endbr32", { Skip_MODRM
}, PREFIX_OPCODE
},
10938 { "nopQ", { Ev
}, 0 },
10939 { "nopQ", { Ev
}, 0 },
10940 { "nopQ", { Ev
}, 0 },
10941 { "nopQ", { Ev
}, 0 },
10944 /* RM_0FAE_REG_6_MOD_3 */
10945 { "mfence", { Skip_MODRM
}, 0 },
10948 /* RM_0FAE_REG_7_MOD_3 */
10949 { "sfence", { Skip_MODRM
}, 0 },
10954 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
10956 /* We use the high bit to indicate different name for the same
10958 #define REP_PREFIX (0xf3 | 0x100)
10959 #define XACQUIRE_PREFIX (0xf2 | 0x200)
10960 #define XRELEASE_PREFIX (0xf3 | 0x400)
10961 #define BND_PREFIX (0xf2 | 0x400)
10962 #define NOTRACK_PREFIX (0x3e | 0x100)
10964 /* Remember if the current op is a jump instruction. */
10965 static bfd_boolean op_is_jump
= FALSE
;
10970 int newrex
, i
, length
;
10975 last_lock_prefix
= -1;
10976 last_repz_prefix
= -1;
10977 last_repnz_prefix
= -1;
10978 last_data_prefix
= -1;
10979 last_addr_prefix
= -1;
10980 last_rex_prefix
= -1;
10981 last_seg_prefix
= -1;
10983 active_seg_prefix
= 0;
10984 for (i
= 0; i
< (int) ARRAY_SIZE (all_prefixes
); i
++)
10985 all_prefixes
[i
] = 0;
10988 /* The maximum instruction length is 15bytes. */
10989 while (length
< MAX_CODE_LENGTH
- 1)
10991 FETCH_DATA (the_info
, codep
+ 1);
10995 /* REX prefixes family. */
11012 if (address_mode
== mode_64bit
)
11016 last_rex_prefix
= i
;
11019 prefixes
|= PREFIX_REPZ
;
11020 last_repz_prefix
= i
;
11023 prefixes
|= PREFIX_REPNZ
;
11024 last_repnz_prefix
= i
;
11027 prefixes
|= PREFIX_LOCK
;
11028 last_lock_prefix
= i
;
11031 prefixes
|= PREFIX_CS
;
11032 last_seg_prefix
= i
;
11033 active_seg_prefix
= PREFIX_CS
;
11036 prefixes
|= PREFIX_SS
;
11037 last_seg_prefix
= i
;
11038 active_seg_prefix
= PREFIX_SS
;
11041 prefixes
|= PREFIX_DS
;
11042 last_seg_prefix
= i
;
11043 active_seg_prefix
= PREFIX_DS
;
11046 prefixes
|= PREFIX_ES
;
11047 last_seg_prefix
= i
;
11048 active_seg_prefix
= PREFIX_ES
;
11051 prefixes
|= PREFIX_FS
;
11052 last_seg_prefix
= i
;
11053 active_seg_prefix
= PREFIX_FS
;
11056 prefixes
|= PREFIX_GS
;
11057 last_seg_prefix
= i
;
11058 active_seg_prefix
= PREFIX_GS
;
11061 prefixes
|= PREFIX_DATA
;
11062 last_data_prefix
= i
;
11065 prefixes
|= PREFIX_ADDR
;
11066 last_addr_prefix
= i
;
11069 /* fwait is really an instruction. If there are prefixes
11070 before the fwait, they belong to the fwait, *not* to the
11071 following instruction. */
11073 if (prefixes
|| rex
)
11075 prefixes
|= PREFIX_FWAIT
;
11077 /* This ensures that the previous REX prefixes are noticed
11078 as unused prefixes, as in the return case below. */
11082 prefixes
= PREFIX_FWAIT
;
11087 /* Rex is ignored when followed by another prefix. */
11093 if (*codep
!= FWAIT_OPCODE
)
11094 all_prefixes
[i
++] = *codep
;
11102 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
11105 static const char *
11106 prefix_name (int pref
, int sizeflag
)
11108 static const char *rexes
[16] =
11111 "rex.B", /* 0x41 */
11112 "rex.X", /* 0x42 */
11113 "rex.XB", /* 0x43 */
11114 "rex.R", /* 0x44 */
11115 "rex.RB", /* 0x45 */
11116 "rex.RX", /* 0x46 */
11117 "rex.RXB", /* 0x47 */
11118 "rex.W", /* 0x48 */
11119 "rex.WB", /* 0x49 */
11120 "rex.WX", /* 0x4a */
11121 "rex.WXB", /* 0x4b */
11122 "rex.WR", /* 0x4c */
11123 "rex.WRB", /* 0x4d */
11124 "rex.WRX", /* 0x4e */
11125 "rex.WRXB", /* 0x4f */
11130 /* REX prefixes family. */
11147 return rexes
[pref
- 0x40];
11167 return (sizeflag
& DFLAG
) ? "data16" : "data32";
11169 if (address_mode
== mode_64bit
)
11170 return (sizeflag
& AFLAG
) ? "addr32" : "addr64";
11172 return (sizeflag
& AFLAG
) ? "addr16" : "addr32";
11177 case XACQUIRE_PREFIX
:
11179 case XRELEASE_PREFIX
:
11183 case NOTRACK_PREFIX
:
11190 static char op_out
[MAX_OPERANDS
][100];
11191 static int op_ad
, op_index
[MAX_OPERANDS
];
11192 static int two_source_ops
;
11193 static bfd_vma op_address
[MAX_OPERANDS
];
11194 static bfd_vma op_riprel
[MAX_OPERANDS
];
11195 static bfd_vma start_pc
;
11198 * On the 386's of 1988, the maximum length of an instruction is 15 bytes.
11199 * (see topic "Redundant prefixes" in the "Differences from 8086"
11200 * section of the "Virtual 8086 Mode" chapter.)
11201 * 'pc' should be the address of this instruction, it will
11202 * be used to print the target address if this is a relative jump or call
11203 * The function returns the length of this instruction in bytes.
11206 static char intel_syntax
;
11207 static char intel_mnemonic
= !SYSV386_COMPAT
;
11208 static char open_char
;
11209 static char close_char
;
11210 static char separator_char
;
11211 static char scale_char
;
11219 static enum x86_64_isa isa64
;
11221 /* Here for backwards compatibility. When gdb stops using
11222 print_insn_i386_att and print_insn_i386_intel these functions can
11223 disappear, and print_insn_i386 be merged into print_insn. */
11225 print_insn_i386_att (bfd_vma pc
, disassemble_info
*info
)
11229 return print_insn (pc
, info
);
11233 print_insn_i386_intel (bfd_vma pc
, disassemble_info
*info
)
11237 return print_insn (pc
, info
);
11241 print_insn_i386 (bfd_vma pc
, disassemble_info
*info
)
11245 return print_insn (pc
, info
);
11249 print_i386_disassembler_options (FILE *stream
)
11251 fprintf (stream
, _("\n\
11252 The following i386/x86-64 specific disassembler options are supported for use\n\
11253 with the -M switch (multiple options should be separated by commas):\n"));
11255 fprintf (stream
, _(" x86-64 Disassemble in 64bit mode\n"));
11256 fprintf (stream
, _(" i386 Disassemble in 32bit mode\n"));
11257 fprintf (stream
, _(" i8086 Disassemble in 16bit mode\n"));
11258 fprintf (stream
, _(" att Display instruction in AT&T syntax\n"));
11259 fprintf (stream
, _(" intel Display instruction in Intel syntax\n"));
11260 fprintf (stream
, _(" att-mnemonic\n"
11261 " Display instruction in AT&T mnemonic\n"));
11262 fprintf (stream
, _(" intel-mnemonic\n"
11263 " Display instruction in Intel mnemonic\n"));
11264 fprintf (stream
, _(" addr64 Assume 64bit address size\n"));
11265 fprintf (stream
, _(" addr32 Assume 32bit address size\n"));
11266 fprintf (stream
, _(" addr16 Assume 16bit address size\n"));
11267 fprintf (stream
, _(" data32 Assume 32bit data size\n"));
11268 fprintf (stream
, _(" data16 Assume 16bit data size\n"));
11269 fprintf (stream
, _(" suffix Always display instruction suffix in AT&T syntax\n"));
11270 fprintf (stream
, _(" amd64 Display instruction in AMD64 ISA\n"));
11271 fprintf (stream
, _(" intel64 Display instruction in Intel64 ISA\n"));
11275 static const struct dis386 bad_opcode
= { "(bad)", { XX
}, 0 };
11277 /* Get a pointer to struct dis386 with a valid name. */
11279 static const struct dis386
*
11280 get_valid_dis386 (const struct dis386
*dp
, disassemble_info
*info
)
11282 int vindex
, vex_table_index
;
11284 if (dp
->name
!= NULL
)
11287 switch (dp
->op
[0].bytemode
)
11289 case USE_REG_TABLE
:
11290 dp
= ®_table
[dp
->op
[1].bytemode
][modrm
.reg
];
11293 case USE_MOD_TABLE
:
11294 vindex
= modrm
.mod
== 0x3 ? 1 : 0;
11295 dp
= &mod_table
[dp
->op
[1].bytemode
][vindex
];
11299 dp
= &rm_table
[dp
->op
[1].bytemode
][modrm
.rm
];
11302 case USE_PREFIX_TABLE
:
11305 /* The prefix in VEX is implicit. */
11306 switch (vex
.prefix
)
11311 case REPE_PREFIX_OPCODE
:
11314 case DATA_PREFIX_OPCODE
:
11317 case REPNE_PREFIX_OPCODE
:
11327 int last_prefix
= -1;
11330 /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
11331 When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
11333 if ((prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
)) != 0)
11335 if (last_repz_prefix
> last_repnz_prefix
)
11338 prefix
= PREFIX_REPZ
;
11339 last_prefix
= last_repz_prefix
;
11344 prefix
= PREFIX_REPNZ
;
11345 last_prefix
= last_repnz_prefix
;
11348 /* Check if prefix should be ignored. */
11349 if ((((prefix_table
[dp
->op
[1].bytemode
][vindex
].prefix_requirement
11350 & PREFIX_IGNORED
) >> PREFIX_IGNORED_SHIFT
)
11355 if (vindex
== 0 && (prefixes
& PREFIX_DATA
) != 0)
11358 prefix
= PREFIX_DATA
;
11359 last_prefix
= last_data_prefix
;
11364 used_prefixes
|= prefix
;
11365 all_prefixes
[last_prefix
] = 0;
11368 dp
= &prefix_table
[dp
->op
[1].bytemode
][vindex
];
11371 case USE_X86_64_TABLE
:
11372 vindex
= address_mode
== mode_64bit
? 1 : 0;
11373 dp
= &x86_64_table
[dp
->op
[1].bytemode
][vindex
];
11376 case USE_3BYTE_TABLE
:
11377 FETCH_DATA (info
, codep
+ 2);
11379 dp
= &three_byte_table
[dp
->op
[1].bytemode
][vindex
];
11381 modrm
.mod
= (*codep
>> 6) & 3;
11382 modrm
.reg
= (*codep
>> 3) & 7;
11383 modrm
.rm
= *codep
& 7;
11386 case USE_VEX_LEN_TABLE
:
11390 switch (vex
.length
)
11403 dp
= &vex_len_table
[dp
->op
[1].bytemode
][vindex
];
11406 case USE_EVEX_LEN_TABLE
:
11410 switch (vex
.length
)
11426 dp
= &evex_len_table
[dp
->op
[1].bytemode
][vindex
];
11429 case USE_XOP_8F_TABLE
:
11430 FETCH_DATA (info
, codep
+ 3);
11431 rex
= ~(*codep
>> 5) & 0x7;
11433 /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */
11434 switch ((*codep
& 0x1f))
11440 vex_table_index
= XOP_08
;
11443 vex_table_index
= XOP_09
;
11446 vex_table_index
= XOP_0A
;
11450 vex
.w
= *codep
& 0x80;
11451 if (vex
.w
&& address_mode
== mode_64bit
)
11454 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
11455 if (address_mode
!= mode_64bit
)
11457 /* In 16/32-bit mode REX_B is silently ignored. */
11461 vex
.length
= (*codep
& 0x4) ? 256 : 128;
11462 switch ((*codep
& 0x3))
11467 vex
.prefix
= DATA_PREFIX_OPCODE
;
11470 vex
.prefix
= REPE_PREFIX_OPCODE
;
11473 vex
.prefix
= REPNE_PREFIX_OPCODE
;
11480 dp
= &xop_table
[vex_table_index
][vindex
];
11483 FETCH_DATA (info
, codep
+ 1);
11484 modrm
.mod
= (*codep
>> 6) & 3;
11485 modrm
.reg
= (*codep
>> 3) & 7;
11486 modrm
.rm
= *codep
& 7;
11488 /* No XOP encoding so far allows for a non-zero embedded prefix. Avoid
11489 having to decode the bits for every otherwise valid encoding. */
11491 return &bad_opcode
;
11494 case USE_VEX_C4_TABLE
:
11496 FETCH_DATA (info
, codep
+ 3);
11497 rex
= ~(*codep
>> 5) & 0x7;
11498 switch ((*codep
& 0x1f))
11504 vex_table_index
= VEX_0F
;
11507 vex_table_index
= VEX_0F38
;
11510 vex_table_index
= VEX_0F3A
;
11514 vex
.w
= *codep
& 0x80;
11515 if (address_mode
== mode_64bit
)
11522 /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
11523 is ignored, other REX bits are 0 and the highest bit in
11524 VEX.vvvv is also ignored (but we mustn't clear it here). */
11527 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
11528 vex
.length
= (*codep
& 0x4) ? 256 : 128;
11529 switch ((*codep
& 0x3))
11534 vex
.prefix
= DATA_PREFIX_OPCODE
;
11537 vex
.prefix
= REPE_PREFIX_OPCODE
;
11540 vex
.prefix
= REPNE_PREFIX_OPCODE
;
11547 dp
= &vex_table
[vex_table_index
][vindex
];
11549 /* There is no MODRM byte for VEX0F 77. */
11550 if (vex_table_index
!= VEX_0F
|| vindex
!= 0x77)
11552 FETCH_DATA (info
, codep
+ 1);
11553 modrm
.mod
= (*codep
>> 6) & 3;
11554 modrm
.reg
= (*codep
>> 3) & 7;
11555 modrm
.rm
= *codep
& 7;
11559 case USE_VEX_C5_TABLE
:
11561 FETCH_DATA (info
, codep
+ 2);
11562 rex
= (*codep
& 0x80) ? 0 : REX_R
;
11564 /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
11566 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
11567 vex
.length
= (*codep
& 0x4) ? 256 : 128;
11568 switch ((*codep
& 0x3))
11573 vex
.prefix
= DATA_PREFIX_OPCODE
;
11576 vex
.prefix
= REPE_PREFIX_OPCODE
;
11579 vex
.prefix
= REPNE_PREFIX_OPCODE
;
11586 dp
= &vex_table
[dp
->op
[1].bytemode
][vindex
];
11588 /* There is no MODRM byte for VEX 77. */
11589 if (vindex
!= 0x77)
11591 FETCH_DATA (info
, codep
+ 1);
11592 modrm
.mod
= (*codep
>> 6) & 3;
11593 modrm
.reg
= (*codep
>> 3) & 7;
11594 modrm
.rm
= *codep
& 7;
11598 case USE_VEX_W_TABLE
:
11602 dp
= &vex_w_table
[dp
->op
[1].bytemode
][vex
.w
? 1 : 0];
11605 case USE_EVEX_TABLE
:
11606 two_source_ops
= 0;
11609 FETCH_DATA (info
, codep
+ 4);
11610 /* The first byte after 0x62. */
11611 rex
= ~(*codep
>> 5) & 0x7;
11612 vex
.r
= *codep
& 0x10;
11613 switch ((*codep
& 0xf))
11616 return &bad_opcode
;
11618 vex_table_index
= EVEX_0F
;
11621 vex_table_index
= EVEX_0F38
;
11624 vex_table_index
= EVEX_0F3A
;
11628 /* The second byte after 0x62. */
11630 vex
.w
= *codep
& 0x80;
11631 if (vex
.w
&& address_mode
== mode_64bit
)
11634 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
11637 if (!(*codep
& 0x4))
11638 return &bad_opcode
;
11640 switch ((*codep
& 0x3))
11645 vex
.prefix
= DATA_PREFIX_OPCODE
;
11648 vex
.prefix
= REPE_PREFIX_OPCODE
;
11651 vex
.prefix
= REPNE_PREFIX_OPCODE
;
11655 /* The third byte after 0x62. */
11658 /* Remember the static rounding bits. */
11659 vex
.ll
= (*codep
>> 5) & 3;
11660 vex
.b
= (*codep
& 0x10) != 0;
11662 vex
.v
= *codep
& 0x8;
11663 vex
.mask_register_specifier
= *codep
& 0x7;
11664 vex
.zeroing
= *codep
& 0x80;
11666 if (address_mode
!= mode_64bit
)
11668 /* In 16/32-bit mode silently ignore following bits. */
11678 dp
= &evex_table
[vex_table_index
][vindex
];
11680 FETCH_DATA (info
, codep
+ 1);
11681 modrm
.mod
= (*codep
>> 6) & 3;
11682 modrm
.reg
= (*codep
>> 3) & 7;
11683 modrm
.rm
= *codep
& 7;
11685 /* Set vector length. */
11686 if (modrm
.mod
== 3 && vex
.b
)
11702 return &bad_opcode
;
11715 if (dp
->name
!= NULL
)
11718 return get_valid_dis386 (dp
, info
);
11722 get_sib (disassemble_info
*info
, int sizeflag
)
11724 /* If modrm.mod == 3, operand must be register. */
11726 && ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
11730 FETCH_DATA (info
, codep
+ 2);
11731 sib
.index
= (codep
[1] >> 3) & 7;
11732 sib
.scale
= (codep
[1] >> 6) & 3;
11733 sib
.base
= codep
[1] & 7;
11738 print_insn (bfd_vma pc
, disassemble_info
*info
)
11740 const struct dis386
*dp
;
11742 char *op_txt
[MAX_OPERANDS
];
11744 int sizeflag
, orig_sizeflag
;
11746 struct dis_private priv
;
11749 priv
.orig_sizeflag
= AFLAG
| DFLAG
;
11750 if ((info
->mach
& bfd_mach_i386_i386
) != 0)
11751 address_mode
= mode_32bit
;
11752 else if (info
->mach
== bfd_mach_i386_i8086
)
11754 address_mode
= mode_16bit
;
11755 priv
.orig_sizeflag
= 0;
11758 address_mode
= mode_64bit
;
11760 if (intel_syntax
== (char) -1)
11761 intel_syntax
= (info
->mach
& bfd_mach_i386_intel_syntax
) != 0;
11763 for (p
= info
->disassembler_options
; p
!= NULL
; )
11765 if (CONST_STRNEQ (p
, "amd64"))
11767 else if (CONST_STRNEQ (p
, "intel64"))
11769 else if (CONST_STRNEQ (p
, "x86-64"))
11771 address_mode
= mode_64bit
;
11772 priv
.orig_sizeflag
|= AFLAG
| DFLAG
;
11774 else if (CONST_STRNEQ (p
, "i386"))
11776 address_mode
= mode_32bit
;
11777 priv
.orig_sizeflag
|= AFLAG
| DFLAG
;
11779 else if (CONST_STRNEQ (p
, "i8086"))
11781 address_mode
= mode_16bit
;
11782 priv
.orig_sizeflag
&= ~(AFLAG
| DFLAG
);
11784 else if (CONST_STRNEQ (p
, "intel"))
11787 if (CONST_STRNEQ (p
+ 5, "-mnemonic"))
11788 intel_mnemonic
= 1;
11790 else if (CONST_STRNEQ (p
, "att"))
11793 if (CONST_STRNEQ (p
+ 3, "-mnemonic"))
11794 intel_mnemonic
= 0;
11796 else if (CONST_STRNEQ (p
, "addr"))
11798 if (address_mode
== mode_64bit
)
11800 if (p
[4] == '3' && p
[5] == '2')
11801 priv
.orig_sizeflag
&= ~AFLAG
;
11802 else if (p
[4] == '6' && p
[5] == '4')
11803 priv
.orig_sizeflag
|= AFLAG
;
11807 if (p
[4] == '1' && p
[5] == '6')
11808 priv
.orig_sizeflag
&= ~AFLAG
;
11809 else if (p
[4] == '3' && p
[5] == '2')
11810 priv
.orig_sizeflag
|= AFLAG
;
11813 else if (CONST_STRNEQ (p
, "data"))
11815 if (p
[4] == '1' && p
[5] == '6')
11816 priv
.orig_sizeflag
&= ~DFLAG
;
11817 else if (p
[4] == '3' && p
[5] == '2')
11818 priv
.orig_sizeflag
|= DFLAG
;
11820 else if (CONST_STRNEQ (p
, "suffix"))
11821 priv
.orig_sizeflag
|= SUFFIX_ALWAYS
;
11823 p
= strchr (p
, ',');
11828 if (address_mode
== mode_64bit
&& sizeof (bfd_vma
) < 8)
11830 (*info
->fprintf_func
) (info
->stream
,
11831 _("64-bit address is disabled"));
11837 names64
= intel_names64
;
11838 names32
= intel_names32
;
11839 names16
= intel_names16
;
11840 names8
= intel_names8
;
11841 names8rex
= intel_names8rex
;
11842 names_seg
= intel_names_seg
;
11843 names_mm
= intel_names_mm
;
11844 names_bnd
= intel_names_bnd
;
11845 names_xmm
= intel_names_xmm
;
11846 names_ymm
= intel_names_ymm
;
11847 names_zmm
= intel_names_zmm
;
11848 index64
= intel_index64
;
11849 index32
= intel_index32
;
11850 names_mask
= intel_names_mask
;
11851 index16
= intel_index16
;
11854 separator_char
= '+';
11859 names64
= att_names64
;
11860 names32
= att_names32
;
11861 names16
= att_names16
;
11862 names8
= att_names8
;
11863 names8rex
= att_names8rex
;
11864 names_seg
= att_names_seg
;
11865 names_mm
= att_names_mm
;
11866 names_bnd
= att_names_bnd
;
11867 names_xmm
= att_names_xmm
;
11868 names_ymm
= att_names_ymm
;
11869 names_zmm
= att_names_zmm
;
11870 index64
= att_index64
;
11871 index32
= att_index32
;
11872 names_mask
= att_names_mask
;
11873 index16
= att_index16
;
11876 separator_char
= ',';
11880 /* The output looks better if we put 7 bytes on a line, since that
11881 puts most long word instructions on a single line. Use 8 bytes
11883 if ((info
->mach
& bfd_mach_l1om
) != 0)
11884 info
->bytes_per_line
= 8;
11886 info
->bytes_per_line
= 7;
11888 info
->private_data
= &priv
;
11889 priv
.max_fetched
= priv
.the_buffer
;
11890 priv
.insn_start
= pc
;
11893 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
11901 start_codep
= priv
.the_buffer
;
11902 codep
= priv
.the_buffer
;
11904 if (OPCODES_SIGSETJMP (priv
.bailout
) != 0)
11908 /* Getting here means we tried for data but didn't get it. That
11909 means we have an incomplete instruction of some sort. Just
11910 print the first byte as a prefix or a .byte pseudo-op. */
11911 if (codep
> priv
.the_buffer
)
11913 name
= prefix_name (priv
.the_buffer
[0], priv
.orig_sizeflag
);
11915 (*info
->fprintf_func
) (info
->stream
, "%s", name
);
11918 /* Just print the first byte as a .byte instruction. */
11919 (*info
->fprintf_func
) (info
->stream
, ".byte 0x%x",
11920 (unsigned int) priv
.the_buffer
[0]);
11930 sizeflag
= priv
.orig_sizeflag
;
11932 if (!ckprefix () || rex_used
)
11934 /* Too many prefixes or unused REX prefixes. */
11936 i
< (int) ARRAY_SIZE (all_prefixes
) && all_prefixes
[i
];
11938 (*info
->fprintf_func
) (info
->stream
, "%s%s",
11940 prefix_name (all_prefixes
[i
], sizeflag
));
11944 insn_codep
= codep
;
11946 FETCH_DATA (info
, codep
+ 1);
11947 two_source_ops
= (*codep
== 0x62) || (*codep
== 0xc8);
11949 if (((prefixes
& PREFIX_FWAIT
)
11950 && ((*codep
< 0xd8) || (*codep
> 0xdf))))
11952 /* Handle prefixes before fwait. */
11953 for (i
= 0; i
< fwait_prefix
&& all_prefixes
[i
];
11955 (*info
->fprintf_func
) (info
->stream
, "%s ",
11956 prefix_name (all_prefixes
[i
], sizeflag
));
11957 (*info
->fprintf_func
) (info
->stream
, "fwait");
11961 if (*codep
== 0x0f)
11963 unsigned char threebyte
;
11966 FETCH_DATA (info
, codep
+ 1);
11967 threebyte
= *codep
;
11968 dp
= &dis386_twobyte
[threebyte
];
11969 need_modrm
= twobyte_has_modrm
[*codep
];
11974 dp
= &dis386
[*codep
];
11975 need_modrm
= onebyte_has_modrm
[*codep
];
11979 /* Save sizeflag for printing the extra prefixes later before updating
11980 it for mnemonic and operand processing. The prefix names depend
11981 only on the address mode. */
11982 orig_sizeflag
= sizeflag
;
11983 if (prefixes
& PREFIX_ADDR
)
11985 if ((prefixes
& PREFIX_DATA
))
11991 FETCH_DATA (info
, codep
+ 1);
11992 modrm
.mod
= (*codep
>> 6) & 3;
11993 modrm
.reg
= (*codep
>> 3) & 7;
11994 modrm
.rm
= *codep
& 7;
12000 memset (&vex
, 0, sizeof (vex
));
12002 if (dp
->name
== NULL
&& dp
->op
[0].bytemode
== FLOATCODE
)
12004 get_sib (info
, sizeflag
);
12005 dofloat (sizeflag
);
12009 dp
= get_valid_dis386 (dp
, info
);
12010 if (dp
!= NULL
&& putop (dp
->name
, sizeflag
) == 0)
12012 get_sib (info
, sizeflag
);
12013 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
12016 op_ad
= MAX_OPERANDS
- 1 - i
;
12018 (*dp
->op
[i
].rtn
) (dp
->op
[i
].bytemode
, sizeflag
);
12019 /* For EVEX instruction after the last operand masking
12020 should be printed. */
12021 if (i
== 0 && vex
.evex
)
12023 /* Don't print {%k0}. */
12024 if (vex
.mask_register_specifier
)
12027 oappend (names_mask
[vex
.mask_register_specifier
]);
12037 /* Clear instruction information. */
12040 the_info
->insn_info_valid
= 0;
12041 the_info
->branch_delay_insns
= 0;
12042 the_info
->data_size
= 0;
12043 the_info
->insn_type
= dis_noninsn
;
12044 the_info
->target
= 0;
12045 the_info
->target2
= 0;
12048 /* Reset jump operation indicator. */
12049 op_is_jump
= FALSE
;
12052 int jump_detection
= 0;
12054 /* Extract flags. */
12055 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
12057 if ((dp
->op
[i
].rtn
== OP_J
)
12058 || (dp
->op
[i
].rtn
== OP_indirE
))
12059 jump_detection
|= 1;
12060 else if ((dp
->op
[i
].rtn
== BND_Fixup
)
12061 || (!dp
->op
[i
].rtn
&& !dp
->op
[i
].bytemode
))
12062 jump_detection
|= 2;
12063 else if ((dp
->op
[i
].bytemode
== cond_jump_mode
)
12064 || (dp
->op
[i
].bytemode
== loop_jcxz_mode
))
12065 jump_detection
|= 4;
12068 /* Determine if this is a jump or branch. */
12069 if ((jump_detection
& 0x3) == 0x3)
12072 if (jump_detection
& 0x4)
12073 the_info
->insn_type
= dis_condbranch
;
12075 the_info
->insn_type
=
12076 (dp
->name
&& !strncmp(dp
->name
, "call", 4))
12077 ? dis_jsr
: dis_branch
;
12081 /* If VEX.vvvv and EVEX.vvvv are unused, they must be all 1s, which
12082 are all 0s in inverted form. */
12083 if (need_vex
&& vex
.register_specifier
!= 0)
12085 (*info
->fprintf_func
) (info
->stream
, "(bad)");
12086 return end_codep
- priv
.the_buffer
;
12089 /* Check if the REX prefix is used. */
12090 if ((rex
^ rex_used
) == 0 && !need_vex
&& last_rex_prefix
>= 0)
12091 all_prefixes
[last_rex_prefix
] = 0;
12093 /* Check if the SEG prefix is used. */
12094 if ((prefixes
& (PREFIX_CS
| PREFIX_SS
| PREFIX_DS
| PREFIX_ES
12095 | PREFIX_FS
| PREFIX_GS
)) != 0
12096 && (used_prefixes
& active_seg_prefix
) != 0)
12097 all_prefixes
[last_seg_prefix
] = 0;
12099 /* Check if the ADDR prefix is used. */
12100 if ((prefixes
& PREFIX_ADDR
) != 0
12101 && (used_prefixes
& PREFIX_ADDR
) != 0)
12102 all_prefixes
[last_addr_prefix
] = 0;
12104 /* Check if the DATA prefix is used. */
12105 if ((prefixes
& PREFIX_DATA
) != 0
12106 && (used_prefixes
& PREFIX_DATA
) != 0
12108 all_prefixes
[last_data_prefix
] = 0;
12110 /* Print the extra prefixes. */
12112 for (i
= 0; i
< (int) ARRAY_SIZE (all_prefixes
); i
++)
12113 if (all_prefixes
[i
])
12116 name
= prefix_name (all_prefixes
[i
], orig_sizeflag
);
12119 prefix_length
+= strlen (name
) + 1;
12120 (*info
->fprintf_func
) (info
->stream
, "%s ", name
);
12123 /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
12124 unused, opcode is invalid. Since the PREFIX_DATA prefix may be
12125 used by putop and MMX/SSE operand and may be overriden by the
12126 PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
12128 if (dp
->prefix_requirement
== PREFIX_OPCODE
12130 ? vex
.prefix
== REPE_PREFIX_OPCODE
12131 || vex
.prefix
== REPNE_PREFIX_OPCODE
12133 & (PREFIX_REPZ
| PREFIX_REPNZ
)) != 0)
12135 & (PREFIX_REPZ
| PREFIX_REPNZ
)) == 0)
12137 ? vex
.prefix
== DATA_PREFIX_OPCODE
12139 & (PREFIX_REPZ
| PREFIX_REPNZ
| PREFIX_DATA
))
12141 && (used_prefixes
& PREFIX_DATA
) == 0))
12142 || (vex
.evex
&& !vex
.w
!= !(used_prefixes
& PREFIX_DATA
))))
12144 (*info
->fprintf_func
) (info
->stream
, "(bad)");
12145 return end_codep
- priv
.the_buffer
;
12148 /* Check maximum code length. */
12149 if ((codep
- start_codep
) > MAX_CODE_LENGTH
)
12151 (*info
->fprintf_func
) (info
->stream
, "(bad)");
12152 return MAX_CODE_LENGTH
;
12155 obufp
= mnemonicendp
;
12156 for (i
= strlen (obuf
) + prefix_length
; i
< 6; i
++)
12159 (*info
->fprintf_func
) (info
->stream
, "%s", obuf
);
12161 /* The enter and bound instructions are printed with operands in the same
12162 order as the intel book; everything else is printed in reverse order. */
12163 if (intel_syntax
|| two_source_ops
)
12167 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
12168 op_txt
[i
] = op_out
[i
];
12170 if (intel_syntax
&& dp
&& dp
->op
[2].rtn
== OP_Rounding
12171 && dp
->op
[3].rtn
== OP_E
&& dp
->op
[4].rtn
== NULL
)
12173 op_txt
[2] = op_out
[3];
12174 op_txt
[3] = op_out
[2];
12177 for (i
= 0; i
< (MAX_OPERANDS
>> 1); ++i
)
12179 op_ad
= op_index
[i
];
12180 op_index
[i
] = op_index
[MAX_OPERANDS
- 1 - i
];
12181 op_index
[MAX_OPERANDS
- 1 - i
] = op_ad
;
12182 riprel
= op_riprel
[i
];
12183 op_riprel
[i
] = op_riprel
[MAX_OPERANDS
- 1 - i
];
12184 op_riprel
[MAX_OPERANDS
- 1 - i
] = riprel
;
12189 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
12190 op_txt
[MAX_OPERANDS
- 1 - i
] = op_out
[i
];
12194 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
12198 (*info
->fprintf_func
) (info
->stream
, ",");
12199 if (op_index
[i
] != -1 && !op_riprel
[i
])
12201 bfd_vma target
= (bfd_vma
) op_address
[op_index
[i
]];
12203 if (the_info
&& op_is_jump
)
12205 the_info
->insn_info_valid
= 1;
12206 the_info
->branch_delay_insns
= 0;
12207 the_info
->data_size
= 0;
12208 the_info
->target
= target
;
12209 the_info
->target2
= 0;
12211 (*info
->print_address_func
) (target
, info
);
12214 (*info
->fprintf_func
) (info
->stream
, "%s", op_txt
[i
]);
12218 for (i
= 0; i
< MAX_OPERANDS
; i
++)
12219 if (op_index
[i
] != -1 && op_riprel
[i
])
12221 (*info
->fprintf_func
) (info
->stream
, " # ");
12222 (*info
->print_address_func
) ((bfd_vma
) (start_pc
+ (codep
- start_codep
)
12223 + op_address
[op_index
[i
]]), info
);
12226 return codep
- priv
.the_buffer
;
12229 static const char *float_mem
[] = {
12304 static const unsigned char float_mem_mode
[] = {
12379 #define ST { OP_ST, 0 }
12380 #define STi { OP_STi, 0 }
12382 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
12383 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
12384 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
12385 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
12386 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
12387 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
12388 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
12389 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
12390 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
12392 static const struct dis386 float_reg
[][8] = {
12395 { "fadd", { ST
, STi
}, 0 },
12396 { "fmul", { ST
, STi
}, 0 },
12397 { "fcom", { STi
}, 0 },
12398 { "fcomp", { STi
}, 0 },
12399 { "fsub", { ST
, STi
}, 0 },
12400 { "fsubr", { ST
, STi
}, 0 },
12401 { "fdiv", { ST
, STi
}, 0 },
12402 { "fdivr", { ST
, STi
}, 0 },
12406 { "fld", { STi
}, 0 },
12407 { "fxch", { STi
}, 0 },
12417 { "fcmovb", { ST
, STi
}, 0 },
12418 { "fcmove", { ST
, STi
}, 0 },
12419 { "fcmovbe",{ ST
, STi
}, 0 },
12420 { "fcmovu", { ST
, STi
}, 0 },
12428 { "fcmovnb",{ ST
, STi
}, 0 },
12429 { "fcmovne",{ ST
, STi
}, 0 },
12430 { "fcmovnbe",{ ST
, STi
}, 0 },
12431 { "fcmovnu",{ ST
, STi
}, 0 },
12433 { "fucomi", { ST
, STi
}, 0 },
12434 { "fcomi", { ST
, STi
}, 0 },
12439 { "fadd", { STi
, ST
}, 0 },
12440 { "fmul", { STi
, ST
}, 0 },
12443 { "fsub{!M|r}", { STi
, ST
}, 0 },
12444 { "fsub{M|}", { STi
, ST
}, 0 },
12445 { "fdiv{!M|r}", { STi
, ST
}, 0 },
12446 { "fdiv{M|}", { STi
, ST
}, 0 },
12450 { "ffree", { STi
}, 0 },
12452 { "fst", { STi
}, 0 },
12453 { "fstp", { STi
}, 0 },
12454 { "fucom", { STi
}, 0 },
12455 { "fucomp", { STi
}, 0 },
12461 { "faddp", { STi
, ST
}, 0 },
12462 { "fmulp", { STi
, ST
}, 0 },
12465 { "fsub{!M|r}p", { STi
, ST
}, 0 },
12466 { "fsub{M|}p", { STi
, ST
}, 0 },
12467 { "fdiv{!M|r}p", { STi
, ST
}, 0 },
12468 { "fdiv{M|}p", { STi
, ST
}, 0 },
12472 { "ffreep", { STi
}, 0 },
12477 { "fucomip", { ST
, STi
}, 0 },
12478 { "fcomip", { ST
, STi
}, 0 },
12483 static char *fgrps
[][8] = {
12486 "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12491 "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12496 "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
12501 "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
12506 "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
12511 "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
12516 "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12521 "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
12522 "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
12527 "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12532 "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12537 swap_operand (void)
12539 mnemonicendp
[0] = '.';
12540 mnemonicendp
[1] = 's';
12545 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED
,
12546 int sizeflag ATTRIBUTE_UNUSED
)
12548 /* Skip mod/rm byte. */
12554 dofloat (int sizeflag
)
12556 const struct dis386
*dp
;
12557 unsigned char floatop
;
12559 floatop
= codep
[-1];
12561 if (modrm
.mod
!= 3)
12563 int fp_indx
= (floatop
- 0xd8) * 8 + modrm
.reg
;
12565 putop (float_mem
[fp_indx
], sizeflag
);
12568 OP_E (float_mem_mode
[fp_indx
], sizeflag
);
12571 /* Skip mod/rm byte. */
12575 dp
= &float_reg
[floatop
- 0xd8][modrm
.reg
];
12576 if (dp
->name
== NULL
)
12578 putop (fgrps
[dp
->op
[0].bytemode
][modrm
.rm
], sizeflag
);
12580 /* Instruction fnstsw is only one with strange arg. */
12581 if (floatop
== 0xdf && codep
[-1] == 0xe0)
12582 strcpy (op_out
[0], names16
[0]);
12586 putop (dp
->name
, sizeflag
);
12591 (*dp
->op
[0].rtn
) (dp
->op
[0].bytemode
, sizeflag
);
12596 (*dp
->op
[1].rtn
) (dp
->op
[1].bytemode
, sizeflag
);
12600 /* Like oappend (below), but S is a string starting with '%'.
12601 In Intel syntax, the '%' is elided. */
12603 oappend_maybe_intel (const char *s
)
12605 oappend (s
+ intel_syntax
);
12609 OP_ST (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
12611 oappend_maybe_intel ("%st");
12615 OP_STi (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
12617 sprintf (scratchbuf
, "%%st(%d)", modrm
.rm
);
12618 oappend_maybe_intel (scratchbuf
);
12621 /* Capital letters in template are macros. */
12623 putop (const char *in_template
, int sizeflag
)
12628 unsigned int l
= 0, len
= 0;
12631 for (p
= in_template
; *p
; p
++)
12635 if (l
>= sizeof (last
) || !ISUPPER (*p
))
12654 while (*++p
!= '|')
12655 if (*p
== '}' || *p
== '\0')
12661 while (*++p
!= '}')
12673 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
12682 if (sizeflag
& SUFFIX_ALWAYS
)
12685 else if (l
== 1 && last
[0] == 'L')
12687 if (address_mode
== mode_64bit
12688 && !(prefixes
& PREFIX_ADDR
))
12701 if (intel_syntax
&& !alt
)
12703 if ((prefixes
& PREFIX_DATA
) || (sizeflag
& SUFFIX_ALWAYS
))
12705 if (sizeflag
& DFLAG
)
12706 *obufp
++ = intel_syntax
? 'd' : 'l';
12708 *obufp
++ = intel_syntax
? 'w' : 's';
12709 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12713 if (intel_syntax
|| !(sizeflag
& SUFFIX_ALWAYS
))
12716 if (modrm
.mod
== 3)
12722 if (sizeflag
& DFLAG
)
12723 *obufp
++ = intel_syntax
? 'd' : 'l';
12726 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12732 case 'E': /* For jcxz/jecxz */
12733 if (address_mode
== mode_64bit
)
12735 if (sizeflag
& AFLAG
)
12741 if (sizeflag
& AFLAG
)
12743 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
12748 if ((prefixes
& PREFIX_ADDR
) || (sizeflag
& SUFFIX_ALWAYS
))
12750 if (sizeflag
& AFLAG
)
12751 *obufp
++ = address_mode
== mode_64bit
? 'q' : 'l';
12753 *obufp
++ = address_mode
== mode_64bit
? 'l' : 'w';
12754 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
12758 if (intel_syntax
|| (obufp
[-1] != 's' && !(sizeflag
& SUFFIX_ALWAYS
)))
12760 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
12764 if (!(rex
& REX_W
))
12765 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12770 if ((prefixes
& (PREFIX_CS
| PREFIX_DS
)) == PREFIX_CS
12771 || (prefixes
& (PREFIX_CS
| PREFIX_DS
)) == PREFIX_DS
)
12773 used_prefixes
|= prefixes
& (PREFIX_CS
| PREFIX_DS
);
12776 if (prefixes
& PREFIX_DS
)
12792 if (l
!= 1 || last
[0] != 'X')
12794 if (!need_vex
|| !vex
.evex
)
12797 || ((modrm
.mod
== 3 || vex
.b
) && !(sizeflag
& SUFFIX_ALWAYS
)))
12799 switch (vex
.length
)
12817 if (address_mode
== mode_64bit
&& (sizeflag
& SUFFIX_ALWAYS
))
12822 /* Fall through. */
12830 if (sizeflag
& SUFFIX_ALWAYS
)
12834 if (intel_mnemonic
!= cond
)
12838 if ((prefixes
& PREFIX_FWAIT
) == 0)
12841 used_prefixes
|= PREFIX_FWAIT
;
12847 else if (intel_syntax
&& (sizeflag
& DFLAG
))
12851 if (!(rex
& REX_W
))
12852 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12856 && address_mode
== mode_64bit
12857 && isa64
== intel64
)
12862 /* Fall through. */
12865 && address_mode
== mode_64bit
12866 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
12871 /* Fall through. */
12879 if ((rex
& REX_W
) == 0
12880 && (prefixes
& PREFIX_DATA
))
12882 if ((sizeflag
& DFLAG
) == 0)
12884 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12888 if ((prefixes
& PREFIX_DATA
)
12890 || (sizeflag
& SUFFIX_ALWAYS
))
12897 if (sizeflag
& DFLAG
)
12901 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12905 else if (l
== 1 && last
[0] == 'L')
12907 if ((prefixes
& PREFIX_DATA
)
12909 || (sizeflag
& SUFFIX_ALWAYS
))
12916 if (sizeflag
& DFLAG
)
12917 *obufp
++ = intel_syntax
? 'd' : 'l';
12920 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12930 if (address_mode
== mode_64bit
12931 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
12933 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
12937 /* Fall through. */
12943 if (intel_syntax
&& !alt
)
12946 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
12952 if (sizeflag
& DFLAG
)
12953 *obufp
++ = intel_syntax
? 'd' : 'l';
12956 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12960 else if (l
== 1 && last
[0] == 'L')
12962 if ((intel_syntax
&& need_modrm
)
12963 || (modrm
.mod
== 3 && !(sizeflag
& SUFFIX_ALWAYS
)))
12970 else if((address_mode
== mode_64bit
&& need_modrm
)
12971 || (sizeflag
& SUFFIX_ALWAYS
))
12972 *obufp
++ = intel_syntax
? 'd' : 'l';
12981 else if (sizeflag
& DFLAG
)
12990 if (intel_syntax
&& !p
[1]
12991 && ((rex
& REX_W
) || (sizeflag
& DFLAG
)))
12993 if (!(rex
& REX_W
))
12994 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13001 if (address_mode
== mode_64bit
13002 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
13004 if (sizeflag
& SUFFIX_ALWAYS
)
13009 else if (l
== 1 && last
[0] == 'L')
13020 /* Fall through. */
13028 if (sizeflag
& SUFFIX_ALWAYS
)
13034 if (sizeflag
& DFLAG
)
13038 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13042 else if (l
== 1 && last
[0] == 'L')
13044 if (address_mode
== mode_64bit
13045 && !(prefixes
& PREFIX_ADDR
))
13061 ? vex
.prefix
== DATA_PREFIX_OPCODE
13062 : prefixes
& PREFIX_DATA
)
13065 used_prefixes
|= PREFIX_DATA
;
13071 if (l
== 1 && last
[0] == 'X')
13076 || ((modrm
.mod
== 3 || vex
.b
) && !(sizeflag
& SUFFIX_ALWAYS
)))
13078 switch (vex
.length
)
13098 /* operand size flag for cwtl, cbtw */
13107 else if (sizeflag
& DFLAG
)
13111 if (!(rex
& REX_W
))
13112 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13118 if (last
[0] == 'X')
13119 *obufp
++ = vex
.w
? 'd': 's';
13120 else if (last
[0] == 'L')
13121 *obufp
++ = vex
.w
? 'q': 'd';
13122 else if (last
[0] == 'B')
13123 *obufp
++ = vex
.w
? 'w': 'b';
13133 if (isa64
== intel64
&& (rex
& REX_W
))
13139 if ((prefixes
& PREFIX_DATA
) || (sizeflag
& SUFFIX_ALWAYS
))
13141 if (sizeflag
& DFLAG
)
13145 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13151 if (address_mode
== mode_64bit
13152 && (isa64
== intel64
13153 || ((sizeflag
& DFLAG
) || (rex
& REX_W
))))
13155 else if ((prefixes
& PREFIX_DATA
))
13157 if (!(sizeflag
& DFLAG
))
13159 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13168 mnemonicendp
= obufp
;
13173 oappend (const char *s
)
13175 obufp
= stpcpy (obufp
, s
);
13181 /* Only print the active segment register. */
13182 if (!active_seg_prefix
)
13185 used_prefixes
|= active_seg_prefix
;
13186 switch (active_seg_prefix
)
13189 oappend_maybe_intel ("%cs:");
13192 oappend_maybe_intel ("%ds:");
13195 oappend_maybe_intel ("%ss:");
13198 oappend_maybe_intel ("%es:");
13201 oappend_maybe_intel ("%fs:");
13204 oappend_maybe_intel ("%gs:");
13212 OP_indirE (int bytemode
, int sizeflag
)
13216 OP_E (bytemode
, sizeflag
);
13220 print_operand_value (char *buf
, int hex
, bfd_vma disp
)
13222 if (address_mode
== mode_64bit
)
13230 sprintf_vma (tmp
, disp
);
13231 for (i
= 0; tmp
[i
] == '0' && tmp
[i
+ 1]; i
++);
13232 strcpy (buf
+ 2, tmp
+ i
);
13236 bfd_signed_vma v
= disp
;
13243 /* Check for possible overflow on 0x8000000000000000. */
13246 strcpy (buf
, "9223372036854775808");
13260 tmp
[28 - i
] = (v
% 10) + '0';
13264 strcpy (buf
, tmp
+ 29 - i
);
13270 sprintf (buf
, "0x%x", (unsigned int) disp
);
13272 sprintf (buf
, "%d", (int) disp
);
13276 /* Put DISP in BUF as signed hex number. */
13279 print_displacement (char *buf
, bfd_vma disp
)
13281 bfd_signed_vma val
= disp
;
13290 /* Check for possible overflow. */
13293 switch (address_mode
)
13296 strcpy (buf
+ j
, "0x8000000000000000");
13299 strcpy (buf
+ j
, "0x80000000");
13302 strcpy (buf
+ j
, "0x8000");
13312 sprintf_vma (tmp
, (bfd_vma
) val
);
13313 for (i
= 0; tmp
[i
] == '0'; i
++)
13315 if (tmp
[i
] == '\0')
13317 strcpy (buf
+ j
, tmp
+ i
);
13321 intel_operand_size (int bytemode
, int sizeflag
)
13325 && (bytemode
== x_mode
13326 || bytemode
== evex_half_bcst_xmmq_mode
))
13329 oappend ("QWORD PTR ");
13331 oappend ("DWORD PTR ");
13340 oappend ("BYTE PTR ");
13345 oappend ("WORD PTR ");
13348 if (address_mode
== mode_64bit
&& isa64
== intel64
)
13350 oappend ("QWORD PTR ");
13353 /* Fall through. */
13355 if (address_mode
== mode_64bit
&& ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
13357 oappend ("QWORD PTR ");
13360 /* Fall through. */
13366 oappend ("QWORD PTR ");
13369 if ((sizeflag
& DFLAG
) || bytemode
== dq_mode
)
13370 oappend ("DWORD PTR ");
13372 oappend ("WORD PTR ");
13373 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13377 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
13379 oappend ("WORD PTR ");
13380 if (!(rex
& REX_W
))
13381 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13384 if (sizeflag
& DFLAG
)
13385 oappend ("QWORD PTR ");
13387 oappend ("DWORD PTR ");
13388 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13391 if (!(sizeflag
& DFLAG
) && isa64
== intel64
)
13392 oappend ("WORD PTR ");
13394 oappend ("DWORD PTR ");
13395 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13398 case d_scalar_swap_mode
:
13401 oappend ("DWORD PTR ");
13404 case q_scalar_swap_mode
:
13406 oappend ("QWORD PTR ");
13409 if (address_mode
== mode_64bit
)
13410 oappend ("QWORD PTR ");
13412 oappend ("DWORD PTR ");
13415 if (sizeflag
& DFLAG
)
13416 oappend ("FWORD PTR ");
13418 oappend ("DWORD PTR ");
13419 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13422 oappend ("TBYTE PTR ");
13426 case evex_x_gscat_mode
:
13427 case evex_x_nobcst_mode
:
13428 case b_scalar_mode
:
13429 case w_scalar_mode
:
13432 switch (vex
.length
)
13435 oappend ("XMMWORD PTR ");
13438 oappend ("YMMWORD PTR ");
13441 oappend ("ZMMWORD PTR ");
13448 oappend ("XMMWORD PTR ");
13451 oappend ("XMMWORD PTR ");
13454 oappend ("YMMWORD PTR ");
13457 case evex_half_bcst_xmmq_mode
:
13461 switch (vex
.length
)
13464 oappend ("QWORD PTR ");
13467 oappend ("XMMWORD PTR ");
13470 oappend ("YMMWORD PTR ");
13480 switch (vex
.length
)
13485 oappend ("BYTE PTR ");
13495 switch (vex
.length
)
13500 oappend ("WORD PTR ");
13510 switch (vex
.length
)
13515 oappend ("DWORD PTR ");
13525 switch (vex
.length
)
13530 oappend ("QWORD PTR ");
13540 switch (vex
.length
)
13543 oappend ("WORD PTR ");
13546 oappend ("DWORD PTR ");
13549 oappend ("QWORD PTR ");
13559 switch (vex
.length
)
13562 oappend ("DWORD PTR ");
13565 oappend ("QWORD PTR ");
13568 oappend ("XMMWORD PTR ");
13578 switch (vex
.length
)
13581 oappend ("QWORD PTR ");
13584 oappend ("YMMWORD PTR ");
13587 oappend ("ZMMWORD PTR ");
13597 switch (vex
.length
)
13601 oappend ("XMMWORD PTR ");
13608 oappend ("OWORD PTR ");
13610 case vex_scalar_w_dq_mode
:
13615 oappend ("QWORD PTR ");
13617 oappend ("DWORD PTR ");
13619 case vex_vsib_d_w_dq_mode
:
13620 case vex_vsib_q_w_dq_mode
:
13627 oappend ("QWORD PTR ");
13629 oappend ("DWORD PTR ");
13633 switch (vex
.length
)
13636 oappend ("XMMWORD PTR ");
13639 oappend ("YMMWORD PTR ");
13642 oappend ("ZMMWORD PTR ");
13649 case vex_vsib_q_w_d_mode
:
13650 case vex_vsib_d_w_d_mode
:
13651 if (!need_vex
|| !vex
.evex
)
13654 switch (vex
.length
)
13657 oappend ("QWORD PTR ");
13660 oappend ("XMMWORD PTR ");
13663 oappend ("YMMWORD PTR ");
13671 if (!need_vex
|| vex
.length
!= 128)
13674 oappend ("DWORD PTR ");
13676 oappend ("BYTE PTR ");
13682 oappend ("QWORD PTR ");
13684 oappend ("WORD PTR ");
13694 OP_E_register (int bytemode
, int sizeflag
)
13696 int reg
= modrm
.rm
;
13697 const char **names
;
13703 if ((sizeflag
& SUFFIX_ALWAYS
)
13704 && (bytemode
== b_swap_mode
13705 || bytemode
== bnd_swap_mode
13706 || bytemode
== v_swap_mode
))
13732 names
= address_mode
== mode_64bit
? names64
: names32
;
13735 case bnd_swap_mode
:
13744 if (address_mode
== mode_64bit
&& isa64
== intel64
)
13749 /* Fall through. */
13751 if (address_mode
== mode_64bit
&& ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
13757 /* Fall through. */
13769 if ((sizeflag
& DFLAG
)
13770 || (bytemode
!= v_mode
13771 && bytemode
!= v_swap_mode
))
13775 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13779 if (!(sizeflag
& DFLAG
) && isa64
== intel64
)
13783 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13786 names
= (address_mode
== mode_64bit
13787 ? names64
: names32
);
13788 if (!(prefixes
& PREFIX_ADDR
))
13789 names
= (address_mode
== mode_16bit
13790 ? names16
: names
);
13793 /* Remove "addr16/addr32". */
13794 all_prefixes
[last_addr_prefix
] = 0;
13795 names
= (address_mode
!= mode_32bit
13796 ? names32
: names16
);
13797 used_prefixes
|= PREFIX_ADDR
;
13807 names
= names_mask
;
13812 oappend (INTERNAL_DISASSEMBLER_ERROR
);
13815 oappend (names
[reg
]);
13819 OP_E_memory (int bytemode
, int sizeflag
)
13822 int add
= (rex
& REX_B
) ? 8 : 0;
13828 /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0. */
13830 && bytemode
!= x_mode
13831 && bytemode
!= xmmq_mode
13832 && bytemode
!= evex_half_bcst_xmmq_mode
)
13848 if (address_mode
!= mode_64bit
)
13854 case vex_scalar_w_dq_mode
:
13855 case vex_vsib_d_w_dq_mode
:
13856 case vex_vsib_d_w_d_mode
:
13857 case vex_vsib_q_w_dq_mode
:
13858 case vex_vsib_q_w_d_mode
:
13859 case evex_x_gscat_mode
:
13860 shift
= vex
.w
? 3 : 2;
13863 case evex_half_bcst_xmmq_mode
:
13867 shift
= vex
.w
? 3 : 2;
13870 /* Fall through. */
13874 case evex_x_nobcst_mode
:
13876 switch (vex
.length
)
13900 case q_scalar_swap_mode
:
13907 case d_scalar_swap_mode
:
13910 case w_scalar_mode
:
13914 case b_scalar_mode
:
13921 /* Make necessary corrections to shift for modes that need it.
13922 For these modes we currently have shift 4, 5 or 6 depending on
13923 vex.length (it corresponds to xmmword, ymmword or zmmword
13924 operand). We might want to make it 3, 4 or 5 (e.g. for
13925 xmmq_mode). In case of broadcast enabled the corrections
13926 aren't needed, as element size is always 32 or 64 bits. */
13928 && (bytemode
== xmmq_mode
13929 || bytemode
== evex_half_bcst_xmmq_mode
))
13931 else if (bytemode
== xmmqd_mode
)
13933 else if (bytemode
== xmmdw_mode
)
13935 else if (bytemode
== ymmq_mode
&& vex
.length
== 128)
13943 intel_operand_size (bytemode
, sizeflag
);
13946 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
13948 /* 32/64 bit address mode */
13958 int addr32flag
= !((sizeflag
& AFLAG
)
13959 || bytemode
== v_bnd_mode
13960 || bytemode
== v_bndmk_mode
13961 || bytemode
== bnd_mode
13962 || bytemode
== bnd_swap_mode
);
13963 const char **indexes64
= names64
;
13964 const char **indexes32
= names32
;
13974 vindex
= sib
.index
;
13980 case vex_vsib_d_w_dq_mode
:
13981 case vex_vsib_d_w_d_mode
:
13982 case vex_vsib_q_w_dq_mode
:
13983 case vex_vsib_q_w_d_mode
:
13993 switch (vex
.length
)
13996 indexes64
= indexes32
= names_xmm
;
14000 || bytemode
== vex_vsib_q_w_dq_mode
14001 || bytemode
== vex_vsib_q_w_d_mode
)
14002 indexes64
= indexes32
= names_ymm
;
14004 indexes64
= indexes32
= names_xmm
;
14008 || bytemode
== vex_vsib_q_w_dq_mode
14009 || bytemode
== vex_vsib_q_w_d_mode
)
14010 indexes64
= indexes32
= names_zmm
;
14012 indexes64
= indexes32
= names_ymm
;
14019 haveindex
= vindex
!= 4;
14026 rbase
= base
+ add
;
14034 if (address_mode
== mode_64bit
&& !havesib
)
14037 if (riprel
&& bytemode
== v_bndmk_mode
)
14045 FETCH_DATA (the_info
, codep
+ 1);
14047 if ((disp
& 0x80) != 0)
14049 if (vex
.evex
&& shift
> 0)
14062 && address_mode
!= mode_16bit
)
14064 if (address_mode
== mode_64bit
)
14066 /* Display eiz instead of addr32. */
14067 needindex
= addr32flag
;
14072 /* In 32-bit mode, we need index register to tell [offset]
14073 from [eiz*1 + offset]. */
14078 havedisp
= (havebase
14080 || (havesib
&& (haveindex
|| scale
!= 0)));
14083 if (modrm
.mod
!= 0 || base
== 5)
14085 if (havedisp
|| riprel
)
14086 print_displacement (scratchbuf
, disp
);
14088 print_operand_value (scratchbuf
, 1, disp
);
14089 oappend (scratchbuf
);
14093 oappend (!addr32flag
? "(%rip)" : "(%eip)");
14097 if ((havebase
|| haveindex
|| needindex
|| needaddr32
|| riprel
)
14098 && (address_mode
!= mode_64bit
14099 || ((bytemode
!= v_bnd_mode
)
14100 && (bytemode
!= v_bndmk_mode
)
14101 && (bytemode
!= bnd_mode
)
14102 && (bytemode
!= bnd_swap_mode
))))
14103 used_prefixes
|= PREFIX_ADDR
;
14105 if (havedisp
|| (intel_syntax
&& riprel
))
14107 *obufp
++ = open_char
;
14108 if (intel_syntax
&& riprel
)
14111 oappend (!addr32flag
? "rip" : "eip");
14115 oappend (address_mode
== mode_64bit
&& !addr32flag
14116 ? names64
[rbase
] : names32
[rbase
]);
14119 /* ESP/RSP won't allow index. If base isn't ESP/RSP,
14120 print index to tell base + index from base. */
14124 || (havebase
&& base
!= ESP_REG_NUM
))
14126 if (!intel_syntax
|| havebase
)
14128 *obufp
++ = separator_char
;
14132 oappend (address_mode
== mode_64bit
&& !addr32flag
14133 ? indexes64
[vindex
] : indexes32
[vindex
]);
14135 oappend (address_mode
== mode_64bit
&& !addr32flag
14136 ? index64
: index32
);
14138 *obufp
++ = scale_char
;
14140 sprintf (scratchbuf
, "%d", 1 << scale
);
14141 oappend (scratchbuf
);
14145 && (disp
|| modrm
.mod
!= 0 || base
== 5))
14147 if (!havedisp
|| (bfd_signed_vma
) disp
>= 0)
14152 else if (modrm
.mod
!= 1 && disp
!= -disp
)
14156 disp
= - (bfd_signed_vma
) disp
;
14160 print_displacement (scratchbuf
, disp
);
14162 print_operand_value (scratchbuf
, 1, disp
);
14163 oappend (scratchbuf
);
14166 *obufp
++ = close_char
;
14169 else if (intel_syntax
)
14171 if (modrm
.mod
!= 0 || base
== 5)
14173 if (!active_seg_prefix
)
14175 oappend (names_seg
[ds_reg
- es_reg
]);
14178 print_operand_value (scratchbuf
, 1, disp
);
14179 oappend (scratchbuf
);
14183 else if (bytemode
== v_bnd_mode
14184 || bytemode
== v_bndmk_mode
14185 || bytemode
== bnd_mode
14186 || bytemode
== bnd_swap_mode
)
14193 /* 16 bit address mode */
14194 used_prefixes
|= prefixes
& PREFIX_ADDR
;
14201 if ((disp
& 0x8000) != 0)
14206 FETCH_DATA (the_info
, codep
+ 1);
14208 if ((disp
& 0x80) != 0)
14210 if (vex
.evex
&& shift
> 0)
14215 if ((disp
& 0x8000) != 0)
14221 if (modrm
.mod
!= 0 || modrm
.rm
== 6)
14223 print_displacement (scratchbuf
, disp
);
14224 oappend (scratchbuf
);
14227 if (modrm
.mod
!= 0 || modrm
.rm
!= 6)
14229 *obufp
++ = open_char
;
14231 oappend (index16
[modrm
.rm
]);
14233 && (disp
|| modrm
.mod
!= 0 || modrm
.rm
== 6))
14235 if ((bfd_signed_vma
) disp
>= 0)
14240 else if (modrm
.mod
!= 1)
14244 disp
= - (bfd_signed_vma
) disp
;
14247 print_displacement (scratchbuf
, disp
);
14248 oappend (scratchbuf
);
14251 *obufp
++ = close_char
;
14254 else if (intel_syntax
)
14256 if (!active_seg_prefix
)
14258 oappend (names_seg
[ds_reg
- es_reg
]);
14261 print_operand_value (scratchbuf
, 1, disp
& 0xffff);
14262 oappend (scratchbuf
);
14265 if (vex
.evex
&& vex
.b
14266 && (bytemode
== x_mode
14267 || bytemode
== xmmq_mode
14268 || bytemode
== evex_half_bcst_xmmq_mode
))
14271 || bytemode
== xmmq_mode
14272 || bytemode
== evex_half_bcst_xmmq_mode
)
14274 switch (vex
.length
)
14277 oappend ("{1to2}");
14280 oappend ("{1to4}");
14283 oappend ("{1to8}");
14291 switch (vex
.length
)
14294 oappend ("{1to4}");
14297 oappend ("{1to8}");
14300 oappend ("{1to16}");
14310 OP_E (int bytemode
, int sizeflag
)
14312 /* Skip mod/rm byte. */
14316 if (modrm
.mod
== 3)
14317 OP_E_register (bytemode
, sizeflag
);
14319 OP_E_memory (bytemode
, sizeflag
);
14323 OP_G (int bytemode
, int sizeflag
)
14326 const char **names
;
14335 oappend (names8rex
[modrm
.reg
+ add
]);
14337 oappend (names8
[modrm
.reg
+ add
]);
14340 oappend (names16
[modrm
.reg
+ add
]);
14345 oappend (names32
[modrm
.reg
+ add
]);
14348 oappend (names64
[modrm
.reg
+ add
]);
14351 if (modrm
.reg
> 0x3)
14356 oappend (names_bnd
[modrm
.reg
]);
14366 oappend (names64
[modrm
.reg
+ add
]);
14369 if ((sizeflag
& DFLAG
)
14370 || (bytemode
!= v_mode
&& bytemode
!= movsxd_mode
))
14371 oappend (names32
[modrm
.reg
+ add
]);
14373 oappend (names16
[modrm
.reg
+ add
]);
14374 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14378 names
= (address_mode
== mode_64bit
14379 ? names64
: names32
);
14380 if (!(prefixes
& PREFIX_ADDR
))
14382 if (address_mode
== mode_16bit
)
14387 /* Remove "addr16/addr32". */
14388 all_prefixes
[last_addr_prefix
] = 0;
14389 names
= (address_mode
!= mode_32bit
14390 ? names32
: names16
);
14391 used_prefixes
|= PREFIX_ADDR
;
14393 oappend (names
[modrm
.reg
+ add
]);
14396 if (address_mode
== mode_64bit
)
14397 oappend (names64
[modrm
.reg
+ add
]);
14399 oappend (names32
[modrm
.reg
+ add
]);
14403 if ((modrm
.reg
+ add
) > 0x7)
14408 oappend (names_mask
[modrm
.reg
+ add
]);
14411 oappend (INTERNAL_DISASSEMBLER_ERROR
);
14424 FETCH_DATA (the_info
, codep
+ 8);
14425 a
= *codep
++ & 0xff;
14426 a
|= (*codep
++ & 0xff) << 8;
14427 a
|= (*codep
++ & 0xff) << 16;
14428 a
|= (*codep
++ & 0xffu
) << 24;
14429 b
= *codep
++ & 0xff;
14430 b
|= (*codep
++ & 0xff) << 8;
14431 b
|= (*codep
++ & 0xff) << 16;
14432 b
|= (*codep
++ & 0xffu
) << 24;
14433 x
= a
+ ((bfd_vma
) b
<< 32);
14441 static bfd_signed_vma
14444 bfd_signed_vma x
= 0;
14446 FETCH_DATA (the_info
, codep
+ 4);
14447 x
= *codep
++ & (bfd_signed_vma
) 0xff;
14448 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 8;
14449 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 16;
14450 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 24;
14454 static bfd_signed_vma
14457 bfd_signed_vma x
= 0;
14459 FETCH_DATA (the_info
, codep
+ 4);
14460 x
= *codep
++ & (bfd_signed_vma
) 0xff;
14461 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 8;
14462 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 16;
14463 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 24;
14465 x
= (x
^ ((bfd_signed_vma
) 1 << 31)) - ((bfd_signed_vma
) 1 << 31);
14475 FETCH_DATA (the_info
, codep
+ 2);
14476 x
= *codep
++ & 0xff;
14477 x
|= (*codep
++ & 0xff) << 8;
14482 set_op (bfd_vma op
, int riprel
)
14484 op_index
[op_ad
] = op_ad
;
14485 if (address_mode
== mode_64bit
)
14487 op_address
[op_ad
] = op
;
14488 op_riprel
[op_ad
] = riprel
;
14492 /* Mask to get a 32-bit address. */
14493 op_address
[op_ad
] = op
& 0xffffffff;
14494 op_riprel
[op_ad
] = riprel
& 0xffffffff;
14499 OP_REG (int code
, int sizeflag
)
14506 case es_reg
: case ss_reg
: case cs_reg
:
14507 case ds_reg
: case fs_reg
: case gs_reg
:
14508 oappend (names_seg
[code
- es_reg
]);
14520 case ax_reg
: case cx_reg
: case dx_reg
: case bx_reg
:
14521 case sp_reg
: case bp_reg
: case si_reg
: case di_reg
:
14522 s
= names16
[code
- ax_reg
+ add
];
14524 case al_reg
: case ah_reg
: case cl_reg
: case ch_reg
:
14525 case dl_reg
: case dh_reg
: case bl_reg
: case bh_reg
:
14528 s
= names8rex
[code
- al_reg
+ add
];
14530 s
= names8
[code
- al_reg
];
14532 case rAX_reg
: case rCX_reg
: case rDX_reg
: case rBX_reg
:
14533 case rSP_reg
: case rBP_reg
: case rSI_reg
: case rDI_reg
:
14534 if (address_mode
== mode_64bit
14535 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
14537 s
= names64
[code
- rAX_reg
+ add
];
14540 code
+= eAX_reg
- rAX_reg
;
14541 /* Fall through. */
14542 case eAX_reg
: case eCX_reg
: case eDX_reg
: case eBX_reg
:
14543 case eSP_reg
: case eBP_reg
: case eSI_reg
: case eDI_reg
:
14546 s
= names64
[code
- eAX_reg
+ add
];
14549 if (sizeflag
& DFLAG
)
14550 s
= names32
[code
- eAX_reg
+ add
];
14552 s
= names16
[code
- eAX_reg
+ add
];
14553 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14557 s
= INTERNAL_DISASSEMBLER_ERROR
;
14564 OP_IMREG (int code
, int sizeflag
)
14576 case ax_reg
: case cx_reg
: case dx_reg
: case bx_reg
:
14577 case sp_reg
: case bp_reg
: case si_reg
: case di_reg
:
14578 s
= names16
[code
- ax_reg
];
14580 case es_reg
: case ss_reg
: case cs_reg
:
14581 case ds_reg
: case fs_reg
: case gs_reg
:
14582 s
= names_seg
[code
- es_reg
];
14584 case al_reg
: case ah_reg
: case cl_reg
: case ch_reg
:
14585 case dl_reg
: case dh_reg
: case bl_reg
: case bh_reg
:
14588 s
= names8rex
[code
- al_reg
];
14590 s
= names8
[code
- al_reg
];
14592 case eAX_reg
: case eCX_reg
: case eDX_reg
: case eBX_reg
:
14593 case eSP_reg
: case eBP_reg
: case eSI_reg
: case eDI_reg
:
14596 s
= names64
[code
- eAX_reg
];
14599 if (sizeflag
& DFLAG
)
14600 s
= names32
[code
- eAX_reg
];
14602 s
= names16
[code
- eAX_reg
];
14603 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14606 case z_mode_ax_reg
:
14607 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
14611 if (!(rex
& REX_W
))
14612 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14615 s
= INTERNAL_DISASSEMBLER_ERROR
;
14622 OP_I (int bytemode
, int sizeflag
)
14625 bfd_signed_vma mask
= -1;
14630 FETCH_DATA (the_info
, codep
+ 1);
14640 if (sizeflag
& DFLAG
)
14650 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14666 oappend (INTERNAL_DISASSEMBLER_ERROR
);
14671 scratchbuf
[0] = '$';
14672 print_operand_value (scratchbuf
+ 1, 1, op
);
14673 oappend_maybe_intel (scratchbuf
);
14674 scratchbuf
[0] = '\0';
14678 OP_I64 (int bytemode
, int sizeflag
)
14680 if (bytemode
!= v_mode
|| address_mode
!= mode_64bit
|| !(rex
& REX_W
))
14682 OP_I (bytemode
, sizeflag
);
14688 scratchbuf
[0] = '$';
14689 print_operand_value (scratchbuf
+ 1, 1, get64 ());
14690 oappend_maybe_intel (scratchbuf
);
14691 scratchbuf
[0] = '\0';
14695 OP_sI (int bytemode
, int sizeflag
)
14703 FETCH_DATA (the_info
, codep
+ 1);
14705 if ((op
& 0x80) != 0)
14707 if (bytemode
== b_T_mode
)
14709 if (address_mode
!= mode_64bit
14710 || !((sizeflag
& DFLAG
) || (rex
& REX_W
)))
14712 /* The operand-size prefix is overridden by a REX prefix. */
14713 if ((sizeflag
& DFLAG
) || (rex
& REX_W
))
14721 if (!(rex
& REX_W
))
14723 if (sizeflag
& DFLAG
)
14731 /* The operand-size prefix is overridden by a REX prefix. */
14732 if ((sizeflag
& DFLAG
) || (rex
& REX_W
))
14738 oappend (INTERNAL_DISASSEMBLER_ERROR
);
14742 scratchbuf
[0] = '$';
14743 print_operand_value (scratchbuf
+ 1, 1, op
);
14744 oappend_maybe_intel (scratchbuf
);
14748 OP_J (int bytemode
, int sizeflag
)
14752 bfd_vma segment
= 0;
14757 FETCH_DATA (the_info
, codep
+ 1);
14759 if ((disp
& 0x80) != 0)
14763 if (isa64
!= intel64
)
14766 if ((sizeflag
& DFLAG
)
14767 || (address_mode
== mode_64bit
14768 && ((isa64
== intel64
&& bytemode
!= dqw_mode
)
14769 || (rex
& REX_W
))))
14774 if ((disp
& 0x8000) != 0)
14776 /* In 16bit mode, address is wrapped around at 64k within
14777 the same segment. Otherwise, a data16 prefix on a jump
14778 instruction means that the pc is masked to 16 bits after
14779 the displacement is added! */
14781 if ((prefixes
& PREFIX_DATA
) == 0)
14782 segment
= ((start_pc
+ (codep
- start_codep
))
14783 & ~((bfd_vma
) 0xffff));
14785 if (address_mode
!= mode_64bit
14786 || (isa64
!= intel64
&& !(rex
& REX_W
)))
14787 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14790 oappend (INTERNAL_DISASSEMBLER_ERROR
);
14793 disp
= ((start_pc
+ (codep
- start_codep
) + disp
) & mask
) | segment
;
14795 print_operand_value (scratchbuf
, 1, disp
);
14796 oappend (scratchbuf
);
14800 OP_SEG (int bytemode
, int sizeflag
)
14802 if (bytemode
== w_mode
)
14803 oappend (names_seg
[modrm
.reg
]);
14805 OP_E (modrm
.mod
== 3 ? bytemode
: w_mode
, sizeflag
);
14809 OP_DIR (int dummy ATTRIBUTE_UNUSED
, int sizeflag
)
14813 if (sizeflag
& DFLAG
)
14823 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14825 sprintf (scratchbuf
, "0x%x:0x%x", seg
, offset
);
14827 sprintf (scratchbuf
, "$0x%x,$0x%x", seg
, offset
);
14828 oappend (scratchbuf
);
14832 OP_OFF (int bytemode
, int sizeflag
)
14836 if (intel_syntax
&& (sizeflag
& SUFFIX_ALWAYS
))
14837 intel_operand_size (bytemode
, sizeflag
);
14840 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
14847 if (!active_seg_prefix
)
14849 oappend (names_seg
[ds_reg
- es_reg
]);
14853 print_operand_value (scratchbuf
, 1, off
);
14854 oappend (scratchbuf
);
14858 OP_OFF64 (int bytemode
, int sizeflag
)
14862 if (address_mode
!= mode_64bit
14863 || (prefixes
& PREFIX_ADDR
))
14865 OP_OFF (bytemode
, sizeflag
);
14869 if (intel_syntax
&& (sizeflag
& SUFFIX_ALWAYS
))
14870 intel_operand_size (bytemode
, sizeflag
);
14877 if (!active_seg_prefix
)
14879 oappend (names_seg
[ds_reg
- es_reg
]);
14883 print_operand_value (scratchbuf
, 1, off
);
14884 oappend (scratchbuf
);
14888 ptr_reg (int code
, int sizeflag
)
14892 *obufp
++ = open_char
;
14893 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
14894 if (address_mode
== mode_64bit
)
14896 if (!(sizeflag
& AFLAG
))
14897 s
= names32
[code
- eAX_reg
];
14899 s
= names64
[code
- eAX_reg
];
14901 else if (sizeflag
& AFLAG
)
14902 s
= names32
[code
- eAX_reg
];
14904 s
= names16
[code
- eAX_reg
];
14906 *obufp
++ = close_char
;
14911 OP_ESreg (int code
, int sizeflag
)
14917 case 0x6d: /* insw/insl */
14918 intel_operand_size (z_mode
, sizeflag
);
14920 case 0xa5: /* movsw/movsl/movsq */
14921 case 0xa7: /* cmpsw/cmpsl/cmpsq */
14922 case 0xab: /* stosw/stosl */
14923 case 0xaf: /* scasw/scasl */
14924 intel_operand_size (v_mode
, sizeflag
);
14927 intel_operand_size (b_mode
, sizeflag
);
14930 oappend_maybe_intel ("%es:");
14931 ptr_reg (code
, sizeflag
);
14935 OP_DSreg (int code
, int sizeflag
)
14941 case 0x6f: /* outsw/outsl */
14942 intel_operand_size (z_mode
, sizeflag
);
14944 case 0xa5: /* movsw/movsl/movsq */
14945 case 0xa7: /* cmpsw/cmpsl/cmpsq */
14946 case 0xad: /* lodsw/lodsl/lodsq */
14947 intel_operand_size (v_mode
, sizeflag
);
14950 intel_operand_size (b_mode
, sizeflag
);
14953 /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
14954 default segment register DS is printed. */
14955 if (!active_seg_prefix
)
14956 active_seg_prefix
= PREFIX_DS
;
14958 ptr_reg (code
, sizeflag
);
14962 OP_C (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
14970 else if (address_mode
!= mode_64bit
&& (prefixes
& PREFIX_LOCK
))
14972 all_prefixes
[last_lock_prefix
] = 0;
14973 used_prefixes
|= PREFIX_LOCK
;
14978 sprintf (scratchbuf
, "%%cr%d", modrm
.reg
+ add
);
14979 oappend_maybe_intel (scratchbuf
);
14983 OP_D (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
14992 sprintf (scratchbuf
, "db%d", modrm
.reg
+ add
);
14994 sprintf (scratchbuf
, "%%db%d", modrm
.reg
+ add
);
14995 oappend (scratchbuf
);
14999 OP_T (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15001 sprintf (scratchbuf
, "%%tr%d", modrm
.reg
);
15002 oappend_maybe_intel (scratchbuf
);
15006 OP_R (int bytemode
, int sizeflag
)
15008 /* Skip mod/rm byte. */
15011 OP_E_register (bytemode
, sizeflag
);
15015 OP_MMX (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15017 int reg
= modrm
.reg
;
15018 const char **names
;
15020 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15021 if (prefixes
& PREFIX_DATA
)
15030 oappend (names
[reg
]);
15034 OP_XMM (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
15036 int reg
= modrm
.reg
;
15037 const char **names
;
15049 && bytemode
!= xmm_mode
15050 && bytemode
!= xmmq_mode
15051 && bytemode
!= evex_half_bcst_xmmq_mode
15052 && bytemode
!= ymm_mode
15053 && bytemode
!= scalar_mode
)
15055 switch (vex
.length
)
15062 || (bytemode
!= vex_vsib_q_w_dq_mode
15063 && bytemode
!= vex_vsib_q_w_d_mode
))
15075 else if (bytemode
== xmmq_mode
15076 || bytemode
== evex_half_bcst_xmmq_mode
)
15078 switch (vex
.length
)
15091 else if (bytemode
== ymm_mode
)
15095 oappend (names
[reg
]);
15099 OP_EM (int bytemode
, int sizeflag
)
15102 const char **names
;
15104 if (modrm
.mod
!= 3)
15107 && (bytemode
== v_mode
|| bytemode
== v_swap_mode
))
15109 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
15110 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15112 OP_E (bytemode
, sizeflag
);
15116 if ((sizeflag
& SUFFIX_ALWAYS
) && bytemode
== v_swap_mode
)
15119 /* Skip mod/rm byte. */
15122 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15124 if (prefixes
& PREFIX_DATA
)
15133 oappend (names
[reg
]);
15136 /* cvt* are the only instructions in sse2 which have
15137 both SSE and MMX operands and also have 0x66 prefix
15138 in their opcode. 0x66 was originally used to differentiate
15139 between SSE and MMX instruction(operands). So we have to handle the
15140 cvt* separately using OP_EMC and OP_MXC */
15142 OP_EMC (int bytemode
, int sizeflag
)
15144 if (modrm
.mod
!= 3)
15146 if (intel_syntax
&& bytemode
== v_mode
)
15148 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
15149 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15151 OP_E (bytemode
, sizeflag
);
15155 /* Skip mod/rm byte. */
15158 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15159 oappend (names_mm
[modrm
.rm
]);
15163 OP_MXC (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15165 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15166 oappend (names_mm
[modrm
.reg
]);
15170 OP_EX (int bytemode
, int sizeflag
)
15173 const char **names
;
15175 /* Skip mod/rm byte. */
15179 if (modrm
.mod
!= 3)
15181 OP_E_memory (bytemode
, sizeflag
);
15196 if ((sizeflag
& SUFFIX_ALWAYS
)
15197 && (bytemode
== x_swap_mode
15198 || bytemode
== d_swap_mode
15199 || bytemode
== d_scalar_swap_mode
15200 || bytemode
== q_swap_mode
15201 || bytemode
== q_scalar_swap_mode
))
15205 && bytemode
!= xmm_mode
15206 && bytemode
!= xmmdw_mode
15207 && bytemode
!= xmmqd_mode
15208 && bytemode
!= xmm_mb_mode
15209 && bytemode
!= xmm_mw_mode
15210 && bytemode
!= xmm_md_mode
15211 && bytemode
!= xmm_mq_mode
15212 && bytemode
!= xmmq_mode
15213 && bytemode
!= evex_half_bcst_xmmq_mode
15214 && bytemode
!= ymm_mode
15215 && bytemode
!= d_scalar_swap_mode
15216 && bytemode
!= q_scalar_swap_mode
15217 && bytemode
!= vex_scalar_w_dq_mode
)
15219 switch (vex
.length
)
15234 else if (bytemode
== xmmq_mode
15235 || bytemode
== evex_half_bcst_xmmq_mode
)
15237 switch (vex
.length
)
15250 else if (bytemode
== ymm_mode
)
15254 oappend (names
[reg
]);
15258 OP_MS (int bytemode
, int sizeflag
)
15260 if (modrm
.mod
== 3)
15261 OP_EM (bytemode
, sizeflag
);
15267 OP_XS (int bytemode
, int sizeflag
)
15269 if (modrm
.mod
== 3)
15270 OP_EX (bytemode
, sizeflag
);
15276 OP_M (int bytemode
, int sizeflag
)
15278 if (modrm
.mod
== 3)
15279 /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
15282 OP_E (bytemode
, sizeflag
);
15286 OP_0f07 (int bytemode
, int sizeflag
)
15288 if (modrm
.mod
!= 3 || modrm
.rm
!= 0)
15291 OP_E (bytemode
, sizeflag
);
15294 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
15295 32bit mode and "xchg %rax,%rax" in 64bit mode. */
15298 NOP_Fixup1 (int bytemode
, int sizeflag
)
15300 if ((prefixes
& PREFIX_DATA
) != 0
15303 && address_mode
== mode_64bit
))
15304 OP_REG (bytemode
, sizeflag
);
15306 strcpy (obuf
, "nop");
15310 NOP_Fixup2 (int bytemode
, int sizeflag
)
15312 if ((prefixes
& PREFIX_DATA
) != 0
15315 && address_mode
== mode_64bit
))
15316 OP_IMREG (bytemode
, sizeflag
);
15319 static const char *const Suffix3DNow
[] = {
15320 /* 00 */ NULL
, NULL
, NULL
, NULL
,
15321 /* 04 */ NULL
, NULL
, NULL
, NULL
,
15322 /* 08 */ NULL
, NULL
, NULL
, NULL
,
15323 /* 0C */ "pi2fw", "pi2fd", NULL
, NULL
,
15324 /* 10 */ NULL
, NULL
, NULL
, NULL
,
15325 /* 14 */ NULL
, NULL
, NULL
, NULL
,
15326 /* 18 */ NULL
, NULL
, NULL
, NULL
,
15327 /* 1C */ "pf2iw", "pf2id", NULL
, NULL
,
15328 /* 20 */ NULL
, NULL
, NULL
, NULL
,
15329 /* 24 */ NULL
, NULL
, NULL
, NULL
,
15330 /* 28 */ NULL
, NULL
, NULL
, NULL
,
15331 /* 2C */ NULL
, NULL
, NULL
, NULL
,
15332 /* 30 */ NULL
, NULL
, NULL
, NULL
,
15333 /* 34 */ NULL
, NULL
, NULL
, NULL
,
15334 /* 38 */ NULL
, NULL
, NULL
, NULL
,
15335 /* 3C */ NULL
, NULL
, NULL
, NULL
,
15336 /* 40 */ NULL
, NULL
, NULL
, NULL
,
15337 /* 44 */ NULL
, NULL
, NULL
, NULL
,
15338 /* 48 */ NULL
, NULL
, NULL
, NULL
,
15339 /* 4C */ NULL
, NULL
, NULL
, NULL
,
15340 /* 50 */ NULL
, NULL
, NULL
, NULL
,
15341 /* 54 */ NULL
, NULL
, NULL
, NULL
,
15342 /* 58 */ NULL
, NULL
, NULL
, NULL
,
15343 /* 5C */ NULL
, NULL
, NULL
, NULL
,
15344 /* 60 */ NULL
, NULL
, NULL
, NULL
,
15345 /* 64 */ NULL
, NULL
, NULL
, NULL
,
15346 /* 68 */ NULL
, NULL
, NULL
, NULL
,
15347 /* 6C */ NULL
, NULL
, NULL
, NULL
,
15348 /* 70 */ NULL
, NULL
, NULL
, NULL
,
15349 /* 74 */ NULL
, NULL
, NULL
, NULL
,
15350 /* 78 */ NULL
, NULL
, NULL
, NULL
,
15351 /* 7C */ NULL
, NULL
, NULL
, NULL
,
15352 /* 80 */ NULL
, NULL
, NULL
, NULL
,
15353 /* 84 */ NULL
, NULL
, NULL
, NULL
,
15354 /* 88 */ NULL
, NULL
, "pfnacc", NULL
,
15355 /* 8C */ NULL
, NULL
, "pfpnacc", NULL
,
15356 /* 90 */ "pfcmpge", NULL
, NULL
, NULL
,
15357 /* 94 */ "pfmin", NULL
, "pfrcp", "pfrsqrt",
15358 /* 98 */ NULL
, NULL
, "pfsub", NULL
,
15359 /* 9C */ NULL
, NULL
, "pfadd", NULL
,
15360 /* A0 */ "pfcmpgt", NULL
, NULL
, NULL
,
15361 /* A4 */ "pfmax", NULL
, "pfrcpit1", "pfrsqit1",
15362 /* A8 */ NULL
, NULL
, "pfsubr", NULL
,
15363 /* AC */ NULL
, NULL
, "pfacc", NULL
,
15364 /* B0 */ "pfcmpeq", NULL
, NULL
, NULL
,
15365 /* B4 */ "pfmul", NULL
, "pfrcpit2", "pmulhrw",
15366 /* B8 */ NULL
, NULL
, NULL
, "pswapd",
15367 /* BC */ NULL
, NULL
, NULL
, "pavgusb",
15368 /* C0 */ NULL
, NULL
, NULL
, NULL
,
15369 /* C4 */ NULL
, NULL
, NULL
, NULL
,
15370 /* C8 */ NULL
, NULL
, NULL
, NULL
,
15371 /* CC */ NULL
, NULL
, NULL
, NULL
,
15372 /* D0 */ NULL
, NULL
, NULL
, NULL
,
15373 /* D4 */ NULL
, NULL
, NULL
, NULL
,
15374 /* D8 */ NULL
, NULL
, NULL
, NULL
,
15375 /* DC */ NULL
, NULL
, NULL
, NULL
,
15376 /* E0 */ NULL
, NULL
, NULL
, NULL
,
15377 /* E4 */ NULL
, NULL
, NULL
, NULL
,
15378 /* E8 */ NULL
, NULL
, NULL
, NULL
,
15379 /* EC */ NULL
, NULL
, NULL
, NULL
,
15380 /* F0 */ NULL
, NULL
, NULL
, NULL
,
15381 /* F4 */ NULL
, NULL
, NULL
, NULL
,
15382 /* F8 */ NULL
, NULL
, NULL
, NULL
,
15383 /* FC */ NULL
, NULL
, NULL
, NULL
,
15387 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15389 const char *mnemonic
;
15391 FETCH_DATA (the_info
, codep
+ 1);
15392 /* AMD 3DNow! instructions are specified by an opcode suffix in the
15393 place where an 8-bit immediate would normally go. ie. the last
15394 byte of the instruction. */
15395 obufp
= mnemonicendp
;
15396 mnemonic
= Suffix3DNow
[*codep
++ & 0xff];
15398 oappend (mnemonic
);
15401 /* Since a variable sized modrm/sib chunk is between the start
15402 of the opcode (0x0f0f) and the opcode suffix, we need to do
15403 all the modrm processing first, and don't know until now that
15404 we have a bad opcode. This necessitates some cleaning up. */
15405 op_out
[0][0] = '\0';
15406 op_out
[1][0] = '\0';
15409 mnemonicendp
= obufp
;
15412 static struct op simd_cmp_op
[] =
15414 { STRING_COMMA_LEN ("eq") },
15415 { STRING_COMMA_LEN ("lt") },
15416 { STRING_COMMA_LEN ("le") },
15417 { STRING_COMMA_LEN ("unord") },
15418 { STRING_COMMA_LEN ("neq") },
15419 { STRING_COMMA_LEN ("nlt") },
15420 { STRING_COMMA_LEN ("nle") },
15421 { STRING_COMMA_LEN ("ord") }
15425 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15427 unsigned int cmp_type
;
15429 FETCH_DATA (the_info
, codep
+ 1);
15430 cmp_type
= *codep
++ & 0xff;
15431 if (cmp_type
< ARRAY_SIZE (simd_cmp_op
))
15434 char *p
= mnemonicendp
- 2;
15438 sprintf (p
, "%s%s", simd_cmp_op
[cmp_type
].name
, suffix
);
15439 mnemonicendp
+= simd_cmp_op
[cmp_type
].len
;
15443 /* We have a reserved extension byte. Output it directly. */
15444 scratchbuf
[0] = '$';
15445 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
15446 oappend_maybe_intel (scratchbuf
);
15447 scratchbuf
[0] = '\0';
15452 OP_Mwait (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
15454 /* mwait %eax,%ecx / mwaitx %eax,%ecx,%ebx */
15457 strcpy (op_out
[0], names32
[0]);
15458 strcpy (op_out
[1], names32
[1]);
15459 if (bytemode
== eBX_reg
)
15460 strcpy (op_out
[2], names32
[3]);
15461 two_source_ops
= 1;
15463 /* Skip mod/rm byte. */
15469 OP_Monitor (int bytemode ATTRIBUTE_UNUSED
,
15470 int sizeflag ATTRIBUTE_UNUSED
)
15472 /* monitor %{e,r,}ax,%ecx,%edx" */
15475 const char **names
= (address_mode
== mode_64bit
15476 ? names64
: names32
);
15478 if (prefixes
& PREFIX_ADDR
)
15480 /* Remove "addr16/addr32". */
15481 all_prefixes
[last_addr_prefix
] = 0;
15482 names
= (address_mode
!= mode_32bit
15483 ? names32
: names16
);
15484 used_prefixes
|= PREFIX_ADDR
;
15486 else if (address_mode
== mode_16bit
)
15488 strcpy (op_out
[0], names
[0]);
15489 strcpy (op_out
[1], names32
[1]);
15490 strcpy (op_out
[2], names32
[2]);
15491 two_source_ops
= 1;
15493 /* Skip mod/rm byte. */
15501 /* Throw away prefixes and 1st. opcode byte. */
15502 codep
= insn_codep
+ 1;
15507 REP_Fixup (int bytemode
, int sizeflag
)
15509 /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
15511 if (prefixes
& PREFIX_REPZ
)
15512 all_prefixes
[last_repz_prefix
] = REP_PREFIX
;
15519 OP_IMREG (bytemode
, sizeflag
);
15522 OP_ESreg (bytemode
, sizeflag
);
15525 OP_DSreg (bytemode
, sizeflag
);
15534 SEP_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15536 if ( isa64
!= amd64
)
15541 mnemonicendp
= obufp
;
15545 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
15549 BND_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15551 if (prefixes
& PREFIX_REPNZ
)
15552 all_prefixes
[last_repnz_prefix
] = BND_PREFIX
;
15555 /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
15559 NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED
,
15560 int sizeflag ATTRIBUTE_UNUSED
)
15562 if (active_seg_prefix
== PREFIX_DS
15563 && (address_mode
!= mode_64bit
|| last_data_prefix
< 0))
15565 /* NOTRACK prefix is only valid on indirect branch instructions.
15566 NB: DATA prefix is unsupported for Intel64. */
15567 active_seg_prefix
= 0;
15568 all_prefixes
[last_seg_prefix
] = NOTRACK_PREFIX
;
15572 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
15573 "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
15577 HLE_Fixup1 (int bytemode
, int sizeflag
)
15580 && (prefixes
& PREFIX_LOCK
) != 0)
15582 if (prefixes
& PREFIX_REPZ
)
15583 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
15584 if (prefixes
& PREFIX_REPNZ
)
15585 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
15588 OP_E (bytemode
, sizeflag
);
15591 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
15592 "xacquire"/"xrelease" for memory operand. No check for LOCK prefix.
15596 HLE_Fixup2 (int bytemode
, int sizeflag
)
15598 if (modrm
.mod
!= 3)
15600 if (prefixes
& PREFIX_REPZ
)
15601 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
15602 if (prefixes
& PREFIX_REPNZ
)
15603 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
15606 OP_E (bytemode
, sizeflag
);
15609 /* Similar to OP_E. But the 0xf3 prefixes should be displayed as
15610 "xrelease" for memory operand. No check for LOCK prefix. */
15613 HLE_Fixup3 (int bytemode
, int sizeflag
)
15616 && last_repz_prefix
> last_repnz_prefix
15617 && (prefixes
& PREFIX_REPZ
) != 0)
15618 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
15620 OP_E (bytemode
, sizeflag
);
15624 CMPXCHG8B_Fixup (int bytemode
, int sizeflag
)
15629 /* Change cmpxchg8b to cmpxchg16b. */
15630 char *p
= mnemonicendp
- 2;
15631 mnemonicendp
= stpcpy (p
, "16b");
15634 else if ((prefixes
& PREFIX_LOCK
) != 0)
15636 if (prefixes
& PREFIX_REPZ
)
15637 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
15638 if (prefixes
& PREFIX_REPNZ
)
15639 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
15642 OP_M (bytemode
, sizeflag
);
15646 XMM_Fixup (int reg
, int sizeflag ATTRIBUTE_UNUSED
)
15648 const char **names
;
15652 switch (vex
.length
)
15666 oappend (names
[reg
]);
15670 CRC32_Fixup (int bytemode
, int sizeflag
)
15672 /* Add proper suffix to "crc32". */
15673 char *p
= mnemonicendp
;
15692 if (sizeflag
& DFLAG
)
15696 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15700 oappend (INTERNAL_DISASSEMBLER_ERROR
);
15707 if (modrm
.mod
== 3)
15711 /* Skip mod/rm byte. */
15716 add
= (rex
& REX_B
) ? 8 : 0;
15717 if (bytemode
== b_mode
)
15721 oappend (names8rex
[modrm
.rm
+ add
]);
15723 oappend (names8
[modrm
.rm
+ add
]);
15729 oappend (names64
[modrm
.rm
+ add
]);
15730 else if ((prefixes
& PREFIX_DATA
))
15731 oappend (names16
[modrm
.rm
+ add
]);
15733 oappend (names32
[modrm
.rm
+ add
]);
15737 OP_E (bytemode
, sizeflag
);
15741 FXSAVE_Fixup (int bytemode
, int sizeflag
)
15743 /* Add proper suffix to "fxsave" and "fxrstor". */
15747 char *p
= mnemonicendp
;
15753 OP_M (bytemode
, sizeflag
);
15757 PCMPESTR_Fixup (int bytemode
, int sizeflag
)
15759 /* Add proper suffix to "{,v}pcmpestr{i,m}". */
15762 char *p
= mnemonicendp
;
15767 else if (sizeflag
& SUFFIX_ALWAYS
)
15774 OP_EX (bytemode
, sizeflag
);
15777 /* Display the destination register operand for instructions with
15781 OP_VEX (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
15784 const char **names
;
15792 reg
= vex
.register_specifier
;
15793 vex
.register_specifier
= 0;
15794 if (address_mode
!= mode_64bit
)
15796 else if (vex
.evex
&& !vex
.v
)
15799 if (bytemode
== vex_scalar_mode
)
15801 oappend (names_xmm
[reg
]);
15805 switch (vex
.length
)
15812 case vex_vsib_q_w_dq_mode
:
15813 case vex_vsib_q_w_d_mode
:
15829 names
= names_mask
;
15843 case vex_vsib_q_w_dq_mode
:
15844 case vex_vsib_q_w_d_mode
:
15845 names
= vex
.w
? names_ymm
: names_xmm
;
15854 names
= names_mask
;
15857 /* See PR binutils/20893 for a reproducer. */
15869 oappend (names
[reg
]);
15872 /* Get the VEX immediate byte without moving codep. */
15874 static unsigned char
15875 get_vex_imm8 (int sizeflag
, int opnum
)
15877 int bytes_before_imm
= 0;
15879 if (modrm
.mod
!= 3)
15881 /* There are SIB/displacement bytes. */
15882 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
15884 /* 32/64 bit address mode */
15885 int base
= modrm
.rm
;
15887 /* Check SIB byte. */
15890 FETCH_DATA (the_info
, codep
+ 1);
15892 /* When decoding the third source, don't increase
15893 bytes_before_imm as this has already been incremented
15894 by one in OP_E_memory while decoding the second
15897 bytes_before_imm
++;
15900 /* Don't increase bytes_before_imm when decoding the third source,
15901 it has already been incremented by OP_E_memory while decoding
15902 the second source operand. */
15908 /* When modrm.rm == 5 or modrm.rm == 4 and base in
15909 SIB == 5, there is a 4 byte displacement. */
15911 /* No displacement. */
15913 /* Fall through. */
15915 /* 4 byte displacement. */
15916 bytes_before_imm
+= 4;
15919 /* 1 byte displacement. */
15920 bytes_before_imm
++;
15927 /* 16 bit address mode */
15928 /* Don't increase bytes_before_imm when decoding the third source,
15929 it has already been incremented by OP_E_memory while decoding
15930 the second source operand. */
15936 /* When modrm.rm == 6, there is a 2 byte displacement. */
15938 /* No displacement. */
15940 /* Fall through. */
15942 /* 2 byte displacement. */
15943 bytes_before_imm
+= 2;
15946 /* 1 byte displacement: when decoding the third source,
15947 don't increase bytes_before_imm as this has already
15948 been incremented by one in OP_E_memory while decoding
15949 the second source operand. */
15951 bytes_before_imm
++;
15959 FETCH_DATA (the_info
, codep
+ bytes_before_imm
+ 1);
15960 return codep
[bytes_before_imm
];
15964 OP_EX_VexReg (int bytemode
, int sizeflag
, int reg
)
15966 const char **names
;
15968 if (reg
== -1 && modrm
.mod
!= 3)
15970 OP_E_memory (bytemode
, sizeflag
);
15982 if (address_mode
!= mode_64bit
)
15986 switch (vex
.length
)
15997 oappend (names
[reg
]);
16001 OP_EX_VexImmW (int bytemode
, int sizeflag
)
16004 static unsigned char vex_imm8
;
16006 if (vex_w_done
== 0)
16010 /* Skip mod/rm byte. */
16014 vex_imm8
= get_vex_imm8 (sizeflag
, 0);
16017 reg
= vex_imm8
>> 4;
16019 OP_EX_VexReg (bytemode
, sizeflag
, reg
);
16021 else if (vex_w_done
== 1)
16026 reg
= vex_imm8
>> 4;
16028 OP_EX_VexReg (bytemode
, sizeflag
, reg
);
16032 /* Output the imm8 directly. */
16033 scratchbuf
[0] = '$';
16034 print_operand_value (scratchbuf
+ 1, 1, vex_imm8
& 0xf);
16035 oappend_maybe_intel (scratchbuf
);
16036 scratchbuf
[0] = '\0';
16042 OP_Vex_2src (int bytemode
, int sizeflag
)
16044 if (modrm
.mod
== 3)
16046 int reg
= modrm
.rm
;
16050 oappend (names_xmm
[reg
]);
16055 && (bytemode
== v_mode
|| bytemode
== v_swap_mode
))
16057 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
16058 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16060 OP_E (bytemode
, sizeflag
);
16065 OP_Vex_2src_1 (int bytemode
, int sizeflag
)
16067 if (modrm
.mod
== 3)
16069 /* Skip mod/rm byte. */
16076 unsigned int reg
= vex
.register_specifier
;
16077 vex
.register_specifier
= 0;
16079 if (address_mode
!= mode_64bit
)
16081 oappend (names_xmm
[reg
]);
16084 OP_Vex_2src (bytemode
, sizeflag
);
16088 OP_Vex_2src_2 (int bytemode
, int sizeflag
)
16091 OP_Vex_2src (bytemode
, sizeflag
);
16094 unsigned int reg
= vex
.register_specifier
;
16095 vex
.register_specifier
= 0;
16097 if (address_mode
!= mode_64bit
)
16099 oappend (names_xmm
[reg
]);
16104 OP_EX_VexW (int bytemode
, int sizeflag
)
16110 /* Skip mod/rm byte. */
16115 reg
= get_vex_imm8 (sizeflag
, 0) >> 4;
16120 reg
= get_vex_imm8 (sizeflag
, 1) >> 4;
16123 OP_EX_VexReg (bytemode
, sizeflag
, reg
);
16131 OP_REG_VexI4 (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
16134 const char **names
;
16136 FETCH_DATA (the_info
, codep
+ 1);
16139 if (bytemode
!= x_mode
)
16143 if (address_mode
!= mode_64bit
)
16146 switch (vex
.length
)
16157 oappend (names
[reg
]);
16161 OP_XMM_VexW (int bytemode
, int sizeflag
)
16163 /* Turn off the REX.W bit since it is used for swapping operands
16166 OP_XMM (bytemode
, sizeflag
);
16170 OP_EX_Vex (int bytemode
, int sizeflag
)
16172 if (modrm
.mod
!= 3)
16174 OP_EX (bytemode
, sizeflag
);
16178 OP_XMM_Vex (int bytemode
, int sizeflag
)
16180 if (modrm
.mod
!= 3)
16182 OP_XMM (bytemode
, sizeflag
);
16185 static struct op vex_cmp_op
[] =
16187 { STRING_COMMA_LEN ("eq") },
16188 { STRING_COMMA_LEN ("lt") },
16189 { STRING_COMMA_LEN ("le") },
16190 { STRING_COMMA_LEN ("unord") },
16191 { STRING_COMMA_LEN ("neq") },
16192 { STRING_COMMA_LEN ("nlt") },
16193 { STRING_COMMA_LEN ("nle") },
16194 { STRING_COMMA_LEN ("ord") },
16195 { STRING_COMMA_LEN ("eq_uq") },
16196 { STRING_COMMA_LEN ("nge") },
16197 { STRING_COMMA_LEN ("ngt") },
16198 { STRING_COMMA_LEN ("false") },
16199 { STRING_COMMA_LEN ("neq_oq") },
16200 { STRING_COMMA_LEN ("ge") },
16201 { STRING_COMMA_LEN ("gt") },
16202 { STRING_COMMA_LEN ("true") },
16203 { STRING_COMMA_LEN ("eq_os") },
16204 { STRING_COMMA_LEN ("lt_oq") },
16205 { STRING_COMMA_LEN ("le_oq") },
16206 { STRING_COMMA_LEN ("unord_s") },
16207 { STRING_COMMA_LEN ("neq_us") },
16208 { STRING_COMMA_LEN ("nlt_uq") },
16209 { STRING_COMMA_LEN ("nle_uq") },
16210 { STRING_COMMA_LEN ("ord_s") },
16211 { STRING_COMMA_LEN ("eq_us") },
16212 { STRING_COMMA_LEN ("nge_uq") },
16213 { STRING_COMMA_LEN ("ngt_uq") },
16214 { STRING_COMMA_LEN ("false_os") },
16215 { STRING_COMMA_LEN ("neq_os") },
16216 { STRING_COMMA_LEN ("ge_oq") },
16217 { STRING_COMMA_LEN ("gt_oq") },
16218 { STRING_COMMA_LEN ("true_us") },
16222 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16224 unsigned int cmp_type
;
16226 FETCH_DATA (the_info
, codep
+ 1);
16227 cmp_type
= *codep
++ & 0xff;
16228 if (cmp_type
< ARRAY_SIZE (vex_cmp_op
))
16231 char *p
= mnemonicendp
- 2;
16235 sprintf (p
, "%s%s", vex_cmp_op
[cmp_type
].name
, suffix
);
16236 mnemonicendp
+= vex_cmp_op
[cmp_type
].len
;
16240 /* We have a reserved extension byte. Output it directly. */
16241 scratchbuf
[0] = '$';
16242 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
16243 oappend_maybe_intel (scratchbuf
);
16244 scratchbuf
[0] = '\0';
16249 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED
,
16250 int sizeflag ATTRIBUTE_UNUSED
)
16252 unsigned int cmp_type
;
16257 FETCH_DATA (the_info
, codep
+ 1);
16258 cmp_type
= *codep
++ & 0xff;
16259 /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
16260 If it's the case, print suffix, otherwise - print the immediate. */
16261 if (cmp_type
< ARRAY_SIZE (simd_cmp_op
)
16266 char *p
= mnemonicendp
- 2;
16268 /* vpcmp* can have both one- and two-lettered suffix. */
16282 sprintf (p
, "%s%s", simd_cmp_op
[cmp_type
].name
, suffix
);
16283 mnemonicendp
+= simd_cmp_op
[cmp_type
].len
;
16287 /* We have a reserved extension byte. Output it directly. */
16288 scratchbuf
[0] = '$';
16289 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
16290 oappend_maybe_intel (scratchbuf
);
16291 scratchbuf
[0] = '\0';
16295 static const struct op xop_cmp_op
[] =
16297 { STRING_COMMA_LEN ("lt") },
16298 { STRING_COMMA_LEN ("le") },
16299 { STRING_COMMA_LEN ("gt") },
16300 { STRING_COMMA_LEN ("ge") },
16301 { STRING_COMMA_LEN ("eq") },
16302 { STRING_COMMA_LEN ("neq") },
16303 { STRING_COMMA_LEN ("false") },
16304 { STRING_COMMA_LEN ("true") }
16308 VPCOM_Fixup (int bytemode ATTRIBUTE_UNUSED
,
16309 int sizeflag ATTRIBUTE_UNUSED
)
16311 unsigned int cmp_type
;
16313 FETCH_DATA (the_info
, codep
+ 1);
16314 cmp_type
= *codep
++ & 0xff;
16315 if (cmp_type
< ARRAY_SIZE (xop_cmp_op
))
16318 char *p
= mnemonicendp
- 2;
16320 /* vpcom* can have both one- and two-lettered suffix. */
16334 sprintf (p
, "%s%s", xop_cmp_op
[cmp_type
].name
, suffix
);
16335 mnemonicendp
+= xop_cmp_op
[cmp_type
].len
;
16339 /* We have a reserved extension byte. Output it directly. */
16340 scratchbuf
[0] = '$';
16341 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
16342 oappend_maybe_intel (scratchbuf
);
16343 scratchbuf
[0] = '\0';
16347 static const struct op pclmul_op
[] =
16349 { STRING_COMMA_LEN ("lql") },
16350 { STRING_COMMA_LEN ("hql") },
16351 { STRING_COMMA_LEN ("lqh") },
16352 { STRING_COMMA_LEN ("hqh") }
16356 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED
,
16357 int sizeflag ATTRIBUTE_UNUSED
)
16359 unsigned int pclmul_type
;
16361 FETCH_DATA (the_info
, codep
+ 1);
16362 pclmul_type
= *codep
++ & 0xff;
16363 switch (pclmul_type
)
16374 if (pclmul_type
< ARRAY_SIZE (pclmul_op
))
16377 char *p
= mnemonicendp
- 3;
16382 sprintf (p
, "%s%s", pclmul_op
[pclmul_type
].name
, suffix
);
16383 mnemonicendp
+= pclmul_op
[pclmul_type
].len
;
16387 /* We have a reserved extension byte. Output it directly. */
16388 scratchbuf
[0] = '$';
16389 print_operand_value (scratchbuf
+ 1, 1, pclmul_type
);
16390 oappend_maybe_intel (scratchbuf
);
16391 scratchbuf
[0] = '\0';
16396 MOVBE_Fixup (int bytemode
, int sizeflag
)
16398 /* Add proper suffix to "movbe". */
16399 char *p
= mnemonicendp
;
16408 if (sizeflag
& SUFFIX_ALWAYS
)
16414 if (sizeflag
& DFLAG
)
16418 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16423 oappend (INTERNAL_DISASSEMBLER_ERROR
);
16430 OP_M (bytemode
, sizeflag
);
16434 MOVSXD_Fixup (int bytemode
, int sizeflag
)
16436 /* Add proper suffix to "movsxd". */
16437 char *p
= mnemonicendp
;
16462 oappend (INTERNAL_DISASSEMBLER_ERROR
);
16469 OP_E (bytemode
, sizeflag
);
16473 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16476 const char **names
;
16478 /* Skip mod/rm byte. */
16492 oappend (names
[reg
]);
16496 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16498 const char **names
;
16499 unsigned int reg
= vex
.register_specifier
;
16500 vex
.register_specifier
= 0;
16507 if (address_mode
!= mode_64bit
)
16509 oappend (names
[reg
]);
16513 OP_Mask (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
16516 || (bytemode
!= mask_mode
&& bytemode
!= mask_bd_mode
))
16520 if ((rex
& REX_R
) != 0 || !vex
.r
)
16526 oappend (names_mask
[modrm
.reg
]);
16530 OP_Rounding (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
16532 if (modrm
.mod
== 3 && vex
.b
)
16535 case evex_rounding_64_mode
:
16536 if (address_mode
!= mode_64bit
)
16541 /* Fall through. */
16542 case evex_rounding_mode
:
16543 oappend (names_rounding
[vex
.ll
]);
16545 case evex_sae_mode
: