1 // SPDX-License-Identifier: MIT
3 * Copyright 2022 Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
14 #include <side/trace.h>
15 #include <rseq/rseq.h>
17 #define SIDE_CACHE_LINE_SIZE 256
19 struct side_rcu_percpu_count
{
24 } __attribute__((__aligned__(SIDE_CACHE_LINE_SIZE
)));
26 struct side_rcu_cpu_gp_state
{
27 struct side_rcu_percpu_count count
[2];
30 struct side_rcu_gp_state
{
31 struct side_rcu_cpu_gp_state
*percpu_state
;
34 pthread_mutex_t gp_lock
;
37 //TODO: implement wait/wakeup for grace period using sys_futex
39 unsigned int side_rcu_read_begin(struct side_rcu_gp_state
*gp_state
)
41 unsigned int period
= __atomic_load_n(&gp_state
->period
, __ATOMIC_RELAXED
);
42 struct side_rcu_cpu_gp_state
*cpu_gp_state
;
45 if (side_likely(rseq_offset
> 0)) {
46 cpu
= rseq_cpu_start();
47 cpu_gp_state
= &gp_state
->percpu_state
[cpu
];
48 if (!rseq_addv((intptr_t *)&cpu_gp_state
->count
[period
].rseq_begin
, 1, cpu
))
52 if (side_unlikely(cpu
< 0))
54 cpu_gp_state
= &gp_state
->percpu_state
[cpu
];
55 (void) __atomic_add_fetch(&cpu_gp_state
->count
[period
].begin
, 1, __ATOMIC_RELAXED
);
58 * This memory barrier (A) ensures that the contents of the
59 * read-side critical section does not leak before the "begin"
60 * counter increment. It pairs with memory barriers (D) and (E).
62 * This memory barrier (A) also ensures that the "begin"
63 * increment is before the "end" increment. It pairs with memory
64 * barrier (C). It is redundant with memory barrier (B) for that
72 void side_rcu_read_end(struct side_rcu_gp_state
*gp_state
, unsigned int period
)
74 struct side_rcu_cpu_gp_state
*cpu_gp_state
;
78 * This memory barrier (B) ensures that the contents of the
79 * read-side critical section does not leak after the "end"
80 * counter increment. It pairs with memory barriers (D) and (E).
82 * This memory barrier (B) also ensures that the "begin"
83 * increment is before the "end" increment. It pairs with memory
84 * barrier (C). It is redundant with memory barrier (A) for that
89 if (side_likely(rseq_offset
> 0)) {
90 cpu
= rseq_cpu_start();
91 cpu_gp_state
= &gp_state
->percpu_state
[cpu
];
92 if (!rseq_addv((intptr_t *)&cpu_gp_state
->count
[period
].rseq_end
, 1, cpu
))
96 if (side_unlikely(cpu
< 0))
98 cpu_gp_state
= &gp_state
->percpu_state
[cpu
];
99 (void) __atomic_add_fetch(&cpu_gp_state
->count
[period
].end
, 1, __ATOMIC_RELAXED
);
102 #define side_rcu_dereference(p) \
105 __typeof__(p) _____side_v = __atomic_load_n(&(p), __ATOMIC_CONSUME); \
109 #define side_rcu_assign_pointer(p, v) __atomic_store_n(&(p), v, __ATOMIC_RELEASE); \
111 void side_rcu_wait_grace_period(struct side_rcu_gp_state *gp_state) __attribute__((visibility("hidden")));
112 void side_rcu_gp_init(struct side_rcu_gp_state
*rcu_gp
) __attribute__((visibility("hidden")));
113 void side_rcu_gp_exit(struct side_rcu_gp_state
*rcu_gp
) __attribute__((visibility("hidden")));
115 #endif /* _SIDE_RCU_H */