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ARCv2: perf: Finally introduce HS perf unit
[deliverable/linux.git] / arch / arc / include / asm / perf_event.h
CommitLineData
9c57564e 1/*
0dd450fe
MJ		 2 * Linux performance counter support for ARC
3 *
fb7c5725 4 * Copyright (C) 2014-2015 Synopsys, Inc. (www.synopsys.com)
0dd450fe 5 * Copyright (C) 2011-2013 Synopsys, Inc. (www.synopsys.com)
9c57564e
VG		 6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 */
12
13#ifndef __ASM_PERF_EVENT_H
14#define __ASM_PERF_EVENT_H
15
fb7c5725
VG		 16/* Max number of counters that PCT block may ever have */
17#define ARC_PERF_MAX_COUNTERS 32
0dd450fe
MJ		 18
19#define ARC_REG_CC_BUILD 0xF6
20#define ARC_REG_CC_INDEX 0x240
21#define ARC_REG_CC_NAME0 0x241
22#define ARC_REG_CC_NAME1 0x242
23
24#define ARC_REG_PCT_BUILD 0xF5
25#define ARC_REG_PCT_COUNTL 0x250
26#define ARC_REG_PCT_COUNTH 0x251
27#define ARC_REG_PCT_SNAPL 0x252
28#define ARC_REG_PCT_SNAPH 0x253
29#define ARC_REG_PCT_CONFIG 0x254
30#define ARC_REG_PCT_CONTROL 0x255
31#define ARC_REG_PCT_INDEX 0x256
36481cf7
AB		 32#define ARC_REG_PCT_INT_CNTL 0x25C
33#define ARC_REG_PCT_INT_CNTH 0x25D
34#define ARC_REG_PCT_INT_CTRL 0x25E
35#define ARC_REG_PCT_INT_ACT 0x25F
0dd450fe 36
e6b1d126
AB		 37#define ARC_REG_PCT_CONFIG_USER (1 << 18) /* count in user mode */
38#define ARC_REG_PCT_CONFIG_KERN (1 << 19) /* count in kernel mode */
39
0dd450fe
MJ		 40#define ARC_REG_PCT_CONTROL_CC (1 << 16) /* clear counts */
41#define ARC_REG_PCT_CONTROL_SN (1 << 17) /* snapshot */
42
43struct arc_reg_pct_build {
44#ifdef CONFIG_CPU_BIG_ENDIAN
36481cf7 45 unsigned int m:8, c:8, r:5, i:1, s:2, v:8;
0dd450fe 46#else
36481cf7 47 unsigned int v:8, s:2, i:1, r:5, c:8, m:8;
0dd450fe
MJ		 48#endif
49};
50
51struct arc_reg_cc_build {
52#ifdef CONFIG_CPU_BIG_ENDIAN
53 unsigned int c:16, r:8, v:8;
54#else
55 unsigned int v:8, r:8, c:16;
56#endif
57};
58
59#define PERF_COUNT_ARC_DCLM (PERF_COUNT_HW_MAX + 0)
60#define PERF_COUNT_ARC_DCSM (PERF_COUNT_HW_MAX + 1)
61#define PERF_COUNT_ARC_ICM (PERF_COUNT_HW_MAX + 2)
62#define PERF_COUNT_ARC_BPOK (PERF_COUNT_HW_MAX + 3)
63#define PERF_COUNT_ARC_EDTLB (PERF_COUNT_HW_MAX + 4)
64#define PERF_COUNT_ARC_EITLB (PERF_COUNT_HW_MAX + 5)
0a8a4767
VG		 65#define PERF_COUNT_ARC_LDC (PERF_COUNT_HW_MAX + 6)
66#define PERF_COUNT_ARC_STC (PERF_COUNT_HW_MAX + 7)
67
68#define PERF_COUNT_ARC_HW_MAX (PERF_COUNT_HW_MAX + 8)
0dd450fe
MJ		 69
70/*
bde80c23 71 * Some ARC pct quirks:
0dd450fe
MJ		 72 *
73 * PERF_COUNT_HW_STALLED_CYCLES_BACKEND
74 * PERF_COUNT_HW_STALLED_CYCLES_FRONTEND
75 * The ARC 700 can either measure stalls per pipeline stage, or all stalls
76 * combined; for now we assign all stalls to STALLED_CYCLES_BACKEND
77 * and all pipeline flushes (e.g. caused by mispredicts, etc.) to
78 * STALLED_CYCLES_FRONTEND.
79 *
80 * We could start multiple performance counters and combine everything
81 * afterwards, but that makes it complicated.
82 *
83 * Note that I$ cache misses aren't counted by either of the two!
84 */
85
bde80c23
VG		 86/*
87 * ARC PCT has hardware conditions with fixed "names" but variable "indexes"
88 * (based on a specific RTL build)
89 * Below is the static map between perf generic/arc specific event_id and
90 * h/w condition names.
91 * At the time of probe, we loop thru each index and find it's name to
92 * complete the mapping of perf event_id to h/w index as latter is needed
93 * to program the counter really
94 */
0dd450fe 95static const char * const arc_pmu_ev_hw_map[] = {
bde80c23 96 /* count cycles */
0dd450fe
MJ		 97 [PERF_COUNT_HW_CPU_CYCLES] = "crun",
98 [PERF_COUNT_HW_REF_CPU_CYCLES] = "crun",
99 [PERF_COUNT_HW_BUS_CYCLES] = "crun",
bde80c23 100
0dd450fe
MJ		 101 [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = "bflush",
102 [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = "bstall",
bde80c23
VG		 103
104 /* counts condition */
105 [PERF_COUNT_HW_INSTRUCTIONS] = "iall",
09074950 106 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = "ijmp", /* Excludes ZOL jumps */
bde80c23 107 [PERF_COUNT_ARC_BPOK] = "bpok", /* NP-NT, PT-T, PNT-NT */
9b28829d
VG		 108#ifdef CONFIG_ISA_ARCV2
109 [PERF_COUNT_HW_BRANCH_MISSES] = "bpmp",
110#else
bde80c23 111 [PERF_COUNT_HW_BRANCH_MISSES] = "bpfail", /* NP-T, PT-NT, PNT-T */
9b28829d 112#endif
0a8a4767
VG		 113 [PERF_COUNT_ARC_LDC] = "imemrdc", /* Instr: mem read cached */
114 [PERF_COUNT_ARC_STC] = "imemwrc", /* Instr: mem write cached */
115
bde80c23
VG		 116 [PERF_COUNT_ARC_DCLM] = "dclm", /* D-cache Load Miss */
117 [PERF_COUNT_ARC_DCSM] = "dcsm", /* D-cache Store Miss */
118 [PERF_COUNT_ARC_ICM] = "icm", /* I-cache Miss */
119 [PERF_COUNT_ARC_EDTLB] = "edtlb", /* D-TLB Miss */
120 [PERF_COUNT_ARC_EITLB] = "eitlb", /* I-TLB Miss */
0dd450fe
MJ		 121};
122
123#define C(_x) PERF_COUNT_HW_CACHE_##_x
124#define CACHE_OP_UNSUPPORTED 0xffff
125
126static const unsigned arc_pmu_cache_map[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
127 [C(L1D)] = {
128 [C(OP_READ)] = {
0a8a4767 129 [C(RESULT_ACCESS)] = PERF_COUNT_ARC_LDC,
0dd450fe
MJ		 130 [C(RESULT_MISS)] = PERF_COUNT_ARC_DCLM,
131 },
132 [C(OP_WRITE)] = {
0a8a4767 133 [C(RESULT_ACCESS)] = PERF_COUNT_ARC_STC,
0dd450fe
MJ		 134 [C(RESULT_MISS)] = PERF_COUNT_ARC_DCSM,
135 },
136 [C(OP_PREFETCH)] = {
137 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
138 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
139 },
140 },
141 [C(L1I)] = {
142 [C(OP_READ)] = {
0a8a4767 143 [C(RESULT_ACCESS)] = PERF_COUNT_HW_INSTRUCTIONS,
0dd450fe
MJ		 144 [C(RESULT_MISS)] = PERF_COUNT_ARC_ICM,
145 },
146 [C(OP_WRITE)] = {
147 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
148 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
149 },
150 [C(OP_PREFETCH)] = {
151 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
152 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
153 },
154 },
155 [C(LL)] = {
156 [C(OP_READ)] = {
157 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
158 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
159 },
160 [C(OP_WRITE)] = {
161 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
162 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
163 },
164 [C(OP_PREFETCH)] = {
165 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
166 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
167 },
168 },
169 [C(DTLB)] = {
170 [C(OP_READ)] = {
0a8a4767 171 [C(RESULT_ACCESS)] = PERF_COUNT_ARC_LDC,
0dd450fe
MJ		 172 [C(RESULT_MISS)] = PERF_COUNT_ARC_EDTLB,
173 },
0a8a4767 174 /* DTLB LD/ST Miss not segregated by h/w*/
0dd450fe
MJ		 175 [C(OP_WRITE)] = {
176 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
177 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
178 },
179 [C(OP_PREFETCH)] = {
180 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
181 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
182 },
183 },
184 [C(ITLB)] = {
185 [C(OP_READ)] = {
186 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
187 [C(RESULT_MISS)] = PERF_COUNT_ARC_EITLB,
188 },
189 [C(OP_WRITE)] = {
190 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
191 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
192 },
193 [C(OP_PREFETCH)] = {
194 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
195 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
196 },
197 },
198 [C(BPU)] = {
199 [C(OP_READ)] = {
200 [C(RESULT_ACCESS)] = PERF_COUNT_HW_BRANCH_INSTRUCTIONS,
201 [C(RESULT_MISS)] = PERF_COUNT_HW_BRANCH_MISSES,
202 },
203 [C(OP_WRITE)] = {
204 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
205 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
206 },
207 [C(OP_PREFETCH)] = {
208 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
209 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
210 },
211 },
212 [C(NODE)] = {
213 [C(OP_READ)] = {
214 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
215 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
216 },
217 [C(OP_WRITE)] = {
218 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
219 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
220 },
221 [C(OP_PREFETCH)] = {
222 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
223 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
224 },
225 },
226};
227
9c57564e 228#endif /* __ASM_PERF_EVENT_H */
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