ARM: dts: DRA7: Add dsp1_system syscon node
[deliverable/linux.git] / arch / arm / boot / dts / dra74x.dtsi
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1/*
2 * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 * Based on "omap4.dtsi"
8 */
9
10#include "dra7.dtsi"
11
12/ {
13 compatible = "ti,dra742", "ti,dra74", "ti,dra7";
14
15 cpus {
16 #address-cells = <1>;
17 #size-cells = <0>;
18
19 cpu0: cpu@0 {
20 device_type = "cpu";
21 compatible = "arm,cortex-a15";
22 reg = <0>;
23
24 operating-points = <
25 /* kHz uV */
26 1000000 1060000
27 1176000 1160000
28 >;
29
30 clocks = <&dpll_mpu_ck>;
31 clock-names = "cpu";
32
33 clock-latency = <300000>; /* From omap-cpufreq driver */
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34
35 /* cooling options */
36 cooling-min-level = <0>;
37 cooling-max-level = <2>;
38 #cooling-cells = <2>; /* min followed by max */
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39 };
40 cpu@1 {
41 device_type = "cpu";
42 compatible = "arm,cortex-a15";
43 reg = <1>;
44 };
45 };
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46
47 pmu {
48 compatible = "arm,cortex-a15-pmu";
7136d457 49 interrupt-parent = <&wakeupgen>;
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50 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
51 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
f53e3c53 52 };
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53
54 ocp {
4f6dec70 55 omap_dwc3_4: omap_dwc3_4@48940000 {
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56 compatible = "ti,dwc3";
57 ti,hwmods = "usb_otg_ss4";
58 reg = <0x48940000 0x10000>;
59 interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>;
60 #address-cells = <1>;
61 #size-cells = <1>;
62 utmi-mode = <2>;
63 ranges;
64 status = "disabled";
65 usb4: usb@48950000 {
66 compatible = "snps,dwc3";
67 reg = <0x48950000 0x17000>;
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68 interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
69 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
70 <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>;
71 interrupt-names = "peripheral",
72 "host",
73 "otg";
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74 tx-fifo-resize;
75 maximum-speed = "high-speed";
76 dr_mode = "otg";
77 };
78 };
79 };
38b248db 80};
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81
82&dss {
83 reg = <0x58000000 0x80>,
84 <0x58004054 0x4>,
85 <0x58004300 0x20>,
86 <0x58005054 0x4>,
87 <0x58005300 0x20>;
88 reg-names = "dss", "pll1_clkctrl", "pll1",
89 "pll2_clkctrl", "pll2";
90
91 clocks = <&dss_dss_clk>,
92 <&dss_video1_clk>,
93 <&dss_video2_clk>;
94 clock-names = "fck", "video1_clk", "video2_clk";
95};
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96
97&mailbox5 {
98 mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
99 ti,mbox-tx = <6 2 2>;
100 ti,mbox-rx = <4 2 2>;
101 status = "disabled";
102 };
103 mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
104 ti,mbox-tx = <5 2 2>;
105 ti,mbox-rx = <1 2 2>;
106 status = "disabled";
107 };
108};
109
110&mailbox6 {
111 mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
112 ti,mbox-tx = <6 2 2>;
113 ti,mbox-rx = <4 2 2>;
114 status = "disabled";
115 };
116 mbox_dsp2_ipc3x: mbox_dsp2_ipc3x {
117 ti,mbox-tx = <5 2 2>;
118 ti,mbox-rx = <1 2 2>;
119 status = "disabled";
120 };
121};
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