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3d739985 JL |
1 | /* linux/arch/arm/mach-exynos4/cpuidle.c |
2 | * | |
3 | * Copyright (c) 2011 Samsung Electronics Co., Ltd. | |
4 | * http://www.samsung.com | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | */ | |
10 | ||
11 | #include <linux/kernel.h> | |
12 | #include <linux/init.h> | |
13 | #include <linux/cpuidle.h> | |
67173ca4 | 14 | #include <linux/cpu_pm.h> |
3d739985 | 15 | #include <linux/io.h> |
76ee4557 KP |
16 | #include <linux/export.h> |
17 | #include <linux/time.h> | |
3d739985 JL |
18 | |
19 | #include <asm/proc-fns.h> | |
67173ca4 ADK |
20 | #include <asm/smp_scu.h> |
21 | #include <asm/suspend.h> | |
22 | #include <asm/unified.h> | |
06c77b3c | 23 | #include <asm/cpuidle.h> |
0f9e0359 | 24 | #include <mach/regs-clock.h> |
67173ca4 | 25 | #include <mach/regs-pmu.h> |
67173ca4 ADK |
26 | |
27 | #include <plat/cpu.h> | |
28 | ||
ccd458c1 KK |
29 | #include "common.h" |
30 | ||
67173ca4 ADK |
31 | #define REG_DIRECTGO_ADDR (samsung_rev() == EXYNOS4210_REV_1_1 ? \ |
32 | S5P_INFORM7 : (samsung_rev() == EXYNOS4210_REV_1_0 ? \ | |
33 | (S5P_VA_SYSRAM + 0x24) : S5P_INFORM0)) | |
34 | #define REG_DIRECTGO_FLAG (samsung_rev() == EXYNOS4210_REV_1_1 ? \ | |
35 | S5P_INFORM6 : (samsung_rev() == EXYNOS4210_REV_1_0 ? \ | |
36 | (S5P_VA_SYSRAM + 0x20) : S5P_INFORM1)) | |
37 | ||
38 | #define S5P_CHECK_AFTR 0xFCBA0D10 | |
3d739985 | 39 | |
67173ca4 ADK |
40 | static int exynos4_enter_lowpower(struct cpuidle_device *dev, |
41 | struct cpuidle_driver *drv, | |
42 | int index); | |
3d739985 | 43 | |
3d739985 JL |
44 | static DEFINE_PER_CPU(struct cpuidle_device, exynos4_cpuidle_device); |
45 | ||
46 | static struct cpuidle_driver exynos4_idle_driver = { | |
06c77b3c ADK |
47 | .name = "exynos4_idle", |
48 | .owner = THIS_MODULE, | |
2eb89f89 DL |
49 | .states = { |
50 | [0] = ARM_CPUIDLE_WFI_STATE, | |
51 | [1] = { | |
52 | .enter = exynos4_enter_lowpower, | |
53 | .exit_latency = 300, | |
54 | .target_residency = 100000, | |
55 | .flags = CPUIDLE_FLAG_TIME_VALID, | |
56 | .name = "C1", | |
57 | .desc = "ARM power down", | |
58 | }, | |
59 | }, | |
60 | .state_count = 2, | |
61 | .safe_state_index = 0, | |
3d739985 JL |
62 | }; |
63 | ||
67173ca4 ADK |
64 | /* Ext-GIC nIRQ/nFIQ is the only wakeup source in AFTR */ |
65 | static void exynos4_set_wakeupmask(void) | |
66 | { | |
67 | __raw_writel(0x0000ff3e, S5P_WAKEUP_MASK); | |
68 | } | |
69 | ||
70 | static unsigned int g_pwr_ctrl, g_diag_reg; | |
71 | ||
72 | static void save_cpu_arch_register(void) | |
73 | { | |
74 | /*read power control register*/ | |
75 | asm("mrc p15, 0, %0, c15, c0, 0" : "=r"(g_pwr_ctrl) : : "cc"); | |
76 | /*read diagnostic register*/ | |
77 | asm("mrc p15, 0, %0, c15, c0, 1" : "=r"(g_diag_reg) : : "cc"); | |
78 | return; | |
79 | } | |
80 | ||
81 | static void restore_cpu_arch_register(void) | |
82 | { | |
83 | /*write power control register*/ | |
84 | asm("mcr p15, 0, %0, c15, c0, 0" : : "r"(g_pwr_ctrl) : "cc"); | |
85 | /*write diagnostic register*/ | |
86 | asm("mcr p15, 0, %0, c15, c0, 1" : : "r"(g_diag_reg) : "cc"); | |
87 | return; | |
88 | } | |
89 | ||
90 | static int idle_finisher(unsigned long flags) | |
91 | { | |
92 | cpu_do_idle(); | |
93 | return 1; | |
94 | } | |
95 | ||
96 | static int exynos4_enter_core0_aftr(struct cpuidle_device *dev, | |
97 | struct cpuidle_driver *drv, | |
98 | int index) | |
99 | { | |
67173ca4 ADK |
100 | unsigned long tmp; |
101 | ||
67173ca4 ADK |
102 | exynos4_set_wakeupmask(); |
103 | ||
104 | /* Set value of power down register for aftr mode */ | |
7d44d2ba | 105 | exynos_sys_powerdown_conf(SYS_AFTR); |
67173ca4 ADK |
106 | |
107 | __raw_writel(virt_to_phys(s3c_cpu_resume), REG_DIRECTGO_ADDR); | |
108 | __raw_writel(S5P_CHECK_AFTR, REG_DIRECTGO_FLAG); | |
109 | ||
110 | save_cpu_arch_register(); | |
111 | ||
112 | /* Setting Central Sequence Register for power down mode */ | |
113 | tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION); | |
114 | tmp &= ~S5P_CENTRAL_LOWPWR_CFG; | |
115 | __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION); | |
116 | ||
117 | cpu_pm_enter(); | |
118 | cpu_suspend(0, idle_finisher); | |
119 | ||
120 | #ifdef CONFIG_SMP | |
a633208f AK |
121 | if (!soc_is_exynos5250()) |
122 | scu_enable(S5P_VA_SCU); | |
67173ca4 ADK |
123 | #endif |
124 | cpu_pm_exit(); | |
125 | ||
126 | restore_cpu_arch_register(); | |
127 | ||
128 | /* | |
129 | * If PMU failed while entering sleep mode, WFI will be | |
130 | * ignored by PMU and then exiting cpu_do_idle(). | |
131 | * S5P_CENTRAL_LOWPWR_CFG bit will not be set automatically | |
132 | * in this situation. | |
133 | */ | |
134 | tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION); | |
135 | if (!(tmp & S5P_CENTRAL_LOWPWR_CFG)) { | |
136 | tmp |= S5P_CENTRAL_LOWPWR_CFG; | |
137 | __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION); | |
138 | } | |
139 | ||
140 | /* Clear wakeup state register */ | |
141 | __raw_writel(0x0, S5P_WAKEUP_STAT); | |
142 | ||
e978aa7d | 143 | return index; |
3d739985 JL |
144 | } |
145 | ||
67173ca4 ADK |
146 | static int exynos4_enter_lowpower(struct cpuidle_device *dev, |
147 | struct cpuidle_driver *drv, | |
148 | int index) | |
149 | { | |
150 | int new_index = index; | |
151 | ||
152 | /* This mode only can be entered when other core's are offline */ | |
153 | if (num_online_cpus() > 1) | |
154 | new_index = drv->safe_state_index; | |
155 | ||
156 | if (new_index == 0) | |
06c77b3c | 157 | return arm_cpuidle_simple_enter(dev, drv, new_index); |
67173ca4 ADK |
158 | else |
159 | return exynos4_enter_core0_aftr(dev, drv, new_index); | |
160 | } | |
161 | ||
0f9e0359 AK |
162 | static void __init exynos5_core_down_clk(void) |
163 | { | |
164 | unsigned int tmp; | |
165 | ||
166 | /* | |
167 | * Enable arm clock down (in idle) and set arm divider | |
168 | * ratios in WFI/WFE state. | |
169 | */ | |
170 | tmp = PWR_CTRL1_CORE2_DOWN_RATIO | \ | |
171 | PWR_CTRL1_CORE1_DOWN_RATIO | \ | |
172 | PWR_CTRL1_DIV2_DOWN_EN | \ | |
173 | PWR_CTRL1_DIV1_DOWN_EN | \ | |
174 | PWR_CTRL1_USE_CORE1_WFE | \ | |
175 | PWR_CTRL1_USE_CORE0_WFE | \ | |
176 | PWR_CTRL1_USE_CORE1_WFI | \ | |
177 | PWR_CTRL1_USE_CORE0_WFI; | |
178 | __raw_writel(tmp, EXYNOS5_PWR_CTRL1); | |
179 | ||
180 | /* | |
181 | * Enable arm clock up (on exiting idle). Set arm divider | |
182 | * ratios when not in idle along with the standby duration | |
183 | * ratios. | |
184 | */ | |
185 | tmp = PWR_CTRL2_DIV2_UP_EN | \ | |
186 | PWR_CTRL2_DIV1_UP_EN | \ | |
187 | PWR_CTRL2_DUR_STANDBY2_VAL | \ | |
188 | PWR_CTRL2_DUR_STANDBY1_VAL | \ | |
189 | PWR_CTRL2_CORE2_UP_RATIO | \ | |
190 | PWR_CTRL2_CORE1_UP_RATIO; | |
191 | __raw_writel(tmp, EXYNOS5_PWR_CTRL2); | |
192 | } | |
193 | ||
3d739985 JL |
194 | static int __init exynos4_init_cpuidle(void) |
195 | { | |
5db9f436 | 196 | int cpu_id, ret; |
3d739985 | 197 | struct cpuidle_device *device; |
46bcfad7 | 198 | |
0f9e0359 AK |
199 | if (soc_is_exynos5250()) |
200 | exynos5_core_down_clk(); | |
201 | ||
5db9f436 DL |
202 | ret = cpuidle_register_driver(&exynos4_idle_driver); |
203 | if (ret) { | |
204 | printk(KERN_ERR "CPUidle failed to register driver\n"); | |
205 | return ret; | |
46bcfad7 | 206 | } |
3d739985 | 207 | |
329afd26 | 208 | for_each_online_cpu(cpu_id) { |
3d739985 JL |
209 | device = &per_cpu(exynos4_cpuidle_device, cpu_id); |
210 | device->cpu = cpu_id; | |
211 | ||
2eb89f89 DL |
212 | /* Support IDLE only */ |
213 | if (cpu_id != 0) | |
214 | device->state_count = 1; | |
3d739985 | 215 | |
5db9f436 DL |
216 | ret = cpuidle_register_device(device); |
217 | if (ret) { | |
218 | printk(KERN_ERR "CPUidle register device failed\n"); | |
219 | return ret; | |
3d739985 JL |
220 | } |
221 | } | |
67173ca4 | 222 | |
3d739985 JL |
223 | return 0; |
224 | } | |
225 | device_initcall(exynos4_init_cpuidle); |