[deliverable/linux.git] / arch / arm / mach-omap1 / ams-delta-fiq.c

/*
 *  Amstrad E3 FIQ handling
 *
 *  Copyright (C) 2009 Janusz Krzysztofik
 *  Copyright (c) 2006 Matt Callow
 *  Copyright (c) 2004 Amstrad Plc
 *  Copyright (C) 2001 RidgeRun, Inc.
 *
 * Parts of this code are taken from linux/arch/arm/mach-omap/irq.c
 * in the MontaVista 2.4 kernel (and the Amstrad changes therein)
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License version 2 as published by
 * the Free Software Foundation.
 */
#include <linux/gpio.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/module.h>
#include <linux/io.h>

#include <plat/board-ams-delta.h>

#include <asm/fiq.h>
#include <mach/ams-delta-fiq.h>

static struct fiq_handler fh = {
	.name	= "ams-delta-fiq"
};

/*
 * This buffer is shared between FIQ and IRQ contexts.
 * The FIQ and IRQ isrs can both read and write it.
 * It is structured as a header section several 32bit slots,
 * followed by the circular buffer where the FIQ isr stores
 * keystrokes received from the qwerty keyboard.
 * See ams-delta-fiq.h for details of offsets.
 */
unsigned int fiq_buffer[1024];
EXPORT_SYMBOL(fiq_buffer);

static unsigned int irq_counter[16];

static irqreturn_t deferred_fiq(int irq, void *dev_id)
{
	struct irq_desc *irq_desc;
	struct irq_chip *irq_chip = NULL;
	int gpio, irq_num, fiq_count;

	irq_desc = irq_to_desc(IH_GPIO_BASE);
	if (irq_desc)
		irq_chip = irq_desc->irq_data.chip;

	/*
	 * For each handled GPIO interrupt, keep calling its interrupt handler
	 * until the IRQ counter catches the FIQ incremented interrupt counter.
	 */
	for (gpio = AMS_DELTA_GPIO_PIN_KEYBRD_CLK;
			gpio <= AMS_DELTA_GPIO_PIN_HOOK_SWITCH; gpio++) {
		irq_num = gpio_to_irq(gpio);
		fiq_count = fiq_buffer[FIQ_CNT_INT_00 + gpio];

		while (irq_counter[gpio] < fiq_count) {
			if (gpio != AMS_DELTA_GPIO_PIN_KEYBRD_CLK) {
				struct irq_data *d = irq_get_irq_data(irq_num);

				/*
				 * It looks like handle_edge_irq() that
				 * OMAP GPIO edge interrupts default to,
				 * expects interrupt already unmasked.
				 */
				if (irq_chip && irq_chip->irq_unmask)
					irq_chip->irq_unmask(d);
			}
			generic_handle_irq(irq_num);

			irq_counter[gpio]++;
		}
	}
	return IRQ_HANDLED;
}

void __init ams_delta_init_fiq(void)
{
	void *fiqhandler_start;
	unsigned int fiqhandler_length;
	struct pt_regs FIQ_regs;
	unsigned long val, offset;
	int i, retval;

	fiqhandler_start = &qwerty_fiqin_start;
	fiqhandler_length = &qwerty_fiqin_end - &qwerty_fiqin_start;
	pr_info("Installing fiq handler from %p, length 0x%x\n",
			fiqhandler_start, fiqhandler_length);

	retval = claim_fiq(&fh);
	if (retval) {
		pr_err("ams_delta_init_fiq(): couldn't claim FIQ, ret=%d\n",
				retval);
		return;
	}

	retval = request_irq(INT_DEFERRED_FIQ, deferred_fiq,
			IRQ_TYPE_EDGE_RISING, "deferred_fiq", 0);
	if (retval < 0) {
		pr_err("Failed to get deferred_fiq IRQ, ret=%d\n", retval);
		release_fiq(&fh);
		return;
	}
	/*
	 * Since no set_type() method is provided by OMAP irq chip,
	 * switch to edge triggered interrupt type manually.
	 */
	offset = IRQ_ILR0_REG_OFFSET + INT_DEFERRED_FIQ * 0x4;
	val = omap_readl(DEFERRED_FIQ_IH_BASE + offset) & ~(1 << 1);
	omap_writel(val, DEFERRED_FIQ_IH_BASE + offset);

	set_fiq_handler(fiqhandler_start, fiqhandler_length);

	/*
	 * Initialise the buffer which is shared
	 * between FIQ mode and IRQ mode
	 */
	fiq_buffer[FIQ_GPIO_INT_MASK]	= 0;
	fiq_buffer[FIQ_MASK]		= 0;
	fiq_buffer[FIQ_STATE]		= 0;
	fiq_buffer[FIQ_KEY]		= 0;
	fiq_buffer[FIQ_KEYS_CNT]	= 0;
	fiq_buffer[FIQ_KEYS_HICNT]	= 0;
	fiq_buffer[FIQ_TAIL_OFFSET]	= 0;
	fiq_buffer[FIQ_HEAD_OFFSET]	= 0;
	fiq_buffer[FIQ_BUF_LEN]		= 256;
	fiq_buffer[FIQ_MISSED_KEYS]	= 0;
	fiq_buffer[FIQ_BUFFER_START]	=
			(unsigned int) &fiq_buffer[FIQ_CIRC_BUFF];

	for (i = FIQ_CNT_INT_00; i <= FIQ_CNT_INT_15; i++)
		fiq_buffer[i] = 0;

	/*
	 * FIQ mode r9 always points to the fiq_buffer, becauses the FIQ isr
	 * will run in an unpredictable context. The fiq_buffer is the FIQ isr's
	 * only means of communication with the IRQ level and other kernel
	 * context code.
	 */
	FIQ_regs.ARM_r9 = (unsigned int)fiq_buffer;
	set_fiq_regs(&FIQ_regs);

	pr_info("request_fiq(): fiq_buffer = %p\n", fiq_buffer);

	/*
	 * Redirect GPIO interrupts to FIQ
	 */
	offset = IRQ_ILR0_REG_OFFSET + INT_GPIO_BANK1 * 0x4;
	val = omap_readl(OMAP_IH1_BASE + offset) | 1;
	omap_writel(val, OMAP_IH1_BASE + offset);
}
Commit	Line	Data
11f9562a JK	1	/*
	2	* Amstrad E3 FIQ handling
	3	*
	4	* Copyright (C) 2009 Janusz Krzysztofik
	5	* Copyright (c) 2006 Matt Callow
	6	* Copyright (c) 2004 Amstrad Plc
	7	* Copyright (C) 2001 RidgeRun, Inc.
	8	*
	9	* Parts of this code are taken from linux/arch/arm/mach-omap/irq.c
	10	* in the MontaVista 2.4 kernel (and the Amstrad changes therein)
	11	*
	12	* This program is free software; you can redistribute it and/or modify it
	13	* under the terms of the GNU General Public License version 2 as published by
	14	* the Free Software Foundation.
	15	*/
	16	#include <linux/gpio.h>
	17	#include <linux/interrupt.h>
	18	#include <linux/irq.h>
	19	#include <linux/module.h>
	20	#include <linux/io.h>
	21
	22	#include <plat/board-ams-delta.h>
	23
	24	#include <asm/fiq.h>
	25	#include <mach/ams-delta-fiq.h>
	26
	27	static struct fiq_handler fh = {
	28	.name = "ams-delta-fiq"
	29	};
	30
	31	/*
	32	* This buffer is shared between FIQ and IRQ contexts.
	33	* The FIQ and IRQ isrs can both read and write it.
	34	* It is structured as a header section several 32bit slots,
	35	* followed by the circular buffer where the FIQ isr stores
	36	* keystrokes received from the qwerty keyboard.
	37	* See ams-delta-fiq.h for details of offsets.
	38	*/
	39	unsigned int fiq_buffer[1024];
	40	EXPORT_SYMBOL(fiq_buffer);
	41
	42	static unsigned int irq_counter[16];
	43
	44	static irqreturn_t deferred_fiq(int irq, void *dev_id)
	45	{
	46	struct irq_desc *irq_desc;
	47	struct irq_chip *irq_chip = NULL;
	48	int gpio, irq_num, fiq_count;
	49
	50	irq_desc = irq_to_desc(IH_GPIO_BASE);
	51	if (irq_desc)
a51eef7e	52	irq_chip = irq_desc->irq_data.chip;
11f9562a JK	53
	54	/*
	55	* For each handled GPIO interrupt, keep calling its interrupt handler
	56	* until the IRQ counter catches the FIQ incremented interrupt counter.
	57	*/
	58	for (gpio = AMS_DELTA_GPIO_PIN_KEYBRD_CLK;
	59	gpio <= AMS_DELTA_GPIO_PIN_HOOK_SWITCH; gpio++) {
	60	irq_num = gpio_to_irq(gpio);
	61	fiq_count = fiq_buffer[FIQ_CNT_INT_00 + gpio];
	62
	63	while (irq_counter[gpio] < fiq_count) {
	64	if (gpio != AMS_DELTA_GPIO_PIN_KEYBRD_CLK) {
a51eef7e LB	65	struct irq_data *d = irq_get_irq_data(irq_num);
a51eef7e LB	66
11f9562a JK	67	/*
	68	* It looks like handle_edge_irq() that
	69	* OMAP GPIO edge interrupts default to,
	70	* expects interrupt already unmasked.
	71	*/
a51eef7e LB	72	if (irq_chip && irq_chip->irq_unmask)
a51eef7e LB	73	irq_chip->irq_unmask(d);
11f9562a JK	74	}
	75	generic_handle_irq(irq_num);
	76
	77	irq_counter[gpio]++;
	78	}
	79	}
	80	return IRQ_HANDLED;
	81	}
	82
	83	void __init ams_delta_init_fiq(void)
	84	{
	85	void *fiqhandler_start;
	86	unsigned int fiqhandler_length;
	87	struct pt_regs FIQ_regs;
	88	unsigned long val, offset;
	89	int i, retval;
	90
	91	fiqhandler_start = &qwerty_fiqin_start;
	92	fiqhandler_length = &qwerty_fiqin_end - &qwerty_fiqin_start;
	93	pr_info("Installing fiq handler from %p, length 0x%x\n",
	94	fiqhandler_start, fiqhandler_length);
	95
	96	retval = claim_fiq(&fh);
	97	if (retval) {
	98	pr_err("ams_delta_init_fiq(): couldn't claim FIQ, ret=%d\n",
	99	retval);
	100	return;
	101	}
	102
	103	retval = request_irq(INT_DEFERRED_FIQ, deferred_fiq,
	104	IRQ_TYPE_EDGE_RISING, "deferred_fiq", 0);
	105	if (retval < 0) {
	106	pr_err("Failed to get deferred_fiq IRQ, ret=%d\n", retval);
	107	release_fiq(&fh);
	108	return;
	109	}
	110	/*
	111	* Since no set_type() method is provided by OMAP irq chip,
	112	* switch to edge triggered interrupt type manually.
	113	*/
	114	offset = IRQ_ILR0_REG_OFFSET + INT_DEFERRED_FIQ * 0x4;
	115	val = omap_readl(DEFERRED_FIQ_IH_BASE + offset) & ~(1 << 1);
	116	omap_writel(val, DEFERRED_FIQ_IH_BASE + offset);
	117
	118	set_fiq_handler(fiqhandler_start, fiqhandler_length);
	119
	120	/*
	121	* Initialise the buffer which is shared
	122	* between FIQ mode and IRQ mode
	123	*/
	124	fiq_buffer[FIQ_GPIO_INT_MASK] = 0;
	125	fiq_buffer[FIQ_MASK] = 0;
	126	fiq_buffer[FIQ_STATE] = 0;
	127	fiq_buffer[FIQ_KEY] = 0;
	128	fiq_buffer[FIQ_KEYS_CNT] = 0;
	129	fiq_buffer[FIQ_KEYS_HICNT] = 0;
	130	fiq_buffer[FIQ_TAIL_OFFSET] = 0;
	131	fiq_buffer[FIQ_HEAD_OFFSET] = 0;
	132	fiq_buffer[FIQ_BUF_LEN] = 256;
	133	fiq_buffer[FIQ_MISSED_KEYS] = 0;
	134	fiq_buffer[FIQ_BUFFER_START] =
	135	(unsigned int) &fiq_buffer[FIQ_CIRC_BUFF];
	136
	137	for (i = FIQ_CNT_INT_00; i <= FIQ_CNT_INT_15; i++)
138	fiq_buffer[i] = 0;
139
140	/*
141	* FIQ mode r9 always points to the fiq_buffer, becauses the FIQ isr
142	* will run in an unpredictable context. The fiq_buffer is the FIQ isr's
143	* only means of communication with the IRQ level and other kernel
144	* context code.
145	*/
146	FIQ_regs.ARM_r9 = (unsigned int)fiq_buffer;
147	set_fiq_regs(&FIQ_regs);
148
149	pr_info("request_fiq(): fiq_buffer = %p\n", fiq_buffer);
150
151	/*
152	* Redirect GPIO interrupts to FIQ
153	*/
154	offset = IRQ_ILR0_REG_OFFSET + INT_GPIO_BANK1 * 0x4;
155	val = omap_readl(OMAP_IH1_BASE + offset) \| 1;
156	omap_writel(val, OMAP_IH1_BASE + offset);
157	}