[deliverable/linux.git] / arch / arm / mach-omap2 / iommu2.c

/*
 * omap iommu: omap2/3 architecture specific functions
 *
 * Copyright (C) 2008-2009 Nokia Corporation
 *
 * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>,
 *		Paul Mundt and Toshihiro Kobayashi
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/err.h>
#include <linux/device.h>
#include <linux/jiffies.h>
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/stringify.h>

#include <plat/iommu.h>

/*
 * omap2 architecture specific register bit definitions
 */
#define IOMMU_ARCH_VERSION	0x00000011

/* SYSCONF */
#define MMU_SYS_IDLE_SHIFT	3
#define MMU_SYS_IDLE_FORCE	(0 << MMU_SYS_IDLE_SHIFT)
#define MMU_SYS_IDLE_NONE	(1 << MMU_SYS_IDLE_SHIFT)
#define MMU_SYS_IDLE_SMART	(2 << MMU_SYS_IDLE_SHIFT)
#define MMU_SYS_IDLE_MASK	(3 << MMU_SYS_IDLE_SHIFT)

#define MMU_SYS_SOFTRESET	(1 << 1)
#define MMU_SYS_AUTOIDLE	1

/* SYSSTATUS */
#define MMU_SYS_RESETDONE	1

/* IRQSTATUS & IRQENABLE */
#define MMU_IRQ_MULTIHITFAULT	(1 << 4)
#define MMU_IRQ_TABLEWALKFAULT	(1 << 3)
#define MMU_IRQ_EMUMISS		(1 << 2)
#define MMU_IRQ_TRANSLATIONFAULT	(1 << 1)
#define MMU_IRQ_TLBMISS		(1 << 0)

#define __MMU_IRQ_FAULT		\
	(MMU_IRQ_MULTIHITFAULT | MMU_IRQ_EMUMISS | MMU_IRQ_TRANSLATIONFAULT)
#define MMU_IRQ_MASK		\
	(__MMU_IRQ_FAULT | MMU_IRQ_TABLEWALKFAULT | MMU_IRQ_TLBMISS)
#define MMU_IRQ_TWL_MASK	(__MMU_IRQ_FAULT | MMU_IRQ_TABLEWALKFAULT)
#define MMU_IRQ_TLB_MISS_MASK	(__MMU_IRQ_FAULT | MMU_IRQ_TLBMISS)

/* MMU_CNTL */
#define MMU_CNTL_SHIFT		1
#define MMU_CNTL_MASK		(7 << MMU_CNTL_SHIFT)
#define MMU_CNTL_EML_TLB	(1 << 3)
#define MMU_CNTL_TWL_EN		(1 << 2)
#define MMU_CNTL_MMU_EN		(1 << 1)

#define get_cam_va_mask(pgsz)				\
	(((pgsz) == MMU_CAM_PGSZ_16M) ? 0xff000000 :	\
	 ((pgsz) == MMU_CAM_PGSZ_1M)  ? 0xfff00000 :	\
	 ((pgsz) == MMU_CAM_PGSZ_64K) ? 0xffff0000 :	\
	 ((pgsz) == MMU_CAM_PGSZ_4K)  ? 0xfffff000 : 0)


static void __iommu_set_twl(struct iommu *obj, bool on)
{
	u32 l = iommu_read_reg(obj, MMU_CNTL);

	if (on)
		iommu_write_reg(obj, MMU_IRQ_TWL_MASK, MMU_IRQENABLE);
	else
		iommu_write_reg(obj, MMU_IRQ_TLB_MISS_MASK, MMU_IRQENABLE);

	l &= ~MMU_CNTL_MASK;
	if (on)
		l |= (MMU_CNTL_MMU_EN | MMU_CNTL_TWL_EN);
	else
		l |= (MMU_CNTL_MMU_EN);

	iommu_write_reg(obj, l, MMU_CNTL);
}


static int omap2_iommu_enable(struct iommu *obj)
{
	u32 l, pa;
	unsigned long timeout;

	if (!obj->iopgd || !IS_ALIGNED((u32)obj->iopgd,  SZ_16K))
		return -EINVAL;

	pa = virt_to_phys(obj->iopgd);
	if (!IS_ALIGNED(pa, SZ_16K))
		return -EINVAL;

	iommu_write_reg(obj, MMU_SYS_SOFTRESET, MMU_SYSCONFIG);

	timeout = jiffies + msecs_to_jiffies(20);
	do {
		l = iommu_read_reg(obj, MMU_SYSSTATUS);
		if (l & MMU_SYS_RESETDONE)
			break;
	} while (!time_after(jiffies, timeout));

	if (!(l & MMU_SYS_RESETDONE)) {
		dev_err(obj->dev, "can't take mmu out of reset\n");
		return -ENODEV;
	}

	l = iommu_read_reg(obj, MMU_REVISION);
	dev_info(obj->dev, "%s: version %d.%d\n", obj->name,
		 (l >> 4) & 0xf, l & 0xf);

	l = iommu_read_reg(obj, MMU_SYSCONFIG);
	l &= ~MMU_SYS_IDLE_MASK;
	l |= (MMU_SYS_IDLE_SMART | MMU_SYS_AUTOIDLE);
	iommu_write_reg(obj, l, MMU_SYSCONFIG);

	iommu_write_reg(obj, pa, MMU_TTB);

	__iommu_set_twl(obj, true);

	return 0;
}

static void omap2_iommu_disable(struct iommu *obj)
{
	u32 l = iommu_read_reg(obj, MMU_CNTL);

	l &= ~MMU_CNTL_MASK;
	iommu_write_reg(obj, l, MMU_CNTL);
	iommu_write_reg(obj, MMU_SYS_IDLE_FORCE, MMU_SYSCONFIG);

	dev_dbg(obj->dev, "%s is shutting down\n", obj->name);
}

static void omap2_iommu_set_twl(struct iommu *obj, bool on)
{
	__iommu_set_twl(obj, false);
}

static u32 omap2_iommu_fault_isr(struct iommu *obj, u32 *ra)
{
	u32 stat, da;

	stat = iommu_read_reg(obj, MMU_IRQSTATUS);
	stat &= MMU_IRQ_MASK;
	if (!stat)
		return 0;

	da = iommu_read_reg(obj, MMU_FAULT_AD);
	*ra = da;

	iommu_write_reg(obj, stat, MMU_IRQSTATUS);

	return stat;
}

static void omap2_tlb_read_cr(struct iommu *obj, struct cr_regs *cr)
{
	cr->cam = iommu_read_reg(obj, MMU_READ_CAM);
	cr->ram = iommu_read_reg(obj, MMU_READ_RAM);
}

static void omap2_tlb_load_cr(struct iommu *obj, struct cr_regs *cr)
{
	iommu_write_reg(obj, cr->cam | MMU_CAM_V, MMU_CAM);
	iommu_write_reg(obj, cr->ram, MMU_RAM);
}

static u32 omap2_cr_to_virt(struct cr_regs *cr)
{
	u32 page_size = cr->cam & MMU_CAM_PGSZ_MASK;
	u32 mask = get_cam_va_mask(cr->cam & page_size);

	return cr->cam & mask;
}

static struct cr_regs *omap2_alloc_cr(struct iommu *obj, struct iotlb_entry *e)
{
	struct cr_regs *cr;

	if (e->da & ~(get_cam_va_mask(e->pgsz))) {
		dev_err(obj->dev, "%s:\twrong alignment: %08x\n", __func__,
			e->da);
		return ERR_PTR(-EINVAL);
	}

	cr = kmalloc(sizeof(*cr), GFP_KERNEL);
	if (!cr)
		return ERR_PTR(-ENOMEM);

	cr->cam = (e->da & MMU_CAM_VATAG_MASK) | e->prsvd | e->pgsz | e->valid;
	cr->ram = e->pa | e->endian | e->elsz | e->mixed;

	return cr;
}

static inline int omap2_cr_valid(struct cr_regs *cr)
{
	return cr->cam & MMU_CAM_V;
}

static u32 omap2_get_pte_attr(struct iotlb_entry *e)
{
	u32 attr;

	attr = e->mixed << 5;
	attr |= e->endian;
	attr |= e->elsz >> 3;
	attr <<= ((e->pgsz & MMU_CAM_PGSZ_4K) ? 0 : 6);

	return attr;
}

static ssize_t omap2_dump_cr(struct iommu *obj, struct cr_regs *cr, char *buf)
{
	char *p = buf;

	/* FIXME: Need more detail analysis of cam/ram */
	p += sprintf(p, "%08x %08x %01x\n", cr->cam, cr->ram,
					(cr->cam & MMU_CAM_P) ? 1 : 0);

	return p - buf;
}

#define pr_reg(name)							\
	do {								\
		ssize_t bytes;						\
		const char *str = "%20s: %08x\n";			\
		const int maxcol = 32;					\
		bytes = snprintf(p, maxcol, str, __stringify(name),	\
				 iommu_read_reg(obj, MMU_##name));	\
		p += bytes;						\
		len -= bytes;						\
		if (len < maxcol)					\
			goto out;					\
	} while (0)

static ssize_t omap2_iommu_dump_ctx(struct iommu *obj, char *buf, ssize_t len)
{
	char *p = buf;

	pr_reg(REVISION);
	pr_reg(SYSCONFIG);
	pr_reg(SYSSTATUS);
	pr_reg(IRQSTATUS);
	pr_reg(IRQENABLE);
	pr_reg(WALKING_ST);
	pr_reg(CNTL);
	pr_reg(FAULT_AD);
	pr_reg(TTB);
	pr_reg(LOCK);
	pr_reg(LD_TLB);
	pr_reg(CAM);
	pr_reg(RAM);
	pr_reg(GFLUSH);
	pr_reg(FLUSH_ENTRY);
	pr_reg(READ_CAM);
	pr_reg(READ_RAM);
	pr_reg(EMU_FAULT_AD);
out:
	return p - buf;
}

static void omap2_iommu_save_ctx(struct iommu *obj)
{
	int i;
	u32 *p = obj->ctx;

	for (i = 0; i < (MMU_REG_SIZE / sizeof(u32)); i++) {
		p[i] = iommu_read_reg(obj, i * sizeof(u32));
		dev_dbg(obj->dev, "%s\t[%02d] %08x\n", __func__, i, p[i]);
	}

	BUG_ON(p[0] != IOMMU_ARCH_VERSION);
}

static void omap2_iommu_restore_ctx(struct iommu *obj)
{
	int i;
	u32 *p = obj->ctx;

	for (i = 0; i < (MMU_REG_SIZE / sizeof(u32)); i++) {
		iommu_write_reg(obj, p[i], i * sizeof(u32));
		dev_dbg(obj->dev, "%s\t[%02d] %08x\n", __func__, i, p[i]);
	}

	BUG_ON(p[0] != IOMMU_ARCH_VERSION);
}

static void omap2_cr_to_e(struct cr_regs *cr, struct iotlb_entry *e)
{
	e->da		= cr->cam & MMU_CAM_VATAG_MASK;
	e->pa		= cr->ram & MMU_RAM_PADDR_MASK;
	e->valid	= cr->cam & MMU_CAM_V;
	e->pgsz		= cr->cam & MMU_CAM_PGSZ_MASK;
	e->endian	= cr->ram & MMU_RAM_ENDIAN_MASK;
	e->elsz		= cr->ram & MMU_RAM_ELSZ_MASK;
	e->mixed	= cr->ram & MMU_RAM_MIXED;
}

static const struct iommu_functions omap2_iommu_ops = {
	.version	= IOMMU_ARCH_VERSION,

	.enable		= omap2_iommu_enable,
	.disable	= omap2_iommu_disable,
	.set_twl	= omap2_iommu_set_twl,
	.fault_isr	= omap2_iommu_fault_isr,

	.tlb_read_cr	= omap2_tlb_read_cr,
	.tlb_load_cr	= omap2_tlb_load_cr,

	.cr_to_e	= omap2_cr_to_e,
	.cr_to_virt	= omap2_cr_to_virt,
	.alloc_cr	= omap2_alloc_cr,
	.cr_valid	= omap2_cr_valid,
	.dump_cr	= omap2_dump_cr,

	.get_pte_attr	= omap2_get_pte_attr,

	.save_ctx	= omap2_iommu_save_ctx,
	.restore_ctx	= omap2_iommu_restore_ctx,
	.dump_ctx	= omap2_iommu_dump_ctx,
};

static int __init omap2_iommu_init(void)
{
	return install_iommu_arch(&omap2_iommu_ops);
}
module_init(omap2_iommu_init);

static void __exit omap2_iommu_exit(void)
{
	uninstall_iommu_arch(&omap2_iommu_ops);
}
module_exit(omap2_iommu_exit);

MODULE_AUTHOR("Hiroshi DOYU, Paul Mundt and Toshihiro Kobayashi");
MODULE_DESCRIPTION("omap iommu: omap2/3 architecture specific functions");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
2bcb5733 HD	1	/*
	2	* omap iommu: omap2/3 architecture specific functions
	3	*
	4	* Copyright (C) 2008-2009 Nokia Corporation
	5	*
	6	* Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>,
	7	* Paul Mundt and Toshihiro Kobayashi
	8	*
	9	* This program is free software; you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License version 2 as
	11	* published by the Free Software Foundation.
	12	*/
	13
	14	#include <linux/err.h>
	15	#include <linux/device.h>
	16	#include <linux/jiffies.h>
	17	#include <linux/module.h>
5a0e3ad6	18	#include <linux/slab.h>
2bcb5733 HD	19	#include <linux/stringify.h>
2bcb5733 HD	20
ce491cf8	21	#include <plat/iommu.h>
2bcb5733 HD	22
	23	/*
	24	* omap2 architecture specific register bit definitions
	25	*/
	26	#define IOMMU_ARCH_VERSION 0x00000011
	27
	28	/* SYSCONF */
	29	#define MMU_SYS_IDLE_SHIFT 3
	30	#define MMU_SYS_IDLE_FORCE (0 << MMU_SYS_IDLE_SHIFT)
	31	#define MMU_SYS_IDLE_NONE (1 << MMU_SYS_IDLE_SHIFT)
	32	#define MMU_SYS_IDLE_SMART (2 << MMU_SYS_IDLE_SHIFT)
	33	#define MMU_SYS_IDLE_MASK (3 << MMU_SYS_IDLE_SHIFT)
	34
	35	#define MMU_SYS_SOFTRESET (1 << 1)
	36	#define MMU_SYS_AUTOIDLE 1
	37
	38	/* SYSSTATUS */
	39	#define MMU_SYS_RESETDONE 1
	40
	41	/* IRQSTATUS & IRQENABLE */
	42	#define MMU_IRQ_MULTIHITFAULT (1 << 4)
	43	#define MMU_IRQ_TABLEWALKFAULT (1 << 3)
	44	#define MMU_IRQ_EMUMISS (1 << 2)
	45	#define MMU_IRQ_TRANSLATIONFAULT (1 << 1)
	46	#define MMU_IRQ_TLBMISS (1 << 0)
993dd17e KH	47
	48	#define __MMU_IRQ_FAULT \
	49	(MMU_IRQ_MULTIHITFAULT \| MMU_IRQ_EMUMISS \| MMU_IRQ_TRANSLATIONFAULT)
	50	#define MMU_IRQ_MASK \
	51	(__MMU_IRQ_FAULT \| MMU_IRQ_TABLEWALKFAULT \| MMU_IRQ_TLBMISS)
	52	#define MMU_IRQ_TWL_MASK (__MMU_IRQ_FAULT \| MMU_IRQ_TABLEWALKFAULT)
	53	#define MMU_IRQ_TLB_MISS_MASK (__MMU_IRQ_FAULT \| MMU_IRQ_TLBMISS)
2bcb5733 HD	54
	55	/* MMU_CNTL */
	56	#define MMU_CNTL_SHIFT 1
	57	#define MMU_CNTL_MASK (7 << MMU_CNTL_SHIFT)
	58	#define MMU_CNTL_EML_TLB (1 << 3)
	59	#define MMU_CNTL_TWL_EN (1 << 2)
	60	#define MMU_CNTL_MMU_EN (1 << 1)
	61
	62	#define get_cam_va_mask(pgsz) \
	63	(((pgsz) == MMU_CAM_PGSZ_16M) ? 0xff000000 : \
	64	((pgsz) == MMU_CAM_PGSZ_1M) ? 0xfff00000 : \
	65	((pgsz) == MMU_CAM_PGSZ_64K) ? 0xffff0000 : \
	66	((pgsz) == MMU_CAM_PGSZ_4K) ? 0xfffff000 : 0)
	67
ddfa975a KH	68
	69	static void __iommu_set_twl(struct iommu *obj, bool on)
	70	{
	71	u32 l = iommu_read_reg(obj, MMU_CNTL);
	72
	73	if (on)
	74	iommu_write_reg(obj, MMU_IRQ_TWL_MASK, MMU_IRQENABLE);
	75	else
	76	iommu_write_reg(obj, MMU_IRQ_TLB_MISS_MASK, MMU_IRQENABLE);
	77
	78	l &= ~MMU_CNTL_MASK;
	79	if (on)
	80	l \|= (MMU_CNTL_MMU_EN \| MMU_CNTL_TWL_EN);
	81	else
	82	l \|= (MMU_CNTL_MMU_EN);
	83
	84	iommu_write_reg(obj, l, MMU_CNTL);
	85	}
	86
	87
2bcb5733 HD	88	static int omap2_iommu_enable(struct iommu *obj)
	89	{
	90	u32 l, pa;
	91	unsigned long timeout;
	92
	93	if (!obj->iopgd \|\| !IS_ALIGNED((u32)obj->iopgd, SZ_16K))
	94	return -EINVAL;
	95
	96	pa = virt_to_phys(obj->iopgd);
	97	if (!IS_ALIGNED(pa, SZ_16K))
	98	return -EINVAL;
	99
	100	iommu_write_reg(obj, MMU_SYS_SOFTRESET, MMU_SYSCONFIG);
	101
	102	timeout = jiffies + msecs_to_jiffies(20);
	103	do {
	104	l = iommu_read_reg(obj, MMU_SYSSTATUS);
	105	if (l & MMU_SYS_RESETDONE)
	106	break;
055c49d2	107	} while (!time_after(jiffies, timeout));
2bcb5733 HD	108
	109	if (!(l & MMU_SYS_RESETDONE)) {
	110	dev_err(obj->dev, "can't take mmu out of reset\n");
	111	return -ENODEV;
	112	}
	113
	114	l = iommu_read_reg(obj, MMU_REVISION);
	115	dev_info(obj->dev, "%s: version %d.%d\n", obj->name,
	116	(l >> 4) & 0xf, l & 0xf);
	117
	118	l = iommu_read_reg(obj, MMU_SYSCONFIG);
	119	l &= ~MMU_SYS_IDLE_MASK;
	120	l \|= (MMU_SYS_IDLE_SMART \| MMU_SYS_AUTOIDLE);
	121	iommu_write_reg(obj, l, MMU_SYSCONFIG);
	122
2bcb5733 HD	123	iommu_write_reg(obj, pa, MMU_TTB);
2bcb5733 HD	124
ddfa975a	125	__iommu_set_twl(obj, true);
2bcb5733 HD	126
	127	return 0;
	128	}
	129
	130	static void omap2_iommu_disable(struct iommu *obj)
	131	{
	132	u32 l = iommu_read_reg(obj, MMU_CNTL);
	133
	134	l &= ~MMU_CNTL_MASK;
	135	iommu_write_reg(obj, l, MMU_CNTL);
	136	iommu_write_reg(obj, MMU_SYS_IDLE_FORCE, MMU_SYSCONFIG);
	137
	138	dev_dbg(obj->dev, "%s is shutting down\n", obj->name);
	139	}
	140
ddfa975a KH	141	static void omap2_iommu_set_twl(struct iommu *obj, bool on)
	142	{
	143	__iommu_set_twl(obj, false);
	144	}
	145
2bcb5733 HD	146	static u32 omap2_iommu_fault_isr(struct iommu obj, u32 ra)
2bcb5733 HD	147	{
2bcb5733	148	u32 stat, da;
2bcb5733 HD	149
	150	stat = iommu_read_reg(obj, MMU_IRQSTATUS);
	151	stat &= MMU_IRQ_MASK;
	152	if (!stat)
	153	return 0;
	154
	155	da = iommu_read_reg(obj, MMU_FAULT_AD);
	156	*ra = da;
	157
2bcb5733	158	iommu_write_reg(obj, stat, MMU_IRQSTATUS);
37b29810	159
2bcb5733 HD	160	return stat;
	161	}
	162
	163	static void omap2_tlb_read_cr(struct iommu obj, struct cr_regs cr)
	164	{
	165	cr->cam = iommu_read_reg(obj, MMU_READ_CAM);
	166	cr->ram = iommu_read_reg(obj, MMU_READ_RAM);
	167	}
	168
	169	static void omap2_tlb_load_cr(struct iommu obj, struct cr_regs cr)
	170	{
	171	iommu_write_reg(obj, cr->cam \| MMU_CAM_V, MMU_CAM);
	172	iommu_write_reg(obj, cr->ram, MMU_RAM);
	173	}
	174
	175	static u32 omap2_cr_to_virt(struct cr_regs *cr)
	176	{
	177	u32 page_size = cr->cam & MMU_CAM_PGSZ_MASK;
	178	u32 mask = get_cam_va_mask(cr->cam & page_size);
	179
	180	return cr->cam & mask;
	181	}
	182
	183	static struct cr_regs omap2_alloc_cr(struct iommu obj, struct iotlb_entry *e)
	184	{
	185	struct cr_regs *cr;
	186
	187	if (e->da & ~(get_cam_va_mask(e->pgsz))) {
	188	dev_err(obj->dev, "%s:\twrong alignment: %08x\n", __func__,
	189	e->da);
	190	return ERR_PTR(-EINVAL);
	191	}
	192
	193	cr = kmalloc(sizeof(*cr), GFP_KERNEL);
	194	if (!cr)
	195	return ERR_PTR(-ENOMEM);
	196
77bc5abb	197	cr->cam = (e->da & MMU_CAM_VATAG_MASK) \| e->prsvd \| e->pgsz \| e->valid;
2bcb5733 HD	198	cr->ram = e->pa \| e->endian \| e->elsz \| e->mixed;
	199
	200	return cr;
	201	}
	202
	203	static inline int omap2_cr_valid(struct cr_regs *cr)
	204	{
	205	return cr->cam & MMU_CAM_V;
	206	}
	207
	208	static u32 omap2_get_pte_attr(struct iotlb_entry *e)
	209	{
	210	u32 attr;
	211
	212	attr = e->mixed << 5;
	213	attr \|= e->endian;
	214	attr \|= e->elsz >> 3;
	215	attr <<= ((e->pgsz & MMU_CAM_PGSZ_4K) ? 0 : 6);
	216
	217	return attr;
	218	}
	219
	220	static ssize_t omap2_dump_cr(struct iommu obj, struct cr_regs cr, char *buf)
	221	{
	222	char *p = buf;
	223
	224	/* FIXME: Need more detail analysis of cam/ram */
be6d8026 KH	225	p += sprintf(p, "%08x %08x %01x\n", cr->cam, cr->ram,
be6d8026 KH	226	(cr->cam & MMU_CAM_P) ? 1 : 0);
2bcb5733 HD	227
	228	return p - buf;
	229	}
	230
	231	#define pr_reg(name) \
14e0e679 HD	232	do { \
	233	ssize_t bytes; \
	234	const char *str = "%20s: %08x\n"; \
	235	const int maxcol = 32; \
	236	bytes = snprintf(p, maxcol, str, __stringify(name), \
	237	iommu_read_reg(obj, MMU_##name)); \
	238	p += bytes; \
	239	len -= bytes; \
	240	if (len < maxcol) \
	241	goto out; \
	242	} while (0)
	243
	244	static ssize_t omap2_iommu_dump_ctx(struct iommu obj, char buf, ssize_t len)
2bcb5733 HD	245	{
	246	char *p = buf;
	247
	248	pr_reg(REVISION);
	249	pr_reg(SYSCONFIG);
	250	pr_reg(SYSSTATUS);
	251	pr_reg(IRQSTATUS);
	252	pr_reg(IRQENABLE);
	253	pr_reg(WALKING_ST);
	254	pr_reg(CNTL);
	255	pr_reg(FAULT_AD);
	256	pr_reg(TTB);
	257	pr_reg(LOCK);
	258	pr_reg(LD_TLB);
	259	pr_reg(CAM);
	260	pr_reg(RAM);
	261	pr_reg(GFLUSH);
	262	pr_reg(FLUSH_ENTRY);
	263	pr_reg(READ_CAM);
	264	pr_reg(READ_RAM);
	265	pr_reg(EMU_FAULT_AD);
14e0e679	266	out:
2bcb5733 HD	267	return p - buf;
	268	}
	269
	270	static void omap2_iommu_save_ctx(struct iommu *obj)
	271	{
	272	int i;
	273	u32 *p = obj->ctx;
	274
	275	for (i = 0; i < (MMU_REG_SIZE / sizeof(u32)); i++) {
	276	p[i] = iommu_read_reg(obj, i * sizeof(u32));
	277	dev_dbg(obj->dev, "%s\t[%02d] %08x\n", __func__, i, p[i]);
	278	}
	279
	280	BUG_ON(p[0] != IOMMU_ARCH_VERSION);
	281	}
	282
	283	static void omap2_iommu_restore_ctx(struct iommu *obj)
	284	{
	285	int i;
	286	u32 *p = obj->ctx;
	287
	288	for (i = 0; i < (MMU_REG_SIZE / sizeof(u32)); i++) {
	289	iommu_write_reg(obj, p[i], i * sizeof(u32));
	290	dev_dbg(obj->dev, "%s\t[%02d] %08x\n", __func__, i, p[i]);
	291	}
	292
	293	BUG_ON(p[0] != IOMMU_ARCH_VERSION);
	294	}
	295
	296	static void omap2_cr_to_e(struct cr_regs cr, struct iotlb_entry e)
	297	{
	298	e->da = cr->cam & MMU_CAM_VATAG_MASK;
	299	e->pa = cr->ram & MMU_RAM_PADDR_MASK;
	300	e->valid = cr->cam & MMU_CAM_V;
	301	e->pgsz = cr->cam & MMU_CAM_PGSZ_MASK;
	302	e->endian = cr->ram & MMU_RAM_ENDIAN_MASK;
	303	e->elsz = cr->ram & MMU_RAM_ELSZ_MASK;
	304	e->mixed = cr->ram & MMU_RAM_MIXED;
	305	}
	306
	307	static const struct iommu_functions omap2_iommu_ops = {
	308	.version = IOMMU_ARCH_VERSION,
	309
	310	.enable = omap2_iommu_enable,
	311	.disable = omap2_iommu_disable,
ddfa975a	312	.set_twl = omap2_iommu_set_twl,
2bcb5733 HD	313	.fault_isr = omap2_iommu_fault_isr,
	314
	315	.tlb_read_cr = omap2_tlb_read_cr,
	316	.tlb_load_cr = omap2_tlb_load_cr,
	317
	318	.cr_to_e = omap2_cr_to_e,
	319	.cr_to_virt = omap2_cr_to_virt,
	320	.alloc_cr = omap2_alloc_cr,
	321	.cr_valid = omap2_cr_valid,
	322	.dump_cr = omap2_dump_cr,
	323
	324	.get_pte_attr = omap2_get_pte_attr,
	325
	326	.save_ctx = omap2_iommu_save_ctx,
	327	.restore_ctx = omap2_iommu_restore_ctx,
	328	.dump_ctx = omap2_iommu_dump_ctx,
	329	};
	330
	331	static int __init omap2_iommu_init(void)
	332	{
	333	return install_iommu_arch(&omap2_iommu_ops);
	334	}
	335	module_init(omap2_iommu_init);
	336
	337	static void __exit omap2_iommu_exit(void)
	338	{
	339	uninstall_iommu_arch(&omap2_iommu_ops);
	340	}
	341	module_exit(omap2_iommu_exit);
	342
	343	MODULE_AUTHOR("Hiroshi DOYU, Paul Mundt and Toshihiro Kobayashi");
	344	MODULE_DESCRIPTION("omap iommu: omap2/3 architecture specific functions");
	345	MODULE_LICENSE("GPL v2");