Commit | Line | Data |
---|---|---|
1394f032 BW |
1 | # |
2 | # For a description of the syntax of this configuration file, | |
3 | # see Documentation/kbuild/kconfig-language.txt. | |
4 | # | |
5 | ||
53f8a252 | 6 | mainmenu "Blackfin Kernel Configuration" |
1394f032 BW |
7 | |
8 | config MMU | |
9 | bool | |
10 | default n | |
11 | ||
12 | config FPU | |
13 | bool | |
14 | default n | |
15 | ||
16 | config RWSEM_GENERIC_SPINLOCK | |
17 | bool | |
18 | default y | |
19 | ||
20 | config RWSEM_XCHGADD_ALGORITHM | |
21 | bool | |
22 | default n | |
23 | ||
24 | config BLACKFIN | |
25 | bool | |
26 | default y | |
ec7748b5 | 27 | select HAVE_IDE |
42d4b839 | 28 | select HAVE_OPROFILE |
a4f0b32c | 29 | select ARCH_WANT_OPTIONAL_GPIOLIB |
1394f032 | 30 | |
e3defffe AL |
31 | config ZONE_DMA |
32 | bool | |
33 | default y | |
34 | ||
1394f032 BW |
35 | config GENERIC_FIND_NEXT_BIT |
36 | bool | |
37 | default y | |
38 | ||
39 | config GENERIC_HWEIGHT | |
40 | bool | |
41 | default y | |
42 | ||
43 | config GENERIC_HARDIRQS | |
44 | bool | |
45 | default y | |
46 | ||
47 | config GENERIC_IRQ_PROBE | |
e4e9a7ad | 48 | bool |
1394f032 BW |
49 | default y |
50 | ||
b2d1583f | 51 | config GENERIC_GPIO |
1394f032 BW |
52 | bool |
53 | default y | |
54 | ||
55 | config FORCE_MAX_ZONEORDER | |
56 | int | |
57 | default "14" | |
58 | ||
59 | config GENERIC_CALIBRATE_DELAY | |
60 | bool | |
61 | default y | |
62 | ||
7d2284b0 MD |
63 | config HARDWARE_PM |
64 | def_bool y | |
65 | depends on OPROFILE | |
66 | ||
1394f032 | 67 | source "init/Kconfig" |
dc52ddc0 | 68 | |
1394f032 BW |
69 | source "kernel/Kconfig.preempt" |
70 | ||
dc52ddc0 MH |
71 | source "kernel/Kconfig.freezer" |
72 | ||
1394f032 BW |
73 | menu "Blackfin Processor Options" |
74 | ||
75 | comment "Processor and Board Settings" | |
76 | ||
77 | choice | |
78 | prompt "CPU" | |
79 | default BF533 | |
80 | ||
2f6f4bcd BW |
81 | config BF512 |
82 | bool "BF512" | |
83 | help | |
84 | BF512 Processor Support. | |
85 | ||
86 | config BF514 | |
87 | bool "BF514" | |
88 | help | |
89 | BF514 Processor Support. | |
90 | ||
91 | config BF516 | |
92 | bool "BF516" | |
93 | help | |
94 | BF516 Processor Support. | |
95 | ||
96 | config BF518 | |
97 | bool "BF518" | |
98 | help | |
99 | BF518 Processor Support. | |
100 | ||
59003145 MH |
101 | config BF522 |
102 | bool "BF522" | |
103 | help | |
104 | BF522 Processor Support. | |
105 | ||
1545a111 MF |
106 | config BF523 |
107 | bool "BF523" | |
108 | help | |
109 | BF523 Processor Support. | |
110 | ||
111 | config BF524 | |
112 | bool "BF524" | |
113 | help | |
114 | BF524 Processor Support. | |
115 | ||
59003145 MH |
116 | config BF525 |
117 | bool "BF525" | |
118 | help | |
119 | BF525 Processor Support. | |
120 | ||
1545a111 MF |
121 | config BF526 |
122 | bool "BF526" | |
123 | help | |
124 | BF526 Processor Support. | |
125 | ||
59003145 MH |
126 | config BF527 |
127 | bool "BF527" | |
128 | help | |
129 | BF527 Processor Support. | |
130 | ||
1394f032 BW |
131 | config BF531 |
132 | bool "BF531" | |
133 | help | |
134 | BF531 Processor Support. | |
135 | ||
136 | config BF532 | |
137 | bool "BF532" | |
138 | help | |
139 | BF532 Processor Support. | |
140 | ||
141 | config BF533 | |
142 | bool "BF533" | |
143 | help | |
144 | BF533 Processor Support. | |
145 | ||
146 | config BF534 | |
147 | bool "BF534" | |
148 | help | |
149 | BF534 Processor Support. | |
150 | ||
151 | config BF536 | |
152 | bool "BF536" | |
153 | help | |
154 | BF536 Processor Support. | |
155 | ||
156 | config BF537 | |
157 | bool "BF537" | |
158 | help | |
159 | BF537 Processor Support. | |
160 | ||
dc26aec2 MH |
161 | config BF538 |
162 | bool "BF538" | |
163 | help | |
164 | BF538 Processor Support. | |
165 | ||
166 | config BF539 | |
167 | bool "BF539" | |
168 | help | |
169 | BF539 Processor Support. | |
170 | ||
24a07a12 RH |
171 | config BF542 |
172 | bool "BF542" | |
173 | help | |
174 | BF542 Processor Support. | |
175 | ||
176 | config BF544 | |
177 | bool "BF544" | |
178 | help | |
179 | BF544 Processor Support. | |
180 | ||
7c7fd170 MF |
181 | config BF547 |
182 | bool "BF547" | |
183 | help | |
184 | BF547 Processor Support. | |
185 | ||
24a07a12 RH |
186 | config BF548 |
187 | bool "BF548" | |
188 | help | |
189 | BF548 Processor Support. | |
190 | ||
191 | config BF549 | |
192 | bool "BF549" | |
193 | help | |
194 | BF549 Processor Support. | |
195 | ||
1394f032 BW |
196 | config BF561 |
197 | bool "BF561" | |
198 | help | |
cd88b4dc | 199 | BF561 Processor Support. |
1394f032 BW |
200 | |
201 | endchoice | |
202 | ||
46fa5eec GY |
203 | config SMP |
204 | depends on BF561 | |
205 | bool "Symmetric multi-processing support" | |
206 | ---help--- | |
207 | This enables support for systems with more than one CPU, | |
208 | like the dual core BF561. If you have a system with only one | |
209 | CPU, say N. If you have a system with more than one CPU, say Y. | |
210 | ||
211 | If you don't know what to do here, say N. | |
212 | ||
213 | config NR_CPUS | |
214 | int | |
215 | depends on SMP | |
216 | default 2 if BF561 | |
217 | ||
218 | config IRQ_PER_CPU | |
219 | bool | |
220 | depends on SMP | |
221 | default y | |
222 | ||
223 | config TICK_SOURCE_SYSTMR0 | |
224 | bool | |
225 | select BFIN_GPTIMERS | |
226 | depends on SMP | |
227 | default y | |
228 | ||
0c0497c2 MF |
229 | config BF_REV_MIN |
230 | int | |
2f6f4bcd | 231 | default 0 if (BF51x || BF52x || BF54x) |
0c0497c2 MF |
232 | default 2 if (BF537 || BF536 || BF534) |
233 | default 3 if (BF561 ||BF533 || BF532 || BF531) | |
2f6f4bcd | 234 | default 4 if (BF538 || BF539) |
0c0497c2 MF |
235 | |
236 | config BF_REV_MAX | |
237 | int | |
2f6f4bcd | 238 | default 2 if (BF51x || BF52x || BF54x) |
0c0497c2 | 239 | default 3 if (BF537 || BF536 || BF534) |
2f6f4bcd | 240 | default 5 if (BF561 || BF538 || BF539) |
0c0497c2 MF |
241 | default 6 if (BF533 || BF532 || BF531) |
242 | ||
1394f032 BW |
243 | choice |
244 | prompt "Silicon Rev" | |
2f6f4bcd | 245 | default BF_REV_0_1 if (BF51x || BF52x || BF54x) |
46ce0d9a MF |
246 | default BF_REV_0_2 if (BF534 || BF536 || BF537) |
247 | default BF_REV_0_3 if (BF531 || BF532 || BF533 || BF561) | |
24a07a12 RH |
248 | |
249 | config BF_REV_0_0 | |
250 | bool "0.0" | |
2f6f4bcd | 251 | depends on (BF51x || BF52x || BF54x) |
59003145 MH |
252 | |
253 | config BF_REV_0_1 | |
d07f4380 MF |
254 | bool "0.1" |
255 | depends on (BF52x || BF54x) | |
1394f032 BW |
256 | |
257 | config BF_REV_0_2 | |
258 | bool "0.2" | |
49f7253c | 259 | depends on (BF52x || BF537 || BF536 || BF534 || BF54x) |
1394f032 BW |
260 | |
261 | config BF_REV_0_3 | |
262 | bool "0.3" | |
263 | depends on (BF561 || BF537 || BF536 || BF534 || BF533 || BF532 || BF531) | |
264 | ||
265 | config BF_REV_0_4 | |
266 | bool "0.4" | |
dc26aec2 | 267 | depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539) |
1394f032 BW |
268 | |
269 | config BF_REV_0_5 | |
270 | bool "0.5" | |
dc26aec2 | 271 | depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539) |
1394f032 | 272 | |
49f7253c MF |
273 | config BF_REV_0_6 |
274 | bool "0.6" | |
275 | depends on (BF533 || BF532 || BF531) | |
276 | ||
de3025f4 JZ |
277 | config BF_REV_ANY |
278 | bool "any" | |
279 | ||
280 | config BF_REV_NONE | |
281 | bool "none" | |
282 | ||
1394f032 BW |
283 | endchoice |
284 | ||
2f6f4bcd BW |
285 | config BF51x |
286 | bool | |
287 | depends on (BF512 || BF514 || BF516 || BF518) | |
288 | default y | |
289 | ||
59003145 MH |
290 | config BF52x |
291 | bool | |
1545a111 | 292 | depends on (BF522 || BF523 || BF524 || BF525 || BF526 || BF527) |
59003145 MH |
293 | default y |
294 | ||
24a07a12 RH |
295 | config BF53x |
296 | bool | |
297 | depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537) | |
298 | default y | |
299 | ||
300 | config BF54x | |
301 | bool | |
7c7fd170 | 302 | depends on (BF542 || BF544 || BF547 || BF548 || BF549) |
24a07a12 RH |
303 | default y |
304 | ||
1394f032 BW |
305 | config MEM_GENERIC_BOARD |
306 | bool | |
307 | depends on GENERIC_BOARD | |
308 | default y | |
309 | ||
310 | config MEM_MT48LC64M4A2FB_7E | |
311 | bool | |
312 | depends on (BFIN533_STAMP) | |
313 | default y | |
314 | ||
315 | config MEM_MT48LC16M16A2TG_75 | |
316 | bool | |
317 | depends on (BFIN533_EZKIT || BFIN561_EZKIT \ | |
ab472a04 | 318 | || BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM \ |
9db144fe | 319 | || H8606_HVSISTEMAS || BFIN527_BLUETECHNIX_CM) |
1394f032 BW |
320 | default y |
321 | ||
322 | config MEM_MT48LC32M8A2_75 | |
323 | bool | |
dc26aec2 | 324 | depends on (BFIN537_STAMP || PNAV10 || BFIN538_EZKIT) |
1394f032 BW |
325 | default y |
326 | ||
327 | config MEM_MT48LC8M32B2B5_7 | |
328 | bool | |
329 | depends on (BFIN561_BLUETECHNIX_CM) | |
330 | default y | |
331 | ||
59003145 MH |
332 | config MEM_MT48LC32M16A2TG_75 |
333 | bool | |
8cc7117e | 334 | depends on (BFIN527_EZKIT || BFIN532_IP0X || BLACKSTAMP || BFIN526_EZBRD) |
59003145 MH |
335 | default y |
336 | ||
2f6f4bcd | 337 | source "arch/blackfin/mach-bf518/Kconfig" |
59003145 | 338 | source "arch/blackfin/mach-bf527/Kconfig" |
1394f032 BW |
339 | source "arch/blackfin/mach-bf533/Kconfig" |
340 | source "arch/blackfin/mach-bf561/Kconfig" | |
341 | source "arch/blackfin/mach-bf537/Kconfig" | |
dc26aec2 | 342 | source "arch/blackfin/mach-bf538/Kconfig" |
24a07a12 | 343 | source "arch/blackfin/mach-bf548/Kconfig" |
1394f032 BW |
344 | |
345 | menu "Board customizations" | |
346 | ||
347 | config CMDLINE_BOOL | |
348 | bool "Default bootloader kernel arguments" | |
349 | ||
350 | config CMDLINE | |
351 | string "Initial kernel command string" | |
352 | depends on CMDLINE_BOOL | |
353 | default "console=ttyBF0,57600" | |
354 | help | |
355 | If you don't have a boot loader capable of passing a command line string | |
356 | to the kernel, you may specify one here. As a minimum, you should specify | |
357 | the memory size and the root device (e.g., mem=8M, root=/dev/nfs). | |
358 | ||
5f004c20 MF |
359 | config BOOT_LOAD |
360 | hex "Kernel load address for booting" | |
361 | default "0x1000" | |
362 | range 0x1000 0x20000000 | |
363 | help | |
364 | This option allows you to set the load address of the kernel. | |
365 | This can be useful if you are on a board which has a small amount | |
366 | of memory or you wish to reserve some memory at the beginning of | |
367 | the address space. | |
368 | ||
369 | Note that you need to keep this value above 4k (0x1000) as this | |
370 | memory region is used to capture NULL pointer references as well | |
371 | as some core kernel functions. | |
372 | ||
8cc7117e MH |
373 | config ROM_BASE |
374 | hex "Kernel ROM Base" | |
86249911 | 375 | depends on ROMKERNEL |
8cc7117e MH |
376 | default "0x20040000" |
377 | range 0x20000000 0x20400000 if !(BF54x || BF561) | |
378 | range 0x20000000 0x30000000 if (BF54x || BF561) | |
379 | help | |
380 | ||
f16295e7 | 381 | comment "Clock/PLL Setup" |
1394f032 BW |
382 | |
383 | config CLKIN_HZ | |
2fb6cb41 | 384 | int "Frequency of the crystal on the board in Hz" |
1394f032 BW |
385 | default "11059200" if BFIN533_STAMP |
386 | default "27000000" if BFIN533_EZKIT | |
2f6f4bcd | 387 | default "25000000" if (BFIN537_STAMP || BFIN527_EZKIT || H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN538_EZKIT || BFIN518F-EZBRD) |
1394f032 BW |
388 | default "30000000" if BFIN561_EZKIT |
389 | default "24576000" if PNAV10 | |
5d1617b2 | 390 | default "10000000" if BFIN532_IP0X |
1394f032 BW |
391 | help |
392 | The frequency of CLKIN crystal oscillator on the board in Hz. | |
2fb6cb41 SZ |
393 | Warning: This value should match the crystal on the board. Otherwise, |
394 | peripherals won't work properly. | |
1394f032 | 395 | |
f16295e7 RG |
396 | config BFIN_KERNEL_CLOCK |
397 | bool "Re-program Clocks while Kernel boots?" | |
398 | default n | |
399 | help | |
400 | This option decides if kernel clocks are re-programed from the | |
401 | bootloader settings. If the clocks are not set, the SDRAM settings | |
402 | are also not changed, and the Bootloader does 100% of the hardware | |
403 | configuration. | |
404 | ||
405 | config PLL_BYPASS | |
e4e9a7ad MF |
406 | bool "Bypass PLL" |
407 | depends on BFIN_KERNEL_CLOCK | |
408 | default n | |
f16295e7 RG |
409 | |
410 | config CLKIN_HALF | |
411 | bool "Half Clock In" | |
412 | depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS) | |
413 | default n | |
414 | help | |
415 | If this is set the clock will be divided by 2, before it goes to the PLL. | |
416 | ||
417 | config VCO_MULT | |
418 | int "VCO Multiplier" | |
419 | depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS) | |
420 | range 1 64 | |
421 | default "22" if BFIN533_EZKIT | |
422 | default "45" if BFIN533_STAMP | |
dc26aec2 | 423 | default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM || BFIN538_EZKIT) |
f16295e7 | 424 | default "22" if BFIN533_BLUETECHNIX_CM |
9db144fe | 425 | default "20" if (BFIN537_BLUETECHNIX_CM || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM) |
f16295e7 | 426 | default "20" if BFIN561_EZKIT |
2f6f4bcd | 427 | default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN518F_EZBRD) |
f16295e7 RG |
428 | help |
429 | This controls the frequency of the on-chip PLL. This can be between 1 and 64. | |
430 | PLL Frequency = (Crystal Frequency) * (this setting) | |
431 | ||
432 | choice | |
433 | prompt "Core Clock Divider" | |
434 | depends on BFIN_KERNEL_CLOCK | |
435 | default CCLK_DIV_1 | |
436 | help | |
437 | This sets the frequency of the core. It can be 1, 2, 4 or 8 | |
438 | Core Frequency = (PLL frequency) / (this setting) | |
439 | ||
440 | config CCLK_DIV_1 | |
441 | bool "1" | |
442 | ||
443 | config CCLK_DIV_2 | |
444 | bool "2" | |
445 | ||
446 | config CCLK_DIV_4 | |
447 | bool "4" | |
448 | ||
449 | config CCLK_DIV_8 | |
450 | bool "8" | |
451 | endchoice | |
452 | ||
453 | config SCLK_DIV | |
454 | int "System Clock Divider" | |
455 | depends on BFIN_KERNEL_CLOCK | |
456 | range 1 15 | |
5f004c20 | 457 | default 5 |
f16295e7 RG |
458 | help |
459 | This sets the frequency of the system clock (including SDRAM or DDR). | |
460 | This can be between 1 and 15 | |
461 | System Clock = (PLL frequency) / (this setting) | |
462 | ||
5f004c20 MF |
463 | choice |
464 | prompt "DDR SDRAM Chip Type" | |
465 | depends on BFIN_KERNEL_CLOCK | |
466 | depends on BF54x | |
467 | default MEM_MT46V32M16_5B | |
468 | ||
469 | config MEM_MT46V32M16_6T | |
470 | bool "MT46V32M16_6T" | |
471 | ||
472 | config MEM_MT46V32M16_5B | |
473 | bool "MT46V32M16_5B" | |
474 | endchoice | |
475 | ||
73feb5c0 MH |
476 | choice |
477 | prompt "DDR/SDRAM Timing" | |
478 | depends on BFIN_KERNEL_CLOCK | |
479 | default BFIN_KERNEL_CLOCK_MEMINIT_CALC | |
480 | help | |
481 | This option allows you to specify Blackfin SDRAM/DDR Timing parameters | |
482 | The calculated SDRAM timing parameters may not be 100% | |
483 | accurate - This option is therefore marked experimental. | |
484 | ||
485 | config BFIN_KERNEL_CLOCK_MEMINIT_CALC | |
486 | bool "Calculate Timings (EXPERIMENTAL)" | |
487 | depends on EXPERIMENTAL | |
488 | ||
489 | config BFIN_KERNEL_CLOCK_MEMINIT_SPEC | |
490 | bool "Provide accurate Timings based on target SCLK" | |
491 | help | |
492 | Please consult the Blackfin Hardware Reference Manuals as well | |
493 | as the memory device datasheet. | |
494 | http://docs.blackfin.uclinux.org/doku.php?id=bfin:sdram | |
495 | endchoice | |
496 | ||
497 | menu "Memory Init Control" | |
498 | depends on BFIN_KERNEL_CLOCK_MEMINIT_SPEC | |
499 | ||
500 | config MEM_DDRCTL0 | |
501 | depends on BF54x | |
502 | hex "DDRCTL0" | |
503 | default 0x0 | |
504 | ||
505 | config MEM_DDRCTL1 | |
506 | depends on BF54x | |
507 | hex "DDRCTL1" | |
508 | default 0x0 | |
509 | ||
510 | config MEM_DDRCTL2 | |
511 | depends on BF54x | |
512 | hex "DDRCTL2" | |
513 | default 0x0 | |
514 | ||
515 | config MEM_EBIU_DDRQUE | |
516 | depends on BF54x | |
517 | hex "DDRQUE" | |
518 | default 0x0 | |
519 | ||
520 | config MEM_SDRRC | |
521 | depends on !BF54x | |
522 | hex "SDRRC" | |
523 | default 0x0 | |
524 | ||
525 | config MEM_SDGCTL | |
526 | depends on !BF54x | |
527 | hex "SDGCTL" | |
528 | default 0x0 | |
529 | endmenu | |
530 | ||
7eb2c23f MF |
531 | config MAX_MEM_SIZE |
532 | int "Max SDRAM Memory Size in MBytes" | |
533 | depends on !MPU | |
534 | default 512 | |
535 | help | |
536 | This is the max memory size that the kernel will create CPLB | |
537 | tables for. Your system will not be able to handle any more. | |
538 | ||
f16295e7 RG |
539 | # |
540 | # Max & Min Speeds for various Chips | |
541 | # | |
542 | config MAX_VCO_HZ | |
543 | int | |
2f6f4bcd BW |
544 | default 400000000 if BF512 |
545 | default 400000000 if BF514 | |
546 | default 400000000 if BF516 | |
547 | default 400000000 if BF518 | |
f16295e7 | 548 | default 600000000 if BF522 |
1545a111 MF |
549 | default 400000000 if BF523 |
550 | default 400000000 if BF524 | |
f16295e7 | 551 | default 600000000 if BF525 |
1545a111 | 552 | default 400000000 if BF526 |
f16295e7 RG |
553 | default 600000000 if BF527 |
554 | default 400000000 if BF531 | |
555 | default 400000000 if BF532 | |
556 | default 750000000 if BF533 | |
557 | default 500000000 if BF534 | |
558 | default 400000000 if BF536 | |
559 | default 600000000 if BF537 | |
f72eecb9 RG |
560 | default 533333333 if BF538 |
561 | default 533333333 if BF539 | |
f16295e7 | 562 | default 600000000 if BF542 |
f72eecb9 | 563 | default 533333333 if BF544 |
1545a111 MF |
564 | default 600000000 if BF547 |
565 | default 600000000 if BF548 | |
f72eecb9 | 566 | default 533333333 if BF549 |
f16295e7 RG |
567 | default 600000000 if BF561 |
568 | ||
569 | config MIN_VCO_HZ | |
570 | int | |
571 | default 50000000 | |
572 | ||
573 | config MAX_SCLK_HZ | |
574 | int | |
f72eecb9 | 575 | default 133333333 |
f16295e7 RG |
576 | |
577 | config MIN_SCLK_HZ | |
578 | int | |
579 | default 27000000 | |
580 | ||
581 | comment "Kernel Timer/Scheduler" | |
582 | ||
583 | source kernel/Kconfig.hz | |
584 | ||
8b5f79f9 VM |
585 | config GENERIC_TIME |
586 | bool "Generic time" | |
46fa5eec | 587 | depends on !SMP |
8b5f79f9 VM |
588 | default y |
589 | ||
590 | config GENERIC_CLOCKEVENTS | |
591 | bool "Generic clock events" | |
592 | depends on GENERIC_TIME | |
593 | default y | |
594 | ||
595 | config CYCLES_CLOCKSOURCE | |
596 | bool "Use 'CYCLES' as a clocksource (EXPERIMENTAL)" | |
597 | depends on EXPERIMENTAL | |
598 | depends on GENERIC_CLOCKEVENTS | |
599 | depends on !BFIN_SCRATCH_REG_CYCLES | |
600 | default n | |
601 | help | |
602 | If you say Y here, you will enable support for using the 'cycles' | |
603 | registers as a clock source. Doing so means you will be unable to | |
604 | safely write to the 'cycles' register during runtime. You will | |
605 | still be able to read it (such as for performance monitoring), but | |
606 | writing the registers will most likely crash the kernel. | |
607 | ||
608 | source kernel/time/Kconfig | |
609 | ||
5f004c20 | 610 | comment "Misc" |
971d5bc4 | 611 | |
f0b5d12f MF |
612 | choice |
613 | prompt "Blackfin Exception Scratch Register" | |
614 | default BFIN_SCRATCH_REG_RETN | |
615 | help | |
616 | Select the resource to reserve for the Exception handler: | |
617 | - RETN: Non-Maskable Interrupt (NMI) | |
618 | - RETE: Exception Return (JTAG/ICE) | |
619 | - CYCLES: Performance counter | |
620 | ||
621 | If you are unsure, please select "RETN". | |
622 | ||
623 | config BFIN_SCRATCH_REG_RETN | |
624 | bool "RETN" | |
625 | help | |
626 | Use the RETN register in the Blackfin exception handler | |
627 | as a stack scratch register. This means you cannot | |
628 | safely use NMI on the Blackfin while running Linux, but | |
629 | you can debug the system with a JTAG ICE and use the | |
630 | CYCLES performance registers. | |
631 | ||
632 | If you are unsure, please select "RETN". | |
633 | ||
634 | config BFIN_SCRATCH_REG_RETE | |
635 | bool "RETE" | |
636 | help | |
637 | Use the RETE register in the Blackfin exception handler | |
638 | as a stack scratch register. This means you cannot | |
639 | safely use a JTAG ICE while debugging a Blackfin board, | |
640 | but you can safely use the CYCLES performance registers | |
641 | and the NMI. | |
642 | ||
643 | If you are unsure, please select "RETN". | |
644 | ||
645 | config BFIN_SCRATCH_REG_CYCLES | |
646 | bool "CYCLES" | |
647 | help | |
648 | Use the CYCLES register in the Blackfin exception handler | |
649 | as a stack scratch register. This means you cannot | |
650 | safely use the CYCLES performance registers on a Blackfin | |
651 | board at anytime, but you can debug the system with a JTAG | |
652 | ICE and use the NMI. | |
653 | ||
654 | If you are unsure, please select "RETN". | |
655 | ||
656 | endchoice | |
657 | ||
1394f032 BW |
658 | endmenu |
659 | ||
660 | ||
661 | menu "Blackfin Kernel Optimizations" | |
46fa5eec | 662 | depends on !SMP |
1394f032 | 663 | |
1394f032 BW |
664 | comment "Memory Optimizations" |
665 | ||
666 | config I_ENTRY_L1 | |
667 | bool "Locate interrupt entry code in L1 Memory" | |
668 | default y | |
669 | help | |
01dd2fbf ML |
670 | If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked |
671 | into L1 instruction memory. (less latency) | |
1394f032 BW |
672 | |
673 | config EXCPT_IRQ_SYSC_L1 | |
01dd2fbf | 674 | bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory" |
1394f032 BW |
675 | default y |
676 | help | |
01dd2fbf | 677 | If enabled, the entire ASM lowlevel exception and interrupt entry code |
cfefe3c6 | 678 | (STORE/RESTORE CONTEXT) is linked into L1 instruction memory. |
01dd2fbf | 679 | (less latency) |
1394f032 BW |
680 | |
681 | config DO_IRQ_L1 | |
682 | bool "Locate frequently called do_irq dispatcher function in L1 Memory" | |
683 | default y | |
684 | help | |
01dd2fbf ML |
685 | If enabled, the frequently called do_irq dispatcher function is linked |
686 | into L1 instruction memory. (less latency) | |
1394f032 BW |
687 | |
688 | config CORE_TIMER_IRQ_L1 | |
689 | bool "Locate frequently called timer_interrupt() function in L1 Memory" | |
690 | default y | |
691 | help | |
01dd2fbf ML |
692 | If enabled, the frequently called timer_interrupt() function is linked |
693 | into L1 instruction memory. (less latency) | |
1394f032 BW |
694 | |
695 | config IDLE_L1 | |
696 | bool "Locate frequently idle function in L1 Memory" | |
697 | default y | |
698 | help | |
01dd2fbf ML |
699 | If enabled, the frequently called idle function is linked |
700 | into L1 instruction memory. (less latency) | |
1394f032 BW |
701 | |
702 | config SCHEDULE_L1 | |
703 | bool "Locate kernel schedule function in L1 Memory" | |
704 | default y | |
705 | help | |
01dd2fbf ML |
706 | If enabled, the frequently called kernel schedule is linked |
707 | into L1 instruction memory. (less latency) | |
1394f032 BW |
708 | |
709 | config ARITHMETIC_OPS_L1 | |
710 | bool "Locate kernel owned arithmetic functions in L1 Memory" | |
711 | default y | |
712 | help | |
01dd2fbf ML |
713 | If enabled, arithmetic functions are linked |
714 | into L1 instruction memory. (less latency) | |
1394f032 BW |
715 | |
716 | config ACCESS_OK_L1 | |
717 | bool "Locate access_ok function in L1 Memory" | |
718 | default y | |
719 | help | |
01dd2fbf ML |
720 | If enabled, the access_ok function is linked |
721 | into L1 instruction memory. (less latency) | |
1394f032 BW |
722 | |
723 | config MEMSET_L1 | |
724 | bool "Locate memset function in L1 Memory" | |
725 | default y | |
726 | help | |
01dd2fbf ML |
727 | If enabled, the memset function is linked |
728 | into L1 instruction memory. (less latency) | |
1394f032 BW |
729 | |
730 | config MEMCPY_L1 | |
731 | bool "Locate memcpy function in L1 Memory" | |
732 | default y | |
733 | help | |
01dd2fbf ML |
734 | If enabled, the memcpy function is linked |
735 | into L1 instruction memory. (less latency) | |
1394f032 BW |
736 | |
737 | config SYS_BFIN_SPINLOCK_L1 | |
738 | bool "Locate sys_bfin_spinlock function in L1 Memory" | |
739 | default y | |
740 | help | |
01dd2fbf ML |
741 | If enabled, sys_bfin_spinlock function is linked |
742 | into L1 instruction memory. (less latency) | |
1394f032 BW |
743 | |
744 | config IP_CHECKSUM_L1 | |
745 | bool "Locate IP Checksum function in L1 Memory" | |
746 | default n | |
747 | help | |
01dd2fbf ML |
748 | If enabled, the IP Checksum function is linked |
749 | into L1 instruction memory. (less latency) | |
1394f032 BW |
750 | |
751 | config CACHELINE_ALIGNED_L1 | |
752 | bool "Locate cacheline_aligned data to L1 Data Memory" | |
157cc5aa MH |
753 | default y if !BF54x |
754 | default n if BF54x | |
1394f032 BW |
755 | depends on !BF531 |
756 | help | |
01dd2fbf ML |
757 | If enabled, cacheline_anligned data is linked |
758 | into L1 data memory. (less latency) | |
1394f032 BW |
759 | |
760 | config SYSCALL_TAB_L1 | |
761 | bool "Locate Syscall Table L1 Data Memory" | |
762 | default n | |
763 | depends on !BF531 | |
764 | help | |
01dd2fbf ML |
765 | If enabled, the Syscall LUT is linked |
766 | into L1 data memory. (less latency) | |
1394f032 BW |
767 | |
768 | config CPLB_SWITCH_TAB_L1 | |
769 | bool "Locate CPLB Switch Tables L1 Data Memory" | |
770 | default n | |
771 | depends on !BF531 | |
772 | help | |
01dd2fbf ML |
773 | If enabled, the CPLB Switch Tables are linked |
774 | into L1 data memory. (less latency) | |
1394f032 | 775 | |
ca87b7ad GY |
776 | config APP_STACK_L1 |
777 | bool "Support locating application stack in L1 Scratch Memory" | |
778 | default y | |
779 | help | |
780 | If enabled the application stack can be located in L1 | |
781 | scratch memory (less latency). | |
782 | ||
783 | Currently only works with FLAT binaries. | |
784 | ||
6ad2b84c MF |
785 | config EXCEPTION_L1_SCRATCH |
786 | bool "Locate exception stack in L1 Scratch Memory" | |
787 | default n | |
788 | depends on !APP_STACK_L1 && !SYSCALL_TAB_L1 | |
789 | help | |
790 | Whenever an exception occurs, use the L1 Scratch memory for | |
791 | stack storage. You cannot place the stacks of FLAT binaries | |
792 | in L1 when using this option. | |
793 | ||
794 | If you don't use L1 Scratch, then you should say Y here. | |
795 | ||
251383c7 RG |
796 | comment "Speed Optimizations" |
797 | config BFIN_INS_LOWOVERHEAD | |
798 | bool "ins[bwl] low overhead, higher interrupt latency" | |
799 | default y | |
800 | help | |
801 | Reads on the Blackfin are speculative. In Blackfin terms, this means | |
802 | they can be interrupted at any time (even after they have been issued | |
803 | on to the external bus), and re-issued after the interrupt occurs. | |
804 | For memory - this is not a big deal, since memory does not change if | |
805 | it sees a read. | |
806 | ||
807 | If a FIFO is sitting on the end of the read, it will see two reads, | |
808 | when the core only sees one since the FIFO receives both the read | |
809 | which is cancelled (and not delivered to the core) and the one which | |
810 | is re-issued (which is delivered to the core). | |
811 | ||
812 | To solve this, interrupts are turned off before reads occur to | |
813 | I/O space. This option controls which the overhead/latency of | |
814 | controlling interrupts during this time | |
815 | "n" turns interrupts off every read | |
816 | (higher overhead, but lower interrupt latency) | |
817 | "y" turns interrupts off every loop | |
818 | (low overhead, but longer interrupt latency) | |
819 | ||
820 | default behavior is to leave this set to on (type "Y"). If you are experiencing | |
821 | interrupt latency issues, it is safe and OK to turn this off. | |
822 | ||
1394f032 BW |
823 | endmenu |
824 | ||
1394f032 BW |
825 | choice |
826 | prompt "Kernel executes from" | |
827 | help | |
828 | Choose the memory type that the kernel will be running in. | |
829 | ||
830 | config RAMKERNEL | |
831 | bool "RAM" | |
832 | help | |
833 | The kernel will be resident in RAM when running. | |
834 | ||
835 | config ROMKERNEL | |
836 | bool "ROM" | |
837 | help | |
838 | The kernel will be resident in FLASH/ROM when running. | |
839 | ||
840 | endchoice | |
841 | ||
842 | source "mm/Kconfig" | |
843 | ||
780431e3 MF |
844 | config BFIN_GPTIMERS |
845 | tristate "Enable Blackfin General Purpose Timers API" | |
846 | default n | |
847 | help | |
848 | Enable support for the General Purpose Timers API. If you | |
849 | are unsure, say N. | |
850 | ||
851 | To compile this driver as a module, choose M here: the module | |
852 | will be called gptimers.ko. | |
853 | ||
1394f032 | 854 | choice |
d292b000 | 855 | prompt "Uncached DMA region" |
1394f032 | 856 | default DMA_UNCACHED_1M |
86ad7932 CC |
857 | config DMA_UNCACHED_4M |
858 | bool "Enable 4M DMA region" | |
1394f032 BW |
859 | config DMA_UNCACHED_2M |
860 | bool "Enable 2M DMA region" | |
861 | config DMA_UNCACHED_1M | |
862 | bool "Enable 1M DMA region" | |
863 | config DMA_UNCACHED_NONE | |
864 | bool "Disable DMA region" | |
865 | endchoice | |
866 | ||
867 | ||
868 | comment "Cache Support" | |
3bebca2d | 869 | config BFIN_ICACHE |
1394f032 | 870 | bool "Enable ICACHE" |
3bebca2d | 871 | config BFIN_DCACHE |
1394f032 | 872 | bool "Enable DCACHE" |
3bebca2d | 873 | config BFIN_DCACHE_BANKA |
1394f032 | 874 | bool "Enable only 16k BankA DCACHE - BankB is SRAM" |
3bebca2d | 875 | depends on BFIN_DCACHE && !BF531 |
1394f032 | 876 | default n |
3bebca2d RG |
877 | config BFIN_ICACHE_LOCK |
878 | bool "Enable Instruction Cache Locking" | |
1394f032 BW |
879 | |
880 | choice | |
881 | prompt "Policy" | |
3bebca2d | 882 | depends on BFIN_DCACHE |
46fa5eec GY |
883 | default BFIN_WB if !SMP |
884 | default BFIN_WT if SMP | |
3bebca2d | 885 | config BFIN_WB |
1394f032 | 886 | bool "Write back" |
46fa5eec | 887 | depends on !SMP |
1394f032 BW |
888 | help |
889 | Write Back Policy: | |
890 | Cached data will be written back to SDRAM only when needed. | |
891 | This can give a nice increase in performance, but beware of | |
892 | broken drivers that do not properly invalidate/flush their | |
893 | cache. | |
894 | ||
895 | Write Through Policy: | |
896 | Cached data will always be written back to SDRAM when the | |
897 | cache is updated. This is a completely safe setting, but | |
898 | performance is worse than Write Back. | |
899 | ||
900 | If you are unsure of the options and you want to be safe, | |
901 | then go with Write Through. | |
902 | ||
3bebca2d | 903 | config BFIN_WT |
1394f032 BW |
904 | bool "Write through" |
905 | help | |
906 | Write Back Policy: | |
907 | Cached data will be written back to SDRAM only when needed. | |
908 | This can give a nice increase in performance, but beware of | |
909 | broken drivers that do not properly invalidate/flush their | |
910 | cache. | |
911 | ||
912 | Write Through Policy: | |
913 | Cached data will always be written back to SDRAM when the | |
914 | cache is updated. This is a completely safe setting, but | |
915 | performance is worse than Write Back. | |
916 | ||
917 | If you are unsure of the options and you want to be safe, | |
918 | then go with Write Through. | |
919 | ||
920 | endchoice | |
921 | ||
f099f39a SZ |
922 | config BFIN_L2_CACHEABLE |
923 | bool "Cache L2 SRAM" | |
94106e0f | 924 | depends on (BFIN_DCACHE || BFIN_ICACHE) && (BF54x || (BF561 && !SMP)) |
f099f39a SZ |
925 | default n |
926 | help | |
927 | Select to make L2 SRAM cacheable in L1 data and instruction cache. | |
928 | ||
b97b8a99 BS |
929 | config MPU |
930 | bool "Enable the memory protection unit (EXPERIMENTAL)" | |
931 | default n | |
932 | help | |
933 | Use the processor's MPU to protect applications from accessing | |
934 | memory they do not own. This comes at a performance penalty | |
935 | and is recommended only for debugging. | |
936 | ||
1394f032 BW |
937 | comment "Asynchonous Memory Configuration" |
938 | ||
ddf416b2 | 939 | menu "EBIU_AMGCTL Global Control" |
1394f032 BW |
940 | config C_AMCKEN |
941 | bool "Enable CLKOUT" | |
942 | default y | |
943 | ||
944 | config C_CDPRIO | |
945 | bool "DMA has priority over core for ext. accesses" | |
946 | default n | |
947 | ||
948 | config C_B0PEN | |
949 | depends on BF561 | |
950 | bool "Bank 0 16 bit packing enable" | |
951 | default y | |
952 | ||
953 | config C_B1PEN | |
954 | depends on BF561 | |
955 | bool "Bank 1 16 bit packing enable" | |
956 | default y | |
957 | ||
958 | config C_B2PEN | |
959 | depends on BF561 | |
960 | bool "Bank 2 16 bit packing enable" | |
961 | default y | |
962 | ||
963 | config C_B3PEN | |
964 | depends on BF561 | |
965 | bool "Bank 3 16 bit packing enable" | |
966 | default n | |
967 | ||
968 | choice | |
969 | prompt"Enable Asynchonous Memory Banks" | |
970 | default C_AMBEN_ALL | |
971 | ||
972 | config C_AMBEN | |
973 | bool "Disable All Banks" | |
974 | ||
975 | config C_AMBEN_B0 | |
976 | bool "Enable Bank 0" | |
977 | ||
978 | config C_AMBEN_B0_B1 | |
979 | bool "Enable Bank 0 & 1" | |
980 | ||
981 | config C_AMBEN_B0_B1_B2 | |
982 | bool "Enable Bank 0 & 1 & 2" | |
983 | ||
984 | config C_AMBEN_ALL | |
985 | bool "Enable All Banks" | |
986 | endchoice | |
987 | endmenu | |
988 | ||
989 | menu "EBIU_AMBCTL Control" | |
990 | config BANK_0 | |
991 | hex "Bank 0" | |
992 | default 0x7BB0 | |
993 | ||
994 | config BANK_1 | |
995 | hex "Bank 1" | |
996 | default 0x7BB0 | |
197fba56 | 997 | default 0x5558 if BF54x |
1394f032 BW |
998 | |
999 | config BANK_2 | |
1000 | hex "Bank 2" | |
1001 | default 0x7BB0 | |
1002 | ||
1003 | config BANK_3 | |
1004 | hex "Bank 3" | |
1005 | default 0x99B3 | |
1006 | endmenu | |
1007 | ||
e40540b3 SZ |
1008 | config EBIU_MBSCTLVAL |
1009 | hex "EBIU Bank Select Control Register" | |
1010 | depends on BF54x | |
1011 | default 0 | |
1012 | ||
1013 | config EBIU_MODEVAL | |
1014 | hex "Flash Memory Mode Control Register" | |
1015 | depends on BF54x | |
1016 | default 1 | |
1017 | ||
1018 | config EBIU_FCTLVAL | |
1019 | hex "Flash Memory Bank Control Register" | |
1020 | depends on BF54x | |
1021 | default 6 | |
1394f032 BW |
1022 | endmenu |
1023 | ||
1024 | ############################################################################# | |
1025 | menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)" | |
1026 | ||
1027 | config PCI | |
1028 | bool "PCI support" | |
a95ca3b2 | 1029 | depends on BROKEN |
1394f032 BW |
1030 | help |
1031 | Support for PCI bus. | |
1032 | ||
1033 | source "drivers/pci/Kconfig" | |
1034 | ||
1035 | config HOTPLUG | |
1036 | bool "Support for hot-pluggable device" | |
1037 | help | |
1038 | Say Y here if you want to plug devices into your computer while | |
1039 | the system is running, and be able to use them quickly. In many | |
1040 | cases, the devices can likewise be unplugged at any time too. | |
1041 | ||
1042 | One well known example of this is PCMCIA- or PC-cards, credit-card | |
1043 | size devices such as network cards, modems or hard drives which are | |
1044 | plugged into slots found on all modern laptop computers. Another | |
1045 | example, used on modern desktops as well as laptops, is USB. | |
1046 | ||
a81792f6 JB |
1047 | Enable HOTPLUG and build a modular kernel. Get agent software |
1048 | (from <http://linux-hotplug.sourceforge.net/>) and install it. | |
1394f032 BW |
1049 | Then your kernel will automatically call out to a user mode "policy |
1050 | agent" (/sbin/hotplug) to load modules and set up software needed | |
1051 | to use devices as you hotplug them. | |
1052 | ||
1053 | source "drivers/pcmcia/Kconfig" | |
1054 | ||
1055 | source "drivers/pci/hotplug/Kconfig" | |
1056 | ||
1057 | endmenu | |
1058 | ||
1059 | menu "Executable file formats" | |
1060 | ||
1061 | source "fs/Kconfig.binfmt" | |
1062 | ||
1063 | endmenu | |
1064 | ||
1065 | menu "Power management options" | |
1066 | source "kernel/power/Kconfig" | |
1067 | ||
f4cb5700 JB |
1068 | config ARCH_SUSPEND_POSSIBLE |
1069 | def_bool y | |
1070 | depends on !SMP | |
1071 | ||
1394f032 | 1072 | choice |
1efc80b5 | 1073 | prompt "Standby Power Saving Mode" |
1394f032 | 1074 | depends on PM |
cfefe3c6 MH |
1075 | default PM_BFIN_SLEEP_DEEPER |
1076 | config PM_BFIN_SLEEP_DEEPER | |
1077 | bool "Sleep Deeper" | |
1078 | help | |
1079 | Sleep "Deeper" Mode (High Power Savings) - This mode reduces dynamic | |
1080 | power dissipation by disabling the clock to the processor core (CCLK). | |
1081 | Furthermore, Standby sets the internal power supply voltage (VDDINT) | |
1082 | to 0.85 V to provide the greatest power savings, while preserving the | |
1083 | processor state. | |
1084 | The PLL and system clock (SCLK) continue to operate at a very low | |
1085 | frequency of about 3.3 MHz. To preserve data integrity in the SDRAM, | |
1086 | the SDRAM is put into Self Refresh Mode. Typically an external event | |
1087 | such as GPIO interrupt or RTC activity wakes up the processor. | |
1088 | Various Peripherals such as UART, SPORT, PPI may not function as | |
1089 | normal during Sleep Deeper, due to the reduced SCLK frequency. | |
1090 | When in the sleep mode, system DMA access to L1 memory is not supported. | |
1091 | ||
1efc80b5 MH |
1092 | If unsure, select "Sleep Deeper". |
1093 | ||
cfefe3c6 MH |
1094 | config PM_BFIN_SLEEP |
1095 | bool "Sleep" | |
1096 | help | |
1097 | Sleep Mode (High Power Savings) - The sleep mode reduces power | |
1098 | dissipation by disabling the clock to the processor core (CCLK). | |
1099 | The PLL and system clock (SCLK), however, continue to operate in | |
1100 | this mode. Typically an external event or RTC activity will wake | |
1efc80b5 MH |
1101 | up the processor. When in the sleep mode, system DMA access to L1 |
1102 | memory is not supported. | |
1103 | ||
1104 | If unsure, select "Sleep Deeper". | |
cfefe3c6 | 1105 | endchoice |
1394f032 | 1106 | |
1394f032 | 1107 | config PM_WAKEUP_BY_GPIO |
1efc80b5 | 1108 | bool "Allow Wakeup from Standby by GPIO" |
1394f032 BW |
1109 | |
1110 | config PM_WAKEUP_GPIO_NUMBER | |
1efc80b5 | 1111 | int "GPIO number" |
1394f032 BW |
1112 | range 0 47 |
1113 | depends on PM_WAKEUP_BY_GPIO | |
d1a3336e | 1114 | default 2 |
1394f032 BW |
1115 | |
1116 | choice | |
1117 | prompt "GPIO Polarity" | |
1118 | depends on PM_WAKEUP_BY_GPIO | |
1119 | default PM_WAKEUP_GPIO_POLAR_H | |
1120 | config PM_WAKEUP_GPIO_POLAR_H | |
1121 | bool "Active High" | |
1122 | config PM_WAKEUP_GPIO_POLAR_L | |
1123 | bool "Active Low" | |
1124 | config PM_WAKEUP_GPIO_POLAR_EDGE_F | |
1125 | bool "Falling EDGE" | |
1126 | config PM_WAKEUP_GPIO_POLAR_EDGE_R | |
1127 | bool "Rising EDGE" | |
1128 | config PM_WAKEUP_GPIO_POLAR_EDGE_B | |
1129 | bool "Both EDGE" | |
1130 | endchoice | |
1131 | ||
1efc80b5 MH |
1132 | comment "Possible Suspend Mem / Hibernate Wake-Up Sources" |
1133 | depends on PM | |
1134 | ||
1efc80b5 MH |
1135 | config PM_BFIN_WAKE_PH6 |
1136 | bool "Allow Wake-Up from on-chip PHY or PH6 GP" | |
2f6f4bcd | 1137 | depends on PM && (BF51x || BF52x || BF534 || BF536 || BF537) |
1efc80b5 MH |
1138 | default n |
1139 | help | |
1140 | Enable PHY and PH6 GP Wake-Up (Voltage Regulator Power-Up) | |
1141 | ||
1efc80b5 MH |
1142 | config PM_BFIN_WAKE_GP |
1143 | bool "Allow Wake-Up from GPIOs" | |
1144 | depends on PM && BF54x | |
1145 | default n | |
1146 | help | |
1147 | Enable General-Purpose Wake-Up (Voltage Regulator Power-Up) | |
1394f032 BW |
1148 | endmenu |
1149 | ||
1394f032 BW |
1150 | menu "CPU Frequency scaling" |
1151 | ||
1152 | source "drivers/cpufreq/Kconfig" | |
1153 | ||
5ad2ca5f MH |
1154 | config BFIN_CPU_FREQ |
1155 | bool | |
1156 | depends on CPU_FREQ | |
1157 | select CPU_FREQ_TABLE | |
1158 | default y | |
1159 | ||
14b03204 MH |
1160 | config CPU_VOLTAGE |
1161 | bool "CPU Voltage scaling" | |
73feb5c0 | 1162 | depends on EXPERIMENTAL |
14b03204 MH |
1163 | depends on CPU_FREQ |
1164 | default n | |
1165 | help | |
1166 | Say Y here if you want CPU voltage scaling according to the CPU frequency. | |
1167 | This option violates the PLL BYPASS recommendation in the Blackfin Processor | |
73feb5c0 | 1168 | manuals. There is a theoretical risk that during VDDINT transitions |
14b03204 MH |
1169 | the PLL may unlock. |
1170 | ||
1394f032 BW |
1171 | endmenu |
1172 | ||
1394f032 BW |
1173 | source "net/Kconfig" |
1174 | ||
1175 | source "drivers/Kconfig" | |
1176 | ||
1177 | source "fs/Kconfig" | |
1178 | ||
74ce8322 | 1179 | source "arch/blackfin/Kconfig.debug" |
1394f032 BW |
1180 | |
1181 | source "security/Kconfig" | |
1182 | ||
1183 | source "crypto/Kconfig" | |
1184 | ||
1185 | source "lib/Kconfig" |